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F2MC-16FX MB96380 Series

1. ns 2 Hysteresis input Hysteresis input Automotive inputs TTL input Analog input SEG output pull up control Hysteresis input Hysteresis input Automotive intputs TTL intput Analog input SEG output Vx intput CMOS level output programmable lo 5mA 5mA and lo 2 2mA 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull up registor approx Analogue input SEG output CMOS level output programmable lo 5mA 5mA and lo 2mA 2mA 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull up registor approx Analogue input SEG output MB96380 DS pin circuit typefm 23 96380 Series Circuit Standby control for input shutdown Standby control for input shutdown Standby control pull up control Pout 77 Standby control Hysteresis input for input shutdown gt gt gt for input shutdown Do Hysteresis input Automotive inputs TTL input SEG COM output Specification Remarks CMOS level output
2. 50pF Parameter Pin Conditions MB96380 Address valid Data hold time A 23 0 AD 15 0 RDX T ALE T time RDX ALE EACL STS 1 and EACL ACE 1 3tcvc 2 10 other ECL STS EACL ACE setting tcvc 2 10 Valid address f time tavcH A 23 0 ECLK AD 15 0 15 2 15 RDX L ECLK f time 2 10 ALE 4 gt i time TLLAL ALE RDX EACL STS 0 tcvc 2 10 EACL STS 1 10 ECLKT Valid data input Ta 40 C to 125 C Vcc 3 0 to 4 5V Vss 0 0 Parameter ALE pulse width tcHov AD 15 0 ECLK V lOcrive 50pF Conditions EACL STS 0 and EACL ACE 0 tcvc 2 8 EACL STS 1 8 EACL STS 0 and EACL ACE 1 3tcvc 2 8 Valid address ALE time ALE A 23 16 EACL STS 0 and EACL ACE 0 tcvc 20 EACL STS 1 and EACL ACE 0 2 20 EACL STS 0 and EACL ACE 1 20 EACL STS 1 and EACL ACE 1 2 20 TADVLL ALE AD 15 0 EACL STS 0 and EACL ACE 0 tcyc 2 20 EACL STS 1 and EACL ACE 0 tove 20 EACL STS 0 and EACL ACE 1 2 20 EACL STS 1 and EACL ACE 1 20 ALE L Address vali
3. SPECIFICATION FME MB96380 rev 6 16 bit Proprietary Microcontroller CMOS F2MC 16FX 96380 Series DESCRIPTION MB96380 series is based on Fujitsu s advanced 16FX architecture 16 bit with instruction pipeline for RISC like performance The CPU uses the same instruction set as the established 16LX series enabling thus easy migration of 16LX Software to the new 16FX products In comparison with the previous generation the 16FX products include significantly improved performance even at the same operation frequency a reduced power consumption and a faster start up time For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator The result is a minimum instruction cycle time of 17 8ns going together with excellent EMI behavior An on chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum The emitted power is minimised by the on chip voltage regulator that reduces the internal CPU voltage A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed FUJITSU FME EMDC 2007 11 14MB96380 DS cover fm 96380 Series Specification 2 FME EMDC 2007 11 14 MB96380_DS_cover fm Specification MB96380 FEATURES Feature Description Technology 0 18u
4. 0 36 AVcc 5 0 36 AVcc 0 36 5 INTREF 0 ALARMO ALARM1 0 78 AVcc 396 0 78 AVcc 0 78 AVcc 4396 INTREF 0 14 1 25 1 4 INTREF 1 2 4 2 55 2 7 INTREF 1 250 0 1 CMD 1 fast Comparator Output lt h VivrH Vuvs 100 VALIN MB96300 DS el alarm fm CMD 0 slow 107 96380 Series Specification 108 FME EMDC 2007 11 14 MB96300_DS_el_alarm fm Specification LOW VOLTAGE DETECTOR CHARACTERISTICS 40 C to 125 C 3 0V 5 5V Vgs AVss Value Parameter Symbol Min Max Stabilization time TLVDSTAB MB96380 Remarks Level 0 Vpio Level 1 Vout Level 2 Vpi2 Level 3 Level 4 VoLa Level 5 5 Level 6 Level 7 VoL7 Level 8 lt lt lt lt lt lt lt lt lt Level 9 9 V Level 10 VpL10 not used Level 11 Vpu11 not used Level 12 VoL12 not used Level 13 VoL13 not used Level 14 VoL14 not used Level 15 Levels 10 to 15 are not used in this device For correct detection the slope of the voltage level must satisfy Faster variations are regarded as noise and may not be detected VoL15 FME EMDC 20
5. 000805 CAN1 Error Counter Receive ERRCNTH1 000806H 1 bit Timing Register BTRL1 000807H bit Timing Register BTRH1 000808H Interrupt Register INTRL1 1 INTR1 000809H Interrupt Register INTRH1 00080AH 1 Test Register TESTRL1 TESTR1 00080BH CAN1 Test Register reserved TESTRH1 00080 CAN1 BRP Extension register BRPERL1 00080DH CAN 1 BRP Extension register reserved 000810H 1 IF1 Command request register IF1CREQL1 BRPER1 IF1CREQ1 000811H CAN1 IF1 Command request register IF1CREQH 1 000812 CAN1 IF1 Command Mask register IF1CMSKL1 IF1CMSK1 000813H CAN1 IF1 Command Mask register reserved IF1CMSKH1 000814H CAN1 IF1 Mask Register IF1MSK1L1 IF1MSK11 RW 000815H CAN1 IF1 Mask Register IF1MSK1H1 RW 000816H 1 IF1 Mask Register IF1MSK2L1 IF1MSK21 RW 000817H CAN1 IF1 Mask Register IF1MSK2H1 000818H CAN1 IF1 Arbitration register IF1ARB1L1 IF1ARB11 000819H CAN1 Arbitration register IF1ARB1H1 00081AH CAN1 IF1 Arbitration register IF1ARB2L1 IF1ARB21 RW 00081BH CAN 1 IF1 Arbitration register IF1ARB2H1 RW 00081CH CAN1 IF1 Message Control Register 1 IFIMCTR1 RW 00081DH CAN1 IF1 Message Control Register IFIMCTRH1 00081EH 1 IF1 Data 1 IF1DTA1L1 IF1DTA1 1 00081FH CAN1 IF1 Data A1 I
6. AVRL Vcc AVcc 3 0V to 5 5V Vss AVss Parameter Resolution Total error Nonlinearity error Differential nonlineari ty error Zero reading voltage Full scale reading AVRH 1 LSB voltage 5 Compare time 4 5V lt AVcc lt 5 5V us 3 0V lt AVcc lt 4 5V 5 0 5 1 0 16 500 u 4 Sampling time Analog port input cur 300 1 Analog input voltage AVRL b AVRH V range Reference voltage range mA Converter active Power supply current AD Converter not operated 1 mA AC Converter active Reference voltage cur rent AD Converter not operated Offset between input channels 1 If A D converter is not operating a current when CPU is stopped is applicable VCC AVCC AVRH 5 0 Note The accuracy gets worse as AVRH AVRL becomes smaller Definition of A D Converter Terms Resolution Analogue variation that is recognized by an A D converter Non linearity error Deviation between a line across zero transition line 00 0000 0000 lt gt 00 0000 0001 and full scale transition line 11 1111 1110 lt gt 11 1111 1111 and actual conversion characteristics FME EMDC 2007 11 14 MB96300 DS el _adc fm 103 96380 Series Specification Differential linearity error Deviation of input voltage which is required for changing output code by 1 LSB from an ideal value Total
7. Max Units Remarks Pin floating HAKX J time txHAL HAKX HAKX f time Pin valid time Ta 40 to 125 Vcc 3 0 to 4 5 Vss 0 0 IOarve Ci 50pF m Value Parameter Condition Units Remarks Min Max HAKX Each pin Refer to the Hardware Manual for detailed Timing Charts FME EMDC 2007 11 14 MB96300_DS_el_AC_ext_bus fm 97 96380 Series Specification 98 FME EMDC 2007 11 14 MB96300_DS_el_AC_ext_bus fm Specification USART timing MB96380 Ta 40 C to 125 C Vcc 3 0V to 5 5V Vss AVss DVss C 50pF Parameter Serial clock cycle time tscvci SCK SOT delay 1 time SOT SCK T delay tovsHi time Valid SIN gt 5 tivsHi SCK gt Valid SIN hold time Serial clock L pulse width Serial clock pulse width SLSHE SHSLE SCK SOT delay tsLove time Valid SIN gt SCK T TIVSHE SCK T gt Valid SIN hold time SCK fall time SCK rise time tsHixe Vcc AVcc 4 5V to 5 5V Condition Vcc AVcc 3 0V to 4 5V 4 30 N tcike1 Internal Shift 20 Clock Mode N tcLkp1 307 lcuke1 45 10 10 55 ns QL 1 an 0 ns 0
8. register address pointer low byte 000135 6 register address pointer high byte 000136H DMA6 Data counter low byte 000137H DMA6 Data counter high byte 000180H General Purpose registers RAM access GPR RAM RW 000380H DMAO Interrupt select DISELO 000381H Interrupt select DISEL1 RW 000382H Interrupt select DISEL2 000383H Interrupt select DISEL3 000384H Interrupt select DISEL4 000385H DMAS Interrupt select DISEL5 000386H DMA6 Interrupt select DISEL6 FME EMDC 2007 11 14 MB96380_DS_memory fm 37 38 96380 Series 000390H DMA7 DMAO status register Abbreviation 8 bit access DSRL Specification Abbreviation 16 bit access DSR RW Access 000392H DMA7 DMAO stop status register DSSRL DSSR RW 000394H DMA7 DMAO enable register DERL DER RW 0003A0H Interrupt level register ILR ICR RW RW 0003A2H Interrupt vector Table base register TBRL TBR RW RW 0003A3H Interrupt vector Table base register 0003A4H Delayed Interrupt register RW 0003A5H Non maskable Interrupt register RW 0003ACH EDSU communication interrupt selection W 0003ADH EDSU communication interrupt selection W W R R 0003AEH ROM mirror control register ROMM R R 0003AFH EDSU configuration register 0003BOH Memory patch control status register
9. Notes on PLL clock mode operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied the microcontroller attempts to work with the free oscillating PLL Performance of this operation however cannot be guaranteed Power supply pins Vcc Vss It is required that all Vcc level as well as all Vss level power supply pins are at the same potential If there is more than one Vcc or Vss level the device may operate incorrectly or be damaged even within the guaranteed operating range Vcc and Vss must be connected to the device from the power supply with lowest possible impedance As a measure against power supply noise it is required to connect a bypass capacitor of about 0 1 uF between Vcc and Vss as close as possible to Vcc and Vss pins Crystal oscillator circuit Noise at XO or X1 pins might cause abnormal operation It is required to provide bypass capacitors with shortest possible distance to X1 pins crystal oscillator or ceramic resonator and ground lines and to the utmost effort that the lines of oscillation circuit do not cross the lines of other circuits It is highly recommended to provide a printed circuit board art work surrounding and X1 pins with a ground area for stabilizing the operation It is highly recommended to evaluate the quartz MCU system at the quartz manufacturer Turn on sequence of power supply to A D converter and analog inputs It is required to tu
10. Yes 35 es 36 Specification Programmable Pulse Generator 6 Programmable Pulse Generator 7 RLTO Reload Timer 0 Reload Timer 1 RLT2 Yes 37 Reload Timer 2 RLT3 Yes 38 Reload Timer 3 PPGRLT 39 Reload Timer 6 dedicated for PPG ICUO Yes 40 Input Capture Unit 0 41 Input Capture Unit 1 Input Capture Unit 2 Input Capture Unit 3 Input Capture Unit 4 46 47 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7 Output Compare Unit 0 Output Compare Unit 1 Output Compare Unit 2 52 53 Output Compare Unit 3 Free Running Timer 0 Free Running Timer 1 Real Timer Clock Clock Calibration Unit Sound Generator 0 Sound Generator 1 IICO Yes 58 I2C interface ALARMO Yes 59 A D Converter Alarm Comparator 0 ALARM1 Alarm Comparator 1 LINRO LIN USART 0 RX LINTO 2 2 8 2F4 LINR1 Yes LIN USART 0 TX LIN USART 1 RX LIN USART 1 TX 2F0 54 FME EMDC 2007 11 14 64 66 7 LINR2 Yes LIN USART 2 RX LINT2 Yes 6 LIN USART 2 TX MB96380_DS_memory fm Specification MB96380 Interrupt vector table MB96 F 38x 3 3 Offset in Index in vector ta Vector name bY J ICR to pro Description gram LINR4 Yes 68 LIN USART 4 RX LINT4 Yes 69 LIN USART 4 TX 70 2E4 LINR5 LIN USART 5 RX 71 2E0 LINT5 LIN USART 5 TX 72 2DC MAIN_FLASH Main Flash
11. 1 1 External Shift __ 2 ns 55 2 45 Clock Mode tc kr 2 10 10 Notes AC characteristic in CLK synchronized mode e Chis the load capacity value of pins when testing e Depending on the used machine clock frequency the maximum possible baud rate can be limited by some tcukei 2 E 10 IE __ __ ns 10 20 20 ns 20 20 ns parameters These parameters are shown 96300 Super series HARDWARE MANUAL is the cycle time of the peripheral clock 1 CLKP1 Unit ns 1 Parameter depends on tscvci and can be calculated as follows if tscvci 2 1 then where is an integer gt 2 if tscvci 2 k 1 tcike1 then N k 1 where is an integer gt 1 Examples FME EMDC 2007 11 14 4 tcLkP1 6 7 8 tcLKP1 MB96300 DS el AC usart fm 99 96380 Series Specification SCK for ESCR SCES 0 SCK for ESCR SCES 1 SOT SIN E tc 0 8 Vcc 0 2 Vcc 0 2 Vcc 0 8 Vcc 0 8 Vcc 0 2 Vcc LLL 0 8 Vcc 0 2 Vcc 5 Internal Shift Clock Mode VIH VIL VIH VIL SCK for ESCR SCES 0 SCK for ESCR SCES 1 100 FME EMDC 2007 11 14 SLSHE
12. 4MHz SM CR LPMSS 0 Main Timer mode with CLKMC 4MHz SM CR LPMSS 1 Value Max Unit Remarks CLKRC and CLKSC stopped Core voltage at 1 9V 1 Flash wait state CLKPLL CLKRC and CLKSC stopped Volt age regulator in high power mode 1 Flash wait state CLKPLL CLKRC and CLKSC stopped Volt age regulator in low pow er mode 1 Flash wait state Power supply cur rent in Timer modes lccrRcH ccTRcL 72 FME EMDC 2007 11 14 RC Timer mode with CLKRC 2MHz SM CR LPMSS 0 RC Timer mode with CLKRC 2MHz SM CR LPMSS 1 RC Timer mode with CLKRC 100kHz SM CR LPMSS 0 CLKMC CLKPLL and CLKSC stopped Volt age regulator in high power mode 1 Flash wait state CLKMC CLKPLL and CLKSC stopped Volt age regulator inlow pow er mode 1 Flash wait state CLKMC CLKPLL and CLKSC stopped Volt age regulator in high power mode 1 Flash wait state RC Timer mode with CLKRC 100kHz SM CR LPMSS 1 CLKMC CLKPLL and CLKSC stopped Volt age regulator in low pow er mode 1 Flash wait state MB96300_DS_el_DC_char fm Specification MB96380 Ta 40 C to 125 C Vcc AVcc 3 0V to 5 5V DVcc 3 0V to 5 5V Vss AVss DVss OV Power supply cur rent in Timer modes lccrsuB Condition Sub Timer mode with CLKSC 32kHz Value Max Unit Remarks CLKMC CLKPLL and CLKRC stopp
13. 86 FME EMDC 2007 11 14 MB96380 DS el AC HC slew rate fm Specification MB96380 External Bus timing WARNING The values given below are for an IOarive of 5MA If is 2MA all the maximum output timing described in the different tables must then be increased by 10ns Basic Timing Ta 40 C to 125 C Voc 5 0 10 Vss 0 0 5mA Ci 50pF Value Parameter Symbol Condition Max Unit 10 2 5 5 tcvc 24 5 gt CSn UBX LBX CSn time LBX 10 gt ALE time ALE ECLK 10 gt address valid time A 23 16 a ECLK 15 15 15 id ti t 15 OM ita en CLAV 15 ECLK gt address valid time E AD 15 0 tcHRWH RDX WRX l ECLK gt RDX WRX time CHRWL WRLX WRHX tcLRWH Berk Ta 40 C to 125 C Vcc 3 0 to 4 5 Vss 0 0 lOvrive 5 50pF ACID Parameter Symbol Condition Unit tcvc 24 8 tcvc 2 8 2 8 2007 11 14 MB96300_DS_el_AC_ext_bus fm 87 88 96380 Series Specification Ta 40 to 125 C Vcc 3 0 to 4 5V Vss 0 0 V lOvrive 5mA CL 50pF ACID Parameter Symbol Condition Unit 25 25 ECLK gt UBX LBX CSn time ECLK gt ALE time
14. Abbreviation 8 bit access MB96380 Abbreviation 16 bit access Access 0003C8H Memory Patch function Patch address 5 middle 0003C9H Memory Patch function Patch address 5 high 0003CAH 0003CBH Memory Patch function Patch address 6 middle 0003CCH Memory Patch function Patch address 6 low Memory Patch function Patch address 6 high PFAM6 0003CDH Memory Patch function Patch address 7 low 0003CEH Memory Patch function Patch address 7 middle 0003CFH Memory Patch function Patch address 7 high 0003DOH 0003D1H Memory Patch function Patch data O 0003D2H Memory Patch function Patch data 0 Memory Patch function Patch data 1 PFDHO 0003D3H Memory Patch function Patch data 1 0003D4H Memory Patch function Patch data 2 0003D5H 0003D6H Memory Patch function Patch data 3 0003D7H Memory Patch function Patch data 3 0003D8H Memory Patch function Patch data 4 0003D9H Memory Patch function Patch data 2 Memory Patch function Patch data 4 PFDL3 PFDH3 PFDL4 0003DAH Memory Patch function Patch data 5 0003DBH 0003DCH Memory Patch function Patch data 6 0003DDH Memory Patch function Patch data 6 0003DEH Memory Patch function Patch data 7 0003DFH Memory Patch function Patch data 5 Memory Patch function Patch data 7 PFDL6 PFDH6 PFDL7 PFDH7 0003F1H Flash Memory Configura
15. I O Port Port Output Drive Register PODRO3 RW RW W 000485 P05 I O Port Port Output Drive Register PODRO5 R 000486H P06 I O Port Port Output Drive Register PODRO6 RW 000488 P08 I O Port Port Output Drive Register PODRO8 RW 000489H 9 I O Port Port Output Drive Register PODRO09 00048AH P10 I O Port Port Output Drive Register PODR10 00048 P11 I O Port Port Output Drive Register PODR11 00048CH 12 I O Port Port Output Drive Register PODR12 RW 00048DH P13 Port Port Output Drive Register PODR13 00049CH P08 I O Port Port High Drive Register PHDRO8 00049DH 09 1 Port Port High Drive Register PHDRO9 00049 P10 I O Port Port High Drive Register PHDR10 0004A8H P00 I O Port Pull Up resistor Control Register PUCROO 0004A9H P01 I O Port Pull Up resistor Control Register PUCRO1 0004 P02 I O Port Pull Up resistor Control Register PUCRO2 0004ABH I O Port Pull Up resistor Control Register PUCROS 0004ACH P04 I O Port Pull Up resistor Control Register 4 0004ADH P05 I O Port Pull Up resistor Control Register PUCRO5 0004AEH P06 I O Port Pull Up resistor Control Register PUCRO6 0004BOH 08 Port Pull Up resistor Control Register PUCRO8 0004B1H P09 I O Port Pull Up resistor Control Register PUCRO9 0004B2H P10 I O Port Pull Up resistor Control Register PUCR10 0004B3H P11 I
16. 3 0V to 5 5V Vss AVss DVss OV Input H voltage Condition Port inputs if CMOS Hysteresis 0 8 0 2 input is selected Port inputs if CMOS Hysteresis 0 7 0 3 input is selected D Vcc gt 4 5V lt 4 5 Port inputs if AU TOMOTIVE Hys teresis inputis se lected Port inputs if TTL input is selected MD2 MDO ViHxoF Input L voltage X0 Port inputs if CMOS Hysteresis 0 8 0 2 input is selected Port inputs if CMOS Hysteresis 0 7 0 3 input is selected RSTX input pin CMOS Hysteresis MDx input pins External clock in Fast Clock Input mode Port inputs if AU TOMOTIVE Hys teresis inputis se lected Port inputs if TTL input is selected D Vcc 2 4 5V D Vcc 4 5V RSTX RSTX input pin CMOS Hysteresis MD2 MDO MDx input pins ViLxoF FME EMDC 2007 11 14 X0 External clock in Fast Clock Input mode MB96300 DS el DC charfm 67 96380 Series Specification Ta 40 C to 125 C Vcc 3 0V to 5 5V DVcc 3 0 to 5 5V Vss AVss DVss Normal and High Current outputs Normal and High Current outputs Condition 4 5V lt D Vcc 5 5V 2mA 3 0V lt D Vcc lt 4 5V lou 1 6mA 4 5V lt D Vcc 5 5V 5mA 3 0V lt D Vcc 4 5V 3mA Driving strength set to 2mA Driving
17. EACL STS 1 and EACL ACE 1 3tcvc 2 15 other ECL STS EACL ACE setting tcvc 2 15 Valid address f time A 23 0 AD 15 0 ECLK tcvc 20 2 20 RDX f time RDX CLK tevc 2 15 ALE 4 time ALE RDX EACL STS 0 2 15 EACL STS 1 15 ECLKT Valid data input FME EMDC 2007 11 14 AD 15 0 ECLK 55 MB96300 DS el ext bus fm Specification MB96380 tavcH ve a ADVCH ECLK 0 8 Vcc tav L gt 4 lADvLL RHLH tRLRH gt RDX taxDx AD 15 0 Address Read data VIL VIL Refer to the Hardware Manual for detailed Timing Charts Bus Timing Write Ta 40 C to 125 C Vcc 5 0 V 10 Vss 0 0 50pF Parameter Valid address WRX J time WRX WRLX WRHX A 23 16 Condition EACL ACE 0 Remarks 2 15 EACL ACE 1 2 15 Valid address WRX J time Non Multiplexed WRX WRLX WRHX A 23 0 EACL STS 0 2 15 EACL STS 1 tcvc 15 Valid address WRX J time tapvwL WRX WRLX WRHX AD 15 0 EACL ACE 0 15 EACL ACE 1 15 WRX pulse width FME EMDC 2007 11 14 WR
18. FME EMDC 2007 11 14 EACHO EACL1 EACH1 MB96380_DS_memory fm 47 48 96380 Series Abbreviation OOO6E4H External bus Area configuration register 2 Specification Abbreviation 16 bit access Access RW 0006E5H External bus Area configuration register 2 RW 0006E6H External bus Area configuration register 3 RW 0006E7H External bus Area configuration register 3 R 0006E9H External bus Area configuration register 4 EACH4 W 0006E8H External bus Area configuration register 4 EACL4 EAC4 RW RW W 0006 External bus Area configuration register 5 R 0006EBH External bus Area configuration register 5 RW 0006ECH External bus Area select register 2 RW 0006EDH External bus Area select register R 0006EFH External bus Area select register 5 EAS5 W 0006 External bus Area select register 4 EAS4 RW RW W 0006FOH External bus Mode register EBM R 0006F1H External bus Clock and Function register EBCF RW 0006F2H External bus Address output enable register 0 EBAEO RW 0006F3H External bus Address output enable register 1 EBAE1 0006F4H External bus Address output enable register 2 2 0006F5H External bus Control signal register EBCS 000700H CANO Control register CTRLRLO CTRLRO RW 000701H Control register reserved CTRLRHO 000702H Status register STAT
19. Internal or external voltage generation Duty cycle Selectable from options 1 2 1 3 and 1 4 Fixed 1 3 bias Programmable frame period Clock source selectable from three options peripheral clock subclock or RC oscillator clock On chip drivers for internal divider resistors or external divider resistors On chip data memory for display LCD display can be operated in Timer Mode Blank display selectable All SEG COM and V pins can be switched between general and specialized purposes External divided resistors can be also used to shut off the current when LCD is deactivated 8 bit PWM signal is mixed with tone frequency from 16 bit reload counter PWM clock by internal prescaler 1 1 2 1 4 1 8 of peripheral clock Tone frequency PWM frequency 2 reload value 1 Real Time Clock FME EMDC 2007 11 14 Can be clocked either from sub oscillator devices with partnumber suffix W main oscillator or from the RC oscillator Facility to correct oscillation deviation of Sub clock or RC oscillator clock clock calibration Read write accessible second minute hour registers Can signal interrupts every halfsecond second minute hour day Internal clock divider and prescaler provide exact 1s clock MB96300 DS features fm 5 96380 Series Specification WWW Feature Description External Interrupts Edge sensitive or level sensitive Interrupt mask and pending bit per channel Each available CAN ch
20. PPG6 Period setting register 000568H PPG6 Duty cycle register 000569H PPG6 Duty cycle register 00056 PPG6 Control status register PCNL6 00056 PPG6 Control status register 00056 PPG7 Timer register 00056DH PPG7 Timer register 00056 PPG7 Period setting register 00056FH PPG7 Period setting register 000571H PPG7 Duty cycle register 000572H PPG7 Control status register 000573H PPG7 Control status register 0005 SMCO PWM control register internal 0005E1H SMCO extended control register Output enable PWECO 0005E2H SMCO PWM control register PWM 0 0005E3H SMCO PWM control register PWM 0 0005E4H SMCO PWM control register PWM 1 PWC10 0005E5H SMCO PWM control register PWM 1 0005E6H SMCO PWM Select register internal 0005E7H SMCO PWM Select register PWS20 0005EAH SMC1 PWM control register internal PWC1 0005EBH SMC1 extended control register Output enable PWEC1 0005ECH SMC1 PWM control register PWM 1 0005EDH SMC1 PWM control register PWM 1 0005EEH SMC1 PWM control register PWM 2 0005EFH SMC1 PWM control register PWM 2 0005 SMC1 PWM Select register internal PWS11 0005F1H SMC1 PWM Select register PWS21 0005 SMC2 PWM control register internal 0005F5H SMC2 extended control register Output enable 0005F6H SMC2 PWM control regi
21. SHSLE External Shift Clock Mode MB96300 DS el AC usart fm Specification PC Timing MB96380 Ta 40 C to 125 C Vcc 3 0V to 5 5V Vss AVss DVss Parameter SCL clock frequency Hold time repeated START condition SDAl gt SCL L width of the SCL clock H width of the SCL clock THDSTA THIGH Set up time for a repeated START condition SCLT gt SDAY tsusTA Data hold time SCLI gt SDAJT HDDAT Data set up time SDALTSSCLT Set up time for STOP condition SCLT gt SDAT tsuDAT tsusto Bus free time between a STOP and START condition taus Standard mode Fast mode Min Min Max Condition 1 R C Pull up resistor and load capacitor of the SCL and SDA lines 2 The maximum have only to be met if the device does not stretch the L width tow of the SCL signal 3 Fast mode I C bus device can be used a Standard mode I C bus system but the requirement tsupat gt 250 ns must then be met 4 For use at over 100 kHz set the peripheral clock 1 to at least 6 MHz gt tHDSTA FME EMDC 2007 11 14 THDSTA MB96300_DS el 2 101 96380 Series Specification 102 FME EMDC 2007 11 14 MB96300_DS_el_AC_i2c fm Specification MB96380 5 Analogue Digital Converter Ta 40 C to 125 C 3 0
22. tcHCBH tcHCBL tcLcBH CSn UBX LBX ALE ECLK gt address valid time gt address valid time non Multiplexed tcLav A 23 16 ECLK A 23 0 EBM NMS 1 gt address valid time tcLaDv AD 15 0 ECLK gt RDX WRX time FME EMDC 2007 11 14 tcHRWH ICHRWL tcLRWH tcLRWL RDX WRX WRLX WRHX ECLK MB96300 DS el ext bus fm Specification MB96380 tove 8 V ECLK 0 8 Vcc A 23 0 tcLcBH CSn LBX tcHRWH RDX WRX WRLX WRHX ALE tcLaDv AD 15 0 Refer to the Hardware Manual for detailed Timing Charts FME EMDC 2007 11 14 MB96300_DS_el_AC_ext_bus fm 89 90 96380 Series Bus Timing Read Ta 40 C to 125 C Vcc 5 0 10 Vss 0 0 50pF Parameter ALE pulse width Conditions EACL STS 0 and EACL ACE 0 Specification tcvc 2 5 EACL STS 1 tove 5 EACL STS 0 and EACL ACE 1 2 5 Valid address gt ALE J time ALE A 23 16 EACL STS 0 and EACL ACE 0 15 EACL STS 1 and EACL ACE 0 3tcvc 2 15 EACL STS 0 and EACL ACE 1 15 EACL STS 1 and EACL ACE 1 2 15 TADVLL ALE AD 15 0 EACL STS 0 and EACL ACE 0 te
23. 11 14 MB96380 MB96380_DS_pin_circuit_type fm 20 96380 Series NN 120 21 Circuit type 90 to 91 Supply 92 to 112 113 to 116 117 to 119 120 1 Devices with suffix 2 Devices without suffix W FME EMDC 2007 11 14 Specification MB96380_DS_pin_circuit_type fm Specification MB96380 I O CIRCUIT TYPE Circuit Standby control signal Remarks Oscillation circuit High speed oscillation feedback resistor approx 1 MQ Do Xout Standby control signal Oscillation circuit Low speed oscillation feedback resistor approx 10 MQ Hysteresis inputs Mask ROM and EVA device CMOS Hysteresis input pin Flash device CMOS input pin Pull up Resistor Hysteresis inputs FME EMDC 2007 11 14 CMOS Hysteresis input pin Pull up resistor value approx 50 KQ Power supply input protection circuit MB96380 DS pin circuit type fm 21 96380 Series Circuit pull up control Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input Hysteresis input Automotive inputs TTL
24. 2007 11 14 MB96380_DS_memory fm Specification Abbreviation 00011CH DMAS I O register address pointer low byte MB96380 Abbreviation 16 bit access Access 00011DH DMAS I O register address pointer high byte 00011EH DMAS Data counter low byte 00011FH DMAS Data counter high byte 000120H DMA4 Buffer address pointer low byte BAPL4 000121H DMAZ4 Buffer address pointer middle byte BAPM4 000122 DMAZ4 Buffer address pointer high byte BAPH4 000123H DMA4 DMA control register DMACS4 000124H DMAZ4 I O register address pointer low byte IOAL4 000125H DMAZ4 I O register address pointer high byte 000126 Data counter low byte DCTL4 000127H Data counter high byte 000128 DMA5 Buffer address pointer low byte 000129H DMA5 Buffer address pointer middle byte 00012AH DMAS Buffer address pointer high byte 00012BH DMA5 DMA control register DMACS5 00012CH DMAS I O register address pointer low byte IOAL5 00012DH DMAS register address pointer high byte 5 00012 DMAS Data counter low byte 00012FH DMAS Data counter high byte 000130H DMA6 Buffer address pointer low byte 000131H DMA6 Buffer address pointer middle byte BAPM6 000132 DMA6 Buffer address pointer high byte BAPH6 000133H DMA6 DMA control register DMACS6 000134H 6
25. CAN1 IF2 Data A1 IF2DTA1H1 R 000850H CAN1 IF2 Data A2 IF2DTA2L1 IF2DTA21 RW 000851 CAN1 IF2 Data A2 IF2DTA2H1 RW 000852H CAN1 IF2 Data IF2DTB1L1 000853H CAN1 IF2 Data IF2DTB1H1 000854H CAN1 IF2 Data B2 IF2DTB2L1 000855H CAN1 IF2 Data B2 IF2DTB2H1 IF2DTB11 IF2DTB21 RW 000880H CAN1 Transmission Request Register TREQR1L1 TREQR11 000881H CAN1 Transmission Request Register TREQR1H1 000882H CAN1 Transmission Request Register TREQR2L1 TREQR21 u gt 000883H CAN1 Transmission Request Register TREQR2H1 000890H CAN1 New Data Register NEWDT1L1 NEWDT11 000891H CAN1 New Data Register NEWDT1H1 000892H 1 New Data Register NEWDT2L1 NEWDT21 000893H 1 New Data Register NEWDT2H1 0008A0H CAN 1 Interrupt Pending Register INTPND1L1 INTPND11 D D 22 Dd 0008A1H CAN1 Interrupt Pending Register INTPND1H1 0008A2H CAN1 Interrupt Pending Register INTPND2L1 INTPND21 0008A3H CAN1 Interrupt Pending Register INTPND2H1 0008BOH 1 Message Valid Register MSGVAL1L1 MSGVAL11 0008 1 Message Valid Register MSGVAL1H1 0008B2H CAN1 Message Valid Register MSGVAL2L1 MSGVAL21 d 0008B3H 1 Message Valid Register MSGVAL2H1 COER1 0008 Output enable register FME EMDC 2007 11 14 RW MB96380_DS_
26. I O Port Data Direction Register 00043DH P13 I O Port Data Direction Register 000445H P01 I O Port Port Input Enable Register PIERO1 000446H P02 I O Port Port Input Enable Register PIERO2 000447H I O Port Port Input Enable Register 000448H P04 Port Port Input Enable Register PIERO4 000449H P05 I O Port Port Input Enable Register PIERO5 00044 P08 I O Port Port Input Enable Register PIERO8 00044DH 09 1 Port Port Input Enable Register PIERO9 00044 P10 I O Port Port Input Enable Register PIER10 00044FH P11 I O Port Port Input Enable Register PIER11 000450H P12 I O Port Port Input Enable Register PIER12 000451H P13 I O Port Port Input Enable Register PIER13 000458H P00 I O Port Port Input Level Register PILROO 000459 P01 Port Port Input Level Register PILRO1 00045AH P02 I O Port Port Input Level Register PILRO2 00045BH Port Port Input Level Register PILRO3 00045CH PO4 I O Port Port Input Level Register PILRO4 00045DH P05 I O Port Port Input Level Register PILRO5 00045EH P06 I O Port Port Input Level Register PILRO6 000460H P08 I O Port Port Input Level Register PILRO8 000461H P09 I O Port Port Input Level Register PILRO9 000462H P10 I O Port Port Input Level Register PILR10 000463H P11 I O Port Port Input Level Register PILR11 000464H P12 I O Port Port Input Level Register PILR12 0
27. O Port Pull Up resistor Control Register PUCR11 0004B4H P12 I O Port Pull Up resistor Control Register 12 0004B5H P13 Port Pull Up resistor Control Register PUCR13 FME EMDC 2007 11 14 MB96380_DS_memory fm Specification MB96380 Address pg sss 0004BCH I O Port External Pin State Register EPSROO 0004BDH P01 I O Port External Pin State Register EPSRO1 0004BEH P02 I O Port External Pin State Register EPSRO2 0004BFH P03 I O Port External Pin State Register EPSROS 0004C1H P05 I O Port External Pin State Register EPSRO5 0004C2H P06 I O Port External Pin State Register EPSRO6 0004C4H P08 I O Port External Pin State Register EPSRO08 0004C5H P09 I O Port External Pin State Register EPSRO9 0004C6H P10 I O Port External Pin State Register EPSR10 0004C8H 12 I O Port External Pin State Register EPSR12 0004C9H P13 I O Port External Pin State Register EPSR13 0004DOH ADC analog input enable register 0 ADERO 0004D1H ADC analog input enable register 1 ADER1 0004D2H ADC analog input enable register 2 ADER2 d D d d D D Dd D 2 0004D3H ADC analog input enable register 3 ADER3 0004D4H ADC analog input enable register 4 ADER4 0004D6H Peripheral Resource Relocation Register 0 0004D7H Peripheral Resource Relocation Register 1 0004D8H Peripheral Resource Relocation Register 2 0004D9H Peripheral Resource Rel
28. Vss pins The DVcc power supply level can be set independently of the Vcc power supply level However note that the SMC I O pin state is undefined if DVcc is powered on and Vcc is below To avoid this we recommend to always power Vcc before DVcc FME EMDC 2007 11 14 MB96300_DS_handling fm 59 96380 Series Specification 60 FME EMDC 2007 11 14 MB96300_DS_handling fm Specification ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings MB96380 WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings Rating Parameter Symbol Unit Vcc Vss 0 3 Vss 6 0 Power supply voltage AVcc Vss 0 3 Vss 6 0 AD Converter voltage references AVRH AVRL Vss 0 3 Vss 6 0 Vcc AVoc 1 AVcc gt AVcc gt AVRL AVRH gt AVRL AVRL gt AVss SMC Power supply Vss 0 3 Vss 6 0 V V V V See 7 V LCD power supply voltage to V3 VO to V3 must not exceed Vcc input voltage Vs 03 Vs 60 Vi Output voltage Vo Vss 0 3 Vss 6 0 Vix D Vcc 0 3V 2 V V Vo lt D Vec 0 3V 2 Maximum Clamp Current Applicable to general purpose mA pins Total Maximum Clamp Current Applicable to general purpose mA I O pins 3 L level maximum output current lor
29. block diagram Memory map modified for Flash RAM memory map added Pin circuit type corrected Type L IO is now included MB96380 DS revisionsfm 121 96380 Series Specification 122 FME EMDC 2007 11 14 MB96380_DS_revisions fm
30. ch 0 1 RW 0003B1H Memory patch control status register ch 0 1 RW 0003B2H Memory patch control status register ch 2 3 0003B3H Memory patch control status register ch 2 3 0003B4H Memory patch control status register ch 4 5 0003B5H Memory patch control status register ch 4 5 RW 0003B6H Memory patch control status register ch 6 7 0003B7H Memory patch control status register ch 6 7 0003B8H Memory Patch function Patch address 0 low 0003B9H Memory Patch function Patch address 0 middle 0003BAH Memory Patch function Patch address 0 high 0003BBH Memory Patch function Patch address 1 low PFAMO PFAHO 0003BCH Memory Patch function Patch address 1 middle 0003BDH Memory Patch function Patch address 1 high 0003BEH Memory Patch function Patch address 2 low 0003BFH Memory Patch function Patch address 2 middle 0003C0H Memory Patch function Patch address 2 high 0003C1H Memory Patch function Patch address 3 low PFAM2 PFAH2 0003 2 Memory Patch function Patch address 3 middle 0003C3H Memory Patch function Patch address 3 high 0003C4H Memory Patch function Patch address 4 low 0003C5H Memory Patch function Patch address 4 middle 0003C6H Memory Patch function Patch address 4 high FME EMDG 2007 11 14 PFAM4 PFAH4 MB96380_DS_memory fm Specification Address 0003 7 Memory Patch function Patch address 5 low
31. in this mode Regulator in Low Power Mode B Core Voltage 1 8 V MB96300_DS_el_example_char fm 116 Specification MB96380 PACKAGE DIMENSION MB96 F 38x LQFP 120P 120 pin plastic LQFP Lead pitch 0 50 mm Package width x 16 0 x 16 0 mm package length Lead shape Gullwing Sealing method Plastic mold Mounting height 1 70 mm MAX Weight 0 88 g Code P LFQFP120 16x16 0 50 120 pin plastic LQFP FPT 120P M21 18 00 0 20 709 008 SQ 16 00 220 630 204 SQ O O FME EMDC 2007 11 14 210 08 003 Details of A part 1 50 910 Mounting height 059 785 gene O NM Y 0 10 0 05 LEAD 1 004 002 0 50 020 0 22 0 05 1519 08 003 0 145 o3 0 60 0 15 Stand off Od 009 002 0062 024 006 025 010 Dimensions mm inches 2002 FUJITSU LIMITED F120033S c 4 4 Note The values in parentheses are reference values MB96380_DS_package fm 117 96380 Series Specification 118 FME EMDC 2007 11 14 MB96380_DS_package fm Specification ORDERING INFORMATION Satellite Persistant Part number flash Subclock Low Volt memory Reset MB96384YSA PMC GSE2 MB96384RSA PMC GSE2 MB96384YWA PMC GSE2 MB96384RWA PMC GSE2 MB96385YSA PMC GSE2 MB96385RSA PMC GSE2 MB96385YWA PMC GSE2 MB96385RWA PMC GSE2 MB96F386YSA PMC GSE2
32. memory interrupt 73 2D8 SAT_FLASH Sat Flash memory interrupt and MainFlash are not included for MB96384 and MB96385 devices SAT FLASH are available only for MB96F388 devices FME EMDC 2007 11 14 MB96380 DS memoryfm 55 96380 Series Specification 56 FME EMDC 2007 11 14 MB96380_DS_memory fm Specification MB96380 HANDLING DEVICES Special care is required for the following when handling the device Latch up prevention Unused pins handling External clock Unused sub clock signal Notes on PLL clock mode operation Power supply pins Vcc Vss Crystal oscillator circuit Turn on sequence of power supply to A D converter and analog inputs A D converter unused pins handling Notes on energization Stabilization of power supply voltage SMC power supply pins 1 Latch up prevention CMOS IC chips may suffer latch up under the following conditions A voltage higher than VCC or lower than VSS is applied to an input or output pin A voltage higher than the rated voltage is applied between VCC and VSS The AVCC power supply is applied before the VCC voltage Latch up may increase the power supply current dramatically causing thermal damages to the device For the same reason extra is required to not let the analog power supply voltage AVcc AVRH exceed the digital power supply voltage 2 Unused pins handling Unused input pins can be left op
33. programmable lo 5mA lou 5mA and lo 2mA 2mA lot 30mA 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull up registor 50kQ approx Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown pull up control Hysteresis input Hysteresis input Automotive inputs TTL input 24 FME EMDC 2007 11 14 CMOS level output lo 3mA 3mA 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull up registor approx MB96380_DS_pin_circuit_type fm Specification MB96380 MEMORY 96 300 MB96 F 38x Ef ELLE Start address of User ROM area and Emulation Main Flash number of small sector ROM depends on the device Satellite Flash Sat RCB available on devices with suffix T and H external external Bus Bus Boot ROM external RAM internal internal RAM availability and mapping depending on device ROM RAM ROM RAM Mirror Mirror internal RAM RAMSTART Reserved E
34. 00465H P13 I O Port Port Input Level Register PILR13 00046CH P00 I O Port Extended Port Input Level Register EPILROO 00046DH P01 I O Port Extended Port Input Level Register EPILRO1 00046 P02 Port Extended Port Input Level Register EPILRO2 00046FH I O Port Extended Port Input Level Register EPILRO3 000470H P04 I O Port Extended Port Input Level Register EPILRO4 000471H P05 I O Port Extended Port Input Level Register EPILRO5 FME EMDC 2007 11 14 MB96380_DS_memory fm 41 42 96380 Series Abbreviation 000472H 06 Port Extended Port Input Level Register EPILRO6 Specification Abbreviation 16 bit access Access RW 000474H 08 Port Extended Port Input Level Register EPILRO8 RW 000475H P09 I O Port Extended Port Input Level Register EPILRO9 RW 000476H P10 I O Port Extended Port Input Level Register EPILR10 R 000478H P12 I O Port Extended Port Input Level Register EPILR12 W 000477 P11 Port Extended Port Input Level Register EPILR11 RW RW W 000479H P13 I O Port Extended Port Input Level Register EPILR13 R 000480H P00 I O Port Port Output Drive Register PODROO RW 000481H P01 I O Port Port Output Drive Register PODRO1 RW 000482 P02 I O Port Port Output Drive Register PODRO2 R 000484H P04 I O Port Port Output Drive Register PODRO4 W 000483H
35. 004AH ICU3 Capture Register IPCPL3 IPCP3 00004BH ICU3 Capture Register IPCPH3 R 00004CH ICU4 ICU5 Control Status Register ICS45 00004DH ICU4 ICU5 Edge register ICE45 00004EH ICUA Capture Register IPCPL4 00004FH ICU4 Capture Register IPCPH4 000050H ICU5 Capture Register IPCPL5 IPCP5 000051H ICU5 Capture Register 5 R 000052H ICU6 ICU7 Control Status Register ICS67 000053H ICU6 ICU7 Edge register ICE67 000054H ICU6 Capture Register IPCPL6 000055H ICU6 Capture Register IPCPH6 000056H ICU7 Capture Register IPCPL7 IPCP7 000057H ICU7 Capture Register IPCPH7 R 000058H EXTINTO External Interrupt Enable Register ENIRO EXTINTO External Interrupt Interrupt request Reg 000059H icter EIRRO 00005AH EXTINTO External Interrupt Level Select ELVRLO 00005 EXTINTO External Interrupt Level Select ELVRHO 000060 RLTO Timer Control Status Register Low TMCSRLO 000061 RLTO Timer Control Status Register High TMCSRHO FME EMDC 2007 11 14 TMCSRO MB96380_DS_memory fm Specification Abbreviation 000062H RLTO Reload Register Low TMRLRO MB96380 Abbreviation 16 bit access TMRO Access 000063H RLTO Reload Register High TMRHRO 000064H RLT1 Timer Control Status Register Low TMCSRL1 TMCSR1 000065H RLT1 Timer Control Status Register High TMCSRH1 000066H RLT1 Reload R
36. 0074EH CANO IF2 Data 1 IF2DTA1LO IF2DTA10 00074FH CANO IF2 Data A1 IF2DTA1HO 000750H CANO IF2 Data A2 IF2DTA2LO IF2DTA20 RW 000751H CANO IF2 Data A2 IF2DTA2HO RW FME EMDC 2007 11 14 MB96380_DS_memory fm 49 50 96380 Series Abbreviation 8 bit access IF2DTB1LO 000752H CANO IF2 Data Specification Abbreviation 16 bit access IF2DTB10 Access RW 000753H CANO IF2 Data IF2DTB1HO RW 000754H IF2 Data B2 IF2DTB2LO IF2DTB20 RW 000755H IF2 Data B2 IF2DTB2HO 000780H CANO Transmission Request Register TREQR1LO RW D ID 000781H CANO Transmission Request Register TREQR1HO 000782H Transmission Request Register TREQR2LO TREQR20 000783H CANO Transmission Request Register TREQR2HO 000790H CANO New Data Register NEWDT1LO NEWDT10 000791 New Data Register NEWDT1HO 000792H CANO New Data Register NEWDT2L0 000793H CANO New Data Register NEWDT2HO 0007 Interrupt Pending Register INTPND1LO NEWDT20 INTPND10 gt 0007A1H CANO Interrupt Pending Register INTPND1H0 0007A2H Interrupt Pending Register INTPND2LO INTPND20 0007A3H Interrupt Pending Register INTPND2HO MSGVAL1LO 0007 CANO Message Valid Register 0007B1H CANO Message Valid Register MSGVAL1H
37. 0080H PPG1 Timer register 000081H PPG1 Timer register R R 000082 PPG1 Period setting register PCSR1 000083H PPG1 Period setting register FME EMDC 2007 11 14 MB96380_DS_memory fm 33 34 96380 Series 000085H PPG1 Duty cycle register Abbreviation 8 bit access Specification Abbreviation 16 bit access Access 000086H PPG1 Control status register 000087H PPG1 Control status register 000088H 2 Timer register R 00008AH PPG2 Period setting register PCSR2 00008BH PPG2 Period setting register 00008CH PPG2 Duty cycle register 00008DH PPG2 Duty cycle register 00008EH PPG2 Control status register 00008FH PPG2 Control status register 000090H Timer register 000091H PPGS3 Timer register PCNH2 000092H Period setting register 000093H Period setting register 000094H Duty cycle register 000095H Duty cycle register 000096H PPG3 Control status register 000097H PPG3 Control status register PCNL3 PCNH3 000098H PPG7 PPG4 General Control register 1 Low GCN1L1 000099H PPG7 PPG4 General Control register 1 High GCN1H1 00009 PPG7 PPG4 General Control register 2 Low 00009BH PPG7 PPG4 General Control register 2 High GCN2L1 GCN2H1 00009CH PPG4 Timer register PTMR4 00009DH PPG4 Timer regi
38. 07 11 14 not used lt 0 004 ud MB96300 DS el LVD char fm us 109 Specification MB96380 NH LOW VOLTAGE DETECTOR OPERATION In the following figure the occurence of a low voltage condition is illustrated For a detailed description of the reset and startup behavior please refer to the corresponding hardware manual chapter Voltage V Time s Normal Operation 2 Low Voltage Reset Assertion S Power Reset Extension Time FME EMDC 2007 11 14 MB96300 DS el LVD charfm 110 Specification MB96380 8 FLASH memory program erase characteristics Ta 25 C Voc 5 0V Parameter Min Sector erase time Erasure programming time not included Chip erase time is the number of Flash sector of the device Word 16 bit width pro gramming time System overhead time not in cluded Programme Erase cycle 100 000 cycles for Ta lt 80 C Flash data retention time El 1 This value was converted from the results of evaluating the reliability of the technology using Arrhenius equation to convert high temperature measurements into normalized value at 85 C FME EMDC 2007 11 14 MB96300 DS el Flash fm 111 96380 Series Specification 112 2007 11 14 MB96300 DS el Flash fm Specification MB96380 EXAMPLE CHARACTERISTICS The diagrams below show the characteristics of one measured sample
39. 08 5 PWM1M1 DVss DVcc P08_4 PWM1P1 08 S PWM2MO P08 2 PWM2PO 08 1 PWM1MO P08_0 PWM1PO P05_7 AN15 TOT2 SGA1_R SEG64 P05_6 AN14 TIN2 SGO1_R SEG63 P05_5 AN13 TX1 SEG62 9 2 1 AN9 ALARM1 SEG58 P05_0 AN8 ALARM0 SEG57 MB96380_DS_pin_assignement fm 13 96380 Series Specification 14 FME EMDC 2007 11 14 MB96380_DS_pin_assignement fm Specification MB96380 PIN FUNCTION DESCRIPTION Pin Function description 1 3 Feature Description External bus interface nonmultiplexed mode data input output External bus interface multiplexed mode address data input output ADn External bus ADTG ADC A D converter trigger input Alarm Comparator n input External bus External bus Address Latch Enable output ALARMn Alarm comparator ALE An External bus External bus non multiplexed mode address output A D converter channel n input ANn ADC AVCC Supply Analogue circuits power supply AVRH ADC A D converter high reference voltage input Alternative A D converter high reference voltage input I AVRH2 AVRL AID converter low reference voltage input AVSS Supply Analogue circuits power supply Voltage regulator Internally regulated power supply stabilization capacitor pin Clock output function CKOTn Clock Output function n output CKOTXn Clock output function Clock Output Function n inverted output LCD COM pins LCD E
40. 1 tcvc 20 WRX gt CSn time WRX CSn time Non Multiplexed FME EMDC 2007 11 14 WRX WRLX WRHX CSn WRX WRLX WRHX CSn EACL STS 0 2 20 EACL STS 1 20 MB96300_DS_el_AC_ext_bus fm 95 96380 Series twLcH 0 8 Vcq ECLK tavwL taDvwL www m WRX WRLX WRHX O 3 tovwH 0 2 Vcc lwHcsH T Specification Refer to the Hardware Manual for detailed Timing Charts Ready Input Timing Ta 40 C to 125 C Voc 5 0 V 10 Vss 0 0 IOarve 5mA Ci 50pF Rated Value Parameter i Test Condition Min RDY setup time 35 RDY hold time Remarks Ta 40 C to 125 C Vcc 3 0 to 4 5 Vss 0 Parameter i Test Condition RDY setup time RDY hold time Remarks Note If the RDY setup time is insufficient use the auto ready function 96 FME EMDC 2007 11 14 MB96300 DS el AC ext bus fm Specification MB96380 0 8 Vcc ECLK tRYHS 97 tRYHH VIH4 V VIH RDY When WAIT is not used RDY When WAIT is used Refer to the Hardware Manual for detailed Timing Charts Hold Timing Ta 40 C to 125 C Vcc 5 0 V 10 Vss 0 0 5mA Ci 50pF Parameter Symbol Pin Condition
41. 41 OCU 0 1 2 3 1 ee parator 2 ch lt a ALARMI 3 gt lO Timer 1 T ICU 4 5 6 7 TTGO TTG7 Sch PPGO PPG7 Stepper PWM1PO0 Motor PWM2MO gt Controller PWM2P0 5 ch DVCC DVSS External Real Time gt INTO INT7 interrupt lt gt Clock NOT MB96380 DS block diagram fm 11 96380 Series Specification 12 FME EMDC 2007 11 14 MB96380_DS_block_diagram fm Specification PIN ASSIGNMENTS Pin assignment of MB96 F 38x P12_3 0UT2_R A12 SEG7 P00_1 1 NT4_R WRHX SEG13 0 NT3_R HAKX SEG12 P12_7 INT1_R HRQ SEG11 P12 6 TOT2 R A15 SEG10 P12 2 R A14 SEG9 2 INT5 R RDY SEG14 P12 4 OUT3 R A13 SEG8 o o gt Vss P00_3 INT6_R A00 CS3_R SEG15 P00_4 INT7_R ALE SEG16 P00_5 TTG2 TTG6 IN6 RDX SEG17 P00_6 TTG3 IN7 WRLX TTG8 SEG18 P00 7 SGOO ECLK SEG19 P01_0 SGA0 AD00 SEG20 P01 1 OUTO CKOT1 ADO1 SEG 1 P01 2 OUT1 CKOTX1 ADO2 SEG22 P01_3 PPG5 AD03 SEG23 P01_4 AD04 SIN4 SEG24 P01_5 AD05 SOT4 SEG25 P01_6 AD06 SCK4 SEG26 P01_7 CKOTX1_R AD07 SEG27 P02_0 CKOT1_R AD08 SEG28 P02_1 IN6_R AD09 SEG29 P02 2 IN7 R AD10 SEG30 2 5 0 R AD11 SEG31 P02 4 SGA0 R AD12 SEG32 P02_5 OUTO_R AD13 SEG33 P02_6 0UT1_R AD14 SEG34 P02_7 PPG5_R AD15 SEG35 P03_0 V0 A16 SEG36 P03_1 V1 A17 SEG37 P03_2 V2 A18 SEG38 P03_3 V3 A19 SEG39 P03_4 INT4 RXO 5 TXO 6 NMI INTO Vc
42. 6F386Y MB96F387Y MB96F388H MB96F389Y Alternative mode Flash memory Main Flash size Main Flash size Main Flash size Main Flash size CPU address mode address 288kByte 416kByte 576kByte 832kByte FF FFFFh 3F FFFFh en on 39 64K 39 64 39 64K 39 64K FFFFh 3E FFFFh oN 538 64K 38 64K S38 64K S38 64K FD FFFFh 3D FFFFh S37 64K S37 64K S37 64K S37 64K 2 6 64K 36 64K 36 64K FC 0000h 3C 0000h 536 536 64K 2 FB FFFFh 3B FFFFh FB 0000h 3B 0000h 535 64K S35 64K S35 64K FA FFFFh 3A FFFFh FA 0000h 3A 0000h S34 64K S34 64K 534 64K F9 FFFFh 39 FFFFh an Se muse 0 annnm T 7 0000 37 0000 31 64K F6 FFFF FFFF F5 0000h 35 0000h 29 64K FA FFFFh 34 FFFFh S28 64K F4 0000h 34 0000h 7 F3 FFFFh 33 FFFFh F3 0000h 33 0000h F2 FFFFh 32 FFFFh F2 0000h 32 0000h F1 FFFFh 31 FFFFh F1 0000h 31 0000h FO FFFFh 30 FFFFh F0 0000h 30 0000h EO FFFFh 20 00005 20 0000 8 steps 8k steps Jepma 18 60001 M SA3 8K 3553 55 5 m DE 4000p 12000 SA2 SK sa2 3K W 52 W 3A sK DF 2000h 1F 2000 a 5 1 8 SA1 8K I 5 1 8 a 5 1 8 BF 0000n 16 06600 SA0 8K g SA0 8K N SA0 8K B 5408K 8k steps 8k steps DE 4000h 1 1000 a A A SB2 8K a SB2 8K DB 2000h 2000h E E 5 1 8 E gt E s BE 00008 15 05550 E 5 0 8K I MB96380_D
43. 6Y MB96F387R MB96F387Y MB96F388T MB96F388H MB96F389R MB96F389Y Package BGA416 FPT 120P M21 DMA 16 channels 7 channels USART 10 channels 5 channels 2 2 channels 1 channel A D Converter 40 channels 16 channels A D Converter I Reference Voltage switch yes Only for MB96F386R MB96F386Y MB96F387R MB96F387Y 16 bit Reload 6 channels 4 channels 1 channel for PPG 16 bit Free Running Timer 4 channels FME EMDC 2007 11 14 2 channels MB96380 DS lineup fm 9 96380 Series NN Features MB96V300B Specification MB9638x 16 bit Output Compare 12 channels 4 channels 16 bit Input Capture 12 channels 8 channels 16 bit Programmable Pulse Generator 20 channels 8 channels CAN Interface 5 channels 2 channels MB96384R MB96384Y MB96385R MB96385Y 1 channel Stepping Motor Controller 6 channels 5 channels External Interrupts 16 channels 8 channels Non Maskable Interrupt 1 channel Sound generator 2 channels 2 channels LCD Controller 4 COM x 72 SEG 4 COM x 65 SEG Real Time Clock 1 1 0 Ports 136 94 for part number with suffix W 96 for part number with suffix S Alarm comparator 2 channels 2 channels MB96384R MB96384Y MB96385R MB96385Y 1 channel External bus i
44. 88 MB96F389 Internal peripheral clock fre quency Clock 2 CLKP2 FME EMDG 2007 11 14 All devices MB96300 DS el AC int clk fm 77 96380 Series Specification 78 FME EMDC 2007 11 14 MB96300_DS_el_AC_int_clk fm Specification MB96380 External Reset timing Ta 40 C to 125 C Vcc 3 0V to 5 5 DVcc 3 0 to 5 5 Vss AVss DVss p wwe A M Reset inputtime tem RSTX 500 RSTX FME EMDC 2007 11 14 MB96300 DS el AC ext rst m 179 96380 Series Specification 80 FME EMDC 2007 11 14 MB96300_DS_el_AC_ext_rst fm Specification MB96380 Power On Reset timing Ta 40 C to 125 C Vcc AVcc 3 0V to 5 5 DVcc 3 0 to 5 5 Vss AVss DVss Power rise time 0 05 30 Power off time torF Vcc 1 ms Due to repetitive operation torr If the power supply is changed too rapidly a power on reset may occur We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation as shown in the figure below This action can be performed only while not using the PLL clock However if voltage drops are below 1 V s it is possible to operate while using the PLL clock Rising edge of 50 mV ms QV cole d maximum is allowed FME EMDC 2007 11 14 MB96300 DS el AC pon
45. BH CANO IF1 Arbitration register IF1ARB2HO 00071CH CANDO IF1 Message Control Register IFIMCTRLO IFIMCTRO 00071DH CANO IF1 Message Control Register IFIMCTRHO 00071EH IF1 Data 1 IF1DTA1LO 00071FH IF1 Data A1 IF1DTA1HO IF1DTA10 000720H IF1 Data A2 IF1DTA2LO IF1DTA20 000721H CANO IF1 Data A2 IF1DTA2HO 000722H CANO IF1 Data B1 IF1DTB1LO 000723H CANO IF1 Data IF1DTB1HO RW 000724H CANO IF1 Data B2 IF1DTB2LO IF1DTB20 RW 000725H CANO IF1 Data B2 IF1DTB2HO RW 000740H CANO IF2 Command request register IF2CREQLO IF1DTB10 IF2CREQO 000741H CANO IF2 Command request register 000742H IF2 Command Mask register IF2CMSKLO 000743H IF2 Command Mask register reserved IF2CMSKHO R 000744H CANO IF2 Mask Register IF2MSK1LO IF2MSK10 RW 000745 CANO IF2 Mask Register IF2MSK1HO RW 000746H CANO IF2 Mask Register IF2MSK2LO IF2CMSKO IF2MSK20 000747H IF2 Mask Register IF2MSK2HO 000748H IF2 Arbitration register IF2ARB1L0 IF2ARB10 000749H IF2 Arbitration register IF2ARB1HO 00074AH IF2 Arbitration register IF2ARB2LO IF2ARB20 RW 00074BH IF2 Arbitration register IF2ARB2HO RW 00074CH IF2 Message Control Register IF2MCTRLO IF2MCTRO 00074DH IF2 Message Control Register IF2MCTRHO 0
46. CLK External bus External bus clock output External bus External bus chip select n output FRCKn Free Running Timer Free Running Timer n input HAKX External bus External bus Hold Acknowlegde External bus External bus Hold Request Input Capture Unit n input INn INn_R Relocated Input Capture Unit n input External Interrupt External Interrupt n input External Interrupt Relocated External Interrupt n input External bus INTn_R LBX External Bus Interface Lower Byte select strobe output Core Input pins for specifying the operating mode External Interrupt Non Maskable Interrupt input FME EMDC 2007 11 14 MB96300_DS_pin_function_desc fm 15 96380 Series Specification Pin Function description 2 3 Feature Description Output Compare Unit n waveform output OUTn_R Relocated Output Compare Unit n waveform output Programmable Pulse Generator n output I S SMC PWM high current RDX External bus External bus interface read strobe output External bus External bus interface external wait state request input RXn CAN interface n RX input USART n serial clock input output I2C interface n clock I O input output SDAn 2 interface n serial data input output SEGn LCD segment n I I SGO Sound Generator SG sound tone output SGA_R Sound Generator SG amplitude output SINn USART n serial data input USART n serial data output TINn_R Reload Timer Reloca
47. Cascading TMISR W 000520H USART4 Serial Mode Register SMR4 RW W R 000521H USART4 Serial Control Register SCR4 R 000522H USARTA TX Register W 000522H USART4 RX Register R 000523H USARTA Serial Status RW 000524H USART4 Control Com Register internal ESCR4 BGRL4 000525H USART4 Ext Status Register 000526H USART4 Baud Rate Generator Register Low 000527H USART4 Baud Rate Generator Register High RW 000528H USART4 Extended Serial Interrupt Register 00052 USARTS Serial Mode Register 00052 USARTS Serial Control Register 00052CH USART5 RX Register TDR5 W 00052CH USART5 TX Register RDR5 R 00052DH USART5 Serial Status 00052EH USARTS Control Com Register 00052FH USARTS Ext Status Register 000530H USART5 Baud Rate Generator Register Low 000531H USART5 Baud Rate Generator Register High 000532H USART5 Extended Serial Interrupt Register 000560H ALARMO Control Status Register BGRH5 ESIR5 ACSRO 000561 ALARMO Extended Control Status Register AECSRO 000562H ALARM Control Status Register ACSR1 000563H ALARM Extended Control Status Register AECSR1 000564H PPG6 Timer register PTMR6 R FME EMDC 2007 11 14 MB96380_DS_memory fm Specification Abbreviation 000566H PPG6 Period setting register MB96380 Abbreviation 16 bit access Access 000567
48. EMDC 2007 11 14 MB96300 DS el abs max rat fm 63 96380 Series Specification 64 FME EMDC 2007 11 14 MB96300_DS el abs max rat fm Specification MB96380 2 Recommended Conditions Value Parameter Typ Max Power supply voltage Vcc DVcc 5 5 V capacitor at Cs 10 uF Use a X7R Ceramic Capacitor 0 70 MB96V300B Operating temperature Ta C 40 125 WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the devices electrical characteristics are guarranted when the device is operated within these ranges Semiconductor devices must always be operated within their recommended operating condition ranges Oper ation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU repre sentatives beforehand 1 If used at a temperature exceeding Ta 105 C please contact Fujitsu for reliability limitations FME EMDC 2007 11 14 MB96300 DS el rec condfm 65 96380 Series Specification 66 FME EMDC 2007 11 14 MB96300_DS_el_rec_cond fm Specification 3 DC characteristics MB96380 Ta 40 C to 125 C Vcc AVcc 3 0V to 5 5V DVcc
49. F1DTA1H1 000820H CAN1 IF1 Data A2 IF1DTA2L1 000821H CAN1 IF1 Data A2 IF1DTA2H1 RW 000822H CAN1 IF1 Data B1 IF1DTB1L1 IF1DTB11 RW 000823H CAN1 IF1 Data IF1DTB1H1 IF1DTA21 000824H CAN1 IF1 Data B2 IF1DTB2L1 IF1DTB21 000825H CAN1 IF1 Data B2 IF1DTB2H1 000840H CAN1 IF2 Command request register IF2CREQL1 000841H CAN1 IF2 Command request register IF2CREQH1 000842H CAN1 IF2 Command Mask register IF2CMSKL1 IF2CMSK1 RW FME EMDC 2007 11 14 IF2CREQ1 RW MB96380_DS_memory fm 51 52 96380 Series Abbreviation 8 bit access IF2CMSKH1 000843H CAN1 IF2 Command Mask register reserved Specification Abbreviation 16 bit access Access R 000844H CAN1 IF2 Mask Register IF2MSK1L1 IF2MSK11 RW 000845H CAN1 IF2 Mask Register IF2MSK1H1 RW 000846H CAN1 IF2 Mask Register IF2MSK2L1 IF2MSK21 R 000848H IF2 Arbitration register IF2ARB1L1 IF2ARB1 1 W 000847H CAN1 IF2 Mask Register IF2MSK2H1 RW RW 000849H CAN1 IF2 Arbitration register IF2ARB1H1 R 00084AH CAN1 IF2 Arbitration register IF2ARB2L1 IF2ARB21 RW 00084BH 1 IF2 Arbitration register IF2ARB2H1 RW 00084CH CAN1 IF2 Message Control Register IF2MCTRL1 IF2MCTR1 R 00084EH 1 IF2 Data 1 IF2DTA1L1 IF2DTA1 1 W 00084DH CAN1 IF2 Message Control Register IF2MCTRH1 RW RW W 00084FH
50. Fast Clock Input mode not available in MB96V300 MB96F386A and MB96F387A PLL off When using a single phase external clock in Fast Clock Input mode not available in MB96V300 MB96F386A and MB96F387A PLL on Clock frequency When using an oscillation circuit When using an opposite phase external clock When using a single phase external clock Clock frequency Clock frequency feLkvco When using slow frequency of RC oscil lator When using fast frequency of RC oscil lator VCO output frequency of PLL CLKVCO Inputclockpulse width Pw Duty ratio is about 30 to 70 Inputclockpulse width FME EMDC 2007 11 14 MB96300 DS el src clk fm 75 96380 Series Specification 76 FME EMDC 2007 11 14 MB96300_DS_el_AC_src_clk fm Specification Internal Clock timing MB96380 Ta 40 C to 125 C Vcc AVcc 3 0 to 5 5V DVcc 3 0 to 5 5 Vss AVss DVss Parameter Core Voltage Settings Remarks Internal System clock fre quency CLKS1 and CLKS2 Internal System clock fre quency CLKS1 and CLKS2 82 MB96v300B MB96F38x Internal CPU clock frequen cy CLKB internal periph eral clock frequency CLKP1 Internal CPU clock frequen cy CLKB internal periph eral clock frequency CLKP1 MB96v300B MB96F38x MB96F3
51. L level average output current L level maximum output current love Normal outputs for normal drive mA output port setting 5 Normal outputs for normal drive output port setting High current outputs L level average output current loLava High current outputs L level maximum overall output current L level maximum overall output current L level average overall output current Zlouav1 Normal outputs for normal drive output port setting High current outputs Normal outputs for normal drive output port setting level average overall output current XloLava High current outputs H level maximum output current lou H level average output current H level maximum output current 5 Normal outputs for normal drive output port setting mA Normal outputs for normal drive output port setting High current outputs H level average output current loHav2 High current outputs H level maximum overall output current level maximum overall output current FME EMDC 2007 11 14 Normal outputs for normal drive output port setting 330 mA High current outputs MB96300 DS el abs max rat fm 61 96380 Series Specification Parameter Symbol Unit Normal outputs for normal drive H level average overall output current Xlouavi output port setting H level average overa
52. LCD Data register for Segment LCD Data register for Segment VRAM14 VRAM15 VRAM16 00063BH LCD Data register for Segment VRAM17 00063CH LCD Data register for Segment VRAM18 00063DH 00063EH LCD Data register for Segment 41 40 00063FH LCD Data register for Segment 000640H LCD Data register for Segment 000641H LCD Data register for Segment LCD Data register for Segment VRAM19 VRAM20 VRAM21 VRAM22 VRAM23 000642H LCD Data register for Segment VRAM24 000643H 000644H LCD Data register for Segment 000645H LCD Data register for Segment 000646H LCD Data register for Segment 000647H LCD Data register for Segment 51 50 LCD Data register for Segment VRAM25 VRAM26 VRAM27 VRAM28 VRAM29 000648H LCD Data register for Segment 61 60 VRAM30 000649H LCD Data register for Segment VRAM31 00064AH 000660H Peripheral Resource Relocation Register 10 000661H Peripheral Resource Relocation Register 11 000662H Peripheral Resource Relocation Register 12 LCD Data register for Segment VRAM32 PRRR10 PRRR11 PRRR12 000663H Peripheral Resource Relocation Register 13 PRRR13 0006 External bus Area configuration register 0 EACLO 0006E1H External bus Area configuration register 0 0006 2 External bus Area configuration register 1 0006 External bus Area configuration register 1
53. LX WRHX A 23 16 EACL STS 1 Condition EACL ACE 0 15 3tcvc 2 20 EACL ACE 1 2 20 Valid address WRX J time Non Multiplexed FME EMDC 2007 11 14 WRX WRLX WRHX A 23 0 EACL STS 0 2 20 EACL STS 1 tove 20 MB96300_DS_el_AC_ext_bus fm Specification Valid address WRX J time WRX pulse width Valid data output gt WRX f time tapvwL WRX WRLX WRHX AD 15 0 WRX WRLX WRHX WRX WRLX WRHX AD 15 0 Condition EACL ACE 0 tcvc 20 EACL ACE 1 2lcvc 20 tove 25 MB96380 w o cycle extension w o cycle extension WRX T Data hold time WRX WRLX WRHX AD 15 0 2 20 WRX T Address valid time WRX WRLX WRHX A 23 16 EACL STS 0 2 20 WRX T Address valid time Non Multiplexed WRX WRLX WRHX A 23 0 EACL STS 1 20 WRX T ALE f time WRX WRLX WRHX ALE EBM ACE 1 and EACL STS 1 15 other EBM ACE and EACL STS setting tcvc 15 WRX L gt ECLKT time WRX WRLX 2 15 CSn gt WRX time tesiwL WRX WRLX WRHX CSn EACL ACE 0 2 20 EACL ACE 1 btcvc 2 20 CSn gt WRX time Non Multiplexed WRX WRLX CSn EACL STS 0 tcvc 2 20 EACL STS
54. MB96F386RSA PMC GSE2 MB96F386YWA PMC GSE2 MB96F386RWA PMC GSE2 MB96F387YSA PMC GSE2 MB96F387RSA PMC GSE2 MB96F387YWA PMC GSE2 MB96F387RWA PMC GSE2 MB96F388TSA PMC GSE2 MB96F388HSA PMC GSE2 MB96F388TWA PMC GSE2 MB96F388HWA PMC GSE2 MB96F389YSA PMC GSE2 MB96F389RSA PMC GSE2 MB96F389YWA PMC GSE2 MB96F389RWA PMC GSE2 MB96380 Package Remarks 120 pin Plastic LQFP FPT 120P M21 MB96V300RB ES FME EMDC 2007 11 14 Emulated by ext RAM 416 pin Plastic BGA BGA416 M02 For evalua tion MB96380 DS order fm 96380 Series Specification 120 FME EMDC 2007 11 14 MB96380_DS_order fm Specification REVISION HISTORY Revision 2007 05 2 MB96380 Modification Creation 2007 05 24 Electrical characteristics and memory description updates 2007 08 09 2007 08 31 Typo errors corrections Flash memory programming interface update Update of DC characteristics new 388 and 389 added LVD chapter added as well as an example characteristics chapter 2007 09 06 Updates of the DC characteristics interrupt vector table update update of the LVD characteristics 2007 11 14 FME EMDC 2007 11 14 Memory map for external bus modified Modifications of the drawing of the pin circuits Electrical characteristics updates Rephrasing and typos corrections Add Slew rate high current outputs chapter Modification of the
55. Main clock timer control register MCTCR 00040AH Sub clock timer control register SCTCR 00040BH ias cause and clock status register with clear unction 00040CH Reset configuration register 00040DH Reset cause and clock status register RCCSRC RCR 00040EH Watch dog timer configuration register 00040FH Watch dog timer clear pattern register 000415H output activation register 000416H Clock output configuration register 0 initial 000417H Clock output configuration register 1 initial 000418H Clock Modulator control register COCRO COCR1 00041AH Clock Modulator Parameter register Low 00041BH Clock Modulator Parameter register High 00042CH Voltage Regulator Control register 000430H 00 Port Data Direction Register 000431H 01 Data Direction Register 000432H PO2 Port Data Direction Register DDROO DDRO1 000433H Port Data Direction Register 000434H P04 Port Data Direction Register 000435H P05 I O Port Data Direction Register 000436H P06 I O Port Data Direction Register 000438H P08 I O Port Data Direction Register 000439H P09 I O Port Data Direction Register FME EMDC 2007 11 14 DDRO6 DDRO8 DDRO9 MB96380_DS_memory fm Specification MB96380 00043AH P10 I O Port Data Direction Register 00043BH P11 I O Port Data Direction Register 00043CH P12
56. O 0007B2H CANO Message Valid Register MSGVAL2LO MSGVAL10 MSGVAL20 gt 0007B3H Message Valid Register MSGVAL2H0 0007 Output enable register COER0 RW 0007 SGO Sound Generator Control Register Low SGCRL0 R 0007D1H SGO Sound Generator Control Register High SGCRHO W RW 0007D2H SGO Sound Generator Frequency Register SGFRO RW W 0007D3H SGO Sound Generator Amplitude Register SGARO R 0007D4H SGO Sound Generator Decrement Register SGDRO RW 0007D5H SGO Sound Generator Tone Register SGTRO RW 0007D6H SG1 Sound Generator Control Register Low SGCRL1 W 0007D7H SG1 Sound Generator Control Register High SGCRH1 W W W R R 0007D8H SG1 Sound Generator Frequency Register SGFR1 R R 0007D9H 591 Sound Generator Amplitude Register SGAR1 0007DAH SG1 Sound Generator Decrement Register SGDR1 RW 0007DBH SG1 Sound Generator Tone Register SGTR1 RW 000800H 1 Control register CTRLRL1 CTRLR1 R 000801H CAN1 Control register reserved W 000802H 1 Status register STATRL1 STATR1 RW FME EMDG 2007 11 14 MB96380 DS memory fm Specification Abbreviation 000803H Status register reserved STATRH1 MB96380 Abbreviation 16 bit access Access 000804H CAN1 Error Counter Transmit ERRCNTL1 ERRCNT1
57. O Buffer address pointer middle byte BAPMO R W 000102H Buffer address pointer high byte BAPHO RW RW W 000103H DMAO DMA control register DMACSO 000104H DMAO I O register address pointer low byte R 000105H I O register address pointer high byte RW 000106 DMAO Data counter low byte RW 000107H DMAO Data counter high byte RW 000108H DMA1 Buffer address pointer low byte BAPL1 000109H DMA1 Buffer address pointer middle byte BAPM1 00010 1 Buffer address pointer high byte BAPH1 00010BH DMA1 DMA control register DMACS1 00010CH DMA1 I O register address pointer low byte IOAL1 00010DH DMA1 register address pointer high byte IOAH1 00010 DMA1 Data counter low byte DCTL1 00010FH DMA1 Data counter high byte DCTH1 000110H DMA2 Buffer address pointer low byte BAPL2 000111H DMA2 Buffer address pointer middle byte BAPM2 000112H DMA2 Buffer address pointer high byte BAPH2 000113H DMA control register DMACS2 000114H DMA2 I O register address pointer low byte IOAL2 000115 DMA2 register address pointer high byte IOAH2 000116 DMA2 Data counter low byte 000117 DMA2 Data counter high byte 000118H DMAS Buffer address pointer low byte 000119H DMAS Buffer address pointer middle byte 00011AH DMAS Buffer address pointer high byte BAPHS 00011BH DMA control register DMACS3 36 FME EMDC
58. RH Analog input Non linearity error of digital output N Differential linearity error of digital output N 1 LSB MB96380 Differential linearity error Ideal characteristics N 1 Actual conversion characteristics EN te 5 8 V N T ON 1L M ___ actual measurement i value VNT actual measurement value N 2 Lu l i r Actual conversion characteristics AVRL AVRH Analog input m x Ver 1L8Bx N 1 Ved 1 LSB net en 1 LSB LSB TLSB LSB Vest A A 1022 V Vor Voltage at which digital output transits from 000v to 001 Vest Voltage at which digital output transits from to SFFu Notes on A D Converter Section About the external impedance of the analog input and the sampling time of the A D converter with sample and hold circuit If the external impedance is too high to keep sufficient sampling time the analog voltage charged to the internal sample and hold capacitor is insufficient adversely affecting A D conversion precision Analogue input circuit model Analog input po Sampling switch Reference value C 8 5 pF 2007 11 14 MB96300 DS el adcfm 105 96380 Series Specification 106 To satisfy the A D conversion precision standard the relationship between the external impedance and minimum sampling time must be considered and t
59. RLO STATRO 000703H CANO Status register reserved STATRHO 000704H Error Counter Transmit ERRCNTLO ERRCNTO 000705H Error Counter Receive ERRCNTHO R 000706H bit Timing Register BTRLO 000707H CANO bit Timing Register BTRHO 000708H CANO Interrupt Register INTRLO 000709H Interrupt Register INTRHO 00070AH CANO Test Register TESTRLO TESTRO 00070BH CANO Test Register reserved TESTRHO R 00070CH CANO BRP Extension register BRPERLO BRPERO 00070DH CANO BRP Extension register reserved BRPERHO 000710H IF1 Command request register IFiCREQLO IF1CREQO 000711H CANO IF1 Command request register IF1CREQHO 000712H IF1 Command Mask register IF1CMSKLO IFICMSKO RW 000713H IF1 Command Mask register reserved IF1CMSKHO R FME EMDC 2007 11 14 MB96380 DS memory fm Specification 000714H CANO IF1 Mask Register Abbreviation 8 bit access IF1MSK1LO MB96380 Abbreviation 16 bit access IF1MSK10 Access 000715H CANO IF1 Mask Register IF1MSK1HO 000716H CANO IF1 Mask Register IFIMSK2LO IFIMSK20 000717H CANO IF1 Mask Register IFIMSK2HO 000718H IF1 Arbitration register IF1ARB1LO 000719H CANO IF1 Arbitration register IF1ARB1HO IF1ARB10 00071AH CANO IF1 Arbitration register IF1ARB2LO IF1ARB20 00071
60. Register 3 Seq 31 24 000620H LCD Output Enable Register 4 Seq 39 32 000622H LCD Output Enable Register 6 Seq 55 48 LCDER3 LCDER4 LCDER5 LCDER6 000623H LCD Output Enable Register 7 Seq 63 56 LCDER7 000624H LCD Output Enable Register 8 Seq 71 64 LCDER8 000626H LCD Output Enable Register Vx 000627H LCD Extended Control Register 000628H LCD Common pin switching register 000629H LCD Control Register LCDVER LECR LCDCMR 00062AH LCD Data register for Segment 0 1 00062BH LCD Data register for Segment 3 2 00062CH LCD Data register for Segment 5 4 00062DH LCD Data register for Segment 00062EH LCD Data register for Segment FME EMDC 2007 11 14 VRAM3 VRAM4 MB96380_DS_memory fm Specification 00062FH LCD Data register for Segment 11 10 Abbreviation 8 bit access MB96380 Abbreviation 16 bit access Access 000630H LCD Data register for Segment 000631H LCD Data register for Segment 000632H 000633H LCD Data register for Segment 000634H LCD Data register for Segment LCD Data register for Segment 21 20 VRAM9 VRAM10 000635H LCD Data register for Segment VRAM1 1 000636H LCD Data register for Segment VRAM12 000637H LCD Data register for Segment VRAM13 000638H 000639H LCD Data register for Segment 31 30 00063AH
61. S_memory fm 27 96380 Series Specification ROM CONFIGURATION MB96384 MB96385 CPU address FF FFFFh ROM size 128kByte ROM size 128kByte FD 0000h DF 7FFFh pone ROM configuration DF 0000h block 28 FME EMDC 2007 11 14 MB96380_DS_memory fm Specification PARALLEL PROGRAMMING FLASH MEMORY CONTROL SIGNALS Flash memory control signals MD 2 0 111 MB96F38X Pin number LQFP Normal function Flash memory mode 32 P05 4 TMODIX 33 to 35 to 5 AQ19 to AQ21 3 P03_7 RY BY 12 to 13 P13 4 to 5 P04_4 to P04 5 AQ8 to AQ9 AQ10 to AQ11 10 to 11 P13 6to P13 7 AQ12 to AQ13 14 to 15 26 to 27 P06 0 to PO6 1 P05 0 to PO5 1 AQ22 to AQ23 AQ14 to AQ15 P05 2 87 to 89 92 to 96 97 to 104 P00_0 to P00 7 P01 Oto 7 DQO to DQ7 DQ8 to DQ15 105 to 112 P02_0 to P02 7 AQO to AQ7 117 to 118 P03_4 to _5 119 6 FME EMDC 2007 11 14 MB96380 a gt MB96380_DS_memory fm 96380 Series Specification SERIAL PROGRAMMING COMMUNICATION INTERFACE USART pins for Flash serial programming MD 2 0 010 Pin number LQFP 120 MB96F38x USART Number USARTO USART1 USART2 Normal function Note For handshaking pin please use for thi
62. Unit Remarks CLKRC and CLKSC stopped Core voltage at 1 9V 2 Flash wait state PLL Run mode with CLKS1 2 48MHz CLKB CLKP1 2 24MHz Main Run mode with CLKS1 2 CLKB CLKP1 2 4MHz RC Run mode with CLKS1 2 CLKB CLKP1 2 2MHz CLKRC and CLKSC stopped Core voltage at 1 9V 0 Flash wait states CLKPLL CLKSC and CLKRC stopped 1 Flash wait state CLKMC CLKPLL and CLKSC stopped 1 Flash wait state FME EMDC 2007 11 14 RC Run mode with CLKS1 2 CLKB CLKP1 2 100kHz SM CR LPMS 0 CLKMC CLKPLL and CLKSC stopped Volt age regulator in high power mode 1 Flash wait state RC Run mode with CLKS1 2 CLKB 2 100kHz SM CR LPMS 1 CLKMC CLKPLL and CLKSC stopped Volt age regulator in low pow er mode no Flash pro gramming erasing allowed 1 Flash wait state MB96300 DS el DC char fm 69 96380 Series Specification Ta 40 C to 125 C Vcc 3 0V to 5 5V DVcc 3 0V to 5 5V Vss AVss DVss OV Power supply cur 70 FME EMDC 2007 11 14 Condition Sub Run mode with CLKS1 2 CLKB CLKP1 2 32kHz Value Remarks Max Unit CLKMC CLKPLL and CLKRC stopped no Flash programming erasing allowed 1 Flash wait state MB96300_DS_el DC_char fm Specification MB96380 Ta 40 C to 125 C Vcc A
63. Vcc 3 0V to 5 5V DVcc 3 0V to 5 5V Vss AVss DVss OV Iccsp L Iccsma n Condition PLL Sleep mode with CLKS1 2 CLKP1 56MHz CLKP2 28MHz Value Max Unit Remarks CLKRC and CLKSC stopped 1 Flash wait state PLL Sleep mode with CLKS1 2 48 2 CLKP1 2 24MHz Main Sleep mode with CLKS1 2 CLKP1 2 4MHz CLKRC and CLKSC stopped 1 Flash wait state CLKPLL CLKRC and CLKSC stopped 1 Flash wait state Power supply cur rent in Sleep IccsRcH modes RC Sleep mode with CLKS1 2 CLKP1 2 2MHz CLKMC CLKPLL and CLKSC stopped 1 Flash wait state IccsrcL RC Sleep mode with CLKS1 2 CLKP1 2 100kHz SM CR LPMSS 0 RC Sleep mode with CLKS1 2 CLKP1 2 100kHz SM CR LPMSS 1 CLKMC CLKPLL and CLKSC stopped Volt age regulator in high power mode 1 Flash wait state CLKMC CLKPLL and CLKSC stopped Volt age regulator in low pow er mode 1 Flash wait state IccssuB FME EMDC 2007 11 14 Sub Sleep mode with CLKS1 2 CLKP1 2 32kHz CLKMC CLKPLL and CLKRC stopped 1 Flash wait state MB96300 DS el charfm 71 96380 Series Specification Ta 40 C to 125 C Vcc 3 0V to 5 5V DVcc 3 0V to 5 5V Vss AVss DVss OV ccTPLL Condition PLL Timer mode with CLKMC 4MHz PLL 56MHz Main Timer mode with CLKMC
64. X WRXL WRHX tove 5 MB96300_DS_el_AC_ext_bus fm w o cycle extension 93 96380 Series Specification 94 Ta 40 C to 125 C Vcc 5 0 V 10 Vss 0 0 5mA 50pF Parameter Valid data output f time WRX WRLX WRHX AD 15 0 Condition 20 Remarks w o cycle extension WRX T Data hold time WRX WRLX WRHX AD 15 0 2 15 WRX Address valid time WRX WRLX WRHX A 23 16 EACL STS 0 tcvc 2 15 WRX T Address valid time Non Multiplexed WRX WRLX WRHX A 23 0 EACL STS 1 2715 WRX ALE f time WRX WRLX WRHX ALE EBM ACE 1 and EACL STS 1 10 other EBM ACE and EACL STS setting tcvc 10 WRX L ECLKT time WRX WRLX WRHX ECLK 2 10 WRX gt CSn time WRX WRLX CSn EACL ACE 0 2 15 EACL ACE 1 2 15 WRX CSn time Non Multiplexed tesiwL WRX WRLX WRHX CSn EACL STS 0 2 15 EACL STS 1 tcvc 15 WRX gt CSn time WRX CSn time Non Multiplexed TA 40 C to 125 C Vcc 3 0 to 4 5V Vss 0 0 lOvrive 5mA 50pF twHcsH twHcsH WRX WRLX CSn EACL STS 0 tcyc 2 15 WRX WRLX CSn Valid address WRX J time WRX WR
65. annel RX has an external interrupt for wake up Selected USART channels SIN have an external interrupt for wake up Non Maskable Interrupt Disabled after reset Once enabled can not be disabled other than by reset Level high or level low sensitive Pin shared with external interrupt 0 External bus interface 8 bit or 16 bit bidirectional data Up to 24 bit addresses 6 chip select signals Multiplexed address data lines Non multiplexed address data lines Wait state request External bus master possible Timing programmable Alarm comparators Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds Threshold voltages defined externally or generated internally Status is readable interrupts can be masked separately I O Ports Flash Memory Virtually all external pins be used as general purpose All push pull outputs except when used as 2 SDA SCL line Bit wise programmable as input output or peripheral signal Bit wise programmable input enable Bit wise programmable input levels Automotive CMOS Schmitt trigger TTL Bit wise programmable pull up resistor Bit wise programmable output driving strength for EMI optimization Supports automatic programming Embedded Algorithm Write Erase Erase Suspend Resume commands A flag indicating completion of the algorithm Number of erase cycles 10 000 times Data retention t
66. atus SSRO 0000C4H USARTO Control Com Register RW 0000C5H USARTO Ext Status Register 0000C6H USARTO Baud Rate Generator Register Low 0000C7H USARTO Baud Rate Generator Register High BGRHO 0000C8H USARTO Extended Serial Interrupt Register ESIRO 0000 USART1 Serial Mode Register 0000CBH USART1 Serial Control Register 0000 USART1 TX Register 0000 USART1 RX Register 0000CDH USART1 Serial Status 0000CEH USART1 Control Com Register 0000 USART1 Ext Status Register ESCR1 0000DOH USART1 Baud Rate Generator Register Low 0000D1H USART1 Baud Rate Generator Register High 0000D2H USART1 Extended Serial Interrupt Register 0000D4H USART2 Serial Mode Register 0000D5H USART2 Serial Control Register SCR2 0000D6H USART2 TX Register TDR2 W FME EMDC 2007 11 14 MB96380_DS_memory fm 35 96380 Series Specification Sas men 0000D6H USART2 RX Register R 0000D7H USART2 Serial Status RW 0000D8H USART2 Control Com Register RW 0000D9H USART2 Ext Status Register R W 0000DAH USART2 Baud Rate Generator Register Low BGRL2 BGR2 RW RW W 0000DBH USART2 Baud Rate Generator Register High BGRH2 0000DCH USART2 Extended Serial Interrupt Register ESIR2 R 0000FOH external bus EXTBUSO RW 000100H DMAO Buffer address pointer low byte BAPLO RW 000101H DMA
67. c Jo o Jo ER o jo L P13_4 SINO INT6 SEG45 P13_5 SOTO ADTG INT7 SEG46 P13 6 SCKO CKOTXO LBX SEG47 O INTZ SOT1 CS1 A21 SEG41 P1 31 INT3 SCK1 CS2 A22 SEG42 P13_2 P PGO TINO FRCK1 CS3 A23 SEG43 7 INT1 SIN1 CS0 A20 SEG40 3 PPG1 TOTO WOT UBX SEG44 Devices with suffix W XOA X1A Devices with suffix S P04 0 P04 1 2 MB96384 5 Alarm1 not available 3 96384 5 TX1 resp RX1 not available 4 AVRH2 only available for MB96F386 and MB96F387 FME EMDC 2007 11 14 90 89 88 87 86 85 84 83 82 81 80 7 2ou 6 ces alee Es EES NNN D Oz a P11_7 1N0_R A08 SEG3 P11_6 FRCKO_R A07 SEG2 y N N S o N 11 5 PPG4 R AO6 SEG1 P11 4 PPG3 R AO5 SEGO P11 3 PPG2_R A04 COM3 I P11_2 PPG1_R A03 COM2 LOFP 120 Package code mold FPT 120P M21 P04_4 PPG3 SDAO 7 PPG2 CKOTO CS4 SEG48 04 5 PPG4 SCLO O ANO SCKS IN2 R SEG49 P06_1 AN1 SOT5 IN3_R SEG50 P06_2 AN2 INT5 SIN5 SEG51 4 ANA INO TTGO TTG4 SEG53 3 AN3 FRCKO SEG52 06 5 ANS IN1 TTG1 TTGS5 SEG54 FPT 120P M21 MB96380 P10 2 PWM2P4 SCK2 PPG6 P10_1 PWM1M4 SOT2 TOT3 P10_0 PWM1P4 SIN2 TIN3 P09_7 PWM2M3 DVss DVcc 09 6 PWM2P3 9 5 PWM1M3 P09 4 PWM1P3 09 3 PWM2M2 09 2 PWM2P2 09 1 PWM1M2 09 0 PWM1P2 P08 7 PWM2M1 P08 6 PWM2P1 P
68. d time ALE AD 15 0 EACL STS 0 2 20 EACL STS 1 20 Valid address gt RDX time FME EMDG 2007 11 14 RDX A 23 16 EACL ACE 0 2 20 EACL ACE 1 2 20 MB96300 DS el AC ext busfm 91 92 96380 Series AAA Ta 40 C to 125 C Vcc 3 0 to 4 5V Vss 0 0 V lOaive Parameter Valid address RDX J time Non mul RDX A 23 0 Conditions EBM NMS 1 Specification 2 20 Valid address gt RDX time tapvRL RDX AD 15 0 EACL ACE 0 tcvc 20 EACL ACE 1 20 Valid address Valid data input tavov A 23 16 AD 15 0 EACL ACE 0 60 EACL ACE 1 Atcyc 60 w o cycle extension Valid address gt Valid data input Non multiplexed A 23 0 AD 15 0 EBM NMS 1 2tcvc 60 w o cycle extension Valid address gt Valid data input tapvov AD 15 0 EACL ACE 0 2 60 EACL ACE 1 2 60 w o cycle extension RDX pulse width TRLRH RDX 3tcvc 2 8 w o cycle extension RDX 4 Valid data input trLov RDX AD 15 0 3tcvc 2 55 w o cycle extension RDX T Data hold time RDX AD 15 0 0 Address valid Data hold time taxDx A 23 0 0 RDX T ALE f time RDX ALE
69. e Voltage 1 9 V CLKS1 CLKS2 CLKP1 CLKP2 4 MHz CLKB is stopped in this mode Regulator in High Power Mode Core Voltage 1 8 V RC clock fast CLKS1 CLKS2 CLKP1 CLKP2 2 MHz CLKB is stopped in this mode Regulator in High Power Mode Core Voltage 1 8 V RC clock slow Sub osc FME EMDC 2007 11 14 CLKS1 CLKS2 CLKP1 CLKP2 100 kHz CLKB is stopped in this mode Regulator in High Power Mode Core Voltage 1 8 V CLKS1 CLKS2 CLKP1 CLKP2 32 kHz CLKB is stopped in this mode Regulator in Low Power Mode A Core Voltage 1 8 MB96300_DS_el_example_char fm 115 Specification MB96380 Timer mode Stop mode Selected Source Clock Used settings Clock Regulator Settings CLKMC 4 MHz CLKPLL 56 MHz System clocks are stopped in this mode Regulator in High Power Mode Core Voltage 1 9 V Main osc RC clock fast CLKMC 4 MHz System clocks are stopped in this mode Regulator in High Power Mode Core Voltage 1 8 V CLKRC 2 MHz System clocks are stopped in this mode Regulator in High Power Mode Core Voltage 1 8 V RC clock slow CLKRC 100 kHz System clocks are stopped in this mode Regulator in High Power Mode Core Voltage 1 8 V Sub osc stopped FME EMDC 2007 11 14 CLKSC 100 kHz System clocks are stopped in this mode Regulator in Low Power Mode A Core Voltage 1 8 V All clocks are stopped
70. ed 1 Flash wait state VROR LPMB 2 0 110 Core voltage at 1 8V VRCR LPMB 2 0 000 Power supply cur rent for active Low Icc vo Voltage detector Low voltage detector en abled RCR LVDE 1 Core voltage at 1 2V This current must be added to all Power sup ply currents above Clock modulator current Flash Write Erase CCFLASH current Clock modulator en abled 47 mA Must be added to all cur rent above Must be added to all cur rent above Input capacitance AAA The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator See chapter 10 of the Harware Manual for further details about voltage regulator control FME EMDC 2007 11 14 MB96300 DS el DC charfm 73 96380 Series Specification 74 FME EMDC 2007 11 14 MB96300 DS el DC char fm Specification 4 AC Characteristics Source Clock timing MB96380 Ta 40 C to 125 C Vcc AVcc 3 0V to 5 5V DVcc 3 0 to 5 5V Vss AVss DVss Clock frequency When using an oscillation circuit PLL off When using an opposite phase external clock PLL off When using an oscillation circuit or op posite phase external clock PLL on Clock frequency When using a single phase external clock in
71. egister Low TMRLR1 000067H RLT1 Reload Register High TMRHR1 000068H RLT2 Timer Control Status Register Low TMCSRL2 TMCSR2 000069H RLT2 Timer Control Status Register High TMCSRH2 00006 RLT2 Reload Register Low TMRLR2 TMR2 00006BH RLT2 Reload Register High TMRHR2 00006CH RLT3 Timer Control Status Register Low TMCSRL3 00006DH RLT3 Timer Control Status Register High TMCSRH3 TMCSR3 00006 Reload Register Low TMRLR3 00006FH RLT3 Reload Register High TMRHR3 RLT6 Timer Control Status Register Low dedic RLT for PPG RLT6 Timer Control Status Register High dedic 000071H RLT for TMCSRH6 000072H RLT6 Reload Register Low dedic for PPG TMRLR6 000070H TMCSRL6 TMCSR6 000073H RLT6 Reload Register High dedic RLT for PPG TMRHR6 000074 PPG3 PPGO General Control register 1 Low GCN1LO 000075H PPG3 PPGO General Control register 1 High GCN1HO 000076H PPG3 PPGO General Control register 2 Low GCN2LO 000077H PPG3 PPGO General Control register 2 High GCN2HO RW 000078H PPGO Timer register RW GCN20 RW 000079H PPGO Timer register 00007 PPGO Period setting register 00007BH PPGO Period setting register 00007CH PPGO Duty cycle register PDUTO 00007DH PPGO Duty cycle register 00007 Control status register 00007FH PPGO Control status register 00
72. en when the input is disabled corresponding bit of Port Input Enable register PIER 0 Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage the device They must therefore be pulled up or pulled down through resistors To prevent latch up those resistors should be more than 2 kQ Unused bidirectional pins can be set either to the output state and be then left open or to the input state with either input disabled or external pull up pull down resistor as described above 3 External clock usage The permitted frequency range of an external clock depends on the oscillator type and configuration See AC Characteristics for detailed modes and frequency limits Single and opposite phase external clocks must be connected as follows 1 Single phase external clock When using a single phase external clock XO pin must be driven X1 pin left open gt X0 CJ 1 777 2 Opposite phase external clock FME EMDC 2007 11 14 MB96300_DS_handling fm 57 96380 Series Specification 9 When using an opposite phase external clock X1 X1A must be supplied with a clock signal which has the opposite phase to the pins gt X0 CJ 1 CATT Unused sub clock signal If the pins XOA and X1A are not connected to an oscillator a pull down resistor must be connected on the pin and the X1A pin must be left open
73. error Difference between an actual value and an ideal value A total error includes zero transition error full scale transition error and linear error Zero reading voltage Input voltage which results in the minimum conversion value Full scale reading voltage Input voltage which results in the maximum conversion value Total error 3FF 3FE Actual conversion characteristics queue get 2 1 LSB x 1 0 5 LSB a pU 3 1 1 5 004 D mS VNT 2 Actually measured value 008 F i Actual conversion 002 Si characteristics Ideal characteristics 0 5 LSB AVRL AVRH Analog input Var 1 LSB 1 0 5 LSB 1 LSB 1 LSB Ideal value An Vor Ideal value AVRL 0 5 LSB V Vest Ideal value AVRH 1 5 LSB V A voltage at which digital output transitions from 1 to Total error of digital output LSB 104 FME EMDC 2007 11 14 MB96300_DS_el_adc fm Specification Non linearity error 3FF Actual conversion characteristics 1 LSB x N 1 Vor 3FE 3FD 77 actual measurement value VNT actual measurement value Digital output _ Actual conversion characteristics Ideal characteristics actual measurement value AVRL AV
74. hen either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time Tsamp is longer than the minimum value Usually this value is set to 77 where If the external input resistance Rex connected to the analog input is included the sampling time is expressed as follows Tsamp min 7 Rext 2 6kQ C for 4 5 lt AVec lt 5 5 Tsamp min 7 Rext 12 1kQ C for 3 0 lt AVe lt 4 5 If the sampling time cannot be sufficient connect a capacitor of about 0 1 to the analog input pin About the error The accuracy gets worse as AVRH AVRL becomes smaller FME EMDC 2007 11 14 MB96300 DS el adc fm Specification 6 Alarm Comparator Ta 40 to 125 Voc AVcc 3 0V 5 5V Vss AVss Parameter Power supply current lAsALMS 96380 Alarm comparator enabled in fast mode one channel Alarm comparator enabled in slow mode one channel Alarm comparator disabled ALARM pin input cur rent ALARM input volt age range VaLin External low threshold VevtL External high threshold Internal low threshold Internal high threshold VivrH Switching hysteresis Vuvs Comparison time FME EMDC 2007 11 14 tcomrs 25
75. his may affect other devices e Note that if a B signal is input when the microcontroller power supply is off not fixed at O V the power supply is provided from the pins so that incomplete operation may result Note that if the B input is applied during power on the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset except devices with persistant low voltage reset in internal vector mode e When using the LCD controller No B signal must be applied to any LCD pin including unused FME EMDC 2007 11 14 MB96300 DS el abs max rat fm Specification MB96380 SEG COM pins e Sample recommended circuits Protective Diode Limiting resistance B input OV to 16V N ch 4 If used at a temperature exceeding Ta 105 C please contact Fujitsu for reliability limitations 5 Value for a package mounted on single layer PCB at Ta 125 C 6 The total power dissipation can be experessed as Pint Pio with Pint lecriass and gt Vor lor The sum is performed on all IO ports with Icore current flowing in the core logic and lccriasn the Flash write erase current 7 f DVcc is powered before Vcc then SMC pins state is undefined To avoid this we recommend to always power Vcc before DVcc It is not necessary to set Vcc and DVcc to the same value FME
76. ime 20 years Erase can be performed on each sector individually Sector protection Flash Security feature to protect the content of the Flash Low voltage detection during Flash erase 6 FME EMDC 2007 11 14 MB96300_DS_features fm Specification MB96380 Feature Description 77 Embedded Algorithm is a trade mark of Advanced Micro Devices Inc FME EMDC 2007 11 14 MB96300_DS_features fm 7 96380 Series Specification 8 FME EMDC 2007 11 14 MB96300_DS_features fm Specification MB96380 PRODUCT LINEUP Features MB96V300B 9638 Product type Product options Evaluation sample Flash product MB96F38x Mask ROM product MB9638x YS RS YW RW TS HS TW HW Flash ROM LVD persistently on Single clock devices LVD can be disabled Single clock devices LVD persistently on Dual clock devices LVD can be disabled Dual clock devices satellite Flash LVD persistently on Single clock devices satellite Flash LVD can be disabled Single clock devices satellite Flash LVD persistently on Dual clock devices satellite Flash LVD can be disabled Dual clock devices 128kB 160kB 288kB 416kB Main 544 Sat 32kB 832kB 32kB ROM Flash memory emulation by external RAM 92kB internal RAM MB96384R MB96384Y MB96385R MB96385Y MB96F386R MB96F38
77. input Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown FME EMDC 2007 11 14 pull up control Hysteresis input Hysteresis input Automotive inputs TTL input SEG COM output Specification Remarks CMOS level output programmable lo 5mA 5mA and lo 2 2mA 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull up registor 50kQ approx CMOS level output programmable lo 5mA 5mA and lo 2 2mA 2 different CMOS hysteresis inputs with input shutdown function Automotive input with input shutdown function TTL input with input shutdown function Programmable pull up registor approx SEG or COM output MB96380_DS_pin_circuit_type fm Specification MB96380 Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown FME EMDC 2007 11 14 pull up control e
78. ll output current Llonave High current outputs Power consumption Po MB96380 series 5 Operating temperature MB96V300B Operating temperature at Flash erase write Storage temperature 1 2 52 62 AVcc Vcc must be set to the same voltage It is required that AVcc does not exceed Vcc and that the voltage at the analog inputs does not exceed AVcc neither when the power is switched on Vi and Vo should not exceed D Vcc 0 3 V Vi should also not exceed the specified ratings However if the maximum current to from a input is limited by some means with external components the rating super cedes the Vi rating Input output voltages of high current ports depend on DVcc Input output voltages of standard ports depend on Vcc e Applicable to all general purpose I O pins e Use within recommended operating conditions e Use at DC voltage current e The B signal should always be applied a limiting resistance placed between the B signal and the microcontroller e The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pin does not exceed rated values either instantaneously or for prolonged periods e Note that when the microcontroller drive current is low such as in the power saving modes the B input potential may pass through the protective diode and increase the potential at the VCC pin and t
79. m CMOS F2MC 16FX CPU Up to 56 MHz internal 17 8 ns instruction cycle time Optimized instruction set for controller applications bit byte word and long word data types 23 different addressing modes barrel shift variety of pointers 8 byte instruction execution queue Signed multiply 16 bit x 16 bit and divide 32 bit 16 bit instructions available System clock On chip PLL clock multiplier x1 25 x1 when PLL stop 3 16 MHz external quartz clock Up to 56MHz external clock for devices with fast clock input feature 32 100 kHz subsystem quartz clock 100kHz 2MHz internal RC clock for quick and safe startup oscillator stop detection watchdog Clock source selectable from main and subclock oscillator partnumber suffix W on chip RC oscillator independently for CPU and 2 clock domains of peripherals Low Power Consumption 13 operating modes different Run Sleep Timer modes Stop mode Clock modulator On chip voltage regula tor Internal voltage regulator supports reduced internal MCU voltage offering low EMI and low power consumption figures Low voltage reset Reset is generated when supply voltage is below minimum Code Security Protects ROM content from unintended read out Memory Patch Function Replaces ROM content Can also be used to implement embedded debug support DMA Automatic transfer function independent of CPU can be assigned freely to resources Interrup
80. memory fm Specification INTERRUPT VECTOR TABLE Interrupt vector table MB96 F 38x 1 3 Offset in Vector number vector ta ble Vector name CALLVO CALLV1 Cleared by DMA No No Index in ICR to pro gram MB96380 CALLV2 No CALLV3 No CALLV4 No CALLV5 CALLV6 CALLV7 No No RESET No INT9 No EXCEPTION N gt No 1 No 1 MC_TIMER 2 4 Main Clock Timer SC_TIMER No 15 Sub Clock Timer RESERVED N Reserved EXTINTO External Interrupt 0 EXTINT2 e External Interrupt 2 Y o 16 Yes 17 Yes 19 es 20 External Interrupt 3 EXTINT4 Yes 21 External Interrupt 4 EXTINT5 Yes 22 External Interrupt 5 26 394 EXTINT6 EXTINT7 Y Y es es No CAN Controller 1 23 24 25 External Interrupt 6 External Interrupt 7 27 390 Yes Programmable Pulse Generator 0 28 38 Yes Programmable Pulse Generator 1 29 388 FME EMDC 2007 11 14 Yes Programmable Pulse Generator 2 PPG3 Yes 30 Programmable Pulse Generator 3 PPG4 Yes 31 Programmable Pulse Generator 4 PPG5 Yes 32 Programmable Pulse Generator 5 MB96380_DS_memory fm 53 96380 Series Interrupt vector table MB96 F 38x 2 3 Vector Offset in number vector ta 35 Vector name ble Cleared by DMA Y Index in ICR to pro gram
81. nterface Yes Chip select 6 signals Clock output function 2 channels Low voltage reset Reset is generated when supply voltage is below minimum On chip RC oscillator 10 FME EMDC 2007 11 14 Yes MB96380 DS lineup fm Specification DIAGRAM 96380 ADOO AD15 A00 A23 T P gt ALE RDX WRHX med T LBX UBX we CS0 CS5 CKOT1 at CKOTXO CKOTX1 MDO MD2 XO X1 X1A External Bus 16FX Interrupt Main Flash Interface CPU Controller Memory Satellite Flash Memory Memory Patch Clock amp Unit Mode Controller 16FX Core Bus CLKB TINO TINS 16 bit Reload Timer TOTO TOT3 lt Ach VO LCD COMO COM3 controller SEGO SEG64 driver FME EMDC 2007 11 14 DMA Peripheral Peripheral Voltage Controller Watchdog Bus Bridge Bus Bridge RAM Boot ROM Regulator a SDAO 12C 3 3 1 ch a SCLO m A AVCC T Interface AVSS 1 10 bit ADC E 2 ch AVRL 16 ch E ANO AN15 2 a Sound ADTG rud 2 ch SINO SIN2 SIN4 SIN5 TXO TX1 RX1 SGO0 SGO1 SGA1 SGA1 SOTO SOT2 SOT4 SOT5 SCKO SCK2 SCK4 SCK5 USART lt 5 ch lt gt FRCKO Timer 0 INO INS ICU 0 1 2 3 OUTO OUT3
82. ocation Register PRRR3 0004DAH Peripheral Resource Relocation Register 4 PRRR4 0004DBH Peripheral Resource Relocation Register 5 PRRR5 0004DCH Peripheral Resource Relocation Register 6 0004DDH Peripheral Resource Relocation Register 7 0004DEH Peripheral Resource Relocation Register 8 0004DFH Peripheral Resource Relocation Register 9 0004 Sub Second Register L WTBRLO 0004E1H RTC Sub Second Register M WTBRHO 0004E2H RTC Sub Second Register 0004E3H RTC Second Register 0004E4H RTC Minutes 0004E5H RTC Hour 0004 6 RTC Timer Control Extended Register WTCER 0004E7H RTC Clock select register WTCKSR FME EMDC 2007 11 14 MB96380_DS_memory fm 43 44 96380 Series Abbreviation 8 bit access 0004E8H RTC Timer Control Register L initernal Specification Abbreviation 16 bit access Access RW 0004E9H RTC Timer Control Register H RW 0004 CAL Calibration unit Control register RW 0004 CAL Sub RC clock timer data register L W 0004EDH CAL Sub RC clock timer data register H CUTDH RW R R 0004 CAL Main clock timer data register 2 L CUTR2L CUTR2 0004EFH CAL Main clock timer data register 2 H CUTR2H R 0004FOH CAL Main clock timer data register 1 L CUTRIL R 0004F1H CAL Main clock timer data register 1 CUTR1H R 0004FAH RLT Timer input select for
83. of peripheral clock frequency Event count function Free Running Timers Signals an interrupt on overflow supports timer clear upon match with Output Compare 0 4 Prescaler with 1 1 21 1 22 1 23 1 24 1 25 1 28 1 27 1 28 of peripheral clock frequency Input Capture Units 16 bit wide Signals an interrupt upon external event Rising edge falling edge or rising amp falling edge sensitive Output Compare Units 16 bit wide Signals an interrupt when a match with 16 bit Timer occurs A pair of compare registers can be used to generate an output signal FME EMDC 2007 11 14 MB96300 DS features fm Specification Feature MB96380 Description Programmable Pulse Generator 16 bit down counter cycle and duty setting registers Interrupt at trigger counter borrow and or duty match PWM operation and one shot operation Internal prescaler allows 1 1 4 1 16 1 64 of peripheral clock as counter clock and Reload timer overflow as clock input Can be triggered by software or reload timer Stepper Motor Control ler LCD Controller Sound Generator Stepper Motor Controller with integrated high current output drivers Four high current outputs for each channel Two synchronized 8 10 bit PWMs per channel Internal prescaling for PWM clock 1 1 4 1 5 1 6 1 8 1 10 1 12 1 16 of peripheral clock Separate power supply for high current output drivers LCD controller with up to 4 COM x 65 SEG
84. register of free running timer TCCSLO 000023H FRTO Control status register of free running timer TCCSHO 000024H FRT1 Data register of free running timer 000025H FRT1 Data register of free running timer 000026H FRT1 Control status register of free running timer 000027H Control status register of free running timer TCCSL1 TCCSH1 000028H OCUO Output Compare Control Status OCSO 000029H OCU1 Output Compare Control Status OCS1 00002AH OCUO Compare Register 00002CH OCU1 Compare Register OCCP1 RW FME EMDC 2007 11 14 MB96380 DS memoryfm 321 32 96380 Series Abbreviation 00002 OCU2 Output Compare Control Status Specification Abbreviation 16 bit access Access 00002FH Output Compare Control Status 000030H OCU2 Compare Register 000031H OCU2 Compare Register 000032H OCU3 Compare Register OCCP3 000040H ICUO ICU1 Control Status Register 501 RW 000041H ICUO ICU1 Edge register ICEO1 000042H ICUO Capture Register IPCPLO 000043H ICUO Capture Register IPCPHO 000044H ICU1 Capture Register IPCPL1 IPCP1 000045H ICU1 Capture Register 000046H ICU2 ICU3 Control Status Register ICS23 000047H ICU2 ICU3 Edge register internal version ICE23 000048H ICU2 Capture Register IPCPL2 000049H ICU2 Capture Register IPCPH2 00
85. rn the A D converter power supply AVCC AVRH AVRL and analog inputs ANn on after turning the digital power supply VCC on It is also required to turn the digital power off after turning the A D converter supply and analog inputs off In this case the voltage must not exceed AVRH or AVCC turning the analog and digital power supplies simultaneously on or off is acceptable A D converter unused pins handling It is required to connect the unused pins of the A D converter as AVcc Vcc AVss AVRH AVRL Vss 10 Notes on energization 58 To prevent malfunction of the internal voltage regulator supply voltage profile while turning the power supply on should be slower than 50us from 0 2 V to 2 7 V FME EMDC 2007 11 14 MB96300_DS_handling fm Specification MB96380 11 Stabilization of power supply voltage f the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage a malfunction may occur The Vcc power supply voltage must therefore be stabilized As stabilization guidelines the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations peak to peak value in the commercial frequencies 50 to 60 Hz fall within 10 of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0 1V us or less in instantaneous fluctuation for power supply switching 12 SMC power supply pins All DVss pins must be set to the same level as the
86. rst fm 81 96380 Series Specification 82 FME EMDC 2007 11 14 MB96300_DS_el_AC_pon_rst fm Specification External Input timing MB96380 Ta 40 C to 125 C Vcc 3 0V to 5 5V DVcc 3 0 to 5 5 Vss AVss DVss Value D Parameter Symbol Condition unit Used Pin input func Min Max tion External Interrupt NMI Input pulse width 200 tcukp12 1 Note Relocated Resource Inputs have same characteristics General Purpose IO Reload Timer PPG Trigger input AD Converter Trigger Free Running Timer external clock Input Capture External Pin input FME EMDC 2007 11 14 MB96300 DS el AC ext inpt fm 83 96380 Series Specification 84 FME EMDC 2007 11 14 MB96300_DS_el_AC_ext_inpt fm Specification MB96380 Slew Rate High Current Outputs Ta 40 C to 125 C Vcc AVcc 3 0V to 5 5V DVcc 3 0V to 5 5 Vss AVss DVss Output driving strength set to 30mA P08_0 to PO9_6 P09 7to P10 3 Note Relocated Resource Inputs have same characteristics Slew rate output timin P 9 Vu Vu Vors0 0 9 x VoLso L Vorso 0 1 x VoLso Vi VL trao FME EMDC 2007 11 14 MB96380 DS el AC slew rate fm 85 96380 Series Specification
87. s device the default pin 1 If any other pin is required please contact the Flash programmer device vendor 30 FME EMDC 2007 11 14 MB96380_DS_memory fm Specification MB96380 I O MAP All non mentionned registers in the address map are reserved 000000H 00 Port Port Data Register 000001H P01 I O Port Port Data Register 000002H P02 I O Port Port Data Register Abbreviation 8 bit access PDROO PDRO1 Abbreviation 16 bit access Access RW RW 000003H I O Port Port Data Register 000004H P04 I O Port Port Data Register 000005H P05 I O Port Port Data Register 000006 06 Port Port Data Register 000008H P08 I O Port Port Data Register 000009H P09 I O Port Port Data Register PDRO8 00000AH P10 I O Port Port Data Register 00000BH P11 I O Port Port Data Register 00000CH 12 I O Port Port Data Register 00000DH P13 O Port Port Data Register 000018H ADC Control Status register 0 Low 000019H ADC Control Status register 0 High 00001 ADC Data Register 0 Low PDR13 ADCSL ADCSH 00001BH ADC Data Register 0 High 00001CH ADC Setting Register 0 Low 00001DH ADC Setting Register 0 High 00001 ADC Extended Configuration Register 000020H FRTO Data register of free running timer 000021H FRTO Data register of free running timer ADECR 000022H FRTO Control status
88. ster 00009EH PPG4 Period setting register 00009FH 4 Period setting register 0000A0H PPG4 Duty cycle register 0000A2H PPG4 Control status register 0000A3H PPG4 Control status register PCNL4 PCN4 0000A4H PPG5 Timer register 0000A5H 5 Timer register 0000A6H PPG5 Period setting register 0000A7H PPG5 Period setting register 42201000 0000A8H PPG5 Duty cycle register PDUT5 FME EMDC 2007 11 14 MB96380_DS_memory fm Specification Abbreviation 0000A9H PPG5 Duty cycle register MB96380 Abbreviation 16 bit access Access 0000AAH PPG5 Control status register 0000ABH PPG5 Control status register 0000ACH 12 0 Bus Status Register 0000ADH 12 0 Bus Control Register IBCRO 0000 12 0 Ten bit Slave address Register Low ITBALO 0000AFH 12 0 Ten bit Slave address Register High ITBAHO 0000BOH 12C0 Ten bit Address mask Register Low ITMKLO 0000B1H 12 0 Ten bit Address mask Register High ITMKHO 0000B2H 12 0 Seven bit Slave address Register ISBAO 0000B3H 12C0 Seven bit Address mask Register ISMKO 0000B4H 12 0 Data Register 0000B5H 12 0 Clock Control Register 0000C0H USARTO USART Serial Mode Register 0000C1H USARTO Serial Control Register 0000C2H USARTO TX Register TDRO W 0000C2H USARTO RX Register RDRO R 0000C3H USARTO Serial St
89. ster PWM 1 0005F7H SMC2 PWM control register PWM 1 0005F8H SMC2 PWM control register PWM 2 PWC22 RW 0005F9H SMC2 PWM control register PWM 2 FME EMDC 2007 11 14 MB96380 DS memoryfm 45 46 96380 Series 0005 SMC2 PWM Select register internal Abbreviation 8 bit access Specification Abbreviation 16 bit access Access 0005 SMC2 PWM Select register 0005 SMC3 PWM control register internal 0005FFH SMC3 extended control register Output enable 000600H SMC3 PWM control register PWM 1 PWC13 000601H SMC3 PWM control register PWM 1 a 000602H SMC3 PWM control register PWM 2 000603H SMC3 PWM control register PWM 2 000604H SMC3 PWM Select register internal 000605H SMC3 PWM Select register 000608H SMC4 PWM control register internal PWC4 000609H SMC4 extended control register Output enable PWEC4 00060 SMC4 PWM control register PWM 1 00060BH SMC4 PWM control register PWM 1 00060CH SMC4 PWM control register PWM 2 00060DH SMC4 PWM control register PWM 2 00060 SMC4 PWM Select register internal 00060FH SMC4 PWM Select register 00061CH LCD Output Enable Register 0 Seg 7 0 PWS14 PWS24 LCDERO 00061DH LCD Output Enable Register 1 Seq 15 8 LCDER1 00061EH LCD Output Enable Register 2 Seq 23 16 LCDER2 00061FH LCD Output Enable
90. strength set to 5mA Output H voltage High cur rent out puts 4 5V DVcc lt 5 5V 30mA 3 0V lt DVcc lt 4 5V 20mA Driving strength set to 30mA 2 outputs Normal and High Current outputs 4 5V lt Vcc lt 5 5V 3mA 3 0V lt Vcc lt 4 5V 2mA 4 5 lt D Vcc lt 5 5V lo 2mA 3 0V lt D Vcc lt 4 5V lo 2 41 6mA Driving strength set to 2mA Normal and High Current outputs 4 5N lt D Vcc 5 5V lo 5mA 3 0 lt D Vcc lt 4 5V lo 3mA Driving strength set to 5mA Output L voltage High cur rent out puts 2 outputs 4 5V lt DVcc lt 5 5V lo 30mA 3 0V lt DVcc lt 4 5V lo 20mA 4 5V lt Vcc lt 5 5V lo 3mA 3 0V lt Vcc lt 4 5V lo 2mA Driving strength set Input leak current DVcc Vcc 5 5V Vss lt Vi lt Vcc Pull up resistance Internal LCD di R vide resistance des Note Input output voltages of high current ports depend DVcc of other ports on Vcc FME EMDC 2007 11 14 Between V3 and Vss MB96300 DS el DC char fm Specification MB96380 Ta 40 C to 125 C Vcc AVcc 3 0V to 5 5V DVcc 3 0V to 5 5V Vss AVss DVss Power supply cur rent in Run modes Condition PLL Run mode with CLKS1 2 56MHz CLKB CLKP1 CLKP2 28MHz Value Max
91. ted Reload Timer n event input Reload Timer Reload Timer n output Programmable Pulse Generator n trigger input CAN interface n TX output LCD voltage references Power supply Supply Power supply RTC Real Timer clock output External bus External bus High byte Write strobe output 16 FME EMDC 2007 11 14 MB96300_DS_pin_function_desc fm Specification MB96380 Pin Function description 3 3 Feature Description WRLX External bus External bus Low byte Write strobe output X0 Oscillator input Subclock Oscillator input only for devices with suffix W x1 Oscillator output Subclock Oscillator output only for devices with suffix W FME EMDC 2007 11 14 MB96300 DS pin function descfm 17 96380 Series Specification 18 FME EMDC 2007 11 14 MB96300_DS_pin_function_desc fm Specification E CIRCUIT 120 21 Pin no Circuit type 1 Supply 2 C pin I 3to 11 12 13 14 to 21 22 Supply 23 G 24 to 25 Supply 26 to 29 K 30 31 Supply 32 to 35 K 36 to 40 M 41 42 Supply 43 to 52 M 53 54 Supply 55 to 59 M 60 61 Supply 62 to 64 65 66 67 68 69 68 69 70 71 to 89 7 Devices with suffix 2 Devices without suffix FME EMDC 2007
92. tion register Main Flash EVA internal MFMCS 0003F2H 0003F3H Flash Memory Timing Configuration register 0 Main Flash EVA internal Flash Memory Timing Configuration register 1 Main Flash MFMTCL MFMTCH 0003F4H Flash Memory Security register Sat Flash SFMSEC 0003F5H Flash Memory Configuration register Sat Flash SFMCS 0003F6H 0003F7H Flash Memory Timing Configuration register 0 Sat ellite Flash Flash Memory Timing Configuration register 1 Sat ellite Flash SFMTCL SFMTCH 0003F9H Flash Memory Write Control register 1 FME EMDC 2007 11 14 FMWC1 MB96380_DS_memory fm 39 40 96380 Series 0003FAH Flash Memory Write Control register 2 Abbreviation 8 bit access Specification Abbreviation 16 bit access Access 0003FBH Flash Memory Write Control register 3 0003FCH Flash Memory Write Control register 4 0003FDH Flash Memory Write Control register 5 000400H Standby Mode control register 000401H Clock select register 000402H Clock Stabilisation select register SMCR CKSR CKSSR 000403H Clock monitor register CKMR 000404 Clock Frequncy control register Low CKFCRL 000405H Clock Frequncy control register High 000406H PLL Control register Low 000407H PLL Control register High internal 000408H RC clock timer control register CKFCRH PLLCRL PLLCRH RCTCR 000409H
93. ts Fast Interrupt processing 8 programmable priority levels Non Maskable Interrupt NMI Timers FME EMDC 2007 11 14 Two independent clock timers 23 bit RC clock timer 23 bit Main clock timer 17 bit Sub clock timer Watchdog Timer MB96300 DS features fm 3 4 96380 Series Specification Feature Description Supports CAN protocol version 2 0 part A and B 15016845 certified Bit rates up to 1 Mbit s 32 message objects Each message object has its own identifier mask Programmable FIFO mode concatenation of message objects Maskable interrupt Disabled Automatic Retransmission mode for Time Triggered CAN applications Programmable loop back mode for self test operation Full duplex USARTs SCI LIN Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device Up to 400 kbit s Master and Slave functionality 8 bit and 10 bit addressing A D converter SAR type 10 bit resolution Signals interrupt on conversion end single conversion mode continuous conversion mode stop conversion mode activation by software external trigger or reload timer A D Converter Refer ence Voltage switch 2 independant positive A D converter reference voltages available Reload Timers 16 bit wide Prescaler with 1 21 1 22 1 23 1 24 1 25 1 26
94. vc 2 15 EACL STS 1 and EACL ACE 0 tove 15 EACL STS 0 and EACL ACE 1 3tcvc 2 15 EACL STS 1 and EACL ACE 1 15 ALE J Address valid time ALE AD 15 0 EACL STS 0 2 15 EACL STS 1 15 Valid address gt RDX time RDX A 23 16 EACL ACE 0 2 15 EACL ACE 1 2 15 Valid address gt RDX J time Non Multiplexed RDX A 23 0 EBM NMS 1 tevc 2 15 Valid address gt RDX time tADVAL RDX AD 15 0 EACL ACE 0 tcvc 15 EACL ACE 1 2lcvc 15 Valid address gt Valid data input tavov A 23 16 AD 15 0 EACL ACE 0 55 EACL ACE 1 Atcyc 55 w o cycle extension Valid address Valid data input Non Multiplexed A 23 0 AD 15 0 EBM NMS 1 2tcvc 55 w o cycle extension Valid address gt Valid data input AD 15 0 EACL ACE 0 btcvc 2 55 EACL ACE 1 2 55 w o cycle extension RDX pulse width TRLRH RDX 3 2 5 w o cycle extension RDX L Valid data input trLov RDX AD 15 0 3 tcvc 2 50 w o cycle extension RDX T Data hold time 2007 11 14 RDX AD 15 0 0 MB96300_DS_el_AC_ext_bus fm Specification Ta 40 C to 125 C Vcc 5 0 10 Vss 0 0
95. with typical process parameters PLL clock 56 MHz Main osc 4 MHz RC clock 2 MHz RC clock 100 kHz Sub osc 32 kHz 50 00 Ta C Sleep mode PLL clock 56 MHz Main osc 4 MHz RC clock 2 MHz RC clock 100 kHz 1 Sub osc 32 kHz 50 00 Ta C FME EMDC 2007 11 14 MB96300_DS el example_char fm 113 Specification MB96380 SSS Timer mode PLL clock 56 MHz Main osc 4 MHz Sub osc 32 kHz 50 00 Ta C Stop mode 50 00 Ta C FME EMDC 2007 11 14 MB96300_DS_el_example_char fm 114 Specification MB96380 Mode Run mode Selected Source Clock PLL Used settings Clock Regulator Settings CLKS1 CLKS2 CLKB CLKP1 56 MHz CLKP2 28 MHz Regulator in High Power Mode Core Voltage 1 9 V Main osc CLKS1 CLKS2 CLKB CLKP1 CLKP2 4 MHz Regulator in High Power Mode Core Voltage 1 8 V RC clock fast RC clock slow CLKS1 CLKS2 CLKB CLKP1 CLKP2 2 MHz Regulator in High Power Mode Core Voltage 1 8 V CLKS1 CLKS2 CLKB CLKP1 CLKP2 100 kHz Regulator in High Power Mode Core Voltage 1 8 CLKS1 CLKS2 CLKB CLKP1 CLKP2 32 kHz Regulator in Low Power Mode A Core Voltage 1 8 V Sleep mode Main osc CLKS1 CLKS2 CLKP1 56 MHz CLKP2 28 MHz CLKB is stopped in this mode Regulator in High Power Mode Cor
96. xternal Bus end address ext bus ext bus Peripheral Peripheral GPR DMA Peripheral Peripheral Unused GPR banks be used as RAM area Please refer to the table RAMSTART for different RAM sizes on the next page ROM Configuration Block must not be used for other purposes than described in the manual The external Bus area DMA area are only available if the device contains the corresponding resource The available RAM and ROM area depends on the device configuration FME EMDC 2007 11 14 MB96380_DS_memory fm 25 96380 Series Specification m RAMSTART AND EXTERNAL BUS END ADDRESS FOR DIFFERENT RAM SIZES Devices MB96384 MB96385 MB96F386 MB96F387 MB96F388 RAM size 6kB 8kB 16kB End address of exter 69FF 61FF 41FF 6A40 6240 4240 1240 MB96F389 additionnal RAM 0x01 8000 0x01 9000 1240 11FF 11FF 32kB 32kB default 02 0000 RAM Mirroring off RAM Mirroring on unused unused 01 9000 01 8000 OO AX 33 unused unused 01 0000 ROM ROM mirroring mirroring bank Fx bank Fx 00 8000 77 8kB 32k 28kB 28kB continues 8kB RAM RAM 8kB 00 1200 4kB RAMSTART 26 FME EMDC 2007 11 14 MB96380 DS memory fm Specification FLASH SECTOR CONFIGURATION FME EMDC 2007 11 14 MB96380 MB96F386R MB96F387R MB96F388T MB96F389R MB9

F2MC-16FX MB96380 Series

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