Application Note - Atmel Corporation
Contents
1. CS CS CS cs cs NRD CFOE OE OE OE OE OE OE NWRO0O NWE WE WE WE WE WE WE NWR1 NBS1 WE NUB WE NUB BE1 NWR3 NBS3 WE NUB BE3 Notes 1 NWRO enables lower byte writes NWR1 enables upper byte writes 2 NWRx enables corresponding byte x writes x 0 1 2 or 3 3 NBSO and NBS1 enable respectively lower and upper bytes of the lower 16 bit word 4 NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16 bit word 5 BEx Byte x Enable x 0 1 2 or 3 11 6493A ATARM 31 Jul 09 AMEL AMEL Table 4 2 EBI Pins and External Devices Connections Pins of the Interfaced Device Compact SDRAM pi cach NAND Flash Pins True IDE Mode Controller SDRAMC SMC DO D7 DO D7 DO D7 DO D7 1 00 1 07 D8 D15 D8 D15 D8 15 D8 15 1 08 1 015 D16 D31 D16 D31 AO NBSO DQMO AO AO A1 NWR2 NBS2 DQM2 A1 A1 A2 A10 A 0 8 A 2 10 A 2 10 A11 A9 SDA10 A10 A12 A13 A14 A 11 12 A15 A16 BA0 BAO A17 BA1 BAI A18 A20 A21 CLE A22 REG REG ALE A23 A24 A25 CFRNW CFRNW NCSO NCS1 SDCS cs NCS2 NCS3 NANDCS CE NCS4 CFCSO CFCSo CFCSso NCS5 CFCS1 CFCSs1 CFcs1 NCS6 NANDOE RE NCS7 NANDWE WE NRD CFOE OE NWRO NWE CFWE WE WE NW2. Note i Signal Name Recommended Pin Connection Description Clock Oscillator and PLL Crystal load capacitance to check Corystal AT91SAM9G10 XOUT GNDOSC Crystals between 3 and 20 MHz XIN XOUT Capacitors on XIN and XOUT K i crystal load capacitance dependent Geavera i i Main Oscillator ee oe in 1 kOhm resistor on XOUT only required Normal Mode for crystals with frequencies lower than Ai wills 8 MHz Crex Crex Example for an 18 432 MHz crystal with a load capacitance of Copysqa 12 5 pF external capacitors are required C x7 16 2 pF Refer to the electrical specifications of the AT91SAM9G10 datasheet XIN XOUT 3 3V square wave signal VDDPLL XIN external clock source ae o a ee Mie Main Oscillator XOUT can be left unconnected uty yc S z o Refer to the electrical specifications of the n AT91SAM9G10 datasheet Bypass Mode AMEL s 6493A ATARM 31 Jul 09 AMEL Signal Name Recommended Pin Connection Description Crystal load capacitance to check CeorystaL32 AT91SAM9G10 XOUT32 XIN32 XOUT32 CorysTaL32 Slow Clock Capacitors on XIN32 and XOUT32 ao ie crystal load capacitance dependent ae a a Crexr32 T Crextaa _ 32 768 kHz Crystal Example for a 32 768 kHz crystal with a load capacitance of Corystatgo 12 5 pF external capacitors are required Crextge 18 pF Refer to the electrical speci
3. down resistor DDP Application dependent To reduce power consumption if USB Device is not used connect DDM to GND No internal pull down resistor DDM Application dependent To reduce power consumption if USB Device is not used connect DDM to GND Notes 1 These values are given only as a typical example 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF H VDDCORE 100nF fa VDDCORE 100nF Hi VDDCORE GND 3 The double power supplies VDDIOM and VDDIOP power the device differently when interfacing with memories or with peripherals 4 It is recommended to establish accessibility to a JTAG connector for debug in any case 5 Ina well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended AMEL 6493A ATARM 31 Jul 09 AMEL 6 Example of USB Host connection A termination serial resistor Rey must be connected to HDPA HDPB and HDMA HDMB A recommended resistor value is defined in the electrical specifications of the AT91SAM9G10 datasheet 5V 0 20A a i BE OuF Hii J OnF Rext Type A Connector HDMA or HDMB HDPA or HDPB 7 Example of USB Device connection As there is an embedded pull up no external circuitry is necessary to enable and disable the 1 5 kOh
4. AT91SAM9G10 Microcontroller Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding the Atmel ARM Thumb based AT91SAM9G10 microcontroller It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9G10 It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AMEL T O AT91 ARM Thumb based Microcontrollers Application Note 6493A ATARM 31 Jul 09 AMEL 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest documents for the AT91SAM9G10 Microcontroller on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Characteristics AT91 ARM Thumb based Microcontrollers AT91SAM9G10 Ordering Information Preliminary Datasheet Errata I
5. R1 NBS1 CFIOR DQM1 IOR IOR NWR3 NBS3 CFIOW DQM3 IOW IOW CFCE1 CE1 cso CFCE2 CE2 CS1 SDCK CLK 12 Application Note memm 6493A ATARM 31 Jul 09 es caton Note Table 4 2 EBI Pins and External Devices Connections Continued Pins of the Interfaced Device Compact SDRAM ee ie NAND Flash Pins True IDE Mode Controller SDRAMC SMC SDCKE CKE RAS RAS CAS CAS SDWE WE NWAIT WAIT WAIT Pxx CD1 or CD2 CD1 or CD2 Pxx CE Pxx RDY Notes 1 Not directly connected to the CompactFlash slot Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot Any PIO line For SDRAM connection examples see Using SDRAM on AT91SAM9 Microcontrollers application note For NAND Flash connection examples see NAND Flash Support in AT91SAM Microcontrollers application note 1 08 1 015 bits used only for 16 bit NAND Flash CE connection depends on the Nand Flash For standard NAND Flash devices it must be connected to any free PIO line Oak wD For CE don t care NAND Flash devices it can be either connected to NCS3 NANDCS or to any free PIO line 6493A ATARM 31 Jul 09 AMEL 13 AMEL 5 AT91SAM Boot Program Hardware Constraints See the AT91SAM Boot Program section of the AT91SAM9G10 datasheet for more details on the boot program 5 1 AT91SAM Boot Pro
6. ce source voltage drop VDDBU 1 08V to 1 32V Powers the Slow Clock oscillator and a part of the System Decoupling capacitor 100 nF Controller 1 65 to 1 95V or 3 0V to 3 6V Powers External Bus Interface I O lines VDDIOM Decoupling Filtering capacitors Dye voltage angs supported 100 nF and 10pF 2 Decoupling Filtering capacitors must be added to improve H startup stability and reduce source voltage drop 27V to 3 6V Powers Peripheral I O lines and USB transceivers VDDIOP Decoupling Filtering capacitors 100 nF and 10yF 2 Decoupling Filtering capacitors must be added to improve H startup stability and reduce source voltage drop 3 0V to 3 6V VDDOSC Decoupling capacitor 100 nrj Powers the Main Oscillator 3 0V to 3 6V VDDPLL P the PLL cells Decoupling capacitor 100 nF ee Ss GND pins are common to VDDCORE VDDIOM and VDDIOP pins ND a aroung GND pins should be connected as shortly as possible to the system ground plane GNDBU pin is provided for VDDBU pin GNDBU Backup Ground GNDBU pin should be connected as shortly as possible to the system ground plane GNDPLL pin is provided for VDDPLL pin GNDPLL PLL Ground GNDPLL pin should be connected as shortly as possible to the system ground plane GNDOSC pin is provided for VDDOSC pin GNDOSC Oscillator Ground GNDOSC pin should be connected as shortly as possible to the system ground plane Application Note mmm 6493A ATARM 31 Jul 09 es caton
7. fer to the column Reset State of the PIO Controller PAx multiplexing tables in the product datasheet PBx Application dependent PCx Schmitt Trigger on All Inputs To reduce power consumption if not used the concerned PIO can be configured as an output driven at 0 with internal pull up disabled EBI Data Bus DO to D31 Data bus lines are pulled up inputs to Vyppioy at reset DO D31 Application dependent Note D16to D31 are multiplexed with the PIOC controller Address Bus AO to A25 All address lines are driven to 0 at reset A0 A22 Application dependent A23 A25 Note A23 PA30 A24 PA31 and A25 PC3 are enabled by default at reset through the PIO controllers SMC SDRAM Controller CompactFlash Support NAND Flash Support See External Bus Interface EBI Hardware Interface on page 11 Application Note m 6493A ATARM 31 Jul 09 es caton Note i Signal Name Recommended Pin Connection Description USB Host UHP No internal pull down resistors HDPA Application dependent HDPB Typically 15 kOhm resistor to GND To reduce power consumption if USB Host is not used connect HDPA HDPB to GND No internal pull down resistors HDMA Application dependent HDMB Typically 15 kOhm resistor to GND To reduce power consumption if USB Host is not used connect HDMA HDMB to GND USB Device UDP Integrated programmable pull up resistor USB_PUCR No internal pull
8. fications of the AT91SAM9G10 datasheet See the Excel spreadsheet contained in ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx zip available from Software Files on the Atmel Web site allowing calculation of the best R C1 C2 component values for the PLL Loop Back Filter PLLRC Second order filter O PLL PLLRCA PLLRCB C Can be left unconnected if PLL not used R Q N Cl GNDPLL R C1 and C2 must be placed as close as possible to the pins Application Note memm 6493A ATARM 31 Jul 09 es caon Note Recommended Pin Connection Description Mw Signal Name ICE and JTAG TCK Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TMS Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDI Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDO Floating Output driven at up to Vyppiop RTCK Floating Output driven at up to Vyppiop Please refer to the I O line considerations NTRST and the errata sections of the Internal pull up resistor to Vyppiop 15 kOhm AT91SAM9G10 datasheet In harsh environments It is strongly JTAGSEL recommended to tie this pin to GNDBU Internal pull down resistor to GNDBU 15 kOhm if not used or to add an external low Must be tied to Vyppgy to enter JTAG Boundary Scan value resistor such a
9. gram Supported Crystals MHz The Main Oscillator is not bypassed by the Boot ROM Thus It is possible to use the crystals shown in Table 5 1 but not external clocks Table 5 1 Supported Crystals MHz 3 0 3 2768 3 6864 3 84 4 0 4 433619 4 608 4 9152 5 0 5 24288 6 0 6 144 6 4 6 5536 7 159090 7 3728 7 864320 8 0 9 8304 10 0 11 05920 12 0 12 288 13 56 14 31818 14 7456 16 0 17 734470 18 432 20 0 5 2 SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port Table 5 2 Pins Driven during SAM BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PAQ DBGU DTXD PA10 5 3 Serial and DataFlash Boot The Serial and DataFlash Boot programs search for a valid application in either a SPI Serial Flash or a DataFlash memory The memory must be connected to NPCSO of the SPIO The DataFlash and Serial Flash downloaded code size must be smaller than 12 kbytes Table 5 3 Pins Driven during DataFlash Boot Program Execution Peripheral Pin PIO Line SPIO MOSI PA1 SPIO MISO PAO SPIO SPCK PA2 SPIO NPCSO PA3 5 4 NAND Flash Boot The NAND Flash Boot program searches for a valid application in an SLC 8 bit or 16 bit NAND Flash memory 14 Application Note memm 6493A ATARM 31 Jul 09 es caton Note The NandFlash downloaded code size must be smaller than 12 kbytes Table 5 4 Pins Driven during NAND Fla
10. kes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life OWERED ARM 2009 Atmel Corporation All rights reserved Atmel Atmel logo and combinations thereof DataFlash SAM BA and others are registered trademarks and others are trademarks of Atmel Corporation or its subsidiaries ARM the ARM Powered logo Thumb and others are regis tered trademarks or trademarks of ARM Ltd Other terms and product names may be the trademarks of others 6493A ATARM 31 Jul 09
11. m pull up To prevent over consumption when the host is disconnected an external pull down can be added to DDP and DDM A termination serial resistor Rext must be connected to DDP and DDM A recommended resistor value is defined in the electrical specifications of the AT91SAM9G10 datasheet 5V Bus Monitoring 27K PIO DDP 3 TypeB 4 Connector 330 K 330 K 10 Application Note mem 6493A ATARM 31 Jul 09 es caton Note 4 External Bus Interface EBI Hardware Interface Table 4 1 and Table 4 2 detail the connections to be applied between the EBI pins and the external devices for each Memory Controller Table 4 1 EBI Pins and External Static Devices Connections Pins of the Interfaced Device 8 bit Static wie 16 bit Static 2 at 32 bit Static Pins Device Devices Device Devices Devices Device Controller MC DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 D8 D15 D8 D15 D8 D15 D8 D15 D8 15 D8 15 D16 D23 D16 D23 D16 D23 D16 D23 D24 D31 D24 D31 D24 D31 D24 D31 A0 NBSO AO NLB NLB BEO A1 NWR2 NBS2 A1 AO AO WE NLB BE2 A2 A25 A 2 25 A 1 24 A 1 24 A 0 23 A 0 23 A 0 23 NCSO CS CS CS CS CS cs NCS1 SDCS CS CS CS CS cs cs NCS2 CS CS CS CS CS cs NCS3 NANDCS cs CS CS CS cs cs NCS4 CFCSO CS CS CS CS cs cs NCS5 CFCS1 CS CS CS CS cs cs NCS6 NANDOE cs CS CS CS cs cs NCS7 NANDWE CS
12. nternal architecture of processor ARM Thumb instruction sets Embedded in circuit emulator ARM9QEu S Technical Reference Manual ARM926EJ S Technical Reference Manual Evaluation Kit User Guide AT91SAM9G10 EKES User Guide Using SDRAM on AT91SAM9 Microcontrollers Using SDRAM on AT91SAM9 Microcontrollers Application Note NAND Flash Support in AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers Application Note 2 Application Note memm 6493A ATARM 31 Jul 09 es caton Note 3 Schematic Check List CAUTION The AT91SAM9 board design must comply with the power up and power down sequence guidelines provided in the datasheet to guarantee reliable operation of the device 1 2V and 3 3V Dual Power Supply Schematic Example 100nF vpDosc GNDOSC 100nF vooPLL GNDPLL VDDIOP 10pF T 1001F DC DC Converter GND nA o VDDIOM 10pF T 100nF F GND re L VDDBU DC DC Converter spay L VDDCORE io ard Power Supply on VDDIOP 3 3V Power Supply on VDDIOM 3 3V 1 These values are given only as a typical example AMEL 6493A ATARM 31 Jul 09 Signal Name AMEL Recommended Pin Connection 1 08V to 1 32V Description Powers the device VDDCORE Decoupling Filtering capacitors E f 100 nF and 10yF 2 Decoupling Filtering capacitors must be added to improve H startup stability and redu
13. roduct Contact Web Site www atmel com www atmel com AT91SAM Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel ma
14. s 1 kOhm Reset Test NRST is configured as an open drain output at power up Application dependent NRST Can be connected to a push button for NRST is controlled by the Reset Controller RSTC hardware reset An internal pull up resistor to Vyppiop 100 kOhm is available for User Reset and External Reset control In harsh environments It is strongly recommended to tie this pin to GNDBU TST if not used or to addian external low Internal pull down resistor to GNDBU 15 kOhm value resistor such as 1 kOhm Internal pull up resistor to Vyppiop 100 kOhm HAr Must be tied to V to boot from Embedded ROM BMS PB Applicat t VDDIOP AUPEN ppsa Gepandan Must be tied to GND to boot from external memory EBI Chip Select 0 Shutdown Wakeup Logic Application dependent Ain no oa tieover Vvopsu e This pin is a push pull output SHDN typical application connects the pin SHDN pin is driven low to GNDBU by the Shutdown SHDN to the shutdown input of the DC DC Controller SHDWC Converter providing the main power supplies This pin is an input only WKUP OV to Vyppeu WKUP behavior can be configured through the Shutdown Controller SHDWC 6493A ATARM 31 Jul 09 AMEL AMEL Signal Name Recommended Pin Connection Description PIO All PIOs are pulled up inputs 100 kOhms at reset except those which are multiplexed with the Address Bus signals that require to be enabled as peripherals Re
15. sh Boot Program Execution Peripheral Pin PIO Line PIOC NAND CS PC14 PIOC NAND OE PCO PIOC NAND WE PC1 Address Bus NAND CLE A21 Address Bus NAND ALE A22 5 5 EEPROM Boot 5 6 SD Card Boot 6493A ATARM 31 Jul 09 The EEPROM Boot program searches for a valid application in the EEPROM memory con nected to the TWI The EEPROM downloaded code size must be smaller than 12 kbytes Table 5 5 Pins driven during EEPROM Boot Program Execution Peripheral Pin PIO Line TWI TWCK PA8 TWI TWD PA7 The SD Card Boot program searches for a valid application in a standard SD Card memory High Capacity SDCards SDHC are not supported by the SDCard Boot The SDCard downloaded code size must be smaller than 12 kbytes Table 5 6 Pins Driven during SD Card Boot Program Execution Peripheral Pin PIO Line MCIO MCCK PA2 MCIO MCCDA PA1 MCIO MCDAO PAO MCIO MCDA1 PA4 MCIO MCDA2 PA5 MCIO MCDA3 PA6 AMEL 1s AMEL Revision History Change Request Doc Rev Comments Ref 6493A First issue 16 Application Note memm 6493A ATARM 31 Jul 09 AIMEL T Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Unit 1 5 amp 16 19 F BEA Tower Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel 852 2245 6100 Fax 852 2722 1369 P
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