IDT - Single Chip Wireless Power Transmitter IC for TX-A1
Contents
1. SAMPLE Sampling Rate Channel Number of Channels at ADC MUX input ADC Clock Full Scale Input Microcontroller FcLock Clock Frequency Input Voltage Note 1 BUCK5VT_IN IN REG IN These pins must be connected together at all times Note 2 This current is the sum of the input currents for IN REG IN and BUCK5VT_IN Note 3 DC DC BUCK5VT LDO2P5V and LDOSV are intended only as internal device supplies and must not be loaded externally except for the EEPROM thermistor LED buzzer and pull up resistor loads up to an absolute maximum of 25mA as recommended in Figure 15 WPC Qi Compliance Schematic and Table 6 WPC Qi Compliance Bill of Materials Note 4 Any external load at the output of the DC DC converter must not inject noise onto the output node and care must be taken with parasitic inductance and capacitance Note 5 Guaranteed by design L H Output Logic Low 7 H L Ro Ro E Es O NO al Revision 1 0 2 8 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet IDT PIN CONFIGURATION TQFN 48L G S o Z Q Z S 2 2 2 S 5 SS B Z z zz 48 42. Product Datasheet Features s Single Chip 5W Solution for Wireless Power Consortium WPC compliant power transmitter design A1 Conforms to WPC specification version 1 1 specifications 19 1V Operating Input Voltage Integrated Half Bridge Inverter Closed Loop Power Transfer Control between Base IDT Station and Mobile Device Demodulates and Decodes WPC Compliant Message Packets 5V Regulated DC DC Converter Integrated RESET Function Proprietary Back Channel Communication 2C Interface Open Drain LED Indicator Outputs Over Temperature Voltage Current Protection Security and encryption up to 64 bits Foreign Object Detection FOD for safety Applications WPC Compliant Wireless Charging Base Stations Package 6x6 48 TQFN See page 27 Ordering Information See page 28 Revision 1 0 2 Wireless Reflection single Chip Wireless Power Transmitter IC for TX A1 IDTP9030 Description The IDTP9030 is a highly integrated single chip WPC compliant wireless power transmitter IC for power transmitter design A1 The device operates with a 19V 1V adapter and supplies an integrated half bridge inverter for DC AC conversion It controls the transferred power by modulating the switching frequency of the half bridge inverter from 110kHz to 205kHz at a fixed 50 duty cycle specified by the WPC specification for an A1 transmitter It contains logic circuits required
3. K P OREN re IK R70 ST j H d E 5 8 3 LEDB 47k 7 35 cPioo 9 9 9 29 S z z z SW v eros sw LT C20 C23 C25 L1 LDO2P5_OUT ee sw 3 2x47nF 250V COG or WPC TX A1 COIL 3x33nF 250V COG LEDC R72 1 COG 24uH gt GPIO_6 C25 33nF 250V vo b D3 NE R9 NP 3 32 Se GPIO_4 PGND D6 NW E S Co 33nF 250V L GPIO_2 PGND e l w D4 200V Diode 36 29 A x NC PGND e C20 33nF 250V oe NP rio NP R71 LDO2P5_OUT 31 28 ES R31 LEDD 7 x NC U1 PGND NP C27 22n 50V 1 5K 23 27 SS S R21 2 Nc IDTP9030 VOSNS e e y NP BZ1 R30 20K 10 6 1 ba XTAL_CLK_IN GPIO_1 DS dJ ete R27 lt T R28 R29 C28 11 2 R22 X XTAL_CLK_OUT 4 7n 47K a 20K 10K 1 2nF 100V 47k 21 gen 7 eye 4 e A v 14 PS1240P02CT3 EEND i x 22n C15 10K R26 43 e Al GND WZ Th1 C5 49 41 T 9 100n ER HPF T kd a R17 10K 22 Gig an ill o DGND J1 10K NZ 1 8nF 1 SCL 8 24 y VIN SCL BUCK5VT_IN e e 2 SDA 9 L SDA c16 c21 0 14u 50V 10u 25V 3 VIN 25 4 LDO5_OUT BUCK5VT_SNS SN j Bsr LZ 5 EN 13 T EN LY L2 4 7uH 5 47nF g G 6 12 26 5V 5 RESET LX A CZ e tu C29 7 RESET S 8 LDO2P5 OUT z gt 6 6 5 C22 C26 Q S A R18 R24 o 3 E 2 2 5 0 1uF 10uF 6 3V u Q Q Q 2 EA gt D 9 WD LDO2P5_OUT 4 E a 100K 10K D o a o 10 5V 2 gt L gt VIN LDO5_OUT LDO2P5_OUT cr R16 R19 R23 0 tuF 10K 2 7K 27K c8 c9 CH C12 u2 T du tu 1u 1u 1 AO VCC S WEE 2 m we 31 sc
4. LDO2P5V SDA T lt gt V y 5 1K R 100 p lt TOR De AN GPIO_6 47K RESET Duc PI 5K V 514K GPIO_5 K 100K 5K YA GPIO_4 Na LEDA Y gt YW LEDB Ye 7 LDO5V are 5K Set M VY NV 5K y SDA lt gt 100nFL Y GPIO_1 5K GPIO_0 Ka 5K y M y Figure 6 IDTP9030 IDTP9020 Simplified Systems Application Diagram Revision 1 0 2 14 2012 Integrated Device Technology Inc IDT IDTP9030 THEORY OF OPERATION The IDTP9030 is a highly integrated WPC Wireless Power Consortium compliant wireless power charging IC solution for the transmitter base station It can deliver more than 5W of power to the receiver when used with the IDTP9020 or BW in WPC Qi mode using near field magnetic induction as a means to transfer energy lt is the industry s first single chip WPC compliant solution designed to drive a WPC compliant Type A1 transmitter coil OVERVIEW Figure 2 shows the block diagram of the IDTP9030 When the VIN_UVLO block detects that the voltage at IN REG_IN and BUCKSVT_IN all connected together externally is above the Vin_rising threshold and EN is at a logic LOW the Enable Sequence circuitry activates the voltage reference the 5V and 2 5V LDOs the 5V buck switching regulator and the Driver Control for the output inverter The voltages at the outputs of the LDOs and the buck regulator are monitored to ensure that they remain in regulation and the adapter voltage coil current and internal temp
5. left to the end user External Components The IDTP9030 requires a minimum number of external components for proper operation see the BOM in Table 10 A complete design schematic compliant to the WPC Qi standard is given in Figure 19 It includes WPC Qi LED signaling buzzer thermistor circuit and EEPROM for loading IDTP9030 firmware Revision 1 0 2 21 2C Communication The IDTP9030 includes an 2C block which can support either 12C Master or 12C Slave operation After power on reset POR the IDTP9030 will initially become DC Master for the purpose of uploading firmware from an external memory device such as an EEPROM The SC Master mode on the IDTP9030 does not support multi master mode and it is important for system designers to avoid any bus master conflict until the IDTP9030 has finished any firmware uploading and has released control of the bus as C Master After any firmware uploading from external memory is complete and when the IDTP9030 begins normal operation the IDTP9030 is normally configured by the firmware to be exclusively in IC Slave mode O 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet For maximum flexibility the IDTP9030 tries to communicate with the first address on the EEPROM at 100kHz If no ACK is received communication is attempted at the other addresses at 300kHz EEPROM The IDTP9030 uses an external EEPROM which contains either standard or custom TX
6. as close to the device and power PGND pins as possible Since the LDOs have been designed to function with very low ESR capacitors a ceramic capacitor is recommended for best performance PCB Layout Considerations For optimum device performance and lowest output phase noise the following guidelines must be observed Please contact IDT for Gerber files that contain the recommended board layout As for all switching power supplies especially those providing high current and using high switching frequencies layout is an important design step If layout is not carefully done the regulator could show 2012 Integrated Device Technology Inc IDT instability as well as EMI problems Therefore use wide and short traces for high current paths The 0 1uF decoupling capacitors must be mounted on the component side of the board as close to the VDD pin as possible Do not use vias between decoupling capacitors and VDD pins Keep PCB traces to each VDD pin and to ground vias as short as possible To optimize board layout place all components on the same side of the board and limit the use of vias Route other signal traces away from the IDTP9030 For example use keepouts for signal traces routing on inner and bottom layers underneath the device The NQG48 6 0 mm x 6x0 mm x 75mm 48L package has an inner thermal pad which requires blind assembly It is recommended that a more active flux solder paste be used such as Al
7. firmware The external EEPROM memory chip is pre programmed with a Standard start up program that is automatically loaded when 19V power is applied The IDTP9030 uses 12C slave address 0x52 to access the EEPROM The IDTP9030 Slave address is 0x39 The EEPROM can be reprogrammed to suit the needs of a specific application using the IDTP9030 software tool see the IDTP9030 Q Demo Board User Manual for complete details The IC will look initially for an external EEPROM and use the firmware built into the IC ROM only if no custom firmware is found A serial 8Kbyte 8Kx8 64Kbits external EEPROM is sufficient If the standard default built in firmware is not suitable for the application custom ROM options are possible Please contact IDT sales for more information IDT will provide the appropriate image in the format best suited to the application Overview of Standard GPIO Usage There are 7 GPIO s on the IDTP9030 transmitter IC of which five are available for use as follows e GPIO0O Red LED_A to indicate standby fault conditions and FOD warnings see table 7 e GPIO2 Temperature sensor input Contact IDT for a spreadsheet facilitating selection and use of thermistors e GPIO3 Green LED B to indicate standby power transfer and power complete Table 7 lists how the red and green LEDs can be used to display information about the IDTP9030 s operating modes The table also includes information about external resistors or intern
8. 2 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet TYPICAL PERFORMANCE CHARACTERISTICS EN 0 IN BUCK5VT_IN REG IN 19V TA 25 C Unless otherwise noted System Efficiency versus RX Output Power TX Input to RX Output IDTP9030 Qi TX A1 Evaluation Kit and IDTP9020 CSP Engineering Sample PCB V1 0 gt Q c wv Q E GQ LL 2 2 5 3 RX Output Power W Figure 4 Efficiency vs RX Output Power with IDTP9020 Receiver Efficiency versus RX Output Power TX DC to AC IDTP9030 Qi TX A1 Evaluation Kit and AVID Technologies Inc Qi Receiver Simulator Efficiency 2 2 5 3 3 5 4 4 5 5 RX Output Power W O gt Ln LA LA Ln Figure 5 Spacing between TX and RX coils is 2 mm Revision 1 0 2 13 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet SYSTEMS APPLICATIONS DIAGRAM Inverter C Modulation Modulation O0 m LET hased ADAPTOR C5 EN gt E WPC TX A1 10K 4x22uF 1 100nF VO Gase 183nF i gt gt REC_OUT 250V y 1 5K 22nF 20K 11 4uH 2nF l J 10K 1 PEN K Y 20K USB ADP_IN gt 1 gur REC OUT gt LDOSV_T sche d gt BUCK5VR Y 47nF y LDO2P5V_T BUCK5VT i 1uF 25V REC OUT gt 4 7uH d 47nF LDO2P5V_IN L___ gt TE gt 10uF C gt LDO5V RESET T gt T L Buzzer 47K BUCK5VR gt SCL_T lt gt gt gt
9. 5K 22nF 20K d WW bs IER Ki Ki 10K S 2 2nF K 1 Sep HPA L H LDO5V BUCKSVT el LDO2P5V_IN Y LDO2P5V BUCK5VT 1uF 25V 4 7uH 10uF L Buzzer am D ps Z 4 a Y Y O 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet ADAPTOR ECO Sus WPC TX A1 4x22uF 1 100nF VO 3x33nF 250V 1 5K IL luF 25V EN CS RESET L gt SCL lt SDA lt gt Figure 1 IDTP9030 Simplified Application Schematic Note 1 NPO COG type ceramic capacitor Note 2 For PCB layout use single point reference star ground refer to design schematic in Figure 15 Note 3 In circuit at GPIO_2 Rrop is required to linearize the temperature range of the thermistor Rnrc Please contact IDT for a spreadsheet calculator to guide thermistor selection Revision 1 0 2 2 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet ABSOLUTE MAXIMUM RATINGS These absolute maximum ratings are stress ratings only Stresses greater than those listed below Table 1 and Table 2 may Cause permanent damage to the device Functional operation of the IDTP9030 at absolute maximum ratings is not implied Exposure to absolute maximum rating conditions for extended periods may affect long term reliability Table 1 Absolute Maximum Ratings Summary All voltages are referred to ground unless otherwise noted PINS MAXIMUM us RATING BUCKSVT_I
10. 7 46 45 44 43 42 41 40 39 38 37 GPIO 6 1 ae MG GPIO5 2 O 35 SW i GPIO 4 3 p 34 SW d GPIO 3 4 33 ew GPIO 2 5 32 PGND i GPIO 1 6 31 NC i EP Center Exposed Pad GPIO 0 7 30 PGND i SCL 8 29 PGND i SDA 9 28 PGND XTAL CLK IN 10 i 27 VOSNS XTAL CLK_OUT 11 26 LX LC e A SS SS Sie Ss Ss SSS Sas Ss Ss SR Ae Set J RESET 12 25 BUCK5VT_SNS 13 14 15 16 17 18 19 20 21 22 23 24 A za gt gt za ke a A O Z Z LO LX K Y Z zZ Z G O Q Ay gt So m O G E LL Ww a O LO ef A gt W cc a S S 2 e a O E O A gt l faa Figure 3 IDTP9030 Pin Configuration NTG48 TQFN 48L 6 0 mm x 6 0 mm x 0 75 mm 0 4mm pitch Revision 1 0 2 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet PIN DESCRIPTION Table 7 IDTP9030 NTG48 Package Pin Functions by Pin Number NAME TYPE DESCRIPTION e on e ome TRI e TRI STR ees e rea orana A E Active high chip reset pin A 1uF ceramic capacitor must be connected between this pin and LDOS5V and a 100kQ resistor to GND 12 RESET gt Active low enable pin Device is suspended and placed in low current sleep mode when pulled high Tie to GND for stand alone operation REFGND Signal ground connection Must be connected to AGND Signal ground connection Must be connected to Signal ground connection Must be connected to AGND REG
11. 9030 IC package in proximity to other heat generating devices in a given application design The ambient temperature around the power IC will also have an effect on the thermal limits of an application The main factors influencing Du in the order of decreasing influence are PCB characteristics die package attach thermal pad size and internal package construction Board designers should keep in mind that the package thermal metric Du is impacted by the characteristics of the PCB itself upon which the TQFN is mounted For example in a still air environment as is often the case a significant amount of the heat that is generated 60 85 sinks into the PCB Changing the design or configuration of the PCB changes impacts the overall thermal resistivity and thus the board s heat sinking efficiency 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet Implementation of integrated circuits in low profile and fine pitch surface mount packages typically requires special attention to power dissipation Many system dependant issues such as thermal coupling airflow added heat sinks and convection surfaces and the presence of other heat generating components affect the power dissipation limits of a given component Three basic approaches for performance are listed below 1 Improving the power dissipation capability of the PCB design 2 Improving the thermal coupling of the component to the PCB 3 Introducing airf
12. Buzzer Function An optional buzzer feature is supported on GPIO4 The default configuration is an AC buzzer The signal is created by toggling GPIO4 active high active low at a 2KHz frequency Buzzer Action Power Transfer Indication The IDTP9030 supports audible notification when the device operation successfully reaches the Power Transfer State The duration of the power transfer indication sound is 400ms The latency between reaching the Power Transfer state and sounding the buzzer does not exceed 500ms Additionally the buzzer sound is concurrent within 250ms of any change to the LED configuration indicating the start of power transfer Buzzer Action No Power Transfer due to Foreign Object Detected FOD When a major FOD situation is detected such that for safety reasons power transfer is not initiated or that power transfer is terminated the buzzer is sounded in a repeating sequence Revision 1 0 2 23 LED1 Green BLINKSLOW ON OFF OFF Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINKFAST For 30 seconds 400ms ON 800ms OFF repeat Next 30 seconds Off silence but no change to LED on off patterns The pattern is repeated while the error condition exists The buzzer is synchronized with the FOD LED such that the 400ms on tone corresponds with the Red LED illumination and 800ms off no sound corresponds with Red LED being off Decoupling Bulk Capacitors As with any high performance
13. DE Table 8 Ordering Summary PART NUMBER AMBIENT TEMP SHIPPING MARKING PACKAGE RANGE CARRIER QUANTITY P9030 ONTGI P9030NTG NTG48 TQFN 48 6x6x0 75mm 40 C to 85 C Tape or Canister 29 P9030 ONTGI8 P9OSONTG NTG48 TQFN 48 6x6x0 75mm 40 C to 85 C Tape and Reel 2 000 IDT www IDT com 6024 Silver Creek Valley Road San Jose California 95138 Tel 800 345 7015 DISCLAIMER Integrated Device Technology Inc IDT and its subsidiaries reserve the right to modify the products and or specifications described herein at any time and at IDT s sole discretion All information in this document including descriptions of product features and performance is subject to change without notice Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in life support systems or similar devices w
14. N IN REG_IN THESE PINS MUST BE CONNECTED TOGETHER AT ALL TIMES 0 3 to 24 V EN LX SWS 0 3 to 24 V BST 0 3 to 29 V LDO2P5V XTAL CLK_IN XTAL CLK_OUT 0 3 to 2 75 V AGND DGND PGND REFGND 0 3 to 0 3 V BUCKSVT_SNS BUCKSVT GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 HPF 0310455 V ISNS LDO2P5V_IN LDOSV RESET SCL SDA VOSNS DIO Table 2 Package Thermal Information SYMBOL DESCRIPTION UNITS MAXIMUM RATING Oya Thermal Resistance Junction to Ambient NTG48 TQFN 30 8 C W Buc Thermal Resistance Junction to Case NTG48 TQFN 14 6 C W Dm Thermal Resistance Junction to Board NTG48 TQFN 0 75 C W TLEAD Lead Temperature soldering 10s oC Note 1 The maximum power dissipation is Pomax Tumax Ta Qa where Tumax is 125 C Exceeding the maximum allowable power dissipation will result in excessive die temperature and the device will enter thermal shutdown Note 2 This thermal rating was calculated on JEDEC 51 standard 4 layer board with dimensions 3 x 4 5 in still air conditions Note 3 Actual thermal resistance is affected by PCB size solder joint quality layer count copper thickness air flow altitude and other unlisted variables Note 4 For the NTG48 package connecting the 4 1 mm X 4 1 mm EP to internal external ground planes with a 5x5 matrix of PCB plated through hole PTH vias from top to bottom sides of the PCB is recommended for improving the overall thermal perform
15. ON 800ms OFF 400ms ON 800ms OFF repeat The red FOD warning LED is synchronized with the buzzer if implemented such that a 400ms_ tone corresponds with the FOD red LED illumination and 800ms of silence corresponds with the LED being off During the 30s that the buzzer is off the FOD LED must continue to blink 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet Table 7 IDTP9030 LED Resistor Optioning Not all options supported shaded rows are for future development LED Control LED Select LED Option Resistor Value Description Color Operational Status FOD Standby Warning 1 Pull Down Standby LEDs ON Standby LEDs ON plus wee Bad on fee fe Standby LEDs ON plus LEDZ Red DECIA a E ETON TEO LED1 Green ON BLINKSIOW ON OFF OFF Standby LEDs ON plus LED2 Red ON OFF OFF o BLINKFAST LED1 Green ON BLINKSLOW ON OFF OFF Standby LEDs ON plus LED2 Red ON OFF OFF ON __ BLINKFAST en Kl ll Pull Up Standby LEDs Op LED2 Red OFF OFF Tor ON BLINKFAST Ba L on oe ore Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINK FAST LED1 Green BLINKSLOW ON OFF OFF Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINKFAST LED1 Green BLINK SLOW ON OFF OFF Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINKFAST R1 R8 are created using combination of two 1 resistors Designates Future Option
16. WPC Operating Range in o at SW compliance with WPC requirements II me kHz Between IN and SW A mo BOER O em ON Ls Between SW and PGND UVLO and Inverter OCP nig ws Vimo DEE Dr al IL a RE e EES e Over Current Vin 20V cycle by cycle A Geet Protection Trip Point protection DC DC Converter For Biasing Internal Circuitry Only Input Voltage EEE Veur Output Voltage 1 External lw 25mA 45 55 vw floor Extemalloadi fm Switching Frequency rn Fred AOS Te Low Drop Out Regulators For Biasing Internal Circuitry Only LDO2P5V Vivos Input Voltage Range SuppliedfromBUCKSVT_ J LV Vicos OutputVoltage naw 2mA rs Y wo dor Extemalload Pm LDOSV Veco InputVoltage Range SeeNotet s 20 vw Vivo OutputVoltage how 2mA loo wo Revision 1 0 2 6 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet ELECTRICAL CHARACTERISTICS EN RESET OV IN REG_IN BUCK5VT_IN 19V Ta 40 to 85 C unless otherwise noted Typical values are at 25 C unless otherwise noted Table 5 Device Characteristics Continued SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNITS Thermal Shutdown Te memaisuitom S AM 8 Temperature Falling Threshold of Ve LL LL 00 1 nm Mo ET mm mV Gi Auen oem LL Jm O vwaw Lal m General Purpose Inputs Outputs GPIO Vu imputThresholdHign IL 38 LL Ly Ve ImputThres
17. Wi A 1uF ceramic capacitor must be connected between this pin and GND This pin must be connected to pins 37 38 and 39 ER LDOSV2 0 AF ceramic capacitor must be connected between tis pin and GND A 1uF ceramic capacitor must be connected between this pin and AUF ceramic capacitor must be connected between this pin and a LDO2P5V2 0 25V LDO output TE ceramic capacitor must be connected between this pin and GND 2 5V 25V LDO output A uF ceramic capacitor must be connected between this pin and GND output A 1uF ceramic capacitor must be connected between this pin and GND 2 5V LDO input The LDO2P5V_IN input must be connected to BUCKOVT A 1uF ceramic LDO2P5V_IN capacitor must be connected between this pin and GND E BUCK5SVT2 1 Power and digital supply input to internal aana Power and digital supply input to intemal circuitry and digital supply input to internal circuitry Revision 1 0 2 10 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet Table 7 IDTP9030 NTG48 Package Pin Functions by Pin Number NAME TYPE DESCRIPTION COCO ETT E ON O E Buck converter power supply input Connect 0 1uF and 1uF ceramic capacitors between 1 24 BUCKOVT_IN this pin and PGND This pin must be connected to pins 37 38 and 39 EMO TON CC EN IO CN IC E CN a ee E CN o f e pee a ee pe a fe Pins 33 34 and 35 must be connected together Inverter switch node Must be connected to capacitor
18. al pull up down options to select LED modes Eight of the ten LED modes those associated with advanced charging modes are currently designated as Future modes e GPIO4 AC or DC buzzer optional with resistor options for different buzzer configurations Revision 1 0 2 e GPIO5 LEDC and GPIO6 LEDD are for future development and are currently not defined LED FUNCTIONS Two GPIOs are used to drive LEDs which indicate through various on off and illumination options the state of charging and some possible fault conditions A red LED indicates various Fault and FOD Foreign Object Detection states The green LED indicates Power Transfer and Charge Complete state information Upon power up the two LEDs together may optionally indicate the Standby State and remain in this state until another of the defined Operational States occurs As shown in Figure 16 one or two resistors configure the defined LED option combinations The DC voltage set in this way is read one time during power on to determine the LED configuration To avoid interfering with the LED operation the useful DC voltage range must be limited to not greater than 1Vdc LDO2P5V_OUT IDTP9030 Ra GPIO3 Resistor BB To ADC to set Rb options LED Mode Resistor Configuration Figure 16 IDTP9030 LED Resistor Options LED Pattern Operational Status Definitions Blink Slow 1s ON 1s OFF repeat Blink Fast 400ms
19. ance Note 5 If the voltage at VIN is less than 24V limit the voltages on EN LX SW to V VIN 0 3V and the voltage on BST to V VIN 5V Revision 1 0 2 3 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet Table 3 ESD Information MAXIMUM Bie RATINGS All except IN Only IN 37 38 and 39 Revision 1 0 2 4 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet BLOCK DIAGRAM IN E cen o BUCKSVT L L pos CT LX BUCKSVT_IN LL Be REG IN 1 Current Limit EN SW VIN_OVP Demodulator GND T PGND SCL anal HPF SDA ISNS VOSNS Micro Controller GPIO lt 6 0 gt Unit MCU MCU Peripherals Clock XTAL CLK_IN 1 Generation ctrl_osc_sel XTAL CLK_OUT IDTP9030 Figure 2 IDTP9030 Internal Functional Block Diagram Revision 1 0 2 5 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet ELECTRICAL CHARACTERISTICS EN RESET OV IN REG_IN BUCK5VT_IN 19V Ta 40 to 85 C unless otherwise noted Typical values are at 29 C unless otherwise noted Table 4 Device Characteristics SYMBOL DESCRIPTION CONDITIONS MAX Half Bridge Inverter Input Supply VIN Operating Voltage V Range After power up sequence complete Standby Input No coil no load at SW LDOSV R wat Current LDO2P5V LX No wireless power lin transfer to ae Sp CE pete Switching Frequency
20. ation from the WPC specification IDT has found that the circuit of Figure 9 is preferred for lower noise in the demodulation channel 19V 24 uH Driver A1 Coil 400 nF Sp Figure 9 Half Bridge inverter TX Coil Driver EXTERNAL CHIP RESET and EN The IDTP9030 can be externally reset by pulling the RESET pin to a logic high above the V level The RESET pin is a dedicated high impedance active high digital input and the effect is similar to the power up reset function Because of the internal low voltage monitoring scheme the use of the external RESET pin is not mandatory A manual external reset scheme can be added by connecting 5V to the RESET pin through a simple switch When RESET is HIGH the microcontrollers registers are set to the default configuration When the RESET pin is released to a LOW the microcontroller starts executing the code from the boot address If the application is in a noisy environment an external RC filter is recommended see Figure 10 for reference 2012 Integrated Device Technology Inc IDT LDOSV PUSH BUTTON C2 SWITCH 1 uF RESET C1 R 0 uF 10K 100K Figure 10 External Pushbutton Reset Circuit When the EN pin is pulled high the device is suspended and placed in low current sleep mode If pulled low the device is active EN rising edge function see UV Buck BVour 2 5V Div ENV 5V Div O lt Time 1ms div Figure 11 EN Fu
21. connected to the ADC have limited input range so attention must be paid to the maximum VIN 2 5V 0 01uF decoupling capacitors can be added to the GPIO inputs to minimize noise WPC TX A1 Coil The SW pin connects to a series resonance circuit comprising a WPC Type A1 coil 24uH and a series resonant capacitor 100nF as shown in Figures 8 and 9 The inductor serves as the primary coil in a loosely coupled transformer the secondary of which is the inductor connected to the power receiver IDTP9020 or another receiver The TX A1 power transmitter coil is mounted on a ferrite shield to reduce EMI The coil assembly can be mounted next to the IDTP9030 Either ground plane or grounded copper shielding can be added beneath the ferrite shield for added reduction in radiated electrical field emissions The coil ground plane shield must be connected to the IDTP9030 ground plane by a single trace Resonance Capacitors The resonance capacitors must be COG type dielectric and have a DC rating to 250V The highest efficiency combination is three 33nF in parallel to get the lowest ESR Using a single 100nF or two 47nF capacitors is also an option The part numbers are shown in Table 6 Buck Converter The input capacitors Cin must be connected directly between the power Vin and power PGND pins The output capacitor Cour and power ground must be connected Revision 1 0 2 24 CG Y T l d D together to minimize any DC reg
22. eceived the IDTP9030 goes to the Identification and Configuration Phase If the IDTP9030 does not move to the Identification and Configuration Phase after receiving the signal strength packet or if a packet other than a signal strength packet is received then power is terminated IDENTIFICATION AND CONFIGURATION ID amp Config In this phase the IDTP9030 tries to identify the mobile device and collects configuration information Required packet s in ID amp Config 1 Identification packet 0x71 2 Extended Identification packet 0x81 3 Configuration packet 0x51 If Ext bit of 0x71 packet is set to 1 Revision 1 0 2 IDT Also the IDTP9030 must correctly receive the following sequence of packets without changing the operating point 175 kHz 50 duty cycle 1 Identification Packet 0x71 2 Extented Identification 0x81 3 Up to 7 optional configuration Packets from the following set a Power Control Hold Off Packet 0x06 b Proprietary Packet 0x18 OxF2 c Reserved Packet 4 Configuration Packet 0x51 If the IDTP9030 does not detect the start bit of the header byte of the next Packet in the sequence within a WPC specified time after receiving the stop bit of the checksum byte of the preceding Signal Strength Packet then the Power Signal is removed within after a delay If a correct control packet in the above sequence Is received late or if control packets that are not in the sequence are rec
23. ed Figure 12 System state machine diagram The IDTP9030 performs four phases Selection Ping Identification amp Configuration and Power Transfer START SELECTION PHASE 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet In this phase the IDTP9030 operates in a low power mode to determine if a potential receiver has been placed on the coil surface prior to the PING state Twice a second the IDTP9030 applies a brief ac signal to its coil and listens for a response PING PHASE In this phase the IDTP9030 applies a power signal at 175 kHz with a fixed 50 duty cycle and attempts to establish a communication link with a mobile device Required packet s in PING 1 Signal strength packet 0x01 The mobile device must send a Signal Strength Packet within a time period specified by the WPC otherwise the power signal is terminated and the process repeats The mobile device calculates the Signal Strength Packet value which is an unsigned integer value between 0 255 based on this formula U 256 max Signal Strength Value where U is a monitored variable i e rectified voltage current power and Umax is a maximum value of that monitored variable expected during the digital ping phase at 175 kHz If the IDTP9030 does not detect the start bit of the header byte of the Signal Strength Packet during the Ping Phase it removes the power signal after a delay If a signal strength packet is r
24. eived the IDTP9030 removes the Power Signal after a delay POWER TRANSFER PHASE In this phase the IDTP9030 adapts the power transfer to the receiver based on control data it receives in control error packets Required packet s in Power Transfer 1 Control Error Packet 0x03 2 Rectified Power Packet 0x04 For this purpose the IDTP9030 may receive zero or more of the following Packets 1 Control Error Packet 0x03 Rectified Power Packet 0x04 Charge Status Packet 0x05 End Power Transfer Packet 0x02 Any Proprietary Packet 6 Any reserved Packets oe SS a If the IDTP9030 does not correctly receive the first Control Error Packet in time it removes the Power Signal after a delay Because Control Error Packets come at a regular interval the IDTP9030 expects a new Control Error Packet after receiving the stop bit of the checksum byte of the preceding Control Error Packet If that does not 2012 Integrated Device Technology Inc IDT happen then the IDTP9030 removes the Power Signal Similary the IDTP9030 must receive a Rectified Power Packet within a WPC specified time after receiving the stop bit of the checksum byte of the Configuration Packet which was received earlier in the identification and configuration phase Otherwise it removes the Power Signal Upon receiving a Control Error value the IDTP9030 makes adjustments to its operating point after a delay to enable the Primary Coil current to stab
25. erature are monitored The Driver Control block converts a PWM signal from the MCU to the gate drive signals required by the output inverter to drive the external resonant tank Communication packets from the receiver in the mobile device are recovered by the Demodulator and converted to digital signals that can be read by the MCU Several internal voltages and the external thermistor voltage through GPIO2 are converted to their digital representations by the ADC and supplied to the MCU Five GPIO ports are available to the system designer for measuring an external temperature ambient or inductor for example and driving LEDs and a buzzer The clock for the MCU and other circuitry is generated by either an external crystal or an internal RC oscillator H SDA and SCL pins permit communication with an external device or host Note 1 Refer to the WPC specification at http www wirelesspowerconsortium com for the most current information Revision 1 0 2 15 Product Datasheet UNDER VOLTAGE LOCKOUT UVLO The IDTP9030 has a built in UVLO circuit that monitors the input voltage and enables normal operation as shown in Figure 7 UVLO exit event Veon 10V div 3 G Vin 10V maaan gt OV 0 Time 1s div Figure 7 Vin versus UVLO threshold with EN low OVER CURRENT VOLTAGE TEMPERATURE PROTECTION The current in the inverter is monitored by an analog Current Limit block If the instantaneous coil cu
26. here the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own risk absent an express written agreement by IDT Integrated Device Technology IDT and the IDT logo are registered trademarks of IDT Other trademarks and service marks used herein including protected names logos and designs are the property of IDT or their respective third party owners O Copyright 2012 All rights reserved
27. i 4 5 VSS SDA z 24LC64 IDT Figure 15 IDTP9030 WPC Qi Compliance Schematic See IDTP9030 Evaluation Kit User Manual for complete details 20 2012 Integrated Device Technology Inc Die y e IDTP9030 Product Datasheet Table 6 IDTP9030 WPC Qi Compliance Bill of Materials Item Qty gt 3 k ojo de 4 k R e 8 9 18 N N NINININININJ 1INJ o O Description Manufacturer Part PCBFootprint JMK212B7106KG T CAP CER 3300PF 50V 5 NPO COG GCM1885C1H332JA16D DK DK DK i S DK ko 4 7uH 20 580mA XPL2010 472ML 24uH Transmitter Coil WPC TX A1 TIx 52 T2V 53mmx53mm ae RES 10 0K OHM 1 10W 1 0603 SMD IC Wireless Power Transmitter 6x6x0 8 48TQFN THERMISTOR NTC 10K OHM 19 RAD Note 1 Recommended capacitor temperature dielectric and voltage ratings 250V capacitors are recommended because 200Vp p voltage levels may appear on the resonance capacitors as stated in the WPC specification COG NPO type capacitor values stay relatively constant with voltage while X7R and X5R ceramic capacitor values de rate from 40 to over 80 The decision to use lower voltage 100V capacitors or other type temperature dielectric capacitors is
28. ilize again after communication If the IDTP9030 correctly receives a Packet that does not comply with the sequence then it removes the Power Signal FOREIGN OBJECT DETECTION FOD In addition to over temperature protection the IDTP9030 employs a proprietary FOD technique for safety which detects foreign objects placed on the base station The FOD algorithm is multi layered and issues warnings depending on the severity of the warning The FOD warning comes on during the PING phase indicating the presence of a smaller object and larger object respectively The FOD warning is asserted during the Power Transfer phase indicating presence of a foreign object With this warning ON the IDTP9030 stops power transfer goes back to the PING phase and stays there until the surface is cleared and the process starts over again Revision 1 0 2 19 IDTP9030 Product Datasheet 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet APPLICATIONS INFORMATION Revision 1 0 2 y L AC Adapter 2 p 3 c2 C4 VIN VIN l J3 A 82uF 25V OSCON gt gt ou C6 E gt 610 Gil cia LDO2P5_OUT out 22uF 25V 22uF 25V 22uF 25V 22uF 25V LEDA R69 NE E K D1 RED R7 514K RR NS D2
29. in series with TX A1 coll Inverter power supply input Connect at least four 22uF x 25V ceramic capacitors and a 0 1uF capacitor between this pin and ground as close to the pin as possible Connect all three pins 37 38 39 in parallel e ISNS o ISNS output signal Revision 1 0 2 11 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet Table 7 IDTP9030 NTG48 Package Pin Functions by Pin Number NAME TYPE DESCRIPTION PIN DESCRIPTION IU O mem ERC E EEE of e E CIN ERC O ETE o E EE Internal connection must be connected to GND e NS Internal connection must be connected to GND e Internal connection do not connect EP is on the bottom of the package and must be electrically tied to GND For thermal Center Exposed performance solder to a large copper pad embedded with a pattern of plated through hole vias Pad Thermal The die is not electrically bonded to the EP and the EP must not be used as current carrying electrical connection Note 1 IN REG_IN BUCK5VT_IN These pins must be connected together at all times Note 2 DC DC BUCK5VT LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM thermistor LED buzzer and pull up resistor loads up to an absolute maximum of 25mA as recommended in Figure 15 WPC Qi Compliance Schematic and Table 6 WPC Qi Compliance Bill of Materials Revision 1 0 2 1
30. low into the system First the maximum power dissipation for a given situation must be calculated enhancing thermal Pomax T waw Ta Qua Where Pomax Maximum Power Dissipation W Oya Package Thermal Resistance C W T ymax Maximum Device Junction Temperature C Ta Ambient Temperature C The maximum recommended junction temperature T wa for the IDTP9030 device is 150 C The thermal resistance of the 48 pin NQG package NGQ48 is optimally 8j 30 C W Operation is specified to a maximum steady Revision 1 0 2 26 IDT state ambient temperature Ta of 85 C Therefore the maximum recommended power dissipation is Pomax 150 C 85 C 30 C W 2 Watt Thermal Overload Protection The IDTP9030 integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions This circuitry will shut down or reset the device if the die temperature exceeds 140 C To allow the maximum load current on each regulator and resonant transmitter and to prevent thermal overload it is important to ensure that the heat generated by the IDTP9030 is dissipated into the PCB The package exposed paddle must be soldered to the PCB with multiple vias evenly distributed under the exposed paddle and exiting the bottom side of the PCB This improves heat flow away from the package and minimizes package thermal gradients Special N
31. mixed signal IC the IDTP9030 must be isolated from the system power supply noise to perform optimally A decoupling capacitor of 0 1uF must be connected between each power supply and the PCB ground plane as close to these pins as possible For optimum device performance the decoupling Capacitor must be mounted on the component side of the PCB Avoid the use of vias in the decoupling circuit Additionally medium value capacitors in the 22uF range must be used at the VIN input to minimize ripple current and voltage droop due to the large current requirements of the resonant half Half Bridge driver At least four 22uF 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet Capacitors must be used close to the IN pins of the device Since the operating voltage is 18V to 20V the value of the capacitors will decrease due to voltage derating characteristics For example a 22uF X7R 25V capacitor s value is actually 6uF when operating at 20V There must also be an 82uF to 100uF bulk capacitor connected at the node where the input voltage to the board is applied A 25V Oscon type or aluminum electrolytic must be connected between the input supply and ground as shown in Figure 20 Oscon capacitors have much lower ESR than aluminum electrolytic capacitors and will reduce voltage ripple ADC Considerations The GPIO pins are connected internally to a successive approximation ADC with a multiplexed input The GPIO pins that are
32. moldlow CT 15 vw lxs Imputleakage _____________ _ 4 pa Vo OutputlogicHigh Loc n IL 2 vw Va OutputLogiclow la 8ma____ gt _ gt ___ _0s vw low OutputCuentHigh Tm dao OutputCurrentlow LL 8 ma RESET v InputThresholdHigh CT va imputThreshodlow 1 LL 18 vw lxs Imputleakage ______________J _ 4 LL Lu SCL SDA SC Interface fs Clock Frequency ERE EE 100 a kHz Zi Clock Frequency oo MN 300 UN kHz fscL Clock Frequency DTP9030 as Slave Hold Time tHD STA Repeated for START Condition CBUS compatible masters ls oo oo ys pata hod Time Ise devices SSC P Clock LowPeriod ota S S Se tHon Clock High Period d o Ce Set up Time for Repeated START Condition tSU STA e lt CH O 5 N T 2012 Integrated Device Technology Inc IDTP9030 IDT Product Datasheet ELECTRICAL CHARACTERISTICS EN RESET OV IN REG_IN BUCK5VT_IN 19V Ta 40 to 85 C unless otherwise noted Typical values are at 25 C unless otherwise noted Table 6 Device Characteristics Continued SYMBOL DESCRIPTION CONDITIONS Bus Free Time Tour Between STOP and START Condition c Capacitive Load for Each Bus Line c SCL SDA Input E Capacitance nput Threshold Low V V vu Input Threshold High Leakage Current B O O Output Current High Output Current Low Analog to Digital Converter ADC Conversion N Resolution
33. nction The current into EN is about v EN 2v 300k or close to zero if V EN is less than 2V XTAL_CLK IN and XTAL_CLK OUT A 32 68kHz crystal connected between the XTAL CLK_IN and XTAL CLK_OUT pins establishes a precise time base Either that clock or the output of an on I EN Revision 1 0 2 17 IDTP9030 Product Datasheet chip RC oscillator is provided to the input of a PLL to generate the system clock IDT recommends using the internal oscillator SYSTEM FEEDBACK CONTROL WPC The IDTP9030 contains logic to demodulate and decode error packets sent by the mobile device Rx side and adjusts power transfer accordingly The IDTP9030 varies the switching frequency of the half bridge inverter between 110kHz to 205 kHz to adjust power transfer The mobile device controls the amount of power transferred via a communication link that exists from the mobile device to the base station The mobile device IDTP9020 or another WPC compliant receiver communicates with the IDTP9030 via communication packets Each packet has the following format Table 5 Data Packet Format Preamble Header Pmt te e The overall system behavior between the transmitter and receiver follows the state machine diagram below Transmitter Receiver E Signal gt PA Object Signal detected 5 Ze El rng Ze S E S 0 s 5 Oo Detected 7 S E i a z Identification E C dentification _ S 5 Required Power E Adapt
34. otes NQG TQFN 48 Package Assembly Note 1 Unopened Dry Packaged Parts have a one year shelf life Note 2 The HIC indicator card for newly opened Dry Packaged Parts should be checked If there is any moisture content the parts must be baked for minimum of 8 hours at 125 C within 24 hours of the assembly reflow process 2012 Integrated Device Technology Inc IDT IDTP9030 Product Datasheet PACKAGE OUTLINE DRAWING REVISIONS DESCRIPTION DATE APPROVED INITIAL RELEASE 3 16 10 POD IN BOTTOM VIEW 6 00 0 10 40 Ref P SIZE 4 5x4 5 6 00 0 10 4 10 0 10 0 10 0 55 mi 0 40 N JL TOLERANCES 7 6024 SILVER CREEK UNLESS SPECIFIED pm VALLEY ROAD SAN JOSE POD IN SIDE VIEW DECIMAL ANGULAR CA 95138 S a 1 PHONE 408 284 8200 S Ge o0 www IDT com FAX 408 284 3572 APPROVALS DATE TITLE NT NTG48 PACKAGE OUTLINE DRAWN PKP 12 04 09 6 0 x 6 0 mm BODY CHECKED 0 4 mm PITCH TQFN SIZE DRAWING No REV C PSC 4294 00 DO NOT SCALE DRAWING SHEET OF 1 0 75 0 05 Figure 17 IDTP9030 Package Outline Drawing NTG48 TQFN 48L 6 0 mm x 6 0 mm x 0 75 mm48L 0 4mm pitch Revision 1 0 2 27 2012 Integrated Device Technology Inc VPAXxxx IDT Preliminary Product Data ORDERING GUI
35. pha OM 350 solder paste from Cookson Electronics http www cooksonsemi com Please contact IDT for Gerber files that contain recommended solder stencil design The package center exposed pad EP must be reliably soldered directly to the PCB The center land pad on the PCB set 1 1 with EP must also be tied to the board ground plane primarily to maximize thermal performance in the application The ground connection is best achieved using a matrix of PTH vias embedded in the PCB center land pad for the NTG48 The PTH vias perform as thermal conduits to the ground plane thermally a heat spreader as well as to the solder side of the board There these thermal vias embed in a copper fill having the same dimensions as the center land pad on the component side Recommendations for the via finished hole size and array pitch are 0 3mm to 0 33mm and 1 3mm respectively Layout and PCB design have a significant influence on the power dissipation capabilities of power management ICs This is due to the fact that the surface mount packages used with these devices rely heavily on thermally conductive traces or pads to transfer heat away from the package Appropriate PC layout techniques must then be used to remove the heat due to device power dissipation The following general guidelines will be helpful in designing a board layout for lowest thermal resistance 1 PC board traces with large cross sectional areas remove more heat For optim
36. rrent exceeds 2A the chip is shut down VIN_OVP monitors the voltage applied to the IDTP9030 by the external AC adapter and shuts the part down if the adapter voltage rises above 24V to protect against excessive power transfer to the receiver The internal temperature is also monitored and the part is temporarily deactivated if the temperature exceeds 140 C and reactivated when the temperature falls below 110 C DRIVER CONTROL BLOCK and INVERTER The Driver Control block contains the logic shoot through protection and gate drivers for the on chip power FETs The FETs are configured as a very large inverter that switches the SW pin between the voltage at IN and ground at a rate set by the MCU 2012 Integrated Device Technology Inc IDTP9030 Product Datasheet DEMODULATOR Power is transferred from the transmitter to the receiver through their respective coils a loosely coupled transformer How much power is transferred is determined by the transmitter s switching frequency 110kHz 205kHz and is controlled by the receiver through instructions sent back through the coils to the transmitter to change its frequency end power transfer or do something else The instructions take the form of data packets which are capacitively coupled into the IDTP9030 s Demodulator through the HPF pin Recovering the data packets is the function of the Demodulator Understanding the packets is up to the MCU OUTPUT VOLTAGE SENSE The vol
37. tage at the junction of the external inductor and capacitor that comprise the resonant tank is monitored by the VOSNS block digitized by the ADC and fed to the digital control logic The control algorithm also requires knowledge of the voltage across the inverter so that voltage is also processed by the ADC and sent to the digital block MICRO CONTROLLER UNIT MCU The IDTP9030 s MCU processes the algorithm commands and data that control the power transferred to the reciever The MCU is provided with RAM and ROM and parametric trim and operational modes are set at the factory through the One Time Programming OTP block read by the MCU at power up Communication with external memory is performed through H via the SCL and SDA pins APPLICATIONS INFORMATION The recommended applications schematic diagram is shown in Figure 15 The IDTP9030 operates with a 19Vpc 1V input The switching frequency varies from 110kHz to 205kHz At the 205kHz limit the duty cycle is also variable The power transfer is controlled via changes in switching frequency The base or TX side has a series resonance circuit made of a WPC Type A1 coil 24uH and a series resonant capacitor 100nF circuit driven by a half bridge inverter as shown in Figure 8 Revision 1 0 2 16 IDT gt 19V C 100 nF T Driver L P 24 uH A1 Coil T Figure 8 Half Bridge inverter TX Coil Driver Figure 8 shows the resonant tank configur
38. to demodulate and decode WPC compliant message packets sent by the mobile device to adjust the transferred power The IDTP9030 is an intelligent device that periodically pings the area surrounding the base station to detect a mobile device for charging while minimizing idle power Once the mobile device is detected and authenticated the IDTP9030 continuously monitors all communications from the mobile device and adjusts the transmitted power accordingly by varying the switching frequency of the half bridge inverter The IDTP9030 features a proprietary back channel communication mode which enables the device to communicate to IDT s wireless power receiver solutions e g IDTP9020 This feature enables additional layers of capabilities relative to standard WPC requirements This device also features optional security and encryptions to securely authenticate the receiver before transferring power This feature is available when an IDTP9020 is used for the receiver The device includes over temperature voltage current protection and a Foreign Object Detection FOD method to protect the base station and mobile device from overheating in the presence of a metallic foreign object It manages fault conditions associated with power transfer and controls status LEDs to indicate operating modes Typical Application Circuit ADAPTOR IN EGEREN SW WPC TX A1 3 100nF x vO PGND d 3x33nF 250V 1
39. ulation errors caused by ground potential differences The bootstrap pin requires a small capacitor connect a 47nF bootstrap capacitor rated above 25V between the BST pin and the LX pin The output sense connection to the feedback pins must be separated from any power trace Connect the output sense trace as close as possible to the load point to avoid additional load regulation errors Sensing through a high current load trace will degrade DC load regulation The power traces including PGND traces the SW or OUT traces and the VIN trace must be kept short direct and wide to allow large current flow The inductor connection to the SW or OUT pins must be as short as possible Use several via pads when routing between layers LDOs Input Capacitor The input capacitors must be located as physically close as possible to the power pin LDO2P5V_IN and power ground GND Ceramic capacitors are recommended for their higher current operation and small profile Also ceramic capacitors are inherently more capable than are tantalum capacitors to withstand input current surges from low impedance sources such as batteries used in portable devices Typically 10V or 16V rated capacitors are required The recommended external components are shown in Table 10 Output Capacitor For proper load voltage regulation and operational stability a Capacitor is required on the output of each LDO LDO2P5V and LDOSV The output capacitor must be placed
40. um Revision 1 0 2 25 IDTP9030 Product Datasheet results use large area PCB patterns with wide and heavy 2 oz copper traces placed on the top layer of the PCB 2 In cases where maximum heat dissipation is required use double sided copper planes connected with multiple vias 3 Thermal vias are needed to provide a thermal path to the inner and or bottom layers of the PCB to remove the heat generated by device power dissipation 4 Where possible increase the thermally conducting surface area s openly exposed to moving air so that heat can be removed by convection or forced air flow if available 5 Do not use solder mask or place silkscreen on the heat dissipating traces pads as they increase the net thermal resistance of the mounted IC package Power Dissipation Thermal Requirements The IDTP9030 is offered in a TQFN 48L package The maximum power dissipation capability is 2W limited by the des specified maximum operating junction temperature Tj of 125 C The junction temperature rises with the device power dissipation based on the package thermal resistance The package offers a typical thermal resistance junction to ambient Ou of 31 C W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section The techniques as noted in the PCB Layout section need to be followed when designing the printed circuit board layout as well as the placement of the IDTP
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