LAB 2 Design and Simulation of Sequential Logic Circuits
Contents
1. Pins All then click on the button List and move all found nodes from the left list to the right pane by clicking E then press OK to return to your vwf files 6 To set time characteristics of the simulation clock click on the clock signal CCLK to select it then do Edit gt gt Value gt gt Clock and in the Clock window put a Period of 20 ns a close approximation of the DE2 115 board clock and click OK Make sure you assign logic 1 to Reset by Forcing High 1 to allow your counter operates under the CCLK control At this point you can run a functional simulation The binary representation of the counter s states can be displayed by grouping Q2 Qo in a bus 7 To choose a grid of 20 ns do Edit gt gt Grid Size then put 20 ns for Period Run your simulation Processing gt Start simulation or click on the toolbar icon Pin and inspect the time diagram of your Simulation Report Simulation Waveforms window and verify if your synchronous counter follows the given counting sequence if it doesn t verify your equations and or debug your circuit NOTE Make sure that under the simulator is the Quartus II simulator Under Simulation menu go to Options and select Quartus II Simulator as the simulator Show the simulation to your instructor and capture it in a graphic format for your lab report copy to clipboard all the waveforms and paste them into a doc file to get a better visualization of your waveforms you m2. USB Blaster and click Close NOTE if the USB Blaster doesn t show up in the list of Currently Selected Hardware close the window and open it again You might have to repeat this process a few times 7 Inthe Programmer window check that the sof file is listed If it is not then click the Add File button on the left panel and look for the sof file under the output_files directory in the current working directory 8 Make sure Program Configure is checked in Click Start and verify your circuit Remember that a LED illuminates when its control input is 1 NOTE Once done you do not need to save the cdf file 9 Find experimentally the count table of your synchronous counter by pressing the KEY0 pushbutton until you rollover a full counting sequence Verify that the output of your synchronous counter matches the corresponding state diagram you were initially given 10 Demonstrate the operation of your circuit to your instructor References 1 DE2 115 User Manual Terasic Technologies Inc http www terasic com tw cgi bin page archive pl Lanquage English amp CategoryNo 165 amp No 502 amp PartNo 4 2013 EECS Fall 2015 9 CEG 2136 Lab 2 Page 10 of 10 APPENDIX A Switch debouncing In the past students were given an Altera UP2 board On those boards two push buttons MAX PBI and MAX PB2 provide active low signals and are pulled up through 10 KQ resistors as shown in Figure 1 When the contacts of any mechanic
3. Design and Simulation of Sequential Logic Circuits Synchronous Counters 1 Purpose This lab will enable students gain practice in the conversion of functional requirements into logic circuits and their implementation using on the Altera DE2 115 board The purpose of this lab is to introduce students to the design of sequential circuits based on Altera s Quartus development environment and their implementation and testing with an FPGA e Enter the design of synchronous counters using Quartus II graphics editor e Assign the input output pins and prepare the design for downloading and testing on the Altera DE2 115 board e Test the counter Display the counter outputs as binary values on LEDs Using an oscilloscope trace and record the waveforms at various flip flops 2 Requirements of the Lab The following results need to be submitted in your report The log of what you did The screen shots of all schematics and all waveform diagrams Compilation simulation and downloading messages if any Your test results 3 Equipment and Supplies Quartus II web edition Altera DE2 115 board with USB Blaster cable Power supply 12V 2A Probe Coaxial cable Wires Ribbon cable 4 References i Chapterl and 2 of the Text book Computer Systems Architecture Morris Mano 3rd Ed ii DE2 115 User Manual posted in the Documentation section under the Laboratories tab of CEG2136 Virtual Campus 5 PreLab For each of t
4. F10 GPIO 13 AF15 GPIO 15 AE21 GP10 17 AC22 GPIO 19 AF21 GPIOf21 AD22 GPIO 23 AD25 GPIiOf25 AE25 GPI0 27 AE24 GPIO 29 AF26 GPIO 31 AG23 GPIO 33 AH26 GPIO 35 AG26 Figure 2 GPIO 40 pin assignments a Select Assignments gt Assignment Editor under Category select ALL b Double click on the entry lt lt new gt gt in the column labeled To Press the binoculars to open the Node finder window then select i Filter gt Pins all then click on List ii Select highlight GCLK1 Q3 Q2 Q1 QO and RESET from the left column of Nodes Found and then click on gt to have all GCLK1 Q3 Q2 Q1 QO and RESET in the right Selected Nodes column The EECS Fall 2015 CEG 2136 Lab 2 Page6o of 10 content of the left column is entirely copied to the right without having to select them by simply hitting gt gt Click OK to close the Node Finder window c Compile your project with the assigned pins 4 Make sure the RUN PROG switch SW19 leftmost toggle switch is set to RUN 5 Select Tools gt Programmer in the Quartus II window From Hardware Settings in the Currently Selected Hardware box select USB Blaster and click Close NOTE if the USB Blaster doesn t show up in the list of Currently Selected Hardware close the window and open it again You might have to repeat this process a few times 6 Inthe Programmer window check that the sof file is listed If it is not then click the Add Fil
5. Project Wizard or you can proceed manually with the following design flow For each circuit designed above 3 bit modulo 6 and 4 bit BCD synchronous counters 1 Draw the circuit diagrams using the graphics editor of Quartus in a schematic file and save the corresponding bdf file Use the counter s signal names suggested in the block diagram Figure 1 a when editing the names of the pins of your circuit In the Project Navigator pane select the Files tab right click on your schematic file bdf and select Set as Top Level Entity Also save the schematics as a jpeg file or print it for inclusion in your report 2 To assign EP4CE115F29C7 to your project go to Assignments in the main menu select Device and in the window Settings chose Cyclone IV E for the Device Family and then from the list of Available Devices choose EP4CE115F29C7 EECS Fall 2015 2 CEG 2136 Lab 2 Page3 of 10 In the main menu select Processing gt Start compilation or click on the toolbar icon or press Ctrl L 3 To visualize the input and output signals of your counter clock reset flip flops outputs you have to create a University VWF file where you will catch the time diagram of these signals 4 To define the set of pins of your test circuit while in the vwf tab do select in the main menu Edit gt gt Insert gt gt Insert Node or Bus and click on Node Finder 5 In the option Filter of the popped up Node Finder window choose
6. al switch bang together they rebound a bit before settling causing bounce and generating an uncontrolled number of oscillations before coming to a still as shown in the time diagram of Figure 2 MAX PBI Figure 2 High to low switch transitory oscillations R1 i Debouncing is the process of removing those bounces and generating a single pulse preferably synchronous L with the system s clock as soon as a steady stable contact is made Figure 1 Pull up resistors To correct such issue they used the debounce tdf module that describes a debouncing circuit in a Hardware Description Language While implementing it on the CPLD it will generate a single pulse after a delay which is triggered by the rising edge of any oscillation of the switch MAX PBI i e at the end of pressing MAX PB1 where the delay duration has to be greater than the time between two parasitic pulses Figure 3 MAX_PB1 pulse Figure 3 Time diagram of single pulse generator debounce module You will learn more about switch debouncing in CEG3136 Computer Architecture II EECS Fall 2015 10
7. ay want to change the time base in your vwf file by choosing in Edit End Time a Time EECS Fall 2015 3 CEG 2136 Lab 2 Page4 of 10 0 5 us Show the design and demonstrate the simulations to your TA PART II Testing experiment Two different speed approaches can be considered to experimentally test the counters designed above II 1 Automatic free running highest speed by connecting CCLK to the DE2 115 board general clock GCLK1 generated on board and visualizing the flip flops outputs with an oscilloscope II 2 Manual control by deriving CCLK from a push button and displaying the flip flops outputs on LEDs as shown below block diagram of Figure 2 II 1 Automatic free running counter In this mode you can visualize the signals of your real circuit by employing an oscilloscope The real signals should be similar to the waveforms you obtained by simulating your circuit in PART I 1 Return to your bdf file and from File gt gt Create Update gt gt Create Symbol Files For Current File you can create a symbol bsf file for your synchronous counter 2 Now you can create a test circuit for the counter with the Quartus graphic editor testI bdf Save the file and set the project to the current file with Set as Top Level Entity The counter Symbol created above can be inserted into your schematics by going Edit gt gt Insert Symbol and looking for it in the Project directory of the Symbol Libraries The clock i
8. counter s clock CCLK from a push button KEY0 and displaying the flip flops outputs on LEDs as shown below block diagram of Figure 3 EECS Fall 2015 VCC KEY0 gt CCLK Q3 Q2 gt Reset Q1 COUNTER Q0 Figure 3 COUNTER test circuit The DE2 115 board provides four push button switches as shown in Figure 3 Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 4 The four outputs called KEY0 KEY1 KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when depressed Since the push button switches are debounced they are appropriate for using as clock or reset inputs in a circuit 1 In the past student were provided with FPGA boards where the push buttons where mechanical switches Therefore they had to add a debouncer in order to correct the oscillation encountered while pushing on the mechanical switches For more information see Appendix A VCC3P3 KEYS 6S O 0 KEY3 KEY2 KEYS gis KEY2 O Q m na AERA KEY1 74HC245 KEY1 j 6S ma Cyclone IV O Oo KEYO M23 KEYO O Oo Figure 4 Block diagram of 4 push button on DE2 115 boards CEG 2136 Lab 2 Page8 of 10 ea depressed pem released Before Debouncing LUUN UUL Schmitt Trigger Debounced tem Figure 5 Debouncing mec
9. e button on the left panel and look for the sof file under the output_files directory in the current working directory 7 Make sure Program Configure is checked in Click Start and verify your circuit Remember that a LED illuminates when its control input is 1 NOTE Once done you do not need to save the cdf file 8 Use an oscilloscope to visualize the clock and the flip flops outputs Connect the probe of oscilloscope channel to one of your ribbon cable pins that maps to your counter pin assignments one by one and use the coaxial cable to output the clock signal Draw these time diagrams Measure the rising and falling times of your signals Hint Under Measure menu on the oscilloscope select the Meas push button Make sure channel 2 is selected Select the Type on screen menu and search for Snapshot all option When select the Add measurement option it will display all the necessary values you will need NOTE How to use the oscilloscope When turning on the oscilloscope wait a few minutes it takes time to boot up Once the oscilloscope is powered on select channel 2 channel on which the probe is on and select the Probe menu on screen use the push buttons below to select the Probe menu Once Probe menu is selected change the probe Ratio to 10 1V use the control knob under the green arrow named Push to select EECS Fall 2015 6 CEG 2136 Lab 2 Page7 of 10 H 2 Manual control For this mode you have to derive the
10. hanism Schmitt Trigger 1 Return to your bdf file and from File gt gt Create Update gt gt Create Symbol Files For Current File you can create a symbol bsf file for your synchronous counter Table 3 Manual Control Pin Assignment Value Pin assignment Component CCLK PIN_M23 KEY0 Q3 PIN_E24 LEDG3 Q2 PIN_E25 LEDG2 QI PIN_E22 LEDG1 QO PIN_E21 LEDGO RESET PIN_AB28 SWo 2 Assign the EPM7128SLC84 7 device number to your design Assign Device and then assign pin numbers as shown in Table 3 Select Assignments gt Assignment Editor under Category select ALL 3 Double click on the entry lt lt new gt gt in the column labeled To Press the binoculars to open the Node finder window then select a Filter gt Pins all then click on List b Select highlight CCLK Q3 Q2 Q1 QO and RESET from the left column of Nodes Found and then click on gt to have all CCLK Q3 Q2 Q1 QO and RESET in the right Selected Nodes column The content of the left column is entirely copied to the right without having to select them by simply hitting gt gt Click OK to close the Node Finder window 4 Compile your project with the assigned pins EECS Fall 2015 8 CEG 2136 Lab 2 Page9 of 10 5 Make sure the RUN PROG switch SW19 leftmost toggle switch is set to RUN 6 Select Tools gt Programmer in the Quartus II window From Hardware Settings in the Currently Selected Hardware box select
11. he following counters a and b e Draw the state diagram and derive the excitation table for all the flip flops involved in the counter the excitation table for counter a is already given below e Derive and simplify the Boolean expression of every flip flop input using Karnaugh maps CEG 2136 Lab 2 Page2 of 10 a 3 bit synchronous modulo 6 counter Block diagram in Fig 1 a has to observe the following counting sequence 000 gt 010 gt 110 gt 011 gt 101 gt 100 gt 000 This counter is to be implemented with JK flip flops which have active low asynchronous Reset inputs CLRN the flip flops clock inputs CLK are connected all together to CCLK counter clock Present Next Synchronous State State Inputs msb Isb msb Isb msb Isb Q2Q1Q0 Q2Q1Qo J2K2 J K JoKo 000 010 0x 1x 0x 001 XXX XX XX XX oro 110 010 110 Ix x0 0x 011 101 lx xl x 0 100 000 xl 0x 0x 101 100 x0 0x x a 110 011 x1 x 0 1x 111 XXX XX XX XX Figure 1 a Block diagram and Table 1 The Excitation Table for the JK b State Diagram of a Modulo 6 counter flip flops Modulo 6 counter b 4 bit synchronous BCD counter 0000 gt 0001 gt 0010 gt 0011 gt 0100 gt 0101 gt 0110 gt 0111 gt 1000 gt 1001 gt 0000 gt PART I Design and simulation To capture your design in the Altera s development environment you can use Quartus New
12. nput of the counter clk has to be connected to the system clock GCLK1 from the on board oscillator of 50MHz that is directly connected to the FPGA PIN Y2 Remember to compile your file before assigning the pins 3 Assign the EP4CE115F29C7 device number to your design Assign Device and then assign pin numbers as shown in Table 2 EECS Fall 2015 4 CEG 2136 Lab 2 Page5 of 10 Table 2 Free running Pin Assignment Value Pin assignment Component GCLK PIN _Y2 50MHz oscillator Q3 PIN Y17 Oscilloscope output Q2 PIN_AB21 Oscilloscope output Ql PIN AC15 Oscilloscope output QO PIN AB22 Oscilloscope output RESET PIN AB28 SWo CLKOUT PIN AE23 SMA CLKOUT In order to have the SOMHz clock as output create a CLKOUT signal and assign its value to GCLK You can select a different output pin but following the GPIO pin assignment below When viewing the oscilloscope output you will need to connect a ground to your probe to close the loop Select pin right 15 from top as your ground AB22 GPIO O AB21 GPIO 2 AC21 GPIO 4 AD21 GPIO G ADI5 GPIO 8 5y AC19 GPIO 10 AD19 GP10 12 AF24 GP10 14 AF25 GPIO 16 AE22 GPIO 18 AF22 GPIO 20 AG25 GP10 22 AH25 GPIO 24 3 3V AG22 GPIO 26 AN22 GPIO 28 AE20 GP10130 AF20 GPIO 32 AH23 GPIO GPIO JPS GPIO 11 A
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