78Q2120C09 10/100BASE-TX Transceiver MII Evaluation Board
Contents
1. vec e a vec Note This demo 0603 0603 0603 0603 Pun END lend END toc ND board schematic is 601 104 0603 0603 oem gr only applicable for 7 0603 the 78Q2120C09 iaj revision 68 ohm Impedance Traces 459 428 499 499 1 1 28 888888 100 ohm Diff Impedance Traces 196 1 0603 0603 TXCLK R5 100 0603 27 0603 0603 TXCLK TXER 26 TXCLK 61 TXER TAS 25 TXER HiL LE TXOP TXD3 1553 32 TXD3 TXON TXON TXD2 TXD1 30_ TXD2 52 RXIP TXD1 20 TXD1 RXIP 4 XN RXIP TXDO TXDO RXIN 4 RXIN RXCLK Re 100 0603 RC 24 Ac RXER R7 100 0603 RE 25 eee 39 RPTR RAER RXD3 RB 100 0603 R3 39 RXD2 100 0603 R2 20 34 RXD2 RXD2 CRS CRS vec BND RXD1 Rit 100 0803 Ri 2i 2 ERS 33 CoL D RXDO R13 100 0603 RO 22 PADA nup 28 125 Use 33 ohm for maximum drive RXDV R15 LEDL tok TEDL LEDL 0603 MDC 18 655 LEDTX LEDTX MDIO MDIO LEDRX 035 EBERT LEDRX ST al LEDCOL 27 DAI LEDCOL RST RST LEDEDX TEDOS LEDFD PWRDN 7 LEDBTX Dag LEDIO 1ED100 PWRDN LEDBT LED10 ANEGA 47 ANEGA R16 vec o 3 TECH 44 35 TECHA 25 TECH2 INTR 2 a vec 46 ND 1 cons R18 102. DESCRIPTION The 78Q2120C09 DB is a design example for 10 100BASE TX Mbit second Fast Ethernet Interface adaptor The 78Q2120C09 transceiver provides the network physical interface and MII Medium Independent Interface interface Teridian Semiconductors 78Q2120C09 is an auto sensing auto switching 10 100BASE TX Fast Ethernet transceiver with full duplex operation capability The device interfaces directly to the IEEE 802 3u port Full featured management functions are included along with an extended register set A five bit configurable PHY address is provided for multiple PHY architectures The 78Q2120C09 interfaces to CAT5 UTP cable via a 1 1 transformer The transceiver s transmitter includes on chip the pulse shaper and low power line driver The receiver incorporates a sophisticated combination of real time adaptive equalization an adaptive DC offset adjustment circuit and baseline wander correction Smart squelch circuitry further improves the receivers noise rejection Full featured auto negotiation or parallel detect modes are supported Using 0 18um CMOS technology the 78Q2120C09 operates at 3 3V Intelligent power management and power down modes minimize power consumption The demo board requires operation with a 3 3V power supply Design Kit contains 78Q2120C09 MII Demo Board Demo Board Parts List P C B Gerber Files Demo Board schematic 78Q2120C09 Data Sheet 2007
3. Semiconductor 78Q2120C09 MII Adapter and Lancast Fast Ethernet Adapter were attached to the Netcom s Ports A amp B respectively Twisted pair Category 5 General Cable P N 459360 was used to connect the two transceivers 100 Mbps performance was measured using cable lengths of both 12 inches and 115 meters 10 Mbps performance was evaluated using 100 meters of Category 3 cable The Netcom was configured to use the Baseline Wander Packet file Packet length was 1500 bytes All transformers listed above met or exceeded IEEE s 802 3 Bit Error Rate requirements of 10 2007 Teridian Semiconductor Corporation Proprietary and Confidential 6 Rev 1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP MII Evaluation Board Design Kit PCB Layout Considerations The following recommendations enhance the 7802120 09 performance while minimizing EMC emissions Oo 0509 11 13 14 15 16 The transformer to transceiver signal traces must be 100 ohm differential transmission lines Place the termination network components near the input data pins of the transceiver or transformer Make all differential signal pairs short and of the same length Decouple the transceiver thoroughly with 0 01 yf and 0 1 capacitors Locate these decoupling capacitors as close as possible to the respective transceiver VCC and GND pins All decoupling capacitor and transceiver VCC and GND connections should tie immediately to a VCC or GND
4. f m 4 RXIN lt RD RX 5 i 6 227 eis 25 py vec o 4 Torta pu 7 10PF 10PF RN c15 0603 0603 01 SMTIG 0503 zu ND ND 0603 o MTHOLE ND 0 01 0503 0603 RJAS Optional ESD noise suppression 1 5KV 1812 GND CONNECT CGND TO LK MOUNTING BRACKET D1 gt LEDL 1 2244 2 LLED LED vec TX D2 LEDTX LEDTX 1 1 21 2 TLED sii LED 54K Use 1 5K 10K RX 68 ohm Impedance Traces lt 0603 D3 1 LEDRX LEDRX 1 2 RLEB MDIO lt gt B VOD 2 LED vec i RXD3 A RXD3 4 COL E D RXD2 D4 R42 680 0603 EXT 1 RXD1 5 LEDCOL 1 1 2 CLED R43 680 0603 1 RXDO 8 LEDCOL We R44 680 0603 RXDV LED R45 680 0603 Run RXCLK 8 FD 680 0603 E 5 1 RXER 40 05 R47 680 0603 i TXER 10 LEDFD 1 1 4 2 FLED 680 0603 fa 13 LED Ks TXDO 100 TDO TXDi n Y 06 5 TXD2 15 100 gt LED190 1 2214 2__HLED TXD3 108 17 LED GoL CRS 18 CRS 19 10 or a LED10 1 2 SLED LED10 7 M 2 i LED INTERFACE 24 25 2 43 3V CON3 VEXT 28 we spay 29 4 30 VEXT VIN 30 32 MH3 MH4 Mox e E MTHOLE MTHOLE MTHOLE vec 0 1 10 35 0603 0805 36 37 E E of e 40 78Q2120C09 Evaluation Board Schematic Line Interface FCN 238P040 G F FUJITSU 2007 Teridian Semiconductor Corporation Proprietary and Confidential Rev 1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP Mil Evaluatio
5. 09 SEMICONDUCTOR CORP Mil Evaluation Board Design Kit 200 lt gt VCC Layer 2007 Teridian Semiconductor Corporation Proprietary and Confidential 13 Rev 1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP Mil Evaluation Board Design Kit 200 lt gt Ground Layer 2007 Teridian Semiconductor Corporation Proprietary and Confidential 14 Rev 1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP MII Evaluation Board Design Kit Bottom Layer 2007 Teridian Semiconductor Corporation Proprietary and Confidential 15 Rev 1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP MII Evaluation Board Design Kit 3588425 iB 28 28 o Bottom Silkscreen No responsibility is assumed by TERIDIAN SEMICONDUCTOR CORPORATION for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use No license is granted under any patents patent rights or trademarks of Teridian Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice Accordingly the reader is cautioned to verify that the data sheet is current before placing orders Teridian Semiconductor Corporation 6440 Oak Canyon Irvine CA 92618 5201 714 508 8800 FAX 714 508 8877 http www teridian com 2007 Teridian Semiconductor Corporation Propriet
6. K 0603 PCSBP 64 R19 10K 0603 ai 150 Pals NTR R20 10K 0603 ISODEF Ac Ro ae neo 8 R21 10K 0803 51 R22 10K 0603 1 R23 10K 0603 PHYAD4 AD cui s CKIN R25 10K 0603 1 18 EHYADA iM R26 10K 0800 1 PHYAD2 14 EHYADS xnp 39 XTLP ND 15 58 XTLN PHYADU Te PHYAD1 XTLN PHYADO i swt Ni ia 3oPF 50ppm 0603 0603 olleelle ND ND lt gt ND 78Q2120C09 CGT TSC LOFP64 vec 827 10K 0603 4 R28 10K 0603 i R29 10K 0803 T R30 10K 0603 i R31 10 0603 1 R32 10K 0803 1 R33 10K 0803 i R34 10K 0603 sw2 78Q2120C09 Evaluation Board Schematic MII Interface 2007 Teridian Semiconductor Corporation Proprietary and Confidential Rev 1 2 SEMICONDUCTOR CORP 78Q2120C09 Mil Evaluation Board Design Kit vec 6 C13 C14 0 1 0 01 0603 0603 100 ohm Diff Impedance Traces ND ND 100 ohm Diff is BD Impedance Traces R3 KZ 0603 RSS E TDCT TXCT 75 75 TXON 3 14 i J2 TRON lbs Reg 0603 0603 NC NC4 1 RXIP NC2 NC3 2 RXP 7 RX Fag ZR TA 3 RXIN g RXCT 5
7. OFF used PCSBP ON PWRDN ON Switch SW1 positions ANEGA 2 set the line interface technology capabilities Refer to the data sheet for a complete description For full Auto Negotiation capabilities set ANEGA and 2 to OFF Use With the Netcom Smart Bits The Netcom expects to be the master and defaults to 100BASE TX Half Duplex operation To allow Fast Ether Windows to reconfigure the 78Q2120C09 s control register MRO bits set ANEGA and 2 all to OFF If the 78Q2120C09 s technology pins set to anything else the 78Q2120C09 will disable some modes and prevent the Netcom from reconfiguring the 78Q2120C09 and data errors may be observed After initialization the 78Q2120C09 defaults to 100BASE TX Full Duplex operation When connected to another fully capable transceiver the transceivers will be in full duplex mode The default configuration of the Netcom is 100BASE TX Half Duplex operation If data transfers were to commence the Netcom would display Collision errors because it does not automatically read the transceivers and reconfigure If a transceiver is used which defaults to 100BASE TX Half Duplex operation the 78Q2120C09 will adjust itself for half duplex operation assuming the 7802120 09 is setup for the proper technologies To establish proper operation between the 78Q2120C09 and the Netcom click on the Options button followed by selecting Full Duplex MII Repeat select
8. Teridian Semiconductor Corporation Proprietary and Confidential 78Q2120C09 10 100BASE TX Transceiver MII Evaluation Board Design Kit UM 78Q2120C09 v1 2 iiit 2007 100Base TX Interface RJ45 Pin Assignment Pin Signal Pin Signal 1 TX 5 N C 2 TX 6 RX 3 RX 7 N C 4 N C 8 N C Mil Medium Independent Interface Pin Assignment 40 Pin Male Subminiature D 0 050 Pin Signal Pin Signal 1 3 3V 21 3 3V 2 MDIO 22 COMMON 3 MDC 23 COMMON 4 RXD3 24 COMMON 5 RXD2 25 COMMON 6 RXD1 26 COMMON 7 RXDO 27 COMMON 8 RXDV 28 COMMON 9 RXCLK 29 COMMON 10 RXER 30 COMMON 11 TXER 31 COMMON 12 TXCLK 32 COMMON 13 TXEN 33 COMMON 14 TXDO 34 COMMON 15 TXD1 35 COMMON 16 TXD2 36 COMMON 17 TXD3 37 COMMON 18 COL 38 COMMON 19 CRS 39 COMMON 20 3 3V 40 3 3V Rev 1 2 78Q2120C09 10 100BASE TX Transceiver Mil Evaluation Board Design Kit UM 78Q2120C09 v1 2 April 2007 Mil ADAPTOR WITH 78Q2120C09 Switch Positions The OFF switch position sets a logic level 1 and conversely the ON position sets a logic level 0 Some DIP switch markings are different ON equals CLOSED OFF equals OPEN For normal operation switch SW2 should be set as follows ISO ON ISODEF ON TEST ON PAD4 0 PHY Address 0 the 78Q2120C09 responds all accesses PHY Address non zero the 78Q2120C09 responds only to its unique address For normal operation the following SW1 switches should be set as follows N U
9. ary and Confidential 16 Rev_1 2
10. h smaller than the GND plane If multiple transceivers are used provide partitions in the VCC and GND planes between the analog sections Maintain the partition from the transformer up to the transceiver s analog interface Do not cross these partitions with signal traces in particular any digital signals from adjacent transceivers Add series resistors on all transceiver MII outputs to minimize digital output driver peak currents Minimize the use of vias when routing the analog signal traces Isolate the crystal and its capacitors from the analog signals with a guard ring The crystal compensation capacitor value C11 amp C12 must be selected to trim the oscillator s frequency to 25 0000 MHz 50ppm The optimum value will be layout dependent A mere 4pf can shift the 25MHz 100Hz The 25 0000 MHz 50ppm is specified by the IEEE Note System vendors need to select the proper crystal according to their applications such as operating environment product lifetime and etc since crystal aging operating temperature and other factors can affect the crystal frequency tolerance 2007 Teridian Semiconductor Corporation Proprietary and Confidential 7 1 2 SEMICONDUCTOR CORP 78Q2120C09 Mil Evaluation Board Design Kit
11. ing Full Duplex MII twice to ensure that everything is configured identically The 78Q2120C09 be configured for half duplex operation ANEGA ON and 2 ON OFF ON to minimize incompatibilities with other transceivers and the Netcom 2007 Teridian Semiconductor Corporation Proprietary and Confidential 2 Rev 1 2 4 jTERIDIAN 78Q2120C09 7 SEMICONDUCTOR MII Evaluation Board Design Kit 10 100Mbps Transformer Selection The line interface for the 7802120 09 requires a pair of 1 1 isolation transformers Integrated common mode chokes are recommended for satisfying FCC radiated EMI requirements Additional filtering is not required with the 78Q2120C09 due to internal waveform shaping circuitry The line transformer characteristics are outlined below ______ Condition 1CT 1CT Open Circuit Inductance 350 uH min 10 mV 10 KHz See Note 1 Leakage Inductance 0 40 pH max 1 Mhz min po D C Resistance ___ __ HiPOT ___ ___ __ _ O Note 1 The receive line transformers Open Circuit Inductance can be as low as 100 pH for the 7802120 09 The 78Q2120C09 incorporates baseline wander correction circuitry which allows the receiver to track the incoming data signal when there is excessive transformer droop For Commercial Temperature 0 C 70 C Teridian Semiconductor has performed line testing with the following transformer
12. luation Board Design Kit Commercial Temperature Connectors continued LED color Compatible L R Vendor Part number Shielding Lead free Footprints MIC24010 5101T LF3 Down MIC24010 5104T LF3 Down MIC24011 0101T Down MIC24011 0101T LF3 Down MIC24011 0101W LF3 Down MIC24011 0104T Down MIC24012 5101T LF3 Down Wurth Midcom MIC24012 5204T LF3 Down MIC24013 5104T Down MIC24018 5101T LF3 Down MIC24019 0101T Down MIC24111 0101T Up MIC24111 0101T LF3 Up MIC24412 0128T LF3 Up MIC24F11 0101T LF3 Up gt co O 70004 10012 LJ1011 51 10021 51 60002 51 40139 5 60001 51 50170 51 50170 51 50177 51 50177 51 50193 51 50193 51 50196 5016 Up Nes G G No Yes F TLA 6T704 Down hasra No NA ves a Yes TLA 6T707 Down N A Yes Yes 2007 Teridian Semiconductor Corporation Proprietary and Confidential 5 Rev 1 2 4 jTERIDIAN 78Q2120C09 7 SEMICONDUCTOR MII Evaluation Board Design Kit Notes 1 The letters stand for different footprint drawings 2 Lower case is for the tab down version Upper case is for tab up version 3 The compatible connectors are labeled with the same letter The above evaluations were performed using Netcom s Smart Bits Fast Ethernet Analyzer The Teridian
13. n Board Design Kit 200 78Q2120C09 MII Demo Board Parts List REFERENCE NUMBER PARTNUMBER MANUFACTURER 01 10 100Mbps LAN 78Q2120C09 CGT LOFP64 5 cme ee 2 swisw2 QpPSWmTCH8POS S amp A4 6 R35 R36 R37 R38 R39R40 JRES75 0003 7 R amp ReRZRBR9SRITRIS RES 100 0603 7 15 16 18 19 20 21 22 RES 10K CC0603 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 l Do R1 R2 R3 R4 RES 499 157 CCO003 19 020 0603 Optional 2 000603 5 4 7 66063 1608 5 1 1042 1 2 3 4 6 7 13 15 17 CAP CER O IUF 7 1608 5 1 1042 DK DK c16 CAPCEROO1UF 15KV 7 182 8 1 1 1 1 CAP CER TOUF 1 0 V ___________ 0805 UJITSU 7 9 gt 2007 Teridian Semiconductor Corporation Proprietary and Confidential 10 Rev 1 2 4 FTERIDIAN 78Q2120C09 7 SEMICONDUCTOR CORP MII Evaluation Board Design Kit 7H02120C 84 MII INTERFACE CARD DEMO BOARD REV B Top Silkscreen 2007 Teridian Semiconductor Corporation Proprietary and Confidential 11 Rev_1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP MII Evaluation Board Design Kit Top Layer 2007 Teridian Semiconductor Corporation Proprietary and Confidential 12 Rev 1 2 4 jTERIDIAN 78Q2120C
14. plane via with minimum trace inductance Total decoupling capacitance should be greater than the load capacitance that the digital output drivers must drive Use low inductance ceramic surface mount decoupling capacitors Use a multi layer PCB with the inner layers dedicated to GND and VCC A single VCC and GND plane is recommended for optimum performance The lowest possible series impedance is required between the analog and digital VCC and GND pins respectively of the transceiver The outer layers of a 4 layer PCB are to be used for signal routing Place the highest speed signals on the layer adjacent to the GND plane Physically separate the analog signals from the digital signals by placing them on opposite layers or routing them away from each other Additional component and solder side ground layers may be added for maximum EMC containment The GND plane should extend out to the transceiver side of the transformer Remove the VCC and GND planes from the line side of the transformer to the RJ 45 connector Do not allow the chassis ground plane to cross over the transceiver GND plane Minimum separation must accommodate over 1 5KV Provide onboard termination of the unused signal pairs in the CAT 5 cable Use a shielded RJ 45 connector with its case stakes soldered to the chassis ground Locate the transformer adjacent to the RJ 45 to minimize the shunt capacitance to the line Minimize RF current fringing by making the VCC plane 0 10 inc
15. s and found their performance acceptable with the 7802120 09 Manufacturer Part Number TDK TLA 6T103 Bel Fuse 5558 5999 46 TG22 3506ND Pulse PE 68515 Valor ST6118 YCL 20PMT04 The following transformers are low profile packages 0 100 in 2 5 mm or less TDK TLA 6T118 Halo TG110 S050 PCA EPF8023G 2007 Teridian Semiconductor Corporation Proprietary and Confidential 3 Rev_1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP Mil Evaluation Board Design Kit The following devices integrate the transformers RJ45 connector LEDs and termination resistors Commercial Temperature Connectors LED color L R Compatible Vendor Part number Cok Footprints Shielding Lead free J0011D21 J0011D21NL J0011D21B J0011D21BNL J0011D21E J0011D21ENL J0011D01 J0011D01NL J0011D01B J0011D01BNL J0012D21 J0012D21NL J1011F01P J1011F01PNL J1011F21P J1011F21PNL gt o o o0 HFJ11 2450EURL Down No N A No Yes HFJ11 2450EU L11RL Down Yes G G No Yes HFJ11 2450ERL Down No N A Yes Yes Halo HFJ11 2450E L11RL Down Yes G G Yes Yes HFJT1 S003E L11RL Yes G G Yes Yes HFJT1 S003 L11RL _ Yes G G Yes Yes HFJT1 S003 Up No N A Yes Yes 2007 Teridian Semiconductor Corporation Proprietary and Confidential 4 Rev 1 2 4 jTERIDIAN 78Q2120C09 SEMICONDUCTOR CORP Mil Eva
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