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R8C/M11A Group, R8C/M12A Group User`s Manual

1. Register Name Register Name 00180h Comparator B Control Register WCMPR 001COh Address Match Interrupt Register 0 AIADROL 119 00181h Comparator B1 Interrupt Control Register WCBI1INTR 001Cth AIADROM 00182h Comparator B3 Interrupt Control Register WCBS3INTR 001C2h AIADROH 00183h 001C3h Address Match Interrupt Enable Register 0 AIENO 119 00184h 001C4h Address Match Interrupt Register 1 AIADRIL 119 00185h 001C5h AIADR1M 00186h 001C6h AIADR1H 00187h 001C7h Address Match Interrupt Enable Register 1 AIEN1 119 00188h 001C8h 00189h 001C9h 0018Ah 001CAh 0018Bh 001CBh 0018Ch 001CCh 0018Dh 001CDh 0018Eh 001CEh 0018Fh 001CFh 00190h 001D0h 00191h 001D1h 00192h 001D2h 00193h 001D3h 00194h 001D4h 00195h 001D5h 00196h 001D6h 00197h 001D7h 00198h 001D8h 00199h 001D9h 0019Ah 001DAh 0019Bh 001DBh 0019Ch 001DCh 0019Dh 001DDh 0019Eh 001DEh 0019Fh 001DFh 001A0h 001E0h 001A1h 001E1h 001A2h 001E2h 001A3h 001E3h 001A4h 001E4h 001A5h 001E5h 001A6h 001E6h 001A7h 001E7h 001A8h 001E8h 001A9h Flash Memory Status Register 001E9h 001AAh Flash Memory Control Register 0 001EAh 001ABh Flash Memory Control Register 1 001EBh 001ACh Flash Memory Control Register 2 001ECh 001ADh Flash Memory Refresh Control Register 001EDh 001AEh 001EEh 001AFh 001EFh 001B0h 001FOh 001B1h 001F1h 001B2h 001F2h 001B3h 001F3h 001B4h 001F4h 001B5h 001F5h 001B6h 001F6h 001B7h 001F7
2. NOTE F 1 DIMENSIONS 1 Nom AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET es pes sees n a GC Ir Index mark Terminal cross section H H l a Ni Pd Au plating Reference Dimension in Millimeters a H Symbol 7 i Min Nom Max 7 D D 5 00 5 30 E E 4 40 Zz bp 18 L A el Au 0 03 0 07 0 10 A 1 10 bp 0 15 0 20 0 25 by 5 H c 0 10 0 15 0 20 A OD lt i ae J d o o 8 lt L He 6 20 6 40 6 60 gt e 0 65 Cyle Detail F X T T013 y 0 10 Z 0 83 L 0 4 0 5 0 6 Li 1 0 JEITA Package Code RENESAS Code Previous Code MASS Typ P DIP14 6 35x19 3 2 54 PRDP0014AC A 14P4X A 0 94g 14 8 1 i NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH
3. Hardware reset Power on Power on reset reset circuit Voltage monitor 0 Voltage reset detection circuit Watchdog timer reset Watchdog timer CPU SFRs and UO ports Software reset Note 1 The CWR bit in the RSTFR register is set to 0 cold start up after power on or voltage monitor 0 reset This bit remains unchanged after a hardware reset software reset or watchdog timer reset Figure 6 1 Reset Circuit Block Diagram RO1UHO050EJ0200 Rev 2 00 RENESAS Page 36 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 2 Registers Table 6 2 lists the Register Configuration for Reset Table 6 2 Register Configuration for Reset Processor Mode Register 0 00010h Register Name After Reset Address Access Size Reset Source Determination Register 0005Fh Option Function Select Register 2 OFFDBh Option Function Select Register OFFFFh Notes 1 2 The value of the RSTFR register after a reset differs depending on the reset source For details see 6 2 2 Reset Source Determination Register RSTFR The OFS2 register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS2 register Erasure of the block including the OFS2 register causes the OFS2 register to be set to FFh When blank products are shipped the OFS2 register is set to FFh It is set to the written value af
4. TI Transmit buffer empty flag RE Set to 1 to enable reception RI Receive complete flag Select the UARTO transmit interrupt source to be transmit buffer empty or transmit complete Select continuous receive mode from disabled or enabled 1 The write value must be 0 for all bits not listed in this table RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 287 of 426 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 1 1 Operation Examples Transmit timing example internal clock selected TC la Transfer clock Li U TE bit in H UOC1 register 1 U U 1 Data is set in UOTB register TI bit in U0C1 register H 9 wW From UOTB register to UARTO transmit register TEUK Stopped because TE bit is 0 TXDO TXEPT bit in UOCO register UOTIF bit in UOIR register Set to 0 by a program The above diagram applies for the following settings TC TCLK 2 n 1 fi e CKDIR bit in UOMR register 0 internal clock fi Frequency of UOBRG count source f1 f8 or 32 CKPOL bit in UOCO register 0 transmit data is output on the falling n Value set in UOBRG register edge and receive data is input on the rising edge of the transfer clock e UOIRS bit in UOC1 register 0 transmit buffer is empty e Receive timing example external clock selected RE bit in U0C1 register TE bit in U0C1 register i Dummy data is set in UOTB
5. 21 10 Notes on Serial Interface UARTO Regardless of clock synchronous I O mode or clock asynchronous I O mode read the UORB register in 16 bit units When the UORBH register is read bits FER and PER in the UORB register are set to 0 no framing error no parity error Also the RI bit in the UOC1 register is set to 0 the UORB register empty To check receive errors use the data read from the UORB register e Program example to read the receive buffer register MOV W 0086H RO Read the UORB register When the transfer data is 9 bits long in clock asynchronous I O mode write to the UOTB register in the order UOTBH first and then UOTBL in 8 bit units e Program example to write to the transmit buffer register MOV B XXH 0083H Write to the UOTBH register MOV B XXH 0082H Write to the UOTBL register Do not set the MSTUART bit in the MSTCR register to 1 standby during communication When setting the module to the standby state confirm whether communication has completed After communication has completed set bits TE and RE in the UOC1 register to 0 communication disabled before setting the module to the standby state After the module standby state is cleared the initial settings for communication must be set again RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 403 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 11 Notes on A D Converter 21 11 1 A D Converter Standby Setting The A D convert
6. Conditions for entering erase program suspend e Set bits FMR20 to FMR21 in the FMR2 register to 1 by a program e Set bits FMR20 and FMR22 in the FMR2 register to 1 and the enabled maskable interrupt is generated Set bits FMR20 and FMR22 in the FMRz2 register to 1 and the enabled maskable interrupt is generated CPU clock Max 20 MHz Max 20 MHz RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 329 of 426 R8C M11A Group R8C M12A Group 19 Flash Memory 19 5 Registers CPU Rewrite Mode Table 19 6 lists the Flash Memory Register Configuration Table 19 6 Flash Memory Register Configuration After Reset Address Access Size Register Name Flash Memory Status Register 10000000b 001A9h Flash Memory Control Register 0 00h 001AAh Flash Memory Control Register 1 00h 001ABh Flash Memory Control Register 2 00h 001ACh Flash Memory Refresh Control Register 19 5 1 Flash Memory Status Register FST Address 001A9h Bit After Reset RDYSTI b 7 Bit Name Flash ready status interrupt request flag 1 4 00h 001ADh 7 b6 b5 b4 b3 b2 b1 b Symbol Function No flash ready status interrupt requested Flash ready status interrupt requested BSYAEI Flash access error interrupt request flag 2 4 No flash access error interrupt requested Flash access error interrupt requested FST2 LBDATA monitor flag
7. TREYR 00136h TRECR 00137h TRECSR 00138h TREADJ 00139h TREIFR 0013Ah TREIER 0013Bh TREAMN 0013Ch TREAHR 0013Dh TREAWK 0013Eh TREPRC 0013Fh Registers added UiMR 00190h U1BRG 00191h U1TBL 00192h U1TBH 00193h U1C0 00194h U1C1 00195h U1RBL 00196h U1RBH 00197h U1iIR 00198h Registers added IRCR 0019Ch Register added IICCR 00160h SSBR 00161h SITDR 00162h SIRDR 00164h SICR1 00166h SICR2 00167h SIMR1 00168h SIER 00169h SISR 0016Ah SIMR2 0016Bh Registers added R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 424 of 426 R8C M11A Group R8C M12A Group Index Index A ADCOND M ADi i 0 or 1 ADICSR 0 ADINSEL ADMOD S AIADRi i 0 or 1 D AIENi i Dor B e E C E EXCKGR eonia dinates F EMS ed FREER veecccccsssssssecorsecsecsesscsassessesarsecsrsarsacsecersarsacsesersaveaseveees 338 S e el EE 78 T H blei ET 28 TRBIOC n TRBIR TRBMR 1 TRBOCR ILVLi i 0 OF 2 to E ENEE 115 TRBPR Geerteertetbeg eet TE E EE dee Ee ed be 112 TRBPRE cocccccccccccccccccccccccccccececceeeeeceseseseeeeesceseeseseeeeeseeseeesses TRBSC D D TRGAD COB degt
8. Time from Wait Mode to First Instruction Execution after Exit after WAITM Bit in RO1UH0050EJ0200 Rev 2 00 May 18 2012 RENESAS Page 101 of 426 R8C M11A Group R8C M12A Group 10 Power Control 10 4 Stop Mode All oscillations are stopped in stop mode Thus the CPU clock and the peripheral function clock are stopped and the CPU and the peripheral functions that operate using these clocks are stopped However when the low speed on chip oscillator is selected as the count source for the watchdog timer in count source protection mode or when bits WDTC7 to WDTC6 in the WDTC register are set to 11b division of low speed on chip oscillator by 16 the low speed on chip oscillator oscillates Power consumption is lowest compared to other modes When the voltage applied to the VCC pin is VRAM or above the content of the internal RAM is retained 10 4 1 Entering Stop Mode Stop mode is entered when the STPM bit in the CKSTPR register is set to 1 all clocks are stopped stop mode 10 4 2 Pin States in Stop Mode The I O ports retain the states immediately before stop mode is entered If bits CKPT1 to CKPTO in the EXCKCR register are 11b P4_6 XIN and P4_7 XOUT pins XIN P4_6 and XOUT P4_7 become the high impedance state If bits CKPT1 to CKPTO in the EXCKCR register are 01b XIN clock input do not use stop mode 10 4 3 Returning from Stop Mode A reset or a peripheral function interrupt is used to return from stop mod
9. 12 3 6 Port 1 Function Mapping Register 0 PML1 Address 000C8h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol 0 0 0 0 0 0 0 After Reset 0 Bit Name Function P10SELO Port P1_0 function select bits P10SEL1 I O port or ANO input TRCIOD KIO Do not set P11SELO0 Port P1_1 function select bits PHSELI I O port or AN1 input TRCIOA TRCTRG KI1 Do not set P12SELO0 Port P1_2 function select bits P12SEL1 HO port or AN2 input TRCIOB KI2 Do not set P13SELO0 Port P1_3 function select bits P13SEL1 I O port or AN3 input TRCIOC KIS TRBO The PML register is used to select the functions of pins P1_0 to P1_3 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 146 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 7 Port 1 Function Mapping Register 1 PMH1 Address 000C9h Bit b 7 b6 b5 b4 b3 b2 b1 bO Symbol P17SEL1 P17SELO P16SEL1 P16SELO P15SEL1 P15SEL0 P14SEL1 P14SELO 0 0 0 0 0 0 0 After Reset 0 Bit Name Function P14SELO Port P1_4 function select bits bx b1 bO P14SEL1 0 0 0 UO port or AN4 input 0 0 1 TXDO 0 1 0 RXDO 011 INTO 100 TRCIOB Other than the above Do not set bx P14SEL2 bit in the PMH1E register P15SELO Port P1_5 function select bits bx b3 b2 000 UO port P15SEL1 0 0 1 RXDO 0 1 0 TRJIO 0 11 INT1 100 VCOUT1 Other than the above Do not set bx P15SEL2 bit in the PMH1E
10. Locked Not locked FST3 Program suspend status flag Program not suspended Program suspended FST4 Program error status flag 3 No program error Program error FST5 Erase error blank check error status flag 3 No erase error blank check error Erase error blank check error FST6 Erase suspend status flag Erase not suspended Erase suspended FST7 Notes Ready busy status flag Busy Ready 1 The RDYSTI bit cannot be set to 1 flash ready status interrupt requested by a program Read this bit dummy read before writing 0 no flash ready status interrupt requested to the RDYSTI bit To check this bit set the RDYSTIE bit in the FMRO register to 1 flash ready status interrupt enabled 2 The BSYAEI bit cannot be set to 1 flash access error interrupt requested by a program Read this bit dummy read before writing 0 no flash access error interrupt requested to the BSYAEI bit To check this bit set the BSYAEIE bit in the FMRO register to 1 flash access error interrupt enabled or set the CMDERIE bit in the FMRO register to 1 erase write error interrupt enabled 3 This bit is also set to 1 error when a command sequence error occurs 4 When this bit is 1 do not set the FMR01 bit in the FMRO register to 0 CPU rewrite mode disabled RO1UHOO50EJ0200 Rev 2 00 ztENESAS May 18 2012 Page 330 of 426 R8C M11A Group R8C M12A Group 19 Fla
11. RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 232 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 2 Timer RC General Register A B C and D TRCGRA TRCGRB TRCGRC and TRCGRD Address 000EAh to OOOEBh TRCGRA OOOECh to OOOEDh TRCGRB OOOEEh to OOOEFh TRCGRC O00F0h to 000F1h TRCGRD Bit b7 b6 b5 b4 b3 b2 b1 b Symboi l RECH After Reset 1 1 1 1 1 1 1 1 Bit b15 b14 b13 b12 b11 b10 b9 b8 Symbol tS E a After Reset 1 1 Table 15 5 Functions of TRCGRj Register when Using Input Capture Function Input Capture Input Pin General register Can be used to read the TRC register value TRCIOA at input capture TRCIOB BUFEA 0 General register Can be used to read the TRC register value TRCIOC BUFEB 0 at input capture TRCIOD BUFEA 1 Buffer registers Can be used to hold transferred value from TRCIOA BUFEB 1 the general register Refer to 15 5 5 Buffer Operation TRCIOB Timing Register Setting Register Function j A B C or D BUFEA BUFEB Bits in TRCMR register Table 15 6 Functions of TRCGRj Register when Using Output Compare Function Output Compare Output Pin General register Write a compare value to one of these TRCIOA registers TRCIOB BUFEA 0 General register Write a compare value to one of these TRCIOC BUFEB 0 registers TRCIOD BUFEA 1 Buffer register Write the next compare value to one of TRCIOA BUFEB 1 thes
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13. Reserved Set to 1 R W b7 Note 1 The OFS2 register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS2 register Erasure of the block including the OFS2 register causes the OFS2 register to be set to FFh When blank products are shipped the OFS2 register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS2 register is the value programmed by the user For an example of the OFS2 register settings see 5 6 1 Option Function Select Area Setting Example Bits WDTUFSO to WDTUFS1 Watchdog timer underflow period setting bits These bits are used to select the underflow period for the watchdog timer Bits WDTRCSO to WDTRCS1 Watchdog timer refresh acceptance period setting bits These bits are used to select the refresh acceptance period as a percentage Note that the period from the start of counting to underflow is 100 For details see 8 3 1 1 Refresh Acceptance Period RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 40 of 426 R8C M11A Group R8C M12A Group 6 Resets 6 2 4 Option Function Select Register OFS Address OFFFFh Bit b7 b6 b5 b4 b3 b2 bi bO Symbol CSPROINI LVDAS VDSEL1 VDSELO ROMCP1 ROMCR o o i WDTON After Reset User Setting Value 1 Bit Name Function Watchdog timer start select bit 0 Wat
14. 00h 001ADh Flash Memory Refresh Control Register 00h 001AEh 001AFh DO BO 001Bih 001B2h 001B3h 001B4h 001B5h 001B6h 001B7h 001B8h 001B9h 001BAh 001BBh 001BCh 001BDh 001BEh 001BFh Note 1 The blank areas are reserved No access is allowed RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 21 of 426 R8C M11A Group R8C M12A Group 3 Address Space Table 3 8 Address SFR Information 8 1 Register Name Address Match Interrupt Register 0 Symbol AIADROL After Reset AIADROM AIADROH Address Match Interrupt Enable Register 0 AIENO 001C6h Address Match Interrupt Register 1 AIADRI1L AIADR1M AIADR1H 001C7h Address Match Interrupt Enable Register 1 AIEN1 001C8h 001C9h 001CAh 001CBh 001CCh 001CDh 001CEh 001CFh 001D0h 001D1h 001D2h 001D3h 001D4h 001D5h 001D6h 001D7h 001D8h 001D9h 001DAh 001DBh 001DCh 001DDh 001DEh 001DFh 001E0h 001E1h 001E2h 001E3h 001E4h 001E5h 001E6h 001E7h 001E8h 001E9h 001EAh 001EBh 001ECh 001EDh 001EEh 001EFh 001FOh 001F1h 001F2h 001F3h 001F4h 001F5h 001
15. 1 Read the RDYSTI bit in the FST register dummy read 2 Write 0 no flash ready status interrupt requested to the RDYSTI bit 3 Set the RDYSTIE bit to 1 flash ready status interrupt enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 334 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 5 3 Flash Memory Control Register 1 FMR1 Address 001ABh Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol FRITZ FMRTE FMRTS weem After Reset 0 0 0 0 0 0 0 0 Bit Name Function Reserved Set to 0 WTFMSTP Flash memory stop bit in wait 0 Flash memory operates in wait mode mode 1 Flash memory is stopped in wait mode FMR13 Lock bit disable select bit 1 0 Lock bit enabled 1 Lock bit disabled Nothing is assigned The write value must be 0 The read value is 0 Data flash block A rewrite disable 0 Rewrite enabled software commands acceptable bit 2 3 1 Rewrite disabled software commands not Data flash block B rewrite disable acceptable no error occurred bit 2 3 Notes 1 To set this bit to 1 first write O and then write 1 immediately Interrupts must be disabled between writing 0 and then writing 1 2 To set this bit to 0 first write 1 and then write 0 immediately Interrupts must be disabled between writing 1 and then writing 0 3 This bit is set to 0 when the FMR01 bit in the FMRO register is set to 0 CPU rewrite mode disabled WTFMSTP Bit
16. 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified Parameter Power supply current 1 Notes High speed clock mode Condition Oscillation Circuit On Chip Oscillator XIN 2 High Speed Low Speed 125 kHz CPU Clock No division Low Power Consumption Setting Standard Typ 3 125 kHz No division 125 kHz No division 125 kHz Division by 8 125 kHz Division by 8 125 kHz Division by 8 High speed on chip oscillator mode 125 kHz No division 125 kHz Division by 8 125 kHz Division by 16 MSTTRC 1 Low speed on chip oscillator mode 125 kHz Division by 8 FMR27 1 LPE 0 Wait mode 125 kHz Peripheral clock supplied during WAIT instruction execution 125 kHz VC1E 0 VCOE 0 LPE 1 WCKSTP 1 Peripheral clock stopped during WAIT instruction execution Stop mode VC1E 0 VCOE 0 STPM 1 Topr 25 C Peripheral clock stopped VC1E 0 VCOE 0 STPM 1 Topr 85 C Peripheral clock stopped 1 Vcc 4 0 V to 5 5 V single chip mode output pins are open and other pins are connected to Vss Vcc 5 0 V kwon When the XIN input is a square wave Set the system clock to 4 MHz with the PHISEL register RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page
17. A D conversion time tCONV with no start delay time tD included end processing time tEND ADST bit in ADCONO register Input sampling timing A D comparison timing ADF bit in ADICSR register la png pg gg gt tD tSPL tCMP tEND tCONV tD A D conversion start delay time tSPL Input sampling time tCMP A D comparison time tCONV A D conversion time tEND End processing time Figure 17 2 A D Conversion Timing RO1UH0050EJ0200 Rev 2 00 RENESAS Page 307 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter Table 17 6 A D conversion start delay time 3 A D Conversion Time tD A D Conversion Clock H fAD CKSO 1 CKSO 0 CKS CKS1 0 0 1 3 to 10 CKS2 1 2 Input sampling time tSPL 61 121 A D comparison time tCMP 100 200 A D conversion time tCONV 84 to 85 164 to 167 324 to 331 End processing time CKSO CKS1 CKS2 Bits in ADMOD register Notes tEND 2 to 3 cycles of fAD 1 The numerical values in the table indicate the number of system clock f cycles 2 The numerical values in the table indicate the number of fAD cycles 3 In repeat mode single sweep mode and repeat sweep mode there is no delay time during the A D conversion time tCONV for the second and subsequent rounds 17 3 1 2 External Trigger Input Timing A D conversion can also be s
18. FST3 Bit Program suspend status flag This is a read only bit indicating the suspend status This bit is set to 1 when a program suspend request is acknowledged and a program suspend status is entered otherwise it is set to 0 FST4 Bit Program error status flag This is a read only bit indicating the auto programming status The bit is set to 1 if a program error occurs otherwise it is set to 0 For details see the description in 19 6 7 Full Status Check FST5 Bit Erase error blank check error status flag This is a read only bit indicating the status of auto erase or block blank check command The bit is set to 1 if an erase error or blank check error occurs otherwise it is set to 0 For details see the description in 19 6 7 Full Status Check FST6 Bit Erase suspend status flag This is a read only bit indicating the suspend status This bit is set to 1 when an erase suspend request is acknowledged and an erase suspend status is entered otherwise it is set to 0 FST7 Bit Ready busy status flag When the FST7 bit is set to 0 busy the flash memory is in one of the following states e During programming e During erasure e During the lock bit program e During the read lock bit status e During the block blank check e During forced stop operation e The flash memory is being stopped e The flash memory is being activated Otherwise the FST7 bit is set to 1 ready RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 332 of
19. INT 1 comparator B1 output 0 U When waveform output manipulation event is cancelled EB bit in TRCOER register Corresponding output with waveform output manipulation disabled f Timer RC output TRCIOB_XP internal signal Output control signal TRCOBE_XN internal signal 4 r TRCIOB output E TC 4 KS EB bit is set to 0 Le e es i 7a sal fase W ES Se r SE Output is enabled Timer RC output level is fixed at low during waveform output manipulation period Synchronized so that less than one cycle of waveform is not output Figure 15 25 Example of Waveform Output Manipulation Operation 3 RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 267 of 426 R8C M11A Group R8C M12A Group 15 Timer RC e When the OPE bit in the TRCOPR register is 1 waveform output manipulation control enabled bits OPOL1 to OPOLO are 11b timer RC output level is fixed at high during waveform output manipulation period and the RESTATS bit is 1 output is automatically restarted Waveform output Waveform output manipulation manipulation event is input event is cancelled Waveform output i P i i manipulation event d INT 1 comparator B1 output EB bit in TRCOER register Corresponding output with waveform output manipulation disabled U 1 9i When waveform output manipulation event is cancelled EB bit is se
20. The voltage monitor 0 reset is due to the on chip voltage detection 0 circuit The voltage detection 0 circuit monitors the voltage applied to the VCC pin Vdet0 is the detection level The Vdet0 level is set with bits VDSELO to VDSEL1 in the OFS register When the input voltage to the VCC pin falls to the VdetO level or lower the CPU SFRs and I O ports are initialized The internal RAM is not initialized If the supply voltage falls to VdetO or lower while writing to the internal RAM the RAM values will be undefined When the voltage applied to the VCC pin next rises to the Vdet0 level or higher counting of the low speed on chip oscillator clock starts When the low speed on chip oscillator clock count reaches 256 the internal reset signal goes high and the MCU proceeds to the reset sequence see Figure 6 2 The low speed on chip oscillator clock no division is automatically selected as the CPU clock after a reset The LVDAS bit in the OFS register can be used to enable or disable the voltage monitor 0 reset after a reset The setting of the LVDAS bit is valid at all resets Bits VDSELO to VDSEL1 and LVDAS cannot be changed by a program To change these bits write values to b4 to b6 at address OFFFFh using a flash programmer For details on the OFS register see 6 2 4 Option Function Select Register OFS For details on the voltage monitor 0 reset see 7 Voltage Detection Circuit Figure 6 5 shows an Example of Voltage Monitor 0 Reset O
21. Y 3 Select fHSCK Set the HSCKSEL bit in the SCKCR register HSCKSEL 1 High speed on chip oscillator clock HSCKSEL 0 XIN clock 4 Select the system base clock fBASE Set the SCKSEL bit in the CKSTPR register SCKSEL 1 fHSCK SCKSEL 0 Low speed on chip oscillator clock Operating on the target clock Figure 9 4 Flowchart for Clock Switching between XIN Clock Oscillation Circuit Low Speed On Chip Oscillator and High Speed On Chip Oscillator RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 88 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 4 6 1 Procedure for Switching System Base Clock to High Speed On Chip Oscillator Figure 9 5 shows the Flowchart for Switching from Low Speed On Chip Oscillator to High Speed On Chip Oscillator Clock Operating on the low speed on chip oscillator clock Start reset y Set the HOCOE bit in the OCOCR register to 1 1 When the HOCOE bit is set to 1 high speed on chip oscillator on the high speed on chip oscillator starts oscillating Wait for the high speed on chip oscillator to 2 Assure the wait time for oscillation stabilization stabilize by a program 3 When the HSCKSEL bit is set to 1 high speed Set the HSCKSEL bit on chip oscillator clock fHSCK is switched in the SCKCR register to 1 from the XIN clock to the high speed on chip clock Set the SCKSEL bit 4 When the SCKSEL is set to 1 f HSCK fBASE in t
22. b6 b5 b4 0 0 0 f1 00 1 f8 0 10 fHOCO 011 f2 Other than the above Do not set TCKCUT Notes Timer RJ count source cutoff bit 2 0 Count source is supplied 1 Count source is cut off 1 When event counter mode is selected the external input TRJIO is selected as the count source regardless of the setting of bits TCKO to TCK2 2 Do not switch or cut off the count source during count operation When switching or cutting off the count source set the TSTART bit in the TRJCR register to 0 count is stopped and the TCSTF bit to 0 count is stopped to stop the timer count Select the operating mode when the count is stopped the TSTART bit is 0 and the TCSTF bit is 0 When a value is written to the TRJMR register the toggle flip flop is initialized 13 3 5 Timer RJ Event Select Register TRJISR Address 000DDh Bit b7 After Reset RCCPSELO 0 Bit Name Timer RC output signal select VR b RCCPSEL1 bits Function 0 0 TRCIOD 0 1 TRCIOC 1 0 TRCIOB 11 TRCIOA b6 b5 b4 b3 b2 b1 bO RPSL RCOPSEL TROOPSELY 0 0 0 0 0 0 0 RCCPSEL2 Timer RC output signal inversion bit 0 Low level period of timer RC output signal is counted 1 High level period of timer RC output signal is counted Nothing is assigned The write value must be 0 The read value is 0 RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 184 of 426 R8
23. 1 PA_O output L MOV B 00000001b PA PA_O become hiz output open drain 21 6 2 UO Pins for Peripheral Functions In this MCU the pin assignment of the peripheral functions can be changed using the port function mapping register However multiple pins must not be assigned to the same peripheral function input at the same time Otherwise no signal can be input correctly RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 395 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 7 Notes on Timer RJ2 1 Timer RJ2 stops counting after a reset Start the count only after setting the value in the timer 2 After 1 count is started is written to the TSTART bit in the TRJCR register while the count is stopped the TCSTF bit in the TRJCR register remains 0 count is stopped for two to three cycles of the count source Do not access the registers associated with timer RI OU other than the TCSTF bit until this bit is set to 1 count is in progress The count is started from the first active edge of the count source after the TCSTF bit is set to 1 After O count is stopped is written to the TSTART bit during a count operation the TCSTF bit remains 1 for two to three cycles of the count source When the TCSTF bit is set to 0 the count is stopped Do not access the registers associated with timer RJ2 UN other than the TCSTF bit until this bit is set to 0 Note 1 Registers associated with timer RJ2 TRJ TRJCR TRJIOC and T
24. 2 DIMENSION 3 DOES NOT Di D INCLUDE TRIM OFFSET Reference Dimension in Millimeters a Symbol Min Nom Max Ka lt 21 7 69 i SEATING PLANE D 19 2 19 3 19 4 d E 6 25 6 35 6 45 4 A 48 Au 0 5 Ae 3 05 3 25 3 45 z w lles bp 0 38 0 55 ba 1 47 1 52 1 57 s SG 0 21 LOS 8 OP dE e 2 54 Zp 2 03 L 2 92 RO1UHOO50EJ0200 Rev 2 00 w N E SZ Page 415 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ_ P LSSOP20 4 4x6 5 0 65 PLSP0020JB A 20P2F A 0 1g 11 r RARAARAAR 20 w F NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET 4 index mark ae c M A 2 Reference Dimension in Mil
25. Address 000B2h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol P47 P46 P45 P2 After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P4_2 bit 0 Low level 1 High level Nothing is assigned The write value must be 0 The read value is 0 Port P4_5 bit 0 Low level Port P4_6 bit 1 High level Port P4_7 bit The P4 register is an I O port data register Data input to and output from external devices are accomplished by reading from and writing to the P4 register The P4 register consists of a port latch to retain output data and a circuit to read the pin states The value written to the port latch is output from the pin Each bit in the P4 register corresponds to individual ports RO1UHO050EJ0200 Rev 2 00 RENESAS Page 158 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 5 3 Pull Up Control Register 4 PUR4 Address 000B8h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symboi P07 Pe Pas Paa 0 0 0 0 0 0 0 After Reset 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P4_2 pull up control bit 0 No pull up resistor 1 Pull up resistor Nothing is assigned The write value must be 0 The read value is 0 Port P4_5 pull up control bit 0 No pull up resistor Port P4_6 pull up control bit 1 Pull up resistor Port P4_7
26. BSYAEI FMRO RDYSTIE BSYAEIE CMDERIE Periodic timer WDTIR WDTIF WDTIR WDTIE IRWD Comparator B Note WCBI1INTR WCBI1F WCBI1INTR WCBI1INTEN WCBS3INTR WCB3F WCBSINTR WCBSINTEN IRCMP1 IRCMP3 1 Timer RC and the flash memory each have multiple interrupt request sources An interrupt request is generated 11 4 2 2 R01UH0050EJ0200 Rev 2 00 by the logical OR of several interrupt request sources and is reflected in the monitor flag the IRTC bit in the IRRO register or the IRFM bit in the IRR1 register IRR3 Register The IRR3 register is the flag register for external interrupts INTO to INT3 and KIO to KI3 When external input is enabled and an active edge is detected the interrupt request flag in the IRR3 register is set to 1 When an interrupt request is acknowledged the flag for this interrupt request is automatically set to 0 after the CPU branches to the corresponding interrupt vector Writing 0 after reading the value 1 also sets the interrupt request flag to 0 ztENESAS May 18 2012 Page 122 of 426 R8C M11A Group R8C M12A Group 11 Interrupts 11 4 3 Interrupt Priority Levels in ILVLi Register i 0 or 2 to E and IPL Interrupt priority levels can be set by the ILVLi register i 0 or 2 to E Table 11 8 lists the Interrupt Priority Level Settings Table 11 9 lists the Interrupt Priority Levels Enabled by IPL
27. Enabled Falling edge Rising edge Disabled Enabled Falling edge Rising edge KIO input edge select bit 1 KIT input enable bit KIT input edge select bit 1 KIZ input enable bit KIZ input edge select bit 1 KI3 input enable bit KI3 input edge select bit 1 O O zk O zk oO oO O oO HY CH Note 1 Changing the bits KIiPL or KIiEN i 0 to 3 may set the IRKI bit in the IRR3 register to 1 interrupt requested See 11 9 4 Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 114 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 5 Bit After Reset ILVLiO b 0 0 Bit Name ILVLi1 Interrupt priority level setting bits b1 bo i 0 0 Level 0 interrupt disabled 0 1 Level 1 1 0 Level 2 11 Level 2 Interrupt Priority Level Register i ILVLi i 0 or 2 to E Address 00040h ILVLO 00042h to 0004Eh ILVL2 to ILVLE Function 7 b6 b5 b4 b3 b2 b1 b sma CC Ce Nothing is assigned The write value must be 0 The read value is 0 ILVLi4 ILVLi5 Interrupt priority level setting bits b5 b4 0 0 Level 0 interrupt disabled 0 1 Level 1 1 0 Level 2 11 Level 2 Nothing is assigned The write value must be 0 The read value is 0 The ILVLi register i 0 or 2 to E is used to set the priority
28. Erase command re execution times lt 3 Re execute the block erase command Program error Program error Execute the clear status register command Set bits FST4 through FST5 to 0 Is the lock bit disabled Set FMR13 bit to 1 Yes Specify a program address other than the FST4 FST5 Bits in FST register write address where the error occurred 1 Full status check completed Note 1 To write again to the address where a program error occurred execute the block erase command and confirm the full status check is completed normally before writing Re execute the program command to the address Figure 19 19 Full Status Check and Handling Procedures for Individual Errors RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 357 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 7 Standard Serial UO Mode In standard serial I O mode a serial programmer that supports the MCU can be used to rewrite the user ROM area with the MCU mounted on board There are three standard serial I O modes e Standard serial I O mode 1 Connection to a serial programmer via clock synchronous serial I O e Standard serial I O mode 2 Connection to a serial programmer via clock asynchronous serial I O e Standard serial I O mode 3 Connection to a serial programmer via special clock asynchronous serial I O Standard serial I O modes 2 and 3 can be used with the MCU See Appendix 2 Connection Examples between Serial Pr
29. External Interrupt Flag Register IRR3 00053h Address Match Interrupt Register 0 AIADROL 001C0h AIADROM 001C1h AIADROH 001C2h Address Match Interrupt Enable Register 0 AIENO 001C3h Address Match Interrupt Register 1 AIADRiL 001C4h AIADR1iM 001C5h AIADR1H 001C6h Address Match Interrupt Enable Register 1 RO1UH0050EJ0200 Rev 2 00 May 18 2012 AIEN1 ztENESAS 001C7h o CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO 0 CO 0 0 CO Page 111 of 426 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 1 External Input Enable Register INTEN Address 00038h Bit b7 b6 b5 b4 b3 b2 b1 b Syme Jl MIER INTEN NEN INTOEN After Reset 0 0 0 0 0 0 0 0 Bit Name Function INTOEN NTO input enable bit 1 0 Disabled 1 Enabled INTIEN INTT input enable bit 1 INT2EN INT2 input enable bit 1 INTSEN NT3 input enable bit 1 Reserved Set to 0 Nothing is assigned The write value must be 0 The read value is 0 Reserved Set to 0 Notes 1 Changing the INTiEN bit i 0 to 3 may set the IRIi bit i 0 to 3 in the IRR3 register to 1 interrupt requested See 11 9 4 Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN 11 2 2 INT Input Filter Select Register 0 INTFO Address 0003Ah Bit b 7 b6 b5 b4 b3 b2 b1 bO
30. Figure 14 2 Operation Example in Timer Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 208 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 4 2 Programmable Waveform Generation Mode In the 8 bit timer with 8 bit prescaler the values in registers TRBPR and TRBSC are counted alternately In the 16 bit timer the lower 8 bits are counted by the TRBPRE register and the higher 8 bits are counted by registers TRBPR and TRBSC alternately The TRBO pin outputs a signal which is inverted each time the counter underflows The count is started from the value set in the TRBPR register In programmable waveform generation mode the TRBOCR register is not used When count is started is written to the TSTART bit in the TRBCR register the count is started after the count source is sampled three times When 0 count is stopped is written to the TSTART bit the count is stopped after the count source is sampled three times When count is forcibly stopped is written to the TSTOP bit in the TRBCR register the count is stopped The actual count state should be monitored with the TCSTF bit in the TRBCR register An interrupt request is generated when timer RB2 underflows during the secondary period When registers TRBPRE and TRBPR are read each count value can be read Read the TRBPR register even while the secondary period is counted When registers TRBPRE TRBPR and TRBSC are written while the count is stopped values are writt
31. Figure 15 10 shows an Example of Buffer Operation in PWM Mode In this example the TRCIOB pin is set to PWM mode and the TRCGRD register is set as the buffer register for the TRCGRB register The TRCCNT register is cleared by compare match A and output is set to low at compare match A and high at compare match B Since buffer operation is set the output is changed when compare match B occurs and the value in the buffer register TRCGRD is transferred to the TRCGRB register at the same time This operation is repeated each time compare match B occurs TRCCNT register value TRCGRA register TRCGRB register 0000h TRCGRD register TRCGRB register TRCIOB Figure 15 10 Example of Buffer Operation in PWM Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 253 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 11 shows an Operation Example in PWM Mode Duty Cycle 0 Duty Cycle 100 e Bits TOB TOC and TRCCNT TOD in TRCCR1 register value register are 0 8 initial output is low TRCGRA register TRCGRB register 0000h Output remains unchanged when compare matches in the period and duty cycle registers occur simultaneously TRCCNT register value TRCGRA register TRCGRB register 0000h j U TRCIOB Duty cycle 100 Output remains unchanged when compare matches in the period and duty cycle registers Note 1 occur simultaneously TRCCNT register value TRCGRA register TRCGR
32. Output compare TLILILU LULU LEU UL Compare match signal TRCCNT register n n 1 l 1 Registers TZ a TRCGRC and TRCGRD 1 coe gt TRCGRA and TRCGRB e Input capture Bel Ek CFE LL KC Input capture signal TRCCNT register Registers TRCGRA and TRCGRB Registers TRCGRC and TRCGRD Figure 15 31 Buffer Operation Timing RO1UH0050EJ0200 Rev 2 00 RENESAS Page 271 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 5 6 Setting Timing at Compare Match While the TRCSR register functions as an output compare register bits IMFA to IMFD are set to 1 when TRCCNT register and the general registers TRCGRA TRCGRB TRCGRC TRCGRD match A compare match signal occurs at the last state timing when the TRCCNT register updates a matched value Thus after the TRCCNT register and the general register match a compare match signal does not occur until an input clock to the TRCCNT register is generated Figure 15 32 shows the Timing at Compare Match i a TT KEE TRCCNT register input clock TRCCNT register Registers TRCGRA to TRCGRD Compare match signal IMFA to IMFD IMFA to IMFD Bits in TRCSR register Figure 15 32 Timing at Compare Match 15 5 7 Setting Timing at Input Capture While the TRCSR register functions as an input capture register bits IMFA to IMFD are set to 1 when an input capture occurs Figure 15 33 shows the Timing at Input Capture TLL UU UU U UL Input capture si
33. P37SEL1 b7 b6 0 0 I O port 0 1 ADTRG 10 TRJO 11 TRCIOD The PMH3 register is used to select the functions of pins P3_4 P3_5 and P3_7 RO1UHOO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 155 of 426 R8C M11A Group R8C M12A Group 12 I O Ports 12 4 8 Pin Settings for Port 3 Tables 12 12 to 12 15 list the pin settings for port 3 Table 12 12 Port P3_3 IVCMP3 TRCCLK INT3 Register PMH3 Bit Setting value X 0or 1 P33SEL Function Input port IVCMP3 Output port TRCCLK input Table 12 13 Port P3_4 IVREF3 TRCIOC INT2 Register PMH3 Bit Setting value X 0or1 P34SEL Timer RC Setting X INT3 input Function Input port IVREF3 X Output port See Table 12 23 TRCIOC Pin Settings TRCIOC input See Table 12 23 TRCIOC Pin Settings TRCIOC output X Table 12 14 Port P3_5 TRCIOD KI2 VCOUT3 Register PMH3 Bit Setting value X 0 or 1 P35SEL Timer RC Setting X INT2 input Function Input port X Output port See Table 12 24 TRCIOD Pin Settings TRCIOD input See Table 12 24 TRCIOD Pin Settings TRCIOD output X KI2 input X Table 12 15 Port P3_7 ADTRG TRJO TRCIOD Register PMH3 Bit Setting value X 0or 1 P37SEL Timer RC Setting VCOUTS3 output Function Input p
34. R8C M11A Group R8C M12A Group 19 Flash Memory When the FMR272 bit is set to 1 suspend request enabled by interrupt request the FMR21 bit is automatically set to 1 suspend request when an interrupt request is generated during auto erase Set the FMR22 bit to 1 when suspend is used while the user ROM area is rewritten in EW1 mode Maskable interrupt FMR20 1 Access the flash memory FMR22 1 Write the command code 20h 1 interrupt enabled JMP S CMD2 Write DOh to any block address 39 Flash memory dummy read 4 NOP instruction x 4 Flash memory dummy read nl FMR21 Full status check Flag in CPU register FST6 FST7 Bits in FST register Program completed FMR20 FMR21 FMR22 Bits in FMR2 register Notes 1 The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other than the programming target area 2 td SR SUS is required from when the maskable interrupt is generated until suspend is acknowledged The interrupt to enter suspend must be enabled beforehand 3 Use one of the following instructions for the second command writing e MOV B A0 A1 or MOV B A1 A0 e MOV B IMM An e MOV B IMM abs16 e MOV B Bn An e MOV B RnH abs16 e MOV B RnL An e MOV B RnL abs16 Use one of the following instructions to read the same address as the second command write address e MOV B An RnL e MOV
35. RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 91 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 6 Notes on Clock Generation Circuit 9 6 1 Oscillation Stop Detection Function The oscillation stop detection function cannot be used when the XIN clock frequency is below 2 MHz so set bits CKSWIE to XINBAKE in the BAKCR register to 00b interrupt disabled oscillation stop detection function disabled 9 6 2 Oscillation Circuit Constants Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system RO1UHO050EJ0200 Rev 2 00 stENESAS Page 92 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 Power Control Power control refers to controlling power consumption by selecting or stopping the CPU clock and the peripheral function clocks 10 1 Overview There are three power control modes Standard operating mode is further divided into three modes depending on the system base clock fBASE Table 10 1 Types of Modes Standard operating mode The CPU and the peripheral functions operate High speed clock mode System base clock fBASE XIN clock High speed on chip oscillator mode High speed on chip oscillator clock Low speed on chip oscillator clock The CPU is stopped and the peripheral functions operate The CPU and the peripheral functions are stopped and power consumption is lowest Low speed on chip
36. RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 387 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 Usage Notes 21 1 Notes on System Control 21 1 1 Option Function Select Area Setting Example The option function select area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program The following shows a setting example e To set FFh in the OFS2 register org OOFFDBH byte OFFh Programming formats vary depending on the compiler Check the compiler manual e To set FFh in the OFS register org OOFFFCH lword reset OFF000000h RESET Programming formats vary depending on the compiler Check the compiler manual 21 2 Notes on Watchdog Timer e Do not switch the count sources during watchdog timer operation e There is a delay of two cycles of the count source from a write to the WDTR register until the initialization of the watchdog timer e Allow at least three cycles of the count source between the previous and the next initialization of the watchdog timer 21 3 Notes on Clock Generation Circuit 21 3 1 Oscillation Stop Detection Function The oscillation stop detection function cannot be used when the XIN clock frequency is below 2 MHz so set bits CKSWIE to XINBAKE in the BAKCR register to 00b interrupt disabled oscillation stop detection function disabled 21 3 2 Oscillation Circuit Constants Consult the oscillator manufacturer to determine the optimal oscil
37. WDTON Bit Watchdog timer start select bit This bit is used to select whether the watchdog timer is automatically started after a reset is cleared Bits VDSELO to VDSEL1 Voltage detection 0 level select bits These bits are used to select the detection level Vdet0 for voltage monitor 0 reset The same level of the voltage detection 0 level selected by bits VDSELO to VDSEL1 is set in both the voltage monitor 0 reset and power on reset functions LVDAS Bit Voltage detection 0 circuit start bit This bit is used to select whether voltage monitor 0 reset is enabled Set the LVDAS bit to 0 voltage monitor 0 reset enabled after reset to use the power on reset CSPROINI Bit Count source protection mode after reset select bit This bit is used to select whether to protect the count source for the watchdog timer from being changed RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 41 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 3 Operation 6 3 1 Reset Sequence Figure 6 2 shows the Reset Sequence using a hardware reset as an example When the internal reset signal is cleared the CPU starts operation from the reset vector addresses OFFFCh to OFFFEh after a predetermined time has elapsed es FLL Ug LDL ig LLL LS LLL RESET pin m 10 us or more required Ui i 1 eg fLOCO clock x 2 cycles 1 Internal reset signal a Start time for flash memory CPU clock x 75 cycles CPU clock x 28
38. one of the following methods e Rewrite the contents of the stack and use the REIT instruction to return e Use an instruction such as POP to restore the stack to its previous state where the interrupt request was acknowledged Then use a jump instruction to return Table 11 13 lists the PC Value Saved When Address Match Interrupt Request is Acknowledged Table 11 14 lists the Correspondence between Address Match Interrupt Sources and Associated Registers Table 11 13 PC Value Saved When Address Match Interrupt Request is Acknowledged Instruction at Address Indicated by AIADRi Register i 0 or 1 PC Value Saved 1 e Instruction with 16 bit operation code Address indicated by e Instruction shown below among the instructions with 8 bit operation code AIADRi register 2 ADD B S IMM8 dest SUB B S IMM8 dest AND B S IMM8 dest OR B S IMM8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMMB8 dest PUSHM src POPM dest JMPS IMM8 JSRS IMM8 MOV B S IMM dest however dest AO or A1 Instructions other than the above Address indicated by AIADRi register 1 Note 1 PC value saved See 11 4 7 Saving Registers Table 11 14 Correspondence between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIENOO AIADRO Address match interrup
39. pe CH INT2 84 to 87 00054h to 00057h ine ILVLA5 to ILVLA4 Timer RJ2 88 to 91 00058h to 0005Bh ILVLB1 to ILVLBO Periodic timer 80 to 83 00050h to 00053h 92 to 95 0005Ch to 0005Fh ILVLB5 to ILVLB4 Timer RB2 96 to 99 00060h to 00063h ILVLC1 to ILVLCO INT1 100 to 103 00064h to 00067h ILVLC5 to ILVLC4 INT3 104 to 107 00068h to 0006Bh ILVLD1 to ILVLDO Reserved 27 to 28 INTO 116 to 119 00074h to 00077h 29 ILVLES to ILVLE4 Reserved 30 Reserved 31 Software 2 Notes 128 to 131 00080h to 00083h to 252 to 255 000FCh to 000FFh 32 to 63 1 These addresses are relative to those indicated by the INTB register 2 These interrupts are not disabled by the flag RO1UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 121 of 426 R8C M11A Group R8C M12A Group 11 Interrupts 11 4 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the priority for acknowledgement This description does not apply to non maskable interrupts 11 4 1 Flag The I flag enables or disables maskable interrupts Setting the I flag to 1 enabled enables maskable interrupts Setting the I flag to 0 disabled disables all maskable interrupts 11 4 2 Registers IRRO to IRR3 11 4 2 1 Table 11 7 Regis
40. select bits 1 Interrupt request is generated on the falling edge of INT1 input Interrupt request is generated on the rising edge of INT1 input Do not set Interrupt request is generated on both the falling and rising edges of INT1 input INT2SA INT2 input edge INT2SB select bits 1 Interrupt request is generated on the falling edge of INT2 input Interrupt request is generated on the rising edge of INT2 input Do not set Interrupt request is generated on both the falling and rising edges of INT2 input INT3SA INT3 input edge INT3SB select bits 1 Interrupt request is generated on the falling edge of INT3 input Interrupt request is generated on the rising edge of INT3 input Do not set Interrupt request is generated on both the falling and rising edges of INT3 input Note 1 Changing bits INTISA to INTISB i 0 to 3 may set the IRIi bit i O to 3 in the IRR3 register to 1 interrupt requested See 11 9 4 Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 113 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 4 Key Input Enable Register KIEN Address 0003Eh Bit b7 b6 b5 b4 b3 b2 b1 b Symbol After Reset 0 Bit Name Function KIO input enable bit Disabled Enabled Falling edge Rising edge Disabled Enabled Falling edge Rising edge Disabled
41. 1 2 7 V lt Vcc lt 4 0 V and Topr 20 C to 85 C N version 40 C to 85 C D version f XIN 10 MHz unless otherwise specified 2 High drive capacity can also be used while the peripheral output function is used RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 380 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 20 DC Characteristics 4 2 7 V lt Vcc lt 4 0 V Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified Parameter Power supply current 1 Notes High speed clock mode Condition Oscillation Circuit On Chip Oscillator XIN 2 High Speed Low Speed 125 kHz CPU Clock No division Low Power Consumption Setting Standard Typ 3 125 kHz No division 125 kHz No division 125 kHz Division by 8 125 kHz Division by 8 125 kHz Division by 8 High speed on chip oscillator mode 125 kHz No division 125 kHz Division by 8 125 kHz No division 125 kHz Division by 8 125 kHz Division by 16 MSTTRC 1 Low speed on chip oscillator mode 125 kHz Division by 8 FMR27 1 LPE 0 Wait mode 125 kHz Peripheral clock supplied during WAIT instruction execution 125 kHz VC1E 0 VCOE 0 LPE 1 WCKSTP 1 Peripheral clock stopped during WAIT instruction
42. 2012 R8C M11A Group R8C M12A Group 3 Address Space 3 Address Space 3 1 Memory Map Figure 3 1 shows the Memory Map The R8C M11A Group and R8C M12A Group have a 1 Mbyte address space from addresses 00000h to FFFFFh The internal ROM program ROM is allocated at lower addresses beginning with address OFFFFh For example an 8 Kbyte internal ROM area is allocated at addresses OE000h to OFFFFh The fixed interrupt vector table is allocated at addresses OFFDCh to OFFFFh The start address of each interrupt routine is stored here The internal ROM data flash is allocated at addresses 03000h to 037FFh The internal RAM is allocated at higher addresses beginning with address 00400h For example a 512 byte internal RAM area is allocated at addresses 00400h to OOSFFh The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged Special function registers SFRs are allocated at addresses 00000h to 002FFh Peripheral function control registers are allocated here All unallocated spaces within the SFRs are reserved and cannot be accessed by users 00000h SFR See 3 2 Special Function Registers 002FFh SFRs 00400h Internal RAM OFED8h OXXXXh Reserved area OFFDCh Undefined instruction 03000h i Overflow Internal ROM i BRK instruction data flash i Address match 037FFh Single step OYYYYh i Watchdog timer oscillation stop detec
43. Address Data ROM data flash SFR ar ee ee Co P CPU clock Address Data CPU clock Address Data CPU clock Address Data CPU clock Address Data ROM program ROM RAM Cou y o R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 24 of 426 R8C M11A Group R8C M12A Group 5 System Control 5 1 This Overview chapter describes system control functions such as ID code checking register access protection and option functions 5 2 Registers Table 5 1 lists the Register Configuration for System Control Table 5 1 Register Configuration for System Control Register Name After Reset Address Access Size Processor Mode Register 0 00010h Module Standby Control Register 00012h Protect Register 00013h Hardware Reset Protect Register 00016h Reset Source Determination Register 0005Fh Option Function Select Register 2 OFFDBh Option Function Select Register OFFFFh Notes 1 2 3 See the description of the individual registers The value of the RSTFR register after a reset differs depending on the reset source For details see 5 2 5 Reset Source Determination Register RSTFR The OFS2 register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS2 register Erasure of the block including the OFS2
44. CLKO input high width tW CKL CLKO input low width ta C Q TXDO output delay time th C Q TXDO hold time tsu D C RXDO input setup time th C D RXDO input hold time Figure 20 10 Serial Interface Timing When Vcc 3 V Table 20 24 External Interrupt INTi Input Key Input Interrupt Kli i 0 to 3 Standard Min Parameter tw INH INTI input high width KI input high width tW INL INTI input low width Kli input low width 1 When the digital filter is enabled by the INTI input filter select bit the INTI input high width is 1 digital filter clock frequency x 3 or the minimum value of the standard whichever is greater SEN 2 When the digital filter is enabled by the INTi input filter select bit the INTi input low width is 1 digital filter clock frequency x 3 or the minimum value of the standard whichever is greater Figure 20 11 Timing for External Interrupt INTi Input and Key Input Interrupt Kli When Vcc 3 V RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 383 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 25 DC Characteristics 5 1 8 V lt Vcc lt 2 7 V Standard Parameter Condition Min Output high voltage P1_2 P1_3 P1_4 P1 When drive lOH 2 mA P3_3 P3_4 P3_5 P3 capacity is high When drive loH 1 mA capacity is low P1_0 P1_1 P1_6 P1 loH 1 mA P4_2 P4_5 P4_6 P4 PA_O Output low voltage P1_2
45. EEN 97 10 3 1 Peripheral Function Clock Stop Function 2 0 0 eee eccesseesecseeeseceesaeceeceecesecesceseseaeeseseaecaessaseeeeseseeseaeeags 97 10 3 2 Entering Wait Mode eeneg Ee Seed Ee 97 10 3 3 Pin Statesin Wat Mode asec ege EE EES soe soedess dsssb sees e EE oo biseecseguestyyesveesuees seeds SESE a TEE 97 10 34 Returning from Wait Mode gedd EEN 98 10 4 SLOP Mode sieses cost E E E be EEN Eeer Een Eet deet 102 104 1 Entering Stop Mode 102 10 4 2 Pin States 0 Stop Mode siapin E E A R sdbencetbestcuneesesthevceboessbgesegvecbscsvasencesevebecteds 102 10 4 3 Returning ee EE 102 10 5 Reducing Power Consumption 0 eee ceceeseeseceeceseessceeeeseeeseeseecsecsaecaecsaesaecsscssecesseseseseeeeseeeseseaseseseaseaaeeaes 104 LIT Voltage Detection Circuit sisec seca cn ei eth ete ec cdot eho escent oc Ra ae 104 1O 5 2 rn 104 UL E EE 104 10 5 4 Wat Mod and Stop Mode stedengiiuetrdergbregtestSiedEeeSt deed 104 10 5 5 Stopping Peripheral Function Clocks AA 104 UA Deet 104 UE Ge A D EE 104 105 8 Senaldntertace UARTO 3c28 cette eet es en aes ee ee See Ee ES 104 10 5 9 Reducing Internal Power Consumption 0 0 0 0 eee eeeceeeseeseceseeecesceeeeeeceeseaeeseecaecaeecaecaessacesesseesensees 105 10 5 10 Stopping Flash Memory 000 eee ceeeeeeeseeeeecseessecaecsaecaeceseeseeeaseaeseaecneseaecaaesaecsecuaecnessesseseaseseseaeeaaeeaes 106 10 5 11 Low Current Consumption Read Mode oo cece csecsseesecesceeceseeseeseseseesae
46. Flash memory operating modes 2 modes CPU rewrite and standard serial I O modes Erase block division See Figure 19 1 Flash Memory Block Diagram Programming method Byte units Erase method Block erase Program erase control method 1 Program erase control by software commands Blocks 1 and 2 program ROM 2 Rewrite control method Rewrite protect control in block units by lock bits Blocks A and B data flash Individual rewrite control on blocks A and B by bits FMR16 to FMR17 in the FMR1 register 6 commands 10 000 times Number of commands Program erase endurance 3 Blocks 1 and 2 program ROM 2 Blocks A and B data flash ID code check function 4 Standard serial UO mode supported Notes 1 When programming erasing the program ROM and the data flash use a VCC supply voltage in the range of 1 8 V to 5 5 V 2 The number of blocks and their division differ depending on products For details see Figure 19 1 Flash Memory Block Diagram 3 Definition of program erase endurance The number of program erase cycles is defined on a per block basis If the number of cycles is 10 000 each block can be erased 10 000 times For example if 1 024 cycles of 1 byte write are performed to different addresses in 1 Kbyte of block A and then the block is erased the number of cycles is counted as one When rewrites are performed 100 or more times the actual erase count can
47. High speed on chip oscillator mode 125 kHz No division 125 kHz Division by 8 125 kHz Division by 16 MSTTRC 1 Low speed on chip oscillator mode 125 kHz Division by 8 FMR27 1 LPE 0 Wait mode 125 kHz Peripheral clock supplied during WAIT instruction execution 125 kHz VC1E 0 VCOE 0 LPE 1 WCKSTP 1 Peripheral clock stopped during WAIT instruction execution Stop mode VC1E 0 VCOE 0 STPM 1 Topr 25 C Peripheral clock stopped VC1E 0 VCOE 0 STPM 1 Topr 85 C Peripheral clock stopped 1 Vcc 1 8 V to 2 7 V single chip mode output pins are open and other pins are connected to Vss 2 When the XIN input is a square wave 3 Vcc 2 2 V 4 Set the system clock to 5 MHz or 4 MHz with the PHISEL register RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 385 of 426 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Timing Requirements Vcc 2 2 V Vss 0 V at Topr 25 C unless otherwise specified Table 20 27 External Clock Input XIN Standard Symbol Parameter te XIN XIN input cycle time TWH XIN XIN input high width tWL XIN XIN input low width Vcc 2 2 V External Clock input Figure 20 12 External Clock Input Timing When Vcc 2 2 V Table 20 28 TRUJIO Input Standard Symbol Parameter Min te TRJIO TRJIO i
48. Li I Li LI H 1 H D d l S Set to 0 by acknowledgement p l of an interrupt request I l i Li 1 Set to 0 by a program I Set to 0 by acknowledgement of an interrupt request U Set to 0 by a program I L I I Set to 0 by acknowledgement of an interrupt request 1 Set to 0 by a program 1 1 1 g Set to 0 by acknowledgement of an interrupt request Set to 0 by a program Set to 0 by acknowledgement of an interrupt request Set to 0 by a program Set to 0 by acknowledgement of an interrupt request VCAC1 Bit in VCAC register VW1C1 VW1C2 VW1C3 VW1C7 Bits in VW1C register The above diagram applies under the following conditions e VC1E bit in VCA2 register 1 voltage detection 1 circuit enabled e VW1CO bit in VW1C register 1 voltage detection 1 interrupt enabled Note 1 If voltage monitor 0 reset is not used VCC must be at least 1 8 V Example of Voltage Monitor 1 Interrupt Operation ztENESAS Page 60 of 426 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 6 Digital Filter for Voltage Detection Circuits 0 and 1 Figure 7 6 shows a Block Diagram of Voltage Detection Circuit Digital Filter In digital filter enabled mode the voltage detection signal from the voltage detection circuit is used to generate a voltage monitor 0 reset signal and a voltage monitor interrupt signal individually through the digital filter circuit The filter width of the digital fi
49. Port PA_O functions as a hardware reset RESET Nothing is assigned The write value must be 0 The read value is 0 Note 1 Setting this bit to 1 open drain enables N channel open drain output and setting this bit to 0 not open drain enables CMOS output The PAMCR register is used to control the port PA open drain and the port A function The open drain is enabled when the peripheral function or output port function is selected Set the PAMCRE bit in the HRPR register to 1 write enabled before rewriting the PAMCR register 12 6 4 Pin Setting for Port A Table 12 20 lists the pin setting for port A Table 12 20 RESET Port DA O Register PAMCR Function Bit HWRSTE Sp RESET etting 1 value Input port 1 Output port 2 X 0or1 Notes 1 Connect a pull up resistor For details see 12 11 1 Notes on PA_0 Pin 2 Setting the PODA_0 bit to 1 enables N channel open drain output 12 7 Procedure for Setting Peripheral Functions Associated with Ports 1 3 and 4 After a reset use the following procedure to set the peripheral functions associated with ports 1 3 and 4 1 Set the function mapping registers for ports 1 3 and 4 2 Set the operating mode for the peripheral functions 3 Start operation of the peripheral functions RO1UHO050EJ0200 Rev 2 00 RENESAS Page 165 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 8 Pin Settings for Peripheral
50. Previous value New value 1Ah reload register Reloaded at the second underflow I 25h 24h 23h When the TWRC bit in TRBMR register is 1 write to reload register only Secondary Write 01h to TRBPRE register 25h to TRBPR register and 1Ah to TRBSC register underflow ower FLL After the value is written it is written to the reload register by the third count source TRBPRE j Previous value New value 01h reload register Reloaded at underflow Prescaler Prescaler underflow After the valua is written to the TRBPR register H it is written e el reload register immediately 1 before the end of the secondary output period TRBPR Previous value New value 25h reload register 1 After the valug is written to the TRBPR register it is written en reload register immediately before the end of the secondary output period TRBSC Previous value New value 1Ah reload register T Reloaded at the counter underflow 25h Figure 14 11 Example of Prescaler and Counter Operation in 8 Bit Timer with 8 Bit Prescaler Programmable Waveform Generation Mode or Programmable Wait One Shot Generation Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 222 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 e When the TWRC bit in TRBMR register is 0 write to reload register and counter Write 01h to TRBPRE register and 25h to TRBPR register Count source Afterjthe value
51. R8C M12A Group 9 Clock Generation Circuit 9 2 Registers Table 9 3 lists the Clock Generation Circuit Register Configuration Table 9 3 Clock Generation Circuit Register Configuration Register Name External Clock Control Register EXCKCR After Reset 00h Address 00020h Access Size High Speed Low Speed On Chip Oscillator Control Register OCOCR 00h 00021h System Clock f Control Register SCKCR 00h 00022h System Clock f Select Register PHISEL 00h 00023h Clock Stop Control Register CKSTPR 00h 00024h Clock Control Register When Returning from Modes CKRSCR 00h 00025h Oscillation Stop Detection Register BAKCR 00h 00026h High Speed On Chip Oscillator 18 432 MHz Control Register 0 FR18S0 Value when shipped 00064h High Speed On Chip Oscillator 18 432 MHz Control Register 1 FR18S1 Value when shipped 00065h High Speed On Chip Oscillator Control Register 1 FRV1 Value when shipped 00067h High Speed On Chip Oscillator Control Register 2 FRV2 Value when shipped 00068h R01UH0050EJ0200 Rev 2 00 May 18 2012 stENESAS Page 75 of 426 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 1 External Clock Control Register EXCKCR Address 00020h Bit b7 b6 b5 b4 b3 b2 b1 b Smo BET Ill DEET Teen After Reset 0 0 0 0 0 0 0 0 Bit Name Function Port P4_6 and P4_7 pin function
52. RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 363 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 8 2 3 Access Methods To set one of the following bits to 1 first write 0 and then 1 immediately Interrupts must be disabled between writing 0 and then writing 1 e The FMRO1 or FMRO2 bit in the FMRO register e The FMR13 bit in the FMRI register e The FMR20 FMR22 or FMR27 bit in the FMR2 register To set one of the following bits to 0 first write 1 and then 0 immediately Interrupts must be disabled between writing and then writing 0 The FMR16 or FMR17 bit in the FMR1 register 19 8 2 4 Rewriting User ROM Area When EWO mode is used and the supply voltage falls while rewriting a block where a rewrite control program is stored the rewrite control program is not be rewritten correctly As a result it may not be possible to rewrite the flash memory afterwards Use standard serial I O mode to rewrite this block 19 8 2 5 Programming Do not perform even a single additional write to an already programmed address 19 8 2 6 Entering Wait Mode or Stop Mode Do not enter wait mode or stop mode during suspend When the FST7 bit in the FST register is 0 busy while programming or erasing the flash memory do not enter wait mode or stop mode Do not set the FMR27 bit to 1 while the FMSTP bit flash memory stop bit in the FMRO register is 1 flash memory is stopped 19 8 2 7 Flash Memory Programming and Erase Vol
53. SSTR and RMPA instructions if an interrupt request is generated while the instruction is being executed the MCU suspends the instruction to start the interrupt sequence The interrupt sequence is performed as described below Figure 11 3 shows the Time Required for Executing Interrupt Sequence 1 2 3 4 5 6 7 The CPU obtains interrupt information interrupt number and interrupt request level by reading address 00000h Then for an INT interrupt and a key input interrupt the corresponding interrupt request flag is set to 0 no interrupt requested For any other peripheral interrupts the corresponding interrupt request flag remains 1 interrupt requested and does not change The FLG register is saved to a temporary register 1 in the CPU immediately before the interrupt sequence is entered Flags I D and U in the FLG register are set as follows e The I flag is O interrupt disabled e The D flag is 0 single step interrupt disabled e The U flag is set to 0 ISP selected However the U flag does not change if an INT instruction for software interrupt number 32 to 63 is executed The CPU internal temporary register 1 is saved on the stack The PC is saved on the stack The interrupt priority level of the acknowledged interrupt is set in the IPL The start address of the interrupt routine set in the interrupt vector is stored in the PC After the interrupt sequence is completed instructions are exe
54. The oscillation stop detection function is used to detect whether the XIN clock oscillation is stopped Whether this function is enabled can be selected by the XINBAKE bit in the BAKCR register Table 9 9 lists the Oscillation Stop Detection Function Specifications When the XIN clock is selected as the system base clock and bits CKSWIE to XINBAKE in the BAKCR register are set to 11b interrupt enabled oscillation stop detection function enabled if the XIN clock is stopped the states will change as follows e The low speed on chip oscillator oscillates However the value in the LOCODIS bit in the OCOCR register does not change e The SCKSEL bit in the CKSTPR register 0 LOCO e The XINHALT bit in the BAKCR register 0 XIN clock halted e An oscillation stop detection interrupt is generated Table 9 9 Oscillation Stop Detection Function Specifications Item Specification Clock frequency range for oscillation stop detection f XIN gt 2 MHz Condition for enabling the oscillation stop detection function Set bits CKSWIE through XINBAKE to 11b interrupt enabled oscillation stop detection function enabled Operation at oscillation stop detection An oscillation stop detection interrupt is generated 9 5 1 How to Use Oscillation Stop Detection Function e The oscillation stop detection interrupt shares a vector with the watchdog timer and voltage monitor 1 interrupts To use both the oscillation stop detection and
55. Timer RB2 14 2 W O Pins Table 14 2 lists the Timer RB2 Pin Configuration Table 14 2 Timer RB2 Pin Configuration Assigned Pin INTO P1_4 P4_5 l External trigger TRBO P1_3 P4_2 O Continuous pulse or one shot pulse output For details on INTO see 11 Interrupts RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 197 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 Registers Table 14 3 lists the Timer RB2 Register Configuration Table 14 3 Timer RB2 Register Configuration Register Name After Reset Address Access Size Timer RB Control Register TRBCR 000E0h Timer RB One Shot Control Register TRBOCR 000E1h Timer RB I O Control Register TRBIOC 000E2h Timer RB Mode Register TRBMR OOOE3h 8 bit timer with 8 bit prescaler TRBPRE 000E4h Timer RB Prescaler Register 16 bit timer Timer RB Primary Secondary Register Lower 8 Bits 8 bit timer with 8 bit prescaler 000E5h Timer RB Primary Register 16 bit timer Timer RB Primary Register Higher 8 Bits 8 bit timer with 8 bit prescaler 000E6h Timer RB Secondary Register 16 bit timer Timer RB Secondary Register Higher 8 Bits Timer RB Interrupt Control Register 000E7h R01UH0050EJ0200 Rev 2 00 RENESAS Page 198 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 1 Timer RB Control Register TRBCR Address 000E0h Bit b7 b6 b5 b4 b3 b2 b1 b Smo ITF TCSTF
56. Timer RC A D Conversion Trigger Control Register 000FCh Timer RC Waveform Output Manipulation Register RCOPR 000FDh OOOFEh OOOFFh Register Name Register Name 00140 00141 00142 00143 00144 00145 00146 00147h 00148h 00149h 0014Ah 0014Bh 0014Ch 0014Dh 0014Eh 0014Fh Oh 00150h th 00151 2h 00152 3h 00153 4h 00154 5h 00155 6h 00156 7h 00157 8h 00158 9h 00159 Ah 0015Ah Bh 0015Bh 0011Ch 0015Ch 0011Dh 0015Dh 0011Eh 0015Eh 0011Fh 0015Fh 00120h 00160 00121h 00161 00122h 00162 00123h 00163 00124h 00164 00125h 00165 00126h 00166 00127h 00167 00128h 00168 00129h 00169h 0012Ah 0016Ah 0012Bh 0016Bh 0012Ch 0016Ch 0012Dh 0016Dh 0012Eh 0016Eh 0012Fh 0016Fh 00130h 00170h 00131h 00171h 00132h 00172h 00133h 00173 00134h 00174 00135h 00175 00136h 00176 00137h 00177h 00138h 00178h 00139h 00179h 0013Ah 0017Ah 0013Bh 0017Bh 0013Ch 0017Ch 0013Dh 0017Dh 0013Eh 0017Eh 0013Fh 0017Fh Note 1 The blank areas are reserved No access is allowed
57. When a low level is input to the RESET pin before a reset is cleared the level will be recognized by the MCU as hardware reset and the reset state will not be cleared until a high level is input to the RESET pin When the HWRSTE bit is set to 0 the RESET PA_0 pin becomes the PA_0 I O port When this pin is used as an input port an external pull up resistor must be connected When used as an output port the open drain output function must be enabled to avoid conflicting with an external reset signal accidently See the following assembly language e Program example to set DA OU as an output port MOV B 00000000b HRPR MOV B 00000001b HRPR PAMCRE 1 un protect PAMCR register MOV B 00000001b PAMCR HWRSTE 0 PODA_0 1 MOV B 00000001b PDA PDA_0 1 PA_O output L MOV B 00000001b PA PA_O become hiz output open drain 12 11 2 I O Pins for Peripheral Functions In this MCU the pin assignment of the peripheral functions can be changed using the port function mapping register However multiple pins must not be assigned to the same peripheral function input at the same time Otherwise no signal can be input correctly RO1UH0050EJ0200 Rev 2 00 RENESAS Page 177 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 Timer RJ2 Timer RJ2 is a 16 bit timer that can be used for pulse output external input pulse width or period measurement and counting an internal source or external pu
58. When an external clock is selected the requirements must be met in either of the following states e The external clock is set to high when the CKPOL bit in the UOCO register is 0 transmit data is output on the falling edge and receive data is input on the rising edge of the transfer clock e The external clock is set to low when the CKPOL bit is 1 transmit data is output on the rising edge and receive data is input on the falling edge of the transfer clock 2 If an overrun error occurs the receive data b0 to b7 in the UORB register is undefined The UORIF bit in the UOIR register remains unchanged RO1UHO050EJ0200 Rev 2 00 RENESAS Page 286 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO Table 16 5 Register Registers and Settings Used in Clock Synchronous Serial UO Mode bO to b7 Function Set the transmit data bO to b7 The receive data can be read OER Overrun error flag bO to b7 Set the bit rate SMD2 to SMDO Set to 001b clock synchronous serial I O mode CKDIR Select an internal or external clock CLKO to CLK1 Select the UOBRG count source f1 f8 or f32 TXEPT Transmit register empty flag NCH Select the output type CMOS or N channel open drain output of the TXDO pin CKPOL Select the polarity of the transfer clock UFORM Select LSB first or MSB first Note TE Set to 1 to enable transmission
59. When read the value is read from the reload register In the 16 bit timer the TRBSC register is used to set the higher 8 bit secondary period used in programmable waveform and programmable wait one shot generation modes This setting can be made in timer mode and programmable one shot generation mode but it is not used for counter operation When read the value is read from the reload register The TRBSC register is configured with a master reload register structure so the reload register is written simultaneously while the count is stopped During the counter operation the timing for updating the reload register differs in each mode For details see Table 14 6 Reload Register Update Timing for Registers TRBPR and TRBSC in 8 Bit Timer with 8 Bit Prescaler and Table 14 7 Reload Register Update Timing for Registers TRBPRE TRBPR and TRBSC in 16 Bit Timer RO1UH0050EJ0200 Rev 2 00 RENESAS Page 205 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 8 Timer RB Interrupt Control Register TRBIR Address 000E7h Bit b7 b6 b5 b4 b3 b2 b1 b sma TREI After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Timer RB interrupt request flag 0 No interrupt requested 1 Interrupt requested Timer RB interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled TRBIF Bit Timer RB interrupt request flag Condition
60. _ Hoh TRCIOB CTS Bit in TRCMR register Figure 15 17 Example of One Shot Pulse Waveform Output Operation in PWM2 Mode RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 260 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 18 shows an Example of One Shot Waveform Output Operation in PWM2 Mode Count is Started by TRCTRG Input After the CTS bit in the TRCMR register is set to 1 count is started the increment is started on the rising edge of TRCIOA TRCTRG and the counter is changed to 0000h by a compare match with the TRCGRA register the count operation is stopped and a one shot waveform is output under the following conditions e Bits TCEG1 to TCEGO in the TRCCR2 register are set to 10b falling edge to set the falling edge of the TRCTRG input e The CSTP bit in the TRCCR2 register is set to 1 increment is stopped to stop the increment when a compare match with the TRCGRA register occurs e The CCLR bit in the TRCCRI register is set to 1 TRCCNT counter is cleared by input capture compare match A to clear the TRCCNT register by a compare match e The TOB bit in the TRCCR 1 register is set to O output value 0 to set the initial value of the output level to 0 TRCCNT register value FFFFh TRCGRA register TRCGRB register TRCGRC register 0000h TRCIOA TRCTRG High TRCIOB CTS Bit in TRCMR register Figure 15 18 Example of One Shot Waveform Output Operation in PWM2 Mode Count
61. execution Stop mode VC1E 0 VCOE 0 STPM 1 Topr 25 C Peripheral clock stopped VC1E 0 VCOE 0 STPM 1 Topr 85 C Peripheral clock stopped 1 Vcc 2 7 V to 4 0 V single chip mode output pins are open and other pins are connected to Vss 2 When the XIN input is a square wave 3 Veo 3 0 V 4 Set the system clock to 10 MHz or 4 MHz with the PHISEL register RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 381 of 426 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Timing Requirements Vcc 3 V Vss 0 V at Topr 25 C unless otherwise specified Table 20 21 External Clock Input XIN Standard Parameter Symbo Min 50 24 24 te XIN XIN input cycle time TWH XIN XIN input high width tWL XIN XIN input low width External Clock input Figure 20 8 External Clock Input Timing When Vcc 3 V Table 20 22 TRJIO Input Standard Parameter Symbo Min te TRJIO TRJIO input cycle time 300 twH TRJIO TRUIO input high width twL TRJIO TRUIO input low width tC TRJIO TRJIO input Figure 20 9 TRJIO Input Timing When Vcc 3 V RO1UHO050Ev0200 Rev 2 00 stENESAS Page 382 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 23 Serial Interface Standard Parameter Min te Ck CLKO input cycle time tw CKH
62. no wait states and the divisor is a register b 21 cycles for address match and single step interrupts Figure 11 4 Interrupt Response Time 11 4 6 IPL Change When Interrupt Request is Acknowledged When a maskable interrupt request is acknowledged the interrupt priority level of the acknowledged interrupt is set in the IPL For a software interrupt or special interrupt request the level listed in Table 11 10 is set in the IPL Table 11 10 IPL Value When Software Interrupt or Special Interrupt is Acknowledged Watchdog timer oscillation stop detection voltage monitor 1 7 Software address match single step Not changed RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 125 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 4 7 Saving Registers In the interrupt sequence the FLG register and PC are saved on the stack After a total of 16 bits higher 4 bits in the PC higher 4 IPL and lower 8 bits in the FLG register are saved on the stack the lower 16 bits in the PC are saved Figure 11 5 shows the Stack State Before and After Interrupt Request is Acknowledged Any other necessary registers should be saved by a program at the beginning of the interrupt routine The PUSHM instruction can save several registers in the register bank being used with a single instruction Note 1 Selectable from among registers RO R1 R2 R3 AO Al SB and FB MSB MSB Address Address SP Previous stack
63. of the TXDO pin CKPOL Set to 0 transmit data is output on the falling edge and receive data is input on the rising edge of the transfer clock UFORM Select LSB first or MSB first when transfer data is 8 bits long Set to 0 LSB first when transfer data is 7 bits or 9 bits long TE Set to 1 to enable transmission TI Transmit buffer empty flag RE Set to 1 to enable reception RI Receive complete flag Select the UARTO transmit interrupt source to be transmit buffer empty or transmit complete Set to 0 continuous receive mode disabled 1 The bits used are as follows e Bits 0 to 6 when transfer data is 7 bits long e Bits 0 to 7 when transfer data is 8 bits long e Bits 0 to 8 when transfer data is 9 bits long 2 The contents of the following are undefined Bits 7 and 8 when transfer data is 7 bits long and bit 8 when transfer data is 8 bits long R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 292 of 426 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 2 1 Operation Examples When transfer data is 8 bits long parity enabled one stop bit TC SE Transfer clock 1 I U U TE bit in i l UOC1 register i H Data is set in UOTB register i TI bit in U0C1 register From UOTB register to UARTO transmit register 4 ECH Stopped because TE bit is 0 TXDO TXEPT bit in UOCO register UOTIF bit in U
64. or leave the pin open Reset input User reset signal VSS XIN XOUT d g Seu Connect an oscillator 9 Notes 1 Controlled pins and external circuits vary depending on the programmer For details see the programmer manual 2 In this example modes are switched between single chip mode and standard serial I O mode by connecting a programmer 3 When operating on the on chip oscillator clock it is not necessary to connect an oscillation circuit Figure 19 21 Pin Handling Example in Standard Serial I O Mode 3 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 360 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 8 Notes on Flash Memory 19 8 1 ID Code Area Setting Example The ID code area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program The following shows a setting example To set 55h in all of the ID code area org OOFFDCH lword dummy 55000000h UND lword dummy 55000000h INTO lword dummy BREAK lword dummy 55000000h ADDRESS MATCH lword dummy 55000000h SET SINGLE STEP lword dummy 55000000h WDT lword dummy 55000000h RESERVE lword dummy 55000000h RESERVE Programming formats vary depending on the compiler Check the compiler manual RO1UH0050EJ0200 Rev 2 00 RENESAS Page 361 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 8 2 CPU Rewrite M
65. system MODE MODE Input a low level DI A TXD output Serial data output P16 RXD input Serial data input Other pins Data output Data input User reset signal Notes 1 Input a low level or a high level or leave the pin open Connect an oscillator In this example modes are switched between single chip mode and standard serial I O mode by controlling the MODE input with a switch 2 When operating on the on chip oscillator clock it is not necessary to connect an oscillation circuit See Appendix Figures 2 1 and 2 2 MF Ten Nine Cable M3A 0652CBL Connection Examples Figure 19 20 Pin Handling Example in Standard Serial I O Mode 2 RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 359 of 426 R8C M11A Group R8C M12A Group 19 Flash Memory Table 19 11 Pin Functions Flash Memory Standard Serial UO Mode 3 Pin Name Description VCC VSS Power supply input Apply the guaranteed program erase voltage to the VCC pin and 0 V to the VSS pin RESET Reset input Reset input P4_6 XIN P4_6 input clock input When operating with the on chip oscillator clock it is not P4_7 XOUT P4_7 input clock output necessary to connect an oscillation circuit Operation is not affected even if an external oscillator is connected in the user system MODE MODE Serial data I O Connect this pin to a flash programmer Other pins Input a low level or a high level
66. the flash memory can be read and the read lock bit status command can be sent For erase suspend only the flash memory can be programmed and the read lock bit status is enabled For program suspend only the read lock bit status of the flash memory is enabled Erase write 0 mode EWO mode and erase write 1 mode EW1 mode are available in CPU rewrite mode Table 19 5 lists the Differences between EWO Mode and EW1 Mode Table 19 5 Operating mode Differences between EWO Mode and EW1 Mode EWO Mode User mode EW1 Mode User mode Area where rewrite control program can be allocated User ROM User ROM Areas where rewrite control program can be executed RAM The rewrite control program must be transferred before being executed User ROM or RAM Rewritable area User ROM User ROM Other than blocks which contain the rewrite control program Software command restrictions Program and block erase commands cannot be executed to any block which contains the rewrite control program Mode after programming or block erasure or after entering suspend Read array mode Read array mode CPU state during programming block erase The CPU operates The CPU is put in the hold state I O ports retain the states before the command is executed Flash memory status detection Read bits FST2 to FST7 in the FST register by a program Read bits FST2 to FST7 in the FST register by a program
67. 0 data present in the UOTB register Receive start conditions To start reception the following requirements must be met 1 e The RE bit in the UOC1 register must be 1 reception enabled e The TE bit in the UOC1 register must be 1 transmission enabled e The TI bit in the UOC1 register must be 0 data present in the UOTB register Interrupt request e For transmission One of the following can be selected generation timing The UOIRS bit in the UOC1 register is 0 transmit buffer is empty When data is transferred from the UOTB register to the UARTO transmit register at start of transmission The UOIRS bit in the U0C1 register is 1 transmission is completed When data transmission from the UARTO transmit register is completed e For reception When data is transferred from the UARTO receive register to the UORB register at completion of reception Error detection Overrun error 2 This error occurs if the next data reception is started and the 7th bit is received before the UORB register is read Selectable functions e CLK polarity selection The output and input timing of transfer data can be selected to be either the rising or the falling edge of the transfer clock e LSB first or MSB first selection The start bit can be selected to be bit 0 or bit 7 when transmission and reception are started e Continuous receive mode selection Reading the UORB register enables reception at the same time Notes 1
68. 0 voltage detection 1 detection levels selectable Watchdog timer e 14 bits x 1 with prescaler e Reset start function selectable e Count source protection function selectable e Periodic timer function selectable Clock generation circuits e 3 circuits XIN clock oscillation circuit high speed on chip oscillator with frequency adjustment function low speed on chip oscillator e Oscillation stop detection XIN clock oscillation stop detection function Clock frequency divider circuit integrated Power control e Standard operating mode e Wait mode CPU stopped peripheral functions in operation e Stop mode CPU and peripheral functions stopped Interrupts e Number of interrupt vectors 69 e External interrupt inputs 8 INT x 4 key input x 4 e Priority levels 2 I O ports Programmable I O ports e CMOS I O 17 pull up resistor selectable e High current drive ports 8 Timer Timer RJ2 16 bits x 1 Timer mode pulse output mode output level inverted every period event counter mode pulse width measurement mode pulse period measurement mode Timer RB2 8 bits x 1 with 8 bit prescaler or 16 bits x 1 selectable Timer mode programmable waveform generation mode PWM output programmable one shot generation mode programmable wait one shot generation mode Timer RC 16 bits x 1 with 4 capture compare registers Timer mode output compare function input capture funct
69. 0 0 0 0 0 0 0 Bit Name Function Port PA_0 direction bit 0 Input mode functions as an input port 1 Output mode functions as an output port Nothing is assigned The write value must be 0 The read value is 0 The PDA register is used to select whether PA_0 is used as input or output 12 6 2 Port PA Register PA Address 000B3h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol TTT P After Reset 0 0 0 0 0 0 0 0 Bit Name Function Port DA O bit 0 Low level 1 High level Nothing is assigned The write value must be 0 The read value is 0 The PA register is an I O port data register Data input to and output from external devices are accomplished by reading from and writing to the PA register The PA register consists of a port latch to retain output data and a circuit to read the pin states The value written to the port latch is output from the pin RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 164 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 6 3 Port PA Mode Control Register PAMCR Address 000C5h Bit b7 b6 b5 b4 b3 b2 b1 b Smo pse PODAD After Reset 0 0 0 1 0 0 0 1 Bit Name Function Port DA D open drain control bit 1 0 Not open drain 1 Open drain Nothing is assigned The write value must be 0 The read value is 0 Hardware reset enabled bit 0 Port PA_O functions as an I O port 1
70. 00h and then FFh are written to the WDTR register e Underflow Count start conditions The operation of the watchdog timer after a reset is selected by the WDTON bit in the OFS register address OFFFFh e When the WDTON bit is 1 watchdog timer is stopped after reset The watchdog timer and the prescaler are stopped after a reset and only start counting when the WDTS register is written e When the WDTON bit is 0 watchdog timer is automatically started after reset The watchdog timer and the prescaler automatically start counting after a reset Count stop conditions When wait mode or stop mode is entered while the count source is the CPU clock Operation at underflow Note e When the RIS bit in the RISR register is 0 Watchdog timer interrupt e When the RIS bit in the RISR register is 1 Watchdog timer reset See 6 3 5 Watchdog Timer Reset 1 The watchdog timer is initialized by writing 00h and then writing FFh to the WDTR register The prescaler is initialized after a reset This results in discrepancies in the watchdog timer period due to the prescaler RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 68 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 3 3 When Count Source Protection Mode is Enabled When count source protection mode is enabled the count source for the watchdog timer is the low speed on chip oscillator clock If the CPU clock is stopped when a program runs out of control
71. 1 Peripheral function Single step Address match Figure 11 7 Hardware Interrupt Priority RO1UHO050EJ0200 Rev 2 00 zeENESAS Page 128 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 4 10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt Figure 11 8 shows the Interrupt Priority Level Selection Circuit Priority level of interrupts Level 0 initial value Highest A T Priority of peripheral function interrupts if priority levels are same UARTO reception A D conversion UARTO transmission Key input Output signal to determine interrupt request levels Be gt Interrupt request acknowledgement Address match Watchdog timer Oscillation stop detection Voltage monitor 1 Figure 11 8 Interrupt Priority Level Selection Circuit RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 129 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 5 INT Interrupt 11 5 1 INTi Interrupt i 0 to 3 The INTi interrupt is generated by an INTi input To use the INTi interrupt set the INTiEN bit in the INTEN register is to 1 enabled The edge polarity can be selected by bits INTiSA to INTiSB in the ISCRO register The input pins used as the INTO to INT2 input can be selected Inputs can be passed through a digital filter with three dif
72. 1 count is started is written to the TSTART bit in the TRBCR register while the count is stopped the TCSTF bit in the TRBCR register remains 0 count is stopped for two to three cycles of the count source Do not access the registers associated with timer RB2 other than the TCSTF bit until this bit is set to 1 count is in progress The count is started on the first active edge of the counter source after the TCSTF bit is set to 1 After 0 count is stopped is written to the TSTART bit during count operation the TCSTF bit remains 1 for two to three cycles of the count source When the TCSTF bit is set to 0 the count is stopped Do not access the registers associated with timer RB2 other than the TCSTF bit until this bit is set to 0 Note 1 Registers associated with timer RB2 TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBPR and TRBSC e In timer mode do not set both the TRBPRE and TRBPR registers to 00h at the same time e When the TSTART bit in the TRBCR register is 0 count is stopped change the values of registers TRBPRE TRBPR and TRBSC then wait for at least two cycles of the system clock f before setting the TSTART bit in the TRBCR register to count is started e When the TSTART bit in the TRBCR register is 1 count is started or the TCSTF bit is 1 count is in progress do not change the values in registers TRBIOC and TRBMR and the TRBIE bit in the TRBIR register e Make sure the TCSTF bit in the TRBCR register is 1 cou
73. 1 revised 177 Figure 13 1 and Table 13 2 revised 178 Table 13 3 and 13 3 1 revised 181 TOPCR Bit and Table 13 6 revised 183 13 3 6 revised 186 13 4 3 revised 187 13 4 4 revised 191 386 13 5 21 7 revised 193 388 Figures 13 10 13 11 21 6 and 21 7 revised 195 14 2 revised 196 Table 14 3 revised 197 14 3 1 Notes 2 and 3 deleted 217 Tables 14 6 and 14 7 revised 228 Table 15 2 revised 230 15 2 1 revised 231 15 2 2 revised 232 15 2 3 revised 233 15 2 4 revised 238 15 2 9 revised 244 15 3 1 revised 252 Figure 15 12 revised 259 Figure 15 19 revised 262 toggle output from TRCIOD pin gt toggle output from TRCIOB pin 263 Figure 15 23 revised 264 Figures 15 24 and 15 25 revised 265 Figure 15 26 revised 266 Figure 15 27 revised 271 391 15 6 2 15 6 4 15 6 7 21 9 2 21 9 4 and 21 9 7 revised 275 Figure 16 2 revised 280 16 2 6 revised 289 Figure 16 6 revised 291 Table 16 8 Note 1 revised 295 Table 17 1 revised 296 Figure 17 1 and Table 17 2 revised 298 17 2 1 revised 299 17 2 2 revised 300 17 2 3 revised 301 17 2 4 revised REVISION HISTORY R8C M11A Group R8C M12A Group User s Manual Hardware Description Summary Nov 30 2010 302 17 2 5 revised 303 17 3 17 3 1 1 and Figure 17 2 revised 304 Table 17 6 revised the last Table 17 7 deleted 17 3 1 2 and Figure 17 3 revised 305 17 3 2 and Figure 17 4 revised 306 17 3 3 and Figure 17 5 revised 307 17 3 4 and Figure 17 6 revised 308 17
74. 15 2 1 Timer RC Counter TRCCNT eree er ee aE Eere oeri ENEE 232 15 2 2 Timer RC General Register A B C and D TRCGRA TRCGRB TRCGRC and TRCGRD 233 15 2 3 Timer RC Mode Register TREM R a e eana ari aeaea Pear e Ee EPEa osooobees EEE ES EES ARENAER EASi 235 15 2 4 Timer RC Control Register 1 TRCOCR1 merriami aie nta Eei E Eo eE r ENEE ea EE EERE E Saias 236 15 2 5 Timer RC Interrupt Enable Register TRCIER s sssesseeesseresesresrsssseesesrsresesertssreresreestesertrsrersreeteresreresrt 237 15 2 6 Timer RC Status Register TRCSR enera EE a i E 238 15 2 7 Timer RC I O Control Register 0 TRCIORO 0 e cee eee ceesecsseeesseceneecereeeseceneesseceaeeceeeecaeeeeeceneeeaeenaeeees 239 15 2 8 Timer RC I O Control Register 1 TRCIOR1 oo ee eee ceeccceseeeseceneeceeeeeseceeneesaecesceceeeecaaeeeaeceseeesaeceneeees 240 15 2 9 Timer RC Control Register 2 TRCCR2 oo cee rinnen EE aE ERE A E E 241 15 2 10 Timer RC Digital Filter Function Select Register TRCDE 0 00 eeceeeceseeeeeceecaeceseaeceseseeneensees 242 15 2 11 Timer RC Output Enable Register TRCOER A 243 15 2 12 Timer RC A D Conversion Trigger Control Register TRCADCR AAA 244 15 2 13 Timer RC Waveform Output Manipulation Register TRCOPR AA 245 15 3 Operat OT EE 246 al Timer Mode eee eare a e E EE E EEE E EE REEE A E EEE 247 153 2 PWM Mode EE 251 153 3 C GA RE 255 15 4 selectable Functrons i3i5 si ee aia ee A E as 262 15 4 1 Input Digital Fil
75. 3 5 and Figure 17 7 revised 309 17 4 revised the last 17 5 and the last Figures 17 8 to 17 9 deleted 310 394 17 5 1 17 5 2 21 11 1 21 11 2 revised the last Figure 17 10 the last Figure 21 6 deleted 311 395 17 5 3 21 11 3 revised 313 Table 18 2 Note 1 added 318 Table 18 4 revised 332 19 5 5 revised 339 19 6 6 2 and Figure 19 8 revised 340 Figure 19 9 revised 341 Figure 19 10 revised 342 When the FMR22 bit is in EW1 mode and Figure 19 11 added 343 19 6 6 3 and Figure 19 12 revised 344 Figure 19 13 revised 345 Figure 19 14 revised 346 When the FMR22 bit is in EW1 mode and Figure 19 15 added the last Figures 19 20 and 19 21 moved to 10 Power Control 353 Figure 19 20 revised 361 Table 20 3 revised 366 Tables 20 10 and 20 11 revised 402 to 403 Package Dimensions added 404 Appendix Figure 2 1 revised 405 Appendix Figure 2 2 revised May 18 2012 4 Under development deleted 9 Table 1 6 Voltage detection circuit deleted 24 4 Description revised 28 5 2 3 b3 Function revised 5 2 4 Note 1 added 29 5 2 5 and 6 2 2 CWR Bit Description revised 33 Table 5 2 revised 78 9 2 3 Bits PHISSELO to PHISSEL2 Description revised 79 9 2 4 b7 to bO Bit Name revised 80 9 2 5 STPM and WCKSTP Bit Description revised 81 9 2 6 Note 2 added 82 9 2 6 Bits CKSTO to CKST3 Description revised 85 9 3 1 Description Figure 9 3 revised 88 9 4 5 Description revised REVISION HISTORY R8C M11A
76. 4 4 kQ maximum RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 314 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter Sensor equivalent circuit RO Figure 17 8 Analog Input Pin and External Sensor Equivalent Circuit 17 5 3 Register Setting e Registers ADMOD and ADINSEL must be written only when A D conversion is stopped e Do not enter stop mode during A D conversion e Do not enter wait mode during A D conversion while the WCKSTP bit in the CKSTPR register is 1 system clock is stopped in wait mode e Do not set the FMSTP bit in the FMRO register to 1 flash memory is stopped or the FMR27 bit in the FMR2 register to 1 low current consumption read mode enabled during A D conversion e During A D conversion if the ADST bit in the ADCONDO register is set to 0 A D conversion stops by a program to forcibly terminate the conversion the conversion result from the A D converter will be undefined and no interrupt will be generated The value of the ADi register i 0 or 1 which is not engaged in A D conversion may also be undefined If the ADST bit is set to 0 by a program do not use any of the values of the ADi register e When using the A D converter it is recommended that the average of the conversion results be taken RO1UH0050EJ0200 Rev 2 00 RENESAS Page 315 of 426 May 18 2012 R8C M11A Group R8C M12A Group 18 Comparator B 18 Comparator B Comparator B consists of two independent comparato
77. AAA 199 14 3 2 Timer RB One Shot Control Register TRBOCR AA 200 14 3 3 Timer RB I O Control Register TRBIOC AA 201 14 3 4 Timer RB Mode Register TRBMR A 202 14 3 5 Timer RB Prescaler Register TRBPRE AA 203 14 36 Timer RB Primary Register TRBPR eigtl edeeedeegieee deed teed 204 14 3 7 Timer RB Secondary Register TRBSC oo eceeeeseeseecsecseecaeceecseeseceseeseeseceseeeeecaessaecaecaeeaeeeensees 205 14 3 8 Timer RB Interrupt Control Register TRBIR AAA 206 14 4 Operation eisene a T EEN EE DEES 207 PAPAL Timer Mode verii i T E E ENEE an E E E dean cosh NEEN 207 14 4 2 Programmable Waveform Generation Mode A 209 14 4 3 Programmable One Shot Generation Mode ssessessesesseeesesresrsresrsrsseerrstenrsrrsrertnsernrenrenenentnseneesesreresr 212 14 4 4 Programmable Wait One Shot Generation Mode esessesessssesrsssseesseeresresesresrerrstentrreserrrsrerrssrersrenreresre 215 14 5 Selectable ul ee E 218 14 5 1 Configuration and Update Timing for Registers TRBPRE TRBPR and TRBSC 0 eee 218 A 6 14 5 2 Prescaler and Counter Using TWRC Bit oo eee eeeeeeecseescecaecaeeaeceececeseeeeeeseseeecaessaecaecaseeseeeeees 220 145 3 TOCNT Bit Setting and Pim States ENEE ENEE REENEN AE 225 14 6 Interrupt Request ege end ceed Sinha A a eS 226 14 7 INTO Input Trigger BEEN eegene get eet 226 14 8 Notes on Timer R B2 ecoe vg escsitig EES 227 Vie Mert EEE enee ie eebe Eed ee ee ee 229 15 1 Ve EE 229 15 2 LE 232
78. Auto erase can be restarted by setting the FMR21 bit to 0 restart Address match Do not use during auto erasing or auto programming UND INTO and BRK instructions Single step Watchdog timer When an interrupt request is acknowledged auto erase or auto programming is forcibly stopped Oscillation stop immediately and the flash memory is reset After the specified period the flash memory is detection restarted before interrupt handling is started Since auto erase or auto programming is forcibly stopped the correct values may not be read from the block being auto erased or the address being auto programmed After the flash memory is restarted execute auto erase again and verify it complete normally The watchdog timer does not stop while the command is executing so interrupt requests may be generated Initialize the watchdog timer periodically using the erase suspend function Since the flash memory control registers are initialized in this case these registers must be set again 1 FMR20 FMR21 FMR22 Bits in FMR2 register Note 1 Registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated while the flash memory is busy When the FMR01 bit in the FMRO register is 1 CPU rewrite mode enabled and the FMSTP bit is 1 flash memory is stopped registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt
79. B An RnH e MOV W An Rn Figure 19 15 Block Erase Flowchart in EW1 Mode Flash Ready Status Interrupt Disabled and Suspend Enabled R01UH0050EJ0200 Rev 2 00 RENESAS May 18 2012 Page 352 of 426 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 6 5 Lock Bit Program This command is used to set the lock bit for any block in the program ROM area to 0 locked When 77h is written as the first command and DOh is written to the start address in the block with the second command 0 is written to the lock bit in the specified block The address for the first command must be the same as that for the second which specifies the start address in the block Figure 19 16 shows the Lock Bit Program Flowchart The lock bit status lock bit data can be read using the read lock bit status command The FST7 bit in the FST register can be used to confirm whether writing to the lock bit is completed For details on the lock bit function and how to set the lock bit to 1 not locked see 19 6 5 Data Protect Function Write the command code 77h Write DOh to the start address in the block H Full status check Completed FST7 Bit in FST register Figure 19 16 Lock Bit Program Flowchart RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 353 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 6 6 Read Lock Bit Status Command This command is used to read the lock bit status for any block in the progra
80. CV ADTA ege ss de Sota si ita SE EE A EE REESEN cae oebtae 178 13 2 W O PNS eea eeo Hees AS EEE E E ag ela eat Sod hile a aes ulti kote 179 13 3 Registers snn ea a ENEE AER neta ane E 180 13 3 1 Timer RJ Counter Register TRJ Timer RJ Reload Register 0 cece esecseceeeseceeceseeeeceeeeseseaeeaeeeaes 180 13 3 2 Timer RJ Control Register TRICR A 181 13 3 3 Timer RJ I O Control Register TRJIOC A 182 13 3 4 Timer RJ Mode Register TRIMR AAA 184 13 3 5 Timer RJ Event Select Register TRIISR sisiccssscesscdesscosstevessisssozeseossssveseosgeosngesvscovaseoadcunasounosvassbesabeniess 184 13 3 6 Timer RJ Interrupt Control Register TRIIR oc eee eeecseeeeecaeceseeaececeseeeeseeeeseeecaessaecaecaeeseeeensees 185 13 4 Operation eet Agedro Seed eege eege deeg Eder ee 186 13 4 1 Reload Register and Counter Rewrite Operation 0 0 eee eceeeeeceseeeseceecaecseeseceeceseceseeseseeeeseseeseaeeeaes 186 DS ALD gt me MO de ege ele EE EE ES 187 13 24 32 Pulse Ree EE 188 13 44 Event Counter Mode cise cisoncatsccteoviceces Ze sek au titeonecoanttadeh cvavost seh Eege EE ene 189 13 4 5 Pulse Width Measurement Mode A 190 13 4 6 Pulse Period Measurement Mode A 191 134 7 Output Settings for Each Mode stees ergeet geg ged E Seege deed ney 192 13 5 INOtes on Timer RE 193 E Zenn un EE 196 14 1 OVV E EEN 196 14 2 WO Pans E A E E EE E E SE E EEN 197 14 3 IGA TE EEEE E A O E RA Re ee ees aA GER E E 198 14 3 1 Timer RB Control Register TRBCR
81. Comparison between R8C M11A Group and R8C M12A Group The explanations in 1 1 3 and subsequent sections apply to the R8C M12A Group specifications only unless otherwise specified Table 1 1 Interrupts Specification Comparison between R8C M11A Group and R8C M12A Group Function External interrupt inputs R8C M11A Group 6 INT x 3 key input x 3 R8C M12A Group 8 INT x 4 key input x 4 I O ports Number of pins 14 Non provided pins P1_O ANO TRCIOD KIO P3_3 IVCMP3 TRCCLK INT3 P3_4 IVREF3 TRCIOC INT2 P3_5 TRCIOD Kl2 VCOUT3 P4_2 TRBO TXDO KI3 P4_5 INTO ADTRG 20 Number of CMOS I O ports 11 Non provided ports P1_0 P3_3 P3_4 P3_5 P4_2 P45 Number of high current drive ports 5 Non provided ports P3_3 P3_4 P3_5 A D converter Number of A D channels 5 channels Non provided port ANO 6 channels Comparator B Number of channels Comparator B1 Comparator B1 comparator B3 RO1UHO0O50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 2 of 426 R8C M11A Group R8C M12A Group 1 Overview Table 1 2 lists the R8C M11A Group Register Settings These settings correspond to the specification differences between the R8C M11A Group and R8C M12A Group Table 1 2 Related Function Register Name INTEN Address 00038h R8C M11A Group Register Settings INT3EN Setting Method for Access Reserved bit Set to 0 INTFO 0003Ah
82. Counter Operation When the TRCGRA register for period setting is set as an output compare register and the CCLR bit in the TRCCRI register is set to 1 a period count operation is performed When the count value matches the TRCGRA register the TRCCNT register changes to 0000h and the IMFA bit in the TRCSR register is set to 1 If the corresponding IMIEA bit in the TRCIER register is 1 interrupt request IMIA by IMFA bit in TRCSR register is enabled at this time an interrupt request is generated The TRCCNT register continues increment operation from 0000h Figure 15 3 shows an Example of Period Counter Operation TRCCNT register value TRCGRA register 0000h CIS ee Flag clearing by software IMFA CTS Bit in TRCMR register IMFA Bit in TRCSR register Figure 15 3 Example of Period Counter Operation RO1UH0050EJ0200 Rev 2 00 RENESAS Page 247 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC By setting the general register as an output compare register low level high level or toggle output is performed by compare matches A to D from pins TRCIOA TRCIOB TRCIOC TRCIOD Figure 15 4 shows an Example of Low Level and High Level Output Operation The TRCCNT register is used for the free running count operation a low level is output at compare match B and a high level is output at compare match A When the set level and the pin level are the same the pin level remains unchanged e TOA bit is 0 and
83. Debugging Emulator Open collector buffer 4 7 kQ or more gt R8C M12A Group Connect oscillation CSS T circuit 1 4 7kQ 10 13 RESET E8a emulator ROEQOOO8AKCE00 Note 1 When operating on the on chip oscillator clock it is not necessary to connect an oscillation circuit Appendix Figure 2 4 E8a Emulator ROEQOOO8AKCE00 Connection Example 2 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 420 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 3 Oscillation Evaluation Circuit Example Appendix 3 Oscillation Evaluation Circuit Example Appendix Figures 3 1 and 3 2 show Oscillation Evaluation Circuit Examples Connect oscillation circuit 1 R8C M11A Group Note 1 After a reset the XIN clock is stopped Write a program to oscillate the XIN clock Appendix Figure 31 Oscillation Evaluation Circuit Example 1 Connect oscillation circuit 0 R8C M12A Group Note 1 After a reset the XIN clock is stopped Write a program to oscillate the XIN clock Appendix Figure 3 2 Oscillation Evaluation Circuit Example 2 RO1UHO050EJ0200 Rev 2 00 RENESAS Page 421 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 4 Comparison between R8C M12A Group and R8C M13B Group Appendix A Comparison between R8C M12A Group and R8C M13B Group Appendix Table 4 1 lists Specification Comparison between R8C M12A Group and R8C M13B Group For details on the R8C M13
84. EENS as Suegbssededsvensceustosecsspeacs s 275 ISt TRECNT Register a aere Boia ties Se Sad Hae a es 275 P72 TREK egene Eege Ee Seed 275 15 7 32 TRCSR Register 2 is eh Sun int Sie eR ed ed een AR a eA ege es 213 WSFA Count SourceS Witching eessen 275 13 7 5 Input Capture Functioning nirereseta E EE E E EEE E eaves EEE R EE EEES 276 15 7 6 TRCMR Register in PWM2 Mode oo cc eeeeeecneeeseceeesaecaeceaecsecesesecseeseeeeeeeseaeeseesaecaaeeaseaeseesees 276 NZ MS TCRERE G18 tet eet ie eeben 276 15 7 8 Mode Swtchng seseris ensirep o shots o Ee EEK EE EEE r PEE aer EET r EE EEA EEO an ESEE 276 15 7 9 Procedure for Setting Registers Associated with Timer RC essseessseeesrsrrererrererrsreererenesenrerrnsenresenreresre 276 16 Serial Interface UARTO 00 cece eeceeeeeeeeneeeeeeeneeeaeeeseeecanesuaeessaeesneesseeseseessaeseeeeseaeeeaeeseeessanesseeeeaes 277 16 1 Eege eege a a ad a dats ee tel AE cl ee eet 277 16 2 LE 280 16 2 1 UARTO Transmit Receive Mode Register UOMR AA 280 16 2 2 UARTO Bit Rate Register UOBRG oo cceseeesececesecneceseesecesceseseaeesescaecaaesaecseceseesecneseaeeaeeeaes 281 16 2 3 UARTO Transmit Buffer Register UOTB 0 eee esceceneecseceneeceseecsaeeseeeseecsaeseneecreseaeceseecreseneeeeneens 281 16 2 4 UARTO Transmit Receive Control Register 0 U0CO oe eee eeseceeeceseeenceeeneececeeeeceeeeesaeeeaeeceeeeneeeeneen 282 16 2 5 UARTO Transmit Receive Control Register 1 UCI 283 16 2 6 UARTO Receive B
85. Flash memory stop bit in wait mode When the WTFMSTP bit is flash memory is stopped in wait mode the flash memory is stopped when wait mode is entered To perform A D conversion in wait mode set the WTFMSTP bit to 0 flash memory operates in wait mode FMR13 Bit Lock bit disable select bit When the FMR13 bit is set to 1 lock bit disabled the lock bit is disabled When the FMR13 bit is set to 0 the lock bit is enabled For details on the lock bit see 19 6 5 Data Protect Function The FMR13 bit is used to enable the lock bit function only and the lock bit data remains unchanged However when a block erase command is executed while the FMR13 bit is 1 lock bit disabled the lock bit data set to 0 lock bit enabled is changed to 1 lock bit disabled after erase completes Conditions for setting to 0 e When the FST7 bit in the FST register is changed from 0 busy to 1 ready and the program erase command completes e When the FST7 bit in the FST register is changed from 0 busy to 1 ready and program suspend erase suspend is entered e When a command sequence error occurs e When the FMRO1 bit in the FMRO register is set to 0 CPU rewrite mode disabled e When the FMSTP bit in the FMRO register is set to 1 flash memory is stopped e When the CMDRST bit in the FMRO register is set to 1 erase write sequence reset Condition for setting to 1 e When is written to this bit by a program FMR16 Bit Data flash bl
86. Group R8C M12A Group User s Manual Hardware Description Summary May 18 2012 90 Figure 9 6 revised 97 10 3 Description revised 99 Figure 10 2 title revised 106 Figure 10 6 revised 108 389 10 6 1 10 6 2 21 4 1 and 21 4 2 revised 115 118 11 2 5 and 11 2 9 Description revised 119 11 2 10 and 11 2 11 Description revised 130 11 5 1 Description and Table 11 11 Assigned Pin revised 131 Figures 11 9 and 11 10 revised 136 391 Figures 11 13 and 21 1 Note 2 added 139 394 11 9 7 Changing Interrupt Priority Levels and Flag Registers and 21 5 7 Changing Interrupt Priority Levels and Flag Registers added 177 395 12 11 2 and 21 6 2 Description revised 179 Figure 13 1 revised 180 13 3 1 Note 2 revised Note 3 added 181 13 3 2 Note 2 revised Description added 182 13 3 3 b6 and b7 Function revised 183 13 3 3 Bits TIOGTO to TIOGT1 Description added 184 13 3 4 Note 1 deleted Description added 186 13 4 1 and Figure 13 2 revised 187 Figure 13 3 revised 188 Figure 13 4 revised 191 13 4 6 Description Figure 13 7 revised 193 396 13 5 and 21 7 3 revised 5 deleted 13 added 199 14 3 1 Note 1 revised 200 14 3 2 b0 and b1 Function revised description added 201 Table 14 4 Timer mode revised 202 14 3 4 Note 2 revised 204 14 3 6 Note 1 added 205 14 3 7 Description revised 207 14 4 1 Description revised 209 14 4 2 Description revised 212 14 4 3 Description revised 215 14 4 4 Description revised 220
87. IMFB bit in TRCSR register is enabled Input capture compare match C Interrupt request IMIC by IMFC bit in TRCSR interrupt enable bit register is disabled Interrupt request IMIC by IMFC bit in TRCSR register is enabled Input capture compare match D Interrupt request IMID by IMFD bit in TRCSR interrupt enable bit register is disabled Interrupt request IMID by IMFD bit in TRCSR register is enabled Nothing is assigned The write value must be 1 The read value is 1 Timer overflow interrupt enable bit 0 Interrupt request FOVI by OVF bit in TRCSR register is disabled 1 Interrupt request FOVI by OVF bit in TRCSR register is enabled RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 237 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 6 Timer RC Status Register TRCSR Address 000F5h Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo OF WFD WFC Me MA After Reset 0 1 1 1 0 0 0 0 Bit Name Function Input capture compare match A flag Condition for setting to 0 Input capture compare match B flag e When 0 is written to this bit after reading it as 1 1 Condition for setting to 1 e See Table 15 9 Conditions for Setting Each Flag to 1 Nothing is assigned The write value must be 1 The read value is 1 Input capture compare match C flag Input capture compare match D flag Timer overflow flag Condition for setting
88. Note however that the same address must not be programmed more than once before completion of an erase overwriting prohibited 3 This indicates the number of times up to which all electrical characteristics can be guaranteed after the last programming erase operation Operation is guaranteed for any number of operations in the range of 1 to the specified minimum Min 4 In a system that executes multiple programming operations the actual erase count can be reduced by shifting the write addresses in sequence and programming so that as much of the flash memory as possible is used before performing an erase operation For example when programming in 16 byte units the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one operation It is also advisable to retain data on the number of erase operations for each block and establish a limit for the number of erase operations performed 5 If an error occurs during a block erase execute a clear status register command and then a block erase command at least three times until the erase error does not occur 6 For information on the program erase failure rate contact a Renesas technical support representative 7 The data hold time includes the time that the power supply is off and the time the clock is not supplied R01UH0050EJ0200 Rev 2 00 ztENESAS Page 371 of 426 May 18 2012 20 Electrical Characteristics R8C M11A Group R8C M12A Group 2
89. Note 1 00034h Periodic Timer Interrupt Control Register Note 00h 1 See the description of the individual registers 8 2 1 Watchdog Timer Function Register RISR Address 00030h Bit b After Reset 1 00035h 7 b6 b5 b4 b3 b2 b1 bO Symbol The above applies when the CSPROINI bit in the OFS register is 0 After Reset 0 0 0 0 0 0 0 The above applies when the CSPROINI bit in the OFS register is 1 Symbol Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 WDT underflow detection flag 1 Watchdog timer underflow 1 0 No watchdog timer underflow Notes WDT interrupt reset switch bit 0 Watchdog timer interrupt 1 Watchdog timer reset 2 1 After reading this bit as 1 wait at least one cycle of the count source before writing 0 to it 2 The RIS bit is set to 1 by writing 1 by a program but writing O to this bit has no effect When the CSPRO bit in the CSPR register is 1 count source protection mode enabled the RIS bit is automatically set to 1 Set the PRC1 bit in the PRCR register to 1 write enabled before rewriting the RISR register UFIF Bit WDT underflow detection flag Condition for setting to 0 e When 0 is written to this bit Conditions for setting to 1 e When the watchdog timer underflows while the RIS bit is 0 watchdog timer interrupt e When a refresh is executed during the peri
90. Operation RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 321 of 426 May 18 2012 R8C M11A Group R8C M12A Group 18 Comparator B 18 3 2 Comparator Bi i 1 or 3 Setting Procedure and Operation Example Comparator B1 and comparator B3 operate independently of each other Table 18 4 lists the Procedure for Setting Registers Associated with Comparator B Table 18 4 Procedure for Setting Registers Associated with Comparator B Register Select the functions of pins IVCMPi an Setting Value d IVREFi For the settings see 12 I O Ports WCBiINTR WCBIF1 to WCBiFO e Enable or disable the digital filter Select the sampling frequency WCMPR WCB1MO 1 operation enabled WCB3M0 Wait for the comparator stabilization time 100 us max ILVL2 ILVL21 to ILVL20 When an interrupt is used Select the interrupt priority level for comparator B1 ILVL25 to ILVL24 When an interrupt is used Select the interrupt priority level for comparator B3 WCBiINTR WCBIiS1 to WCBiSO When an interrupt is used Select the input polarity WCBiINTR WCBiF 0 no interrupt requested WCBiINTR WCBIINTEN When an interrupt is used 1 interrupt enabled Figure 18 3 shows an Example of Comparator Bi i 1 or 3 Operation When the analog input voltage is higher than the reference input voltage the WCBiOUT bit in the WCMPR register is set to 1 When the analog input voltage is
91. P1_3 P1_4 P1 When drive loL 2 mA P3_3 P3_4 P3_5 P3 capacity is high When drive loL 1 mA capacity is low P1_0 P1_1 P1_6 P1 loL 1 mA P4_2 P4_5 P4_6 P4_7 PA_O Hysteresis INTO INT1 INT2 INT3 Vcc 2 2 V KIO KI KI2 KI3 TRJIO TRCIOA TRCIOB TRCIOC TRCIOD RXDO CLKO RESET Vcc 2 2 V IIH Input high current V 2 2 V Vcc 2 2 V liL Input low current Vi 0 V Vcc 2 2 V RPULLUP Pull up resistance Vi OV Vcc 2 2 V Dr Feedback resistance VRAM RAM hold voltage In stop mode Notes 1 1 8 V lt Vcc lt 2 7 V and Topr 20 C to 85 C N version 40 C to 85 C D version f XIN 5 MHz unless otherwise specified 2 High drive capacity can also be used while the peripheral output function is used RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 384 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 26 DC Characteristics 6 1 8 V lt Vcc lt 2 7 V Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified Parameter Power supply current 1 Notes High speed clock mode Condition Oscillation Circuit On Chip Oscillator XIN 2 High Speed Low Speed 125 kHz CPU Clock No division Low Power Consumption Setting Standard Typ 3 125 kHz Division by 8
92. PD2_2 PD2_1 PD2_0 Register added P2 000B0h P2_2 P2_1 P2_0 Register added PUR2 000B6h PU2_2 PU2_1 PU2_0 Register added POD2 000C2h POD2_2 POD2_1 POD2_0 Register added PML2 O000CAh P22SEL1 P22SELO0 P21SEL1 P21SELO P20SEL1 P20SELO Register added P3_1 P3_3 P3_4 PD3 OOOABh PD3_1 Functions added P3 000B1h P3_1 Functions added PUR3 000B7h PU3_1 Functions added POD3 000C3h POD3_1 Functions added PML3 000CCh P33SEL1 P33SELO P31SEL1 P31SELO P34SEL1 P34SELO P42SEL1 P42SELO0 P47SEL1 P47SELO P46SEL1 P46SELO P45SEL1 P45SELO ADGSEL1 ADGSELO Functions changed Functions added Functions changed Functions changed Functions changed PMH3 PML4 PMH4 000CDh 000CEh 000CFh ADINSEL 0009Dh Functions changed R01UH0050EJ0200 Rev 2 00 ztENESAS May 18 2012 Page 423 of 426 R8C M11A Group R8C M12A Group Appendix 4 Comparison between R8C M12A Group and R8C M13B Group Appendix Table 4 3 Register Comparison between R8C M12A Group and R8C M13B Group 2 Address 188h Related Function Register TMKCR 00189h TMKLD 0018Ah TMKCMP 0018Bh TMKIR 0018Ch Remarks Registers added Timer RE2 TRESEC TRECNT 00130h TREMIN 00131h TREHR 00132h TREWK 00133h TREDY 00134h TREMON 00135h
93. PM2 to PMO 100b PM2 to PMO 101b PM1 PMO P42SEL1 P42SELO P3_7 P3_7 TRCIOD P37SEL1 P37SELO RESET PA_O P4_7 XOUT P4_7 XOUT P47SEL1 P47SELO VSS AVSS P4_6 XIN P4_6 XIN INT1 P46SEL2 P46SEL1 P46SELO VCC AVCC MODE O O N Dm oO BR oO pm A P3_5 P3_5 TRCIOD VCOUT3 P35SEL1 P35SELO P3_4 P3_4 IVREF3 TRCIOC P34SEL1 P34SELO P3_3 P3_3 IVCMP3 TRCCLK P33SEL1 P33SELO P45 P4_5 INTO P45SEL1 P45SELO P1_7 AN7 IVCMP1 INT1 TRCCLK P17SEL1 P17SELO P1_6 IVREF1 CLKO TRCIOB P16SEL1 P16SELO P15 RXDO INT1 VCOUT1 P15SEL2 P15SEL1 P15SELO P1_4 AN4 TXDO INTO TRCIOB P14SEL2 P14SEL1 P14SELO P1_3 AN3 TRCIOC TRBO P13SEL1 P13SELO P1_2 AN2 TRCIOB P12SEL1 P12SELO P1_1 AN1 TRCIOA TRCTRG P11SEL1 P11SELO P1_0 ANO R01UH0050EJ0200 Rev 2 00 May 18 2012 TRCIOD ztENESAS P10SEL1 Page 140 of 426 P10SELO R8C M11A Group R8C M12A Group 12 I O Ports Table 12 3 UO Port Register Configuration Register Name After Reset Address Access Size Port P1 Direction Register OOOA9h Port P3 Direction Register OOOABh Port P4 Direction Register 0O00ACh Port PA Direction Register OOOADh Port P1 Register OQOOAFh Port P3 Register 000B1h Port P
94. PMH4 register is used to select the functions of pins P4_5 to P4_7 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 160 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 5 7 Port 4 Function Mapping Expansion Register PMH4E Address 000D5h Bit b7 b6 b5 b4 b3 b2 b1 b symool e oo e e e After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 The P4_6 pin function is selected in conjunction with bits PA6SELO to P46SEL1 in the PMH4 register For details see 12 5 6 Port 4 Function Mapping Register 1 PMH4 Nothing is assigned The write value must be 0 The read value is 0 The PMH4E register is used to select the port 4 function in conjunction with registers PML4 and PMH4 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 161 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 5 8 Pin Settings for Port A Tables 12 16 to 12 19 list the pin settings for port 4 Table 12 16 Port P4_2 TRBO TXDO KI3 Register PML4 Bit P42SEL Function Input port Output port Setting value TRBO output TXDO output X 0 or 1 Table 12 17 Port P4_5 INTO0 ADTRG Register PMH4 INT input P45SEL Function Bit Input port Setting Output port value INTO input X 0 or 1 ADTRG input Table 12 18 Port P4_6 XIN RXDO TXDO IN
95. RB Secondary Register Timer RB Secondary Register Higher 8 Bits 000E7h OOOABh Port P3 Direction Register Timer RB Interrupt Control Register 000E8h 000ACh Port P4 Direction Register 000ADh Port PA Direction Register Timer RC Counter OOOAEh OOOAFh Port P1 Register Timer RC General Regis 000B0h 000B1h Port P3 Register Timer RC General Regist 000B2h Port P4 Register 000B3h Port PA Register Timer RC General Regis 000B4h OOOF 1h 000B5h Pull Up Control Register 1 Timer RC General Regisi 000F2 000B6h Timer RC Mode Register R 000F3 000B7h Pull Up Control Register 3 Timer RC Control Register 1 Ri O00F 4 000B8h Pull Up Control Register 4 Timer RC Interrupt Enable Register 000F5 000B9h Port UO Function Control Register Timer RC Status Register 000F6 000BAh Timer RC UO Control Register 0 RCIORO 000F71 000BBh Drive Capacity Control Register 1 Timer RC I O Control Register 1 RCIOR1 000F8 000BCh Timer RC Control Register 2 000BDh Drive Capacity Control Register 3 000F91 Timer RC Digital Filter Function Select Register 000FAh OOOBEh Timer RC Output Enable Register OOOFBh 000BFh Note 1 The blank areas are reserved No access is allowed
96. RESET PA_0 lt gt 2 a P1_2 AN2 TRCIOB KI2 P4_7 XOUT INT2 lt q gt 3 R8C M1 1A Group lt gt P1_3 AN3 TRCIOC KI3 TRBO VSS AVSS 4 PTSP0014JA B lt gt P1_4 AN4 TXDO RXDO INTO TRCIOB PRDP0014AC A P4_6 XIN RXDO TXDO INTT E VCOUT1 TRJIO Top view lt q P1_5 RXDO TRJIO INT1 VCOUT1 VCC AVCC gt 6 9 lt P1_6 IVREF1 CLKO TRJO TRCIOB MODE 7 8 lt P1_7 AN7 IVCMP1 NTT TRJIO TRCCLK Note 1 Confirm the pin 1 position on the package by referring to Appendix 1 Package Dimensions Figure 1 3 R8C M11A Group Pin Assignment Top View P4_2 TRBO TXDOKIS lt b 1 e ak P1_0 AN0 TRCIOD KO P3_7 ADTRG TRJO TRCIOD lt p 2 lt gt P1_1 AN1 TRCIOA TRCTRG KIT RESET PA_0 SI lt gt P1_2 AN2 TRCIOB KIZ P4_7 XOUT NT2 lt q 4 lt gt P1_3 AN3 TRCIOC KIG TRBO R8C M12A Group VSS AVSS gt 5 lt 4 P1_4 AN4 TXDO RXDO INTO TRCIOB PLSP0020JB A P4_6 XIN RXDO TXDO INTT VCOUTI TRJIO gt 6 PRDPOO20AD A lt 4 P1_5 RXDO TRJIO INTT VCOUT1 Top view VCC AVCC gt 7 lt 4 P1_6 IVREF1 CLKO TRJO TRCIOB MODE gt 8 lt gt P1_7 AN7 IVCMP1 NTT TRJIO TRCCLK P3_5 TRCIOD KI2 VCOUT3 a IO a P4_5 INTO ADTRG P3_4 IVREF3 TRCIOC INT2 lt 10 lt 4 P3_3 IVCMP3 TRCCLK INTS Note 1 Confirm the pin 1 position on the package by referring to Appendix 1 Package Dimensions Figure 1 4 R8C M12A Group Pin Assignment Top View RO1UHO050EJ0200 Rev 2 00 zt
97. Reset Address 001C2h AIADROH 001C6h AIADR1H Bit b23 b22 b21 b20 b19 b18 b17 b16 a eae zld e Ee ees eae er Reset Function Setting Range b19 to bO Setting for the addresses to be matched 00000h to FFFFFh b20 Nothing is assigned The write value must be 0 The read value is 0 b21 b22 b23 The AIADRi register i 0 or 1 is initialized after a voltage monitor 0 reset power on reset or hardware reset This register remains unchanged after a watchdog timer reset or software reset 11 2 11 Address Match Interrupt Enable Register i AIENi i 0 or 1 Address 001 SE WEE Bit Symbol EE After Reset Address 001 e AENT Bit Symbol EE EE After Reset Bit Name Function Address match interrupt enable i bit 0 Disabled i 0 or 1 1 Enabled Nothing is assigned The write value must be 0 The read value is 0 The AJENi register i 0 or 1 is initialized after a voltage monitor 0 reset power on reset or hardware reset This register remains unchanged after a watchdog timer reset or software reset RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 119 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 3 Interrupts and Interrupt Vectors There are 4 bytes in each vector Set the start address of an interrupt routine in each interrupt vector When an interrupt request is acknowledged the CPU branches to the address set in the corresponding i
98. Reset Bit Name WCB1MO 7 b6 b5 0 0 0 Comparator B1 operation enable bit WCB3INTR 00182h Comparator B Control Register WCMPR b4 b 0 Function 0 Operation disabled 1 Operation enabled 3 b2 bi 0 Symbol KEE 0 0 0 0 b Reserved Set to 0 WCB10UT Comparator B1 monitor flag 1 IVCMP1 gt IVREF1 0 IVCMP1 lt IVREF1 or comparator B1 disabled WCB3M0 Comparator B3 operation enable bit 0 Operation disabled 1 Operation enabled Reserved Set to 0 WCB30UT Comparator B3 monitor flag 1 IVCMP3 gt IVREF3 0 IVCMP3 lt IVREF3 or comparator B3 disabled RO1UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 318 of 426 R8C M11A Group R8C M12A Group 18 Comparator B 18 2 2 Comparator B1 Interrupt Control Register WCB1INTR Address 00181h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol WCB1F WGRBIINTEN WCB1S1 WCB1S0 WCB1F1 WCB1F0O After Reset 0 0 0 0 0 0 0 0 Bit Name Function WCB1F0_ Comparator B1 filter select bits b1 b0 0 0 No filter 0 1 Filter sampled at f1 1 0 Filter sampled at f8 1 1 Filter sampled at f32 Es Nothing is assigned The write value must be 0 The read value is 0 WCB1F1 WCB1S0__ Comparator B1 interrupt edge select WCB1S1 bits b5 b4 0 0 When the analog input voltage is lower than the reference input voltage 0 1 When the analog input voltage is higher than the
99. Reset 0 Bit Name Function Reserved The write value is invalid The read value is undefined Reserved Set to 0 The read value is 0 Nothing is assigned The write value must be 0 The read value is 0 TRJIOSEL TRJIO input signal select bit 0 Input from external TRJIO pin 1 Internal input from VCOUT1 of comparator B IOINSEL Pin level forced read out bit 0 Disabled control by PDi Register 1 Enabled read of pin input level Set the PRC4 bit in the PRCR register to 1 write enabled before rewriting the PINSR register When the IOINSEL bit in the PINSR register is 0 When the PDi_j bit j 0 to 7 in the PDi register i 1 3 4 or A is O input mode if the Pi_j bit in the Pi register is read the input level of the corresponding pin is read If the Pi_j bit in the Pi register is read when the PDi_j bit is 1 output mode the port latch is read When the IOINSEL bit in the PINSR register is 1 If the Pi register is read the input level of the corresponding pin is read regardless of the setting of the PDi register RO1UH0050EJ0200 Rev 2 00 RENESAS Page 142 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 Port Figure 12 1 shows the Port Pin Configuration P1_0 ANO TRCIOD KIO P1_1 AN1 TRCIOA TRCTRG KIT P1_2 AN2 TRCIOB KI2 P1_3 AN3 TRCIOC KI3 TRBO P1_4 AN4 TXDO RXDO INTO TRCIOB P1_5 RXDO TRJIO INT1 VCOUT1 P1_6 IVREF1 CLK0 TRJO TRCIOB P1_7 A
100. Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN An 391 21 5 5 INTi Input Filter i 0 to 3 When Returning from Wait Mode or Stop Mode to Standard Mode 392 21 5 6 Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions cccc0e0 393 21 5 7 Changing Interrupt Priority Levels and Flag Registers eee eeeesesseceseceeceseeseceeceeeeseeeeseneeseecseeseenaes 394 21 6 Notes on HCH Ports E E EEES TE EE 395 21 6 1 Note s on PA O P EE EES EES EE 395 21 6 2 I O Pins for Peripheral Functions ii cece eee eeeeecseeseecaecsecoeceeceseeseceaeeeeeeseseaecaecsaesaecsacseseeecsaesaeensenaes 395 21 7 Notes on Timer RJZ enee aana E a EA Teee Erea oe EE e EE a EEEE e 396 21 8 Notes om Timer RIB 2 A E 399 21 9 Notes on Timer RE accessed dng dree Eder deeg dte deed geheegt Ee echte dee Biel 401 21 9 TRECNT Resister seeme ye dingo eae ate AA 401 21 9 2 TREGR Register siis one Mises ees AER Alege tester Rave Ades to ie 401 219 3 TRESR Register E 401 21 94 Count Source S withing EEN Deas EES 401 21 9 3 opt Capture Pune tron ierse e E tases saben EE ERR vas entosceate ghee E ES 402 21 9 6 TRCMR Register in PWM2 Mode eee eceseseseeeeceeceeseesecnecaeeecsaecseeececsaenaeeeeseceeeaeesessceaecaseeceeeeeeneeaees 402 219 7 MSTCR Register afres rnp eee Eder eege 402 21 9 8 Mode SwitchinS s c ss04cccseiien aectienustinganting e TOE ETET nettle EEE EER Sa o ai EE t 402 21 9 9 Procedure
101. Symbol INT3F1 INT3FO INT2F1 INT2FO INT1F1 INT1FO INTOF1 INTOFO 0 0 0 0 0 0 0 After Reset 0 Bit Name Function INTO ji A H b1 b po Aaa INTO input filter select bits Do No ter nm 0 1 Filter sampled at f1 1 0 Filter sampled at f8 1 1 Filter sampled at f32 b2 INT1FO NT1 input filter select bits OD No fitter R W SS FREI 0 1 Filter sampled at f1 RS 1 0 Filter sampled at f8 1 1 Filter sampled at f32 FA a e b5 b4 a ware INT2 input filter select bits 0 0 No filtet nm 0 1 Filter sampled at f1 1 0 Filter sampled at f8 1 1 Filter sampled at f32 b6 INT3FO NT3 input filter select bits bree R W 0 0 No filter b7 INT3F1 0 1 Filter sampled at f1 SE 1 0 Filter sampled at f8 1 1 Filter sampled at f32 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 112 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 3 INT Input Edge Select Register 0 ISCRO Address 0003Ch Bit b 7 b6 b5 b4 b3 b2 b1 bO Symbol INT3SB INT3SA INT2SB INT2SA INT1SB INT1SA INTOSB INTOSA 0 0 0 0 0 0 0 After Reset 0 Bit Name Function INTOSA NTO input edge INTOSB select bits 1 Interrupt request is generated on the falling edge of INTO input Interrupt request is generated on the rising edge of INTO input Do not set Interrupt request is generated on both the falling and rising edges of INTO input INT1SA INT1 input edge INT1SB
102. TOB bit is 1 in TRCCR1 register TRCCNT register value FFFFh TRCGRA register r TRCGRB register H U l U 0000h 1 1 U l i TRCIOA No change No change LU I I l TRCIOB No change No change Figure 15 4 Example of Low Level and High Level Output Operation Figure 15 5 shows an Example of Toggle Output Operation during Free Running Count The TRCCNT register is used for the free running count operation and toggle output is performed at compare matches A and B e TOA bit is 0 and TOB bit is 1 in TRCCR1 register TRCCNT register value FFFFh TRCGRA register l TRCGRB register H 0000h i U I I 1 TRCIOA Toggle h output Li I 1 D TRCIOB Toggle output Figure 15 5 Example of Toggle Output Operation during Free Running Count RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 248 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 6 shows an Example of Toggle Output Operation during Period Count The TRCCNT register is used for the period count operation and toggle output is performed at compare matches A and B e TOA bit is 0 and TOB bit is 1 in TRCCR1 register TRCCNT register value Counter cleared by compare match with TRCGRA register FFFFh TRCGRA register TRCGRB register 0000h Time Toggle output TRCIOB Toggle output Figure 15 6 Example of Toggle Output Operation during Period Count The input capture function can be used to measure the pulse width or perio
103. TRBSC Address 000E6h Bit b 7 b6 b5 b4 b3 b2 b1 bO yee Se ee ee ES ee 2 E After Reset 1 1 b7 to bO Timer mode Disabled Invalid Note 1 Function 8 Bit Timer with 8 Bit Prescaler Initial Setting 16 Bit Timer Value Range Programmable waveform Timer RB prescaler Internal count 00h to FFh generation mode underflow source or timer RJ2 underflow 1 Programmable one shot Disabled Invalid generation mode Programmable wait one shot Timer RB prescaler Internal count 00h to FFh generation mode underflow source or timer RJ2 underflow 1 The values in registers TRBPR and TRBSC are reloaded and counted alternately The count value can be read from the TRBPR register while the secondary period is counted In the 8 bit timer with 8 bit prescaler use the following procedure when writing to the TRBSC register 1 Write a value to the TRBSC register 2 Write a value to TRBPR register write the same value as the previous one again even if the value is not changed In the 16 bit timer use the following procedure when writing to the TRBSC register 1 Write values to registers TRBPRE and TRBSC 2 Write a value to TRBPR register write the same value as the previous one again even if the value is not changed In the 8 bit timer with 8 bit prescaler the TRBSC register is used to set the secondary period used in programmable waveform and programmable wait one shot generation modes
104. TRBSC register is written register is written Programmable waveform generation mode TWRC 1 Updated immediately before the end of the secondary output period after the TRBPR register is written TWRC 0 Updated in synchronization with the count source after the TRBPR register is written 2 Programmable one shot gene ration mode Updated in synchronization with Updated in synchronization with the count source after the TRBPR the count source after the TRBSC register is written register is written 3 Programmable wait one shot generation mode TWRC 1 Updated immediately before the end of the secondary output period after the TRBPR register is written TWRC 0 TWRC Bit in the TRBMR register Notes Updated in synchronization with the count source after the TRBPR register is written 2 1 For details see 14 5 2 Prescaler and Counter Using TWRC Bit 2 When the TWRC bit is 0 write to reload register and counter in programmable waveform and programmable wait one shot generation modes if the data in registers TRBSC and TRBPR is updated during count operation the waveform is output for the updated period from that time 3 When the TWRC bit is 0 write to reload register and counter in programmable one shot generation mode if the data in the TRBPR register is updated during count operation the waveform is output for the updated period from that time RO1UHO
105. TSTART After Reset 0 0 0 0 0 0 0 0 Bit Name Function TSTART Timer RB count start bit 1 When the TMOD1 bit in the TRBMR register is 0 0 Count is stopped 1 Count is started When the TMOD1 bit in the TRBMR register is 1 0 Count is stopped 1 Count is enabled Timer RB count status flag 1 When the TMOD1 bit in the TRBMR register is 0 0 Count is stopped 1 Count is in progress When the TMOD1 bit in the TRBMR register is 1 0 Count is stopped 1 Count is enabled Timer RB count forced stop bit 1 2 When 1 is written to this bit the count is forcibly stopped The read value is 0 Nothing is assigned The write value must be 0 The read value is 0 Notes 1 For notes on using bits TSTART TCSTF and TSTOP see 14 8 Notes on Timer RB2 2 When 1 count is forcibly stopped is written to the TSTOP bit the counter registers TRBPRE TRBPR and TRBSC bits TSTART and TCSTF and bits TOSST TOSSP and TOSSTF in the TRBOCR register are initialized The TRBO output is also initialized TSTART Bit Timer RB count start bit Condition for setting to 0 e When 0 is written to this bit Condition for setting to 1 e When 1 is written to this bit TCSTF Bit Timer RB count status flag Conditions for setting to 0 e When 0 is written to the TSTART bit e When 1 is written to the TSTOP bit Condition for setting to 1 e When 1 is written to the TSTART bit RO1UHO050EJ
106. Timer Interrupt or Voltage Monitor 1 Interrupt RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 134 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 9 Notes on Interrupts 11 9 1 Reading Address 00000h Do not read address 00000h by a program When an external interrupt request is acknowledged the CPU reads interrupt information interrupt number and interrupt request level from address 00000h in the interrupt sequence At this time the corresponding bit in the IRR3 register for the acknowledged interrupt is set to 0 If a program is used to read address 00000h the corresponding bit in the IRR3 register for the interrupt which has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 11 9 2 SP Setting Set a value in the SP before any interrupt is acknowledged The SP is 0000h after a reset If an interrupt is acknowledged before setting a value in the SP the program may run out of control 11 9 3 External Interrupt and Key Input Interrupt Signal input to pins INTO to INT3 and pins KIO to KI3 must meet either the low level width or the high level width requirements shown in External Interrupt INTi Input i 0 to 3 in the Electrical Characteristics regardless of the CPU operating clock For details see Table 20 18 Vcc 5 V Table 20 24 Vcc 3 V and Table 20 30 Vcc 2 2 V External Interrupt INTi Input Key Inpu
107. When 0 is written to this bit by a program Condition for setting to 1 e When the counter underflows RO1UHOO050EJ0200 Rev 2 00 ztENESAS Page 181 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 3 3 Timer RJ I O Control Register TRJIOC Address 000DBh Bit b7 b6 b5 b4 b3 b2 b1 bo Symbol TOGTT mom TIFT mero J TOPOR TEDGSEL After Reset 0 0 0 0 0 0 0 0 Bit Name Function TEDGSEL I O polarity switch bit Function varies depending on the operating mode TOPCR_ TRJIO output control bit 0 TRJIO output enabled toggle output is started 1 TRJIO output disabled toggle output is stopped Reserved Set to 0 TRJIO input filter select bits No filter Filter sampled at f1 Filter sampled at f8 Filter sampled at f82 TIOGTO TRJIO count control bits TIOGT1 Event is always counted Event is counted only during INT2 high level period Event is counted during timer RC output signal period specified by RCCPSEL bit in TRJISR register Do not set TEDGSEL Bit I O polarity switch bit The TEDGSEL bit is used to switch the TRJO output polarity and the TRJIO I O edge and polarity In pulse output mode only the inversion non inversion of toggle flip flop is controlled The toggle flip flop is initialized when the TRJMR register is written or is written to the TSTOP bit in the TRJCR register Table 13 4 TRJIO I O Edge and Polarity Switch
108. X A D converter input AN3 ae X x x x 0 1 See Table 12 23 TRCIOC Pin Settings X TRCIOC input D xX X X 0 1 See Table 12 23 TRCIOC Pin Settings D TRCIOC output X xIx xX 140 X X K input xX xX X X 1 1 X X TRBO output X 0 or 1 RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 149 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Table 12 8 Port P1_4 AN4 TXDO RXDO INTO TRCIOB Register ADINSEL PMH1E PMH1 Bit a CHO P14SEL2 P14SEL Timer RC Setting Function 0 Input port Output port A D converter input AN4 TXDO output RXDO input X INTO input See Table 12 22 TRCIOB Pin Settings TRCIOB input See Table 12 22 TRCIOB Pin Settings TRCIOB output Setting value x x X x x oj o X X X X X zi z X X K x x o x Xx X X X X x O x Xx hi kl OO OOlOOOc OO Of Of Of OF ojoj oO O OF X 0or 1 Table 12 9 Port P1_5 RXDO TRJIO INT1 VCOUT1 Register PMH1E PMH1 TRJIOC P15SEL Functi Bit P15SEL2 BS TOPCR SH 2 X Input port X Output port xX RXDO input Other than 000b TRJIO input 001b TRJIO pulse output X X INT1 input X X VCOUT1 output Setting value el Al Al schiele oO O O CO ojo X 0or1 Table 12 10 Port P1_6 IVREF1 CLK0 TRJO TRCIOB Register PMH1 P16SEL 0 n el Bit Timer RC Setting Functio
109. X X X X Symbol Function R W Bit bO kg Transmit data D8 to DO b1 b2 b3 b4 b5 b6 b7 b8 b9 Nothing is assigned The write value must be 0 The read value is undefined If the transfer data is 9 bits long write to the UOTBH register first and then the UOTBL register in 8 bit units Write to the UOTB register using the MOV instruction Word access is prohibited RO1UHO050EJ0200 Rev 2 00 stENESAS Page 281 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 2 4 UARTO Transmit Receive Control Register 0 U0CO Address 00084h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol UFORM CKPOL TXEPT TE CLKO After Reset 0 0 0 0 1 0 0 0 Bit Name Function UOBRG count source select bits 1 T0 1 01 f8 1 0 32 1 1 Do not set Reserved Set to 0 Transmit register empty flag 0 Data present in the transmit register transmission is in progress 1 The transmit register empty transmission is completed RXDO digital filter enable bit 2 Digital filter disabled Digital filter enabled Data output select bit TXDO pin is set to CMOS output TXDO pin is set to N channel open drain output CLK polarity select bit 3 Transmit data is output on the falling edge and receive data is input on the rising edge of the transfer clock Transmit data is output on the rising edge and receive data is input on the falling edg
110. a clock will still be supplied to the watchdog timer Table 8 4 lists the Watchdog Timer Specifications When Count Source Protection Mode is Enabled Table 8 4 Watchdog Timer Specifications When Count Source Protection Mode is Enabled Item Specification Count source Low speed on chip oscillator clock Count operation Decrement Period Count value in the watchdog timer m Low speed on chip oscillator clock m Value set by WDTUFSO to WDTUFS1 in the OFS2 register Ex When the low speed on chip oscillator clock is 125 kHz and bits WDTUFS1 to WDTUFSO are 00b 03FFh the period is approx 8 2 ms Watchdog timer initialization conditions e Reset e 00h and then FFh are written to the WDTR register e Underflow Count start conditions The operation of the watchdog timer after a reset is selected by the WDTON bit in the OFS register address OFFFFh e When the WDTON bit is 1 watchdog timer is stopped after reset The watchdog timer is stopped after a reset and only starts counting when the WDTS register is written e When the WDTON bit is 0 watchdog timer is automatically started after reset The watchdog timer automatically starts counting after a reset Count stop condition None The count is not stopped even in wait mode or stop mode once it is started Operation at underflow Watchdog timer reset See 6 3 5 Watchdog Timer Reset Registers bits When the CSPRO bit in the CSPR regi
111. active low active high Nothing is assigned The write value must be 1 The read value is 1 Count stop bit 2 0 Count is continued even after compare match with TRCGRA register 1 Count is stopped at compare match with TRCGRA register TRCTRG input edge select bits 3 Notes 1 Enabled in PWM mode 2 Enabled in the output compare function PWM mode and PWM2 mode For notes on PWM2 mode see 15 7 6 TRCMR Register in PWM2 Mode 3 Enabled in PWM2 mode b7 b6 0 0 TRCTRG input disabled 0 1 Rising edge 1 0 Falling edge 1 1 Both rising and falling edges RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 241 of 426 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 10 Timer RC Digital Filter Function Select Register TRCDF Address 000F9h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol DFOKT DFCKO DFTRG 0 0 0 0 0 0 0 After Reset 0 Bit Name Function bO DFA TRCIOA digital filter function bit 1 0 Function is not used R W b1 DER TRCIOB digital filter function bit 1 1 Function is used R W b2 DFC TRCIOC digital filter function bit 1 R W b3 DFD TRCIOD digital filter function bit 1 R W b4 DFTRG TRCTRG digital filter function bit 2 R W b5 Nothing is assigned The write value must be 0 The read value is 0 b6 DFCKO Digital filter clock select bits 1 2 00 90 R W b7 DFCK1 01 18 R W 10 f1 1 1 Count source c
112. and 5 can be executed at the same time with one instruction RO1UHO050EJ0200 Rev 2 00 stENESAS Page 59 of 426 May 18 2012 When VCAC1 bit is 1 two way edge VW1C1 bit is 0 digital filter enabled mode When VCAC1 bit is 0 one way edge VW1C1 bit is 0 digital filter enabled mode VW1C7 bit is 0 VCC reaches Vdet1 or above When VCAC1 bit is 0 one way edge VW1C1 bit is 0 digital filter enabled mode VW1C7 bit is 1 VCC reaches Vdet1 or below When VCAC1 bit is 1 two way edge VW1C1 bit is 1 digital filter disabled mode When VCAC1 bit is 0 one way edge VW1C1 bit is 1 digital filter disabled mode VW1C7 bit is 0 VCC reaches Vdet1 or above When VCAC1 bit is 0 one way edge VW1C1 bit is 1 digital filter disabled mode VW1C7 bit is 1 VCC reaches Vdet1 or below Figure 7 5 RO1UH0050EJ0200 Rev 2 00 May 18 2012 R8C M11A Group R8C M12A Group VW1C3 bit VW1C2 bit Voltage monitor 1 interrupt request VW1C2 bit Voltage monitor 1 interrupt request VW1C2 bit Voltage monitor 1 interrupt request VW1C2 bit Voltage monitor 1 interrupt request VW1C2 bit Voltage monitor 1 interrupt request VW1C2 bit Voltage monitor 1 interrupt request 7 Voltage Detection Circuit Digital filter sampling clock lt gt x 2 cycles 1 Digital filter sampling clock gt x 2 cycles 1 H l Set to 0 by a program 1 H H I d Li I
113. and the instruction queue buffer Example 1 Use the NOP instruction to separate the interrupt priority level and the flag register operation and I flag operation INT_SWITCH1 FCLR I Disable interrupts AND B 0CFH ILVLE Set INTO interrupt priority level 0 NOP NOP FSET I Enable interrupts Example 2 Use a dummy read to delay the FSET instruction INT_SWITCH2 FCLR I Disable interrupts AND B 0CFH ILVLE Set INTO interrupt priority level 0 MOV W MEM RO Dummy read FSET I Enable interrupts Example 3 Use the POPC instruction to change the I flag INT_SWITCH3 PUSHC FLG FCLR I Disable interrupts AND B 0CFH ILVLE Set INTO interrupt priority level 0 POPC FLG Enable interrupts RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 139 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 I O Ports There are 17 I O ports P4_6 and P4_7 can be used as I O ports when the XIN clock oscillation circuit is not used PA Ocean be used as an I O port when a hardware reset is not used In addition all the ports are multiplexed with multiple peripheral functions 12 1 Overview The functions of the ports are selected by the peripheral function mapping registers PMLi PMHi i 1 3 or 4 and the peripheral function mapping expansion registers PMH1E and PMH4E The functions of the I O ports are selected by the port direction registers PDi i 1 3 4 or A In addition the drive ca
114. are written to while the count is stopped values are written to both the reload register and counter respectively When these registers are written during the count operation values are written to both the reload register and counter When the TWRC bit is 1 values are written to the reload register only Figure 14 2 shows an Operation Example in Timer Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 207 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 e 8 bit timer with 8 bit prescaler in timer mode Set to 1 by a program TSTART bit in TRBCR register Count source Underflow signal from timer RB prescaler Timer RB2 counter Count is started Timer RB primary is reloaded Li l Interrupt request signal Set to 0 by a program The above diagram applies under the following conditions TRBPRE register 02h TRBPR register 01h TOCNT bit in TRBIOC register 0 waveform output TCNT16 bit in TRBMR register 0 8 bit timer with 8 bit prescaler e 16 bit timer in timer mode Set to 1 by a program TSTART bit in TRBCR register Count source Timer RB2 counter Count is started Timer RB primary is reloaded i i Interrupt request i signal H Set to 0 by a program The above diagram applies under the following conditions TRBPRE register 02h TRBPR register 01h TOCNT bit in TRBIOC register 0 waveform output e TCNT16 bit in TRBMR register 1 16 bit timer
115. b6 b5 b4 b3 b2 b1 b Smo BORIS mn CWA After Reset 0 0 0 0 X 1 X 1 x x1 Bit Name Function Cold start up warm start up Cold start up determine flag Warm start up Hardware reset detect flag Not detected Detected Not detected Detected Not detected Detected Nothing is assigned The write value must be 0 The read value is 0 Software reset detect flag Watchdog timer reset detect flag 0 1 0 1 0 1 0 1 Note 1 The value after a reset differs depending on the reset source CWR Bit Cold start up warm start up determine flag This flag indicates whether a cold start up or warm start up has occurred The CWR bit is set to 0 cold start up after power on or voltage monitor 0 reset This bit remains unchanged after a hardware reset software reset or watchdog timer reset The CWR bit is set to 1 by writing 1 by a program but writing 0 to this bit has no effect Condition for setting to 0 e When a reset occurs after power on or voltage detection 0 Condition for setting to 1 e When is written to this bit by a program HWR Bit Hardware reset detect flag This flag indicates that a hardware reset has occurred Condition for setting to 0 e When a software reset watchdog timer reset power on reset or voltage monitor 0 reset occurs Condition for setting to 1 e When a hardware reset occurs SWR Bit Software reset detect flag This fl
116. bit is set to 1 suspend request enabled by interrupt request the FMR21 bit is automatically set to 1 suspend request when an interrupt request is generated during auto programming Set the FMR22 bit to 1 when suspend is used while the user ROM area is rewritten in EW1 mode Figure 19 11 FMR20 1 i FMR22 1 Access the flash memory Write the command code 40h 1 interrupt enabled JMP S CMD2 Write data to the write address 2 Flash memory dummy read 4 NOP instruction x 4 Flash memory dummy read 4 FMR21 Full status check I Flag in CPU register Program completed FST3 FST7 Bits in FST register FMR20 FMR21 FMR22 Bits in FMR2 register Notes 1 The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other than the programming target area 2 td SR SUS is required from when the maskable interrupt is generated until suspend is acknowledged The interrupt to enter suspend must be enabled beforehand 3 Use one of the following instructions for the second command writing e MOV B A0 A1 or MOV B A1 A0 e MOV B IMM An e MOV B IMM abs16 e MOV B Bn An e MOV B RnH abs16 e MOV B RnL An e MOV B RnL abs16 Use one of the following instructions to read the same address as the second command write address e MOV B An RnL e MOV B An RnH e MOV W An Rn Program Flowchart in EW1 Mode Fla
117. block Block 2 OE000h Block 1 OFOOOh x Any address in the user ROM area Note 1 For block erase lock bit program read lock bit status and block blank check commands if FFh is written as the second command the command code written as the first command becomes invalid A command sequence error does not occur The data flash does not have a lock bit so the lock bit program and the read lock bit status commands are handled as illegal 19 6 6 1 Read Array This command is used to read the flash memory When FFh is written as the first command the MCU enters read array mode When the read address is input in the following cycles the content of the specified address can be read in 8 bit units Since read array mode is retained until another command is written the contents of multiple addresses can be read continuously In addition after a reset the MCU enters read array mode after a program block erase block blank check read lock bit status or clear status register command or after entering suspend RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 344 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 6 2 Clear Status Register The clear status register command is used to set bits FST4 and FST5 in the FST register to 0 When 50h is written as the first command bits FST4 and FST5 in the FST register are set to 0 19 6 6 3 Program This command writes data to
118. buffer register MOV W 0086H RO Read the UORB register When the transfer data is 9 bits long in clock asynchronous I O mode write to the UOTB register in the order UOTBH first and then UOTBL in 8 bit units e Program example to write to the transmit buffer register MOV B XXH 0083H Write to the UOTBH register MOV B XXH 0082H Write to the UOTBL register Do not set the MSTUART bit in the MSTCR register to 1 standby during communication When setting the module to the standby state confirm whether communication has completed After communication has completed set bits TE and RE in the UOC1 register to 0 communication disabled before setting the module to the standby state After the module standby state is cleared the initial settings for communication must be set again RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 298 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 A D Converter This MCU features a 10 bit successive approximation A D converter that can process analog inputs for up to six channels 17 1 Overview Table 17 1 lists the A D Converter Specifications Figure 17 1 shows the A D Converter Block Diagram Table 17 1 A D Converter Specifications Item Specification A D conversion method Successive approximation with capacitive coupling amplifier Analog input voltage 0 V to AVCC Input channels 6 channels ANO to AN4 AN7 Resolution 10 bits A D con
119. command can be executed when the FST7 bit in the FST register is set to 1 ready The block blank check operation is disabled during suspend 3 The MCU enters read array mode immediately after entering suspend Figure 19 3 shows the Timing for Erase Suspend Operation Figure 19 4 shows the Timing for Program Suspend Operation Erase command Set FMR21 to 1 Program command Set FMR21 to 0 td SR SUS User Suspend Suspend User Usor ROM readable readable 1 is set 1 is set automatically 1is set automatically automatically RDYSTI Set to 0 by a program RDYSTI FST6 FST7 Bits in FST register FMR21 Bit in FMR2 register Figure 19 3 Timing for Erase Suspend Operation RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 340 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory Program command Set FMR21 to 1 Set FMR21 to 0 td SR SUS User User FMR21 1 is set 1 is set automatically stemt RDYSTI Set to 0 by a program RDYSTI FST3 FST7 Bits in FST register FMR21 Bit in FMR2 register Figure 19 4 Timing for Program Suspend Operation RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 341 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 4 Setting and Cancelling Each Mode Figure 19 5 shows Setting and Cancelling EWO Mode Figure 19 6 shows Setting and Cancelling EW1 Mode EWO Mode Execution Procedure Transfer a rewrite mode program which Write 0 and then 1 CPU rewrite m
120. consumption generally depends on the number of the operating clocks and their frequencies The fewer the number of operating clocks or the lower their frequencies the more power consumption decreases Unnecessary clocks should be stopped accordingly Stopping low speed on chip oscillator oscillation LOCODIS bit in OCOCR register Stopping high speed on chip oscillator oscillation HOCOE bit in OCOCR register 10 5 4 Wait Mode and Stop Mode Power consumption can be reduced in wait mode and stop mode 10 5 5 Stopping Peripheral Function Clocks If the peripheral function clocks f1 to 128 are not necessary set the PSCSTP bit in the CKSTPR register to 1 to stop these peripheral function clocks If the peripheral function clocks f1 to f128 are not necessary in wait mode set the WCKSTP bit in the CKSTPR register to 1 to stop the system clock in wait mode 10 5 6 Timers When timer RJ2 is not used set the TCKCUT bit in the TRJMR register to 1 count source cutoff Or set the MSTTRJ bit in the MSTCR register to 1 standby When timer RB2 is not used set the TCKCUT bit in the TRBMR register to 1 count source cutoff Or set the MSTTRB bit in the MSTCR register to 1 standby When timer RC is not used set the MSTTRC bit in the MSTCR register to 1 standby 10 5 7 A D Converter When the A D converter is not used set the MSTAD bit in the MSTCR register to 1 standby 10 5 8 Serial Interface UARTO When the serial interface UARTO is no
121. conversion FMR20 Bit Suspend enable bit When the FMR20 bit is set to 1 enabled the suspend function is enabled FMR21 Bit Suspend request bit When the FMR21 bit is set to 1 suspend request program erase suspend mode is entered When the FMR22 bit is 1 suspend request enabled by interrupt request if an interrupt request for the enabled interrupt is generated the FMR21 bit is automatically set to 1 suspend request and suspend mode is entered To restart auto erase or auto programming set the FMR21 bit to 0 restart Condition for setting to 0 e When 0 is written to this bit by a program Conditions for setting to 1 e When the FMR22 bit is 1 suspend request enabled by interrupt request at the time an interrupt request is generated e When 1 is written to this bit by a program while the flash memory is busy FMR22 Bit Interrupt request suspend request enable bit When the FMR272 bit is set to 1 suspend request enabled by interrupt request the FMR21 bit is automatically set to 1 suspend request at the time an interrupt request is generated during auto erase or auto programming Set the FMR22 bit to 1 when erase suspend is used while the user ROM area is rewritten in EW1 mode RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 336 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory FMR27 Bit Low current consumption read mode enable bit When the FMR27 bit is set to 1 low current consumption re
122. conversion ADCONDO register starts 1 1 1 ADF bit in I 1 1 I Set to 0 by a program ADICSR register Ge Anio Standhy S Standby for conversion operation conversion conversion 1 Channel 1 AN1 1 i A D operation Standby fon conversion conversion 2 Standby for conversion in in Channel 2 AN2 in Channel 3 AN3 in Channel 4 AN4 in Channel 7 AN7 in operation Standtly for conversion I Stand for conversion operation i l e Standty for conversion operation operation Standby for conversion U i ADO register A D conversion result 1 U U l AD1 register A D conversion result 2 Figure 17 6 Operation Example in Single Sweep Mode When Channels 0 and 1 are Selected R01UH0050EJ0200 Rev 2 00 ztENESAS Page 311 of 426 May 18 2012 17 A D Converter R8C M11A Group R8C M12A Group 17 A D Converter 17 3 5 Repeat Sweep Mode Figure 17 7 shows an Operation Example in Repeat Sweep Mode When Channels 0 and 1 are Selected In repeat sweep mode A D conversions of the analog inputs are performed for the specified two channels repeatedly as follows 1 When the ADST bit in the ADCONDO register is set to 1 A D conversion starts by software trigger timer RC trigger or external trigger input A D conversion is started from ANO when channel group 0 is selected and AN2 when channel group 1 is selected When channel group 2 is selected A D conversion is started from AN
123. detection 1 circuit enabled Set the VC1E bit from 0 to 1 and wait for td E A After that the voltage detection 1 circuit operates For details on td E A see 20 Electrical Characteristics Set the PRC3 bit in the PRCR register to 1 write enabled before rewriting the VCA2 register RO1UHO050EJ0200 Rev 2 00 RENESAS Page 53 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 2 3 Voltage Detection 1 Level Select Register VD1LS Address 0005Bh Bit b7 b6 b5 b4 b3 b2 b1 b Smo _ vorss vors2 vorst S E After Reset 0 0 0 0 0 1 1 1 Bit Name Function Reserved Set to 1 j i b3 b2 bi Voltage detection 1 level select bits 0 0 0 2 35 V Vdet1_1 0 0 1 2 65 V Vdet1_3 0 1 0 2 95 V Vdet1_5 0 1 1 3 25 V Vdet1_7 1 0 0 3 55 V Vdet1_9 10 1 3 85 V Vdet1_B 1 10 4 15 V Vdet1_D 111 4 45 V Vdet1_F Reserved Set to 0 Set the PRC3 bit in the PRCR register to 1 write enabled before rewriting the VDILS register RO1UHO050EJ0200 Rev 2 00 stENESAS Page 54 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 2 4 Voltage Monitor 0 Circuit Control Register VWOC Address 0005Ch Bit b7 b6 b5 b4 b3 b2 b1 bO Sme Wmr wo er vwoco After Reset 1 1 0 0 X 0 1 1 The above applies when the LVDAS bit in the OFS register is 0 After Reset 1 1 0 0 X 0 1 0 The above applies when the LVDAS b
124. disabled RO1UHO050EJ0200 Rev 2 00 RENESAS Page 283 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 2 6 UARTO Receive Buffer Register UORB Address GES Ges Bit Symbol Ge After Reset Address 00087h UORBH Bit b15 b14 b13 b12 b11 b10 Symbol Son FER FRO After Reset Symbol Bit Name Function Receive data D8 to DO Nothing is assigned The write value must be 0 The read value is undefined No overrun error has occurred An overrun error has occurred No framing error has occurred A framing error has occurred No parity error has occurred A parity error has occurred No error has occurred An error has occurred Overrun error flag 1 Framing error flag 1 2 Parity error flag 1 2 o OI zk O zk Oo Error sum flag 1 2 Notes 1 Bits OER FER PER and SUM are set to 0 no error has occurred when bits SMD2 to SMDO in the UOMR register are set to 000b serial interface disabled or the RE bit in the UOC1 register is set to 0 reception disabled The SUM bit is set to 0 no error has occurred when all of bits OER FER and PER are set to 0 no error has occurred In addition bits FER and PER are set to 0 when the UORBH register is read When setting bits SMD2 to SMDO in the UOMR register to 000b set the TE bit in the UOC1 register to 0 transmission disabled and the RE bit to 0 rec
125. e The CKDIR bit in the UOMR register is 1 external clock fEXT 16 n 1 fEXT input from the CLKO pin n Value set in the UOBRG register 00h to FFh Transmit start conditions To start transmission the following requirements must be met e The TE bit in the UOC1 register must be 1 transmission enabled e The TI bit in the UOC1 register must be 0 data present in the UOTB register Receive start conditions To start reception the following requirements must be met e The RE bit in the UOC1 register must be 1 reception enabled e Start bit detection Interrupt request generation timing e For transmission One of the following can be selected The UOIRS bit in the UOC1 register is 0 transmit buffer is empty When data is transferred from the UOTB register to the UARTO transmit register at start of transmission The UOIRS bit in the UOC1 register is 1 transmission is completed When data transmission from the UARTO transmit register is completed e For reception When data is transferred from the UARTO receive register to the UORB register at completion of reception Error detection Notes e Overrun error 1 This error occurs if the next data reception is started and the next to last bit is received before the UORB register is read e Framing error This error occurs when the set number of stop bits is not detected 2 e Parity error This error occurs when parity is enabled and the num
126. execution and the selected SP is used Watchdog timer interrupt This interrupt is generated by the watchdog timer For details see 8 Watchdog Timer Oscillation stop detection interrupt This interrupt is generated by the oscillation stop detection function For details on the oscillation stop detection function see 9 Clock Generation Circuit Voltage monitor 1 interrupt This interrupt is generated by the voltage detection circuit For details on the voltage detection circuit see 7 Voltage Detection Circuit Single step interrupt Do not use this interrupt It is provided exclusively for use in development tools Address match interrupt When one of the AIENiO bit i 0 or 1 in the AIENi register is 1 enabled an address match interrupt is generated immediately before executing the instruction that is stored at an address indicated by the corresponding AIADRi register i 0 or 1 For details on the address match interrupt see 11 7 Address Match Interrupt Peripheral function interrupt A peripheral function interrupt is generated by a peripheral function in the MCU For the interrupt sources for the corresponding peripheral function interrupt see the interrupts and the vector table addresses as listed in Table 11 6 Relocatable Vector Table For details on the peripheral functions see the descriptions of individual peripheral functions RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 110 of 426 May 18 2012
127. filter enabled mode filter disabled mode Set the LOCODIS bit in the OCOCR register to 0 low speed on chip oscillator on Wait for 2 cycles of the digital filter sampling clock No wait time Set the VWOCO bit in the VWOC register to 1 voltage monitor 0 reset enabled Note 1 When the VWOCO bit in the VWOC register is 0 voltage monitor 0 reset disabled steps 4 and 5 can be executed at the same time with one instruction Digital filter sampling clock x 2 cycles When VW0C1 bit is 0 Keeser 2 digital filter enabled mode erna OSeNSIg low active When VW0C1 bit is 1 intemalresetsianal digital filter disabled mode erna TESersig low active VW0C1 Bit in VWOC register The above diagram applies under the following conditions e VCOE bit in VCA2 register 1 voltage detection 0 circuit enabled e VWOCO bit in VWOC register 1 voltage monitor 0 reset enabled When the internal reset signal goes low the CPU SFRs and I O ports are initialized When the internal reset signal changes from low to high program execution starts from the address indicated by the reset vector For the states of the SFRs see 3 2 Special Function Registers SFRs Figure 7 4 Example of Voltage Monitor 0 Reset Operation RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 58 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 5 Voltage Monitor 1 Interrupt Table 7
128. filter is used Five cycles of the digital filter sampling clock three cycles of the timer RC operating clock minimum refer to Figure 15 19 Digital Filter Circuit Block Diagram e The value of the TRCCNT register is transferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj j A B C or D pin when the digital filter function is not used 21 9 6 TRCMR Register in PWM2 Mode When the CSTP bit in the TRCCR2 register is 1 increment is stopped do not set the TRCMR register when a compare match occurs between registers TRCCNT and TRCGRA 21 9 7 MSTCR Register After stopping the timer RC count set the MSTTRC bit in the MSTCR register to 1 standby 21 9 8 Mode Switching e When switching the modes during operation set the CTS bit in the TRCMR register to 0 count is stopped before switching e After switching the modes set each flag in the TRCSR register to 0 before operation is started 21 9 9 Procedure for Setting Registers Associated with Timer RC Set the registers associated with timer RC following the procedure below 1 Set timer RC operating mode bits PWMB PWMC PWMD and PWM2 in the TRCMR register 2 Set the registers other than that set in 1 3 Set the port output to be enabled bits EA to ED in the TRCOER register RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 402 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes
129. for 42 ps Conditions when entering flash memory operation state from flash memory stop state e Set the FMSTP bit to 0 the flash memory operates e Return from wait mode while the WTFMSTP bit is 1 the flash memory is stopped in wait mode e Return from stop mode Conditions when entering flash memory stop state from flash memory operation state e Set the FMSTP bit to 1 the flash memory is stopped e Enter wait mode while the WTFMSTP bit is 1 the flash memory is stopped in wait mode e Enter stop mode RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 367 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics 20 Electrical Characteristics Table 20 1 Absolute Maximum Ratings Parameter Condition Rated Value Vcc AVcc Power supply voltage 0 3 to 6 5 Vi Input voltage XIN XOUT oscillation on 0 3 to 1 9 oscillation circuit used 1 XIN XOUT oscillation off 0 3 to Vcc 0 3 oscillation circuit not used 1 Other pins 0 3 to Vcc 0 3 Output voltage XOUT XIN XOUT oscillation on 0 3 to 1 9 oscillation circuit used 1 XIN XOUT oscillation off 0 3 to Vcc 0 3 oscillation circuit not used 1 Other pins 0 3 to Vcc 0 3 Power consumption 40 C lt Topr lt 85 C 500 Operating ambient temperature 20 to 85 N version 40 to 85 D version Storage temperature 60 to 150 Note 1 When the oscillation circuit is used bits CKPT1 to CKPT
130. for Setting Registers Associated with Timer RC sssesseesseeesssessesssseeresreresrererrsserresreerrrsrene 402 21 10 Notes on Serial Interface UARTO 0 0 ccccecessscecessececeneeecssecesssaeecseaaeeceeeeceesaeecesaececessesesaeeesesaeseseeeenees 403 ZEIT Notes cm A D Converter s2 icccse dices ethic a eens SR eS 404 21161 A D Converter Standby Setting siiri tege eet EES ENEE een 404 21 11 2 Sensor Output Impedance during A D Conversion 00 0 0 eee eee ceeceeceeeeeeceseeeeecaecesecaecsacsaecseceseeeeeeseeaeenaes 404 ASA WR DEE 405 21 12 Notes op Flash Memory uge EE EEN EE EE eg EES EE 406 21 12 1 ID Code Area Setting Example 0 0 ec eesessessceesneecoeeseessenssensensoonssansceesneescecssessevssenseessesescnseseeseeenees 406 21 122 CRU Rewrite Moderne e vey Rdetdegt DE atesiies stp Ste d SO To aap dip aiar ain gnia 407 21 12 3 Notes on Flash Memory Stop and Operation Transition 00 0 cece csecese cee ceeeseeeeceeeeeeceseseeeeseesaeeaeenaes 412 2113 een 413 21 13 1 Inserting a Bypass Capacitor between Pins VCC and VSS as a Countermeasure against Noise and Een EE 413 21 13 2 Countermeasures against Noise Error in Port Control Registers cece cee eeceseeeeceeeeeeceseeeeecaeesaecneenaes 413 21 14 Note on Power Supply Voltage Fluctuation 2 0 eesceeecesseceseeceneecsseeeeceeseeesaecesceceaeeeaeeseeeecaeeeeaeceeeeeaeeenees 413 22 Notes on On Chip Debugger cceceeceeeeeeeeeeeeeeceaeeeeeeeeeeeaaeesecaeeeeeeaees
131. i 50 WDTRCS1 to WDTRCSO 01b Refresh Illegal refresh acceptable 25 WDTRCS1 to WDTRCSO 00b Lt WDTRCSO to WDTRCS1 Bits in OFS2 register Note 1 A watchdog timer interrupt or watchdog timer interrupt reset is generated Figure 8 2 Watchdog Timer Refresh Acceptance Period RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 67 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 3 2 When Count Source Protection Mode is Disabled When count source protection mode is disabled the count source for the watchdog timer is the CPU clock or low speed on chip oscillator clock Table 8 3 lists the Watchdog Timer Specifications When Count Source Protection Mode is Disabled Table 8 3 Watchdog Timer Specifications When Count Source Protection Mode is Disabled Item Specification Count source CPU clock or low speed on chip oscillator clock 1 16 Count operation Decrement Period Prescaler division ratio n x Count value in the watchdog timer m 1 Count source n 2 16 or 128 selected by bits WDTC6 to WDTC7 in the WDTC register However when bits WDTC7 to WDTC6 are 11b count source is low speed on chip oscillator n is 16 m Value set by bits WOTUFSO to WDTUFS1 in the OFS2 register Ex When the prescaler divides a CPU clock of 20 MHz by 16 and bits WDTUFS1 to WDTUFSO are 11b 8FFFh the period is approx 13 1 ms Watchdog timer initialization conditions e Reset e
132. is generated Suspend Enabled FMR20 1 Voltage monitor 1 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 362 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory Table 19 13 Interrupt Handling during CPU Rewrite Operation EW1 Mode Interrupt Type Maskable interrupt Data Flash Program ROM Suspend Disabled FMR20 0 When an interrupt request is acknowledged the FMR21 bit is Auto erase or auto automatically set to 1 suspend request if the FMR22 bit is 1 programming has priority suspend request enabled by interrupt request Interrupt handling is The flash memory suspends auto erase or auto programming after executed after auto erase td SR SUS and interrupt handling is executed or auto programming When auto erase is being suspended auto programming and reading can be executed for any block other than the blocks being auto erased When auto programming is being suspended any block other than the blocks being auto programmed can be read After interrupt handling completes auto erase or auto programming can be restarted by setting the FMR21 bit is set to 0 restart If the FMR22 bit is set to 0 suspend request disabled by interrupt request auto erasure and auto programming have priority and interrupt requests are put on standby Interrupt handling is executed after auto erase and auto program complete Suspend Enabled FMR20 1 Address ma
133. is necessary can be used to return from wait mode Table 10 3 lists the Interrupts Used to Return from Wait Mode and Usage Conditions Table 10 3 Interrupt Oscillation stop detection interrupt Interrupts Used to Return from Wait Mode and Usage Conditions CKSTPR Register When WCKSTP Bit 0 Usable When WCKSTP Bit 1 Not usable INTO to INT3 interrupts Usable Usable without a filter Key input interrupt Usable Usable Periodic timer interrupt Usable when fLOCO 16 is selected as the count source Not usable Timer RJ2 interrupt Usable in all modes e Usable without a filter in event counter mode e Usable when fHOCO is selected as the count source Timer RB2 interrupt Usable in all modes Usable when timer RJ2 is used without a filter in event mode and timer RJ2 is selected as the count source for timer RB2 Timer RC interrupt Usable in all modes Not usable Serial interface interrupt Usable with an internal clock or external clock supplied Usable with an external clock supplied A D conversion interrupt Usable Usable when the flash memory operates and fAD is selected as the A D conversion clock Voltage monitor 1 interrupt Usable Usable Comparator B1 interrupt Usable Usable without a filter Comparator B3 interrupt Usable Usable without a filter Figure 10 2 shows the Sequence from Wait Mode to
134. is started when an interrupt request is generated If the system base clock is the XIN clock set pins P4_6 and P4_7 to XIN oscillation by a program to start oscillation before entering wait mode Depending on the clock to be used set appropriate values for oscillation stabilization time using bits CKSTO to CKST3 in the CKRSCR register It is unnecessary to generate a wait time by a program When returning from wait mode using the same clock as the one used immediately before entering the mode no oscillation stabilization time is generated FMRO FMR1 VCA2 Register Register Register FMSTP WTFMSTP 0 low power consumption 0 flash wait mode flash memory disabled memory is stopped 1 operates in wait low power mode consumption wait mode enabled 0 low power consumption 1 wait mode flash disabled memory 1 is stopped Internal Power Stabilization Time T0 low power consumption wait mode enabled 0 low power 0 consumption 0 flash wait mode flash memory disabled memory operates 1 operates in wait low power mode consumption wait mode enabled Internal Power Stabilization Time Interrupt request is generated Figure 10 2 Executed Time until Flash Memory Activation T1 60 us max Flash memory is not activated Flash memory activation sequence Clock Stabilization Time T2 Set by bits CKSTO0 to CKST3 in the CKRSCR register if the clocks a
135. on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement
136. one shot generation modes For details on the change in the states of the TRBO output in each mode see 14 5 3 TOCNT Bit Setting and Pin States Table 14 4 Functions of Timer RB Output Level Select Bit Operating Mode Function Timer mode Set to 0 in timer mode Programmable waveform generation mode High level output during primary period 0 Low level output during secondary period Low level output at timer stop Low level output during primary period High level output during secondary period High level output at timer stop Programmable one shot generation mode High level one shot pulse output Low level output at timer stop Low level one shot pulse output High level output at timer stop Programmable wait one shot generation mode High level one shot pulse output Low level output at timer stop and during wait period Low level one shot pulse output High level output at timer stop and during wait period RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 201 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 4 Timer RB Mode Register TRBMR Address 000E3h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol 0 0 0 0 0 0 0 After Reset 0 Bit Name Function i i its 1 b1 bo Timer RB operating mode select bits 0 0 Tirer mode 0 1 Programmable waveform generation mode 1 0 Programmable one shot generation mode 1 1 Programmable wait one shot generation mode TCNT16 Timer RB co
137. output to the output compare output pins TRCIOA TRCIOB TRCIOC and TRCIOD After the TRCCNT register and the general register match a compare match signal does not occur until an input clock to the TRCCNT register is generated Figure 15 28 shows the Output Compare Output Timing a a a i a ECH 3 TRCCNT register input clock TRCCNT register Registers TRCGRA to TRCGRD Compare match signal TRCIOA to TRCIOD Figure 15 28 Output Compare Output Timing 15 5 3 Input Capture Input Timing A falling edge rising edge or two way edge can be selected for input capture input by setting registers TRCIORO and TRCIORI Figure 15 29 shows the Input Capture Input Timing This applies when a falling edge is selected tO a EE TE Input capture input Input capture signal TRCCNT register Registers TRCGRA to TRCGRD Figure 15 29 Input Capture Input Timing RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 270 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 5 4 Timing for Counter Clearing by Compare Match Figure 15 30 shows the Timing for Counter Clearing by Compare Match If the value in the TRCGRA register is n the counter counts from 0 to n and the period is thus set ton 1 wA gs EAC KCE Compare match signal TRCCNT register n 0000h TRCGRA register Figure 15 30 Timing for Counter Clearing by Compare Match 15 5 5 Buffer Operation Timing Figure 15 31 shows the Buffer Operation Timing
138. pull up control bit The PUR4 register is used to control the port P4 pull up resistors I O ports are pulled up when the corresponding PD4_j bit j 2 or 5 to 7 in the PD4 register is set to 0 input mode functions as I O port and the PU4_j bit j 2 or 5 to 7 in the PUR4 register is set to 1 The input pins for peripheral functions are pulled up when the corresponding PD4_j bit is set to 0 and the PU4_j bit is set to 1 Do not set the corresponding PU4_j bit to 1 for the output pins for peripheral functions 12 5 4 Open Drain Control Register 4 POD4 Address 000C4h Bit b7 b6 b5 b4 b3 b2 b1 b Symboi PODE 7 Poo S Pos e l e ooe E 0 0 0 0 0 0 0 After Reset 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P4_2 open drain control bit 0 Not open drain 1 Open drain Nothing is assigned The write value must be 0 The read value is 0 Port P4_5 open drain control bit 0 Not open drain Port P4_6 open drain control bit 1 Open drain Port P4_7 open drain control bit The POD4 register is used to select whether the output type is CMOS output or N channel open drain output These settings are enabled when the peripheral function output or output port function is selected The corresponding pins are set to N channel open drain output when the POD4_j bit Gj 2 or 5 to 7 is set to 1 open drain and CMOS output when the bit is set
139. reference input voltage 1 0 Do not set 1 1 When the analog input voltage is lower or higher than the analog input voltage WCBI1INTEN Comparator B1 interrupt enable 0 Interrupt disabled signal bit 1 Interrupt enabled WCB1F Comparator B1 interrupt request flag 0 No interrupt requested 1 Interrupt requested WCB1F Bit Comparator B1 interrupt request flag Condition for setting to 0 e When 0 is written to this bit Condition for setting to 1 e When an interrupt request is generated RO1UHO050EJ0200 Rev 2 00 RENESAS Page 319 of 426 May 18 2012 R8C M11A Group R8C M12A Group 18 Comparator B 18 2 3 Comparator B3 Interrupt Control Register WCB3INTR Address 00182h Bit b7 b6 b5 b4 b3 b2 bi b Symbol WCB3F WCGRBOINTEN WCB3S1 WCB3S0 d WCB3F1 WCB3F0 After Reset 0 0 0 0 0 0 0 0 Bit Name Function WCB3F0 C tor B3 filt lect bits bi bo omparator ilter selec O O No filter 0 1 Filter sampled at f1 1 0 Filter sampled at f8 1 1 Filter sampled at f32 Es Nothing is assigned The write value must be 0 The read value is 0 WCB3F1 WCB3S0___ Comparator B3 interrupt edge select WCB3S1 Dis b5 b4 0 0 When the analog input voltage is lower than the reference input voltage 0 1 When the analog input voltage is higher than the reference input voltage 1 0 Do not set 1 1 When the analog input voltage is lower or higher than the analog input voltage WCBSINT
140. register P16SELO Port P1_6 function select bits Ee I O port or IVREF4 input P16SEL1 0 1 CLKO 1 0 TRJO 11 TRCIOB P17SELO Port P1_7 function select bits b7 b6 P17SEL1 0 0 I O port or AN7 input or IVCMP1 input 0 1 INT1 1 0 TRJIO 11 TRCCLK The PMH register is used to select the functions of pins P1_4 to P1_7 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 147 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 8 Port 1 Function Mapping Expansion Register PMH1E Address 000D1h Bit b7 b6 b5 b4 b3 b2 b1 b Smo peee e pase After Reset 0 0 0 0 0 0 0 0 Bit Name Function P14SEL2 The P1_4 pin function is selected in conjunction with bits P14SELO to P14SEL1 in the PMH1 register For details see 12 3 7 Port 1 Function Mapping Register 1 PMH1 Nothing is assigned The write value must be 0 The read value is 0 P15SEL2 The P1_5 pin function is selected in conjunction with bits P15SELO to P15SEL1 in the PMH1 register For details see 12 3 7 Port 1 Function Mapping Register 1 PMH1 Nothing is assigned The write value must be 0 The read value is 0 The PMHIE register is used to select the port 1 function in conjunction with registers PML1 and PMH1 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 148 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 9 Pin Settings for Port 1 Tables 12 4 to 12 11 l
141. register TI bit in x U0C1 register i iit From UOTB register to UARTO transmit register 1 fEXT Si a CLKO Receive data is taken in pang Jooo heege 27 Aeee hezeek From UARTO receive d S UORB register is read RI bit in register to UORB register UOC1 register E i SE U U ape U UORIF bit in 1 an UOIR register Set to 0 by a program fEXT Frequency of external clock The following requirements must be met when an input to the CLKO pin is high before data reception The above diagram applies for the following settings e TE bit in UOC1 register gt 1 transmission enabled e CKDIR bit in UOMR register 1 external clock e RE bit in U0C1 register gt 1 reception enabled CKPOL bit in UOCO register 0 transmit data is output on the falling Dummy data is written to UOTB register edge and receive data is input on the rising edge of the transfer clock Figure 16 3 Transmit and Receive Timing in Clock Synchronous Serial UO Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 288 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 1 2 Polarity Select Function Figure 16 4 shows the Transfer Clock Polarity The CKPOL bit in the UOCO register can be used to select the polarity of the transfer clock CKPOL bit in UOCO register 0 transmit data is output on the falling edge and receive data is input on the rising edge of the transfer clock e CKPOL bit in UOCO register 1 transmit
142. register causes the OFS2 register to be set to FFh When blank products are shipped the OFS2 register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS2 register is the value programmed by the user The OFS register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS register Erasure of the block including the OFS register causes the OFS register to be set to FFh When blank products are shipped the OFS register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS register is the value programmed by the user RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 25 of 426 May 18 2012 5 System Control R8C M11A Group R8C M12A Group 5 System Control 5 2 1 Processor Mode Register 0 PMO Address 00010h Bit b7 b6 b5 b4 b3 b2 b1 b Symboi EENEG EI After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Software reset bit 0 State is retained 1 Reset is generated Nothing is assigned The write value must be 0 The read value is 0 Set the PRC1 bit in the PRCR register to 1 write enabled before rewriting the PMO register SRST Bit Software reset bi
143. sets the IRIO bit to 0 This bit is also automatically set to 0 when the corresponding interrupt INTO is acknowledged IRI1 Bit INT1 interrupt request flag Writing 0 after reading the value sets the IRI1 bit to 0 This bit is also automatically set to 0 when the corresponding interrupt INT 1 is acknowledged IRI2 Bit INT2 interrupt request flag Writing 0 after reading the value 1 sets the IRI2 bit to 0 This bit is also automatically set to 0 when the corresponding interrupt INT2 is acknowledged IRI3 Bit INT3 interrupt request flag Writing 0 after reading the value sets the IRI3 bit to 0 This bit is also automatically set to 0 when the corresponding interrupt INT3 is acknowledged IRKI Bit Key input interrupt request flag Writing 0 after reading the value 1 sets the IRKI bit to 0 This bit is also automatically set to 0 when the corresponding interrupt key input is acknowledged The interrupt priority level register must be rewritten only while no interrupt requests corresponding to that register are generated See 11 9 7 Changing Interrupt Priority Levels and Flag Registers RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 118 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 10 Address Match Interrupt Register i AIADRi i 0 or 1 Address SE GE GE Ge Bit D d EE er Reset Address 001C1h AIADROM 001C5h AIADR1M Bit b15 b14 b13 b12 b11 b10 Symbol EE EE After
144. tatus confirmed 4 Flag in the CPU register FMRO01 FMRO2 Bits in the FMRO register FMR20 FMR21 Bits in the FMR2 register FST3 FST6 FST7 Bits in the FST register Notes 1 When executing the read array command and clear status register command this countermeasure is not necessary 2 Use one of the following instructions for the second command writing e MOV B A0 A1 or MOV B A1 A0 e MOV B IMM An e MOV B IMM abs16 e MOV B RnH An e MOV B RnH abs16 e MOV B RnL An e MOV B RnL abs16 Use one of the following instructions to read the same address as the second command write address e MOV B An RnL e MOV B An RnH e MOV W An Rn Confirm the suspend status using the FST3 bit for the program command and the FST6 bit for the block erase command Figure 19 23 Procedure for Software Command Execution When Suspend is Enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 366 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 8 3 Notes on Flash Memory Stop and Operation Transition 1 Do not enter stop mode while the FMSTP bit is 1 the flash memory is stopped 2 Do not enter wait mode while the FMSTP bit is 1 the flash memory is stopped and the WTFMSTP bit is 1 the flash memory is stopped in wait mode 3 Do not enter flash memory stop state for 42 us after entering from flash memory stop state to flash memory operation state And do not rewrite the LOCODIS bit in the OCOCR register
145. the interrupt request flag to 0 Set the interrupt request flag to 0 Interrupt enabled lt _ The interrupt is enabled Notes 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INTS or KIO to KI3 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INTS are used 2 See 11 9 7 Changing Interrupt Priority Levels and Flag Registers for the instructions to use and related notes Figure 11 13 Procedure for Manipulating Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN and Setting Interrupt Request Flag to 0 RO1UHO050EJ0200 Rev 2 00 RENESAS Page 136 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 9 5 INTI Input Filter i 0 to 3 When Returning from Wait Mode or Stop Mode to Standard Mode When a transition is made to wait mode or stop mode with the WCKSTP bit in the CKSTPR register set to 1 system clock stopped in wait mode while in use of the INTi input filter the INTi interrupt cannot be used to return to standard operating mode When the INTi interrupt is used to return set the WCKSTP bit to 1 and bits INTiF1 to INTiFO in the INTFO register to 00b no filter before a transition is made to wait mode or stop mode When the INTi input filter is used again select the sampling clock with bits INTiFO to INTiF1 to enable the INTiEN bit in the INTEN register Figure 11 14 sho
146. to 0 e When 0 is written to this bit e When a compare match occurs while the CSTP bit in the TRCCR2 register is 1 increment is stopped in PWM2 mode Condition for setting to 1 e When is written to this bit RO1UHO050EJ0200 Rev 2 00 RENESAS Page 235 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 4 Timer RC Control Register 1 TRCCR1 Address 000F3h Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol After Reset 0 0 0 0 0 0 0 0 Bit Name Function Timer output level select A bit 0 Output value 0 1 Timer output level select B bit 1 Output value 1 1 Timer output level select C bit Timer output level select D bit Count source select bits b6 b5 b4 000 001 010 011 100 10 1 Falling edge of TRCCLK input 3 1 1 0 fHOCO 2 11 1 Do not set TRCCNT counter clear select bit 0 Clear disabled free running operation 1 TRCCNT counter is cleared by input capture compare match A Notes 1 The values set by bits TOA to TOD are reflected immediately after they are changed Set the value when the CTS bit in the TRCMR register is 0 count is stopped 2 When selecting fHOCO set these bits with the on chip oscillator operating When switching the count sources set these bits with the counter stopped 3 The pulse width of an external clock input to TRCCLK must be three or more cycles of the operating clock TOA Bit Timer output level select A bit This bit i
147. to 0 not open drain RO1UHO050EJ0200 Rev 2 00 RENESAS Page 159 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 5 5 Port 4 Function Mapping Register 0 PML4 Address 000CEh Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo pempe After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 P42SELO Port P4_2 function select bits b5 b4 0 0 I O port P42SEL1 0 1 TRBO 1 0 TXDO 11 KI3 Nothing is assigned The write value must be 0 The read value is 0 The PML4 register is used to select the P4_2 pin function 12 5 6 Port 4 Function Mapping Register 1 PMH4 Address 000CFh Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol P47SEL1 P47SELO P46SEL1 P46SELO P45SEL1 P45SEL0 0 0 0 0 0 0 0 0 After Reset Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 P45SELO Port P4_5 function select bits b3 b2 P45SELI 0 0 I O port 0 1 INTO 10 ADTRG 1 1 Do not set P46SELO Port P4_6 function select bits 0 0 0 VO port or XIN input P46SEL1 E RXDO i 0 0 1 RXDO 0 1 0 TXDO 011 INT1 100 VCOUT1 101 TRJIO Other than the above Do not set bx P46SEL2 bit in the PMH4E register P47SELO Port P4_7 function select bits b7 b6 0 0 I O port or XOUT output P47SEL1 0 1 INT2 Other than the above Do not set The
148. to ratio select bits system base clock fBASE to generate the PHISELO system clock f and the A D converter clock fAD e System clock f f fBASE n 1 e Clock for A D converter fAD fAD fBASE n 1 when n 1 is nota multiple of 4 fAD 4 x fBASE n 1 when n 1 isa multiple of 4 n Binary value set by the PHISEL register Setting Range 00h to FFh Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the PHISEL register Table 9 6 lists the PHISEL Register Setting Example Table 9 6 PHISEL Register Setting Example Value Set in PHISEL Register n System Clock f A D Converter Clock fAD fBASE fBASE Division of fBASE by 2 Division of fBASE by 2 Division of fBASE by 3 Division of fBASE by 3 Division of fBASE by 4 fBASE Division of fBASE by 5 Division of fBASE by 5 Division of fBASE by 6 Division of fBASE by 6 Division of fBASE by 7 Division of fBASE by 7 Division of fBASE by 8 Division of fBASE by 2 RO1UHOO50EJ0200 Rev 2 00 ztENESAS May 18 2012 Page 79 of 426 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 5 Clock Stop Control Register CKSTPR Address 00024h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol SCKSEL T _ PSCSTP WCKSTP STPM After Reset 0 0 0 0 0 0 0 0 Bit Name Function STPM All clock stop control bit 0 Clocks oscillate 1 All clocks are stopped
149. x 2 wait states When the oscillation stop detection function is disabled the system base clock used after returning from stop mode is the XIN clock The stabilization time generated by the hardware is expressed as follows Stabilization time XIN clock period x System clock division ratio x Number of steps for stabilization When the oscillation stop detection function is enabled the system base clock used after returning from stop mode is the low speed on chip oscillator clock The stabilization time generated by the hardware is expressed as follows Stabilization time Low speed on chip oscillator clock cycle x System clock division ratio x Number of steps for stabilization RO1UHO050EJ0200 Rev 2 00 stENESAS Page 82 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 7 Oscillation Stop Detection Register BAKCR Address 00026h Bit b7 b6 b5 b4 b3 b2 b1 b Smo __ CKSWIF XINHALT CKSWIE XINBAKE After Reset 0 0 0 0 0 0 0 0 Bit Name Function XINBAKE Oscillation stop detection enable bit Oscillation stop detection function disabled Oscillation stop detection function enabled CKSWIE Oscillation stop detection interrupt Interrupt disabled enable bit Interrupt enabled XINHALT Clock monitor bit 1 XIN clock oscillating XIN clock halted CKSWIF Oscillation stop detection interrupt No oscillation stop detection interrupt request is request fla
150. 0 Electrical Characteristics Table 20 6 Flash Memory Blocks A and B of Data Flash Electrical Characteristics Standard Typ Parameter Condition Program erase endurance 2 Byte programming time Block erase time Time delay from suspend request until 0 25 CPU clock suspend x 3 cycles Time from suspend until erase restart 30 CPU clock x 1 cycle td CMDRST Time from when command is forcibly 30 CPU clock READY stopped until reading is enabled x 1 cycle Program erase voltage 1 8 5 5 Read voltage 1 8 5 5 Program erase temperature 20 85 N version 40 85 D version Data hold time 7 Ambient temperature 85 C 10 1 Vcc 2 7 V to 5 5 V and Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified 2 Definition of program erase endurance The number of program erase cycles is defined on a per block basis If the number of cycles is 10 000 each block can be erased 10 000 times For example if 1 024 cycles of 1 byte write are performed to different addresses in 1 Kbyte of block A and then the block is erased the number of cycles is counted as one Note however that the same address must not be programmed more than once before completion of an erase overwriting prohibited 3 This indicates the number of times up to which all electrical characteristics can be guaranteed after the last programming erase operation Operatio
151. 0 reset enabled after reset to use the power on reset CSPROINI Bit Count source protection mode after reset select bit This bit is used to select whether to protect the count source for the watchdog timer from being changed RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 32 of 426 May 18 2012 R8C M11A Group R8C M12A Group 5 System Control 5 3 ID Code Check Function The ID code check function prevents the flash memory from being read rewritten or erased when standard serial I O mode is used This function is realized by examination of the ID codes written in the ID code area For details see 19 3 ID Code Check Function 5 4 Register Access Protect Function The protection function protects important registers from being easily rewritten if a program runs out of control Table 5 2 lists the PRCR Register Bits and Registers Protected For details on each bit see 5 2 3 Protect Register PRCR Table 5 2 PRCR Register Bits and Registers Protected Registers Protected Registers EXCKCR OCOCR SCKCR PHISEL CKSTPR CKRSCR BAKCR FRV1 and FRV2 Registers PMO and RISR Registers VCA2 VD1LS VWOC and VW1C PINSR register Table 5 3 lists the HRPR Register Bit and Register Protected For details on each bit see 5 2 4 Hardware Reset Protect Register HRPR Table 5 3 HRPR Register Bit and Register Protected Dn Registers Protected PAMCRE PAMCR register RO1UHO050Ev0200 Rev 2 00 stENESAS Page 33 of 426 May
152. 0 3 Parameter Resolution A D Converter Characteristics Condition Standard Absolute accuracy AVcc 5 0 V ANO to AN4 AN7 input AVcc 3 0 V ANO to AN4 AN7 input AVcc 1 8 V ANO to AN4 AN7 input A D conversion clock 4 0 V lt AVcc lt 5 5 V 2 3 2 V lt AVcce lt 5 5 V 2 2 2 7 V lt AVcce lt 5 5 V 2 1 8 V lt AVcce lt 5 5 V 2 Permissible signal source impedance Conversion time AVcc 5 0 V A D conversion clock 20 MHz Sampling time A D conversion clock 20 MHz Analog input voltage 1 Vcc AVcc 1 8 V to 5 5 V and Vss 0 V and Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified 2 The A D conversion result will be undefined in stop mode or when the flash memory is in low current consumption read mode or stopped Do not perform A D conversion in these states Do not enter these states during A D conversion Table 20 4 Parameter IVREF1 IVREF3 input reference voltage Comparator B Electrical Characteristics Condition Standard IVCMP1 IVCMP3 input voltage Offset Comparator output delay time 2 Vi Vref 100 mV Notes Comparator operating current Vcc 5 0 V 1 Vcc 2 7 V to 5 5 V and Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified 2 When the
153. 0 7 Voltage Detection 0 Circuit Electrical Characteristics ae Standard Parameter Condition Typ Nodem Voltage detection level Vdet0_0 2 1 80 1 90 2 05 V Voltage detection level Vdet0_1 2 2 15 2 35 2 50 V Voltage detection level Vdet0_2 2 2 70 2 85 3 05 V Voltage detection level Vdet0_3 2 3 55 3 80 4 05 V Voltage detection 0 circuit response time 3 When Vcc decreases from 5 V 30 us to Vdet0_0 0 1 V Self power consumption in voltage detection VCOE 1 Vcc 5 0 V 1 5 uA circuit EA Wait time until voltage detection circuit 100 us operation starts 4 Notes 1 The measurement condition is Vcc 1 8 V to 5 5 V and Topr 20 C to 85 C N version 40 C to 85 C D version Select the voltage detection level with bits VDSELO and VDSEL1 in the OFS register 2 3 The response time is from when the voltage passes Vdeit until the voltage monitor 0 reset is generated 4 The wait time is necessary for the voltage detection circuit to operate when the VCOE bit in the VCA2 register is set to 0 and then 1 Table 20 8 Parameter Voltage detection level Vdet1_1 2 Voltage Detection 1 Circuit Electrical Characteristics Condition When Vcc decreases Standard Typ lt Voltage detection level Vdet1_3 2 When Vcc decreases When Vcc decreases Voltage detection level Vdet1_7 2 When Vcc decreases Voltage detection level Vdet1_5 2 Voltage det
154. 0 of 426 May 18 2012 R8C M11A Group R8C M12A Group FMRO Register FMSTP Bit 0 flash memory operates 1 flash memory is stopped 0 flash memory operates Figure 10 3 FMR1 Register WTFMSTP Bit 1 flash memory is stopped in wait mode 0 flash memory operates in wait mode Wait mode VCA2 Register LPE Bit 0 low power consumption wait mode disabled 1 low power consumption wait mode enabled 0 low power consumption wait mode disabled 1 low power consumption wait mode enabled 0 low power consumption wait mode disabled 1 low power consumption wait mode enabled Internal Power Stabilization Time TO Internal Power Stabilization Time Time until Flash Memory Stabilization Activation T1 60 us max Flash memory is not activated Flash memory activation sequence Interrupt request is generated Set by bits CKSTO to CKST3 in the CKRSCR register if the clocks are switched when returning from wait mode 0 if the clocks are not switched when returning from wait mode stabilization time SCKCR Register is Set to 1 Wait Mode is Entered 10 Power Control Time until CPU Clock Supply T3 Remarks The total on the left CPU clock amounts to period the time from x wait mode 2cycles until execution of an interrupt routine Setting prohibited CPU clock restart sequence
155. 00035h Periodic Timer Interrupt Control Register 00075 00036h 00076 00037h 00077 00038h External Input Enable Regis 00078 00039h 00079 0003Ah INT Input Filter Select Regis 0007Ah 0003Bh 0007Bh 0003Ch INT Input Edge Select Regis 0007Ch 0003Dh 0007Dh 0003Eh Key Input Enable Register 0007Eh 0003Fh 0007Fh Note 1 The blank areas are reserved No access is allowed 00080h Register Name ARTO Transmit Receive Mode Register 000C0 Register Name 00081h ARTO Bit Rate Register 000C1 Open Drain Control Register 1 00082h 00083h ARTO Transmit Buffer Register 000C2 000C3 Open Drain Control Register 3 00084h ARTO Transmit Receive Control Register 0 000C4 Open Drain Control Register 4 00085h ARTO Transmit Receive Control Register 1 000C5 Port PA Mode Control Register 00086h 00087h ARTO Receive Buffer Register 000C 6 000C7 00088h ARTO Interrupt Flag and Enable Register 000C8 ion Mapping Register 0 00089h 000C9 ion Mapping Register 1 0008Ah 000CAh 0008Bh 000CBh 0008Ch 000CCh ion Mapping Register 0 0008Dh 000CDh ion Mapping Register
156. 015h 00055 00016h Hardware Reset Protect Register 00056 00017h 000571 00018h 00058h Voltage Monitor Circuit Edge Select Register 00019h 000591 0001Ah 0005Ah Voltage Detect Register 2 0001Bh 0005Bh Voltage Detection 1 Level Select Register 0001Ch 0005Ch Voltage Monitor 0 Circuit Control Register 0001Dh 0005Dh Voltage Monitor 1 Circuit Control Register 0001Eh 0005Eh 0001Fh 0005Fh Reset Source Determination Register 00020h External Clock Control Register EXCKCR 00060h 00021h High Speed Low Speed On Chip Oscillator OCOCR 00061 Control Register 00062 00022h System Clock f Control Register SCKCR 00063 00023h System Clock f Select Register PHISEL 00064h High Speed On Chip Oscillator 18 432 MHz FR18S0 00024h Clock Stop Control Register CKSTPR Control Register 0 00025h Clock Control Register When Returning from CKRSCR 00065h High Speed On Chip Oscillator 18 432 MHz FR18S1 Modes Control Register 1 00026h Oscillation Stop Detection Register BAKCR 00066 00027h 00067h High Speed On Chip Oscillator Control Register 1 00028h 00068h High Speed On Chip Oscillator Control Register 2 00029h 00069h 0002Ah 0006Ah 0002Bh 0006Bh 0002Ch 0006Ch 0002Dh 0006Dh 0002Eh 0006Eh 0002Fh 0006Fh 00030h Watchdog Timer Function Register 00070h 00031h Watchdog Timer Reset Register 00071 00032h Watchdog Timer Start Register 00072 00033h Watchdog Timer Control Register 00073 00034h Count Source Protection Mode Register 00074
157. 0200 Rev 2 00 RENESAS Page 199 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 2 Timer RB One Shot Control Register TRBOCR Address 000E1h Bit b7 b6 b5 b4 b3 b2 b1 b Smo ll EES TOssP TOSST After Reset 0 0 0 0 0 0 0 0 Bit Name Function Timer RB one shot start bit 1 2 When 1 is written to this bit a one shot trigger is generated The read value is 0 TOSSP Timer RB one shot stop bit 2 3 When 1 is written to this bit the one shot pulse count including wait time is stopped The read value is 0 TOSSTF Timer RB one shot status flag 0 One shot is stopped 1 One shot is operating including wait period Nothing is assigned The write value must be 0 The read value is 0 Notes 1 Make sure the TOSSTF bit is 0 one shot is stopped before writing 1 one shot count is started to the TOSST bit 2 When 0 is written to this bit the value is invalid 3 Make sure the TOSSTF bit is 1 one shot is operating including wait period before writing 1 one shot count is stopped to the TOSSP bit TOSSTF Bit Timer RB one shot status flag Conditions for setting to 0 e When the TSTOP bit in the TRBCR register is set to 1 count is forcibly stopped e When the count value reaches 00h and is reloaded in programmable one shot generation mode e When the secondary count value reaches 00h and is reloaded in programmable wait one shot generation mode e When the TOS
158. 04FDh Figure 21 6 External Pulse Signal Timing in Event Counter Mode 1 TRUJIO pin TEDGSEL bit in TRJIOC register TSTART bit in TRJCR register Count source Counter 0503h initial value 0502h 0501h 0500h 04FFh 04FEh 04FDh 04FCh Figure 21 7 External Pulse Signal Timing in Event Counter Mode 2 R01UH0050EJ0200 Rev 2 00 ztENESAS Page 398 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 8 Notes on Timer RB2 e Timer RB2 stops counting after a reset Start the count after setting the value in the timer and prescaler e In the 8 bit timer with 8 bit prescaler even if the prescaler and timer are read in 16 bit units they are actually read sequentially byte by byte in the MCU This may cause the value in the timer to be updated during reading of these two registers In the 16 bit timer access the TRBPRE register first and then the TRBPR register Read the TRBPRE register first to read the count value in the lower byte The count value in the higher byte will be retained Next read the TRBPR register to read the retained value in the higher byte The timer value is not updated during reading of these two registers e In programmable one shot and programmable wait one shot generation modes when the TOSSP bit in the TRBOCR register is set to 1 and the one shot is stopped the timer reloads the reload register value and is stopped The timer count value must be read before the timer is stopped e After
159. 050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 219 of 426 R8C M11A Group R8C M12A Group 14 Timer RB2 14 5 2 Prescaler and Counter Using TWRC Bit In timer RB2 the TWRC bit in the TRBMR register can be used to select whether to write to the reload register only TRBPR TRBSC TRBPRE or both the reload register and counter However when the TCSTF bit in the TRBCR register is 0 count is stopped both the reload register and counter are written regardless of the setting of the TWRC bit In the 8 bit timer with 8 bit prescaler when the TWRC bit is 0 write to reload register and counter transfer from the reload register to the prescaler is performed in synchronization with the count source and transfer to the counter is performed in synchronization with prescaler underflows Therefore the count value is not updated immediately after the write instruction is executed When the TWRC bit is 1 write to reload register only transfer from the reload register to the prescaler is performed in synchronization with prescaler underflows and transfer to the counter is performed in synchronization with counter underflows Only the value of the prescaler is updated before the counter underflows Figures 14 10 and 14 11 show Examples of Prescaler and Counter Operation in 8 Bit Timer with 8 Bit Prescaler In the 16 bit timer when the TWRC bit is 0 write to reload register and counter transfer to the 16 bit counter is performed in synchronization wi
160. 1 0008Eh 000CEh ion Mapping Register 0 0008Fh 000CFh ion Mapping Register 1 00090h 000D0 00091h 000D1 ion Mapping Expansion Register 00092h 000D2 00093h 000D3 00094h 000D4 00095h 000DS ion Mapping Expansion Register 00096h 000D 6 00097h 000D7 00098h 00099h A D Register 0 ADOL ADOH 000D8 o00D 9 Timer RJ Counter Register 0009Ah 0009Bh A D Register 1 ADIL AD1H 000DAh Timer RJ Control Register 000DBh Timer RJ I O Control Register 0009Ch A D Mode Register ADMOD 000DCh Timer RJ Mode Register 0009Dh A D Input Select Register ADINSEL 000DDh Timer RJ Event Select Register 0009Eh A D Control Register 0 ADCONO 000DEh Timer RJ Interrupt Control Register 0009Fh A D Interrupt Control Status Register ADICSR 000DFh 000A0h 000E0h Timer RB Control Register 000A1h 000E1h Timer RB One Shot Control Register 000A2h 000E2h Timer RB UO Control Register 000A3h O00E3h Timer RB Mode Register 000A4h 000E4h O00ASh 000A6h Timer RB Prescaler Register Timer RB Primary Secondary Register Lower 8 Bits 000A7h O00ESh 000A8h Timer RB Primary Register Timer RB Primary Register Higher 8 Bits 000E6h 000A9h Port P1 Direction Register OO0AAh Timer
161. 1 interrupt signal Non maskable interrupt signal Page 51 of 426 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 2 Registers Table 7 2 lists the Voltage Detection Circuit Register Configuration Table 7 2 Voltage Detection Circuit Register Configuration Register Name After Reset Address Access Size Voltage Monitor Circuit Edge Select Register 00h 00058h Voltage Detect Register 2 Note 1 0005Ah Voltage Detection 1 Level Select Register 00000111b 0005Bh Voltage Monitor 0 Circuit Control Register Note 1 0005Ch Voltage Monitor 1 Circuit Control Register 10001010b 0005Dh Note 1 See the description of the individual registers 7 2 1 Voltage Monitor Circuit Edge Select Register VCAC Address 00058h Bit b7 b6 b5 b4 b3 b2 b 0 0 0 0 0 1 b gw reet After Reset 0 Bit Name Function Reserved Set to 0 Voltage monitor 1 circuit edge select bit 1 0 One way edge 1 Two way edge Reserved Set to 0 Nothing is assigned The write value must be 0 The read value is 0 Note 1 When the VCAC1 bit is 0 one way edge the VW1C7 bit in the VW1C register can be used to select an interrupt generated when the voltage increases or decreases Set the VCAC1 bit to 0 before setting the VW1C7 bit RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 52 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 2 2 Voltage
162. 1 Set the CTS bit in the TRCMR register to 0 count is stopped 2 Change bits CKSO to CKS2 in the TRCCR1 register 3 Wait for at least two cycles of the system clock 4 Set the HOCOE bit in the OCOCR register to 0 high speed on chip oscillator off RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 275 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 7 5 Input Capture Function e Set the pulse width of the input capture signal as follows When the digital filter is not used Three or more cycles of the timer RC operation clock refer to Table 15 1 Timer RC Specifications When the digital filter is used Five cycles of the digital filter sampling clock three cycles of the timer RC operating clock minimum refer to Figure 15 19 Digital Filter Circuit Block Diagram e The value of the TRCCNT register is transferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj j A B C or D pin when the digital filter function is not used 15 7 6 TRCMR Register in PWM2 Mode When the CSTP bit in the TRCCR2 register is 1 increment is stopped do not set the TRCMR register when a compare match occurs between registers TRCCNT and TRCGRA 15 7 7 MSTCR Register After stopping the timer RC count set the MSTTRC bit in the MSTCR register to standby 15 7 8 Mode Switching e When switching the modes during operation set the CTS bit in the
163. 14 3 Example of 8 Bit Timer with 8 Bit Prescaler Operation in Programmable Waveform Generation Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 210 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 Set to 1 by a program TSTART bit in TRBCR register Count source f i r J Timer RB2 counter 0101h 0100h OOFFh Timer RB e is reloaded Timer RB a is reloaded I I U Interrupt request signal I Set to 0 by a program TRBIOC register D i H Set to 0 by a program i i 1 U I TOPL bit in U 1 1 Waveform output is started Waveform output is inverted Waveform output is started TRBO pin output i I i The level of the initial output is Primary period d Secondary period the same as that of the inverted TRBPRE TRBPR 1 TRBPRE TRBSC 1 TOPL bit value fixed value output Primary period TRBPRE TRBPR The above diagram applies under the following conditions TRBPRE register 01h TRBPR register 01h TRBSC register 02h TOPL bit 0 TOCNT bit 0 waveform output in TRBIOC register e TCNT16 bit in TRBMR register 1 16 bit timer Figure 14 4 Example of 16 Bit Timer Operation in Programmable Waveform Generation Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 211 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 4 3 Programmable One Shot Generation Mode In this mode a one shot pulse is output from the TRBO pin by a
164. 14 5 2 Description revised 221 to 224 Figures 14 10 to 14 13 revised 227 228 14 8 and 21 8 revised 399 400 229 Table 15 1 Operating clock added 232 15 2 1 Description revised 233 234 15 2 2 Description deleted Tables 15 5 to 15 8 added 235 15 2 3 Notes 1 and 2 revised REVISION HISTORY R8C M11A Group R8C M12A Group User s Manual Hardware Description Summary May 18 2012 236 15 2 4 b7 Function revised Note 3 added 238 15 2 6 Note 1 added Table 15 9 Note 2 added 239 15 2 7 bO b1 b4 b5 Function revised Note 1 revised 240 241 15 2 8 bO b1 b4 and b5 Function revised Note 8 added 242 15 2 10 Description deleted bO to b4 Function revised Notes 1 and 2 added 243 15 2 11 Note 3 added 246 Table 15 10 revised 251 15 3 2 Description revised 253 Figure 15 10 and title revised 255 15 3 3 Description revised 257 Figure 15 14 15 3 3 Description revised 262 Figure 15 19 revised 264 15 4 3 Description revised 266 15 4 4 Description revised 267 Figure 15 24 revised 271 Figure 15 31 revised 273 15 5 8 Figure 15 34 revised 274 15 6 Timer RC Interrupt added 275 276 15 7 4 15 7 5 25 9 4 and 25 9 5 revised 556 557 277 16 1 Description revised 280 16 2 1 Notes 1 and 2 added 284 16 2 6 b0 to b8 Bit Name Note 1 revised Note 2 added 288 293 Figures 16 3 16 6 and 16 7 revised 294 291 16 3 2 Note 2 added 297 16 4 Description revised 299 Table 17 1 revised 308 Table
165. 17 6 Notes 1 and 2 revised 309 to 312 Figures 17 4 to 17 7 revised 314 404 17 5 2 and 21 11 2 Description revised 328 19 3 2 1 and 19 3 2 2 Description revised 329 19 4 Description Table 19 5 revised 330 19 5 1 After Reset revised Notes 1 to 4 added 331 19 5 1 RDYSTI and BSYAEI Description revised 332 19 5 1 Bits FST2 to FST6 Description revised FST7 bit Description added 19 5 2 Notes 2 to 4 FMSTP bit description revised FMRO1 and FMRO2 bit description added 19 5 2 CMDRST CMDERIE BSYAEIE and RDYSTIE bit description revised 19 5 3 FMR13 bit description revised FMR16 and FMR17 bit description added 19 5 4 Note 2 and FMR22 bit revised FMR20 bit description added 19 5 4 FMR27 bit description revised REVISION HISTORY R8C M11A Group R8C M12A Group User s Manual Hardware Description Summary May 18 2012 19 6 1 Description revised 340 Table 19 7 Notes 1 to 3 added Figure 19 3 revised 341 Figure 19 4 revised 343 19 6 5 Description revised 344 19 6 6 Description revised and 19 6 6 1 Read Array added 345 19 6 6 2 and 19 6 6 3 Description revised 348 Figure 19 11 revised 349 19 6 6 4 Description revised 352 Figure 19 15 revised 355 Figure 19 18 revised 356 Table 19 9 revised 359 Table 19 10 revised 360 Table 19 11 revised 362 363 Tables 19 12 19 13 21 1 and 21 2 revised 407 408 364 409 19 8 2 6 and 21 12 2 6 revised 365 366 19 8 2 9 EW1 Mode and 21 15
166. 170h 00171h 00172h 00173h 00174h 00175h 00176h 00177h 00178h 00179h 0017Ah 0017Bh 0017Ch 0017Dh 0017Eh 0017Fh Note 1 The blank areas are reserved No access is allowed R01UH0050EJ0200 Rev 2 00 CENESAS P 2 ee ate age 20 of 426 R8C M11A Group R8C M12A Group 3 Address Space Table 3 7 Address 00180h SFR Information 7 Register Name Comparator B Control Register Symbol After Reset 00181h Comparator B1 Interrupt Control Register WCMPR WCBIINTR 00182h Comparator B3 Interrupt Control Register WCB3INTR 00183h 00184h 00185h 00186h 00187h 00188h 00189h 0018Ah 0018Bh 0018Ch 0018Dh 0018Eh 0018Fh 00190h 00191h 00192h 00193h 00194h 00195h 00196h 00197h 00198h 00199h 0019Ah 0019Bh 0019Ch 0019Dh 0019Eh 0019Fh 001A0h 001A1h 001A2h 001A3h 001A4h 001A5h 001A6h 001A7h 001A8h 001A9h Flash Memory Status Register 10000000b 001AAh Flash Memory Control Register 0 00h 001ABh Flash Memory Control Register 1 00h 001ACh Flash Memory Control Register 2
167. 18 2012 R8C M11A Group R8C M12A Group 5 System Control 5 5 Option Functions The option functions allow the user to select the MCU state after a reset is cleared Table 5 4 lists the Option Functions The option functions can be selected by registers OFS2 and OFS These registers are allocated at the addresses OFFFFh highest of the reset vector and OFFDBh as shown in Figure 5 1 The option function select area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Option function select area Address E E OFFD8h to OFFDBh OFS2 Reserved area H OFFFCh to OFFFFh Core Reset vector 4 L L Le 4 bytes Figure 5 1 Option Function Select Area Table 5 4 Option Functions Option Function Name Register Name Bit Name Reference Watchdog timer Start select function OFS register WDTON bit 8 Watchdog Timer Count source protection CSPROINI bit select function Underflow period select OFS2 register Bits WDTUFSO to function WDTUFS1 Refresh acceptance Bits WDTRCSO to period select function WDTRCS1 Voltage detection Voltage monitor 0 reset OFS register Bits VDSELO to 6 Resets circuit level function VDSEL1 7 Voltage Detection Circuit Voltage monitor 0 reset LVDAS bit start select function Flash memory ROM code protection Bits ROMCR to 19 Flash Memory function ROMCP1 R01UH0050EJ0
168. 1UHO050EJ0200 Rev 2 00 ztENESAS Page 245 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 3 Operation Table 15 10 lists the Timer RC Operating Modes Table 15 10 Timer RC Operating Modes Item Description Timer mode Timer mode is used by setting the PWM2 bit to 0 and bits PWMB to PWMD to 0 in the TRCMR register In this case the output compare function or input capture function is used by setting bits IOAO to IOA2 and IOBO to IOB2 in the TRCIORO register and bits OCO to IOC2 and IODO to IOD2 in the TRCIOR1 register PWM mode is used by setting the PWM2 bit to 0 and bits PWMB to PWMD to 1 in the TRCMR register PWM2 mode is used by setting the PWM2 bit in the TRCMR register to 1 PWM mode PWM2 mode Tables 15 11 to 15 14 list the settings of pins TRCIOA to TRCIOD For the assignments of pins TRCIOA to TRCIOD see 12 I O Ports Table 15 11 TRCIOA Pin Settings Register TRCOER TRCIORO Bit Setting value X 0or 1 IOA1 Function Timer mode waveform output output compare function Timer mode input capture function Table 15 12 TRCIOB Pin Settings Register TRCOER TRCIORO Bit Setting value X 0 or 1 EB lOB2 IOB1 IOBO I O port Function PWM2 mode waveform output PWM mode waveform output Timer mode waveform output output compare function 0 1 Timer mode input captur
169. 2 18 show the I O Port Configuration Figure 12 19 shows the Pin Configuration P1_0 to P1_1 Pull up selection Direction register Pin function mapping register Open drain _ _ Output from O individual peripheral selection function enabled S Output from individual peripheral function Port latch lt Pin function Input to individual peripheral function mapping register Analog input to A D converter Digital Input to external interrupt filter IOINSEL Bit in PINSR register Figure 12 6 UO Port Configuration 1 P1_2 to P1_4 Drive capacity selection Pull up selection Direction Pin function mapping register Output from individual peripheral lt function enabled i Output from individual Li peripheral function Q H O Pin function Input to individual peripheral function mapping register Analog input to A D converter Drive capacity selection Input to external interrupt IOINSEL Bit in PINSR register Figure 12 7 UO Port Configuration 2 RO1UHO050EJ0200 Rev 2 00 RENESAS Page 168 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Drive capacity selection Pull up selection Direction Pin function mapping register Open drain Output from O 3 individual peripheral selection lt function enabled Output from individual peripheral function Pin function mapping register Drive capa
170. 2 9 EW1 Mode added 410 411 367 412 19 8 3 Notes on flash memory stop and operation transition and 21 15 3 Notes on flash memory stop and operation transition added 370 Table 20 3 revised 417 Appendix Figure 2 1 Note 1 revised 422 to 424 Appendix 4 Comparison between R8C M12A Group and R8C M13B Group added R8C M11A Group R8C M12A Group User s Manual Hardware Publication Date Rev 0 01 Jan 29 2010 Rev 2 00 May 18 2012 Published by Renesas Electronics Corporation 2 CENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 903 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204
171. 200 Rev 2 00 RENESAS May 18 2012 Page 34 of 426 R8C M11A Group R8C M12A Group 5 System Control 5 6 Notes on System Control 5 6 1 Option Function Select Area Setting Example The option function select area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program The following shows a setting example e To set FFh in the OFS2 register org OOFFDBH byte OFFh Programming formats vary depending on the compiler Check the compiler manual e To set FFh in the OFS register org OOFFFCH lword reset OFFOOO000h RESET Programming formats vary depending on the compiler Check the compiler manual RO1UHO050EJ0200 Rev 2 00 stENESAS Page 35 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 Resets The following resets are provided hardware reset power on reset voltage monitor 0 reset triggered by the voltage detection circuit watchdog timer reset and software reset 6 1 Overview Table 6 1 lists the Reset Names and Sources Figure 6 1 shows the Reset Circuit Block Diagram Table 6 1 Reset Names and Sources Reset Name Hardware reset When a low level is input to the RESET pin Power on reset When VCC is turned on Voltage monitor 0 reset When VCC decreases below Vdet0 which is detected by voltage detection circuit 0 Watchdog timer reset When the watchdog timer underflows Software reset When 1 is written to the SRST bit in the PMO register by a program
172. 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2012 Renesas Electronics Corporation All rights reserved Colophon 1 1 R8C M11A Group R8C M12A Group tENESAS Renesas Electronics Corporation R01UH0050EJ0200
173. 377 of 426 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Timing Requirements Vcc 5 V Vss 0 V at Topr 25 C unless otherwise specified Table 20 15 External Clock Input XIN Standard Symbol Parameter mm Min 50 24 24 te XIN XIN input cycle time TWH XIN XIN input high width tWL XIN XIN input low width External Clock input Figure 20 4 External Clock Input Timing When Vcc 5 V Table 20 16 TRJIO Input Standard Symbol Parameter eee Min te TRUIO TRJIO input cycle time 100 tWH TRJIO TRJIO input high width 40 twL TRJIO TRJIO input low width 40 tC TRJIO TRJIO input Figure 20 5 TRJIO Input Timing When Vcc 5 V RO1UHO050Ev0200 Rev 2 00 stENESAS Page 378 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 17 Serial Interface Standard Parameter Min te Ck CLKO input cycle time tw CKH CLKO input high width tw CKL CLKO input low width ta C Q TXDO output delay time th C Q TXDO hold time tsu D C RXDO input setup time th C D RXDO input hold time Figure 20 6 Serial Interface Timing When Vcc 5 V Table 20 18 External Interrupt INTi Input Key Input Interrupt Kli i 0 to 3 Standard Min Parameter tw INH INTI input high width KI input high width tW INL INTI input low width Kli input low width 1 When t
174. 4 2 When A D conversion has completed on each channel the result is transferred to the corresponding ADi register i 0 or 1 3 When A D conversion has completed on all the selected channels the ADF bit in the ADICSR register is set to interrupt requested Writing 0 after reading the value sets the ADF bit to 0 no interrupt requested 4 While the ADST bit is 1 A D conversion starts steps between 2 and 3 are repeated When the ADST bit is set to 0 A D conversion stops A D conversion is stopped and the A D converter enters the standby state Then when the ADST bit is set to 1 A D conversion is restarted from ANO when channel group 0 is selected and AN2 when channel group 1 is selected When channel group 2 is selected A D conversion is started from AN4 Set to 1 by a program Set to 0 by a program A D conversions are performed repeatedly I U 1 ADST bit in A D conversion ADCONDO register starts Set to 0 bya ADF bit in program ADICSR register Channel 0 ANO Standby for A D Standby for A D 1 A A d d Standby for conversion in operation conversion conversion 1 conversion conversion 3 H i i Li U Standby for A D conversion conversion 2 conversion conversion 4 1 Standby for conversion Channel 1 AN1 in operation standby fo z o Channel 2 AN2 U g Standby for conversion in operation 1 Channel 3 AN3 U Stand for conversion in operation 1 Channel 4 AN4 in
175. 4 CPU DEET 329 19 5 Registers CPU Rewrite Modernne i a E E R EE A E E R EA k 330 195 1 Flash Memory Status Register FST misemi nn ea E E E EE E E R RSE 330 19 5 2 Flash Memory Control Register O FMRO ssssesesssesssresrssssrssssrerssresrsrenrerrnsesesserrssrerestentereneeresserresrereere 333 19 5 3 Flash Memory Control Register 1 FMR1 sesesessssesssresrsresrsresserrsesrestererresestssertsseeeestentstentrrrnsesresreresrt 335 19 5 4 Flash Memory Control Register 2 FMR2 sessesesserssssresesresrsresserrserresrnrestesestestrrrsrersseetsrenterrnsesreereresrt 336 19 5 5 Flash Memory Refresh Control Register FREFR AAA 338 19 6 CPU Rewrite Mode rrarena e E A EERE E ERE E Eed Eed SEEE STEF 339 19 6 1 HMO Moe AE 339 19 6 2 EWL MOE nrinn Secherheet 339 19 6 3 Suspend Operation EE 340 19 6 4 Setting and Cancelling Each Mode A 342 19 6 5 Data Protect Funci n nisreen tresen EENS OP EEE EE EEEE 343 19 6 6 Software Commande ise s e E e E EEN 344 Jet Pull Status CROCK ss cssencosesesces dy cndevevsdeseesteedivesdossestpesletereduyetees tut EEEE EE E ATE SS EES SEEE 356 19 7 Standard Serial UO Mode siin aae r E E E E a a AA a KEREN 358 19 8 Notes on Flash Memory 21252 Loss ce Go oniani a oE E oA see EE EE EOR 361 19 8 1 ID Code Area Setting Example cc cccscscsscsscssseeschvasscsescseesssseschvecoctesssougsvvessssnsssvessseastsentoseenesubesseasssonsess 361 19 8 2 gt CPU Rewrite Mode ee Wikies EEN ESA 362 19 8 3 Notes on Flash Memo
176. 4 Register 000B2h Port PA Register 000B3h Pull Up Control Register 1 000B5h Pull Up Control Register 3 000B7h Pull Up Control Register 4 000B8h Port I O Function Control Register 000B9h Drive Capacity Control Register 1 000BBh Drive Capacity Control Register 3 000BDh Open Drain Control Register 1 000C1h Open Drain Control Register 3 000C3h Open Drain Control Register 4 000C4h Port PA Mode Control Register 00010001b 000C5h Port 1 Function Mapping Register 0 00h 000C8h Port 1 Function Mapping Register 1 00h 000C9h Port 3 Function Mapping Register 0 00h 000CCh Port 3 Function Mapping Register 1 00h 000CDh Port 4 Function Mapping Register 0 00h OOOCEh Port 4 Function Mapping Register 1 00h OOOCFh Port 1 Function Mapping Expansion Register 00h 000D1h Port 4 Function Mapping Expansion Register 00h 000D5h CO CO CO CO CO CO CO CO CO CO CO CO CO CO 0 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 141 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 2 Reading of Port Input Level Regardless of the mapping settings for port functions whether to read the port latch or the pin level can be selected when reading the Pi register i 1 3 4 or A 12 2 1 Port I O Function Control Register PINSR Address 000B9h Bit b7 b6 b5 b4 b3 b2 b1 bO symbol TONSEL ose ll 0 0 0 0 0 0 0 After
177. 4 b3 b2 b1 b Symbol ADCAPT ADCAPO MDI Mbo cks2 CKST Geer After Reset 0 0 0 0 0 0 0 0 Bit Name Function A D conversion clock select 6261 bo bits 000 f8 00 1 f4 0 10 f2 011 f1 100 fAD Other than the above Do not set A D operating mode select b4 b3 bits 0 0 One shot mode 0 1 Repeat mode 1 0 Single sweep mode 1 1 Repeat sweep mode Reserved Set to 0 ADCAPO A D conversion trigger select 7 b6 ADCAP1 bits 00 A D conversion start by timer RC or external trigger is disabled 0 1 Do not set 1 0 A D conversion is started by conversion trigger from timer RC 1 1 A D conversion is started by external trigger ADTRG The ADMOD register must be written only when A D conversion is stopped Bits CKSO to CKS2 A D conversion clock select bits These bits are used to select the clock for A D conversion Bits ADCAPO to ADCAP1 A D conversion trigger select bits These bits are used to select or disable the trigger for starting A D conversion When using a software trigger set bits ADCAP1 to ADCAPO to a value other than 01b RO1UHO050EJ0200 Rev 2 00 RENESAS Page 303 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 2 3 A D Input Select Register ADINSEL Address 0009Dh Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol Desenes S S cho After Reset 0 0 0 0 0 0 0 0 Bit Name Function Channel select bit See T
178. 4 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt Figure 7 5 shows an Example of Voltage Monitor 1 Interrupt Operation Set the VW1C1 bit in the VWIC register to 1 digital filter disabled mode to use the voltage monitor 1 interrupt to clear stop mode Table 7 4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt Step When the Digital Filter is Used When the Digital Filter is Not Used Set bits VD1S1 to VD1S3 in the VD1LS register to select the detection voltage for voltage detection 1 Set the VC1E bit in the VCA2 register to 1 voltage detection 1 circuit enabled Wait for td E A Set bits VW1F0 to VW1F1 in the VW1C register to select the sampling clock for the digital filter Set the VW1C1 bit in the VW1C register to 0 digital Set the VW1C1 bit in the VW1C register to 1 digital filter enabled mode filter disabled mode Set the VCAC1 bit in the VCAC register and the VW1C7 bit in the VW1C register to select the timing for an interrupt request Set the VW1C2 bit in the VW1C register to 0 not detected Set the LOCODIS bit in the OCOCR register to 0 low speed on chip oscillator on Wait for 2 cycles of the digital filter sampling clock No wait time Set the VW1CO bit in the VW1C register to 1 voltage monitor 1 interrupt enabled Note 1 When the VW1CO bit in the VW1C register is 0 voltage monitor 1 interrupt disabled steps 4
179. 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 5 2 Flash Memory Control Register 0 FMRO Address 001AAh Bit b 7 b6 b5 b4 b3 b2 b1 bO Symbol RDYSTIE BSYAEIE CMDERIE CMDRST FMSTP FMR02 FMRO1 KE A 0 0 0 0 0 0 0 After Reset 0 Bit Name Function Reserved Set to 0 FMRO1 CPU rewrite mode select bit CPU rewrite mode disabled 1 4 CPU rewrite mode enabled FMRO2 EW1 mode select bit EWO mode 1 5 EW1 mode FMSTP_ Flash memory stop bit 2 Flash memory operates Flash memory is stopped No erase write sequence reset Erase write sequence reset CMDERIE Erase write error blank check Erase write error blank check error command error command sequence error sequence error interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled BSYAEIE Flash access error interrupt enable 0 Flash access error interrupt disabled bit 5 Flash access error interrupt enabled RDYSTIE Flash ready status interrupt enable 0 Flash ready status interrupt disabled bit 5 Flash ready status interrupt enabled CMDRST Erase write sequence reset bit 3 0 1 0 1 0 1 0 1 Notes 1 To set this bit to 1 first write O and then write 1 immediately Interrupts must be disabled between writing 0 and then writing 1 2 Only write to the FMSTP bit by a program transferred to the RAM The FMSTP bit is enabled when the FMRO1 bit is 1 CPU rewrite mod
180. 8 2012 ztENESAS Page 310 of 426 R8C M11A Group R8C M12A Group 17 3 4 Single Sweep Mode Figure 17 6 shows an Operation Example in Single Sweep Mode When Channels 0 and 1 are Selected In single sweep mode A D conversions of the analog inputs are performed for the specified two channels a single time as follows 1 2 3 4 When the ADST bit in the ADCONDO register is set to 1 A D conversion starts by software trigger timer RC trigger or external trigger input A D conversion is started from ANO when channel group 0 is selected and AN2 when channel group 1 is selected When channel group 2 is selected A D conversion is started from AN4 When A D conversion has completed on each channel the result is transferred to the corresponding ADi register i 0 or 1 When A D conversion has completed on all the selected channels the ADF bit in the ADICSR register is set to interrupt requested Writing 0 after reading the value sets the ADF bit to 0 no interrupt requested The ADST bit remains 1 A D conversion starts during A D conversion When A D conversion has completed on all the selected channels the ADST bit is automatically set to 0 A D conversion stops and the A D converter enters the standby state When the ADST bit is set to 0 during A D conversion A D conversion is stopped and the A D converter enters the standby state Set to 1 by SE a program A D conversion is performed ADST bit in A D
181. Address Space Table 3 3 Address SFR Information 3 1 Register Name After Reset UARTO Transmit Receive Mode Register 00h UARTO Bit Rate Register XXh UARTO Transmit Buffer Register XXh XXh UARTO Transmit Receive Control Register 0 00001000b UARTO Transmit Receive Control Register 1 00000010b UARTO Receive Buffer Register XXh XXh UARTO Interrupt Flag and Enable Register 00h A D Register 0 ADOL XXh ADOH 000000XXb 0009Bh A D Register 1 AD1L XXh AD1H 000000XXb 0009Ch A D Mode Register ADMOD 00h 0009Dh A D Input Select Register ADINSEL 00h 0009Eh A D Control Register 0 ADCONO 00h 0009Fh A D Interrupt Control Status Register ADICSR 00h O00A0h OO00A1h 000A2h 000A3h 000A4h 000A5h 000A6h 000A7h 000A8h 000A9h Port P1 Direction Register OOOAAh OOOABh Port P3 Direction Register 000ACh Port P4 Direction Register 000ADh Port PA Direction Register OOOAEh OOOAFh Port P1 Register 000B0h 000B1h Port P3 Register 000B2h Port P4 Register 000B3h Port PA Register 000B4h 000B5h Pull Up Control Register 1 000B6h 000B7h Pull Up Control Register 3 000B8h Pull Up Control
182. B Group specifications refer to the R8C M13B Group User s Manual Hardware Appendix Table 4 1 Specification Comparison between R8C M12A Group and R8C M13B Group Memory Function ROM R8C M12AGroup 2 KB 4 KB 8 KB R8C M13B Group 4 KB 8 KB 16 KB RAM 256 bytes 384 bytes 512 bytes 384 bytes 512 bytes 1K byte Clock generation circuit XCIN clock generation circuit Not available Available I O port Number of pins 32 Added ports P2_2 TRCIOD TRKI SSO SDA P2_1 TRCIOC TRKO SSCK SCL P2_0 TRCIOB TRKO INT1 P3_1 XIN TRBO PO_7 TRCIOC TRKO PO_6 TRCIOD PO_5 TRCIOB PO_4 TRCIOB TREO P0_3 TRCIOB CLK1 PO_2 TRCIOA TRCTRG RXD1 IrRXD PO_1 TRCIOA TRCTRG TXD1 IrTXD PO_0 TRCIOA TRCTRG Number of CMOS UO ports 29 Added ports Timer Timer RE2 Not available Available Timer RK Not available Available Serial interface UART1 Not available Available Clock synchronous serial interface IIC SSU Not available Available IrDA interface Not available Available A D converter Number of A D channels 6 channels 8 channels Added channels ANS AN6 Package R01UH0050EJ0200 Rev 2 00 May 18 2012 20 pin LSSOP 20 pin DIP ztENESAS 32 pin LQFP Page 422 of 426 R8C M11A Group R8C M12A Group Appendix 4 Comparison between R8C M12A Group and R8C M13B Group Appendix Tables 4 2 and 4 3 list the Reg
183. B register 0000h e Bits TOB TOC and TRCCNT TOD in TRCCR1 register value register are 1 initial output is high TROGRA register TRCGRB register TRCIOB Duty cycle 100 Output remains unchanged when compare matches in the period and duty cycle registers occur simultaneously TRCCNT register value TRCGRA register TRCGRB register 0000h Output remains unchanged when compare matches in the period and duty cycle registers Note 1 occur simultaneously TRCGRA register Q vi TRCCNT register value TRCGRB register 0000h U Li I H H 1 TRCIOB i Duty cycle 0 Duty cycle 100 Li Note 1 The TRCGRB register is rewritten Figure 15 11 Operation Example in PWM Mode Duty Cycle 0 Duty Cycle 100 R01UH0050EJ0200 Rev 2 00 ztENESAS Page 254 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 3 3 PWM2 Mode Unlike PWM mode in PWM2 mode a waveform is output from the TRCIOB pin at a compare match with registers TRCGRB and TRCGRC When the BUFEB bit in the TRCMR register is set to 1 TRCGRD register is used as a buffer register for TRCGRB register the TRCGRD register functions as a buffer register for the TRCGRB register The output level is determined by the TOB bit in the TRCCR1 register When the TOB bit is 0 output value 0 a low level is output at a compare match with the TRCGRB register and a high level is output at a compare match with the TRCGRC register When the TOB bit is 1 ou
184. C d i D me o lt A 5 C D L O CENESAS R8C M1 1 A Group R8C M1 OA Group User s Manual Hardware RENESAS MCU R8C Family R8C Mx Series All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics www renesas com Rev 2 00 May 2012 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein
185. C M11A Group R8C M12A Group 13 Timer RJ2 13 3 6 Timer RJ Interrupt Control Register TRJIR Address 000DEh Bit b 7 b6 b5 b4 b3 b2 b1 b0 Symbol TRIE ARE Sf aa 0 0 0 0 0 D 0 After Reset 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Timer RJ interrupt request flag 0 No interrupt requested 1 Interrupt requested Timer RJ interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled TRUJIF Bit Timer RJ interrupt request flag Condition for setting to 0 e When 0 is written to this bit after reading it as 1 Conditions for setting to 1 e When timer RJ2 underflows e When the measurement of the active width of the external input TRJIO is completed in pulse width measurement mode e When the set edge of the external input TRJIO is input in pulse period measurement mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 185 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 Operation 13 4 1 Reload Register and Counter Rewrite Operation Regardless of the operating mode the timing of the rewrite operation to the reload register and the counter differs depending on the value in the TSTART bit in the TRJCR register When the TSTART bit is 0 count is stopped the count value is directly written to the reload register and then to the counter in synchronization with the system clock f When the TSTART bit is 1 c
186. CGRD register gt 0000h D H 1 D 1 1 TRCIOA 1 i 1 i TRCIOB Figure 15 22 Operation Example When TRCIOA and TRCIOB Output is not Overlapped 1 1 1 1 1 1 H 1 H i 1 H RO1UH0050EJ0200 Rev 2 00 RENESAS Page 265 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 4 4 Waveform Output Manipulation Function By setting the TRCOPR register the waveform output for timer RC can be controlled by the INTI pin input or comparator B1 output When the OPE bit in the TRCOPR register is 0 the waveform output manipulation function is disabled The TRCIOA TRCIOB TRCIOC and TRCIOD output from timer RC is output by setting registers TRCIORO TRCIORI and TRCOER When the PTO bit in the TRCOER register is 1 pulse output forced cutoff signal input INTO pin enabled if a low level is input to the INTO pin bits EA EB EC and ED in the TRCOER register are set to all 1 timer RC output disabled and output pins TRCIOA to TRCIOD become high impedance When the OPE bit in the TRCOPR register is 1 the waveform output manipulation function is enabled If a waveform output manipulation event is input bits EA to ED in the TRCOER register are set to 1 Bits OPOLO to OPOL in the TRCOPR register enable the output level of the timer RC pin to be fixed at low high or to high impedance during the waveform output manipulation period After the waveform output manipulation event is cancelled the waveform output manip
187. CPU clock or low speed on chip oscillator Low speed on chip oscillator clock clock 1 16 Count operation Decrement Count start condition Either of the following can be selected e The count is automatically started after a reset e The count is started by writing to the WDTS register Count stop conditions When wait mode or stop mode is entered None while the count source is the CPU clock Watchdog timer initialization conditions e Reset e 00h and then FFh are written to the WDTR register during the refresh acceptance period when a refresh acceptance period is set e Underflow Operation at underflow Watchdog timer interrupt or watchdog timer Watchdog timer reset reset Selectable functions Selection of the count source Selected by bits WDTC6 to WDTC7 in the WDTC register Count source protection mode Whether count source protection mode is enabled or disabled after a reset can be selected by the CSPROINI bit in the OFS register If count source protection mode is disabled whether count source protection mode is enabled or disabled is selected by the CSPRO bit in the CSPR register e Start or stop of the watchdog timer after a reset Selected by the WDTON bit in the OFS register e Initial value of the watchdog timer underflow period Selected by bits WOTUFSO to WDTUFS1 in the OFS2 register e Refresh acceptance period for the watchdog timer Selected by bits WOTRCSO to WDTRCS1 i
188. Detect Register 2 VCA2 Address 0005Ah Bit b7 b6 b5 b4 b3 b2 b1 bO sma vee ve E After Reset 0 0 1 0 0 1 0 0 The above applies when the LVDAS bit in the OFS register is 0 After Reset 0 0 0 0 0 1 0 0 The above applies when the LVDAS bit in the OFS register is 1 Bit Name Function Internal low power consumption enable 0 Low power consumption wait mode disabled bit 1 1 Low power consumption wait mode enabled Reserved Set to 0 Reserved Set to 1 Reserved Set to 0 Voltage detection 0 enable bit 2 0 Voltage detection 0 circuit disabled 1 Voltage detection 0 circuit enabled Voltage detection 1 enable bit 3 0 Voltage detection 1 circuit disabled 1 Voltage detection 1 circuit enabled Reserved Set to 0 Notes 1 Use the LPE bit only when entering wait mode To set the LPE bit see Figure 10 5 Procedure for Reducing Internal Power Consumption by Using LPE Bit When the LPE bit is 1 low power consumption wait mode do not set the STPM bit in the CKSTPR register to 1 all clocks are stopped stop mode 2 When voltage monitor 0 reset is used set the VCOE bit to 1 voltage detection 0 circuit enabled Set the VCOE bit from 0 to 1 and wait for td E A After that the voltage detection 0 circuit operates For details on td E A see 20 Electrical Characteristics 3 When a voltage detection 1 interrupt or the VW1C3 bit in the VW1C register is used set the VC1E bit to 1 voltage
189. EN Comparator B3 interrupt enable 0 Interrupt disabled signal bit 1 Interrupt enabled WCB3F Comparator B3 interrupt request flag 0 No interrupt requested 1 Interrupt requested WCBS3F Bit Comparator B3 interrupt request flag Condition for setting to 0 e When 0 is written to this bit Condition for setting to 1 e When an interrupt request is generated RO1UHO050EJ0200 Rev 2 00 RENESAS Page 320 of 426 May 18 2012 R8C M11A Group R8C M12A Group 18 Comparator B 18 3 Operation Comparator B1 and comparator B3 compare an input voltage from the reference voltage input pin IVREFi and an input voltage from the analog input voltage pin IVCMP i 1 or 3 18 3 1 Comparator Bi Digital Filter i 1 or 3 In comparator Bi the digital filter can be used The sampling clock can be selected by bits WCBiF0 to WCBiF 1 in the WCBiINTR register The WCBiOUT signal output from comparator Bi is sampled on every sampling clock When the level matches three successive times the WCBiF bit in the WCBiINTR register is set to 1 interrupt requested Figure 18 2 shows an Example of Comparator Bi Digital Filter Operation WCBIOUT signal Sampling timing WCBIF bit in WCBIINTR register Set to 0 by a program i 1or3 Note 1 This example applies when bits WCBiF1 to WCBiFO in the WCBIINTR register are 01b 10b or 11b filter used Figure 18 2 Example of Comparator Bi Digital Filter
190. ENESAS Page 8 of 426 May 18 2012 R8C M11A Group R8C M12A Group 1 Overview Table 1 6 Pin Name Information by Pin Number Pin Number I O Pins for Peripheral Functions R8C M11A R8C M12A Control Pin Serial A D Converter Group Group Interrupt Timer Interface Comparator B TRBO TRJO TRCIOD RESET XOUT VSS AVSS XIN E RXD0 TXDO VCOUT1 VCC AVCC MODE TRCIOD VCOUT3 TRCIOC IVREF3 TRCCLK IVCMP3 ADTRG TRJIO TRCCLK AN7 IVCMP1 TRJO TRCIOB CLKO IVREF 1 TRJIO RXDO VCOUT1 TRCIOB RXDO TXDO AN4 TRBO TRCIOC AN3 TRCIOB AN2 TRCIOA TRCTRG AN1 TRCIOD ANO RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 9 of 426 May 18 2012 R8C M11A Group R8C M12A Group 1 5 Pin Functions Table 1 7 lists the Pin Functions Table 1 7 Power supply input Pin Functions Pin Name VCC VSS 1 Overview Description Apply 1 8 V through 5 5 V to the VCC pin Apply 0 V to the VSS pin Analog power supply input AVCC AVSS Power supply input for the A D converter Connect a capacitor between pins AVCC and AVSS Reset input RESET Applying a low level to this pin resets the MCU MODE MODE Connect this pin to the VCC pin via a resistor XIN clock input XIN XIN clock output XOUT I O for the XIN clock generation circuit Connect a ceramic resonator or a crystal oscillator between pins XIN and XOUT 1 To
191. F bit at that time To set to 0 by a program use the MOV instruction to write 0 to the TUNDF bit in TRJCR register and write 1 to the TEDGF bit at that time Figure 13 7 Operation Example in Pulse Period Measurement Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 191 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 7 Output Settings for Each Mode Table 13 7 TRJIO Pin Setting TRJIOC Register TRJIO Pin I O Operating Mode Timer mode TOPCR Bit TEDGSEL Bit Input Pulse output mode Output disabled 1 Output is started at low Output is started at high Event counter mode Pulse width measurement mode Pulse period measurement mode Note 1 The port selected as the TRJIO function becomes high impedance Table 13 8 TRJO Pin Setting TRJIOC Register Operating Mode All modes TEDGSEL Bit 1 Input TRJO Pin Output Output is started at high 0 Output is started at low RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 192 of 426 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 5 Notes on Timer RJ2 1 Timer RJ2 stops counting after a reset Start the count only after setting the value in the timer 2 After 1 count is started is written to the TSTART bit in the TRJCR register while the count is stopped the TCSTF bit in the TRJCR register remains 0 count is stopped for two to three cycles o
192. F6h 001F7h 001F8h 001F9h 001FAh 001FBh 001FCh 001FDh 001FEh 001FFh Note 1 The blank areas are reserved No access is allowed R01UH0050EJ0200 Rev 2 00 stENESAS May 18 2012 Page 22 of 426 R8C M11A Group R8C M12A Group 3 Address Space Table 3 9 ID Code Area and Option Function Select Area OFFDEA Option Function Select Register 2 OFS2 Note 1 OFEDFR D1 Note 2 OFFESH D2 Note 2 l OFFER 103 Note 2 l OFFEFH TE Note 2 l JFFF TR Note 2 l FFF DS Note 2 l OFEFER M07 Note 2 Notes 1 The option function select area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the option function select area Erasure of the block including the option function select area causes the option function select area to be set to FFh When blank products are shipped the option function select area is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the option function select area is the value programmed by the user 2 The ID code area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the ID code area Erasure of the block including the ID code
193. FSET I Interrupt enabled BSET 0 CKSTPR Stop mode JMP B LABEL_001 LABEL_001 NOP NOP NOP NOP RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 108 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 Interrupts 11 1 Overview Interrupts are classified into non maskable and maskable interrupts These differ in whether or not the interrupt can be enabled or disabled by an interrupt enable flag I flag and in whether or not the interrupt priority level can be changed as listed in Table 11 1 Table 11 1 Maskable Non Maskable Interrupts Disabling Interrupt by Interrupt Changing Priority by Setting Interrupt Enable Flag I Flag Priority Level Non maskable interrupts Not possible Not possible Maskable interrupts Possible Possible Figure 11 1 shows the Types of Interrupts Table 11 2 lists the Descriptions of Interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction r Software non maskable interrupts Interrupts lt Watchdog timer Oscillation stop detection Special W _ Voltage monitor 1 non maskable interrupts Single step Address match 3 Hardware Peripheral function maskable interrupts Notes 1 Peripheral function interrupts are generated by the peripheral functions in the MCU 2 Do not use this interrupt It is provided exclusively for use in development tools 3 Do not use an address match interrupt w
194. Function P1_6 Transfer clock input and output P1_4 P1_5 P4_6 Serial data input P1_4 P4_2 P4 6 Serial data output RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 279 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 2 Registers Table 16 3 lists the UARTO Register Configuration Table 16 3 UARTO Register Configuration Register Name After Reset Address Access Size UARTO Transmit Receive Mode Register 00080h UARTO Bit Rate Register 00081h UARTO Transmit Buffer Register 00082h 00083h UARTO Transmit Receive Control Register 0 00001000b 00084h UARTO Transmit Receive Control Register 1 00000010b 00085h UARTO Receive Buffer Register XXh 00086h XXh 00087h UARTO Interrupt Flag and Enable Register 00h 00088h X Undefined Note 1 For details on access see the description of the individual registers 16 2 1 UARTO Transmit Receive Mode Register UOMR Address 00080h Bit b7 b6 b5 b4 b3 b2 b1 b gent PRYE J PRY STPS eet SDT ee After Reset 0 Bit Name Function i its 1 2 b2 b1 bO Serial VO mode select bits 0 0 0 Serial interface disabled 0 0 1 Clock synchronous serial I O mode 1 00 UART mode transfer data 7 bits long 101 UART mode transfer data 8 bits long 1 10 UART mode transfer data 9 bits long Other than the above Do not set Internal external clock select bit 0 Internal clock External clock Stop bit lengt
195. Function Clocks Table 9 2 lists the Clock Generation Circuit Pin Configuration Table 9 1 Clock frequency XIN Clock Oscillation Circuit 0 MHz to 20 MHz 2 MHz to 20 MHz when an oscillator is used Clock Generation Circuit Specifications High Speed On Chip Oscillator Approx 20 MHz Low Speed On Chip Oscillator Approx 125 kHz Connectable oscillator Ceramic resonator e Crystal oscillator Oscillator connect pins XIN XOUT 1 Oscillation start and stop Usable Usable Usable State after reset Stopped Stopped Oscillates Others Note e An externally generated clock can be input A feed back resistor is included connected or not connected can be selected The system clock can be output from P4_7 The system clock can be output from P4_7 1 When the on chip oscillator clock instead of the XIN clock oscillation circuit is used as the CPU clock these pins can be used as P4_6 and P4_7 RO1UHOO50EJ0200 Rev 2 00 May 18 2012 stENESAS Page 72 of 426 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit Registers FRV1 and FRV2 PHISELO to PHISEL7 PHISSELO to PHISSEL2 Frequency adjustable High speed on chip SS HSCKSEL 1 System clock oscillator i division circuit fs fe division by 1 cpu OE speed to 32 clock clock SCKSEL 1 selection System XIN clock circuit High base oscillation HSCKSEL 0 speed clock fs for
196. Function UO Tables 12 21 to 12 24 list the pin settings for peripheral function I O Table 12 21 Register TRCOER TRCIOA Pin Settings TRCIORO TRCCR2 Bit Setting value X 0 or 1 IOA2 IOA1 IOAO TCEG1 TCEGO Function Timer mode waveform output output compare function Timer mode input capture function Table 12 22 TRCIOB Pin Settings Register TRCOER TRCIORO Bit Setting value X 0 or 1 IOB1 PWM2 mode TRCTRG input Function PWM2 mode waveform output PWM mode waveform output Timer mode waveform output output compare function Table 12 23 TRCIOC Pin Settings Register TRCOER TRCIOR1 Bit Setting value X 0 or 1 IOC Timer mode input capture function Function PWM mode waveform output Timer mode waveform output output compare function Table 12 24 TRCIOD Pin Settings Register TRCOER TRCIOR1 Bit Setting value X 0 or 1 1OD1 Timer mode input capture function Function PWM mode waveform output Timer mode waveform output output compare function Timer mode input capture function RO1UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 166 of 426 R8C M11A Group R8C M12A Group 12 I O Ports 12 9 Handling of Unused Pins Table 12 25 lists
197. INTSFO INT3F1 Reserved bits Set to 0 ISCRO 0003Ch INT3SA INT3SB Reserved bits Set to 0 ILVLD 0004Dh ILVLDO ILVLD1 Reserved bits Set to 0 IRR3 00053h IRI3 Reserved bit Set to 0 KIO KIEN 0003Eh KIOEN KIOPL Reserved bits Set to 0 Comparator B3 interrupt ILVL2 00042h ILVL24 ILVL25 Reserved bits Set to 0 IRR2 00052h IRCMP3 Reserved bit Set to 0 P1_0 PD1 000A9h PD1_0 Reserved bit Set to 0 P1 OOOAFh P1_0 Reserved bit Set to 0 PUR1 000B5h PU1_0 Reserved bit Set to 0 POD1 000C1h POD1_0 Reserved bit Set to 0 PML1 000C8h P10SELO P10SEL1 Reserved bits Set to 0 PD3 OOOABh PD3_3 PD3_4 PD3_5 Reserved bits Set to 0 P3 000B1h P3_3 P3_4 P3_5 Reserved bits Set to 0 PUR3 000B7h PU3_3 PU3_4 PU3_5 Reserved bits Set to 0 DRR3 000BDh DRR3_3 DRR3_4 DRR3_5 Reserved bits Set to 0 POD3 000C3h POD3_3 POD3_4 POD3_5 Reserved bits Set to 0 PML3 000CCh P33SELO0 P33SEL1 Reserved bits Set to 0 PMH3 000CDh P34SELO P34SEL1 P35SELO0 P35SEL1 Reserved bits Set to 0 P4 2 P4 5 PD4 000ACh PD4_2 PD4_5 Reserved bits Set to 0 P4 000B2h P4_2 P4_5 Reserved bits Set to 0 PUR4 000B8h PU4_2 PU4_5 Reserved
198. IOC register is output Update conditions for pin states e When the TSTART bit in the TRBCR register is changed from 0 count is stopped to 1 count is started e When the TRBPR register is reloaded to the counter RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 225 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 6 Interrupt Request When the TRBIF bit in the TRBIR register is 1 interrupt requested and the TRBIE bit is 1 interrupt enabled an interrupt request is generated to the CPU The conditions for setting the TRBIF bit to 1 differ depending on the mode See the descriptions of the TRBIF bit and individual modes 14 7 INTO Input Trigger Selection In programmable one shot and programmable wait one shot generation modes when 1 one shot count is started is written to the TOSST bit in the TRBCR register or a trigger is input to the INTO pin with the TCSTF bit in the TRBCR register set to 1 count is in progress one shot operation is started When using the trigger input from the INTO pin make the following settings beforehand 1 Set the port mapping register to set port P1_4 or P4_5 as the INTO pin 2 Set bits INTOFO to INTOF1 in the INTFO register to select the digital filter sampling clock for the INTO pin 3 Set the INTOEN bit in the INTEN register to 1 enabled to enable an interrupt 4 Set the INOSEG bit in the TRBIOC register to select the falling or rising edge 5 Set the INOSTG bit i
199. IOj1 j A B C or D in registers TRCIOO and TRCIOR1 However all of bits IOA2 and IOB2 in the TRCIORO register and bits IOC2 and IOD2 in the TRCIOR1 register must be set to 1 input capture function 2 Includes when bits BUFEA and BUFEB in the TRCMR register are 1 buffer registers for TRCGRA and TRCGRB RO1UHO050EJ0200 Rev 2 00 RENESAS Page 238 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 7 Timer RC I O Control Register 0 TRCIORO Address OOOF6h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol is eee IOB2 IOB1 IOBO KL ze IOA2 IOA1 IOAO After Reset 1 0 0 0 1 0 0 0 Bit Name Function TRCGRA control AO bit IOA2 0 output compare function P b1 b TRCGRA control i 0 0 Pin output by compare match A is disabled 0 1 Low level output from TRCIOA pin at compare match A 1 0 High level output from TRCIOA pin at compare match A 1 1 Toggle output from TRCIOA pin at compare match A IOA2 1 input capture function b1 b0 0 0 Rising edge on TRCIOA pin 0 1 Falling edge on TRCIOA pin 1 0 Two way edge on TRCIOA pin 1 1 Do not set TRCGRA control A2 bit 1 0 Output compare function 1 Input capture function Reserved Set to 1 TRCGRB control BO bit IOB2 0 output compare function H b5 b4 TRCGRB control B1 bit 0 0 Pin output by compare match B is disabled 0 1 Low level output from TRCIOB pin at compare match B 1 0 High level output from TRCIOB pin at compare match B 1 1 Tog
200. Interrupt Routine Execution after WAIT instruction is Executed When a peripheral function interrupt is used to return from wait mode the following items must be set before executing the WAIT instruction 1 Set the interrupt priority level in bits ILVLi0 to ILVLi1 or bits ILVLi4 to ILVLi5 in the interrupt priority level registers for the peripheral function interrupts that are used to return from wait mode Also set 00b level 0 interrupt disabled in bits ILVLil to ILVLi0 or bits ILVLi5 to ILVLi4 for the peripheral function interrupts that are not to be used to return from wait mode 2 3 Set the I flag to 1 maskable interrupts enabled Operate the peripheral functions to be used to return from wait mode RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 98 of 426 R8C M11A Group R8C M12A Group 10 Power Control The system base clock when returning from wait mode by a peripheral interrupt is the clock set by the WAITRS bit in the CKRSCR register At this time bits PHISSELO to PHISSEL 2 in the SCKCR register and the SCKSEL bit in the CKSTPR register are automatically changed according to bits PHISRS and WAITRS If the system base clock when returning is different from the clock used immediately before entering wait mode a period until the clock supply oscillation stabilization time is generated automatically If the system base clock when returning is the high speed on chip oscillator clock oscillation
201. M An e MOV B IMM abs16 e MOV B RnH An e MOV B RnH abs16 e MOV B RnL An e MOV B RnL abs16 Use one of the following instructions to read the same address as the second command write address e MOV B An RnL e MOV B An RnH e MOV W An Rn Confirm the suspend status using the FST3 bit for the program command and the FST6 bit for the block erase command Figure 21 10 Procedure for Software Command Execution When Suspend is Enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 411 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 12 3 Notes on Flash Memory Stop and Operation Transition 1 Do not enter stop mode while the FMSTP bit is 1 the flash memory is stopped 2 Do not enter wait mode while the FMSTP bit is 1 the flash memory is stopped and the WTFMSTP bit is 1 the flash memory is stopped in wait mode 3 Do not enter flash memory stop state for 42 us after entering from flash memory stop state to flash memory operation state And do not rewrite the LOCODIS bit in the OCOCR register for 42 ps Conditions when entering flash memory operation state from flash memory stop state e Set the FMSTP bit to 0 the flash memory operates e Return from wait mode while the WTFMSTP bit is 1 the flash memory is stopped in wait mode e Return from stop mode Conditions when entering flash memory stop state from flash memory operation state e Set the FMSTP bit to 1 the flash memory is stopped e En
202. N7 IVCMP1 INT1 TRJIO TRCCLK Figure 12 1 Port 1 Pin Configuration RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 143 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 1 Port P1 Direction Register PD1 Address 000A9h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol After Reset 0 0 0 0 0 0 0 0 Bit Name Function Port P1_0 direction bit 0 Input mode functions as an input port Port P1_1 direction bit 1 Output mode functions as an output port Port P1_2 direction bit Port P1_3 direction bit Port P1_4 direction bit Port P1_5 direction bit Port P1_6 direction bit Port P1_7 direction bit The PD1 register is used to select whether I O ports are used as input or output Each bit in the PD1 register corresponds to individual ports 12 3 2 Port P1 Register P1 Address 000AFh Bit b7 b6 b5 b4 b3 b2 b1 b Symbol After Reset 0 Bit Name Function Port P1_0 bit 0 Low level Port P1_1 bit 1 High level Port P1_2 bit Port P1_3 bit Port P1_4 bit Port P1_5 bit Port P1_6 bit Port P1_7 bit The P1 register is an I O port data register Data input to and output from external devices are accomplished by reading from and writing to the P1 register The P1 register consists of a port latch to retain output data and a circuit to read the pin states The value written to the port latch is output from the pins Each bit in the P1 register corresponds
203. O in the EXCKCR register are set to 11b When the oscillation circuit is not used bits CKPT1 to CKPTO in the EXCKCR register are set to any value other than 11b RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 368 of 426 May 18 2012 R8C M11A Group R8C M12A Group Table 20 2 Vcc AVcc Parameter Power supply voltage Recommended Operating Conditions Condition 20 Electrical Characteristics Standard Min 1 8 Max lt Vss AVss Power supply voltage VIH Input high voltage Other than CMOS input 0 8 Vcc CMOS input 4 0 V lt Vcc lt 5 5 V 0 65 Vcc 2 7 V lt Vcc lt 4 0 V 0 7 Vcc 1 8 V lt Vcc lt 2 7 V 0 8 Vcc Input low voltage Other than CMOS input CMOS input 4 0 V lt Vece lt 5 5 V 2 7 V lt Vcc lt 4 0 V 1 8 V lt Vcc lt 2 7 V lt lt lt lt lt lt lt lt lt IOH sum Peak sum output high current Sum of all pins loH peak 3 gt IOH sum Average sum output high current Sum of all pins loH avg IOH peak Peak output high current When drive capacity is low When drive capacity is high 5 When drive capacity is low IOH avg Average output high current When drive capacity is high 5 Peak sum output low current Average sum output low current Peak output low current L sum Sum of all pins loL peak L sum Sum of all pins loL avg L pe
204. O mode disabled function Table 19 3 lists the ID Code Reserved Words When the combination of ID codes and addresses match those listed in Table 19 3 respectively the ID codes forms the reserved word When the forced erase function or standard serial I O mode disabled function is not used use another combination of ID codes Table 19 3 ID Code Reserved Words Reserved Word of ID Code ASCII 1 ALeRASE Protect forced erase function standard serial UO mode disabled function 41h A upper case P upper case 4Ch L upper case r lower case 65h e lower case 0 lower case 52h R upper case t lower case 4th A upper case e lower case ID Code Storage Address 53h S upper case c lower case 45h E upper case t lower case Note 1 When the combination of ID codes and addresses match those listed in Table 19 3 respectively the set of characters forms the corresponding reserved word R01UH0050EJ0200 Rev 2 00 zeENESAS Page 327 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 3 2 1 Forced Erase Function This function is used in standard serial I O mode When the sent ID codes are ALeRASE in ASCII and the stored ID codes are the same the entire data in the user ROM area will be erased forced erase Even if the stored ID codes are other than ALeRASE see Table 19 3 ID Code Reserved Words the entire data in
205. OIR register Set to 0 by a program The above diagram applies for the following settings TC 16 n 1 fj or 16 n 1 EXT e STPS bit in UOMR register 0 one stop bit fj Frequency of UOBRG count source f1 f8 or 32 PRYE bit in UOMR register 1 parity enabled fEXT Frequency of UOBRG count source external clock e UOIRS bit in UOC1 register 1 transmission is completed n Value set in UOBRG register When transfer data is 9 bits long parity disabled two stop bits TC gt a Transfer clock f TE bit in I U0C1 register i Data is set in UOTB register TI bit in fy i U0C1 register gt From UOTB register to UARTO transmit register 1 Start Stop bit bit roo Aen SII A PEFFER le 9 I 1 TXEPT bit in UOCO register UOTIF bit in UOIR register 3 1 Set to 0 by a program The above diagram applies for the following settings TC 16 n 1 fj or 16 n 1 EXT STPS bit in UOMR register 1 two stop bits fj Frequency of UOBRG count source f1 f8 or f32 e PRYE bit in UOMR register 0 parity disabled fEXT Frequency of UOBRG count source external clock e UOIRS bit in UOC1 register 0 transmit buffer is empty n Value set in UOBRG register Figure 16 6 Transmit Timing in Clock Asynchronous Serial UO Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 293 of 426 May 18 2012 R8C M11A Group R8C M12A Group e When transfer data is 8 bits long parity disable
206. PMHi i 1 3 or 4 ISCRO INTEN and KIEN and Setting Interrupt Request Flag to 0 Note 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INT3 or KIO to KI3 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT3 are used When all maskable interrupts can be disabled use the flag When all maskable interrupts cannot be disabled use the Interrupt disabled t corresponding bits ILVLjO to ILVLj1 or bits ILVLj4 to ILVLj5 j 6 A C D or E for the interrupt whose source to be changed Rewrite registers PMLi PMHi ISCRO INTEN and KIEN F ar After manipulating the registers wait for a certain period Wait for a certain period lt lt to set the interrupt request flag to 0 Set the interrupt request flag to 0 Interrupt enabled lt _ The interrupt is enabled Notes 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INTS or KIO to KD are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT3 are used 2 See 11 9 7 Changing Interrupt Priority Levels and Flag Registers for the instructions to use and related notes Figure 21 1 Procedure for Manipulating Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN and Setting Interrupt Request Flag to 0 RO1UHO050Ev0200 R
207. PR register WCB1F0 to WCB1F1 WCB1INTEN Bits in WCB1INTR register WCB3F0 to WCB3F1 WCBSINTEN Bits in WCB3INTR register Figure 18 1 Comparator B Block Diagram Table 18 2 Comparator B Pin Configuration Pin Name IVCMP1 Assigned Pin P1_7 Function Analog voltage input for comparator B1 IVREF1 P16 Reference voltage input for comparator B1 VCOUT1 DI 5o0rP4 6 Comparison result output for comparator B1 IVCMP3 P3_3 Analog voltage input for comparator B3 IVREF3 P3_4 Reference voltage input for comparator B3 VCOUT3 Note P3_5 Comparison result output for comparator B3 1 When port P1_5 or port P4_6 is set as the VCOUT1 pin while operation of comparator B1 is disabled WCB1MO0O 0 the initial level of the pin is set to low When port P3_5 is set as the VCOUT3 pin while operation of comparator B3 is disabled WCB3M0 0 the initial level of the pin is set to low RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 317 of 426 R8C M11A Group R8C M12A Group 18 Comparator B 18 2 Registers Table 18 3 lists the Comparator B Register Configuration Table 18 3 Comparator B Register Configuration Register Name Comparator B Control Register After Reset Address WCMPR 00180h Access Size Comparator B1 Interrupt Control Register WCBI1INTR 00181h Comparator B3 Interrupt Control Register 18 2 1 Address 00180h Bit b After
208. R8C M11A Group R8C M12A Group 11 2 Registers Table 11 3 lists the Register Configuration for Interrupts Table 11 3 External Input Enable Register Register Configuration for Interrupts Register Name INTEN After Reset Address 00038h 11 Interrupts Access Size CO INT Input Filter Select Register 0 INTFO 0003Ah INT Input Edge Select Register 0 ISCRO 0003Ch Key Input Enable Register KIEN 0003Eh Interrupt Priority Level Register 0 ILVLO 00040h Interrupt Priority Level Register 2 ILVL2 00042h Interrupt Priority Level Register 3 ILVL3 00043h Interrupt Priority Level Register 4 ILVL4 00044h Interrupt Priority Level Register 5 ILVL5 00045h Interrupt Priority Level Register 6 ILVL6 00046h Interrupt Priority Level Register 7 ILVL7 00047h Interrupt Priority Level Register 8 ILVL8 00048h Interrupt Priority Level Register 9 ILVL9 00049h Interrupt Priority Level Register A ILVLA 0004Ah Interrupt Priority Level Register B ILVLB 0004Bh Interrupt Priority Level Register C ILVLC 0004Ch Interrupt Priority Level Register D ILVLD 0004Dh Interrupt Priority Level Register E ILVLE 0004Eh Interrupt Monitor Flag Register 0 IRRO 00050h Interrupt Monitor Flag Register 1 IRR1 00051h Interrupt Monitor Flag Register 2 IRR2 00052h
209. RB Mode Register TRBMR 00h 000E4h Timer RB Prescaler Register 2 TRBPRE FFh Timer RB Primary Secondary Register Lower 8 Bits 3 000E5h Timer RB Primary Register 2 TRBPR FFh Timer RB Primary Register Higher 8 Bits 3 000E6h Timer RB Secondary Register 2 TRBSC FFh Timer RB Secondary Register Higher 8 Bits 3 000E7h Timer RB Interrupt Control Register TRBIR 00h OOOE8h Timer RC Counter TROCNT 00h 00h Timer RC General Register A TRCGRA FFh FFh Timer RC General Register B TRCGRB FFh FFh Timer RC General Register C TRCGRC FFh FFh Timer RC General Register D TRCGRD FFh FFh Timer RC Mode Register TRCMR 01001000b Timer RC Control Register 1 TRCCR1 00h Timer RC Interrupt Enable Register TRCIER 01110000b Timer RC Status Register TRCSR 01110000b Timer RC I O Control Register 0 TRCIORO 10001000b Timer RC UO Control Register 1 TRCIOR1 10001000b Timer RC Control Register 2 TRCCR2 00011000b Timer RC Digital Filter Function Select Register TRCDF 00h Timer RC Output Enable Register TRCOER 01111111b Timer RC A D Conversion Trigger Control Register TRCADCR 11110000b Timer RC Waveform Output Manipulation Register TRCOPR 00h Notes 1 The blank areas are reserved No access is allowed 2 The TCNT16 bit in the TRBMR register is 0 3 The TCNT16 bit in the TRBMR register is 1 RO1UHO050EJ0200 Rev 2 00
210. RCOPR register Figure 15 1 Timer RC Block Diagram Table 15 3 Timer RC Pin Configuration Pin Name Function TRCCLK External clock input TRCIOA TRCTRG TRCGRA output compare output TRCGRA input capture input external trigger input TRCTRG TRCIOB TRCGRB output compare output TRCGRB input capture input PWM output in PWM mode TRCIOC TRCGRC output compare output TRCGRC input capture input PWM output in PWM mode TRCIOD TRCGRD output compare output TRCGRD input capture input PWM output in PWM mode INTO Timer output disabling control input INT1 Waveform output manipulation event input RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 231 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 Registers Table 15 4 lists the Timer RC Register Configuration Table 15 4 Timer RC Register Configuration Register Name After Reset Address Access Size Timer RC Counter TRCCNT 00h OOOE8h 00h 000E9h Timer RC General Register A TRCGRA FFh OOOEAh FFh OOOEBh Timer RC General Register B TRCGRB FFh OOOECh FFh OOOEDh Timer RC General Register C TRCGRC FFh OOOEEh FFh OOOEFh Timer RC General Register D TRCGRD FFh OOOFOh FFh OOOF 1h Timer RC Mode Register TRCMR 01001000b 000F2h Timer RC Control Register 1 TRCCR1 00h 000F3h Timer RC Interrupt Enable Register TRCIER 01110000b 000F4h Timer RC Status Register TRCSR 01110000b 000F5h Timer RC I O Control Register 0 TRCIORO 10001000b OOOF6h Timer RC I O C
211. RJMR 3 In event counter mode set the TSTART bit in the TRJCR register to 1 count is started and then input an external pulse 4 In pulse width pulse period measurement modes bits TEDGF and TUNDF in the TRJCR register used are set to 0 by writing 0 by a program but remain unchanged even if 1 is written to these bits If a read modify write instruction is used to set the TRJCR register bits TEDGF and TUNDF may be erroneously set to 0 depending on the timing even when the TEDGF bit is set to 1 active edge received and the TUNDF bit is set to 1 underflow during execution of the instruction In this case write 1 using the MOV instruction to the TEDGF or TUNDF bit which is not supposed to be set to 0 5 Insert NOP instructions between writing to and reading from registers associated with the TRJ counter while the counter is stopped 6 When the TSTART bit in the TRJCR register is 1 count is started or the TCSTF bit is 1 count is in progress allow at least three cycles of the count source clock for each write interval when writing to the TRJ register successively 7 Note the following when writing 0 to the TEDGF bit in the TRJCR register in pulse width measurement mode or pulse period measurement mode Set the TRJIF bit in the TRJIR register to 0 before setting the TEDGF bit to 0 When reading the TEDGF bit immediately after setting it to 0 it is read as 0 However the internal signal of the TEDGF bit remains 1 for one to two cycle
212. Register 4 000B9h Port I O Function Control Register OOOBAh OOOBBh Drive Capacity Control Register 1 000BCh 000BDh Drive Capacity Control Register 3 OOOBEh OOOBFh X Undefined Note 1 The blank areas are reserved No access is allowed RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 17 of 426 R8C M11A Group R8C M12A Group 3 Address Space Table 3 4 SFR Information 4 1 Address Register Name After Reset Open Drain Control Register 1 00h Open Drain Control Register 3 00h Open Drain Control Register 4 00h Port PA Mode Control Register 00010001b Port 1 Function Mapping Register 0 Port 1 Function Mapping Register 1 Port 3 Function Mapping Register 0 Port 3 Function Mapping Register 1 Port 4 Function Mapping Register 0 Port 4 Function Mapping Register 1 Port 1 Function Mapping Expansion Register Port 4 Function Mapping Expansion Register Timer RJ Counter Register TRJ FFh 000D9h EEN 000DAh Timer RJ Control Register TRJCR 00h 000DBh Timer RJ I O Control Register TRJIOC 00h 000DCh Timer RJ Mode Register TRJMR 00h 000DDh Timer RJ Event Select Register TRJISR 00h 000DEh Timer RJ Interrupt Control Register TRJIR 00h OOODFh 000E0h Timer RB Control Register TRBCR 00h OOOE1h Timer RB One Shot Control Register TRBOCR 00h 000E2h Timer RB I O Control Register TRBIOC 00h 000E3h Timer
213. SAS Page 10 of 426 R8C M11A Group R8C M12A Group 2 Central Processing Unit CPU 2 Central Processing Unit CPU Figure 2 1 shows the 13 CPU Registers The registers RO R1 R2 R3 AO Al and FB form a single register bank The CPU has two register banks INTBH INTBL The higher 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL b19 Note 1 These registers form a single register bank The CPU has two register banks Figure 2 1 CPU Registers RO1UHO050EJ0200 Rev 2 00 May 18 2012 stENESAS Data registers 0 Address registers 1 Frame base register UI Interrupt table register Program counter User stack pointer Interrupt stack pointer Static base register Flag register Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bits Processor interrupt priority level Reserved bit Page 11 of 426 R8C M11A Group R8C M12A Group 2 Central Processing Unit CPU 2 1 Data Registers RO R1 R2 and R3 RO is a 16 bit register for transfer arithmetic and logic operations The same applies to R1 through R3 RO can be split into high order ROH and low order ROL registers to be used separately as 8 bit data registers The same applies to RIH and RIL R2 can be combined with RO and used as a 32 bit data
214. SP bit is set to 1 one shot count is stopped e When the TSTART bit in the TRBCR register is set to 0 count is stopped and then 1 count is forcibly stopped is written to the TSTOP bit in the TRBCR register Conditions for setting to 1 e When the TOSST bit is set to 1 one shot count is started e When a trigger is input The TRBOCR register is enabled when bits TMOD1 to TMODO in the TRBMR register are 10b programmable one shot generation mode or 11b programmable wait one shot generation mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 200 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 3 Timer RB I O Control Register TRBIOC Address 000E2h Bit b 7 b6 b5 b4 b3 b2 b1 b Smo e ROSE NORTE TOGHT TORT After Reset 0 0 Bit Name TOPL Timer RB output level select bit See Table 14 4 Functions of Timer RB Output Function Level Select Bit TOCNT Timer RB output switch bit 0 Waveform output 1 Fixed value output INOSTG One shot trigger control bit 0 One shot trigger to INTO pin disabled 1 One shot trigger to INTO pin enabled INOSEG One shot trigger polarity select bit 0 Falling edge 1 Rising edge Nothing is assigned The write value must be 0 The read value is 0 TOCNT Bit Timer RB output switch bit The setting of the TOCNT bit is valid only in programmable waveform programmable one shot and programmable wait
215. SR Write JMP B Ll JMP B instruction LI MOV B TRCSR DATA Read 21 9 4 Count Source Switching When switching the count sources stop the count before switching After switching the count sources wait for at least two cycles of the system clock before writing to the registers at addresses OOOE8h to 0OOFCh associated with timer RC e Switching procedure 1 Set the CTS bit in the TRCMR register to 0 count is stopped 2 Change bits CKSO to CKS2 in the TRCCR1 register 3 Wait for at least two cycles of the system clock 4 Write to the registers at addresses OOOE8h to OOOFCh associated with timer RC When changing the count source from fHOCO to another source and stopping fHOCO wait for at least two cycles of the system clock after changing the clock setting before stopping fHOCO e Switching procedure 1 Set the CTS bit in the TRCMR register to 0 count is stopped 2 Change bits CKSO to CKS2 in the TRCCR1 register 3 Wait for at least two cycles of the system clock 4 Set the HOCOE bit in the OCOCR register to 0 high speed on chip oscillator off RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 401 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 9 5 Input Capture Function e Set the pulse width of the input capture signal as follows When the digital filter is not used Three or more cycles of the timer RC operation clock refer to Table 15 1 Timer RC Specifications When the digital
216. Set to 1 by a program TSTART bit in TRBCR register Set to 1 by writing 1 to TOSST bit in TRBOCR register or INTO input trigger TOSSTF bit in TRBOCR register Set to 0 on completion of count Count source Timer RB2 counter Timer RB secondary is reloaded Timer RB primary is reloaded 1 Interrupt request signal Set to 0 by a program Set to 0 bya programi Li TOPL bit in TRBIOC register H Wait state is started Waveform output is started Waveform output is completed TRBO pin output H 1 D LU I re Wait period i One shot pulse output period TRBPRE TRBPR TRBPRE TRBSC 1 The above diagram applies under the following conditions TRBPRE register 01h TRBPR register 01h TRBSC register 03h TOPL bit 0 TOCNT bit 0 waveform output INOSTG bit 1 one shot trigger to INTO pin enabled INOSEG bit 1 rising edge in TRBIOC register TCNT16 bit in TRBMR register 1 16 bit timer Figure 14 8 Example of 16 Bit Timer Operation in Programmable Wait One Shot Generation Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 217 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 5 Selectable Functions 14 5 1 Configuration and Update Timing for Registers TRBPRE TRBPR and TRBSC Registers TRBPRE TRBPR and TRBSC are configured with a master reload register structure Figure 14 9 shows the Configuration of Registers TRBPRE TRBPR and TRBSC When the TSTART bit in the TRBCR r
217. Speed On Chip Oscillator Clock The clock generated by the low speed on chip oscillator is used as the clock source for the CPU clock and the peripheral function clock After the LOCODIS bit in the OCOCR register is set to 0 low speed on chip oscillator on and the wait time for oscillation stabilization has elapsed when the LSCKSEL bit in the SCKCR register is set to 0 low speed on chip oscillator clock and the SCKSEL bit in the CKSTPR register is set to 0 f LOCO the low speed on chip oscillator clock is the system base clock fBASE After a reset the on chip oscillator clock with no division is the CPU clock The frequency of the on chip oscillator clock will vary greatly depending on the power supply voltage and operating ambient temperature Application products must be designed with sufficient margin to allow for these variations in frequency RO1UHO050EJ0200 Rev 2 00 stENESAS Page 86 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 4 Clocks 9 4 1 System Base Clock fBASE The system base clock is selected from the XIN clock oscillation circuit high speed on chip oscillator or low speed on chip oscillator to operate the MCU After a reset the MCU operates using the on chip oscillator clock in standard mode 9 4 2 System Clock f The system clock is obtained by dividing the system base clock by any value from 1 to 256 set by bits PHISELO to PHISEL7 in the PHISEL register Aft
218. T I Interrupt enabled 21 4 2 Program Restrictions When Entering Stop Mode To enter stop mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before setting the STPM bit in the CKSTPR register to 1 all clocks are stopped stop mode The 4 bytes of instruction data following the instruction that sets the STPM bit to 1 are prefetched from the instruction queue and then the program stops Insert at least four NOP instructions following the JMP B instruction immediately after the instruction that sets the STPM bit to 1 e Program example to enter stop mode BCLR 1 FMRO CPU rewrite mode disabled BCLR 7 FMR2 Low current consumption read mode disabled BSET 0 PRCR Writing to CKSTPR register enabled FSET I Interrupt enabled BSET 0 CKSTPR Stop mode JMP B LABEL_001 LABEL_001 NOP NOP NOP NOP RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 389 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 5 Notes on Interrupts 21 5 1 Reading Address 00000h Do not read address 00000h by a program When an external interrupt request is acknowledged the CPU reads interrupt information interrupt number and interrupt request level from address 00000h in the interrupt sequence At this time the corresponding bit in the IRR3 register for the acknowledged interrupt is set to 0 If a program is used to read address 00000h the corresponding bit in the IRR3 register for the interrupt which has the hig
219. T1 VCOUT1 TRJIO Register PMH4E TRJIOC Bit P46SEL2 TOPCR x lt Function Input port Output port XIN clock input external clock input XIN oscillation RXDO input Setting value TXDO output X X X gt lt x x x INT1 input o0 ojojojojojo oj oj ojo j ojo jo X X X X X Xx x x PO X X X gt lt X Xx x x O X VCOUT1 output Other than 000b 001b TRuJIO input oj o oj o o oj ojo j x XxX X XxX x Kx ojojo x XxX X XxX x x oO x x X XxX X XxX x x x x o X 0or 1 Table 12 19 Port P4_7 XOUT INT2 Register PMH4 oi X X x x lt z EXCKCR 001b TRJIO output P47SEL Bit CKPT Function Input port Output port Setting value System clock f output XOUT output X 0or1 INT2 input RO1UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 162 of 426 R8C M11A Group R8C M12A Group 12 I O Ports 12 6 Pont A Figure 12 4 shows the Port A Pin Configuration RESET PA_0 Figure 12 4 Port A Pin Configuration RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 163 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 6 1 Port PA Direction Register PDA Address 000ADh Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACH After Reset 0
220. TRCMR register to 0 count is stopped before switching e After switching the modes set each flag in the TRCSR register to 0 before operation is started 15 7 9 Procedure for Setting Registers Associated with Timer RC Set the registers associated with timer RC following the procedure below 1 Set timer RC operating mode bits PWMB PWMC PWMD and PWM2 in the TRCMR register 2 Set the registers other than that set in 1 3 Set the port output to be enabled bits EA to ED in the TRCOER register RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 276 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 Serial Interface UARTO The serial interface consists of a single channel UARTO 16 1 Overview UARTO has a dedicated timer to generate the transfer clock It supports two modes Clock synchronous serial I O mode and clock asynchronous serial I O UART mode Table 16 1 lists the UARTO Specifications Figure 16 1 shows the UARTO Block Diagram Figure 16 2 shows the Transmit Receive Unit Block Diagram Table 16 2 lists the UARTO Pin Configuration For details see Table 16 4 Clock Synchronous Serial I O Mode Specifications and Table 16 6 Clock Asynchronous Serial I O Mode Specifications Table 16 1 I O pins UARTO Specifications Item Description 3 pins CLKO RXDO and TXDO Clock synchronous serial I O mode Transfer data format Transfer data length 8 bits Transfer clo
221. The following are the conditions when an interrupt is acknowledged eI flag 1 e The interrupt request flag and interrupt enable bit for each peripheral function 1 or external interrupt request flag RR3 1 e Interrupt priority level gt IPL The I flag registers IRRO to IRR3 the ILVLi register i 0 or 2 to E and IPL are independent of each other They do not affect one another Table 11 8 Interrupt Priority Level Settings Bits ILVLi1 to ILVLiO or Bits ILVLi5 to ILVLi4 1 Interrupt Priority Level Level 0 interrupt disabled Priority Level Level 1 Level 2 Level 2 Note 1 Values to be set in interrupt priority level register i ILVLi i 0 or 2 to E Table 11 9 Interrupt Priority Levels Enabled by IPL 000b Levels 1 and 2 Interrupt Priority Level to be Enabled 001b Level 2 010b to 111b None all maskable interrupts are disabled RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 123 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 4 4 Interrupt Sequence The following describes the interrupt sequence performed from when an interrupt request is acknowledged until the interrupt routine is executed When an interrupt request is generated while an instruction is being executed the CPU determines its interrupt priority level after the instruction has completed The CPU starts the interrupt sequence from the following cycle However for the SMOVB SMOVF
222. W An Rn Figure 21 9 Procedure for Software Command Execution When Suspend is Disabled RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 410 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes When the FMR01 bit is 1 CPU rewrite mode enabled the FMRO02 bit is 1 EW1 mode and the FMR20 bit is 1 suspend enabled 7 Program example for the countermeasure when First command writing using the program command MOV B 40h A1 First command writing FSET Interrupts enabled l 1 JMP S CMD2 interrupts enabled NOP CMD2 MOV B A0 A1 Second command writing II MOV B A1 ROL Dummy read JMP S CMD2 NOP NOP NOP NOP LABEL1 BTST FST7 Flash memory status confirmed JNC LABEL1 Speci CMD2 BTST FST3 Suspend status confirmed EI RE iting 2 BCLR to be used _ MOV B A1 ROL Dummy read JMP LABEL Additional Flash memory dummy LABEL2 processing read NOP instruction x 4 Additional processing Flash memory Additional dummy read processing FMR21 0 Suspend tatus confirmed 4 Flag in the CPU register FMRO01 FMRO2 Bits in the FMRO register FMR20 FMR21 Bits in the FMR2 register FST3 FST6 FST7 Bits in the FST register Notes 1 When executing the read array command and clear status register command this countermeasure is not necessary 2 Use one of the following instructions for the second command writing e MOV B A0 A1 or MOV B A1 A0 e MOV B IM
223. a emulator and VCC revised Nov 30 2010 Allpages Preliminary and Under development deleted B 1 00021h 00025h 00030h and 00035h revised B 2 OOODEh and 000E7h revised 1 1 revised Table 1 2 IRR3 and IRR2 revised Table 1 3 Watchdog timer revised Table 1 4 Note 1 revised Table 1 5 revised Table 1 7 revised Figure 2 1 revised Table 3 1 00021h 00025h 00030h to 00033h and 00035h revised Table 3 4 OOODEh and 000E7h revised Table 3 9 Notes 1 and 2 revised 4 revised Table 5 1 Notes 3 and 4 revised 5 2 1 6 2 1 SRST Bit revised 5 2 2 After Reset Note 3 revised When changing peripheral function beforehand added 5 2 5 6 2 2 revised 5 2 6 6 2 3 Note 1 revised 5 2 7 6 2 4 Note 1 revised Table 5 3 5 2 4 Hardware Reset Protect Register HRPR and Table 5 3 added Table 6 2 Notes 2 and 3 revised Figure 6 2 Note 1 revised 6 3 2 revised the last Figure 6 3 deleted 7 2 2 Note 1 revised 7 6 and Figure 7 6 added Table 8 1 revised Note 1 deleted Figure 8 1 revised Table 8 2 and 8 2 1 revised 8 2 2 to 8 2 4 After Reset revised 8 2 6 revised 8 3 1 1 and Figure 8 2 revised REVISION HISTORY R8C M11A Group R8C M12A Group User s Manual Hardware Description Summary Nov 30 2010 68 Table 8 3 revised Notes 2 and 3 deleted 69 Table 8 4 Notes 1 to 3 deleted 70 Table 8 5 revised Note 1 added and Figure 8 3 revised 71 8 4 revised 721090 9 Clock Gener
224. a is allocated separately from the user ROM area Product with 2 KB ROM Product with 4 KB ROM Product with 8 KB ROM 03000h 03000h 03000h SECH Block A 1 Kbyte SECH Block A 1 Kbyte SECH Block A 1 Kbyte BECH 037FFh Block B 1 Kbyte 037FEh Block B 1 Kbyte 037FFh Block B 1 Kbyte OE000h Block 2 4 Kbytes OF000h Program ROM Block 1 4 Kbytes Block 1 4 Kbytes OF800h Block 1 2 Kbytes OFFFFh OFFFFh OFFFFh User ROM area User ROM area User ROM area Figure 19 1 Flash Memory Block Diagram RO1UH0050EJ0200 Rev 2 00 RENESAS Page 325 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 3 ID Code Check Function The ID code check function prevents the flash memory from being read rewritten or erased when standard serial T O mode is used This function is implemented by checking the ID codes written in the ID code area The ID code area is assigned to certain of the highest addresses for each vector in the fixed vector table OFFDFh OFFE3h OFFEBh OFFEFh OFFF3h OFFF7h and OFFFBh The ID code area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Figure 19 2 shows the ID Code Area ID code area i Address i OFFDCh to OFFDFh Undefined instruction vector Li Li U OFFEOh to OFFE3h Overflow vector EE OFFE4h to OFFE7h BRK instruction vector U U U A OFFE8h to OFFEBh Je Address match vector U U I L OFFECh to OFFEFh 104 S
225. a system evaluation test for each of the products 1 How to Use This Manual Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU It is intended for users designing application systems incorporating the MCU A basic knowledge of electric circuits logical circuits and MCUs is necessary in order to use this manual The manual comprises an overview of the product descriptions of the CPU system control functions peripheral functions and electrical characteristics and usage notes Particular attention should be paid to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions For details see the text of the manual The following documents apply to the R8C M11A Group and R8C M12A Group Make sure to see the latest versions of these documents The newest versions of the documents listed may be obtained from the Renesas Electronics Web site Document Type Description Document Title Document No Datasheet Hardware overview and electrical characteristics R8C M11A R0O1DS0010EJ Group R8C M12A Group Datasheet User s manual Hardware specifications pin assignments memory R8C M11A This User s manual Hardware maps per
226. able 17 5 Channel Groups and A D Converter Input Channels Reserved Set to 0 ADGSELO A D input group select bits b7 b6 ADGSEL1 0 0 Channel group 0 ANO AN1 0 1 Channel group 1 AN2 AN3 1 0 Channel group 2 AN4 AN7 1 1 Do not set The ADINSEL register must be written only when A D conversion is stopped CHO Bit Channel select bit The input channel must be selected when the ADST bit in the ADCONDO register is 0 A D conversion stops Table 17 5 Channel Groups and A D Converter Input Channels e One Shot Mode Single Sweep Mode ADGSEL1 Bit ADGSELO Bit CHO Bit Repeat Mode Repeat Sweep Mode Channel group 0 ANO AN1 Channel group 1 AN2 AN3 Channel group 2 AN4 AN7 RO1UHO050EJ0200 Rev 2 00 RENESAS Page 304 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 2 4 A D Control Register 0 ADCONO Address 0009Eh Bit b7 b6 b5 b4 b3 b2 b1 b Symbol TTT AS After Reset 0 0 0 0 0 0 0 0 Bit Name Function A D conversion start bit 0 A D conversion stops 1 A D conversion starts Nothing is assigned The write value must be 0 The read value is 0 The ADCONDO register is used to control A D conversion operation ADST Bit A D conversion start bit The ADST bit is used to start or stop A D conversion Conditions for setting to 0 e When A D conversion is completed in one
227. ad mode enabled in low speed on chip oscillator mode XIN clock stopped power consumption when reading the flash memory can be reduced Refer to 10 5 11 Low Current Consumption Read Mode for details When the CPU clock is set to the low speed on chip oscillator clock divided by 4 8 or 16 low current consumption read mode can be used When divided by 1 no division or divided by 2 is set do not use low current consumption read mode After setting the divide ratio of the CPU clock set the FMR27 bit to 1 Enter wait mode or stop mode after setting the FMR27 bit to 0 low current consumption read mode disabled Do not enter wait mode or stop mode while the FMR27 bit is 1 ow current consumption read mode enabled When the FMR27 bit is set to 1 low current consumption read mode enabled do not execute the program block erase or lock bit program command To change the FMSTP bit from 1 flash memory stops to 0 flash memory operates make the setting when the FMR27 bit is set to 0 low current consumption read mode disabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 337 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 5 5 Flash Memory Refresh Control Register FREFR Address 001ADh Bit b 7 b6 b5 b4 b3 b2 b1 b Smo PEFS ert REFS REF REPT REF After Reset 0 0 Bit Name Function Periodic refresh interval control bits Value in the FREFR register fs 103 the result value is e
228. adient Figure 21 11 Ripple Voltage Definition RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 413 of 426 May 18 2012 R8C M11A Group R8C M12A Group 22 Notes on On Chip Debugger 22 Notes on On Chip Debugger When using the on chip debugger to develop and debug programs for the R8C M11A Group and R8C M12A Group attention must be paid to the following restrictions 1 Some of the user flash memory and RAM areas are used by the on chip debugger These areas cannot be accessed by the user See the on chip debugger manual for which areas are used 2 Do not set the address match interrupt registers AIENi and AIADRi i 0 or 1 and fixed vector table in a user system 3 Do not use the BRK instruction in a user system 4 The debugging is possible with VCC in the range of 1 8 V to 5 5 V Set the supply voltage to 2 7 V or above for rewriting the flash memory There are some special restrictions on connecting and using the on chip debugger For details see the on chip debugger manual RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 414 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 1 Package Dimensions Appendix 1 Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the Packages section of the Renesas Electronics website JEITA Package Code RENESAS Code Previous Code MASS Typ P TSSOP14 4 4x5 0 65 PTSP0014JA B TTP 14DV 0 05g
229. ag indicates that a reset has been generated by software Condition for setting to 0 e When a watchdog timer reset hardware reset power on reset or voltage monitor 0 reset occurs Condition for setting to 1 e When a software reset occurs RO1UHO050EJ0200 Rev 2 00 RENESAS Page 38 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets WDR Bit Watchdog timer reset detect flag This flag indicates that a reset has been generated by the watchdog timer Condition for setting to 0 e When a software reset hardware reset power on reset or voltage monitor 0 reset occurs Condition for setting to 1 e When a watchdog timer reset occurs RO1UHO050EJ0200 Rev 2 00 stENESAS Page 39 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 2 3 Address OFFDBh Bit b7 b6 Option Function Select Register 2 OFS2 b5 b4 b3 b2 b1 bO MSN _ WOTACST WOTRCSO WOTUFST WOTUFSO After Reset User Setting Value 1 Bit Name Function bO WDTUFSO Watchdog timer underflow period b1 bO R W b1 WDTUFST setting bits GE R W 0 1 OFFFh 10 1FFFh 11 3FFFh b2 WDTRCSO Watchdog timer refresh acceptance 1 63 2 R W b3 WDTRCS1 period setting bits 0 0 25 R W 01 50 10 75 11 100 b4 Reserved Set to 1 R W b5 MSTINI MSTCR register initial value select bit 0 MSTCR register is set to 00h after reset R W 1 MSTCR register is set to 77h after reset b6
230. age 375 of 426 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 13 DC Characteristics 1 4 0 V lt Vcc lt 5 5 V Standard Parameter Condition Min Output high voltage P1_2 P1_3 P1_4 P1 When drive lOH 20 mA P3_3 P3_4 P3_5 P3 capacity is high When drive lOH 5 mA capacity is low P1_0 P1_1 P1_6 P1 Ion 5 mA P4_2 P4_5 P4_6 P4 PA_O Output low voltage P1_2 P1_3 P1_4 P1 When drive loL 20 mA P3_3 P3_4 P3_5 P3 capacity is high When drive loL 5 mA capacity is low P1_0 P1_1 P1_6 P1 loL 5 mA P4_2 P4_5 P4_6 P4_7 PA_O Hysteresis INTO INT1 INT2 INT3 Vec 5V KIO KI1 Kl2 KI3 TRJIO TRCIOA TRCIOB TRCIOC TRCIOD RXDO CLKO RESET Vec 5V IIH Input high current Vi 5V Vcc 5 0 V liL Input low current V 0 V Vcc 5 0 V Rputtur Pull up resistance Vi 0V Vcc 5 0 V R XIN Feedback resistance VRAM RAM hold voltage In stop mode Notes 1 4 0 V lt Vcc lt 5 5 V and Topr 20 C to 85 C N version 40 C to 85 C D version f XIN 20 MHz unless otherwise specified 2 High drive capacity can also be used while the peripheral output function is used RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 376 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 14 DC Characteristics 2 4 0 V lt Vcc lt 5 5 V Topr
231. ait one shot generation modes when the TOSSP bit in the TRBOCR register is set to 1 and the one shot is stopped the timer reloads the reload register value and is stopped The timer count value must be read before the timer is stopped e After 1 count is started is written to the TSTART bit in the TRBCR register while the count is stopped the TCSTF bit in the TRBCR register remains 0 count is stopped for two to three cycles of the count source Do not access the registers associated with timer RB2 other than the TCSTF bit until this bit is set to 1 count is in progress The count is started on the first active edge of the counter source after the TCSTF bit is set to 1 After 0 count is stopped is written to the TSTART bit during count operation the TCSTF bit remains 1 for two to three cycles of the count source When the TCSTF bit is set to 0 the count is stopped Do not access the registers associated with timer RB2 other than the TCSTF bit until this bit is set to 0 Note 1 Registers associated with timer RB2 TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBPR and TRBSC e In timer mode do not set both the TRBPRE and TRBPR registers to 00h at the same time e When the TSTART bit in the TRBCR register is 0 count is stopped change the values of registers TRBPRE TRBPR and TRBSC then wait for at least two cycles of the system clock f before setting the TSTART bit in the TRBCR register to count is started e When the TSTART bit
232. ak When drive capacity is low When drive capacity is high 5 When drive capacity is low L avg Average output low current When drive capacity is high 5 2 7 V lt Vcc lt 5 5 V 1 8 V lt Vcc lt 2 7 V 2 7 V lt Vcc lt 5 5 V 1 8 V lt Vcc lt 2 7 V 1 8 V lt Vcc lt 5 5 V 1 8 V lt Vece lt 5 5 V 2 7 V lt Vcc lt 5 5 V 1 8 V lt Vcc lt 2 7 V 2 7 V lt Vcc lt 5 5 V 1 8 V lt Vcc lt 2 7 V F XIN XIN oscillation frequency XIN clock input oscillation frequency High speed on chip oscillator oscillation frequency 3 Low speed on chip oscillator oscillation frequency 4 System clock frequency CPU clock frequency Notes 1 Vcc 1 8 V to 5 5 V and Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified The average output current indicates the average value of current measured during 100 ms For details see Table 20 10 High Speed On Chip Oscillator Circuit Electrical Characteristics For details see Table 20 11 Low Speed On Chip Oscillator Circuit Electrical Characteristics The pins with high drive capacity are P1_2 P1_3 P1_4 P1_5 P3_3 P3_4 P3_5 and P3_7 of WP 30 pF rh Figure 20 1 Ports P1 P3 and P4 Timing Measurement Circuit R01UH0050EJ0200 Rev 2 00 May 18 2012 RENESAS Page 369 of 426 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 2
233. am Table 14 1 Timer RB2 Specifications Item Description Operating modes Timer mode An internal count source or timer RJ2 underflow is counted Programmable waveform An arbitrary pulse width is output successively generation mode Programmable one shot A one shot pulse is output generation mode Programmable wait one shot A delayed one shot pulse is output generation mode Count source Selectable from f1 f2 f4 f8 82 f64 f128 and timer RJ2 underflow Interrupt Timer RB2 underflow TRBPRE TCK2 to TCKO register Reload Reload Reload TCKCUT register register register Timer RJ2 underflow a NE 5 Timer RB2 interrupt 8 bit counter 8 bit counter e r 8 bit timer with 8 bit prescaler Ui e 16 bit timer TMOD1 to TMODO Tew 10b or 11b INOSEG INOSTG ee O TOCNT 1 Write 1 to TSTOP TMOD1 to TMODO 01b 10b or 11b INTOEN Bit in INTEN register TSTART TSTOP Bits in TRBCR register TOSST Bit in TRBOCR register TOPL TOCNT INOSTG INOSEG Bits in TRBIOC register TMODO to TMOD1 TCKO to TCK2 TCKCUT Bits in TRBMR register Notes 1 When the TCNT16 bit in the TRBMR register is 0 the 8 bit timer with 8 bit prescaler is selected 2 When the TCNT16 bit in the TRBMR register is 1 the 16 bit timer is selected Figure 14 1 Timer RB2 Block Diagram RO1UHO050EJ0200 Rev 2 00 RENESAS Page 196 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14
234. ammable wait one shot generation mode Note Timer RB prescaler underflow is counted the wait period is counted 16 Bit Timer An internal count source or the timer RJ2 underflow is counted Initial Value Setting 00h to FFh Range 00h to FFh 00h to FFh 1 The values in registers TRBPR and TRBSC are reloaded and counted alternately 00h to FFh In the 8 bit timer with 8 bit prescaler the TRBPR register is used to set the period of the counter and the primary period When read the value is from the 8 bit counter In the 16 bit timer the TRBPR register is used to set the period of the higher 8 bit counter and the primary period When read the value is read from the higher 8 bits of the 16 bit timer Access the TRBPRE register and then the TRBPR register The TRBPR register is configured with a master reload register structure so the reload register is written simultaneously while the count is stopped During the counter operation the timing for updating the reload register differs in each mode For details see Table 14 6 Reload Register Update Timing for Registers TRBPR and TRBSC in 8 Bit Timer with 8 Bit Prescaler and Table 14 7 Reload Register Update Timing for Registers TRBPRE TRBPR and TRBSC in 16 Bit Timer RO1UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 204 of 426 R8C M11 A Group R8C M12A Group 14 Timer RB2 14 3 7 Timer RB Secondary Register
235. area causes the ID code area to be set to FFh When blank products are shipped the ID code areas are set to FFh They are set to the written value after written by the user When factory programming products are shipped the value of the ID code areas is the value programmed by the user RO1UHO050Ev0200 Rev 2 00 stENESAS Page 23 of 426 May 18 2012 R8C M11A Group R8C M12A Group 4 Bus Control 4 Bus Control The number of bus cycles differ depending on the area accessed ROM RAM or SFR Table 4 1 lists the Number of Bus Cycles for Accessing Different Areas Table 4 2 lists the Access Units and Bus Operations The units for SFR access are specified as Access Size in the register configuration table in each chapter The peripheral function modules are connected to the CPU via an 8 bit bus Thus when these areas are accessed as word 16 bit units they are accessed twice in 8 bit units Table 4 1 Number of Bus Cycles for Accessing Different Areas Access Area Bus Cycle ROM data flash 2 cycles of CPU clock SFR other than FMR2 register SFR FMR2 register 6 cycles of CPU clock ROM program ROM 1 cycle of CPU clock RAM Table 4 2 Access Units and Bus Operations Even address byte access Odd address byte access Even address word access Odd address word access CPU clock Address Data CPU clock Address Data CPU clock Address Data CPU clock
236. ation INTi input Sampling timing 4 ii ii A t j j t IRIi bit in IRR3 register Set to 0 by a program i 0to3 Note 1 In this example bits INTIF1 to INTIFO in the INTFO register are 01b 10b or 11b filter used Figure 11 10 Example of INTi Input Filter Operation RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 131 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 6 Key Input Interrupt A key input interrupt request is generated by one of the input edges on pins KIO to KI3 The key input interrupt can be used as a key on wakeup function to cancel wait mode or stop mode The KHIEN bit i 0 to 3 in the KIEN register is be used to select whether the pins are used as the KD input The KIiPL bit in the KIEN register is be used to select the input polarity When a low level is input to the KD pin which sets the KIiPL bit to 0 falling edge inputs to the other pins KIO to KI are not detected as interrupts Likewise when a high level is input to the KD pin which sets the KIiPL bit to 1 rising edge inputs to the other pins KIO to KI3 are not detected as interrupts Figure 11 11 shows the Block Diagram for Key Input Interrupts Table 11 12 lists the Pin Configuration for Key Input Interrupts PU1_3 bit in PUR1 register a PD1_3 bit in PD1 register transistor d _9 biti egiste KISEN bit K3 KI2EN bit Pull up transistor A Interrupt Key input B control circuit interrupt request KI1EN
237. ation The symbols and terms used in register diagrams are described below X X X XXX Register Symbol Address XXXXXh Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol XXX7 XXX6 XXX5 Le ee ee XXX1 XXX0 After Reset 0 0 0 0 0 0 0 0 Bit Name Function bt bO 0 0 XXX 0 1 XXX 1 0 Do not set 1 1 XXX Nothing is assigned The write value must be 0 The read value is undefined Reserved Set to 0 XXX bits Function varies depending on the operating mode XXX bit WI R W Read and write R Read only W Write only Nothing is assigned 2 e Reserved Reserved bits Set to the specified value 3 e Nothing is assigned Nothing is assigned to the bit As the bit may be used for future functions if necessary set to 0 e Do not set Operation is not guaranteed when a value is set e Function varies depending on the operating mode The function of the bit varies with the peripheral function mode For information on the individual modes see the register diagram 4 List of Abbreviations and Acronyms Abbreviation Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment Bus Input Output Infrared Data Association Least Significant Bit Most Significant Bit Non Connect Phase Locked Loop Pulse Width Modulation Subsc
238. ation Circuit revised 91 379 9 6 21 3 revised 92 to 106 10 Power Control revised 107 380 10 6 21 4 revised 108 Table 11 1 revised 111 11 2 1 Note 1 added 113 11 2 4 Note 1 revised 115 11 2 6 and 11 2 7 revised 116 11 2 8 revised 118 11 2 10 and 11 2 11 The resister remains or software reset added 119 Table 11 5 OFFE7h gt OFFE6h 121 11 4 2 revised Table 11 7 added 122 11 4 3 revised 123 11 4 4 1 revised 125 11 4 7 revised 128 Figure 11 8 Note 1 deleted 129 11 5 1 revised 130 11 5 2 and Figure 11 9 revised 131 Figure 11 11 revised 132 11 7 revised 133 Figure 11 12 revised 135 382 11 9 4 21 5 4 Figure 11 13 and Figure 21 1 revised 136 383 11 9 5 21 5 5 revised Figure 11 14 Figure 21 2 added 137 384 11 9 6 21 5 6 Figure 11 15 Figure 21 3 added 140 12 2 and 12 2 1 revised 142 12 3 2 revised 143 12 3 4 Note 1 added 148 Tables 12 9 and 12 10 revised 150 12 4 2 revised 151 12 4 4 Note 1 added 154 Table 12 15 revised 156 12 5 2 revised 160 Table 12 16 Table 12 18 and Table 12 19 revised 162 12 6 2 revised 163 12 7 added 166 Figure 12 6 revised Figure 12 7 added 167 Figure 12 9 revised 168 Figure 12 10 revised REVISION HISTORY R8C M11A Group R8C M12A Group User s Manual Hardware Description Summary Nov 30 2010 169 Figure 12 11 revised 172 Figures 12 15 and 12 16 revised 173 Figure 12 17 revised 175 385 12 11 2 21 6 2 added 176 13 and Table 13
239. atus register command this countermeasure is not necessary 2 Use one of the following instructions for the second command writing e MOV B A0 A1 or MOV B A1 AO MOV B IMM An eMOV B IMM abs16 e MOV B RnH An e MOV B RnH absi6 e MOV B RnL An e MOV B RnL abs16 Use one of the following instructions to read the same address as the second command write address e MOV B An RnL e MOV B An RnH e MOV W An Rn Figure 19 22 Procedure for Software Command Execution When Suspend is Disabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 365 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory When the FMR01 bit is 1 CPU rewrite mode enabled the FMRO02 bit is 1 EW1 mode and the FMR20 bit is 1 suspend enabled Program example for the countermeasure when First command writing using the program command MOV B 40h A1 First command writing FSET Interrupts enabled l 1 JMP S CMD2 interrupts enabled NOP CMD2 MOV B A0 A1 Second command writing MOV B A1 ROL Dummy read 9 JMP S CMD2 NOP NOP NOP NOP LABEL1 BTST FST7 Flash memory status confirmed JNC LABEL Specif CMD2 BTST FST3 Suspend status confirmed S a Gr iting 2 BCLR to be used _ MOV B A1 ROL Dummy read JMP LABEL Additional Flash memory dummy LABEL2 processing read 3 NOP instruction x 4 Additional processing Flash memory Additional dummy read Di processing FMR21 0 Suspend
240. authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not su
241. be reduced by executing program operations in such a way that all blank areas are used up before performing an erase operation Avoid rewriting only particular blocks and average out the number of programming erasure of the blocks It is also advisable to retain data on the number of erasure of each block and limit the number to a certain extent 4 For details on the ID code check function see 19 3 ID Code Check Function Table 19 2 Flash Memory Rewrite Mode Function Flash Memory Rewrite Mode CPU Rewrite Mode The user ROM area is rewritten by executing software commands from the CPU User ROM User program Standard Serial UO Mode The user ROM area is rewritten using a dedicated serial programmer User ROM Standard boot program Rewritable area Rewrite programs RO1UHO050EJ0200 Rev 2 00 May 18 2012 RENESAS Page 324 of 426 R8C M11A Group R8C M12A Group 19 Flash Memory 19 2 Memory Map The flash memory contains a user ROM area and a boot ROM area reserved Figure 19 1 shows the Flash Memory Block Diagram The user ROM area contains program ROM and data flash e Program ROM Flash memory mainly used for storing programs e Data flash Flash memory mainly used for storing data to be rewritten The user ROM area is divided into several blocks The rewrite control program standard boot program for standard serial I O mode is stored in the boot ROM area when the MCU is shipped The boot ROM are
242. ber of 1 s in the parity and character bits do not match the set number of 1 s 2 e Error sum flag This flag is set to 1 if an overrun framing or parity error occurs 1 If an overrun error occurs the receive data b0 to b8 in the UORB register is undefined The UORIF bit in the UOIR register remains unchanged 2 The framing error flag and the parity error flag are set to 1 when data is transferred from the UARTO receive register to the UORB register RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 291 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO Table 16 7 Register Registers and Settings Used in Clock Asynchronous Serial I O Mode bO to b8 Function Set the transmit data 1 bO to b8 The receive data can be read 2 OER Overrun error flag FER Framing error flag PER Parity error flag SUM Error sum flag bO to b7 Set the bit rate SMD2 to SMDO Set to 100b when transfer data is 7 bits long Set to 101b when transfer data is 8 bits long Set to 110b when transfer data is 9 bits long CKDIR Select an internal or external clock STPS Select one or two stop bits PRY PRYE Select whether parity is enabled and whether odd or even CLKO to CLK1 Select the UOBRG count source f1 f8 or 32 TXEPT Transmit register empty flag NCH Select the output type CMOS or N channel open drain output
243. bit Pull up transistor KIOEN bit Pull up transistor KIOEN KHEN KI2EN KISEN KIOPL KI1PL KI2PL KI3PL Bits in KIEN register Figure 11 11 Block Diagram for Key Input Interrupts Table 11 12 Pin Configuration for Key Input Interrupts Pin Name Function KIO interrupt input KI interrupt input KI2 interrupt input KI3 interrupt input RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 132 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 7 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the AIADRi register i 0 or 1 This interrupt is used as a break function for the debugger When the on chip debugger is used do not set an address match interrupt registers AIENi and AJIADRi and fixed vector table in the user system Set the start address of any instruction in these registers The AIENiO bit i 0 or 1 in the AIENi register can be used to enable or disable the interrupt The address match interrupt is not affected by the I flag and IPL The PC value see 11 4 7 Saving Registers which is saved on the stack when an address match interrupt request is acknowledged will differ depending on the instruction at the address indicated by the AIADRi register The appropriate return address is not saved on the stack When the MCU returns from the address match interrupt use
244. bit in the FMRO register is 1 flash memory is stopped For details on the setting of this bit see 10 5 10 Stopping Flash Memory RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 333 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory CMDRST Bit Erase write sequence reset bit This bit is used to initialize the flash memory sequence and forcibly stop a program or block erase command If the program or block erase command is forcibly stopped using the CMDRST bit in the FMRO register execute the clear status register command after the FST7 bit in the FST register is changed to ready To program the same address again execute the block erase command again and ensure it has been completed normally before programming If the addresses and blocks which the program or block erase command is forcibly stopped are allocated in the program area set the FMR13 bit in the FMRI register to 1 lock bit disabled before executing the block erase command again When the CMDRST bit is set to 1 erasure writing stopped during erase suspend the suspend status is also initialized Thus execute block erasure again to the block which the block erasure is being suspended When td CMDRST READY has elapsed after the CMDRST bit is set to 1 erasure writing stopped the executing command is forcibly terminated and reading from the flash memory is enabled CMDERIE Bit Erase write error blank check error command sequence error interrupt enable b
245. bits Set to 0 POD4 000C4h POD4_2 POD4_5 Reserved bits Set to 0 PML4 000CEh P42SEL0 P42SEL1 Reserved bits Set to 0 PMH4 000CFh P45SELO P45SEL1 Reserved bits Set to 0 ANO ADINSEL 0009Dh CHO ADGSELO ADGSEL1 Do not set to 000 Comparator B3 WCMPR 00180h WCB3M0 WCB30UT Reserved bits Set to 0 WCBS3INTR 00182h All bits Reserved register No access is allowed RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 3 of 426 R8C M11A Group R8C M12A Group 1 Overview 1 1 3 Specifications Tables 1 3 and 1 4 outline the Specifications Table 1 3 Specifications 1 Function Central processing unit Description R8C CPU core e Number of fundamental instructions 89 e Minimum instruction execution time 50 ns f XIN 20 MHz VCC 2 7 V to 5 5 V 200 ns f XIN 5 MHz VCC 1 8 V to 5 5 V e Multiplier 16 bits x 16 bits 32 bits e Multiply accumulate instruction 16 bits x 16 bits 32 bits 32 bits e Operating mode Single chip mode address space 1 Mbyte Memory ROM RAM data flash See Table 1 5 Product List Reset sources e Hardware reset by RESET e Power on reset e Watchdog timer reset e Software reset e Reset by voltage detection 0 Voltage detection Voltage detection circuit Voltage detection with two check points Voltage detection
246. bject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or u
247. ble interrupts AND B 0CFH ILVLE Set INTO interrupt priority level 0 POPC FLG Enable interrupts RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 394 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 6 Notes on UO Ports 21 6 1 Notes on PA_0 Pin The PA_0 pin is multiplexed with the hardware reset function RESET The PA_0 pin functions as the RESET function after any reset hardware reset power on reset voltage monitor 0 reset by voltage detection circuit watchdog timer reset and software reset occurs After the reset is cleared the PA_O pin can be set to the I O port function or the hardware reset function by the HWRSTE bit in the PAMCR register When a low level is input to the RESET pin before a reset is cleared the level will be recognized by the MCU as hardware reset and the reset state will not be cleared until a high level is input to the RESET pin When the HWRSTE bit is set to 0 the RESET PA_0 pin becomes the PA_0 I O port When this pin is used as an input port an external pull up resistor must be connected When used as an output port the open drain output function must be enabled to avoid conflicting with an external reset signal accidently See the following assembly language e Program example to set DA OU as an output port MOV B 00000000b HRPR MOV B 00000001b HRPR PAMCRE 1 un protect PAMCR register MOV B 00000001b PAMCR HWRSTE 0 PODA_0 1 MOV B 00000001b PDA PDA_0
248. ble to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power
249. caecsaecaeceaesseeeeseeeeeseaeeaeeeaes 107 10 6 Notes on Power Control 2 csecd cca RASA ee Eed 108 10 6 1 Program Restrictions When Entering Wait Mode ou eee esses cssessececeseeseceseeseeeeceeeeseecaecaeecaesaeneeeees 108 10 6 2 Program Restrictions When Entering Stop Mode oo ee eeceeeeeeceeeeeeeseeeeecneeseecsecsaecaesaeessesseeensees 108 BIEN e EE 109 11 1 Overview n ha A ES A ee EE Re Bo be a et eo 109 11 2 RES ISECTS eist ed Eer 111 11 2 1 External Input Enable Register INTEN AAA 112 11 2 2 INT Input Filter Select Register O INTRO 0 eee ceceseeseceseeeecesceeeeeeeeseseaeeseeeaecaeecaecaesaeeeeeseseensees 112 11 23 INT Input Edge Select Register 0 ISCRO oo eee ceceeeeeceeeceeeeseecaecaeecaecsaesaecesesessesseseeseseseaeeaeeeaes 113 11 2 4 Key Input Enable Register KIEN AA 114 11 2 5 Interrupt Priority Level Register i ILVLi i 0 or 2 to E wee cece eeeeeseeceececeeceeeeceseeesaeceeecaeeeaeeeeneens 115 11 2 6 Interrupt Monitor Flag Register 0 IRRO oo eee eee ceeceseeseceseesecesceseeeeesseseaeesecsaecaecsaecsesaeeeesseensensees 116 11 2 7 Interrupt Monitor Flag Register 1 IRR1 oo ceeceseeseceseeseceeceeeseeeseeeaeesecsaecaecsaecaseaeeaeseseeneensees 116 11 2 8 Interrupt Monitor Flag Register 2 IRR2 oo eee eeeesecseceseeseceseeeecesceeeeeeceseseaseseesaecsecsaecaseaeeaeeseensesees 117 11 2 9 External Interrupt Flag Register IRR3 oo cece ceeceseceecesceseeeeceseeseeeaeeesecaaesaecaecnaecaeessesseseeeeseseaeeaaeea
250. cessscesseceseecsseceseeceneeenecesneessecescecneecsaeeeaeeeeeesaaeeneeesaes 76 9 2 2 High Speed Low Speed On Chip Oscillator Control Register OCOCR s sssseeeessersessrerssresrsrrsrrrrsreerereee 77 9 2 3 System Clock f Control Register SCKCR oo eeecsecssesseeseceseeseceeceeeeeneeseesaecsaesaecaeceseeeseseeessaesaeenaes 78 9 2 4 System Clock f Select Register PHISEL ooo eee eee ccceeeceeeeeecseesaecasesaecnecsaeesecsaeeseceeeeseseeseaeesaeaeenaes 79 9 2 5 Clock Stop Control Register CKSTPR ssessesseessssresssreresrssesresrrrrsrentsresrsrresetsesteststesresestrsrerrnseetsrentees 80 9 2 6 Clock Control Register When Returning from Modes CKRSCR A 81 9 2 7 Oscillation Stop Detection Register BAKCR A 83 9 2 8 High Speed On Chip Oscillator 18 432 MHz Control Register 0 FR18S0 oo ee eee eee eeeeereeeeeeee 83 9 2 9 High Speed On Chip Oscillator 18 432 MHz Control Register 1 FR18S1 oo eee ceeeeeeeeeeeeeene 84 9 2 10 High Speed On Chip Oscillator Control Register 1 FRV1 oo eee ceececseeseeceeceaeceeceaeeseceseeeeneeeaeeees 84 9 2 11 High Speed On Chip Oscillator Control Register 2 FRV2 oo cee eceeeceeeeeeseeseecsecssecsecsseesecescneenseeseeaes 84 9 3 Clock Oscillation Circuit tee ANERE ee AANEREN 85 9 3 1 XIN Clock Oscillation Circuit isere ieri reie s Enosa AeKa EI EES EEE TE EEEE Ear EE ESSE 85 9 3 2 High Speed On Chip Oscillator Clock AA 86 9 3 3 Low Speed On Chip Oscillator Clock oo eeeececeeeesceseeesecseecaecsecsaeesec
251. chdog timer is automatically started after reset 1 Watchdog timer is stopped after reset Reserved Set to 1 ROMCR ROM code protect disable bit 0 ROM code protect disabled 1 ROMCP1 bit enabled ROMCP1 ROM code protect bit 0 ROM code protect enabled 1 ROM code protect disabled VDSELO Voltage detection 0 level select VDSEL1 bits b5 b4 0 0 3 80 V typ selected Vdet0_3 0 1 2 85 V typ selected Vdet0_2 1 0 2 35 V typ selected Vdet0_1 1 1 1 90 V typ selected Vdet0_0 LVDAS _ Voltage detection 0 circuit start bit 0 Voltage monitor 0 reset enabled after reset 1 Voltage monitor 0 reset disabled after reset CSPROINI Count source protection mode 0 Count source protect mode enabled after reset after reset select bit 1 Count source protect mode disabled after reset Note 1 The OFS register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS register Erasure of the block including the OFS register causes the OFS register to be set to FFh When blank products are shipped the OFS register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS register is the value programmed by the user For an example of the OFS register settings see 5 6 1 Option Function Select Area Setting Example
252. city selection IOINSEL Bit in PINSR register Figure 12 8 UO Port Configuration 3 Pull up selection Pin function mapping register Output from Open drain Direction register individual peripheral Q selection lt function enabled Output from individual peripheral function Port latch ac Pin function Input to individual peripheral function mapping register Reference input to comparator B IOINSEL Bit in PINSR register Figure 12 9 UO Port Configuration 4 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 169 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Pull up selection Direction register Pin function mapping register T Output from Open drain individual peripheral selection function enabled Output from individual peripheral function Port latch a Pin function Input to individual peripheral function mapping register Analog input to A D converter Analog voltage input to comparator B Input to external interrupt IOINSEL Bit in PINSR register Figure 12 10 UO Port Configuration 5 RO1UHOO050EJ0200 Rev 2 00 ztENESAS Page 170 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Drive capacity selection Pull up selection Direction register Pin function mapping register Output from individual peripheral function enabled Output from individual peripheral function Port latch a Pin function I
253. ck e The CKDIR bit in the UOMR register is 0 internal clock fi 2 n 1 fi f1 f8 or f32 n Value set in the UOBRG register 00h to FFh e The CKDIR bit in the UOMR register is 1 external clock fEXT input from the CLKO pin Error detection Overrun error Clock asynchronous serial I O mode Transfer data format e Character bits transfer data Selectable from 7 8 or 9 bits e Start bit 1 bit e Parity bit Selectable from odd even or none e Stop bit Selectable from 1 or 2 bits Transfer clock e The CKDIR bit in the UOMR register is 0 internal clock fj 16 n 1 fj f1 f8 or 32 n Value set in the UOBRG register 00h to FFh e The CKDIR bit in the UOMR register is 1 external clock fEXT 16 n 1 fEXT input from the CLKO pin n Value set in the UOBRG register 00h to FFh Error detection Overrun error framing error parity error error sum flag Interrupt sources RO1UH0050EJ0200 Rev 2 00 May 18 2012 Transmit buffer empty or transmit complete interrupt multiplexed and receive complete interrupt ztENESAS Page 277 of 426 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO RXDO e Receive 1 16 oe Receive CLK1 to CLKO UART reception cantiol clock 00b CKDIR 0 ueppe circuit i fi Q Transmit Zob nternal register Clock synchronous type S fg o 0 0 0 receive Transmit j 10b O 1 n 1 1 1 16 i unit fg2 yg o a UART transmi
254. clock generated by the prescaler are stopped 10 3 1 Peripheral Function Clock Stop Function When the WCKSTP bit in the CKSTPR register is 1 peripheral function clock stopped in wait mode the system clock and the prescaler are stopped in wait mode to reduce power consumption At this time the peripheral functions that use the system clock and a divided system clock generated by the prescaler are stopped 10 3 2 Entering Wait Mode Wait mode is entered when the WAIT instruction is executed or the WAITM bit in the SCKCR register is set to 1 wait mode is entered 10 3 3 Pin States in Wait Mode The I O ports retain the states immediately before wait mode is entered RO1UHO050EJ0200 Rev 2 00 stENESAS Page 97 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 3 4 Returning from Wait Mode A reset or a peripheral function interrupt is used to return from wait mode Peripheral function interrupts are affected by the WCKSTP bit in the CKSTPR register When the WCKSTP bit is 0 system clock is supplied in wait mode the peripheral function interrupts can be used to return from wait mode When the WCKSTP bit is 1 system clock is stopped in wait mode the peripheral functions that use the peripheral function clock are stopped Only the peripheral function interrupts that operate using external signals fAD the high speed on chip oscillator clock or the low speed on chip clock oscillation of each oscillator
255. clock oscillation stabilizes when the HSCKSEL bit in the SCKCR register is set to 0 XIN clock and the SCKSEL bit in the CKSTPR register is set to 1 FHSCK the XIN clock is selected to be used as the clock source for the CPU clock and the peripheral function clock When the high speed on chip oscillator or the low speed on chip oscillator is used as the system base clock the XIN clock oscillation is stopped by setting bits CKPT1 to CKPTO in the EXCKCR register to 00b This reduces power consumption T he XIN clock is stopped in stop mode When inputting an externally generated clock to the XIN clock do not use stop mode See 10 Power Control for details Note 1 When the P46SEL2 bit in the PMH4E register e When the P46SEL2 bit in the PMH4E is 0 bits P47SEL1 to P47SELO and P46SEL1 register is 0 bits PA46SEL1 to P46SELO to P46SELO in the PMH4 register are 0000b in the PMH4 register are 00b and bits and bits CKPT1 to CKPTO in the EXCKCR CKPT1 to CKPTO in the EXCKCR register are 11b P4_6 XIN P4_7 XOUT register are 11b P4_6 XIN clock input external clock input P4_7 I O port MCU MCU on chip feedback resistor on chip feedback resistor XIN XOUT XIN XOUT Externally generated clock SC JUU LU External ceramic resonator connected circuit External clock input circuit Insert a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity Use the values r
256. contents SP value before interrupt Previous stack contents request is acknowledged Ui SP j New SP value 1 Previous stack contents Previous stack contents Stack state before interrupt Stack state after interrupt request is acknowledged request is acknowledged PCL Lower 8 bits of PC PCM 8 bits in the middle of PC Note PCH Higher 4 bits of PC 1 When an INT instruction for software interrupts numbered 32 to 63 FLGL Lower 8 bits of FLG has been executed this SP is the SP specified by the U flag FLGH Higher 4 bits of FLG Otherwise it is ISP Figure 11 5 Stack State Before and After Interrupt Request is Acknowledged RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 126 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts The register saving operation in the interrupt sequence uses four operations each one of which saves 8 bits Figure 11 6 shows the Register Saving Operation MSB Address SP SP SP Saved 8 bits at a time SP Register saving completed in four operations PCL Lower 8 bits of PC PCM 8 bits in the middle of PC PCH Higher 4 bits of PC FLGL Lower 8 bits of FLG FLGH Higher 4 bits of FLG Note 1 SP indicates the SP initial value when an interrupt request is acknowledged After registers are saved the SP content becomes SP minus 4 When an INT instruction for software interrupts numbered 32 to 63 has been executed this SP is the SP specif
257. conversion accurately charging of the internal capacitor C shown in Figure 17 8 must be completed within the period of time specified as T sampling time Let the output impedance of the sensor equivalent circuit be RO the internal resistance of the microcomputer be R the accuracy error of the A D converter be X and the resolution of A D converter be Y Y is 1024 in 10 bit mode Se VC is generally VC vin e C RO R And when t T VC VIN VIN vin 1 ee Oe e C RO R lt I zal me in C RO R Y T CeinX Y Hence RO R Figure 17 8 shows the Analog Input Pin and External Sensor Equivalent Circuit The user can obtain an impedance RO that makes the pin to pin voltage VC increase from 0 to VIN 0 1 1024 VIN within time T when the difference between VIN and VC becomes 0 1 LSB The value 0 1 1024 indicates a precondition for the calculation of RO when the degradation due to insufficient capacitor charge is suppressed to 0 1 LSB during A D conversion in 10 bit mode The actual error however is the absolute accuracy plus 0 1 LSB A D conversion clock 20 MHz T 0 8 us Output impedance RO through which an capacitor C is fully charged within T is obtained as follows T 0 8 us R 10 KQO C 6 0 pF X 0 1 and Y 1024 Hence 0 8 x 1076 6 0 x 10 712 e jn Hl 1024 RO 10 x 10 4 4 x 103 Thus the maximum output impedance of a sensor circuit for an accuracy error of 0 1 LSB or less is
258. counter is stopped 6 When the TSTART bit in the TRJCR register is 1 count is started or the TCSTF bit is 1 count is in progress allow at least three cycles of the count source clock for each write interval when writing to the TRJ register successively 7 Note the following when writing 0 to the TEDGF bit in the TRJCR register in pulse width measurement mode or pulse period measurement mode Set the TRJIF bit in the TRJIR register to 0 before setting the TEDGF bit to 0 When reading the TEDGF bit immediately after setting it to 0 it is read as 0 However the internal signal of the TEDGF bit remains 1 for one to two cycles of the count source If an active edge is input during this period the internal signal of the TEDGF bit does not become 0 and the TEDGF bit is read as 1 Since the TRJIF bit becomes when the internal signal of the TEDGF bit changes from 0 to 1 the TRJIF bit does not become and no interrupt is generated After setting the TEDGF bit to 0 confirm that 0 can be read after waiting for three or more count source cycles in order to accept the next interrupt request RO1UH0050EJ0200 Rev 2 00 RENESAS Page 193 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 8 When the TEDGSEL bit in the TRJIOC register is set to O count on rising edge and the external signal TRJIO is counted in event counter mode the signal may not be counted correctly depending on the state of the TSTART bit in the TRJCR re
259. ctions to be used to return from wait mode If the MCU returns from wait mode without executing any interrupt for external interrupts INTO to INT3 and KIO to KI3 bits IRIO to IRI3 and IRKI in the IRR3 register are not changed automatically Set these bits to 0 by a program The system base clock when returning from wait mode by a peripheral interrupt is the clock set by the WAITRS bit in the CKRSCR register At this time bits PHISSELO to PHISSEL 2 in the SCKCR register and the SCKSEL bit in the CKSTPR register are automatically changed according to bits PHISRS and WAITRS If the system base clock when returning is different from the clock used immediately before entering wait mode a period until the clock supply oscillation stabilization time is generated automatically If the system base clock when returning is the high speed on chip oscillator clock oscillation is started when an interrupt request is generated If the system base clock is the XIN clock set pins P4_6 and P4_7 to XIN oscillation by a program to start oscillation before entering wait mode Depending on the clock to be used set appropriate values for oscillation stabilization time using bits CKSTO to CKST3 in the CKRSCR register It is unnecessary to generate a wait time by a program When returning from wait mode using the same clock as the one used immediately before entering the mode no oscillation stabilization time is generated RO1UH0050EJ0200 Rev 2 00 RENESAS Page 10
260. ctive high the TRCIOB output pin is set to high at compare match B and low at compare match A The setting values of bits PWMD to PWMB in TRCMR take precedence over those in registers TRCIORO and TRCIOR1 When the values set in the period and duty registers are the same the output value remains unchanged even if a compare match occurs RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 251 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 9 shows an Operation Example in PWM Mode High level output when TRCCNT register is cleared at compare match A Low level output at compare matches B C and D POLB bit 0 POLC bit 0 and POLD bit 0 in TRCCR2 register TRCCNT register value Counter cleared by TRCGRA register compare match TRCGRA register TRCGRB register TRCGRC register TRCGRD register 0000h 1 1 1 1 I TRCIOB i TRCIOC U TRCIOD e Low level output when TRCCNT register is cleared at compare match A High level output at compare matches B C and D POLB bit 1 POLC bit 1 and POLD bit 1 in TRCCR2 register TRCCNT register value Counter cleared by TRCGRA register compare match TRCGRA register TRCGRB register TRCGRC register TRCGRD register 0000h TRCIOB I 1 Li Li TRCIOC TRCIOD Figure 15 9 Operation Example in PWM Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 252 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC
261. cture 512 bytes Package type SP PTSP0014JA B PLSP0020JB A DD PRDP0014AC A PRDP0020AD A Classification N Operating ambient temperature 20 C to 85 C D Operating ambient temperature 40 C to 85 C ROM capacity 0 2 KB 1 4 KB 2 8 KB Number of pins 1 14 pins 2 20 pins R8C MXXA Group R8C Mx Series Memory type F Flash memory Renesas MCU Renesas semiconductor R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 6 of 426 R8C M11A Group R8C M12A Group 1 Overview 1 3 Block Diagram Figure 1 2 shows the Block Diagram UO ports Peripheral functions Timers Timer RJ2 16 bits x 1 Timer RB2 8 bits x 1 or 16 bits x 1 Timer RC 16 bits x 1 Watchdog timer 14 bits A D converter 10 bits x 6 channels Figure 1 2 Block Diagram UART Clock synchronous serial I O Clock asynchronous serial I O Comparator B R8C CPU core System clock generation circuit XIN XOUT High speed on chip oscillator Low speed on chip oscillator Voltage detection circuit Notes 1 ROM size varies with the product 2 RAM size varies with the product RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 7 of 426 R8C M11A Group R8C M12A Group 1 Overview 1 4 Pin Assignment Figures 1 3 and 1 4 show Pin Assignment Top View Table 1 6 lists the Pin Name Information by Pin Number P3_7 ADTRG TRJO TRCIOD SI C lt 4 P1_1 AN1 TRCIOA TRCTRGAIT
262. cute the block blank check command when the FST6 bit in the FST register is 1 erase suspended or the FST3 bit is 1 program suspended Figure 19 18 shows the Block Blank Check Flowchart Write the command code 25h Write DOh to any address in the block R Full status check a Completed FST7 Bit in FST register Figure 19 18 Block Blank Check Flowchart This command is intended for programmer manufacturers not for general users RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 355 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 7 Full Status Check If an error occurs bits FST4 to FSTS in the FST register are set to 1 indicating the occurrence of the error The execution result can be confirmed by checking these status bits full status check Table 19 9 lists the Errors and FST Register States Figure 19 19 shows the Full Status Check and Handling Procedures for Individual Errors Table 19 9 Errors and FST Register States FST Register States FST5 Bit FST4 Bit Command sequence error Error Occurrence Condition e When a command is not written correctly e When data other than valid data i e DOh or FFh is written as the second command of the block erase lock bit program read lock bit status or block blank check command 1 e The erase command is executed during erase suspend or the block blank check command is executed e The program lock bit program erase or block blank ch
263. cuted from the start address of the interrupt routine Note 1 Temporary registers cannot be used by the user we LC e y N uo WR Note 1 The length of the undefined state depends on the instruction queue buffer A read cycle occurs when the instruction queue buffer is ready to accept instructions Figure 11 3 Time Required for Executing Interrupt Sequence R01UH0050EJ0200 Rev 2 00 ztENESAS Page 124 of 426 May 18 2012 11 Interrupts R8C M11A Group R8C M12A Group 11 Interrupts 11 4 5 Interrupt Response Time Figure 11 4 shows the Interrupt Response Time The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed This time consists of two periods the first period ranges from when an interrupt request is generated until the currently executing instruction is completed a in Figure 11 4 and the second from when an interrupt request is acknowledged until the interrupt sequence is executed 20 cycles b Interrupt request Interrupt request is generated is acknowledged Instruction in Instruction Interrupt sequence i interrupt routine a 20 cycles b Interrupt response time a The period from when an interrupt request is generated until the currently executing instruction is completed The length of this time varies with the instruction being executed The DIVX instruction requires the longest time 30 cycles
264. cycles R CPU clock Lg IL Address internal el OFFFCh t OFFFEh L M address signal Notes 1 This applies to the hardware reset K OFFFDh Content of reset vector 2 When the width of a low level input to the RESET pin is fLOCO clock x 2 cycles or more the internal reset signal goes high and the RESET pin is set to high at the same time Figure 6 2 Reset Sequence RO1UH0050EJ0200 Rev 2 00 May 18 2012 stENESAS Page 42 of 426 R8C M11A Group R8C M12A Group 6 Resets 6 3 2 Hardware Reset The hardware reset is the reset that is caused by the RESET pin When a low level is input to the RESET pin under the condition that the power supply voltage meets the recommended operating conditions the CPU SFRs and I O ports are initialized See 3 2 Special Function Registers SFRs for the states of the SFRs after a reset and Tables 6 3 and 6 4 Pin States for the states of I O ports The internal RAM is not initialized If the RESET pin is set to low while writing to the internal RAM the RAM values will be undefined When the RESET pin is changed from low to high a program is executed starting at the address indicated by the reset vector The low speed on chip oscillator clock no division is automatically selected as the CPU clock after a reset Figure 6 3 shows the Hardware Reset Circuit Example Using External Power Supply Voltage Detection Circui
265. d In EW1 mode do not execute this command for any address where the rewrite control program is allocated When the RDYSTIE bit in the FMRO register is 1 flash ready status interrupt enabled a flash ready status interrupt is generated when auto programming is completed When the RDYSTIE bit in the FMRO register is 1 flash ready status interrupt enabled and the FMR20 bit in the FMR2 register is 1 suspend enabled a flash ready status interrupt is generated when the FMR21 bit is set to 1 suspend request and auto programming is suspended The result can be confirmed by reading the FST register in the interrupt routine Write the command code 40h Write data to the write address H Full status check Program completed FST7 Bit in FST register Figure 19 8 Program Flowchart Flash Ready Status Interrupt Disabled and Suspend Disabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 345 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory FMR20 1 Write the command code 40h 1 interrupt enabled Yes Access the flash memory FMR21 0 Write data to the write address Flag in CPU register Full status check i FST3 FST7 Bits in FST register Program completed FMR20 FMR21 Bits in FMR2 register Notes 1 The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other than the programming target area 2 td SR SUS is req
266. d By setting the general register to be an input capture register the value in the TRCCNT register on input edge detection of pins TRCIOA to TRCIOD is transferred to registers TRCGRA to TRCGRD This value is used to measure the period The detection edge can be selected to be a rising edge falling edge or two way edge Figure 15 7 shows an Example of Input Capture Operation The TRCCNT register is used for the free running operation and a two way edge is selected for the input capture input to the TRCIOA pin and a falling edge is selected for the input capture input to the TRCIOB pin TRCCNT register value TRCIOA TRCGRA register TRCIOB TRCGRB register Figure 15 7 Example of Input Capture Operation RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 249 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 8 shows an Example of Buffer Operation during Input Capture This example applies when the TRCGRA register is set as an input capture register and the TRCGRC register is set as a buffer register for the TRCGRA register In this example the TRCCNT register is used for the free running count operation and both rising and falling edges are selected for the input capture input to the TRCIOA pin Since buffer operation is set the value in the TRCCNT register is stored in the TRCGRA register by input capture A and the value that has been stored in the TRCGRA register is transferred to the TRCGRC register at the same ti
267. d one stop bit UOBRG output RE bit in U0C1 register RXDO Transfer clock Transmission is started when a transfer RI bit in clock is generated on the falling edge UOC1 register of the start bit UORIF bit in UOIR register The above diagram applies for the following settings e STPS bit in UOMR register 0 one stop bit PRYE bit in UOMR register 0 parity disabled 16 Serial Interface UARTO Stop bit From UARTO receive register to UORB i ies Ee gt 3 f1 Set to 0 by a program Figure 16 7 Receive Timing in Clock Asynchronous Serial UO Mode R01UH0050EJ0200 Rev 2 00 ztENESAS Page 294 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 2 2 Bit Rate In clock asynchronous serial I O mode the bit rate is obtained by dividing the frequency with the UOBRG register and further dividing it by 16 The value to be set in the UOBRG register is calculated as follows e When an internal clock is selected fj Value set in UOBRG register Bitrate x16 1 fj Frequency of UOBRG count source f1 f8 or f32 e When an external clock is selected fEXT Value set in UOBRG register Bitrate x16 1 fEXT Frequency of UOBRG count source external clock Table 16 8 Setting Example for Clock Asynchronous Serial UO Mode Internal Clock Selected 1200 81h System Clock 20 MHz System Clock 18 432 MHz 1 System Clock 8 MHz UOBRG Count Value Set Act
268. d by dividing the low speed on chip oscillator clock by any value from 1 no division to 256 The CPU clock is obtained by dividing the system clock by 1 no division 2 4 8 16 or 32 Also the peripheral function clock is obtained by dividing the system clock with the prescaler In addition fHOCO can be used as the peripheral function clock when the HOCOE bit in the OCOCR register is 1 high speed on chip oscillator on In this mode low power operation can be enabled by stopping the XIN clock and the high speed on chip oscillator and setting the FMR27 bit in the FMR2 register to 1 low current consumption read mode enabled Furthermore if wait mode is entered from this mode power consumption in wait mode can be reduced even further by setting the VCA2 register LPE bit to 1 low power consumption wait mode enabled For details on how to reduce power consumption see 10 5 Reducing Power Consumption RO1UHO050EJ0200 Rev 2 00 stENESAS Page 96 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 3 Wait Mode The watchdog timer is stopped when count source protection mode is disabled and the CPU clock is used The XIN clock and the high speed low speed on chip oscillator clock are not stopped so the peripheral functions that use these clocks continue operating The system clock can be stopped with WCKSTP bit in the CKSTPR register At this time the peripheral functions that use the system clock and a divided system
269. d value is 0 Port P3_3 direction bit 0 Input mode functions as an input port Port P3_4 direction bit 1 Output mode functions as an output port Port P3_5 direction bit Nothing is assigned The write value must be 0 The read value is 0 Port P3_7 direction bit 0 Input mode functions as an input port 1 Output mode functions as an output port The PD3 register is used to select whether I O ports are used as input or output Each bit in the PD3 register corresponds to individual ports 12 4 2 Port P3 Register P3 Address 000B1h Bit b7 b6 b5 b4 b3 b2 b1 b symool P87 Pas Pas rss After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P3_ 3 bit 0 Low level Port P3_4 bit 1 High level Port P3_5 bit Nothing is assigned The write value must be 0 The read value is 0 Port P3_7 bit 0 Low level 1 High level The P3 register is an I O port data register Data input to and output from external devices are accomplished by reading from and writing to the P3 register The P3 register consists of a port latch to retain output data and a circuit to read the pin states The value written to the port latch is output from the pins Each bit in the P3 register corresponds to individual ports RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 152 of 426 May 18 2012 R8C M11A Gr
270. dard Serial I O Mode Disabled Function for the case where the ID codes are Protect 19 3 2 2 Standard Serial I O Mode Disabled Function This function is used in standard serial I O mode When the stored ID codes are Protect in ASCII see Table 19 3 ID Code Reserved Words no communication with the serial programmer or the on chip debugging emulator is performed This prevents the flash memory from being read written or erased using the serial programmer or the on chip debugging emulator If the stored ID codes are set to Protect in ASCII when bits ROMCP1 to ROMCR in the OFS register are 01b ROM code protect enabled ROM code protection cannot be disabled using the serial programmer or the on chip debugging emulator This prevents the flash memory from being read written or erased using the serial programmer or the on chip debugging emulator RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 328 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 4 CPU Rewrite Mode In CPU rewrite mode the user ROM area can be rewritten by executing software commands from the CPU Therefore the user ROM area can be rewritten directly with the MCU mounted on a board without using a ROM programmer Software commands should be executed only for blocks in the user ROM area The MCU has a suspend function program suspend erase suspend which halts erase or program operation temporarily in CPU rewrite mode During suspend
271. data is output on the rising edge and receive data is input on the falling edge of the transfer clock Notes 1 The CLKO pin level is high when transfer is not performed 2 The CLKO pin level is low when transfer is not performed Figure 16 4 Transfer Clock Polarity 16 3 1 3 LSB First or MSB First Selection Figure 16 5 shows the Transfer Format The UFORM bit in the UOCO register can be used to select the transfer format UFORM bit in UOCO register 0 LSB first CLKO moo o GCI OCA CC GC OCA CO aoo o ON CA OD OLA OA EO e UFORM bit in UOCO register 1 MSB first CLKO noo or OA OA ZO EECH ECH RG 7 5 4 3 2 1 DO me or bs fos oe fos oe 7 Note 1 The above applies when the CKPOL bit in the UOCO register 0 transmit data is output on the falling edge and receive data is input on the rising edge of the transfer clock Figure 16 5 Transfer Format RO1UHO050EJ0200 Rev 2 00 RENESAS Page 289 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 1 4 Continuous Receive Mode Continuous receive mode is selected by setting the UORRM bit in the UOC1 register to 1 continuous receive mode enabled In this mode reading the UORB register sets the TI bit in the UOC1 register to 0 data present in the UOTB register When the UORRM bit is 1 do not write dummy data to the UOTB register by a program 16 3 1 5 Dealing with Communication Errors If communicati
272. derflow signal TRCIOA o RCCPSEL1 to SH D D 16 bit counter gt Q e Timer RJ2 TIPF1 to TIPFO RCCPSELO GO D 010b 01b fi Q 10b TIPF1 to TIPFO 8 p 2 P other than 00b TMOD2 to TMODO Ro o One way 011b or 100b Digital edge two Counter filter FO way edge Polarity control circuit g2 selection switching interrupt Measurement complete signal TRJIOSEL 1 TEDGPL TEDGSEL gt qo C TMOD2 to TMODO 001b TRJIOSEL 0 p TORCR TEDGSEL 1 9 24 O Toggle flip flop TEDGSEL 0 He TRJO O lt Write to TRJMR register pin Write 1 to TSTOP VCOUT1 TRJIO pin O TRJIOSEL Bit in PINSR register TSTART TSTOP Bits in TRUCR register TEDGSEL TOPCR TIPFO to TIPF1 TIOGTO to TIOGT1 Bits in TRJIOC register TMODO to TMOD2 TCKO to TCK2 TCKCUT Bits in TRJMR register TEDGPL Bit in TRJMR register enabled in event counter mode RCCPSELO to RCCPSEL2 Bits in TRJISR register TRCIOA TRCIOB TRCIOC TRCIOD Output signal pins for timer RC VCOUT1 When TRJIOSEL 1 VCOUT1 is set to the input for timer RJ2 instead of the TRJIO input function In event counter mode VCOUT1 is set for the count source In pulse width period measurement mode the width period of VCOUT1 can be measured Figure 13 1 Timer RJ2 Block Diagram 13 2 I O Pins Table 13 2 lists the Timer RJ2 Pin Configuration Table 13 2 Timer RJ2 Pin Configuration Pin Name Assigned Pin Function P3_4 P4_7 Event counter mode coun
273. digital filter is disabled RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 370 of 426 R8C M11A Group R8C M12A Group Table 20 5 Flash Memory Program ROM Electrical Characteristics a Standard Parameter Condition Typ Program erase endurance 2 10 000 3 times Byte programming time 80 us program erase endurance lt 1 000 times Byte programming time 160 us program erase endurance gt 1 000 times Block erase time 0 12 s ta SR SUS Transition time to suspend 0 25 CPU clock ms x 3 cycles Time from suspend until erase restart 30 CPU clock us x 1 cycle td CMDRST Time from when command is forcibly 30 CPU clock us READY terminated until reading is enabled x 1 cycle Program erase voltage 1 8 5 5 V Read voltage 1 8 5 5 V Program erase temperature 0 60 C Data hold time 7 Ambient temperature 85 C 10 years Notes Vcc 2 7 V to 5 5 V and Topr 0 C to 60 C unless otherwise specified 2 Definition of program erase endurance The number of program erase cycles is defined on a per block basis If the number of cycles is 10 000 each block can be erased 10 000 times For example if 1 024 cycles of 1 byte write are performed to different addresses in 1 Kbyte of block A and then the block is erased the number of cycles is counted as one
274. duet deeed ugeduet TROCNT vecccccccccsssecsecsesscsecersecsessecsessrsessecersatsesseseesenseceereneess TRCCA1 TRCCR2 TRCDF TRCGRA K TRCGRB SS Se EE EE Oe TRCIER Se SE M EIERE Ee MSTGR E 27 TRCIOR1 TRCOER TRCOPR RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 425 of 426 May 18 2012 R8C M11A Group R8C M12A Group Index pia ta ungeet EEE vecwarduere e geet td Eder GEAR veer kg 185 TAJISR EE 184 OSTEN 184 U JOB RG EE 281 WO GO WEE 282 IR Tale NEE 283 MOURA EE 285 UI E WEE 280 VORB WE 284 MOTB es vevesereesesssceertadsnzAvavateneceediaeePA Ea R TE EAS 281 V VOAZ EE 53 NM GAG ergeet D eg ege 52 VIR 54 AYATA OT ARONI LIN AE EEA RTA ET EIE 55 VAN 56 w WCBIINTR au cccccceceseceesscccessseccesseeccesseeceesaeeccssseeccssatecesseees 319 WGOB IN TR EE 320 e dE EE 318 MER E E eege e Eege Seege ee g 65 ADS UE G EEE corer reece reece 66 VIER US EE 65 DA ESA E ses eevee eeeedeidt Acc SES eeE 65 RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 426 of 426 May 18 2012 REVISION HISTORY R8C M11A Group R8C M12A Group Users Manual Hardware Description Summary Jan 29 2010 First Edition issued Jun 14 2010 All pages Revised Jun 29 2010 180 13 4 1 next count source gt next system clock f 231 15 2 11 revised 232 15 2 12 revised 233 15 2 13 Note 1 revised Jul 06 2010 400 401 Appendix Figures 2 3 and 2 4 Connection line between E8
275. e Table 10 4 lists the Interrupts Used to Return from Stop Mode and Usage Conditions Table 10 4 Interrupts Used to Return from Stop Mode and Usage Conditions Interrupt Usage Condition INTO to INT3 interrupts Usable without a filter Key input interrupt Usable Timer RJ2 interrupt Usable when an external pulse is counted without a filter in event counter mode Timer RB2 interrupt Usable when timer RJ2 is used without a filter in event counter mode and timer RJ2 underflow is selected as the count source for timer RB2 Serial interface interrupt Usable with an external clock supplied Voltage monitor 1 interrupt Usable in digital filter disabled mode when the VW1C1 bit in the VW1C register is 1 Comparator B1 interrupt Usable without a filter Comparator B3 interrupt Usable without a filter Figure 10 4 shows the Sequence from Stop Mode to Interrupt Routine Execution When a peripheral function interrupt is used to return from stop mode the following items must be set before setting the STPM bit in the CKSTPR register to 1 all clocks are stopped stop mode 1 Set the interrupt priority level in bits ILVLi0 to ILVLil or bits ILVLi4 to ILVLi5 in the interrupt priority level registers for the peripheral function interrupts that are used to return from stop mode Also set 00b level O interrupt disabled in bits ILVLil to ILVLi0 or bits ILVLi5 to ILVLi4 for the peripheral function interrupts that are not t
276. e Product Part Number Structure Table 1 5 Group Name R8C M11A Group Product List Part No R5F2M110ANSP Internal ROM Capacity Current of May 2012 Internal RAM Remarks Program ROM 2 Kbytes Data Flash Kbyte x 2 Capacity Package Type 256 bytes PTSP0014JA B N version R5F2M111ANSP 4 Kbytes Kbyte x 2 384 bytes R5F2M112ANSP 8 Kbytes Kbyte x 2 512 bytes R5F2M110ANDD 2 Kbytes Kbyte x 2 256 bytes PRDP0014AC A R5F2M111ANDD 4 Kbytes Kbyte x 2 384 bytes R5F2M112ANDD 8 Kbytes Kbyte x 2 512 bytes R5F2M110ADSP 2 Kbytes Kbyte x 2 256 bytes PTSP0014JA B D version R5F2M111ADSP 4 Kbytes Kbyte x 2 384 bytes R5F2M112ADSP 8 Kbytes Kbyte x 2 512 bytes R8C M12A Group Part No R5 F 2MXXXANSP Ess SS Figure 1 1 R5F2M120ANSP 2 Kbytes Kbyte x 2 256 bytes PLSP0020JB A N version R5F2M121ANSP 4 Kbytes Kbyte x 2 384 bytes R5F2M122ANSP 8 Kbytes Kbyte x 2 512 bytes R5F2M120ANDD 2 Kbytes Kbyte x 2 256 bytes PRDP0020AD A R5F2M121ANDD 4 Kbytes Kbyte x 2 384 bytes R5F2M122ANDD 8 Kbytes Kbyte x 2 512 bytes R5F2M120ADSP 2 Kbytes Kbyte x 2 256 bytes PLSP0020JB A D version R5F2M121ADSP 4 Kbytes Kbyte x 2 384 bytes R5F2M122ADSP 8 Kbytes Kbyte x 2 Product Part Number Stru
277. e RO through which an capacitor C is fully charged within T is obtained as follows T 0 8 us R 10 KQO C 6 0 pF X 0 1 and Y 1024 Hence 0 8 x 1076 6 0 x 10 712 e jn Hl 1024 RO 10 x 10 4 4 x 103 Thus the maximum output impedance of a sensor circuit for an accuracy error of 0 1 LSB or less is 4 4 kQ maximum RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 404 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes Sensor equivalent circuit RO Figure 21 8 Analog Input Pin and External Sensor Equivalent Circuit 21 11 3 Register Setting e Registers ADMOD and ADINSEL must be written only when A D conversion is stopped e Do not enter stop mode during A D conversion e Do not enter wait mode during A D conversion while the WCKSTP bit in the CKSTPR register is 1 system clock is stopped in wait mode e Do not set the FMSTP bit in the FMRO register to 1 flash memory is stopped or the FMR27 bit in the FMR2 register to 1 low current consumption read mode enabled during A D conversion e During A D conversion if the ADST bit in the ADCONDO register is set to 0 A D conversion stops by a program to forcibly terminate the conversion the conversion result from the A D converter will be undefined and no interrupt will be generated The value of the ADi register i 0 or 1 which is not engaged in A D conversion may also be undefined If the ADST bit is set to 0 by a program do not use any of th
278. e When a watchdog timer reset occurs RO1UHO050EJ0200 Rev 2 00 stENESAS Page 30 of 426 May 18 2012 R8C M11A Group R8C M12A Group 5 System Control 5 2 6 Address OFFDBh Bit b7 b6 Option Function Select Register 2 OFS2 b5 b4 b3 b2 b1 bO MSN _ WOTACST WOTRCSO WOTUFST WOTUFSO After Reset User Setting Value 1 Bit Name Function bO WDTUFSO Watchdog timer underflow period b1 bO R W b1 WDTUFST setting bits GE R W 0 1 OFFFh 10 1FFFh 11 3FFFh b2 WDTRCSO Watchdog timer refresh acceptance 1 63 2 R W b3 WDTRCS1 period setting bits 0 0 25 R W 01 50 10 75 11 100 b4 Reserved Set to 1 R W b5 MSTINI MSTCR register initial value select bit 0 MSTCR register is set to 00h after reset R W 1 MSTCR register is set to 77h after reset b6 Reserved Set to 1 R W b7 Note 1 The OFS2 register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS2 register Erasure of the block including the OFS2 register causes the OFS2 register to be set to FFh When blank products are shipped the OFS2 register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS2 register is the value programmed by the user For an example of the OFS2 register settings see 5 6 1 Option Funct
279. e capacity control bit Port P1_5 drive capacity control bit Reserved Set to 0 Note 1 Both H and L output are set to high drive capacity The DRRI1 register is used to select the drive capacity of the output transistors low or high when P1 is set to output an output port or a peripheral function output pin The drive capacity of the corresponding output transistors is high when the DRR1_j bit G 2 to 5 in the DRRI1 register is set to 1 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 145 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 5 Open Drain Control Register 1 POD1 Address 000C1h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol After Reset 0 0 0 0 0 0 0 0 Bit Name Function Port P1_0 open drain control bit 0 Not open drain Port P1_1 open drain control bit 1 Open drain Port P1_2 open drain control bit Port P1_3 open drain control bit Port P1_4 open drain control bit Port P1_5 open drain control bit Port P1_6 open drain control bit Port P1_7 open drain control bit The POD register is used to select whether the output type is CMOS output or N channel open drain output These settings are enabled when the peripheral function output or output port function is selected The corresponding pins are set to N channel open drain output when the POD1_j bit j 0 to 7 is set to 1 open drain and CMOS output when the bit is set to 0 not open drain
280. e enabled Set the FMSTP bit to 1 flash memory is stopped when the FST7 bit in the FST register is 1 ready 3 The CMDRST bit can be set when the FMR01 bit is 1 CPU rewrite mode enabled and the FST7 bit in the FST register is 0 busy 4 Set the FMRO1 bit to O CPU rewrite mode disabled only when the RDYSTI bit in the FST register is 0 no flash ready status interrupt requested and the BSYAEI bit is 0 no flash access error interrupt requested 5 This bit is set to 0 when the FMR01 bit is O CPU rewrite mode disabled FMR01 Bit CPU rewrite mode select bit When the FMRO1 bit is set to 1 CPU rewrite mode enabled the MCU is made ready to accept software commands FMRO2 Bit EW1 mode select bit When the FMRO2 bit is set to 1 EW1 mode EW1 mode is selected FMSTP Bit Flash memory stop bit This bit is used to initialize the control circuits and to reduce the amount of current consumed in the flash memory When the FMSTP bit is set to 1 flash memory is stopped the flash memory cannot be accessed Therefore only write to the FMSTP bit by a program transferred to the RAM To reduce the power consumption further in high speed on chip oscillator mode and low speed on chip oscillator mode XIN clock is stopped set the FMSTP bit to 1 flash memory is stopped Do not set the FMSTP bit in the FMRO register to 1 flash memory is stopped during A D conversion Do not set the FMR27 bit to 1 while the FMSTP bit flash memory stop
281. e function Table 15 13 TRCIOC Pin Settings Register TRCOER TRCIOR1 Bit Setting value X 0or 1 IOC2 IOC UO port Function PWM mode waveform output Timer mode waveform output output compare function Timer mode input capture function Table 15 14 TRCIOD Pin Settings Register TRCOER TRCIOR1 Bit Setting value X 0or 1 IOD2 1OD1 I O port Function PWM mode waveform output Timer mode waveform output output compare function Timer mode input capture function I O port RO1UH0050EJ0200 Rev 2 00 May 18 2012 Page 246 of 426 R8C M11A Group R8C M12A Group 15 Timer RC 15 3 1 Timer Mode The TRCCNT register performs free running or period count operations Immediately after a reset the TRCCNT register functions as a free running counter When the CTS bit in the TRCMR register to set to 1 count is started count operation is started When the TRCCNT register overflows from FFFFh to 0000h the OVF bit in the TRCSR register is set to 1 and an interrupt request is generated if the OVIE bit in the TRCIER register is 1 interrupt request FOVI by OVF flag is enabled Figure 15 2 shows an Example of Free Running Counter Operation TRCCNT register value Flag clearing by software CTS Bit in TRCMR register OVF Bit in TRCSR register Figure 15 2 Example of Free Running
282. e of the transfer clock Transfer format select bit LSB first MSB first Notes 1 If the UOBRG count source is changed set the UOBRG register again 2 The DFE bit is enabled in clock asynchronous serial I O mode In clock synchronous serial I O mode set this bit to 0 digital filter disabled 3 The CKPOL bit is enabled in clock synchronous serial I O mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 282 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 2 5 UARTO Transmit Receive Control Register 1 U0C1 Address 00085h Bit b7 b6 b5 b4 b3 b2 b1 b Smo UoRRMT UoRS TAI RE 1 Te After Reset 0 0 0 0 0 0 1 0 Bit Name Function Transmit enable bit Transmission disabled Transmission enabled Transmit buffer empty flag Data present in the UOTB register The UOTB register empty Receive enable bit Reception disabled Reception enabled Receive complete flag 1 The UORB register empty Data present in the UORB register UARTO transmit interrupt source Transmit buffer is empty TI 1 select bit Transmission is completed TXEPT 1 UARTO continuous receive mode Continuous receive mode disabled enable bit 2 1 Continuous receive mode enabled Reserved Set to 0 Notes 1 The RI bit is set to when the UORBH register is read 2 In clock asynchronous I O mode set the UORRM bit to 0 continuous receive mode
283. e registers Refer to 15 5 5 Buffer Operation TRCIOB Timing Register Setting Register Function j A B C or D BUFEA BUFEB Bits in TRCMR register RO1UH0050EJ0200 Rev 2 00 RENESAS Page 233 of 426 May 18 2012 Table 15 7 Register R8C M11A Group R8C M12A Group Functions of TRCGRh Register in PWM Mode Setting Register Function General register Set the PWM period 15 Timer RC PWM Output Pin General register Set the PWM output change point TRCIOB BUFEA 0 BUFEB 0 General register Set the PWM output change point TRCIOC TRCIOD BUFEA 1 Buffer register Set the next PWM period Refer to 15 5 5 Buffer Operation Timing BUFEB 1 h A B C or D BUFEA BUFEB Bits in TRCMR register Note Buffer register Set the next PWM output change point Refer to 15 5 5 Buffer Operation Timing TRCIOB 1 The output level does not change even when a compare match occurs if the TRCGRA register value PWM period is the same as the TRCGRB TRCGRC or TRCGRD register value May 18 2012 Table 15 8 Functions of TRCGRj Register in PWM2 Mode Register Setting Register Function PWM2 Output Pin TRCGRA General register Set the PWM period TRCIOB pin TRCGRB 1 General register Set the PWM output change point TRCGRC 1 BUFEA 0 General register Set the PWM output change point wait time a
284. e time The pulse output level is also initialized Use the MOV instruction to set the TRJCR register in pulse width measurement mode and pulse period measurement mode To avoid changing TEDGF and TUNDF at this time write 1 to these bits TSTART Bit Timer RJ count start bit Count operation is started by writing 1 to the TSTART bit and stopped by writing 0 When the TSTART bit is set to 1 count is started the TCSTF bit is set to 1 count is in progress in synchronization with the count source Also after 0 is written to the TSTART bit the TCSTF bit is set to 0 count is stopped in synchronization with the count source For details see 13 5 Notes on Timer RJ2 2 TCSTF Bit Timer RJ count status flag Conditions for setting to 0 e When 0 is written to the TSTART bit the TCSTF bit is set to 0 in synchronization with the count source e When is written to the TSTOP bit Condition for setting to 1 e When is written to the TSTART bit the TCSTF bit is set to 1 in synchronization with the count source TEDGF Bit Active edge judgement flag Condition for setting to 0 e When 0 is written to this bit by a program Conditions for setting to 1 e When the measurement of the active width of the external input TRJIO is completed in pulse width measurement mode e The set edge of the external input TRJIO is input in pulse period measurement mode TUNDF Bit Timer RJ underflow flag Condition for setting to 0 e
285. e values of the ADi register e When using the A D converter it is recommended that the average of the conversion results be taken RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 405 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 12 Notes on Flash Memory 21 12 1 ID Code Area Setting Example The ID code area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program The following shows a setting example To set 55h in all of the ID code area org OOFFDCH lword dummy 55000000h UND lword dummy 55000000h INTO lword dummy BREAK lword dummy 55000000h ADDRESS MATCH lword dummy 55000000h SET SINGLE STEP lword dummy 55000000h WDT lword dummy 55000000h RESERVE lword dummy 55000000h RESERVE Programming formats vary depending on the compiler Check the compiler manual RO1UH0050EJ0200 Rev 2 00 RENESAS Page 406 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 12 2 CPU Rewrite Mode 21 12 2 1 Prohibited Instructions The following instructions cannot be used while the program ROM area is being rewritten in EWO mode because they reference data in the flash memory UND INTO and BRK 21 12 2 2 Interrupts Tables 21 1 and 21 2 list the Interrupt Handling during CPU Rewrite Operation Table 21 1 Interrupt Handling during CPU Rewrite Operation EWO Mode Data Flash Program ROM Interru
286. e width measurement mode and pulse period measurement mode TRJ is a 16 bit register The write value is written to the reload register and the read value is read from the counter The states of the reload register and the counter are changed depending on the TSTART bit in the TRJCR register For details see 13 4 1 Reload Register and Counter Rewrite Operation RO1UHO0050EJ0200 Rev 2 00 RENESAS Page 180 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 3 2 Timer RJ Control Register TRJCR Address 000DAh Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo ONF TIET STOP TCSTF TSTART After Reset 0 0 0 0 0 0 0 0 Bit Name Function TSTART Timer RJ count start bit 1 0 Count is stopped 1 Count is started TCSTF Timer RJ count status flag 1 0 Count is stopped 1 Count is in progress TSTOP Timer RJ count forced stop bit 2 When 1 is written to this bit the count is forcibly stopped The read value is 0 Nothing is assigned The write value must be 0 The read value is 0 Active edge judgement flag 0 No active edge received 1 Active edge received Timer RJ underflow flag 0 No underflow 1 Underflow Nothing is assigned The write value must be 0 The read value is 0 Notes 1 For notes on using bits TSTART and TCSTF see 13 5 Notes on Timer RJ2 2 2 When 1 count is forcibly stopped is written to the TSTOP bit bits TSTART and TCSTF are initialized at the sam
287. eading the value sets the ADF bit to 0 no interrupt requested 4 The ADST bit remains at 1 A D conversion starts during A D conversion When conversion completes the ADST bit is automatically set to 0 A D conversion stops and the A D converter enters the standby state When the ADST bit is set to 0 during A D conversion A D conversion is stopped and the A D converter enters the standby state Set to 1 by a program Set to 1 by a program ADST bit in ADCONDO register Set to 0 by ADF bit in a program ADICSR register Set to 0 by a program Channel 0 AN0 in operation Standby for convers 1 1 1 1 1 1 on i 1 1 1 Channel 1 AN1 in operation Channel 2 AN2 in operation Channel 3 AN3 in operation Channel 4 AN4 in operation Channel 7 AN7 in operation ADO register AD1 register A D conversion regult 1 Figure 17 4 Operation Example in One Shot Mode When Channel 1 is Selected R01UH0050EJ0200 Rev 2 00 RENESAS Page 309 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 3 3 Repeat Mode Figure 17 5 shows an Operation Example in Repeat Mode When Channel is Selected In repeat mode A D conversions of an analog input are performed for the specified single channel repeatedly as follows 1 When the ADST bit in the ADCONDO register is set to 1 A D conversion starts by software trigger timer RC trigger or external trigger inpu
288. eaeeeeaaaeeseeeeseaeesecieeesiaeeeeees 414 Appendix 1 Package DIMENSIONS 415 Appendix 2 Connection Examples between Serial Programmer and On Chip Debugging Emulator 417 Appendix 3 Oscillation Evaluation Circuit Example cccecceeeeeeeeeeeeeeceeeeeeeeeeeseaeeeseaeeeseaaeeeseeeeessaeeeteeees 421 Appendix 4 Comparison between R8C M12A Group and R8C M13B Group ssssssesssesssesiessrrssrrresrsssne 422 MINOX EE 425 SFR Page Reference Address Register Name Address Register Name 00000h 00040 errupt Priority Level Register 0 00001h 00041 00002h 00042 errupt Priority Level Register 2 00003h 00043 errupt Priority Level Register 3 00004h 00044 errupt Priority Level Register 4 00005h 00045 errupt Priority Level Register 5 00006h 00046 errupt Priority Level Register 6 00007h 00047 errupt Priority Level Register 7 00008h 00048 errupt Priority Level Register 8 00009h 00049h errupt Priority Level Register 9 0000Ah 0004Ah errupt Priority Level Register A 0000Bh 0004Bh errupt Priority Level Register B 0000Ch 0004Ch errupt Priority Level Register C 0000Dh 0004Dh errupt Priority Level Register D 0000Eh 0004Eh errupt Priority Level Register E 0000Fh 0004Fh 00010h Processor Mode Register 0 00050h errupt Monitor Flag Register 0 00011h 00051h errupt Monitor Flag Register 1 00012h Module Standby Control Register 00052h errupt Monitor Flag Register 2 00013h Protect Register 00053h External Interrupt Flag Register 00014h 00054 00
289. eck command is executed during program suspend e The program lock bit program erase or block blank check command is executed to the block during suspend e The lock bit program or read lock bit status commands are executed to the data flash Erase error When the block erase command is executed and auto erase does not complete normally Blank check error When the block blank check command is executed and data other than the blank data FFh is read Program error When the program command is executed and auto programming does not complete normally Lock bit program error Note When the lock bit command is executed but the lock bit is not set to 0 locked 1 When FFh is written as the second command of these commands the MCU enters read array mode At the same time the command code written as the first command becomes invalid RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 356 of 426 R8C M11A Group R8C M12A Group 19 Flash Memory Command sequence error Execute the clear status register command Set bits FST4 through FST5 to 0 Check if the command was correctly input Re execute the command i Command sequence Erase error blank check error N error Execute the clear status register command Set bits FST4 through FST5 to 0 Is the lock bit disabled Set FMR13 bit to 1 Yes The erase target block cannot be used Erase error blank check error
290. ecommended by the oscillator manufacturer If the manufacturer specifies that a feedback resistor be added to the chip externally insert a feedback resistor between XIN and XOUT following the instructions Figure 9 3 XIN Clock Circuit Connection Examples RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 85 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 3 2 High Speed On Chip Oscillator Clock The clock generated by the high speed on chip oscillator is used as the clock source for the CPU clock and the peripheral function clock After the HOCOE bit in the OCOCR register is set to 1 high speed on chip oscillator on and the wait time for oscillation stabilization has elapsed when the HSCKSEL bit in the SCKCR register is set to 1 high speed on chip oscillator clock and the SCKSEL bit in the CKSTPR register is set to 1 fHSCK the high speed on chip oscillator clock is the system base clock fBASE Frequency adjustment data is stored in registers FRV1 FRV2 FR18S0 and FR18S1 To adjust the frequency of the high speed on chip oscillator clock to 18 432 MHz transfer the adjustment values in registers FR18SO and FR18S1 to registers FRV1 and FRV2 respectively before use This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0 when the serial interface is used in UART mode See Table 16 8 Setting Example for Clock Asynchronous Serial I O Mode Internal Clock Selected 9 3 3 Low
291. ection level Vdet1_9 2 When Vcc decreases Voltage detection level Vdet1_B 2 When Vcc decreases Voltage detection level Vdet1_D 2 When Vcc decreases Voltage detection level Vdet1_F 2 When Vcc decreases Hysteresis width at the rising of Vcc in voltage detection 1 circuit Vdet1_1 to Vdet1_5 selected Vdet1_7 to Vdet1_F selected lt lt lt lt lt lt lt lt lt Voltage detection 1 circuit response time 3 When Vcc decreases from 5 V to Vdet1_0 0 1 V Self power consumption in voltage detection circuit VC1E 1 Vcc 5 0 V Wait time until voltage detection circuit operation starts 4 1 The measurement condition is Vcc 1 8 V to 5 5 V and Topr 20 C to 85 C N version 40 C to 85 C D version 2 Select the voltage detection level with bits VD1S1 to VD1S3 in the VD1LS register 3 The response time is from when the voltage passes Vdet1 until the voltage monitor 1 interrupt request is generated 4 The wait time is necessary for the voltage detection circuit to operate when the VC1E bit in the VCA2 register is set to 0 and then 1 RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 373 of 426 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 9 Power On Reset Circuit 2 Sandar SE E Min Max a a eaae oP SE 1 The measurement condition is Topr 20 C to 85 C N vers
292. eecneceseeseeeeceaeeeeceseceaecaessaesaecnecssecascseeseseaseaessaeeneenaes 134 11 9 Notes on Interrupts EE 135 11 9 1 Reading Address QOQQOOW s sssc sccssceuscoecesiocs neriie tesgeeveesseduecs se sucess scavesdvtest REESEN EES 135 DD SP Setting EE EE AE IS Sg oe ihe es ee ens acco EE 135 11 9 3 External Interrupt and Key Input Interrupt 20000 eeeeereeeeecseeseecaeceaecnecseeeeeeesseesaeseaseseseaeeaeeeaes 135 11 9 4 Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN 00 0 ee eeeeeeeeeeeee 136 11 9 5 INTi Input Filter i 0 to 3 When Returning from Wait Mode or Stop Mode to Standard Mode 137 11 9 6 Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions ccccece8 138 11 9 7 Changing Interrupt Priority Levels and Flag Registers cece eeeeceeeeeeeeseeeeecaeecaeceaeaeceesseeneeeens 139 120 VO PONS minn EE 140 12 1 Overview reese dereen Enders copeblesacsdepensunag e a E a a Steels 140 12 2 Reading of Port Input Level o ccccccssscscssscccscasussccettesgnnesssbccovessspovecovsnesscasnesaenaeonnvenapetscesasesedensneessavensoveneevans 142 12 2 1 Port I O Function Control Register PINSR A 142 12 3 LN EE 143 123 1 Port Pl Direction Register PDI ZE ENEE e SEELEN 144 12 3 2 Rore PERES GA E 144 12 3 3 Pull Up Control Register 1 PURI oe cece eseceseeeeceeceseeeeeeeeeaeeseecsecaaecaecsaesaeeeeceeeseseaesaseasesaeeaeenaes 145 12 3 4 Drive Capacity Control Regist
293. egister To set one of the following bits to 0 first write 1 and then 0 immediately Interrupts must be disabled between writing and then writing 0 The FMR16 or FMR17 bit in the FMR1 register 21 12 2 4 Rewriting User ROM Area When EWO mode is used and the supply voltage falls while rewriting a block where a rewrite control program is stored the rewrite control program is not be rewritten correctly As a result it may not be possible to rewrite the flash memory afterwards Use standard serial I O mode to rewrite this block 21 12 2 5 Programming Do not perform even a single additional write to an already programmed address 21 12 2 6 Entering Wait Mode or Stop Mode Do not enter wait mode or stop mode during suspend When the FST7 bit in the FST register is 0 busy while programming or erasing the flash memory do not enter wait mode or stop mode Do not set the FMR27 bit to 1 while the FMSTP bit flash memory stop bit in the FMRO register is 1 flash memory is stopped 21 12 2 7 Flash Memory Programming and Erase Voltages When performing a program erase operation use a VCC supply voltage in the range of 1 8 V to 5 5 V Do not perform a program erase operation at less than 1 8 V 21 12 2 8 Block Blank Check Do not execute a block blank check command during erase suspend R01UH0050EJ0200 Rev 2 00 zeENESAS Page 409 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 12 2 9 EW1 Mode When sett
294. egister is set to 0 count is stopped values are updated to the reload registers immediately after the registers are written However when the TSTART bit is 1 count is started the timing for updating the reload registers differs in each mode In the 8 bit timer with 8 bit prescaler after the TRBPRE register is written the TRBPRE register reload register is updated in synchronization with the count source Table 14 6 lists the Reload Register Update Timing for Registers TRBPR and TRBSC in 8 Bit Timer with 8 Bit Prescaler Table 14 7 lists the Reload Register Update Timing for Registers TRBPRE TRBPR and TRBSC in 16 Bit Timer Write to register TRBPRE register update signal Reload a o 5 a o e 03 2 Register select signal Write to register TRBPR register update signal Reload register Write to register TRBSC register update signal Figure 14 9 Configuration of Registers TRBPRE TRBPR and TRBSC RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 218 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 Table 14 6 Reload Register Update Timing for Registers TRBPR and TRBSC in 8 Bit Timer with 8 Bit Prescaler Operating Mode Timer mode Update Timing 1 TRBPR Register TRBSC Register Updated in synchronization with the prescaler underflow Programmable waveform generation mode TWRC 1 Updated immediately before the end of the secondary output period after the TRBPR register is w
295. egisters associated with the A D converter addresses 00098h to 0009Fh is disabled 4 When the MSTTRC bit is set to 1 standby access to the registers associated with timer RC addresses OOOE8h to OOOFCh is disabled 5 When the MSTUART bit is set to 1 standby access to the registers associated with UARTO addresses 00080h to 00088h is disabled When changing each standby bit to standby stop the corresponding peripheral function beforehand RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 27 of 426 May 18 2012 R8C M11A Group R8C M12A Group 5 System Control 5 2 3 Protect Register PRCR Address 00013h Bit b7 b6 b5 b4 b3 b2 b1 b Smo J Pros PROS PRCT PRCO After Reset 0 0 0 0 0 0 0 0 Bit Name Function Protect bit 0 Writing to registers EXCKCR OCOCR SCKCR PHISEL CKSTPR CKRSCR BAKCR FRV1 and FRV2 0 Disabled 1 Enabled 1 Protect bit 1 Writing to registers PMO and RISR 0 Disabled 1 Enabled 1 Nothing is assigned The write value must be 0 The read value is 0 Protect bit 3 Writing to registers VCA2 VD1LS VWOC and VW1C 0 Disabled 1 Enabled 1 Protect bit 4 Writing to the PINSR register 0 Disabled 1 Enabled 1 Nothing is assigned The write value must be 0 The read value is 0 Note 1 Once this bit is set to 1 writing remains enabled until it is set to 0 by a program 5 2 4 Hardware Reset Protect Register HRPR Address 00016h Bi
296. en the program stops Insert at least four NOP instructions after the instruction that sets the WAITM bit to 1 wait mode is entered or after the WAIT instruction e Program example to execute the WAIT instruction BCLR 1 FMRO CPU rewrite mode disabled BCLR 7 FMR2 Low current consumption read mode disabled FSET I Interrupt enabled WAIT Wait mode NOP NOP NOP NOP e Program example to set the WAITM bit to 1 BCLR 1 FMRO CPU rewrite mode disabled BCLR 7 FMR2 Low current consumption read mode disabled BSET 0 PRCR Writing to the SCKCR register enabled FCLR I Interrupt disabled BSET 5 SCKCR Wait mode NOP NOP NOP NOP BCLR 0 PRCR Writing to the SCKCR register disabled FSET I Interrupt enabled 10 6 2 Program Restrictions When Entering Stop Mode To enter stop mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before setting the STPM bit in the CKSTPR register to 1 all clocks are stopped stop mode The 4 bytes of instruction data following the instruction that sets the STPM bit to 1 are prefetched from the instruction queue and then the program stops Insert at least four NOP instructions following the JMP B instruction immediately after the instruction that sets the STPM bit to 1 e Program example to enter stop mode BCLR 1 FMRO CPU rewrite mode disabled BCLR 7 FMR2 Low current consumption read mode disabled BSET 0 PRCR Writing to CKSTPR register enabled
297. en to both the reload register and counter respectively When these registers are written during the count operation values are written to the reload register and then transferred to the counter at the next reload operation Figure 14 3 shows an Example of 8 Bit Timer with 8 Bit Prescaler Operation in Programmable Waveform Generation Mode Figure 14 4 shows an Example of 16 Bit Timer Operation in Programmable Waveform Generation Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 209 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 Set to 1 by a program TSTART bit in TRBCR register Count source Underflow signal from timer RB mot LJ Oh Timer RB secondary is reloaded Timer RB primary is reloaded i Interrupt request signal Li Set to 0 by a program TOPL bit in TRBIOC register 1 1 1 1 U Li Li 1 1 Set to 0 by a program i Li 1 1 1 I Waveform output is started Waveform output is inverted Waveform output is started TRBO pin output I The level of the initial output is Primary period Secondary period i Primary period the same as that of the inverted TRBPR TRBSC l TRBPR TOPL bit value fixed value output The above diagram applies under the following conditions TRBPRE register 01h TRBPR register 01h TRBSC register 02h e TOPL bit 0 TOCNT bit 0 waveform output in TRBIOC register e TCNT16 bit in TRBMR register 0 8 bit timer with 8 bit prescaler Figure
298. eption disabled 2 These error flags are invalid when bits SMD2 to SMDO in the UOMR register are set to 001b clock synchronous serial UO mode When these bits are read the values are undefined The UORB register must be read in 16 bit units Do not access this register in 8 bit units When this register is accessed as 16 bit units it is accessed twice in 8 bit units RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 284 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 2 7 UARTO Interrupt Flag and Enable Register UOIR Address 00088h Bit After Reset b 0 Bit Name 7 b6 b5 b4 b3 b2 b1 b0 symbol Uor 0R J ooe von E 0 0 0 0 0 0 0 Function Nothing is assigned The write value must be 0 The read value is 0 UARTO receive interrupt enable bit 0 Receive interrupt disabled 1 Receive interrupt enabled UARTO transmit interrupt enable bit 0 Transmit interrupt disabled 1 Transmit interrupt enabled Nothing is assigned The write value must be 0 The read value is 0 UARTO receive interrupt flag 0 No receive interrupt requested 1 Receive interrupt requested UARTO transmit interrupt flag 0 No transmit interrupt requested 1 Transmit interrupt requested UORIF Bit UARTO receive interrupt flag Condition for setting to 0 e When 0 is written to this bit after reading it as 1 Condition for setting to 1 e When the RI b
299. er 00h 2 01110111b 3 00013h Protect Register 00h 00014h 00015h 00016h Hardware Reset Protect Register 00017h 00018h 00019h 0001Ah 0001Bh 0001Ch 0001Dh 0001Eh 0001Fh 00020h External Clock Control Register EXCKCR 00021h High Speed Low Speed On Chip Oscillator Control Register OCOCR 00022h System Clock f Control Register SCKCR 00023h System Clock f Select Register PHISEL 00024h Clock Stop Control Register CKSTPR 00025h Clock Control Register When Returning from Modes CKRSCR 00026h Oscillation Stop Detection Register BAKCR 00027h 00028h 00029h 0002Ah 0002Bh 0002Ch 0002Dh 0002Eh 0002Fh 00030h Watchdog Timer Function Register 10000000b 4 00h 5 00031h Watchdog Timer Reset Register XXh 00032h Watchdog Timer Start Register XXh 00033h Watchdog Timer Control Register 01XXXXXXb 00034h Count Source Protection Mode Register 10000000b 4 00h 5 00035h Periodic Timer Interrupt Control Register 00h 00036h 00037h 00038h External Input Enable Register 00039h Notes 1 The blank areas are reserved No access is allowed of WP The MSTINI bit in the OFS2 register is 0 The MSTINI bit in the OFS2 register is 1 The CSPROINI bit in the OFS regis
300. er 1 DRR1 A 145 12 3 5 Open Drain Control Register 1 POD1 sssrinin seisnes reeeo enr nersini ins En e Eees 146 12 3 6 Port 1 Function Mapping Register 0 ODMI 1 146 12 3 7 Port 1 Function Mapping Register 1 PMH1 sesesssessssseessssesrssssrerrsresrsrenrerenresessenrssrerestenterenserrsseereseeresrs 147 12 3 8 Port 1 Function Mapping Expansion Register PMHIE sssessssessssssrssssresssresssrrererresesrsserresrnresensesreneeresre 148 1239 Pin Settings tor Port EE 149 12 4 POLE EE 151 124 1 Port P3 Direction Resister PDI ena e E E EEE A E EE AA E EEN 152 E242 Porta Resister P3 yiera rin a ae EEEE EEA EREE EA E EAEE EEE E E 152 12 4 3 Pull Up Control Register 3 PUR 153 12 4 4 Drive Capacity Control Register 3 DRR3 seesssesssrssssresrsresrsresserreseeresrsresreesrestrtenrertssentesrntestnserreseeresr 153 12 4 5 Open Drain Control Register 3 POD3 ssssesssssssssesrrsrsresrsreerssrssestssenrssrnresteresteserrenreetssentnsreserensesresrereer 154 12 4 6 Port 3 Function Mapping Register 0 ODMI 31 154 12 4 7 Port 3 Function Mapping Register 1 PMH3 sssesessessssssssessesrssrsserrsesrssensesreresresrerrnreenseerssreresrnsesresreresrt 155 12 4 8 Pin Settings for Port 3 tinere dee i ne E E inetd 156 12 5 POr EE 157 12 5 1 Port P4 Direction Register PD4 sesessessesssesssssesessesesseseseereeseeseeeseeseeesesressesseeesesresseeesesreeseeseeeseeseeeseeseenet 158 123 2 Port PA Register RA EEN 158 12 5 3 Pull Up Control Regis
301. er a reset is cleared the low speed on chip oscillator clock no division is used as the system clock 9 4 3 CPU Clock fs The CPU clock can be obtained by dividing the system clock by 1 no division 2 4 8 16 or 32 for CPU operation The frequency division ratio for the system clock is set by bits PHISSELO to PHISSEL2 in the SCKCR register After a reset is cleared the low speed on chip oscillator clock no division will be the CPU clock 9 4 4 Various Clocks Table 9 8 lists the Names and Descriptions of Various Clocks that can be generated in the clock generation circuit Table 9 8 Names and Descriptions of Various Clocks Clock Name Description Peripheral function clocks f1 to 128 Clocks for the peripheral functions These clocks are generated by dividing the system clock They are used in timer RJ2 timer RB2 timer RC UARTO or the A D converter The peripheral function clocks are stopped when wait mode is entered after the WCKSTP bit in the CKSTPR register is set to 1 system clock stopped in wait mode fHOCO is generated by the high speed on chip oscillator and oscillates when the HOCOE bit in the OCOCR register is set to 1 fHOCO is not stopped in wait mode fLOCO is generated by the low speed on chip oscillator and oscillates when the LOCODIS bit in the OCOCR register is set to 0 fLOCO is not stopped in wait mode fHSCK is selected from the XIN clock or high speed on chip oscillator clock us
302. er can be set to standby or active using the MSTAD bit in the MSTCR register Stop A D conversion before setting to module standby Register access is enabled by clearing the A D converter standby state For details see 5 System Control 21 11 2 Sensor Output Impedance during A D Conversion To perform A D conversion accurately charging of the internal capacitor C shown in Figure 21 8 must be completed within the period of time specified as T sampling time Let the output impedance of the sensor equivalent circuit be RO the internal resistance of the microcomputer be R the accuracy error of the A D converter be X and the resolution of A D converter be Y Y is 1024 in 10 bit mode SE VC is generally VC vin e C RO R And when t T VC VIN VIN vin 1 oe T e C RO R KIX ee rT In amp C R0 R Y T Ce In Y R Hence RO Figure 21 8 shows the Analog Input Pin and External Sensor Equivalent Circuit The user can obtain an impedance RO that makes the pin to pin voltage VC increase from 0 to VIN 0 1 1024 VIN within time T when the difference between VIN and VC becomes 0 1 LSB The value 0 1 1024 indicates a precondition for the calculation of RO when the degradation due to insufficient capacitor charge is suppressed to 0 1 LSB during A D conversion in 10 bit mode The actual error however is the absolute accuracy plus 0 1 LSB A D conversion clock 20 MHz T 0 8 us Output impedanc
303. ered after the IRTC bit is set to 1 the IRTC bit remains set to 1 and does not change e If multiple bits in the TRCIER register are set to 1 use the TRCSR register to determine the source of the interrupt request e The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged Set them to O within the interrupt routine Refer to 15 2 6 Timer RC Status Register TRCSR for the procedure for setting these bits to 0 Refer to 15 2 5 Timer RC Interrupt Enable Register TRCIER for details of the TRCIER register Refer to 11 4 Interrupt Control for details of the ILVL3 register and 11 3 2 Relocatable Vector Table for information on interrupt vectors RO1UH0050EJ0200 Rev 2 00 RENESAS Page 274 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 7 Notes on Timer RC 15 7 1 TRCCNT Register The following note applies when the CCLR bit in the TRCCR1 register is set to 1 TRCCNT counter is cleared by input capture compare match A e When writing a value to the TRCCNT register by a program while the CTS bit in the TRCMR register is set to 1 count is started ensure that the write timing does not coincide with when the TRCCNT register is set to 0000h e If the timing when the TRCCNT register is set to 0000h and is written coincide with each other the value is not be written and the TRCCNT register is set to 0000h If the TRCCNT register is written and read the value before this regis
304. errupt request signal is generated to the CPU In addition a pulse can be output from pins TRJIO and TRJO The output level is inverted each time an underflow occurs The pulse output from the TRJIO pin can be stopped by the TOPCR bit in the TRJIOC register Also the output level can be selected by the TEDGSEL bit in the TRJIOC register Figure 13 4 shows an Operation Example in Pulse Output Mode Write 0002h to TRJ register by a program Write 0004h to TRJ register by a program Count source TSTART bit in ra SE REN H TRJCR register 0004h TRJ register FFFFh 0002h Reload register FFFFh 0002h 0004h U I 1 1 1 I TEDGSEL bit in i TRJIOC register TOPCR bit in TRJIOC register U U TRJO pin output i U High i o TRJIO pin output 1 igh impedance state TRJIF bit in TRUIR register Set to 0 by a program Note 1 The port selected as the TRJIO function becomes high impedance Figure 13 4 Operation Example in Pulse Output Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 188 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 4 Event Counter Mode In this mode the counter is decremented by an external pulse signal input to the TRJIO pin Various periods for counting events can be set by bits TIOGTO to TIOGT1 in the TRJIOC register and the TRJISR register In addition the filter function for the TRJIO input can be specified by bits TIPFO to TIPF1 in the TRJIOC register Also the ou
305. es 1 flash memory 100 us max Flash memory is is stopped not activated Internal Power Stop mode Stabilization Time Flash memory Clock stabilization CPU clock Interrupt activation sequence time restart sequence sequence Interrupt request is generated Figure 10 4 Sequence from Stop Mode to Interrupt Routine Execution Remarks The total on the left amounts to the time from stop mode to execution of an interrupt routine R01UH0050EJ0200 Rev 2 00 stENESAS May 18 2012 Page 103 of 426 R8C M11A Group R8C M12A Group 10 Power Control 10 5 Reducing Power Consumption The following describes key points and processing methods for reducing power consumption They should be referred to when designing a system or creating a program 10 5 1 Voltage Detection Circuit When voltage monitor is not used set the VC1E bit in the VCA2 register to 0 voltage detection 1 circuit disabled When power on reset or voltage monitor 0 reset is not used set the VCOE bit in the VCA2 register to 0 voltage detection 0 circuit disabled 10 5 2 Ports Even after entering wait mode or stop mode the states of the I O ports are retained Current flows into the output ports in the active state Shoot through current flows into the input ports in the high impedance state Unnecessary ports should be set to input and fixed to a stable electric potential before entering wait mode or stop mode 10 5 3 Clocks Power
306. es 118 11 2 10 Address Match Interrupt Register i ATADRi1 1 0 OF 1 voce eeeeeeeceececeeeecsaeeeneeceeesaeceaeeceeseneeeeneee 119 11 2 11 Address Match Interrupt Enable Register i ATENi 1 0 or 1 woe eeceeeecseceeeeceeeeesaeceneecereeeneeeeneees 119 11 3 Interrupts and Interrupt Vectors orenera eeii E E EE EE E E E E a r ESTES 120 11 3 1 Fixed Vector Table E 120 DAC Relocatable Vector Table nn pinse Rai siete EES AEN 121 11 4 Interrupt Control asses cern derer eege 122 IAU Flag se seni s ce as Se ia ae BAI LE is hn i 122 11422 Registers IR RO 16 TRR3 NEE 122 11 4 3 Interrupt Priority Levels in ILVLi Register i 0 or 2 to E and IPL oe ceeceeeecneenseeneeneees 123 NF E SW Interrupt S quence EE 124 11 45 Interrupt Response KE 125 11 4 6 IPL Change When Interrupt Request is Acknowledged 0 0 eee esecsecesececsseeseceseeseceseeseeeeeeseesaeeneenaes 125 UN eet EE 126 11 4 8 Returning from Interrupt Routine oo eee ceseeeeceeeeeeeeeeeeeeeaecseecaecaaecaecsaesaecnsessesseeseseeseseseaseaaeeaes 128 H A8 Interrupt Bengelen 128 11 4 10 Interrupt Priority Level Selection Circuit eee cee ceseeeeceseeseceeceeeeseeeeeeeaeeseecaecaeecaecaaesaecessseensensees 129 11 5 On WEE 130 11 5 1 INTi Interpreten Ee EE 130 11 52 INTI Input Filter G OO 3 EE 131 11 6 Key Inp tInterr pt eeneg 132 11 7 Address Match Imterrtipts ue re tdi red Seed deed Gregor RnR ap e du iech E SaS 133 11 8 How to Determine Interrupt Sources oo cece csec
307. esceseceeeesessaecaaesaecaecsaesseseeeeaseneregs 86 9 4 COCKS EE 87 9 4 1 system Bas Clock BASE Ehe 87 9 4 2 SYSTEM Clock EE 87 9 4 3 PU Clock Cs ice A aiih se Rai ease eae EE 87 9 4 4 Various Clocks aoine GAMERA RHEE AIS EE EELER A EE aie 87 9 4 5 Presale EE 88 9 4 6 Procedure for Switching System Base Clock ooo eeee ee eeceseseececesecoeceseeseeseceeeeseseaeseaecaecsaesaeceeseseseeeeeeaes 88 9 5 Oscillation Stop Detection FUNGON 22e0et iere eet eee a aaee eE a are ase sonei ingosh 91 9 5 1 How to Use Oscillation Stop Detection Function sssesssseeessseesrsssesesterrsrestsresrerisrenssrenrerrnenrssenteensenteses 91 9 6 Notes on Clock Generation Circuit ceseisiereseecen iie eiee enk Eek ea iess as 92 9 6 1 Oscillation Stop Detection Function i e eee ceeese cee ceseeseeeceeseeeeceseeeeecaecsaesaecsacaecasceeesessaecaecnsesaeenaes 92 9 6 2 Oscillation Circuit Constants ee eset cosbes AEN AAA 92 10 Power Control cccvu csaie ig ech haan ie davies gege beatae 93 10 1 NEIEN Age egene saab Eed Eder 93 10 2 Standard Operating Mode is sscssssisvesctesctsadessasessusconascesycs ses ssebesesessbstesteebssviuatcysiostesbessceencssdesinet ssbasdstpessoansanes 95 10 2 1 High Speed Clock Mode s cc bcc cscessiesicssebvebet cea ctatved os datectetocestectea nadsteuscd suecnnetcdepevesientovocmavedesdenaievensdeeetenses 96 10 2 2 High Speed On Chip Oscillator Mode AAA 96 10 2 3 Low Speed On Chip Oscillator Mode AA 96 10 3 KE L
308. ess 00098h ES EEN AD1L Bit b7 b5 b4 b3 b2 b1 bO D SC EE er Reset Address 00099h ADOH 0009Bh AD1H Bit b15 b14 b13 b12 b11 b10 Symbol Ge After Reset Function b7 to b Lower 8 bits in the A D conversion result b8 Higher 2 bits in the A D conversion result b9 Nothing is assigned The write value must be 0 The read value is 0 ADi i 0 or 1 is a 16 bit read only register that stores the A D conversion results It is divided into ADiL lower and ADiH higher Table 17 4 lists the Correspondence between Analog Input Channels and ADi Register When the higher 6 bits in the ADiH register are read the value is 0 Access can be made in 8 bit or 16 bit units To read the ADi register as 8 bit units read the ADiL register first and then ADiH register When the ADi register is read as 16 bit units it is read twice in 8 bit units Table 17 4 Correspondence between Analog Input Channels and ADi Register Analog Input Channel A D Data Register that Channel Group 0 Channel Group 1 Channel Group 2 Stores ADGSEL1 to ADGSELO 00b ADGSEL1 to ADGSELO 01b ADGSEL1 to ADGSELO 10b Conversion Result ADO register AD1 register ADGSELO to ADGSEL1 Bits in ADINSEL register RO1UHO050EJ0200 Rev 2 00 RENESAS Page 302 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 2 2 A D Mode Register ADMOD Address 0009Ch Bit b7 b6 b5 b
309. essseseessecssevsseessesncnnsessonsesssonsssce coesnee risp Eear SSE TESS 32 5 3 ID Code Check Funct om ae a e a E E EE E a Lisuicbeontoasd E E E eS 33 5 4 Regsistet Access Protect FUMCtOM ee EENS dEEeEEh 33 5 5 Option Mee 34 5 6 Notes on System Control gek ie ei ah ER A E n R le Se 39 5 6 1 Option Function Select Area Setting Example 0 0 0 cece eceeceseeeeeeseeseeceecesesaecaeaeceeceseeeesseseeseseeeesenes 35 6 PROSOUS eege E EE EE EE EEN 36 6 1 OVOLVIEW eege sated ne Aenea suchen EES ee ee i ha ia me As 36 6 2 RES ISLELS Zieser ae ote BAR alee 37 6 2 1 Processor Mode Register 0 PMO rarse echdossnedecseosezevschensenndscucesenededhevsts s vebevetysvsensvocaateds 37 6 2 2 Reset Source Determination Register RSTFR eseescesscesseceeeeceeeeeneceneesaeceaeeceneesaeceaeecsueeeaaeeaeeeerees 38 6 2 3 Option Function Select Register 2 OFS2 oo e a a e aae EE E ES ES ESS 40 6 2 4 Option Function Select Register OFS oo cece cssesseceeceseessceseeeeceseeeeesseeeaecaecsaecsecsaecaeceaeeseseseeseeeseneeegs 41 6 3 le e EE 42 6 3 1 Reset UE 42 6 3 2 Hardware Resets cAc cs innit ee ERAS haat ak on eats el ee DEE ENK 43 6 3 3 Power RE 44 6 3 4 Voltage Monitor 0 Reser rn neoa eree ae E ESEE EE Sea NES S eTR ESSES oE IESIRE ORT NS 45 6 3 5 Watchdog Timer Resets nre enera E a A ste aoe a a a cee ae Meco ee 46 6 3 6 Software RESet ietie ersan na ea aE ria Sra O EEE ESES R Ear ae EEEa cave ESEE EEN Desse 46 6 3 7 Cold Start Up Wa
310. etO Detection by passing up or down through Vdet1 Detection voltage Selectable from 4 levels with the OFS register Selectable from 8 levels with the VD1LS register Monitor None The VW1C3 bit in the VW1C register Higher or lower than Vdet1 Process at voltage detection Reset Voltage monitor 0 reset Reset at VdetO gt VCC CPU operation is restarted at VCC gt VdetO None Interrupts None Voltage monitor 1 interrupt Interrupt request at Vdet1 gt VCC and or VCC gt Vdet1 Digital filter Switching enable disable Available Available Sampling time Division of fLOCO by n x 2 n 1 2 4 or 8 Division of fLOCO by n x 2 1 n 1 2 4 or 8 RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 49 of 426 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit Level Voltage detection selection 1 signal circuit 8 levels Level Voltage detection selection O signal circuit 4 levels Reference voltage VDSELO to VDSEL1 VCOE VC1E Bits in VCA2 register VD1S1 to VD1S3 Bits in VD1LS register VW1C3 Bit in VW1C register VDSELO to VDSEL1 Bits in OFS register Figure 7 1 Voltage Detection Circuit Block Diagram RO1UHO050EJ0200 Rev 2 00 stENESAS Page 50 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit Voltage monitor 0 reset generation circuit VWOF1 to VWOFO 00b Vol
311. ev 2 00 ztENESAS Page 391 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 5 5 INTI Input Filter i 0 to 3 When Returning from Wait Mode or Stop Mode to Standard Mode When a transition is made to wait mode or stop mode with the WCKSTP bit in the CKSTPR register set to 1 system clock stopped in wait mode while in use of the INTi input filter the INTi interrupt cannot be used to return to standard operating mode When the INTi interrupt is used to return set the WCKSTP bit to 1 and bits INTiF1 to INTiFO in the INTFO register to 00b no filter before a transition is made to wait mode or stop mode When the INTi input filter is used again select the sampling clock with bits INTiFO to INTiF1 to enable the INTiEN bit in the INTEN register Figure 21 2 shows the Register Setting Procedure When INTi Input Filter i 0 to 3 is Used Interrupt disabled 1 Rewrite registers PMLk PMHk k 1 3 or 4 and ISCRO if Set the INTIEN bit i 0 to 3 in the INTEN register to 0 i Set the bits INTIFO to INTiF1 i 0 to 3 in INTFO register Set the INTIEN bit i 0 to 3 in the INTEN register to 1 Wait for a certain period Set the interrupt request flag to 0 Yi Figure 21 2 Interrupt enabled Note When all maskable interrupts can be disabled use the flag When all maskable interrupts cannot be disabled use the corresponding bits ILVLjO to ILVLj1
312. ext verify the FST7 bit in the FST register is set to 1 ready then verify the FST3 bit is set to 1 during program suspend or the FST6 bit is set to 1 during erase suspend before accessing the flash memory When the FST3 bit is set to 0 programming completes When the FST6 bit is set to 0 erasure completes When the FMR21 bit in the FMR register is set to 0 restart auto erase or auto programming is restarted To confirm whether auto programming or auto erase has restarted verify the FST7 bit in the FST register is set to 0 then verify the FST3 bit is set to 0 other than program suspend or the FST6 bit is set to 0 other than erase suspend 19 6 2 EW1 Mode When the FMRO1 bit in the FMRO register is set to 1 CPU rewrite mode enabled and then the FMR02 bit is set to 1 EW1 mode EW1 mode is selected The FST register can be used to confirm the status when programming erase is completed To enable the suspend function during auto erase or auto programming set the FMR20 bit in the FMR2 register to 1 suspend enabled and the FMR22 bit to 1 suspend request enabled by interrupt request and then execute the block program erase command The interrupt to enter suspend must be enabled beforehand When an interrupt request is generated the FMR21 bit in the FMR2 register is automatically set to 1 suspend request and auto erase or auto programming is suspended after td SR SUS Set the FMR21 bit to 0 restart to restart auto erase or aut
313. f 16 Bit Timer Operation in Programmable Wait One Shot Generation Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 215 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 Set to 1 by a program I 1 TSTART bit in l H TRBCR register 1 Set to 0 on Set to 1 by writing 1 to TOSST bit in completion of count TRBOCR register or INTO input trigger TOSSTF bit in TRBOCR register Count source Underflow signal from timer RB prescaler Timer RB2 counter Timer RB secondary is reloaded Timer RB primary is reloaded 1 Interrupt request signal Set to 0 by a program TOPL bit in TRBIOC register 1 UH 1 i H 1 H Set to 0 by a program i 1 i I i Wait state is started Waveform output is started Waveform output is completed i U U i U Li Li Li TRBO pin output Wait period One shot pulse output period TRBSC The above diagram applies under the following conditions TRBPRE register 01h TRBPR register 01h TRBSC register 03h TOPL bit 0 TOCNT bit 0 waveform output INOSTG bit 1 one shot trigger to INTO pin enabled INOSEG bit 1 rising edge in TRBIOC register TCNT16 bit in TRBMR register 0 8 bit timer with 8 bit prescaler Figure 14 7 Example of 8 Bit Timer with 8 Bit Prescaler Operation in Programmable Wait One Shot Generation Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 216 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2
314. f 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 3 Operation This A D converter provides operating four modes One shot repeat single sweep and repeat sweep modes This converter is a successive approximation type with 10 bit resolution The operating mode analog input channel and A D conversion clock should be switched while the ADST bit in the ADCONDO register is 0 A D conversion stops 17 3 1 Items Common to Multiple Modes 17 3 1 1 Input Sampling and A D Conversion Time The A D converter includes a sample and hold circuit When the ADST bit in the ADCONDO register is set to 1 A D conversion starts the A D converter samples the input and starts conversion after the A D conversion start delay time tD has elapsed Figure 17 2 shows the A D Conversion Timing Table 17 6 lists the A D Conversion Time As shown in Figure 17 2 the A D conversion time tCONV includes tD and the input sampling time tSPL Here tD is determined by the timing for writing to the ADCONDO register and is not a fixed value The conversion time therefore varies within the range shown in Table 17 6 In one shot mode and single sweep mode the ADF bit in the ADICSR register is set to 1 during end processing time and the last A D conversion result is stored in the ADi register e In one shot mode A D conversion time tCONV end processing time END e When two channels are selected in single sweep mode A D conversion time tCONV
315. f the count source Do not access the registers associated with timer RI OU other than the TCSTF bit until this bit is set to 1 count is in progress The count is started from the first active edge of the count source after the TCSTF bit is set to 1 After O count is stopped is written to the TSTART bit during a count operation the TCSTF bit remains 1 for two to three cycles of the count source When the TCSTF bit is set to 0 the count is stopped Do not access the registers associated with timer RJ2 UN other than the TCSTF bit until this bit is set to 0 Note 1 Registers associated with timer RJ2 TRJ TRJCR TRJIOC and TRJMR 3 In event counter mode set the TSTART bit in the TRJCR register to 1 count is started and then input an external pulse 4 In pulse width pulse period measurement modes bits TEDGF and TUNDF in the TRJCR register used are set to 0 by writing 0 by a program but remain unchanged even if 1 is written to these bits If a read modify write instruction is used to set the TRJCR register bits TEDGF and TUNDF may be erroneously set to 0 depending on the timing even when the TEDGF bit is set to 1 active edge received and the TUNDF bit is set to 1 underflow during execution of the instruction In this case write 1 using the MOV instruction to the TEDGF or TUNDF bit which is not supposed to be set to 0 5 Insert NOP instructions between writing to and reading from registers associated with the TRJ counter while the
316. ferent sampling clocks The interrupt by the INTi input can be used as a wakeup function to cancel wait mode or stop mode Table 11 11 lists the Pin Configuration for INTi Interrupt Table 11 11 Pin Configuration for INTi Interrupt Pin Name Assigned Pin Function P1_4 P4_5 INTO interrupt input P1_5 P1_7 P4_6 INT1 interrupt input P3_4 P4_7 INT2 interrupt input P3 3 INTS interrupt input RO1UH0050EJ0200 Rev 2 00 RENESAS Page 130 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 5 2 INTI Input Filter i 0 to 3 The INTi input has a digital filter The sampling clock can be selected by bits INTiFO to INTiF1 in the INTFO register The INTi level is sampled every sampling clock cycle and the corresponding IRIi bit in the IRR3 register is set to 1 interrupt requested when the sampled input level matches three successive times Figure 11 9 shows the INTi Input Filter Configuration Figure 11 10 shows an Example of INTi Input Filter Operation INTIF1 to INTIFO INTIEN O Sampling clock Digital filter INTiF1 to INTiFO matches three Other than 00b successive 2 times Two way edge S detection To INTI interrupt selection circuit INTIEN INTiSB INTiSA To timer RJ2 timer RB2 timer RC etc i Oto3 INTiEN Bit in INTEN register INTIFO to INTiF1 Bits in INTFO register INTISA INTiSB Bits in ISCRO register Figure 11 9 INTi Input Filter Configur
317. for setting to 0 e When 0 is written to this bit after reading it as 1 Condition for setting to 1 e See Table 14 5 Conditions for Setting TRBIF Bit to 1 Table 14 5 Conditions for Setting TRBIF Bit to 1 Operating Mode Condition Timer mode When timer RB2 underflows Programmable waveform generation mode When timer RB2 underflows during the secondary period Programmable one shot generation mode When timer RB2 underflows Programmable wait one shot generation mode When timer RB2 underflows during the secondary period RO1UHO050EJ0200 Rev 2 00 RENESAS Page 206 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 4 Operation 14 4 1 Timer Mode In this mode an internally generated count source or the timer RJ2 underflow is counted Registers TRBOCR and TRBSC are not used When count is started is written to the TSTART bit in the TRBCR register the count is started after the count source is sampled three times When 0 count is stopped is written to the TSTART bit the count is stopped after the count source is sampled three times When count is forcibly stopped is written to the TSTOP bit in the TRBCR register the count is stopped The actual count state should be monitored with the TCSTF bit in the TRBCR register An interrupt request is generated when timer RB2 underflows When registers TRBPRE and TRBPR are read each count value can be read When registers TRBPRE and TRBPR
318. fter trigger TRCGRD BUFEB 0 Not used in PWM2 mode TRCGRD BUFEB 1 Buffer register Set the next PWM output change point TRCIOB pin Refer to 15 5 5 Buffer Operation Timing j A B C or D BUFEA BUFEB Bits in TRCMR register Note 1 Do not set the TRCGRB and TRCGRC registers to the same value RO1UHO050EJ0200 Rev 2 00 stENESAS Page 234 of 426 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 3 Timer RC Mode Register TRCMR Address 000F2h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol CTS BUFEB BUFEA PWM2 PWMD PWMC PWMB After Reset 0 1 0 0 1 0 0 0 Bit Name Function TRCIOB PWM mode select bit 1 0 Timer mode TRCIOC PWM mode select bit 1 1 PWM mode TRCIOD PWM mode select bit 1 PWM2 mode select bit 0 PWM2 mode 1 Timer mode or PWM mode TRCGRC register function select 0 Output compare or input capture register bit 2 1 TRCGRC register is used as a buffer register for TRCGRA register TRCGROD register function select bit 0 Output compare or input capture register 1 TRCGRD register is used as a buffer register for TRCGRB register Nothing is assigned The write value must be 1 The read value is 1 TRCCNT count start bit 0 Count is stopped 1 Count is started Notes 1 These bits are enabled when the PWM2 bit is 1 timer mode or PWM mode 2 Set the BUFEA bit to 0 general register in PWM2 mode CTS Bit TRCCNT count start bit Conditions for setting
319. g generated 1 Oscillation stop detection interrupt request is generated Nothing is assigned The write value must be 0 The read value is 0 Note 1 Bits XINHALT and CKSWIF are enabled when the XINBAKE bit is 1 oscillation stop detection function enabled When the XINHALT bit is 0 XIN clock oscillating it indicates that the XIN clock is oscillating It does not indicate oscillation is stable Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the BAKCR register CKSWIF Bit Oscillation stop detection interrupt request flag Condition for setting to 0 e When 0 is written to this bit Condition for setting to 1 e When oscillation stop is detected while the XIN clock is selected as the system base clock and the XINBAKE bit in the BAKCR register is 1 oscillation stop detection function enabled 9 2 8 High Speed On Chip Oscillator 18 432 MHz Control Register 0 FR18S0 Address 00064h Bit b7 b6 b5 b4 b3 b2 b1 bO SE fl After Reset Value when shipped Bit Function R W Pit Function RW b7 to bO Frequency adjustment data for 18 482 MHz is stored The frequency of the high speed on chip oscillator can be adjusted to 18 432 MHz by transferring this value to the FRV1 register and the adjustment value in the FR18S1 register to the FRV2 register RO1UHO050EJ0200 Rev 2 00 RENESAS Page 83 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circu
320. ge 266 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC e When the timer RC pin is pulled up the OPE bit in the TRCOPR register is 1 waveform output manipulation enabled bits OPOL1 to OPOLO are 01b when timer RC pin is pulled up timer RC output level is fixed to high impedance during waveform output manipulation period and the RESTATS bit is 0 output is restarted by software Waveform output manipulation event is input U Waveform output manipulation event INT1 comparator B1 output EB bit in TRCOER register Corresponding output with waveform output manipulation disabled Timer RC output TRCIOB_XP internal signal Output control signal TRCOBE_XN internal signal high impedance and at high when timer RC pin is pulled up Waveform output manipulation event is cancelled 1 Waveform output manipulation is stopped by software and output Synchronized so that less than one cycle of waveform is not output Figure 15 24 Example of Waveform Output Manipulation Operation 2 e When the OPE bit in the TRCOPR register is 1 waveform output manipulation enabled bits OPOL1 to OPOLO are 10b timer RC output level is fixed at low during waveform output manipulation period and the RESTATS bit is 1 output is automatically restarted Waveform output manipulation Waveform output event is input manipulation event Waveform output manipulation event is cancelled
321. gister Compare match Output control Compare match Trigger Compare match TRCGRA register TRCGRB TRCGRD register register TRCGRC register 1 The above applies when the BUFEB bit in the TRCMR register is 1 TRCGRD register is used as a buffer register for TRCRGB register Figure 15 12 Block Diagram in PWM2 Mode RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 255 of 426 R8C M11A Group R8C M12A Group 15 Timer RC e Transfer by compare match TRCCNT register l 0000h TRCGRA register l TRCGRD register TRCGRB register Compare match e Transfer by TRCTRG input TRCCNT register TRCGRA register TRCGRD register TRCGRB register Counter clearing by TRCTRG input Figure 15 13 Timing of Buffer Operations for Registers TRCGRD and TRCGRB in PWM2 Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 256 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC In PWM2 mode the TRCTRG input is used to output a pulse with an arbitrary delay time and width from the TRCIOB pin Set bits TCEG1 to TCEGO in the TRCCR2 register to 10b falling edge to set the falling edge for the TRCTRG input Set the CSTP bit in the TRCCR2 register to 0 increment is continued to continue incrementing when compare match A with the TRCGRA register occurs Set the BUFEB bit in the TRCMR register to 1 TRCGRD register is used as a buffer register for TRCGRB register to set the TRCGRD register as
322. gister see Figure 13 8 If the TRJIO pin is set to low before the TSTART bit is set to 1 count is started and a valid event is input after the TSTART bit is set to 1 the signal is not counted on the first rising edge of the TRJIO input Thus the number of counted events is obtained as follows Number of counted events initial value in the counter value in the counter on completion of the valid event 1 1 To avoid this set the TRJIO pin to low after setting the TSTART bit to 1 count is started see Figure 13 9 TRUJIO pin A TEDGSEL bit in x 0 TRJIOC register TSTART bit in TRJCR register Not counted on first rising edge Count source Counter 0503h initial value 0502h 0501h 0500h 04FFh 04FEh 04FDh Figure 13 8 TSTART Setting Timing in Event Counter Mode 1 TRJIO pin TEDGSEL bit in TRJIOC register TSTART bit in TRJCR register Count source Counter 0503h initial value 0502h 0501h 0500h 04FFh 04FEh 04FDh 04FCh Figure 13 9 TSTART Setting Timing in Event Counter Mode 2 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 194 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 9 When the TEDGSEL bit in the TRJIOC register is set to 1 count on falling edge and the external signal TRJIO is counted in event counter mode the signal may not be counted correctly depending on the state of the TSTART bit in the TRJCR register see Figure 13 10 Even if the TRJIO pin is set to
323. gle output from TRCIOB pin at compare match B IOB2 1 input capture function b5 b4 0 0 Rising edge on TRCIOB pin 0 1 Falling edge on TRCIOB pin 1 0 Two way edge on TRCIOA pin 1 1 Do not set TRCGRB control B2 bit 1 0 Output compare function 1 Input capture function Nothing is assigned The write value must be 1 The read value is 1 Note 1 When bits BUFEA and BUFEB in the TRCMR register are set to 1 registers TRCGRA and TRCGRC and registers TRCGRB and TRCGRD are paired The same values must be set in the IOA2 bit and the IOC2 bit in the TRCIOR1 register and in the IOB2 bit and the IOD2 bit in the TRCIOR1 register respectively The setting of the TRCIORO register is invalid in PWM and PWM2 modes RO1UHO050EJ0200 Rev 2 00 RENESAS Page 239 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 8 Timer RC I O Control Register 1 TRCIOR1 Address 000F7h Bit b 7 b6 b5 b4 b3 b2 b1 bO Symbol After Reset 1 Bit Name Function TRCGRC IOC2 0 IOC3 0 output from TRCIOA pin at compare match CH 1 2 control CO bit bibo OI TRCGRG 0 0 Pin output by compare match C is disabled control C1 bit 0 1 Low level output from TRCIOA pin at compare match C 1 0 High level output from TRCIOA pin at compare match C 1 1 Toggle output from TRCIOA pin at compare match C IOC2 0 IOC3 1 output from TRCIOC pin at compare match CH 1 b1 b 0 0 P
324. gnal TRCCNT register SE EH TRCGRA to TRCGRD IMFA to IMFD IMFA to IMFD Bits in TRCSR register Figure 15 33 Timing at Input Capture RO1UHO050EJ0200 Rev 2 00 RENESAS Page 272 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 5 8 Timing for Setting Bits IMFA to IMFD and OVF to 0 Bits IMFA to IMFD and OVF are set to 0 when 0 is written after the CPU reads it as 1 Figure 15 34 shows the Timing for Setting Bits IMFA to IMFD and OVF by CPU Write cycle to TRCSR register Ti T2 EE LU LULU ULE Write signal IMFA to IMFD and OVF IMFA to IMFD and OVF Bits in TRCSR register Figure 15 34 Timing for Setting Bits IMFA to IMFD and OVF by CPU 15 5 9 Timing of A D Conversion Start Trigger due to Compare Match Figure 15 35 shows the Timing of A D Conversion Start Trigger due to Compare Match TRCCNT register input clock TRCCNT register Registers TRCGRA to TRCGRD A D conversion start trigger signal Figure 15 35 Timing of A D Conversion Start Trigger due to Compare Match RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 273 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 6 Timer RC Interrupt Timer RC generates a timer RC interrupt request from five sources The timer RC interrupt uses bits ILVL35 and ILVL34 in the ILVL3 register the IRTC bit in the IRRO register and a single vector Table 15 18 lists the Registers Associated with Timer RC Interrupt and Figure 15 36 s
325. h 001B8h 001F8h 001B9h 001F9h 001BAh 001FAh 001BBh 001FBh 001BCh 001FCh 001BDh 001FDh 001BEh 001FEh 001BFh 001FFh Note 1 The blank areas are reserved No access is allowed I OFFDBh Option Function Select Register 2 OFS2 31 40 OFFFFh Option Function Select Register OFS 32 41 CENESAS R8C M11A Group R8C M12A Group RO1UH0050EJ0200 RENESAS MCU Rev 2 00 May 18 2012 1 Overview 1 1 Features The R8C M11A Group and R8C M12A Group of single chip microcontrollers MCUs incorporate the RSC CPU core which provides sophisticated instructions for a high level of efficiency With 1 Mbyte of address space the CPU core is capable of executing instructions at high speed In addition it features a multiplier for high speed arithmetic processing Power consumption is low and the supported operating modes allow additional power control These MCUs are designed to maximize EMI EMS performance Integration of many peripheral functions on the same chip including multifunction timer and serial interface reduces the number of system components The R8C M11A Group and R8C M12A Group include data flash 1 KB x 2 blocks 1 1 1 Applications Home appliances office equipment audio equipment consumer products etc RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 1 of 426 May 18 2012 R8C M11A Group R8C M12A Group 1 Overview 1 1 2 Differences between Groups Table 1 1 lists the Specification
326. h select bit One stop bit Two stop bits Odd even parity select bit 3 Odd parity Even parity Parity enable bit Parity disabled 1 Parity enabled Reserved Set to 0 Notes 1 When setting bits SMD2 to SMDO to 000b serial interface disabled set the TE bit in the UOC1 register to 0 transmission disabled and the RE bit to 0 reception disabled 2 When bits SMD2 to SMDO are set to 001b clock synchronous serial I O mode the error flags bits FER PER and SUM in the UORB register are disabled When these bits are read the values are undefined 3 The PRY bit is enabled when the PRTYE bit is 1 parity enabled RO1UH0050EJ0200 Rev 2 00 RENESAS Page 280 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 2 2 UARTO Bit Rate Register UOBRG Address 00081h Bit b7 b6 b5 b4 b3 b2 b1 b symbol ek e After Reset X X X x X X X X e Sting Fangs b7 to bO If the set value is n UOBRG divides the count source by n 1 00h to EEN Write to the UOBRG register using the MOV instruction while transmission and reception are stopped Set bits CLKO to CLK1 in the UOCO register before writing to this register 16 2 3 UARTO Transmit Buffer Register UOTB Address 00082h UOTBL Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol ae Bee ee ee eee After Reset X Address 00083h UOTBH Bit bus mu ba b12 bi bag b9 b8 a ee ee After Reset X X X
327. he CKSTPR register to 1 is switched from fLOCO to fHSCK Operating on the high speed on chip oscillator clock Figure 9 5 Flowchart for Switching from Low Speed On Chip Oscillator to High Speed On Chip Oscillator Clock RO1UHO050EJ0200 Rev 2 00 RENESAS Page 89 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 4 6 2 Procedure for Switching System Base Clock to XIN Clock Figure 9 6 shows the Flowchart for Switching from Low Speed On Chip Oscillator to XIN Clock Operating on the low speed on chip oscillator clock Start reset U U I U U U U I f Set the P46SEL2 bit in the PMH4E register is 0 bits P47SEL1 to P47SELO and P46SEL1 l to P46SELO in the PMH4 register are 0000b 1 The XIN clock starts oscillating i and bits CKPT1 to CKPTO in the EXCKCR register are 11b U I U U I U U U U I U I U U I U 2 Assure the wait time for oscillation stabilization Wait for the XIN clock to stabilize by a program Set the SCKSEL bit 3 When the SCKSEL bit is set to 1 HSCk in the CKSTPR register to 1 fBASE is switched from fLOCO to fHSCK Operating on the XIN clock Operating on the XIN clock Figure 9 6 Flowchart for Switching from Low Speed On Chip Oscillator to XIN Clock RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 90 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 5 Oscillation Stop Detection Function
328. he digital filter is enabled by the INTI input filter select bit the INTI input high width is 1 digital filter clock frequency x 3 or the minimum value of the standard whichever is greater SEN 2 When the digital filter is enabled by the INTi input filter select bit the INTi input low width is 1 digital filter clock frequency x 3 or the minimum value of the standard whichever is greater Figure 20 7 Timing for External Interrupt INTi Input and Key Input Interrupt Kli When Vcc 5 V RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 379 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 19 DC Characteristics 3 2 7 V lt Vcc lt 4 0 V i Standard Parameter Condition Min Output high voltage P1_2 P1 When drive loH 5 mA P3_3 P3 capacity is high When drive loH 1 mA capacity is low P1_0 P1 loH 1 mA P4_2 P4_5 P4 PA_O Output low voltage P1_2 P1 When drive loL 5 mA P3_3 P3 capacity is high When drive Io 1 mA capacity is low loL 1 mA Hysteresis INTO INT1 INT2 INT3 Vcc 3 V KIO KI1 KI2 KI3 TRJIO TRCIOA TRCIOB TRCIOC TRCIOD RXDO CLKO RESET Vec 3V IIH Input high current V 3 V Vcc 3 0 V liL Input low current Vi 0 V Vcc 3 0 V RPuLLuP Pull up resistance V 0 V Vcc 3 0 V R XIN Feedback resistance VRAM RAM hold voltage In stop mode Notes
329. he erase target area 2 td SR SUS is required from when the FMR21 bit is set to 1 until suspend is acknowledged The interrupt to enter suspend must be enabled beforehand Figure 19 13 Block Erase Flowchart in EW Mode Flash Ready Status Interrupt Disabled and Suspend Enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 350 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory Maskable interrupt i Y RDYSTIE 1 FMR20 1 Write the command code 20h 1 interrupt enabled Write DOh to any address in the block C Block erase completed FMR21 1 Flash ready status interrupt 1 3 Access the flash memory FMR21 0 Full status check H RDYSTI 0 i REIT Notes Flag in CPU register RDYSTI FST6 Bits in FST register RDYSTIE Bit in FMRO register FMR20 FMR21 Bits in FMR2 register 1 The interrupt vector table and interrupt routine to be used must be allocated to an area other than the erase target area 2 td SR SUS is required from when the FMR21 bit is set to 1 until suspend is acknowledged The interrupt to enter suspend must be enabled beforehand 3 A flash ready status interrupt is generated when auto erase is suspended Figure 19 14 Block Erase Flowchart in EW Mode Flash Ready Status Interrupt Enabled and Suspend Enabled RO1UH0050EJ0200 Rev 2 00 RENESAS May 18 2012 Page 351 of 426
330. he high speed on chip oscillator clock Process in low speed on chip oscillator mode Switch the clock source for the CPU clock 2 Write 0 flash memory operates to the FMSTP bit Wait until the flash memory circuit stabilizes 10 ps Write 0 CPU rewrite mode disabled to the FMR01 bit FMR01 FMSTP Bits in FMRO register Wait until the flash memory circuit stabilizes Notes 115 us 1 Set the FMRO1 bit to 1 CPU rewrite mode enabled and then set the FMSTP bit to 1 flash memory is stopped When switching the clock source for the CPU clock Jump to any address in the flash memory the new clock must be stable Provide a wait time of 10 us or 115 us by a program Do not access the flash memory during this wait time Figure 10 6 Procedure for Reducing Power Consumption Using FMSTP Bit RO1UHO050EJ0200 Rev 2 00 RENESAS Page 106 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 5 11 Low Current Consumption Read Mode In low speed on chip oscillator mode the current consumption when reading the flash memory can be reduced by setting the FMR27 bit in the FMR2 register to 1 low current consumption read mode enabled Set the CPU clock fs to a frequency in the range of 3 kHz to 50 kHz Figure 10 7 shows the Procedure for Using Low Current Consumption Read Mode Handling procedure for enabling low current consumption read mode using FMR27 bit Enter low speed on chip oscilla
331. he values of registers TRBPRE and TRBPR before reading them RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 400 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 9 Notes on Timer RC 21 9 1 TRCCNT Register The following note applies when the CCLR bit in the TRCCR1 register is set to 1 TRCCNT counter is cleared by input capture compare match A e When writing a value to the TRCCNT register by a program while the CTS bit in the TRCMR register is set to 1 count is started ensure that the write timing does not coincide with when the TRCCNT register is set to 0000h e If the timing when the TRCCNT register is set to 0000h and is written coincide with each other the value is not be written and the TRCCNT register is set to 0000h If the TRCCNT register is written and read the value before this register is written may be read In this case execute the JMP B instruction between the write and read instructions e Program Example MOV W XXXXh TRCCNT Write JMP B LI JMP B instruction LI MOV W TRCCNT DATA Read 21 9 2 TRCCR1 Register To set bits CKS2 to CKSO in the TRCCRI register to 110b HOCO set fHOCO to the clock frequency higher than the system clock frequency 21 9 3 TRCSR Register If the TRCSR register is written and read the value before this register is written may be read In this case execute the JMP B instruction between the write and read instructions e Program Example MOV B XXh TRC
332. hen the on chip debugger is used Figure 11 1 Types of Interrupts RO1UH0050EJ0200 Rev 2 00 RENESAS Page 109 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts Table 11 2 Descriptions of Interrupts Interrupt Description Undefined instruction interrupt An unidentified instruction interrupt is generated when the UND instruction is executed Overflow interrupt An overflow interrupt is generated when the O flag is 1 arithmetic operation overflow and the INTO instruction is executed Instructions that change the O flag are as follows ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA and SUB BRK instruction interrupt A BRK interrupt is generated when the BRK instruction is executed INT instruction interrupt An INT instruction interrupt is generated when the INT instruction is executed Software interrupt numbers the INT instruction can specify are 0 to 63 The number is assigned to each peripheral function interrupt When the INT instruction is executed specifying the number the peripheral function interrupt with the same number can be executed For software interrupt numbers 0 to 31 the U flag is saved on the stack during instruction execution and the U flag is set to 0 ISP before the interrupt sequence is executed The U flag is restored from the stack when the MCU returns from the interrupt routine For software interrupt numbers 32 to 63 the U flag does not change state during instruction
333. her a cold start up or warm start up has occurred The CWR bit is set to 0 cold start up after power on or voltage monitor 0 reset This bit remains unchanged after a hardware reset software reset or watchdog timer reset The CWR bit is set to 1 by writing 1 by a program but writing 0 to this bit has no effect Condition for setting to 0 e When a reset occurs after power on or voltage detection 0 Condition for setting to 1 e When is written to this bit by a program HWR Bit Hardware reset detect flag This flag indicates that a hardware reset has occurred Condition for setting to 0 e When a software reset watchdog timer reset power on reset or voltage monitor 0 reset occurs Condition for setting to 1 e When a hardware reset occurs SWR Bit Software reset detect flag This flag indicates that a reset has been generated by software Condition for setting to 0 e When a watchdog timer reset hardware reset power on reset or voltage monitor 0 reset occurs Condition for setting to 1 e When a software reset occurs RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 29 of 426 May 18 2012 R8C M11A Group R8C M12A Group 5 System Control WDR Bit Watchdog timer reset detect flag This flag indicates that a reset has been generated by the watchdog timer Condition for setting to 0 e When a software reset hardware reset power on reset or voltage monitor 0 reset occurs Condition for setting to 1
334. hest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 21 5 2 SP Setting Set a value in the SP before any interrupt is acknowledged The SP is 0000h after a reset If an interrupt is acknowledged before setting a value in the SP the program may run out of control 21 5 3 External Interrupt and Key Input Interrupt Signal input to pins INTO to INT3 and pins KIO to KI3 must meet either the low level width or the high level width requirements shown in External Interrupt INTi Input i 0 to 3 in the Electrical Characteristics regardless of the CPU operating clock For details see Table 20 18 Vcc 5 V Table 20 24 Vcc 3 V and Table 20 30 Vcc 2 2 V External Interrupt INTi Input Key Input Interrupt KIi i 0 to 3 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 390 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 5 4 Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN When changing the functions of the INTO to INT3 and KIO to KI3 interrupts an interrupt request flag may be set to 1 by rewriting registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN When an interrupt function is switched rewrite these registers with interrupt requests disabled and wait for a certain period before setting the interrupt request flag to 0 Figure 21 1 shows the Procedure for Manipulating Registers PMLi
335. hows a Timer RC Interrupt Block Diagram Table 15 18 Registers Associated with Timer RC Interrupt Timer RC Interrupt Request Monitor Flag Register TASR TRIER mvs mo Timer RC Status Timer RC Interrupt Timer RC Interrupt Register Enable Register Control Register IMFA bit e Timer RC interrupt request IMEA Dit IRTC bit in IRRO register IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit OVF bit OVIE bit IMFA IMFB IMFC IMFD OVF Bits in TRCSR register IMIEA IMIEB IMIEC IMIED OVIE Bits in TRCIER register Figure 15 36 Timer RC Interrupt Block Diagram Like other maskable interrupts the timer RC interrupt is controlled by the combination of the I flag IRTC bit bits ILVL35 to ILVL34 and IPL However it differs from other maskable interrupts in the following respects because a single interrupt source timer RC interrupt is generated from multiple interrupt request sources e The IRTC bit in the IRRO register is set to 1 interrupt requested when a bit in the TRCSR register is set to 1 and the corresponding bit in the TRCIER register is also set to 1 interrupt enabled e The IRTC bit is set to 0 no interrupt requested when the bit in the TRCSR register or the corresponding bit in the TRCIER register is set to 0 or both are set to 0 In other words the interrupt request is not maintained if the IRTC bit is once set to 1 but the interrupt is not acknowledged e If another interrupt source is trigg
336. iding the system clock by no division 2 4 8 16 or 32 Also the peripheral function clock is obtained by dividing the system clock with the prescaler In addition fHOCO can be used as the peripheral function clock when the HOCOE bit in the OCOCR register is 1 high speed on chip oscillator on and LOCO when the LOCODIS bit is 0 low speed on chip oscillator on 10 2 2 High Speed On Chip Oscillator Mode When the HOCOE bit in the OCOCR register is 1 high speed on chip oscillator on the HSCKSEL bit in the SCKCR register is 1 high speed on chip oscillator clock and the SCKSEL bit in the CKSTPR register is 1 fHSCK the high speed on chip oscillator clock is used as the system base clock fBASE At this time the system clock is obtained by dividing the high speed on chip oscillator clock by any value from 1 no division to 256 The CPU clock is obtained by dividing the system clock by 1 no division 2 4 8 16 or 32 Also the peripheral function clock is obtained by dividing the system clock with the prescaler In addition LOCO can be used as the peripheral function clock when the LOCODIS bit is 0 low speed on chip oscillator on 10 2 3 Low Speed On Chip Oscillator Mode When the LOCODIS bit in the OCOCR register is 0 low speed on chip oscillator on and the SCKSEL bit in the CKSTPR register is 0 f LOCO the low speed on chip oscillator clock is used as the system base clock fBASE At this time the system clock is obtaine
337. ied by the U flag Otherwise it is ISP Figure 11 6 Register Saving Operation R01UH0050EJ0200 Rev 2 00 RENESAS Page 127 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 4 8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine the FLG register and PC which have been saved on the stack are restored The program that was running before the interrupt request was acknowledged starts running again The registers saved by a program in the interrupt routine should be restored using the POPM or similar instruction before executing the REIT instruction 11 4 9 Interrupt Priority If two or more interrupt requests are generated while a single instruction is being executed the interrupt with the higher priority is acknowledged Any maskable interrupt peripheral function priority level can be selected by bits ILVLi0 to ILVLi1 or bits ILVLi4 to ILVLi5 However if two or more maskable interrupts have the same priority level the interrupt with higher priority given by hardware is acknowledged The priority of special interrupts such as the watchdog timer interrupt is set by hardware Figure 11 7 shows the Hardware Interrupt Priority Software interrupts are not affected by the interrupt priority If a software interrupt instruction is executed the MCU will execute the corresponding interrupt routine Watchdog timer Oscillation stop detection Voltage monitor
338. ies when the digital filter is not used Figure 6 6 Example of Cold Start Up Warm Start Up Function Operation 6 3 8 Reset Source Determination Function The RSTFR register can be used to detect whether a hardware reset software reset or watchdog timer reset has occurred If a hardware reset occurs the HWR bit is set to 1 detected If a software reset occurs the SWR bit is set to 1 detected If a watchdog timer reset occurs the WDR bit is set to 1 detected R01UH0050EJ0200 Rev 2 00 ztENESAS Page 46 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 4 States during Reset 6 4 1 Pin States While RESET Pin Level is Low Tables 6 3 and 6 4 list the Pin States Table 6 3 Pin States R8C M11A Group Pin Name Pin Function P1_1 to P1_7 Input port P3_7 Input port P4_6 P4_7 Input port DA 0 Input port Table 6 4 Pin States R8C M12A Group P1_0 to P1_7 Input port P3_3 to P3_5 P3_7 Input port P4_2 P4_5 to P4_7 Input port PA_0O Input port RO1UHO050EJ0200 Rev 2 00 stENESAS Page 47 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 4 2 CPU Register States After Reset Figure 6 7 shows the CPU Register States After Reset b19 bO 0000h Content of addresses OFFFEh to OFFFCh b15 bO b15 bO 0000h 1 DIS b8 l b7 D Te fufijoje s zjo c Figure 6 7 CPU Register States After Reset Data register RO Da
339. illator by 16 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 65 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 2 5 Count Source Protection Mode Register CSPR Address 00034h Bit b7 b6 b5 b4 b3 b2 b1 bO symbol CSPROT Jl After Reset 1 0 0 0 0 0 0 0 The above applies when the CSPROINI bit in the OFS register is 0 After Reset 0 0 0 0 0 0 0 0 The above applies when the CSPROINI bit in the OFS register is 1 Bit Name Function Reserved Set to 0 Count source protection mode select bit 1 0 Count source protection mode disabled 1 Count source protection mode enabled Note 1 To set the CSPRO bit to 1 first write 0 and then write 1 to it This bit cannot be set to 0 by a program Do not write to any register other than the CSPR register between writing 0 and then writing 1 8 2 6 Periodic Timer Interrupt Control Register WDTIR Address 00035h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol After Reset 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Periodic timer interrupt request flag 0 No periodic timer interrupt requested 1 Periodic timer interrupt requested Periodic timer interrupt enable bit 1 0 Periodic timer interrupt disabled 1 Periodic timer interrupt enabled Note 1 When bits WDTRCS1 to WDTRCSO in the OFS2 register is 11b 100 set the WDTIE bit to 0 per
340. in PWM2 mode Table 15 17 lists the States Where A D Conversion Start Trigger Sources are Generated Table 15 17 States Where A D Conversion Start Trigger Sources are Generated A D Conversion Start Trigger Source Operaling Mader Bile Operate TRCGRA TRCGRB TRCGRC TRCGRD Input capture Used Not used Compare match Used Not used PWM mode Used Not used PWM2 mode Used Not used Yes An A D conversion start trigger is generated No No A D conversion start trigger is generated RO1UHO050EJ0200 Rev 2 00 RENESAS Page 263 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 4 3 Changing Output Pins and General Registers The settings for bits IOC3 and IOD3 in the TRCIOR1 register can redirect the compare match output with registers TRCGRC and TRCGRD from pins TRCIOC and TRCIOD to pins TRCIOA and TRCIOB respectively The TRCIOA pin can output a combination of compare matches A and C and the TRCIOB pin can output a combination of compare matches B and D Figure 15 21 shows the Block Diagram for Changing Output Pins and General Registers Compare match utpu TRCIOA O control Comparator TRCGRA Gem Compare match utpu TRCIOC O ES p control Comparator TRCGRC Compare match utpu TRCIOB CH control Comparator TRCGRB marp o Compare match utpu IOC3 IOD3 Bits in TRCIOR1 register Figure 15 21 Block Diagram for Changing Output Pins and General Reg
341. in output by compare match C is disabled 0 1 Low level output from TRCIOC pin at compare match C 1 0 High level output from TRCIOC pin at compare match C 1 1 Toggle output from TRCIOC pin at compare match C IOC2 1 IOC3 1 TRCIOC input edge selected at input capture CH 3 b1 b 0 0 Input capture C occurs on the rising edge of TRCIOC input 0 1 Input capture C occurs on the falling edge of TRCIOC input 1 0 Input capture C occurs on the two way edge of TRCIOC input 1 1 Do not set TRCGRC 0 Output compare function control C2 bit 4 1 Input capture function TRCGRC 0 Output from TRCIOA pin at compare match C 8 control C3 bit 1 Output from TRCIOC pin at compare match C TRCGRD IOD2 0 IOD3 0 output from TRCIOB pin at compare match D 5 6 control DO bit bSb4 SC TRCGRD 0 0 Pin output by compare match D is disabled control D1 bit 0 1 Low level output from TRCIOB pin at compare match D 1 0 High level output from TRCIOB pin at compare match D 1 1 Toggle output from TRCIOB pin at compare match D IOD2 0 IOD3 1 output from TRCIOD pin at compare match D 5 b5 b4 0 0 Pin output by compare match D is disabled 0 1 Low level output from TRCIOD pin at compare match D 1 0 High level output from TRCIOD pin at compare match D 1 1 Toggle output from TRCIOD pin at compare match D IOD2 1 IOD3 1 TRCIOD input edge selected at input capture D 7 b5 b4 0 0 Input capture D occurs on the ris
342. in the TRBCR register is 1 count is started or the TCSTF bit is 1 count is in progress do not change the values in registers TRBIOC and TRBMR and the TRBIE bit in the TRBIR register e Make sure the TCSTF bit in the TRBCR register is 1 count is in progress before writing 1 one shot count is started to the TOSST bit in the TRBOCR register When the TCSTF bit is 0 count is stopped writing 1 one shot count is started to the TOSST bit is invalid e When writing to registers TRBPRE TRBPR and TRBSC during count operation the TSTART bit is 1 or the TCSTF bit is 1 note the following points When writing to the TRBPRE register successively allow at least three cycles of the count source for each write interval When writing to the TRBPR register successively allow at least three cycles of the count source for each write interval When writing to the TRBSC register successively allow at least three cycles of the count source for each write interval e When the TRBPR register is rewritten in programmable waveform generation mode do not write to the TRBPRE TRBPR or TRBSC register during the secondary output period as described below after rewriting 8 bit timer with 8 bit prescaler Two cycles of the prescaler underflow before the secondary output period ends 16 bit timer Two cycles of the count source clock before the secondary output period ends e When the underflow signal from timer RJ2 is used as the count source fo
343. ing Enter low speed on chip oscillator mode LPE lt 0 low power consumption wait mode disabled 4 If the high speed clock or high speed on chip oscillator WTFMSTP lt 0 Stop the XIN clock and starts in the flash memory operates in wait mode high speed on chip oscillator clock interrupt routine execute steps 1 to 3 at the end of the routine Start the XIN clock or LPE lt 1 high speed on chip oscillator clock low power consumption wait mode enabled 4 5 Wait until the XIN clock or high speed on chip oscillator clock oscillation stabilizes Enter high speed clock mode or high speed on chip oscillator mode LPE Bit in VCA2 register WTFMSTP Bit in FMR1 register Interrupt handling completed Notes 1 Execute this routine for all interrupt processing that occurs in wait mode However this is not required if it is not necessary to start the high speed clock or high speed on chip oscillator in the interrupt routine 2 When a maskable interrupt request is generated in wait mode set by the WAITM bit in the SCKCR register interrupt handling is not performed but execution is resumed immediately after the instruction used to set the WAITM bit to 1 See 10 3 Wait Mode for returning from wait mode 3 When the FMSTP bit in the FMRO register is 1 flash memory is stopped the WTFMSTP bit is disabled This setting is not required 4 Do not write 0 to the LPE bit with the instruction immediately after 1 is
344. ing Operating Mode Function Pulse output mode Output is started at high Output is started at low Event counter mode Count on rising edge Count on falling edge Pulse width measurement mode Low level width is measured High level width is measured Pulse period measurement mode 0 Measure from one rising edge to the next rising edge Measure from one falling edge to the next falling edge Table 13 5 TRJO Output Polarity Switching Operating Mode Function All modes 0 Output is started at low 1 Output is started at high RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 182 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 TOPCR Bit TRJIO output control bit The TOPCR bit is enabled only in pulse output mode When this bit is set to 0 a pulse can be output from the TRJIO pin When it is set to 1 output is disabled and the port selected as the TRJIO function becomes high impedance In other operating modes the functions listed in Table 13 6 are supported regardless of the setting of the TOPCR bit Table 13 6 TRJIO Pin Function Timer mode Not used Event counter mode Event input count source input Pulse width measurement mode Input for pulse width measurement Pulse period measurement mode Input for pulse period measurement Bits TIPFO to TIPF1 TRJIO input filter select bits These bits are used to specify the sampling frequency of the filter for the TRJIO i
345. ing VdetO Vdet0 cannot be monitored 7 3 2 Monitoring Vdet1 Make the following settings and wait for td E A see 20 Electrical Characteristics After that the comparison result from voltage monitor 1 can be monitored with the VW1C3 bit in the VWIC register 1 Set bits VD1S1 to VD1S3 in the VDILS register to select the detection voltage for voltage detection 1 2 Set the VCIE bit in the VCA2 register to 1 voltage detection 1 circuit enabled RO1UHO050EJ0200 Rev 2 00 stENESAS Page 57 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 4 Voltage Monitor 0 Reset Table 7 3 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset Figure 7 4 shows an Example of Voltage Monitor 0 Reset Operation Set the VWOC1 bit in the VWOC register to 1 digital filter disabled mode to use the voltage monitor 0 interrupt to clear stop mode Table 7 3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset Step When the Digital Filter is Used When the Digital Filter is Not Used Set bits VDSELO to VDSEL1 in the OFS register to select the detection voltage for voltage detection 0 Set the VCOE bit in the VCA2 register to 1 voltage detection 0 circuit enabled Wait for td E A Set VWOFO to VWOF1 in the VWOC register to select the sampling clock for the digital filter Set the VWOC1 bit in the VWOC register to 0 digital Set the VWOC1 bit in the VWOC register to 1 digital
346. ing edge of TRCIOD input 0 1 Input capture D occurs on the falling edge of TRCIOD input 1 0 Input capture D occurs on the two way edge of TRCIOD input 1 1 Do not set TRCGRD 0 Output compare function control D2 bit 4 1 Input capture function TRCGRD 0 Output from TRCIOB pin at compare match D 8 control D3 bit 1 Output from TRCIOD pin at compare match D Notes 1 When the BUFEA bit in the TRCMR register is 1 TRCGRC register is used as a buffer register for TRCGRA register the value of the TRCGRC register is transferred to the TRCGRA register at compare match A 2 When the IOA2 bit in the TRCIORO register is 0 output compare function if compare matches A and C occur simultaneously the output from the TRCIOA pin at compare match C takes precedence 3 When the BUFEA bit is 1 TRCGRC register is used as a buffer register for TRCGRA register the value of the TRCGRA register is transferred to the TRCGRC register at input capture A When the input capture edge of the TRCIOC pin selected by bits OCO to IOC1 is input the IMFC bit in the TRCSR register is set to 1 However the count value is not transferred to the TRCGRC register RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 240 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 4 In buffer operation registers TRCGRA and TRCGRC and registers TRCGRB and TRCGRD are paired The same values must be set in the IOC2 bit and
347. ing the HSCKSEL bit in the SCKCR register A clock for the A D converter This clock is obtained by dividing the system clock fAD is not stopped in wait mode RO1UH0050EJ0200 Rev 2 00 May 18 2012 RENESAS Page 87 of 426 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 4 5 Prescaler The prescaler is a 13 bit counter that uses the system clock as an input clock The divided output is used as the internal clock for the on chip peripheral functions The prescaler starts operating when the PSCSTP bit in the CKSTPR register is set to 0 prescaler operates The prescaler is stopped when wait mode is entered after the WCKSTP bit in the CKSTPR register is set to 1 system clock stopped in wait mode If the clock is switched by the WAITRS bit in the CKRSCR register when a transition is made from wait mode to standard mode the prescaler is initialized When a transition is made from stop mode to standard mode the prescaler is initialized The prescaler cannot be read or written 9 4 6 Procedure for Switching System Base Clock Figure 9 4 shows the Flowchart for Clock Switching between XIN Clock Oscillation Circuit Low Speed On Chip Oscillator and High Speed On Chip Oscillator Operating on the clock used before switching Start the clock to be used after switching 1 Start the target clock by a program 2 Assure the wait time for oscillation stabilization Wait for the clock to stabilize by a program
348. ing the FMRO1 bit in the FMRO register to 1 CPU rewrite mode enabled and the FMRO2 bit to 1 EW 1 mode to execute CPU rewrite mode follow the procedure below in EW1 mode Figure 21 9 shows the Procedure for Software Command Execution When Suspend is Disabled Figure 21 10 shows the Procedure for Software Command Execution When Suspend is Enabled When the FMR01 bit is 1 CPU rewrite mode enabled the FMRO2 bit is 1 EW1 mode and the FMR20 bit is 0 suspend disabled Program example for the countermeasure when using the program command First command writing MOV B 40h A1 JMP S CMD2 NOP CMD2 JMP S CMD2 MOV B A0 A1 Second command writing Additional MOV B A1 ROL Dummy read processing LABEL BTST FST7 Flash memory status confirmed JNC LABEL First command writing Specify instruction to be used Additional processing FMR01 FMRO02 Bits in the FMRO register FMR 20 Bit in the FMR2 register FST7 Bit in the FST register Notes 1 When executing the read array command and clear status register command this countermeasure is not necessary 2 Use one of the following instructions for the second command writing e MOV B A0 A1 or MOV B A1 AO MOV B IMM An e MOV B IMM abs16 e MOV B RnH An e MOV B RnH absi6 e MOV B RnL An e MOV B RnL abs16 Use one of the following instructions to read the same address as the second command write address e MOV B An RnL e MOV B An RnH e MOV
349. ingle step vector 1 Watchdog timer oscillation stop detection OFFF4h to OFFF7h me d Reserved L 5 OFFF8h to OFFFBh 107 l Reserved GE 1 OFFFCh to OFFFFh OFS Reset vector Figure 19 2 ID Code Area RO1UH0050EJ0200 Rev 2 00 RENESAS Page 326 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 3 1 Operation The ID code check function is used in standard serial I O mode Its operation differs depending on whether the three bytes in the reset vector at addresses OFFFCh to OFFFEh are FFFFFFh or not If the value is FFFFFFh the ID codes are not examined and all commands are accepted If the value is not FFFFFFh the ID codes stored in the ID code area stored ID code and those sent from the serial programmer or the on chip debugging emulator are examined to see whether they match If they match the commands are accepted Otherwise the commands are not accepted To use the serial programmer or the on chip debugging emulator write predetermined ID codes in advance to the ID code area In addition to the reserved word see 19 3 2 Reserved Words any ID codes can be used The ID code area is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program 19 3 2 Reserved Words The ID code with the character combination ALeRASE in ASCII is the reserved word for the forced erase function The ID code Protect is the reserved word for the standard serial I
350. iodic timer interrupt disabled WDTIF Bit Periodic timer interrupt request flag Condition for setting to 0 e When 0 is written to this bit after reading it as 1 Condition for setting to 1 e When the watchdog timer completes counting an illegal write range RO1UH0050EJ0200 Rev 2 00 RENESAS Page 66 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 3 Operation 8 3 1 Items Common to Multiple Modes 8 3 1 1 Refresh Acceptance Period The period for accepting a refresh operation to the watchdog timer a write to the WDTR register can be selected by bits WDTRCSO to WDTRCS 1 in the OFS2 register Figure 8 2 shows the Watchdog Timer Refresh Acceptance Period When the period from the start of counting to underflow is 100 a refresh operation executed during the acceptance period is accepted as shown below A refresh operation executed during a period other than the acceptance period is processed as an illegal refresh generating a watchdog timer interrupt or watchdog timer reset selected by the RIS bit in the RISR register In addition the UFIF bit in the RISR register is set to 1 Do not perform a refresh operation when the watchdog timer is stopped Watchdog timer period ooo Underflow Refresh acceptance period Refresh acceptable i 100 WDTRCS1 to WDTRCSO 11b Illegal refresh Refresh acceptable 75 WDTRCS1 to WDOTRCSO 10b 1 1 i Illegal refresh Refresh acceptable
351. ion PWM mode 3 outputs PWM2 mode 1 PWM output Serial interface Clock synchronous serial I O Also used for asynchronous serial I O A D converter e Resolution 10 bits x 6 channels Sample and hold function sweep mode Comparator B 2 circuits RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 4 of 426 R8C M11A Group R8C M12A Group 1 Overview Table 1 4 Specifications 2 Function Description Flash memory e Program erase voltage for program ROM VCC 1 8 V to 5 5 V e Program erase voltage for data flash VCC 1 8 V to 5 5 V e Program erase endurance 10 000 times data flash 10 000 times program ROM e Program security ID code check protection enabled by lock bit e Debug functions On chip debug on board flash rewrite function Operating frequency Power supply voltage f XIN 20 MHz VCC 2 7 V to 5 5 V f XIN 5 MHz VCC 1 8 V to 5 5 V Temperature range 20 C to 85 C N version 40 C to 85 C D version 1 Package Note 14 pin TSSOP Package code PTSP0014JA B 14 pin DIP Package code PRDP0014AC A 20 pin LSSOP Package code PLSP0020JB A 20 pin DIP Package code PRDPOO20AD A 1 Specify the D version if it is to be used RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 5 of 426 R8C M11A Group R8C M12A Group 1 Overview 1 2 Product List Table 1 5 lists the Product List Figure 1 1 shows th
352. ion A0 C to 85 C D version unless otherwise specified 2 To use the power on reset function enable the voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0 0 5 V External power Vcc Voltage detection 0 circuit response time Internal reset signal low active Notes 1 VdetO indicates the voltage detection level of the voltage detection 0 circuit For details see 7 Voltage Detection Circuit 2 tw por is required for a power on reset to be enabled with the external power Vcc held below the valid voltage 0 5 V to enable a power on reset When Vcc decreases with voltage monitor 0 reset disabled and then turns on maintain tw por for 1 ms or more Figure 20 3 Power On Reset Circuit Electrical Characteristics RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 374 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 10 High Speed On Chip Oscillator Circuit Electrical Characteristics Parameter High speed on chip oscillator frequency after reset is cleared Package 14 pin TSSOP 20 pin LSSOP 14 pin DIP 20 pin DIP Condition Vcc 1 8 V to 5 5 V 20 C lt Topr lt 85 C Standard Typ 14 pin TSSOP 20 pin LSSOP Vcc 1 8 V to 5 5 V 40 C lt Topr lt 85 C High speed on chip oscillator frequency when the FR18S0 register adjustment value is written into the FRV1 register and the FR18S1 register adjustme
353. ion Select Area Setting Example Bits WDTUFSO to WDTUFS1 Watchdog timer underflow period setting bits These bits are used to select the underflow period for the watchdog timer Bits WDTRCSO to WDTRCS1 Watchdog timer refresh acceptance period setting bits These bits are used to select the refresh acceptance period as a percentage Note that the period from the start of counting to underflow is 100 For details see 8 3 1 1 Refresh Acceptance Period RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 31 of 426 R8C M11A Group R8C M12A Group 5 System Control 5 2 7 Option Function Select Register OFS Address OFFFFh Bit b7 b6 b5 b4 b3 b2 bi bO Symbol CSPROINI LVDAS VDSEL1 VDSELO ROMCP1 ROMCR o o i WDTON After Reset User Setting Value 1 Bit Name Function Watchdog timer start select bit 0 Watchdog timer is automatically started after reset 1 Watchdog timer is stopped after reset Reserved Set to 1 ROMCR ROM code protect disable bit 0 ROM code protect disabled 1 ROMCP1 bit enabled ROMCP1 ROM code protect bit 0 ROM code protect enabled 1 ROM code protect disabled VDSELO Voltage detection 0 level select VDSEL1 bits b5 b4 0 0 3 80 V typ selected Vdet0_3 0 1 2 85 V typ selected Vdet0_2 1 0 2 35 V typ selected Vdet0_1 1 1 1 90 V typ selected Vdet0_0 LVDAS _ Voltage detection 0 circuit start bit 0 Voltage monitor 0 reset enabled after rese
354. ip Oscillator Control Register OCOCR Address 00021h Bit b7 b6 b5 b4 b3 b2 b1 b Ssma T CSHEKESE After Reset 0 0 0 0 0 0 0 0 Function 0 High speed on chip oscillator off 1 High speed on chip oscillator on 0 Low speed on chip oscillator on 1 Low speed on chip oscillator off Bit Name High speed on chip oscillator oscillation enable bit Low speed on chip oscillator oscillation stop bit HOCOE LOCODIS Nothing is assigned The write value must be 0 The read value is 0 Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the OCOCR register HOCOE Bit High speed on chip oscillator oscillation enable bit The high speed on chip oscillator clock generated by the high speed on chip oscillator is stopped after a reset Table 9 4 lists the Register Settings and High Speed On Chip Oscillator States When selecting the high speed on chip oscillator clock as the system base clock switch the clock according to 9 4 6 Procedure for Switching System Base Clock Table 9 4 Register Settings and High Speed On Chip Oscillator States Register CKSTPR SCKCR CKSTPR Bit STPM HSCKSEL SCKSEL Other than 11b Setting Other than 11b Oscillation on value 11b Oscillation on X Oscillation off High Speed On Chip Oscillator State Oscillation off X 0or1 LOCODIS Bit Low speed on chip oscillator oscillation stop bit Table 9 5 lists the Registe
355. ipheral function specifications electrical Group characteristics timing charts and operation R8C M12A Group description User s Manual Note For details on using peripheral functions see Hardware the application notes User s manual Description of CPU instruction set R8C Tiny Series REJO9B0001 Software Software Manual Application note Information on using peripheral functions and Available from Renesas Electronics application examples Web site Sample programs Information on writing programs in assembly language and C Renesas technical Product specifications updates on documents etc update 2 Notation of Numbers and Symbols The notation conventions for register names bit names numbers and symbols used in this manual are described below 1 Register Names Bit Names and Pin Names Registers bits and pins are referred to in the text by symbols The symbol is accompanied by the word register bit or pin to distinguish the three categories Examples the SRST bit in the PMO register P3_5 pin VCC pin 2 Notation of Numbers The indication b is appended to numeric values given in binary format However nothing is appended to the values of single bits The indication h is appended to numeric values given in hexadecimal format Nothing is appended to numeric values given in decimal format Examples Binary 11b Hexadecimal EFAOh Decimal 1234 3 Register Not
356. is Started by TRCTRG Input RO1UHOO050EJ0200 Rev 2 00 stENESAS Page 261 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 4 Selectable Functions 15 4 1 Input Digital Filter for Input Capture Figure 15 19 shows the Digital Filter Circuit Block Diagram The TRCIOA to TRCIOD and TRCTRG input can be latched internally through the digital filter circuit This circuit consists of three cascaded latch circuits and a match detection circuit When the TRCIOA to TRCIOD and TRCTRG input are sampled on the clock selected by bits DFCKO to DFCK1 in the TRCDF register and three outputs from the latch circuits match the level is passed forward to the next circuit If they do not match the previous level is retained That is the pulse input with a width of three sampling clocks or more is recognized as a signal If not the change in the signal is recognized as noise and cancelled Do not use the digital filter immediately after a reset Wait for four cycles of the sampling clock and make the setting for input capture before using the input capture function CKSO to CKS2 fHOCO 32 TRCCLK Sampling clock TRCIOA to TRCIOD or TRCTRG input Timer RC operating clock f1 or fHOCO Clock period selected by CKSO to CKS2 or DFCKO to DFCK1 Sampling clock TRCIOA to TRCIOD or TRCTRG input Input after passing through digital filter aN DFCKO to DFCK1 7 R01UH0050EJ0200 Rev 2 00 May 18 2012 If the o
357. is written to the TRBPR register it is written to the reload register by the third count source TRBPRE reload register Previous value New value 01h Afterjthe value is written to the TRBPR register it is written to the reload register by the third count source TRBPR reload register Previous value New value 25h Reloaded by the next count source V Counter 0307h 0305h 0304h 2501h 2500h When the TWRC bit in TRBMR register is 1 write to reload register only Write 01h to TRBPRE register and 25h to TRBPR register Count source After the value is written to the TRBPR register it is written to the reload register by the third count source TRBPRE reload register Previous value New value 01h After the value is written to the TRBPR register U I itis written to the reload register by the third count source TRBPR reload register Previous value New value 25h Reloaded at underflow i Counter 0307h 0001h 0000h 2501h 2500h Figure 14 12 Example of Counter Operation in 16 Bit Timer Timer Mode or Programmable One Shot Generation Mode R01UH0050EJ0200 Rev 2 00 ztENESAS Page 223 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 When the TWRC bit in TRBMR register is 0 write to reload register and counter Write 01h to TRBPRE register 25h to TRBPR register and 1Ah to TRBSC register eae LLLP After the value is written to the TRBPR register i itis written to the reload
358. ist the pin settings for port 1 Table 12 4 Port P1_0 ANO TRCIOD KIO Register ADINSEL PML1 Bit ADGSEL CHO P10SEL Timer RC Setting Function 1 0 0 Input port Output port Setting A D converter input ANO value See Table 12 24 TRCIOD Pin Settings TRCIOD input See Table 12 24 TRCIOD Pin Settings TRCIOD output X KIO input X 0 or 1 Table 12 5 Port P1_1 AN1 TRCIOA TRCTRG KI1 Register ADINSEL PML1 Bit Setting value ADGSEL CHO P11SEL P 0 0 Timer RC Setting Function Input port Output port A D converter input AN1 See Table 12 21 TRCIOA Pin Settings TRCIOA input or TRCTRG input See Table 12 21 TRCIOA Pin Settings TRCIOA output X KIT input X 0 or 1 Table 12 6 Port P1_2 AN2 TRCIOB KI2 Register ADINSEL PML1 Bit ADGSEL CHO P12SEL Timer RC Setting Function 1 0 0 Input port Output port Setting A D converter input AN2 value See Table 12 22 TRCIOB Pin Settings TRCIOB input See Table 12 22 TRCIOB Pin Settings TRCIOB output D KI2 input X 0 or 1 Table 12 7 Port P1_3 AN3 TRCIOC KI3 TRBO ADINSEL ADGSEL Bit GS CHO PML1 P13SEL Register Timer RB2 Timer RC Setting Function 1 0 1 Setting 0 x x x tolo x X Input port 1 xX X X 0 0 D xX Output port 0 0 1 1 0 0 X
359. ister Comparison between R8C M12A Group and R8C M13B Group For details on the R8C M13B Group registers refer to the R8C M13B Group User s Manual Hardware Appendix Table 4 2 Register Comparison between R8C M12A Group and R8C M13B Group 1 Address 012h Related Function Register System Control MSTCR Remarks Functions added MSTCR1 00017h MSTUART1 MSTTRK MSTICSU MSTIRDA Register added Clock EXCKCR 00020h CKPT1 CKPTO Functions changed XCRCUT XCINNC1 XCINNCO CKPT3 CKPT2 Functions added SCKCR 00022h LSCKSEL Functions added ILVL1 00041h ILVL11 ILVL10 Register added ILVL5 00045h ILVL51 ILVL50 Functions added ILVL7 00047h ILVL75 ILVL74 Functions added ILVL9 00049h ILVL95 ILVL94 Functions added ILVLA 0004Ah ILVLA1 ILALAO Functions added IRRO 00050h IRS1R IRS1T IRTE Functions added IRR1 00051h IRTK IRIS Functions added PDO 000A8h Register added PO OOOAEh Register added PURO 000B4h Register added PODO 000C0h Register added PMLO 000C6h Register added PMHO 000C7h Register added P1 0 P1_2 PMLI P1_4 P1_5 P1_6 000C8h P12SEL1 P12SELO0 P10SEL1 P10SELO Functions changed PME 000C9h P16SEL1 P16SELO P15SEL1 P15SELO0 P14SEL1 P14SELO Functions changed P2 0 P21 P2_2 PbD2 OOOAAh
360. isters Change output pins in registers TRCGRC and TRCGRD as follows e Set the IOC3 bit in the TRCIORI register to 0 TRCIOA output register and the IOD3 bit to 0 TRCIOB output register e Set bits BUFEA and BUFEB in the TRCMR register to 0 general register e Set different values in registers TRCGRA and TRCGRC Also set different values in registers TRCGRB and TRCGRD RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 264 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 22 shows an Operation Example When TRCIOA and TRCIOB Output is not Overlapped The following items must be set e Set the CCLR bit in the TRCCR1 register to 1 TRCCNT counter is cleared by input capture compare match A to clear the counter by a compare match and set the TRCCNT register for period count operation e Set bits IOA2 to IOAO in the TRCIORO register to 011b toggle output from TRCIOA pin at compare match A for toggle output e Set bits IOB2 to IOBO in the TRCIORO register to 011b toggle output from TRCIOB pin at compare match B for toggle output e Set bits IOC3 to IOCO in the TRCIOR1 register to 0011b toggle output from TRCIOA pin at compare match C for toggle output e Set bits IOD3 to IODO in the TRCIORI register to 0011b toggle output from TRCIOB pin at compare match D for toggle output TRCCNT register value Counter cleared by TRCGRA register compare match FFFFh TRCGRA register TRCGRC register TRCGRB register TR
361. it 9 2 9 High Speed On Chip Oscillator 18 432 MHz Control Register 1 FR18S1 Address 00065h Bit b7 b6 b5 b4 b3 b2 b1 bO oml ea Ee After Reset Value when shipped Bit Function R W Pit Function RW b7 to bO Frequency adjustment data for 18 482 MHz is stored The frequency of the high speed on chip oscillator can be adjusted to 18 432 MHz by transferring this value to the FRV2 register and the adjustment value in the FR18S0 register to the FRV1 register 9 2 10 High Speed On Chip Oscillator Control Register 1 FRV1 Address 00067h Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol E After Reset Value when shipped b7 to bO The frequency of the high speed on chip oscillator can be adjusted by setting as follows 20 MHz FRV1 Value after reset FRV2 Value after reset 18 432 MHz Transfer the value in the FR18S0 register to the FRV1 register and the value in the FR18S1 register to the FRV2 register Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the FRV1 register 9 2 11 High Speed On Chip Oscillator Control Register 2 FRV2 Address 00068h Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol l After Reset Value when shipped Bit Function R W Pit Function RW b7 to bO The frequency of the high speed on chip oscillator can be adjusted by setting as follows 20 MHz FRV1 Value after reset FRV2 Value after reset 18 432 MHz Transfer the value in the FR18S0 register t
362. it This bit enables a flash command error interrupt to be generated if the following errors occur e Program error e Block erase error e Command sequence error e Block blank check error e Lock bit program error When the CMDERIE bit is set to 1 interrupt enabled an interrupt is generated if the above errors occur If a flash command error interrupt is generated execute the clear status register command during interrupt handling To change the CMDERIE bit from 0 interrupt disabled to 1 interrupt enabled make the setting as follows 1 Execute the clear status register command 2 Set the CMDERIE bit to 1 BSYAEIE Bit Flash access error interrupt enable bit This bit enables flash access error interrupt generation if the flash memory being rewritten is accessed To change the BSYAEIE bit from 0 flash access error interrupt disabled to 1 flash access error interrupt enabled follow the steps below 1 Read the BSYAEI bit in the FST register dummy read 2 Write 0 no flash access error interrupt requested to the BSYAEI bit 3 Set the BSYAEIE bit to 1 flash access error interrupt enabled RDYSTIE Bit Flash ready status interrupt enable bit This bit enables flash ready status interrupt generation when the status of the flash memory sequence changes from busy to ready To change the RDYSTIE bit from 0 flash ready status interrupt disabled to 1 flash ready status interrupt enabled follow the steps below
363. it disabled set the VW1CO bit to 0 voltage monitor 1 interrupt disabled To set the VW1CO bit to 1 voltage monitor 1 interrupt enabled see Table 7 4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt 2 When the digital filter is used the VW1C1 bit is 0 set the LOCODIS bit in the OCOCR register to 0 low speed on chip oscillator on When the voltage monitor 1 interrupt is used to return from stop mode set the VW1C1 bit to 1 digital filter disabled mode 3 Bits VW1C2 and VW1C3 are enabled when the VC1E bit in the VCA2 register is 1 voltage detection 1 circuit enabled 4 Set this bit to 0 by a program The VW1C2 bit can be set to 0 by writing 0 by a program but writing 1 to this bit has no effect 5 When the VW1CO0 bit is 1 voltage monitor 1 interrupt enabled do not set bits VW1C1 and VW1F0 to VW1F1 at the same time with one instruction 6 The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is 0 one way edge Set the VCAC1 bit to 0 before setting the VW1C7 bit Set the PRC3 bit in the PRCR register to 1 write enabled before rewriting the VWIC register Rewriting the the VWIC register may set the VW1C2 bit to 1 Vdet1 passing detected Rewrite this register before setting the VW1Cz2 bit to 0 not detected RO1UHO050EJ0200 Rev 2 00 RENESAS Page 56 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 3 Monitoring VCC Input Voltage 7 3 1 Monitor
364. it in the OFS register is 1 Bit Name Function Voltage monitor 0 reset enable bit 1 0 Voltage monitor 0 reset disabled 1 Voltage monitor 0 reset enabled Voltage monitor 0 digital filter mode 0 Digital filter enabled mode select bit 2 3 digital filter circuit enabled 1 Digital filter disabled mode digital filter circuit disabled Reserved Set to 0 Reserved The read value is undefined j tc 3 b5 b4 Sampling cock select Dis 0 0 Division of LOCO by 1 no division 0 1 Division of fL OCO by 2 1 0 Division of fLOCO by 4 1 1 Division of fLOCO by 8 Reserved Set to 1 Notes 1 The VWOCO bit is enabled when the VCOE bit in the VCA2 register is 1 voltage detection 0 circuit enabled When the VCOE bit is 0 voltage detection 0 circuit disabled set the VWOCO bit to 0 voltage monitor 0 reset disabled To set the VWOCO bit to 1 voltage monitor 0 reset enabled see Table 7 3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset 2 When the digital filter is used while the VWOC1 bit is 0 set the LOCODIS bit in the OCOCR register to 0 low speed on chip oscillator on When the voltage monitor 0 reset is used to return from stop mode set the VWOC1 bit to 1 digital filter disabled mode 3 When the VWOCO bit is 1 voltage monitor 0 reset enabled do not set bits VWOC1 and VWOFO to VWOF1 at the same time with one instruction Set the PRC3 bit in the PRCR register
365. it in the UOC1 register is changed from 0 the UORB register empty to 1 data present in the UORB register UOTIF Bit UARTO transmit interrupt flag Condition for setting to 0 e When 0 is written to this bit after reading it as 1 Condition for setting to 1 e When the transmit buffer becomes empty or transmission completes RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 285 of 426 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 Operation UARTO supports two modes Clock synchronous serial I O mode and clock asynchronous serial I O UART mode 16 3 1 Clock Synchronous Serial UO Mode In clock synchronous serial I O mode transmission or reception is performed using a transfer clock Table 16 4 lists the Clock Synchronous Serial I O Mode Specifications Table 16 5 lists the Registers and Settings Used in Clock Synchronous Serial I O Mode Table 16 4 Clock Synchronous Serial UO Mode Specifications Transfer data format Transfer data length 8 bits Transfer clock e The CKDIR bit in the UOMR register is 0 internal clock fi 2 n 1 fi f1 f8 or f32 n Value set in the UOBRG register 00h to FFh e The CKDIR bit in the UOMR register is 1 external clock fEXT input from the CLKO pin Transmit start conditions To start transmission the following requirements must be met 1 e The TE bit in the UOC1 register must be 1 transmission enabled e The TI bit in the UOC1 register must be
366. it to 1 reception enabled RO1UH0050EJ0200 Rev 2 00 RENESAS Page 296 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 4 UARTO Interrupt The UARTO interrupt requests are the transmit buffer empty or transmit complete interrupt and the receive complete interrupt Table 16 9 lists the Interrupt Requests Table 16 9 Interrupt Requests Interrupt Request Interrupt Generation Condition UOTIF 1 transmit interrupt requested and UOTIE 1 transmit interrupt enabled Transmit buffer empty Transmit complete Receive complete UORIF 1 receive interrupt requested and UORIE 1 receive interrupt enabled UOTIF UOTIE UORIF UORIE Bits in UOIR register Note 1 The CPU executes interrupt exception handling when the interrupt generation conditions are met and the flag in the FLG register is 1 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 297 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 5 Notes on Serial Interface UARTO Regardless of clock synchronous I O mode or clock asynchronous I O mode read the UORB register in 16 bit units When the UORBH register is read bits FER and PER in the UORB register are set to 0 no framing error no parity error Also the RI bit in the UOC1 register is set to 0 the UORB register empty To check receive errors use the data read from the UORB register e Program example to read the receive
367. ity control bit 1 High drive capacity 1 Port P3_5 drive capacity control bit Nothing is assigned The write value must be 0 The read value is 0 Port P3_7 drive capacity control bit 0 Low drive capacity 1 High drive capacity 1 Note 1 Both H and L output are set to high drive capacity The DRR3 register is used to select the drive capacity of the output transistors low or high when P3 is set to output an output port or a peripheral function output pin The drive capacity of the corresponding output transistors is high when the DRR3_j bit j 3 to 5 or 7 in the DRR3 register is set to 1 RO1UHO050EJ0200 Rev 2 00 RENESAS Page 153 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 4 5 Open Drain Control Register 3 POD3 Address 000C3h Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol POD 7 PODS s PoDs4 Popss After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P3_3 open drain control bit 0 Not open drain Port P3_4 open drain control bit 1 Open drain Port P3_5 open drain control bit Nothing is assigned The write value must be 0 The read value is 0 Port P3_7 open drain control bit 0 Not open drain 1 Open drain The POD3 register is used to select whether the output type is CMOS output or N channel open drain output These settings are enabled when
368. lation circuit constants for the user system RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 388 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 4 Notes on Power Control 21 4 1 Program Restrictions When Entering Wait Mode To enter wait mode by setting the WAITM bit to 1 set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before setting the WAITM bit to 1 To enter wait mode with the WAIT instruction set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction The 4 bytes of instruction data following the instruction that sets the WAITM bit to 1 wait mode is entered or the WAIT instruction are prefetched from the instruction queue and then the program stops Insert at least four NOP instructions after the instruction that sets the WAITM bit to 1 wait mode is entered or after the WAIT instruction e Program example to execute the WAIT instruction BCLR 1 FMRO CPU rewrite mode disabled BCLR 7 FMR2 Low current consumption read mode disabled FSET I Interrupt enabled WAIT Wait mode NOP NOP NOP NOP e Program example to set the WAITM bit to 1 BCLR 1 FMRO CPU rewrite mode disabled BCLR 7 FMR2 Low current consumption read mode disabled BSET 0 PRCR Writing to the SCKCR register enabled FCLR I Interrupt disabled BSET 5 SCKCR Wait mode NOP NOP NOP NOP BCLR 0 PRCR Writing to the SCKCR register disabled FSE
369. ledged the FMR21 bit is Auto erase or auto automatically set to 1 suspend request if the FMR22 bit is 1 programming has priority suspend request enabled by interrupt request Interrupt handling is The flash memory suspends auto erase or auto programming after executed after auto erase td SR SUS and interrupt handling is executed or auto programming When auto erase is being suspended auto programming and reading can be executed for any block other than the blocks being auto erased When auto programming is being suspended any block other than the blocks being auto programmed can be read After interrupt handling completes auto erase or auto programming can be restarted by setting the FMR21 bit is set to 0 restart If the FMR22 bit is set to 0 suspend request disabled by interrupt request auto erasure and auto programming have priority and interrupt requests are put on standby Interrupt handling is executed after auto erase and auto program complete Suspend Enabled FMR20 1 Address match UND INTO and BRK instructions Single step Do not use during auto erasing or auto programming Watchdog timer Oscillation stop detection Voltage monitor 1 When an interrupt request is acknowledged auto erase or auto programming is forcibly stopped immediately and the flash memory is reset After the specified period the flash memory is restarted before interrupt handling is s
370. levels levels 0 to 2 of the maskable interrupts The settings in bits ILVLi0 to ILVLi1 or bits ILVLi4 to ILVLi5 in each register are used to decide the priority of the corresponding interrupt request See Table 11 4 Correspondence between Interrupt Requests and ILVLi i 0 or 2 to E for the interrupt setting bits The interrupt priority level register must be rewritten only while no interrupt requests corresponding to that register are generated See 11 9 7 Changing Interrupt Priority Levels and Flag Registers Table 11 4 ILVLi Register Correspondence between Interrupt Requests and ILVLi i 0 or 2 to E b5 b4 b1 bO ILVLI5 ILVLi4 Flash ready ILVLi1 ILVLiO Comparator B3 Comparator B1 Timer RC Key input A D conversion UARTO transmission UARTO reception INT2 Periodic timer Timer RJ2 INT1 Timer RB2 INT3 Not used The write value must be 0 i O or2toE INTO RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 115 of 426 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 6 Interrupt Monitor Flag Register 0 IRRO Address 00050h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol i Sees ol IRSOR IRSOT IRTC IRTB IRTJ After Reset 0 0 0 0 0 0 0 0 Bit Name Function Timer RJ2 interrupt request monitor flag 0 No interrupt requested Timer RB2 interrupt request monitor flag 1 Interrupt requested Timer RC in
371. limeters D Symbol Min Nom Max D 6 4 6 5 6 6 E 43 44 4 5 s 7 Az 115 A CU ek A 18 f l S Au o 0 1 0 2 Ls ADIs beta F bp 0 17 0 22 0 32 0 13 0 15 0 2 H OF 10 He 6 2 64 6 6 Se 0 53 0 65 0 77 y 010 0 3 0 5 0 7 JEITA Package Code RENESAS Code Previous Code MASS Typ P DIP20 6 6x25 9 2 54 PRDP0020AD A 20P4X A 1 39g Ml Ml gi O SE l l 1 10 NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT 2D INCLUDE TRIM OFFSET I Reference Dimension in Millimeters l a Symbol Min Nom Max z l i e 7 69 Seana BNE D 24 9 25 9 26 9 E 61 66 74 lt A 533 Ai 0 38 E i A2 31 3 3 35 25 iy e by Bp 0 36 0 46 0 56 bs 1 32 1 52 1 72 c 0 21 0 35 6 o 15 a 254 Zo 152 L 29 RO1UHO0O50EJ0200 Rev 2 00 stENESAS Page 416 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 2 Connection Examples between Serial Programmer and On Chip Debugging Emulator Appendix 2 Connection Examples between Serial Programmer and On Chip Debugging Emulator Appendix Figures 2 1 and 2 2 show MF Ten Nine Cable M3A 0652CBL Connection Examples Appendix Figures 2 3 and 2 4 show E8a Emulator ROE00008AKCE00 Connection E
372. llation i circuit Input to external interrupt filter ircui Pull up selection Direction register Pin function mapping register Output from individual peripheral function enabled Output from individual peripheral function Port latch a IOINSEL Pin function mapping register CKPTO to CKPT1 XRCUT Bits in EXCKCR register STPM Bit in CKSTPR register IOINSEL Bit in PINSR register Figure 12 17 UO Port Configuration 12 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 175 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports RESET PA_0 Direction register Cc j kd Open drain K HWRSTE i selection lt q FI Kon 4 RESET input signal IOINSEL Bit in PINSR register HWRSTE Bit in PAMCR register Figure 12 18 UO Port Configuration 13 MODE input signal Si Figure 12 19 Pin Configuration RO1UHO050EJ0200 Rev 2 00 stENESAS Page 176 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 11 Notes on I O Ports 12 11 1 Notes on PA_0 Pin The PA_0 pin is multiplexed with the hardware reset function RESET The PA_0 pin functions as the RESET function after any reset hardware reset power on reset voltage monitor 0 reset by voltage detection circuit watchdog timer reset and software reset occurs After the reset is cleared the PA_O pin can be set to the I O port function or the hardware reset function by the HWRSTE bit in the PAMCR register
373. lock selected by bits CKS2 to CKSO in the TRCCR1 register Notes 1 Enabled in the input capture function 2 Enabled when in PWM2 mode and bits TCEG1 to TCEGO in the TRCCR2 register are set to 01b 10b or 11b TRCTRG trigger input enabled RO1UHO050EJ0200 Rev 2 00 RENESAS Page 242 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 11 Timer RC Output Enable Register TRCOER Address 000FAh Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo Po e eA After Reset 0 1 1 1 1 1 1 1 Bit Name Function TRCIOA output disable When the OPE bit in the TRCOPR register is 0 waveform bit 3 output manipulation disabled 1 TRCIOB output disable 0 Output enabled bit 3 dependent on settings of registers TRCMR and TRCIORO 1 Output disabled independent of settings of registers TRCMR and TRCIORO When the OPE bit in the TRCOPR register is 1 waveform output manipulation enabled 2 0 Output enabled dependent on settings of registers TRCMR and TRCIORO 1 Output level is fixed or high impedance depending on TRCOPR register setting TRCIOC output disable When the OPE bit in the TRCOPR register is 0 waveform bit 3 output manipulation disabled 1 TRCIOD output disable 0 Output enabled bit 3 dependent on settings of registers TRCMR and TRCIOR1 1 Output disabled independent of settings of registers TRCMR and TRCIOR1 When the OPE bit in the TRCOPR register is 1 waveform output
374. log input pins are divided into three channel groups Table 17 2 A D Converter Pin Configuration Pin Name Assigned Pin ADMOD register ADINSEL register ADCONDO register ADICSR register A D conversion interrupt Conversion start trigger from timer RC Function Power supply input for the A D converter Analog input for channel group 0 Analog input for channel group 1 Analog input for channel group 2 External trigger input for starting A D conversion RO1UHOO50EJ0200 Rev 2 00 May 18 2012 RENESAS Page 300 of 426 R8C M11A Group R8C M12A Group 17 A D Converter 17 2 Registers Table 17 3 lists the A D Converter Register Configuration Table 17 3 A D Converter Register Configuration Register Name After Reset Address Access Size A D Register 0 Lower 8 bits ADOL XXh 00098h 8 or 16 1 Higher 2 bits ADOH 000000XXb 00099h A D Register 1 Lower 8 bits ADIL XXh 0009Ah Higher 2 bits AD1H 000000XXb 0009Bh A D Mode Register ADMOD 00h 0009Ch A D Input Select Register ADINSEL 00h 0009Dh A D Control Register 0 ADCONO 00h 0009Eh A D Interrupt Control Status Register ADICSR 00h 0009Fh X Undefined Note 1 For details on access see the description of the individual registers R01UH0050EJ0200 Rev 2 00 RENESAS Page 301 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 2 1 A D Register i ADi i 0 or 1 Addr
375. low after the TSTART bit is set to 1 count is started the signal is not counted on the falling edge Thus the number of counted events is obtained as follows Number of counted events initial value in the counter value in the counter on completion of the valid event 1 1 To avoid this set the TSTART bit to 1 count is started and input a valid event after setting the TRJIO pin to low see Figure 13 11 TRUJIO pin TEDGSEL bit in d TRJIOC register H H TSTART bit in TRJCR register Not counted on first falling edge Count source D Counter 0503h initial value 0502h 0501h 0500h 04FFh 04FEh 04FDh 04FCh Figure 13 10 External Pulse Signal Timing in Event Counter Mode 1 TRUJIO pin TEDGSEL bit in TRJIOC register TSTART bit in TRJCR register Count source Counter 0503h initial value 0502h 0501h 0500h 04FFh 04FEh 04FDh 04FCh Figure 13 11 External Pulse Signal Timing in Event Counter Mode 2 R01UH0050EJ0200 Rev 2 00 RENESAS Page 195 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 Timer RB2 Timer RB2 can be used as an 8 bit timer with an 8 bit prescaler or as a 16 bit timer The prescaler and timer each consist of a reload register and counter which are allocated to the same address Timer RB2 has timer RB primary and timer RB secondary reload registers 14 1 Overview Table 14 1 lists the Timer RB2 Specifications Figure 14 1 shows the Timer RB2 Block Diagr
376. lower than the reference input voltage the WCBiOUT bit is set to 0 When a comparator Bi interrupt i 1 or 3 is used set the WCBiINTEN bit in the WCBiINTR register to 1 interrupt enabled If the comparison result changes at this time a comparator Bi interrupt request is generated For details on interrupts see 11 Interrupts RO1UHO050EJ0200 Rev 2 00 May 18 2012 RENESAS Page 322 of 426 R8C M11A Group R8C M12A Group 18 Comparator B IVCMPi Reference input IVREFi voltage Ge E SZ o D bal o gt Z a D OG bel E Ka WCBIiOUT bit in WCMPR register WCBIF bit in WCBIINTR register Set to 0 by a program i 1or3 The above diagram applies under the following conditions e Bits WCBiF1 to WCBIFO 00b no filter bits WCBiS1 to WCBiSO 11b when the analog input voltage is lower or higher than the reference input voltage in WCBiINTR register Figure 18 3 Example of Comparator Bi i 1 or 3 Operation RO1UH0050EJ0200 Rev 2 00 RENESAS Page 323 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 Flash Memory The flash memory supports two rewrite modes CPU rewrite mode and standard serial I O mode 19 1 Overview Table 19 1 lists the Flash Memory Specifications see Tables 1 3 and 1 4 Specifications for items not listed in Table 19 1 Table 19 2 outlines Flash Memory Rewrite Mode Table 19 1 Flash Memory Specifications Item Specification
377. lse This timer consists of a reload register and down counter which are allocated to the same address 13 1 Overview Table 13 1 lists the Timer RJ2 Specifications Figure 13 1 shows the Timer RJ2 Block Diagram Table 13 1 Timer RJ2 Specifications Operating modes Timer mode The internal count source is counted Pulse output mode The internal count source is counted and the output is inverted at each underflow of the timer Event counter mode An external pulse is counted Pulse width measurement mode An external pulse width is measured Pulse period measurement mode An external pulse period is measured Count source f1 f2 f8 fHOCO or external pulse selectable Interrupt e When the counter underflows e When the measurement of the active width of the external input TRJIO is completed in pulse width measurement mode e When the set edge of the external input TRJIO is input in pulse period measurement mode RO1UHOO050EJ0200 Rev 2 00 May 18 2012 RENESAS Page 178 of 426 R8C M11A Group R8C M12A Group 13 Timer RJ2 TCK2 to TCKO 000b ao 010b O fHOCO o ep Dn TIOGT1 to TIOGTO Event is always counted 00b Q Event is counted only during op INTZ high level period O Event is counted during specified SE RC output signal period TCKCUT TSTART ag TRCIOD ib TMOD2 to register TRCIOC TMODO RCCPSEL2 TRCIOB COPS other than Un
378. lter circuit is the sampling clock x 2 Bits VWiF1 to VWiFO in VWiC register 00b Sampling clock Voltage detection c Filter output i signal Voltage detection i signal Sampling clock If the sampled output does not match i 0 1 twice it is assumed to be noise and not transmitted Note 1 After the voltage detection 0 signal is recognized as low a voltage monitor 0 reset is generated Thus only the falling edge of the voltage detection signal is enabled for the voltage monitor 0 filter Figure 7 6 Block Diagram of Voltage Detection Circuit Digital Filter RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 61 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 Watchdog Timer The watchdog timer is a function for detecting program malfunctions Using this function is recommended since it can improve system reliability The watchdog timer also has a function that can be used as a periodic timer 8 1 Overview The watchdog timer has a 14 bit down counter and count source protection mode can be enabled or disabled Table 8 1 lists the Watchdog Timer Specifications For details on the watchdog timer reset see 6 3 5 Watchdog Timer Reset For details on the periodic timer see 8 3 4 Periodic Timer Function Figure 8 1 shows the Watchdog Timer Block Diagram Table 8 1 Watchdog Timer Specifications Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled Count source
379. lue is read from the prescaler In the 16 bit timer the TRBPRE register is used as the lower 8 bit counter Each time the counter decrements and underflows the value in the TRBPRE register is reloaded When read the value is read from the lower 8 bits of the counter Access the TRBPRE register first and then the TRBPR register The TRBPRE register is configured with a master reload register structure so the reload register is written simultaneously while the count is stopped During the counter operation the timing for updating the reload register differs in each mode For details see Table 14 6 Reload Register Update Timing for Registers TRBPR and TRBSC in 8 Bit Timer with 8 Bit Prescaler and Table 14 7 Reload Register Update Timing for Registers TRBPRE TRBPR and TRBSC in 16 Bit Timer The value is updated in synchronization with the count source RO1UH0050EJ0200 Rev 2 00 RENESAS Page 203 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 6 Timer RB Primary Register TRBPR Address 000E5h Bit b 7 b6 b5 b4 b3 b2 b1 bO yee A ee ee a ee 2 E After Reset 1 1 b7 to bO Timer mode Function 8 Bit Timer with 8 Bit Prescaler Timer RB prescaler underflow is counted Programmable waveform generation mode Timer RB prescaler underflow is counted 1 Programmable one shot generation mode Timer RB prescaler underflow is counted the one shot width is counted Progr
380. m ROM area When 71h written as the first command and DOh is written to the start address in the block with the second command the lock bit status in the specified block is stored in the FST2 bit in the FST register Read the FST2 bit after the FST7 bit in the FST register has changed to 1 ready Figure 19 17 shows the Read Lock Bit Status Flowchart Write the command code 71h Write DOh to the start address in the block Block not locked Block locked FST2 FST7 Bits in FST register Figure 19 17 Read Lock Bit Status Flowchart RO1UHO050Ev0200 Rev 2 00 stENESAS Page 354 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 6 7 Block Blank Check This command is used to confirm that all addresses in any block are blank data FFh When 25h is written as the first command and DOh is written to any address in the block with the second command a blank check is started for the specified block The FST7 bit in the FST register can be used to confirm whether blank check is completed The FST7 bit is set to 0 during the blank check period and changed to when the blank check has completed After the blank check has completed the result can be determined by reading the FST5 bit in the FST register see 19 6 7 Full Status Check This command is also used to verify the target block has not been written To confirm whether erase has completed normally execute the full status check Do not exe
381. manipulation enabled 2 0 Output enabled dependent on settings of registers TRCMR and TRCIOR1 1 Output level is fixed or high impedance depending on TRCOPR register setting Nothing is assigned The write value must be 1 The read value is 1 Timer output disable bit When the OPE bit in the TRCOPR register is 0 waveform output manipulation disabled 0 Bits EA to ED do not change even if a low level is input to the INTO pin _ 1 When a low level is input to the INTO pin bits EA to ED are set to 1 output disabled For INTO see 11 Interrupts When the OPE bit in the TRCOPR register is 1 waveform output manipulation enabled The function of the PTO bit is disabled bits EA to ED do not change even if a low level is input to the INTO pin This bit can be read or written Notes 1 Bits EA to ED can be set by software When the PTO bit is 1 and a low level is input to the INTO pin bits EA to ED are set to 1 output disabled _ 2 Regardless of the set value of the PTO bit bits EA to ED do not change even if a low level is input to the INTO pin When the RESTATS bit in the TRCOPR register is 1 bits EA to ED cannot be set by software When the waveform output manipulation event selected by bits OPSELO to OPSEL1 in the TRCOPR register is input bits EA to ED are set to 1 If the waveform output manipulation event is cancelled bits EA to ED are set to 0 When the RESTATS bit is 0 bi
382. me TRCCNT register value FFFFh DA91h F i 5480h L i Li 1 I Li I 0245h r F Li 0000h 7 1 i H D TRCIOA f t f U TRCGRA register 0245h 5480h 0245h TRCGRC register Figure 15 8 Example of Buffer Operation during Input Capture RO1UH0050EJ0200 Rev 2 00 RENESAS Page 250 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 3 2 PWM Mode In PWM mode when the TRCGRA register is set as the period register and registers TRCGRB TRCGRC and TRCGRD are set as duty registers a PWM waveform is output from pins TRCIOB TRCIOC and TRCIOD individually A PWM waveform with up to three phases can be output In this mode the general register automatically functions as an output compare register The settings of bits IOB2 IOC2 and IOD2 are invalid The initial output level of the corresponding pin is set according to the values in bits TOA to TOD in the TRCCRI register and bits POLB to POLD in the TRCCR2 register Table 15 15 lists the Initial Output Levels of TRCIOB Pin Table 15 15 Initial Output Levels of TRCIOB Pin TOB Bit in TRCCR1 Register POLB Bit in TRCCR2 Register Initial Output Level 0 1 0 1 0 0 0 1 1 The output level is determined by bits POLB to POLD in the TRCCR2 register When the POLB bit is 0 output level is active low the TRCIOB output pin is set to low at compare match B and high at compare match A When the POLB bit is output level is a
383. n I Input port IVREF1 Output port CLKO external clock input CLKO internal clock output TRJO output See Table 12 22 TRCIOB Pin Settings TRCIOB input See Table 12 22 TRCIOB Pin Settings TRCIOB output X X X Setting X value X X X o X X gt lt N x x X o x x x X X X x x X 0or1 Table 12 11 Port P1_7 AN7 IVCMP1 INT1 TRJIO TRCCLK Register ADINSEL PML1 TRJIOC TRJMR ADGSEL P17SEL TMOD Function Bit i 0 CHO i 0 TOPCR z J 0 0 x X X Input port 0 X X X Output port 0 X X X A D converter input AN7 SE 0 1 D X INTI input 1 Other than 000b 001b TRJIO input 1 001b TRJIO pulse output 1 X X TRCCLK input X 0 or 1 RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 150 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 4 Port3 Figure 12 2 shows the Port 3 Pin Configuration P3_3 IVCMP3 TRCCLK INT3 P3_4 IVREF3 TRCIOC INT2 P3_5 TRCIOD KI2 VCOUT3 P3_7 ADTRG TRJO TRCIOD Figure 12 2 Port 3 Pin Configuration RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 151 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 4 1 Port P3 Direction Register PD3 Address 000ABh Bit b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD 7 Poss Pa e After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The rea
384. n is guaranteed for any number of operations in the range of 1 to the specified minimum Min 4 Ina system that executes multiple program operations the actual erase count can be reduced by shifting the write addresses in sequence and programming so that as much of the flash memory as possible is used before performing an erase operation For example when programming in 16 byte units the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one operation It is also advisable to retain data on the number of erase operations for each block and establish a limit for the number of erase operations performed 5 If an error occurs during a block erase execute a clear status register command and then a block erase command at least three times until the erase error does not occur 6 For information on the program erase failure rate contact a Renesas technical support representative 7 The data hold time includes the time that the power supply is off and the time the clock is not supplied Suspend request FMR21 i i FST7 i 1 FST6 f Clock dependent i Fixed time time Li H H H H aS FST6 FST7 Bits in FST register FMR21 Bit in FMR2 register Figure 20 2 Transition Time until Suspend RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 372 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 2
385. n the OFS2 register RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 62 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer Prescaler WDTC7 to WDTC6 CPU clock fs 14 bit watchdog timer 1 O CSPRO 1 WDTUFSO Underflow Selected underflow period WDTUFS1 period and WDTRCSO refresh range WDTRCS1 selection Underflow Selected refresh range RIS 0 Watchdog timer interrupt Watchdog timer value Watchdog timer initialization Write to WDTR register RIS 1 Illegal Watchdog timer refresh reset Periodic timer interrupt Note 1 The value set by bits WOTUFSO and WDTUFS1 is set value when shipped 3FFFh RIS Bit in RISR register WDTC6 to WDTC7 Bits in WDTC register CSPRO Bit in CSPR register WDTIF WDTIE Bits in WDTIR register WDTUFSO WDTUFS1 WDTRCSO WDTRCS1 Bits in OFS2 register Figure 8 1 Watchdog Timer Block Diagram RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 63 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 2 Registers Table 8 2 lists the Watchdog Timer Register Configuration Table 8 2 Watchdog Timer Register Configuration Register Name Watchdog Timer Function Register After Reset Note 1 Address 00030h Access Size Watchdog Timer Reset Register XXh 00031h Watchdog Timer Start Register XXh 00032h Watchdog Timer Control Register 01XXXXXXb 00033h Count Source Protection Mode Register
386. n the TRBIOC register to 1 one shot trigger to INTO pin enabled When an interrupt request is generated by the trigger input from the INTO pin note the following e Set bits INTOSA to INTOSB in the ISCRO register to select the falling edge rising edge or two way edge for the interrupt Even if a one shot trigger is generated while the TOSSTF bit in the TRBOCR is 1 one shot is operating including wait period timer RB2 operation is not influenced but the IRIO bit in the IRR3 register is changed For details on interrupts see 11 Interrupts RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 226 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 8 Notes on Timer RB2 e Timer RB2 stops counting after a reset Start the count after setting the value in the timer and prescaler e In the 8 bit timer with 8 bit prescaler even if the prescaler and timer are read in 16 bit units they are actually read sequentially byte by byte in the MCU This may cause the value in the timer to be updated during reading of these two registers In the 16 bit timer access the TRBPRE register first and then the TRBPR register Read the TRBPRE register first to read the count value in the lower byte The count value in the higher byte will be retained Next read the TRBPR register to read the retained value in the higher byte The timer value is not updated during reading of these two registers e In programmable one shot and programmable w
387. n to this bit e When the MCU returns from wait mode when the WAITRS bit in the CKRSCR register is 1 AHSCK e When the MCU returns from stop mode when the STOPRS bit in the CKRSCR register is 1 fHSCK RO1UHO050EJ0200 Rev 2 00 RENESAS Page 80 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 6 Clock Control Register When Returning from Modes CKRSCR Address 00025h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol STOPAS WATRS PHISAS J OKSTS CKST2 een Coren 0 0 0 0 0 0 0 After Reset 0 Bit Name Function Clock oscillator circuit oscillation Number of wait states stabilization state select bits b3 b2 b1 b0 0000 4 0001 16 0010 0011 0100 0101 0110 0111 1000 1001 1 1 0 0 1 1 262144 Nothing is assigned The write value must be 0 The read value is 0 PHISRS CPU clock division select bit when 0 The value set in bits PHISSELO to PHISSEL2 in returning from wait mode or stop the SCKCR register is valid mode No division WAITRS System base clock select bit when Return using the system base clock used returning from wait mode immediately before entering wait mode fHSCK 1 2 STOPRS System base clock select bit when Return using the system base clock used returning from stop mode immediately before entering stop mode fHSCK 1 2 Notes 1 When the HSCKSEL bit in the SCKCR register is 0 XIN clock set pins P4_6 a
388. nction enabled Output from individual peripheral function Port latch a Pin function Input to individual peripheral function mapping register Drive capacity selection IOINSEL Bit in PINSR register Figure 12 14 UO Port Configuration 9 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 173 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Pull up selection Direction register Pin function mapping register Output from individual peripheral function enabled e Output from individual peripheral function Port latch Es Pin function mapping register IOINSEL Bit in PINSR register Figure 12 15 UO Port Configuration 10 Pull up selection Direction register Pin function mapping register Open drain _ _ Output from O 2 individual peripheral selection function enabled Output from individual peripheral function Pin function mapping register IOINSEL Bit in PINSR register Figure 12 16 UO Port Configuration 11 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 174 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Pull up selection Pin function mapping register Output from individual peripheral Direction register A function enabled Output from individual peripheral function Port latch Pin function CKPT1 to Input to individual peripheral function mapping register CKPTO other than 11b Digital XIN osci
389. nd P4_7 to XIN oscillation by a program before entering wait mode or stop mode 2 Set this bit to 0 before entering wait mode or stop mode if the FMR27 bit in the FMR2 register is set to 1 low current consumption read mode enabled Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the CKRSCR register RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 81 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit Bits CKSTO to CKST3 Clock oscillator circuit oscillation stabilization state select bits These bits are used to set the oscillation stabilization time of the oscillator circuit for the system base clock when returning wait mode or stop mode Set appropriate values according to Table 9 7 Table 9 7 Oscillation Stabilization Time When Returning Wait Mode or Stop Mode System Base Clock Stabilization Time Setting Value for Number of Wait States after Returning Automatic Generation Bits CKSTO to CKST3 XIN clock XIN clock period x system clock division Contact the oscillator manufacturer ratio x number of wait states High speed on chip High speed on chip oscillator clock period See Table 20 10 High Speed On Chip oscillator clock x system clock division ratio x number of Oscillator Circuit Electrical Characteristics wait states Low speed on chip Low speed on chip oscillator clock period Value set in CKSTO to CKSTS3 is invalid oscillator clock x system clock division ratio
390. nde a Tee a yes ere Se E IE EN O EEE EEEE eng aes 12 2 8 3 Zero HIE WEE 12 2 8 4 Sie RS EE 12 2 8 5 Register Bank Select Flag B tegen EE EEEE tye sche ston dea sbestee sisne ae E STe SERES ro EESE osre e aoaie 12 2 8 6 Overflow Flag OH code tel eater iene E eae neh ea a ee a ee ae 12 2 8 7 Interrupt Fnable Plap D eebe Ee eelere ee 13 2 8 8 stack Pointer Select Flas U sree t ni ca caeunceuanteuan tel E A E E RE EEN Een 13 2 8 9 Processor Interrupt Priority Level IPL essseessssesseseesrsresesresreersresreresseresretstentesrssestsseetnsrsrerrsrentereneses 13 28 40 Reserved D EE 13 3 ele 14 3 1 Memory Map age aco EE seb a EE 14 3 2 Special Function Registers SFRS oe eri eoi riea aea aere EIE EESE Coes SEE EEEE E Sae EREE EE SEa KOENE eis 15 4 Bus OOO T a a e A a a ae 24 5 System Control EE 25 5 1 DEENEN E E E E EA E EA E E E EE 25 5 2 LE 25 5 2 1 Processor Mode Register O PMOU 4 cecteescessnstenteesciih nea eeo enake EEEE E EN ESEE E E E KE E EEEa eia 26 5 2 2 Module Standby Control Register MSTCR oon eeececeseceeeeeeeseecaecseecaecaeceaeaecsseeseseseseseaesaeeeasaeenaes 27 5 2 3 Protect Register PRERE A R NEE ENEE E i acs eee 28 5 2 4 Hardware Reset Protect Register HRPR AA 28 5 2 5 Reset Source Determination Register RSTFR A 29 5 2 6 Option Function Select Register 2 OFS2 oo ceeeeseececeseeeeceeeeeeeeseecsecaaecaecsaesaecsecsaeceseeseseeeeeeeeseneeegs 31 5 2 7 Option Function Select Register OFS scs
391. ng is assigned The write value must be 1 The read value is 1 RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 244 of 426 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 13 Timer RC Waveform Output Manipulation Register TRCOPR Address 000FCh Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol OPE RESTATS OPOL1 OPOLO OPSEL1 OPSELO After Reset 0 0 0 0 0 0 0 0 Bit Name Function b1 b Geser cate 0 0 Waveform output is manipulated during low level period of select bits 1 comparator B1 VCOUT1 output level 0 1 Waveform output is manipulated during low level period of INT1 input level Other than the above Waveform output is manipulated during low level period of comparator B1 VCOUT1 output level or INT1 input level Waveform output manipulation period output level select bits When timer RC pin is pulled down timer RC output level is fixed to high impedance during waveform output manipulation period When timer RC pin is pulled up timer RC output level is fixed to high impedance during waveform output manipulation period 1 0 Timer RC output level is fixed at low during waveform output manipulation period 1 1 Timer RC output level is fixed at high during waveform output manipulation period RESTATS Restart method select 0 Output is restarted by software 3 bit 2 1 Output is automatically restarted 4 Waveform output 0 Waveform output manipulation disabled mani
392. nitial level TRCCNT register value FFFFh TRCGRA register TRCGRB register TRCGRC register 0000h CTS TRCIOA TRCTRG TRCIOB output change when TOB 0 TRCIOB output change when TOB 1 CTS Bit in TRCMR register TOB Bit in TRCCR1 register Figure 15 16 Example of Count Stop Operation in PWM2 Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 259 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 17 shows an Example of One Shot Pulse Waveform Output Operation in PWM2 Mode The count is started when the CTS bit in the TRCMR register is set to 1 count is started under the following conditions Then the counter is changed to 0000h by a compare match with the TRCGRA register the count operation is stopped and a one shot waveform is output e Bits TCEG1 to TCEGO in the TRCCR2 register are set to 00b TRCTRG input disabled to disable the TRCTRG input e The CSTP bit in the TRCCR2 register is set to 1 increment is stopped to stop the increment when compare match A with the TRCGRA register occurs e The CCLR bit in the TRCCRI register is set to 1 TRCCNT counter is cleared by input capture compare match A to clear the TRCCNT register by compare match A e The TOB bit in the TRCCR 1 register is set to O output value 0 to set the initial value of the output level to 0 TRCCNT register value FFFFh TRCGRA register TRCGRB register TRCGRC register 0000h TRCIOA TROTRG b
393. nput If the input to the TRJIO pin is sampled and the value matches three successive times that value is taken as the input value Bits TIOGTO to TIOGT1 TRJIO count control bits These bits are enabled only in event counter mode They are used to select the period to count an event input from the TRJIO pin When bits TIOGT1 to TIOGTO are set to 00b an event is always counted When bits TIOGT1 to TIOGTO are set to 01b an event is counted while the INT2 pin is held high When bits TIOGT1 to TIOGTO are set to 10b an event is counted for the period corresponding to the timer RC output set by the TRJISR register Bits RCCPSELO to RCCPSEL1 in the TRJISR register are used to select the timer RC output signal and the RCCPSEL2 bit is used to select the level of the timer RC output signal RO1UH0050EJ0200 Rev 2 00 RENESAS Page 183 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 3 4 Timer RJ Mode Register TRJMR Address 000DCh Bit b 7 b6 b5 b4 b3 b2 b1 b Symbol 0 0 0 0 0 0 0 0 After Reset Bit Name Timer RJ operating mode select bits Function b2 b1 b 0 0 0 Timer mode 0 0 1 Pulse output mode 0 1 0 Event counter mode 0 1 1 Pulse width measurement mode 1 0 0 Pulse period measurement mode Other than the above Do not set TEDGPL TRJIO edge polarity select bit 0 One way edge 1 Two way edge TCKO TCK1 TCK2 Timer RJ count source select bits 1 2
394. nput cycle time 500 tWH TRJIO TRJIO input high width 200 twL TRJIO TRUIO input low width 200 tC TRJIO Vcc 2 2 V TRJIO input Figure 20 13 TRJIO Input Timing When Vcc 2 2 V R01UH0050EJ0200 Rev 2 00 ztENESAS Page 386 of 426 May 18 2012 R8C M11A Group R8C M12A Group 20 Electrical Characteristics Table 20 29 Serial Interface Standard Parameter Min te Ck CLKO input cycle time tw CKH CLKO input high width tW CKL CLKO input low width ta C Q TXDO output delay time th C Q TXDO hold time tsu D C RXDO input setup time th C D RXDO input hold time Figure 20 14 Serial Interface Timing When Vcc 2 2 V Table 20 30 External Interrupt INTi Input Key Input Interrupt Kli i 0 to 3 Standard Min Parameter tw INH INTI input high width KI input high width tW INL INTI input low width Kli input low width 1 When the digital filter is enabled by the INTI input filter select bit the INTI input high width is 1 digital filter clock frequency x 3 or the minimum value of the standard whichever is greater SEN 2 When the digital filter is enabled by the INTi input filter select bit the INTi input low width is 1 digital filter clock frequency x 3 or the minimum value of the standard whichever is greater Vcc 2 2 V Figure 20 15 Timing for External Interrupt INTi Input and Key Input Interrupt Kli When Vcc 2 2 V
395. nput to individual peripheral function mapping register Analog voltage input to comparator B So Drive capacity selection Input to external interrupt IOINSEL Bit in PINSR register Figure 12 11 1 O Port Configuration 6 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 171 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Drive capacity selection Pull up selection Direction register Pin function mapping register Output from individual peripheral function enabled Output from individual peripheral function Port latch a Pin function Input to individual peripheral function mapping register Reference input to comparator B a Drive capacity selection Input to external interrupt IOINSEL Bit in PINSR register Figure 12 12 UO Port Configuration 7 R01UH0050EJ0200 Rev 2 00 ztENESAS Page 172 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports Drive capacity selection Pull up selection Direction Pin function mapping register Open drain Output from O s individual peripheral selection lt function enabled Output from individual peripheral function Pin function mapping register Drive capacity selection IOINSEL Bit in PINSR register Figure 12 13 UO Port Configuration 8 Drive capacity selection Pull up selection Direction register Pin function mapping register Output from individual peripheral fu
396. nt is in progress before writing 1 one shot count is started to the TOSST bit in the TRBOCR register When the TCSTF bit is 0 count is stopped writing 1 one shot count is started to the TOSST bit is invalid e When writing to registers TRBPRE TRBPR and TRBSC during count operation the TSTART bit is 1 or the TCSTF bit is 1 note the following points When writing to the TRBPRE register successively allow at least three cycles of the count source for each write interval When writing to the TRBPR register successively allow at least three cycles of the count source for each write interval When writing to the TRBSC register successively allow at least three cycles of the count source for each write interval e When the TRBPR register is rewritten in programmable waveform generation mode do not write to the TRBPRE TRBPR or TRBSC register during the secondary output period as described below after rewriting 8 bit timer with 8 bit prescaler Two cycles of the prescaler underflow before the secondary output period ends 16 bit timer Two cycles of the count source clock before the secondary output period ends e When the underflow signal from timer RJ2 is used as the count source for timer RB2 set timer RJ2 to timer mode pulse output mode or event counter mode RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 399 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes e When 1 is written to the TOSST bit o
397. nt value into the FRV2 register 2 14 pin TSSOP 20 pin LSSOP 14 pin DIP 20 pin DIP Vcc 1 8 V to 5 5 V 20 C lt Topr lt 85 C 14 pin TSSOP 20 pin LSSOP Vcc 1 8 V to 5 5 V 40 C lt Topr lt 85 C Oscillation stabilization time Notes Self power consumption at oscillation Vcc 5 0 V Topr 25 C 1 Vcc 1 8 V to 5 5 V Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified 2 This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0 when the serial interface is used in UART mode Table 20 11 Parameter Low speed on chip oscillator frequency Condition Low Speed On Chip Oscillator Circuit Electrical Characteristics Standard Oscillation stabilization time Note Self power consumption at oscillation Vcc 5 0 V Topr 25 C 1 Vcc 1 8 V to 5 5 V Topr 20 C to 85 C N version 40 C to 85 C D version unless otherwise specified Table 20 12 Power Supply Circuit Timing Characteristics d P R Time for internal oe supply stabilization 2 oa during power on Notes 1 The measurement condition is Vcc 1 8 V to 5 5 V and Topr 25 C 2 Wait time until the internal power supply generation circuit stabilizes during power on Condition Standard Unit R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS P
398. nterrupt vector Figure 11 2 shows an Interrupt Vector Vector address L Lower address Middle address Higher address Vector address H 0000 Figure 11 2 Interrupt Vector 11 3 1 Fixed Vector Table The fixed vector table is allocated to addresses OFFDCh to OFFFFh Table 11 5 lists the Fixed Vector Table The vector addresses H of the fixed vectors are used by the ID code check function For details see 19 3 ID Code Check Function Table 11 5 Fixed Vector Table Interrupt Source vector Adaress Remarks Address L to Address H Undefined instruction OFFDCh to OFFDFh Interrupt by the UND instruction Overflow OFFEOh to OFFE3Sh Interrupt by the INTO instruction BRK instruction OFFE4h to OFFE7h If the content of address OFFE6h is FFh program execution starts from the address indicated by the vector in the relocatable vector table Address match OFFE8h to OFFEBh Single step 1 OFFECh to OFFEFh Watchdog timer oscillation stop detection OFFFOh to OFFF3h voltage monitor 1 Reserved OFFF4h to OFFF7h Reserved OFFF8h to OFFFBh Reset OFFFCh to OFFFFh Note 1 Do not use this interrupt It is provided exclusively for use in development tools RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 120 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 3 2 Relocatable Vector Table The relocatable vector table occupies 256 bytes beginning from the start address set in the INTB regi
399. o be used to return from stop mode 2 Set the I flag to 1 maskable interrupt enabled 3 Operate the peripheral function to be used to return from stop mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 102 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control The system base clock when returning from stop mode by a peripheral interrupt is the clock set by the STOPRS bit in the CKRSCR register At this time bits PHISSELO to PHISSEL 2 in the SCKCR register and the SCKSEL bit in the CKSTPR register are automatically changed according to bits PHISRS and STOPRS When an interrupt is generated oscillation is started and a period until the clock supply oscillation stabilization time is generated automatically If the system base clock when returning is the XIN clock set pins P4_6 and P4_7 to XIN oscillation by a program before entering stop mode Depending on the clock to be used set appropriate values for oscillation stabilization time using bits CKSTO to CKST3 in the CKRSCR register It is unnecessary to generate a wait time by a program FMRO Register Internal Power Time until Flash Stabilization Memory Activation Clock Stabilization Time until CPU Time for Interrupt EMSTP bit Time T0 T1 Time T2 Clock Supply T3 Sequence T4 0 flash memory 100 us max 60 ps max operates Set by bits CKSTO CPU clock period CPU clock period to CKST3 in the x x CKRSCR register 2 cycles 20 cycl
400. o programming after interrupt handling is completed RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 339 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 3 Suspend Operation The erase suspend function temporarily halts the auto erase during the operation The program suspend function temporarily halts the auto programming during the operation When auto erase or auto programming is suspended the following operation can be executed see Table 19 7 Executable Operation during Suspend e When auto erase of any block in the user ROM is suspended auto programming and reading of another block in the user ROM can be executed e When auto programming of any block in the user ROM is suspended reading of another block in the user ROM can be executed Table 19 7 Executable Operation during Suspend Operation during Suspend Block where erase or program operation is Block where erase or program operation is executed before entering suspend not yet executed before entering suspend Read Read Erase Program lock bit Read Erase Program lock bit Read status status Command in Erase execution Program Notes 1 Yes indicates operation is possible by using the suspend function and No indicates operation is disabled 2 The block erase command can be executed for erasure The program and lock bit program commands can be executed for programming The clear status register
401. o the FRV1 register and the value in the FR18S1 register to the FRV2 register Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the FRV2 register RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 84 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 3 9 3 1 T C Clock Oscillation Circuit XIN Clock Oscillation Circuit he XIN clock is supplied by the XIN clock oscillation circuit This clock is used as the clock source for the PU clock and the peripheral function clock The XIN clock oscillation circuit is configured by connecting an oscillator between pins XIN and XOUT The XIN clock oscillation circuit includes an on chip feedback resistor which is disconnected from the oscillation circuit in stop mode to reduce power consumption To input an externally generated clock to the XIN pin set the P46SEL2 bit in the PMH4E register to 0 bits P46SEL1 to P46SELO in the PMH4 register to 00b I O port or XIN input and bits CKPT1 to CKPTO in the EXCKCR register to 01b XIN clock input Figure 9 3 shows the XIN Clock Circuit Connection Examples The XIN clock is stopped during and after a reset T he XIN clock starts oscillating when the P46SEL2 bit in the PMH4E register is set to 0 bits P47SEL1 to P47SELO and P46SEL1 to P46SELO in the PMH4 register are set to 0000b and bits CKPT1 to CKPTO in the E XCKCR register are set to 11b P4_6 XIN P4_7 XOUT After the XIN
402. oaded at underflow U d V Counter 0307h 0001h O000h 2501h 2500h Figure 14 13 Example of Counter Operation in 16 Bit Timer Programmable Waveform Generation Mode or Programmable Wait One Shot Generation Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 224 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 5 3 TOCNT Bit Setting and Pin States The TOCNT bit in the TRBIOC register can be used to select whether a timer waveform or fixed value is output However regardless of the setting of the TOCNT bit an undefined value is output in timer mode and a waveform is output in programmable one shot and programmable wait one shot generation modes Table 14 8 lists the Output Data in Each Mode Table 14 8 Output Data in Each Mode Operating Mode Output Enabled Disabled Output Data Timer mode Output disabled Undefined value output Programmable waveform generation mode TCONT Waveform output Fixed value inverted value of TOPL Programmable one shot generation mode Output enabled Waveform output Programmable wait one shot generation mode TOPL TOCNT Bits in TRBIOC register If the TOCNT bit is rewritten in programmable waveform generation mode the pin state is not changed immediately The data is reflected in the pin state when one of the following conditions is met Note that when the TOCNT bit is 1 fixed value output the value which is set for the primary period in the TOPL bit in the TRB
403. ock A rewrite disable bit When the FMR16 bit is set to 0 data flash block A accepts program and block erase commands FMR17 Bit Data flash block B rewrite disable bit When the FMR17 bit is set to 0 data flash block B accepts program and block erase commands RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 335 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 5 4 Flash Memory Control Register 2 FMR2 Address 001ACh Bit b7 b6 b5 b4 b3 b2 b1 b Syme FMR Cum ouer FWR20 After Reset 0 0 0 0 0 0 0 0 Bit Name Function Suspend enable bit 0 Suspend disabled 1 1 Suspend enabled Suspend request bit 0 Restart 2 1 Suspend request Interrupt request suspend request 0 Suspend request disabled by interrupt request enable bit 1 1 Suspend request enabled by interrupt request Reserved Set to 0 Low current consumption read mode 0 Low current consumption read mode disabled enable bit 1 3 1 Low current consumption read mode enabled Notes 1 To set this bit to 1 first write O and then write 1 immediately Interrupts must be disabled between writing 0 and then writing 1 2 The FMR21 bit can be set when the FMR01 bit in the FMRO register is 1 CPU rewrite mode enabled and the FMR20 bit is 1 suspend enabled 3 In low current consumption read mode set the FMR01 bit in the FMRO register to 0 CPU write mode disabled Set this bit to 0 to perform A D
404. ock Erase Flowchart in EW1 Mode Flash Ready Status Interrupt Disabled and Suspend Enabled In EW1 mode do not execute this command for the block where the rewrite control program is allocated When the RDYSTIE bit in the FMRO register is 1 flash ready status interrupt enabled a flash ready status interrupt is generated when auto erase is completed When the RDYSTIE bit in the FMRO register is 1 flash ready status interrupt enabled and the FMR20 bit in the FMR2 register is 1 suspend enabled a flash ready status interrupt is generated when the FMR21 bit is set to 1 suspend request and auto erase is suspended The result can be confirmed by reading the FST register in the interrupt routine Write the command code 20h Write DOh to any address in the block Full status check i Block erase completed FST7 Bit in FST register Figure 19 12 Block Erase Flowchart Flash Ready Status Interrupt Disabled and Suspend Disabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 349 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory FMR20 1 FMR21 1 2 Write the command code 20h 1 interrupt enabled Write DOh to any address in the block Full status check Flag in CPU register FST6 FST7 Bits in FST register FMR20 FMR21 Bits in FMR2 register Block erase completed Notes 1 The interrupt vector table and interrupt routine to be used must be allocated to an area other than t
405. od other than the acceptance period illegal refresh while the RIS bit is O watchdog timer interrupt RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 64 of 426 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 2 2 Watchdog Timer Reset Register WDTR Address DECH Bit Symbol Ge After Reset Function b7 to bO The watchdog timer is initialized by writing OOh and then writing FFh during the acceptance period When 00h and then FFh is written during a period other than the acceptance period a watchdog timer reset or watchdog timer interrupt is generated If a watchdog timer interrupt is selected the watchdog timer is not initialized The initial value in the watchdog timer is specified by bits WOTUFSO to WDTUFS1 in the OFS2 register 1 Note 1 Only write to the WDTR register when the watchdog timer is counting 8 2 3 Watchdog Timer Start Register WDTS Address 00032h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol e After Reset b7 to bO The watchdog timer is started by executing a write instruction to this register 8 2 4 Watchdog Timer Control Register WDTC Address 00033h Bit b7 bO Symbol WDTC7 wore e After Reset 0 Bit Name Function Reserved The read value is undefined Watchdog timer count source select 67 b6 Veure 0 0 Division of CPU clock by 2 0 1 Division of CPU clock by 16 1 0 Division of CPU clock by 128 1 1 Division of low speed on chip osc
406. ode 19 8 2 1 Prohibited Instructions The following instructions cannot be used while the program ROM area is being rewritten in EWO mode because they reference data in the flash memory UND INTO and BRK 19 8 2 2 Interrupts Tables 19 12 and 19 13 list the Interrupt Handling during CPU Rewrite Operation Table 19 12 Interrupt Handling during CPU Rewrite Operation EWO Mode Data Flash Program ROM Interrupt Type Suspend Disabled FMR20 0 Maskable interrupt When an interrupt request is acknowledged interrupt handling is Interrupt handling is executed The interrupt vector is allocated in the RAM executed with auto erase The suspend state can be entered by either of the following or auto programming 1 When the FMR22 bit is 1 suspend request enabled by executed The interrupt interrupt request the FMR21 bit is automatically set to 1 vector is allocated in the suspend request RAM The flash memory suspends auto erase or auto programming after td SR SUS When the FMR22 bit is 0 suspend request disabled by interrupt request and suspend is required set the FMR21 bit to 1 Suspend request in the interrupt handling The flash memory suspends auto erase or auto programming after td SR SUS While auto erase is suspended auto programming and reading can be executed for any block other than the blocks being auto erased While auto programming is suspended any block other than the blocks being auto programmed can be read
407. ode enabled uses CPU rewrite mode to the RAM to the FMR01 bit Jump to the rewrite control program transferred to RAM Execute software commands The subsequent processing is performed by the rewrite control program in the RAM Write 0 CPU rewrite mode disabled to the FMR01 bit Jump to any address in the flash memory FMR01 Bit in FMRO register Note 1 To set the FMRO01 bit to 1 first write O and then 1 immediately Interrupts must be disabled between writing 0 and then writing 1 Writing to the FMR01 bit must be performed in the RAM Figure 19 5 Setting and Cancelling EWO Mode EW1 Mode Execution Procedure Program in ROM Write 0 and then 1 CPU rewrite mode enabled to the FMR01 bit Write 0 and then 1 EW1 mode to the FMRO2 bit i Execute software commands Write 0 CPU rewrite mode disabled to the FMRO1 bit FMR01 FMRO2 Bits in FMRO register Note 1 To set the FMR01 bit to 1 first write 0 and then 1 immediately Interrupts must be disabled between writing 0 and then writing 1 Figure 19 6 Setting and Cancelling EW1 Mode RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 342 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 5 Data Protect Function Each block in the program ROM in the flash memory has a nonvolatile lock bit The lock bit is enabled when the FMR13 bit in the FMR1 register is 0 lock bit enabled The lock bit can be used to disable lock prog
408. ogrammer and On Chip Debugging Emulator for examples of connecting a serial programmer Contact the manufacturer for more information on the serial programmer Also see the user s manual for how to use the serial programmer Table 19 10 lists the Pin Functions Flash Memory Standard Serial I O Mode 2 Figure 19 20 shows a Pin Handling Example in Standard Serial I O Mode 2 Table 19 11 lists the Pin Functions Flash Memory Standard Serial I O Mode 3 Figure 19 21 shows a Pin Handling Example in Standard Serial I O Mode 3 When a program in the flash memory is run in user mode after the pins are handled as shown in Table 19 11 and the flash memory is rewritten with the programmer input a high level to the MODE pin and reset the hardware For details on the ID code check function see 19 3 ID Code Check Function RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 358 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory Table 19 10 Pin Functions Flash Memory Standard Serial UO Mode 2 Pin Name VCC VSS Power supply input Description Apply the guaranteed program erase voltage to the VCC pin and 0 V to the VSS pin RESET Reset input Reset input P4_6 XIN P4_6 input clock input P4_7 XOUT P4_7 input clock output When operating with the on chip oscillator clock it is not necessary to connect an oscillation circuit Operation is not affected even if an external oscillator is connected in the user
409. ollowing states is disabled e TOB 0 output value 0 during high level output e TOB 1 output value 1 during low level output Figure 15 14 Operation Example in PWM2 Mode When TRCTRG Input is Enabled RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 257 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC TRCCNT register value FFFFh TRCGRA register TRCGRB register TRCGRC register 0000h TRCIOA TRCTRG TRCIOB output change when TOB 0 TRCIOB output change when TOB 1 TRCGRD register TRCGRB register Data is transferred from registers TRCGRD to TRCGRB CTS Bit in TRCMR register TOB Bit in TRCCR1 register Figure 15 15 Operation Example in PWM2 Mode When TRCTRG Input is Disabled RO1UH0050EJ0200 Rev 2 00 RENESAS Page 258 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC Figure 15 16 shows an Example of Count Stop Operation in PWM2 Mode In this example the TOB bit in the TRCCRI register is set to 0 output value 0 and the TOB bit is set to 1 output value 1 By setting the CSTP bit in the TRCCR2 register to 1 increment is stopped and the CCLR bit in the TRCCR1 register to 1 TRCCNT counter is cleared by input capture compare match A the counter is changed to 0000h and stopped by the compare match between registers TRCCNT and TRCGRA By setting the CTS bit in the TRCMR register to 0 count is stopped the counter is forcibly stopped and the output is set to the i
410. on is aborted or a communication error occurs while transmitting or receiving in clock synchronous serial I O mode follow the procedure below 1 Set the TE bit in the UOC1 register to 0 transmission disabled and the RE bit to 0 reception disabled 2 Set bits SMD2 to SMDO in the UOMR register to 000b serial interface disabled 3 Set bits SMD2 to SMDO in the UOMR register to 001b clock synchronous serial I O mode 4 Set the TE bit in the UOC1 register to 1 transmission enabled and the RE bit to 1 reception enabled RO1UH0050EJ0200 Rev 2 00 RENESAS Page 290 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 2 Clock Asynchronous Serial UO UART Mode In clock asynchronous serial I O mode transmission and reception are performed at an arbitrary bit rate and in an arbitrary format Table 16 6 lists the Clock Asynchronous Serial I O Mode Specifications Table 16 7 lists the Registers and Settings Used in Clock Asynchronous Serial I O Mode Table 16 6 Clock Asynchronous Serial I O Mode Specifications Item Specification Transfer data format e Character bits transfer data Selectable from 7 8 or 9 bits e Start bit 1 bit e Parity bit Selectable from odd even or none e Stop bits Selectable from 1 or 2 bits Transfer clock e The CKDIR bit in the UOMR register is 0 internal clock fj 16 n 1 fj f1 f8 or D n Value set in the UOBRG register 00h to FFh
411. ontrol Register 1 TRCIOR1 10001000b 000F7h Timer RC Control Register 2 TRCCR2 00011000b OOOF8h Timer RC Digital Filter Function Select Register TRCDF 00h OOOF9h Timer RC Output Enable Register TRCOER 01111111b OOOFAh Timer RC A D Conversion Trigger Control Register TRCADCR 11110000b OOOFBh Timer RC Waveform Output Manipulation Register TRCOPR 00h 000FCh CO GO GO C amp 15 2 1 Timer RC Counter TRCCNT Address 000E8h to 000E9h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol TTT After Reset 0 0 0 0 0 0 0 0 Bit b15 b14 b13 b12 b11 b10 b9 b8 symbol l After Reset 0 0 0 0 0 0 0 0 Function Setting Range b15 to bO 16 bit readable writable up counter 0000h to FFFFh When this counter overflows the OVF bit in the TRCSR register is set to 1 If the OVIE bit in the TRCIER register is set to 1 interrupt request FOVI by OVF bit is enabled at this time an interrupt request is generated The count source for the TRCCNT register is selected by bits CKSO to CKS2 in the TRCCR1 register When the CCLR bit in the TRCCRI1 register is 1 the TRCCNT register is cleared to 0000h when a compare match with the TRCGRA register occurs TRCCNT register must be accessed in 16 bit units Do not access this register in 8 bit units When this register is accessed as 16 bit units it is accessed twice in 8 bit units
412. operation SCHER for conversion Channel 7 AN7 I in operation Standby for conversion I l I 1 A D conversion result 1 l ADO register A D conversion result 3 I l l AD1 register A D conversion result 2 1 i L I U L l Note 1 When the ADST bit is set to 0 by a program the result of the corresponding A D conversion is not stored in the ADi register Figure 17 7 Operation Example in Repeat Sweep Mode When Channels 0 and 1 are Selected R01UH0050EJ0200 Rev 2 00 ztENESAS Page 312 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 4 A D Converter Interrupt Table 17 7 lists the A D Converter Interrupt When A D conversion completes the ADF bit in the ADICSR register is set to 1 interrupt requested If the ADIE bit is 1 interrupt enabled an A D conversion interrupt is generated Table 17 7 A D Converter Interrupt Interrupt Source Interrupt Name Interrupt Flag RO1UHOO50EJ0200 Rev 2 00 ztENESAS Page 313 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 5 Notes on A D Converter 17 5 1 A D Converter Standby Setting The A D converter can be set to standby or active using the MSTAD bit in the MSTCR register Stop A D conversion before setting to module standby Register access is enabled by clearing the A D converter standby state For details see 5 System Control 17 5 2 Sensor Output Impedance during A D Conversion To perform A D
413. or O Reset srono ihe aeee aid er REESEN aes EE E Aa 58 7 5 Voltage Monitor 1 Interrupt EE 59 7 6 Digital Filter for Voltage Detection Circuits 0 and 1 61 8 VUE ele e RRE 62 8 1 OVEL VIEW eene ee iere EES Deet Sei 62 8 2 LEE 64 8 2 1 Watchdog Timer Function Register RISR A 64 8 2 2 Watchdog Timer Reset Register WDTR 0 cece ceteceecesceseceeeeeeceeceseeeaeeesenecaeecaecaaesaecnaeeaeeeseeseeeseneeaes 65 8 2 3 Watchdog Timer Start Register WDTS sissors sissies stesso ke tesise eb Sesser p KSE e IESE E ES SSE ESES 65 8 2 4 Watchdog Timer Control Register OW DICH 65 8 2 5 Count Source Protection Mode Register CSR 66 8 2 6 Periodic Timer Interrupt Control Register WDTIR sssssessssessssesrsrssesresreresreresresreresrenresenresrnrerenserrrsreeesrene 66 A 2 8 3 Opera ON gedoe Bee EELER Eet seen 67 8 3 1 Items Common to Multiple Modes AA 67 8 3 2 When Count Source Protection Mode is Disabled 000 0 eee eeeceseseeesecnseceeceeceeeseceaeeseseaecseecaecsaeeaneneeaes 68 8 3 3 When Count Source Protection Mode is Enabled AAA 69 8 3 4 Periodic Timer Function NENNEN EENS 70 8 4 Not s on Watchdoe TIME casaria i a e Bee ste couch sue aa a a n weds i EEN 71 9 Clock Generation Circult eiiiai ela Miah a a ae hes ee a 72 9 1 OVGEVICW reiros seedonds d et d reet geregelte derre eegen g iert eh d e gerode eer Eder de 72 9 2 RES ISLETS ae Sess US SSR De RN DEE Se ed I ee ae 75 9 2 1 External Clock Control Register EXCKCR eccec
414. or bits ILVLj4 to ILVLj5 j 6 A C D or E for the interrupt whose source to be changed lt _ The interrupt is enabled 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INT3 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT3 are used RO1UHOO50EJ0200 Rev 2 00 May 18 2012 Register Setting Procedure When INTi Input Filter i 0 to 3 is Used ztENESAS Page 392 of 426 R8C M11A Group R8C M12A Group 21 Usage Notes 21 5 6 Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions Figure 21 3 shows the Register Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions Timer RJ2 Timer RB2 and Timer RC Rewrite registers PMLj and PMHj j 1 3 or 4 Set the INTIEN bit i 0 to 2 in the INTEN register to 0 Set bits INTIFO to INTE i 0 to 2 in INTFO register Set the INTIEN bit i 0 to 2 in the INTEN register to 1 Wait for a certain period Set the registers associated with the peripheral functions Note 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INT2 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT2 are used Figure 21 3 Register Setting Procedure When INTi Input Fil
415. ore interrupt handling is started Since auto erase or auto programming is forcibly stopped the correct values may not be read from the block being auto erased or the address being auto programmed After the flash memory is restarted execute auto erase again and verify it complete normally The watchdog timer does not stop while the command is executing so interrupt requests may be generated Initialize the watchdog timer periodically using the erase suspend function Since the flash memory control registers are initialized in this case these registers must be set again 1 FMR20 FMR21 FMR22 Bits in FMR2 register Note 1 Registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated while the flash memory is busy When the FMR01 bit in the FMRO register is 1 CPU rewrite mode enabled and the FMSTP bit is 1 flash memory is stopped registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated Suspend Enabled FMR20 1 Voltage monitor 1 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 407 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes Table 21 2 Interrupt Handling during CPU Rewrite Operation EW1 Mode Interrupt Type Maskable interrupt Data Flash Program ROM Suspend Disabled FMR20 0 When an interrupt request is acknow
416. ort Output port X X X ADTRG input X TRJO output See Table 12 24 TRCIOD Pin Settings TRCIOD input See Table 12 24 TRCIOD Pin Settings TRCIOD output R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 156 of 426 R8C M11A Group R8C M12A Group 12 I O Ports 12 5 Port4 Figure 12 3 shows the Port 4 Pin Configuration P4_2 TRBO TXDO KI3 P4_5 INTO ADTRG P4_6 XIN RXDO TXDO INT1 VCOUT1 TRJIO P4_7 XOUT INT2 Figure 12 3 Port 4 Pin Configuration RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 157 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 5 1 Port P4 Direction Register PD4 Address 000ACh Bit b 7 b6 b5 b4 b3 b2 b1 b0 symbol Poa 7 PDAS Ps a 0 0 0 0 0 0 0 After Reset 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P4_2 direction bit 0 Input mode functions as an input port 1 Output mode functions as an output port Nothing is assigned The write value must be 0 The read value is 0 Port P4_5 direction bit 0 Input mode functions as an input port Port P4_6 direction bit 1 Output mode functions as an output port Port P4_7 direction bit The PD4 register is used to select whether I O ports are used as input or output Each bit in the PD4 register corresponds to individual ports 12 5 2 Port P4 Register P4
417. oscillator mode Wait mode Stop mode RO1UHO050EJ0200 Rev 2 00 stENESAS Page 93 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control Figure 10 1 shows the Power Control State Transition Diagram Figure 10 1 Standard operating mode CKPT1 to CKPTO 11b or 01b HSCKSEL 0 SCKSEL 1 LOCODIS 0 SCKSEL 0 High speed clock mode System base clock fXIN HSCKSEL 0 SCKSEL 1 HOCOE 1 HSCKSEL 1 SCKSEL 1 CKPT1 to CKPTO 11b or 01b HSCKSEL 0 SCKSEL 1 1 WAIT instruction 2 WAITM 1 CKPTO CKPT1 Bits in EXCKCR register WAITM HSCKSEL Bits in SCKCR register STPM SCKSEL Bits in CKSTPR register HOCOE LOCODIS Bits in OCOCR register Low speed on chip oscillator mode System base clock LOCO HSCKSEL 0 or 1 SCKSEL 0 HOCOE 1 HSCKSEL 1 SCKSEL 1 LOCODIS 0 SCKSEL 0 High speed on chip oscillator mode System base clock fHOCO HSCKSEL 1 SCKSEL 1 Interrupt Power Control State Transition Diagram RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 94 of 426 R8C M11A Group R8C M12A Group 10 Power Control 10 2 Standard Operating Mode In standard operating mode the system clock is supplied to operate the CPU and the peripheral functions Power consumption control is implemented by controlling the frequency of the system clock or CPU clock The higher the CPU clock frequency the higher proces
418. ount is started the value is written to the reload register in synchronization with the count source after two or three cycles and then to the counter in synchronization with the next count source Figure 13 2 shows the Timing of Rewrite Operation with TSTART Bit Value Write 5678h to TRJ register by a program Write 1234h to TRJ register by a program Count source TSTART bit in TRJCR register TCSTF bit in TRJCR register TRJ register FFFFh After the value is written it is written to the reload register after 2 or 3 cycles of the count source Reload register FFFFh The reload register value is reloaded to the counter by the first count source The reload register value is reloaded to the counter on the completion of the 16 bit count Timer Puz couer EFEM oo Note 1 It takes 3 or 4 cycles of the count source after 1234h is written to the TRJCR register before the value is reloaded to the counter Figure 13 2 Timing of Rewrite Operation with TSTART Bit Value RO1UH0050EJ0200 Rev 2 00 RENESAS Page 186 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 2 Timer Mode In this mode the counter is decremented by the count source selected by bits TCKO to TCK2 in the TRJMR register The count value is decremented by 1 each time the count source is input and an underflow occurs if the next count source is input after the count value reaches 0000h The TRJIF bit in the TRJIR register is se
419. oup R8C M12A Group 12 I O Ports 12 4 3 Pull Up Control Register 3 PUR3 Address 000B7h Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo P7 Puss Pa P After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P3_3 pull up control bit 0 No pull up resistor Port P3_4 pull up control bit 1 Pull up resistor Port P3_5 pull up control bit Nothing is assigned The write value must be 0 The read value is 0 Port P3_7 pull up control bit 0 No pull up resistor 1 Pull up resistor The PUR3 register is used to control the port P3 pull up resistors I O ports are pulled up when the corresponding PD3_j bit j 3 to 5 or 7 in the PD3 register is set to 0 input mode functions as an I O port and the PU3_j bit j 3 to 5 or 7 in the PUR3 register is set to 1 The input pins for peripheral functions are pulled up when the corresponding PD3_j bit is set to 0 and the PU3_j bit is set to 1 Do not set the corresponding PU3_j bit to 1 for the output pins for peripheral functions 12 4 4 Drive Capacity Control Register 3 DRR3 Address 000BDh Bit b7 b6 b5 b4 b3 b2 b1 b Symbol DRRS7 DRRSS DRRS4 DRAS3 After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Port P3_3 drive capacity control bit 0 Low drive capacity Port P3_4 drive capac
420. output compare or input capture registers individually Can be used as buffer registers for output compare or input capture Operating modes Timer mode e Output compare function Low level high level or toggle output can be performed e Input capture function A rising edge falling edge or two way edge can be detected e Counter clear function A count period can be set PWM mode PWM output with up to three phases PWM2 mode Pulse output with an arbitrary period and duty Interrupt sources e Compare match input capture multiplexed interrupt x 4 sources e Overflow interrupt Others e The initial value of the timer RC output can be set arbitrarily e A D conversions triggered by compare matches in registers TRCGRA TRCGRB TRCGRC and TRCGRD can be set RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 229 of 426 Table 15 2 General registers output compare input capture multiplexed registers R8C M11A Group R8C M12A Group Timer RC Functions Counter Period setting with the TRCGRA register I O Pin 15 Timer RC TRCIOA TRCGRA register TRCIOB TRCGRB register TRCIOC TRCGRC register In buffer operation Buffer register for the TRCGRA register TRCIOD TRCGRD register In buffer operation Buffer register for the TRCGRB register Counter clear function Input capture compare match for the TRCGRA register Inpu
421. pacity of some ports can be switched Table 12 1 shows the I O Port Overview Table 12 2 lists the Port Functions by Pin R8C M12A Group Table 12 3 lists the I O Port Register Configuration Table 12 1 P1_0 to P1_7 UO Port Overview Output Type 3 state CMOS I O Setting Set in 1 bit units Internal Pull Up Resistor Set in 1 bit units 3 Drive Capacity Switching Set in 1 bit units 4 P3_3 P3_4 P3_5 P3_7 3 state CMOS Set in 1 bit units Set in 1 bit units 3 Set in 1 bit units 4 PA_0 1 3 state CMOS Set in 1 bit units None None KENE P4_6 P4_7 2 3 state CMOS Set in 1 bit units Set in 1 bit units 3 1 When the hardware reset is not used this port can be used as an UO port 2 When the XIN clock oscillation circuit or direct input of the XIN clock is not used these can be used as I O ports 3 In input mode whether an internal pull up resistor is connected or not can be selected by the PURi register i 1 3 or 4 None 4 The drive capacity of the output transistors low or high can be selected by the DRRi register i 1 or 3 Table 12 2 Pin R8C M12A Number Group P42 Function 0 Function 1 Function 2 Port Functions by Pin R8C M12A Group Function 3 Function 4 Function 5 Function Select Bit PM2 to PMO 000b P4_2 PM2 to PMO 001b PM2 to PMO PM2 to PMO 011b KI3 010b
422. peration External power VCC Vdet0 Sampling time Internal reset signal low active x 256 1 fLOCO Note 1 The voltage monitor 0 digital filter samples VCC to monitor the voltage If VCC falls below the operating voltage range 1 8 V or more the voltage cannot be correctly measured This factor should be considered when selecting the sampling clock for the digital filter For details see 7 Voltage Detection Circuit Figure 6 5 Example of Voltage Monitor 0 Reset Operation R01UH0050EJ0200 Rev 2 00 ztENESAS Page 45 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 3 5 Watchdog Timer Reset When the RIS bit in the RISR register is 1 watchdog timer reset enabled if the watchdog timer underflows or if the WDTR register is written at a time other than the refresh acceptance period a watchdog timer reset is generated This reset initializes the CPU SFRs and I O ports The internal reset signal goes high and the watchdog timer reset is cleared at the same time The MCU then proceeds to the reset sequence see Figure 6 2 The low speed on chip oscillator clock no division is automatically selected as the CPU clock after a reset The internal RAM is not initialized When the watchdog timer underflows the RAM values will be undefined The underflow period and refresh acceptance period for the watchdog timer are set by bits WDTUFSO to WDTUFS1 and WDTRCSO to WDTRCS1 in the OFS2 register respectivel
423. program or the INTO pin input When a trigger is generated from that point the timer operates only once to count a given length of the time equal to the setting value of the TRBPR register In the 8 bit timer with 8 bit prescaler the count value is set in the TRBPR register In the 16 bit timer the count value of the higher 8 bits is set in the TRBPR register and that of the lower 8 bits is set in the TRBPRE register In programmable one shot generation mode the TRBSC register is not used When one shot count is started is written to the TOSST bit in the TRBOCR register while the TCSTF bit in the TRBCR register is 1 count is enabled the count is started after the count source is sampled three times If an enabled trigger is input to the INTO pin while the TCSTF bit is 1 the count is started after the count source is sampled three times When the count value in the timer RB secondary overflows and then it is reloaded the count is stopped The count is also stopped with any of the following settings e When 1 one shot count is stopped is written to the TOSSP bit in the TRBOCR register the count is stopped after the count source is sampled three times e When 0 count is stopped is written to the TSTART bit in the TRBCR register the count is stopped after the count source is sampled three times e When count is forcibly stopped is written to the TSTOP bit in the TRBCR register the count is stopped The actual count state mus
424. pt Type Suspend Disabled FMR20 0 Maskable interrupt When an interrupt request is acknowledged interrupt handling is Interrupt handling is executed The interrupt vector is allocated in the RAM executed with auto erase The suspend state can be entered by either of the following or auto programming 1 When the FMR22 bit is 1 suspend request enabled by executed The interrupt interrupt request the FMR21 bit is automatically set to 1 vector is allocated in the suspend request RAM The flash memory suspends auto erase or auto programming after td SR SUS When the FMR22 bit is 0 suspend request disabled by interrupt request and suspend is required set the FMR21 bit to 1 Suspend request in the interrupt handling The flash memory suspends auto erase or auto programming after td SR SUS While auto erase is suspended auto programming and reading can be executed for any block other than the blocks being auto erased While auto programming is suspended any block other than the blocks being auto programmed can be read Auto erase can be restarted by setting the FMR21 bit to 0 restart Address match Do not use during auto erasing or auto programming UND INTO and BRK instructions Single step Watchdog timer When an interrupt request is acknowledged auto erase or auto programming is forcibly stopped Oscillation stop immediately and the flash memory is reset After the specified period the flash memory is detection restarted bef
425. pulation enable 1 Waveform output manipulation enabled bit 5 Nothing is assigned The write value must be 0 The read value is 0 Notes 1 When the OPE bit is 1 waveform output manipulation enabled bits EA to ED in the TRCOER register are set to 1 output level is fixed or high impedance depending on TRCOPR register setting if the waveform output manipulation event is input 2 When the OPE bit is 0 waveform output manipulation disabled bits EA to ED in the TRCOER register are not affected by the setting of this bit 3 When the OPE bit is 1 or the RESTATS bit is 0 output is restarted by software bits EA to ED in the TRCOER register are set to 0 by software Bits EA to ED are not automatically set to 0 even if the waveform output manipulation event is cancelled 4 When the OPE bit is 1 or the RESTATS bit is 1 output is automatically restarted bits EA to ED are automatically set to 0 if the waveform output manipulation event is cancelled 5 When the OPE bit is 0 only the setting of the TRCOER register is used to manipulate the output for timer RC When the OPE bit is 1 regardless of the setting of the PTO bit in the TRCOER register the waveform output for timer RC is manipulated with the settings of the TRCOPR register Bits EA to ED in the TRCOER register are used as the flags for manipulating the waveform output When a waveform output manipulation event is input bits EA to ED are set to 1 RO
426. r Circuit Edge Select Register 00h 00059h 0005Ah Voltage Detect Register 2 00100100b 2 00000100b 3 0005Bh Voltage Detection 1 Level Select Register 00000111b 0005Ch Voltage Monitor 0 Circuit Control Register 1100X011b 2 1100X010b 3 0005Dh Voltage Monitor 1 Circuit Control Register 10001010b 0005Eh 0005Fh Reset Source Determination Register 0000XXXXb 4 00060h 00061h 00062h 00063h 00064h High Speed On Chip Oscillator 18 432 MHz Control Register 0 FR18S0 Value when shipped 00065h High Speed On Chip Oscillator 18 432 MHz Control Register 1 FR18S1 Value when shipped 00066h 00067h High Speed On Chip Oscillator Control Register 1 FRV1 Value when shipped 00068h High Speed On Chip Oscillator Control Register 2 FRV2 Value when shipped 00069h 0006Ah 0006Bh 0006Ch 0006Dh 0006Eh 0006Fh 00070h 00071h 00072h 00073h 00074h 00075h 00076h 00077h 00078h 00079h X Undefined Notes 1 The blank areas are reserved No access is allowed 2 The LVDAS bit in the OFS register is 0 3 The LVDAS bit in the OFS register is 1 4 The value after a reset differs depending on the reset source R01UH0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 16 of 426 R8C M11A Group R8C M12A Group 3
427. r Settings and Low Speed On Chip Oscillator States If the XINBAKE bit in the BAKCR register is 1 oscillation stop detection function enabled when the XIN clock is stopped the low speed on chip oscillator starts operation and supplies the system base clock Table 9 5 Register Bit WDTC7 Register Settings and Low Speed On Chip Oscillator States WDTC CKSTPR OCOCR WDTC6 STPM SCKSEL LOCODIS Low Speed On Chip Oscillator State Setting value X 0or1 RO1UHOO50EJ0200 Rev 2 00 May 18 2012 Other than 11b Oscillation on Other than 11b Oscillation off Other than 11b Oscillation on Other than 11b Oscillation off 11b Oscillation on X ztENESAS Oscillation on Page 77 of 426 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 3 System Clock f Control Register SCKCR Address 00022h Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol SCRS WAM PHISSELPFTSSELPHISSELA After Reset 0 Bit Name Function PHISSELO CPU clock division ratio select bits These bits are used to select the division ratio PHISSEL1 of the system clock f to generate the CPU PHISSEL2 clock fs b2 b1 b 0 0 0 fs System clock with no division 0 0 1 fs System clock divided by 2 0 1 0 fs System clock divided by 4 0 1 1 fs System clock divided by 8 1 0 0 fs System clock divided by 16 fs System clock divided by 32 01 1 0 Do no
428. r the TOSSP bit in the TRBOCR register the TOSSTF bit is changed after two to three cycles of the count source If 1 is written to the TOSSP bit from when is written to the TOSST bit until the TOSSTF bit is set to 1 the TOSSTF bit may be set to 0 or 1 depending on the internal state Likewise if 1 is written to the TOSST bit from when 1 is written to the TOSSP bit until the TOSSTF bit is set to 0 the TOSSTF may be set to 0 or 1 depending on the internal state e In programmable waveform generation mode and programmable wait one shot mode write to the TRBSC register before writing to the TRBPR register At the underflow during the secondary period after the TRBPR register is written the value written to the TRBPR register is transferred to the counter If registers TRBPR and TRBSC are written two or more times after the TRBPR register is written until the underflow during the secondary period the last written value is transferred to the counter at the underflow e When 1 is written to the TSTOP bit in the TRBCR register during count operation timer RB2 is immediately stopped e If the count is forcibly stopped by writing 1 to the TSTOP bit during count operation the TRBIF bit in the TRBIR register may be set to 1 interrupt requested Set the TRBIF bit to 0 no interrupt requested before restarting the count e When the TSTART bit in the TRBCR register is 0 count is stopped wait for at least two cycles of the system clock f after writing t
429. r timer RB2 set timer RJ2 to timer mode pulse output mode or event counter mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 227 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 e When 1 is written to the TOSST bit or the TOSSP bit in the TRBOCR register the TOSSTF bit is changed after two to three cycles of the count source If 1 is written to the TOSSP bit from when is written to the TOSST bit until the TOSSTF bit is set to 1 the TOSSTF bit may be set to 0 or 1 depending on the internal state Likewise if 1 is written to the TOSST bit from when 1 is written to the TOSSP bit until the TOSSTF bit is set to 0 the TOSSTF may be set to 0 or 1 depending on the internal state e In programmable waveform generation mode and programmable wait one shot mode write to the TRBSC register before writing to the TRBPR register At the underflow during the secondary period after the TRBPR register is written the value written to the TRBPR register is transferred to the counter If registers TRBPR and TRBSC are written two or more times after the TRBPR register is written until the underflow during the secondary period the last written value is transferred to the counter at the underflow e When 1 is written to the TSTOP bit in the TRBCR register during count operation timer RB2 is immediately stopped e If the count is forcibly stopped by writing 1 to the TSTOP bit during count operation the TRBIF bit in the TRBIR register may be set
430. ramming erasing each block This prevents data from being written or erased inadvertently The block status changes according to the lock bit as follows e When the lock bit data is 0 locked the block cannot be programmed erased e When the lock bit data is 1 not locked the block can be programmed erased The lock bit data is set to 0 locked when the lock bit program command is executed and 1 not locked when the block is erased There are no commands that can be used to set only the lock bit data to 1 The lock bit data can be read using the read lock bit status command When the FMR13 bit is set to 1 lock bit disabled the lock bit function is disabled and no blocks are locked The lock bit data remains unchanged When the FMR13 bit is set to 0 lock bit enabled the lock bit function is enabled The lock bit data is retained When the block erase command is executed while the FMR13 bit is 1 lock bit disabled the target block is erased regardless of the lock bit status The lock bit for the erase target block is set to 1 after erase is completed For details on individual commands see 19 6 6 Software Commands The FMR13 bit is set to 0 after auto erase is completed This bit is also set to 0 when one of the following conditions is met To program erase a block with a lock bit in a different state set the FMR 13 bit to 1 lock bit disabled again and execute the program command or the block erase command e When the FST7 bit in
431. re switched when returning from wait mode 0 if the clocks are not switched when returning from wait mode stabilization time Time until CPU Clock Supply T3 CPU clock period x 2 cycles CPU clock restart sequence Time for Interrupt Sequence T4 CPU clock period x 20 cycles Interrupt sequence Remarks The total on the left amounts to the time from wait mode until execution of an interrupt routine Setting prohibited Sequence from Wait Mode to Interrupt Routine Execution after WAIT instruction is RO1UHO0050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 99 of 426 R8C M11A Group R8C M12A Group 10 Power Control Figure 10 3 shows the Time from Wait Mode to First Instruction Execution after Exit after WAITM Bit in SCKCR Register is Set to 1 Wait Mode is Entered When a peripheral function interrupt is used to return from wait mode the following items must be set before setting the WAITM bit to 1 1 Set the I flag to 0 maskable interrupt disabled 2 Set the interrupt priority level in bits ILVLi0 to ILVLi1 or bits ILVLi4 to ILVLi5 in the interrupt priority level registers for the peripheral function interrupts that are used to return from wait mode Also set 00b level 0 interrupt disabled in bits ILVLil to ILVLi0 or bits ILVLi5 to ILVLi4 for the peripheral function interrupts that are not to be used to return from wait mode 3 Operate the peripheral fun
432. register R2RO In the same way as with RO and R2 R3 and R1 can be used as a 32 bit data register R3R1 2 2 Address Registers A0 and A1 AO is a 16 bit register for address register indirect addressing and address register relative addressing It is also used for transfer arithmetic and logic operations Al functions in the same manner as AO Al can be combined with AO and used as a 32 bit address register AT AO 2 3 Frame Base Register FB FB is a 16 bit register used for FB relative addressing 2 4 Interrupt Table Register INTB INTB is a 20 bit register that indicates the start address of a relocatable interrupt vector table 2 5 Program Counter PC PC is a 20 bit register that indicates the address of the next instruction to be executed 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP The stack pointers SP USP and ISP are each 16 bits wide The U flag of the FLG register is used to switch between USP and ISP 2 7 Static Base Register SB SB is a 16 bit register used for SB relative addressing 2 8 Flag Register FLG FLG is an 11 bit register that indicates the CPU state 2 8 1 Carry Flag C The C flag retains carry borrow or shift out bits that have been generated in the arithmetic and logic unit 2 8 2 Debug Flag D The D flag is for debugging only It must only be set to 0 2 8 3 Zero Flag Z The Z flag is set to 1 when an arithmetic operation results in 0 Otherwise it i
433. register H i 1 U Li 1 1 Li I LU T Measurement pulse input I Counter is reloaded 1 Timer RJ2 counter 02FFh O2FEh 0300h 02FFh 02FEh 02FDI 02FBI 02F9h 02F8h 02F7h 02FFh 02FEh U 1 U Li Bi L Li Lower 8 bit read signal of counter Note 1 U i 1 Higher 8 bit read signal H of counter 1 1 U 1 H Read data Fa o oz TEDGF bit in I i 1 i U I i Note 2 i i i I i TRJCR register 1 I D Set to 0 by a program 4 TUNDF bit in TRJCR register I Set to 0 by a program TRUIF bit in TRUJIR register Set to 0 by a program Notes Reading from the TRJ register must be performed during the period from when the TEDGF bit is set to 1 active edge received until the next active edge is input The content of the read out buffer is retained until the TRJ register is read If it is not read before the active edge is input the measurement result of the previous period is retained When the TRu register is read in pulse period measurement mode the content of the read out buffer is be read After the active edge of the measurement pulse is input the TRJ register is reloaded at the third rising edge of the count source Then the TEDGF bit in the TRJCR register is set to 1 active edge received at the fourth rising edge of the system clock f To set to 0 by a program use the MOV instruction to write 0 to the TEDGF bit in TRJCR register and write 1 to the TUND
434. register by the third count source Me Previous va New value 01h oad register ter fhe value is written to the TRBPR register itis written to the reload register by the third count source TRBPR oad register Previous va New value 25h After the value is written to the TRBPR register itis written to the reload register by the third count source TRBSC oad register Previous val New value 1Ah 1 Reloaded by the next count source d Counter 0307h os06n os05h Waat Lo n 2soon 24FFh e4rEnfe4rDh e4rci24renle4r Anj24ron 24F eh 24F 7h When the TWRC bit in TRBMR register is 1 write to reload register only Secondary Write 01h to TRBPRE register 25h to TRBPR register and 1Ah to TRBSC register underflow Count source After the value is written to the TRBPR register it is wrjtten to the reload register immediately beforeithe end of the secondary output period TRBPRE i Previous value New value 01h oad register 1 After the value is written to the TRBPR register it is wrftten to the reload register immediately 1 beforeithe end of the secondary output period TRBPR Previous value New value 25h oad register 1 After the value is written to the TRBPR register itis wrftten to the reload register immediately 1 beforeithe end of the secondary output period TRBSC S Previous value New value 1Ah oad register U Rel
435. register is set to 1 underflow and the TRJIF bit in the TRJIR register is set to 1 interrupt requested When the TRJIE bit in the TRJIR register is 1 interrupt enabled an interrupt request signal is generated to the CPU Figure 13 6 shows an Operation Example in Pulse Width Measurement Mode When accessing bits TEDGF and TUNDF in the TRJCR register see 13 5 Notes on Timer RJ2 4 This example applies when the high level width of the measurement pulse is measured TEDGSEL bit in TRJIOC register 1 n TRJ register content i Measurement is started KE Underflow Measurement Measurement is stopped is stopped Counter content hex Measurement Measurement is started is started TSTART bit in TRJCR register Measurement pulse input to TRJIO pin TRUIF bit in TRJIR register I Set to 0 by a program TEDGF bit in TRJCR register Set to 0 by a program Set to 0 by a program TUNDF bit in TRJCR register Set to 0 by a program Figure 13 6 Operation Example in Pulse Width Measurement Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 190 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 6 Pulse Period Measurement Mode In this mode the pulse period of an external signal input to the TRJIO pin is measured The counter is decremented by the count source selected by bits TCKO to TCK2 in the TRJMR register When a pulse with the period specified by the TEDGSEL bit in the TRJIOC register is inpu
436. riber Identity Module Universal Asynchronous Receiver Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners Table of Contents SFRiPage Reference ssi eats tah alii heen es elle oe tad arate Meee ti PU ead GEN 1 OVEIVIOW E A EE EE 1 1 1 IN EE 1 1 1 1 he EE 1 1 1 2 Differences between Groups ie cases eve seos r cs saben we uss reba BENENNEN 2 1 1 3 SPCCUICALLONS 5 sb ssscecsseteesstte cs eshte sh tsbeon digs eigats Mes teonsd setae E tees 4 1 2 PrOGUCE LA St gebr eet EE RE Ee booubcbinadecetenteesios ontertavas ce roeevntegege evel cate 6 1 3 Block Dia Sain egen Siet dree EES eege Eed H 1 4 Pin ASSisnMent EE Sens oe Ae I As ee ee a AR eh ee ee ay 8 1 5 Pins ai Lee e 10 2 Central Processing Unit CPU merna e aaa a a e aa tits Leed Zeg EEGEN a ATENE 11 2 1 Data Regist rs RO RL RZ and RI oe eia EE EET E EAE E a R 12 2 2 Address Registers AQ and ATI ecdat nininini nn i a i aer a E 12 2 3 Frame Base Keser EB vascvecidsceshs cSinceseck cvedessseaeede a dee eg e e aa a eiio i ERa 12 2 4 Interrupt Table Register ONTB AA 12 25 Program Counter PC geegent Be ege ge 12 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP AA 12 2 7 Static Base Resister bitze AER ee AE ELE ee Ee cd 12 2 8 Flap Resister E EE 12 2 8 1 Carry Blag ncaa ti ee et ee IG es A he S 12 2 8 2 Deb s Flas D piei ac deeb o
437. ritten TWRC 0 Updated in synchronization with the prescaler underflow after the TRBPR register is written 2 Programmable one shot gene ration mode Updated in synchronization with the prescaler underflow 3 Programmable wait one shot generation mode TWRC 1 Updated immediately before the end of the secondary output period after the TRBPR register is written TWRC 0 TWRC Bit in the TRBMR register Notes Updated in synchronization with the prescaler underflow after the TRBPR register is written 2 1 For details see 14 5 2 Prescaler and Counter Using TWRC Bit 2 When the TWRC bit is 0 write to reload register and counter in programmable waveform and programmable wait one shot generation modes if the data in registers TRBSC and TRBPR is updated during count operation the waveform is output for the updated period from that time 3 When the TWRC bit is 0 write to reload register and counter in programmable one shot generation mode if the data in the TRBPR register is updated during count operation the waveform is output for the updated period from that time Table 14 7 Reload Register Update Timing for Registers TRBPRE TRBPR and TRBSC in 16 Bit Timer Operating Mode Timer mode Update Timing 1 Registers TRBPRE and TRBPR TRBSC Register Updated in synchronization with Updated in synchronization with the count source after the TRBPR the count source after the
438. rm Start Up Determination Function seeseseesesseeessseeresresesresreresreersseeresrnresteserrrsreersreee 46 6 3 8 Reset Source Determination FUNCHON peenes enos snas aa Eiee E E E EE S SERE 46 6 4 States durino Reset iye eee ean a Ee EE es Se hk id 47 6 4 1 Pin States While RESET Pin Level is LOW c sccscssssssssesssssssessessesscescescsscsesueascasssscscescsuesuesesseeseeseeceseeseaneass 47 6 4 2 CPU Register States After Reset irais iiron eer er o reo Ea a E E EEE Eana iaar TE nr aS 48 7 Voltage Detection Circuiten eiio a a a E a AA AERE eA E EE 49 7 1 Overview e Deeg eee a ae E E E a a ae se ea 49 72 EAEn E EEEE E N EEEE sde ege EEEN ETE SEPE E ded leevtcaey Siebert ATE 52 7 2 1 Voltage Monitor Circuit Edge Select Register VCAC sssesesesesseressseeresresrsresrrrrsreerssrsresreresreserrrsreersrene 52 7 2 2 Voltage Detect Register 2 VCA2 c cccscccsciessveceues sees cescactsetcuaghes cwnscasheususcecbouscasvecacushovdenscbcbsuccesceck cuschssees 53 7 2 3 Voltage Detection 1 Level Select Register VDILS oo ee eeeseececneecnecsesecnecaecseeseeeseseseeseneeegs 54 7 2 4 Voltage Monitor 0 Circuit Control Register VWWOC occ eee eeeeceseeeeecseeeeecaeesaecaecsaecnecseeeeeneeeeeeeeeaes 55 7 2 5 Voltage Monitor 1 Circuit Control Register VW10C s essssesssseseesseeesesrererrssesrssreresresesrenrerrnserenseseesrereseene 56 73 Monitoring VCC Input Voltage A 57 7 3 1 Monitoring VdetO 22 ENEE EENS 57 7 3 2 Monitoring E 57 71 4 Voliage Monit
439. roup 11 Interrupts 11 2 8 Interrupt Monitor Flag Register 2 IRR2 Address 00052h Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo poeme TT After Reset 0 0 0 0 0 0 0 0 Bit Name Function Reserved The read value is 0 IRCMP1 Comparator B1 interrupt request monitor flag 0 No interrupt requested IRCMP3 Comparator B3 interrupt request monitor flag 1 Interrupt requested Nothing is assigned The write value must be 0 The read value is 0 The IRR2 register is the monitor flag register for comparator B1 and comparator B3 interrupt requests See 11 4 2 1 Registers IRRO to IRR2 for the relation between interrupt monitor flag bits and peripheral function interrupts RO1UH0050EJ0200 Rev 2 00 RENESAS Page 117 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 2 9 External Interrupt Flag Register IRR3 Address 00053h Bit b7 b6 b5 b4 b3 b2 b1 b0 Smo LLDT m Re TD Re After Reset 0 0 0 0 0 0 0 0 Bit Name Function INTO interrupt request flag 0 No interrupt requested 1 Interrupt requested INT1 interrupt request flag INT2 interrupt request flag INTS interrupt request flag Reserved Set to 0 Key input interrupt request flag 0 No interrupt requested 1 Interrupt requested Nothing is assigned The write value must be 0 The read value is 0 IRIO Bit INTO interrupt request flag Writing 0 after reading the value
440. rror or lock bit program error occurs when the CMDERIE bit in the FMRO register is 1 interrupt enabled During interrupt handling set the BS YAEI bit to 0 no flash access error interrupt requested Conditions for setting to 0 e When 0 is written to this bit after reading it as 1 e When the clear status register command is executed Conditions for setting to 1 e If the user ROM area is read or written while the flash memory is busy when the BSYAEIE bit in the FMRO register is flash access error interrupt enabled Note that the read value is undefined Writing has no effect e If a block erase error program error block blank check error command sequence error or lock bit program error occurs when the CMDERIE bit in the FMRO register is interrupt enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 331 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory FST2 Bit L BDATA monitor flag This is a read only bit indicating the lock bit status To confirm the lock bit status execute the read lock bit status command and then read the FST2 bit after the FST7 bit is set to 1 ready This bit is updated when the program erase and read lock bit status commands are generated When the read lock bit status command is input the FST7 bit is set to 0 busy When the FST7 bit is set to 1 ready the lock bit status is stored in the FST2 bit The data in the FST2 bit is retained until the next command is input
441. rs B1 and B3 which compare an analog input voltage with a reference input voltage 18 1 Overview The comparison result between the reference input voltage and the analog input voltage can be read by software Table 18 1 lists the Comparator B Specifications Figure 18 1 shows the Comparator B Block Diagram Table 18 2 lists the Comparator B Pin Configuration Table 18 1 Comparator B Specifications Item Specification Input voltage Reference input Input from the reference pin IVREFi Analog input Input voltage from the analog pin IVCMPi Comparison result The result can be read from the WCBiOUT bit in the WCMPR register or monitored with the VCOUTI pin Interrupt request generation timing When the comparison result changes Digital filter function e The digital filter can be enabled or disabled e The sampling frequency can be selected f1 f8 or f32 i 1or3 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 316 of 426 May 18 2012 R8C M11A Group R8C M12A Group WCB3F1 to WCB3F0 Sampling clock Digital filter matches three successive times WCB30UT WCB1F1 to WCB1FO Sampling clock Digital filter IVCMP1 matches three IVREF1 successive times 18 Comparator B WCB3F1 to WCB3INTEN WCB3F0 other than 00b Edge detection circuit WCBIF1 to WCBI1INTEN WCB1F0O other than 00b Edge detection circuit To interrupt To interrupt WCB1OUT WCB10UT WCB30UT Bits in WCM
442. ry Stop and Operation Transition cece eeceeeesceeeeseeesecseeeaeesecseeeeseeeseeeeseaes 367 20 Electrical Characteristics innocens e a a ao aada anae i pa 368 2k Usage Notes neor ie eet et tA i en ee ees AR ed 388 21 1 Notes on System Control lr a Sates sees e Tar ea AEE a E seen tesa EEEE EAS TEE Eae Toei aos 388 21 1 1 Option Function Select Area Setting Example 0 0 cece eecseeeecseesseceeceseeseeeseseeeeeeseecaecaeeeaecnaeeaeenaes 388 21 2 Notes on Watchdog Timer enee Seen eegend Seed E sens Sege 388 21 3 Notes on Clock Generation Circuit 20 ceecsecsseesecescesecesceeeeeeenseseecsecaaecaecaecsacsecseceseseeeeseseaseaeseaseaaesaes 388 21 3 1 Oscillation Stop Detection Function oe ee ceeee cee ceseesecesceeeeeeceseeeaecaaesaesaeceeessecuscesesaseasesaecaeesaesaee 388 21 3 2 Oseillation Circuit Constant ENER EENS EEN EEEE EE ES r e ER EEEE Eit 388 21 4 Notes on Power Control mosie cb scecsacsceses EE SEENEN Ee e 389 21 4 1 Program Restrictions When Entering Wait Mode AE 389 21 4 2 Program Restrictions When Entering Stop Mode ssssesseseseeseeessssrersreresreerereeserrnseereseeresrnesenseresrerrssent 389 21 5 NOteS Rn EE 390 215 1 Reading Address O0000D 0 ses sect cssesdscescesissnsbadesstavasiesdutseesectescspecepbesh es EEr s re SC hos sessnebespustowsczeceatsy 390 215 2 SP Setting EE 390 21 5 3 External Interrupt and Key Input Interrupt essssseesseeesseeeseerssrsrsserrsseeresrsesrestsrsrertsrentesrnerresesrrereersseet 390 21 5 4
443. s always 0 8 VCC or more When using the RESET pin as an I O port see 12 11 1 Notes on PA_0 Pin When the input voltage to the VCC pin reaches Vdet0 or above counting of the low speed on chip oscillator clock starts When the low speed on chip oscillator clock count reaches 256 the internal reset signal goes high and the MCU proceeds to the reset sequence see Figure 6 2 The low speed on chip oscillator clock no division is automatically selected as the CPU clock after a reset For the states of the SFRs after a power on reset see 3 2 Special Function Registers SFRs To use the power on reset set the LVDAS bit in the OFS register to 0 voltage monitor 0 reset enabled and enable the voltage monitor 0 reset Figure 6 4 shows the Power On Reset Circuit Example and Operation 4 7 KQ reference Vdeto 0 5 V External power VCC Internal reset signal low active x 256 1 fLOCO Notes 1 Vdet0 indicates the voltage detection level of the voltage detection 0 circuit For details see 7 Voltage Detection Circuit 2 For details on the electrical characteristics see 20 Electrical Characteristics 3 To use the power on reset enable the voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0 Figure 6 4 Power On Reset Circuit Example and Operation RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 44 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 3 4 Voltage Monitor 0 Reset
444. s of the count source If an active edge is input during this period the internal signal of the TEDGF bit does not become 0 and the TEDGF bit is read as 1 Since the TRJIF bit becomes when the internal signal of the TEDGF bit changes from 0 to 1 the TRJIF bit does not become and no interrupt is generated After setting the TEDGF bit to 0 confirm that 0 can be read after waiting for three or more count source cycles in order to accept the next interrupt request RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 396 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 8 When the TEDGSEL bit in the TRJIOC register is set to O count on rising edge and the external signal TRJIO is counted in event counter mode the signal may not be counted correctly depending on the state of the TSTART bit in the TRJCR register see Figure 21 4 If the TRJIO pin is set to low before the TSTART bit is set to 1 count is started and a valid event is input after the TSTART bit is set to 1 the signal is not counted on the first rising edge of the TRJIO input Thus the number of counted events is obtained as follows Number of counted events initial value in the counter value in the counter on completion of the valid event 1 1 To avoid this set the TRJIO pin to low after setting the TSTART bit to 1 count is started see Figure 21 5 TRUJIO pin A TEDGSEL bit in x 0 TRJIOC register TSTART bit in TRJCR register Not co
445. s set to 0 2 8 4 Sign Flag S The S flag is set to 1 when an arithmetic operation results in a negative value Otherwise it is set to 0 2 8 5 Register Bank Select Flag B Register bank 0 is selected when the B flag is 0 Register bank 1 is selected when this flag is 1 2 8 6 Overflow Flag O The O flag is set to 1 when an operation results in an overflow Otherwise it is set to 0 RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 12 of 426 May 18 2012 R8C M11A Group R8C M12A Group 2 Central Processing Unit CPU 2 8 7 Interrupt Enable Flag I The I flag enables maskable interrupts Interrupts are disabled when the I flag is 0 and are enabled when the I flag is 1 The I flag is set to 0 when an interrupt request is acknowledged 2 8 8 Stack Pointer Select Flag U ISP is selected when the U flag is 0 USP is selected when the U flag is 1 The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7 If a requested interrupt has higher priority than IPL the interrupt is enabled If IPL is set to levels from 2 to 7 all maskable interrupt requests are disabled 2 8 10 Reserved Bit The write value must be 0 The read value is undefined RO1UHO050EJ0200 Rev 2 00 stENESAS Page 13 of 426 May 18
446. s used to set the output value from the TRCIOA pin until the first compare match A occurs In PWM mode this bit is used to control the output level of the TRCIOA pin TOB Bit Timer output level select B bit This bit is used to set the output value from the TRCIOB pin until the first compare match B occurs In PWM mode this bit is used to control the output level of the TRCIOB pin TOC Bit Timer output level select C bit This bit is used to set the output value from the TRCIOC pin until the first compare match C occurs In PWM mode this bit is used to control the output level of the TRCIOC pin TOD Bit Timer output level select D bit This bit is used to set the output value from the TRCIOD pin until the first compare match D occurs In PWM mode this bit is used to control the output level of the TRCIOD pin RO1UHO050EJ0200 Rev 2 00 RENESAS Page 236 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 5 Timer RC Interrupt Enable Register TRCIER Address 000F4h Bit After Reset b 7 b6 b5 b4 b3 b2 b1 b0 Smo OVE TT MED Ee E TER 0 1 Bit Name Function Input capture compare match A Interrupt request IMIA by IMFA bit in TRCSR interrupt enable bit register is disabled Interrupt request IMIA by IMFA bit in TRCSR register is enabled Input capture compare match B Interrupt request IMIB by IMFB bit in TRCSR interrupt enable bit register is disabled Interrupt request IMIB by
447. se by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 General Precautions in the Handling of MPU MCU Products The following usage notes are applica
448. select Register Setting Pin Function bits P4 6 P4_7 I O port I O port XIN clock input I O port External clock input I O port System clock output XIN XOUT Nothing is assigned The write value must be 0 The read value is 0 XIN XOUT on chip 0 On chip feedback resistor enabled feedback resistor 1 On chip feedback resistor disabled select bit Nothing is assigned The write value must be 0 The read value is 0 Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the EXCKCR register Bits CKPTO to CKPT1 Port PA Gand P4_7 pin function select bits When stopping oscillation with an oscillator attached set bits CKPT1 to CKPTO to 00b and set P4_6 and P4_7 to input ports according to Tables 12 18 and 12 19 While the high speed on chip oscillator clock or the low speed on chip oscillator clock is selected as the system base clock the system clock can be output from P4_7 by setting bits CKPT1 to CKPTO to 10b and bits P47SEL1 to P47SELO in the PMH4 register to 00b XRCUT Bit XIN XOUT on chip feedback resistor select bit The XRCUT bit is enabled only when bits CKPT1 to CKPTO are 1 1b When the STPM bit in the CKSTPR register is set to 1 stop mode the on chip feedback resistor is disabled RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 76 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 2 High Speed Low Speed On Ch
449. sh Memory RDYSTI Bit Flash ready status interrupt request flag When the RDYSTIE bit in the FMRO register is set to 1 flash ready status interrupt enabled and auto programming or auto erase completes or suspend mode is entered the RDYSTI bit is set to 1 flash ready status interrupt requested During interrupt handling set the RDYSTI bit to 0 no flash ready status interrupt requested Condition for setting to 0 e When 0 is written to this bit after reading it as 1 Condition for setting to 1 e If the flash memory status transits from busy to ready when the RDYSTIE bit in the FMRO register is 1 flash ready status interrupt request enabled The status changes from busy to ready in the following states e Completion of programming erasing the flash memory e Suspend acknowledgement e Completion of forced termination e Completion of the lock bit program e Completion of the read lock bit status e Completion of the block blank check e When the flash memory can be read after it has been activated from disabling flash memory stop BSYAEI Bit Flash access error interrupt request flag The BSYAEI bit is set to 1 flash access error interrupt requested if the user ROM area is read or written while the flash memory is busy when the BS YAEIE bit in the FMRO register is 1 flash access error interrupt enabled The BS YAEI bit is also set to 1 if a block erase error program error block blank check error command sequence e
450. sh Ready Status Interrupt Disabled and Suspend Enabled R01UH0050EJ0200 Rev 2 00 stENESAS May 18 2012 Page 348 of 426 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 6 4 Block Erase When 20h is written as the first command and then DOh is written to any address in the block with the second command an auto erase erase and erase verify operation is started in the specified block The FST7 bit in the FST register can be used to confirm whether auto erase is completed The FST7 bit is set to 0 during auto erase and changed to 1 when auto erase is completed After auto erase completes all data in the block is set to FFh After auto erase is completed the result can be confirmed by the FSTS bit in the FST register see 19 6 7 Full Status Check For each block in the program ROM the program erase command can be disabled using the lock bit When the FMR16 bit in the FMRI register is 1 rewrite disabled the block erase command for block A of data flash is not accepted When the FMR17 bit is 1 rewrite disabled the block erase command for block B is not accepted Figure 19 12 shows the Block Erase Flowchart Flash Ready Status Interrupt Disabled and Suspend Disabled Figure 19 13 shows the Block Erase Flowchart in EW Mode Flash Ready Status Interrupt Disabled and Suspend Enabled Figure 19 14 shows the Block Erase Flowchart in EWO Mode Flash Ready Status Interrupt Enabled and Suspend Enabled Figure 19 15 shows the Bl
451. shot mode or single sweep mode e When 0 is written to this bit by software A D conversion stops Conditions for setting to 1 e When is written to this bit by software A D conversion starts e When the A D conversion start trigger enabled by the TRCADCR register is input e When an external trigger ADTRG is input RO1UH0050EJ0200 Rev 2 00 RENESAS Page 305 of 426 May 18 2012 R8C M11A Group R8C M12A Group 17 A D Converter 17 2 5 A D Interrupt Control Status Register ADICSR Address 0009Fh Bit b7 b6 b5 b4 b3 b2 b1 b0 sma a ae After Reset 0 0 0 0 0 0 0 0 Bit Name Function Reserved Set to 0 A D conversion interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled A D conversion interrupt request bit 0 No interrupt requested 1 Interrupt requested Note 1 Only 0 no interrupt requested can be written to the ADF bit ADF Bit A D conversion interrupt request bit This bit indicates whether an A D conversion interrupt is requested It also indicates whether A D conversion has completed Conditions for setting to 0 e When 0 is written to this bit after reading it as 1 Conditions for setting to 1 e When A D conversion is completed in one shot mode or single sweep mode e When A D conversion is completed on all the selected channels in repeat mode or repeat sweep mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 306 o
452. si iieo eee rea rr E TE ero EE aer ESEE EE STEES e EErEE Et 314 17 5 1 A D Converter Standby Setting 20 0 ieiet eneee renier e ag OOs EEE E EENE aE Eaker 314 17 5 2 Sensor Output Impedance during A D Conversion ssseesseeeseesressseessreresreresrrsrertsrerinsreresrnertnserreseeeesr 314 17 5 3 Register Seting th iste esac Atel ete ines eas a Se I A R AEAT 315 18 Comparator EE 316 18 1 COVEL EE 316 18 2 Registers verore eaei Derek ee SCENE dedetiede feed e ve a a Eie deeg tends 318 18 2 1 Comparator B Control Register WCMPR 00 ee cece eeeeeeeeeeeeseeseecnecasecaecsacsaecnsessecseeeseseeseseseneeaaeeaee 318 18 2 2 Comparator B1 Interrupt Control Register WCB ILINTR oe eee cee ceecsecsseeeceeensecesceseseeeeseeeaeeaeeeaes 319 18 2 3 Comparator B3 Interrupt Control Register WCB3INTR eee ee eecceeeeeeeeseeeeecaeecaecesesaecneesseeneensees 320 18 3 EIDEL ee EES aed 321 18 3 1 Comparator Bi Digital Filter i 1 or 3 oe eee eceeeeeeeceeeseecaeceaesaeceecsesseeeeeeseseaeeseesaecaeceseseensensees 321 18 3 2 Comparator Bi i 1 or 3 Setting Procedure and Operation Example 0 0 0 cece ee eeseeeceeeeeeeeeeeeenes 322 A 8 19 Flash MEMON EE 324 19 1 QOVELVICW geesde eege den 324 19 2 Memory Mapisnees nsecisst ne eee eo ai HE ie OR a ee eal Se oes 325 19 3 WD Code Check Functon ressesie nee iee S REEERE eS o ERNES S SEESE RE EEES 326 19 3 Oper ti n EE 327 1T9 3 2 Reserved Words orei e a ai ees EES Ae Ges reba 327 19
453. sing power The lower the CPU clock frequency the lower the power consumption Stopping unnecessary oscillation circuits will further reduce power consumption When the clock sources for the CPU clock are switched the new clock needs to be oscillating and stable Assure the wait time for the new clock oscillation to stabilize by a program before switching the clocks Table 10 2 lists the Register Settings in Standard Operating Mode Table 10 2 mode Register OCOCR Register Settings in Standard Operating Mode SCKCR CKSTPR EXCKCR Bit HOCOE LOCODIS HSCKSEL SCKSEL CKPT1 CKPTO Content to be Switched High speed clock fHOCO Oscillate Stop fLOCO Oscillate Stop XIN FHOCO fLOCO fHSCK DA Gand P4_7 Pin Function High speed on chip oscillator mode P oscillate Low speed on chip oscillator mode Indicates that either 0 or 1 can be set The setting in is selected oscillate RO1UH0050EJ0200 Rev 2 00 May 18 2012 stENESAS Page 95 of 426 R8C M11A Group R8C M12A Group 10 Power Control 10 2 1 High Speed Clock Mode When the HSCKSEL bit in the SCKCR register is 0 XIN clock and the SCKSEL bit in the CKSTPR register is 1 fHSCK the XIN clock is used as the system base clock fBASE At this time the system clock is obtained by dividing the XIN clock by any value from no division to 256 The CPU clock is obtained by div
454. ssion Tans clock External CKDIR 1 Clock synchronous type control circuit CKDIR 0 Clock synchronous type internal clock selected 1 2 Clock synchronous type CKDIR 1 external clock selected CLK Clock synchronous type internal clock selected polarity switch circuit CKDIR Bit in UOMR register CLKO to CLK1 Bits in UOCO register Figure 16 1 UARTO Block Diagram RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 278 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO Clock synchronous type UART 7 bits Clock gt UARTO synchronous i receive register PAR disabled type PRYE 0 O Digital filter synchronous type PAR enabled UART 8 bits MSB LSB conversion circuit UART 9 bits D7 D6 D5 D41D3 D2 1D1 D0 UORD register Data bus bits D7 D6 D5 D41D3 D21D1 DO Clock synchronous PAR enabled type MSBILSB conversion circuit PRYE 1 UART 8 bits O PAR disabled PRYE 0 Clock synchronous UARTO UART type synchronous A 0 yp y 7 bits transmit register SP Stop bit PAR Parity bit PRYE Bit in UOMR register Notes 1 Enabled when the DFE bit in the UOCO register is 1 in UART mode 2 Disabled when the DFE bit in the UOCO register is 0 in UART mode or when in clock synchronous mode Figure 16 2 Transmit Receive Unit Block Diagram Table 16 2 UARTO Pin Configuration Pin Name Assigned Pin
455. ster Table 11 6 lists the Relocatable Vector Table Table 11 6 Interrupt Source BRK instruction 2 Relocatable Vector Table Vector Address 1 Address L to Address H 0 to 3 00000h to 00003h Software Interrupt Number 11 Interrupts Priority Level Setting ILVLO or ILVL2 to ILVLE Flash ready 4 to 7 00004h to 00007h ILVLO5 to ILVLO4 Reserved O wo Comparator B1 16 to 19 00010h to 00013h ILVL21 to ILVL20 Comparator B3 20 to 23 00014h to 00017h ILVL25 to ILVL24 Reserved 24 to 27 00018h to 0001Bh Timer RC 28 to 31 0001Ch to 0001Fh ILVL35 to ILVL34 Reserved CO N On A IN O Reserved 32 to 35 00020h to 00023h 36 to 39 00024h to 00027h o Reserved 40 to 43 00028h to 0002Bh CH Reserved 44 to 47 0002Ch to 0002Fh b Reserved N Key input 48 to 51 00030h to 00033h 52 to 55 00034h to 00037h 4 wo ILVL65 to ILVL64 A D conversion 56 to 59 00038h to 0003Bh A ILVL71 to ILVL70 Reserved 60 to 63 0003Ch to 0003Fh i oa Reserved er e gt UARTO transmission 68 to 71 00044h to 00047h a N ILVL85 to ILVL84 UARTO reception 72 to 75 00048h to 0004Bh CO ILVL91 to ILVL90 Reserved 76 to 79 0004Ch to 0004Fh 4 o Reserved
456. ster is set to 1 count source protection mode enabled the following are automatically set The low speed on chip oscillator oscillates e The RIS bit in the RISR register is set to 1 watchdog timer reset RO1UHOO50EJ0200 Rev 2 00 stENESAS Page 69 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 3 4 Periodic Timer Function The count range is determined by the underflow period setting bits WDTUFSO to WDTUFS 1 in the OFS2 register and the refresh acceptance period setting bits WDTRCSO to WDTRCS 1 in the OFS register The periodic timer cannot be used in stop mode Table 8 5 lists the Periodic Timer Settings Figure 8 3 shows the Timing of Periodic Timer Function When the periodic timer runs beyond the count range in Table 8 5 the WDTIF bit in the WDTIR register is set to periodic timer interrupt requested Table 8 5 Periodic Timer Settings Initial Value Set by Bits WDTUFS1 Refresh Range Set by Bits WDTRCS1 to to WDTUFSO in OFS2 Register WDTRCS0 in OFS2 Register 1 Range Counted by Periodic Timer 3FFFh gt 2FFFh 3FFFh gt 1FFFh 3FFFh OFFFh 1FFFh gt 17FFh 1FFFh gt OFFFh 1FFFh gt 07FFh OFFFh gt OBFFh OFFFh 07FFh OFFFh gt 03FFh 03FFh gt 02FFh 03FFh gt O1FFh 03FFh gt OOFFh Note 1 When bits WDTRCS1 to WDTRCSO in the OFS2 register is 11b 100 set the WDTIE bit to 0 periodic timer interrupt disabled Co
457. stop mode WCKSTP fBASE stop bit in wait mode 0 System clock supplied in wait mode 1 System clock stopped in wait mode PSCSTP Prescaler stop bit 0 Prescaler operates 1 Prescaler is stopped Nothing is assigned The write value must be 0 The read value is 0 SCKSEL System base clock select bit Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the CKSTPR register STPM Bit All clock stop control bit The low speed on chip oscillator clock is not stopped when e The count source protection mode for the watchdog timer is enabled e A clock obtained by dividing the low speed on chip oscillator by 16 is selected as the count source for the watchdog timer WCKSTP Bit fBASE stop bit in wait mode This bit is used to control supply and stop of the system clock in wait mode PSCSTP Bit Prescaler stop bit Setting the PSCSTP bit to 1 stops the prescaler The peripheral functions that use f2 to f128 are stopped operating However the values of corresponding registers are retained SCKSEL Bit System base clock select bit Conditions for setting to 0 e When 0 is written to this bit e When the XIN clock oscillation stop is detected and the system clock is switched to LOCO if the XIN clock is selected as the system clock and the XINBAKE bit in the BAKCR register is 1 oscillation stop detection function enabled Conditions for setting to 1 e When is writte
458. t When the SRST bit is set to 1 the entire MCU is reset The read value is 0 For details see 6 Resets RO1UHO050Ev0200 Rev 2 00 stENESAS Page 26 of 426 May 18 2012 R8C M11A Group R8C M12A Group 5 System Control 5 2 2 Module Standby Control Register MSTCR Address 00012h Bit b7 b6 b5 b4 b3 b2 bi bO Symbol MSTUART WSTTRC MSTAD MSTRE WSTTRI After Reset 0 0 0 0 0 0 0 0 The above applies when the MSTINI bit in the OFS2 register is 0 After Reset 0 1 1 1 0 1 1 1 The above applies when the MSTINI bit in the OFS2 register is 1 Bit Name Function MSTTRJ Timer RJ2 standby bit 0 Active 1 Standby 1 MSTTRB Timer RB2 standby bit 0 Active 1 Standby 2 Reserved Set to 0 The read value is undefined Nothing is assigned The write value must be 0 The read value is 0 MSTAD_ A D converter standby bit 0 Active 1 Standby 3 MSTTRC Timer RC standby bit 0 Active 1 Standby 4 MSTUART UARTO standby bit 0 Active 1 Standby 5 Nothing is assigned The write value must be 0 The read value is 0 Notes 1 When the MSTTRJ bit is set to 1 standby access to the registers associated with timer RJ2 addresses 000D8h to OOODEN is disabled 2 When the MSTTRB bit is set to 1 standby access to the registers associated with timer RB2 addresses OO0EOh to 000E7h is disabled 3 When the MSTAD bit is set to 1 standby access to the r
459. t 1 rising edge in TRBIOC register e TCNT16 bit in TRBMR register 1 16 bit timer Figure 14 6 Example of 16 Bit Timer Operation in Programmable One Shot Generation Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 214 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 4 4 Programmable Wait One Shot Generation Mode In this mode a one shot pulse is output from the TRBO pin by a program or an external trigger INTO pin input after a specified period When a trigger is generated from that point the timer outputs a pulse only once for a given length of the time equal to the setting value of the TRBSC register after waiting for a given length of time equal to the setting value of the TRBPR register In the 8 bit timer with 8 bit prescaler set the count value of the wait time in the TRBPR register and set the count value of the pulse width in the TRBSC register In the 16 bit timer set the count value of the wait time of the higher 8 bits in the TRBPR register and that of the lower 8 bits in the TRBPRE register Set the count value of the pulse width of the higher 8 bits in the TRBSC register and that of the lower 8 bits in the TRBPRE register When one shot count is started is written to the TOSST bit in the TRBOCR register while the TCSTF bit in the TRBCR register is 1 count is enabled the count is started after the count source is sampled three times If an enabled trigger is input to the INTO pin while
460. t 1 Voltage monitor 0 reset disabled after reset CSPROINI Count source protection mode 0 Count source protect mode enabled after reset after reset select bit 1 Count source protect mode disabled after reset Note 1 The OFS register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS register Erasure of the block including the OFS register causes the OFS register to be set to FFh When blank products are shipped the OFS register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS register is the value programmed by the user For an example of the OFS register settings see 5 6 1 Option Function Select Area Setting Example WDTON Bit Watchdog timer start select bit This bit is used to select whether the watchdog timer is automatically started after a reset is cleared Bits VDSELO to VDSEL1 Voltage detection 0 level select bits These bits are used to select the detection level Vdet0 for voltage monitor 0 reset The same level of the voltage detection 0 level selected by bits VDSELO to VDSELI1 is set in both the voltage monitor 0 reset and power on reset functions LVDAS Bit Voltage detection 0 circuit start bit This bit is used to select whether voltage monitor 0 reset is enabled Set the LVDAS bit to 0 voltage monitor
461. t A D conversion is started on the selected channel 2 When A D conversion completes the result is transferred to the ADi register i 0 or 1 corresponding to the channel 3 When A D conversion completes the ADF bit in the ADICSR register is set to 1 interrupt requested Writing 0 after reading the value sets the ADF bit to 0 no interrupt requested 4 While the ADST bit is 1 A D conversion starts steps between 2 and 3 are repeated When the ADST bit is set to 0 A D conversion stops A D conversion is stopped and the A D converter enters the standby state Then when the ADST bit is set to 1 A D conversion is restarted on the selected channel ADST bit in ADCONDO register ADF bit in ADICSR register Channe 0 ANO in operation Channe 1 AN1 in operation Channe 2 AN2 in operation Channe 3 AN3 in operation Channe 4 AN4 in operation Channe 7 AN7 in operation ADO register AD1 register Figure 17 5 Set to 1 by a program A D conversion is performed repeatedly A D conversion starts y A D conversion A D conversion result 1 result 2 d A D conversion result 3 Set to 0 by a program Set to 0 by a program 1 When the ADST bit is set to 0 by a program the result of the corresponding A D conversion is not stored in the ADi register Operation Example in Repeat Mode When Channel 1 is Selected R01UH0050EJ0200 Rev 2 00 May 1
462. t and Operation The RESET pin is multiplexed with port PA_0 so it can be used as general purpose I O ports when not used for a hardware reset For details see 12 11 1 Notes on PA_0 Pin 6 3 2 1 When Power Supply is Stable 1 Input a low level to the RESET pin 2 Wait for 10 ps 3 Input a high level to the RESET pin 6 3 2 2 When Power Supply is Turned on 1 Input a low level to the RESET pin 2 Let the power supply voltage increase until it meets the recommended operating conditions 3 Wait for td P R until the internal power supply is stabilized see 20 Electrical Characteristics 4 Wait for 10 ps 5 Input a high level to the RESET pin Power supply 5V voltage detection circuit AN VCC oV 5V td P R 10 us or more L Example when VCC 5 V Note 1 See 20 Electrical Characteristics Figure 6 3 Hardware Reset Circuit Example Using External Power Supply Voltage Detection Circuit and Operation RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 43 of 426 May 18 2012 R8C M11A Group R8C M12A Group 6 Resets 6 3 3 Power On Reset When the RESET pin is connected to the VCC pin via a resistor and the VCC pin voltage level rises the power on reset is activated and the CPU SFRs and I O ports are initialized The internal RAM values will be undefined In addition when a capacitor is connected to the RESET pin assure that the voltage applied to the RESET pin i
463. t 1 AIEN10 AIADR1 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 133 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 8 How to Determine Interrupt Sources Table 11 15 lists How to Determine Interrupt Source for Oscillation Stop Detection Interrupt Watchdog Timer Interrupt or Voltage Monitor 1 Interrupt Figure 11 12 shows Example of How to Determine Interrupt Sources for Oscillation Stop Detection Interrupt Watchdog Timer Interrupt or Voltage Monitor 1 Interrupt Table 11 15 How to Determine Interrupt Source for Oscillation Stop Detection Interrupt Watchdog Timer Interrupt or Voltage Monitor 1 Interrupt Generated Interrupt Source Bit Indicating Interrupt Source Oscillation stop detection CKSWIF bit in BAKCR register 1 Watchdog timer UFIF bit in RISR register 1 Voltage monitor 1 VW1C2 bit in VW1C register 1 Determining interrupt source CKSWIF 1 oscillation stop detected UFIF 1 watchdog timer underflow Set the CKSWIE bit to 0 oscillation stop detection interrupt disabled Set the CKSWIF bit to 0 no oscillation stop detection interrupt requested To oscillation stop To watchdog timer To voltage monitor 1 detection interrupt routine interrupt routine interrupt routine CKSWIE CKSWIF Bits in BAKCR register UFIF Bit in RISR register Figure 11 12 Example of How to Determine Interrupt Sources for Oscillation Stop Detection Interrupt Watchdog
464. t Interrupt KIi i 0 to 3 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 135 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 9 4 Rewriting Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN When changing the functions of the INTO to INT3 and KIO to KI3 interrupts an interrupt request flag may be set to 1 by rewriting registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN When an interrupt function is switched rewrite these registers with interrupt requests disabled and wait for a certain period before setting the interrupt request flag to 0 Figure 11 13 shows the Procedure for Manipulating Registers PMLi PMHi i 1 3 or 4 ISCRO INTEN and KIEN and Setting Interrupt Request Flag to 0 Note 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INT3 or KIO to KI3 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT3 are used When all maskable interrupts can be disabled use the flag When all maskable interrupts cannot be disabled use the Interrupt disabled lt 4 corresponding bits ILVLjO to ILVLj1 or bits ILVLj4 to ILVLj5 j 6 A C D or E for the interrupt whose source to be changed Rewrite registers PMLi PMHi ISCRO INTEN and KIEN p ai After manipulating the registers wait for a certain period Wait for a certain period UI lt _ to set
465. t b7 b6 b5 b4 b3 b2 b1 bO Smo pP After Reset 0 0 0 0 0 0 0 0 Bit Name Function PAMCR register write enable bit 0 Write disabled 1 1 Write enabled Nothing is assigned The write value must be 0 The read value is 0 Note 1 To set this bit to 1 first write O and then write 1 immediately Interrupts must be disabled between writing 0 and then writing 1 PAMCRE Bit PAMCR register write enable bit Condition for setting to 0 e When 0 is written to this bit Condition for setting to 1 e When 0 and then 1 is written to this bit RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 28 of 426 May 18 2012 R8C M11A Group R8C M12A Group 5 System Control 5 2 5 Reset Source Determination Register RSTFR Address 0005Fh Bit b7 b6 b5 b4 b3 b2 b1 bO Smo WoR sw am ew After Reset 0 0 0 0 X 1 X 1 x x1 Bit Name Function Cold start up warm start up Cold start up determine flag Warm start up Hardware reset detect flag Not detected Detected Not detected Detected Not detected Detected Nothing is assigned The write value must be 0 The read value is 0 Software reset detect flag Watchdog timer reset detect flag 0 1 0 1 0 1 0 1 Note 1 The value after a reset differs depending on the reset source CWR Bit Cold start up warm start up determine flag This flag indicates whet
466. t be monitored with the TCSTF bit in the TRBCR register An interrupt request is generated when timer RB2 underflows When registers TRBPRE and TRBPR are read each count value can be read When registers TRBPRE and TRBPR are written while the count is stopped values are written to both the reload register and counter respectively When these registers are written during the count operation values are written to the reload register and then transferred to the counter at the next reload operation For the setting of trigger by the INTO input see 14 7 INTO Input Trigger Selection Figure 14 5 shows an Example of 8 Bit Timer with 8 Bit Prescaler Operation in Programmable One Shot Generation Mode Figure 14 6 shows an Example of 16 Bit Timer Operation in Programmable One Shot Generation Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 212 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 Set to 1 by a program UH i TSTART bit in TRBCR register l Set to 0 on Set to 1 by INTO mpletion of count input trigger 1 is written to TOSST Comp en S input trigg bit in TRBOCR TOSSTF bit in register TRBOCR register Count source Underflow signal from timer RB prescaler Timer RB2 counter Timer RB primary is reloaded Timer RB primary is reloaded H H Interrupt request signal Set to 0 by a program Set to 0 by a program TOPL bit in TRBIOC register I I U U U U I Waveform output is s
467. t capture compare match for the TRCGRA register TRCTRG input Setting function for initial output level Available Available Available Available Buffer operation Available Available Low level output Compare match Available Available Available Available High level output Available Available Available Available Toggle output Available Available Available Available Input capture function Available Available Available Available PWM mode Available Available Available PWM2 mode Available Interrupt sources Overflow RO1UHO050EJ0200 Rev 2 00 May 18 2012 Compare match input capture Compare match input capture ztENESAS Compare match input capture Compare match input capture Page 230 of 426 R8C M11A Group R8C M12A Group 15 Timer RC f1 f2 f4 f8 82 or fHOCO TRCMR register TRCCR1 register TRCIER register TRCCLK _ Count source Comparator TRCSR register selection circuit TRCIOA TRCTRG Cet P TRCIORO register TRCIOB lt gt TRCIOR1 register Timer RC control circuit TRCIOC lt gt TRCCNT register TRCIOD Cas TRCGRA register Waveform output TRCGRB register manipulation TRCGRC register TRCGRD register TRCCR2 register Timer RC TRCDF register interrupt request peed TRCOER register TRCADCR register T
468. t control P1_5 P1_7 P4_6 External pulse input and pulse output for timer RJ2 P1_6 P3_7 Pulse output for timer RJ2 Note 1 When a pulse is output from TRJIO and TRJO simultaneously TRJIO is set to the inverted output of TRJO RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 179 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 3 Registers Table 13 3 lists the Timer RJ2 Register Configuration Table 13 3 Timer RJ2 Register Configuration Register Name After Reset Address Access Size Timer RJ Counter Register TRJ 000D8h 000D9h Timer RJ Control Register TRJCR OOODAh Timer RJ I O Control Register TRJIOC OOODBh Timer RJ Mode Register TRJMR 000DCh Timer RJ Event Select Register TRJISR 000DDh Timer RJ Interrupt Control Register TRJIR 000DEh 13 3 1 Timer RJ Counter Register TRJ Timer RJ Reload Register Address 000D8h to 000D9h Bit b7 b6 b5 b4 b3 b2 b1 b0 S Se ter Reset Bit b15 mu ba ms bn bp b9 b8 R SC ter Reset J Senma Range b15tob0 16 bit counter and reload register 1 2 3 0001h to FFFFh R W Notes 1 When 1 is written to the TSTOP bit in the TRUCR register the 16 bit counter is forcibly stopped and set to FFFFh 2 The TRJ register must be accessed in 16 bit units Do not access this register in 8 bit units When this register is accessed as 16 bit units it is accessed twice in 8 bit units 3 Do not set the TRJ register to 0000h in puls
469. t set 1 1 Do not set Nothing is assigned The write value must be 0 The read value is 0 WAITM _ Wait control bit 0 Not in wait mode 1 Wait mode is entered HSCKSEL High speed on chip oscillator XIN clock 0 XIN clock select bit 1 High speed on chip oscillator clock Nothing is assigned The write value must be 0 The read value is 0 Set the PRCO bit in the PRCR register to 1 write enabled before rewriting the SCKCR register Bits PHISSELO to PHISSEL2 CPU clock division ratio select bits Bits PHISSEL2 to PHISSELO are set to 000b system clock with no division if the PHISRS bit in the CKRSCR register is 1 no division when the MCU returns from wait mode or stop mode WAITM Bit Wait control bit Condition for setting to 0 e When a peripheral function interrupt is used to return from wait mode Condition for setting to 1 e When is written to the WAITM bit after the PRCO bit in the PRCR register is set to 1 write enabled RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 78 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 2 4 System Clock f Select Register PHISEL Address 00023h Bit b 7 b6 b5 b4 b3 b2 b1 bO Symbol PHISEL7 PHISEL6 PHISEL5 PHISEL4 PHISEL3 PHISEL2 PHISEL1 PHISELO 0 0 0 0 0 0 0 After Reset 0 Bit Name Function b7 to bO PHISEL7 System clock division These bits used to set the division ratio of the
470. t to 0 4 Leben i 1 I DECH ee a BEE 3 H Li E TC e Se E mi ie WW a me H J Timer RC output TRCIOB_XP internal signal Output control signal TRCOBE_XN internal signal 4 E Output is enabled I U I i i BEE TRCIOB output Timer RC output level is fixed at high during waveform output pi manipulation period Ma Synchronized so that less than one cycle of waveform is not output J Figure 15 26 Example of Waveform Output Manipulation Operation 4 RO1UH0050EJ0200 Rev 2 00 RENESAS Page 268 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 5 Operation Timing 15 5 1 TRCCNT Register Count Timing Figure 15 27 shows the Count Operation Timing e Internal clock PLE LI LIU UU LU Uk Internal clock Rising edge TRCCNT register internal clock TRCCNT register e External clock External clock Falling edge TRCCNT register internal clock TRCCNT register Figure 15 27 Count Operation Timing RO1UH0050EJ0200 Rev 2 00 RENESAS Page 269 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 5 2 Output Compare Output Timing A compare match signal occurs at the last state timing when the TRCCNT register updates a matched value when the TRCCNT register and the general register match When the compare match occurs the output value set by the TRCIOR register is
471. t to 1 interrupt requested at that time and the value set in the reload register is loaded simultaneously When the TRJIE bit in the TRJIR register is 1 interrupt enabled an interrupt request signal is generated to the CPU Figure 13 3 shows an Operation Example in Timer Mode Write 1010h to TRJ register by a program Count source Reload register Previous value 0300h of counter The counter is reloaded with the reload The counter is reloaded with the reload register register value by the first count source value on the completion of the 16 bit count Timer RJ2 counter Interrupt request signal Timer RJ2 counter underflow Set to 0 by a program Figure 13 3 Operation Example in Timer Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 187 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 3 Pulse Output Mode In this mode the counter is decremented by the count source selected by bits TCKO to TCK2 in the TRJMR register and a pulse is output from the TRJIO pin The output level is inverted when an underflow occurs The count value is decremented by each time the count source is input and an underflow occurs if the next count source is input after the count value reaches 0000h The TRJIF bit in the TRJIR register is set to 1 interrupt requested at that time and the value set in the reload register is loaded simultaneously When the TRJIE bit in the TRJIR register is 1 interrupt enabled an int
472. t to the TRJIO pin the count value is transferred to the read out buffer on the rising edge of the count source The value in the reload register is loaded to the counter on the next rising edge The TEDGF bit in the TRJCR register is set to 1 active edge received and the TRJIF bit in the TRJIR register is set to 1 interrupt requested at the same time The read out buffer TRJ register is read at this time and the difference from the reload value is the period data of the input pulse The period data is retained until the read out buffer is read When the counter underflows the TUNDF bit in the TRJCR register is set to 1 underflow and the TRJIF bit in the TRJIR register is set to 1 interrupt requested When the TRJIE bit in the TRJIR register is 1 interrupt enabled an interrupt request signal is generated to the CPU Figure 13 7 shows an Operation Example in Pulse Period Measurement Mode Only input pulses with a period longer than twice the period of the count source Also the low level and high level widths must be both longer than the period of the count source If a pulse period shorter than these conditions is input the input may be ignored This example applies when the initial value in the TRJ register is set to 0300h the TEDGSEL bit in the TRJIOC register is set to 0 and the period from one rising edge to the next edge of the measurement pulse is measured Count source L 1 1 1 TSTART bit in H H TRUJCR
473. t used set the MSTUART bit in the MSTCR register to 1 standby RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 104 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 5 9 Reducing Internal Power Consumption When entering wait mode using low speed on chip clock mode or low speed on chip oscillator mode internal power consumption can be reduced using the LPE bit in the VCA2 register To enable low internal power consumption using the LPE bit follow Figure 10 5 Procedure for Reducing Internal Power Consumption by Using LPE Bit Return from wait mode by an interrupt 1 2 Procedure for reducing internal power e consumption enabled by the LPE bit In the interrupt routine Enter low speed on chip oscillator mode LPE lt 0 low power consumption wait mode disabled 4 When returning from wait mode the MCU is automatically set as above Stop the XIN clock and high speed on chip oscillator clock Start the XIN clock or high speed on chip oscillator clock ae If it is necessary to WTFMSTP lt 1 start the high speed flash memory is stopped in wait mode clock or high speed Wait until the XIN clock or high speed on chip on chip oscillator in oscillator clock oscillation stabilizes the interrupt TPE 4 routine execute n in low power consumption wait mode enabled 4 5 Se ES Enter high speed clock mode or Enter wait mode 9 high speed on chip oscillator mode Interrupt handl
474. ta register R1 Data register R3 Data register R2 Address register A0 Address register A1 Frame base register FB Interrupt table register INTB Program counter PC User stack pointer USP Interrupt stack pointer ISP Static base register SB Flag register FLG R01UH0050EJ0200 Rev 2 00 RENESAS May 18 2012 Page 48 of 426 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 Voltage Detection Circuit The voltage detection circuit is used to monitor the voltage applied to the VCC pin The VCC input voltage can be monitored by a program 7 1 Overview The detection voltage for voltage detection 0 can be selected from four levels with the OFS register For details on the OFS register see 5 System Control The detection voltage for voltage detection 1 can be selected from eight levels with the VD1LS register The voltage monitor 0 reset and voltage monitor 1 interrupt can be used Table 7 1 lists the Voltage Detection Circuit Specifications Figure 7 1 shows the Voltage Detection Circuit Block Diagram Figure 7 2 shows the Voltage Monitor 0 Reset Generation Circuit Block Diagram Figure 7 3 shows the Voltage Monitor 1 Interrupt Generation Circuit Block Diagram Table 7 1 VCC monitor Voltage to be monitored Voltage Detection Circuit Specifications Voltage Monitor 0 VdetO Voltage Monitor 1 Vdet1 Detection target Detection by passing down through Vd
475. tage detection 0 circuit VWOC1 0 Level NGE selection Digital Voltage filter detection 0 signal Ui VDSELO to VDSEL1 Reference voltage Voltage monitor 0 reset signal VCOE Bit in VCA2 register VWO0CO VW0C1 VWOFO to VWOF1 Bits in VWOC register VDSELO to VDSEL1 Bits in OFS register Note 1 When the VCOE bit is 0 voltage detection 0 circuit disabled the voltage detection 0 signal will be high Figure 7 2 Voltage Monitor 0 Reset Generation Circuit Block Diagram Voltage monitor 1 interrupt generation circuit VW1F1 to VW1FO 00b Voltage detection 1 circuit Watchdog timer VW1C3 interrupt signal Level VW1C1 0 VOG selection Voltage VD1S1 to detection VD1S3 1 signal Reference voltage VCAC1 Bit in VCAC register VC1E Bit in VCA2 register VD1S1 to VD1S3 Bits in VD1LS register VW1C1 1 Digital filter VW1C02 selection circuit VW1CO VW1C1 VW1C2 VW1C3 VW1FO to VW1F1 VW1C7 Bits in VW1C register Notes 1 When the VC1E bit is 0 voltage detection 1 circuit disabled the voltage detection 1 signal will be high 2 The VW1C2 bit is set to 0 by writing 0 by a program When the VC1E bit is 0 voltage detection 1 circuit disabled the VW1C2 bit will be 0 not detected Figure 7 3 RO1UHO050EJ0200 Rev 2 00 May 18 2012 Voltage Monitor 1 Interrupt Generation Circuit Block Diagram ztENESAS Voltage monitor
476. tages When performing a program erase operation use a VCC supply voltage in the range of 1 8 V to 5 5 V Do not perform a program erase operation at less than 1 8 V 19 8 2 8 Block Blank Check Do not execute a block blank check command during erase suspend R01UH0050EJ0200 Rev 2 00 zeENESAS Page 364 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 8 2 9 EW1 Mode When setting the FMRO1 bit in the FMRO register to 1 CPU rewrite mode enabled and the FMRO2 bit to 1 EW 1 mode to execute CPU rewrite mode follow the procedure below in EW1 mode Figure 19 22 shows the Procedure for Software Command Execution When Suspend is Disabled Figure 19 23 shows the Procedure for Software Command Execution When Suspend is Enabled When the FMR01 bit is 1 CPU rewrite mode enabled the FMRO2 bit is 1 EW1 mode and the FMR20 bit is 0 suspend disabled Program example for the countermeasure when using the program command MOV B 40h A1 First command writing JMP S CMD2 NOP CMD2 JMP S CMD2 MOV B A0 A1 Second command writing 2 Additional MOV B A1 ROL Dummy read processing LABEL BTST FST7 Flash memory status confirmed JNC LABEL First command writing Specify instruction to be used Additional processing FMR01 FMRO02 Bits in the FMRO register FMR 20 Bit in the FMR2 register FST7 Bit in the FST register Notes 1 When executing the read array command and clear st
477. tarted Since auto erase or auto programming is forcibly stopped the correct values may not be read from the block being auto erased or the address being auto programmed After the flash memory is restarted execute auto erase again and verify it complete normally The watchdog timer does not stop while the command is executing so interrupt requests may be generated Initialize the watchdog timer periodically using the erase suspend function Since the flash memory control registers are initialized in this case these registers must be set again 1 FMR20 FMR21 FMR22 Bits in FMR2 register Note 1 Registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated while the flash memory is busy When the FMR01 bit in the FMRO register is 1 CPU rewrite mode enabled and the FMSTP bit is 1 flash memory is stopped registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 408 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 12 2 3 Access Methods To set one of the following bits to 1 first write 0 and then 1 immediately Interrupts must be disabled between writing 0 and then writing 1 e The FMRO1 or FMRO2 bit in the FMRO register e The FMR13 bit in the FMRI register e The FMR20 FMR22 or FMR27 bit in the FMR2 r
478. tarted Waveform output is completed Waveform output is started Waveform output is completed TRBO pin output The above diagram applies under the following conditions TRBPRE register 01h TRBPR register 01h e TOPL bit 0 TOCNT bit 0 waveform output INOSTG bit 1 one shot trigger to INTO pin enabled INOSEG bit 1 rising edge in TRBIOC register TCNT16 bit in TRBMR register 0 8 bit timer with 8 bit prescaler Figure 14 5 Example of 8 Bit Timer with 8 Bit Prescaler Operation in Programmable One Shot Generation Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 213 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 Set to 1 by a program l H TSTART bit in H TRBCR register Set to 0 on Set to 1 by INTO letion of count input trigger 1 is written to TOSST complenion ot COU input trigg bit in TRBOCR TOSSTF bit in register TRBOCR register Count source l Timer RB2 counter kenen Timer RB primary is reloaded Timer RB primary is reloaded 1 U Interrupt request signal Set to 0 by a program Set to 0 by a program TOPL bit in TRBIOC register Waveform output is started Waveform output is completed Waveform output is started Waveform output is completed TRBO pin output The above diagram applies under the following conditions e TRBPRE register 03h TRBPR register 00h e TOPL bit 0 TOCNT bit 0 waveform output INOSTG bit 1 one shot trigger to INTO pin enabled INOSEG bi
479. tarted by an external trigger input When bits ADCAP1 to ADCAPO in the ADMOD register are 11b A D conversion is started by external trigger ADTRG an external trigger can be input to the ADTRG pin The ADST bit in the ADCONDO register is set to 1 A D conversion starts on the rising edge of the ADTRG input pin and A D conversion is started Other operations are the same as when the ADST bit in the ADCONDO register set to 1 by software Figure 17 3 shows the External Trigger Input Timing ADTRG ADST bit in ADCONDO register A D conversion Internal synchronization period 2 to 3 cycles of fAD Figure 17 3 External Trigger Input Timing RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 308 of 426 R8C M11A Group R8C M12A Group 17 A D Converter 17 3 2 One Shot Mode Figure 17 4 shows an Operation Example in One Shot Mode When Channel 1 is Selected In one shot mode A D conversion of an analog input is performed for the specified single channel a single time as follows 1 When the ADST bit in the ADCONDO register is set to 1 A D conversion starts by software trigger timer RC trigger or external trigger input A D conversion is started on the selected channel 2 When A D conversion completes the result is transferred to the ADi register i 0 or 1 corresponding to the channel 3 When A D conversion completes the ADF bit in the ADICSR register is set to 1 interrupt requested Writing 0 after r
480. tch UND INTO and BRK instructions Single step Do not use during auto erasing or auto programming Watchdog timer Oscillation stop detection Voltage monitor 1 When an interrupt request is acknowledged auto erase or auto programming is forcibly stopped immediately and the flash memory is reset After the specified period the flash memory is restarted before interrupt handling is started Since auto erase or auto programming is forcibly stopped the correct values may not be read from the block being auto erased or the address being auto programmed After the flash memory is restarted execute auto erase again and verify it complete normally The watchdog timer does not stop while the command is executing so interrupt requests may be generated Initialize the watchdog timer periodically using the erase suspend function Since the flash memory control registers are initialized in this case these registers must be set again 1 FMR20 FMR21 FMR22 Bits in FMR2 register Note 1 Registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated while the flash memory is busy When the FMR01 bit in the FMRO register is 1 CPU rewrite mode enabled and the FMSTP bit is 1 flash memory is stopped registers FMRO FMR1 and FMR2 are initialized if a watchdog timer oscillation stop detection or voltage monitor 1 interrupt is generated
481. ter i 0 to 2 is Used for Peripheral Functions Timer RJ2 Timer RB2 and Timer RC RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 393 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 5 7 Changing Interrupt Priority Levels and Flag Registers a The interrupt priority level and the flag register must be changed only while no interrupt requests are generated If an interrupt may be generated using the I flag to disable the interrupt before changing the interrupt priority level and the flag register b When using the I flag to disable an interrupt set the I flag as shown in the sample programs below Examples 1 to 3 show how to prevent the I flag from being set to 1 interrupts enabled before the interrupt priority level and the flag register are changed due to effects of the internal bus and the instruction queue buffer Example 1 Use the NOP instruction to separate the interrupt priority level and the flag register operation and I flag operation INT_SWITCH1 FCLR I Disable interrupts AND B 0CFH ILVLE Set INTO interrupt priority level 0 NOP NOP FSET I Enable interrupts Example 2 Use a dummy read to delay the FSET instruction INT_SWITCH2 FCLR I Disable interrupts AND B 0CFH ILVLE Set INTO interrupt priority level 0 MOV W MEM RO Dummy read FSET I Enable interrupts Example 3 Use the POPC instruction to change the I flag INT_SWITCH3 PUSHC FLG FCLR I Disa
482. ter 4 PURA preisi eroten aE eea Saroe TEET er E Eer EEEE EEs 159 12 5 4 Open Drain Control Register 4 PODA sssssesssssssssisrssrsresrsresresrnsestssestestnsesteestestrtrsretnseetssretestssesresreresre 159 12 5 5 Port 4 Function Mapping Register 0 ODMI Ai 160 12 5 6 Port 4 Function Mapping Register 1 PMH4 oo ceeeeceseeeeeseecsecesecaecsaesaecnsesecnseeseseaeeseseaseneeeaes 160 12 5 7 Port 4 Function Mapping Expansion Register PMH4E 00 0 cece ececeeeeecseesseceeceseceecseesecneeeseseneeaeeeaes 161 LNS Pin Settings for Port 4 ee eeh onan Gl ead Aelia ene E he ay 162 12 6 POPU EE 163 2 6 1 Port PA Direction Register RAN teen See EE BEER EA EENS e ENEE ERAN 164 12 6 2 Port PA Re ister PA REECH 164 12 6 3 Port PA Mode Control Register PAMCR ccesccssssesseceececercessecescecsaeeeaeesceceaeseneeceneesaeeeseeceeeesaeeeneeees 165 12 6 4 Pin Setting for Port A EENS EENS 165 12 7 Procedure for Setting Peripheral Functions Associated with Ports 1 3 and 4 oo eee eeeeeeeeeeereereeenee 165 12 8 Pin Settings for Peripheral Function W O sssrinds ner pesso eines menie ee l aspre iasi piisi 166 12 9 Handling of Unused PINS iieiea naa E E ES EE E R ET E ES E IIE 167 12 10 VO Port Configuration 0 devs EENS aeo E AIA r E EEA a EEEE a thence 168 RTE Notes on TLO E 0 t EAEE EEE E E 177 UCL Notes oA PA O P a ee ee ees 177 SEL TO Pins for Peripheral uge Dong steiere a ewes E E SEE R EA E 177 EC St un eg EE 178 13 1
483. ter for Input Capture eee ya e e E ae E E E E 262 154 2 A D Conversion Start Tre ger si cc csccccssescsssscsecssscuscssck sesedcssessscesci ENEE EEN EES NEESS 263 15 4 3 Changing Output Pins and General Registers 0 eee ee eee eeceseecseceseeseceeceseeseeeeceeeeeecaeesaecaeeaeeneensensees 264 15 4 4 Waveform Output Manipulation Function 2 0 eee eeseeeeceseeseceeceseseeeeseseaeeseecaecasecaecsaesaecneesseesesees 266 15 5 Operation imine asco Ae ee Eer ee A As ee 269 Dr i TRCCNT Register Count TMINE sees gege EE a E E eegene tee Add 269 15 5 2 Output Compare Output Timing oo cece ceseeseceeceeeeeeeesesesecseecaecsaecaecsacsaecesesecseeseseeseaeseaeeaaeeaes 270 15 5 3 Input Capture Input Taming EEN EENEG 270 15 5 4 Timing for Counter Clearing by Compare Match A 271 15 5 5 Buffer Operation TIMINE ieies eieren enes r r AE EE 271 Dap Setting Timing at Compare Matebistscosesccsrecsesssesschaees Georg Seed 272 15 5 7 Setting Timing at Input Capture oo eee ceseeseceeceeeeeeeeeeeenecseecsecaaecaecsacsaecnsessesseseseaseaeseaeeaeeeaes 272 15 5 8 Timing for Setting Bits IMFA to IMFD and OVE to 0 oe cececeseceeceeeeseeeeeeseecaeessesaecsseeseeeeneeeaes 273 15 5 9 Timing of A D Conversion Start Trigger due to Compare Match 000 eee eeeeeeseeeeeceessecseensecneenseenees 273 15 6 Tamer RE Interrupt dee ee ove E EEO EEE sobs ap EREE 274 15 7 Notes om Timer RO cs 5ifccsssssssscesscessssts secascspesssvasscova chun so seasons Ee pTO dda seuss
484. ter is 0 The CSPROINI bit in the OFS register is 1 RO1UHO050EJ0200 Rev 2 00 May 18 2012 ztENESAS Page 15 of 426 R8C M11A Group R8C M12A Group Table 3 2 Address 0003Ah SFR Information 2 1 Register Name INT Input Filter Select Register 0 3 Address Space After Reset 0003Bh 0003Ch INT Input Edge Select Register 0 0003Dh 0003Eh Key Input Enable Register 0003Fh 00040h Interrupt Priority Level Register 0 00041h 00042h Interrupt Priority Level Register 2 00043h Interrupt Priority Level Register 3 00044h Interrupt Priority Level Register 4 00045h Interrupt Priority Level Register 5 00046h Interrupt Priority Level Register 6 00047h Interrupt Priority Level Register 7 00048h Interrupt Priority Level Register 8 00049h Interrupt Priority Level Register 9 0004Ah Interrupt Priority Level Register A 0004Bh Interrupt Priority Level Register B 0004Ch Interrupt Priority Level Register C 0004Dh Interrupt Priority Level Register D 0004Eh Interrupt Priority Level Register E 0004Fh 00050h Interrupt Monitor Flag Register 0 00051h Interrupt Monitor Flag Register 1 00052h Interrupt Monitor Flag Register 2 00053h External Interrupt Flag Register 00054h 00055h 00056h 00057h 00058h Voltage Monito
485. ter is 1 digital filter enabled the RXDO input is latched internally through the digital filter circuit for noise cancellation The noise canceller consists of three cascaded latch circuits and a match detection circuit When the RXDO input is sampled on the base clock with frequency of 16 times the transfer rate and three latch outputs match the level is passed forward to the next circuit When they do not match the previous level is retained That is if the RXDO input retains the same level for three clocks or more it is recognized as a signal If not it is recognized as noise Figure 16 8 shows the RXDO Digital Filter Block Diagram Sampling clock C D c y c Match DFE bit D Q D Q detection in UOCO Internal RXDO input l Latch it Latch ii circuit register Figure 16 8 RXDO Digital Filter Block Diagram 16 3 2 4 Dealing with Communication Errors If communication is aborted or a communication error occurs while transmitting or receiving in UART mode follow the procedure below 1 Set the TE bit in the UOC1 register to 0 transmission disabled and the RE bit to 0 reception disabled 2 Set bits SMD2 to SMDO in the UOMR register to 000b serial interface disabled 3 Set bits SMD2 to SMDO in the UOMR register to 100b UART mode transfer data 7 bits long 101b UART mode transfer data 8 bits long or 110b UART mode transfer data 9 bits long 4 Set the TE bit in the UOC1 register to 1 transmission enabled and the RE b
486. ter is written may be read In this case execute the JMP B instruction between the write and read instructions e Program Example MOV W XXXXh TRCCNT Write JMP B LI JMP B instruction LI MOV W TRCCNT DATA Read 15 7 2 TRCCR1 Register To set bits CKS2 to CKSO in the TRCCRI register to 110b HOCO set fHOCO to the clock frequency higher than the system clock frequency 15 7 3 TRCSR Register If the TRCSR register is written and read the value before this register is written may be read In this case execute the JMP B instruction between the write and read instructions e Program Example MOV B XXh TRCSR Write JMP B Ll JMP B instruction LI MOV B TRCSR DATA Read 15 7 4 Count Source Switching When switching the count sources stop the count before switching After switching the count sources wait for at least two cycles of the system clock before writing to the registers at addresses OOOE8h to 0OOFCh associated with timer RC e Switching procedure 1 Set the CTS bit in the TRCMR register to 0 count is stopped 2 Change bits CKSO to CKS2 in the TRCCR1 register 3 Wait for at least two cycles of the system clock 4 Write to the registers at addresses OOOE8h to OOOFCh associated with timer RC When changing the count source from fHOCO to another source and stopping fHOCO wait for at least two cycles of the system clock after changing the clock setting before stopping fHOCO e Switching procedure
487. ter wait mode while the WTFMSTP bit is 1 the flash memory is stopped in wait mode e Enter stop mode RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 412 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 21 13 Notes on Noise 21 13 1 Inserting a Bypass Capacitor between Pins VCC and VSS as a Countermeasure against Noise and Latch up Connect a bypass capacitor approximately 0 1 uF across pins VCC and VSS using the shortest and thickest possible wiring 21 13 2 Countermeasures against Noise Error in Port Control Registers During rigorous noise testing or the like external noise mainly power supply system noise can exceed the capacity of the MCU s internal noise control circuitry In such cases the contents of the port related registers may be changed As a firmware countermeasure it is recommended that the port registers port direction registers and pull up control registers be reset periodically However examine the control processing fully before introducing the reset routine as conflicts may occur between the reset routine and interrupt routines 21 14 Note on Power Supply Voltage Fluctuation After a reset is cleared the supply voltage applied to the VCC pin must meet either or both of the allowable ripple voltage Vr vcc and the ripple voltage falling gradient dVr vcc dt shown in Figure 21 11 Standard Symbol Parameter Typ Vr vcc Allowable ripple voltage dVr vcc dt Ripple voltage falling gr
488. ter written by the user When factory programming products are shipped the value of the OFS2 register is the value programmed by the user The OFS register is allocated in the flash memory not in the SFRs Set appropriate values as ROM data by a program Do not perform an additional write to the OFS register Erasure of the block including the OFS register causes the OFS register to be set to FFh When blank products are shipped the OFS register is set to FFh It is set to the written value after written by the user When factory programming products are shipped the value of the OFS register is the value programmed by the user 6 2 1 Processor Mode Register 0 PMO Address 00010h Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol Se ee Se After Reset 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 Software reset bit 0 State is retained 1 Reset is generated Nothing is assigned The write value must be 0 The read value is 0 Set the PRC1 bit in the PRCR register to 1 write enabled before rewriting the PMO register SRST Bit Software reset bit When the SRST bit is set to 1 the entire MCU is reset The read value is 0 For details see 6 Resets RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 37 of 426 May 18 2012 6 Resets R8C M11A Group R8C M12A Group 6 Resets 6 2 2 Reset Source Determination Register RSTFR Address 0005Fh Bit b7
489. terrupt request monitor flag Reserved The read value is 0 UARTO transmit interrupt request monitor flag 0 No interrupt requested UARTO receive interrupt request monitor flag 1 Interrupt requested Reserved The read value is 0 The IRRO register is the monitor flag register for timer RJ2 timer RB2 timer RC UARTO transmit and UARTO receive interrupt requests See 11 4 2 1 Registers IRRO to IRR2 for the relation between interrupt monitor flag bits and peripheral function interrupts 11 2 7 Interrupt Monitor Flag Register 1 IRR1 Address 00051h Bit b7 b6 b5 b4 b3 b2 b1 b smo wo eM RAD T After Reset 0 0 0 0 0 0 0 0 Bit Name Function Reserved The read value is 0 A D conversion interrupt request monitor flag 0 No interrupt requested 1 Interrupt requested Reserved The read value is 0 Flash ready interrupt request monitor flag 0 No interrupt requested Periodic timer interrupt request monitor flag 1 Interrupt requested Nothing is assigned The write value must be 0 The read value is 0 The IRR1 register is the monitor flag register for A D conversion flash ready and periodic timer interrupt requests See 11 4 2 1 Registers IRRO to IRR2 for the relation between interrupt monitor flag bits and peripheral function interrupts RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 116 of 426 May 18 2012 R8C M11A Group R8C M12A G
490. ters IRRO to IRR2 Registers IRRO to IRR2 are the monitor flag registers for peripheral function interrupts These registers can only be read and cannot be written Table 11 7 lists the Relation between Registers IRRO to IRR2 and Registers Associated with Peripheral Function Interrupts Peripheral functions have individual interrupt request flags and interrupt enable registers When both of the interrupt request flag and interrupt enable bit for a peripheral function are set to 1 the monitor flag in the corresponding IRRO to IRR2 registers is set to 1 interrupt requested When either or both of the interrupt request flag and interrupt enable bit for a peripheral function are set to 1 the monitor flag in the corresponding IRRO to IRR2 registers is set to 0 no interrupt requested Relation between Registers IRRO to IRR2 and Registers Associated with Peripheral Function Interrupts Peripheral Function Interrupt Request Flag Peripheral Function Interrupt Enable Corresponding Interrupt Monitor Flag Timer RJ2 Register Bit TRJIF Register TRJIR Bit TRJIE Register Bit Timer RB2 TRBIF TRBIR TRBIE Timer RC 1 IMFA IMFB IMFC IMFD OVF TRCIER IMIEA IMIEB IMIEC IMIED OVIE Serial interface UARTO UOIR UOTIF UORIF UOIR UOTIE UORIE A D converter ADICSR ADF ADICSR ADIE Flash memory 1 FST RDYSTI
491. th the count source When the TWRC bit is 1 write to reload register only transfer to the 16 bit counter is performed in synchronization with 16 bit counter underflows Figures 14 12 and 14 13 show Examples of Counter Operation in 16 Bit Timer During programmable wait one shot generation mode when the TCSTF bit in the TRBCR register is 1 count is in progress and the TOSSTF bit in the TRBOCR register is 0 one shot is stopped the reload register and counter can be written because the setting of the TWRC bit in the TRBMR register is invalid RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 220 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 e When the TWRC bit in TRBMR register is 0 write to reload register and counter Write 01h to TRBPRE register and 25h to TRBPR register Count source After the value is written it is written to the reload register by tHe third count source TRBPRE Previous value New value 01h reload register Prescaler Prescaler underflow i After the value is written it is written to the reload register atthe first uhderflow TRBPR 8 Previous value New value 25h reload register Reloaded at the second underflow When the TWRC bit in TRBMR register is 1 write to reload register only Write 01h to TRBPRE register and 25h to TRBPR register Count source After the value is written it is written to the reload register by the third count source TRBPRE U d Previous val
492. the user ROM area will be erased if bits ROMCP1 to ROMCR in the OFS register are any value other than 01b ROM code protect disabled If the stored ID codes are any value other than ALeRASE see Table 19 3 ID Code Reserved Words and when bits ROMCP1 to ROMCR in the OFS register are 01b ROM code protect enabled a forced erase is not performed and the ID codes are examined with the ID code check function Table 19 4 lists the Conditions and Operations of Forced Erase Function Also when the stored ID codes are set to ALeRASE in ASCII if the sent ID codes are ALeRASE the data in the user ROM area will be erased If the sent ID codes are any value other than ALeRASE the ID codes do not match and no command is accepted thus the user ROM area remains protected Table 19 4 Conditions and Operations of Forced Erase Function Condition ID Code from Serial Programmer ID Code in ID Code Bits ROMCP1 to ROMCR Operation or On Chip Debugging Emulator Storage Address in OFS Register ALeRASE ALeRASE Erasure of the whole user Other than Other than 01b ROM area forced erase ALeRASE 1 ROM code protect disabled function 01b ID code examination ROM code protect enabled ID code check function Other than ALERASE ALeRASE ID code examination ID code check function No ID code match Other than ID code examination ALeRASE 1 ID code check function Note 1 See 19 3 2 2 Stan
493. the FST register is changed from 0 busy to 1 ready and the program erase command completes e When the FST7 bit in the FST register is changed from 0 busy to 1 ready and program suspend erase suspend is entered e When a command sequence error occurs e When the FMRO1 bit in the FMRO register is set to 0 CPU rewrite mode disabled e When the FMSTP bit in the FMRO register is set to 1 flash memory is stopped e When the CMDRST bit in the FMRO register is set to 1 erase write sequence reset Figure 19 7 shows the Timing for FMR13 Bit Operation Erase operation starts Erase operation completes 1 1 FST7 i 1 Set to 0 on rising edge of FST7 bit FMR13 Set to 1 by a program Lock bit is enabled FST7 Bit in FST register FMR13 Bit in FMR1 register Figure 19 7 Timing for FMR13 Bit Operation RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 343 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 6 Software Commands The software commands are described below Commands must be read or written and data in 8 bit units Do not input any command other than those listed in the table below Table 19 8 Software Commands First Command Second Command 1 Mode Address Mode Address Data Command Read array Clear status register Program Block erase Lock bit program Read lock bit status Block blank check WA Write address WD Write data BA Any address in the block BT Start address in the
494. the Handling of Unused Pins Figure 12 5 shows the Handling of Unused Pins Table 12 25 Handling of Unused Pins Ports P1 P3_3 to P3_5 P Set each of these pins to input mode and either connect the pin to VSS through P4_2 P4 5to4 7 a resistor pull down or connect it to VCC through a resistor pull up 2 e Set each of these pins to output mode and leave it open 2 3 RESET PA_0 1 Connect to VCC through a pull up resistor 2 Notes 1 When the power on reset is used 2 Use lines that are as short as possible 2 cm or shorter to handle unused pins in the vicinity of the MCU 3 When these ports are set to output mode and left open keep the following in mind They remain in input mode until they are switched to output mode by a program The voltage level of these pins may be unstable and the power current may increase while the ports remain in input mode The content of the direction registers may change due to noise or program runaway caused by noise The program should periodically reconfigure the content for enhanced reliability Ports P1 Input mode P3_3 to P3_5 S BS 7 P4_2 P4_5 to P4_7 Input mode Output mode RESET PA_0 Note 1 When the power on reset function is used Figure 12 5 Handling of Unused Pins RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 167 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 10 I O Port Configuration Figures 12 6 to 1
495. the IOA2 bit in the TRCIORO register and in the IOD2 bit and the IOB2 bit in the TRCIORO register respectively 5 When the BUFEB bit in the TRCMR register is 1 TRCGRD register is used as a buffer register for TRCGRB register the value of the TRCGRD register is transferred to the TRCGRB register at compare match B 6 When the IOB2 bit in the TRCIORO register is 0 output compare function if compare matches B and D occur simultaneously the output from the TRCIOB pin at compare match D takes precedence 7 When the BUFEB bit is 1 TRCGRD register is used as a buffer register for TRCGRB register the value of the TRCGRB register is transferred to the TRCGRD register at input capture B When the input capture edge of the TRCIOD pin selected by bits IODO to IOD1 is input the MED bit in the TRCSR register is set to 1 However the count value is not transferred to the TRCGRD register 8 When IOC2 1 do not set the IOC3 bit to 0 When IOD2 1 do not set the IOD3 bit to 0 The setting of the TRCIOR1 register is invalid in PWM and PWM2 modes 15 2 9 Timer RC Control Register 2 TRCCR2 Address 000F8h Bit After Reset b 0 Bit Name TRCIOB PWM mode output level control bit 1 TRCIOC PWM mode output level control bit 1 TRCIOD PWM mode output level control bit 1 0 Output level is 1 Output level is 7 b6 b5 b4 b3 b2 b1 bO symbol TCEGT TOEGO STP o Pon Poe POLE 0 0 1 1 0 0 0 Function
496. the TCSTF bit is 1 the count is started after the count source is sampled three times When the count value in the timer RB secondary underflows and then it is reloaded the count is stopped The count is also stopped with any of the following settings e When 1 one shot count is stopped is written to the TOSSP bit in the TRBOCR register the count is stopped after the count source is sampled three times e When 0 count is stopped is written to the TSTART bit in the TRBCR register the count is stopped after the count source is sampled three times e When count is forcibly stopped is written to the TSTOP bit in the TRBCR register the count is stopped The actual count state must be monitored with the TCSTF bit in the TRBCR register An interrupt request is generated when timer RB2 underflows during the secondary period When registers TRBPRE and TRBPR are read each count value is read When registers TRBPRE TRBPR and TRBSC are written while the count is stopped values are written to both the reload register and counter respectively When these registers are written during the count operation values are written to the reload register and then transferred to the counter at the next reload operation For the setting of trigger by the INTO input see 14 7 INTO Input Trigger Selection Figure 14 7 shows an Example of 8 Bit Timer with 8 Bit Prescaler Operation in Programmable Wait One Shot Generation Mode Figure 14 8 shows an Example o
497. the buffer register Set the TOB bit in the TRCCR1 register to 0 output value 0 or 1 output value 1 to set the initial level of the output level to 0 or 1 Next set the CCLR bit in the TRCCR1 register to 1 TRCCNT counter is cleared by input capture compare match A to clear the TRCCNT register by compare match A Figure 15 14 shows an Operation Example in PWM2 Mode When TRCTRG Input is Enabled Figure 15 15 shows an Operation Example in PWM2 Mode When TRCTRG Input is Disabled These examples apply when the PWM2 bit in the TRCMR register is set to 0 PWM2 mode and a waveform is output from the TRCIOB pin In PWM2 mode when the TOB bit in the TRCCR1 register is 0 output value 0 the TRCTRG input edge is disabled while a high level is output from the TRCIOB pin Likewise when the TOB bit is 1 output value 1 the TRCTRG input edge is disabled while a low level is output from the TRCIOB pin In addition transfer from registers TRCGRD to TRCGRB is performed when a compare match with the TRCGRA register or TRCTRG input occurs However if the TRCTRG input is disabled depending on the level of the TRCIOB pin transfer from registers TRCGRD to TRCGRB is not performed TRCCNT register value FFFFh TRCGRA register TRCGRB register TRCGRC register 0000h TRCIOA TRCTRG TRCIOB output change when TOB 0 TRCIOB output change when TOB 1 TRCGRD register el TRCGRB register TOB Bit in TRCCR1 register TRCTRG input under the f
498. the flash memory in byte units When 40h is written as the first command and data is written to the write address with the second command auto programming a data program and verify operation starts The address value for the first command must be the same address as the write address specified with the second command The FST7 bit in the FST register can be used to confirm whether auto programming has completed The FST7 bit is set to 0 during auto programming and is set to 1 when auto programming completes After auto programming has completed the auto program result can be confirmed by the FST4 bit in the FST register see 19 6 7 Full Status Check Do not write additions to the already programmed addresses For each block in the program ROM the program command can be disabled using the lock bit When the FMR16 bit in the FMRI register is 1 rewrite disabled the program command for block A of data flash is not accepted When the FMR17 bit is 1 rewrite disabled the program command for block B is not accepted Figure 19 8 shows the Program Flowchart Flash Ready Status Interrupt Disabled and Suspend Disabled Figure 19 9 shows the Program Flowchart in EWO Mode Flash Ready Status Interrupt Disabled and Suspend Enabled Figure 19 10 shows the Program Flowchart in EWO Mode Flash Ready Status Interrupt Enabled and Suspend Enabled Figure 19 11 shows the Program Flowchart in EW1 Mode Flash Ready Status Interrupt Disabled and Suspend Enable
499. the peripheral function output or output port function is selected The corresponding pins are set to N channel open drain output when the POD3_j bit j 3 to 5 or 7 is set to 1 open drain and CMOS output when the bit is set to 0 not open drain 12 4 6 Port 3 Function Mapping Register 0 PML3 Address 000CCh Bit b7 b6 b5 b4 b3 b2 b1 bO Symbol ee e After Reset 0 0 0 0 0 0 0 0 Bit Name Function Nothing is assigned The write value must be 0 The read value is 0 P33SELO Port P3_3 function select bits 90 1 0 port or IVCMP3 input P33SEL1 reck CH 01 TRCCLK 10 INT3 1 1 Do not set The PML3 register is used to select the P3_3 pin function RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 154 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 4 7 Port 3 Function Mapping Register 1 PMH3 Address 000CDh Bit b After Reset P34SELO 0 Bit Name Port P3_4 function select bits P34SEL1 7 b6 b5 b4 b3 b2 b1 bO Symbol P37SEL1 P37SELO Laks P35SEL1 P85SELO P34SEL1 P34SELO 0 0 0 0 0 0 0 Function b1 b 0 0 I O port or IVREF3 input 0 1 TRCIOC 1 0 INT2 1 1 Do not set P35SELO Port P3_5 function select bits P35SEL1 b3 b2 0 0 I O port 0 1 TRCIOD 1 0 Kl2 1 1 VCOUT3 Nothing is assigned The write value must be 0 The read value is 0 P37SELO Port P3_7 function select bits
500. tion voltage monitor 1 Internal ROM H Reserved program ROM H Reserved Expanded area FFFFFh Notes 1 Data flash indicates block A 1 Kbyte and block B 1 Kbyte 2 The blank areas are reserved No access is allowed Internal ROM Internal RAM Part Number z Capacity AddressOYYYYh Capacity Address OXXXXh R5F2M110ANSP R5F2M110ANDD R5F2M110ADSP 2 Kbytes OF800h 256 bytes 004FFh R5F2M120ANSP R5F2M120ANDD R5F2M120ADSP R5F2M111ANSP R5F2M111ANDD R5F2M111ADSP 4 Kbytes OFOOOh 384 bytes 0057Fh R5F2M121ANSP R5F2M121ANDD R5F2M121ADSP R5F2M112ANSP R5F2M112ANDD R5F2M112ADSP 8 Kbytes OE000h 512 bytes OO5FFh R5F2M122ANSP R5F2M122ANDD R5F2M122ADSP Figure 3 1 Memory Map RO1UH0050EJ0200 Rev 2 00 ztENESAS Page 14 of 426 May 18 2012 R8C M11A Group R8C M12A Group 3 Address Space 3 2 Special Function Registers SFRs An SFR special function register is a control register for a peripheral function Tables 3 1 to 3 8 list the SFR Information Table 3 9 lists the ID Code Area and Option Function Select Area Table 3 1 Address 00000h SFR Information 1 Register Name After Reset 00001h 00002h 00003h 00004h 00005h 00006h 00007h 00008h 00009h 0000Ah 0000Bh 0000Ch 0000Dh 0000Eh 0000Fh 00010h Processor Mode Register 0 00h 00011h 00012h Module Standby Control Regist
501. to 0 e When 0 is written to this bit after reading it as 1 Condition for setting to 1 e See Table 15 9 Conditions for Setting Each Flag to 1 Note 1 The results of writing this bit are as follows sl the result of reading this bit is 1 writing O to this bit will set it to 0 If the result of reading this bit is 0 writing O to this bit will not change its value If this bit changes from 0 to 1 after the read the bit will remain 1 even if 0 is written e Writing 1 has no effect Table 15 9 Conditions for Setting Each Flag to 1 Timer Mode Output Compare PWM Mode PWM2 Mode Function When the value in the TRCCNT register When the values in registers TRCCNT and TRCGRA match is transferred to the TRCGRA register on the input edge 1 of the TRCIOA pin When the value in the TRCCNT register When the values in registers TRCCNT and TRCGRB match is transferred to the TRCGRB register on the input edge 1 of the TRCIOB pin When the value in the TRCCNT register When the values in registers TRCCNT and TRCGRC match 2 is transferred to the TRCGRC register on the input edge 1 of the TRCIOC pin When the value in the TRCCNT register When the values in registers TRCCNT and TRCGRD match 2 is transferred to the TRCGRD register on the input edge of the TRCIOD pin When the TRCCNT register overflows from FFFFh to 0000h Input Capture Function Notes 1 The edge is selected by bits Oo to
502. to 1 interrupt requested Set the TRBIF bit to 0 no interrupt requested before restarting the count e When the TSTART bit in the TRBCR register is 0 count is stopped wait for at least two cycles of the system clock f after writing the values of registers TRBPRE and TRBPR before reading them RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 228 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 Timer RC Timer RC is a 16 bit timer that provides output compare and input capture functions and can count external events It can be used as a multifunction timer with various applications such as generation of pulse output with an arbitrary duty cycle using the compare match between the timer RC counter and four general registers 15 1 Overview Table 15 1 lists the Timer RC Specifications Table 15 2 lists the Timer RC Functions Figure 15 1 shows the Timer RC Block Diagram Table 15 3 lists Timer RC Pin Configuration Table 15 1 Timer RC Specifications Item Description Count sources counter input clocks Operating Internal clock clock ef f2 f4 f8 or 32 Selected when bits CKS2 to CKSO in the TRCCR1 register are 000b to 100b e fHOCO Selected when bits CKS2 to CKSO in the TRCCR1 register are 110b External clock external event count TRCCLK input Selected when bits CKS2 to CKSO in the TRCCR1 register are 101b Pulse I O pins 4 General registers 4 e Can be set as
503. to 1 write enabled before rewriting the VWOC register RO1UHO050EJ0200 Rev 2 00 RENESAS Page 55 of 426 May 18 2012 R8C M11A Group R8C M12A Group 7 Voltage Detection Circuit 7 2 5 Voltage Monitor 1 Circuit Control Register VW1C Address 0005Dh Bit b7 b6 b5 b4 b3 b2 b1 b Symbol VW1C7 EP Ses ll VW1F1 VW1FO VW1C3 VW1C2 VW1C1 VW1CO After Reset 1 0 0 0 1 0 1 0 Bit Name Function Voltage monitor 1 interrupt enable 0 Voltage monitor 1 interrupt disabled bit 1 Voltage monitor 1 interrupt enabled Voltage monitor 1 digital filter 0 Digital filter enabled mode mode select bit 2 5 digital filter circuit enabled Digital filter disabled mode digital filter circuit disabled Not detected Detected by passing through Vdet1 Voltage change detection flag 3 4 0 i Voltage detection 1 signal monitor 0 VCC lt Vdet1 E flag 3 i i b5 b4 Sampling clock select bits 0 0 Division of fLOCO by 1 no division 0 1 Division of LOCO by 2 1 0 Division of fLOCO by 4 1 1 Division of fLOCO by 8 Reserved Set to 0 Voltage monitor 1 interrupt 0 VCC reaches Vdet1 or above generation condition select bit 6 1 VCC reaches Vdet1 or below VCC gt Vdet1 or voltage detection 1 circuit disabled Notes 1 The VW1CO bit is enabled when the VC1E bit in the VCA2 register is 1 voltage detection 1 circuit enabled When the VC1E bit is 0 voltage detection 1 circu
504. to individual ports RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 144 of 426 May 18 2012 R8C M11A Group R8C M12A Group 12 I O Ports 12 3 3 Pull Up Control Register 1 PUR1 Address 000B5h Bit b7 b6 b5 b4 b3 b2 b1 b Symbol After Reset 0 0 0 0 0 0 0 0 Bit Name Function Port P1_0 pull up control bit 0 No pull up resistor Port P1_1 pull up control bit 1 Pull up resistor Port P1_2 pull up control bit Port P1_3 pull up control bit Port P1_4 pull up control bit Port P1_5 pull up control bit Port P1_6 pull up control bit Port P1_7 pull up control bit The PURI register is used to control the port P1 pull up resistors I O ports are pulled up when the corresponding PD1_j bit j 0 to 7 in the PD1 register is set to 0 input mode functions as an I O port and the PU1_j bit j 0 to 7 in the PURI register is set to 1 The input pins for peripheral functions are pulled up when the corresponding PD1_j bit is set to 0 and the PU1_j bit is set to 1 Do not set the corresponding PU1_j bit to 1 for the output pins for peripheral functions 12 3 4 Drive Capacity Control Register 1 DRR1 Address 000BBh Bit b7 b6 b5 b4 b3 b2 b1 b Sym DRAT_S DRRT_4 DRAT_s DRRTI2 After Reset 0 0 0 0 0 0 0 0 Bit Name Function Reserved Set to 0 Port P1_2 drive capacity control bit 0 Low drive capacity Port P1_3 drive capacity control bit 1 High drive capacity 1 Port P1_4 driv
505. tor mode Stop the high speed on chip oscillator clock FMR27 lt 1 low current consumption read mode enabled 7 Enter low current consumption read mode II FMR27 lt 0 low current consumption read mode disabled Start the high speed on chip oscillator clock Wait until the high speed on chip oscillator clock oscillation stabilizes Enter high speed on chip oscillator mode FMR27 Bit in FMR2 register Notes 1 To set the FMR27 bit to 1 first write 0 and then write 1 immediately Interrupts must be disabled between writing 0 and then writing 1 2 In low current consumption read mode set the FMRO01 bit in the FMRO register to 0 CPU rewrite mode disabled Figure 10 7 Procedure for Using Low Current Consumption Read Mode RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 107 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 6 Notes on Power Control 10 6 1 Program Restrictions When Entering Wait Mode To enter wait mode by setting the WAITM bit to 1 set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before setting the WAITM bit to 1 To enter wait mode with the WAIT instruction set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled before executing the WAIT instruction The 4 bytes of instruction data following the instruction that sets the WAITM bit to 1 wait mode is entered or the WAIT instruction are prefetched from the instruction queue and th
506. tput from the TRJO pin can be toggled even in event counter mode When event counter mode is used see 13 5 Notes on Timer RJ2 3 8 9 Figure 13 5 shows an Operation Example in Event Counter Mode Event counter mode is entered Bits TMOD2 to TMODO in TRJMR register Event is always counted on rising edge Control bit in TRJIOC register TSTART bit in TRJCR register E Event input is completed TRUJIO pin event input d Timer RJ2 counter FFFFh FFFEh FFFDh 0000h FFFFh FFFEh LU sags Counter initial value is set 1 TRUIF bit in TRJIR register Set to 0 by a program Figure 13 5 Operation Example in Event Counter Mode RO1UH0050EJ0200 Rev 2 00 RENESAS Page 189 of 426 May 18 2012 R8C M11A Group R8C M12A Group 13 Timer RJ2 13 4 5 Pulse Width Measurement Mode In this mode the pulse width of an external signal input to the TRJIO pin is measured When the level specified by the TEDGSEL bit in the TRJIOC register is input to the TRJIO pin the decrement is started with the selected count source When the specified level on the TRJIO pin ends the counter is stopped the TEDGF bit in the TRJCR register is set to 1 active edge received and the TRJIF bit in the TRJIR register is set to interrupt requested The measurement of pulse width data is performed by reading the count value while the counter is stopped Also when the counter underflows during measurement the TUNDF bit in the TRJCR
507. tput value 1 a high level is output at a compare match with the TRCGRB register and a low level is output at a compare match with the TRCGRC register Table 15 16 lists the Combinations of Pin Functions and General Registers for PWM2 Mode and General Registers for PWM2 Mode Figure 15 12 shows the Block Diagram in PWM2 Mode Figure 15 13 shows the Timing of Buffer Operations for Registers TRCGRD and TRCGRB in PWM2 Mode The value in the TRCGRD register is transferred to the TRCGRB register and the counter is cleared by a compare match with the TRCGRA register However the counter is cleared only when the CCLR bit in the TRCCRI register is set to 1 TRCCNT counter is cleared by input capture compare match A Also when trigger input is enabled by bits TCEGO to TCEG1 in the TRCCR2 register in PWM2 mode the value in the TRCGRD register is transferred to the TRCGRB register and the counter is cleared by a trigger The timer I O pins that are not used in PWM2 mode can be used as I O ports 15 Timer RC Table 15 16 Combinations of Pin Functions and General Registers for PWM2 Mode Buffer Register Pin Name Compare Match Register Port function TRCTRG input TRCGRB register TRCGRD register TRCGRC register Note Port function 1 1 To use the port function set the corresponding bit in registers PMLi and PMHi i 1 3 or 4 to 0 TRCIOA TRCTRG Q Note Count clearing Input control TRCCNT 3 re
508. ts EA to ED can be set by software When the waveform output manipulation event selected by bits OPSELO to OPSEL1 is input bits EA to ED are set to 1 However bits EA to ED are not automatically set to 0 even if the waveform output manipulation event is cancelled Set these bits to 0 by software 3 Disabled when the corresponding pin is used as input capture input RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 243 of 426 May 18 2012 R8C M11A Group R8C M12A Group 15 Timer RC 15 2 12 Timer RC A D Conversion Trigger Control Register TRCADCR Address 000FBh Bit b 7 b a After Reset 1 ADTRGAE 1 Bit Name TRCGRA A D conversion start trigger enable bit No A D conversion start trigger occurs at compare match A An A D conversion start trigger occurs at compare match A 6 b5 b4 b3 b2 b1 bO RBTRGDEADTRGCE ADTAGEEADTRGAE 1 1 0 0 0 0 ADTRGBE TRCGRB A D conversion start trigger enable bit No A D conversion start trigger occurs at compare match B An A D conversion start trigger occurs at compare match B ADTRGCE TRCGRC A D conversion start trigger enable bit No A D conversion start trigger occurs at compare match C An A D conversion start trigger occurs at compare match C ADTRGDE TRCGRD A D conversion start trigger enable bit No A D conversion start trigger occurs at compare match D An A D conversion start trigger occurs at compare match D Nothi
509. ual Setting Value Set Actual Setting Value Set Actual Setting Source in UOBRG Error in UOBRG Error in UOBRG Error Rate bps Register Rate bps Register Rate bps 1201 92 D 77h 1200 00 1201 92 Register 2400 40h 2403 85 3Bh 2400 00 2403 85 4800 20h 4734 85 1Dh 4800 00 d 4807 69 9600 E 8ih 9615 38 n 77h 9600 00 9615 38 19200 40h 19230 77 3Bh 19200 00 19230 77 28800 42 2Ah 29069 77 27h 28800 00 29411 76 38400 20h 38400 00 d 38461 54 57600 57600 00 i 55555 56 39 37878 79 Dh 56818 18 9 13h 15h 115200 0 OAh 64 40h 9 3Bh 32 20h 9 OD 81h 14400 86 56h 14367 82 0 79 4Fh 14400 00 0 14285 71 64 40h 59 3Bh 32 20h 9 1Dh 21 15h 113636 36 9 09h 115200 00 F Note 1 For the high speed on chip oscillator write the adjustment values in registers FR18SO and FR18S1 to registers FRV1 and FRV2 respectively This applies when the high speed on chip oscillator is selected as the system clock and the PHISEL register is set to 00h no division For details on the accuracy of the high speed on chip oscillator see 20 Electrical Characteristics RO1UHO050EJ0200 Rev 2 00 RENESAS Page 295 of 426 May 18 2012 R8C M11A Group R8C M12A Group 16 Serial Interface UARTO 16 3 2 3 RXDO Digital Filter When the DFE bit in the UOCO regis
510. ue New value 01h reload register 1 U Reloaded at underflow U Prescaler Prescaler underflow After the value is written itis writtento the reload register at the first underflow TRBPR Previous value New value 25h reload register Reloaded at the 1 counter underflow Counter 25h The above diagram applies under the following condition e When bits TSTART and TCSTF in the TRBCR register are both 1 count in progress Figure 14 10 Example of Prescaler and Counter Operation in 8 Bit Timer with 8 Bit Prescaler Timer Mode or Programmable One Shot Generation Mode RO1UHO050EJ0200 Rev 2 00 RENESAS Page 221 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 When the TWRC bit in TRBMR register is 0 write to reload register and counter Write 01h to TRBPRE register 25h to TRBPR register and 1Ah to TRBSC register t aaa Neel L294 eI LEI ET EK LA Me After ithe value is written it is written to the reload register by th third count source TRBPRE d Previous value New value 01h reload register Li Reloaded by the next count source Li d Prescaler Prescaler underflow After the value is written to the TRBPR register it is written td the reload register at the first underflow TREES Previous value New value 25h reload register After the value is written to the TRBPR register it is written td the reload register at the first underflow TRBSC
511. uffer Register UORB 0 0 eee ceeecsseeesceesreececenceceseecsseeceeecereesaeceseeesseeeneeceeeeenaeeeneens 284 16 2 7 UARTO Interrupt Flag and Enable Register UOIR eee cece ceceeeeeeeceeeeeecaeesaecaecnaecaeeaeeesnseeeensees 285 16 3 Operation ugekennegt EEEE 286 163 1 Clock Synchronous Serial VO Mode merere e a o pia ea a Ea e ET a 286 16 3 2 Clock Asynchronous Serial I O UART Mode A 291 16 4 UARTO Interrupted sca seni cwedcacterct nach ecsegscachbouscb sees Ab E ase aia EATE ees 297 16 5 Notes on Serial Interface OU ARTO e n a a a aaa ae Aa E aao aae SEESE ai 298 T7 AD G nverter orreri dee 299 17 1 OEO E R A as ds 299 17 2 LEE 301 17 2 1 A D Register i ADI S0 or I E 302 17 2 2 A D Mode Register ADMOD ege ule led a E EE E E S EEEE EEEa 303 1723 A D Input Select Resister APNS E e e e E E E anion an NRS ERES RR 304 17 2 4 A D Control Register 0 ADCONO vesiin e a ee E Se E EO E EE N eS eE EE EE a reeet 305 17 2 5 A D Interrupt Control Status Register ADICSR ssssseseessessseeseessseeresreresreresresrerrnreenseerenrnsenesserreseneesr 306 17 3 Operation EE 307 17 3 1 Items Common to Multiple Modes AA 307 17 322 One Shot EE 309 T733 Repeat Mode aiecic Sigtk Se ae i eed Saas ce E 310 173 4 Single Sweep Node eege tege uerge A eege Eege Beedegen S 311 17 3 5 Repeat Sweep Mode s ncs siete iene EEN EE HS Se He eS 312 17 4 A D Converter Interrupt 2 Ee ENEE BEER EES 313 17 5 Notes on A D Converter ca
512. uired from when the FMR21 bit is set to 1 until suspend is acknowledged The interrupt to enter the suspend state must be enabled beforehand Figure 19 9 Program Flowchart in EWO Mode Flash Ready Status Interrupt Disabled and Suspend Enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 346 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory Maskable interrupt RDYSTIE 1 i FMR20 1 Write the command code 40h 1 interrupt enabled Write data to the write address Program completed Flash ready status interrupt 1 2 Access the flash memory Full status check FMR21 0 RDYSTI 0 Flag in CPU register RDYSTI FST3 Bits in FST register RDYSTIE Bit in FMRO register REIT FMR20 FMR21 Bits in FMR2 register Notes 1 The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other than the programming target area 2 td SR SUS is required from when the FMR21 bit is set to 1 until suspend is acknowledged The interrupt to enter the suspend state must be enabled beforehand 3 A flash ready status interrupt is generated when auto programming is suspended Figure 19 10 Program Flowchart in EWO Mode Flash Ready Status Interrupt Enabled and Suspend Enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 347 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory When the FMR272
513. ulation for the timer RC pin is stopped and the output is restarted The timing is automatically synchronized so that less than one cycle of waveform is not output after the output is restarted Figures 15 23 to 15 26 show Examples of Waveform Output Manipulation Operation e When the timer RC pin is pulled down the OPE bit in the TRCOPR register is 1 waveform output manipulation enabled bits OPOL1 to OPOLO are 00b when timer RC pin is pulled down timer RC output level is fixed to high impedance during waveform output manipulation period and the RESTATS bit is 0 output is restarted by software Waveform output Waveform output manipulation manipulation event is input event is cancelled Waveform output P manipulation event ch f 4 SE 1 Waveform output manipulation is e i stopped by software and output EB bit in is restarted TRCOER register U Corresponding output EZE I zadi dE INT 1 comparator B1 output with waveform output manipulation disabled pe aa Timer RC output TRCIOB_XP internal signal Output control signal TRCOBE_XN internal signal TRCIOB output During waveform output manipulation a period timer RC output is fixed to high Synchronized so that less than impedance and at low when timer RC one cycle of waveform is not pin is pulled down output Figure 15 23 Example of Waveform Output Manipulation Operation 1 RO1UH0050EJ0200 Rev 2 00 RENESAS Pa
514. unt value in SEEEh aeren Y 3FFDh gt 1000h OFFFh OFFEh OFFDh OFFCh OFFBh OFFAh watchdog timer G WDTIF bit in WDTIR register Set to 0 by a program WDTIE bit in WDTIR register Set to 1 by a program The above diagram applies under the following condition e Bits WOTUFS1 to WDTUFSO in OFS2 register 11b underflow period 3FFFh and bits WOTRCS1 to WDTRCSO 00b refresh acceptance period 25 Figure 8 3 Timing of Periodic Timer Function RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 70 of 426 May 18 2012 R8C M11A Group R8C M12A Group 8 Watchdog Timer 8 4 Notes on Watchdog Timer e Do not switch the count sources during watchdog timer operation e There is a delay of two cycles of the count source from a write to the WDTR register until the initialization of the watchdog timer e Allow at least three cycles of the count source between the previous and the next initialization of the watchdog timer RO1UHO050EJ0200 Rev 2 00 stENESAS Page 71 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit 9 Clock Generation Circuit 9 1 Overview The following three circuits are included in the clock generation circuit e XIN clock oscillation circuit e High speed on chip oscillator e Low speed on chip oscillator Table 9 1 lists the Clock Generation Circuit Specifications Figure 9 1 shows the Clock Generation Circuit Block Diagram Figure 9 2 shows the Supply of Peripheral
515. unted on first rising edge Count source Counter 0503h initial value 0502h 0501h 0500h 04FFh O4FEh 04FDh Figure 21 4 TSTART Setting Timing in Event Counter Mode 1 TRUJIO pin TEDGSEL bit in TRJIOC register TSTART bit in TRJCR register Count source Counter 0503h initial value 0502h 0501h 0500h 04FFh 04FEh 04FDh 04FCh Figure 21 5 TSTART Setting Timing in Event Counter Mode 2 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 397 of 426 May 18 2012 R8C M11A Group R8C M12A Group 21 Usage Notes 9 When the TEDGSEL bit in the TRJIOC register is set to 1 count on falling edge and the external signal TRJIO is counted in event counter mode the signal may not be counted correctly depending on the state of the TSTART bit in the TRJCR register see Figure 21 6 Even if the TRJIO pin is set to low after the TSTART bit is set to 1 count is started the signal is not counted on the falling edge Thus the number of counted events is obtained as follows Number of counted events initial value in the counter value in the counter on completion of the valid event 1 1 To avoid this set the TSTART bit to 1 count is started and input a valid event after setting the TRJIO pin to low see Figure 21 7 TRUJIO pin TEDGSEL bit in d TRJIOC register H H TSTART bit in TRJCR register Not counted on first falling edge Count source D Counter 0503h initial value 0502h 0501h 0500h 04FFhIO4FEh
516. unter select bit 1 0 8 bit timer with 8 bit prescaler 1 16 bit timer TWRC Timer RB write control bit 2 0 Write to reload register and counter 1 Write to reload register only TCKO Timer RB count source select bits 1 bobo be TCK1 SE 001 f8 TCK2 0 1 0 Timer RJ2 underflow 011 100 101 110 111 TCKCUT Timer RB count source cutoff bit 1 0 Count source is supplied 1 Count source is cut off Notes 1 Only change these bits when bits TSTART and TCSTF in the TRBCR register are 0 count is stopped 2 For details on writing to the register and counter using the TWRC bit see 14 5 2 Prescaler and Counter Using TWRC Bit RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 202 of 426 May 18 2012 R8C M11A Group R8C M12A Group 14 Timer RB2 14 3 5 Timer RB Prescaler Register TRBPRE Address 000E4h Bit b7 b6 b5 b4 b3 b2 b1 b0 M n er Reset Function Initial Value Setting Range b7 to bO Timer mode An internal count source or the timer 00h to FFh Programmable waveform RJ2 underflow is counted 00h to EEN generation mode Programmable one shot 00h to FFh generation mode Programmable wait one shot 00h to FFh generation mode In the 8 bit timer with 8 bit prescaler the TRBPRE register is used to set the period of the prescaler Each time the prescaler decrements and underflows the value in the TRBPRE register is reloaded When read the va
517. use an external clock input it to the XIN pin P4_7 can be used as an I O port at this time INT interrupt input INTO to INT3 INT interrupt input Key input interrupt KIO to KI3 Key input interrupt input I O ports P1 Oto P1_7 P3_0 to P3_5 b i P4_2 P4 5 to P4 7 PA 0 CMOS I O ports Each port has an I O select direction register enabling switching input and output for each port For input ports other than PA_O the presence or absence of a pull up resistor can be selected by a program P1_2 to P1_5 P3_3 to P3_5 and P3_7 can be used as LED drive ports Timer RJ2 TRJIO Timer RJ2 I O TRJO Timer RJ2 output Timer RB2 TRBO Timer RB2 output Timer RC TRCCLK External clock input TRCTRG External trigger input TRCIOA TRCIOB TRCIOC TRCIOD Timer RC I O Serial interface CLKO Transfer clock I O RXDO Serial data input TXDO Serial data output A D converter ANO to AN4 AN7 Analog input for the A D converter ADTRG External trigger input for the A D converter Comparator B Note IVCMP1 IVCMP3 Analog voltage input for comparator B IVREF1 IVREF3 Reference voltage input for comparator B VCOUT1 VCOUT3 Comparison result output for comparator B 1 Contact the oscillator manufacturer for oscillation characteristics RO1UHOO50EJ0200 Rev 2 00 May 18 2012 ztENE
518. utput does not match three successive times it is recognized as noise and not transmitted CKSO to CKS2 Bits in TRCCR1 register IOAO to IOA1 IOBO to IOB1 Bits in TRCIORO register IOC to IOC1 IODO to IOD1 Bits in TRCIOR1 register DFA to DFD DFTRG DFCKO to DECKT Bits in TRCDF register TCEGO to TCEG1 Bits in TRCCR2 register Figure 15 19 Digital Filter Circuit Block Diagram ztENESAS DFA to DFD or DFTRG Match detection circuit selection circuit Matched three times so recognized as a signal change Signal transmission is delayed by a maximum of five sampling clocks IOAO to IOA1 IOBO to IOB1 IOCO to IOC1 IODO to IOD1 or TCEGO to TCEG1 Edge detection circuit Page 262 of 426 R8C M11A Group R8C M12A Group 15 Timer RC 15 4 2 A D Conversion Start Trigger By setting the TRCADCR register an A D conversion start trigger can be generated at compare matches A to D Figure 15 20 shows a Setting Example of A D Conversion Start Trigger by Compare Matches B and C TRCCNT register value FFFFh TRCGRA register TRCGRB register TRCGRC register 0000h i U ADTRG A D conversion A D conversion start trigger start trigger Figure 15 20 Setting Example of A D Conversion Start Trigger by Compare Matches B and C An A D conversion start trigger is not generated from the buffer register during buffer operation The TRCGRC register cannot operate as a buffer register for the TRCGRA register
519. version clock f1 f2 f4 f8 or fAD Conversion time 2 2 us A D conversion clock 20 MHz A D operating modes One shot mode A D conversion is performed on the specified single channel for a single round e Repeat mode A D conversion is performed on the specified single channel repeatedly Single sweep mode A D conversion is performed on the specified two channels for a single round e Repeat sweep mode A D conversion is performed on the specified two channels repeatedly A D conversion data register x 2 16 bit data register corresponding to each channel group where the A D conversion result is stored valid data length 10 bits A D conversion start conditions e Software trigger e Conversion start trigger from timer RC e External trigger Interrupt source An A D conversion interrupt is generated when A D conversion completes Others RO1UHO050EJ0200 Rev 2 00 May 18 2012 The A D converter is set to standby by the MSTAD bit in the MSTCR register ztENESAS Page 299 of 426 R8C M11A Group R8C M12A Group Analog Circuit Multiplexer Successive approximation register Sample and hold circuit 17 A D Converter Data bus ADO register Figure 17 1 A D Converter Block Diagram AD1 register Table 17 2 lists the A D Converter Pin Configuration Pins AVCC and AVSS are used for the power supply to the analog block in the A D converter The six ana
520. watchdog circuit Oscillation low division timer stop speed circuit detection selection division Circuit circuit by 1 to 256 CPU memory Low speed Low speed clock on chip SCKSEL 0 oscillator Prescaler to LOCODIS 128 Peripheral functions 1 Clock generation circuit Controlled discharge when XINBAKE 0 Pulse generation j circuit for clock Charge Oscillation stop Oscillation stop detection XIN clock edge detection discharge detection interrupt watchdog timer and charge circuit generation circuit voltage monitor 1 interrupt discharge control Watchdog timer interrupt Voltage monitor 1 interrupt SCKSEL bit switch signal HOCOE LOCODIS Bits in OCOCR register PHISSELO to PHISSEL2 HSCKSEL Bits in SCKCR register PHISELO to PHISEL7 Bits in PHISEL register PSCSTP SCKSEL Bits in CKSTPR register XINBAKE CKSWIE Bits in BACKCR register Note 1 See Figure 9 2 Supply of Peripheral Function Clocks Figure 9 1 Clock Generation Circuit Block Diagram RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 73 of 426 May 18 2012 R8C M11A Group R8C M12A Group 9 Clock Generation Circuit Watchdog timer i i Figure 9 2 Supply of Peripheral Function Clocks Table 9 2 Clock Generation Circuit Pin Configuration Function XIN l XIN clock input external clock input XOUT O XIN clock output RO1UHO050EJ0200 Rev 2 00 stENESAS Page 74 of 426 May 18 2012 R8C M11A Group
521. watchdog timer interrupts the interrupt source needs to be determined See 11 8 How to Determine Interrupt Sources for how to determine interrupt sources e When the XIN clock starts oscillating after oscillation is stopped switch the XIN clock to the clock source for the CPU clock and the peripheral functions by a program Figure 9 6 shows the Flowchart for Switching from Low Speed On Chip Oscillator to XIN Clock e The oscillation stop detection function can stop the XIN clock by an external cause In that case set bits CKSWIE to XINBAKE in the BAKCR register to 00b interrupt disabled oscillation stop detection function disabled to stop or oscillate the XIN clock by a program to select stop mode or change bits CKPTO to CKPT1 in the EXCKCR register e This function cannot be used when the XIN clock frequency is below 2 MHz In this case set bits CKSWIE to XINBAKE in the BAKCR register to 00b interrupt disabled oscillation stop detection function disabled e After the oscillation stop is detected the low speed on chip oscillator is used as the clock source for the CPU clock and the peripheral functions To reduce power consumption the low speed on chip oscillator can be set to stop while the oscillation stop detection function is enabled In that case allow the low speed on chip oscillator to automatically oscillate when the stop of the XIN clock is detected then switch the system clock after the wait time for oscillation stabilization
522. write registers PMLj and PMHj j 1 3 or 4 Set the INTIEN bit i 0 to 2 in the INTEN register to 0 Set bits INTIFO to INTE i 0 to 2 in INTFO register Set the INTIEN bit i 0 to 2 in the INTEN register to 1 Wait for a certain period Set the registers associated with the peripheral functions Note 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INT2 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT2 are used Figure 11 15 Register Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions Timer RJ2 Timer RB2 and Timer RC RO1UHO050EJ0200 Rev 2 00 RENESAS Page 138 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 9 7 Changing Interrupt Priority Levels and Flag Registers a The interrupt priority level and the flag register must be changed only while no interrupt requests are generated If an interrupt may be generated using the I flag to disable the interrupt before changing the interrupt priority level and the flag register b When using the I flag to disable an interrupt set the I flag as shown in the sample programs below Examples 1 to 3 show how to prevent the I flag from being set to 1 interrupts enabled before the interrupt priority level and the flag register are changed due to effects of the internal bus
523. written to the LPE bit Sequential writes in the opposite order are also not allowed When the LPE bit is 1 do not set the STPM bit in the CKSTPR register to 1 all clocks are stopped stop mode For entering wait mode see 10 3 Wait Mode Figure 10 5 Procedure for Reducing Internal Power Consumption by Using LPE Bit RO1UHO050EJ0200 Rev 2 00 RENESAS Page 105 of 426 May 18 2012 R8C M11A Group R8C M12A Group 10 Power Control 10 5 10 Stopping Flash Memory In low speed on chip oscillator mode the flash memory can be stopped using the FMSTP bit in the FMRO register to further reduce the power consumption When the FMSTP bit is set to 1 flash memory is stopped the flash memory cannot be accessed The FMSTP bit must be written by a program that has been transferred to the RAM When the MCU enters stop mode or wait mode with CPU rewrite mode disabled the power supply for the flash memory is automatically turned off It is turned on again when MCU exits stop mode or wait mode This eliminates the need to set the FMRO register Figure 10 6 shows the Procedure for Reducing Power Consumption Using FMSTP Bit Transfer the FMSTP bit setting program Write 0 and then 1 CPU rewrite mode enabled to the RAM to the FMRO1 bit Jump to the FMSTP bit setting program Write 1 flash memory is stopped The subsequent processing is executed to the FMSTP bit by the program in the RAM Enter low speed on chip oscillator mode Stop t
524. ws the Register Setting Procedure When INTi Input Filter i 0 to 3 is Used When all maskable interrupts can be disabled use the flag When all maskable interrupts cannot be disabled use the Interrupt disabled corresponding bits ILVLjO to ILVLj1 or bits ILVLj4 to ILVLj5 j 6 A C D or E for the interrupt whose source to be changed Rewrite registers PMLk PMHk k 1 3 or 4 and ISCRO if Set the INTIEN bit i 0 to 3 in the INTEN register to 0 Yi Set the bits INTIFO to INTiF1 i 0 to 3 in INTFO register Set the INTIEN bit i 0 to 3 in the INTEN register to 1 Wait for a certain period Set the interrupt request flag to 0 Yi Interrupt enabled lt The interrupt is enabled Note 1 A period of two to three cycles x the system clock f when the digital filter is disabled and INTO to INT3 are used It is five to six cycles x the sampling clock when the digital filter is enabled and INTO to INT3 are used Figure 11 14 Register Setting Procedure When INTi Input Filter i 0 to 3 is Used RO1UHO050EJ0200 Rev 2 00 ztENESAS Page 137 of 426 May 18 2012 R8C M11A Group R8C M12A Group 11 Interrupts 11 9 6 Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions Figure 11 15 shows the Register Setting Procedure When INTi Input Filter i 0 to 2 is Used for Peripheral Functions Timer RJ2 Timer RB2 and Timer RC Re
525. xamples Connect oscillation circuit MF Ten Nine Cable M3A 0652CBL Note 1 It is not necessary to connect an oscillation circuit when operating with the on chip oscillator clock Appendix Figure 2 1 MF Ten Nine Cable M3A 0652CBL Connection Example 1 RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 417 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 2 Connection Examples between Serial Programmer and On Chip Debugging Emulator Connect oscillation circuit R8C M12A Group MF Ten Nine Cable M3A 0652CBL Note 1 When operating on the on chip oscillator clock it is not necessary to connect an oscillation circuit Appendix Figure 2 2 MF Ten Nine Cable M3A 0652CBL Connection Example 2 RO1UH0050EJ0200 Rev 2 00 zeENESAS Page 418 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 2 Connection Examples between Serial Programmer and On Chip Debugging Emulator Open collector buffer 4 7 KQ or more gt Connect oscillation ESD circuit 1 4 7kQ 10 13 RESET MODED E8a emulator ROE00008AKCE00 Note 1 When operating on the on chip oscillator clock it is not necessary to connect an oscillation circuit Appendix Figure 2 3 E8a Emulator ROE00008AKCE00 Connection Example 1 R01UH0050EJ0200 Rev 2 00 ztENESAS Page 419 of 426 May 18 2012 R8C M11A Group R8C M12A Group Appendix 2 Connection Examples between Serial Programmer and On Chip
526. xpressed as an integer If the clock source for the CPU clock fs is the low speed on chip oscillator it is taken to be the minimum fLOCO value 60 kHz Ex Value set in the FREFR register when the CPU clock fs is set to 12 5 kHz 12 5 x 103 103 12 001100b Nothing is assigned The write value must be 0 The read value is 0 The FREFR register is used to control the interval between refresh operations when the FMR27 bit in the FMR2 register is 1 low current consumption read mode enabled First set the FMR27 bit in the FMR2 register to 0 low current consumption read mode disabled to set the value in the register After that set the FMR27 bit to 1 low current consumption read mode enabled RO1UHO050Ev0200 Rev 2 00 ztENESAS Page 338 of 426 May 18 2012 R8C M11A Group R8C M12A Group 19 Flash Memory 19 6 CPU Rewrite Mode Each mode is described as below 19 6 1 EWO Mode When the FMRO1 bit in the FMRO register is set to 1 CPU rewrite mode enabled CPU rewrite mode is entered and software commands are accepted Since the FMRO2 bit in the FMRO register is 0 at this time EW mode is selected Software commands are used to control programming erase The FST register can be used to confirm the status when programming erase is completed To enter suspend during auto erase or auto programming set the FMR20 bit to 1 suspend enabled and the FMR21 bit to 1 suspend request N
527. y For details on the watchdog timer see 8 Watchdog Timer 6 3 6 Software Reset When the SRST bit in the PMO register is 1 reset is generated the CPU SFRs and I O ports are initialized Next the program located at the address indicated by the reset vector is executed The low speed on chip oscillator clock no division is automatically selected as the CPU clock after the reset is cleared For the states of the SFRs after a software reset see 3 2 Special Function Registers SFRs The internal RAM is not initialized 6 3 7 Cold Start Up Warm Start Up Determination Function The CWR bit in the RSTFR register is used to determine whether a cold start up reset process was initiated at power on or whether a warm start up reset process was initiated during operation The CWR bit is set to 0 cold start up at power on and also set to 0 by a voltage monitor 0 reset If 1 is written to the CWR bit by a program it is set to 1 This bit remains unchanged after a hardware reset software reset or watchdog timer reset The cold start up warm stat up determination function uses the voltage monitor 0 reset For the bit settings associated with the voltage monitor 0 reset see Table 7 3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset Figure 6 6 shows an Example of Cold Start Up Warm Start Up Function Operation Set to 1 by a program H CWR bit in RSTFR register I I I I Voltage monitor 0 reset The above appl
528. ztENESAS Page 18 of 426 May 18 2012 R8C M11A Group R8C M12A Group 3 Address Space Table 3 5 SFR Information 5 1 S Register Name After Reset 00101h 00102h 00103h 00104h 00105h 00106h 00107h 00108h 00109h 0010Ah 0010Bh 0010Ch 0010Dh 0010Eh 0010Fh 00110h 00111h 00112h 00113h 00114h 00115h 00116h 00117h 00118h 00119h 0011Ah 0011Bh 0011Ch 0011Dh 0011Eh 0011Fh 00120h 00121h 00122h 00123h 00124h 00125h 00126h 00127h 00128h 00129h 0012Ah 0012Bh 0012Ch 0012Dh 0012Eh 0012Fh 00130h 00131h 00132h 00133h 00134h 00135h 00136h 00137h 00138h 00139h 0013Ah 0013Bh 0013Ch 0013Dh 0013Eh 0013Fh Note 1 The blank areas are reserved No access is allowed R01UH0050EJ0200 Rev 2 00 CENESAS P i ee ate age 19 of 426 R8C M11A Group R8C M12A Group 3 Address Space Table 3 6 SFR Information 6 1 Register Name After Reset 00141h 00142h 00143h 00144h 00145h 00146h 00147h 00148h 00149h 0014Ah 0014Bh 0014Ch 0014Dh 0014Eh 0014Fh 00150h 00151h 00152h 00153h 00154h 00155h 00156h 00157h 00158h 00159h 0015Ah 0015Bh 0015Ch 0015Dh 0015Eh 0015Fh 00160h 00161h 00162h 00163h 00164h 00165h 00166h 00167h 00168h 00169h 0016Ah 0016Bh 0016Ch 0016Dh 0016Eh 0016Fh 00

R8C/M11A Group, R8C/M12A Group User`s Manual

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