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MPC8560 and MPC8555 - Freescale Semiconductor
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1. 25 Q I O drivers are used on the PCI interface PCI I O PCI_GNT1 MPC8560 cfg_pci_impd Impedance MPC8560 PCl1_GNT1 MPC8555 cfg_pcii_impd MPC8555 1 42 I O drivers are used on the PCI interface default 25 Q I O drivers are used on the PCI 2 interface PCl2_GNT1 MPC8555 cfg_pci2_impd 1 42 I O drivers are used on the PCI 2 interface default PCI arbiter disabled 1 PCI arbiter enabled default PCI Arbiter PCI _GNT2 MPC8560 cfg_pci_arbiter PCl1_GNT2 MPC8555 MPC8560 cfg_pcil_ arbiter MPC8555 PCl2_GNT2 MPC8555 cfg_pcii_arbiter PCI 2 arbiter disabled 1 PCI 2 arbiter enabled default PCI debug is enabled PCI Debug PCI_GNT3 MPC8560 cfg_pci debug PCI1_GNT3 MPC8555 Normal PCI mode default Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 15 Port C External Interrupts Differences Table 17 POR Configuration Differences continued GanhaurstionSianals Reset Configuration Value g g Name Binary PCI Debug PCI_GNT3 MPC8560 cfg_pci_debug PCI debug is enabled PCI_GNT3 MPC8555 Normal PCI mode default PCI X PCI _GNT4 MPC8560 cfg_pci_mode PCI X mode Memory MSRCIDO cfg_mem_debug Debug PCI mode default DDR Debug MSRCID1 cfg_ddr_debug LBC debug info driven DDR debug info driven default Debug info driven on ECC pins PCI Output LWE 0 1 MPC8560 cfg_pci_hold 0 1 Hold Debug info
2. Table 5 MPC8560 RapidlO Pin Mapping to MPC8555 PCI Signals Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 5 Pin Differences Table 5 MPC8560 RapidlO Pin Mapping to MPC8555 PCI Signals continued Pin MPC8560 MPC8555 AD22 RIO_TD5 PCI2_REQ2 AE22 RIO_TD5 PCl2_REQ3 2 4 CPM Pins MPC8560 Changed to DUART Pins MPC8555 Table 6 shows which MPC8560 CPM pins were reassigned to implement the DUART interface in the MPC8555 For reference the last column of the table shows the pin assignments for the equivalent UART signals on the MPC8560 using the SCCs However it should be noted that the CPM SCC UARTs programming model is different than the DUART block of the MPC8555 For recommended CPM pin mux configurations for both the MPC8560 and MPC8555 see Section 3 One to One CPM Pin Mapping Table 6 MPC8560 CPM Pin Mapping to MPC8555 DUART Signals MPC8560 CPM Port Name MPC8555DUARTName dulvalent SCC UART Signal Pin Assignment od4 UART_RTSO 0d29 SCC1_RTS AD6 pd5 UART_CTSO pc15 5CC1 CTS U9 P11 UART_SINO 0d31 SCC1_RXD AE2 2 5 CPM Pins MPC8560 Changed to No Connect MPC8555 Table 7 shows which MPC8560 CPM pins are reassigned as no connects N C on the MPC8555 Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 6 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Pin D
3. Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 21 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK Designing a Universal PowerQUICC Ill Board MPC8560 and MPC8555 Rev 1 22 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 23 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 0047 Japan 0120 191014 81 3 3440 3569 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Lid Technical Infor
4. the clock pins also map directly to each TDM interface as shown in Table 16 4 Configuration Differences Most POR configuration pins are the same between the MPC8560 and MPC8555 however there are a few exceptions Table 17 shows these exceptions in addition to all possible configurations These differences are due mostly to the differences in available peripheral blocks or relocation of configuration signals Table 17 POR Configuration Differences Confiquration Sianals Reset Configuration Value j 3 Name Binary CCB Clock LA 28 31 cfg_sys_pli 0 3 0010 SYSCLK Ratio A on Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 13 Configuration Differences Table 17 POR Configuration Differences continued Contiauration Sianals Reset Configuration Value 3 Name e S e500 Core LALE LGPL2 cfg_core_pll 0 1 CCB Clock Ratio TSEC1_TXD 6 4 cfg_rom_loc 0 2 PCI PCI X MPC8560 MPC8560 PCI 1 MPC8555 Local bus GPCM 32 bit ROM default Host Agent LWE 2 3 MPC8560 cfg _host_agt 0 1 00 PCI PCI X amp RapidlO agent LWE 2 MPC8555 cfg_host_agt 0 PCI1 Agent MPC8555 a a CPU Boot LA27 cfg_cpu_boot 0 CPU boot hold off mode pee eerste LGPL3 LGPL5 cfg_boot_seq 0 1 11 Boot sequencer disabled default TSEC Width EC MDC cfg_tsec_reduce EN Reduced mode RTBI or RGMII Standard mode TB
5. 0x8079 0010 8 Board Identification It is important to be able to identify the version of the board based on how it is populated To do this the version of the board can be indicated through the use of the value found in the general purpose POR configuration register GPPORCR This value is sampled from the local bus address data signals LAD 0 31 during POR Software can use this value to inform the operating system about initial system configuration allowing software to not only disable those features not used on the processor but to also initialize all of the populated devices on that version of the board using the same software package Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 19 Disabling Peripherals Additionally the POR configuration values of all device parameters sampled from pins at reset such as PLL multiplication values are available through memory mapped registers in the global utilities block 9 Disabling Peripherals The device disable register DEVDISR contains disable bits for various PowerQUICC III functional blocks The register is different between the MPC8560 and MPC8555 because available peripherals differ All functional blocks are enabled after reset unneeded blocks can be disabled to reduce power consumption or allow their signals to be used as general purpose I O signals The disablement of these blocks can be b
6. TDMb2 8555 Port Pins Signals pb27 LiTXD pb26 L1RXD pb25 LiTSYNC pb24 Li1RSYNC 3 4 SPI Pin Muxing The pins for SPI that map one to one are shown in Table 14 Table 14 Recommended SPI Pins for Footprint Compatibility ee ee 3 5 CPM IC Pin Muxing The pins for I C that map one to one are shown in Table 15 Table 15 Recommended I C Pins for Footprint Compatibility Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 12 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Configuration Differences 3 5 1 Banks of Clocks Mapping The CPM provides for multiple clock sources into the PowerQUICC III device The MPC8560 provides 20 possible sources CLK1 CLK20 whereas the MPC8555 provides 14 possible clock sources CLK3 CLK16 When using one to one mapped controllers with NMSI pin muxing available clocks to each controller are the same When using the dedicated serial interfaces for TDM there are exceptions to the available clock sources as shown in Table 16 Table 16 CLK Mapping for MPC8560 and MPC8555 MPC8555 Clock MPC8560 Clock Available clock sources Available clocks for TDMa2 are identical Because the MPC8555 TDMc2 does not map to TDMc2 T SS another TDM interface on MPC8560 care should e l e ed ERIS be taken when using TDMc2 on the MPC8555 Because TDMc2 of the MPC8560 maps directly to the TDMb2 of the MPC8555 as discussed in Section 3 3 TDM Pin Muxing
7. is not driven on ECC pins default PCI 2 buffer delays PCI X 0 buffer delay default PCI 3 buffer delays PCI X 1 buffer delay PCI 0 buffer delay PCI X 2 buffer delays PCI 1 buffer delay PCI X 3 buffer delays PCl1 2 buffers delays default PCl1 0 buffer delay PCl2 2 buffers delays default PCl2 0 buffer delays _h l PCI1_GNT4 MPC8555 cfg_pci1_hold PCI2_GNT4 MPC8555 cfg_pci2_hold Local Bus TSEC2_TXD 6 5 cfg_lb_hold 0 1 Output Hold MPC8560 One buffer delay default Two buffer delays LWE 0 1 MPC8555 EE Three buffer delays 00 Zero buffer delays General LAD 0 31 cfg_gpporcr Xx Vector placed in GPPORCR Purpose POR 5 Port C External Interrupts Differences The MPC8560 has 16 potential external interrupts through the use of the CPM s Port C Since PC2 and PC3 are N Cs on the MPC8555 two potential interrupts had to be moved to another location in Port C PC23 and PC29 However it should be noted that the priority levels of PC23 and 29 are higher than the rest of the external interrupts and not the same as PC2 and PC3 The available interrupts and their priority levels are shown in Table 15 To maintain interrupt priorities and pin compatibility PC2 PC3 PC23 and PC29 should not be used for interrupts on a universal PowerQUICC III board Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 16 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale S
8. must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The PowerPC name is a trademark of IBM Corp and is used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 Lo 2 freescale semiconductor
9. to provide a population option for the 100 Q 1 KQ resistor for the MPC8555 These changes are summarized in Table 2 Table 2 MPC8560 to MPC8555 TEST_SEL Pin Changes Pin Assignments MPC8560 MPC8555 AH20 TEST SEL TEST _SELO 2 Kbyte 10 Kbyte pull up to OVdd 2 Kbyte 10 Kbyte pull up to OVdd AG26 GND TEST SEL1 0 Q resistor to GND 100 Q 1 KQ resistor to GND 2 2 PCI Pin Changes There are no changes if using the MPC8555 PCI1 interface as one 64 bit port or as one 32 bit port in synchronous mode However the MPC8555 can also be configured to have two independent PCI 32 interfaces PCI1 and PCI2 The following sections describe changes in the pins when using the PCI2 features of the MPC8555 2 2 1 No Connects MPC8560 to Functional Pins MPC8555 No Changes if Used the Same as MPC8560 Table 3 shows the differences between no connect N C pins in the MPC8560 and pin assignments in the MPC8555 using the PCI interface in asynchronous mode Table 3 MPC8560 No Connects Mapping to MPC8555 PCI Signals Pe ween AF28 AVDD4 If PCI1 is disabled DEVDISR PCI1 1 or is in synchronous mode this signal can float or be tied to VDD in asynchronous mode this signal must be tied to VDD When tied to VDD the PLL power supply filter circuit See Figure 1 should be implemented AE28 AVDD5 If PCI2 is disabled DEVDISR PCI2 1 or is in synchronous mode this signal can float or be tied to Vpp in asynchronous mode this signal must be t
10. 4 All rights reserved PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE COO WANN NAN FB WN p Document Revision History Contents Feature Differences c4 042660040 e eae we ve ctu we es 2 Pin Differences 2 4 0 24404 She dee dens oe Ree ted 2 One to One CPM Pin Mapping 9 Configuration Differences 0 13 Port C External Interrupts Differences 16 Register Differences 2 ccc2a eee cis ces dioaeeds 17 Processor Identification 0000 19 Board Identification 1905 2aessn aw aden eeeaws 19 Disabling Peripherals 444 5 444e6a06 e4944 20 Universal Schematic and Layout Symbol Creation 20 Wy 2 freescale semiconductor Feature Differences 1 Feature Differences The PowerQUICC III architecture of the MPC8560 and the MPC8555 integrates two processing blocks the high performance embedded e500 core and the communications processor module CPM The e500 core implements the Book E instruction set architecture and provides unprecedented levels of hardware and software debugging support The CPM supports a wide variety of protocols However as shown in Table 1 the MPC8555 provides a subset of the MPC8560 s CPM capabilities Both processors offer a 256 Kbyte L2 cache two integrated TSECs a DDR SDRAM memory controller a programmable interrupt controller C controllers a four channel DMA controller and a general purpose I O port Howev
11. Freescale Semiconductor Application Note AN2657 Rev 1 12 2004 Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 by Kyle Aubrey Field Applications Engineering NCSG San Jose CA Each processor in the PowerQUICC III family has unique features targeted to interface with a particular price point and functionality set Because the 8555 and 8560 PowerQUICC III devices have the same footprint it is possible to design a single board to support either of these PowerQUICC III processors This allows a universal board to support a wide variety of applications through different component populations For instance a board populated one way could support lower port count and lower power using a MPC8555 at 533 MHz but could be populated differently to support a higher port count and higher performance using the MPC8560 at 833 MHz The result is lower fabrication costs and a wider portfolio selection Also because devices in the PowerQUICC III family have an e500 core and in most cases the same peripherals a single software package can be maintained for the different builds of the same fabricated board This application note is intended to assist hardware and software engineers in designing such a universal board specifically for the MPC8560 and the MPC8555 by providing the pin configuration and register differences as well as other recommendations The following topics are addressed Freescale Semiconductor Inc 200
12. I or GMII default TSEC1 TSEC1_TXD7 MPC8560 a TSEC1 GMII or RGMII Protocol TSEC2 TSEC2_TXD7 MPC8560 cfg_tsec2 i TSEC2 GMII or RGMII Protocol TSEC2_ TXD2 MPC8SSS TSEC2 TBI or RTBI default Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 14 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Configuration Differences Table 17 POR Configuration Differences continued Genilauration Signals Reset Configuration Value g g Name Binary RapidlO LGPLO LGPL1 MPC8560 cfg_no_clk 0 1 01 RapidlO RxCLK is source of Transmit TxCLK 10 RapidlO TxCLK inputs are source of TxCLK 11 CCB clock is source of TxCLK default RapidlO TSEC2 TXD2 MPC8560 cfg dev_ID5 Device ID for RapidlO hosts Device ID j TSEC2 TXD3 MPC8560 cfg_dev_ID6 Device ID for RapidlO hosts TSEC2_TXD4 MPC8560 cfg_dev_ID7 X Device ID for RapidlO hosts TSEC2_TXD1 MPC8555 cfg_pcil_clk Async mode PCI1_CLK used 1 Sync mode SYSCLK used default TSEC2_TXDO MPC8555 cfg_pci2_clk Async mode PCI2_CLK used 1 Sync mode SYSCLK used default PCI Width PCI _REQ64 MPC8560 cfg_pci width PCI PCI X operates in 64 bit mode MPC8560 PCI operates in 64 bit mode MPC8555 Clock Source PCI 1 Clock Select PCI 2 Clock Select PCI1_REQ64 PCI2_ FRAME MPC8555 PCI PCI X operates in 32 bit mode MPC8560 default PCI operates as two 32 bit interfaces MPC8555 default
13. _AD20 PCI1_AD21 PCI1_AD22 PCI1_AD23 PCI1_AD24 PCI1_AD25 PCI1_AD26 PCI1_AD27 PCI1_AD28 PCI1_AD29 PCI1_AD3 PCI1_AD30 PCI1_AD31 PCI1_AD4 PCI1_AD5 W11 AF5 AF3 AE4 G4 E5 Y11 V11 AG10 AF18 AF17 AD16 AC16 AB16 W16 V16 AH15 AG15 AD15 AC15 AB15 AE17 AE14 MPC8555 PCl1_IRDY PCl1_PERR PCI1_REQO PCl1_REQ1 PCI1_REQ2 PCI1_REQ3 PCl1_REQ4 PCl1_SERR PCl1_STOP PCl1_TRDY PCl2_ADO PCI2_AD1 PCI2_AD10 PCI2_AD11 PCI2_AD12 PCI2_AD13 PCI2_AD14 PCI2_AD15 PCI2_AD16 PCI2_AD17 PCI2_AD18 PCI2_AD19 PCI2_AD2 PCI2_AD20 PCI2_AD21 PCI2_AD22 PCI2_AD23 PCI2_AD24 PCI2_AD25 PCI2_AD26 PCI2_AD27 Freescale Semiconductor Pin Differences Table 4 PCI Signal Mapping MPC8560 to MPC8555 continued AE12 PCI1_AD6 AD14 PCI2_AD28 AD12 PCI1_AD7 AC14 PCI2_AD29 AB12 PCI1_AD8 AB17 PCI2 AD3 Y12 PCI1_AD9 AB14 PCI2_AD30 AC12 PCI1_C BEO AA14 PCI2_AD31 AD11 PCI1_C BE1 AA17 PCI2_AD4 AB10 PCI1_C BE2 Y17 PCI2_AD5 AH8 PCI1_C BE3 W17 PCI2_AD6 AH10 PCI1_DEVSEL V17 PCI2_AD7 AC10 PCI1_FRAME AF16 PCI2_AD8 AE6 PCI1_GNTO AE16 PCI2_AD9 AG5 PCI1_GNT1 W14 PCI2_C BEO AH5 PCI1_GNT2 V14 PCI2_C BE1 AF6 PCI1_GNT3 AH13 PCI2_C BE2 AAQ AE13 PCI2_ FRAME 2 3 RapidlO Pins MPC8560 Changed to Second 32 Bit PCI Interface MPC8555 Table 5 shows which MPC8560 RapidIO pins were reassigned to implement the second 32 bit PCI interface in the MPC8555 If the RapidIO interface is not used on the MPC8560 DEVDISR RIO should be set to disable the logic
14. a particular revision level marked on the device as shown in Table 21 These registers can be accessed as SPRs through the e500 core or as memory mapped registers As such a single software package can be created based on these registers that supports not only multiple silicon revisions of the same PowerQUICC III processor by addressing certain errata workarounds for a particular revision but that also supports different members of the PowerQUICC III family The PVR identifies the version of the processor and the implementation of the version Different version numbers indicate major differences between processors such as which optional facilities and instructions are supported Different revision numbers indicate minor differences between processors having the same version number such as clock rate and engineering change level The SVR identifies the version of the system logic and the implementation of the version Different version numbers indicate major differences in system logic Different revision numbers indicate less significant changes in system logic to address system logic errata or enhance certain features Table 21 Revision Level to Device Marking Cross Reference Silicon e500 Core Device Markin Processor Version System Version Revision Revision g Register PVR Register SVR MPC8560 Rev 1 PPC8560PXxxxLA 0x8020 0010 0x8070 0010 MPC8560 Rev 2 MPC8560PXxxxLB 0x8020 0020 0x8070 0020 MPC8555 Rev 1 MPC8555PXxxxLA 0x8020 0010
15. ased on either the system version and or the board version as mentioned in the previous two sections Please note that blocks disabled by DEVDISR must not be re enabled without a hard reset 10 Universal Schematic and Layout Symbol Creation The MPC8560 and MPC8555 have identical footprints so the same layout symbol may be used for both It is recommended that unified schematic symbols be created for both the MPC8560 and MPC8555 if both processors are going to be used for the same fabricated board If this is not feasible the creation of two identical symbol blocks with all NCs and Reserved pins shown should be created Additionally all signals listed in Section 2 Pin Differences should maintain the identical pin placement for creating visual compatibility in the schematic To obtain the schematic symbols for both the MPC8560 and MPC8555 contact your local Motorola salesperson or field applications engineer FAE Symbols are available in Mentor Graphics compatible and EDIF formats 11 Document Revision History Table 22 provides a revision history for this application note Table 22 Revision History Table Revision Date Substantive Change s 1 12 2004 Updated document template In Table 5 changed pin assignments to PCI2_STOP AC21and PCI2_REQ4 AC23 4 2004 Initial release Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 20 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
16. emiconductor Register Differences Table 18 Port C External Interrupt Differences 18 Highest PC15 54 Lowest PCO PCO 6 Register Differences Due to peripheral differences between the MPC8560 and MPC8555 certain register differences need to be addressed For instance the MPC8555 has added registers for the second PCI port but has removed the RapidIO registers This section discusses other associated register and field differences between the two devices Additionally note that any reserved field or area of memory should not be programmed doing so could cause unwanted behavior of the device In most cases reserved fields should be cleared when programming registers however this may not always be the case The user should refer to the user manual for more information on proper programming of reserved fields This section only covers the differences common registers are not shown 6 1 MPC8560 Only Registers Table 19 indicates which registers are available only on the MPC8560 for those registers that are only available on the MPC8555 refer to Table 20 Please note that there may be some fields in matching registers that are only available for the MPC8560 or vice versa The user should refer to the user manuals of both devices for a comparison of these registers Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 17 Register Difference
17. er as Table also shows there are differences in the peripheral interfaces for PCI and RapidIO support The MPC8555 has an integrated hardware encryption block that 1s not supported by the MPC8560 Table 1 MPC8560 and MPC8555 Feature Differences TDMa2 TDMb2 TDMc2 TDMd2 TDMa2 TDMb2 TDMc2 Max logical TDM channels 256 128 per MCC ATM UTOPIA L2 FCC1 8 16b FCC2 8 bit FCC1 8 bit FCC2 8 bit 155 Mbps AALx AAL1 CES IMA TC Layer Muxed with SCC3 Low or full speed TT h aC only O Dedicated and non dedicated SCC1 SCC2 SCC3 SCC4 SCC1 SCC3 SCC4 SMC1 SMC2 SCCs SMCs UARTs DUART Security O IPSec SSL TLS SRTP 802 11i iSCSI IKE N N Single 32 64 bit PCI PCI X Single 32 64 bit PCI or dual PCI 32 bit 32 bit 2 Pin Differences Except where noted this section lists different pin assignments from the MPC8560 to the MPC8555 2 1 TEST SEL Pin Changes The AH20 TEST_SEL signal on the MPC8560 should be pulled high This signal is named TEST_SELO on the MPC8555 and should also be tied high with a 2 10 KQ resistor Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 2 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Pin Differences The AG26 pin is a GND signal on the MPC8560 but it is TEST_SEL1 on the MPC8555 and should be tied to ground through a 100 Q 1 KQ resistor For a universal board the MPC8560 should use a 0 Q resistor to GND for this signal
18. ied to VDD When tied to VDD the PLL power supply filter circuit see Figure 1 should be implemented AH25 PCl1_CLK If PCI1 is disabled or is in synchronous mode this signal can float or be tied to VDD if in asynchronous mode connect to PCI clock AH27 PCl2 CLK If PCl2 is disabled or is in synchronous mode this signal can float or be tied to VDD if in asynchronous mode connect to PCI clock Figure shows the PLL power supply filter circuit for AVDD when running in asynchronous PCI mode 10 Q Vap AVDD4 or AVDD5 2 2 uF 2 2 uF Low ESL Surface Mount Capacitors Figure 1 PLL Power Supply Filter Circuit Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Pin Differences 2 2 2 PCI Pins MPC8560 Changed to Dual PCI Functionality MPC8555 No Changes if Used the Same as MPC8560 Table 4 shows the MPC8560 PCI signals that were renamed to implement the dual PCI functionality in the MPC8555 Table 4 PCI Signal Mapping MPC8560 to MPC8555 AD13 PCL ACK64 I co Z as o AH12 PCI AD4 AG12 PCI_AD5 Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE MPC8555 PCl2_DEVSEL PCI2_PAR PCl1_PAR PCl1_ADO PCl1_AD1 PClI1_AD10 PCl1_AD11 PCI1_AD12 PCI1_AD13 PCl1_AD14 PCI1_AD15 PCl1_AD16 PCl1_AD17 PCl1_AD18 PCI1_AD19 PCI1_AD2 PCI1
19. ifferences Table 7 MPC8560 CPM Pin Mapping to No Connects on MPC8555 Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 7 Pin Differences 2 6 MPC8560 RapidlO Pins Changed to No Connect MPC8555 Table 8 shows which MPC8560 RapidIO pins are reassigned as no connects on the MPC8555 Note that if the MPC8560 s RapidIO port is not used it should be disabled with software by setting DEVDISR RIO If disabled all RapidIO signals can be seen as N Cs and left unterminated saving valuable board space Table 8 MPC8560 RapidlO Pin Mapping to No Connects on MPC8555 AF24 N C j r Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 8 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor One to One CPM Pin Mapping 3 One to One CPM Pin Mapping Because some functionality and port pins have been removed from the MPC8555 s CPM care should be taken in selecting which pins to use to maintain functionality on the universal PowerQUICC III board when moving from the MPC8560 to the MPC8555 This section describes which dedicated controller signals and serial interfaces are identical for the MPC8560 and MPC8555 3 1 FCC Pin Muxing The logic for FCC3 and the 16 bit UTOPIA interface for FCC1 is not available with the MPC8555 CPM Additionally the 8 bit UTOPIA interface pins on the FCC2 do not map one to one be
20. ing The logic for SCC2 is not available with the MPC8555 CPM The pins for SCC1 SCC3 and SCC4 that map one to one for the MPC8560 and MPC8555 are shown in Table 11 Table 11 Recommended SCCx Pins for Footprint Compatibility UART HDLC Transparent pd23 RTS pc11 pc8 CTS pd21 TxD pd22 pd20 pc9 pc8 3 3 TDM Pin Muxing MPC8560 and MPC8555 support multiple serial interfaces for dedicated TDM streams The MPC8560 supports a total of eight possible serial interfaces TDMal TDMd1 and TDMa2 TDMd2 whereas the MPC8555 supports only three TDMa2 TDMb2 and TDMc2 For complete one to one mapping only TDMa2 can be used If LIRQ and LICLKO are not required TDMc2 MPC8560 TDMb2 MPC8555 can be used However it should be noted that SIRAM register differences apply Lastly TDMc2 on the MPC8555 does not map to another TDM port on the MPC8560 The pins for TDMa2 that map one to one for the MPC8560 and MPC8555 are shown in Table 12 Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 11 One to One CPM Pin Mapping Table 12 Recommended TDMaz2 Pins for Footprint Compatibility Serial Interface Port Pins TDMa2 Signals pd22 L1TXD The pins for TDMc2 MPC8560 and TDMb2 MPC8555 that map one to one are shown in Table 13 Table 13 Recommended TDMc2 MPC8560 TDMb2 MPC8555 Pins for Footprint Compatibility Serial Interface TDMc2 8560
21. mation Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com AN2657 Rev 1 12 2004 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals
22. s Table 19 MPC8560 Only CCSR Registers ee O DPRAM1 Dual Port RAM 16k DPRAM2 Dual Port RAM 16k Ox9_13D0 0x9_13FF OxA_O000 0xA_7FFF IRAM instruction RAM 32k OxC_0000 0x RapidlO registers See the MPC8560 Reference Manual for a full description of all associated registers 6 2 MPC8555 Only Registers Table 20 indicates which registers are only available only on the MPC8555 for those registers which are only available on the MPC8560 refer to Table 19 Table 20 MPC8555 Only CCSR Registers a Ox0_4500 0x 0 4511 UARTO registers Ox0_4600 0x0_ 4611 UART1 registers 0x0_9000 0x0_9FFC PCl2 registers Ox3_0000 0x3_CFFF Security engine registers Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 18 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Processor Identification Table 20 MPC8555 Only CCSR Registers continued ae se 0x8 _0000 0x8_1FFF DPRAM1 dual port RAM 8 Kbytes Ox8_8000 0x8_9FFF DPRAM2 dual port RAM 8 Kbytes 0x9 1A82 0x9_1A8F SMC1 registers 0x9 1A92 0x9_1A9F SMC2 registers 0x9_1B0C CMXSMR CPM Mux SMC clock route register 0x9_1B60 0x9_1FFF USB registers OxA_0000 0xA_OFFF IRAM instruction RAM 4 Kbytes See the MPC8555 Reference Manual for a full description of all associated registers 7 Processor Identification The revision codes in the processor version register PVR and the system version register SVR map to
23. tween the MPC8560 and MPC8555 so it is recommended to only use FCC1 for the UTOPIA interface when designing a universal PowerQUICC III board to support ATM In summary the interfaces that map one to one for FCC1 for both the MPC8560 and MPC8555 are 8 bit UTOPIA for ATM Fast Ethernet via RMII or MII HDLC and Transparent as shown in Table 9 Table 9 Recommended FCC1 Pins for Footprint Compatibility FCC1 NMSI UTOPIA L2 Port Pins 8 Bit Transparent pa18 3 po p TxADDR3 pd19 TxADDR4 Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 9 One to One CPM Pin Mapping Table 9 Recommended FCC1 Pins for Footprint Compatibility continued FCC1 NMSI RA om a HDLC Port Pins 8 Bit Transparent w f E me fa E O w mow en R e se n o o r soc ov osv CO er e o o The interfaces for FCC2 are Fast Ethernet using MII or RMII HDLC and Transparent as shown in Table 10 Table 10 Recommended FCC2 Pins for Footprint Compatibility FCC2 NMSI om foam HDLC Port Pins Transparent pb26 CRS ae Designing a Universal PowerQUICC III Board MPC8560 and MPC8555 Rev 1 10 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor One to One CPM Pin Mapping Table 10 Recommended FCC2 Pins for Footprint Compatibility continued FCC2 NMSI HDLC Port Pins Transparent pb28 RX_ER RX_ER RTS 3 2 SCC Pin Mux
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