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AD1000 User`s Manual - RTD Embedded Technologies, Inc.

1. 20 usec typ Sample and hold acquisition time eese 20 usec max 25 kHz Digital UO conan CMOS 82C55 Number of lines eese 24 16 at 1 O connector amp 8 on board High level output voltage 4 2 min Low level output voltage esses 0 45V max High level input voltage eese 2 2V min 5 5V max Low level input voltage 0 3V min 0 8V max High level output current Isource sese eene nnne nennt 100 pA max Low level output current Isink eese eee eene 1 7 mA max Darlington drive current DAR 1 0 mA min 5 0 mA max Available on any 8 pins from port B and port C mM 10 Input capacitance eo LEA 10 pF Output capacitance G OUT lt F 1MHZ E 20 pF iuge de CMOS 82C54 Three 16 bit down counters Binary or BCD counting Programmable operating modes 6 Interrupt on terminal count programmable one shot rate generator Square wave rate generator software triggered strobe hardware triggered strobe Counter input 2 External clock 8 MHz max on board 5 MHz clock Counter Outputs euresnsonennsnesonensne
2. eese entente teen ete entente tnt 1 5 EXTINT and Interrupt Jumpers P4 esee tete rn arena 1 5 8254 Programmable Interval Timer Jumpers P5 susus0sssensnenssenenonnenssnssenenenssnenenssnenennnnnnenenennenenentenn 1 6 8254 and P5 1 7 Base Address Jumper P6 1 8 End of Convert Jumper 8 1 9 P7 Connector Pin Assignments 1 0 0 2 3 Analog Input Connection eueesssusnensnsonenenenenenenensnnenenennonsnansnsnsnnnnsnsnnnnnnsnensstsnsnsstssssnnssnennesenssnensnssanssosnensnnene 2 4 AD1000 Block Diagram apre iei LEa 3 3 A D Conversion Timing Diagram 1 1 4 8 8254 Timer Counter Circuitry 4 14 Single Conversi n Flow Diagram 4 16 O nee 5 3 iii INTRODUCTION The AD1000 medium speed multichannel analog input board turns your IBM PC XT AT or compatible computer into a high performance data acquisition and control system Installed within a single short or full size expansion slot in the computer the AD1000 board features
3. outor L3 o 3 n neu 3 o meu eur 12 oureur oureur El gs en ERE ES 3 3 eurer 3 8 eur MODE 0 Configurations CONTROL WORD 9 CONTROL WORD 2 O 0 D D D D D 0 0 D 0 0 0 D D CONTROL WORD 81 CONTROL WORD 3 9 0 0 D 0 5 0 D D 0 D D D D 231256 10 3 131 82C55A MODE 0 Configurations Continued CONTROL WORD 4 D De 0 D CONTROL WORD 5 0 0 0 0 0 CONTROL WORD 66 D 9 D D 0 0 D D CONTROL WORD 7 D 0 D 0 D D D 3 132 CONTROL WORD 68 D 0 D CONTROL WORD 98 D De 0 D D D 0 D CONTROL WORD 10 0 0 0 0 D 0 D 0 CONTROL WORD 611 D 0 0 0 0 D D 231256 11 intel 82C55A MODE 0 Configurations Continued CONTROL WORD 912 O 0 Os 0 0 0 0 CONTROL WORD 13 D Os 0 D D D Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring 1 data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 Port and Port B use the lines on Port C to generate or accept these handshaking signals CONTROL WORD D De 0 0 D 0 D CONTROL WORD 615 0 0 0 0 0 0 D Dy 3 Pa 231256 12
4. 18 8254 Timer Counter 2 Read Write cersessessrenesoenesnsonsnnsnanenssnnunenonsnennrsorsnesntnresenorensensansenensossnnsnsnrenne 4 6 19 8254 Timer Counter Control Word Write Only essersessesnenensssensssnennnsnnnnesntsssnennsnnnnensenensennennenennsenen 4 6 Programming the AD1000 4 7 A D Conversions enaenssssnsnessnesnonsnenssenensonenenenenenennenensnnnennnensnssesnnsnussenssnensnenssnsennsnssssnsannsunsuensnenuersusnanssnesussensarsenee 4 8 Initializing the 1000 22 4 8 Selecting a 44 4 8 Starting A D Conversion PR 4 8 Monitoring Conversion Status eesseecssnssssnssnsnnansunensnnensensnssnsnssnsnssnsnsenessenessenssntnsnstnsnsensnsenensansnensenenssssnsnosnensenen 4 9 Reading the Converted Data urusesesssssnssnsesnnsnsnsnnnnsuensenenennnersnsnsenennnnensnnnsensnesenensnnnssnensunnsnsensurnensnsnsnnenenene 4 9 entre E 4 10 What Is an Interrupt eeeescesssessenenssenanasnsnsnenenssusnenunsnsnnnnsnsnssenssnssennsensssensnennessnsusnsonsnenssssnssesnensssaennensnssnsesnene 4 10 Interrupt Request Lines uceeeeseceseseosenenesoresnensnsonsnenennnsnnnnnnenennunnnnnennsnnassestnnsnnnensnsnssnsssssenenssennensnastsnssnsnsnsonen 4 10 8259 Programmable Interrupt 4 10 Interrupt M
5. Supply Current Standby cik Frag DC Supply Current Standby ANE All Inputs Data Bus All Outputs Floating CLK Freq CS Voc All Other Inputs Pins Outputs Open Input Capacitance fe 1MHz Capacitance EM A Output Capacitance IAN E pe CHARACTERISTICS TA 0 C to 70 C 5V 10 GND 0V 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE 0 omm un Stable Before RD ion Eo p FD Pulse With ao uo Data Delay Ad ress we ROT to Data Fioatng 5 200 NOTE 1 AC timings measured at 2 0V 0 8 9 96 intel 82054 A C CHARACTERISTICS Continued WRITE CYCLE Parameter Units Address Stable Before WR S Stable Before WR Address Hold Time After WR R Pulse Width ata Setup Time Before WR ata Hold Time After WR T Command Recovery Time o 1 1 W BE gt Y C gt gt gt tav 165 gt CLOCK AND GATE Parameter 82654 Symbol 826542 CA A tax 115 Dc wo oc m town HighPulsewiath om 309 tw LowPuseWim eo som m Ta 5
6. Mode 1 Basic functional Definitions e Two Groups Group A and Group B e Each group contains one 8 bit data port and one 4 bit control data port e The 8 bit data port can be either input or output Both inputs and outputs are latched e The 4 bit port is used for contro and status of the 8 bit data port 3 133 intel 82C55A Input Contro Signal Definition MODE 1 PORT A STB Strobe Input A low on this input loads data into the input latch CONTROL WORD 0 Os D 0 0 D 0 IBF input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR interrupt Request MODE 1 PORT B A high on this output can be used to interrupt the REED CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one ORO T KO and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B 231256 13 Controlled by bit set reset of Figure 8 MODE 1 input INPUT FROM __ PERIPHERAL 231256 14 Figure 9 MODE 1 Strobed Input intel 82 55 Output Control Signal Definition OBF Output Buff
7. Towra Ds O Latch count of selected counter s Da O Latch status of selected counter s Da 1 Select counter 2 02 1 Select counter 1 D4 1 Select counter 0 Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the 82654 count all but the first are ignored the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits 05 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s ou
8. Analog Word 00000000000000000000 ADDRESS 00000000 00055555 0 5 9 AD1000 Board Layout ATLANTIS assumes that the base address of your AD1000 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The base addresses on the AD1000 board are given in hexadecimal The ATINST program requires the base address to be entered in decimal notation The following table provides the hex and decimal values P5 8254 Timer Counter I O Configuration The 8254 must be configured with jumpers placed between the pins as shown in Figure E 2 This is the factory setting Verify that each jumper is in the proper location Any remaining jumpers must be removed from the 5 header connector E 4 P5 OUT1 CLK2 OUT2 Fig E 2 8254 TimerCounter Jumpers for ATLANTIS P5 XTAL EXCKO 5V EXGTO CKOTO CKOTO CK1 XTAL EXCK1 5V EXGT1 CKOT1 CKOT1 CK2 XTAL EXCK2 5V EXGT2 CKOT2 CKOT2 EXTINT RESET P3 Timer Counter Output Interrupt To select an IRQ channel and an interrupt source you must install the two jumpers which are stored on this header connector To configure this header for ATLANTIS place one jumper across the pins of your desired IRQ channel and place the second jumper across the pins of OUT2 the output
9. Group Port C Upper L a a a a as 4 0 output 1 input Group A ee zl Set Reset Bit Set Reset Function Bit Bit Select 0 set bit to 0 0 active 000 PCO 1 set bit to 1 001 PC1 010 PC2 011 PC3 100 PC4 101 PC5 110 PC6 111 PC7 For example if you want to set Port bit 0 to 1 you would set up control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is set up like this 4 5 0 X X X 0 0 0 1 Sets PCO to 1 written to BA 15 X don t care Set Reset Set PCO Function Bit Bit Select 000 PCO BA 16 8254 Timer Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 17 8254 Timer Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 18 8254 Timer Counter 2 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded BA 19 8254 Timer Counter Control Word Write Only Accesses the 8254 control register to directly control the three timer counters BCD Binary 0 binary 1 BCD Counter Select 00 Counter 0 01 Counter 1 Counter Mode Select 000 Mode 0 eve
10. 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens MEN intel 82054 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written CWx18 1583 FF FF FF FF 0 0 0 0 N 3 2 1 0 FE Fo CWs18 158 3 pepepe S4 18 58 3 158 2 0 lo Fe 231244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again 3 94 After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does n
11. 3 gt o gt a a BA 0 Channel 1 AINI Select Write Only Writing to this address selects analog input channel 1 AIN1 The data written is irrelevant After you select channel 1 it remains active until you select another channel or power down BA 1 Channel 2 AIN2 Select Write Only Writing to this address selects analog input channel 2 AIN2 The data written is irrelevant After you select channel 2 it remains active until you select another channel or power down BA 2 Channel 3 AIN3 Select Write Only Writing to this address selects analog input channel 3 AIN3 The data written is irrelevant After you select channel 3 it remains active until you select another channel or power down 43 BA 3 Channel 4 4 Select Write Only Writing to this address selects analog input channel 4 AIN4 The data written is irrelevant After you select channel 4 it remains active until you select another channel or power down BA 4 Channel 5 AIN5 Select Write Only Writing to this address selects analog input channel 5 AIN5 The data written is irrelevant After you select channel 5 it remains active until you select another channel or power down BA 5 Channel 6 AIN6 Select Write Only Writing to this address selects analog input channel 6 AIN6 The data written is irrelevant After you select channel 6 it remains active until you se
12. 3 142 intel 82C55A OTHER TIMINGS we 100 tm Per Data After STBHigh ACK 0tOuput ko ACK 1toOutputrioat two 1toOBF 0 to OBF 1 tsa STB Oto IBF 1 tie 0 1 Units o 3 3 Ple RD R B wr w mw wr WR oemm o me ns semi wes ResetPuse wam so NOTE 1 INTR may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses may be 500 ns minimum 3 143 intel 82C55A WAVEFORMS MODE 0 BASIC INPUT 231256 22 MODE 0 BASIC OUTPUT 231256 23 3 144 intel 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM PERIPHERAL 231256 24 MODE 1 STROBED OUTPUT 231256 25 3 145 intel 82 55 WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 8255 PERIPHERAL Bus r DATA FROM DATA FROM PERIPHERAL TO 8255 8255 TO PERIPHERAL DATA FROM 8255 TO 080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD is permissible INTR IBF MASK e STB RD MASK e WR WRITE TIMING READ TIMING DATA BUS DATA BUS 7 HIGH IMPEDANCE VALID THIGH IMPEDANCE 231256 28 A C TESTING LOAD CIRCUIT 231256 29 A C
13. AD1000 board In the directory there are several H files which are needed to implement the programs These files contain the routines called by the main programs In the Pascal directory PSL files contain all of the procedures needed to implement the main Pascal programs Analog to Digital READ Demonstrates how to take A D conversions Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer Digital VO INPO Simple program that shows how to set up the PPI lines as input lines OUTO Simple program that shows how to set up the PPI lines as output lines BASIC Programs These programs include source code files for easy custom program development Analog to Digital READ Demonstrates how to take A D conversions Timer Counters TIMER A short program demonstrating how to program 8254 for use as a timer Digital INPO Simple program that shows how to set up the PPI lines as input lines OUTO Simple program that shows how to set up the PPI lines as output lines 4 15 Flow Diagrams Single Convert Flow Diagram Figure 4 3 This flow diagram shows you the steps for taking a single sample on a selected channel A sample is taken each time you send the Start Convert command All of the samples will be taken on the same channel until you select a new channel Changing the I O address before each Start Convert command is issued lets you take the next readin
14. Eight single ended analog input channels 12 bit 20 microsecond A D converter 25 kHz maximum throughput 5 volt analog input range Three independent 8 MHz timer counters 3 24 TTL CMOS compatible 8255 based digital I O lines 16 at the 1 connector and 8 at on board pads The following paragraphs briefly describe the major functions of the board More detailed discussions of board functions are included in Chapter 3 Hardware Description and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Analog to Digital Conversion The analog to digital A D circuitry receives up to eight single ended analog inputs and converts these inputs into 12 bit digital data words which can then be read and or transferred to PC memory The input voltage range is 5 to 5 volts with overvoltage protection to 35 volts A D conversions are per formed by an industry standard 12 bit successive approximation converter This high performance converter and the high speed sample and hold amplifier preceding it make sure that dynamic input voltages are accurately digitized The resolution of a 12 bit conversion is 2 4414 millivolts and themaximum throughput is 25 kHz The converted data is read and or transferred to PC memory one byte at a time through the PC data bus 8254 Timer Counter An 8254 programmable interval timer contains three 16 bit 8 MHz timer counters to support a wide range
15. Testing inputs Are Driven At 2 4V For A Logic 1 And 0 45V j For A Logic 0 Timing Measurements Are Made At 2 0V For Is Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For A Logic 0 The Specification Includes Jig Capacitance 231256 30 3 146 APPENDIX D CONFIGURING THE AD1000 FOR SIGNAL MATH D 1 D 2 Jumper Settings When running SIGNAL MATH you may need to change some of the AD1000 s on board jumpers from their current positions Before using SIGNAL MATH on the AD1000 board check the following jumpers P6 Base address P5 8254 timer counter I O configuration P2 amp P4 Interrupts P8 End of convert monitor The board layout is shown in Figure D 1 0000 9000 25 o samp Dm AD1000 DATA ACQUISITION amp CONTROL SYSTEM j m 5 000000000 ar ED d 000000000 0000000 ar er 0000000 _00000000000000000000 Kama 0000000 A OO EERETRRT NE EEEE 00000000 sx 00000000 00000000 00000000 ee 00000000 V 00005000 S Real Time Devices Inc State College PA 16804 USA 000000000000 000000000000 00000000000009 S s Fig D 1 AD1000 Board Layout P6 Base Address SIGNAL MATH assumes that the base address of your AD1000 is the fac
16. 3 m corame 2s 5 tw GaewahHgn so m s so Gate Hold Time so so Too Output Delay from 100 topa Delay trom Gate 120 100 wc GLK Delay torLoading o s o s nm Gate Delay for Sampling 4 s5 5 40 ns two OUT Delay from Mode Write 240 ms CountLaton 40 45 40 40 NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns tor the 82 54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwH tew may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampied not 100 tested Ta 25 C 6 CLK present at Two min then Count equals N 2 CLK pulses max equals Count N 1 CLK pulse min to max count will be either N 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at min Counter will not be triggered at max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Tc min CLK will be reflected in count value latched at max CLK will not be reflected in the count value latched Writing a Counter Latch or ReadBack Command betw
17. 4 EXTINT and PC3 Interrupt Jumpers P4 P5 8254 Timer Counter I O Header Connector Factory Settings As Shown in Figure 1 5 Header connector P5 shown in Figure 1 5 configures the 8254 programmable interval timer s clock and gate sources and output connections Also included on P5 are pins to route an external interrupt EXTINT from and the computer s RESET signal to external I O connector P7 Figure 1 5 shows the factory settings All three timer counters are cascaded These are the settings used by SIGNAL MATH and ATLANTIS acquisition and analysis software see Appendixes D and E 5 XTAL o EXCKO o 45V LE o EXGTO CKOTO 2 CKOTO sl XTAL al 1 5V H O EXGT1 CKOT1 5 CKOT1 5 XTAL 2 5V H EXGT2 CKOT2 CKOT2 EXTINT RESET Fig 1 5 8254 Programmable Interval Timer Jumpers 5 The 8254 provides three independent 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts Each timer counter has two inputs clock CK in and gate GT in and one output timer counter OUT Figure 1 6 shows a block diagram of the 8254 and PS circuitry Starting from the top of P5 the first three groups of pins on the left side are labeled and OUTO the three I O signals for timer counter 0 The signals on the right side for timer counter 0 are
18. CARRIER 231244 1 Figure 1 82C54 Block Diagram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82 54 Pinout September 1989 3 83 Order Number 231244 005 intel 8254 Table 1 Pin Description m O Output 0 Output of Counter I Gate 0 Gate input of Counter 0 ts Ground Power supply connection O Outs Output of Counter 1 Gate 1 Gate input of Clock 1 Clock input of Countert Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus Counter 0 Counter 1 Counter 2 Control Word Register Chip Select A low on this input enables the 82054 to respond to RD and WR signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations Write Control This input is low during CPU write operations Power 5V power supply connection 1 11 15 25 FUNCTIONAL DESCRIPTION sired delay After the desired delay the 82C54 will interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated General Some of the other counter timer functions common The 82C54 is a programmable interval timer counter to microcomputers which can be implemented with designed for use with Intel microcompu
19. Start Convert A D Status Converting Not Converting Converting Not Converting End of Convert Read Data LSB MSB LSB MSB Fig 4 1 A D Conversion Timing Diagram 4 8 Monitoring Conversion Status The A D conversion status can be monitored through the end of convert EOC signal This signal the inverse of the STATUS signal output by the A D converter is low when a conversion is in progress and goes high when the conversion is completed This low to high transition can be monitored through any one of three PPI digital I O lines PB7 or PC7 or through an interrupt line Reading the Converted Data The general algorithm for taking an A D reading is 1 Start a 12 bit conversion by writing to BA 8 out base _address 8 0 Note that the value you send is not important The act of writing to this 1 O location is the key to starting a conversion 2 Delay at least 20 microseconds monitor PPI port A or C bit 7 fora transition or use an interrupt to ensure that the conversion is compieted 3 Read the least significant byte of the converted data from BA 9 lsb inp base_address 9 4 Read the most significant byte of the converted data from BA 8 msb inp base_address 8 5 Combine them into the 12 bit result by shifting the four LSB bits to the right The MSB must also be weighted correctly result msb 16 1sb 16 For a 12 bit conversion the A D data read is le
20. Word LSB of count MSB of count LSB of count MSB of count LSB of count MSB of count Counter 2 Counter 1 Counter 0 Counter 2 Counter 2 Counter 1 Counter 1 Counter 0 Counter 0 o0o 00 gt 0000 au 3 us Y o Control Word Control Word LSB of count Control Word LSB of count MSB of count LSB of count MSB of count MSB of count Counter 1 Counter 0 Counter 1 Counter 2 Counter 0 Counter 1 Counter 2 Counter 0 Counter 2 2000 02 0000 In all four examples all counters are programmed to read write two byte counts These are only four of many possibie programming sequences Figure 8 A Few Possible Programming Sequences Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82054 There are three possible methods for reading the counters a simple read operation the Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result intel 82 54 COUNTER LATCH COMMAND The second m
21. at a Time XTAL This input to all three timer counter circuits is from the 5 MHz crystal oscillator labeled Y 1 located in the upper left corner of the board Installing a jumper horizontally across the pair of pins connects the 5 MHz clock to the timer counter clock input If required by your application the XTAL frequency can be changed by installing a different crystal oscillator at Y 1 Note however that the maximum frequency at which the timer counters will operate is 8 MHz EXCKx This input allows an external clock to control the timing of the corresponding timer counter This pin can be horizontally jumpered to the CKx input on the right side of the connector in place of the XTAL source The signals are brought onto the board through external I O connector P7 see Appendix B CKx This input connects the output of one timer counter to the clock input of the next timer counter CKx is provided for timer counters 1 and 2 only and is connected to the output of the previous timer counter timer counter 0 or 1 by placing a jumper horizontally between the pins These connections are used to cascade the timer counters for longer time delays than are supported by a single 16 bit timer counter Gate Inputs Connect Only ONE at a Time 45V This input if connected to the GTx input by installing a jumper horizontally across the two pins places the timer counter in an enabled state at all times EXGTx This i
22. control word to the 82 55 The contro word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82 55 Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Contro Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports B and All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This p
23. done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ1 is used by the key board IRQ3 by COM2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the AD1000 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you will need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOT command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit O is for IRQO bit 1 is for IRQI and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H mas mos Ras mas moz mon moo 0 Porz For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an inter
24. few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines 4 11 which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating po
25. from timer counter 2 in the 8254 Make certain that there are no other jumpers on this connector and that there are no jumpers installed across the pins on P2 or P4 the factory setting for all interrupt jumpers is disabled as shown in Chapter 1 Also make sure that the IRQ channel you have selected is not used by any other device in your system Figure E 3 shows you how to configure P3 for IRQ channel 4 P3 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 OUTO OUT1 OUT2 Fig E 3 8254 Timer Counter Output interrupt Jumpers for ATLANTIS P3 P8 End of Convert Monitor The end of convert signal is monitored through PB7 when using ATLANTIS The factory setting of this connector is PB7 the middle set of pins on P8 as shown in Figure E 4 If the factory setting has been changed place the jumper across the pins for PB7 EOC Fig E 4 End of Convert Jumper P8 E 6 F 1 APPENDIX F WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants hardware and software products manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective producis or parts at no additional charge provided that the product is returned shipping prep
26. labeled XTAL EXCKO 5V CKOTO this signal has a bar over top of the signal name on the board because it is the inverse of the CKOTO signal and the output which cascades timer counter 0 to timer counter 1 The groups of signals for timer counters 1 and 2 are identical to timer counter 0 except that OUT2 can be connected to EXTINT an external signal or RESET the computer s reset signal The following paragraphs describe these signals An x is used in place of O 1 or 2 in the signal names whenever the application can be applied to any or all of the three timer counters 1000 VO CONNECTOR P7 1 8254 PIT l I T 5 MHz 16 I PIN 29 COUNTER EXTCLKO 0 S OL sv 1 PIN 30 PIN 31 6 CLKOUTO CLKOUTO 5 MHz OT xTAL TIMER PIN 32 COUNTER A EXTCLK1 1 om 5V PIN 33 EXTGATE1 CLKOUT1 CLKOUT1 CLKOUTI 5 MHz TIMER 35 N CLKOUT2 CLKOUT2 EXTINT RESET me e Den eus I 4 EXTERNAL INTERRUPT FROM 10 PC BUS Sv Fig 1 6 8254 and P5 Circuitry Counter Inputs Connect Only ONE
27. 0 OUTPUT 80 PORT STROBED OUTPUT PORT B STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions e Used in Group A only One 8 bit bi directional bus port Port A and a 5 bit control port Port C Both inputs and outputs are latched e The 5 bit control port Port C is used tor control and status for the 8 bit bi directional bus port Port A Bidirectional Bus 1 0 Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit set reset of PCg Input Ope
28. 1583 CWz12 158 3 CW 12 1 8 2 FFI 0 re 4 IS 231244 9 Figure 16 Mode 1 3 92 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also CW 14 15853 1 5 CWz 4 15B 3 14 158 4 231244 10 A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 82054 Writing a new count while counting does not affect the current counting sequence If
29. 2 highest priority channel through lowest priority channel The jumper is stored vertically across the top two leftmost pins as shown in Figure 1 2a By placing this jumper horizontally across the pins of one of the IRQ channels the EOC signal can be used to generate interrupts Figure 1 2b shows the EOC connected to IRQ3 The EOC goes high when a conversion is completed therefore an inter rupt will occur when the EOC line transitions from low converting to high not converting P2 1 P2 IRQ7 IRQ7 IRQ6 IRQ6 o IRQS IRQ5 IRQ4 194 IRQ3 IRQ3 IRQ2 IRQ2 Fig 1 2a Factory Fig 1 2b EOC setting disabled connected to IRQ3 Fig 1 2 End of Convert Interrupt Channel Selection Jumper P2 P3 8254 Timer Counter Output Interrupt Factory Setting Disabled Header connector P3 shown in Figure 1 3 is used to jumper one of the three 8254 timer counter outputs OUTO OUT1 or OUT to one of the computer s interrupt channels IRQ2 highest priority channel through IRQ7 lowest priority channel The top six pairs of pins on this header connector are used to select the IRQ channel and the bottom three pairs of pins are used to select the desired 8254 output The two jumpers stored vertically across the top four pairs of pins as shown in Figure 1 3a must be installed to connect an 8254 output to an interrupt channel Place one jumper horizontally across the pins of the selected timer counter output one of the bott
30. AD1000 User s Manual FU 1509001 and AS9100 Certified Real Time Devices Inc Accessing the Analog World AD1000 us User s Manual IED REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 Copyright 1993 by Real Time Devices Inc All rights reserved Printed in U S A Rev C 9302 TABLE OF CONTENTS INTRODUCTION PRRRRRRRRRRE 1 Analog to Digital Conversion eese eerte entente 1 3 8254 Timer Co nter 1 3 Digital O A 1 3 What Comes With Your Board scccccsssssssssessssscscssesccsssscsccseceseecececessesssssscssescecseeseseetesesescecescsseenseasesasenessseeasaeses i 3 Board Accessories uceseesesesesesneossenenneornensnnentnennnunsanensnenenennsnenensnenesenneunnsnnsnsnentnesssnsnenserensorsssosnenennnnsnontersnsnensenensonsenese i 3 Application Software and Drivers uessssenenssesnsnssnsnensusensnensanenenenennssnsnsonnsnnsnensnsnenssnsnsnsnsnnensnensnsnsnsnssnsnsssnstsentaren 14 Hardware Accessories uuseseesansseneonsnnnennennnnnensnennnennsnsnensssnnentnsnnnensnnensnsssnnesssensnnssenenssnsnenssnenansnnssnnsansssnnnnsenesnsasnnne 14 Using This Man
31. AG 4 EXTGATEO EXTCLK1 CLKOUTVCLKOUTI EXTGATE2 CLKOUT2 CLKOUT2 DIGITAL GND EXTCLKO CLKOUTO CLKOUTO EXTGATE1 6363 EXTCLK2 G3 G9 12 VOLTS 0969 12 VOLTS 69 49 Fig 2 1 P7 I O Connector Pin Assignments 2 3 Connecting the Analog Inputs Connect the high side of each analog input to one of the analog input channels AIN1 through AIN8 and connect the low side to any one of the two ANALOG GND signals P4 1 or 7 Figure 2 2 shows how these connec tions are made NOTE It is good practice to connect all unused channels to ANALOG GND as shown with channel 8 in the diagram below Failure to do so may affect the accuracy of your conversion results 1000 1 0 CONNECTOR 7 YOU CONNECT THE GROUND SIGNALS TO ANY ANALOG GND PIN 1 OR 7 Fig 2 2 Analog Input Connection Connecting the Timer Counters and Digital I O For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is connected to any DIGITAL GND Running the RTDDIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use diagnostics program RTDDIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another devic
32. IMER m Compatible with all Intel and most Three independent 16 bit counters other microprocessors Low Power CHMOS High Speed Zero Wait State Icc 10 mA 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 m Completely TTL Compatible m Handles Inputs from DC to 8 MHz 10 MHz for 82C54 2 a 4 counter Modes Available in EXPRESS m Binary OF SSU Couns Standard Temperature Range Status Read Back Command Extended Temperature Range _ m Available in 24 DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82 54 is fabricated on Intel s advanced CHMOS technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82054 is available in 24 DIP and 28 pin plastic leaded chip carrier PLCC packages DATA BUS BUFFER TUTOoUuUUuUnD OUTO GATEO GND NC OUTIGATE1CLK1 231244 3 PLASTIC LEADED CHIP
33. R 4 15 Flow Diagrams 31 1 gt 4 16 Single Convert Flow Diagram Figure 4 3 esee entere eene nette teen nen tn enenatis senta satanas 4 16 CHAPTER 5 CALIBRATION ssssssssosessesseseonssnsnnsansnsssennesssnnsunssesensuennene PR A Required Equipment 5 3 Calibration O Is 5 4 APPENDIX A AD1000 SPECIFICATIONS s cssesusonssunsossnnssnnessssnesunennessssnussnensnesnnsnensnesnssnsnennenne 1 APPENDIX CONNECTOR PIN ASSIGNMENTS ssnecossosssnssnnsnnennesnnesosensssnusnnnsonsonsennennen nu Bol APPENDIX COMPONENT DATA SHEETS sscsssussnssonsonenussnessnsnossnsnnsnnnnsssnunsnnnnnesnensnnnnene C 1 APPENDIX D CONFIGURING THE AD1000 FOR 8 D 1 APPENDIX E CONFIGURING THE AD1000 FOR ATLANTIS E 1 APPENDIX WARRANTY scsosssesssssnsenssnsusssssssonsnsssnennesnnssnesnussstnnssnsnnnsnonssnsnsesnsensessnsenn LIST OF ILLUSTRATIONS 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 2 1 2 2 3 1 4 1 4 3 5 1 Board Layout Showing Factory Configured Settings eere eren tenente tnnt 1 3 End of Convert Interrupt Channel Selection Jumper 14 8254 Timer Counter Output Interrupt Jumpers
34. Source 5 to 5 volts Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment While not required the RTDDIAG diagnostics program included with example software is helpful when performing calibrations Figure 5 1 shows the board layout The trimpots used for calibration are located in the upper center area of the board py TA 0000 0000 7555 Ed z oo 18 AD1000 E DATA ACQUISITION amp CONTROLSYSTEM 229 Ors 000000000 009090099909 x EPA fuum pus Accessing he Analog Word 000000000000 0006000000000 D 00000000000000 s 0000000000000 0000500 _00000000000000000000 Druso 6090989 b BERR EZR base D O O O O O O OJ 00000000 00000000 00000000 De Wetec 7 00000000 V 50055000 050509 C y Am Real Time Devices Inc State College PA 16804 USA Fig 5 1 Board Layout A D Calibration Two adjustments are made to calibrate the A D converter One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR1 is used to make the offset adjustment and trimpot TR2 is used for gain adjustment Adjustments are made using 12 bit resolution Table 5 1 shows the ideal input voltage range for each bit
35. TY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE F 3 End of Convert PPI Monitor Bit Selected A D End of Convert PPI Bit PB7 or
36. Vector The next step after writing ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at I O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the AD1000 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H 4 12 With the start
37. a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle in mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK Cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue
38. aid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILI
39. al count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high unti N 1 pulses after the new count of N is written If an initial count is written while GATE 0 it will Still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 18824 WR FF FE 10 1883 Bern cT 1 amp 10 18B 3 88 2 rest 231244 8 NOTE The Following Conventions To All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte 188 only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 hex is written to the counter 4 LSB st
40. ands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 82 54 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT new count is written to the Counter during one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires 12
41. ask Register IMR uuessesnssssnensnsnsenansssssnnsenensnsnensnensnsnssesentnsnsnenennssnsnnssnssassnssasnsesnsnsnsossensnsnen 4 10 End of Interrupt EOI Command 4 10 What Exactly Happens When an Interrupt Occurs 2202022 4 4 8 4 4 10 Using Interrupts in Your Programs 3 eese eese 4 11 Special Considerations for AD1000 Interrupt Programming 4 11 Writing an Interrupt Service Routine ISR sssssssscsssssssscssesssescecssssecssssssesesssssssesssusssessnsesessnseesssnssssnsennessss 4 11 Saving the Startup Interrupt Mask Register IMR and Interrupt 4 12 Restoring the Startup IMR and Interrupt Vector csssssssssssscssssseeeeeesseseseseresssacscessssncessssessaseseneecassrensneees 4 13 Common Interrupt Mistakes sesesescsecccesesecesssvssesessssssssssscsuseseseseesaceesceeacereceserstssassonensaeacseseaeoreeses 4 13 4 13 Digital I O D 4 14 Example Programs and Flow Diagrams esee neret ennt nnne tnnt entem ente 4 15 and Pascal Programs PRRRRRRRRRRRRRR 4 15 IO ERRE ERRO
42. ation depending on your application For example if you want to monitor the end of convert signal through Port B bit 7 you must set up Port B as a Mode 0 input This is done by writing the following control word to BA 15 X don t care 1 X x x x 0 1 x os pr If we replace the Xs don t care with zeros the command in BASIC is OUT BA 15 130 The 8254 timer counter must be programmed to define the desired mode of operation if you are using any of the OUT signals as an interrupt or when using 8254 for timing or counting operations The 8254 is initialized by writing the control word at BA 19 Failure 10 initialize 8254 when an output is connected to an interrupt channel may cause erratic system operation Selecting a Channel To select a conversion channel you must simply write to the address port of the desired channel as shown in Table 4 1 The data written is irrelevant Note that when the system is first powered up all channels are disabled After you program a channel it remains active until you select another channel Starting an A D Conversion A D conversions are started by writing a START CONVERT command to the appropriate I O port For 12 bit conversions Port BA 8 is used For 8 bit conversions Port BA 9 is used ASTART CONVERT command must be written for each A D conversion The data written is irrelevant Figure 4 1 shows the timing diagram for A D conversions
43. ched for Counter 0 Status latched for Counter 1 Figure 13 Read Back Command Example 3 90 82054 CS RD WRIA A 80 8 0 0 0 WiteitoCounterO 1 Write into Counter 1 Write into Counter2 o 0 1 1 witeControlWord__ 0 0 1 Readtrom _ 0 Read 0 1 0 ReadfromCounter2 o o 1 t no Operation 3 State 1 x x x x No Operation 3 State Lo 1 1 x x No Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The tollowing are defined for use in describing the operation of the 82C54 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Contro Word and initial count are written to a Counter the initi
44. combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the 2 PC4 and PCE bit positions as illustrated by Figure 18 Through a Write Port C command only the Port pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to GROUP A ONLY MODE 0 OR MODE 1 ONLY gt lt gt gt gt lt gt gt gt gt change an interrupt enable flag the Port C Bit command must be used With a Set Reset Port C Bit command any Port C line programmed as an output including INTR IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset Port Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Gro
45. connected Connects one of the 8254 timer counter outputs to an interrupt channel Disabled not connected Connects an external interrupt or an interrupt P4 generated by the PPI INTRA to an interrupt channel Disabled not connected All timer counters are cascaded Configures the 8254 timer counters see diagram for P5 Sets the base address 300 hex 768 decimal Connects the A D end of convert signal so that it can be monitored through the PPI at PA7 PB7 or PC7 Monitored through PB7 8255 Port B pads available for soldering connections pr gr B8 0000 0000 9 5 0 0000 n Or 10 DATA ACQUISITION Dooo coNTroLsrstEM tie a 000000000 Es i 000000000 0000000 F nf 0550000 _00000000000000000000 13 uU 0000000 0 0 a 5 es C2 B 00 PREE rs I O O O O O O wess 00000000 00000000 00000000 E ccc RAD 00000000 00000000 00000000 us us v cm 000000000000 GO0000000000 00000000000000 c2 Am Real Time Devices Inc State College PA 16804 USA mm Fig 1 1 Board Layout Showing Factory Configured Settings 1 3 P2 P3 and P4 Interrupts Header connectors P2 P3 and P4 let you connect var
46. des 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there 82C54 Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5t0 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V sections of this specification is not implied Ex Voltage on any Input GND 2Vto 6 5V posure to absolute maximum rating conditions for Voltage on any Output GND 0 5V to 0 5V extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C Vec 5V 10 GND 0V 40 C to 85 for Extended Temperature symbol Parameter mm Max Units TestConditon Ev inputtowvottage os os vw ____________ InputHighVotage 20 veros v ___________ Vor OutputtowVoltage 04 V a Voc 0 4 V 100 nA tu Input Load Current 20 pA Vin Voctoov Output Float Leakage Current T zo Vout Vcc to 0 0V liL Current mA 8MHz 82054 Freg 10MHz82C54 2
47. e CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the features of the AD1000 hardware The major circuits are the A D converter the 8254 timer counters and the 8255 programmable peripheral interface which provides the digital 1 O lines Board interrupts are also described in this chapter 3 1 The AD1000 board has three major circuits the A D converter the timer counters and the programmable peripheral interface PPI which provides the digital I O lines Figure 3 1 shows the block diagram of the board This chapter describes hardware which makes up the major circuits It also discusses interrupts DATA ADDRESS ADDRESS DECODE CONTROL SELECT e 8 ANALOG INPUTS 5 DIGITAL UO CONNECTOR TIMER ER COUNTER VO SELECT Fig 3 1 AD1000 Block Diagram A D Conversion Circuitry The AD1000 board performs analog to digital conversions on up to eight analog input channels The following paragraphs describe the A D circuitry Analog Inputs Eight single ended analog input channels are available on the AD1000 board The analog input range is 5 to 5 volts with 35 Vdc overvoltage protection The channels are connected to a sample and hold amplifier through an eight channel multiplexer The active channel is selected through software by writing to the desired channels I O port as described in Chapter 4 The S H amplifier captures and holds
48. e interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 One of the most common mistakes when writing an ISR is forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR Timer Counters The 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts Figure 4 2 shows the timer counter circuitry Each timer counter has two inputs CK in and GT in and one output timer counter OUT They can be pro grammed as binary or BCD down counters by writing the appropriate data to the command word as described in the 1 O map section at the beginning of this chapter One of two clock sources the on board 5 MHz crystal or the external clock can be jumpered as the clock input to each timer counter Or the output from the previous timer counter can be used to clock the next timer counter to cascade multiple counters Two gate sources are available for enabling the timer counters a 5 volt source and an external gate source The outputs are available at the P7 1 0 connector and interrupt header connector P3 The timer counters can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While th
49. e timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely 1000 WO CONNECTOR P7 EXTCLK1 PIN 33 EXTGATE1 CLKOUT2 CLKOUT2 EXTINT RESET TO P4 EXTERNAL INTERRUPT FROM RESET PC BUS i Las Fig 4 2 8254 Timer Counter Circuitry Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is i
50. een Tc min and Tw max will result in a latched count vallue which is one least significant bit EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature CLK Delay for Loading Gate Delay for Sampling intel 82054 WAVEFORMS WRITE DATA BUS 231244 14 DATA BUS em 231244 15 RECOVERY 231244 16 3 98 82654 CLOCK AND QUTPUTO 231244 17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 0 8 231244 18 A C Testing Inputs are driven at 2 4V for a logic 1 and 0 45V tor a logic 0 Timing measurements are made 2 0V for a logic 1 and 0 8V for a logic 0 231244 19 C 150 pF includes jig capacitance 3 99 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Compatible with all Intel and Most m Control Word Read Back Capability Other Microprocessors m Direct Bit Set Reset Capability m High Speed Zero Wait State ES Operation with 8 MHz 8086 88 and oe Capability Available i Pin and 44 PLCC 24 Programmable 1 0 Pins 1 4 us m Available in m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A
51. er Full F F The output will MODE 1 PORT A go low to indicate that the CPU has written data CONTROL WORD out to the specified port The OBF F F will be set b D 0 0 0 D 0 D the rising edge of the WR input and reset by 10 es INPUT Input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU MODE 1 PORT INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU xe INTR is set when ACK is a one OBF is a one Sisa Hi ak uc and INTE is a one It is reset by the falling edge of DDI DG WR INTE A Controlled by bit set reset of PCg INTE B Controlled by bit set reset of PCo ee Figure 10 MODE 1 Output 231256 16 Figure 11 MODE 1 Strobed Output 3 135 82 55 Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed 1 O applications CONTROL WORD D D D D D 0 D PC INPUT 0 OUTPUT Le WP eo PORT ISTROBED INPUT PORT B ISTROBED OUTPUT CONTROL WORD D Dg D D D Dz D D BOO C 5 INPUT
52. er and ail ports are set to the input mode WRITE CONTROL This input is low during CPU write operations VO PORT A PINS 4 7 Upper nibble of an 8 bit data Output latch buffer and an 8 bit data input latch No Connect S O 3 125 intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose 1 component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no externai logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a
53. ese programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming 4 1 Defining the VO Map The I O map for the AD1000 is shown in Table 4 1 As shown the board occupies 20 I O port locations The base address designated as BA can be selected by changing the jumper on header connector P6 as described in Chapter 1 Board Settings The following sections describe the register contents of each address used in the map Table 4 1 AD1000 Address Register Description Read Function Decimal Channel 1 AIN1 Select Activate channel 1 BA 0 Channel 2 AIN2 Select BA 1 Channel 3 AIN3 Select BA 2 Channel 4 AIN4 Select BA 3 Channel 5 AIN5 Select 4 Channel 6 AIN6 Select 5 BA 6 Channel 8 AIN8 Select BA 7 Start 12 Bit Conversion Read A D converted data MSB Start 12 bit A D conversion 8 Bi i Read A D converted data LSB Start 8 bit A D conversion BA 9 gt w 3 5 o gt 2 o 2 2 DIDID NIN IN IN lo lo 5 ajala ljla l I 21815 la gt o alalialsle lo 212 o S15 5 3 21213 212 lt lol o Lx gt 17 5 9 lt 145 3 Is Is Is lt 1 o o a ia o m
54. ethod uses the Counter Latch Com mand Like a Control Word this command is written to the Control Word Register which is selected when A4 Ao 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word Ben Ds 04 02 Dy Do De x Dx 15 SC1 SCO specify counter to be latched SC1 SCO Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the cou
55. from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts 3 93 OUT will be high for N 1 2 counts and low for N 1 2 counts 158 4 CW t6 LSB 5 DOE 139 4 sled NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE
56. ft justified in a 16 bit word with the least significant four bits equal to zero Because of this the two bytes of A D data read must be scaled to obtain a valid A D reading Once it is calculated the reading can be correlated to a voltage value by subtracting 2048 to scale it and then multiplying by 2 4414 millivolts For example if the A D reading is 1024 the analog input voltage is calculated as follows 1024 2048 bits 2 4414 mV bit 2 49999 volts Note that 8 bit A D conversions can also be performed by writing to I O location BA 9 to start a conversion While an 8 bit conversion has a lower resolution it is performed much more rapidly in about 13 microseconds A 12 bit conversion takes about 20 microseconds The key digital codes and their input voltage values are given for 12 bit and 8 bit conversions in the following two tables 12 bit A D Bipolar Code Table Input Voltage Output Code 4 9976 volts MSB 1111 1111 1111 LSB 2 500 volts 1100 0000 0000 8 bit A D Bipolar Code Table Input Voltage 44 9609 volts 2 500 volts 2 500 volts 5 000 volts 2 500 volts 5 000 volts Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Inter
57. g from a different channel Select Channel Start Conversion BA 8 for 12 bit BA 9 for 8 bit Change Channel Check End of Convert EOC 1 ReadLSB BA 9 Contains bits 0 3 of 12 bit conversion Yes Read 5 8 Contains bits 4 11 of 12 bit conversion bits 0 7 of 8 bit conversion Stop Program Fig 4 3 Single Conversion Flow Diagram 4 16 5 CALIBRATION This chapter tells you how to calibrate the AD1000 using the RTDDIAG calibration program included in the example software package and the two trimpots TR1 and TR2 on the board These trimpots calibrate the A D converter gain and offset 5 1 This chapter tells you how to calibrate the A D converter gain and offset The offset and full scale performance of the board s A D converter is factory calibrated Any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjusts as necessary Using the RTDDIAG diagnostics program is a convenient way to monitor conversions while you calibrate the board Calibration is done with the board installed in your PC You can access the trimpots with the computer s cover removed Power up computer and let the board circuitry stabilize for 15 minutes before you start calibrating Required Equipment The following equipment is required for calibration Precision Voltage
58. general purpose programmable 1 device which is designed for use with all Intel and most other microprocessors It provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255 5 In MODE O each group of 12 1 O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control MODE 2 is a strobed bi directional bus configuration The 82C554 is fabricated on Intel s advanced CHMOS technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82 55 is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages v 231256 1 Figure 1 82 55 Diagram 1312323823220 Yo Y 113113123 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 82C55A PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch SiS j N lo lt cc 0 2 oO m N Mm 4 4 20 22 PORT PINS 0 7 An 8 bit data outpu
59. h the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked and enjoy the benefits of properly executed interrupts Special Considerations for AD1000 Interrupt Programming Two special considerations must be taken into account when using interrupts on the AD1000 First you must be very careful to make sure that the 8259 programmable interrupt controller is properly configured to ignore interrupts on the selected channel immediately after power up This is necessary because the 8254 timer counter must first be initialized to define the desired mode s of operation Before the 8254 is initialized its modes counts and outputs are all undefined If system interrupts are not disabled the counter outputs may cause erratic behavior To use the 8255 PPI s PC3 interrupt you must enable the interrupt by writing a 1 to the INTE mask bit in the PPI control word This operation is fully described in the 8255 data sheet included in Appendix C Note that the INTE mask is always disabled at power up or reset and whenever the PPI modes are changed Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each
60. ice operation a simple logical I O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port Aor B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU EL Y 4 The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C BIT SELECT oj 1121374151617 1011101101 r o 1 allow a specific 1 device to interrupt the CPU with out affecting any other device in the interrupt struc ture BIT SET RESET FLAG RE INTE flip flop definition This function allows the Programmer to disallow or 231256 7 BIT SET INTE is SET Interrup
61. in CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis Se DATA BUS vo 1 PB PB CONTROL OR CONTROL PA PA OR UO vo BIDIRECTIONAL PA 7 O 757 231256 5 Figure 5 Basic Mode Definitions and Bus interface CONTROL WORD PORT C LOWER 1 INPUT 0 OUTPUT PORT 8 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE O 1 MODE 1 PORT C UPPER 1 INPUT 0 OUTPUT MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete dev
62. int emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt
63. ious on board and external signals to the computer s interrupt channels Interrupts can be generated by the A D converter s end of convert signal by any one of the three timer counter outputs and by the 8255 programmable peripheral interface or from an external interrupt source brought onto the board through the I O connector Before trying to use interrupts you must be familiar with the procedure for initializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines These procedures are beyond the scope of this manual but must be understood to effectively use interrupts in your computer system Chapter 4 provides an overview on using interrupts Also be careful to avoid contention with other devices that may use interrupts in your computer when you choose your interrupt channel Each interrupt source activated must be assigned to an unused interrupt channel Use the table inside the back cover of this manual to record the interrupt channel you have selected It is also very important to note that the board interrupt source is a TTL totem pole push pull type output it is not open collector Therefore do not connect this interrupt to any other interrupt output P2 A D End of Convert EOC Interrupt Factory Setting Disabled Header connector P2 shown in Figure 1 2 lets you connect the A D converter s end of convert EOC signal to any of the computer s interrupt channels IRQ
64. lect another channel or power down BA 6 Channel 7 AIN7 Select Write Only Writing to this address selects analog input channel 7 AIN7 The data written is irrelevant After you select channel 7 it remains active until you select another channel or power down BA 7 Channel 8 AIN8 Select Write Only Writing to this address selects analog input channel 8 AIN8 The data written is irrelevant After you select channel 8 it remains active until you select another channel or power down BA 8 Start 12 Bit Conversion Read MSB Data Read Write Writing to this address starts a 12 bit A D conversion the data written is irrelevant A read provides the MSB 8 most significant bits of the 12 bit A D conversion as defined below The converted data is left justified When you are performing 8 bit conversions only the MSB must be read 12 Bit Bit11 BitiO Bit9 Bit7 Bit6 Bits Bit 4 8 Bit Bit 7 Bit6 Bit5 Bt4 Bits Bit2 Bit 0 BA 9 Start 8 Bit Conversion Read LSB Data Read Write Writing to this address starts an 8 bit A D conversion the data written is irrelevant A read provides the LSB 4 least significant bits of the 12 bit A D conversion as defined below The converted data is left justified ee e e Bit 3 Bit 2 Bit 1 Bit 0 BA 10 Reserved BA 11 Reserved BA 12 PPI Port A Digital VO Read Write Transfers the 8 bit Port A digital input and digital output data between the board and an exte
65. lled on P4 P3 P2 IRQ7 IRQ7 IRQ6 IRQ6 IRQ5 9 IRQS 104 1804 IRQ3 IRQ3 IRQ2 IRQ2 OUTO OUT1 OUT2 Fig D 3 End of Convert Interrupt amp Timer Counter Out Jumpers P2 amp P3 P8 End of Convert Monitor When running SIGNAL MATH place a jumper between EOC and PB7 as shown in Figure D 4 EOC A B Fig D 4 End of Convert Jumper P8 D 5 Running ADAINST After the jumpers are set and the AD1000 board is installed in the computer you are ready to configure SIGNAL MATH so that it is compatible with your board s settings This is done by running ADAINST driver installation program After running program open AD1000 EXE from Open a File menu You will see a screen similar to screen shown in Figure D 5 below The factory default settings are shown in the illustration Your settings may or may not match the default settings depending on whether you have made changes to these settings before Base Address The board s base address setting is entered in the upper right block as shown in the diagram The factory setting for all Real Time Devices boards is 300 hex 768 decimal The base address can be entered as a decimal or hexadecimal value hex values must be preceded by a dollar sign for example 300 Refer to your board s manual if you need help in determining the correct value to enter EOC IT End of Convert Interrupt In this block enter the IRQ channel number which correspo
66. mmon to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Mo
67. n be selected using jumpers on header connector P5 see Chapter 1 The timer counters can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six program mable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Digital Programmable Peripheral Interface The 8255 programmable peripheral interface PPI is used for digital I O functions This high performance TTL CMOS compatible chip has 24 digital I O lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines Sixteen lines Port A Port C Lower and Port C Upper are brought out to the I O connector Port B s eight lines are available at the P9 pads on the board You can use these ports in one of these three PPI operating modes Mode 0 Basic input output Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A or Port B in conjunction with strobes or hand
68. nds to your jumper setting on P2 Timer IT Timer Counter Interrupt In this block enter the IRQ channel number which corresponds to your jumper setting on P3 LabTech SW IT Labtech Notebook Software Interrupt This sets the software interrupt address where Labtech Notebook s rtdLinx NB 1000 driver is installed The factory setting is 60 This setting can be ignored when running SIGNAL MATH A D Parameters Six A D board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity End of Convert Timer Counter Interrupt Channel Interrupt Channel Base Address Software Interrupt Address A D D A DMA Channel Channel Select Select External Gain External Gain amp Loss amp Loss A D Unipolar Bipolar Select D A Unipolar Bipolar Select Fig D 5 ADAINST EXE Screen D 6 Resolution and number of channels are fixed by the program for your board The DMA channel number block is not valid on the AD1000 and should be left blank The next two blocks gain and loss are provided so that you can make adjustments for external gain or loss If your input signal is externally attenuated then you can adjust for this by setting a value other than 1 for loss If you have an external gain factor then you can adjust for this condition Numbers must be entered as whole decimal values The factory default setting for gain and loss is 1 Since the input range f
69. nitially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again For more information about the 8254 see the data sheet included in Appendix C Digital VO The 24 digital I O lines in the 8255 can be used to transfer data between the computer and external devices Sixteen lines are available at the I O connector eight lines are available at the P9 on board pads For more information about the 8255 see the data sheet included in Appendix C Example Programs and Flow Diagrams Included with the AD1000 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C Pascal and BASIC Also included is an easy to use menu driven diagnostics program RTDDIAG which is especially helpful when you are first checking out your board after installation and when calibrating the board Chapter 5 Before using the software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your
70. nput can be horizontally jumpered to the GTx input on the right side of the connector to provide an external gate The EXGTx signals are brought onto the board through external I O connector P7 see Appendix B Counter Outputs Connect Only ONE at a Time CKOTx This output can be horizontally jumpered to the corresponding OUT pin on the right side of the connector so that the timer counter s output signal can be routed to external I O connector P7 see Appendix B The CKOTx signals are available at P7 CKOTx This output can be horizontally jumpered to the corresponding OUT pin on the right side of the connector to provide the inverse of the timer counter output signal to external I O connector P7 see Appendix B The CKOTx signals are available at P7 EXTINT and RESET timer counter 2 only These two pairs of pins at the bottom of the header let you connect an external interrupt signal to one of the PC s interrupt channels or bring the PC bus reset signal out to the external I O connector P7 Both signals are routed through the same P7 pin that carries the CKOT2 and CKOT2 signals 38 CKOT2 CKOT2 EXINT and RESET are all internally connected on header P5 Only one of these four pairs of pins can be jumpered at a time The jumpered signal is available at P7 38 For example when the external interrupt is connected to P7 38 the jumper is installed across the EXTINT pins on P5 see Figure 1 6 This route
71. nsonee 4 4 5 Channel 6 AIN6 Select Write Only ussesssscssnsnsusnsnsnensssnsnensnensnensnentnnsessssnnenensnsnensnenessnsnasssnne 4 4 BA 6 Channel 7 AIN7 Select Write 4 4 7 Channel 8 AIN8 Select Write Only ueessssesesensnsnsnonsnnsnensssenenennnensonnnnnnnsnsnissnsnenssosnsnsasnsnsnenssnsnsnse 44 BA 8 Start 12 Bit Conversion Read MSB Data Read Write 4 4 BA 9 Start 8 Bit Conversion Read LSB Data Read Write 4 4 BA 3 107 BERN in vie ET IR CUR Ue apu 4 4 11 Reserved A NN 4 4 12 PPI Port Digital I O Read Write uaeeesessesnsnenssnensorsenennnnsnsnnnnonsnnnnnnnnssnssenennsnnnnnonsasonssonsuonsnneen 4 4 BA 13 PPI Port B Digital I O Read Write 4 5 14 PPI Port C Digital Read Write nenssssssnsnsssnensnensnenenenenenenanentnnnnnnsssrennonnsnsnssenrosssnsunannn 4 5 BA 15 8255 PPI Control Word Write Only 202 4 5 BA 16 8254 Timer Counter 0 Read Write 41 1 1 encon etos ta reto ttt en tns senem 4 6 BA 17 8254 Timer Counter 1 Read Write curscessnnsersosnoneonssnnsnnsssnnsnnnnnssnnnnnsensessernnesnesnnensnannessnenrnsnronen seen 4 6
72. nstall the board 1 Turn OFF the power to your computer 2 Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this 3 Select any unused short or full size expansion slot and remove the slot bracket 4 Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag 5 Holding the board by its edges orient it so that its card edge bus connector lines up with the expansion slot connector in the bottom of the selected expansion slot 6 After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the board or to the computer 7 After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer External VO Connections Figure 2 1 shows the AD1000 s P7 I O connector pinout Refer to this diagram as you make your I O connec tions ANALOG GND AINS AING ANALOG GND AINI PAS DIGITAL GND AIN7 AINS DIGITAL GND P
73. nsunsnssnennnenenonsnunnnnnunnonsanssnnanssnnnanennen Available externally used as PC interrupts or cascaded to adjacent counter Counter gate External gate or always enabled Miscellaneous Inputs Outputs PC bus sourced 12 volts Digital ground Current Requirements ONO 68 mA TAA rfe 20 mA SA A ON 28 mA A 3 Connector 40 pin right angle shrouded header with ejector tabs Size Short slot 3 875 H x 5 40 W 99mm x 137mm B 1 APPENDIX B CONNECTOR PIN ASSIGNMENTS ANALOG GND 22 DIGITAL GND AiN8 3 4 ans 5 6 Ans ANALOG GND 7 8 AIN3 CO AIN2 14 DIGITAL GND 3 4 Pas PAS Q Pas 1709 Paz Par 4969 Pc GNG Pcs pcs 0362 6969 Pc 6269 Pco EXTCLKO G9 69 CLKOUTO CLKOUTO 61 62 EXTCLK1 63 63 CLKOUTI CLKOUTI EXTCLK2 65 69 EXTGATE2 12 VOLTS 6768 CLKOUT2 CLKOUT2 12 VOLTS DIGITAL GND AD1000 P7 Connector Mating Connector AD1000 P7 Connector Fujitsu FCN 705Q040 AU M FCN 707B040 AU B 3M 3417 7040 Robinson Nugent IDS C40PK C SR TG MIL C 83503 M83503 7 09 C 1 APPENDIX C COMPONENT DATA SHEETS Intel 82C54 Programmable Interval Timer Data Sheet Reprint intel 82C54 CHMOS PROGRAMMABLE INTERVAL T
74. nt at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the 82054 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Contro Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 A1 11 CS 0 Do T Eos stares or
75. nt atento attente stononeun 24 Connecting the Timer Counters and Digital I O eese erret tnt tenente 2 4 Running the RTDDIAG Diagnostics Program 24 CHAPTER 3 HARDWARE DESCRIPTION nc dE 3 1 A D Conversion Circuitry s eeeseeeeeeeee entente ttes te ton rare toten 3 3 Analog 0 0 3 3 Converter SERRE 3 3 Timer Counters RR 3 4 Digital I O Programmable Peripheral Interface 1 1 3 4 440 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING 2 2 4 1 Defining the YO Map 4 3 0 Channel 1 AIN1 Select Write Only 4 4 4 3 1 Channel 2 AIN2 Select Write Only 2 4 3 2 Channel 3 AIN3 Select Write Only eese esee tenete 4 3 3 Channel 4 AIN4 Select Write 4 4 BA 4 Channel 5 AINS Select Write Only susssssssssensuseseonsosssensosnsosnassnssnnsnsnsnnsnsonsssnsosssnsnsnssnsnsnsn
76. nt count 10 Counter2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 Read load LSB then MSB 101 Mode 5 hardware triggered strobe 4 6 Programming the AD1000 This section gives you some general information about programming and the AD1000 board and then walks you through the major AD1000 programming functions These descriptions will help you as you use the example programs included with the board and programming flow diagram at the end of this chapter All of the program descriptions in this section use decimal values unless otherwise specified The AD1000 is programmed by writing to and reading from the correct I O port locations on the board These ports were defined in the previous section Most high level languages such as BASIC Pascal and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to 1 0 ports using some popular programming languages Y Assembly mov dx Address mov dx Address in al dx mov al Data out dx al In addition to being able to read write the I O ports on the AD1000 you must be able to perform a variety of operations that you might not normally use in y
77. ntrol Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay Ag in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used D3 02 D Do rw Bco SC Select Counter Select Counter 0 Select Counter 1 Select Counter 2 Read Back Command See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations 1 Read Write least significant byte only 1 EN Read Write most significant byte only 1 Read Write least significant byte first then most significant byte NOTE Don t care bits X should be 0 to insure compatibility with future Intel products M MODE Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 82054 Write Operations The programming procedure for the 82054 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Coun
78. of timing and counting functions The clock gate and output pins for each of the three timer counters are available at the 1 O connector Digital O The AD1000 has 24 TTL CMOS compatible digital I O lines which can be directly interfaced with extemal devices or signals to sense switch closures trigger digital events or activate solid state relays The lines are pro vided by the on board 8255 programmable peripheral interface PPI chip Sixteen of the lines are brought out to the I O connector and eight are available at a set of on board pads What Comes With Your Board You receive the following items in your AD1000 package AD1000 interface board Software and diagnostics diskette with example programs in BASIC Turbo Pascal and Turbo C source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your AD1000 package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Application Software and Drivers Our custom application software packages provide excellent data acquisition and analysis support Use SIGNAL MATH for integra
79. om three pairs of pins Then place the second jumper across the pins of the selected interrupt channel one of the top six pairs of pins Figure 1 3b shows an example 1 4 P3 IRQ7 IRQ7 IRQ6 IRQ6 IRQS 1895 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 OUTO OUTO OUT1 OUT1 OUT2 OUT2 Fig 1 3a Factory Fig 1 3b OUT2 settings disabled connected to IRQ4 Fig 1 3 8254 Timer Counter Output Interrupt Jumpers P3 P4 EXTINT and PPI PC3 Interrupts Factory Setting Disabled Header connector P4 shown in Figure 1 4 lets you connect an external signal EXTINT or the 8255 PPI s PC3 INTRA signal to one of the computer s interrupt channels IRQ2 highest priority channel through IRQ7 lowest priority channel EXTINT is routed onto the board through external I O connector P7 PC3 is generated when the 8255 PPI is being operated in mode 1 or mode 2 as explained in the data sheet in Appendix C To connect one of these two signals to an interrupt channel the two stored jumpers shown in Figure 1 4a must be installed across the appropriate pairs of pins Place one jumper horizontally across the pins of the signal chosen and place the second jumper horizontally across the pins of the selected IRQ channel Figure 1 4b shows the PC3 connected to IRQ7 P4 P4 IRQ7 IRQ7 IRQ6 IRQ6 IRQ5 IRQS IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 PC3 PC3 EXTINT EXTINT Fig 1 4a Factory Fig 1 4b PC3 settings disabled connected to IRQ7 Fig 1
80. operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability OV TA 40 C to 85 C for Extended Temperture Test Conditions lt lt lt VouT 3 0V Ports Voc 5 5V Vin or GND Port Conditions Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High 3 141 intel 82C55A ee 25 C GND 0V ET MEC NN Input oF _ NOTE 5 Sampled not 100 tested Test Conditions Unmeasured pins returned to GND fc 1 MHz A C CHARACTERISTICS 0 to 70 C 5V 10 GND 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE w tea o ns mwn 1 m wo m w we Remo rs w Recover Tine between ROAR 200 m WRITE CYCLE Test Symbol Parameter ETE etn Conditions em an twa Address Hold Time After WR T See Pro m D ne two Data Hold Time After WA T 30 ns PortsA amp B 39 Ponc
81. or the AD1000 is 5 volts an X should be placed before Bipolar on the screen default setting D A Parameters These settings are not applicable to the AD1000 D 7 APPENDIX E CONFIGURING THE AD1000 FOR ATLANTIS If you have purchased ATLANTIS data acquisition and real time monitoring application software for your AD1000 please note that the ATLANTIS drivers for your board must be loaded from the driver disk into the same directory as the ATLANTIS EXE program When running the ATLANTIS data acquisition software you may need to change some of the AD1000 s on board jumpers from their current positions Before using ATLANTIS on the AD1000 board check the following jumpers P6 Base address 5 8254 timer counter I O configuration P3 Timer counter output interrupt P8 End of convert monitor Figure E 1 shows the board layout 000000000000 0000000 741504 0000000 00000000 5 7415138 Dooooooo gm Fig E 1 P6 Base Address 00000000000000 EOC Oja 0000000 Eset 12090996 e 0000000 us e 00000000 00000000 ve AM Real Time Devices Inc State College PA 16804 USA o 0000 0000 aooo 556 01000 DATA ACQUISITION 4 CONTROL SYSTEM 5 ES o 000000000 NM 000000000 ARA
82. ort can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 POWER SUPPLIES GND B OtRECTIONAL DATA BUS 82 55 Figure 3 82C55A Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions INTERNAL DATA IN INTERNAL DATA OUT INTERNAL DATA NOTE Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration 3 127 EXTERNAL PORT A PIN EXTERNAL PORT B C PIN 231256 4 intel 82C55A 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices
83. ot decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CW tA 58 3 0 he ELSE CWz A 15823 FRIO 5 rel 5 4 231244 13 pla paa Figure 20 Mode 5 82654 Signal Low Status Or Going Rising Modes Low Disables Enable counting counti 5 ng 1 Initiates after next clock counting 2 Resets output Enables counting 1 Disables counting Initiates 2 Sets output counting immediately high 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high Disables Enables counting counting Initiates counting Figure 21 Gate Pin Operations Summary NOTE O is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum Initial Counts 3 95 Operation Co
84. our programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB WES RUF CROCO PU MOD DIV AND b b AND Bone BASIC MOD backslash AND a bMODc a b c a bANDc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the AD1000 Now that you know some of the language basics we are ready to look at the programming steps for the AD1000 board functions A D Conversions The following paragraphs walk you through the programming steps for performing A D conversions You can follow these steps on the flow diagram at the end of this chapter and in our example programs included with the board In this discussion BA refers to the base address Initializing the AD1000 Before operating the AD1000 you may have to initialize the 8255 PPI and 8254 timer counter The PPI must be programmed so that the digital I O lines are set up as inputs or outputs Mode 0 1 or 2 oper
85. put Mode 1 Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 2 3 140 intel 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 to 150 C Supply Voltage 0 5to 8 0V Operating Voltage 4Vto 7V Voltage on any Input 2V to 6 5V Voltage on any Output GND 0 5V to 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS 0 C to 70 C 5V 10 GND Symbol Parameter ru Input High Voltage Input Leakage Current IDAR Darlington Drive Current PHH Port Hold High Leakage Current Voc Supply Current Standby NOTES 1 Pins Ay Ag CS WA RD Reset 2 Data Bus Ports B C 3 Outputs open 4 Limit output current to 4 0 mA Vu Input Low Vottage cos n F o ov High Voltage 3 0 lon 2 5 mA Vcc 0 4 100 pA Vin Vcc to 0V Note 1 loFL Output Float Leakage Current t10 pA Vin to OV Note 2 Port Hold Low Leakage Current 300 Vout 1 0V Port A only Port Hold Low Overdrive Current Vout 0 8V loc Voc Supply Current TR Note 3 Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional
86. rations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset ot PC4 3 136 intel 82C55A CONTROL WORD 5 5 D O 0 D D PL DDO 1 INPUT 0 OUTPUT GROUP B MODE 0 MODE 0 1 gt MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 Y y PERIPHERAL us PERIPHERAL 620564 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before and STB occurs before RD is permissible IBF e MASK STB RD MASK e WR 3 137 intel 82C55A MODE 2 AND MODE 0 OUTPUT MODE 2 AND MODE 0 INPUT CONTROL WORD D D D D Dy D3 D Do PD PDT Fel 1BF 1 INPUT 0 OUTPUT CONTROL WORD D D 0 D Dj D D D DS PCa INPUT 0 OUTPUT MODE 2 AND MODE 1 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD CONTROL WORD D D D D D D D D D Ds D Dy D D D IBF 231256 21 Figure 16 MODE 1 Combinations 3 138 82C55A Mode Definition Summary Special Mode Combination Considerations There are several
87. red unless the 82054 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ag 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Contro Word Register can only be written to status information is available with the Read Back Command PA gt 2 lt 2 z z Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82654 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synch
88. ree digital lines from the PPI through which to monitor the EOC Port A bit 7 Port B bit 7 PB7 and Port C bit 7 PC7 One of these three lines is selected by installing a jumper horizontally across the appropriate pair of pins The selected digital line must be configured as a Mode 0 input see Chapter 4 EOC A B 8 Fig 1 8 End of Convert Jumper P8 1 9 1 10 CHAPTER 2 BOARD INSTALLATION The AD1000 board is easy to install in your IBM PC XT AT or compatible computer It can be placed in any slot short or full size This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the RTDDIAG board diagnostics program included on your example software disk to verify that your board is working 2 2 Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check jumper settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To i
89. rnal device A read transfers data from the external device through P7 and into PPI Port A a write transfers the written data from Port A through P7 to an external device BA 13 PPI Port B Digital Read Write Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device to the on board pads at P9 and into PPI Port B a write transfers the written data from Port B through the on board pads at P9 to an external device BA 14 PPI Port C Digital VO Read Write Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device read transfers data from the external device through P7 and into PPI Port C a write transfers the written data from Port C through P7 to an external device BA 15 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the PPI configuration When you want to monitor the end of convert signal through P8 bit 7 of PPI Port A B or C the PPI must be programmed so that the port used is a Mode 0 input port Mode Set Flag Port C Lower 1 active 0 output Mode Select 1 input 00 mode 0 01 mode 1 Port B 10 2 0 output Lo 1 input Port A 0 output Mode Select 1 input 0 mode 0 1 mode 1
90. ronous down counter and OL are 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRm and CR for Count Register Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is 3 86 stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be toaded from the internal bus Both bytes are trans ferred to the CE simultaneously CR and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written in
91. rupt service routine is completed the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the AD 1000 the 4 10 interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer 1P and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often wort
92. rupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your AD1000 board can interrupt the processor when a variety of conditions are met such as conversion completed timer countdown finished and others By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is
93. s the EXTINT signal through P5 to header connector P4 where it can be jumpered to a PC interrupt channel P6 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the AD1000 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the AD1000 has a header connector P6 which lets you select any one of eight starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address These addresses are from left to right on P6 To change the base address setting remove the jumper from the fifth pair of pins 300 hex and using Figure 1 7 as a guide install it in the desired location Record the new base address setting on the table inside the back cover of this manual CQ 9 BASE P6 ADDRESS Fig 1 7 Base Address Jumper P6 P8 End of Convert Monitor Factory Setting 8255 PPI Port B Bit 7 The A D converter s end of convert EOC signal can be used to monitor the status of A D conversions Header connector P8 shown in Figure 1 8 lets you choose one of th
94. shaking signals Mode 2 Strobed bidirectional input output Lets you communicate bidirectionally with an external device through Port A Handshaking is similar to Mode 1 These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C Interrupts The AD1000 has four jumper selectable interrupt sources end of convert 8254 timer counter outputs PC3 INTRA from the 8255 PPI and an external interrupt brought onto the board through P7 The end of convert signal can be used to interrupt the computer when an A D conversion is completed The 8254 timer counter interrupts can be used to generate various end of count interrupts The 8255 PC3 interrupt can be generated when PPI Port A is operated in mode 1 or mode 2 as explained on the 8255 data sheet Appendix C The external interrupt can be used to generate interrupts at any desired interval We recommend that you have an understanding of how to use inter rupts in your system before you connect an interrupt to an IRQ channel Chapter 4 provides a more detailed discus sion about interrupts 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your AD1000 board It provides a complete description of the I O map a detailed description of programming operations and a flow diagram to aid you in programming The example programs provided on the disk in your board package are listed at the end of this chapter Th
95. t enable BIT RESET INTE is RESET Interrupt disable Figure 7 Bit Set Reset Format Note Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82C55A Operating Modes Mode 0 Basic Functional Definitions Mode 0 Basic Input Output This functional con NO Poit poris 05 figuration provides input and output Any port can be input or output tions for each of the three ports No handshaking e Outputs are latched is required data is simply written to or read from a e Inputs are not latched specified port P 16 different input Output configurations are pos sible in this Mode MODE 0 BASIC INPUT 231256 8 MODE 0 BASIC OUTPUT 231256 9 3 130 intel 82C55A MODE 0 Port Definition s h os o 00 Porra o o o o oureur oureur o GUTPUT o o 1 ourur 1 oureur meur o o ouu ourur 2 outor o o 1 t ovrur a meor eur o 1 o o ourur 4 ouor o 3 oureur input 8 oureur Lo 3 3 ooru meor 6 ouor o 3 3 ovreur weur 7 eur o o meur s ouor outor 31 e s outor meur 3 f o 1 o meur oureur
96. t latch buffer and B 24 28 bit data input buffer 18 25 27 34 37 40 41 44 1 12 23 34 READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82 55 to respond to RD and WR signals RD and WR are ignored otherwise ADDRESS These input signals in conjunction RD and WA control the selection of one of the three ports or the control word registers As AD WR CS input Operation Read o rora DataBus Poro Data us 1 1 fo 1 Conto word DataBus Output Operation Write 1 DaaBus Pona DatBu Pons DeaBu Porc Pats s DaaBu Conto Disable Function x x 1 1 o databus 3 State 11 13 15 PORTC PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and PORT C PINS 0 3 Lower nibble of Port C SYSTEM POWER 5V Power Supply DATA BUS Bi directional tri state data bus lines connected to System data bus RESET A high on this input clears the control regist
97. ted data acquisition and sophisticated digital signal processing and analysis or ATLANTIS for real time monitoring and data acquisition rtdLinx and rtdLinx NB drivers provide full featured high level interfaces between the AD1000 and custom or third party software including Labtech Notebook Note book XE and LT Control rtdLinx source code is available for a one time fee Our Pascal and C Programmer s Toolkit provides routines with documented source code for custom programming Hardware Accessories Hardware accessories for the AD1000 include the TB40 terminal board and XB40 prototype terminal board for prototype development and easy signal access EX XT and EX AT extender boards for simplified testing and debugging of prototype circuitry and the XP40 single wire flat ribbon cable for external interfacing The AD1000 can be interfaced to RTD s 50 pin channel expansion and signal conditioning boards by using a Discrete Wire Kit Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included
98. ter systems the 82C54 are is a general purpose multi timing element that can be treated as an array of I O ports in the system software Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller The 82C54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures the 82C54 to match his require ments and programs one of the counters for the de intel 82054 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to in terface the 82 54 to the system bus see Figure 3 a gt 2 lt 1 z w Wi z COUNTER 2 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from sys tem bus and generates control signals for the other functional blocks of the 82654 and Ay select one of the three counters or the Control Word Regis ter to be read from written into A low on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR igno
99. ters have separate addresses selected by the 1 Ag inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in b Control Word LSB of count MSB of count Control Word LSB of count MSB of count Control Word LSB of count MSB of count Counter O Counter 0 Counter O Counter 1 Counter 1 Counter 1 Counter 2 Counter 2 Counter 2 20000 gt 2 b Control Word Counter Word Control Word LSB of count LSB of count LSB of count MSB of count MSB of count MSB of count Counter 0 Counter 1 Counter 2 Counter 2 Counter 1 Counter 0 Counter 0 Counter 1 Counter 2 0000 D 2 NOTE struction sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting Counter s pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count Control Word Control Word Control
100. the input signal at a constant level while the conversion is performed ensuring that dynamic analog signals are accurately digitized This capacitive circuit quickly charges to a level corresponding to the input voltage being sampled and holds the charge for the duration of the conversion The AD1000 uses a 01 uF low dielectric capacitor with a maximum acquisition time of 20 microseconds A D Converter The industry standard HI574 A D converter performs conversions at a rate of up to 50 kHz or one conversion every 20 microseconds This conversion time is added to the S H amplifier s acquisition time of 20 microseconds to 3 3 give a board maximum throughput rate of 25 kHz The A D output is a 12 bit data word which is output in two 8 bit bytes Note that 8 bit conversions can be performed when speed is more critical than resolution Because the converted data is contained in a single 8 bit byte 8 bit conversions take about 13 microseconds increasing Ihe maximum board throughput to about 30 kHz Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions These timer counters can be cascaded or used individually for many applications including triggering an A D conversion at a specified time Each timer counter has two inputs CK in and GT in and one output timer counter OUT The sources or destinations of the timer counter I O ca
101. time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must write an end of interrupt EOI command to the 8259 interrupt controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a
102. to the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82 54 SYSTEM INTERFACE The 82054 is treated by the systems software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ag Ay connect to the Ag A address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems ADDRESS BUS 16 CONTROL BUS 55 COUNTER 0 COUNTER 1 T COUNTER 2 ae OUT GATE CLK OUT GATE CLK OUT GATE CLK 231244 7 Figure 6 82C54 System Interface 82 54 OPERATIONAL DESCRIPTION General After power up the state of the 82654 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format Ap 11 CS 0 RD 1 WR 0 De 05 D4 Programming the 82054 Counters are programmed by writing a Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when Ay Ag 11 The Co
103. tory setting of 300 hex 768 deci mal If you change this setting you must run the ADAINST program and reset the base address NOTE When using the ADAINST program you can enter the base address in decimal or hexadecimal notation When entering a hex value you must precede the number by a dollar sign for example 300 D 3 P5 8254 Timer Counter VO Configuration The 8254 must be configured with the jumpers placed between the pins as shown in Figure D 2 This is the factory setting Verify that each jumper is in the proper location Any remaining jumpers must be removed from the PS header connector P5 XTAL EXCKO 5V EXGTO CKOTO CKOTO CK1 XTAL EXCK1 5V EXGT1 CKOT1 XTAL EXCK2 5V EXGT2 CKOT2 CKOT2 EXTINT RESET CLKO le Sul OUTO OUT1 GT1 CLK2 GT2 OUT2 Fig D 2 8254 Timer Counter Jumpers P5 D 4 P2 P3 amp P4 Interrupts To select IRQ channels and interrupt sources for SIGNAL MATH you must install one jumper on P2 and two jumpers First install a jumper on the end of convert interrupt header P2 across the pins of your desired IRQ channel Then install a jumper on P3 OUT2 and a second jumper across the pair of P3 pins for the IRQ channel you select The IRQ selected on P3 must be different from the IRQ set on P2 Figure D 3 shows EOC jumpered to IRQ3 and OUT2 jumpered to IRQ4 Make sure that no jumpers are insta
104. tput via software possibly eliminating some hardware from a system Ds D4 D2 D D D Dg 0 NULL Je er D Out Pin is 1 Out Pin is O Null count 0 Count available for reading Ds Do Counter Programmed Mode See Figure 7 0 06 1 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command 07 06 05 04 02 Dy Do Description 1 Read back count and status of Counter 0 1 Read back status of Counter 1 11111 111 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 1 1 0 0 1 1 0 0 0 Read back count of Counter 2 Count latched for Counter 2 1 Read back count and status of Count latched for Counter 1 Counter 1 but not status 111 1 Read status of Counter 1 Command ignored status already latched for Counter 1 CAUSES Null count 1 THIS ACTION A Write to the control word 11 Write to the count register 12 New co
105. ual 1 1 0 006 0 01 0 000 10 4 When You Need 1 1 4 CHAPTER 1 BOARD SETTINGS 2 2ssscs0scosoonennenuesoesuennsenneonrssensnsssssnnennensssnnensennnnnenssnnsnneusessusne 1 1 Factory Configured Jumper Settings 1 3 P2 and P4 Interrupts RR 1 4 P2 A D End of Convert EOC Interrupt Factory Setting Disabled 42 01 0 00 04004 0 1404 1 1 4 8254 Timer Counter Output Interrupt Factory Setting Disabled 1 4 P4 EXTINT and PPI Interrupts Factory Setting Disabled eene 1 5 P5 8254 Timer Counter I O Header Connector Factory Settings As Shown in Figure 1 5 1 5 P6 Base Address Factory Setting 300 hex 768 decimal rere essere eret tenen entente ent nana 1 8 P8 End of Convert Monitor Factory Setting 8255 PPI Port B Bit 7 eene 1 9 CHAPTER 2 BOARD INSTALLATION ssssssnsonensonssnsnnsnusnsenenssonennsnensennennnsnennennennene 2 1 Board Installation RR anes 2 3 External YO Connections BER 2 3 Connecting the Analog Inputs eene eene entente ttes n tone tnte tente
106. unt is loaded into CE CR Null count 1 Null count 0 11 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 2 the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads al but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Count and status lat
107. up B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to d rectiy drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status In Mode 0 Port transfers data to or from pe ripheral device When the 82 55 is programmed to function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de vice Reading the contents of Port C allows the pro grammer to test or verify the status of each ripheral device and change the program flow ac cordingly There is no special instruction to read the status in formation from Port C A normal read operation of Port C is executed to perform this function Position Interrupt Enable INPUT CONFIGURATION 07 06 05 D4 D3 Da D4 Do GROUPA GROUP B EUTIN 06 2 74 D2 SANA EA A GROUP A GROUP B Figure 17a MODE 1 Status Word Format De Ds De D Dy Do par line I I E AS GROUP B GROUP A Defined Mode O or Mode 1 Selection Figure 17b MODE 2 Status Word Format Alternate Port C Pin Signal Mode INTE Output Mode 1 or STBg Input Mode 1 INTE A2 STB Input Mode 1 or Mode 2 1 Out
108. up IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for and so on If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to I O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardwar
109. weight Table 5 1 A D Converter Calibration Table Ideal Input Voltage 5V A D Bit Weight in millivolts 4095 Full Scale 4997 Use analog input channel 1 to calibrate the board Connect your precision voltage source to channel 1 positive side to P7 11 and ground to P7 1 or 7 Ground all other channels Set the voltage source to 4 99878 volts start a conversion and read the resulting data Adjust trimpot TR1 until it flickers between the values listed in the table below Next set the voltage to 4 99634 volts and repeat the procedure this time adjusting TR2 until the data flickers between the values in the table Data Values for Calibrating 5 to 5 Volt Range Offset TR1 Converter Gain TR2 Input Voltage 4 99878V Input Voltage 4 99634V 0000 0000 0000 1111 1111 1110 A D Converted Data 0000 0000 0001 1111 1111 1111 APPENDIX A AD1000 SPECIFICATIONS A 2 AD1000 Characteristics Typical 25 C Interface IBM PC XT AT compatible Jumper selectable base address I O mapped Jumper selectable interrupts Analog Input 8 single ended inputs Input impedance each gt 10 megohms Inp t range pe EE 5 volts Overvoltage protection 20 0 35 Vde SERICO 1 max a imme HI574 Successive approximation A AA A 12 bits guaranteed to 11 bits Linearity e 1 LSB typ Conversion m
110. with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem 1 4 CHAPTER 1 BOARD SETTINGS The AD1000 board has jumper settings you can change if necessary for your application The board is factory configured as listed on the table and shown in the diagram at the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer 1 1 1 2 Factory Configured Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers on the AD1000 board Figure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to setting of P6 base address header connector to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Function Controlled Factory Setting Connects the A D end of convert signal to an interrupt channel Disabled not

AD1000 User`s Manual - RTD Embedded Technologies, Inc.

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