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1. AV Virtex 4 FX 1152 Connector 8196 191 Riso 195 Rzi2 193 182 TRPPADA vos LARS SIK 51K S SIK BIK S BIK S 51K 51K AVCCAUXTX 105 Pete us AVCCAUXRXB 105 nee ser oo ores 15 MENDES I MXN 1 MOD DESEL 105 A4 XE REFCLK nm TX DIS mrs EPUM 5 RABANUS LAGE 22 sci 19 sou cose s us 105 mue 2 REFCLK 2 i ABs sco uon ads 10 MOD NR 13 XFP1 MOD NR VITXA 105 RX Los XFPI RX LOS x 105 DOWN DOWN TXPPADB 105 VEES E 17 25 18 ER ves 2 n vecs 8 VCCSI XFPT case VS oar e TEA olus poser T 2 RxDp CAGE NCC 25 150R R104 RXPPADB 105 xFPT RxDn CAGE voce 1508 RXNPADB 105 CAGE MGTCLK P 105 CAGE MGTCLK NOS 250202202522 GND aD 888858224 N29 1122000 RTERM 105 55555
2. DIMM place near 054 DDR Buffer R296 47 58 R297 47 5R C937 137 DDRB PLL CKOUTp DDRB PLL CKp 4 38 DORE PLL CKOUT DDHRE PLL CR ck Yo F370 ERI 5 ll 5 yon 375 C938 21 39 2598 Y 20 9 OE Yin oO 28 3 0 51 5 0 ii H VDDQ 5 0 als Nia SIS 88 Slal Ais Sle SIS ig VDDQ 2 2 54 ns 58 3225 28 15 32 V WA HA m Wh e zya vs Pago u gg 33 33 33 33 33 38 33 33 5 34 DDRB CK TEST 99 99 99 az gg ET VDDQ H 1 88 52 46200 co OO 5552 OR DNI DDRB PLL amp 25 25 24 88 go 88 C202 AVDD Hn SiS Se Sa 843 56 lal 470 210 943 207 208 c204 ves 2 70 za zt uF uF p tuF R79 R80 n VER EI 2825 hri 33 23d oR H2 DIMME CKO DIMMB eg DIMMB_CKno 9 T 7 19 DIMMB CK1 H DIMMB CK1 PLL Bypassed 10 yan DIMMB 0124 Virtex 4 LX 1518 1 16 va 7 FPGA B Clock yon Inputs 2 FBIN FBOUT U12 5 4 LX 1513 25 55 22 0 0877 T Www o DES R90 94 22 1008 44
3. 122 1 1 WHATIS THE REFERENCE DESIGN 122 2 REFERENCE DESIGN MEMORY MAP 2 1 USING THE REFERENCE DESIGN reet eere ra eee e e EXE dene ke in ee e aen ede 126 2 1 1 Buili In RocketlO 127 3 MEMORY MAPPED DATA FLOWN e eeeeeee eren eese sensns enean senec ERROR BOOKMARK NOT DEFINED 3 1 COMPILING THE REFERENCE DESIGN cscccsscssscssscesscessessecesseesscesscssecesseesscsseessecssecssecessessecesscesseesseesecesecsseeeseeeseeenee 133 3 1 1 The Xilinx Embedded Development Kit tenente 133 3 1 2 Xinlinx 3 13 Xilinx 3 1 4 The Build Utility M ke b tszus iae ena e tiat ERR EE OE EE Per ORE THER ETE RE 4 GETTING MORE 2 21 entente enean tatnen enata tata 134 4 1 PRINTED DOCUMENTATION 138 4 2 DOCUMENTATION ER 138 4 3 ONLNE DOCUMENTATION rm 138 5 FPGA OPTIONS a r EA NEEE 141 Sel M 141 912 P PT ERAN 141 5 3 gue wo 6 MULTI GIGABIT SERIAL OPTIONS 142 6 1
4. 3 3 Green 10mA DS33 R112 LEDCO 4 RLEDCO 1208 1 DS34 R113 LEDC1 4 RLEDC1 120R 0535 114 910 2 LEDC2 RLEDC2 1208 LEDCO i0 D31 1C 1 IO LIN D30 LC 1 DS36 R115 IO L2P_D29 LC 1 TEDCT LEDCS RLEDC3 1208 IO L2N D28 LC 1 HS TEDCI 10 L3P D27 LC 1 Gi6 TEDCS p mmm 2 M 1208 LAN 024 VREF 10 1 RIS 224 IO L5P D23 LC 1 TEDCS IO L5N D22 LC 1 5 DS38 R117 1O_L6F_D21_LC_1 rid 1 5 RLEDCS 120R dis IO LeN D20 LC 1 HETS LEDC 22 OFZ 1 10 17 019 10 1 Fie o veco IO L7N D18 LC1 0539 R118 IO L8P D17 CC LC 1 20R OIN Die cele LEDCG RLEDCS ah 1 0540 R119 Virtex 4 FX 1152 LEDC7 E RLEDC7 120R 1 P272 DS41 R120 1 8 RLEDC8 180R 1 0542 R121 LEDCS RLEDCS 1208 1 0543 R122 LEDC10 d RLEDC10 120R 0544 R123 LEDC11 RLEDC11 120R 0545 R124 1 12 RLEDC12 120 DS46 R125 LEDC13 4 RLEDC13 120 0847 R126 1 14 RLEDC14 120 0548 R127 LEDC15 RLEDC15 120 Figure 32 FPGA C LEDs FPGA A is connected to 8 green LEDs FPGA C is connected to 16 LEDs These LEDs can be used for the user design The brightness of these LEDs can be controlled by changing the output
5. DIMM VREF 1 2 D vss bos Ce 08 0 5 amp 9 VSS ig DIMMB DIMMB 005 0 Til eS 12 DIMME DOST DIMMB_DQ6 13 H4 DIMMB DO2 17 vss DIMM VIT 002 vss 29 D 21 003 0912 22 a DIMMB 1 32 vss DQ13 DIMMB 5 0 32 11 DIMMB DM1 DIMME ODTO 27 28 DOS T 25 SS 588 30 DIMMB DIMMB DIMME DOST CKO T x 31 bos 22 FS BNME Cko 56R DIMMB DQ10 1 35 Eo Misi 36 DIMMB 0014 DIMME DOTS 37 Dan pais 38 DIMM VIT ves UT 41 42 DIMMB DQ16 toa vss VSS 44 DIMMB DIMMB A15 45 0016 0020 46 DIMMB DGZT DIMME ATT 47 0017 0921 Tas DIMMB 2 451 85 WSS Perey DIMMB DQS2 51 2052 NC 52 _ 2 23 0052 DM2 56R DIMMB DQ18 1 55 VSS VSS 86 DIMMB DQ22 57 0018 0022 5g DIMME DG23 DQ19 0023 DIMM VIT 56 60 9 DIMMB 0024 T 611 ud poe 62 28 DIMME DQ25 63 64 DIMMB DG29 4 STA DIMMB DM3 871755 DIMMB DQSn3 1 69 70 DIMME 11557 75 DIMMB DQ26 131 sd 74 50R DNI omena 76 DIMMB L9 vss SS Lemme DIMMB CKEOc TE 8i CKE
6. 433v EE ET 433v Reset Circuit R359 124R R373 R367 R358 1K 845R OR R364 R371 1K 2 4 88 79 u23 RST 2 VREF amm t 324 H Svs 8 8 7 28 0K TI R360 VPG 1 va R368 8 7 28 0K R361 5 3 1108 T M VEG T 100R R372 R363 5 z C102 715 100R TORT R357 TCZ800MMSOPi0 2 7nF GND 71 5K TOZ800 MSOPi0 1018 2 7nF 433v EU WV e pus MA 25 53 R374 10K V3 1 8V MAL V4 ADJ V2 2 5V Ee 0 5 V3 1 8V v4 ADJ 0 5 V HARD RESET 5 2 Secondary Power Supplies The secondary power supplies are derived from a primary supply 5 21 DDR2 Termination Power DDR2 memory modules use the 5511 18 signaling standard Properly terminating SSTL18 requires a termination power supply of 0 9V Since as much as 1 6 Amps of termination current are needed a switching power supply is required DDR Switching Power Supply VTT 0 9V amp 3A C981 C980 C967 43V 100uF DNI 100uF DNI 100 10V 10V 10V C959 TANT n 0 9 AVCC IN R328 1008 1 8V i cosa C982 21 100uF u40 w T T 1 8V 16 1 m 10 R325 71 cess AGO Fg TANT 1 156 15 2 vcca PVDDt Pv
7. 200Mhz BCLK 200Mhz BCLK DDR2 DDR2 75Mhz 75Mhz BARO BAR1 BAR2 BAR3 BAR4 BARS BAR6 7 QL5064 DN8000K10PCI Host PC Host PCI Bus 33 66 Mhz 2 1 Using the Reference Design DN8000K10PCI User Guide www dinigroup com 126 INTRODUCTION TO THE SOFTWARE TOOLS 2 1 1 Built In RocketlO test From the AETest main menu select option 4 MGT Menu The MGT test sends a repeating test pattern out all of the RocketIO transmit pairs and compares the input of each RocketIO channel to that pattern To run the test you must loop back each RocketIO pair mulator PCI Controller Driver M on Jul 22 2005 at 12 58 24 P PCI Menu M Memory Menu FPGAs stuffed 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 Menu Q Quit PCI E 0 e1000009 1 0000900 2 41000000 3 4 000000 4 44000000 5 000000 Please select option _ You can easily loopback the SMA channels by connecting the RX and TX connectors of each pair together with an SMA cable modules be tested with an LR loopback attenuator Option 5 of the MGT menu allows you to invert the polarity of one of the SFP channels For the test to pass this must be done since SFP2 is received with inverted polarity The MGT menu also allows you to modify the The M
8. GND PCI_PRSNT1 X Bo 55 TA cn Pci PRSNT2 Xii Fat GND ag VV POLPRSNT2 BI 330R GND RSVD g EE 9 RE 58 59 PCI CLK J i8 GND GNT PCI Be GND 31 Hm 8 RIS RIS 2 2 5 gt S RS NS 2 gt 8 B33 017 AD16 f Q 5 gt E 2 lt an00oners0 c ale e ee e ned E2 GND FRAME IRDY GND 5 Remember Most users will use the same power supply to power the motherboard and Aux IDE power connector P3 In this configuration these modifications are not required 11 8 PCI Signaling To allow universal 3 3V or 5 0V PCI IO the DN8000K10PCI uses the PCI bus s VIO pins to detect the IO levels used by your motherboard Most motherboards use 5V signal levels on the DN8000K10PCI User Guide www dinigroup com 119 PCI bus but many servers and all 64bit PCI slots require 3 3V signaling levels 45 0V Quicklogic 5064 Power and NC VIO 45 0 01 T 2 vioQL 3 4 WA C1000 C997 C1002 C1001 1uF IO voltage for the DN8000K10PCI is provided a jumper connecting the PCI slot s VCCIO signal to the Quicklogic 5064 For correct operation in stand alone mode a jumper should be installed b
9. FPGA BUSY 20 0 TK 2 DOUT BUSY Y23 MSELAO GND WE Y24 MSELAT R20 25 E uN 22 KY 32577 R214 JTAG FPGA TMS 1K ET Hn JTAG FPGA TCKACC TCK JTAG FPGA TDI 7 TON ABIZ rry vooo o TDO VCCO 0 zm VCCO 0 2 R223 JTAG FPGA TDIB JTAG FPGA Figure 27 FPGA A Configuration Bank If you ordered your DN8000K10PCI with one or more FPGAs not installed Option FPGA A NONE FPGA B NONE or FPGA NONE then a bypass resistor is installed connecting the TDI pin to the TDO pin of the uninstalled This is so the JTAG chain will remain intact when FPGAs are missing 2 2 2 SmartMedia When the DN8000K10PCI powers on the microcontroller reads the contents of any SmartMedia card that is in the SmartMedia slot The microcontroller by default opens a file on the root directory named Main txt if it exists This file contains instructions for the configuration circuitry to configure the Virtex 4 FPGAs To create SmartMedia card to control the DN8000K10PCI configuration insert the SmartMedia card into a card reader provided and connect it to a PC Create a file on the root directory of the card and call it Main txt main txt write a series of configuration commands separated each by a new line A valid command is one of the following comment FPGA A filena
10. ww dinigroup com 118 shorted to the PCI slot 5 0V and 3 3V The power supply driving the PCI slot and IDE power cable must be driven from the same unit If you ate operating DN8000K10PCI in a server or other enclosure that does not have available IDE hard drive cables and you intend to use the DN8000K10PCI in a high power application then an alternate setup will be required There are eight 00 resistors shorting the PCI edge connector s 5V pins and the power distribution plane on the DN8000K10PCI This connection disallows safely connecting the Aux IDE power connector to an external power supply To allow the use of a separate power supply dedicated to the DN8000K10PCI while it is in a PCI slot these resistors be removed Phase e mail tech support if you think that you need these resistors removed You will also need remove the 12V wire on the IDE hard drive cable to prevent contention with the PCI slot s 12V supply Note that in this configuration the 5 0V power for the DN8000K10PCI and most of the required power will be supplied from the external supply over P3 The 3 3V power for the DN8000K10PCI will continue to be supplied from The eight OQ resistors are RN4 RN6 RN5 RN47 RN48 RN50 RN51 COMPONENT SOLL SIDE SIE BH aav TrsT HA GND X RN mmo B4 GND TMS Aa PCL H 18 5 TA 48 C206 7 e 220
11. 1 mw fene T uer 4 HHHH HHH m 4 4 4 444344444449 x PEE luf a 2 AR 5 t E Ti MI d E tex as 7 The topside clearance with the factory installed active heatsinks is 23mm 3 45 80 R TYP 40mm CHAMFER TYP B PLCS 09561 uuo vot This leaves just enough room for airflow if the adjacent PCI slot is left unoccupied or the DN8000K10PCI is the last PCI card in the row The default heatsinks can be removed if you do not require high power operation allowing DN8000K10PCI to meet the PCI height restriction The back side clearance is 3 5mm This exceeds the PCI specification by 2 5mm If it is required that DN8000K10PCI use only one PCI slot the fan can be removed from the active heatsink assembly as long as sufficient airflow is provided Most PC cases do not provide sufficient airflow for high power applications The board should plug into any PCI or PCI X slot with 5V or 3 3V keying 32 bit or 64 bit slot widths 33Mhz or 66Mhz 100 and 133Mhz will be brought down to 66Mhz automatically DN8000K10PCI User Guide www dinigroup com 121 INTRODUCTION TO THE SOFTWARE TOOLS Chapter Introduction to the Reference Design This c
12. TP5 F2 Switching Power Supply 1 2V 20A 41 2V PSU2 IN L2V 6 yw vour s C288 C264 C338 C279 C310 C357 SENSE 2 C339 C340 l Q00uF 24 100uF 100uF 1OuF 10uF 1OuF il 150ur L 150uF 10V 10V 10V 6 3V 6 1096 10 10 1 2 1 ON OFF _ 20 20 C TANT F TANT TANT 12V VTRIM C TANT TANT R2 R177 R176 10K 1 81 431 i YNCO5S20 0 7 gt The DN8000K10PCI is shipped with a fun mounted above the power supplies to help keep them cool If you need to remove this fan the DN8000K10PCI will function properly without it but be careful not to touch the power supplies with your fingers because they will burn Each power supply is protected with a 15A fuse on the inputs If you need to operate the DN8000K10PCI with more than 15A of current for a power supply you can change this fuse but you need to find a heatsink solution for keeping the Virtex 4 FPGAs cool The heatsink and fan provided appropriate for a power consumption of about 10 15W per FPGA DN8000K10PCI User Guide www dinigroup com 82 Each of the primary power rails 5 0 3 3 2 5 1 8 1 2 is monitored for under voltage If the voltage monitor circuit detects a low voltage it will hold the board in reset until the supply is back within 5 of its set point See section X Reset Circuit for information on reset 12V 18V 25V 50V
13. MGT25 9034 103 ES 1 AD34 103 AVCCAUXMGT_103 2O33 MGT2S 1 103 MGT25 1 103 16 VCC MGT25 2 888888 0 222 555544 888888 222222 555556 Vinex 4 FX T1852 SISSE 852422 1 21V 8 MGT12 top 18V Us t 5 veowen vout Sag al A 1OuF SENSE 1 C301 C300 C49 52 51 C53 C50 10V C312 ADJ 2 150 150uF 2 2uF 2 2uF 2 2uF 2 2uF 2 2uF 2 2uF 20 10 3V V C54 TANT 10V T1580CQ R21 20 20 20 100R TANT TANT TANT 4 4 4 Five linear rails 5 2 3 Optical Module Power Optional optical modules have a variety of power by the DN8000K10PCI XFP power filtering 5 0V L4 5 0 4 Y 4 s VCC50 XFP1 4 7uH 6820 310337 0317 0 tuF m 0 tuF gt 2 TANT 3 3V L3 3 3V rey gt VCC33 XFP1 4 7uH 5 0V 0519 0336 0316 9 45 0V 22uF 0 1uF 10V 0 1uF 42 5V 1 8V gt 20 9 42 5V 17 1 8V VCC18 XFP1 Y 3 3V 1 1 1 9 43 3V 089 41 0594 0619 GND T 22uF eS 0 1uF 10V 0 1uF es 20 TANT Since the DN8000K10PCI has DN8000K10PCI User Guide supply requirements most of which are met 0 5A 0 75A 1A no negative voltage supply it cannot generate the 5 2V required to supply ECL based optical transceiver modules An auxiliary power connector is supplied to connect to an external voltage
14. ABCLKP2 ABCLKP3 ABCLKP4 ABCLKP5 ABCLKP6 FROM BACLKNO BACLKN1 BACLKN2 BACLKN3 BACLKN4 BACLKN5 BACLKN6 BACLKPO BACLKP2 BACLKPS DN8000K10PCI User Guide C15 G26 L39 038 AG38 AU37 AW27 D15 G25 K39 T38 AG37 AV37 AV27 D16 B27 D39 W39 AJ37 AT38 AT25 E16 C27 C39 V39 C27 D16 G1 M2 AE2 AV12 B27 E16 F1 M3 AES AU2 AW12 D27 C15 A4 M1 AD4 AT3 AR13 E27 D15 A5 L1 www dinigroup com 88 BACLKP4 AJ36 AD5 BACLKP5 AU38 AU3 BACLKP6 AT24 AT13 6 2 Main Bus There is a 40 signal wide bus connecting all three Virtex 4 FPGAs This bus is used by the Dini Group reference design to communicate over USB and PCI If you require PCI communication you will likely communicate directly from FPGA A to the Quicklogic 5064 and not need the main bus If you need to communicate over USB from your user design you may want to copy the main bus interface module out of the Dini Group reference design so you can use the existing USB software If the main bus is not required these 40 signals can be used by the user design for inter FPGA communication In the USB Controller application that came with your User CD there is a button near the top of the screen labeled Enable USB lt gt FPGA communication As long as this button is present the USB Controller program will not cause the main bus signals to be driven from the Spartan 2 FPGA If the button text
15. 5 0 XM os LS To E 9 mes FPGAs E Nc JH 4 L 7 Vdd nas o 234 Our 3 os H o Ha 33V R179 AA 1 22 yrat set 21 SND 2 SEL Ho 22 11 18 21 DCLK Fo SDATA 19 5 1585408 ALLCLK SLOAD 333V 26 V Mmeo 28 PLOAD ALLCLK SRST I 17 ast 18 GND vee H a GND vec Ha ICSS44210FP32 The 8442 outputs are connected to a 1 8 LVDS buffer and distributed to the FPGAs Aclk and Bclk are also distributed to the expansion headers as well DN8000K10PCI User Guide www dinigroup com 74 The clocks ACLK BCLK DCLK are LVDS so a IGBUFDS module should be used to receive the clock differentially External differential termination is not provided so the DIFF TERM attribute should be set on this module See the example source code The crystal supplied for ACLK is 25 0 Mhz With the 84426 PLL range possible output frequencies are 31 25 62 50 125 00 250 00 34 38 68 75 137 50 275 00 37 50 75 00 150 00 300 00 40 63 81 25 162 50 325 00 43 75 87 50 175 00 350 00 46 88 93 75 187 50 375 00 50 00 100 00 200 00 400 00 53 13 106 25 212 50 425 00 56 25 112 50 225 00 450 00 59 38 118 75 237 50 475 00 62 50 125 00 250 00 500 00 65 63 131 25 262 50 68 75 137 50 275 00 71 88 143 75 287 50 75 00 150 00 300 00 78 13 156 25 312 50 81 25 162 50 325 00
16. DVAL DF48 FPGA_PH1_DVAL DF49 FPGA_PH2_DVAL DF50 OFFSET DFE NEW CONFIG VERSION DFFD NEW BOARD VERSION DFFE OLD BOARD VERSION DFFF These registers can be written to from the USB interface See USB Software Programmers Guide 2 4 5 USB The Cypress CY7C68013 has a built in USB 2 0 interface The USB type B connector on the DN8000K10PCI 12 is connected directly to the USB pins on the Cypress MCU DN8000K10PCI User Guide www dinigroup com 68 R248 VBUS VBUS PWR VALID us 3 9K R249 6 34K 1 MCU USB MCU_USB USB_GND lt GND SHIELD 5 GND SHIELD 99 USB M USBp 2 C672 1 2 2uF USBp OV 3 dd CM1213 01ST SOT23 3 5 2 USBn OV 2 2uF USBn OV USB Transient Protection The USB protocol is completed the Cypress CPU The Cypress receives a 24Mhz clock from an oscillator The Cypress internally multiplies this clock to 480Mhz for USB 2 0 and 48Mhz for GPIF operation The core runs at 24Mhz along with the external memory interface Communication over this external memory interface is clocked using the MCU IFCLK signal driven from the MCU at 48Mhz The Spartan communicates over main bus with the Virtex 4 FPGAs using a separate 48Mhz oscillator X1 and distributes this clock to each FPGA including itself MCU 480 2 PLL Sparta
17. are single ended signal with an external pull up resistor The daughter can ground these signals to indicate the daughter card s presence The HAp nCC and HBp nCC signals are connected to global clock input pins on the FPGAs These can be used as differential clock inputs from the daughter card headers to the FPGAs They can also be used as outputs The ACLK and BCLK signals are copies of the DN8000K10PCI global differential clocks ACLK and BCLK The signals are synchronized at the daughter card connector with the ACLK and BCLK signals at the pins of the The signals HApXX HAnXX and are connected to Virtex 4 IOs Generally these signals are LVCMOS25 outputs LVCMOS25 inputs or LVDS inputs Some of these signals are connected to BANK 1 of FPGA A and B On the DN8000K10PCI these two banks can be set to operate at 3 3V This allows the use of LVCMOS33 outputs LVDS inputs are still OK The table below contains the list of BANK 1 IO sites on a Virtex 4 FPGA Table 2 FPGA A and B bank 1 pins F26 25 K16 L16 E26 J16 M25 G16 123 16 026 15 N24 G15 R22 B16 D20 E19 D21 C18 D22 G20 22 22 21 N18 G23 M18 E22 H17 B23 E18 C20 D19 E21 C19 C22 F19 H22 T19 19 H23 L18 23 G18 C23 F18 T20 L24 N17 J17 D25 D17 M17 K24 K23 C17 R17 C25 B25 A25 E17 A18 E24 P17 F24 B17 J24 U20 A24 B18 D24 C24 K17 DN8000K10PCI User Guide www din
18. User LEDs from FPGA C DN8000K10PCI User Guide www dinigroup com 29 DS40 DS39 DS38 DS37 User LEDs from FPGA C 10836 DS35 DS34 12833 0532 0531 0530 10529 User LEDs from 0528 DS27 DS26 0525 Figure 10 DN8000K10PCI LEDs 4 Using the Reference Design with the Provided Software To communicate with the reference design or user design on the emulation board the DN8000K10PCI provides three options out of the box e USB e PCI e RS222 The USB and PCI interfaces allow configuration of the FPGAs and bulk data transfer to and from the User design The RS232 interface allows low speed data transfers to and from the User design and control and monitoring of the configuration process This section will get you started and show you how to operate the provided software For detailed information about the reference design and implementation details see Chapter 5 The Reference Design 4 1 Operating the USB controller program Use the provided USB monitoring software to verify that the design is loaded into the FPGAs 1 Insert the CDROM that came with your DN8000K10PCI into the CDROM drive of yout computer 2 Connect the USB cable to your DN8000K10PCI and a Windows XP PC Before or after the DN8000K10PCI has powered on 3 When you connect the USB cable to your PC for the first time Windows detects the DN8000K10PCI and asks for a driver The board should identify itself
19. 33 lis 45 33 99 EET 99 55 88 OO 5 9 GH 89 09 99 DDRB PLL FBn az az az az az 1 DDHE PLL FBp NN 55 HH GOGO KR BH OO 222111254155 33 24 ee oo oo oo SS SR ag aes SEI Ge 58 SEL SEI 5 52 55 90 lt 44 lt lt 24 42 lt lt lt lt 2 5V DDRB_FB_Cn A clock is provided to the SODIMM modules from the FPGA signal DDR CLKOUT This is buffered through a CDCU877 SSTL clock buffer and sent to the SODIMM modules Signal DIMM DIMM There is no length relationship between the clock signals to the DIMMS and the data signals to the DIMMs The user should use the FB C signal with a DCM to synchronize the FPGA clock to the clock received by the DIMM module 7 2 Serial presence detect The EEPROM on the SODIMM is accessible by PCI USB or configuration UART DN8000K10PCI User Guide www dinigroup com 90
20. WRITER A20 3 A21 TDO D377 NC GND CFPOGA PHOGn 1iw2o WRITEn 1 2 650 JTAC CFPOR TOT NC GND Ev mnes M CU URS 0 24 28_ PROM HAG FROM TCK 18770217044 33 433V E R365 100R 267 8269 R70 JTAG PROM TMS DS24 v 10 12 14 R268 2 1K CFPGA DONE 1 2 Gi2 al 87332 1420 Figure 21 Spartan II Configuration As soon as the Spartan II FPGA is configured it resets the Cypress microcontroller Pull downs on the PROG pin of FPGAs A B and C ensure that the FPGAs cannot be active unless the Spartan II is successfully configured 2 1 2 Smart Media The Smart Media interface 15 connected to the IOs of the Spartan 2 To Microcontroller J24 SM CLE 2 0216 SM ALE 3 CLE von SM WES 41 ALE 102 10 SM WPn 59 WE 103 0 Io ABS SM CEn 214 WP 104 lo 10 ws 2 SM REn 204 105 10 10 agg RE 106 9 10 a 107 10 10 vig 108 10 10 848 B 10 IO WPtn 27 WP CARD INS IO 10 Hia WP CARD INS IO yita IO 10 B6 ART 19 SM RDYBUSYn AAT lo AATE GND RB H7 wey 10 18 GND x 0 10 25 GND 22 Dyo 0 50 15 oH io CGND VCC Basse SmartMedia 999999 X
21. NES GER SEHR Ge PEOR ONEEN 142 6 2 MODULE SOCKETS PELLEN CAVES ERE 142 7 OTHER OPTIONS 143 HEADER S AMNES 143 72 POWER 143 8 OPTIONAL EQUIPMENT Chapter About This Manual Wekome to DINSOOOK10PCI Logic Board Congratulations on your purchase of the DINSO00KTOPCI LOGIC Emulation Board If you are unfamnikar with Dini Group produds you should read Chapter 2 Start Guide to fanahanze yourself with the user interfaces the DINSOOOK10PCI Figure 1 DN8000K10PCI 1 Manual Contents This manual contains the following chapters About This Manual List of available documentation and resources available Reader s Guide to this manual Quick Start Guide Step by step instructions for powering on the DN8000K10PCI loading and communicating with a simple provided FPGA design and using the board controls Board Hardware Detailed description and operating instructions of each individual circuit on the DN8000K10PCI Controller Software summary of the functionality of the provided software Implementation details for the remote USB board control functions and instructions for developing your own USB host software Reference Design Detailed description of the provided DN8000K10PCI reference design Implementation details of the reference desi
22. Number Pin Pin 1 12 NC 2 GND GND 3 2 5V 2 5V 4 5 0V 5 0V 5 2 5V 2 5V 6 5 0V 5 0V 7 NC NC 8 GND GND 9 43 3V 3 3V 10 NC NC 11 GND GND 12 BCLKHAP BCLKp 13 BCLKHAN BCLKn 14 HBP67 AF34 15 NC HBN67 AF35 16 NC HBP73 AG23 17 HBN73 AH23 18 NC HBP71 AG22 19 NC HBN71 AF21 20 NC HBP69 AE22 21 NC HBN69 AD21 22 GND GND 23 HBP75 AH17 24 NC HBN75 AG17 25 HAP65 65 W34 26 HAN65 65 W35 27 HAP63 5 HBP63 R36 28 HAN63 C35 HBN63 T36 29 HAP61 J32 HBP61 R28 30 HAN61 K32 HBN61 R29 31 59 D30 HBP59 J32 32 59 D31 HBN59 K32 33 GND GND 34 HAP57 R28 HBP57 D30 35 HAN57 R29 HBN57 D31 36 55 E26 HBP55 N23 37 55 D26 HBN55 M23 38 53 D25 HBP53 T23 39 5 C25 HBN53 R22 40 51 M25 HBP51 T20 DN8000K10PCI User Guide www dinigroup com 94 41 51 N24 HBN51 T19 42 49 F24 HBP49 T18 43 49 24 49 R18 44 GND GND 45 47 H23 HBP47 P17 46 47 G23 HBN47 R17 47 45 D22 HBP45 M17 48 HAN45 22 45 N17 49 HAP43 J22 HBP43 F26 50 H22 HBN43 F25 51 HAP41 G22 HBP41 F24 52 41 F21 HBN41 E24 53 9 T23 HBP39 F23 54 9 R22 HBN39 E22 55 GND 56 7 G20 HBP37 G22 57 HAN37 F19 HBN37 F21 58 5 T20 HBP35 G20 59 5 T19 HBN35 F19 60 T18 HBP33 D19 61 R18 HBN33 E19 62 HAP31 C19 HBP31 E18 63 1 C18 HBN31 F18 64 2
23. 1152 1 1 21 423 CONN SMA 1 3 4 116 SMA FPGA RocketIO 010 20 1 4 AVCCAUXRXA 110 RXPPADA 110 AVCCAUXRXB 110 RXNPADA 110 AVCCAUXTX 110 417 SMA TXPPADA_110 TXNPADA_110 VTRXB 110 RIO SMA TXp1 TTA MO J18 CONN SMA 1 TXPPADB 110 VTRXA 110 5 gt MP TXNPADB 110 VTTXB 110 1 a A RIO SMA RXpt RXPPADB 110 AVCCAUXMGT 110 RXNPADB 110 MGTVREF 110 RTERM 110 5 1 4 9 ES ELE SES MGTCLK P 110 99999999 MGTCLK N 110 66000000 Virtex 4 FX 1182 Figure 40 SMA Connections The loopback pair AP26 and AP25 can be used to test your Virtex 4 fabric design You may want to get the loopback pair working before attempting to transmit high data rates over a cable system 11 PCI interface 11 1 PCI edge connector 3 3v or 5 0V universal 64 bit card edge connector DN8000K10PCI User Guide www dinigroup com 115 DN80O0KIOPCIj COPYRIGHT 2005 THE DINI GROUP LA JOLLA INC PCI bezel Do not attempt to plug a PCI in backwatds if it does not fit 11 2 The Quicklogic 5064 I
24. 2 Untitled Configuration Mode gt iMPACT Dn BHimosss3x 300g460n08YV Boundary Sean Slave Serial SelectMAP Desktop Configuration Before Progamming 7 r Pead Protect r Validating chain idary tcan chain validated s PROGRESS END End E Tm 045 vo20 xct 8p 648 setAttribute position 1 attr devicePartName value xcl v02 setAttribute position 1 attr configFileHeme value blackhorse F DiniProd DN50001 17 Loading file blackhorse F DiniProd DN5000121 SourcesConf igFPGANIMPLEHENT pros acs done Device 41 selected Figure 18 Impact Window To program the prom Right click on the prom and select Program from the popup menu In the options dialog that follows the options Erase before programming should be selected and Verify should be deselected Press OK The programming takes about 35 seconds over the parallel port Power cycle the DN8000K10PCI The new firmware is now loaded You can close impact and disconnect the Parallel IV cable DN8000K10PCI User Guide www dinigroup com 47 Chapter Hardware 1 Overview The DN8000K10PCI was designed to maximize the number of useful gates in your emulation project running at speed by providing the densest interconnect possible achieve this goal the DN8000K10PCI is equipped with the highest capacity FPGAs available today the Xilinx Virtex 4 LX200 The FPGAs the DN8
25. 8 1 SWITCHING POWER SUPPLIES 8 2 SECONDARY POWER SUPPLIES 8 2 1 DDR2 Termination POWEr iiti CL ERE TE 8 2 2 HG ON C 8 2 3 Optical Module Power 83 HEAT DISSIPATION Z ttiv sas RENOVARE ORE TRA RE NE UR EET NE 9 PPS 86 9 1 BUS 89 10 MEMORY INTERFACE Dc 89 10 1 D 90 10 2 SERIAT PRESENCE 90 11 HEADERS 11 1 3000K10 COMPATIBILITY hine ret iier En et i EFE ERE RUE RE 93 11 2 FPGA CONNECTION 11 3 CO POWER 11 4 PHY SIGAT is S 11 5 DAUGHTERCARD POWER 11 6 IU 12 JN c 102 13 ROCKETIO 13 1 ROCKETIO CLOCK RESOURCES eGR GAO RUG Ody 103 13 2 MGT POWER NETWORK 13 21 FX CES2 FEWOYFE 4 oia 13 3 THE CONNECTIONS nint ee 13 4 SAMTEC MULTI GIGABIT RIBBON CABLE 13 5 13 5 1 13 5 2 13 6 14 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 15 16 1 EXPLORING THE REFERENCE 5
26. 12 LX160 10 11 12 LX200 10 11 1 3 FPGA C Select an FPGA part to be supplied in the C position This fpga is connected to a memory module socket This FPGA 15 required to provide Multi Gigabit serial communication In order to achieve 10 Gbps SelectIO operation the 12 speed grade is required NONE FX40 10 11 11x 12 This option makes the 200 pin SODIMM memory socket one SMA channel four QSE cable channels and one optical module socket unusable EX60 10 11 11x 12 This option makes four channels of QSE cable unusable FX100 10 11 11x 12 2 Multi Gigabit Serial Options 2 1 Serial Clock Crystals If you need to interface to a specific Multi gigabit serial IO protocol you may need to install a custom crystal as a reference to the RocketIO clock synthesizer Consult the Dini Group when ordering for availability The following frequencies in Mhz are standard and Dini Group keeps a stock 9 8304 12 890 14 318 16 000 21 477 24 576 25 000 The default option is 25 000 Mhz 2 2 Module Sockets and SFP Modules provide 1 0 10 5 Gb optical serial communications to FPGA DN8000K10PCI has two optical ports each can be installed with either an SFP connector modules operate only in the 9 5 10 5 Gb s range Available 5 modules operate between 1 4 25 Gb s For 10Gb operation a 12 speed grade FX part may be required These parts may not yet
27. 160 DIMME 0953 1er 0049 0953 Hes Totes 055 VSS 164 DIMMB CK 56R X65 NC TEST Her DE CRT DIMMB_CK1 DIMMB 00506 T3867 Ss ECES DIMMB 1 DIMME DOSE DIMMB_DM6 DIMM_VTT A 169 0086 ome F122 X RN38 DIMMB_DQ50 173 VSS VSS 474 DIMMB 0954 DIMMB 1 176 2950 0954 7176 DIMMB DQ55 DIMME ATZ 2 177 1951 9056 178 3 DIMMB DQ56 T3789 2 180 DIMMB OIMMB AB DIMMB 15261 E 1814 0057 basi 182 DIMMB DM7 185 VSS 88 186 DIMMB DOSn7 56R m 187 0057 188 DIMMB_DOS7 DIMMB_Dass T 388 VSS 0957 30 DIMM_VTT DIMME DOSY 0058 VSS 182 f _0062 m 1219 DIMME DOSS R349 SDA 17 195 196 10K DIMMB 197 SDA ves DDRB SAO MME W x 2 E 189 SA 200 DORE SAT 333V R350 CONN_DDR2_SODIMMz00 10K The DIMM_CKE signals are not end terminated These signals should not be operated at full frequency 8 Headers There are two daughter card headers the DN8000K10PCI one attached to FPGA Header A and one attached to FPGA B Header B Header A contains 135 user IOs designed to operate as 67 differential pairs Header B has 154 user IOs that can be used as 77 differential pairs The signals RESET FPGAs is driven by the Spartan Configuration FPGA This signal is the same as the RESET FPGAs driven to FPGAs A B and DN8000K10PCI User Guide www dinigroup com 91 PDETECTA and
28. Signal Name On setting Off setting Position S1 1 Off Reserved 2 jor Reserved 51 3 Off Boot mode Firmware update Normal operation default S1 4 Off Reserved DN8000K10PCI User Guide www dinigroup com 3 3 Memory and heatsinks There should be an active heatsink installed on each FPGA the DN8000K10PCI and a fan the power supply units Virtex 4 FPGAs are capable of dissipating 15W or more so you should always run them with heatsinks installed The DN8000K10PCI comes packaged without memory installed If you want the Dini Group reference design to test your memory modules you can install them now in the 1 8 DDR2 DIMM sockets 8 1 Es 02 2420 THE CEIP LA Figure 4 FPGA Names The socket DIMMB is connected to FPGA B The socket can accept any capacity DDR2 SODIMM module Note that DDR1 modules will not work in these slots since they ate supplied with 1 8V power and DDR1 requires 2 5V power and a completely different pin out 3 4 Prepare configuration files The DN8000K10PCI reads FPGA configuration data from a SmartMedia program the FPGAs on the DN8000K10PCI FPGA design files with a bit file extension put on the root directory of the SmartMedia card file using the provided USB card reader The DN8000K10PCI ships with a 32 MB SmartMedia card preloaded with the Dini Group reference
29. 15 3 1 VERIFY JUMPER SETTING mee n Een REEL C 17 3 2 VERIFY SWITCH SETTINGS 17 3 3 MEMORY AND HEATSINKS 19 34 PREPARE CONFIGRATION FILES 19 3 5 CONNECT CABLES eere 20 3 6 VIEW CONFIGURATION FEEDBACK OVER RS232 21 3 6 1 Watch the configuration status output 21 3 6 2 Interactive configuration 24 3 6 3 Read temperature sensors 24 3 6 4 Multiplex Serial port 25 37 CHECK LED STATUS LIGHTS 2 25 USING THE REFERENCE DESIGN WITH THE PROVIDED SOFTWARE eee eee eene 30 4 1 OPERATING THE USB CONTROLLER PROGRAM cccssssssssssseesecsesseessesecseessesssseseesessesseesscsesseesecaeensesseeeeesseasesssaeeseenseass 30 42 COMMUNICATING TO THE USER DESIGN OVER THE SERIAL PORT 32 4 3 USING AETEST TO RUN HARDWARE TESTS 33 4 3 1 AETest Windows96 version 33 4 3 2 AETest DOS version 33 4 3 3 33 4 3 4 Use VA 34 44 MOVING eI 35 CONTROLLER SOFTWARE 1 USB CONTROLLER 141 MENU OPTIONS 36 1 1 1 File Menu 1 1 2 Edit MENU 37 1 1 3 FPGA Configuration Men ee ODER CORO e ce
30. 23 24 22 25 26 26 TRG MICTORT L 26 28 PPC TRC TSTE UT 29 30 31 32 1 4 154 0 23 TRC TSA OR 35 36 37 38 GND LOC iH ono st GND GND Figure 31 Mictor Header Signal Pin on Name FPGA C RISC Watch signal MICTOR 1 AM10 MICTOR 2 AJ15 MICTOR 5 AF13 MICTOR 6 AF9 PPC TRC TCK MICTOR 7 AG13 PPC DBG HALTn MICTOR 9 AE13 MICTOR 11 AH13 PPC_JTAG_TDO MICTOR 13 AH9 MICTOR 15 AJ12 PPC_JTAG_TCK MICTOR 17 AK12 PPC_JTAG_TMS MICTOR 19 AF11 PPC JTAG TDI MICTOR 21 AG11 PPC JTAG TRSTn MICTOR 23 AJ9 MICTOR 24 AG12 TRC 51 MICTOR 25 AF14 MICTOR 26 AH12 TRC 520 27 12 28 13 5 29 MICTOR 30 AM12 PPC TRC TS2E DN8000K10PCI User Guide www dinigroup com 100 MICTOR 31 AK11 MICTOR 32 AK14 53 MICTOR 33 AJ11 MICTOR 34 AL14 TRC 54 MICTOR 35 11 MICTOR 36 AK13 PPC TRC TS5 MICTOR 37 AL11 MICTOR 38 AL13 PPC TRC TS6 8 8 RS232 One RS232 port P1 is provided for use by the user design This RS232 port can be accessed from any FPGA but only by one FPGA at a time This multiplexed port can be configured from the USB GUI Windows application Signal Pin on Pin on Pin on Name FPGAA FPGA B FPGAC RS232 RX AF 1 AK16 AH17 RS232 TX AE1 AJ16 AJ17 DN8000K10PCI User Guide www dinigroup com 101 9 LEDs
31. E 10 28 FOUT 01047 34 I 1 12 850 13pF 3010 0 01uF 13 14 R77 i 30 4 15 16 1009 4 499R 25MHz 37 2 1 122247 18 11 R61 D Ma 1 18 20 T E Ms R415 4 FX 1152 E 22 B OUT H 18 26 33 DIN DOUT a R45 2 R452 R453 R454 27 28 P3 3VAFXO ATEN 49 9R 49 9R 49 9R 49 9R mi 3 14 vcc 31 32 R62 R231 R416 iia 33 34 49 9R ISOLVI79W R255 1K 23 1K 35 Ed 1 XTALSEL Mb L 8 37 38 T 22 Ex C1044 38 ES RIO0 VCOSEL 57 XTAL SEL 7 5 001 uF 41 42 VCO_SEL FB72 Jt MGTCLK 113 45 43 1 RCLK2 SCLK SCLK 18 SCLK H2 8 KI MGTCLK N 113 E x ALLCLK SDATA zo SDATA 1035 Ae p3 3varxo ALLCLK_SLOAD CIRO SLOAD 001 uelis R244 TK READ HEADER 23x2 ALLCLK_sAsT 1 P3 3VAFXO H ono vec H2 10R Virtex 4 FX 1152 OPT GND vec 5843020 01 The LVPECL outputs of the ICS843020 are scaled down to meet the input requirements of the MGTCLK inputs An output from the 1 5843020 01 is also converted to LVDS and driven to J3 pins 19 and 21 the Samtec QSE DP connector This can be used to forward a RocketIO clock off board along with rocketIO signals to support standards that require an exact reference clock like PCI Express J3 may also drive pins 20 and 22 The ICS843020 01 can receive this clock and use it to ge
32. Xilinx c FPGAA 2 FPGA B 76 FPGAC 2 LX100 160 200 a LX100 160 200 2 FX60 100 gt 843020 N FF 3 differential EFi 513 differential 1152 uP Contig Virtex 4 or single Virtex 4 arshga Virtex 4 i 1 25 ended ended T H 250Mhz 1 21 pn 64 8 64 8 E dock contig ETE L Rocket WO Clock _ rook DDR2 SODIMM DOR2SODMM SODIMM QL5064 up to 4GB addressing up to 4GB addressing 25 Ics PCI Controller 1 1 1 I 92 l 1 1 1 66 MHz 64 bit PCI 4 5V 1 3 3V Universal y Figure 19 DN8000K10PCI Block Diagram The following sections describe in detail each circuit on the DN8000K10PCI Note that Schematics appearing in this section are illustrative and may have had details omitted or have been modified for clarity and brevity If you need to probe modify or design around the DN8000K10PCI you will need to examine the complete schematics See the schematic pdf on the user CD An assembly drawing has also been provided to help you find probe points on the DNS8000K10PCI 1 1 Overview The goal of the configuration circuit on the DN8000K10PCI is to allow the user to configure his FPGAs using any host interface The configuration system the DN8000K10PCI allows configuration over PCI USB JTAG or automatic configuration from a SmartMedia card DN8000K10PCI User Guid
33. a main bus address latch will occur DN8000K10PCI User Guide www dinigroup com 117 11 5 PCI clocking All communication to the Quicklogic 5064 chip is synchronized with a 75Mhz oscillator The 75Mhz PCI UCLK is delivered to FPGA A the Spartan 2 FPGA and the Quicklogic 5064 QL INTERFACE OSC U36 RPCI UCLKA PCI UCLKA Yo 1 5 gt PCI UCLKA 1 RPCI CUCLKM ae RPCI UCLNO gt PCI UCLKM 1 5 i GND va GND GS74LCT2524M ND 33R IN 11 6 JTAG The PCI connector s JTAG signals are looped back to bypass the DN8000K10PCI when it is plugged into the PCI slot SDONE SBO R376 0 5 1K j R377 54K 11 7 PCI Power In most applications the DN8000K10PCI can draw its power from the PCI slot The PCI specification requires that the motherboard provide 25W of 5V power for the DN8000K10PCI to use Most motherboards provide well in excess of this amount supplying the power for PCI cards directly from the ATX power supply In high power applications exceeding 25W you may need to connect the Auxiliary power connector P3 e The Aux Power connector is a standard IDE hard drive power connector and should be supplied by the ATX power supply that is in your computer case Aux power connector 5 0V and 3 3V are
34. then write 0 0 32 bit to REG ENABLED The value returned will be a coded name for the bus Bits 0 15 are ascii characters representing names Bits 16 31 are an arbitrary unique integer distinguishing the bus Connecting busses from two different FPGAs have the same bus ID To cause an FPGA to output signals on a bus write on REG OE To set the outputs to high write to OUT DN8000K10PCI User Guide www dinigroup com 136 INTRODUCTION TO THE SOFTWARE TOOLS To read the current received value from the bus inputs read from REG IN 5 4 Interconnect Test Highspeed This test requires the LVDS bitfiles 5 5 PCI Test This test requires the PCI interface bitfiles This test requires the application AETEST Run aetest The splash screen should print DN8000K10PCI Virtex Board VendorID 17DF DeviceID 1864 Use the menu items to change A_CLK to 100Mhz Use AETest menu options to configure FPGA A with the PCT design bitfile on the CD Blockram_access_A From AETest menu select Production Tests Menu Run the PCI test 0 This test will print a test status 5 6 RocketlO Test This test requires the RocketIO V4 bitfiles If you are using FX60 CES2 or FX60 CES3 parts you will require a different set of bitfiles and code CES1 parts have no working test Configure FPGA C with the reference design bitfile From the s
35. 00 62 00 124 00 248 00 496 00 64 00 128 00 256 00 66 00 132 00 264 00 68 00 136 00 272 00 70 00 140 00 280 00 72 00 144 00 288 00 74 00 148 00 296 00 DN8000K10PCI User Guide www dinigroup com 76 76 00 78 00 80 00 82 00 84 00 86 00 Each global clock is delivered to the FPGA as LVDS differential clock The IO input on this 152 00 156 00 160 00 164 00 168 00 172 00 304 00 312 00 320 00 328 00 336 00 344 00 clock should be configured as a differential clock input the IBUFGDS primitive The example below shows the Verilog instantiation of this module using the ACLK signal Wire ibufds IBUFGDS ACLK O aclk_ibufg IB ACLKn The signal aclk ibufds should then be fed to either a BUFG or a DCM before being used as an internal clock for FPGA logic 3 2 User Clock The DN8000K10PCI has an SMA pair reserved specifically for inputting a clock The SMA pair is connected to a differential clock input on FPGA A LVDS DCI is a preferred input standard but LVCMOS 25 will work also 20 N20 User CLK Input Note these have been changed to SMA J6 UCLK J21 J20 M21 M20 L20 L19 P22 P21 4 15 0 CONN_SMA J5 T 4 i 5 20 N21 L21 21 2 5V ICE LC 3 1O GC CC IO LIN GC CC LC oe 10_L2P_GC_V
36. 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 HAP20 HAN20 HAP18 HAN18 HAP16 HAN16 HAP14 HAN14 GND HAP12 HAN12 HAP10 HAN10 8 8 HAP6 HAN6 4 4 GND HAP2 HAN2 GND HAPO HANO J16 H15 B10 C10 P17 R17 H7 J7 P11 R11 N5 4 U5 V5 AC10 AD9 AL28 AM28 AF34 AF35 AU35 AU36 HBP20 HBN20 HBP18 HBN18 HBP16 HBN16 HBP14 HBN14 GND HBP12 HBN12 HBP10 HBN10 HBP8 HBN8 HBP6 HBN6 HBP4 HBN4 GND HBP2 HBN2 GND HBPO HBNO B10 C10 AL11 AK11 8 AV7 E8 F8 G7 G6 H7 J7 AJ6 AJ5 N5 4 AVA AV3 Y1 AA1 AT14 AR14 8 3 Getting LVDS on the header Since all of the FPGA pins connected to header and header B are pins the Virtex 4 LVDS standard cannot be used as outputs LVDS signaling is still possible On inputs use the LVDS25 standard On outputs use two LVCMOS25 DRIVE 2 SLEW FAST On the daughtercard terminate the signal with the following circuit DN8000K10PCI User Guide www dinigroup com 98 DN8000K10PCI Daughtercard 4 Daughtercard Virtex 4 Header 20 500 20 500 Rs LVCMOS25 2mA Data in This circuit terminates the differential signal at the destination with 100 Ohms differential impedance It also divides the voltage produced by the LVCMOS25 buffers down to a lt 400mV differential voltage The power
37. 3 A PORT 4 A Enter Port to change 1 4 q to quit 1 Enter FPGA to set port to A I B Do you want to change more RS232 Ports y or n n Figure 8 RS232 Port Menu The DN8000K10PCI only has one serial port Port 1 Changing ports 2 4 will have no effect 3 7 Check LED status lights The DN8000K10PCI has many status LEDs to help the user confirm the status of the configuration process DN8000K10PCI User Guide www dinigroup com 25 Configuration Control status status Spartan FPGA Configuration Activity l 9 990890 TII ux 111111111 i Makum iif i FPoa a DN8000K10PCI i COPYRIGHT 2005 THE DINI GROUP L JOLLA INC o CR 21 11 SS 9m Ui A il 1 5 3V UNIVERSAL M Figure 9 Configuration Status LEDs Check the power voltage indication LEDs to confirm that all voltage rails of the DN8000K10PCI are present From the top the LEDs indicate the presence of 5V 3 3V 2 5V and POWER Green lit LED s on the voltage present LEDs indicate the rails are greater than 1 7V A green lit power indicates that the voltage monitors inside the power supply are within acceptable operating ranges 5V is 4 5 5 5V 3 3V is 3 0 3 6V If this LED is not lit green
38. DONE signal This will allow the Spartan to begin more transactions The FPGA may delay this for up to 256 clock cycles before a timeout is recorded and the transaction is cancelled Main bus can be controlled from the USB Controller program Read and write single addresses ot to from files It can also be written from the main txt configuration method The main txt syntax is MAIN BUS Ox lt addt gt Ox lt data gt Where and data are 8 digit 32 bit hexadecimal numbers 4 Compiling the Reference Design The MainTest reference design for which bit files are included on the user CD and the provided SmartMedia card can be found on the user CD here D FPGA Reference DesignsN common DDR2 controller_ver ddtr2_to_mb dn8000k10pci LVDS_intercon source The top module is D FPGA_Reference_Designs dn8000k10pci LVDS_intercon soutce fpga v This module includes all of the other required sources and expects the directory structure found on the CD The LVDS_intercon directory is named that because the LVDS bitfiles also found on the user CD and the MainTest bitfiles use the same source code with define statements to switch on and off features 4 1 4 The Xilinx Embedded Development Kit EDK The reference design does not use the embedded processors of the FPGA parts Therefore EDK is not a required component of the reference design compilation 4 1 2 Xinlinx XST The Dini Group uses XST
39. Guide The Dini Group DINS000K10PCI is the user friendhiest board available with multiple Virtex 4 FPGAs However due to the number of features and flexibility of the board it will take some time to become familiar with all the control and monitoring interfaces equipped on the DN6000K10PCI Please follow this quick start guide to become familiar with the board before starting your ASIC emulation project 1 Provided Materials Examine the contents of your DN8000K10PCI kit It should contain DN8000K10PCI board Two Smart Media cards USB SmartMedia card reader RS232 IDC header cable to female DB9 USB cable CD ROM containing Virtex 4 Reference Design Virtex 4 Documentation Datasheets User manual PDF Board Schematic PDF Board netlist TXT USB Windows program usbcontroller exe USB Windows documentation PCI program Aetestdj exe Source code for USB program PCI program DN8000K10PCI firmware You should use the customer netlist provided on the user CD for the purpose of generating designs and should consult the schematic PDF provided on the CD when designing any hardware to interface to the DN8000K10PCI All other documentation materials are derived from this schematic For information about the USB Controller program see the document accompanying the program on the CD 2 ESD Warning The DN8000K10PCI is sensitive to static electricity so treat the PCB accordingly The target markets for
40. MN RCLKO 2 LVPECL RCLK2 low jitter Oscillators 88 250Mhz or other speeds SYSCLK 48Mhz Samtec cable FBBCLK SCLK1 ws SCLK2 Mhz Ex ICS8442 ACLK M DCLK BCLK ACLK 143 ICS8442 Mhz BCLK BCLK Daughtercard 18 0 Mhz SYSCLK 48Mhz FBACLK SCLK1 gt SCLK2 3 48 Mhz DELK _ Osc SCLK1 _ EEH Pert 8 4 SYSCLK 48Mhz SYSCLK 48Mhz SPartan2 Dauchtercard PCIUCLK 75Mhz 75Mhz PCIUCLK 75Mhz 48Mhz Quicklogic 5064 PCICLK BB or 33Mhz FBBCLK SCLK1 5 2 PCI Connedor SMA Connedor Figure 30 DN8000K10 clocking DN8000K10PCI User Guide www dinigroup com From the above diagram the global clocks are listed here RCLK1 An ICS frequency synthesizer either 1058442 ICS84321 100 250Mhz or ICS84020 667 2 This clock is configured from the MCU using the USB controller or the SmartMedia card This clock is supplied to CLK pins on FPGA C and can be used as an reference clock for any on the left column The Synthesizer can also be configured to use an external clock input from the QSE DP Samtec Ro
41. T23 IO L6N D20 LC 1 5 a IO L7P D19 16 1 Haps A16 IO L7N D18 LC 1 HAR26 Big 017 CC 1C 1 aie SR I0 L8N D16 CC LC 1 ee IO L9P GC LC 1 IO L25P LC 1 IE HR pig OLIN GC LC 1 IO L25N LC 1 Fagg HAp30 9 L10P GC LC 1 IO L26P LC 1 Bia HAn30 HAp OLION GC LC 1 IO L26N LC 1 524 B8 IO L11P GC 1C 1 IO L27P LC 1 lt EE cis GC LC 1 IO L27N LC 1 o9 1 HAp38 88 IO L12P GC LC 19 L28P LC 1 ggg an D22 10 112 GC VREF LC 1 10 L28N VREF LC 1 Haa HAp50 HAp37 J 0 L13N GC 1C 1 IO L29N LC 1 Tj8 HAR37 E18 114 GC LC 1 IO L30P LC 1 nig HAn33 jez 0 L14N GC 1C 1 IO L30N LC 1 HAp42 HAn 3 122 115 GC 1C 1 IO L31P LC 1 Hms HAn42 T20 01154 GC LC 1 IO L81N LC 1 nape 4184 GC CC LC 1 IO L32P CC LC 1 Harr _ 4 116N CC LC 1 IO L832N CC LC 1 L17N CC 16 1 IO L83N CC LC 1 57 HAp17 GND HPAT Nia 118 VRN LC 1 IO L34P LC 1 Niy HAnT7 2 _ O
42. The MCU is configuring FPGA A according to instructions in MAIN TXT The sanity check option reads the design file headers and vetifies that the design is compiled for the same type of FPGA that the MCU detects on your DN8000K10PCI If the design and FPGA do not match the MCU will reject the file and flash the Error LED You may need to disable to sanity check option See Chapter X section X if you want to encrypt or compress your configuration Sanity check passed files Bere DONE WITH CONFIGURATION OF FPGA A EERE CONEIGURING FPGA The MCU is configuring FPGA B according to instructions in MAIN ee Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME B BIT FILE SIZE 003A943B bytes PART 4vlx100ff151317 05 01 DATA 2005 07 19 TIME 17 05 01 Sanity check passed DONE WITH CONFIGURATION OF FPGA B The MCU is setting the temperature threshold to cause a board reset TEMPERATURE SENSORS YES B YES FPGA Temperature Alarm Threshold 80 degrees C DN8000k10PCI MAIN MENU Jul 27 2005 10 38 05 1 Configure FPGAs using MAIN TXT 2 Interactive configuration menu 3 Check configuration status 42 Change MAIN configuration file 5 List files on Smart Media 6 Display Smart Media text file 7 Change RS232 PPC Port 8 Set FPGA Address 9 Write to FPGA at current address a Read f
43. USB CLK or SYS CLK signal This clock is fixed at 48Mhz and cannot be changed by the user This clock is LVCMOS single ended When the ALE signal is asserted by the configuration circuit the slave device on the bus the FPGA is required to register the data on the on AD bus This is the main bus address All future transfers over the main bus ate said to be at this address until a new address is latched On a later clock cycle the master may assert the RD signal Some time after this within 256 clock cycles the FPGA should assert DONE for one clock cycle On this cycle the master Spartan will register the data on the AD bus and that will be the read data If DONE is not asserted then a timeout will be recorded and the transaction cancelled is write transaction USB CLK SYS CLK RD Spartan IER UM SUL LE EN E EE RE EET E E ITE MB WR Spartan MB 33 DONE FPGA _ When the WR signal is asserted by the Spartan FPGA should register the data on the AD bus Note that by convention FPGAs on the main bus are assigned the address range DN8000K10PCI User Guide www dinigroup com 132 INTRODUCTION TO THE SOFTWARE TOOLS cotresponding to one value of the highest nibble of the address Hex addresses OXXXXXXXX FPGA A IXXXXXXX are FPGA B and ZXXXXXXX are C Some time after this the should assert the
44. a suite of basic tests on the DN8000K10PCI The bit files can be found on the user CD in the Main Test directory To run the test load these bit files onto the FPGAs and run the USB Controller program All of DN8000K10PCI User Guide www dinigroup com 134 INTRODUCTION TO THE SOFTWARE TOOLS the tests in the MainTest suite require clocks to have certain settings You can guarantee this by creating a SmartMedia card with the following lines in main txt Verbose level 2 sanity check y clock frequency A N 4 M 16 100Mhz not used in maintest clock frequency B N 2 M 28 200Mhz clock frequency D N 2 M 25 200Mhz clock frequency 2 N 2 M 24 300Mhz 5 1 4 Temperature From the Settings Info menu select Read FPGA temperatures The temperatures of all installed FPGAs is printed to the log window in degrees celcuis PASS CONDITION The read temperatures should all fall between 20 and 80 0 indicates a failure to read temperatures above 80 indicates that the temperature overload circuit failed to reset an overheating FPGA 5 1 2 Main Bus Make sure that USB gt FPGA communication is enabled The button above the visual display should read Disable USB gt FPGA communication From the Mainbus menu select Read DWORD Read 1 DWORD from address 0x08000002 A 0x18000002 tor B or 0x28000002 tor A message indicating the read value should be returned PASS CONDITION Data should
45. allows the user to specify what frequency the RocketIO CLKs should be set at for each FPGA The supported frequency range is 31 25MHz 700MHz After selecting this option a pop up window will ask which FPGA s RocketIO Frequency you want to set or you can choose to set all to the same frequency and then what frequency you want Check the log window to verify what frequency the CLKs actually set at Set Global clock frequencies The clocks on the DN8000K10PCI are automatically adjusted to the user s desired frequency by reading the setup file on the SmartMedia card If you wish to change the frequency after power on or do not want to use a SmartMedia card you can set the frequency in the USB program ACLK is generated from a 25 MHz crystal Available frequencies are 31 25 34 375 37 5 40 625 43 75 46 875 50 53 125 56 25 59 375 62 5 65 625 68 75 71 875 75 78 125 81 25 84 375 87 5 93 75 100 10625 1125 118 75 125 131 25 137 5 143 75 150 156 25 162 5 168 75 175 1875 200 2125 225 2375 250 262 5 275 2875 300 312 5 325 337 5 350 375 400 425 450 475 500 55 550 575 600 625 650 675 700 BCLK is generated from 14 318 Mhz crystal Supported frequencies ate 32 22 34 01 35 80 37 58 3937 4116 4295 44 74 46 53 48 32 50 11 51 90 53 69 55 48 5727 59 06 60 85 62 64 64 43 66 22 68 01 69 80 71 59 73 38 7517 76 96 7875 80 54 82 33 84 12 85 91 8949 93 07 96 65 100 2 103 8 1074 1110 1145 1181 121 7 125 3 128 9 132 4 136 0 1
46. be 0x05000121 Data 0x DEADDEAD indicates a problem with the FPGA configuration Data 0 12341234 indicates USB Communication is disabled Data 0x DEAD5678 indicates an undefined register was read from the reference design 5 1 3 Clocks From the FPGA Reference Design menu select Read FPGA Clock Frequencies Each FPGA will report the frequency of each global clock measured at the FPGA input 5 1 44 RS232 Connect RS232 termial to the user RS232 port of the DN8000K10PCI The port settings should be 19200bps 1 stop bit 0 parity bits no flow control When the DN8000K10PCI main test is loaded into FPGA A the terminal should see an echo on the terminal This test requires that the RS232 multiplexer is set to FPGA A This is done from the USB Controller program 5 2 Memory Test This test requires the MainTest bitfiles To run the memory test make sure a 256 512 or 1024MB DDR2 SODIMM is plugged into FPGA and FPGA SODIMM sockets Select from the FPGA Reference design menu Test DN8000K10PCI User Guide www dinigroup com 135 INTRODUCTION TO THE SOFTWARE TOOLS DDR In the popup window select either FPGA B or FPGA C The status of the test will print in the log window This test works by writing a random set of data over the main bus to FPGAs B and C at addresses 0x10000000 1 FPGA B and 0x20000000 Ox2FFFFFFF FPGA C This memory space is mapped to the DDR2 SODIMM interf
47. be available before If you have the FPGA C option you may select one of the following options OPTICAL SFP SFP default OPTICAL XFP 142 OPTICAL SFP XFP 3 Other Options 3 1 3 3 V Headers The DN8000K10PCI can be configured to accept 3 3V input and output a subset of expansion header pins These IOs are not voltage selectable by the software You must specify on your order that you would like this option Select any of the following options The default option is all 2 5V header IO 3 3V Header A 3 3V Header B 3 2 12V Power Daughter card supply voltages 12V and 12V are by default disabled by jumpers R411 Header 12V R412 Header B 12V R414 Header A 12V R413 Header B 12V This default setting reduces the chance of damage to the Virtex 4 FPGA IO buffers due to user error or careless use of probes Specify this option to have the jumpers factory installed 4 Optional Equipment The Dinigroup supplies standard daughter cards and memory modules that you can use with the DNS8000K10PCI e SE card 80 signals on 1 pitch headers e Mictor Card 5 Mictor38 headers for use with logic analyzers SRAM module for use the 200 pin SODIMM sockets of the DN8000K10PCI QDRII 300Mhz 64x2Mb SRAM module for use in the 200 pin SODIMM socket 64x2Mb Standard SDR SRAM Pipelined or Flow through NoBL available RLDRAM module for use in the 200 pin SODIMM socket 64
48. before the FPGA is configured for the first time Write a word to the address BARO 0x208 The data word 0x11 represents FPGA A 0x12 is FPGA B 0x13 is FPGA C When the FPGA is read to configure it pulls the SelectMap signal INTn low The configuration process should pause until this occurs To read the current value of INTn on the selected FPGA read from the BARO address 0x208 Bit 5 represents the value of the selected INTn signal DN8000K10PCI User Guide www dinigroup com 60 After the INTn signal is detected the Host should de assert PROGn Reset Write to BARO address 0x208 the data word representing the selected 0x11 is A 0x12 is B 0x13 is FPGA C The configuration stream for the FPGA is then sent to BARO address 0x210 one byte at a time Some time during the configuration stream byte loading process a startup sequence is sent to the FPGA and the FPGA becomes operational This startup sequence is contained within the bit file To determine of the selected FPGA is currently configured i e configuration was successful read from BARO address 0x208 The bit 5 contains the state of the DONE FPGA pin the bit 6 contains the state of the FPGA INIT signal By convention the host program should leave the Spartan in the FPGA deselected state To deselect the write BARO address 0x208 the data 0x10 FPGA SELECT NONE 2 2 4 2 Config Space PCI can also be used to control other configu
49. design DN8000K10PCI User Guide www dinigroup com 19 1 Insert the provided SmartMedia labeled Reference Design into your USB card reader Make sure the card contains the files FPGA_A bit FPGA_B bit FPGA Cit main txt The files A C bit are files created by the Xilinx program bitgen part of the ISE 7 1 tools The file main txt contains instructions for the DN8000K10PCI configuration circuitry including which FPGAs to configure and to which frequency the global clock networks should be automatically adjusted 2 Insert the SmartMedia card labeled Reference Design into the DN8000K10PCT s SmartMedia slot contacts down 3 5 Connect cables The configuration circuitry can accept user input to control FPGA configuration or provide feedback during the configuration process The configuration circuitry IO can also be used to transfer data to and from the user design 1 Use the provided ribbon cable to connect the MCU RS232 port P2 to a computer serial port to view feedback from the configuration circuitry during FPGA configuration Run a serial terminal program on your PC On Windows you can use HyperTerminal Start gt Programs gt Accessories gt Communications gt HyperTerminal and make sure the computer serial port is configured with the following options Bits per second 19200 e Data bits 8 e Parity None e Stop Bits 1 e Flow control None e Terminal Emulation VT100 2 Use the provid
50. end interface It can also be used for the user design in FPGA A UCLK This differential clock input is delivered to FPGA A FBACLK This differential clock is driven from FPGA A and delivered to FPGA A B and This clock can be used for controlled clocks odd clock division and multiplication or forwarding a clock from on FPGA to another FBBCLK This differential clock is driven from FPGA B and received at FPGA A B and HACLK This differential clock is driven from the daughter card header A to FPGA A HBCLK This differential clock is driven from the daughter card header B to FPGA DN8000K10PCI User Guide www dinigroup com 72 DDRACLK DDRBCLK This differential clock is driven by the FPGA to its associated DDR2 SODIMM header A copy of the clock is externally buffered and the clock is received on the FPGA synchronized with its arrival at the SODIMM on the signal DDR FBCLK Clock Name FPGA A pin FPGABpin FPGA C pin ACLKp ACLKn BCLKp BCLKn DCLKp DCLKn FBACLKp FBACLKn FBBCLKp FBBCLKn UCLKp UCLKn SCLK1 AG20 L21 AE18 SCLK2 AL20 P22 AF20 HACLKA 18 L20 SYS CLK AF19 M21 AE21 PCI UCLKA JAH20 All of the signals listed above are point to point That is the BCLKp pin on FPGA and FPGA B are separate equivalent signals 3 1 Global Clocks The three main global clocks are driven by ICS8442 clock synthesizers each capable of produci
51. is lower 4 bits Port 2 is upper 4 bits Select which FPGA PPC s is connected to PPC Port 3 and 4 bits 1 0 01 write address 10 data write 11 data read bits 4 2 r_fpga_state bitb r_fpga_auto_inc when high auto increments fpga after access bit6 r fpga rd done select byte in addr read and data bytes 7 4 GPIF STATE 3 0 FPGA STATE Sets the divider value of GCLKO Sets the multiplier of GCLKO Sets the divider value of GCLK1 Sets the multiplier of GCLK1 Sets the divider value of GCLK2 Sets the multiplier of GCLK2 Various CompactFlash card controls Main txt is read through these registers Disables Main Bus interface Causes reprogramming of onboard synthesizers A checksum of USB configuration data Temperature of FPGA A Temperature of FPGA A www dinigroup com 40 TEMP SENSOR C DF52 SERIAL NUM ADDR DFFA SPARTAN MKS VERSIO N ADDR DFFB SPARTAN VERSION AD DR DFFD BOARD VERSION NEW DFFE BOARD VERSION DFFF Temperature of FPGA A 2 PCI AETEST Application AETEST utility program can test and verify the functionality of DN8000K10PCI Logic Emulation board and provide data transfer to and from the User design All AETEST source code is included on the CD ROM shipped with your DN8000K10PCI Logic Emulation kit AETEST can be installed on a vatiety of operating systems including DOS and Windows 95 98 ME using DPMI DOS Protected Mode Interface e Windows 98 ME using a V
52. or J for connectors FB or L for inductors TP for test points MH for mounting structures FD for fiducials BT for sockets DS for diodes F for fuses HS for mechanicals PSU for power supply modules Q for discreet semiconductors RN for resistor networks X for oscillators Y for crystals lt Y gt is a number uniquely identifying each part from other parts of the same X class on the same PWB lt Z gt is the pin or terminal number or name as defined in the datasheet of the part Datasheets for all standard and optional parts used on the DN8000K10PCI are included in the Document library on the provided User CD 3 2 4 Schematic Clippings Partial schematic drawings are included in this document to aid quick understanding of the features of the DN8000K10PCI These clippings have been modified for clarity and brevity and may be missing signals parts net names and connections Unmodified Schematics are included in the User CD Please refer to this document Use the PDF search feature to search for nets and parts D Schematics REV3 Schematic_DN8000K1 0PCI_503 0121 0000_trev03 pdf 3 2 5 Terminology Abbreviations and pronouns are used for some commonly used phrases MGT and RocketIO are used interchangeably MGT is multi gigabit transceiver is the Xilinx trademark on their mult gigabit transceiver hardware MCU is the Cypress FX2 Microcontroller U39 DN8000K10PCI User Guide www dinigroup com 12 Chapter Quick Start
53. side of the The 1 5843020 01 Frequency Synthesizer is a very low phase noise With the default 25Mhz oscillator the frequency synthesizer is capable of producing frequencies in the ranges 71 875 84 375 143 75 168 75 287 5 337 5 and 575 675 Mhz 10 2 MGT Power network The RocketIO strict power supply constraints require the use of heavy power supply filtering The three power rails are each generated by a linear voltage regulator 10 2 1 FX CES2 rework If your DN8000K10PCI came with the option FPGA C FX60CES2 then a late breaking Virtex 4 erratum required the following rework This rework is not shown in the schematic on the CD DN8000K10PCI User Guide www dinigroup com 106 VCC MGT12 top o 1 217 2 5 1 8V 8 Rework 5 3 VPOWER VOUT Es 4 am 240R VCONTROL 1 SENSE ADJ T158000 R21 150R 100R 1 21V 5 42 5V 1 8 3A VCC 15 5 3 42 5V 4189 VCC MGT12 right VPOWER VOUT TAB o TAB u17 VCONTROL 1 BS 5 3 SENSE 2 100R VPOWER VOUT ADJ TAB R 240R 158007 SENSE z ADJ 158007 R57 150R 100R 6177 78 22R 2 5V 18V MGT12 bottom ug 5 3 VOUT Tag 2 4 240R VCONTROL 1 SENSE gt ADJ Be Ti580d 150R R24 100R Rework Figure 36 MGT 1 1V rework Thi
54. the Xilinx JTAG programming program iMpact 3 1 Updating the MCU flash firmware To protect against accidental erasure the MCU firmware cannot be updated unless the board is put in firmware update mode during power on Find Switch block 1 on the DN8000K10PCI DN8000K10PCI User Guide www dinigroup com 43 Figure 15 Switch block 1 Move switch S1 3 to the ON position Power on the DN8000K10PCI Open the USB Controller program the DN8000K10PCI powered in firmware update mode there will be an Update Flash button near the top of the USB Controller window Click on this button DN8000K10PCI User Guide www dinigroup com 44 DiNi Products USB Controller Settings Info Clear Log Maximum packet size is 0x00000200 512 MCU FLASH VERSION Ox4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION USB to fpga enabled Maximum packet size is 0 00000200 512 MCU FLASH VERSION 0 4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION Figure 16 USB Controller Firmware Update Mode When the Open dialog box appears navigate to the Firmware image file supplied by Dini Group The file name should be flash_flp hex Press OK The USB Controller should freeze for about 10 seconds while the firmware update is taking place When the download is complete the Log window should print Update Complete Move Switch block
55. the junction temperature of the Virtex 4 exceeds 85 degrees the Microcontroller will reset the FPGAs causing them to lose their configuration data An overheating FPGA could be the result of a mis configuration a clock that is set incorrectly or an inadequate heatsink unit The heatsink and fan assembly that comes with the DN8000K10PCI is appropriate for dissipating the amount of heat energy available through a PCI slot without the auxiliary power connector 25W total for the card If you are operating the DN8000K10PCI at very high speeds in stand alone mode and you are causing heat overload resets you may need to install a larger heatsink or increase the system airflow DN8000K10PCI User Guide www dinigroup com 79 011 1 Virtex 4 LX 1513 205 23 PROGRAM B m INIT 95 0 CS B vi DONE PWwRDWN RDWR B 08 DOUT BUSY n Y23 24 z 1 16 0 22 D IN W24 16 VBATT TMS T TMS 16 17 ABI VCCO 0 TDI E OWES VCCO 0 AEA VCCO 0 m R165 1K TEMPA STBY 15 OO FPGA DXP A Ul L 14 50 gt E 12 SMBCLK C280 SDA lt gt SMBDATA DXP 1100pF 1000pF IROn 11 DXN lt lt 1 ALERT FPGA DXN A TEMPA SAI 10 ADDO R168 1K R167 7 3 1K 6 gt gt gt MAX1617A QSOP16 This circuit shows the MAX1617 temperature monitor The IIC bus is connected to the
56. the source Synchronous clock inputs See Chapter X Section X FPGA interconnect 4 Reset Topology The DN8000K10PCI is protected from under voltage and over temperature by a reset circuit When the board powers on a voltage monitor waits until all voltages are above their minimum voltage levels then de asserts reset The Spartan 2 distributes the reset signal to all FPGAs and the Microcontroller unit so until the Spartan 2 is configured reset remains asserted Temperature Monitors 85 deg C FPGAA FPGAA PROG sot PROG Reset gt PROG Y bs 2 Spartan FPGA Voltage Monitor FPGAA RESET FGPAS RESET 2 m 5 88 The user may also assert reset by pressing S3 reset This will trigger the reset signal SYS RSTn which is monitored by the Spartan FPGA When 5 5 is asserted the Spartan FPGA resets the Virtex 4 FPGAs causing them to lose their configuration data and DN8000K10PCI User Guide www dinigroup com 78 deactivate The Spartan also causes a reset the Microcontroller unit which will cause the microcontroller to reload configuration instructions from the Smart Media card USB contact will be lost with the USB host and the DN8000K10PCI will have to re enumerate There is a second button S2 called Soft Reset When
57. this button is pressed the signal RESET FPGAs is asserted This signal is sent to the Virtex 4 FPGAs on a user IO pin and could be used by the user design as a reset signal This signal is also asserted to all FPGAs after any FPGA becomes configured RESET FPGAs is an asynchronous signal 12V 18V 25V 50V 3 3 43 3V 20v x ud 3 3V Reset Circuit R362 oR R373 R367 R358 1K oR R359 124R 845R R364 1K vi RST V2 VREF v3 R371 88 78 u23 RST V2 VREF svs 5 R370 t 1 28 0K 9360 28 0K va VPG e Joja 2 0 1 9 5 6 M le R361 110R wa 2 0 1 R368 8 5 6 222 on C1029 Fisk Toor PBR CRT R357 TC2900 MSOP10 2 7nF GND 71 5K 2500 6 10 ene av vi 3 3v eae x i us 2 2 5V V3 1 8V Vl 3 3V eb V4 ADJ V2 2 5V 0 5 V3 1 8V 3 V4 ADJ 0 5 V HARD RESET The above circuit shows how two LTC2900 voltage monitors are daisy chained together to monitor 5 different voltages Each FPGA is also connected to a temperature monitor The Virtex 4 FPGA can easily overheat if a heatsink and fan are not used The recommended operating temperature for the Virtex 4 is 85 degrees C The absolute maximum temperature for operation is 125 degrees C If at any time
58. this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who ate new to ESD sensitive products http www esda ore basics patt1 cfm There two large grounded metal rails on the DN8000K10PCI The DN8000K10PCI has been factory tested and pre programmed to ensure correct operation reference design is included on the provided CD and SmartMedia The 200 pin connectors are not 5V tolerant According to the Virtex 4 datasheets the maximum applied voltage to these signals 18 VCCO 0 5V 3 0V while powered on These connections are not buffered and the Virtex 4 part is sensitive to ESD Take care when handling the board to avoid touching the daughter connectors 3 Power On Instructions The image below represents your DN8000K10PCI You will need to know the location of the following parts referenced in this chapter 22 DN8000K10PCI User Guide www dinigroup com 15 TS SmartMedia 8 Figure 3 DN8000K10PCI configuration controls To begin working with the DN8000K10PCI follow the steps below DN8000K10PCI User Guide www dinigroup com 3 1 Verify Jumper Setting The DN8000K10PCI uses a jumper to configure the PCI interface IO signal levels Please locate the jumper block on your board and verify that it matches the default settings By defaul
59. 0 Spartan II IO Connections 2 1 4 Spartan Configuration The Spartan 2 FPGA is configured from a Xilinx serial prom The Spartan s configuration mode is hard wired into Master Serial mode After power up the Spartan automatically clocks an external PROM U41 which programs the FPGA over the serial configuration data pin DIN A green LED DS24 lights when the DONE pin is high This signal is driven by the Spartan 2 FPGA when it is configured and running Both the Spartan and the serial prom are connected in a JTAG chain attached to J14 This header is used when performing firmware updates to update the PROM DN8000K10PCI User Guide www dinigroup com 52 Spartan Configuration Prom CFPGA CCLK E Do 50 00 Di 52 0 CFPGA 13 nesem 52 01 7 25 1 Spartan Configuration 3 TSK 08 iaa Interface JTAG CFPGA TDI 7 5 mo cro 0 CFPGA PROGn 30 BE acro I2 PCI UCLKM Eis NS GEOn e Yu SYS DR 26 33 CFPGA CCLK B22 5 GCK oS Nc vcco 25 CCLK 1 SYS gt gt NC 35 BEPRAIDONE a eS Ier 24 EE e NE 33 cerca po lt OH pour 2 282 Master 0 24 NC vecint He PO D20 DIN 2 Serial VCCINT 14 erial 0 4 NC veeint HZ 4 Oo NC CFPGA v19 39 6
60. 000K10PCI are in the largest 1513 ball package to give the user extremely high IO count for high bandwidth and low latency interconnect between FPGAs Three hundred eighty nine differential links between FPGAs and B allow fot as much as 189 Gb s communication between the two FPGAs In order to support enough bandwidth to deliver real time data to your design at speed the DNS8000K10PCI is equipped with an optional Xilinx Virtex 4 FX100 with Multi Gigabit Transceivers Serial connections over Fibre Coax ribbon cable and Coax SMA cables allow for a total aggregate 150 Gb s off boatd communication Monitoring your design and supplying test vectors is simple with an onboard PCI interface bridge chip capable of full 66Mhz 64 bit PCI while reserving 100 of the FPGA fabric for user logic The PCI interface is taken cate of You will be able to communicate to the DN8000K10PCI into a PCI slot right out of the box To allow you to connect the FPGA to the resources that will be on your end product the DN8000K10PCI also has high speed expansion capabilities Below is a block diagram of the DN8000K10PCI DN8000K10PCI User Guide www dinigroup com 49 Ll Samec Cable 1 Lee Expansion Expansion Connector SFP XFP Module Configuration oo ol ole FGPA SUO Spartan II partan 4 Rx TX 7 dock contig Xilinx
61. 0124 Haat TCK A17 AB1 vcco TDI em rS 0 HAE vcco 165 516 1K U4 TEMPA STBY mE 2 STBY vec tl ___ FPGA DXP A SCL 14 SCL CZ 312 SMBCLK lIC SDA 12 3 C280 C428 SDA SMBDATA 4 1100 1000pF IRQn 11 lt ALERT FPGA DXN A TEMPA SAO 5 TEMPA SAT 15 ADDO NG 5 5 ADD1 NC 3 1K R167 7 NOTIS GND NC Hia X GND NC 5 x IAX1617A QSOP1 Above The FPGA temperature monitor circuit The 1617 bus is connected to the Cypress MCU DN8000K10PCI User Guide www dinigroup com 85 Above Cooling fan power connector 6 FPGA interconnect The DN8000K10PCI was designed to maximize the amount of interconnect between the two primary Virtex 4 FPGAs A and B This interconnect was routed as tightly coupled differential LVDS to provide the best immunity to power supply and crosstalk noise so that your interconnect can operate at the full switching speed of the output buffers 6 1 FPGA interconnect Following Xilinx recommendations the interconnect on DN8000K10PCI was designed to operate at 1Gb s for every LVDS pair Note 1Gb s operation requires the fasted speed grade part LX200 12 In order to achieve such breakneck speeds you will need to operate the busses of signals using a source synchronous clocking scheme interc
62. 05 45321 m CAGE d RXNPADB 106 o CAGE MGTCLK P 105 CAGE N 1 N05 888888888 1887073 R109 beth 150R 585585585 dr MGTVREF 105 222222222 10 DS2 200000000 REDLED OPT RSFP LOS ZEE s 52222222 JoSFP1 RED DS6 10 Y RED LED OPT 9 8 mA 2 SFP1_TxFAULT 1 2 ai JQsFP1_LOS 9 8 2 LOS 1 2 as SFP2 voor VCCR SFP2 SFP2 Connector R221 19 Vinex 4 FX 1152 5 R148 1K U10 19 C1056 JNGGAUXE I0 nue NT AUT SFP2 RxD AVCCAUXRXB 109 RXPPADA 109 HABS TXDISABLE 3 SEP TDS 04 109 RXNPADA 109 Clos SFP2 MOD DEF 2 1 Cor 98 1750 APS SFP2 TxDn 7 2 TXPPADA 109 815 mI 2 fon SELEGT 2 sree tos 5 SFP Dn 9 t VEER 1 R150 1k VOCT SFP2 VEER wr T eere VIRXB 109 TXPPADB 109 AHi wv C R149 DNI VITXB 109 TXNPADB 109 VTRXA 109 4 VTTXA 109 o R105 RXPPADB 109 108 1508 150R Ay JRSFP2_FAULT hsre2 105 8888 2 RED AVCCAUXMGT 109 pea e a 5558 zu 1367073 d 10 DS4 W ose 2222 ma REDLED OPTj RED LED 598 x E ASS aupA 109 HANTS Figure 38 SFP modules 10 5 2 XFP FA
63. 1 3 to the OFF position to put the DN8000K10PCI back into normal operation mode Power cycle the board 3 2 Updating the Spartan EEPROM firmware Connect a Xilinx Parallel IV configuration cable to the parallel port of your computer The Parallel IV cable requires external power to operate so you may need to connect the keyboard connector power adapter When the Parallel IV cable has power the status LED on Parallel IV turns ambet Use 2mm cable to connect the Parallel IV cable to the DN8000K10PCI connector 14 DN8000K10PCI User Guide www dinigroup com 45 D L Li jour E Figure 17 Firmware Update Header Power on the DN8000K10PCI When the Parallel IV cable is connected to a header the status light turns green Open the Xilinx program Impact usually found at Start gt programs gt Xilinx ISE 7 1 gt Accessories gt impact Impact may ask you to open an impact project Hit cancel Choose the menu option File gt Initialize Chain Impact should detect 2 devices in the JTAG chain Xc18v02 and Xc2s200 For each item in the chain Impact will direct you to select a programming file for each For the xc18v02 device select the Spartan Firmware update file provided by Dini Group This file should be named prom mcs Hit Open Impact will then ask for a programming file to program the xc2s200 Press Bypass DN8000K10PCI User Guide www dinigroup com 46
64. 120R RFPGAA DONE DS18 x DONE 3 FPGA_DONE_A 11 If your Virtex 4 FPGA design is failing to produce the intended or any results you should check the DONE light above the FPGA to make sure it is configured correctly The design files created by Xilinx bitgen software contain a CRC check so if the Virtex 4 FPGA detects a CRC failure there was a transmission error during configuration and the DONE light will not glow The DN8000K10PCI microcontroller also checks the design files you send to make sure they are compiled for the FPGAs that are installed on your board If they are not then the microcontroller unit halts the configuration process As a result when the DONE light goes on you will know that the configuration process was successful 2 4 MCU The operation of the Spartan II is monitored and controlled by a Cypress CY7C68013 microcontroller The microcontroller also has a USB 2 0 interface that can be used to monitor the board control configuration or transfer data to and from the user FPGA design Basic operation can be controlled over an RS232 link from a computer terminal DN8000K10PCI User Guide www dinigroup com 63 2 4 1 RS232 The primary method of user interaction with the DN8000K10PCI configuration circuitry is the MCU s RS232 port P2 The Cypress CY7C68013 has two RS232 pins that are buffered through a 12V voltage translation buffer for use with a standard com
65. 3 6 3 Read temperature sensors The DN8000K10PCI is equipped with temperature sensors to measure and monitor the temperature on the die of the Virtex 4 FPGAs According to the Virtex 4 datasheet the maximum recommended operating temperature of the die is 85C degrees If the microcontroller measures a temperature above 80 degrees it will reset the DN8000K10PCI If you think your DN8000K10PCI is resetting due to temperature overload you can use the temperature monitor menu to measure the current junction temperature of each FPGA ENTER SELECTION g FPGA TEMPERATURES Degrees Celsius 4 B 29 Set FPGA Temperature Alarm Threshold degrees C decimal values range 1 127 Old Threshold 80 New Threshold 85 Threshold Updated 85 Degrees C Figure 7 Temperature Threshold Menu The Virtex 4 FPGA can operate as hot as 120C degrees before damaging the part although timing specifications are not guaranteed The MCU allows you to change the reset threshold DN8000K10PCI User Guide www dinigroup com 24 although we recommend improving your heat dissipation to maintain a low junction temperature 3 6 4 Multiplex Serial port The DN8000K10PCI has one serial port P1 for user use This single port is multiplexed so that any FPGA can access it through its RX and TX signals You can use the RS232 MCU interface to change the FPGA to which P1 is connected ENTER SELECTION 7 PORT 1 D PORT 2 A PORT
66. 39 6 1432 146 8 150 153 9 157 5 1611 1647 1682 171 8 179 0 1861 193 3 200 5 207 6 2148 2219 2291 2362 2434 2506 2577 2649 2720 2792 286 4 293 5 3007 3078 3150 3222 3293 336 5 2343 6 358 0 372 3 386 6 400 9 415 2 429 5 443 9 4582 472 5 4868 501 1 515 4 5298 5441 5584 5727 587 0 601 4 615 7 630 0 644 3 658 6 672 9 687 3 DN8000K10PCI User Guide www dinigroup com 38 DCLK DCLK is generated from 16 0 Fundamental crystal Supported frequencies 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 12 74 76 78 80 82 84 86 88 92 96 100 104 108 112 116 120 124 128 122 136 140 144 148 152 156 160 164 168 172 176 184 192 200 208 26 224 232 240 245 256 264 272 280 288 26 304 312 30 328 336 336 344 352 368 384 400 416 432 448 464 480 496 52 528 544 560 576 592 608 624 640 656 672 688 3 Change Text Editor This options allows the user to select text editor to use the default editor is notepad 4 FPGA Stuffing Information This option will display the type of FPGAs that are stuffed on the DN8000K10PCI 5 MCU Firmware Version This option will display the MCU Firmware version in the log window 6 BOARD SPARTAN Version This option will display the Board Version along with the Spartan Config Fpga Version 1 1 5 Configuration Register Map The DN8000K10PCI firmware is updated constantly to add compatibility for new products and add features The information in this section may change after this manual is pr
67. 4 PCI interface Due to the available number of IOs on the Spartan 2 FPGA only 32 of the 64 data bits in the Quicklogic interface are connected to 10 on the Spartan 2 Also the Spartan 2 does not connect to any of the signal required for operation over PCI From the PCI host perspective the address range BARO is directed to the Spartan 2 and 1 is directed towatds the Virtex 4 A Since and the Spartan 2 both can access the Quicklogic 5064 back end only one must communicate with the QL5064 at a time The signals SP PCI REQ and PCI are used to control communication with the QL5064 2 1 5 RS232 The DN8000K10PCI has two RS232 headers One P2 is used by the microcontroller unit to provide configuration feedback and control The other P1 15 connected to the Spartan 2 FPGA The Spartan 2 FPGA has one RX and one TX signal connected to each Virtex 4 FPGA The Spartan FPGA will multiplex the RX and TX signals to the Virtex FPGAs to the RS232 header P1 The Spartan 2 internally multiplexes the signals on the user RS232 header P1 to one of these three sets of signals To change the Virtex 4 that has access to the RS232 headers you can use the provided USB application program or you can change the setting on a terminal connected to the Microcontroller unit s RS232 port P2 Since RS232 uses 12V signal levels the RS232 signals from the Spartanll are first buffered through
68. 4 FX 1152 Figure 37 QSE Connector Each connector also has a clock input that can be routed to the MGT CLK of FPGA C to allow standards that require transmitting at an exact frequency such as PCI Express DN8000K10PCI User Guide www dinigroup com 111 10 5 Optical Modules The DN8000K10PCI comes with two optical module connectors If you need to interface to a specific standatd the easiest way is to buy an SFP or XFP module that supports that standard 5 ale m 99999 i ER 22 m d n eo SEP Connector e 4 00 e e se e zs gt mmu i57 mum 9 ed 5 E e BINE m nmmn E MT om ams 2 Es 10 5 1 5 SFP modules support 1 4 5Gbs serial transmission rate There two module options available on the DN8000K10PCI none one or both of which can be SFP or This is a manufacturing time ordering option Two ted LEDs show the status of the channel The LOS LED indicates that the far end transmitter is not operating the cables are not secured or matched to the transmitter wavelength The INT LED indicates The FAULT LED indicates a transmission laser failure or an unsecuted module DN8000K10PCI User Guide www
69. 4LC64 TSSOPB R252 1K Address 00000001 0x01 E RAM Space 0x0000 to Ox1FFF Communication over the MCU memory bus to the Spartan 2 is synchronized to the 24Mhz MCU CLK For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual MCU 480 2 PLL Spartan 2 Memory Mapped 10 Main Bus SYS_CLK FPGA A FPGA C The Configuration FPGA is connected to the 7 0 signals the MCU ADDR 15 0 signals and the OE signal allowing it to decode address accesses of the MCU The Configuration FPGA is programmed to respond to accesses in the XDATA address space in the address range of 0xDF00 to OxDFFF Communication over the MCU memory bus to the Config FPGA is synchronized to the 24Mhz MCU CLK X3 For information regarding the timing of transactions on this bus see the Cypress CY7C68013 user manual DN8000K10PCI User Guide www dinigroup com 66 480 2 PLL IFCLK Spartan 2 Memory Mapped 10 Main Bus SYS_CLK FPGA FPGAB FPGA The following registers implemented in the Configuration FPGA are accessible as part of the MCU s XDATA addtess space Register Name XDATA Description Address DATA DFO00 Used when reading from SM but not configuring COMMAND DF01 Commands for the SM ROW_LADDR DF02 Holds lower 8 bits o
70. 5555 CAGE GND 10 CASE GND e dum RED LED OPT 555555555 CAGE GND x X SEES CAGE GND SRC 0 299 SAGE GND 552142555 LOS RED ol 8 10 92 35 mA wremmuer 1 92 1 892 39V op nw XFP2 Connector Ries piss Rise 187 5 R211 8186 5 Q SIK S SIK lt BIK iai Virtex 4 FX 1152 u7 ANT XFP2 2 XFP2 MOD DESEL AVCCAUXRKA 108 Tb NOD DESEL ecce XFPa MOD DESEL ET 3 Xr DESEL AVGCAUXIX 109 RXNPADA 103 UEM Sls mr XFP TX DIS FPE RXT 17 10 2 SCL TxPPADA 109 HABS soa Ht 2 5 2 Soa 25 z 108 EMI EP P13 AP11 XFP2 REFCLKn NR 14 FPZ HX LO MOD NH 13 109 TXPPADB 108 A Los 14 ee XFP2 AX LOS 2 109 TXNPADE 108 P DOWN P DOWN SARE VIIA 109 0016 0 ves 87 5 He atr RXPPADB 109 voca n p CAGE VCC18 XFP2 51K 9 CARE corte Ca CAGE 2 Gage 84 ace di CAGE T 8 CAGE 3 CAGE GAGE pss pst CAGE Re REDLED OPT M REDLED OPT CASE XFP2 RX LOS Se
71. 6 TxN 31 32 QSE16 RxP A31 B32 QSET6 TxP 33 34 QSET6 AxN AxN 102 AVCCAUXRXA 102 11 E RXNPADA_102 AVCCAUXRXB 102 pee QSE15 38 5 15 AVOGAUXTX 102 5 14 TxP GSETS E 10 QSEIS RN SERA 24 TXPPADA 102 Lx 2 1 TXNPADA 102 pe w y 102 1 1 TG VITXB 102 5331 QSE13 TxP 102 Fea SSE 102 VTRXA 102 034 SE TXNPADB 102 QSE13_RxP RXPPADB 102 AVCCAUXMGT_102 233 5 Note These signals should be routed differential pairs Each of the pairs shall be matched length Each 77 pair must be 100 ohm controlled MGTCLK N 102 342 differential impedance S88888888888828 lt lt lt lt 858885858585885858588 22222222222222 00000000000000 Virtex 4 FX 1152 kdl Ea a E a Iz aa THIS BANK DOES NOT CONNECT ON FX 60 FX 100 Only QSE12_RxP 22 RXPPADA 101 AVCCAUXRXA 10 B80 E RxNPADA 101 AVCCAUXRXB 101 8202 AVCCAUXIX 101 22 2 ISE12 TxP EH TXPPADA 101 REEL HH TXNPADA 101 QSE11_TxP 101 227 322 TXPPADB 101 VTRXA 101 22 6 TXNPADB 101 101 8220 VTTXB 101 a 28 101 RXNPADB 101 8281 GNDA 101 AVCCAUXMGT 101 8285 OBS GNDA 101 0 825 GNDA 101 OBS 101 07 820 GNDA 101 oA GNDA 101 Virtex
72. 76 HBCC AG18 HBP66 AB33 HBN66 AA33 GND HBP72 AE23 HBN72 AF23 HBP74 AH22 HBN74 AJ22 HBP68 23 HBN68 AN22 HBP70 AE18 HBN70 AD17 HBP64 T31 HBN64 030 GND HBP62 M33 www dinigroup com 96 131 62 W35 HBN62 N32 132 60 M33 HBP60 B35 133 HAN60 N32 HBN60 C35 134 58 T31 HBP58 M27 135 58 030 HBN58 L28 136 56 M27 HBP56 M25 137 56 28 HBN56 N24 138 54 B25 HBP52 L24 139 54 A25 HBN52 K23 140 GND GND 141 52 F26 HBP54 K24 142 52 F25 HBN54 J24 143 50 A24 HBP50 H23 144 HAN50 A23 HBN50 G23 145 48 K24 HBP48 J22 146 48 J24 48 H22 147 46 F23 HBP46 L18 148 46 E22 46 18 149 44 124 44 J17 150 44 K23 HBN44 K17 151 GND GND 152 42 N23 HBP42 G18 153 HAN42 M23 HBN42 H17 154 40 E21 HBP40 K16 155 40 D21 40 116 156 8 020 HBP38 J16 157 8 U18 HBN38 H15 158 6 C20 HBP36 B25 159 6 D20 HBN36 A25 160 4 D19 HBP34 A24 161 HAN34 E19 HBN34 A23 162 GND GND 163 2 L18 HBP32 A18 164 HAN32 M18 HBN32 B18 165 0 18 HBP30 A16 166 B18 HBN30 B16 167 28 J17 HBP28 F14 168 HAN28 K17 HBN28 E14 169 HAP26 A16 HBP26 AA14 170 HAN26 B16 HBN26 AA13 171 24 G18 HBP24 AC12 172 24 H17 HBN24 AD11 173 GND GND 174 22 F14 HBP22 P11 175 HAN22 E14 HBN22 R11 DN8000K10PCI User Guide www dinigroup com 97 176 177
73. 84 38 168 75 337 50 87 50 175 00 350 00 The crystal supplied for BCLK is 14 32 Mhz With the 8442 s PLL range possible output frequencies are 32 22 6443 128 86 257 72 34 01 68 01 136 02 272 04 35 80 71 59 143 18 286 36 37 58 75 17 150 34 300 68 39 37 78 75 157 50 315 00 41 16 82 33 16466 329 31 42 95 85 91 171 82 343 63 44 74 89 49 178 08 357 95 46 53 93 07 186 13 372 27 48 32 96 65 193 29 386 59 50 11 100 28 200 45 400 90 51 90 10381 207 61 415 22 53 69 107 39 214 77 429 54 55 48 110 96 221 93 443 86 DN8000K10PCI User Guide www dinigroup com 75 57 27 114 54 229 09 458 18 59 06 118 12 236 25 472 49 60 85 121 70 243 41 486 81 62 00 125 28 250 57 64 43 128 86 257 72 66 22 132 44 264 88 68 01 136 02 272 04 69 80 139 60 279 20 71 59 143 18 286 36 73 38 146 76 293 52 75 17 150 34 300 68 76 96 153 92 307 84 78 75 157 50 315 00 80 54 161 08 322 16 82 33 164 66 329 31 84 12 168 24 336 47 85 91 171 82 343 63 The crystal installed to reference DCLK 15 16 0Mhz Within the 8442 s PLL range the possible output frequencies 32 00 64 00 128 00 256 00 34 00 68 00 136 00 272 00 36 00 72 00 144 00 288 00 38 00 76 00 152 00 304 00 40 00 80 00 160 00 320 00 42 00 84 00 168 00 336 00 44 00 88 00 176 00 352 00 46 00 92 00 184 00 368 00 48 00 96 00 192 00 384 00 50 00 100 00 200 00 400 00 52 00 104 00 208 00 416 00 54 00 108 00 216 00 432 00 56 00 112 00 224 00 448 00 58 00 116 00 232 00 464 00 60 00 120 00 240 00 480
74. 9 18 29 D17 65 HAN29 F18 29 17 66 GND 67 27 B17 HBP27 G16 68 27 C17 27 G15 69 25 D17 HBP25 E26 70 25 E17 HBN25 D26 71 23 G16 HBP23 D25 72 23 G15 HBN23 C25 73 HAP21 AB15 HBP21 D24 74 HAN21 AC14 HBN 1 C24 75 19 K16 HBP19 C23 76 HAN19 L16 HBN19 B23 77 GND 78 17 M17 HBP17 D22 79 17 N17 HBN17 C22 80 HAP15 E8 HBP15 E21 81 15 F8 HBN15 D21 82 HAP13 G7 HBP13 C20 83 1 G6 HBN13 D20 84 HAP11 AA14 HBP11 C19 85 11 13 11 18 DN8000K10PCI User Guide www dinigroup com 95 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 HAP9 AB13 HAN9 AC13 GND HAP7 HAN7 U1 HAP5 AK29 5 AJ29 NC 27 AR27 RESETN HAP1 AJ34 HAN1 AH34 GND NC 12V GND HACLKA NC GND 3 3V NC GND GND GND GND ACLKHAP ACLKHAN PDETECTA HAP76 HACC P20 HAN76 HACC N20 NC NC GND NC NC NC NC NC NC HAP66 AC33 HAN66 AC34 HAP64 R36 64 T36 GND HAP62 W34 DN8000K10PCI User Guide HBP9 B17 HBN9 C17 GND HBP7 U5 HBN7 V5 HBP5 AJ4 HBN5 AH4 NC HBP3 AT1 HBN3 AR1 RESETN HBP1 T1 HBN1 U1 GND NC GND HBCLKA NC GND 3 3V NC GND GND GND GND ACLKp ACLKn PDETECTB HBP76 HBCC AH18 HBN
75. 98 vay Ag ag IO L22N 6 TI ABpz4 499R RBNiS Ca4 122 5 10 30 5 3T ABNZT VRP A6 AB 10 23 VRN 6 LH 24 32 5V VAN Bs 0 122N 5 10 130 5 B36 Eg 23 6 110 25 _ 5 9 L23P_VRN_5 10_L31P_5 7837 ABNiO R7 49 98 L24P CC LC 6 6 ABUS B35 IO L23N VRP 5 IO 131 5 130 ABP24 0 8 i0 t24N CC LC 6 Ria Deer IO L24P CC LC 5 IO LS2P 5 BOR OSE io Lean CC LC 5 10 L32N 5 pS pipa pipi pipi pp pd 9999999999 9999999999 SSSSSSSSSS SEAR SESS 25 42 5 DN8000K10PCI User Guide www dinigroup com 86 Clocking incoming data at high speeds required the used of the each input s delay buffer to align each bit The incoming clock needs to be adjusted and used to clock the inputs within its lane This process can be automated by the use of the new Virtex 4 feature IDELAYCTL For detailed description of the required user design to achieve 1Gbs operation see Xilinx Application note XAPP704 High Speed SDR LVDS Transceiver Synchronous clocking and single ended signaling are still possible on the DN8000K10PCI you are not required to use high speed serial design techniques Single ended interconnect is recommended for signaling below 133Mhz Because of the DN8000K10PCT s excellent low skew clocking network global synchronous clocking should work fine for your interconnect at speeds lower than 300
76. A FPGA A FPGA A FPGA A FPGA A FPGA A FPGA B FPGA B FPGA B FPGA B B B B B FPGA B FPGA B FPGA B FPGA B FPGA B B FPGA B B FPGA B FPGA B FPGA B B FPGA C FPGA C 0x0C000000 0x0C000004 0 0 000008 0 0 00000 0 0 000010 0 0 000014 0 0 000018 0 0 00001 0x0C000X XO 0x0C000X X4 0x0CO00X X8 0x0C000X XC 0x10000000 Ox17FFFFFF 0x18000002 0x18000004 0x18000006 0x18000010 0x18000011 0x18100001 0x18100002 0x18100003 0x18100004 0x18000001 0x18000003 0x18000005 0x18000007 0x18000008 0 1 000 0 1 000 4 0 1 000 8 0 1 000 0x20000000 OxZ7FFFFFF DN8000K10PCI User Guide OUT OE IN Name ABP1 OUT ABP1 OE ABP1 IN ABP1 Name BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 B space IDCODE INTERCONTYPE RWREG LED_OE LED_OUT CLK_COUNTER CLK_COUNTER CLK_COUNTER CLK_COUNTER DDR2HIADDR HIADDRSIZE DDR2SIZEHIADDR DDR2TAPCNTO DDR2TAPCNT1 BUS XX OUT BUS XX OE BUS XX IN BUS XX Name DDR2 space W the output state of FPGA IOs connected to the ABPO interconenct bus W The ouput enable of each FPGA IO on the ABPO interconnect bus The input state of each FPGA IO on the ABPO interconnect bus ABPO ascii W 1 IO output values W Outpu
77. AN_LC DS IO L2N GC VRP LC 3 IO L3P GC LC 3 NE i GC LC 3p IO LAN GC VREF LC IO L4P GC LC 3 IO L5P GC LC 3 IO L5N GC LC 3 IO 16 GC LC 3 IO LeN GC LC 3 IO L7P GC LC 3 IO L7N GC LC 3 IO L8P GC LC 3 VCCO VCCO 3 IO L8N GC LC 3 u 011 4 Virtex 4 LX 1513 DN8000K10PCI User Guide z dM DNBOOOKIOPCI www dinigroup com 77 To use this clock in a synchronous design send a copy of the clock out through the FBA Feedback A clock output pairs A B and C For a chart of clock input pad sites on each FPGA use the provided bioard netlist the schematics or the example UCF file provided with the reference design 3 3 Feedback Clocks User FPGA and B each are capable of sourcing a clock that is distributed to all FPGAs including back to itself These feedback clocks allow the user to control a clock from inside the user design for single stepping multiplication division or distributing a clock to which only one FPGA has access like PCI clock a header clock or the user clock input has 6 feedback outputs one differential pair to each Virtex 4 FBACLKAp FBACLKAn FBACLKBp FBACLKBn FBACLKCp FBACLKCn B has 6 feedback outputs one differential pair to each Virtex 4 FBBCLKAp FBBCLKAn FBBCLKBp FBBCLKBn FBBCLKCp FBBCLKCn Clocks can also be exchanged from one FPGA to another on
78. C28200 F4 43 3V SM POLYSWITCH C1027 C1028 Figure 22 Smart Media interface The Smart Media data bus D 0 7 also connects to the microcontroller Currently the MCU connection is not used The Microcontroller is able to read from the Smart Media interface by accessing the Spartan s memory mapped data over the MCU memory interface for the purposes of reading instructions from SmartMedia catds DN8000K10PCI User Guide www dinigroup com 53 For instructions on creating a Smart Media card for configuring the DN8000K10PCI see the section Configuration Options Smart Media 2 1 3 MCU communication The MCU communicates to the Spartan 2 FPGA over it s external memory interface pins 00 7 and A0 15 The Spartan 2 is assigned the address range OxDFOO to OxDFFF in the Microcontroller s memory space The 480Mbs data rate of USB 2 0 is too fast for the microcontroller to control so the MCU s hardware passes USB bulk transfer data to the MCU GPIF interface These signals SM 0 7 and GPIF_CTL GPIF RDY connect to the Spartan FPGA The SM 0 7 signals also connect to the SmartMedia card socket although the MCU does not communicate with the SmartMedia interface directly The MCU IFCLK signal provides a clock for this interface The signal is driven from the Spartan 2 FPGA 2 1 4 PCI communication To enable configuration over PCI the Spartan 2 is connected to a subset of the Quicklogic 506
79. Cypress microcontroller 4 1 User Reset The three Virtex 4 FPGAs are also connected to a user reset signal This signal is asserted after the FPGAs are configured from the USB GUI controller or using the Soft Reset button on the DN8000K10PCI Signal Pin on Pin on Pin on Name FPGAA FPGA B FPGAC RESETn 19 K21 AG18 5 Power The DN8000K10PCI gets is power from the 5 0V and 3 3V rails of the PCI card edge connectot It can also be operated in stand alone mode with a 20 power supply connector The PCI slot is capable of sourcing The main tails of the DN8000K10PCI are 12 This is the main power supply rail used for the internal digital logic of Virtex 4 FPGAs DN8000K10PCI User Guide www dinigroup com 80 18V This is used for IO signaling and internal logic of DDR2 SDRAM memory It is also used to supply some Gigabit optical modules and is used as low power current source to supply RocketlIO isolated power rails 2 5V This is used to power FPGA interconnect with low power LVDS It is also used as the analog power supply on the Virtex 4 FPGAs 33V This voltage supplies the LVDS clock distribution trees It is also used to power the LVTTL interfaces of the Cypress microcontroller and Quicklogic 5064 PCI bridge 5 0 This voltage is used to supply power to the 1 2 2 5 and 1 8V switching power supplies It also powers the FPGA cooling fans some Gigabit optical modules an
80. D M QL RD FETCH OUT QL UUNE QL DMA FULL TOL DMA TL FULL Virtex 4 Spartan 2 Quicklogic 5064 RESET SPARTAN READY The above diagram shows the signal connections between the Quicklogic Cyclone and Stratic FPGA Data from BAR 1 5 is transferred from the QL5064 to the Stratix FPGA over the 64 bit QLDATA_IN and OUT busses Data on BAR 0 is transferred from the QL5064 to the Cyclone FPGA over the lower 32 bits QLDATA_INO 31 QLDATA OUT0 31 To access the interface follow these steps 6 Write the 32 bit 4 byte MainBus address you wish to access to BAR 0 offset 0x240 This sets the Cyclone s main bus address register This also causes main bus address latch to occur over main bus 7 read from main bus at this address read 4 bytes from BAR 0 offset 0x250 This will cause the Cyclone to read from main bus and return the 32 bit result After this is done the Cyclone will increment the address in its address register so consecutive addresses can be read by reading from this offset multiple times It will then cause a main bus address latch to occur To write to an address on main bus write 4 bytes to BAR 0 offset 0x248 After a write is completed the Address register incrememnts by 1 then
81. DD2 2 TEAS VREF IN is DIMM VIT C957 R326 3 3 R27 10K 09V SHDN 12 3 LDIMM VIT c DIMM VIT 010 1K 1 SHDN vrg 1 958 988 5994 0 9 10 3 3uH il 150uF 150uF 0 1uF VFB 6 3V Tem C956 4 T 206 206 5 ae PGND1 B 0 001uF 87 vrer our H4 TANT TANT AGND 17 DIMM_VREF 8 PKGGND s 55547 5 16 R316 1K The ML6554 produces up to 3A of the required 0 9V termination power rail along with a stable 0 9V reference voltage supply DN8000K10PCI User Guide www dinigroup com 83 5 2 2 RocketlO power MGT12 top U10 16 FB10 R34 T33 VCC MGT12 1 103 MGT12 1 103 FB17 12 top T34 RXPPADA 103 AVCCAUXRXA 103 AE33 VCC 2 2 103 MGT12 2 103 FB13 8 RXNPADA 103 AVCCAUXRXB 103 yas CC MGTT2 3 103 3 103 AVCCAUXTX 103 8 ae C26 L cao TXPPADA 103 P 58 0 22 3 34 TXNPADA 103 i iom qur 5 FBIS VTRXB 103 MGT15 1 103 MGT15 1 d 4 103 easy STIS 3 10 T c28 103184 MGTi5 4 103 MGTI5 4 103 8 025 FB12 022uF ET VTRXA 103 8 C27 14 0 22uF 103 C24 Fen p 022uF BASS TXNPADB 103 L 022 5
82. EST 11 C934 i8pF ACRYSn 30 M1 TEST 1 gt ACLK NC NO generator 23 23 4 48 XTAL SEL x vco SEL SCLK ACLK SCLK 18 2 n ALLCLK 19 ALLCLK SDATA SDATA ALLCLK SLOAD ALLCLK SLOAD 20 SLOAD z 33V APLOAD 26 R281 ALLCLK SRST 17 8 GND vec 13 GND vec CSBAA2 LGFP32 ALLCLK SRST Figure 29 8442 Clock synthesizer The 3 ICS8442 clock synthesizers on the DN8000K10PCI used for generating the global clocks ACLK BCLK and DCLK share a serial configuration bus connected to the MCU to program them The ICS8442 frequency synthesizers are capable of multiplying and dividing the reference frequencies provided by their reference crystals The MCU loads the user s desired multiplication value and division value into the settings registers in the ICS8442 chip 2 4 3 LEDs The is connected to 4 red LEDs that are visible from outside the PC case when the DN8000K10PCI is plugged into a PCI slot The LEDs flash a status code during and after configuration four flashing LEDs means there has been an error configuring at least one FPGA 2 4 4 Memory space The XDATA memory space of the MCU is partitioned into four sections 0 0000 0x1 FFF internal data program memory 0x2000 OxCFFF external SRAM OxDFFO 0xDFFF memory mapped registers no exter
83. Eig 9 18 6 IO L14N 6 812 LABNE E29 10 L6P ADC3 5 10 1148 5 ABNIS ABRE Fig 1017 6 IO L15P 6 Fait ABn17 10168 ADC3 5 10 L14N 5 ABPS 01746 IO L15N 6 B amp ABNO Ase 10 17 ADC2 5 IO L15P 5 esa ABNS Der CC ic 6 IO LI6P 6 Pas ARAE 00 028 10 17 ADC2 5 10 L15N 5 E31 ABP3 BS io rev CC LC 6 10 L16N 8 12 531 IO L8P ADC LC 5 IO L16P 5 E37 OPL io CC LG 5 10 LIN 5 6 10 L25P CC LC 6 ACE a HB ETUR 19 281 0046 6 Lote mer 118 _6 iO L26P 6 E7 C30 01174 5 IO 125N CC LC 5 Ci2 IO L18N 6 10 L26N 6 Fags ABpz0 TABNTS Hag 10 L18P 5 10 126 5 P33 RENZ ABno Dig 10 119 6 Ip 127 6 B6 20 BABP14 B32 10 118 5 IO L26N 5 H30 ABP1 Aep B7 O L19N 6 10 L27N 6 10 ABN Baa O Li9P 5 IO L27P 5 80 ABNT 8110 Cr 101202 6 10 L28P 6 55 2 8 1 429 10 119 5 10 L27N 5 25 pis O L20N VREF 6 0 Le8N VREF 6 SENT ee IO L20P 5 IO L28P 5 232 822 EY IO L21P 8 IG 298 6 HE pa 120 VREF 5 10 L28N VREF 5 ass ABP20 610 10 12146 Ho ABp23 ABNi7 Bai O L21P 5 IO L29P 5 A38 2 Hio 10 122 6 GB 23 R17 BABP19 Cas 0 121N 5 IO L29N 5 igi ABP21 25 RB 49
84. G FPGA E 10 FPGA FPGA TDI Hx i8 14 JTAG FPGA AG ERES Bh Figure 25 FPGA JTAG Header The JT AG signals TMS is bussed to all three Virtex 4 FPGAs connects to FPGA A the TDO of FPGA is connected to TDI of FPGA B the TDO of FPGA B connects to the TDI of FPGA C of FPGA C is connected to the TDI of J13 is buffered and passed to each FPGA in a point to point fashion Note These signals should be matched length JTAG Clock Buffer U32 1 RFPGA R278 33R JTAG FPGA TCKA 3 BUFIN CLKO WA JTAG FPGA TCKA 5 _ 8279 JTAG FPGA _FPGA eua 7 _ R27i JTAG FPGA TCKB 5 JTAG FPGA TCKC i a HgO CLK6 Hie H X CLK8 49 X 42 5V 19 NT 2 ano von 4 FPGA JTAG AVDD 4 10 GND VDD Hig 17 Yee 0851 41 0826 C914 8 10uF 0 1uF 2 9100 21 10V 20 TANT Figure 26 TCK buffer Ihe INITn signal is not used DN8000K10PCI User Guide www dinigroup com 56 011 1 FPGA CCLK A 20 FPGA CCLK A CCLK selection Slave FPGA PROGn A wee PROGRAM_B HSWAPEN 395 Select FPGA INITn A yas INIT o electmap FPGA CSn yig CS_B 5 H DONE 5 FPGA RD WRn A FPGA_ADWRn A 318 PRDWR B PWRDWN B Ho R226
85. GT tiles are connected as follows MGT A MGTB COLO TILEO QSE 1 QSE 1 COLO TILE1 QSE 1 QSE 1 DN8000K10PCI User Guide www dinigroup com 127 INTRODUCTION TO THE SOFTWARE TOOLS COLO TILE2 SFP 1 REFCLK1 1 COLO TILE3 LOOPBACK SMA J22 COLI TILEO QSE 0 QSE 0 COLI TILE SMA 31 SMA J25 COLI TILE2 NC SMA J17 COLI TILE3 XFP2 SFP2 REFCLK2 250MHz EPSON REFCLK 1 ICS 84020 Synthesizer DN8000K10PCI User Guide www dinigroup com 128 4 RCLIG RELEG mk FPGA aCLK 4 0 000 SCLK1 9 009 CLRI 6 008 Fress any key to quit clock frequencies Current reference clock frequency is 48 0 DN8000K10PCI User Guide BCLK 132 452 SCLKZ 6 600 RCLK4 0 000 RCLK3 0 000 MCLK4 0 080 6 600 SCLKZ 8 000 RCLK4 8 000 RCLK3 6 808 MCLK4 9 009 INTRODUCTION TO THE SOFTWARE TOOLS DCLK 32 638 RCLK8 8 888 RCLES 8 888 HCLKO 6 600 MELES 8 600 92 698 SYSCLK 48 888 RCLK1 8 000 RCLEG 6 660 HCLE1 6 000 8 880 48 608 RCLK1 8 000 RCLKG 8 888 8 080 HELKO 8 888 SYSCLK 8 800 refresh every second 080808 Mhz 129 INTRODUCTION TO THE SOFTWARE TOOLS Mis TEST WITH ANY DAUGHTER BOARDS PLUGGED Uerbose output 9 11 72 Pause on Errors default M y M y Loop default Y Y n n Random test data d
86. GT11 XFP1 REFCLKN AK34 XFP1 INTERRUPT N AD9 XFP1 MOD ABS AK9 XFP1 MOD DESEL 14 XFP1 MOD NR AL9 XFP1 P DOWN AD12 XFP1 RX LOS AE12 XFP1 SCL AE11 XFP1 SDA AD11 DN8000K10PCI User Guide www dinigroup com 108 AD10 AP9 AP10 AP6 AP7 109 GT11 X1Y1 AP11 AP12 109 GT11 1 0 XFP2 INTERRUPT N XFP2 MOD ABS XFP2 MOD DESEL SFP1 TXFAULT SFP1 MOD DEFO SFP1 MOD DEF1 SFP1 MOD DEF2 SFP2 TXFAULT SFP2 RATE SEL SFP2 MOD DEFO SFP2 MOD DEF1 DN8000K10PCI User Guide www dinigroup com AG15 AK16 AF15 AF10 AH15 AG10 AJ10 AH10 AJ16 1050711 AP9 AP10 6 1096711 1 0 8 AK8 AB12 AL8 AC13 AD14 109 SFP2 MOD DEF2 SMA connector J22 RIO SMA TXPO 106 GT11 0 0 423 RIO SMA TXNO 420 RIO_SMA_RXPO 421 RIO SMA RXNO J16 SMA TXP1 1106711 X1Y2 J17 RIO SMA 1 J18 RIO SMA RXP1 J19 RIO SMA RXN1 J33 RIO SMA TXP2 112 GT11 X1Y5 J34 RIO SMA TXN2 431 RIO SMA RXP2 432 SMA RXN2 425 RIO SMA TXP3 1126711 1 4 426 RIO_SMA_TXN3 427 428 Other Loopback TXp AP23 106 1 TXn 22 RXp 26 RXn 25 NC AF1 1106711 1 TXn AG1 NC RXp AC1 NC RXn AD1 10 4 Samtec Multi Gigabit ribbon cable For board to board high density connections two Samtec ribbon cable connectors J2 and 3 are connected to RocketIO T
87. I IE ED RC ED 37 1 1 4 Settihgs Info Menu inni bna ir UH ED EE TENERO TA EHHERR NATURE TENUERE IRA 38 2 oon te 41 2 1 FUNCTIONALITY 2 2 BRUNNINGAXETBS 2 3 COMPILING AETEST 2 3 1 Compiling AETest fOr DOS iis veta i Pg ca e ORE XP 42 2 3 2 Compiling AETest for Windows XP 43 3 UPDATING THE FIRMWARE 43 3 1 UPDATING THE MCU PLASH FIRMWARE ERR ETE REP EQR DAR ETERNA ERAN EAM ERES 43 22 UPDATING THE SPARTAN EEPROM 2 2 00 2 22 00000000000000000000000 00 0 00 000 45 HARDWARE 2 4 004 SALAD DTP 49 5 CONFIGURATION CIRCUIT ERROR BOOKMARK NOT DEFINED 5 1 OVERVIEW AED 50 5 2 THE SPARTAN 2 FPGA 201 5 2 1 Spartan Configuration 52 5 2 2 Smart Media 38 222 MCU communication 54 5 2 4 POL COMICON e 54 5 25 5 2 6 5 3 5 3 1 5 3 2 5 3 3 5 3 4 54 5 5 5 5 1 5 5 2 5 3 22 FEEDS pte rei NATIVO t 65 5 5 4 5 5 5 5 5 6 6 1 6 2 6 3
88. L18N VRP LC 1 IO L34N LC 1 R24 R5 49 9R OLIP 1C 1 IO L35P LC 1 HARTE HAp32 iia L19N LC 1 IO L35N LC 3 2517 8 IO L20P 1C 1 L36P LC 1 HApi8 Foa 10 1200 VREF LC 1 IO L36N VREF LC 1 pas HAp53 E22 IO L21P 1C 1 IO L37P LC 1 G58 RHAn53 Hap O L21N LC 1 IO L37N LC 1 pz HAp25 HAn24 L22P 16 1 IO L38P LC 1 Herr 65 100 IO L38N LC 1 gas HAp54 523 L23P 1C 1 IO L39P LC 1 7355 RHAn53 29 IO L23N LC 1 IO L39N LC 1 7 2 5 Fia L24P 1C 1 IO L40P LC 1 Herr IO L24N LC 1 L40N LC S goooooooooooQo 0000000000000 8000000006000900 SSSSSSSSSSSSSS 95 VHDRA_ 2 5V VHDRA R9 0 3 3V R171 0 On both Header A and Header there is a bank that is dedicated entirely to the Headers For details about Virtex 4 IO banks see the Virtex 4 user guide This bank can be used for standards DN8000K10PCI User Guide www dinigroup com 93 requiring a threshold voltage reference such as SSTL You can also use this bank for source synchronous clocking Header Pin Signal FPGAA Signal FPGA B
89. Mhz The source synchronous clock signals can also be used as single ended or differential interconnect or to forwatd clocks from one FPGA to another The total interconnect counts between FPGAs e 378 e B C154 e 112 The following signals should be used for the source synchronous clocking requirements of the serdes inter fpga interface Each bank of interconnect requires a single source synchronous clock in each direction FPGA to B signals in bank 0 should be clocked using ABCLKp0 ABCLKn0 Signals in the same bank in the opposite direction should use BACLKp0 and BACLKn0 as a source synchronous clock These clock signals should be driven as LVDS signals and received using the DIFF_TERM attribute AAA Signal Name FPGAA pinon FPGA C FROM A TOC ACCLKNO C2 AE31 ACCLKN1 U2 21 ACCLKPO C3 AE32 ACCLKP1 U3 AL21 FROM CACLKNO G1 AJ30 CACLKN1 M2 AL28 CACLKPO F1 0 28 AAA Name FPGAB on FPGA C DN8000K10PCI User Guide www dinigroup com 87 FROM B TOC BCCLKNO BCCLKN1 BCCLKN2 BCCLKPO BCCLKP2 FROM C TO B CBCLKNO 1 CBCLKN2 CBCLKPO CBCLKP1 CBCLKP2 G37 AA39 W30 G36 Y39 W29 D39 W39 AJ37 C39 V39 AJ36 E29 G20 D15 F29 F20 D16 C32 E21 H7 D32 D21 G7 AA Clock Ato B pin on FPGAA on FPGA B FROM A TOB ABCLKNO ABCLKN1 ABCLKN2 ABCLKN3 ABCLKN4 ABCLKN5 ABCLKN6 ABCLKPO
90. O CKE1 gt ILE gt DIMMB CKE1 83 VOD VDD DIMMB 415 R348 DIMMB BA2 Lam xz as NG x R347 DIMM_VTT 1K FTE 87 88 STE 1K Q DIMME ATZ 89 YOD VOD 85 RN23 DIMMB 45 12 All ep DIMMB A DIMMB DIMMB_AS 93 9 AT 94 DIMMB DIMME AF TIE 95 6 96 TTE DIMMB AZ DIMME A5 97 VOD von DIMME AT DIMMB DIMME A3 98 5 DIMMB AZ DIMMB 102 DIMMB 18V 103 1 104 18V 56R DIMME ATO 105 VOD VDD 106 DIMME EAT DIMME BAT 107 A10 AP 108 DIMME RAST DIMMB WEn C J 87 109 WE i 510 DIMMB Sn0 DIMMB CASn 113 MOD 114 DIMMB ODTO p rorem ru Heer em DIMME CDTT 118 VDD DIMMB 121 NC H52 DIMMB DQ32 tiz bes Pic i24 f DIMMB DIMM VTT DIMME 05233 125 Hed 5 126 DQ37 9 127 VS VSS 128 omme pasna 29 WSS VSS 130 7 DimmB LAS DIMME 0054 131 132 13371 2755 m34 f Dose DIMMB DQ34 39 535 Dass Base 56 DQ35 vss H38 4 DIMMB pasa DIMMB DQ40 tome Heres 142 D 1118 0045 56R DIMMB DO41 143 144 145 0041 VSS 146 DIMMB DaSns DIMM VIT DIMMB 5 turvas 0955 148 DIMME DOSS RN24 DIMMB_DQ42 151 1 152 DIMMB 0046 DIMMB BAi 1 DIMME 0043 153 0042 0046 7154 70047 DIMMB RASn 2 155 0043 0047 156 DIMMB DO48 157 SS VSS 158 DIMMB DQ52 DIMMB A13 159 0048 0952
91. The NT Group LOGIC Emulation Source DN8000K10PCI User Guide LOGIC EMULATION SOURCE DN8000K10PCI User Manual Revision 3 February 2 2009 6 05 PM The Dini Group 2005 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support a dinigroup com www dinigroup com Table of Contents ABOUT THIS 1 2 3 MANUAL CONTENTS siscesscscssssssssstcevsssnecnsaccesveseshssecnssasvescsssseenssssudubsd uvensnastevetesuseesesscsedsvessensnssvesedeteadnvonssasdecksasesensscents 9 ABOUT THIS MANUAL 49 QUICK START GUIDE 9 BOARD HARDWARE 59 CONTROLLER SOFTWARE ud REFERENCE DESIGN S 9 FPGA DESIGN GUIDE ERROR BOOKMARK NOT DEFINED ORDERING INFORMATION EL X EL UH NE 9 ADDITIONAL HOTO BEIDE 9 10 3 1 10 3 2 CONTENT 11 3 2 1 File names 3 2 2 Physical orientation and Origin 3 23 Part Pin 0005 12 3 2 4 Schematic Clippings n snio ein ERREUR ERREUR PREIS 12 3 2 5 Terminology scs 12 QUICK START GUIDE 7 1 2 3 PROVIDED MATERIA S c 14 ESD WARNING 15 POWER ON SER RIO CO CP
92. The PCI interface on the DN8000K10PCI is primarily used directly by the Virtex 4 FPGA The Quicklogic 5064 implements the PCI interface and delivers the data directly over the OL interface to FPGA A However when the host machine makes a read ot write transaction to the DN8000K10PCI on a BARO address over PCI the data is instead delivered to the Spartan 2 configuration FPGA This allows the Spartan 2 to configure FPGAs change other configuration settings or communicate to FPGAs B and C over PCI The program AETest supplied on the User CD along with the AETest source code allows the user to configure FPGAs and change configuration settings over PCI When used with the Dini Group reference design or if the user has created a compatible Main Bus interface the AETest program can also communicate directly to the A and C designs 2 2 4 1 Configuration To configure an FPGA over PCI the host program writes the following instructions to BARO of the DN8000K10PCI First the host instructs the Spartan 2 FPGA to select an FPGA for configuration Write one word of data to BARO 0x0208 The data 0x11 represents FPGA A 0x12 is FPGA B 0x13 is FPGA C Next the host instructs the Spartan 2 FPGA to assert the PROGn signal Reset of the selected FPGA s SelectMap interface This causes the FPGA to un configure regardless of the reconfiguration setting made by the bit file s reconfigure setting The PROGn signal must be asserted once
93. ULT 2b DA RED SFP2_TxFAULT1 2 10 ony ka 10 2 Los mA 2 LOS modules the only 10Gbs optical module that allows for multiple signaling standards There are two module options available on the DN8000K10PCI none one or both of which be or SFP This is a manufacturing time ordering option The specification allows for an optional 5 2V power supply to be provided by the host board for ECL transmitter modules The DN8000K10PCI provides no 5 2V power so a mounting point U1 is provided for the use of a bench supply if ECL signaling is required 9 E Hun 816 DN8000K10PCI User Guide VEES XFP L5 Ut VES poe xrP C453 i gt 6496 10V DNI TANT 0 tuF 20 support www dinigroup com Mounting Holes for 5 2V 113 Some XFP modules may requite a reference clock to retime the transmitted signal The REFCLK signal in the specification The REFCLK signal is connected to a RocketIO output on FPGA C The REFCLK signal should be 1 64 of the data rate driven onto the XFP s TX pins To drive this signal See Xilinx Application note XAPP656 To meet the input requirements of the XFP module you must increase the differential swing voltage of the MGT transmitter outputs Set DAC to 800mV
94. a cable Note that all tiles will not pass this test because one of QSE has more channels than the other LOOP should always pass Some of the tests ie print ignored if there 15 a failure These tests are expected to fail because XFP connectors are not installed on your board 6 Getting More Information 6 1 Printed Documentation The printed documentation as mentioned previously takes the form of a Virtex 4 datasheet and a DN8000K10PCI User Guide 6 2 Electronic Documentation Multiple documents and datasheets have been included on the CD 6 3 Online Documentation There is a public access site that can be found on the Dini Group web site at http www dinigroup com 6 4 Before seeking support The following mistakes ate the most common reason a design does not work on the DN8000K10PCI Please do the following self checks before seeking support from the Dini Group Make sure that the clock your design uses is running by routing it to an external test point or LED Check the pinout in your constraint file Use the UCF file provided on the user CD for LOC constraints netlist of the DN8000K10PCI is provided on the User CD Check the PAR report file to make sure that 100 of your IOBs used have LOC constraints There is never a situation where pins should not be 100 constrained Use the PAD report to make sure your constraints were applied correctly Some situations can cause the Xilinx tools
95. a core that provides a way to program the Virtex 4 over PCI USB and SmartMedia The Spartan FPGA is connected to the Cypress microcontroller s address and data busses and the control registers within the Spartan II that control configuration are memory mapped into the MCU s address space DN8000K10PCI User Guide www dinigroup com 51 Y 1 Cypress uController Flash SRAM 24Mhz fo E dic 211717 211 2 D A 9 lt x gt NS Pra PREND GPIF 8 CLK 48Mhz in res MB 40 PORE PROM ID CFPGA 3 gt TDI SYS CLK 3 TD TDO SCLKi 3 FPGA SCLK273 LEDs 14 LED 4 RESET 4 LED 4 i SELECT 34 id TM RS232 RX73 d FPGAB Switches 9W 4 Spartan 2 FPGA 2 54 RS232 M FPGAC 232 Cable 85232 DATA OUT 32 1 1 Quicklogic 5064 DATA IN 32 mio 1 8V PCI Control 55 Mp M 2V EFE 83V voltage gt PCI 5 0V Monitor 12 s5v l Buffer 25V 1 4 8 Buttons JTAG Header Figure 2
96. a voltage translation buffer shown below DN8000K10PCI User Guide www dinigroup com 54 RS232 ppc P1 2 RS232 TXD3 4 8232 TX S MCU TX 8 T20UT 22 5 24 2 E 8 3 RS232 RXD3 x RS282 RX S 13 HS x Hox MCU RX R2OUT R2IN 10 16 GND 124 Lour 11 15 GND RS232 MCU swour swn H 24 P2 c2 E SHDN e 2 23 3 4 31 1 vec 23 3 icr 14 7 44 62 Ho 4 ox c1 0 1uF ex 2 29 2 v 2 0 22 GND AXSSBBE TSOP24 Figure 23 RS232 buffer On the back side of the DN8000K10PCI there ate two duplicate RS232 ports P7 and P8 that be used if an installed daughter is covering the headers on the front These duplicate headers are not installed by default but be installed on request They compatible with a surface mount 5x2 0 1 header 2 1 6 There is a single bus on the DN8000K10PCI connecting all enabled chips on the board On this bus are three MAX1617A temperature sensing chips U3 U4 U24 two DDR2 SODIMM sockets and a serial EPROM The temperature sensors on the bus are polled about once per second by MCU to read the temperature of each FPGA 2 2 Configu
97. ace It then reads back the data verifies it is the same 5 3 Interconnect Test DC This test requires the MainTest bitfiles The single ended interconnect test tests the DC connectivity run the interconnect test you must select from the FPGA reference design menu DN7 8000K10PCI interconnect A dialog box will appear asking which type of test Select Single Ended The status of the test will print in the log window The USB Controller has access to the output value output enable and input value of each intercoonect pin The register banks connected to the IO are arranged into busses Each bus has an ID code a OE register bank a ENABLE register bank and a IN register bank The address of the IO registers are as follows FpgaNum 4 bit MB SEL INTERCON 4 bit busnum 20 bit reg offset 4 bit FPGA is 0 0 for FPGA A 0 1 for B 0x2 for FPGA C MB SEL INTERCON is 0 busnum is any number but only low values less than LAST ADDR will contrain valid busses reg offset is 0 0 for REG OUT 0 4 for REG OE 0x8 for REG IN and for REG ENABLED To determine which bits if any in a bus are valid read the ENABLED register 32 bits returned 1 a mask for which of the bits in the REG OUT REG OE and REG IN registers ate meaningful get the bus ID of a bus write value 0 1 32 bit to REG ENABLED then read ENABLED
98. also allows you to easily configure and transfer data to and from the user design on the emulation board More information is provided in Chapter 3 Controller Software 4 2 Communicating to the User Design over the Serial Port You may want to communicate with your design over the user serial port P1 Only one FPGA can use P1 at a time Before you can communicate to your design change the RS232 multiplexing settings as described in Section 3 6 4 You can also change the RS232 multiplexing settings using the USB Controller software Connect a second RS232 cable to P1 the FPGA RS232 It is located right next to the configuration RS232 port 2 If you have the reference design loaded the RS232 port runs at 19200 bps 8 bit no parity By default the RS232 port is connected to A One the computer s terminal the reference design is programmed to digitally loop back the input to the output If on the terminal you can read your own output then the reference design was able to capture the RS232 signal and generate an RS232 signal that your computer could capture If you are familiar with previous Dini Group products the reference design test outputs could be read from this serial port On the DN8000K10PCI you must use the AETEST application to read the results of self test DN8000K10PCI User Guide www dinigroup com 32 4 3 Using AETEST to run hardware tests AETest is the program that you can use to veri
99. as a DiNi Prod FLASH BOOT When the new device detected window appears select the option install from a list gt select search for the best driver in these locations Select include the location in the search and browse to the product CD in Source Code AETEST_USB driver win_wdm gt select finish DN8000K10PCI User Guide www dinigroup com 30 4 After Windows installs the driver you will be able to see the following device in the USB section of Windows device manager DiniGroup DN8000K10PCI FLASH boot 5 Run the USB controller application found on the product CD in Source CodeNUSBConttollerNUSBConttroller exe L DiNi Products USB Controller File Edit FPGA Configuration Settings Info Refresh Enable USB gt FPGA Com PPC Port 1 Clear Log BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0x9 Maximum packet size is 0x00000200 512 MCU FLASH VERSION Ox4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0 9 MCU ERROR REGISTER 0 0 Maximum packet size is 0x00000200 512 MCU FLASH VERSION 0 4 4 BOARD VERSION DN8000k10PCI SPARTAN CONFIG FPGA VERSION 0 9 Figure 11 USB Controller Window 6 This window will appear showing the current state of the DN8000K10PCI Next to each FPGA a green light will appear if that FPGA is configured successfully The above window shows the USB Controller connected to a DN8000K10PCI with a single FPGA in t
100. ation Status Configure FPGA s over USB Configure FPGAs via SmartMedia card Clear Reset 5 Set Global clocks frequency Set RocketIO CLK Frequency Update MCU FLASH firmware The following function interface with the Dini Group reference design Read Write to FPGA s An Address map is contained in the Reference Design chapter Test DDRs FLASH Reigsters FPGA Interconnect 1 1 Menu Options 111 File Menu The File Menu has the following 2 options a Open opens a file with the selected text editor notepad by default change the text editor see Settings Info Menu section b Exit Closes USBController application 1 1 2 Edit Menu The Edit Menu performs the basic edit commands on the command log in the bottom half of the USBController window 1 1 3 FPGA Configuration Menu The FPGA Configuration Menu has the following options 1 2 3 4 5 Configure via USB individually After selecting this option a window will pop and ask which FPGA you want to configure and then what bit file you want to configure the selected FPGA with The status of the FPGA configuration will detailed in the log window and the DN8000K10PCI will be updated after the bit file has been transferred Configure via USB using file This option allows the user to configure more than one FPGA over USB at a time To use this option you must create a setup file that contains informati
101. ations of the DN8000K10PCI The reference design was created using Here ate the default main txt file lines verbose level 2 sanity check y clock frequency AN 4 M 16 100 MHz not used for test clock frequency B N 2 M 28 200 MHz clock frequency D N 2 M 25 200 MHz clock frequency 2 2 M 25 312 MHz 2 Reference Design Memory Map The Dini Group reference design memory maps the main features of the DN8000K10PCI to the host interfaces PCI USB and RS232 This memory map applies to the reference design and may have differences for the LVDS and PCP reference design The Bus interface is used to access the reference design memory map Addresses 32 bits Each address contains a 32 bit word FPGA A 0x00000000 OxOFFFFFF Not defined FPGA A 0x08000002 IDCODE 0x05000121 FPGA A 0x08000004 INTERCONTYPE 0x34561111 FPGA A 0x08000000 RWREG Scratch Register for testing FPGA A 0x08000010 LED OE Controls LED output enables FPGA A 0x08000011 LED OUT Controls LED outputs FPGA A 0x08100001 COUNTER Contains contents of ACLK counter FPGA A 0x08100002 COUNTER Contains contents of BCLK counter FPGA A 0x08100003 COUNTER Contains contents of DCLK counter FPGA 0 08100004 CLK COUNTER Contains contents of SYSCLK counte DN8000K10PCI User Guide www dinigroup com 123 INTRODUCTION TO THE SOFTWARE TOOLS FPGA A FPGA A FPGA
102. between 12V and the expansion headers is not installed on the board DN8000K10PCI User Guide www dinigroup com 81 VEE5 Power for this rail is not supplied by the DN8000K10PCI but is required for the operation of PECL optical modules power this rail you will need to connect an external power connector to the boatd from a low noise voltage supply There are test points for measuring the voltage levels of each rail near the top left of the DN8000K10PCI Each rail is monitored by a voltage monitor circuit and will cause a reset if any of the primary supplies drop 5 or more below their set points There are also LEDs next to each test point to indicate the presence of each voltage rail These LEDs do not indicate that a rail is within 5 of its set point only that the rail is present and above 1 6V A power OK led shows the status of the ATX power supply s PWR OK signal If this LED is lit then 5 0V and 3 3V and 12V 12V are within 5 of their set points 5 0V 42 5V 43 3V 41 8V o o PWR OK i R129 R131 R130 R134 R155 390R 82R 150R 30R 287R _ las ov laz sv 1 8v mA 59 DS11 DS10 DS12 10 DS13 Ww 4 Ww green wp x x x x x x 5 1 Switching power supplies The main power rails for the Virtex 4 FPGAs produced on board with three 20A switching power supplies one for each of 1 8V 2 5V and 1 2V
103. choices lowpwt off Vertical ellipsis Repetitive material that has been omitted 1 Name 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block 07026 name hoc loc2 locn Prefix or suffix sh Indicates hexadecimal notation Read from address 0x00110373 returned 4552494h Letter H 3 2 Content 3 2 1 File names Signal is active low INT is active low fpga inta nis active low Paths to documents included on the User CD ate prefixed with 12 47 This refers to your CD drive s root directory or the directory where you have copied the CD contents 3 2 2 Physical orientation and Origin By convention the board is oriented as show on page 3 with the top of the board being the edge near Headers A and B and the edge with the optical module connectors The right edge is neat the SMA connectors the left side is the side with the PCI bezel topside refers to the DN8000K10PCI User Guide www dinigroup com 11 side of the PWB with FPGAs soldered to it backside is the side with the daughter card connectors The reference origin of the board is the center of the lower PCI bezel mounting hole 3 2 3 Part Pin Names Pin names are given in the form lt X gt lt Y gt lt Z gt The lt gt is one of U for ICs for resistors C for capacitors P
104. cketIO connector 3 RCLK2 3 An Epson 250Mhz oscillator This clock can be used to supply an MGT reference clock to C in either the right of left columns ACLK BCLK DCLK These global clocks are supplied by ICS8442 frequency synthesizers They are configured from the MCU to output a user specified frequency from 31 to 700Mhz They are each distributed to A B and C The clock signals are point to point from a LVDS clock buffer The signal names the schematic for these clocks are ACLKAp ACLKAn ACLKBp ACLKBn ACLKCp ACLKCn BCLKAp BCLKBn BCLKCp BCLKCn DCLKAp DCLKAn DCLKBp DCLKBn DCLKCp DCLKCn SCLK1 2 These single ended clocks run at low speed and controllable from the USB interface allowing for software that controls single stepping designs Both clocks are delivered to FPGAs A B and C The clock is sourced directly from the Spartan 2 configuration FPGA Sysclk this 48Mhz single ended clock is driven from the configuration FPGA at a fixed frequency It is delivered to FPGAs A B C and the configuration FPGA This clock is used by the Dini Group reference design to clock the Main Bus interface MCU clk this reference clock is used by the MCU to generate frequencies required for the USB protocol It is not available to the user PCIUCLK This single ended 75Mhz fixed clock is delivered to the Configuration FPGA the Quicklogic PCI bridge and FPGA A It is used to clock the QL PCI back
105. cratch Register for testing Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte upper address bits for DDR2 interface number of bits in DDR2HIADDR DDR2SIZEHIADDR The size of the DDR2 module DDR2TAPCNTO DDR2TAPCNT1 Current IDELAY values of DDR2 interface www dinigroup com 125 INTRODUCTION TO THE SOFTWARE TOOLS Spartan 2 Vendor Requests xb 5232 Oxbe MEM MAPPED USB Oxbb SET EP6TC EP6 Bulk EP2 Bulk Oxaf CONFIG 0x90 CLEAR FPGA REBOOT MCU RS232 FPGA RS232 Port 0 65 CHECK FPGA CONFIG 0210 CONFIG DATA EP Buk 084 END CONFIG gt RST 15 0 0200 DMA WR ADDR 0238 FPGA STUFFING 0250 FPGA READ 0248 0240 0208 4 CONFIG CONTROL 00 0 10 48Mhz Map 26 Internal Regs 3 11 4 31 0 3 11 4 2 Pai 26 Internal Regs FPGA B PGAC 31 28 31 28 2770010 72 27 gt 27 OXABCDABCD g Internal 3 11 4 Regs Unused
106. d section of the web page contains a document called DN8000K10PCI Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual 3 Conventions This document uses the following conventions An example illustrates each convention 3 1 Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Courier font Messages prompts and speed grade program files that the system 100 displays Courier bold Literal commands that you ngdbuild enter in a syntactical statement design name Garamond bold Commands that you select File 2Open from a menu Keyboatd shortcuts Ctrl C Variables in a syntax statement ngdbuild design_name for which you must supply values DN8000K10PCI User Guide www dinigroup com 10 Convention Meaning or Use Example font References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild opton_name design_name Braces A list of items from which you must choose one ot more lowpwr off Vertical bar Separates items in a list of
107. d the PCI signaling If the PCI slot isn t providing enough power then a Hard Drive 4 pin power cable can be connected to the board from the same ATX power supply to reduce the voltage droop on 5V Please note that the board is capable of exceeding the 25W limit of the PCI connector depending on the density of the FPGAs utilized and the operating frequency The DN8000K10PCI also has these secondary rails 0 9 This voltage is used to terminate the SSTL18 signaling of the DDR2 memory module RocketlIO 1 2V top 1 2V right 1 2V bottom These linear regulated rails are vety low noise supplies for the CML inputs and outputs They are isolated from each other to improve the isolation of multiple RocketlO channels operating simultaneously RocketIO 1 5V This linearly regulated voltage rail supplies the internal digital logic of the RocketIOs RocketIO 2 5V this linearly regulated voltage rail supplies the internal analog circuits of the RocketIO 12V This is passed directly from the PCI edge connector and power connector to the Micropax expansion header See Chapter X Section X Expansion Headers Note that the fuse between 12V and the expansion headers is not installed on the board 12V This rail is passed directly from the PCI edge connector and power connector to the Micropax expansion header See Chapter X Section X Expansion Headers that the fuse
108. dinigroup com 112 G33 N31 P29 P28 N29 N27 B 15 NTO P13 AN9 N14 VCCR_SFP1 9 TxDIS MOD DEF2 SFP1 MOD DEF1 SFP1 MOD DEFO RATE SEL LOS SFP2 TxFAULT SFP2 TxDIS SFP2 MOD DEF2 2 MOD DEF 2 MOD DEFO SFP2 RATE SEL SFP2 LOS VCCT SFP1 U10 17 _ 1 Connector E Virtex 4 FX 1152 C332 O 01uF R141 105 RXPPADA 105 34 61050 A 105 RXNPADA 106 m 105 C333 CSFP1_TxDn VEE TXFAULT CSFPT TxD A SFPT DIS 0 01uF 18 TxDISABLE lr ASPERA 05 2004 SFPi TxDn C1051 T 16 VEET MED DEP MOD DEFT TXNPADA 105 4 potur OPT VECH SPET MOD DEF 0 T T ETT RxDp AVESSE EO 1 1 SFPT LO VTRXA 105 iN VEER VTRXB 105 VEER 105 105 AME x AGE R143 1k TXNPADB 105 CAGE R142 DNI amp CAGE 5 CAGE AVCCAUXMGT 105 CAGE m CAGE 7 RXPPADB 1
109. e tested fo d by a return example ABDEF AB Loop 1 of 1 T drive from FPGA_A Tested 468 pins 104 single ended on FPGA_A Test drive from FPGA_B Tested 514 pins 150 single ended on FPGA_B finished with testing ALL TESTS PASSED press any key Figure 14 AETest Interconnect Menu For more information on the AETEST program see Chapter 3 DN8000K10PCI User Guide www dinigroup com 34 4 4 Moving On Congratulations You have just programmed the DN8000K10PCI and learned all of the features that you must know to statt your emulation ptoject If you are new to Xilinx you might want move to chapter 4 introduction to ISE and Virtex 4 and start adding your Verilog code to the reference design The User CD contains a netlist of the boatd and example UCF files From the reference design All of the source code for the reference design in Verilog including embedded PowerPC code and utility is included on the provided CD DN8000K10PCI User Guide www dinigroup com 35 Chapter Controller Software 1 USB Controller USBController application is used to communicate with the DN8000K10PCI USBController source code is included on the CD ROM shipped with the DNS8000K10PCI The USBController can be installed on Windows 98 ME 2000 XP There is a command line version called AETEST USB that can be installed on Linux and Solaris The USBController Application contains the following functionality Verify Configur
110. e www dinigroup com 50 2 Configuration Circuit V FPGAA XCiBVO2 Master Serial 404 SelectMap 3 3 JTAG Header PCI 64 Quicklogic 5064 N Spartan 2 S200 FPGAB FPGAC Memory Map Smart Media MicroController Clocks 6384421 2 EPROM The circuit is designed to provide an easy configuration solution that will work out of the box for most users For special configuration requirements the configuration circuitry is programmable The Verilog code for the configuration FPGA and the C code for the microcontroller are both provided on the reference CD The C code for the PCI controller program and USB Windows GUI controller program are also included on the User CD 2 1 The Spartan 2 FPGA The configuration circuitry of the DN8000K10PCI is built around Xilinx Spartan Fpga The SelectMap interface of the user FPGAs is connected directly to the general purpose IOs of the Spartan 2 allowing the maximum flexibility of configuration The Spartan 2 also shares connectivity with the three user over a 40 bit Main bus allowing fast transfers from a computer to the user design over PCI or USB The Spartan 2 FPGA also provides IO expansion for the Cypress Microcontroller The Spartan II FPGA comes preloaded with
111. ed USB cable to connect the DN8000K10PCI to a Windows computer Windows XP is recommended DN8000K10PCI User Guide www dinigroup com 20 3 Plug ATX power supply into J1 or plug the DN8000K10PCI into a PCI slot Do not plug an external power supply into J1 if the DN8000K10PCI is plugged into a PCI slot Turn on the ATX power supply When the DN8000K10PCI powers on it automatically loads Xilinx FPGA design files ending with a bit extension found on the SmartMedia in the SmartMedia slot into the FPGAs 3 6 View configuration feedback over RS232 As the DN8000K10PCI powers on your RS232 terminal connected to P2 will display useful information about the Configuration process 3 6 1 Watch the configuration status output DN8000K10PCI User Guide www dinigroup com 21 No USB cable detected rebooting from FLASH please wait Setting ACLK N 01 M 000001000 DONE Setting N 01 M 000001000 DONE Setting DCLK N 01 M 000001000 DONE Setting RICLK N 01 M 000001000 DONE Setting R2CLK N 01 M 000001000 DONE DN8000k10PCI MCU FLASH BOOT FPGAS STUFFED AB SMART MEDIA INFO MAKER ID EC DEVICE ID 75 SIZE 32 MB FILES FOUND ON SMART MEDIA CARD FPGA_B BIT FPGA_A BIT MAIN 1 TXT MAIN TXT CONFIGURATION FILES FPGA A A BIT FPGA FPGA OPTIONS Message level set to default 2 Sanity check is set t
112. efault for walking bit test y Drive rest of board to test short circuit n Enter all FPGA s to be tested followed by a return example ABDEF AB Loop 1 of 1 Test drive from FPGA_A Tested 468 pins 104 single ended on FPGA_A Test drive from FPGA_B Tested 514 pins 150 single ended on FPGA_B finished with testing ALL TESTS PASSED press any key DN8000K10PCI User Guide 130 INTRODUCTION TO THE SOFTWARE TOOLS MEmilator FCI Controller Driver on Jul 22 2005 at 12 58 24 gt PCI Renu Memory Henu FPGAs stuffed AB 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 Menu 1 Quit PCI P 9 1000000 1 08008866 2 41908688 3 de880008 4 44000000 5 dcO00000 Please select option 3 Main Bus interface All memory mapped transactions in the reference design occur over the MB bus This 40 signal bus connects to all Virtex 4 FPGAs and to the Spartan configuration FPGA The Configuration circuit Spartan 2 is the master of the bus All access to the MB bus reads and writes is initiated by the Spartan II FPGA when the reference design is in use DN8000K10PCI User Guide 131 INTRODUCTION TO THE SOFTWARE TOOLS USB CLK dX dXX RD Spartan 1 MB 34D WR ET MB 3 1 1 DONE T MBBp6 All transfers a synchronous to the
113. eference design is loaded these be lit in the pattern 1110110111001011 If you suspect or mote FPGAs did not configure properly check the configuration circuitty s status lights These are four right angle mounted LEDs viewable out the side of the PC case If there has been an error three of the LEDs will blink If there has been no etror there should be two LEDs ON and two OFF If there was an error the easiest way to determine the cause of the error is to connect a terminal to the RS232 port P2 and try to configure again Configuration feedback will be presented over this port You should also notice the Fans mounted above the 3 Virtex 4 FPGAs and the Fan mounted above the power supplies spinning Assembly Number Signal Comment DS9 5 0V PRESENT The 5 0V power rail is present above 1 7V 15510 3 5V PRESENT The 3 3V power rail is present above 1 7V DS11 2 V PRESENT The 2 5V power rail is present above 1 7V 15512 1 8V PRESENT The 1 8V power rail is present above 1 7V 15513 The ATX power supply is generating 5 0V and 3 3V DN8000K10PCI User Guide www dinigroup com 27 within 5 at the soutce 0515 SPARTAN LED3 This LED will flicker when there is PCI configuration activity Bar 0 DS17 SPARTAN_LED2 This LED will flicker when there is Main Bus activity See section X X X DS19 SPARTAN_LED1 This LED will flicker when the
114. elorie com djgpp Follow the installation instructions for DJGPP The download comes with an utility to set your environment variables correctly D PCL_Software_Applications Aetest Contains the source code for AETest Copy this directory to your hard drive Open the file Makefile This file must be edited to define which operating system you wish to target Uncomment the line DN8000K10PCI User Guide www dinigroup com 42 ZDESTOS DOS DJGPP and the line include Makefile make In a DOS shell run make 2 32 Compiling AETest for Windows AETest for Windows requires visual studio to compile Copy the directory on the User CD D VPCI Software Applications VAetestN to your local machine Open the file Makefile and uncomment the lines ZDESTOS WIN WDM and include Makefile make Run make 3 Updating the Firmware Dini Group may release firmware bug fixes or added features to the DN8000K10PCI If a firmware update is released you will need to follow these instructions for access to the new features There ate two firmware files that Dini Group may release the first is a Micro controller MCU software update that 15 stored in a flash memoty This update can be accomplished easily from within the USBController application The second update that may be required is a Spartan core update The configuration data for the Spartan FPGA is contained in a Xilinx configuration PROM This update can be accomplished with
115. ettings Info menu select DN8000K10PCI test The status of the test will print in the log window The test will run twice once for each possible reference clock supplied to the RocketIO tiles Each will print out it s status Col 0 and Coll do not share a clock source so a problem with an entire column may indicate a problem with the clock Frequency settings MT stands for the QSE sametec cables XFP is the XFP module connector SFP is the smaller SFP module connector SMA is the SMA cable connectors LOOP is a hardware loopback TILE 2 is not connected and should fail To check each link the reference design checks that a certain test pattern is successfully recetved be the receiver of each tile If you connect each tile to itself using a loopback on each connector the test will verify that both the transmit and receive of each tile is working properly SMAs are labeled in silkscreen with an arbitrary channel number polarity and direction For each channel connect a cable from RXp to TXp and RXn to TXn Use two cables of the same length and diameter DN8000K10PCI User Guide www dinigroup com 137 INTRODUCTION TO THE SOFTWARE TOOLS For XFP or SFP modules connect a LR loopback cable into the module and insert the module into the socket For the Samtec QSE cables loopback cannot be done unless you have a custom cable You can test these interfaces by connecting one QSE connector to the next with
116. etween JP1 1 and JP1 3 For correct operation in PCI mode a jumper should be installed between JP1 2 and JP1 4 You should never install a jumper in both positions This could short 5 0V to 3 3 V when plugged in to a 64 bit 3 3V slot The DN8000K10PCI can be used in a PCI or PCI X slot operating at 33Mhz or 66Mhz It can also be used in 100Mhz and 133Mhz busses although the DN8000K10PCI will cause the entire bus to operate at 66Mhz 12 FPGA System monitor ADC The System Monitor and ADC functions of the Virtex 4 FPGA are no longer supported by Xilinx The most important responsibility of the System Monitor temperature sensing has been moved to the configuration circuitry The DN8000K10PCI will automatically monitor and prevent thermal overload in the three Virtex 4 FPGAs No user action is required FPGA A LX 200 Reserved pins U11 18 5 AVIS VREFN SM VCCAUXA 2 5V SM AWtg AVDD SM AW20 VN SM AV18 VP SM AVSS SM 0 Hori BEEN VCCAUXA 2 5V VREFP_ADC B22 AVDD VN ADC AVSS ADC Virtex 4 LX 1513 DN8000K10PCI User Guide www dinigroup com 120 13 Mechanical The dimensions of the PWB are 312mm long by 135mm tall plus a 8 25mm PCI edge connector This is taller than the PCI specification allows although the DN8000K10PCI fits easily inside most ATX computer cases 146 62mm 138 4 mm
117. f SM addtess ROW HADDR DF03 Holds upper 8 bits of SM address ROW XADDR DF04 Holds extra bits of SM address BYTES 0 DF05 Holds lower 8 bits of the number of bytes to read NUM BYTES 1 DF06 Holds upper bits of number of bytes to read in BITS 1 DF07 BIT7 mcu config rd BIT6 BITS_2 DF08 4 FPGA DONE BIT3 CPLD idle BIT2 SM SIGNALS DF09 MCU_XADDR DFOA Address register for upper FLASH SRAM bits MCU_CNTL DFOB Addtess register for upper FLASH SRAM bits SELECT DFOC FPGA select 5 0 bits 5 0 PPC RS232 ABSELECT DFOD PPC RS232 CDSELECT DFOE CNTRL DFOF bits 1 0 01 write address 10 data write 11 DF10 select byte addr read and data bytes FPGA RD DATA DF11 FPGA WR DATA DF12 FPGA ADDR DF13 FPGA ERROR DF14 GPIF DATA DF20 GPIF ERROR DF21 HOLD DONES DF22 STATES DF23 7 4 GPIF STATE 3 0 FPGA STATE FPGA FREQ H DF24 FPGA FREQ SEL DF25 DN8000K10PCI User Guide www dinigroup com 67 FPGA FREQ L DF26 STUFFING1 DF27 MCU STUFFING2 DF28 SERIAL CTRL 0 DF29 SERIAL_CLK_CTRL_1 DF30 MB80 1 CTRLO DF36 MB80 1 DF37 MB80 2 CTRLO DF38 COMMUNICATION DF39 MB80 2 DF40 MB64 1 CTRL DF41 MB64 2 CTRL DF42 MB64 3 CTRL DF43 CPLD_CS_N_CTRL DF44 CPLD_DATA DF45 CPLD_ADDR DF46 GCLK_MSEL_CTRL DF47
118. fy the hardware on the DN8000K10PCI as well as to demonstrate the reference design function following instructions assume you have PC running the Windows XP operating system The user CD includes a Windows vetsion of the AETest program If you plan to use the DN8000K10PCI in stand alone mode connect the DNS8000K10PCI to your WindowsXP computer and use aetest_usb in D USB_Software_Applications USB_CMD_Line_AETEST_USB If the computer asks for a driver click Have Disk and browse to D NUSB Software Applications Vdtiver windows wdmNdndevusb inf If you ate going to use the DN8000K10PCI in a PCI slot turn off the computer insert the DN8000K10PCI into an unused PCI slot and turn the computer on If the operating system asks for a driver click Disk and browse to Then run the PCI version of the AETest application at D NUSB Software Applications NUSB Line AETEST USB 4 3 1 AETest Windows98 version win98 driver is provided for using the DN8000K10PCI over USB but support for this driver is limited 4 3 2 AETest DOS version lt This section is out of date Contact support dinigroup com gt The application will also run under DOS The DOS version of AETest will not run under Windows s DOS emulation mode You must boot into DOS using a boot disk 1 Create a windows boot floppy disk The easiest way to do this is to format a disk using WindowsXP with the Create an MS DOS startup dick opti
119. gn interaction with DN8000K10PCI hardware features Ordering Information Contains a list of the available options and available optional equipment Some suggested parts and equipment available from third party vendors 2 Additional Resources For additional information go to http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Descripti on URL UserDN8000K10PCI This is the main source of technical information The manual User Guide should contain most of the answers to your questions Dini Group Web Site The web page will contain the latest manual application notes FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com DN8000K10PCI User Guide www dinigroup com 9 Resource Desctipti on URL Virtex 4 User Guide Xilinx publication UG070 http www xilinx com bvdocs userguides ug070 pdf Most of your questions regarding usage and capabilities of the Virtex 4 devices will be answered here including readback boundary scan configuration and debugging E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ Figure 2 Support Resources The downloa
120. hapter mtrodues the DINSOO0KTOPCI Reference Design induding information on what the reference design does how to build zt from the soune files and how to modify t 1 Exploring the Reference Design 1 1 What is the Reference Design The reference design is a fully functional Virtex 4 FPGA design capable of demonstrating most of the features available on the DN8000K10PCI Features exercised in the reference design include e Access to the DDR2 SDRAM Modules At 200Mhz e Communication e FPGA Interconnect e Interaction with the Configuration FPGA and MCU e Use of Embedded PowerPC Processors eventually Memory Mapped Access Between PPC And User Design eventually e Access to external LEDs e Communication via Rocket I O Transceivers Instantiation of Daughter Card Test Headers e USB memory map to DDR2 memory e PCI memory map to DDR2 memory DN8000K10PCI User Guide www dinigroup com 122 INTRODUCTION TO THE SOFTWARE TOOLS Pin multiplexed FPGA interconnect using LVDS at 700Mbs per signal pair All soutce code for the reference design is included on the CD and may be used freely in customer development Precompiled bit files for the most common stuffing options are also included and be used to verify board functionality before beginning development A build utility described in the section Compiling The Reference Design can be used to generate new bit files or to generate bit files for less common configur
121. he B position If you have the reference design loaded and a DDR2 SODIMM installed you can use the USB Controller to run tests of the SODIMM From the FPGA Memory menu select Test DDR 7 Clear the FPGAs of their configurations Right click on an FPGA and select from the popup menu Clear The green light above the FPGA on the GUI and on the board should stop shinning green 8 Configure an FPGA using the USB Controller program Right click on an FPGA and select Configure FPGA via USB from the popup menu The program will open a dialog DN8000K10PCI User Guide www dinigroup com 31 box for you to select the configuration file to use for configuration Browse to the provided user s CD D FPGA Reference Designs V Programming Files DN8000K10PCIVMMainTestVLX100 If you are configuring an LX200 or FX60 devices you should select a bit file from the LX200 or FX60 directories instead If you are configuring or C you should select fpga_b bit or fpga_c bit instead Done FPGA B cleared successfully FPGA A cleared successfully Doing a sanity check Sanity Check passed Configuring FPGA B via USB please wait File D dn_BitFiles DN8000K10PCI MainTest LX100 fpga_b bit transferred Configured FPGA B via USB Figure 12 USB Controller Log Output 9 message box below the DN8000K10PCI graphic should display some information about the configuration process The USB Controller program
122. he FPGA configuration memory is cleared After configuration this could indicate and error RDWR_B Active low write enable The Documentation refers to this signal as RDWR BUSY When busy is high the SelectMap configuration stream must stop until BUSY goes low CS_B SelectMap chip select The documentation refers to this signal as CSn CCLK Signals D 0 7 DONE RDWR B and CS B are clocked on CCLK DN8000K10PCI User Guide www dinigroup com 62 Each Virtex 4 FPGA has a complete set of SelectMap signals connected point to point to the Spartan 2 except for FPGA B and C who share signals D 0 7 All signals are 2 5 CMOS signals except for D 0 7 of FPGA Signals SELECTMAP D 0 7 which are 3 3V CMOS All commands required to configure a Virtex 4 FPGA are created and embedded in the bit files created by the Xilinx Bitgen program The DN8000K10PCI does not interact with the SelectMap interface other than to reset the FPGA using the PROGn INTn PROGn reset sequence described in UGO71 and to copy a bit stream file unaltered to the FPGA over the data pins D 7 0 Select map commands can be issued to the Virtex 4 FPGA from the host using the same interface used to configure and FPGA After Virtex 4 FPGA 15 configured it asserts the signal DONE On the DN8000K10PCI these signals have an LED attached to each DONE signal placed near the upper corner of each FPGA FPGA A s LED is 0518 is 0514 C is 0516 48 3V o R169
123. he pinouts on the cable allow two DN8000K10PCI boards to be connected to each other for a total of 10 bi directional channels operating at 5Gbs per channel direction The Samtec part number J2 3 QSE 014 01 F D DP A approptiate crossover cable for cabling two DIN8000K10PCIs together 15 the Samtec EQDP 014 09 00 TBR TBL 4 DN8000K10PCI User Guide www dinigroup com 110 ppp Come MO 10 010 16 QSE16_RxP GSETE FAN 84 RXPPADA 103 AVCCAUXRXA 103 Hesg T9 RXNPADA 103 AVCCAUXRXB 103 553 AVCCAUXTX 103 5 16 TxP TXNPADA 103 SAMTEC cabl prs cable VITXA 103 VITXB 103 15 VEDO IDA Use a cable with pins 1 and OSETE TaN 103 40 swapped TXNPADB 103 5 15 RxP SEIEN ACH RXPPADB 103 QSE14 TxN T ES QSE14 RXNPADB 103 AVCCAUXMGT_103 23 QSET4 TxP 3 4 14_ AN 5 6 QSE13 TxN 7 8 QSE13 fue 888888 117 TxP 3 10 Rx 5950 1 888888 QSE12 TxN 13 14 12 RxP 222222 QSE12 TxP 15 16 QSE12 RxN 600040900 TF 18 Virtex 4 FX 1152 1 1 SISSE CABLE COUTT 25 2 CABLE CD CABLE BER CABLE COUTp a CABLE CINn QSE11 TxN 25 26 f iiis TxP 27 28 OSET AxN 2 QSE14 RxP QSE1
124. i AGE CAGE RED vw 98 RED IGFUTSTTAFP OPTI nma 1 898 i 10 o ce mA ul 2 Figure 39 XFP Modules The interface is tested with the module Intel TXN18107 at 3 25 Gbs This module can be purchased from insight com At the time of printing the Virtex 4 MGTs are only capable of 3 25Gbs transmission Note that 3 25 Gbps is not supported by the specification so Dini Group cannot guarantee the interface will interoperate with other equipment The refclock signal is driven from DN8000K10PCI User Guide www dinigroup com 114 10 6 The SMAs The easiest way to connect two RocketIO channels is through the use of SMA cables The SMA connections on the DN8000K10PCI were designed to operate at the full 11Gb potential of the Virtex 4 RocketIO transceivers Bank not present in FX 40 Part U10 18 RXPPADA 106 AVCCAUXRXB 106 LAN RXNPADA 106 AVCCAUXRXA 106 ANZ AVCCAUXTX 106 23 Ap22 IXPPADA 106 TXNPADA 106 J20 CONN SMA RIO SMA TXpO 5 AES TXPPADB 106 VTTXB 106 1 TXNPADB 106 VTRXA 106 3 4 VTRXB 106 HANZ SMA 18 VTTXA 106 RXPPADB 106 421 5 RIO 5 0 AP17 106 5 1 4 9 J22 CONN SMA AVCCAUXMGT 106 06 06 06 06 06 is lt lt lt lt lt aooo 5 22222 1 00000 4 Virtex 4
125. igroup com 92 U18 A23 T18 R18 N23 M23 Header has more signals than Header A daughter card designed to work with header A will wotk with header B 8 1 3000K10 Compatibility The DN8000K10PCI headers use pinout similar to that on the DN3000K10 A compatibility chart with the DN3000K10SD Mictor daughter cards is given on the user CD in the daughter card directory Also see the customer netlist in the schematics directory The 1 5V power supplies MBCLKA F are not present 8 2 FPGA Connection On the DN8000K10PCI all header signals are connected to LC pins on the Virtex 4 FPGA See the Virtex 4 User s Guide for detail about these signals The main result of this is that the headers on the DN8000K10PCI may not be used with the Virtex 4 s current mode LVDS drivers Virtex 4 LVDS receivers may still be used Differential outputs can be acheieved using complementaty logic and output flip flops 011 2 Header Pins HAp52 F26 HAS Ro5 Kig 11 030 aes Lie 1012 29 16 16 LC O_L2N_D28_LC Bee IO L3P 027 2 HAp20 Jie 0 13 026 1 5 HARZU 5 10 14 D25 LC i TST 5 14 024 VREF LC X 24 D23 1 1 ie 15 D22 1C 1 3 5 D21 1C 1 Ej
126. instead reads Disable USB lt gt FPGA communication then the USB controller can at any time cause signals to be driven over these 40 signals possibly disrupting any user use of these signals Also note that the data path that the Spartan and MCU use to communicate over USB is shared by the SmartMedia card If you are running the Reference design tests or have copied the reference design in order to communicate over USB removing or inserting a SmartMedia card in the media card slot may interfere with USB Communication 6 3 DCI The Xilinx SelectIO technology guarantees proper signal termination of FPGA interconnect All DCI IOs on the Virtex 4 FPGA have been properly connected to 50 Ohm reference resistors These IOs VRN VRP must not be used by the user design for DCI to function properly When signaling between FPGAs use LVCMOS25 DCI signal standard for maximum performance Remember to achieve the highest interconnect throughput when operating the interconnect synchronously not using the serdes your IO clock must be deskewed using a DCM and you must use IO flip flops on all inputs and outputs 7 Memory interface There two standard 200 pin DDRZ SODIMM module sockets on the DN8000K10PCI These sockets are supplied with 1 8V power and keyed for use with DDRZ SDRAMs One socket is connected to FPGA B and the other is connected to FPGA DN8000K10PCI User Guide www dinigroup com 89 7 1 Clocking
127. inted The memory space of the MCU is 16 bits wide This table describes registers within the Configuration FPGA that are accessible from the memory space of the MCU REGISTER ADDRESS FUNCTION BIT7 mcu fpga config rd BIT6 mcu fpga config done BIT5 FPGA ack 4 FPGA PROGn BIT3 2 mcu mode BIT1 mcu sm rdy BITS 1 DF07 BITO mcu reading BIT4 FPGA DONE CPLD idle BIT2 SM RDYBUSYn BIT1 FPGA BITS 2 0 08 BITO mcu encrypt DN8000K10PCI User Guide www dinigroup com 39 SM SIGNALS MCU XADDR CNTL FPGA SELECT PPC RS232 12SELECT PPC RS232 34SELECT FPGA CNTRL FPGA BE FPGA RD DATA FPGA WR DATA FPGA ADDR FPGA ERROR GPIF DATA GPIF ERROR HOLD DONES STATES FPGA FREQ H FPGA FREQ SEL FPGA FREQ L MCU_STUFFING1 MCU_STUFFING2 ACLK_N_VAL ACLK_M_VAL BCLK_N_VAL BCLK_M_VAL DCLK N VAL DCLK M VAL BOARD VERSION DUP CF REG OFFSET DF09 DFOA DFOB DFOC DFOD DFOE DFOF DF10 DF11 DF12 DF13 DF14 DF20 DF21 DF22 DF2 DF24 DF25 DF26 DF27 DF28 DF29 DF30 DF31 DF32 DF33 DF34 DF46 DF6X FPGA_COMMUNICATION DF39 PENDING_CLKS CHECKSUM TEMP_SENSOR_A TEMP_SENSOR_B DN8000K10PCI User Guide DF40 DF45 DF50 DF51 address register for upper FLASH SRAM bits address register for upper FLASH SRAM bits FPGA select 3 0 bits 3 0 Selects which FPGA is connected to PPC Port 1 and 2 FPGAs are represented by 4 bits 000 B Ox1 0 8 Port 1
128. lk frequency to be 25 10 250 4 62 5Mhz MAIN BUS 0x0000 0x0001 Writes to a register in FPGA A Even if you are not planning to configure your Virtex 4 FPGAs using a SmartMedia card you may want to leave a SmartMedia card in the socket to automatically program your global and rocketIO clock Clocks may also be programmed using the provided USB application or over the MCU RS232 terminal 2 2 3 USB The USB interface on the DN8000K10PCI is provided by the Cypress microcontroller unit The Cypress microcontroller is programmed to interrupt when it receives a USB vendor request When the MCU receives over USB a Bulk Transfer type request it does not interrupt The raw data contained in the bulk transfer is driven out on the GPIF pins of the MCU the SM 0 7 DN8000K10PCI User Guide www dinigroup com 59 signals to the Spartan 2 The data is clocked out using the IFCLK clock signal to the Spartan 2 As long as the signal is held high by the MCU the Spartan 2 clocks to receive the USB data When data is written to the Spartan 2 from a bulk transfer over the MCU s GPIF interface the Spartan 2 either writes that data onto the SelectMap interface of the Vitex4 FPGAs or onto the Main bus using the Main Bus interface described in the Reference Design chapter The control register SELECT within the Spartan 2 determine to which interface this data is touted to 2 2 4 PCI
129. mand VERBOSE LEVEL level This command will set the amount of output the MCU will produce over the RS232 port during configuration When level is set to 0 the MCU will produce only etror output Before this command is executed the level is set to the default value 3 FPGA A lt filename gt The Virtex 4 FPGA A will be configured with the file named by lt filename gt FPGA B lt filename gt The Virtex 4 FPGA will be configured with the file named by lt filename gt FPGA C lt filename gt The Virtex 4 FPGA will be configured with the file named by lt filename gt SANITY CHECK lt yn gt If lt yn gt is set to y then the MCU will examine the headers in the bit files on the SmartMedia card before using them to configure each FPGA If the target FPGA annotated in the bit file header is not the same type as the FPGA the MCU detects on the board it will reject the file and flash the error LED Before this command is executed lt gt is set to the default value y If you want to encrypt of compress your bit files you will need to set lt yn gt to n Encrypting bit files is not supported or recommended by Dini Group Previous revisions of Xilinx parts have been vulnerable to permanent damage caused by bugs in the encryption circuitry MAIN BUS 0x lt WORDADDR gt Writes data in lt WORDDATA to the address on the main bus interface at DN8000K10PCI U
130. me FPGA B filename FPGA C filename CLOCK FREQUENCY clockname number M number SANITY CHECK yn VERBOSE LEVEL level RS232 lt gt lt fpganame gt MEMORY MAPPED Ox SHORTADDR 0x lt BYTE gt MAIN BUS 0x lt WORDADDR gt 0x lt WORDDATA gt DN8000K10PCI User Guide www dinigroup com 57 lt comment gt can be any string of characters except for newline lt filename gt can be the name of a file on the root directory of the SmartMedia Card number can be any one or two digit positive integer in decimal lt clockname gt can be A B D 2 A is B is BCLK D is DCLK and 2 is the RocketlO clock synthesizet lt yn gt can be the letter y or the letter n lt level gt can be 0 1 2 or 3 lt portnumber gt can be 1 2 3 or 4 The Dn8000K10PCI only has 1 user RS232 port 1 so 2 4 will cause no operation lt fpganame gt can be A B C D E F G H The DN8000K10PCI only has 3 FPGAs A B C so D I will cause the RS232 port to not function lt SHORTADDR gt is 2 digit hex number 16 bits BYTE is a 1 digit hex number 8 bits WORDADDR 4 digit 32 bit hex number representing a main bus address WORDDATA 4 digit 32 bit hex number containing data for main bus transaction The following table describes the function of each of the available main txt commands Instruction Function comment The MCU performs no operation and moves to the next com
131. me directory as Make bat and can be double clicked to open a command prompt window with the proper working directory Four main steps involved in building the reference design Once this has been done once the Make bat script can be used to build the netlist with the command Make ppc_netlist The second step is to synthesize the design with XST third step in to place and route or implement the design with the Xilinx ISE tools The fourth and final step is to compile the PowerPC code and embed it in the bit file This fourth step is referred to by Xilinx as updating the bit file Hence this fourth step will be referred to as the update step The build script creates a directory called out and places its output files there After the script completes you will find 3 files for each FPGA that was built Fpga_ bit is the file to be downloaded to the FPGA 5 Hardware Test Instructions The provided reference design is intended as an example code to get you started with the interfaces on the DN8000K10PCI The provided bit files on the CD were also used to test the hardware of your board Some of these tests can be easily repeated by the customer Bit files are provided for the following tests All testys except for the PCI test are accomplished using the USBController program on the user CD This program requires Windows XP 5 1 Main Test The reference design refers to a set of bitfiles capable of performing
132. n 2 Memory Mapped 10 Main Bus SYS_CLK FPGA A FPGAB FPGA 2 4 6 Smart media The SmartMedia card socket pins are bussed among the Cypress MCU GPIF pins the Spartan 2 FPGA IOs and the SmartMedia card socket After reset the MCU uses this connection to look for and read the contents of the file main txt on the SmartMedia card The main txt file contains instructions for configuring the user design into the three Virtex 4 FPGAs After reading the configuration instructions the MCU treads the headers of the user s FPGA design bit files and verifies that they target the correct type of FPGA that are installed on DN8000K10PCI User Guide www dinigroup com 69 your DN8000K10PCI This will prevent damage to the FPGA from an incorrect or corrupt bit file This behavior can be turned off If this check is passed MCU uses its memory mapped interface with the Spartanll to instruct the SpartanII to read the SmartMedia card and configure the Virtex 4 FPGAs over SelectMap bus 3 Clocking The clocking circuitry on the DN8000K10PCI is designed for high speed operation The flexible clock design should meet the most difficult clocking needs allowing 8 totally asynchronous controllable clock sources for each FPGA All clocks operating above 100Mhz are fully differential LVDS signaled low skew low jitter clocks DN8000K10PCI User Guide www dinigroup com 70 Xa
133. n otder to provide a high speed easy to use interface for your design the DN8000K10PCI comes equipped with a PCI bridge a Quicklogic 5064 The interface to the Quicklogic 5064 is a simple FIFO In order to use this interface you should implement the PCI interface module supplied with the reference design Blockram Access A A description of this module is maintained in a separate document on the user CD QL5064 Interface Module pdf D FPGA Reference Designs V dn8000k10pciVPCI interfaceVQL5064 Interface Module pdf The test of this section describes to function of the PCI hardwate 11 3 Virtex 4 FPGA Communication When the board is in a PCI slot whether or not FPGA A is configured the device will communicate with the host This is because the QL5064 is always active The QL5064 will report a Vendor ID 17DF and a Device ID 1864 The QL5064 will define BARs 0 through 7 BARs 1 5 reserved for user communication with the FPGA The size of the memory space for the is as follows BAR 0 8 BAR 1 5 16MB 11 4 Spartan 2 Communication The QL5064 will also define BAR 0 This range is reserved for the Dini Group reference design configuration and testing purposes The only reason you should use 0 is to communicate over the Main Bus interface DN8000K10PCI User Guide www dinigroup com 116 RESERVE PCI RESERVE CTRLO OUT QL VIO DETECT QL CS n QL RD EN
134. nal memory accesses 000 OxFFFF reserved by MCU RD WR strobes not active in this region The internal data memory region is mapped to an internal SRAM in the Cypress MCU When the microcontroller code calls memory access from this region the external Address and Data busses are not used After power on reset the MCU reads from the EPROM connected to the MCU_EPROM signals and fills this internal memory before allowing the PC to run The code in this section of memory contains core functions of the Dini Group firmware like setting up the interrupt registers communicating with USB and allowing firmware updates The external SRAM 15 used for heap data The memory mapped register region The DF region contains registers in the Spartan 2 FPGA that control FPGA configuration DN8000K10PCI User Guide www dinigroup com 65 The program memory space of the MCU is directly mapped to the external Flash memory When the Cypress MCU is reset which happens after the Spartan 2 is configured it loads its boot code into its 8kB of internal memory from a serial EPROM U13 The code the EPROM instructs the MCU to execute code located on the FLASH memory U19 The code in the EEPROM and FLASH is located on the user CD 43 3V 43 3V 3 3V EEPROM R251 R250 U13 2 2K 2 2K 43 3V R240 1K AO vec CL SCL T 1 MCU EPROM WP D xx 3 s 2
135. nerate a frequency for the MGTCLK inputs For 10Gb serial transmission rates you should use one of the low jitter fundamental frequency SAW oscillators These oscillators operate at 250Mhz and so cover the gaps in the frequency synthesis options given by the ICS843020 01 DN8000K10PCI User Guide www dinigroup com 105 Error NEAR OSC2_3 3VREG FPGA NEAR OSCILLATOR 103 NL FOR EG 2101CA R432 10 0K R433 1K NOTE VC 1 4V IS O PPM PULL R435 R436 T 240R 240R OSC2 1 1 oE vec H PU 2 Nc S3 98C2 Yn OSC2 our X EG Z101CA 250Mhz AES R439 R440 U10 20 33R 33R C1048 0 01uF T MGTCLK N 110 t MGTCLK P 110 C1049 R441 R442 0 01uF 49 9R 49 9R Virtex 4 FX 1152 OPT OSC3_3 3VREG NEAR FPGA OSC3_3 3VFILT 4 1 T 102 NL FOR EG 2101CA R419 10 0K R421 1K R422 R423 is 100R 100R 0563 vc 1 6 m m vec VE DONE FURTHER OSC3 PU x als 0803 Yn 1 0803 Yi 3 our 1 mE EG ZTOTCA 250 R426 R427 angar 88 7R 88 7R C1053 0 01uF Ane MGTCLK 105 MGTCLK N 105 C1054 R428 R429 0 01uF 49 9R 49 9R Vinex 4 FX 1182 Figure 35 MGT PECL Oscillators There are two Epson2101CA SAW oscillators 051 and U48 Each one drives MGTCLK on to one
136. ng frequencies from 30 500Mhz The clock synthesizers can be programmed from a SmartMedia card the Windows GUI application or PCI You may want to leave a pre DN8000K10PCI User Guide www dinigroup com 73 programmed SmartMedia card with a main txt file on it to program your clocks even if you intend to program the FPGAs over PCI or USB VCO SEL XTAL SEL TEST CLK MR S LOAD CONFIGURATION INTERFACE LOAD LOGIC NO N1 Each 1 58442 has an internal multiplication PLL that can operate between 250 and 700 Mhz With 1 2 4 or 8x division on the output the possible output frequencies are 31 25 700Mhz maximum input frequency of the Virtex 4 FPGA is 500Mhz VCO SEL can be used to disable the PLL so BCLK and DCLK can operate at their fundamental 25Mhz 14 3Mhz and 16Mhz respectively The Serial configuration bus 1s connected to the Cypress MCU GPIF pins and controlled through software The crystal inputs ate parallel resonant fundamental mode DCLK generator C341 d8pF Ris Te DCLKA 14 Qo DCLKA 24 TALI i4 16 do DCLKAn 16 0MHz FOUTO C455 18 25 11 oritur DCLKB 1 XTAL2 Hi x nai DCLKBn Hx j 9 DCLKTEST Q2 Fo oeren DCLKC xn TEST 1 m n 2 DOLKCn 53 31 oE 8 aeq
137. o default ON N 00 M 000001010 DONE Setting BCLK 01 M 000001100 DONE Setting DCLK 01 M 000001000 DONE Setting RICLK 01 M 000001000 DONE Setting R2CLK 01 M 000001000 DONE CONFIGURING FPGA AK RAR Performing Sanity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA_A BIT FILE SIZE 003A943B bytes PART 4vlx100ff151317 09 38 DATA 2005 07 25 TIME 17 09 38 The global clocks ACLK BCLK DCLK are frequency configurable The M binary sequence represents the multiplication applied to the installed crystal The N represents the division applied U6 U14 U20 U31 and the ICS8442AY datasheet The MCU is setting the clocks to their default values ACLK 200Mhz BCLK 108 8Mhz DCLK 128Mhz R1CLK not available on DN8000K10PCD R2CLK DEFAULT The MCU detects which FPGAs are present The MCU detects if a SmartMedia card is present The MCU tries to access the SmartMedia card If the MCU is not successful in reading the files on the SmartMedia card be sure you have not formatted the card in Windows Windows uses a non standard format for media cards and will make the card unreadable You can download a format utility from dinigroup com to repair your incorrectly formatted SM card The MCU reads the contents of the file MAIN TXT and executes each instruction line Here the MCU is setting the clocks according to instructions in MAIN TXT
138. ock from a global clock input not recommended or by a recovered clock Finally each tile has a multiplexer than can select from one of the two clock trees to clock that entire tile REFCLK1 or REFCLK2 Use the TXABPMACLKSEL and RXPMACLKSEL parameters The diagram above shows the two RocketIO columns and the connectivity of each DN8000K10PCI User Guide www dinigroup com 104 Once a clock is routed to an MGT tile that clock can be multiplied and divided by the MGT tile Most users will want to use the frequency synthesizer for generating RocketIO reference clocks The 1 5843020 01 synthesizer is very low jitter and should suitable for operation up to 6Gbs RocketIO operation The frequency of the synthesizer can be adjusted through the main txt file on the SmartMedia catd or through the USB GUI program Figure 34 MGT 8442 Connections 43 3V 43 3V CABLE COUTOn CABLE COUTOp R443 R444 R445 R446 100R 1008 1008 100R CABLE COUTO 010 15 u31 m emt sme eme eus 5 FOUTO 1 M34 MGTCLK 102 5 6 25 11 R447 R448 R449 R450 N34 2A 7 8 ETAs EQUTI 12 88 78 lt 5 88 7R 88 7RS S 88 7R MGTCLK_N_102
139. on checked 2 D AETest aetest_floppy contains some files you need to add to the boot disk Copy the contents of this directoty to the disk Add the program D AETest DJGPP CWSDPMLEXE to the floppy The DOS version of AETest requires CWSDPMI EXE to access the PCI bus 3 Plug DN8000K10PCI into the PCI slot 4 Boot from the floppy 5 Run AETESTDJ EXE 4 3 8 AETest on Linux or Solaris To use the AETest application on Linux or Solaris you must compile the source code included on the User CD DN8000K10PCI User Guide www dinigroup com 33 4 3 4 Use AETest The AETest application should display it s main menu mulator PCI Controller Driver M on Jul 22 2005 at 12 58 24 PCI Menu Memory Menu FPGAs stuffed A 1 Interconnect test 2 Read clock frequencies 3 Configure FPGA 4 Menu Q Quit X 0 61000000 UN 2 41900060 Hl 4 44000000 5 dc809000 Please select option Figure 13 AETEST Main Menu Run one of the tests Choose option 1 Remember the FPGA you test has to be loaded with the reference design or the test will fail TEST WITH ANY DAUGHTER BOARDS PLUGGED 11111 LL LLLLLLLLLLLLLLLLLTTTTTTTTTTTTT TT se output 9 9 11 72 on Errors default N 0 Loop default Y Y n n Random test data default M for walking bit test y M y Drive rest of board to test short circuit y n n Enter all FPGA s to b
140. on on which FPGA s should be configured and what bit files should be used for each FPGA The file should be in the following format the first character of each line represents which FPGA you want configured a f or A F this letter should be followed by a colon and then the path to the bit file to use for this FPGA The path to the bit file is relative to the directory where this setup file is or you can use the full path Below is an example of an accepted setup file A fpga_a bit B fpga_b bit C fpga_c bit Configure via SmartMedia Card This option allows the user to use a SmartMedia card to configure the FPGAs Please section Creating Configuration File main txt for information on what files should be on the SmartMedia card to use this option Clear All FPGAs This option will deconfigure all FPGAs Reset This options sends an active low reset active for approx 20ns to all FPGAs on the signal called RESET_FPGASn which is connected to the following I O pins FPGA A AK19 FPGA B K21 C AG18 DN8000K10PCI User Guide www dinigroup com 37 1 1 4 Settings Info Menu The Settings Info Menu has the following options 1 Set FPGA RocketIO CLK Frequency When the DN8000K10PCI is first powered up 2 the RocketIO CLK inputs to the FPGAs are inactive The CLK Inputs are connected to the following FPGA Differential CLK inputs on all FPGAs F21 G21 and AT21 AU21 This menu option
141. onnect signals on the DN8000K10PCI have been optimized to operate in lanes There are 7 lanes between FPGAs and B three between B and C and two between FPGAs and C Each lane has a differential LVDS soutce synchronous clock in each direction FPGA A 011 7 U12 6 AH o Lip 6 L9P CC LC 6 Send o LIN 6 OLN cC 1C 6 HERO B26 io LiP 5 10 CC LC 5 G37 ABC ABpi Ei2 Hre BABNIS 426 B27 ABC Kno aa Ei 12 6 iO L10P 6 252 ABT 28 LIN 5 IO L9N CC LC 5 Big IO L2N 6 10 L10N 6 G3 ABpi3 RBN4 F28 10 L2P ADCG 5 10 10 5 16 Renz Cig 0 13 6 11 6 612 _ BACLKpO_E27 10128 ADC6 5 1 110 5 27 BP12 Dit OLN 6 IO LIN 6 BACLKnd_D27_ 10 1 ADCS 5 IO L1P 5 RABNI2 ABna Ip LizP 6 14 L ABPS A30 O L3N ADCS 5 S c32 ABPB ABEL DIT O L4N VREF 6 10 112 VREF 6 Big ABpis RENE AST 5 IO L12P 5 Fees See E14 10152 IG LI3P 6 Ges 14 VREF 5 10 112 VREF 5 B25 ABP2 L5N 6 10 L13N 6 FEr1 ABpi6 2 O 15 5 19 1136 5 C28 AENZ 815 10 10162 6 6 ABniS D29 LEN 5 10 113 5 Fagg ABPIS Aep
142. puter serial port PPC RS232 Interface MCU and A RS232 ppc RS232 TX 5 m H E tn o H T30UT RS232_RX_S 13 RIOUT 1 10 tour LIN x H swour SWIN RS232 MCU 2 0 24 4 SHDN 2 12 op vec 2 3 3 4 C1 x 4 5 6 5 c2 E Ci 0 1 9 10 V C229 C230 22 GND V 0 1uF 0 1uF 0 1uF lo Jo Figure 28 RS232 Buffer and Headers The RS232 port will be able to communicate with a standard PC serial port set to 19200 baud 8 data bits no parity no handshaking When you connect a computer terminal to the port and power on the DN8000K10PCI the firmware loaded on the microcontroller unit will display menu on the terminal This menu will allow you to control the basic configuration options of the DN8000K10PCI including configuration clock frequencies and the Virtex 4 RS232 ports 2 4 2 Clocks The Cypress CY7C68013 is also responsible for configuring the global clocks and RocketlO clock of DN8000K10PCI The Cypress CY7C68013 MCU reads the file main txt from the SmartMedia card in the socket J24 and follows the users clock configuration commands DN8000K10PCI User Guide www dinigroup com 64 852 18pF ACRYSp 24 H ACLKp FouTo S Ex 25 xrAL2 routs Ht x z5MHz FOUTI x gt 29 9 ACLKT
143. ration Options The DN8000K10PCI allows FPGA configuration from any of four methods When a Virtex 4 15 configured the DONE pin on the FPGA 15 pulled high The DN8000K10PCI has a green LED attached to the DONE signal of each to indicate the state of the DONE pin on the three Virtex 4 FPGAs and on the Spartanll configuration FPGA 3 3V R169 120R FPGAA_DONE 2 5V DS18 FPGA DONE A lt gt FPGA DONE A 11 Figure 24 DONE LEDs DN8000K10PCI User Guide www dinigroup com 55 2 2 4 Jtag Jtag is the only configuration method on the DN8000K10PCI that does not use the Virtex 4 SelectMap configuration interface When programming the user FPGAs over a JTAG cable plugged into 13 the DN8000K10PCI configuration circuitry is not used JT AG connection is required to use some Xilinx configuration tools like ChipScope and readback from Impact Configuration over is slower than SelectMap You can still use the SmartMedia or USB interfaces to control clock settings if you plan to configure through JTAG To configure using JTAG we recommend using Xilinx Parallel cable IV or Xilinx platform USB cable The Xilinx program You should set the configuration speed of your JTAG cable to 4Mhz or below FPGA JTAG Cable IV 42 5V 2 5V J13 hk hk 1 2 3 2 JTAG FPGA TMs FPGA TMS 5 6 RJTAG FPGA TCK L i 4 JTA
144. ration functions on the DN8000K10 such as temperature sensors and clocks This is done by altering the data in the XDATA memory space of the configuration MCU To write to the MCU address space access the DN8000K10 s BARO at the address MCU BAR ADDR 0x258 Send a 32 bit word of data This data is decoded as follows Bits 31 16 address in XDATA space only addresses OxDF00 0xDFTFT reside in the Spartan 2 Bits 15 8 Ignored Bits 7 0 The Data to write To read from the MCU address space access the DN8000K10 s BARO at the following 32 bit addtess Bits 31 24 The DN8000K10PCI s BARO Bits 23 16 the lower 8 bits of XDATA address you would like to read This corresponds to addresses OxDF00 OxDFFF of the XDATA address Only addresses 0xDFO0 0xDFFF reside in the Spartan 2 Bits 15 0 0x0260 2 2 4 3 Main Bus Space PCI can also be used to send information to and from your Virtex 4 user design through the Spartan 2 FPGA Communication directly to the user design can also be accomplished from DN8000K10PCI User Guide www dinigroup com 61 FPGA A by communicating directly with the QL PCI backend interface This method is an order of magnitude faster and allows the use of advanced PCI features like DMA See Hardware PCI interface Communication with the FPGAs through the Spartan occurs using the Main Bus interface For information on the main bus interface see Reference Design Main Bus Interface To write to the main bus in
145. re is USB activity Bulk Transfer 0520 SPARTAN LEDO This LED will flicker when there is SmartMedia card activity 0521 1 MCU LEDO MCU LED 1 0 Codes 0521 2 MCU_LED1 01 FPGA A is configuring 10 FPGA B is configuring 11 FPGA 1 configuring 0521 3 LED2 The last FPGA configuration was successful 0521 4 MCU LED3 Blinking There was configuration error Use the RS232 port to read the error Off No error On The last configuration command was successful DS24 SPARTAN_DONE The Spartan 2 configuration FPGA is configured This light will turn off if the board is in power reset DN8000K10PCI User Guide www dinigroup com 28 DS22 PCI IN PCI data is arriving from the PCI bus DS23 PCI OUT PCI data is being transmitted onto the PCI bus DS18 FPGA A DONE Virtex 4 FPGA is configured DS14 FPGA B DONE 4 FPGA is configured DS16 FPGA_C_DONE The 4 FPGA C is configured DS8 SFP2 LOS SFP module 2 Loss of signal DS4 5 2 FAULT SFP module 2 transmitter fault DS5 XFP2_INT XFP module 2 etror DS1 XFP2 FAULT XFP module 2 transmitter fault DS6 5 1 LOS SEP module 1 Loss of signal DS2 SFP1 FAULT module 1 transmitter fault DS7 XFP1 INT module 1 error DS3 XFP1 LOS XFP module 1 Loss of signal DS48 DS47 DS46 DS45 DS44 DS43 DS42 DS41
146. requirement for this IO remains fixed at 6 2mA regardless of frequency of operation 8 4 IO Power The IOs connected to the headers on the Virtex 4 FPGAs are powered with a 2 5V power rail 8 5 Physical Micropax part number FCI 91294 003 The standard Dini Group mounting hole location for all 200 pin Micropax connections 1s 430 mils 8 6 Daughter card Power Power is supplied to the daughter catd though dedicated power supply pins The maximum allowed current for each of the daughter card supplies is 5 0V 1A 3 3 1A 2 5V 1A 12V 250mA 12V 250mA The 12V and 12V supplies are by default disconnected by removing the series jumper resistors R413 R412 R411 R414 This help prevent accidental damage due to careless probing The 12V and 12V supplies may be able to source as much as 0 5A of current if the current can be supplied by the host PC DN8000K10PCI User Guide www dinigroup com 99 8 7 The Mictor There is a Mictor connected designed to be used with an agilent logic analyzer Riscwatch power PC debugger can also be used over this connection MICTORO MICTOR13 GND 1 4 ORT14 MICTOR2 3 4 TRC 5 6 8 5R 7 8 PPC JTAG TDO A 2 TRC VSENSE R101 33 13113 14 5 15 16 PoC TAG TD 1 4 47 18 28 19 20 VICTOR 21 22 5 TRC 810
147. rom FPGA at current address Here is the MCU main menu g Display FPGA Temperatures h Set FPGA Temperature Alarm Threshold ENTER SELECTION Options 8 9 and A are only available when the DN8000K10PCI reference design is loaded For more information on how the MCU communicates with the reference design see Chapter X The Reference Design Figure 5 RS232 Output You should see the DN8000K10PCI MCU main menu If the reference design is loaded in the Virtex 4 FPGAs then you should see the above on your terminal Try pressing 3 to see if the configuration circuit was successful in programming the FPGAs ENTER SELECTION 3 KKK KKK KKK CONFIGURATION STATUS kkk kk kkk kk KKK KEK FPGA B NOT configured The easiest way to verify your FPGAs are configured is to look at DS18 DS14 0516 located above each FPGA When the green LEDs are lit the FPGA under it is successfully configured DN8000K10PCI User Guide www dinigroup com 23 3 6 2 Interactive configuration If you want to put multiple designs on a single Smart Media card you can use the interactive configuration menu to select which bit file to use on each FPGAs Select menu option 2 ENTER SELECTION 2 INTERACTIVE CONFIGURATION MENU 1 Select bit files to configure FPGA s 2 Set verbose level current level 3 Enable sanity check for bit files M Main Menu Enter Selection Figure 6 Interactive Config Menu
148. s rework drops the 1 2V RocketIO supply from 1 25V to 1 14V This rework only appears on revision 2 boards that have a Virtex 4 FX60 CES2 or CES3 in the FPGA C position 10 3 The connections The following is a connection summary of the RocketlO channels available the DN8000K10PCI Group Signal Pin on ile MGT tile Name Name FPGAC jNumber FPGA C QSEO1 TXP C1 113 GT11_X1Y6 QSE J2 5 01 D1 cable 0 5 01 F1 5 01 RXN G1 5 02 TXP A4 113 GT11_X1Y7 QSE02 5 02 7 5 02 RXN A6 5 TXP A13 1146 11 X1Y8 QSEO3 A12 FX100 QSEO3 A10 NOT ON FX60 QSEO3 RXN A9 5 4 TXP A15 114 GT11 X1Y9 DN8000K10PCI User Guide www dinigroup com 107 5 4 A14 FX100 QSE04_RXP A18 QSE04_RXN 17 60 QSE11 TXP A25 101 6 11 0 8 QsE J3 5 11 A26 FX100 cable 0 QSE11 RXP A28 J3 QSE11_RXN A29 NOT ON FX60 QSE12_TXP A23 101 GT11_X0Y9 QSE12_TXN A24 FX100 QSE12_RXP A20 QSE12_RXN A21 NOT ON FX60 QSE13_TXP F34 102 aT11 0 6 QSE13 TXN G34 QSE13 RXP 134 QSE13 RXN K34 QSE14 TXP D34 1020711 7 QSE14 TXN E34 QSE14 RXP A31 QSE14 RXN A32 QSE15 TXP Y34 103 aT11 XoY4 QSE15 TXN AA34 QSE15 RXP AC34 QSE15 RXN AD34 QSE16 TXP V34 103 GT11 0 5 QSE16 TXN W34 QSE16 RXP R34 QSE16 RXN T34 XFP1 TXDP AL34 105 GT11 Xov2 XFP1 TXDN AM34 XFP1 RXDP AP32 XFP1 RXDN AP31 XFP1 REFCLK AJ34 105
149. ser Guide www dinigroup com 58 0x lt WORDDATA gt lt WORDADDR gt This command only makes sense in the context of the Dini Group reference design unless your design implements a compatible controller on the main bus pins Reference Design chapter contains a distription of this interface See the board netlist or the reference design UCF for pin placement CONFIG REG 0x lt SHORTADDR gt lt gt Writes to an address in the XDATA memory space RS232 lt port gt lt fpga gt The RS232 port P1 will be controlled by the FPGA lt fpga gt if lt port gt is 1 CLOCK FREQUENCY lt clockname gt N lt number gt M lt number gt The MCU will adjust the clock synthesizer producing clock lt clockname gt to multiply it s reference frequency by lt M gt and divide it by lt N gt Note that the clock synthesizers have a limited bandwidth and for clocks A B and D the reference frequency M must fall in the range 250Mhz 700Mhz For clock 2 RocketIO reference must fall between 540 and 680Mhz See datasheets for parts ICS8442AY and ICS843020 01 The reference frequencies are ACLK 25Mhz BCLK 14 18Mhz DCLK 16Mhz 2CLK 25Mhz An example main txt file VERBOSE LEVEL 0 This will prevent the MCU output over RS232 to speed up configuration FPGA A a bit this will load the configuration a bit into FPGA A CLOCK FREQUENCY 4 M 10 This will cause Ac
150. software to for design synthesis The XST projects for each of the 3 FPGAs on the DN8000K10PCI can be found at buildxst xst These projects have been compiled using XST version 9 1 DN8000K10PCI User Guide www dinigroup com 133 INTRODUCTION TO THE SOFTWARE TOOLS 4 1 3 Xilinx ISE Use HDL files as input Modification of the ISE project may also require modification of the HDL timing constraints are in files buildxst xcf sample Project Navigator project is located at DN8000K10PCI implement fpega ise 4 1 4 The Build Utility Make bat The Build Utility is found at DN8000K10PCI build make bat This batch file is used to set system parameters to the desired configuration i e V4FX60 vs V4FX100 etc and to invoke all of the above tools from the command line Instructions for invoking the batch file can be found by viewing the batch file with a text editor Additional information about using the batch file to build the reference design is found below Taking the reference design through all of the various tools for several can be very tedious and time consuming this batch file can do it allin one command The command line utility Make bat is an MS DOS batch file compatible with Windows 2000 and later operating systems Make bat should be run from the command line with command line parameters It should not be double clicked from the windows environment command prompt shortcut is provided in the sa
151. standard on the LED signals from 2 4 12 16 or 24mA Signal Pin on Pin on Pin on Name FPGAA FPGA B FPGA C LEDO AJ6 G18 LED1 AJ5 F18 LED2 AG10 H14 LED3 AK6 H13 LED4 AH10 G17 LED5 AH9 G16 LED6 AK7 G15 LED7 AJ7 H15 LED8 E18 LED9 E17 LED10 F15 LED11 F14 LED12 E16 DN8000K10PCI User Guide www dinigroup com 102 LED13 F16 LED14 F13 LED15 G13 10 RocketlO 10 1 RocketlO Clock Resources Since it is impossible to determine during manufacturing the clocking requirements of every possible end application the DN8000K10PCI comes with a flexible clock network capable of a wide range of serial frequencies while maintaining the tight jitter requirements of the 10 Gigabit serial transceivers The RocketlO clock tree is driven by a synthesizer and two oscillators and dedicated multiplexers inside the Virtex 4 FPGA allow the user to switch between these clock sources DN8000K10PCI User Guide www dinigroup com 103 PIN AP 29 4P 26 Epson GTIICLK Oscillator GTI I CLK 250Mhz PIN M34 N34 Optical Module 1 ICS 043020 Optical Module 2 Epson Oscillator 250Mhz 5 SAMTE C cable Figure 33 Internal MGT clocking The RocketIOs on the Virtex 4 FPGA is divided into two columns XO and X1 The clock netwotk of each column is separate and clocks may not be shared between the two columns Each column has two clock distribution trees and two clock inputs Each tree be driven by a clock input by a cl
152. supply if ECL signaling is required www dinigroup com 84 5 Mountin support L5 4 7uH 5 for 5 2V U1 2 1 JMPR DNI 5 3 Heat dissipation Virtex 4 FPGAs are capable of drawing incredible amounts of current from their 1 2V and 2 5V power supplies According to Xilinx online power estimator tool a fully utilized FPGA running at 300Mhz can draw than 30W of power With this much power used in each FPGA the DN8000K10PCI can dissipate 75 or more Watts of heat For all but the most trivial designs a heatsink must be used with the Virtex 4 FPGA The DN8000K10PCI comes with a forced air heatsink rated at 2 degrees per Watt Since the maximum operating junction temperature of a Virtex 4 FPGA is 85 degrees assuming an ambient temperature of 50 degrees the inside of yout computer case the most amount of energy dissipated by the FPGA using the standard fan is 85 30 2 27 5W This should be sufficient for most applications If you intend to operate the Virtex 4 FPGA at very high speeds or are getting overheating issues with your design you will need to install a larger heatsink U11 1 Virtex 4 LX 1513 295 28 4 HSWAPEN PROGRAM aeri INIT 977 0 CS B xg DONE cH PWRDWN B RDWR B DOUT BUSY LTy24 16 aY2 2
153. t this jumper is installed from JP1 2 JP1 4 Table 1 describes the functionality of the jumper block on the DN8000K10PCI Table 1 Jumper Description Jumper Location Signal Name Description JP1 1 JP1 3 BOARD 5V This jumper fixes the PCI clamping voltage at 5 0V You should use this jumper setting if the DN8000K10PCI is being used in stand alone mode JP1 2 JP1 4 default PCI VIO This jumper should be installed when the board is being operated in 5V or 33 PCI slot Don t install both jumpers at the same time The top two pins are 1 and 3 Pin 1 is the one with a white circle next to it There is a label next to each pin indicating it s connection 1 BOARD 5V 2 BOARD VIO 3 BOARD VIO 4 PCI VIO BOARD 5V BOARD VIO 1 3 is correct when the board is not in PCI PCI VIO BOARD VIO 2 4 is correct when in a PCI slot The effect of an incorrect setting when in PCI is less reliability in a very heavily loaded PCI slot at 66 Mhz The effect of the incorrect setting when not in a PCI slot is the temperature sensors might not work 3 2 Verify Switch Settings The DN8000K10PCI uses a DIP switch to program the FPGA configuration circuitry The function of these DIP switches is Listed in Table 2 Verify that the switch settings on your board match the default settings Table 2 Switch Description DN8000K10PCI User Guide www dinigroup com 17 Switch Default
154. t enable of ABP1 bus R ABP1 input values ABP1 acsit XX can be 0 21 hex Output status of IOs on bus XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface 0x05000121 0x34561111 Scratch Register for testing Controls LED output enables Controls LED outputs Contains contents of ACLK counter Contains contents of BCLK counter Contains contents of DCLK counter Contains contents of SYSCLK counte upper address bits for DDR2 interface number of bits in DDR2HIADDR The size of the DDR2 module Current IDELAY values of DDR2 interface XX can be 0 21 hex Output status of IOs on bus XX XX can be 0 21 hex OE status of IOs XX can be 0 21 hex The input values The name of the bus XX schematic Mapped to DDR2 SODIMM interface www dinigroup com 124 INTRODUCTION TO THE SOFTWARE TOOLS FPGA C FPGA C 0x28000002 0x28000004 0x28000006 0x28000010 0 28000011 0 28100001 0x28100002 0x28100003 0x28100004 0x28000001 0x28000003 0x28000005 0x28000007 0x28000008 DN8000K10PCI User Guide IDCODE INTERCONTYPE RWREG LED OE LED OUT COUNTER COUNTER COUNTER COUNTER DDR2HIADDR HIADDRSIZE 0x05000121 0x34561111 S
155. terface write to BARO address QLPCI MBADDR with the 32 bit value representing the main bus address you would like to write to Then write a second PCI write to address QLPCI REG MBWRDATA with 32 bit data representing the data that you would like to write to main bus After the Spartan 2 has received a write to both the MBADDR and MBWRDATA registers it will write to the main bus interface To read from the main bus interface first write to BARO address QLPCI MBADDR with the 32 bit value representing the main bus address you would like to read from Then read from BARO OLPCI REG MBRDDATA The returned value will be the value read off the main bus at the selected address When an error has occurred No FPGA responded to the read request the Spartan will return the value O ABCDABCD 2 3 FPGA configuration Process For information regarding the JTAG interface and configuration See Xilinx publication 0 071 Virtex 4 configuration guide When configuring over PCI USB or SmartMedia the FPGAs are configured over the Virtex 4 SelectMap bus All SelectMap signals are connected directly to the Spartan2 FPGA The SelectMap signals are D 0 7 SelectMap data signals PROGRAM B Active low asynchronous reset to the configuration logic This will cause the to become unconfigured documentation refers to this signal as PROGn DONE After the FPGA is configured it is driven high by the FPGA INIT Low indicates that t
156. the DN8000K10PCI might not function propetly Check the Configuration status LEDs These LEDs are visible from outside the case when the DN8000K10PCI is installed ATX case Under error conditions all four ted LEDs will blink Check the Spartan FPGA status LED DS24 This LED indicates that the Spartan II FPGA has been configured If this LED is not lit soon after power on then there may be a problem with the firmware on the DN8000K10PCI This LED off or blinking may indicate a problem with one of the board s power supplies DN8000K10PCI User Guide www dinigroup com 26 Check the FPGA status LED 10518 to the upper left of FPGA A This green LED 15 lit when FPGA is configured and operational This light should be on if you loaded the reference design from the SmartMedia Check the FPGA status LED 0514 directly above FPGA B This light should be lit green if your DN8000K10PCI was installed with the FPGA option and the reference design is loaded Check the FPGA C status LED DS16 to the upper left of FPGA C This green LED will light if you have the FPGA C option and the FPGA is configured Check the FPGA A User LEDs on the bottom side of the DN8000K10PCI If you have successfully loaded the Dini Group s DN8000K10PCI reference design these should be lit in the pattern 00011010 Check the FPGA C User LEDs on the bottom side of the DN8000K10PCI If you have ordered the FX FPGA C option and the r
157. to disregard constraints Double check that the connections match between your FPGA pins and the daughter card pins DN8000K10PCI User Guide www dinigroup com 138 INTRODUCTION TO THE SOFTWARE TOOLS If your design uses the MB 37 0 bus make sure that none of the other FPGAs are driving those MB pins Make sure that the Unused IOBs option in bitgen settings is set to Float If it is set to Pull down then those FPGAs are driving any pin that is not assigned in the source code If the signals on the SD daughter card are not working check that you ate asserting output enable OE for the level translation buffer DN8000K10PCI User Guide www dinigroup com 139 DN8000K10PCI User Guide www dinigroup com 140 Chapter Ordering Information Part Number DNS8000K10PCI 1 FPGA Options 1 4 FPGA A Select an FPGA part to be supplied in the A position This FPGA is connected to the PCI bus an expansion header and can source global clocks The 12 speed grade is required for full speed operation 1Gbs pair of the interconnect between FPGAs NONE LX100 10 11 12 LX160 10 11 12 LX200 10 11 1 2 FPGA Select an FPGA part to be supplied in the B position This FPGA is connected to an expansion header a memory module socket and can source global clocks The 12 speed grade is required for full speed operation 1 Gbs pair of the interconnect between FPGAs NONE LX100 10 11
158. x16Mb 300Mhz DDRII e Flash module for use in the 200 pin SODIMM header e Mictor module for use in the 200 pin SODIMM header 2 Mictor 38 connectors for use with logic analyzer 143 The Dini Group can optionally provide the following accessories DN3k10SD Daughter card Provides tenth inch pitch test points DNMictor Daughter card Provides 5 Mictor connectors compatible with logic analyzets Memory modules for use in the DN8000K10PCI DDR2 SODIMM sockets A and B Available Q4 05 QDRII SRAM 64 1 300Mhz Flash memory 32 4 2x4Mb serial flash Reduced Latency DRAM RLDRAM 64x8Mb 300Mhz Standard SRAM 64x2M Select ZBT Pipelined Follow through Test connection module with two Mictor38 You may also want to obtain from a third party vendor 200 pin DDR2 SODIMM s SFP modules for Gigabit Ethernet infiniband IBM part 13N1796 from insight com 180 XFP modules Intel part TXN181070850X18 from insight com 692 XFP heatsink clip Tyco part 1542992 2 5 2V bench supply for powering ECL based XFP modules if required Xilinx Parallel IV cable LVPECL oscillators for RocketlO MGT clocking The DN8000K10PCI is supplied with a 250Mhz oscillator Epson Part EG 2102CA PECL Xilinx ChipScope for embedded logic analyzer functionality 144
159. xD driver e Windows 2000 XP Windows WDM e Windows NT e Linux e Solaris 2 1 Functionality The AETEST utility program contains the following tests e PCI Test e Memory Tests GRAM amp DDR e FLASH Test e Daughter Card Test with or without cables e BAR Memory Range Tests AETEST also provides the user with the following abilities DN8000K10PCI User Guide www dinigroup com 41 e Recognize the DN8000K10PCI Display Vendor and Device ID e Set PCI Device and Function Number e Display all configured PCI devices e Various loops for PCI device function and ID numbers e Write and Read Configuration DWORD Write DWORD Read DWORD Write Read DWORD Same Address e BAR Memory Fill Write and Display e Configure Save BAR s from to a file 2 2 Running AETEST 2 3 Compiling AETEST There are two versions of AETest one that controls the DN8000K10PCI from a PCI bus and the other that controls the DN8000K10PCI over a USB connection The source for the PCI vetsion is found on the User CD D PCL_ Softwatre_Applications Aetest The soutce for the USB version is found on the User CD D USB_Software_Applications USB_CMD_Line_AETEST_USB You will likely want to interface to your ASIC emulation project using PCI You may want to start your controller software by modifying and recompiling AETEST 2 39 4 Compiling AETest for DOS The DOS version of AETest requires DJGPP You can find it at http www d

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