Quartus II Introduction Using VHDL Design
Contents
1. IM Include subentities Stop Cancel Nodes Found Selected Nodes PIM_AE 22 Output gt ES lights PIM_N26 Input PIM_N26 Input E Jlighthi2 PIN_N25 Input PIN_N25 Input k EF light f PIM_AE 22 Output a B gt Figure 35 Selecting nodes to insert into the Waveform Editor Click on the x signal in the Nodes Found box in Figure 35 and then click the gt sign to add it to the Selected Nodes box on the right side of the figure Do the same for x2 and f Click OK to close the Node Finder window and then click OK in the window of Figure 34 This leaves a fully displayed Waveform Editor window as shown in Figure 36 If you did not select the nodes in the same order as displayed in Figure 36 it is possible to rearrange them To move a waveform up or down in the Waveform Editor window click on the node name in the Name column and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor I light vwf 14 15 ns Be OOP OOD DIE gt Figure 36 The nodes needed for simulation 21 4 We will now specify the logic values to be used for the input signals x and x2 during simulation The logic values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on2. Import File s Assignment source f File name Ea Bea f Use LogicLock Import File Assignments i Copy existing assignments inte light gst bak before importing Figure 29 Importing the pin assignment For convenience when using large designs all relevant pin assignments for the DE2 board are given in the file called DE2_pin_assignments csv in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages This file uses the names found in the DE2 User Manual If we wanted to make the pin assignments for our example circuit by importing this file then we would have to use the same names in our VHDL design file namely SW 0 SW 1 and LEDG 0 for x1 x2 and f respectively Since these signals are specified in the DE2_pin_assignments csv file as elements of arrays SW and LE DG we must refer to them in the same way in the VHDL design file For example in the DE2_pin_assignments csv file the 18 toggle switches are called SW 17 to SW O since VHDL uses parentheses rather than square brackets these switches are referred to as SW 17 to SW 0 They can also be referred to as an array SW 17 downto 0 18 6 Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip on the DE2 board it is prudent to simulate it to ascertain its correctness Quartus II software includes a simulation tool that can be used to simul
3. Obviously the Compiler recognized that the logic expression in our design file is equivalent to this expression 13 amp Quartus Il D introtutorial light light Seles File Edit View pe o Processing Tools Window Help osua wej eam agelo pi Navigator 4be light vhd Compilation Report Flow Summ By Cyclone Il EP2C35F672C6 2 S lt b light vhd io light LIBRARY ieee USE ieee std logic _1164 all ENTITY light I5 PORT i x1 x2 IN STD LOGIC Compilation Report Flow Summary I Compilation Report Flow Summary amp EB Legal Notice gE Flow Summary Flow Status Successful Mon Aug 08 17 22 41 2005 aE Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 SJ Full v Full Compilation BBS f gm Flow Elapsed Time Revision Name light Analysis amp Synthesis l amp Flow Log Top level Entity Name light Fitter ao LD Analysis amp Synthesis Family Cyclone Il E Assembler A 4a Fitter Device EP2C35F672C6 Timing Analyzer 00 Es Assembler Timing Models Preliminary 5 4a Timing Analyzer Met timing requirements Yes Total logic elements 1 33 216 lt 1 Total registers 0 i Info Command quartus_tan read_settings_files off vwrite_settings_files off light c light timing_analysis_only Si Info Longest tpd from source pin x2 to destination pin F is 5 740 ns in D D p i a For Help press Fi Analysis B Synthesis Equations BE Legal Noti
4. The Hardware Setup window light cdf a Hardware Setup USB Blaster USB 0 Mode JTAG kd Progress es T CATES ae light sof EP2C35F672 O02F76B6 FFFFFFFF Hi Auto Detect Delete ca Add File ie Change File Figure 43 The updated Programmer window 25 Now press Start in the window in Figure 43 An LED on the board will light up when the configuration data has been downloaded successfully If you see an error reported by Quartus II software indicating that programming failed then check to ensure that the board is properly powered on 7 2 Active Serial Mode Programming In this case the configuration data has to be loaded into the configuration device on the DE2 board which is identified by the name EPCS16 To specify the required configuration device select Assignments gt Device which leads to the window in Figure 44 Click on the Device amp Pin Options button to reach the window in Figure 45 Now click on the Configuration tab to obtain the window in Figure 46 In the Configuration device box which may be set to Auto choose EPCS16 and click OK Upon returning to the window in Figure 44 click OK Recompile the designed circuit Settings light Category General Files i User Libraries Current Project Select the family and device you want to target tor compilation Device Timing Requirements amp Options EDA N P Family Cyclone I ie Device amp Pin Options C
5. display 5 Quartus II File Edit View Project Assignment O New Ctl n Open chl o Close Cirl F4 L New Project Wizard Open Project Ctrl Convert MAX PLUS II Project Save Project Close Project led Save Grits Gave As Save Current Report Section As Eile Properties Create Update Export Convert Programming Files Ri Page Setup E Print Preview ee Print Cri P Recent Files Recent Projects Exit Alt F4 Figure 3 An example of the File menu For some commands it is necessary to access two or more menus in sequence We use the convention Menu1 gt Menu2 gt Item to indicate that to select the desired command the user should first click the left mouse button on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit from the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 1 1 Quartus IT Online Help Quartus II software provides comprehensive online documentation that answers many of the questions that may arise when using the software The documentation is accessed from the menu in the Help window To get some idea of the extent of documentation provided it is worthwhile for the reader to browse through the Help menu F
6. latter approach From the list of available devices choose the device called EP2C35F672C6 which is the FPGA used on Altera s DE2 board Press Next which opens the window in Figure 9 New Project Wizard EDA Tool Settings page 4 of X Specify the other EDA tools in addition to the Quartus Il software used with the project EDA design entry 7 synthesit tool EDA simulation bool EDA timing analysis tool lt Back Finish Cancel Figure 9 Other EDA tools can be specified 5 The user can specify any third party tools that should be used A commonly used term for CAD software for electronic circuits is EDA tools where the acronym stands for Electronic Design Automation This term is used in Quartus II messages that refer to third party tools which are the tools developed and marketed by companies other than Altera Since we will rely solely on Quartus II tools we will not choose any other tools Press Next 6 A summary of the chosen settings appears in the screen shown in Figure 10 Press Finish which returns to the main Quartus II window but with light specified as the new project in the display title bar as indicated in Figure 11 New Project Wizard Summary page 5 of 5 Eg When you click Finish the project will be created with the following settings Project directory D fintrotutorial Project name Top level design entity Number of files added Number of user libraries added Device a
7. these lines which can otherwise be invoked by choosing View gt Snap to Grid Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time 0 position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon Is in the toolbar or the Waveform Editing Tool which is activated by the icon _ To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs In a large circuit the number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can simulate all four input valuations given in Figure 12 We will use four 50 ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform name for the x node Once a waveform is selected the editing commands in the Waveform Editor can be used to draw the desired waveforms Commands are available for setting a selected signal to 0 1 unknown X high impedance Z don t care DC inverting its existing value INV or defining a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu
8. EUSR Enable device wide reset DEY_CLAn JEnable device wide output enable DEY OE L JEnable INIT DONE output J Auto usercode JTAG user code 32 bit hexadecimal FFFFFFFF Description Directs the device to restart the configuration process automatically if a data error it encountered If this option it turned off You must externally direct the device to restart the configuration process if an error occurs Reset Figure 45 The Options window Device amp Pin Options Dual Purpose Pins Voltage Pin Placement Error Detection CAC General Configuration Frogramming Files Unused Pins Specify the device configuration scheme and the configuration device Configuration scheme Active Serial can use Configuration Device z Configuration mode Configuration device W Use configuration device Auto r Auto EPCS EPCS4 ERPCS16 W Generate compressed bitstreams Description Specifies the configuration device that you want to use as the means of configuring the target device Figure 46 Specifying the configuration device The rest of the procedure is similar to the one described above for the JTAG mode Select Tools gt Program mer to reach the window in Figure 41 In the Mode box select Active Serial Programming If you are changing the mode from the previously used JTAG mode the pop up box in Figure 47 will appear asking if you want to 21 clear all devices Click Yes Now the
9. Programmer window shown in Figure 48 will appear Make sure that the Hardware Setup indicates the USB Blaster If the configuration file is not already listed in the window press Add File The pop up box in Figure 49 will appear Select the file light pof in the directory introtutorial and click Open As a result the configuration file light pof will be listed in the window This is a binary file produced by the Compiler s Assembler module which contains the data to be loaded into the EPCS16 configuration device The extension pof stands for Programmer Object File Upon returning to the Programmer window click on the Program Configure check box as shown in Figure 50 Quartus II x AN Some devices in current device list cannot be added to selected programming mode Active Serial Programming Do you want to clear all devices in current device list and switch to selected mode mes No Figure 47 Clear the previously selected devices i light cdf BEIE Hardware Setup USE Blaster 056 0 Mode Active Serial Programming Progress A ARES E Add Device i Up Figure 48 The Programmer window with Active Serial Programming selected Select Programming File Look in B introtutorial x a t db File name Jiight pot Files of type POF Files pof Cancel fe Figure 49 Choose the configuration file 28 light cdf es Hardware Setup U5B Blaster 056 0 Mode Active Serial Pro
10. Quartus II Introduction Using VHDL Design This tutorial presents an introduction to the Quartus II CAD system It gives a general overview of a typi cal CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software The design process is illustrated by giving step by step instructions for using the Quartus II software to implement a very simple circuit in an Altera FPGA device The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the VHDL design entry method in which the user specifies the desired circuit in the VHDL hardware description language Two other versions of this tutorial are also available one uses the Verilog hardware description language and the other is based on defining the desired circuit in the form of a schematic diagram The last step in the design process involves configuring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DE2 board will still find the tutorial useful to learn how the FPGA programming and configuration task is performed The screen captures in the tutorial were obtained using the Quartus II version 5 0 if oth
11. TTL D eam R PIN Mi I O Bank 2 Dedicated Clock CLE1 LYDSCLEOn Input A PIN_M2 O Bank 2 Dedicated Clock CLEO LYDSCLEOp Input E PIN_ NO VWoBank2 Row Tid LYDS31p PIN Nes O Bank 5 Dedicated Clock CLE4 LYDSCLEZp Input I Bank 1 Dedicated Clock CLES LYBSCLE1n Input PIN_P1 PIN_P2 LO Bank 1 Dedicated Clock CLEe LYDSCLE1p Input PIN PS WoBanki Row Tid LYDSZ6p DPCLEL DOSILICOIL PIN P4 WoBank1 Row Tid LYDS26n PIN P VWoBank1 Row Tid LYDS22n PIN PF VWoBanki Row lid LYDS22p PIN PS lOBank Row I O LYDS31n Figure 26 The available pins 2 Assignment Editor ii Category Pin Ti All W Pin A Timing Logic Options Information This cell specifies the pin name to which you want to make an assignment Edit xyC Cd 110 Bank 1 0 Standard Figure 27 The complete assignment The DE2 board has fixed pin assignments Having finished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus II feature allows the user to both export and import the pin assignments from a special file format rather than creating them manually using the Assignment Editor A simple file format that can be used for this purpose is the comma separated value CSV format which is a common text file format that contains comma delimited values This file format is often used in conjuncti
12. ate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 1 Open the Waveform Editor window by selecting File gt New which gives the window shown in Figure 30 Click on the Other Files tab to reach the window displayed in Figure 31 Choose Vector Waveform File and click OK New xi Device Design Files Software Files Other Files Block Diagram Schematic File EDIF File Figure 30 Need to prepare a new file New xj Device Design Files Software Files Other Files AHDL Include File Block Symbol File Chain Description File Hexadecimal Intel Format File Memory Initialization File signalTap Il File Vector Waveform File Figure 31 Choose to prepare a test vector file 19 2 The Waveform Editor window is depicted in Figure 32 Save the file under the name ight vwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 200 ns by selecting Edit gt End Time and entering 200 ns in the dialog box that pops up Selecting View gt Fit
13. ave the file by typing File gt Save or by typing the shortcut Ctrl s Device Design Files Software Files Other Files AHEL File Block DiagramS chematic File EDIF File Verilog HOL File Figure 14 Choose to prepare a VHDL file Save As Save in E introtutorial ga db File name ligh cave Save as type VHDL File vhd vhdl Cancel I Add file to current project Figure 15 Name the file d light vhd Figure 16 Text Editor window 1 Most of the commands available in the Text Editor are self explanatory Text is entered at the insertion point which is indicated by a thin vertical line The insertion point can be moved either by using the keyboard arrow keys or by using the mouse Two features of the Text Editor are especially convenient for typing VHDL code First the editor can display different types of VHDL statements in different colors which is the default choice Second the editor can automatically indent the text on a new line so that it matches the previous line Such options can be controlled by the settings in Tools gt Options gt Text Editor 3 1 1 Using VHDL Templates The syntax of VHDL code is sometimes difficult for a designer to remember To help with this issue the Text Editor provides a collection of VHDL templates The templates provide examples of various types of VHDL statements such as an ENTITY declaration a CASE statement and assignment statements It is wo
14. by using the logic expressions that define the circuit 22 6 1 1 Functional Simulation To perform the functional simulation select Assignments gt Settings to open the Settings window On the left side of this window click on Simulator to display the window in Figure 38 choose Functional as the simulation mode and click OK The Quartus II simulator takes the inputs and generates the outputs defined in the light vwf file Before running the functional simulation it is necessary to create the required netlist which is done by se lecting Processing gt Generate Functional Simulation Netlist A simulation run is started by Processing gt Start Simulation or by using the icon F At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure 39 If your report window does not show the entire simulation time range click on the report window to select it and choose View gt Fit in Window Observe that the output f is as specified in the truth table of Figure 12 Settings light Category General Files User Libraries Device Timing Requirements amp Options a EDA Tool Settings Select options for simulation Note the availability of same options depends on the current device family Design Entry Synthesis Simulation mode famed Simulation oo Timing Analysis i cslocaresla ls rc ec ee Board Level Formal Verifica
15. can also be opened by right clicking on a waveform name Set x to O in the time interval O to 100 ns which is probably already set by default Next set xZ to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 50 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 12 This should produce the image in Figure 37 Observe that the output f is displayed as having an unknown value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the file t light vwf ox 4 Pointer 128 07 ns Interval 128 07 ns Start End 40 0 ng 30 0 ng 120 0 ng 160 0 ng a a a a a a a A M a Figure 37 Setting of test values 6 1 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply
16. ce hiL2 x2 xi BES Flow Summary EB Flow Settings Em Flow Elapsed Time xX2 S xe SB Flow Log operation mode is input J Analysis amp Synthesis S Summary j H Settings SE Source Files Read x1 is xi SBE Resource Usage Summary operation mode is input Bm Resource Utilization by Entity ni SL Sacel Results x1 INPUT B Equations VD Mee Fitter Assembler Timing Analyzer OUTPUT ALL2Z x2 INPUT f is f operation mode is output Figure 20 Compilation report showing the synthesized equations 4 1 Errors Quartus I software displays messages produced during compilation in the Messages window If the VHDL design file is correct one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the VHDL code In this case a message corresponding to each error found will be displayed in the Messages window Double clicking on an error message will highlight the offending statement in the VHDL code in the Text Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of 14 error messages The user can obtain more information about a specific error or warning message by selecting the message and pressing the F1 function key To see the effect of an error open the file light vhd Remove the semicolon in the state
17. ct Pin Double click on the entry lt lt new gt gt which is highlighted in blue in the column labeled To The drop down menu in Figure 25 will appear Click on x1 as the first pin to be assigned this will enter x1 in the displayed table Follow this by double clicking on the box to the right of this new x1 entry in the column labeled Location Now the drop down menu in Figure 26 appears Scroll down and select PIN N25 Instead of scrolling down the menu to find the desired pin you can just type the name of the pin N25 in the Location box Use the same procedure to assign input x2 to pin N26 and output f to pin AE22 which results in the image in Figure 27 To save the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a pop up box will ask if you want to save the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignments Assignment Editor Category Pin T All E Fin A Timing Logic Options Information This cell specifies the pin name to which you want to make an assignment gt Double click bo create a new assignment EE to ecation O Bank PO Standard General Function Special Function X X X Figure 24 The Assignment Editor window Figure 25 The drop down menu displays the input and output names 16 Location 1O Bank I O Standard General Function Special Fun LY
18. e this connection it is necessary to have the USB Blaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DE2 Board for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the configuration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group defined a simple way for testing digital circuits and loading data into them which became an IEEE standard If the FPGA is configured in this manner it will retain its configuration as long as the power remains turned on The configuration information is lost when the power is turned off The second possibility is to use the Active Serial AS mode In this case a configuration device that includes some flash memory is used to store the configuration data Quartus II software places the configuration data into the configuration device on the DE2 board Then this data is loaded into the FPGA upon power up or reconfiguration Thus the FPGA need not be configured by the Quartus II software if the power is turned off and on The choice between the two modes is made by the RUN PROG switch on the DE2 board The RUN position selects the JTAG mode while the PROG position selects the AS mode 7 1 JTAG Programming The programming and configuration task is performed as foll
19. er versions of the software are used some of the images may be slightly different Contents Typical CAD flow Getting started Starting a New Project VHDL Design Entry Compiling the Design Pin Assignment Simulating the Designed Circuit Programming and Configuring the FPGA Device Testing the Designed Circuit Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a pro grammable logic device such as a field programmable gate array FPGA chip A typical FPGA CAD flow is illustrated in Figure 1 Design Entry Functional Simulation No Design correct Yes Timing Analysis and Simulation Timing requirements met Yes Programming and Configuration Figure 1 Typical CAD flow The CAD flow involves the following steps e Design Entry the desired circuit is specified either by means of a schematic diagram or by using a hardware description language such as VHDL or Verilog e Synthesis the entered design is synthesized into a circuit that consists of the logic elements LEs provided in the FPGA chip e Functional Simulation the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues e Fitting the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connection
20. gramming Progress mt a cove Yi Genk amp light pat EPCS16 1C79348E O O W Delete ie Change File Figure 50 The updated Programmer window Flip the RUN PROG switch on the DE2 board to the PROG position Press Start in the window in Figure 50 An LED on the board will light up when the configuration data has been downloaded successfully Also the Progress box in Figure 50 will indicate when the configuration and programming process is completed as shown in Figure 51 light cdf oS Hardware Setup USB Blaster 056 0 ma cove Yi thc light pat EPCS16 1C79348E O O W Delete ie Change File Figure 51 The Programmer window upon completion of programming 8 Testing the Designed Circuit Having downloaded the configuration data into the FPGA device you can now test the implemented circuit Flip the RUN PROG switch to RUN position Try all four valuations of the input variables x and x2 by setting the corresponding states of the switches SW and SWo Verify that the circuit implements the truth table in Figure 12 If you want to make changes in the designed circuit first close the Programmer window Then make the desired changes in the VHDL design file compile the circuit and program the board as explained above 29 Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and al
21. in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 33 You may wish to resize the window to its maximum size light vwf Jojx Master Time Bar 14 15 ns gt Pointer 1 0 ns Interval 13 15ns Start End Name 14 15 ns sececececessceseeoseeosesscescecsoessesseesscoseessesscessessesso 120 0 ns 160 0 ns 200 0 ns Name cececccecesecosocesececesscoscceccoscesscesccoscescssecsscesseesod Figure 33 The augmented Waveform Editor window 3 Next we want to include the input and output nodes of the circuit to be simulated Click Edit gt Insert Node or Bus to open the window in Figure 34 It is possible to type the name of a signal pin into the Name box but it is easier to click on the button labeled Node Finder to open the window in Figure 35 The Node Finder utility has a filter used to indicate what type of nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List button to find the input and output nodes as indicated on the left side of the figure 20 Insert Node or Bus Name Type INPUT Cancel Value type J Level be Node Finder Radix Binary gt Bus width i Start index fo M Display gray code count as binary count Figure 34 The Insert Node or Bus dialogue Node Finder Named f Filter Pins all Customize List Look in ligt
22. itor that stores ASCII files or by using the Quartus II text editing facilities While the file can be given any name it is a common designers practice to use the same name as the name of the top level VHDL entity The file name must include the extension vhd which indicates a VHDL file So we will use the name light vhd LIBRARY ieee USE ieee std_logic_1164 all ENTITY light IS PORT x1 x2 IN STD_LOGIC f OUT STD_LOGIC END light ARCHITECTURE LogicFunction OF light IS BEGIN f lt xl AND NOT x2 OR NOT x1 AND x2 END LogicFunction Figure 13 VHDL code for the circuit in Figure 12 3 1 Using the Quartus IT Text Editor This section shows how to use the Quartus II Text Editor You can skip this section if you prefer to use some other text editor to create the VHDL source code file which we will name light vhd Select File gt New to get the window in Figure 14 choose VHDL File and click OK This opens the Text Editor window The first step is to specify a name for the file that will be created Select File gt Save As to open the pop up box depicted in Figure 15 In the box labeled Save as type choose VHDL File In the box labeled File name type light Put a checkmark in the box Add file to current project Click Save which puts the file into the directory introtutorial and leads to the Text Editor window shown in Figure 16 Maximize the Text Editor 10 window and enter the VHDL code in Figure 13 into it S
23. l other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 30
24. les you want to include in the project Click Add All to add all design files in the project directory to the project Mote you can always add design files to the project later File name ae File name Type Add All Specify the path names of any non default libraries User Libraries g Back Finish Cancel Figure 7 The wizard can include user specified design files 3 The wizard makes it easy to specify which existing files if any should be included in the project Assuming that we do not have any existing files click Next which leads to the window in Figure 8 New Project Wizard Family amp Device Settings p Eg Select the family and device you want to target for compilation Family Cyclone Target device f Auto device selected by the Fitter from the Available devices list Specific device selected in Available devices list Available devices EP2C20F256C6 EP2C20F 2560 Package Ary EP2C20F 25608 Filters Pin count Ary Speed grade Ary EP2C20F 48408 EP2C20F 48418 Core voltage 1 2 W Show Advanced Devices TE EP2CS0F 45406 Advanced Figure 8 Choose the device family and a specific device 4 We have to specify the type of device in which the designed circuit will be implemented Choose Cyclone II as the target device family We can let Quartus II software select a specific device in the family or we can choose the device explicitly We will take the
25. low Settings a Info Command quartus_map read_settings_files on write_settings_files off light c light Se Flow Elapsed Time Error WHOL syntax error at light vhdf 2 near text END expecting pi 4B Flow Log Pee eal cn sk 0 entities in ree eit HE Analysis amp Synthesis mor Quartus Analysis amp Synthesis was unsuccessful 1 error 0 warnings SHE Summary 1 Settings BE Source Files Read Si Messages d light vhd LIBRARY ieee USE ieee std logic 1164 all ENTITY light IS PORT xi Z IN STD LOGIC f OUT STD_LOGIC j END light ARCHITECTURE LogicFunetion OF light I5 BEGIN lt ixi AND NOT x2 GR NOT x1 AND x2 LogicFunction Figure 23 Identifying the location of the error 15 5 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DE2 board has hardwired connections between the FPGA pins and the other components on the board We will use two toggle switches labeled SW o and SW to provide the external inputs x and x2 to our example circuit These switches are connected to the FPGA pins N25 and N26 respectively We will connect the output f to the green light emitting diode labeled LE DGo which is hardwired to the FPGA pin AE22 Pin assignments are made by using the Assignment Editor Select Assignments gt Pins to reach the window in Figure 24 Under Category sele
26. lready a part of the project and will be listed in the 12 window in Figure 17 Otherwise the file must be added to the project So if you did not use the Quartus II Text Editor then place a copy of the file light vhd which you created using some other text editor into the directory introtutorial To add this file to the project click on the File name button in Figure 17 to get the pop up window in Figure 18 Select the light vhd file and click Open The selected file is now indicated in the Files window of Figure 17 Click OK to include the light vhd file in the project We should mention that in many cases the Quartus II software is able to automatically find the right files to use for each entity referenced in VHDL code even if the file has not been explicitly added to the project However for complex projects that involve many files it is a good design practice to specifically add the needed files to the project as described above Select File Look in CO introtutorial File name llight vhd Files of type Design Files tdi vhds vhdlvevlg vhi Y Cancel Figure 18 Select the file 4 Compiling the Designed Circuit The VHDL code in the file light vhd is processed by several Quartus II tools that analyze the code synthesize the circuit and generate an implementation of it for the target chip These tools are controlled by the application program called the Compiler Run the Compiler by selecting Processing gt Star
27. ment that defines the function f illustrating a typographical error that is easily made Compile the erroneous design file by clicking on the icon A pop up box will ask if the changes made to the light vhd file should be saved click Yes After trying to compile the circuit Quartus II software will display a pop up box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report summary given in Figure 21 now confirms the failed result Expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 22 Double click on the first error message Quartus II software responds by opening the light vhd file and highlighting the statement which is affected by the error as shown in Figure 23 Correct the error and recompile the design Compilation Report Flow Summary y Compilation Report 4 Legal Notice SE Flow Summary Flow Status Flow Failed Tue 4ug 09 13 42 09 2005 SE Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 SJ Full version am Flow Elapsed Time Revision Name light BEB Flow Log Top level Entity Mame light E Analysis amp Synthesis Family Cyclone II Device EP2C35Fe 7206 Timing Models Preliminary Met timing requirements M A Figure 21 Compilation report for the failed design SE Compilation Report SEB Legal Notice 2 Bg Flow Summary D Info Running Quartus Il Analysis amp Synthesis 2m F
28. ompilation Process Settings Analysis amp Synthesis Settings Fitter Settings Timing Analyzer Specific device selected in Available devices list i Target device Auto device selected by the Fitter from the Available devices list Design Assistant Ome i SignalT ap Il Logic Analyzer signalProbe settings Available devices show in Available devices list Poel EP2C8F256C Advanced PowerPlay Power Analyzer Settings EP2C8F 25608 Advanced Software Build Settings EP2C8F 25618 Advanced HardCopy Settings EP2CeQ208C Advanced Package Ary ki Fin count Any EP2C80208C8 Advanced lay titi EP2C80 20818 advanced apran gane Any EP2C8T 144 C6 Advanced Core voltage 1 24 EPR2C8T144C7 Advanced i l EP2C8T 14408 Advanced W Show advanced devices EP2C8T7 14418 Advanced Migration compatibility EP2C20F256C8 O migration devices selected EP2C20F 25618 Migration Devices EP2C20F 45416 EP2U35F 45406 EP CS5F4e4l6 EP2L Sore f2C6 Figure 44 The Device Settings window 26 Device amp Pin Options Dual Purpose Pins Voltage Fin Flacement Error Detection CAC General Configuration Frogramming Files Unused Pins Specify general device options These options are not dependent on the configuration scheme Options M Auto restart configuration after error Release clears before tr states Enable user supplied start up clock CL
29. on with the Microsoft Excel spreadsheet program but the file can also be created by hand using any plain ASCII text editor The format for the file for our simple project is To Location xl PIN_N25 x2 PIN_N26 f PIN _AE22 By adding lines to the file any number of pin assignments can be created Such csv files can be imported into any design project If you created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 27 Now select File gt Export which leads to the window in Figure 28 Here the file light csv is available for export Click on Export If you 17 now look in the directory introtutorial you will see that the file light csv has been created Save Ire B introtutorial dh File name ight ce Save as pe Comma Separated Value File cs ki Cancel Figure 28 Exporting the pin assignment You can import a pin assignment by choosing Assignments gt Import Assignments This opens the dia logue in Figure 29 to select the file to import Type the name of the file including the csv extension and the full path to the directory that holds the file in the File Name box and press OK Of course you can also browse to find the desired file Import Assignments Specify the source and categories of assignments to import Click LogicLock Import File Assignments to select LogicLock
30. or instance selecting Help gt How to Use Help gives an indication of what type of help is provided The user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which key words can be entered Another method context sensitive help is provided for quickly finding documentation for specific topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 2 Starting a New Project To start working on a new design we first have to define a new design project Quartus II software makes the designer s task easy by providing support in the form of a wizard Create a new project as follows 1 Select File gt New Project Wizard to reach the window in Figure 4 which indicates the capability of this wizard You can skip this window in subsequent projects by checking the box Don t show me this intro duction again Press Next to get the window shown in Figure 5 New Project Wizard Introduction The New Project Wizard helps vou create a new project and preliminary project settings including the Following Project name and directory Name of the top level design entity Project files and libraries Target device family and device EDA tool settings You can change the settings for an existing project and specify additional project wide settings with the Settings command Assignments menu You can use
31. ows Flip the RUN PROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 41 Here it is necessary to specify the programming hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up as shown in Figure 42 24 Ui light cdf 2 Hardware Setup UISB Blaster USB 0 Mode JTAG kd Progress ao pe p p light of EP2C359F672 0O O 0O 0O Q02F76B6 FFFFFFFF Hi Auto Detect ca Add File Figure 41 The Programmer window Observe that the configuration file ight sof is listed in the window in Figure 41 If the file is not already listed then click Add File and select it This is a binary file produced by the Compiler s Assembler module which contains the data needed to configure the FPGA device The extension sof stands for SRAM Object File Note also that the device selected 1s EP2C35F672 which is the FPGA device used on the DE2 board Click on the Program Configure check box as shown in Figure 43 Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the curent programmer window Currently selected hardware r Available hardware items USB Blaster Local Figure 42
32. rst step is to create a directory to hold its files To hold the design files for this tutorial we will use a directory introtutorial The running example for this tutorial is a simple circuit for two way light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that are located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the left button is used Hence we will not normally specify which button to press In the few cases when it is necessary to use the right mouse button it will be specified explicitly Quartus Il File Edit View Project Assignments Processing Tools Window Help Project Navigator Entity d Compilation Hierarchy QUARTUS II dp Hierarchy E Files d Design Units Version 5 0 Status http www altera com Estra Info Critical waming A Eror Message t Location r Locate For Help press F1 ih a Idle 5 essages x Figure 2 The main Quartus II
33. rthwhile to browse through the templates by selecting Edit gt Insert Template gt VHDL to become familiar with this resource 3 2 Adding Design Files to a Project As we indicated when discussing Figure 7 you can tell Quartus II software which design files it should use as part of the current project To see the list of files already included in the light project select Assignments gt Settings which leads to the window in Figure 17 As indicated on the left side of the figure click on the item Files An alternative way of making this selection is to choose Project gt Add Remove Files in Project Settings light Category Files User Libraries Current Project Select the design files you want to include in the project Click Add All to add all design files in the Device project directory to the project Timing Requirements amp Options EDA Tool Settings Fil ate Compilation Process Settings eee l Analysis amp Synthesis Settings File name Type Add All Fitter Settings light hd VHDL File Fe Timing Analyzer Design Assistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator PowerPlay Power Analyzer Settings Software Build Settings Fioperties HardCopy Settings Cancel Figure 17 Settings window If you used the Quartus II Text Editor to create the file and checked the box labeled Add file to current project as described in Section 3 1 then the light vhd file is a
34. s gt Simulator to get to the window in Figure 38 choose Timing as the simulation mode and click OK Run the simulator which should produce the waveforms in Figure 40 Observe that there is a delay of about 6 ns in producing a change in the signal f from the time when the input signals x and x2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device You may also notice that a momentary change in the value of f from 1 to O and back to 1 occurs at about 106 ns point in the simulation This glitch is also due to the propagation delays in the FPGA device because changes in z and x2 may not arrive at exactly the same time at the logic element that generates f Simulation Waveforms Masher Time Bar 4 Pointer 698 ps Interval B98 ps Start End 40 0 ng 30 0 ng 120 0 ng 160 0 ng Figure 40 The result of timing simulation 7 Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit The required configura tion file is generated by the Quartus II Compiler s Assembler module Altera s DE2 board allows the configuration to be done in two different ways known as JTAG and AS modes The configuration data is transferred from the host computer which runs the Quartus II software to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To us
35. s between specific LEs e Timing Analysis propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit e Timing Simulation the fitted circuit is tested to verify both its functional correctness and timing e Programming and Configuration the designed circuit is implemented in a physical FPGA chip by pro gramming the configuration switches that configure the LEs and establish the required wiring connections This tutorial introduces the basic features of the Quartus II software It shows how the software can be used to design and implement a circuit specified by using the VHDL hardware description language It makes use of the graphical user interface to invoke the Quartus II commands Doing this tutorial the reader will learn about e Creating a project e Design entry using VHDL code e Synthesizing a circuit specified in VHDL code e Fitting a synthesized circuit into an Altera FPGA e Assigning the circuit inputs and outputs to specific pins on the FPGA e Simulating the designed circuit e Programming and configuring the FPGA chip on Altera s DE2 board 1 Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project The software works on one project at a time and keeps all information for that project in a single directory folder in the file system To begin a new logic circuit design the fi
36. ssignments Family name Cyclone Il Device EP2C35F672C6 EDA tool Design entm synthesis None gt Simulation None gt Timing analysis None gt lt Back Hert gt Cancel Figure 10 Summary of the project settings Quartus Il D introtutorial light light File Edit View Project Assignments Processing Tools Window Help Doe bed Sew gt RP light PER A AE Project Navigator ajx Cyclone Il EP2C35F672C6 OUARTUS II Version 5 0 http www altera com Critical Warming A Eror Lopate For Help press F1 Figure 11 The Quartus II display for the created project 3 Design Entry Using VHDL Code As a design example we will use the two way light controller circuit shown in Figure 12 The circuit can be used to control a single light from either of the two switches x and x2 where a closed switch corresponds to the logic value The truth table for the circuit is also given in the figure Note that this is just the Exclusive OR function of the inputs x and x2 but we will specify it using the gates shown X an 5O 5D 0 l l 0 OF OO X2 Figure 12 The light controller circuit The required circuit is described by the VHDL code in Figure 13 Note that the VHDL entity is called light to match the name given in Figure 5 which was specified when the project was created This code can be typed into a file by using any text ed
37. t Compilation or by clicking on the toolbar icon that looks like a purple triangle As the compilation moves through various stages its progress is reported in a window on the left side of the Quartus II display Successful or unsuccessful compilation is indicated in a pop up box Acknowledge it by clicking OK which leads to the Quartus II display in Figure 19 In the message window at the bottom of the figure various messages are displayed In case of errors there will be appropriate messages given When the compilation is finished a compilation report is produced A window showing this report is opened automatically as seen in Figure 19 The window can be resized maximized or closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon The report includes a number of sections listed on the left side of its window Figure 19 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are needed to implement this tiny circuit on the selected FPGA chip Another section is shown in Figure 20 It is reached by selecting Analysis amp Synthesis gt Equations on the left side of the compilation report Here we see the logic expressions produced by the Compiler when synthesizing the designed circuit Observe that f is the output derived as 7 025 71 where the sign is used to represent the Exclusive OR operation
38. the various pages of the Settings dialog bos to add functionality to the project Dont show me this introduction again tens crea Figure 4 Tasks performed by the wizard New Project Wizard Directory Name Top Level Eg What is the working directory for this project D introtutorial 7 ae What is the name of this project light What is the name of the top level design entity for this project This name it case sensitive and must exactly match the entity name in the design file light ka Use Existing Project Settings Finish Cancel Figure 5 Creation of a new project 2 Set the working directory to be introtutorial of course you can use some other directory name of your choice if you prefer The project must have a name which is usually the same as the top level design entity that will be included in the project Choose light as the name for both the project and the top level entity as shown in Figure 5 Press Next Since we have not yet created the directory introtutorial Quartus II software displays the pop up box in Figure 6 asking if it should create the desired directory Click Yes which leads to the window in Figure 7 Quartus II x AN Directory D Antrotutorial does not exist Do you want to create it Yes No Figure 6 Quartus II software can create a new directory for the project New Project Wizard Add Files page 2 of 5 Eg Select the design fi
39. tion Physical Synthesis Le Conipilation Process Settings oo Early Timing Estimate Analysis amp Synthesis Settings Fitter Settings Physical Synthesis Optimizations H Timing Analyzer Design Assistant Simulation period Run simulation until all vector stimuli are used C End simulation at ns i Automatically add pins to simulation output waveforms T Check outputs M Setus and tald time vidlation detection SignalTap Il Logic Analyzer l a abn m ap 7 gt Glitch detection i ns Simulator M Simulation coverage reporting H PowerPlay Power Analyzer Settings H Software Build Settings HardCopy Settings F Overwrite simulation input file with simulation results uPCore lransacton Model File Name ivy Signal activity output for power analysis l Generate Signal Activity File Filename lightsat gt l signal Actwity File Options cre 4 Figure 38 Specifying the simulation mode Simulation Waveforms Master Time Bar etiba a Pointer alelPorter 9886r 196 84 ns Interval menat 19884m 196 84 ns Start End 120 0 ne 160 0 ns Name Figure 39 The result of functional simulation 23 6 1 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select Assignments gt Setting
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