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Datasheet - STMicroelectronics

1. ARS HOC Flexible static memory controller FSMC 25 0 D 15 0 NOE NWE eie SRAM PSRAM NOR Flash NWAIT INT3 as AF JTCK SWCLK JTAG amp SW MPU NAND Flash b JTDO SWD JTDO Em MVC TRACECLK i BK1 IO 3 0 TRACED 3 0 D BUS Quad SPI memory interface D eK ARM Cortex M4 NCS 80 MHz HBUS Eus S BUS Y AES VDDUSB SRAM 96 DP USB gt lt gt DM 2 K gt SRAM 32 KB BIS SCL SDA INTN ID VBUS SOF AHB2 80 MHz Power management DMA Voltage VDD 1 71 to 3 6 V regulator C o T m DMA1 vDD Q VDD MSI reset lt supervision 8 Groups of oe VDDIO VDDUSB Touch sensing controller RC HSI Int A dinde max AE Nc BOR lt VDDA VSSA RCLSI VDD VSS NRST PISO PVD PVM L 1 5 PLL18283 46 x lt cio PoRTB C EB _ 8 XTAL OSC gt OSC_IN PC 15 0 GPIO PORT C lt lt i 4 16MHz OSC OUT nso lt gt E gt 5 0
2. 22 6 OOOO 3 19 9 gt 22 6 gt ai14905e 1 Dimensions are expressed in millimeters DoclD025977 Rev 4 211 231 Package information STM32L486xx 212 231 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 50 LQFP144 marking package top view Optional gate mark Revision code Product identification 1 Ly O LI Date code e Pin 1 identifier 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity MSv36849V2 q DocID025977 Rev 4 STM32L486xx Package information 7 2 q UFBGA132 package information Figure 51 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package outline C Seating plane 4 2 3m A1 ball identifier 1 BOTTOM VIEW e A B
3. Symbol Parameter Conditions Min Typ Max Unit ONL Differential non DAC output buffer ON 2 N as 2 linearity 2 DAC output buffer OFF 3 2 monotonicity 10 bits guaranteed DAC output buffer ON _ _ 4 Integral non CL lt 50 pF RL 2 5 2 INL li 3 inearity DAC output buffer OFF _ _ CL x 50 pF no RL U 3 6V 12 DAC output buffer ON TM Offset error at CL lt 50 pF RL 2 5 _ Offset code 0 800 1 8V 25 DAC output buffer OFF _ 8 CL lt 50 pF no RL Offset error at DAC output buffer OFF Offset code 0x001 CL 50 pF RL VREF 3 6V 5 OffsetCal 0 000 output buffer ON ft librati CL lt 50 pF RL gt 5 atter VREF 1 8V 7 166 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 70 DAC accuracy continued Symbol Parameter Conditions Min Typ Max Unit DAC output buffer ON _ 405 CL lt 50 pF RL gt 5 zo Gain Gain error DAC output buffer OFF _ _ 10 5 CL lt 50 pF no RL UU DAC output buffer ON Total CL 50 pF RL 2 5 kQ i ta TUE unadjusted LSB error DAC output buffer OFF _ 12 CL lt 50 pF no RL E Total unadjusted DAC output buffer ON error after CL lt 50 pF RL gt 5 i 29 USE calibration DAC output buffer ON CL lt 50
4. Symbol Parameter Min Max Unit tw NE FMC_NE low time 0 5 2 FMC_NEx low to FMC NOE low 2 0 5 2TycLK 0 5 NOE low time 0 5 Tucik 1 NOE high to NE high hold time 0 tA FMC NEx low A valid 5 3 twNaDV_NE FMC_NEx low to FMC_NADV low 0 1 twNApv NADV low time 0 5 1 D RAD valid hold time after 0 _ gh th A NOE Address hold time after FMC_NOE high 0 5 BL time after FMC NOE high 0 tg FMC_NEx low to FMC BL valid 2 NE Data to FMC_NEx high setup time 2 tsu Data_NOE Data to NOE high setup time 1 x tn pata NE Data hold time after FMC_NEx high 0 th Data NOE Data hold time after FMC_NOE high 0 1 CL 30 pF 2 Guaranteed by characterization results Table 95 Asynchronous multiplexed PSRAM NOR read NWAIT timings Symbol Parameter Min Max Unit tw NE FMC_NE low time 8Tucikt2 8 1 4 FMC NWE low time 5Tucuc1 5 1 5 tsu NWAIT_NE FMC_NWAIT valid before FMC_NEx high 5 1 5 E nwar FMC_NEx hold time after FMC_NWAIT invalid 4Tyc_Kt1 1 CL 30 pF 2 Guaranteed by characterization results q DocID025977 Rev 4 197 231 Electrical character
5. Symbol Parameter Conditions Min Typ Max Unit fpp Clock frequency in data transfer mode 0 50 MHz SDIO CK fPCLK2 frequency ratio 4 3 tw CKL Clock low time 50 MHz 8 10 ns tw CkH Clock high time fpp 50 MHz 8 10 ns CMD D inputs referenced to CK in MMC and SD HS mode tisu Input setup time HS 50 MHz 2 ns Input hold time HS fpp 50 MHz 4 5 ns CMD D outputs referenced to CK in MMC and SD HS mode tov Output valid time HS fpp 50 MHz 12 14 ns toH Output hold time HS 50MHz 9 i ns CMD D inputs referenced to CK in SD default mode tisup Input setup time SD fpp 50 MHz 2 ns Input hold time SD fpp 50 MHz 4 5 ns q DocID025977 Rev 4 STM32L486xx Electrical characteristics q Table 87 SD MMC dynamic characteristics Vpp 2 7 V to 3 6 Vl continued Symbol Parameter Conditions CMD D outputs referenced to CK in SD default mode Min Typ Max Unit tovp Output valid default time SD fpp 50 MHz Output hold default time SD fpp 50 MHz 1 Guaranteed by characterization results Table 88 eMMC dynamic characteristics 1 71 V to 1 9 V 1 2 Symbol Parameter Conditions Min Typ Max Unit fpp Clock frequency in data transfer mode 0 50 MHz SDIO CK fpci o f
6. AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 COMP4 2 15 UART5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC 2 16 17 EVENTOUT LPUART1 SWPMI LPTIM2 PFO 0 EVENTOUT PF1 3 FMC A1 EVENTOUT PF2 FMC A2 EVENTOUT PF3 FMC A3 EVENTOUT PF4 FMC A4 EVENTOUT PF5 _ 5 EVENTOUT PF6 SAM SD B EVENTOUT a _ _ Port B PF8 SAM SCK B EVENTOUT PF9 SAM FS B TIM15 CH1 EVENTOUT PF10 E TIM15 CH2 EVENTOUT PF11 EVENTOUT PF12 FMC A6 EVENTOUT PF13 FMC A7 EVENTOUT PF14 TSC G8 101 A8 EVENTOUT PF15 TSC G8 102 A9 EVENTOUT uonduosep uid pue sjnouid 987 1ZEINLS y ed 2 6 20 LEc Z8 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued AF8 AF9 AF10 AF11 AF12 AF13 AF 14 AF15 Port UART4 SDMMC1 COMP1 TIM2 TIM15 UARTS CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PGO TSC G8 IO3 FMC A10 EVENTOUT PG1 TSC G8 104 FMC A11 EVENTOUT PG2 FMC A12 SAI2 SCK B EVENTOUT PG3 FMC A13 SAI2 FS B EVE
7. Multi Speed Internal MSI Clock Security System CSS 9 9 a EM Clock Security System on LSE o o OO O O Of I RTC Auto wakeup O O O O O 3 3 3 3 EM 3 EN O O 3 Tamper pins LCD Ly DoclD025977 Rev 4 27 231 Functional overview STM32L486xx Table 5 Functionalities depending on the working mode continued Stop 0 1 Stop 2 Standby Shutdown Low Low 5 5 5 5 Sleep power power 8 8 8 8 VBAT run sleep 5 2 gt gt USB OTG FS o9 o9 2 I Em Emm a E USARTx _ _ _ _ _ x 1 2 3 4 5 9 B 2 Oo Low power UART 6 6 6 6 _ T _ LPUART I2Cx x 1 2 o o pd MEM p I2C3 00 00 o onj SPIx x 1 2 3 E z SDMMC1 E i 2 SWPMI1 3 2 SAlx 1 2 3 E DFSDM E gt ADCx x 1 2 3 i DACx 1 2 VREFB
8. 186 SD MMC dynamic characteristics VDD 2 7 03 6 188 eMMC dynamic characteristics VDD 1 71 01 9 189 USB electrical 191 Asynchronous non multiplexed SRAM PSRAM NOR read timings 194 Asynchronous non multiplexed SRAM PSRAM NOR read NWAIT timings 194 Asynchronous non multiplexed SRAM PSRAM NOR write timings 195 Asynchronous non multiplexed SRAM PSRAM NOR write NWAIT timings 196 DoclD025977 Rev 4 7 231 List of tables STM32L486xx Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 8 231 Asynchronous multiplexed PSRAM NOR read timings 197 Asynchronous multiplexed PSRAM NOR read NWAIT timings 197 Asynchronous multiplexed PSRAM NOR write timings 199 Asynchronous multiplexed PSRAM NOR write NWAIT timings 199 Synchronous multiplexed NOR PSRAM read timings 201 Synchronous multiplexed PSRAM write 203 Synchronous non multiplexed NOR PSRAM read timings
9. Z la b pas a Detail A Seating plane q Z 5999 7 rotated by 90 A02R ME V1 1 Drawing is not to scale Table 108 WLCSP72 72 ball 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 525 0 555 0 585 0 0207 0 0219 0 0230 A1 0 175 0 0069 2 I 0 380 0 0150 A30 0 025 0 0010 b 0 220 0 250 0 280 0 0087 0 0098 0 0110 D 4 3734 4 4084 4 4434 0 1722 0 1736 0 1749 E 3 7244 3 7594 3 7944 0 1466 0 1480 0 1494 e 0 400 I 0 0157 1 3 200 E 0 1260 2 3 200 0 1260 0 6042 0 0238 DoclD025977 Rev 4 219 231 Package information STM32L486xx Table 108 WLCSP72 72 ball 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max G 0 2797 0 0110 aaa 0 100 0 0039 bbb 0 100 0 0039 ccc 0 100 0 0039 ddd 0 050 0 0020 eee 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Back side coating 3 Dimension is measured at the maximum bump diameter parallel to primary datum Z Figure 58 WLCSP72 72 ball 4
10. 49 52 Legend abbreviations used in the pinout table 60 STM32L486xx pin definitions 61 Alternate function AFO to for AF8 to AF15 see Table 17 74 Alternate function AF8 to AF15 for AFO to AF7 see Table 16 81 STM32L486xx memory map and peripheral register boundary addresses cose suyuyuq on a AUD OA UR Go V 90 Voltage 96 Current characteristics 97 Thermal 97 General operating conditions 98 Operating conditions at power up power down 99 Embedded reset and power control block 100 Embedded internal voltage 102 Current consumption in Run and Low power run modes code with data processing running from Flash ART enable Cache ON Prefetch OFF 105 Current consumption in Run and Low power run modes code with data processing running from Flash AR
11. 125 DoclD025977 Rev 4 Ly STM32L486xx List of tables Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Ly Regulator modes transition 127 High speed external user clock 5 127 Low speed external user clock 128 HSE oscillator 129 LSE oscillator characteristics fj sg 32 768 2 130 HSI16 oscillator 132 MSI oscillator 134 LSI oscillator 137 PLL PLLSAM PLLSAI2
12. Analog supply Vrs 1 2 8 3 6 VppA voltage g 0 1 65 2 4 Degraded mode 2 Vgs 7 1 1 65 2 8 V Ves 0 2 046 2 048 2 0499 Normal mode V Voltage Vas 1 2 4989 2 5 2 5029 REFBUF reference Y ead Y OUT m E output Degraded mode RS DDA DDA Vrs 1 Vppa 1 50 mV VppA Trim step L A 0 05 30 1 resolution CL Load capacitor 0 5 1 1 5 HF Equivalent esr Serial Resistor 2 of Cload Static load 7 1 ma 500 pA 200 1000 line reg Line regulation 2 8 V lt Vppa 3 6 V ppm V 4 mA 100 500 Load 500 lt lt 4 mA Normal mod 50 500 mA load regulation S 4 M mode ppm m Tcoett 40 C lt TJ lt 125 C vrefint Temperature 50 5 coefficient 1 ppm C coeff _ 0 lt TJ lt 50 C vrefint 50 40 60 Fower supply dB rejection 100 kHz 25 40 CL 0 5 uF 300 350 Start up time CL 1 1 uF 500 650 us CL 1 5 uF 650 800 Control of maximum DC current drive lINRUSH on VREFBUF _ E 8 E mA OUT during start up phase 4 168 231 00 10025977 Rev 4 Ky STM32L486xx Electrical characteristics Table 71 VREFBUF characteristics continued Symbol IppA VREF BUF Parameter VREFBUF consumption from VDDA Conditions Min Typ Max lioag 16 25 ljoa
13. 98 6 3 2 Operating conditions at power up power down 99 6 3 3 Embedded reset and power control block characteristics 99 6 3 4 Embedded voltage 102 6 3 5 Supply current characteristics 104 6 3 6 Wakeup time from low power modes and voltage scaling transition 125 6 3 7 External clock source characteristics 127 6 3 8 Internal clock source characteristics 132 6 3 9 PLL characteristics 137 6 3 10 Flash memory characteristics 139 6 3 11 characteristics 140 6 3 12 Electrical sensitivity characteristics 141 6 3 13 l O current injection characteristics 142 6 3 14 port characteristics 143 6 3 15 NRST pin characteristics 149 6 3 16 Analog switches booster 150 6 3 17 Analog to Digital converter characteristics 151 6 3 18 Digital to Analog converter characteristics 164 6 3 19 Voltage reference buffer characteristics 168 6 3 20 Comparator characteristics
14. 138 Flash memory 139 Flash memory endurance and data 139 EMS characteristics 140 EMI 141 ESD absolute maximum 08 141 Electrical sensitivities 142 current injection susceptibility 0 0 llle BI 142 I O static characteristics 143 Output voltage characteristics 146 VO AC characteristics sec sl m Raph Rr tenga 4 2204 147 NRST pin characteristics 149 Analog switches booster 150 ADC characteristics 151 Maximum ADC RAIN u u tread bae rem der RR ede ue eae lames 153 ADC accuracy limited test conditions 1 155 ADC accuracy limited test conditions 2 157 ADC accuracy limited test conditions 3 159 ADC accuracy limited test conditions 4 16
15. p na s 05 la s Dimensions expressed millimeters Device marking ai14909c The following figure gives an example of topside marking orientation versus pin 1 identifier location q DocID025977 Rev 4 223 231 Package information STM32L486xx 224 231 Figure 62 LQFP64 marking package top view Revision code Product identification 1 STM32L48b Date code Pin 1 identifier MSv36855V3 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity q DocID025977 Rev 4 STM32L486xx Package information T 6 7 6 1 7 6 2 q Thermal characteristics The maximum chip junction temperature T jmax must never exceed the values given in Table 22 General operating conditions The maximum chip junction temperature max in degrees Celsius may be calculated using the following equation Ty TA max Pp max x Where TA max is the maximum ambient temperature in is the package junction to ambient thermal
16. uonduosep uid pue sjnouid XX987 1C IN LS y ed 2 6 20 LEZ S8 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UART4 SDMMC1 COMP1 TIM2 TIM15 UART5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PEO LCD SEG36 FMC NBLO TIM16 CH1 EVENTOUT PE1 LCD SEG37 FMC NBL1 TIM17 CH1 EVENTOUT PE2 TSC G7 101 LCD SEG38 FMC A23 Hn dE EVENTOUT PE3 TSC G7 IO2 LCD SEG39 FMC A19 SAM SD B EVENTOUT PE4 TSC_G7_103 FMC_A20 SAI1_FS_A EVENTOUT PE5 TSC_G7_104 FMC_A21 SAI1_SCK_A EVENTOUT PE6 FMC_A22 SAI1_SD_A EVENTOUT PE7 FMC_D4 SAI SD B EVENTOUT Port E PE8 FMC_D5 SAI1_SCK_B EVENTOUT PE9 FMC D6 SAI1 FS B EVENTOUT PE10 TSC G5 101 QUADSPI CLK FMC D7 dur be EVENTOUT PE11 TSC G5 IO2 QUADSPI NCS FMC D8 EVENTOUT PE12 TSC G5 IO3 QUADSPI BK1 100 FMC D9 EVENTOUT PE13 TSC G5 04 QUADSPI BK1 101 FMC D10 EVENTOUT PE14 QUADSPI BK1 102 FMC D11 EVENTOUT PE15 QUADSPI BK1 IO3 FMC D12 EVENTOUT XX987 1ZEINLS uonduosep uid pue sjnouid 1550 98 y ed 2 6 20 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued
17. 21 3 9 5 PRESCEIMNOGE ranas t ecce tants AP giae as AN i aie ease 29 3 9 6 VBAT operation 29 3 10 Interconnect 30 3 11 Clocks and startup 32 3 12 General purpose inputs outputs 35 3 13 Direct memory access controller 35 3 14 Interrupts and events 36 3 14 1 Nested vectored interrupt controller 36 3 14 2 Extended interrupt event controller EXTI 36 3 15 Analog to digital converter 37 3 15 1 Temperature 37 3 15 2 Internal voltage reference VREFINT 38 3 15 3 VBAT battery voltage monitoring 38 3 16 Digital to analog converter 38 2 231 DoclD025977 Rev 4 Ly STM32L486xx Contents 3 17 Voltage reference buffer 39 3 88 Comparators COMP 39 3 19 Operational amplifier OPAMP 40 3 20 Touch sensing controller TSC 40 3 21 Liquid crystal display controller LCD
18. 41 3 22 Digital filter for Sigma Delta Modulators DFSDM 41 3 23 Random number generator 43 3 24 Advanced encryption standard hardware accelerator AES 43 3 25 Timers and watchdogs 43 3 25 1 Advanced control timer TIM1 TIM8 44 3 25 2 General purpose timers TIM2 TIM3 TIM4 TIM5 15 TIM16 OM 45 3 25 3 Basic timers TIM6 and 7 45 3 25 4 Low power timer LPTIM1 and LPTIM2 45 3 25 5 Independent watchdog 46 3 25 6 System window watchdog WWDG 46 3 25 7 Syslicktimer 4 2 4 2 46 3 26 Real time clock RTC backup registers 47 3 27 Inter integrated circuit interface 2 48 3 28 Universal synchronous asynchronous receiver transmitter USART 49 3 29 Low power universal asynchronous receiver transmitter LPUART 50 3 30 Serial peripheral interface 51 3 31 Serial audio interfaces 51 3 32 Single wire protocol master interface SWPMI 52 3 33 Controller area network 52 3 34 Secure digital input output and Mu
19. 987 1ZEINLS y ed 2 6 20 2 62 Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS AF TIM5 TIM8 TIM3 TIM4 TIM8 I2C1 12C2 12C3 SPH SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PFO I2C2 SDA PF1 I2C2 SCL PF2 I2C2 SMBA PF3 PF4 PF5 PF6 TIM5 ETR TIM5 CH1 PF7 TIM5_CH2 Port PF8 TIM5 CH3 E PF9 TIM5 CH4 PF10 PF11 PF12 PF13 DFSDM DATING PF14 DFSDM_CKIN6 PF15 XX987 1ZEINLS uonduosep uid pue sjnouid L c 08 y ed 2 6 20 Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS_AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PGO PG1 PG2 SPI1_SCK PG3 SPI1_MISO PG4 SPI1_MOSI PG5 SPI1_NSS PG6 I2C3 SMBA PG7 I2C3 SCL PG8 I2C3 SDA Po
20. 170 6 3 21 Operational amplifiers characteristics 171 6 3 22 Temperature sensor characteristics 174 6 3 23 Vgar monitoring characteristics 174 4 231 DoclD025977 Rev 4 Ly STM32L486xx Contents 6 3 24 controller characteristics 175 6 3 25 DFSDM characteristics 177 6 3 26 Timer characteristics 178 6 3 27 Communication interfaces characteristics 180 6 3 28 192 7 Package information 209 7 1 LQFP144 package information 209 7 2 UFBGA132 package information 213 7 3 LQFP100 package 216 7 4 WLCSP72 package information 219 7 5 LOFP64 package information 222 7 6 Thermal characteristics 225 7 6 1 Reference document 225 7 6 2 Selecting the product temperature range 225 8 Part uh Pres 228 9 Revision history 229 DoclD025977 Rev 4 5 231 List of tables STM32L486
21. Symbol Parameter Conditions Min Typ Max Unit fisg ext User external clock source frequency 32 768 1000 kHz ViseH OSC32 IN input pin high level voltage 0 7 Vppiox Vppiox y ViseL OSC32_IN input pin low level voltage Vss 0 3 Vppiox OSC32 high or low time 250 5 tw LSEL 1 Guaranteed by design 128 231 Figure 16 Low speed external clock source AC timing diagram VLSEH VLSEL MS19215V2 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics q High speed external clock generated from a crystal ceramic resonator The high speed external HSE clock can be supplied with a 4 to 48 MHz crystal ceramic resonator oscillator All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 45 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 45 HSE oscillator characteristics Symbol Parameter Conditions 2 Min Typ Max Unit fosc_in_ Oscillator frequency 4 8 48 MHz Rr Feedback resistor 200 kQ During startup 5 5 Vpp 3 V Rm 300 0 44 CL 10 pF 8 MHz
22. of bits Signal to noise and SINAD distortion ratio SNR Signal to noise ratio q ADC clock frequency lt 26 MHz 1 65 V lt VppA VREF lt 3 6 V Voltage scaling Range 2 Conditions Min Typ Max Unit Single Fast channel max speed 5 5 4 ended Slow channel max speed 4 5 Fast channel max speed 4 5 Differential Slow channel max speed 3 5 4 5 Single Fast channel max speed 2 4 ended Slow channel max speed 2 4 Fast channel max speed 2 3 5 Differential Slow channel max speed 2 3 5 Single Fast channel max speed 4 4 5 ended Slow channel max speed 4 45 Fast channel max speed 3 4 Differential Slow channel max speed 3 Single Fast channel max speed 1 1 5 ended Slow channel max speed 1 1 5 Fast channel max speed 1 1 2 Differential Slow channel max speed 1 1 2 Single Fast channel max speed 2 5 3 ended Slow channel 2 5 3 Fast channel max speed 2 2 5 Differential Slow channel max speed 2 2 5 Single Fast channel max speed 10 2 10 5 ended Slow channel max speed 10 2 10 5 its Fast channel max speed 10 6 10 7 Differential Slow channel max speed 10 6 10 7 Single Fast channel max speed 63
23. 185 Quad SPI timing diagram DDR 185 SAI master timing 187 SAI slave timing waveforms 2 2 2 2 1 188 SDIO high speed mode 189 SD default 190 Asynchronous non multiplexed SRAM PSRAM NOR read waveforms 193 Asynchronous non multiplexed SRAM PSRAM NOR write waveforms 195 Asynchronous multiplexed PSRAM NOR read waveforms 196 Asynchronous multiplexed PSRAM NOR write waveforms 198 Synchronous multiplexed NOR PSRAM read timings 200 Synchronous multiplexed PSRAM write timings 202 Synchronous non multiplexed NOR PSRAM read timings 204 Synchronous non multiplexed PSRAM write timings 205 controller waveforms for read access 207 controller waveforms for write 5 207 controller waveforms for common memory read 207 controller waveforms for common memory write 208 LQFP144 144 pin 20 x 20 mm low profile quad flat package outli
24. 5 D2 5 PE6 22 SAI1 SD ae EVENTOUT 1 9 6 6 VBAT S RTC TAMP1 RTC TS 2 8 7 7 PC13 VO FT 2 EVENTOUT RTC_OUT WKUP2 PC14 1 3 C9 8 D1 8 OSC32 IN VO FT 2 EVENTOUT OSC32 IN PC14 PC15 1 4 88 9 E1 9 OSC32_OUT VO FT 2 EVENTOUT 2 OUT PC15 I2C2 SDA 0 D6 10 PFO VO FT_f EVENTOUT I2C2 SCL 1 D5 11 PF1 VO FT_f EVENTOUT I2C2 SMBA A2 D4 12 PF2 EVENTOUT E4 13 VO FT a FMC A3 EVENTOUT ADC3 IN6 F3 14 PF4 VO FT_a FMC_A4 EVENTOUT ADC3_IN7 F4 15 PF5 VO FT a FMC A5 EVENTOUT ADC3 IN8 Ly DoclD025977 Rev 4 61 231 Pinouts and pin description STM32L486xx Table 15 STM32L486xx pin definitions continued Pin Number Pin functions Nlo l2 5 5 5 5 a qe 8 Alternate functions Badio na took reset gt v 9 functions 9 959 amp 2 10 F2 16 VSS S 11 G2 17 VDD S TIM5_ETR TIM5_CH1 18 PF6 VO FT a SAM SD B EVENTOUT ADC3_IN9 TIM5_CH2 19 PF7 VO FT a SAI1 MCLK B ADC3 10 EVENTOUT TIM5 CH3 SAI1 SCK B 20 PF8 VO FT a EVENTOUT ADC3 IN11 TIM5 CH4 SAM FS B 21 PF9 VO FT a TIM15 CH1 EVENTOUT ADC3 IN12 22 PF10 VO
25. H MS19671V3 Power supply supervisor The device has an integrated ultra low power brown out reset BOR active in all modes except Shutdown and ensuring proper operation after power on and during power down The device remains in reset mode when the monitored supply voltage Vpp is below a specified threshold without the need for an external reset circuit The lowest BOR level is 1 71V at power on and other higher thresholds can be selected through option bytes The device features an embedded programmable voltage detector PVD that monitors the Vpp power supply and compares it to the VPVD threshold An interrupt can be generated when Vpp drops below the VPVD threshold and or when Vpp is higher than the VPVD threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software In addition the devices embeds a Peripheral Voltage Monitor which compares the independent supply voltages Vppa Vppuss Vppio2 With a fixed threshold in order to ensure that the peripheral is in its functional supply range q DocID025977 Rev 4 STM32L486xx Functional overview 3 9 3 3 9 4 q Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries the main regulator MR and the low power regulator LPR is used in the Run and Sleep modes and in the Stop 0 mode e The
26. co co co co 16 7 14 3 co co co co co co co co co co ca co 100 126 aan ___ _ 000000000 12 12 3 16 7 14906 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location DoclD025977 Rev 4 217 231 Package information STM32L486xx 218 231 Figure 56 LQFP100 marking package top view Product identification STMSBe2LHGE Optional gate mark Revision code indentifier MSv36846V2 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity q DocID025977 Rev 4 STM32L486xx Package information 7 4 WLCSP72 package information Figure 57 WLCSP72 72 ball 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package outline Z bbb z aaa A1 ball location Top view Wafer back side Bottom view A Bump side Bump
27. 29 5 34 2 LSl oscillator start _ _ tsu LSI up time 80 130 us LSI oscillator 2 9 tstap LSl stabilissifion dime 5 of final frequency 125 180 us Ipp LSI O LSI oscillator power _ _ 110 180 nA consomption 1 Guaranteed by characterization results 2 Guaranteed by design 6 3 9 q PLL characteristics DocID025977 Rev 4 The parameters given in Table 50 are derived from tests performed under temperature and Vpp supply voltage conditions summarized in Table 22 General operating conditions 137 231 Electrical characteristics STM32L486xx Table 50 PLL PLLSAI1 PLLSAI2 characteristics Symbol Parameter Conditions Min Typ Max Unit PLL input clock 4 16 MHz IN PLL input clock duty cycle 45 55 Voltage scaling Range 1 2 0645 80 P our PLL multiplier output clock P MHz gt Voltage scaling Range 2 2 0645 26 Voltage scaling Range 1 8 80 fPLL our PLL multiplier output clock Q MHz nun Voltage scaling Range 2 8 26 Voltage scaling Range 1 8 80 our PLL multiplier output clock R MHz Voltage scaling Range 2 8 26 Voltage scaling Range 1 64 344 f PLL VCO output MHz ae Voltage scaling Range 2 64 128 tlock PLL lock time 15 40 Hs RMS cycle to cycle jitter 40 Jitter System clock 80 MHz tps RMS period jitter 30 VCO freq 64 MHz 150 200 lop PLL PLL p
28. I Recovereddata 0 X 0 1 4 Xx N 2 IS a af ee ts Wasa Pree up C RS MSv39297V1 Timer characteristics The parameters given in the following tables are guaranteed by design Refer to Section 6 3 14 I O port characteristics for details on the input output alternate function characteristics output compare input capture external clock PWM output DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 79 TIMx characteristics Symbol Parameter Conditions Min Max Unit 1 trIMxCLK tres Tim Timer resolution time friMxCLK 80 MHz 12 5 ns 4 Timer external clock 0 friMxcLk 2 MHz EXT frequency on CH1 to CH4 frIMxCLK 80 MHz 0 40 MHz TIMx except TIM2 16 Resp Timer resolution 5 bit TIM2 and TIM5 32 16 bit counter clock 1 65536 trIMxCLK COUNTER i period frIMxCLK 80 MHz 0 0125 819 2 us t Maximum possible count d 65536 65536 triuxci K COUNT wi with 32 bit counter frimxcLk 80 MHz 53 68 8 1 is used a general term which x stands for 1 2 3 4 5 6 7 8 15 16 17 Table 80 IWDG min max timeout period at 32 kHz 151 1 Min timeout RL 11 0 Max timeout RL 11 0 Prescaler divider PR 2 0 bits 0x000 OxFFF Unit 14 0 0 125 512 18 1 0 250 1024 116 2 0 500 2048 132 3 1 0 4096 ms 164 4 2 0 8192 1128 5 4 0
29. as AF Te Haud I2C3 SMBUS D SCL SDA SMBA as AF channel 1 compl channel BKIN as AF dumb TIM16 16b K gt i gt TX RX as AF 1 channel 8 1 compl channel BKIN as AF C TIM17 16b a RX TX CKCTS lt inl USART1 Ki gt lt lt gt OUT INN INP RTSasAF MOSI MISO OUT INN INE SCK NSS as AF lt lt i MCLK A 50 A FS A SCK EXTCLK 8 MCLK B SD B FS B SCK Bas AF m SAN lt alg LCD Booster Vico 2 5V to 3 6V gt MCLK A SD A FS A SCK A EXTCLK lt 8D B FS Bas AF SAR lt SDCKIN 7 0 SDDATIN 7 0 LCD 8x40 SEGx COMx as AF SDCKOUT SDTRIG as AF DFSDM lt VDDA S LPUART1 RX TX CTS RTS AF INP INN OUT qq COMP1 SWPMI K swe INP INN OUT e COME gt c INT IN2 OUT ETR as AF Firewall lt LPTIM2 IN1 OUT ETR as AF DACi OUT DAC2 OUT MSv31749V3 Ly DoclD025977 Rev 4 15 231 Functional overview STM32L486xx 3 3 1 3 2 3 3 16 231 Functional overview ARM Cortex M4 core with FPU The ARM Cortex M4 with FPU processor is the latest generation of ARM processors for embedded systems It was developed to provide a low cost platform that meets the needs of MCU implementation with a reduced pin count and low power consumption while delivering outstanding computational performance and an advanced response to interrupts T
30. in Shutdown bypassed at 32768 Hz 3v 422 655 1925 4820 12569 B mode Ipp Shutdown backup 3 6V 584 888 2511 6158 15706 I I T with RTC registers 1 8V 329 499 1408 3460 retained RTC clocked by LSE 24v 431 634 1688 4064 2 enabled quartz in low drive mode 3V 554 791 2025 4795 I I I I 3 6V 729 1040 2619 6129 I Ipp wakeup Wakeup clock is Tum from Suc NIS MINES 0 6 7 I I I 7 7 7 7 Shutdown See 9 mode 1 Guaranteed by characterization results unless otherwise specified 2 Basedon characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors 3 Wakeup with code execution from Flash Average value given for a typical wakeup time as specified in Table 41 Low power mode wakeup timings 98 1651 sonsioj2eJeuo e21329 3 L 0 L y ed 2 6 20 Table 39 Current consumption in VBAT mode Symbol Ipp VBAT Parameter Backup domain supply current Conditions TYP 1 25 C 55 C 85 C 105 125 25 C 55 C 85 C 105 125 C 1 8 V 4 29 196 587 1663 10 8 73 490 1468 4158 24V 527 36 226 673 1884 132 90 565 1683 4710 RTC disabled 3V 6
31. FMC_NOE 1 1 1 td CLKL ADIV th CLKH ADV tsu ADV CLKH ta CLKL ADV FMC AD 15 0 1 T tsu NWA TV CLKH CLKH NWAITV FMC_NWAIT i WAITCFG 1b i WAITPOL 0b FMC_NWAIT WAITCFG 0b 1 1 WAITPOL 0b tsu NWAITV CLKH CLKH NWAITV MS32757V1 200 231 DoclD025977 Rev 4 STM32L486xx Electrical characteristics q Table 98 Synchronous multiplexed NOR PSRAM read timings 1 2 Symbol Parameter Min Max Unit tw CLk FMC_CLK period 2 1 taCLKL NExL FMC_CLK low to FMC_NEx low 0 2 2 ta CLKH_NExH FMC_CLK high to FMC_NEx high 0 2 0 5 ta CLKL NADVL FMC_CLK low to NADV low 2 5 taCLKL NADVH FMC_CLK low to FMC_NADV high 1 FMC_CLK low to valid x 16 25 3 5 tacLKH alv FMC_CLK high to Ax invalid x 16 25 THCLK ta CLKL NOEL FMC_CLK low to FMC_NOE low 1 5 ns ta CLKH NOEH FMC_CLK high to FMC_NOE high Tucikt1 tacLKL apv FMC_CLK low to FMC_AD 15 0 valid 4 FMC_CLK low to FMC_AD 15 0 invalid 0 tsu ADV CLKH FMC_A D 15 0 valid data before FMC_CLK high 0 FMC_A D 15 0 valid data after FMC_CLK high 2 5 tsu NWAIT CLKH FMC_NWAIT valid before FMC_CLK high 0 th CLKH NWAIT FMC_NWAIT valid after high 4 1 CL 30 pF 2 Guaranteed by c
32. Master mode 0 Guaranteed by characterization results 2 Maximum frequency in Slave transmitter mode is determined by the sum of tv so and t a which has to fit into SCK low or high phase preceding the sampling edge This value can be achieved when the SPI communicates with a master having 0 while Duty SCK 50 3 SPI mapped on Port G Figure 27 SPI timing diagram slave mode and CPHA 0 NSS input sia 1 tSU NSS ee th NSS 2 4 p 1 I CPHA 0 CPOL 0 I 0 i 4450 betes phe Drew tdis SO 4 1 OUT SCK Input ta SO 4 5 d 1 1 1 er 1 1 6 OUT LSB OUT OUTPUT X em h 1 I I tsu Sl r MOSI BUS MSBIN BIT1 IN o isn X IN le ths 14134 q 182 231 DocID025977 Rev 4 STM32L486xx Electrical characteristics Figure 28 SPI timing diagram slave mode and CPHA 1 NSS input 1 tSU NSS 4 re to sck M th NSS 1 1 5 1 i 1 E 1 2 CPOL 0 i T i n B gt 1 twsck I 9 CPOL 1 i 1 1 h T 4 SCK tdis SO j 4 3 ta so 9 14 MISO OUTPUT OUT BITS OUT OUT 50 51 th si MOSI ai14135b 1 Measurement points are
33. DFSDM CKIN1 USART2 PD8 USART3 TX PD9 USART3 RX PD10 I USART3 CK PD11 USART3 CTS PD12 I TIM4 CH1 USART3_RTS_ DE PD13 TIM4 CH2 PD14 TIM4 CH3 PD15 I TIM4 CH4 I 987 1ZEINLS uonduosep uid pue s ynould 150 84 y ed 2 6 20 Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS AF TIM5ITIM8 TIM3 TIM4 TIM8 I2C1 I2C2 2C3 2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PEO 1 1 TIM4 ETR 2 2 PE1 2 TRACECK TIM3_ETR PE3 TRACEDO TIM3 CH1 PE4 TRACED TIM3_CH2 2 DFSDM DATIN3 TRACED2 TIM3_CH3 DFSDM CKIN3 PE6 TRACED3 TIM3 CH4 gt PE7 TIM1_ETR DFSDM DATIN2 PortE PE8 TIM1_CH1N DFSDM_CKIN2 9 2 TIM1 CH1 s DFSDM CKOUT PE10 TIM1 CH2N DFSDM_DATIN4 11 TIM1 CH2 DFSDM 4 12 TIM1 CH3N SPM NSS DFSDM DATIN5 PE13 TIM1 CH3 SPM SCK DFSDM CKIN5 PE14 TIM1_CH4 TIM1 BKIN2 MM E SPI MISO E PE15 TIM1 BKIN E SPI MOSI E uonduosep uid pue
34. Electrical characteristics STM32L486xx Table 40 Peripheral current consumption continued Peripheral Range 1 Range 2 gere Unit 2 independent clock 44 3 6 38 USART2 APB clock domain 1 4 1 1 1 5 FADE independent clock 47 41 42 USART3 clock domain 1 5 1 3 1 7 RB 2 independent clock 39 32 35 UARTA clock domain 1 5 1 3 1 6 2 independent clock 39 32 35 UART5 APB clock domain 1 3 1 2 1 4 WWDG 0 5 0 5 0 5 All APB1 on 84 2 70 7 80 2 AHB to APB2 bridge 1 0 0 9 0 9 DFSDM 5 6 46 5 3 FW 0 7 0 5 0 7 independent clock domain 2 6 2 1 2 3 SAI1 APB clock domain 2 1 1 8 2 0 2 SAI2 independent clock domain 3 3 2 7 3 0 SAI2 APB clock domain 24 2 1 2 2 independent clock 47 39 42 SDMMCt1 clock domain 2 5 1 9 2 1 APB2 SPI1 2 0 1 6 1 9 SYSCFG VREFBUF COMP 0 6 0 4 0 5 TIM1 8 3 6 9 7 9 TIM8 8 6 7 1 8 1 TIM15 4 1 3 4 3 9 TIM16 3 0 2 5 2 9 TIM17 3 0 24 2 9 2 independent clock 49 40 44 USART1 APB clock domain 1 5 1 3 1 7 All APB2 on 56 8 43 3 48 2 ALL 256 8 189 6 215 5 124 231 DoclD025977 Rev 4 Ky STM32L486xx Electrical characteristics The BusMatrix is automatically active when at least one master is ON CPU DMA 2 The GPIOx x A H dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GP
35. Vpp lt 3 6 12 5 Voltage Range 1 Master receiver Voltage Range 1 I aa fox SAI clock frequency Slave transmitter MHz 2 7 lt Vpp lt 3 6 22 5 Voltage Range 1 Slave transmitter 1 71 lt Vpp lt 3 6 14 5 Voltage Range 1 Slave receiver Voltage Range 1 25 Voltage Range 2 12 5 Master mode _ 22 2 7 Vpp lt 3 6 twes FS valid time ns Master mode _ 40 1 71 lt Vpp lt 3 6 th FS FS hold time Master mode 10 ns tsu FS FS setup time Slave mode 1 ns th FS FS hold time Slave mode 2 ns tsu SD_A_MR Master receiver 2 5 eee Data input setup time lsu SD B SR Slave receiver 3 th SD MR Master receiver 8 Data input hold time ns th SD_B_SR Slave receiver 4 q DocID025977 Rev 4 STM32L486xx Electrical characteristics Table 86 SAI characteristics continued Symbol Parameter Conditions Min Max Unit Slave transmitter after enable edge I 22 2 7 lt Vpp lt 3 6 B sr Data output valid time ns nm Slave transmitter after enable edge _ 34 1 71 lt Vpp 3 6 tsp sr Data output hold time Slave transmitter after enable edge 10 ns Master transmitter after enable edge I 27 2 7 lt Vpp lt 3 6 twsp MT Data output valid time ns Master transmitter
36. fff C iii A1 A A1 ball index area TOP VIEW UFBGA132 008 ME V1 1 Drawing is not to scale Table 105 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 600 0 0236 A1 0 110 0 0043 A2 0 450 0 0177 A3 0 130 0 0051 0 0094 A4 0 320 0 0126 0 240 0 290 0 340 0 0094 0 0114 0 0134 D 6 850 7 000 7 150 0 2697 0 2756 0 2815 D1 5 500 0 2165 E 6 850 7 000 7 150 0 2697 0 2756 0 2815 E1 5 500 0 2165 DoclD025977 Rev 4 213 231 Package information STM32L486xx Table 105 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max e 0 500 0 0197 Z 0 750 0 0295 ddd 0 080 0 0031 eee 0 150 0 0059 fff 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 52 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint 000000000000 00000 00000 Dpad 000000000 000000000000 UFBGA132 A0G8 FP V1 Table 106 UFBGA132 recommended P
37. lt 2 7 V 100 tp 200 mV step m VppA 2 2 7 V 0 55 09 i i edium mode with 100 mV overdrive lt 2 7 V I 0 65 1 ds Ultra low power mode 5 12 Full common Voffset Comparator offset error mode range 5 20 mV No hysteresis 0 Low hysteresis 8 Vhys Comparator hysteresis mV Medium hysteresis 15 High hysteresis 27 Static 400 600 Ultra low With 50 kHz nA power mode 100 mV overdrive 120 square signal Static 5 7 IppA COMP Comparator consumption Medium mode With 50 kHz from VppA 100 mV overdrive 6 square signal Static 70 100 High speed With 50 kHz mode 100 mV overdrive 75 square signal 170 231 00 10025977 Rev 4 Ly STM32L486xx Electrical characteristics 1 Guaranteed by design unless otherwise specified 2 Refer to Table 25 Embedded internal voltage reference 3 Guaranteed by characterization results 6 3 21 Operational amplifiers characteristics Table 73 OPAMP characteristics Symbol Parameter Conditions Min Typ Max Unit Analog supply VpDA voltage 1 8 3 6 V Common mode I I V Input offset 25 C No Load on output 1 5 VlorrsET voltage mV g All voltage Temp 3 Input offset Normal mode 5 4 AVlorrsET drift vortage Low power mode 10 Offset trim step TRIMOFFSE
38. 1565 current PLL ON above u 100 Run mode 48 MHz Reduced code 10 0 125 all peripherals Coremark 9 4 117 disable 9 Dhrystone 2 1 94 mA 114 2 A Fibonacci 9 0 112 5 While 1 9 3 116 Reduced code 358 179 Coremark 392 196 current HCLK MSI z Ipp LPRun Low power all peripherals disable Dhrystone 2 1 390 HA 195 WA MHZz run Fibonacci 385 192 While 1 385 192 1 Reduced code used for characterization results provided in Table 26 Table 27 Table 28 Table 31 Typical current consumption in Run and Low power run modes with different codes running from SRAM1 Conditions TYP TYP Symbol Parameter Voltage Unit Unit g Code 25 C 25 C scaling N Reduced code 2 9 111 2 Coremark 2 9 111 fuck fuse upto 2 Dhrystone 2 1 29 mA 111 pA MHz 48 MHz included X Fibonacci 2 6 100 Supply bypass mode 155 currentin PLL ON above While 28 100 Run mode 48 MHz all I Reduced code 10 2 127 peripherals Coremark 10 4 130 disable Dhrystone 2 1 10 3 mA 129 pA MHz e x Fibonacci 9 6 120 5 While 1 9 3 116 Reduced code 242 121 Coremark 242 121 current in HCLK MSI 2 Ipp LPRun Low power all peripherals disable Dhrystone 2 1 242 HA 121 run Fibonacci 225 112 While 1 242 12
39. 3 V Rm 45 Q 0 45 CL 10 pF 8 MHz HSE current consumption Vpp 3 V mA Rm 300 068 CL 5 pF 48 MHz 3 V Rm 300 0 94 CL 10 pF 48 MHz 3 V Rm 300 1 77 CL 20 pF 48 MHz Maximum critical crystal G m transconductance Startup 1 5 Startup time Vpp is stabilized 2 ms Guaranteed by design Resonator characteristics given by the crystal ceramic resonator manufacturer This consumption level occurs during the first 2 3 of the tsu usg startup time Bow NM tsu HseE is the startup time measured from the moment it is enabled by software to a stabilized 8 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For C 4 and 2 it is recommended to use high quality external ceramic capacitors in the 5 pF to 20 pF range typ designed for high frequency applications and selected to match the requirements of the crystal or resonator see Figure 17 C C 2 are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C and Cj gt PCB and MCU pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing Cu and Cio DoclD025977 Rev 4 129 231 Electrical characteristics STM32L486xx Note
40. 6 3 3 q Operating conditions at power up power down The parameters given in Table 23 are derived from tests performed under the ambient temperature condition summarized in Table 22 Table 23 Operating conditions at power up power down Symbol Parameter Conditions Min Max Vpp rise time rate 0 tvpp a Vpp fall time rate 10 Vppa rise time rate 0 WDDA time rate 10 Vppusa rise time rate 0 Ter cc talks reo 10 Vpplio2 rise time rate 0 eines 10 Unit us V Embedded reset and power control block characteristics The parameters given in Table 24 are derived from tests performed under the ambient temperature conditions summarized in Table 22 General operating conditions DoclD025977 Rev 4 99 231 Electrical characteristics STM32L486xx Table 24 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit 2 Reset temporization after 55 _ IRSTTEMPO BORO is detected Vpp rising 290 200 Hs Rising edge 1 62 1 66 1 7 VBoro 2 Brown out reset threshold 0 V Falling edge 1 6 1 64 1 69 Rising edge 2 06 2 1 2 14 VBOR1 Brown out reset threshold 1 V Falling edge 1 96 2 2 04 Rising edge 2 26 2 31 2 35 VBoR2 Brown out reset threshold 2 V Falling edge 2 16 2 20
41. Alternate functions Badio na reset gt v 9 functions 9 959 amp Z2 SPI2 MOSI DFSDM CKINO 185 B7 118 PD4 USART2 RTS DE FMC NOE EVENTOUT USART2 TX FMC NWE 86 A6 119 PD5 EVENTOUT 120 VSS S 121 VDD S DFSDM DATIN 1 USART2 RX 87 B6 122 PD6 FMC NWAIT SAI SD EVENTOUT DFSDM 1 88 A5 123 PD7 USART2 _ EVENTOUT SPI3 SCK USART1 TX NE2 A4 D9 124 PG9 s SAI2_SCK TIM15 CH1N EVENTOUT LPTIM1 IN1 SPI3 MISO USART1 RX B4 D8 125 PG10 s SAI2 FS TIM15 EVENTOUT LPTIM1 IN2 SPI3 MOSI USART1 CTS 4 G3 126 PG11 s SAI2 TIM15 CH2 EVENTOUT LPTIM1 ETR SPI3 NSS USART1 RTS DE C5 D7 127 PG12 s NE4 SAI2 SD A EVENTOUT I2C1 SDA USART1 CK 5 C7 128 PG13 VO FT_fs A24 EVENTOUT I2C1 SCL FMC A25 A5 C6 129 PG14 VO FT fs EVENTOUT F7 130 VSS S B6 G7 131 VDDIO2 S LPTIM1 OUT E IL Fols UO PTS quas 2 1 SMBA EVENTOUT i DoclD025977 Rev 4 71 231 Pinouts and pin description STM32L486xx Table 15 STM32L486xx pin definitions continued Pin Number LQFP64 32 WLCSP72 LQFP100 UFBGA1 LQFP144
42. FMC_CLK high to FMC_NEx high 0 2 0 5 ty CLKL NADVL FMC_CLK low to NADV low 2 ta CLKL NADVH FMC_CLK low to FMC_NADV high 0 5 ta CLKL AV FMC_CLK low to FMC_Ax valid x 16 25 3 5 tacLkH Alv high to FMC_Ax invalid x 16 25 ns taCLKL NOEL FMC_CLK low to NOE low 2 ta CLKH NOEH FMC_CLK high to FMC_NOE high 0 5 tsu DV cLKH FMC_D 15 0 valid data before high 0 FMC_D 15 0 valid data after FMC_CLK high 5 tsu NWAIT CLKH FMC_NWAIT valid before FMC_CLK high 0 th CLKH NwAIT NWAIT valid after FMC_CLK high 4 q 204 231 DocID025977 Rev 4 Electrical characteristics STM32L486xx 30 pF CL 2 Guaranteed by characterization results 1 Figure 43 Synchronous non multiplexed PSRAM write timings l ta cLKH NExH 1 1 1 1 1 1 1 1 1 1 1 1 1 A 1 ta CLKH t Data latency 0 e ta CLKL NExL FMC_CLK CLKII NADVH ta ta CLKL NADVL FMC_NEx FMC_NADV FMC_A 25 0 NWEL t ir d CLKL Data t D 15 0 FMC NWAIT WAITCFG MSv38002V1 d CLKH NBL H t WAITV th CLKH N INWAITV CLKH tsu Ob WAITPOL Ob FMC NBL 205 231 DoclD025977 Rev 4 Electrical charact
43. PC10 PC11 Pin type structure FT FT FT Notes Pin functions Alternate functions JTDI TIM2_CH1 2 SPI1_NSS SPI3 NSS UARTA RTS DE TSC_G3_101 LCD SEG17 SAI2 FS B EVENTOUT SPI3 SCK USARTS TX UARTA TX TSC G3 IC2 LCD COM4A LCD SEG28 LCD 5 40 SDMMC1 D2 SAI2 SCK B EVENTOUT SPI3 MISO USART3 RX UARTA4 RX TSC G3 103 LCD COMS LCD SEG29 LCD 5 41 SDMMC1_D3 SAI2 MCLK B EVENTOUT Additional functions 53 B3 80 B10 113 PC12 FT I SPI3 MOSI USART3_ CK UART5 TX TSC G3 104 LCD COM6 LCD SEG30 LCD SEG42 SDMMC1 CK SAI2 SD B EVENTOUT 81 82 C9 B9 114 115 PDO PD1 FT FT SPI2 NSS DFSDM DATINT CAN1_RX D2 EVENTOUT SPI2 SCK DFSDM CKIN7 CAN1 TX D3 EVENTOUT 54 A3 83 C8 116 PD2 FT I TIM3 ETR USART3 RTS DE UART5 TSC SYNC LCD COM7 LCD SEG31 LCD SEG43 SDMMC1 CMD EVENTOUT 84 B8 117 PD3 1 0 FT SPI2_MISO DFSDM_DATINO USART2_CTS FMC_CLK EVENTOUT 70 231 DoclD025977 Rev 4 q STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions continued Pin Number Pin functions Nlo l2 5 5 5 5 a qe 8
44. The current consumption is measured as described in Figure 13 Current consumption measurement scheme Typical and maximum current consumption The MCU is placed under the following conditions e AI I O pins in analog input mode e peripherals are disabled except when explicitly mentioned e The Flash memory access time is adjusted with the minimum wait states number depending on the 1 frequency refer to the table Number of wait states according to CPU clock HCLK frequency available in the RMO351 reference manual e When the peripherals are enabled fpci The parameters given in Table 26 to Table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22 General operating conditions q DocID025977 Rev 4 y ed 2 6 20 LEc SOL Table 26 Current consumption in Run and Low power run modes code with data processing running from Flash ART enable Cache ON Prefetch OFF Conditions TYP 1 Symbol Parameter Unit Voltage 25 C 55 85 C 105 125 C 25 55 C 85 C 105 125 scaling 26 MHz 2 88 293 3 05 323 3 58 320 3 37 3 51 3 93 4 76 16 MHz 1 83 1 87 1 98 216 249 2 01 2 16 2 30 2 72 3 34 8MHz 0 98 1 02 1 12 1 29 1 62 1 10 1 17 1 31 1 73
45. o PD15 TIM4_CH4 LCD SEG35 D1 EVENTOUT G10 87 PG2 SPI1_SCK A12 VO FUS SCK B EVENTOUT F9 88 PG3 SPI1 MISO FMC A13 VO FUS gaia FS B EVENTOUT F10 89 PG4 SPI1 MOSI 14 SAI2 MCLK B EVENTOUT VO E9 90 PG5 _ 5 LPUART4 CTS A15 2 SD B EVENTOUT VO G4 H4 91 92 PG6 PG7 I2C3 SMBA s LPUART1 RTS DE EVENTOUT I2C3 SCL LPUART1 TX VO INT3 EVENTOUT J6 93 PG8 I2C3 SDA LPUART1 RX eg ope is EVENTOUT 94 VSS 37 F3 38 F1 63 64 E12 E11 95 96 97 VDDIO2 PC6 PC7 TIM3 CH1 TIM8_CH1 DFSDM CKIN3 TSC G4 101 VO LCD_SEG24 SDMMC1_D6 SAI2 MCLK A EVENTOUT 2 8 2 DFSDM DATING TSC G4 102 VO LCD_SEG25 SDMMC1_D7 SAI2_MCLK_B EVENTOUT 39 F2 65 E10 98 PC8 TIM3 CH3 TIM8_CH3 TSC G4 103 LCD SEG26 SDMMC1 D0 EVENTOUT VO 68 231 DoclD025977 Rev 4 q STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions continued Pin Number Pin functions N Pin name Nlo l2 5 7 8 nec qu 8 E Alternate functions Additional na r
46. 1 1 1 I ae OUT E E Kernel logic IO M GPIOs e logi CPU Digital IN ogic amp Memories gt 5 1 nx VSS gt EA I I m x VDDIO2 Vpbio2 1 OUT z IO 3 logic IN 9 ADCs DACs OPAMPs COMPs VREFBUF MS35001V3 Caution Each power supply pair Vpp Vss Vppa Vssa etc must be decoupled with filtering ceramic capacitors as shown above These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device q DocID025977 Rev 4 95 231 Electrical characteristics STM32L486xx 6 1 7 Current consumption measurement Figure 13 Current consumption measurement scheme IDD USB j VDDUSB IDD_VBAT O VBAT 1 w LI VDDIO2 IDDA VDDA MS35002V2 6 2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 19 Voltage characteristics Table 20 Current characteristics and Table 21 Thermal characteristics may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 19 Voltage characteristics Symbol Ratings Min Max Unit Externa
47. 10 ksps 16 50 ADC consumption from 9 Msp 35m 160 Ippv s ADC Vgge single ended 15 1 Msps 30 40 megs fs 10 ksps 2 0 6 2 ADC consumption from 1 S Mps 298 ae Ippv_p ADC the differential fs 1 Msps 60 70 mode fs 10 ksps 1 3 3 Guaranteed by design 2 The I O analog switch voltage booster is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG CFGR1 when VppA lt 2 4 It is disable when 2 2 4 V 3 Vper can be internally connected to and Vggr can be internally connected to VssA depending on the package rile to Section 4 Pinouts and pin description for further details 152 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Equation 1 max formula Rain Ts N 2 X Canc X In 2 Ranc The formula above Equation 1 is used to determine the maximum external impedance allowed for an error below 1 4 of LSB Here N 12 from 12 bit resolution Table 64 Maximum ADC RAIN 2 RAIN Sampling cycle Sampling time ns Resolution 80 MH 80 MH z Fast channels Slow channels 2 5 31 25 100 N A 6 5 81 25 330 100 12 5 156 25 680 470 24 5 306 25 1500 1200 12 bits 47 5 593 75 2200 1800 92 5 1156 25 4700 3900 247 5 3093 75 12000 10000 640 5 8006 75 39000 33000 2 5 31 25 120 N A 6 5 81 25 39
48. 65 ended Slow channel max speed 63 65 Fast channel max speed 65 66 Differential Slow channel max speed 65 66 dB Single Fast channel max speed 64 65 ended Slow channel max speed 64 65 Fast channel max speed 66 67 Differential Slow channel max speed 66 67 DoclD025977 Rev 4 161 231 Electrical characteristics STM32L486xx Table 68 ADC accuracy limited test conditions 41 23 continued paa Parameter Conditions Min Typ Max Unit ADC clock frequency lt Single Fast channel max speed 71 69 Total 26 MHz ended Slow channel max speed 71 69 THD harmonic 1 65 V lt VREF lt dB distortion 3 6 V Fast channel max speed 73 72 Differential Voltage scaling Range 2 Slow channel max speed 73 72 1 Guaranteed by design 2 ADC DC accuracy values are measured after internal calibration ADC accuracy vs negative Injection Current Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative current 4 The I O analog switch voltage booster is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG_CFGR1 when VppaA lt 2 4 V It is disable
49. 7 lt y life augmented STM32L486xx Ultra low power ARM Cortex M4 32 bit MCU FPU 100DMIPS up to 1MB Flash 128KB SRAM USB OTG FS LCD analog audio AES Features December 2015 Ultra low power with FlexPowerControl 1 71 V to 3 6 V power supply 40 C to 85 105 125 C temperature range 300 nA in Vgar mode supply for RTC and 32x32 bit backup registers 30 nA Shutdown mode 5 wakeup pins 120 nA Standby mode 5 wakeup pins 420 nA Standby mode with 1 1 pA Stop 2 mode 1 4 pA Stop 2 with RTC 100 pA MHz run mode Batch acquisition mode BAM 4 ys wakeup from Stop mode Brown out reset BOR in all modes except shutdown Interconnect matrix Core ARM 32 bit Cortex M4 CPU with FPU Adaptive real time accelerator ART Accelerator allowing O wait state execution from Flash memory frequency up to 80 MHz MPU 100DMIPS 1 25DMIPS MHz Dhrystone 2 1 and DSP instructions Clock Sources 4to 48 MHz crystal oscillator 32 kHz crystal oscillator for RTC LSE Internal 16 MHz factory trimmed RC 1 Internal low power 32 kHz RC 5 Internal multispeed 100 kHz to 48 MHz oscillator auto trimmed by LSE better than 0 25 accuracy 3 PLLs for system clock USB audio ADC RTC with HW calendar alarms and calibration LCD 8 x 40 or 4 x 44 with step up converter Up to 24 capacitive sensing channels support touchkey linear and rotar
50. 84 885 C Suffix 7 T jmax 49 C W x 447 mW 125 20 115 104 885 C Example 2 High temperature application Using the same rules it is possible to address applications that run at high ambient temperatures with a low dissipation as long as junction temperature remains within the specified range Assuming the following application conditions Maximum ambient temperature 100 C measured according to JESD51 2 Ippmax 20 mA Vpp 3 5 V maximum 20 I Os used at the same time in output at low level with Io 8 mA Vor 0 4 V Pintmax 20 mA x 3 5 V 70 mW Piomax 20 x 8 mA x 0 4 V 64 mW This gives 70 mW and Piomax 64 mW Ppmax 70 64 134 mW Thus Ppmax 134 mW q DocID025977 Rev 4 STM32L486xx Package information q Using the values obtained in Table 111 T Jmax is calculated as follows For LQFP64 45 C W 100 C 45 C W x 134 mW 100 C 6 03 C 106 03 C This is above the range of the suffix 6 version parts 40 lt T lt 105 In this case parts must be ordered at least with the temperature range suffix 7 see Section 8 Part numbering unless we reduce the power dissipation in order to be able to use suffix 6 parts Refer to Figure 63 to select the required temperature range suffix 6 or 7 according to your ambient temperature or power requirements Figure 63 LQFP64 Pp max vs TA 700 600
51. e One CAN e One USB OTG full speed e One SWPMI Single Wire Protocol Master Interface The STM32L486xx devices embed AES hardware accelerator The STM32L486xx operates in the 40 to 85 C 105 C junction 40 to 105 C 125 C junction and 40 to 125 C 130 C junction temperature ranges from a 1 71 to 3 6 V power supply A comprehensive set of power saving modes allows the design of low power applications Some independent power supplies are supported analog independent supply input for ADC DAC OPAMPs and comparators 3 3 V dedicated supply input for USB and up to 14 I Os can be supplied independently down to 1 08V A VBAT input allows to backup the RTC and backup registers The STM32L486xx family offers five packages from 64 pin to 144 pin packages q 12 231 DocID025977 Rev 4 STM32L486xx Description Table 2 STM32L486xx family device features and peripheral counts Peripheral STM32L486Zx STM32L486Qx STM32L486Vx STM32L486Jx STM32L486Rx Flash memory 1 MB SRAM 128 KB External memory controller for static Yes Yes Yes No No memories Quad SPI Yes Advanced 2 16 bit control General 5 16 bit purpose 2 32 bit Basic 2 16 bit Timers Low power 2 16 bit SysTick 4 timer Watchdog timers 2 independent Window SPI 3 2 3 USART 3 UART 2 LPUART 1 Comm SAI 2 interfaces CAN
52. the MSI RC the HSI16 RC and the HSE crystal oscillators are also switched off The RTC can remain active Standby mode with RTC Standby mode without RTC The brown out reset BOR always remains active in Standby mode The state of each I O during standby mode can be selected by software I O with internal pull up internal pull down or floating After entering Standby mode SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry Optionally SRAM2 can be retained in q DocID025977 Rev 4 25 231 Functional overview STM32L486xx 26 231 Standby mode supplied by the low power Regulator Standby with RAM2 retention mode The device exits Standby mode when an external reset NRST pin an IWDG reset WKUP pin event configurable rising or falling edge or an RTC event occurs alarm periodic wakeup timestamp tamper or a failure is detected on LSE CSS on LSE The system clock after wakeup is MSI up to 8 MHz Shutdown mode The Shutdown mode allows to achieve the lowest power consumption The internal regulator is switched off so that the VCORE domain is powered off The PLL the HS116 the MSI the LSI and the HSE oscillators are also switched off The RTC can remain active Shutdown mode with RTC Shutdown mode without RTC The BOR is not available in Shutdown mode No power voltage monitoring is possible in this mode therefore the switch to Backup domain is not supported SRAM
53. 105 C 15 1 at TA 125 C 7 RET Data retention qn k Years 10 kcycles 2 at TA 55 C 30 10 kcycles 2 at TA 85 C 15 10 2 at TA 105 C 10 1 Guaranteed by characterization results 2 Cycling performed over the whole temperature range q DocID025977 Rev 4 139 231 Electrical characteristics STM32L486xx 6 3 11 140 231 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization Functional EMS electromagnetic susceptibility While a simple application is executed on the device toggling 2 LEDs through I O ports the device is stressed by two electromagnetic events until a failure occurs The failure is indicated by the LEDs e Electrostatic discharge ESD positive and negative is applied to all device pins until a functional disturbance occurs This test is compliant with the IEC 61000 4 2 standard e FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test is compliant with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in Table 53 They are based on the EMS levels and classes defined in application note AN1709 Table 53 EMS characteristics Level Symbol Parameter Conditions Class Voltage limits to be
54. 2 5 CH2 USART2 RTS DE OPAMP1 VINM 1 GA pat MO I UARTA RX LCD SEGO ADC12 IN6 TIM15 CH1N EVENTOUT TIM2_CH3 TIM5 CH3 USART2 TX LCD SEG1 ADC12 INT 16 G6 25 KS 36 PAZ VO FE la i SAI2 EXTCLK WKUP4 LSCO TIM15_CH1 EVENTOUT TIM2_CH4 5 OPAMP1 17 H7 26 L3 37 PA3 TT USART2 RX LCD SEG2 VOUT TIM15 CH2 EVENTOUT ADC12 IN8 18 J9 27 E3 38 VSS 19 J8 28 39 VDD SPI1_NSS SPI3_NSS 20 5 29 J4 40 PA4 VO TT a USART2_CK SAI1_FS_B S 5 LPTIM2 OUT EVENTOUT TIM2_CH1 TIM2_ETR 21 6 30 K4 41 PA5 VO TT a TIM8 CH1N SPI1 2 LPTIM2 ETR EVENTOUT TIM1_BKIN TIM3 CH1 TIM8 BKIN SPI1 MISO USART3 CTS QUADSPI BK1 1O3 2 VINP 22 H5 31 L4 42 PA6 VO FT la LCD SEG3 ADC12 IN11 TIM1 BKIN COMP2 TIM8 BKIN COMP2 TIM16 CH1 EVENTOUT M4 OPAMP2 VINM TIM1 CH1N TIM3 CH2 TIM8 CH1N SPI1 MOSI 23 H4 32 J5 43 PA7 VO FT_la QUADSPI 102 2 LCD SEGA 17 1 m EVENTOUT TX 1 INM uS RS E POA VO Fia LCD_SEG22 EVENTOUT ADC12 IN13 DoclD025977 Rev 4 63 231 Pinouts and pin description STM32L486xx Table 15 STM32L486xx pin definitions continued Pin Number Pin functions lt Nlo l2 5 5 5 5 a qe 8
55. 396 671 2108 5202 12869 bypassed at 32768Hz 528 853 2531 6095 14915 I 36V 710 1111 3115 7470 18221 E n 18V 416 640 1862 4479 11908 RTC clocked by LSE 2 4V 514 796 2193 5236 13689 quartz 8 in low drive mode 3v 652 961 2589 6103 15598 3 6V 821 1226 3235 7551 17947 XX98PIZENLS sonsioj2eJeuo e21329 3 16 811 y ed 2 6 20 Table 37 Current consumption in Standby mode continued Conditions TYP MAX Symbol Parameter Unit Vpp 25 55 85 105 125 25 55 C 85 105 C 125 C Supply current 1 8V 235 641 2293 5192 11213 588 1603 5733 12980 28033 Ipp SRAM2 24V 237 645 2303 5213 11246 593 1613 5758 13033 28115 4 andby mode when SRAM2 3 V 236 647 2306 5221 11333 593 1618 5765 13053 28333 is retained 3 6V 235 646 2308 5200 11327 595 1620 5770 13075 28350 Ipp wakeup 2 Wakeup clock is from uring wakeup MSI 4 MHz 17 mA Standby from Standby See 5 y mode ee 1 Guaranteed by characterization results unless otherwise specified 2 Guaranteed by test in production 3 Based on characterization d
56. 467 18 65 248 558 1168 LCD 24V 7 14 263 99 6 225 470 18 66 249 563 1175 bled 2 enable 7 31 266 1000 226 474 18 67 250 565 1185 Stop 1 in stop 1 3 6V 7 41 269 1020 229 480 19 67 255 573 1200 x with RTC 18V 6 91 25 2 934 210 440 17 63 234 525 1100 I RTC enabled LCD 24V 704 253 942 241 443 18 63 236 528 1108 at 32768 Hz disabled 7 19 25 7 95 0 212 446 18 64 238 530 1115 36V 7 97 26 0 961 215 451 20 65 240 538 1128 18V 685 25 0 93 0 208 3 2 17 63 233 521 js cua el LCD 24V 6 94 251 932 2003 17 63 233 523 low drive mode disabled 7 10 252 93 6 210 3 18 63 234 526 3 6V 7 34 254 944 212 3 18 64 235 531 sonsiuoj2eJeuo e2129 3 XX987 1ZEINLS y ed 2 6 20 LEC SLL Table 35 Current consumption in Stop 1 mode continued Ipp wakeup Symbol Parameter Supply current during wakeup from Stop 1 from Stop1 Conditions TYP 1 Wakeup clock MSI 48 MHz voltage Range 1 See 4 25 C 1 47 55 C 85 C 105 C 125 C Wakeup clock MSI 4 MHz voltage Range 2 See 4 3V 1 7 Wakeup clock HSI16 16 MHz voltage Range 1 See 4 3V 1 62
57. Additional I O current consumption is due to I Os configured as inputs if an intermediate voltage level is externally applied This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value Unless this specific configuration is required by the application this supply current consumption can be avoided by configuring these I Os in analog mode This is notably the case of ADC input pins which should be configured as analog inputs Any floating input pin can also settle to an intermediate voltage level or switch inadvertently as a result of external electromagnetic noise To avoid current consumption related to floating pins they must either be configured in analog mode or forced internally to a definite digital value This can be done either by using pull up down resistors or by configuring the pins in output mode dynamic current consumption In addition to the internal peripheral current consumption measured previously see Table 40 Peripheral current consumption the I Os used by an application also contribute to the current consumption When an pin switches it uses the current from the I O supply voltage to supply the I O pin circuitry and to charge discharge the capacitive load internal or external connected to the pin Isw Vppiox X fsw x C where lsw is the current sunk by a switching I O to charge discharge the capacitive load Vppiox is the I O supply voltage fsw is the I
58. As applications do not commonly use the STM32L486xx at maximum dissipation it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application The following examples show how to calculate the temperature range needed for a given application Example 1 High performance application Assuming the following application conditions Maximum ambient temperature 82 C measured according to JESD51 2 Ippmax 20 mA Vpp 3 5 V maximum 20 I Os used at the same time in output at low level with Io 8 mA Vg 0 4 V and maximum 8 I Os used at the same time in output at low level with Io 20 mA Vo 1 3 V PiNTmax 50 mA x 3 5 V 175 mW Piomax 20 x 8 mA x 0 4 8x 20 mA x 1 3 272 mW This gives Pintmax 175 mW and Pi omax 272 mW Ppmax 175 272 447 mW Using the values obtained in Table 111 T is calculated as follows For LQFP84 45 C W 82 C 45 C W x 447 mW 82 C 20 115 C 102 115 C This is within the range of the suffix 6 version parts 40 lt T lt 105 C see Section 8 Part numbering In this case parts must be ordered at least with the temperature range suffix 6 see Part numbering With this given we can find the allowed for a given device temperature range order code suffix 6 or 7 Suffix 6 T jmax 49 C W x 447 mW 105 20 115
59. Comparators COMP The STM32L486xx devices embed two rail to rail comparators with programmable reference voltage internal or external hysteresis and speed low speed for low power and with selectable output polarity The reference voltage can be one of the following e External I O DAC output channels e Internal reference voltage or submultiple 1 4 1 2 3 4 All comparators can wake up from Stop mode generate interrupts and breaks for the timers and can be also combined into a window comparator DoclD025977 Rev 4 39 231 Functional overview STM32L486xx 3 19 3 20 Note 40 231 Operational amplifier OPAMP The STM32L486xx embeds two operational amplifiers with external or internal follower routing and PGA capability The operational amplifier features e Low input bias current e Low offset voltage e Low power mode e Rail to rail input Touch sensing controller TSC The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric glass plastic The capacitive variation introduced by the finger or any conductive object is measured using a proven implementation based on a surface charge transfer acquisition principle The touch sensing controller is fully supported by the STMTouch touch sensing fi
60. FT a 15 CH2 EVENTOUT ADC3 IN13 5 09 12 F1 23 EVENTOUT OSC IN PHO 6 8 13 G1 24 dii o EVENTOUT OSC OUT 7 E9 14 H2 25 NRST RST LPTIM1 IN1 12C3 SCL DFSDM_DATIN4 8 F9 15 H1 26 PCO VO FT fla LPUART1 RX ADC123 IN1 LCD SEG18 LPTIM2 IN1 EVENTOUT LPTIM1 OUT I2C3 SDA DFSDM_CKIN4 9 8 16 J2 27 PC1 VO FT_fla LPUART1 TX ADC123 IN2 LCD SEG19 EVENTOUT LPTIM1 IN2 SPI2 MISO 10 F7 17 J3 28 PC2 VO FT la DFSDM CKOUT ADC123 IN3 LCD SEG20 EVENTOUT LPTIM1 ETR SPI2 MOSI 11 67 18 K2 29 PC3 VO FT a LCD VLCD SAI1 SD A ADC123 4 LPTIM2 ETR EVENTOUT 19 30 VSSA S 20 31 VREF S 12 69 J1 VSSANREF S 68 21 11 32 VREF S VREFBUF OUT 9 22 M1 33 VDDA S 13 VDDA VREF S 62 231 DocID025977 Rev 4 STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions continued Pin Number Pin functions i 5 5 5 a qe 8 Alternate functions Badio na reset gt v 9 functions S z 3 5 93 9 TIM2_CH1 TIM5_CH1 TIM8 ETR USART2 CTS 1 P 14 H8 23 L2 34 PAO UARTA TX rM RTC TAMP2 SAI1 EXTCLK WKUP1 TIM2 ETR EVENTOUT M3 OPAMP1_VINM TT TIM2
61. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Ly STM32L486xx block 2 15 Power supply 20 ees c P TT 34 STM32L486Zx LQFP144 57 STM32L486Qx UFBGA132 58 STM32L486Vx LQFP100 eas etta scene der oti n o dt 58 STM32L486Jx WLCSP72 59 STM32L486Rx LQFP64 59 STM32L486 memory map 89 Pin loading 2 94 Pin input volage ee de RO RR REOR 94 Power supply 95 Current consumpt
62. GPIO PORT D E Y ST Standby Y VBAT 1 55 to 3 6 V PE 15 0 C GPIO PORT E lt lt gt i Reset amp clock interface _ control VBAT peso lt lt IN XTAL 32 kHz i Kc Y OSC32 OUT PGH5 0 amp lt ES 160 lt Y GPIO PORT G KS Backup register v reme PH GPIO PORTH E RTC OUT wD Temperature sensor s 2 lt 4 channels ETR as AF VDDA K TIM3 8 analog inputs common 16b a channel E TRES AE to the 3ADCs 5 TIM4 B analog inputs common han gt 4 channels ETR as AF to the ADC1 amp 2 7 TIMS 32b gt 4 channels ETR as AF 8 analog inputs for ADC3 Cy smcard 2 Ke USART2 PER C RX TX CK CTS RTS as AF VREF lt Buffer smeard gt gt RX TX CK CTS RTS as AF AHB APB2 AHB APB1 Kc USARTS irDA dad EXT IT WKUP s UART4 C RX TX CTS RTS as AF 0075 o UARTS gt Rx TX CTS RTS as AF as AF 7 E lt C compl channels TIM1_CH 1 3 N 2 MISO SCK NSS as AF 4 channels TIM1_CH 1 4 Y 1 165 K gt ETR BKIN BKIN2 as AF gt SP3 MISO SCK NSS as AF compl channels TIM1_CH 1 3 N 4 channels TIM1 CH 1 4 C TIM8 PWM 16b lt I2C1 SMBUS SCL SDA SMBA as AF ETR BKIN BKIN2 as AF 2 channels I2C2 SMBUS C SCL SDA SMBA as AF a 165 gt 1 compl channel
63. Pin name function after reset PB3 JTDO TRACESWO Pin type structure FT la Notes Pin functions LCD SEG7 SAM SCK Alternate functions JTDO TRACESWO TIM2_CH2 SPI1 SCK SPI3 SCK USART1 RTS DE EVENTOUT Additional functions COMP2 INM 56 57 90 7 91 5 134 135 PB4 NJTRST PB5 1 0 FT la FT la 3 TSC G2 101 1 SEGS SPI3_MOSI USART1 CK TSC G2 IO2 LCD SEGS9 NJTRST TIM3_CH1 SPI1 MISO SPI3 MISO USART1 CTS 5 RTS DE SAI1 MCLK B TIM17 BKIN EVENTOUT LPTIM1 IN1 TIM3 CH2 I2C1 SMBA SPI1 MOSI UARTS5 CTS COMP2 OUT SAI1 SD B TIM16 EVENTOUT COMP2 INP 58 B7 92 BS 136 PB6 _ SAI1 FS B TIM16 CH1N LPTIM1 4 1 TIM8 BKIN2 I2C1 SCL DFSDM_DATINS USART1_TX TSC_G2_103 TIM8_BKIN2_COMP2 EVENTOUT COMP2_INP 59 7 93 B4 137 PB7 1 0 FT_fla TIM17_CH1N EVENTOUT LPTIM1_IN2 TIM4_CH2 TIM8_BKIN 2 1 SDA DFSDM 5 USART1 RX UARTA CTS TSC G2 104 LCD 5 21 NL TIM8 BKIN 1 COMP2 INM PVD IN 60 07 94 A4 138 BOOTO 61 E7 95 139 8 FT fl TIM4 CHS3 I2C1 SCL DFSDM DATING CAN1 RX LCD SEG16 SDMMC1 DA SAI1 16 1 721231 DoclD0
64. UFBGA1 LQFP144 Pin type structure Notes TIM1_CH1N DFSDM_CKIN2 FMC_D5 SAI1 SCK B EVENTOUT TIM1 DFSDM CKOUT 40 60 PE9 VO FT FMC pe SAM FS B EVENTOUT 26 61 vss s 66 62 VDD S TIM1_CH2N DFSDM DATIN4 TSC G5 101 41 18 63 PE10 FT QUADSPI 07 I SAI1_MCLK_B EVENTOUT TIM1 CH2 DFSDM_CKIN4 42 M9 64 PE11 TSC G5 102 QUADSPI NCS D8 EVENTOUT TIM1 CH3N SPI1 55 DFSDM_DATINS 43 L9 65 PE12 vO FT 5 65 103 QUADSPI BK1 100 D9 EVENTOUT TIM1 CH3 SPI1_SCK DFSDM 5 44 M10 66 PE13 vO FT TSC_G5_104 i QUADSPI_BK1_IO1 FMC_D10 EVENTOUT TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_COMP2 45 11 67 PE14 vo FT SPI1_MISO QUADSPI BK1 102 D11 EVENTOUT TIM1 BKIN TIM1 BKIN 1 46 12 68 PE15 FT SPI1 MOSI QUADSPI BK1 103 FMC D12 EVENTOUT A 4 PE8 q DocID025977 Rev 4 65 231 Pinouts and pin description STM32L486xx Table 15 STM32L486xx pin definitions continued Pin Number LQFP64 WLCSP72 29 H3 LQFP100 47 32 UFBGA1 L10 LQFP144 69 Pin name function after reset PB10 Pin type 1 0 structure
65. a more precise second source clock 50 or 60 Hz can be used to enhance the calendar precision e Digital calibration circuit with 0 95 ppm resolution to compensate for quartz crystal inaccuracy e Three anti tamper detection pins with programmable filter Timestamp feature which can be used to save the calendar content This function can be triggered by an event on the timestamp pin or by a tamper event or by a switch to VBAT mode e 17 bit auto reload wakeup timer WUT for periodic events with programmable resolution and period The RTC and the 32 backup registers are supplied through a switch that takes power either from the Vpp supply when present or from the VBAT pin The backup registers are 32 bit registers used to store 128 bytes of user application data when VDD power is not present They are not reset by a system or power reset or when the device wakes up from Standby or Shutdown mode The RTC clock sources can be e A32 768 kHz external crystal LSE e An external resonator or oscillator LSE e The internal low power RC oscillator LSI with typical frequency of 32 kHz e high speed external clock HSE divided by 32 The RTC is functional in VBAT mode and in all low power modes when it is clocked by the LSE When clocked by the LSI the RTC is not functional in VBAT mode but is functional in all low power modes except Shutdown mode All RTC events Alarm WakeUp Timer Timestamp or Tamper can generat
66. q DocID025977 Rev 4 229 231 Revision history STM32L486xx 230 231 Table 113 Document revision history continued Date 04 Dec 2015 Revision Changes In all the document Stop 1 with main regulator becomes Stop 0 Stop 1 with low power regulator remains as Stop 1 In Section 4 Pinouts and pin description PC14 OSC32 IN becomes PC14 OSC32 IN PC14 15 08 32 OUT becomes PC15 OSC32 OUT PC15 becomes PHO OSC_IN PHO PH1 OSC OUT becomes PH1 OSC OUT PH1 PA13 becomes PA13 JTMS SWDIO PA14 becomes PA14 JTCK SWCLK PA15 becomes PA15 JTDI PB3 becomes PB3 JTDO TRACESWO PB4 becomes PB4 NJTRST Added Table 12 STM32L4x6 USART UART LPUART features Added Note 5 Updated Table 25 Embedded internal voltage reference Updated Table 34 Current consumption in Stop 2 mode Updated Table 35 Current consumption in Stop 1 mode Updated Table 36 Current consumption in Stop 0 mode Updated Table 37 Current consumption in Standby mode Updated Table 38 Current consumption in Shutdown mode Updated Table 41 Low power mode wakeup timings Added Figure 14 VREFINT versus temperature Updated Figure 19 5116 frequency versus temperature Updated Table 58 I O static characteristics Updated Table 69 DAC characteristics Updated Figure 51 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package o
67. 1 3 7 I2Cx x 1 3 LPTIMx x 1 2 LPTIMx 1 2 FS All other peripherals are swPMn 9 frozen BOR PVD PVM RTC LCD IWDG Reset pin all I Os COMPx 1 2 BOR PVD PVM jk 12 3 7 RTC LCD IWDG uA w o RTC 5 us in SRAM Stop 2 LPR No Off ON LSI LPUART1 9 COMPXx x 1 2 14 uA WIRTC LPTIM1 I2c30 7 us in Flash LPUART1 9 All other peripherals are LPTIM1 frozen 98 1651 M IAJBAO y ed 2 6 20 Table 4 STM32L486 modes overview continued Mode Regulator CPU Flash SRAM Clocks DMA amp Peripherals Wakeup source Consumption Wakeup time SRAM2 BOR RTC IWDG 0 35 pA w o RTC LPR ON d 0 65 uA w RTC All other peripherals are Reset pin LSE Standby ie Off P powered off 5 WKUPx 19 14 us OFF Powered BOR RTC IWDG 0 12 uA w o RTC off configuration can be 0 42 pA wi RTC floating pull up or pull down RTC All other peripherals are Reset pin Powered Powered 10 0 03 pA w o RTC Shutdown OFF off Off Of LSE powered off 5 I Os WKUPx 0 33 uA w RTC 256 us 15 RTC configuration can be floating pull up or pull down 11 e a S uo wo wd LPR means Main regulator is OFF and Low power regulator is ON All peripherals can be active or clock gated to save power consumption Typical current at Vpp 1 8 V 25 C Consumptions values provid
68. 1 Wake up time from Stop 0 Wakeup clock HSI16 16 MHz 1 7 2 8 mode to Low power run Wakeup clock MSI 24 MHz 0 8 2 72 SRANI Range 2 Wakeup clock HSI16 16 MHz 17 2 8 Wakeup clock MSI 4 MHz 2 4 11 32 q DocID025977 Rev 4 125 231 Electrical characteristics STM32L486xx Table 41 Low power mode wakeup timings continued Symbol Parameter Conditions Typ Max Unit Wakeup clock MSI 48 MHz 6 2 10 2 Range 1 Wakeup clock HSI16 16 MHz 6 3 8 99 Wakeup Rims mom tap Wakeup clock MSI 24 MHz 6 3 10 46 mode to Run mode in Flash P Range 2 Wakeup clock HSI16 16 MHz 6 3 8 87 Wakeup clock MSI 4 MHz 8 0 13 23 Wakeup clock MSI 48 MHz 4 5 5 78 Range 1 Wake up time from Stop 1 Wakeup clock HSI16 16 MHz 5 5 7 1 twustop1 Mode to Low power run Wakeup clock MSI 24 MHz 5 0 6 5 us mode inSRAMI Range 2 Wakeup clock HSI16 16 MHz 55 7 1 Wakeup clock MSI 4 MHz 8 2 13 5 Wake up time from Stop 1 mode to Low power run Reaulator i 12 7 20 mode in Flash Ow power Wakeup clock MSI 2 MHz mode LPR 1 in Wake up time from Stop 1 PWR CR4 mode to Low power run B 10 7 21 5 mode in SRAM1 Wakeup clock MSI 48 MHz 8 0 9 4 Range 1 Wakeup clock HSI16 16 MHz 7 3 9 3 Wake up time from Stop 2 modeto Run mode in Flach Wakeup clock MSI 2
69. 2 56 Range2 4MHz 0 55 0 59 0 69 0 85 1 18 0 61 0 70 0 89 124 1 95 2MHz 0 34 0 37 0 47 0 64 0 96 037 046 0 64 0 98 1 71 fucik fuse up to 1 MHz 0 23 0 26 0 36 0 53 0 85 027 0 33 0 50 0 86 1 57 Suppl 48MHz included PPlY bypass mode 100kHz 0 14 0 17 0 27 043 0 75 0 17 0 21 0 38 0 74 144 Ipp Run current in PLL ON above mA Run mode sary al 80 MHz 10 2 10 3 10 5 107 111 1122 11 8 12 1 125 13 3 peripherals disable 72MHz 9 24 9 31 9 47 9 69 10 1 10 16 107 11 0 11 4 122 64 MHz 8 25 832 846 8 68 909 9 08 96 9 9 10 3 11 1 Range 1 48 MHz 628 6 35 65 672 7 11 6 91 7 3 7 6 8 0 8 8 32 MHz 4 24 4 30 444 465 5 04 466 497 526 5 67 6 51 24MHz 3 21 327 34 3 61 3 98 3 53 376 405 446 5 30 16MHz 2 19 224 2 36 2 56 294 241 2 66 2 95 3 16 3 99 2MHz 272 303 413 592 958 330 393 579 954 1704 Suppl rm 22 fucik fusi 1MHz 154 184 293 473 835 195 265 457 822 1572 pegada all peripherals disable 400kHz 78 108 217 396 758 110 180 380 755 1505 run mode 100kHz 42 73 182 360 723 75 138 331 706 1456 1 Guaranteed by characterization results unless otherwise specified 98 1551 sonsioj2eJeuo e21329 3 150 901 y ed 2 6 20 Table 2
70. 2 99 3 13 3 35 3 75 3 22 3 43 3 72 4 13 4 97 2MHz 358 392 503 683 1050 435 501 694 1069 1819 Supply ico LPRun current in fusi 1MHz 197 230 340 519 880 245 312 512 887 1637 B Low power all peripherals disable 400kHz 97 126 235 414 778 130 202 402 777 1527 run 100kHz 47 77 186 365 726 85 147 347 711 1472 1 Guaranteed by characterization results unless otherwise specified sonsiuoj2eJeuo e2129 3 XX987 1ZEINLS y ed 2 6 20 186 401 Table 28 Current consumption Run and Low power run modes code with data processing running from SRAM1 Conditions TYP MAX Symbol Parameter Unit Voltage E ee 105 125 I ee 105 125 scaling 25 C 55 C 85 sc 25 C 55 85 C ic 26 MHz 2 88 2 94 3 05 323 3 58 3 18 326 340 402 4 65 16 MHz 1 83 1 87 1 98 2 15 2 50 2 01 2 16 2 30 2 72 3 34 8MHz 0 97 1 00 1 11 1 27 1 62 1 07 1 16 1 32 1 73 2 36 Range2 4MHz 0 54 0 57 0 67 0 84 1 18 0 59 0 69 0 88 1 23 1 96 2MHz 0 33 0 36 0 46 0 62 0 96 0 37 0 45 0 63 0 98 1 70 fuse up to ABMHz included 1 MHz 0 22 0 25 0 35 0 51 0 85 0 25 0 33 0 50 0 86 1 57
71. 2 level voltage 1 2 Vicp gt V V13 Segment Common 1 3 level voltage 1 3 Vi ep Segment Common 1 4 level voltage 1 4 Vi Segment Common lowest level voltage 0 V44 Vo Ly DoclD025977 Rev 4 175 231 Electrical characteristics STM32L486xx 1 Guaranteed by design 2 LCD enabled with 3 V internal step up active 1 8 duty 1 4 bias division ratio 64 all pixels active no LCD connected q 176 231 DocID025977 Rev 4 STM32L486xx Electrical characteristics 6 3 25 DFSDM characteristics Unless otherwise specified the parameters given in Table 78 for DFSDM are derived from tests performed under the ambient temperature fApg2 frequency and Vpp supply voltage conditions summarized in Table 22 General operating conditions e Output speed is set to OSPEEDRy 1 0 10 e Capacitive load C 30 pF e Measurement points are done at CMOS levels 0 5 x VDD Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics DFSDM_CKINy DFSDM_DATINy DFSDM_CKOUT for DFSDM Table 78 DFSDM characteristics Symbol Parameter Conditions Min Typ Max Unit fprspwcuk DFSDM clock fsyscLK Input clock 20 MHz SPI mode SITP 1 0 01 1 frequency See foFspucuk 4 Output clock fckour frequency 7 I I 29 Output clock DuCycxourt frequency 45 50 5
72. 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package recommended footprint Dpad 00000000 00000000 00000000 WLCSP72 A02R FP V1 Table 109 WLCSP72 recommended PCB design rules 0 4 mm pitch BGA Dimension Recommended values Pitch 0 4 mm Dpad 0 225 mm 0 290 mm typ depends on the solder mask registration tolerance Stencil opening 0 250 mm Stencil thickness 0 100 mm 220 231 DoclD025977 Rev 4 Ky STM32L486xx Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location Figure 59 WLCSP72 marking package top view Ball A1 identifier Lu amp bJGYE Product identification Revision code Date code MSv36871V3 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity q DocID025977 Rev 4 221 231 Package information STM32L
73. 43 1 56 1 85 226 3 10 24 MHz 1 01 1 05 1 17 1 37 1 76 1 11 1 23 1 52 1 93 2 77 16 MHz 0 71 0 75 0 87 1 07 1 45 0 80 0 90 1 19 1 60 2 44 Supply 2MHz 96 126 233 412 775 130 202 402 777 1527 currentin e f 1MHz 65 94 202 381 742 95 166 358 733 1483 Ipp LPSleep low power HCLK MSI sleep Peripherals disable 400 43 73 181 359 718 75 138 331 706 1456 mode 100 kHz 33 63 171 348 708 65 128 322 691 1441 1 Guaranteed by characterization results unless otherwise specified sonsiuoj2eJeuo e2129 3 XX987 1ZEINLS y ed LZ6SZ20d190d LEC LLL Table 33 Current consumption in Low power sleep modes Flash in power down Conditions TYP MAX Symbol Parameter Voltaqe Unit coin 25 C 55 85 C 105 125 C 25 C 55 85 C 105 125 C 2MHz 81 110 217 395 754 115 182 375 750 1500 Ipp LPSleep 2 fuese fus 1MHz 50 78 185 362 720 80 149 342 717 1456 sleep mode Peripherals disable kHz 28 57 163 340 698 60 122 314 689 1429 100kHz 18 47 155 332 686 50 114 313 688 1438 1 Guaranteed by characterization results unless otherwise specified
74. 5 Fast channel max speed 1 1 2 Differential Slow channel max speed 1 1 2 Single Fast channel max speed 1 5 3 5 ended Slow channel 1 5 3 5 Fast channel max speed 1 3 Differential Slow channel max speed 1 2 5 Single Fast channel max speed 10 10 5 ended Slow channel max speed 10 10 5 its Fast channel max speed 10 7 10 9 Differential Slow channel max speed 10 7 10 9 Single Fast channel max speed 62 65 ended Slow channel max speed 62 65 Fast channel max speed 66 67 4 Differential Slow channel max speed 66 67 4 dB Single Fast channel max speed 64 66 ended Slow channel max speed 64 66 Fast channel max speed 66 5 68 Differential Slow channel max speed 66 5 68 DoclD025977 Rev 4 157 231 Electrical characteristics STM32L486xx Table 66 ADC accuracy limited test conditions 2 1 2 3 continued Sym bol THD Parameter Total harmonic distortion ADC clock frequency lt 80 MHz Sampling rate lt 5 33 Msps 2 V S VppA Conditions Min Typ Max Unit Single Fast channel max speed 74 65 ended Slow channel max speed 74 67 dB Fast channel max speed 79 70 Differential Slow channel max speed 79 71 1 Guaranteed by design 2 ADC DC accuracy
75. 6 VIN lt 5 5 VOS I I 2009 Vin lt Max Vppxxx 150 FT lu FT uand Viy 2500090 Max Vppxxx 1 V PC3 IO nA kg Max V 1 V lt DDXX 7 VIN lt 5 5 VOGN I I 2507 Vin lt Max Vppxxx 150 TT xx input leakage t Max Vppxxx lt Vin lt 3 curren Be V 20000 OPAMPx VINM x 1 2 dedicated T 275 C _ _ 1 input leakage current UFBGA132 only Weak pull up _ equivalent resistor 8 Vin Vss 25 40 99 is Weak pull down Rpp equivalent resistor Vin Vppiox 29 40 99 Cio I O pin capacitance 5 pF 1 Refer to Figure 21 I O input characteristics 2 Tested in production 3 Guaranteed by design 4 Max Vppxxx is the maximum value of all the I O supplies Refer to Table Legend Abbreviations used in the pinout table 5 All TX IO except FT FT and 6 This value represents the pad leakage of the IO itself The total product pad leakage is provided by this formula Total max 10 number of IOs where Viy is applied on the pad x ly Max 7 To sustain a voltage higher than MIN Vpp Vppa Vppio2 Vi cp 0 3 V the internal Pull up and Pull Down resistors must be disabled 8 Pull up and pull down resistors are designed with a true resistance in series with a switchable PMOS NMOS This PMOS NMOS contribution to the series resistance is minimal 71096 order 144 231 DoclD025977 Rev 4 q STM32L486xx Electrica
76. FMC_NADV low 1 tw NADV FMC_NADV low time 0 5 1 CL 30 pF 2 Guaranteed by characterization results Table 91 Asynchronous non multiplexed SRAM PSRAM NOR read NWAIT timings Symbol Parameter Min Max Unit FMC NE low time 0 5 0 5 NWE low time 5Tucuc0 5 5 0 5 twnwait FMC NWAIT low time 0 5 ns tsu NWAIT_NE FMC_NWAIT valid before FMC_NEx high 5Tucik 2 FMC_NEx hold time after FMC_NWAIT invalid 4 1 CL 30 pF 2 Guaranteed by characterization results 194 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics q Figure 37 Asynchronous non multiplexed SRAM PSRAM NOR write waveforms NOE tw NE FMC A 25 0 NBL 1 0 D 15 0 NADV 1 NWAIT tv NADV NE tw NADV th NE NWAIT tsu NWAIT NE th NE NWE MS32754V1 Table 92 Asynchronous non multiplexed SRAM PSRAM NOR write timings Symbol Parameter Min Max Unit tw NE FMC_NE low time 1 3THcLKt2 twNWE_NE FMC_NEx low to FMC_NWE low 0 5 1 5 twNwe FMC NWE low time 1 1 th NE_NWE FMC_NWE high to FMC NE high hold time 0 5 tA ne NEx low to valid 2 0 nwe Address hold time a
77. FMC_WaitSetupTime 0x03 ATT FMC_HoldSetupTime 0x02 ATT FMC_HiZSetupTime 0x03 Bank FMC_Bank_NAND MemoryDataWidth FMC_MemoryDataWidth_16b ECC FMC_ECC_Enable ECCPageSize FMC_ECCPageSize_512Bytes TCLRSetupTime 0 TARSetupTime 0 In all timing tables the is the HCLK clock period DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Figure 44 NAND controller waveforms for read access FMC_NCEx ALE FMC_A17 CLE FMC_A16 FMC_NWE la NCE NOE th NOE ALE FMC_NOE NRE tsu D NOE D 15 0 MSv38003V1 Figure 45 NAND controller waveforms for write access FMC NCEx ALE A17 CLE FMC A16 ta NCE NWE th NWE ALE NwE FMC_NOE NRE D 15 0 MSv38004V1 Figure 46 NAND controller waveforms for common memory read access FMC_NCEx ALE FMC_A17 CLE FMC_A16 la NCE NOE 4 th NOE ALE FMC_NWE FMC_NOE FMC_D 15 0 MSv38005V1 q DocID025977 Rev 4 207 231 Electrical characteristics STM32L486xx Figure 47 NAND controller waveforms for common memory write access FMC_NCEx ALE FMC_A17 CLE FMC_A16 la NCE NWE gt lt lu NWE gt lt D 15 0 gt n NOE ALE NWE 55 MSv38006V1 Table 102 Switching characteristics for NAND Flash read cycles
78. For information on selecting the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Figure 17 Typical application with an 8 MHz crystal Resonator with integrated capacitors Bias controlled gain MS19876V1 1 Re xz value depends on the crystal characteristics Low speed external clock generated from a crystal resonator The low speed external LSE clock can be supplied with a 32 768 kHz crystal resonator oscillator All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 46 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 46 LSE oscillator characteristics f s 32 768 kHz Symbol Parameter Conditions 2 Min Typ Max Unit LSEDRV 1 0 00 Low drive capability LSEDRWV 1 0 01 _ 315 _ Medium low drive capability LSE current consumption nA LSEDRV 1 0 10 lee re Medium high drive capability LSEDRV 1 0 11 High drive capability LSEDRV 1 0 00 Low drive capability LSEDRV 1 0 01 Bm Maximum critical crystal Medium low drive capab
79. It features 32 231 Clock prescaler to get the best trade off between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register Clock management to reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory System clock source four different clock sources can be used to drive the master clock SYSCLK 4 48 MHz high speed external crystal or ceramic resonator HSE that can supply a PLL The HSE can also be configured in bypass mode for an external clock 16 MHz high speed internal RC oscillator HSI16 trimmable by software that can supply a PLL Multispeed internal RC oscillator MSI trimmable by software able to generate 12 frequencies from 100 kHz to 48 MHz When a 32 768 kHz clock source is available in the system LSE the MSI frequency can be automatically trimmed by hardware to reach better than 0 25 accuracy In this mode the MSI can feed the USB device saving the need of an external high speed crystal HSE The MSI can supply a PLL System PLL which can be fed by HSE HS116 or MSI with a maximum frequency at 80 MHz Auxiliary clock source two ultralow power clock sources that can be used to drive the LCD controller and the real time clock 32 768 kHz low spee
80. KB GPIOC 0x4800 0400 0x4800 07FF 1 KB GPIOB 0x4800 0000 0x4800 1 KB GPIOA 0x4002 4400 Ox47FF FFFF 127 Reserved 0x4002 4000 0x4002 43FF 1 KB TSC 0x4002 3400 0x4002 3FFF 1 KB Reserved 0x4002 3000 0x4002 33FF 1 KB CRC 0x4002 2400 0x4002 2FFF 3 KB Reserved 0x4002 2000 0x4002 23FF 1 KB FLASH registers died 0x4002 1400 0x4002 1FFF 3KB Reserved 0x4002 1000 0x4002 13FF 1 KB RCC 0x4002 0800 0x4002 OFFF 2KB Reserved 0x4002 0400 0x4002 07FF 1 KB DMA2 0x4002 0000 0x4002 1 KB DMA1 DoclD025977 Rev 4 q STM32L486xx Memory mapping q Table 18 STM32L486xx memory map and peripheral register boundary addresses continued Bus Boundary address eras Peripheral 0x4001 6400 0x4001 FFFF 39 KB Reserved 0x4001 6000 0x4000 63FF 1 KB DFSDM 0x4001 5 00 0x4000 5FFF 1 Reserved APB2 0x4001 5800 0x4000 5BFF 1 KB SAI2 0x4001 5400 0x4000 57FF 1 KB 0x4001 4 00 0x4000 53FF 2KB Reserved 0x4001 4800 0x4001 4BFF 1 KB TIM17 0x4001 4400 0x4001 47FF 1 KB TIM16 0x4001 4000 0x4001 43FF 1 KB TIM15 0x4001 3 00 0x4001 3FFF 1 KB Reserved 0x4001 3800 0x4001 3BFF 1 KB USART1 0x4001 3400 0x4001 37FF 1 KB TIM8 0x4001 3000 0x4001 33FF 1 KB SPI1 0x4001 2 00 0x4001 2FFF 1 TIM1 APB2 0x4001 2800 0x4001 2BFF 1 KB SDMMC1 0x4001 2000 0x4001 27FF 2KB Reserved 0x4001 1 00 0x4001 1F
81. LPR is used in Low Power Run Low Power Sleep Stop 1 and Stop 2 modes It is also used to supply the 32 Kbyte SRAM2 in Standby with RAM2 retention e Both regulators are power down in Standby and Shutdown modes the regulator output is in high impedance and the kernel circuitry is powered down thus inducing zero consumption The ultralow power STM32L486xx supports dynamic voltage scaling to optimize its power consumption in run mode The voltage from the Main Regulator that supplies the logic VCORE can be adjusted according to the system s maximum operating frequency There are two power consumption ranges e Range 1 with the CPU running at up to 80 MHz e Range 2 with a maximum CPU frequency of 26 MHz All peripheral clocks are also limited to 26 MHz The VCORE can be supplied by the low power regulator the main regulator being switched off The system is then in Low power run mode e Low power run mode with the CPU running at up to 2 MHz Peripherals with independent clock can be clocked by 5116 Low power modes The ultra low power STM32L486xx supports seven low power modes to achieve the best compromise between low power consumption short startup time available peripherals and available wakeup sources DoclD025977 Rev 4 21 231 y ed 2 6 20 Table 4 STM32L486 modes overview Mode SRAM Clocks DMA amp Peripherals Wake
82. O switching frequency C is the total capacitance seen by the I O pin C Cs Cs is the PCB board capacitance including the pad pin The test pin is configured in push pull output mode and is toggled by software at a fixed frequency DoclD025977 Rev 4 121 231 Electrical characteristics STM32L486xx On chip peripheral current consumption The current consumption of the on chip peripherals is given in Table 40 The MCU is placed under the following conditions e AI I O pins are in Analog mode e given value is calculated by measuring the difference of the current consumptions when the peripheral is clocked on when the peripheral is clocked off e Ambient operating temperature and supply voltage conditions summarized in Table 19 Voltage characteristics e power consumption of the digital part of the on chip peripherals is given in Table 40 The power consumption of the analog part of the peripherals where applicable is indicated in each related section of the datasheet Table 40 Peripheral current consumption Peripheral Range 1 Range 2 dec Unit Bus Matrix 4 5 3 7 4 1 ADC independent clock domain 0 4 0 1 0 2 ADC AHB clock domain 5 5 4 7 5 5 AES 17 1 5 1 6 CRC 0 4 0 2 0 3 DMA 14 1 8 14 DMA2 1 5 1 3 1 4 FLASH 6 2 5 2 5 8 FMC 8 9 7 5 8 4 4 8 3 8 4 4 4 8 4 0 4 6 4 5 3 8 4 3
83. PF9 PF10 PHO OSC PH1 OSC OUT NRST PCO PC1 PC2 PC3 VSSA VREF VREF VDDA PAO PA1 PA2 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDIO2 VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD vss PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 SSSSIIFISSSSIRERKBSBBERSSSSSESIESSSESRER LI U LI LI LI LI LI LI LI LI LI LI U LI LI LI LI LI U U LI LI LI LI LI LI LI LI LI UUU LI LI LI LI MS31270V4 1 The above figure shows the package top view DoclD025977 Rev 4 57 231 Pinouts and pin description STM32L486xx 58 231 Figure 5 STM32L486Qx UFBGA132 ballout 3 OSC32 IN i r OUT TOOL EL BEEN OPAMP1_ VINM BOOTO 5 6 OPAMP2_ VINM EXE ias 11 12 VDDUSB MSv35003V7 1 The above figure shows the package top view Figure 6 STM32L486Vx LQFP100 pinout PE2 r 1 VDD 2 vss PE4 g VDDUSB 4 PA13 5 PA12 VBAT 6 PA11 PC13 7 10 14 05 32 8 PA9 PC15 OSC32 OUT PA8 VSS PC9 VDD PC8 PHO OSC_IN PC7 PH1 OSC_OUT LQFP100 PC6 NRST PD15 PCO PD14 PC1 PD13 PC2 PD12 PC3 PD11 VSSA PD10 VREF PD9 VREF PD8 VDDA PB15 PAO PB14 PB13 PA2 PB12 MS31271V3 1 The above figure shows the package top view DoclD025977 Rev 4 STM32L486xx Pinouts and pin descrip
84. Power supply schemes Updated Section 3 15 1 Temperature sensor In all Section 6 Electrical characteristics renamed table footnotes related to test and characterization Added Note 2 Updated Table 41 Low power mode wakeup timings Updated Table 42 Regulator modes transition times Updated Table 47 5116 oscillator characteristics Added Table 19 HSI16 frequency versus temperature Updated Table 48 MSI oscillator characteristics Updated Table 49 LSI oscillator characteristics Updated Table 57 current injection susceptibility Removed first Note in Table 58 I O static characteristics Removed second Note in Table 59 Output voltage characteristics Updated Table 63 ADC characteristics Updated Table 65 ADC accuracy limited test conditions 1 Added Table 66 ADC accuracy limited test conditions 2 Added Table 67 ADC accuracy limited test conditions 3 Added Table 68 ADC accuracy limited test conditions 4 Updated Table 70 DAC accuracy Updated Table 71 VREFBUF characteristics Added Section 6 3 25 DFSDM characteristics Updated Section Quad SPI characteristics Updated Table 84 Quad SPI characteristics in SDR mode Updated Table 85 QUADSPI characteristics in DDR mode Updated Table 89 USB electrical characteristics Updated Section 7 2 UFBGA132 package information Updated Section 7 4 WLCSP72 package information Updated Table 62 LQFP64 marking package top view
85. SEG41 LCD 6 12 UARTS TX TSC G3 104 i LCD SEG3O SDMMC1_CK SAI2 SD B EVENTOUT LCD SEG42 PC13 5 EVENTOUT PC14 1 EVENTOUT PC15 F EVENTOUT XX987 1ZEINLS uonduosep uid pue s ynould LEc vs y ed 2 6 20 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 UART5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PDO CAN1_RX FMC D2 EVENTOUT PD1 CAN1 TX FMC D3 EVENTOUT LCD COM7 PD2 UART5 RX TSC SYNC LCD SEG31 SDMMC1 EVENTOUT LCD SEG43 PD3 FMC CLK EVENTOUT PD4 FMC NOE EVENTOUT PD5 FMC NWE EVENTOUT PD6 NWAIT SAM SD A EVENTOUT Pot p PD7 NE1 EVENTOUT PD8 LCD SEG28 FMC D13 EVENTOUT PD9 LCD SEG29 FMC D14 imr gt EVENTOUT PD10 TSC G6 101 LCD SEG30 D15 SAI2 SCK A EVENTOUT PD11 TSC G6 102 LCD SEG31 FMC A16 SAI2 SD A LPTIM2 ETR EVENTOUT PD12 TSC G6 103 LCD SEG32 FMC A17 SAI2 FS LPTIM2 IN1 EVENTOUT PD13 TSC G6 104 LCD SEG33 FMC A18 LPTIM2 OUT EVENTOUT PD14 LCD SEG34 DO EVENTOUT PD15 LCD SEG35 FMC D1 EVENTOUT
86. The timers have independent DMA request generation The counters can be frozen in debug mode Basic timers TIM6 and TIM7 The basic timers are mainly used for DAC trigger generation They can also be used as generic 16 bit timebases Low power timer LPTIM1 and LPTIM2 The devices embed two low power timers These timers have an independent clock and are running in Stop mode if they are clocked by LSE LSI or an external clock They are able to wakeup the system from Stop mode LPTIM1 is active in Stop 0 Stop 1 and Stop 2 modes LPTIM2 is active in Stop 0 and Stop 1 mode DoclD025977 Rev 4 45 231 Functional overview STM32L486xx 3 25 5 3 25 6 3 25 7 46 231 This low power timer supports the following features e 16 bit up counter with 16 bit autoreload register e 16 bit compare register e Configurable output pulse PWM e Continuous one shot mode e Selectable software hardware input trigger e Selectable clock source Internal clock sources LSE LSI HSI16 APB clock External clock source over LPTIM input working even with no internal clock Source running used by pulse counter application e Programmable digital glitch filter e Encoder mode LPTIM1 only Independent watchdog IWDG The independent watchdog is based on a 12 bit downcounter and 8 bit prescaler It is clocked from an independent 32 kHz internal RC LSI and as it operates independently from the main clock it can operate in St
87. UAMHz GPIOD 4 6 3 9 44 GPIOEO 5 2 4 5 4 9 GPIOF 5 9 4 9 5 7 GPIOG 4 3 3 8 42 0 7 0 6 0 8 22 independent clock 23 2 NA NA OTG FS AHB clock domain 16 4 NA NA QUADSPI 7 8 6 7 7 8 RNG independent clock domain 2 2 NA NA RNG AHB clock domain 0 6 NA NA SRAM1 0 9 0 8 0 9 122 231 DoclD025977 Rev 4 Ky STM32L486xx Electrical characteristics Table 40 Peripheral current consumption continued Peripheral Range 1 Range 2 Eo Unit SRAM2 1 6 1 4 1 6 AHB TSC 1 8 1 4 1 6 2 All AHB Peripherals 118 5 77 3 87 6 AHB to APB1 bridge 0 9 0 7 0 9 CAN1 4 6 4 0 4 4 DAC1 24 1 9 2 2 I2C1 independent clock domain 3 7 3 1 3 2 I2C1 APB clock domain 1 3 1 1 1 5 I2C2 independent clock domain 3 7 3 0 3 2 12 2 APB clock domain 1 4 1 1 1 5 I2C3 independent clock domain 2 9 2 3 2 5 12 APB clock domain 0 9 0 9 1 1 LCD 1 0 0 8 0 9 2 independent clock 24 46 20 LPUART1 APB clock domain 0 6 0 6 0 6 piii a independent clock 33 26 29 LPTIM1 APB clock domain 0 9 0 8 1 0 APB1 2 piis independent clock 34 27 29 LPTIM2 APB clock domain 0 8 0 6 0 7 OPAMP 0 4 0 4 0 3 PWR 0 5 0 5 0 4 SPI2 1 8 1 6 1 6 SPI3 2 1 1 7 1 8 independent clock 23 48 22 SWPMI1 APB clock domain 1 1 1 1 1 0 TIM2 6 8 5 7 6 3 TIM3 5 4 4 6 5 0 TIM4 5 2 4 4 4 9 TIM5 6 5 5 5 6 1 TIM6 1 1 1 0 1 0 TIM7 1 1 0 9 1 0 Ky DoclD025977 Rev 4 123 231
88. VppA 2 2 4 V su from 10 and Low power mode 180 oe 90 of output Normal mode 300 voltage VppA lt 2 4 V Low power mode 80 Normal mode 55 110 AO Open loop gain dB Low power mode 45 110 Normal mode V 3 High saturation lload max or Rigag 100 OHSAT voltage minInputatVppa VppA Low power mode 50 mV V 3 Low saturation Normal mode load Max or Roa i 100 OLSAT voltage Low power mode Min Input at 0 _ i 50 Normal mode 74 Om Phase margin Low power mode 66 Normal mode 13 GM Gain margin dB Low power mode 20 CLOAD lt 50 pf Normal mode Z 4 5 10 follower Wake up time configuration tWAKEUP us from OFF state C oAp lt 50 pf gt Low power mode RLoap 2 20 kQ 10 30 follower configuration Dedicated input BGA132 only I 4 OPAMP input Ibias bias current General purpose input all packages _ 4 nA except BGA132 2 Non inverting 4 i PGA gain 9 gain value 8 2 16 172 231 DoclD025977 Rev 4 Ly STM32L486xx Electrical characteristics Table 73 OPAMP characteristics continued Guaranteed by design unless otherwise specified The temperature range is limited to 0 C 125 C when is below 2 V Symbol Parameter Conditions Min Typ Max Unit PGA Gain 2 80 80 120 R2 R1 internal PGA Gain 4 40 resistance R
89. a full set of DSP instructions and a memory protection unit MPU which enhances application security The STM32L486xx devices embed high speed memories 1 Mbyte of Flash memory 128 Kbyte of SRAM a flexible external memory controller FSMC for static memories for devices with packages of 100 pins and more a Quad SPI flash memories interface available on all packages and an extensive range of enhanced l Os and peripherals connected to two APB buses two AHB buses and a 32 bit multi AHB bus matrix The STM32L486xx devices embed several protection mechanisms for embedded Flash memory and SRAM readout protection write protection proprietary code readout protection and Firewall The devices offer up to three fast 12 bit ADCs 5 Msps two comparators two operational amplifiers two DAC channels an internal voltage reference buffer a low power RTC two general purpose 32 bit timer two 16 bit PWM timers dedicated to motor control seven general purpose 16 bit timers and two 16 bit low power timers The devices support four digital filters for external sigma delta modulators DFSDM In addition up to 24 capacitive sensing channels are available The devices also embed an integrated LCD driver 8x40 or 4x44 with internal step up converter They also feature standard and advanced communication interfaces e Three 2 e Three SPIs e Three USARTS two UARTs and one Low Power UART e Two SAls Serial Audio Interfaces e One SDMMC
90. after enable edge E 40 1 71 lt Vpp 3 6 tnsp A Mr Data output hold time Master transmitter after enable edge 10 ns 1 Guaranteed by characterization results 2 APB clock frequency must be at least twice SAI clock frequency Figure 32 SAI master timing waveforms output SAI SD X transmit SAI SD X receive FS 9 Vd _f _ SAI FS X m LLL tv SD Me tsu SD_MR gt lt gt th FS lt gt th SD_MT MS32771V1 q DocID025977 Rev 4 187 231 Electrical characteristics STM32L486xx 188 231 Figure 33 SAI slave timing waveforms 145 SAI SCK X tw CKH_ x P9 tw CKL X i 4 SAI FS X input tsu FS 4 SD ST ST transmit tsu SD_SR eo SR receive MS32772N1 SDMMC characteristics Unless otherwise specified the parameters given in Table 87 for SDIO are derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 22 General operating conditions with the following configuration Output speed is set to OSPEEDRy 1 0 11 e Capacitive load 30 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output characteristics Table 87 SD MMC dynamic characteristics Vpp 2 7 V to 3 6 1
91. decouple this converter Table 77 LCD controller characteristics Symbol Parameter Conditions Min Typ Max Unit Vicp LCD external voltage 3 6 Vicpo LCD internal reference voltage 0 2 62 Vi 1 LCD internal reference voltage 1 2 76 Vicp2 LCD internal reference voltage 2 2 89 LCD internal reference voltage 3 3 04 V Vi 4 LCD internal reference voltage 4 3 19 cps LCD internal reference voltage 5 3 32 gt Vi cpe LCD internal reference voltage 6 3 46 Vi cpz LCD internal reference voltage 7 3 62 Buffer OFF 02 2 BUFEN 0 is LCD CR register 7 C V external capacitance M Buffer ON z BUFEN 1 is LCD_CR register Supply current from Vpp at Buffer OFF _ 3 _ Vpp 2 2 V BUFEN 0 is LCD CR register Supply current from Vpp at Buffer OFF _ 45 _ Vpp 3 0 V BUFEN 0 is LCD CR register Buffer OFF _ 0 5 E BUFFEN 0 PON 0 Buffer ON _ 0 6 _ Supply current from V cp BUFFEN 1 1 2 Bias UA VLCD 3V Buffer ON 0 8 BUFFEN 1 1 3 Bias I I Buffer ON _ 1 _ BUFFEN 1 1 4 Bias Run Total High Resistor value for Low drive resistive network 5 5 MQ Rin Total Low Resistor value for High drive resistive network 240 kQ V44 Segment Common highest level voltage Vicp V34 Segment Common 3 4 level voltage 3 4 Vi cp V23 Segment Common 2 3 level voltage 2 3 Vi cp V42 Segment Common 1
92. done at CMOS levels 0 3 Vpp and 0 7 Vpp Figure 29 SPI timing diagram master mode High NSS input 5 Y N 5 CPOL 0 h I i 0 T l o m I 1 1 CPHA 1 b T CPOL 0 1 1 n I CPOL 1 gt SCK Output pia 1 4 91 t dece Tut 5 SCK MISO IND UT O BITS IN LBN 1 th M MOS MsBOUT BIT1 OUT _ OUT OUTPUT C MsBOUT SU ty MO biu lt gt ai14136c 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp Ly DoclD025977 Rev 4 183 231 Electrical characteristics STM32L486xx Quad SPI characteristics Unless otherwise specified the parameters given in Table 84 and Table 85 for Quad SPI are derived from tests performed under the ambient temperature fayp frequency and Vpp supply voltage conditions summarized in Table 22 General operating conditions with the following configuration Output speed is set to OSPEEDRy 1 0 11 e Capacitive load C 15 or 20 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics Table 84 Quad SPI characteristics SDR mode Symbol Parameter Conditions Min Typ Max Unit 1 71 lt Vpp 3 6 V C
93. ensured down to 2 7 V but not the full USB electrical characteristics which are degraded in the 2 7 to 3 0 V voltage range 2 Guaranteed by design 3 No external termination series resistors are required on USB DP D and USB DM D the matching impedance is already included in the embedded driver CAN controller area network interface Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics CAN TX and RX q DocID025977 Rev 4 191 231 Electrical characteristics STM32L486xx 6 3 28 192 231 FSMC characteristics Unless otherwise specified the parameters given in Table 90 to Table 103 for the FMC interface are derived from tests performed under the ambient temperature frequency and Vpp supply voltage conditions summarized in Table 22 with the following configuration Output speed is set to OSPEEDRy 1 0 11 e Capacitive load C 30 pF e Measurement points are done at CMOS levels 0 5Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output characteristics Asynchronous waveforms and timings Figure 36 through Figure 39 represent asynchronous waveforms and Table 90 through Table 97 provide the corresponding timings The results shown in these tables are obtained with the following FMC configuration e AddressSetupTime 0 1 e AddressHoldTime 0x1 DataSetupTime 0x1 except for a
94. ground pin sink 100 Output current sunk by any I O and control pin except FT f 20 lio PIN Output current sunk by any FT f pin 20 Output current sourced by any I O and control pin 20 mA I Total output current sunk by sum of all I Os and control pins 100 IO PIN EIN Total output current sourced by sum of all I Os and control pins 100 Injected current on FT_xxx TT_xx RST and B pins except PA4 4 5 ae liNJ PIN Injected current on PA4 PAS 5 0 2 liNJ PIN Total injected current sum of all I Os and control pins 9 25 1 All main power Vpp VppA 2 Vear and ground Vss Vssa pins must always be connected to the external power supplies in the permitted range 2 This current consumption must be correctly distributed over all I Os and control pins The total output current must not be sunk sourced between two consecutive power supply pins referring to high pin count QFP packages 3 Positive injection is not possible on these I Os and does not occur for input voltages lower than the specified maximum value 4 A positive injection is induced by gt Vppiox while a negative injection is induced by Viy lt Vss must never be exceeded Refer also to Table 19 Voltage characteristics for the maximum allowed input voltage values 5 When several inputs are submitted to a current injection the maximum gt is the absolute sum of the positive and negative injec
95. internal pull up on PA15 PA13 PB4 pins and the internal pull down on 14 pin are activated q DocID025977 Rev 4 73 231 y ed 2 6 20 Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS_AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PAO TIM2 CH1 TIM5 CH1 TIM8 ETR USART2 CTS PA1 TIM2 CH2 TIM5 CH2 EE PA2 TIM2 CH3 TIM5 CH3 USART2 TX PA3 TIM2 4 TIM5 CH4 USART2 RX PA4 SPI1 NSS SPI3 NSS USART2 CK PA5 TIM2 CH1 TIM2 ETR TIM8 CH1N SPI1 SCK PA6 TIM1 BKIN TIM3 CH1 TIM8 SPI1 MISO USART3 CTS PA7 TIM1 CH1N TIM3 CH2 TIM8 CH1N SPI1 MOSI Port A PA8 MCO TIM1 CH1 USART1 CK PA9 TIM1 CH2 USART1 TX PA10 TIM1 CH3 USART1 RX PA11 TIM1 4 TIM1 BKIN2 USART1 CTS PA12 TIM1 ETR USAR TO DE PA13 JTMS SWDIO IR_OUT PA14 JTCK SWCLK PA15 JTDI TIM2 CH1 TIM2 ETR SPI1 NSS SPI3 NSS uonduosep uid pue sjnouid 987 1ZEINLS y ed 2 6 20 LEc Gl Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port T
96. pF RL gt 5 71 2 i dece 1 kHz BW 500 kHz SNR Signal to noise dB ratio DAC output buffer OFF CL s 50 pF no RL 1 kHz 71 6 BW 500 kHz DAC output buffer ON _ 78 _ Total harmonic CL lt 50 pF RL 2 5 1 kHz THD dB distortion DAC output buffer OFF _ _ CL lt 50 pF RL 1 kHz DAC output buffer 70 4 Signal to noise CL lt 50 pF RL gt 5 1 kHz I i I SINAD and distortion dB ratio DAC output buffer OFF _ 71 _ CL s 50 pF RL 1 kHz DAC output buffer ON _ 414 _ Effective CL s 50 pF RL 2 5 kO 1 kHz ENOB bits number of bits DAC output buffer OFF _ _ CL lt 50 pF no RL 1 kHz a fF WON gt q Guaranteed by design Difference between two consecutive codes 1 LSB Difference between the value measured at Code 0x001 and the ideal value DocID025977 Rev 4 Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095 Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and OxFFF when buffer is OFF and from code giving 0 2 V and Vggr 0 2 V when buffer is ON 167 231 Electrical characteristics STM32L486xx 6 3 19 Voltage reference buffer characteristics Table 71 VREFBUF characteristics Symbol Parameter Conditions Min Typ Max Unit 0 2 4 3 6
97. resistance in C W e is the sum of PiNr max and max Pp max Pint e is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pio Max represents the maximum power dissipation on output pins where Pio max gt Voi loi gt Vppiox taking into account the actual Vo 16 and Vor lop of the I Os at low and high level in the application Table 111 Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient 45 LQFP64 10 x 10 mm 0 5 mm pitch Thermal resistance junction ambient 42 LQFP100 14 x 14mm Thermal resistance junction ambient 2 Osa LQFP144 20 x 20 mm ue Thermal resistance junction ambient 55 UFBGA132 7 x 7 mm Thermal resistance junction ambient 46 WLCSP72 Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the ordering information scheme shown in Section 8 Part numbering Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature DoclD025977 Rev 4 225 231 Package information STM32L486xx Note 226 231
98. used to convert digital signals into analog voltage signal outputs The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration This digital interface supports the following features e Upto two DAC output channels e 8 bitor 12 bit output mode e Buffer offset calibration factory and user trimming e Leftor right data alignment 12 bit mode Synchronized update capability q DocID025977 Rev 4 STM32L486xx Functional overview 3 17 3 18 q e Noise wave generation e Triangular wave generation e Dual DAC channel independent or simultaneous conversions e DMA capability for each channel e External triggers for conversion e Sample and hold low power mode with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels Voltage reference buffer VREFBUF The STM32L486xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs DACs and also as voltage reference for external components through the VREF pin The internal voltage reference buffer supports two voltages e 2 048V 25V An external voltage reference can be provided through the VREF pin when the internal voltage reference buffer is off The VREF pin is double bonded with VDDA on some packages In these packages the internal voltage reference buffer is not available
99. when VppA gt 2 4 V No oversampling q 162 231 DocID025977 Rev 4 STM32L486xx Electrical characteristics Figure 24 ADC accuracy characteristics 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Et Total Unajusted Error maximum deviation between the actual and ideal transfer curves Eo Offset Error maximum deviation between the first actual transition and the first ideal one Ec Gain Error deviation between the last ideal transition and the last actual one Differential Linearity Error maximum deviation between actual steps and the ideal ones EL 7 Integral Linearity Error maximum deviation between any actual transition and the end point correlation line VDDA 4093 4094 4095 4096 MS19880V2 Figure 25 Typical connection diagram using the ADC Sample and hold ADC converter AINx 12 bit converter C arasiti Can parasitic 2 MS33900V3 1 Refer to Table 63 ADC characteristics for the values of Rain and CApc 2 represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high Cyarasitic value will downgrade conversion accuracy To remedy this fapc should be reduced General PCB design guidelines Power supply decoupling should be performed as shown in Figure 12 Power
100. 0 0000 e FMC bank 3 0x4000 0000 D Ox1FFF F810 FMC bank 1 amp Option Bytes 3 bank 2 Ox1FFF F800 Ox1FFF F000 System memory Ox1FFF 8000 Ox1FFF 7810 Options Bytes Ox1FFF 7800 Ox1FFF 7400 Ox1FFF 7000 System memory Ox1FFF 0000 0x1000 8000 0x1000 0000 0x0810 0000 Flash memory 0x0800 0000 0x0010 0000 Flash system memory or SRAM depending on Reserved 0x0000 0000 BOOT configuration 0 000 0000 0 4800 0000 0xA000 0000 0x6000 0000 Peripherals reme LL 0x4000 0000 SRAM1 0x2000 0000 CODE 0x0000 0000 MS34100V3 q DocID025977 Rev 4 89 231 Memory mapping STM32L486xx 90 231 Table 18 STM32L486xx memory map and peripheral register boundary addresses Bus Boundary address iren Peripheral OxA000 1000 0xA000 13FF 1 KB QUADSPI OxA000 0000 0xA000 OFFF 4 FMC 0x5006 0800 0x5006 OBFF 1 KB RNG 0x5006 0400 0x5006 07FF 1 Reserved 0x5006 0000 0x5006 1 KB AES 0x5004 0400 0x5005 FFFF 127 KB Reserved 0 5004 0000 0x5004 1 KB ADC 0x5000 0000 0x5003 FFFF 16 KB OTG FS 0 4800 2000 Ox4FFF FFFF 127 Reserved AHB2 0x4800 1 00 0x4800 1FFF 1 KB GPIOH 0x4800 1800 0x4800 1BFF 1 KB GPIOG 0x4800 1400 0x4800 17FF 1 KB GPIOF 0x4800 1000 0x4800 13FF 1 KB GPIOE 0 4800 0 00 0x4800 OFFF 1 KB GPIOD 0x4800 0800 0x4800 OBFF 1
101. 0 180 12 5 156 25 820 560 24 5 306 25 1500 1200 10 bits 47 5 593 75 2200 1800 92 5 1156 25 5600 4700 247 5 3093 75 12000 10000 640 5 8006 75 47000 39000 2 5 31 25 180 N A 6 5 81 25 470 270 12 5 156 25 1000 680 24 5 306 25 1800 1500 8 bits 47 5 593 75 2700 2200 92 5 1156 25 6800 5600 247 5 3093 75 15000 12000 640 5 8006 75 50000 50000 q DocID025977 Rev 4 153 231 Electrical characteristics STM32L486xx Table 64 Maximum ADC RAIN 2 continued RAIN Sampling cycle Sampling time ns Resolution 80 MH 80 MH s Fast channels Slow channels 2 5 31 25 220 N A 6 5 81 25 560 330 12 5 156 25 1200 1000 24 5 306 25 2700 2200 6 bits 47 5 593 75 3900 3300 92 5 1156 25 8200 6800 247 5 3093 75 18000 15000 640 5 8006 75 50000 50000 Guaranteed by design 2 The I O analog switch voltage booster is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG_CFGR1 when Vppa lt 24V It is disable when gt 2 4 V 3 Fast channels are PCO PC1 PC2 PC3 PAO PA1 4 Slow channels are all ADC inputs except the fast channels 154 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 65 ADC accuracy limited test conditions 40000 Sym parameter bol Total ET unadjusted error EO Offset error EG Gain error Differential ED linearity error Inte
102. 1 1 Reduced code used for characterization results provided in Table 26 Table 27 Table 28 Ly DoclD025977 Rev 4 109 231 LEZ OLL y ed 2 6 20 Table 32 Current consumption in Sleep and Low power sleep modes Flash ON Conditions TYP MAX Symbol Parameter Voltage Unit eine 25 C 55 C 85 C 105 C 125 25 C 55 C 85 C 105 125 26 MHz 0 92 0 96 1 07 1 25 1 59 1 012 1 14 1 36 1 77 2 40 16 MHz 0 61 0 65 0 75 0 92 1 27 0 69 0 78 0 97 1 32 2 04 8 MHz 0 36 0 40 0 50 0 66 1 01 0 42 0 50 0 68 1 03 1 75 Range 2 4MHz 0 24 0 27 0 37 0 53 0 87 0 28 0 36 0 54 0 89 1 60 TCL up 2 MHz 0 18 0 20 0 30 0 47 0 81 0 215 0 29 0 46 0 82 1 53 Supply included bypass 1MHz 0 15 0 17 0 27 043 0 77 0 18 025 0 44 0 78 1 49 current in mode 100kHz 0 12 0 14 0 24 0 41 0 74 0 15 0 21 0 39 0 74 1 44 Ipp Sleep mA 2 4 80 MHz 2 96 3 00 3 43 3 33 3 73 326 343 372 4 13 4 97 mode za 72MHz 269 273 285 305 345 296 321 3 50 3 71 4 54 disable 64 MHz 241 245 2 58 277 3 17 2 65 2 88 3 17 3 58 4 21 Range 1 48 MHz 1 88 1 93 2 07 227 2 67 2 10 227 241 2 83 3 66 32MHz 1 30 1 35 148 1 68 2 08 1
103. 1 DAC characteristics 164 DAC accuracy susse gue ee es Pale ie Sor prese Md des us 166 VREFBUF 168 COMP 170 OPAMP characteristics 171 TS characteristics s 2 eR EUR Rx A IB OE RAS Rs 174 Veat monitoring characteristics 174 Vpar charging 174 LCD controller 175 DFSDM 177 TIMx characteristics 179 IWDG min max timeout period at 32 kHz 1 1 179 WWDG min max timeout value at 80 MHz 179 2 analog filter 180 SPI characteristics ke AER x Rue p e PR ad RR 181 Quad SPI characteristics in SDR 184 QUADSPI characteristics in DDR 185 SAI characteristics
104. 1 SRAM2 and register contents are lost except for registers in the Backup domain The device exits Shutdown mode when an external reset NRST pin a WKUP pin event configurable rising or falling edge or an RTC event occurs alarm periodic wakeup timestamp tamper The system clock after wakeup is MSI at 4 MHz q DocID025977 Rev 4 STM32L486xx Functional overview Table 5 Functionalities depending on the working mode Stop 0 1 Stop 2 Standby Shutdown Low Low 5 5 5 5 Sleep power power 8 8 8 8 VBAT run sleep 2 2 2 5 CPU Y Y Flash memory 2 2 2 2 _ _ _ p _ _ _ 1 MB SRAM1 96 KB Y y 3 Y Y v E SRAM2 32 KB Y YO Y YO I r F FSMC Quad SPI i Backup Registers Y Y Y Y Y Y Y Y Y Brown out reset BOR Y Y Y Y Y Y Y Y Y Y Programmable Voltage Detector O O O O O O O PVD Peripheral Voltage Monitor PVMx 1 2 3 4 DMA 2 High Speed Internal 5 5 _ _ _ _ HSI16 B 9 9 High Speed External HSE 2 2 9 E M RE BM Low Speed Internal LSI Low Speed External LSE
105. 1 USB OTG Yes FS SDMMC Yes SWPMI Yes Digital filters for sigma delta modulators Yes filters Number of channels 8 RTC Yes Tamper pins 3 2 2 LCD Yes Yes Yes Yes Yes COM x SEG 8x40 or 4x44 8x40 or 4x44 8x40 or 4x44 8x28 or 4x32 8x28 or 4x32 Random generator Yes AES Yes DoclD025977 Rev 4 13 231 Description STM32L486xx Table 2 STM32L486xx family device features and peripheral counts continued Operating temperature Packages LQFP144 Peripheral STM32L486Zx STM32L486Qx STM32L486Vx STM32L486Jx STM32L486Rx GPIOs 114 109 82 57 51 Wakeup pins 5 5 5 4 4 Nb of I Os down to 1 08 V 14 14 0 6 0 Capacitive sensing Number of channels zi is i 12 bit ADCs 3 3 3 3 3 Number of channels 24 19 16 16 16 12 bit DAC channels 2 Internal voltage reference Yes No buffer Analog comparator 2 Operational amplifiers 2 Max CPU frequency 80 MHz Operating voltage 1 71 to 3 6 V Ambient operating temperature 40 to 85 C 40 to 105 C 40 to 125 C Junction temperature 40 to 105 C 40 to 125 C 40 to 130 C UFBGA132 LQFP100 WLCSP72 LQFP64 1 Forthe LQFP100 package only FMC Bank1 is available Bank1 can only support a multiplexed NOR PSRAM memory using the NE1 Chip Select 14 231 DoclD025977 Rev 4 q STM32L486xx Description Figure 1 STM32L486xx block diagram NE 4 1 NL NBL 1 0
106. 1 2 Symbol Parameter Min Max Unit Tw NOE FMC NOE low width 4Tucuc 4Tucikt1 Tsu D NOE D 15 0 valid data before NOE high 16 TnoE p FMC D 15 0 valid data after FMC NOE high 6 ns Ta NCE NOE NCE valid before FMC NOE low 3THcLKt1 Th NOE ALE _ high to FMC_ALE invalid 2Tucuc2 CL 30 pF 2 Guaranteed by characterization results Table 103 Switching characteristics for NAND Flash write cycles 2 Symbol Parameter Min Max Unit Tw NWE FMC NWE low width 4 1 4 1 Tw NWE D NWE low to D 15 0 valid 2 5 Th NWE D NWE high to D 15 0 invalid 3Tucuc4 Ta D NWE D 15 0 valid before FMC_NWE high 5Tucuc3 NwE valid before NWE low 1 NWE high to invalid 2Tucuc2 1 CL 30 pF 2 Guaranteed by characterization results 208 231 DoclD025977 Rev 4 q STM32L486xx Package information 7 7 1 Ly Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark LQFP144 package information Figure 48 LQFP144 144 pin 20 x 20
107. 1 62 V 10 C 30 pF 2 7 lt lt 3 6 V 3 3 Tr Tf Output rise and fall time C 30 pF 1 62 lt lt 2 7 V 6 ns C 30 pF 1 08 lt lt 1 62 V 16 Fmax Maximum frequency 1 MHz Fm Output fall ime C 50 pF 1 6 lt lt 3 6 V a z 1 The I O speed is configured using the OSPEEDRy 1 0 bits The Fm mode is configured in the SYSCFG CFGRI1 register Refer to the RM0351 reference manual for a description of GPIO Port configuration register 148 231 Guaranteed by design This value represents the I O capability but the maximum system frequency is limited to 80 MHz DoclD025977 Rev 4 The fall time is defined between 7096 and 3096 of the output waveform accordingly to 2 specification q STM32L486xx Electrical characteristics Figure 22 I O AC characteristics definition 90 10 1 1 1 1 1 4 Maximum frequency is achieved if tr lt 2 3 T and if the duty cycle is 45 55 when loaded by the specified capacitance MS32132V2 1 Refer to Table 60 I O AC characteristics 6 3 15 NRST pin characteristics The NRST pin input driver uses the CMOS technology It is connected to a permanent pull up resistor Rpy Unless otherwise specified the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22 General o
108. 12 SWPMI1_IO SAI2 FS A TIM15 BKIN EVENTOUT LPUART1 PB13 cre 18061108 LCD SEG13 SWPMM TX SAI2 SCK A TIM15_CH1N EVENTOUT PB14 TSC G1 103 LCD_SEG14 SWPMI1_RX dr cae TIM15 CH1 EVENTOUT PB15 TSC G1 104 LCD SEG15 SWPMI1_SUSPEND SAI2 SD A TIM15 CH2 EVENTOUT uonduosep uid pue sjnouid XX987 1C IN LS y ed 2 6 20 152 58 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 UARTS CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC 2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PCO od N LCD SEG18 3 2 IN1 EVENTOUT PC1 LPUART4 TX LCD SEG19 EVENTOUT PC2 LCD_SEG20 EVENTOUT PC3 z LCD_VLCD F SAM SD A LPTIM2 ETR EVENTOUT PC4 LCD_SEG22 z EVENTOUT PC5 LCD SEG23 EVENTOUT PC6 TSC G4 101 LCD SEG24 SDMMC1 D6 EVENTOUT PC7 TSC G4 102 LCD_SEG25 SDMMC1_D7 USUS EVENTOUT PC8 TSC G4 103 LCD SEG26 SDMMC1_DO EVENTOUT Port TIM8 BKIN2 PC9 TSC G4 104 OTG FS LCD SEG27 SDMMC1_D1 SAI2 EXTCLK Coup EVENTOUT LCD PC10 UARTA TX TSC G3 102 LCD SEG28 5 1 02 SAI2 SCK B EVENTOUT LCD_SEG40 LCD_COMS PC11 UART4_RX TSC_G3_103 LCD SEG29 SDMMC1 D3 Mc EVENTOUT LCD
109. 16384 256 60r7 8 0 32768 1 The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty Table 81 WWDG min max timeout value at 80 MHz PCLK Prescaler WDGTB Min timeout value Max timeout value Unit 1 0 0 0512 3 2768 2 1 0 1024 6 5536 ms 4 2 0 2048 13 1072 8 3 0 4096 26 2144 DoclD025977 Rev 4 179 231 Electrical characteristics STM32L486xx 6 3 27 180 231 Communication interfaces characteristics interface characteristics I2C interface meets the timings requirements of the I C bus specification and user manual rev 03 for e Standard mode Sm with a bit rate up to 100 kbit s e Fast mode Fm with a bit rate up to 400 kbit s e Fast mode Plus Fm with a bit rate up to 1 Mbit s 2 timings requirements are guaranteed by design when the I2C peripheral is properly configured refer to RM0351 reference manual The SDA and SCL requirements are met with the following restrictions the SDA and SCL I O pins are not true open drain When configured as open drain the PMOS connected between the I O pin and Vppiox is disabled but is still present Only FT pins support Fm low level output current maximum requirement Refer to Section 6 3 14 I O port characteristics for the I2C I Os characteristics All I2C SDA and SCL I Os embed an a
110. 2 108 98 231 DoclD025977 Rev 4 Ky STM32L486xx Electrical characteristics Table 22 General operating conditions continued Symbol Parameter Conditions Min Max Unit Ambient temperature for the Maximum power dissipation 40 85 suffix 6 version Low power dissipation 40 105 Ambient temperature for the Maximum power dissipation 40 105 suffix 7 version Low power dissipation 40 125 Ambient temperature for the Maximum power dissipation 40 125 suffix 3 version Low power dissipation 40 130 Suffix 6 version 40 105 TJ Junction temperature range Suffix 7 version 40 125 Suffix 3 version 40 130 When RESET is released functionality is guaranteed down to Min 2 This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table Maximum I O input voltage is the smallest value between MIN Vpp Vppio2 Vicp 3 6 V 5 5V 3 For operation with voltage higher than Min Vpp VppA Vppio2 Vicp 0 3 V the internal Pull up and Pull Down resistors must be disabled 4 If T is lower higher Pp values are allowed as long as Ty does not exceed jm see Section 7 6 Thermal characteristics low power dissipation state Ta can be extended to this range as long as does not exceed jmax see Section 7 6 Thermal characteristics 6 3 2
111. 2 24 Rising edge 2 56 2 61 2 66 VBoR3 Brown out reset threshold 3 V Falling edge 2 47 2 52 2 57 Rising edge 2 85 2 90 2 95 VBOR4 Brown out reset threshold 4 V Falling edge 2 76 2 81 2 86 Programmable voltage Rising edge 2 1 2 15 2 19 y PVD0 detector threshold 0 Falling edge 2 2 05 2 1 Rising edge 2 26 2 31 2 36 Vpvp1 PVD threshold 1 V Falling edge 2 15 2 20 2 25 Rising edge 2 41 2 46 2 51 Vpvp2 PVD threshold 2 V Falling edge 2 31 2 36 2 41 Rising edge 2 56 2 61 2 66 Vpvp3 PVD threshold 3 V Falling edge 2 47 2 52 2 57 Rising edge 2 69 2 74 2 79 PVD threshold 4 V Falling edge 2 59 2 64 2 69 Rising edge 2 85 2 91 2 96 Vpyps PVD threshold 5 V Falling edge 2 75 2 81 2 86 Rising edge 2 92 2 98 3 04 VPype PVD threshold 6 V Falling edge 2 84 2 90 2 96 Hysteresis in continuous 20 Vnyst Hysteresis voltage of BORHO mode mV Hysteresis in _ 30 _ other mode Hysteresis voltage of BORH Vnyst BOR except BORHO and PVD T id lop BOR except BORO and _ _ i A BOR_PVD PVD consumption from Vpp i H V DDusg Peripheral voltage 1 18 122 126 V monitoring 100 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics q Table 24 Embedded reset and power control block characteristics continued Symbol Parameter Conditions Min Typ Max Unit Vppio2 peripheral voltage _ 2 monitoring 0 92 0 96 1 V VppA Peripheral volt
112. 204 Synchronous non multiplexed PSRAM write 5 206 Switching characteristics for Flash read 208 Switching characteristics for Flash write 208 LQFP144 144 pin 20 x 20 mm low profile quad flat package mechanical de Gad a ea ee 210 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package mechanical 4 213 UFBGA132 recommended PCB design rules 0 5 mm pitch 214 LQPF100 100 pin 14 x 14 mm low profile quad flat package mechanical 1 coins ue ee Pepa ea alt a EC 216 WLCSP72 72 ball 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical 4 219 WLCSP72 recommended PCB design rules 0 4 mm pitch 220 LQFP64 64 pin 10 x 10 mm low profile quad flat package mechanical 222 Package thermal 225 STM32L486xx ordering information scheme 228 Document revision history 229 q DocID025977 Rev 4 STM32L486xx List of figures List of figures
113. 22 General operating conditions All I Os are designed as CMOS and TTL compliant except BOOTO Table 58 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit input low level voltage except 1 62 lt lt 3 6 V 0 3xVppiox 2 BOOTO I O input low level voltage except 1 62 V lt Vppiox lt 3 6 V 0 39xVppjo 0 06 v BOOTO V I O input low level voltage except 1 08 V lt Vppiox lt 1 62 V 0 43xVppiox0 1 BOOTO BOOTO I O input low 3 level voltage 1 62 V Vpp Ox lt 3 6 V 0 17xVppiox I O input high level voltage except 1 62 V lt Vppiox lt 3 6 V 0 7xVppiox 2 BOOTO I O input high level voltage except 1 62 V lt Vppiox lt 3 6 0 49xVppioxt0 26 9 v BOOTO V I O input high level voltage except 1 08 V lt Vppiox lt 1 62 V 0 61xVppiox 0 05 9 I BOOTO BOOTO I O input 3 _ _ high level voltage 1 62 V Vpp ox 3 6 V 0 77xVppiox TT_xx FT_xxx and NRST input 1 62 V lt Vppiox lt 3 6 V 200 hysteresis 3 Vhys FT_sx 1 08 V lt Vppiox lt 1 62 V I 150 BOOTO I O input ydes 1 62 V lt Vppiox lt 3 6 V 200 Ly DoclD025977 Rev 4 143 231 Electrical characteristics STM32L486xx Table 58 I O static characteristics continued Symbol Parameter Conditions Min Typ Max Unit Vin lt 0 100 FT xx input leakage EE Nee E 650 X6 current ax Vppxxx 1 V lt
114. 25 C 55 C 85 C 105 C 125 C Unit mA Ae qw oc Guaranteed by characterization results unless otherwise specified LCD enabled with external voltage source Consumption from VLCD excluded Refer to LCD controller characteristics for cp Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors Wakeup with code execution from Flash Average value given for a typical wakeup time as specified in Table 41 Low power mode wakeup timings XX98T 1C IN LS sonsioj2eJeuo e21329 3 Table 36 Current consumption in Stop 0 mode Parameter Supply current in Stop 0 mode RTC disabled Conditions TYP 1 25 55 C 85 C 105 125 25 C 55 C 85 C 105 125 1 8 V 108 132 217 356 631 153 213 426 773 1461 24V 110 134 219 358 634 158 218 431 778 1468 3V 111 135 220 360 637 161 221 433 783 1476 3 6 V 113 137 222 363 642 166 226 438 791 1488 Unit 1 Guaranteed by characterization results unless otherwise specified 2 Guaranteed by test in production 9 Symbol Ipp Stop 0 Jg o Jg N e N 2 lt sonsiuoj2eJeuo e2129 3 XX987 1ZEINLS y ed 2 6 20 Table 37 Current
115. 25977 Rev 4 q STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions continued Pin Number Pin functions i 5 2 5 I Main E Alternate functions Additional reset gt Y 9 functions S S 5 9 amp 9 2 IR OUT TIM4_CH4 I2C1 SDA SPI2 NSS DFSDM CKIN6 62 E8 96 B3 140 PB9 VO FT fl CAN1 TX LCD COM3 SDMMC1 D5 SAI1 FS A TIM17 CH1 EVENTOUT TIM4_ETR LCD SEG36 97 C3 141 PEO VO 1 NBLO 16 1 EVENTOUT LCD SEG37 NBL1 98 A2 142 VO PES TIM17 CH1 EVENTOUT 63 A8 99 D3 143 VSS S 64 A9 100 4 144 VDD S 1 The speed should not exceed 2 MHz with a maximum load of 30 pF These GPIOs must not be used as current sources e g to drive an LED PC13 PC14 and PC15 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 in output mode is limited After a Backup domain power up PC13 PC14 and PC15 operate as GPIOs Their function then depends on the content of the RTC registers which are not reset by the system reset For details on how to manage these GPIOs refer to the Backup domain and RTC register descriptions in the RM0351 reference manual After reset these pins are configured as JTAG SW debug alternate functions and the
116. 3 6 V 40 MHz Voltage Range 1 Slave mode transmitter full duplex 2 7 lt Vpp lt 3 6 V 260 Voltage Range 1 Slave mode transmitter full duplex 1 71 lt lt 3 6 V 1602 Voltage Range 1 Voltage Range 2 13 1 08 lt lt 1 32 8 tsuNss NSS setup time Slave mode SPI prescaler 2 4 ns 53 NSS hold time Slave mode SPI prescaler 2 2 ns high and low time Master mode 2 2 ns tw SCKL tsu MI Master mode 3 5 Data input setup time ns tsu S Slave mode 3 thmi Master mode 6 5 Data input hold time ns thsi Slave mode 3 tasso Data output access time Slave mode 9 36 ns tasso Data output disable time Slave mode 9 16 ns DoclD025977 Rev 4 181 231 Electrical characteristics STM32L486xx Table 83 SPI characteristics continued Symbol Parameter Conditions Min Typ Max Unit Slave mode 2 7 lt Vpp lt 3 6 V Voltage Range 1 Slave mode 1 71 Vpp 3 6 V 450 Voltage Range 1 129 30 12 5 19 Data output valid time ns Slave mode 1 71 lt Vpp lt 3 6 V Voltage Range 2 12 5 33 Slave mode 1 08 lt Vppio2 lt 1 32 V9 25 62 5 tv MO Master mode 2 5 12 5 tn so Slave mode 9 Data output hold time Slave mode 1 08 lt gt lt 1 32 24 ns
117. 33 Resolution 6 bits 6 15 fapt SO Mie 5 33 MHz frRIG External trigger frequency Resolution 12 bits Resolution 12 bits 15 1 3 Conversion voltage _ _ VAIN range 2 0 VREF V RAIN External input impedance 50 kQ Internal sample and hold Canc capacitor 7 I 5 pr conversion Power up time 1 cycle fApc 80 MHz 1 45 us tcaL Calibration time 3 116 1 fapc CKMODE 00 1 5 2 2 5 Trigger conversion t latency Regular and CKMODE 01 i 2 0 LATR injected channels without CKMODE 10 _ _ 225 ADC conversion abort CKMODE 11 2 125 Ly DoclD025977 Rev 4 151 231 Electrical characteristics STM32L486xx Table 63 ADC characteristics 2 continued Symbol Parameter Conditions Min Typ Max Unit CKMODE 00 2 5 3 3 5 Trigger conversion t latency Injected channels CKMODE 01 7 7 3 0 LATRINJ aborting a regular CKMODE 10 E 3 25 ADC conversion CKMODE 11 3 125 fapc 80 MHz 0 03125 8 00625 Hs ts Sampling time 2 5 640 5 1 fapc ADC voltage regulator 20 ADCVREG 5 start up time E us fADC 80 MHz Resolution 12 bits edere I 51625 HS t Total conversion time CONV including sampling time ts 12 5 cycles for Resolution 12 bits successive approximation 1 15 to 653 fs 5 Msps 730 830 ADC consumption from Ippa ADC the supply fs 1 Msps 160 220 fs
118. 39 90 199 LCD enabled 169 443 159 368 817 35 11 40 92 204 Ipp Stop 2 id E 3 6V 1 86 465 167 385 855 37 12 42 96 214 a with RTC RTC enabled 16V 15 443 152 353 77 6 3 2 10 38 88 194 RTC clocked by LSE 24vy 1 63 433 156 36 796 34 11 39 90 199 5 bypassed at 2 32768HZ LCD disabled 1 79 455 16 1 37 81 8 36 11 40 93 205 3 6V 2 04 49 168 387 856 39 12 42 97 214 ol 3 RTC clocked by LSE 18V 143 399 147 35 3 2 10 37 88 2 quartz 24V 1 54 411 15 35 8 3 3 10 38 90 I low drive mode 1 67 4 29 155 367 3 4 11 39 92 36V 1 87 457 162 383 37 11 41 96 Wakeup clock is MSI 48 MHz voltage Range 1 3V 1 9 I I 5 Supply current Wakeup clock is Ipp wakeup during wakeup MSI 4 MHz _ _ _ _ from Stop2 from Stop 2 voltage Range 2 OVS uses mA mode See 5 Wakeup clock is HSI16 16 MHz voltage Range 1 2 4 j 7 I I See 9 q 1 Guaranteed by characterization results unless otherwise specified 987 1ZEINLS q y ed 2 6 20 LEC ELL e me Guaranteed by test in production LCD enabled with external voltage source Consumption from VLCD excluded Refer to LCD controller characteristics for ly cp Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6
119. 4 MHz 8 2 9 9 Range 2 Wakeup clock HSI16 16 MHz 7 3 9 3 Wakeup clock MSI 4 MHz 10 6 15 8 t S S us MOS Wakeup clock MSI 48 MHz 5 1 6 7 Range 1 A 4 Wake up time from Stop 2 Wakeup clock HSI16 16 MHz 5 7 8 mode to Run mode in Wakeup clock MSI 24 MHz 5 5 6 65 SEAMI Range 2 Wakeup clock HSI16 16 MHz 5 7 7 53 Wakeup clock MSI 4 MHz 8 2 16 6 Wakeup time from Standby Wakeup clock MSI 8 MHz 14 3 20 8 lWUSTBY mode to Run mode Render m Wakeup clock MSI 4 MHz 20 1 35 5 twusrev Wakeup time from Standby Wakeup clock MSI 8 MHz 14 3 24 3 p sRAM2 With SRAM2 to Run mode Wakeup clock MSI 4 MHz 20 1 38 5 Wakeup time from twusHpn Shutdown mode to Run Range 1 Wakeup clock MSI 4 MHz 256 330 6 ys mode 1 Guaranteed by characterization results 126 231 DoclD025977 Rev 4 Ly STM32L486xx Electrical characteristics Table 42 Regulator modes transition times Symbol Parameter Conditions Typ Max Unit Wakeup time from Low power run mode to tWULPRUN Run mode 2 Code run with MSI 2 MHz 5 7 Hs Regulator transition time from Range 2 to tvosT Range 1 or Range 1 to Range 23 Code run with MSI 24 MHz 20 40 1 Guaranteed by characterization results 2 Time until REGLPF flag is cleared in PWR_SR2 3 Time until VOSF flag is cleared in PWR_SR2 6 3 7 External clock source characteristics High speed external user clock generated from an exter
120. 42 264 775 2147 155 106 660 1938 5368 36V 10 58 323 919 2488 258 144 808 2298 6220 18V 183 201 367 729 E 5 P RTC enabled and 24V 268 295 486 901 P P 2 clocked by LSE bypassed at 32768 Hz 3V 376 412 602 1075 d 7 u u 7 3 6V 508 558 752 1299 z 18V 302 344 521 915 1978 2 E enabled and 24V 388 436 639 1091 2289 s clocked by LSE quartz ibl 3V 494 549 784 1301 2656 z z E 3 6V 630 692 971 1571 3115 z Unit nA 1 Guaranteed by characterization results unless otherwise specified 2 Basedon characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors sonsiuoj2eJeuo e2129 3 XX987 1ZEINLS STM32L486xx Electrical characteristics Caution q system current consumption The current consumption of the I O system has two components static and dynamic I O static current consumption All the I Os used as inputs with pull up generate current consumption when the pin is externally held low The value of this current consumption can be simply computed by using the pull up pull down resistors values given in Table 58 I O static characteristics For the output pins any external pull down or external load must also be considered to estimate the current consumption
121. 486xx 7 5 222 231 LQFP64 package information Figure 60 LQFP64 64 pin 10 x 10 mm low profile quad flat package outline SEATING PLANE 0 25 mm GAUGE PLANE K L1 PIN IDENTIFICATION 5W ME V3 1 Drawing is not to scale Table 110 LQFP64 64 pin 10 x 10 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 12 000 0 4724 D1 10 000 0 3937 D3 7 500 0 2953 E 12 000 0 4724 E1 10 000 0 3937 DoclD025977 Rev 4 STM32L486xx Package information Table 110 LQFP64 64 pin 10 x 10 mm low profile quad flat package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max E3 7 500 I I 0 2953 I 0 500 I 0 0197 K 0 3 5 7 0 3 5 7 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 61 LQFP64 64 pin 10 x 10 mm low profile quad flat package recommended footprint 1
122. 486xx Functional overview 3 15 3 15 1 q Analog to digital converter ADC The device embeds 3 successive approximation analog to digital converters with the following features 12 bit native resolution with built in calibration e 5 33 Msps maximum conversion rate with full resolution Down to 18 75 ns sampling time Increased conversion rate for lower resolution up to 8 88 for 6 bit resolution Up to 24 external channels some of them shared between ADC1 and ADC2 1 ADC2 and ADC3 e 5lnternal channels internal reference voltage temperature sensor VBAT 3 DAC1 and DAC2 outputs e One external reference pin is available on some package allowing the input voltage range to be independent from the power supply e Single ended and differential mode inputs e Low power design Capable of low current operation at low conversion rate consumption decreases linearly with speed Dual clock domain architecture ADC speed independent from CPU frequency e Highly versatile digital interface Single shot or continuous discontinuous sequencer based scan mode 2 groups of analog signals conversions can be programmed to differentiate background and high priority real time conversions Handles two ADC converters for dual mode operation simultaneous or interleaved sampling modes Each ADC support multiple trigger inputs for synchronization with on chip timers and external sign
123. 5 duty cycle t Input clock SPI mode SITP 1 0 7 01 PASEN high and low External clock mode 2 0 5 Toxin 2 W CKIN time SPICKSEL 1 0 0 Data input SPI mode SITP 1 0 01 tsu Satu lima External clock mode 0 P SPICKSEL 1 0 0 ns Data input SPI mode SITP 1 0 01 tn hold time External clock mode 2 SPICKSEL 1 0 0 Manchester Manchester mode SITP 1 0 CKOUT T data period 10 or 11 DIV 1 _ 2x CKOUTDIV Manchester recovered Internal clock mode T i x TDFSDMCLK clock period SPICKSEL 1 0 z 0 DFSDMGEK 1 Data based on characterization results not tested in production DoclD025977 Rev 4 177 231 Electrical characteristics STM32L486xx 6 3 26 178 231 Figure 16 DFSDM timing diagram dus dtes h a 2 i AN FHKE QZ SPICKSEL 0 ux ji SN MEME boe d Sa gt lt I z a a a 1 E I l 2 I D 9 G gt lt 2 1 AN LN E SPICKSEL 1 Tf VT VI NT amp lt s i j 75 IM MES MORE IC tsu th gt a Yn a E su th gt lt _ lt gt pA X X X b gt lt MES B E SITP 3 No XS a 8 lt S Recovered clock
124. 50 670 IppA DAC consumption from DAC output No load middle _ _ d DDA buffer OFF code 0x800 315 x 670 x Sample and hold mode Ton Ton Ton Ton 100 nF Toff Toff 4 4 No load middle 185 240 DAC output code 0x800 buffer ON No load worst code OxF1C 340 400 DAC output No load middle buffer OFF code 0x800 I ae Ippv DAC consumption from 185 400 UA REP Sample and hold mode buffer ON _ Ton Ton Ton Ton 100 nF worst case Toff Toff 4 4 155 x 205 x Sample and hold mode buffer OFF Ton Ton Ton Ton 100 nF worst case Toff Toff 4 4 1 Guaranteed by design 2 buffered mode the output can overshoot above the final value for low input code starting from min value Ly DoclD025977 Rev 4 165 231 Electrical characteristics STM32L486xx 3 Refer to Table 58 I O static characteristics 4 is the Refresh phase duration Toff is the Hold phase duration Refer to RM0351 reference manual for more details Figure 26 12 bit buffered non buffered DAC Buffered non buffered DAC 12 bit digital to analog converter ai17157d 1 The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier The buffer can be bypassed by configuring the BOFFx bit in the DAC CR register Table 70 DAC accuracy
125. 500 300 200 100 0 Pp mW 65 75 85 95 105 115 125 135 e Suffix 6 Suffix 7 MSv32143V1 DoclD025977 Rev 4 227 231 Part numbering STM32L486xx 8 228 231 Part numbering Table 112 STM32L486xx ordering information scheme R G T 6 TR Example STM32 1 Device family STM32 ARM based 32 bit microcontroller Product type L ultra low power Device subfamily 486 STM32L486xx Pin count R 64 pins J 72 pins V 100 pins Q 132 pins Z 144 pins Flash memory size G 1 MB of Flash memory Package T LQFP ECOPACK 2 UFBGA ECOPACK 2 Y CSP ECOPACK 2 Temperature range 6 Industrial temperature range 40 to 85 C 105 C junction 7 Industrial temperature range 40 to 105 C 125 C junction 3 Industrial temperature range 40 to 125 C 130 C junction Packing TR tape and reel XXx programmed parts DoclD025977 Rev 4 q STM32L486xx Revision history 9 Revision history Table 113 Document revision history Date 29 May 2015 Revision 1 Changes Initial release 12 Jun 2015 2 Updated Table 15 STM32L486xx pin definitions and Table 72 COMP characteristics 18 Sep 2015 Changed alternate function pin name SWDAT into SWDIO in all the document Updated Section 3 9 1
126. 62 lt lt 2 7 V 10 Fmax Maximum frequency I MHz C 10 pF 2 7 lt lt 3 6 V 50 C 10 pF 1 62 VXVppjoX2 7 V 15 C 10 pF 1 08 lt lt 1 62 V 1 21 C 50 pF 2 7 lt lt 3 6 V 9 C 50 pF 1 62 lt lt 2 7 V 16 Tr Tf Output rise and fall time I i ns C 10 pF 2 7 VSVppjoxS3 6 V 4 5 C 10 pF 1 62 lt 52 7 V 9 C 10 pF 1 08 VSVppio 1 62 V 21 Ly DoclD025977 Rev 4 147 231 Electrical characteristics STM32L486xx Table 60 I O AC characteristics continued Speed Symbol Parameter Conditions Min Max Unit C 50 pF 2 7 VSVppioxS3 6 V 50 C 50 pF 1 62 lt lt 2 7 V 25 Fmax Maximum frequency 5 2 C 10 pF 2 7 lt lt 3 6 V 100 9 C 10 pF 1 62 lt lt 2 7 V 37 5 C 10 pF 1 08 lt lt 1 62 V 5 10 C 50 pF 2 7 VSVppioxS3 6 V 5 8 C 50 pF 1 62 lt lt 2 7 V 11 Tr Tf Output rise and fall time ns C 10 pF 2 7 VSVppio 3 6 V 2 5 C 10 pF 1 62 lt lt 2 7 V 5 C 10 pF 1 08 lt lt 1 62 V 12 C 30 pF 2 7 VsVppjo 33 6 V 120 C 30 pF 1 62 VSVppioxS2 7 V 50 Fmax Maximum frequency MHz C710 pF 2 7 lt 53 6 V 180 11 C 10 pF 1 62 lt lt 2 7 V 75 C 10 pF 1 08 lt lt
127. 7 Current consumption in Run and Low power run modes code with data processing running from Flash ART disable Conditions TYP MAX Symbol Parameter Voltaqe Unit Scio fucuk 25 C 55 85 C 105 125 25 55 C 85 C 105 125 26 MHz 3 15 3 19 3 31 3 50 3 85 347 3 70 3 84 426 4 88 16 MHz 2 24 228 239 2 57 2 90 246 2 60 2 74 3 16 3 78 8MHz 1 26 1 29 1 40 1 57 1 89 1 40 1 50 1 64 2 06 2 68 Range2 4 MHz 0 71 0 75 0 85 1 02 1 34 0 79 0 88 1 06 1 38 2 21 Cn 2MHz 0 42 045 0 55 072 1 04 0 46 0 55 0 73 1 09 1 88 HCLK HSE Supo 48M Hz included 1MHz 0 27 0 30 0 40 0 57 0 89 0 30 0 38 0 57 0 90 1 61 PPY bypass mode 100 kHz 0 14 0 17 0 27 043 0 75 0 17 0 22 0 40 0 74 144 Ipp Run current in PLL ON ab mA Run mode ove 80 MHz 10 0 10 1 10 3 10 6 11 0 11 00 11 35 11 64 12 26 13 10 za 72 9 06 9 13 9 28 9 51 9 92 9 97 10 36 10 65 11 06 11 69 64 MHz 8 96 904 922 948 992 9 86 10 25 10 54 10 95 11 79 Range 1 48 MHz 7 64 772 7 91 8 17 862 840 876 8 90 9 52 10 36 32 MHz 5 49 5 57 574 598 640 6 04 640 6 69 7 10 7 94 24 MHz 4 16 4 22 4 36 4 57 4 96 4 60 4 86 5 15 5 56 6 19 16 MHz 2 93
128. 8 LSB 14 2 75 1 LSB 2 LSB 4 LSB 8 LSB Normal mode DAC output buffer 2 25 OFF 1LSB CL 10 pF Wakeup time from off state Normal mode DAC output buffer ON _ 42 75 setting the ENx bit in the CL lt 50 pF RL 2 5 s DAC Control register until Normal mode DAC output buffer i final value 1 LSB OFF CL lt 10 pF E 2 5 PSRR Vppa supply rejection ratio Leer HL OS oom M S 80 28 dB 164 231 00 10025977 Rev 4 STM32L486xx Electrical characteristics Table 69 DAC characteristics continued Symbol Parameter Conditions Min Typ Max Unit DAC output buffer _ 07 35 DAC OUT 100 nF eer ms Sampling time in sample pin connected DAC output buffer and hold mode code OFF 100 nF 10 5 18 transition between the he teAMP lowest input code and the OUT highest input code when pin not DACOUT reaches final connected DAC output buffer _ 2 35 value 1LSB internal OFF connection only Sample and hold mode 3 lleak Output leakage current DAC OUT pin connected nA Clint Internal sample and hold _ 52 7 88 oF capacitor tTRIM m SOUS Os tin DAC output buffer ON 50 Hs Middle code offsetfor1 VREF 3 6 V 1500 Voffset tri de st uv rim code step Vrer 1 8 V 750 No load middle 315 500 DAC output code 0x800 buffer ON No load worst code OxF1C 4
129. 8 pF loading capacitors Wakeup with code execution from Flash Average value given for a typical wakeup time as specified in Table 41 Low power mode wakeup timings XX98T 1C IN LS sonsioj2eJeuo e21329 3 y ed 2 6 20 Table 35 Current consumption in Stop 1 mode Conditions TYP 1 Symbol Parameter Unit I 25 C 55 85 C 105 C 125 25 C 55 C 85 C 105 C 125 18V 6 59 247 927 208 437 16 62 2322 520 1093 LCD 24V 6 65 248 929 209 439 17 62 232 523 1098 i disabled Simplement isable 6 65 249 933 210 442 17 62 233 525 1105 in Stop 1 36V 6 70 25 1 938 212 447 17 63 235 530 1118 Stop 1 d mode LCD 18V 7 00 25 2 972 219 461 18 63 243 548 1153 RTC disabled enabled2 24V 7 14 254 975 220 463 18 64 244 550 1158 clocked by 7 24 25 7 97 7 221 465 18 64 244 553 1163 LSI 36V 7 36 26 1 98 7 223 471 18 65 247 558 1178 18V 6 88 25 0 93 1 209 439 17 63 233 523 1098 LCD 24V 7 02 25 2 937 210 441 18 63 234 525 1103 disabled 7 12 25 4 942 212 444 18 64 236 530 1110 RTC clocked by 3 6V 7 25 25 7 95 2 214 449 18 64 238 535 1123 LSI 18V 7 01 26 1 990 223
130. Alternate functions Badio na reset gt v 9 functions 9 959 amp 2 COMP1 INP USART3 RX ro 25 J6 34 L5 45 PC5 VO FT la LCD SEG23 EVENTOUT ADC12_IN14 WKUP5 TIM1_CH2N TIM3 CH3 26 J5 35 M5 46 PBO VO TT la P VOUT QUADSPI BK1 101 ADC12 IN15 LCD SEG5 COMP1 OUT EVENTOUT TIM1_CH3N 4 8 DFSDM DATINO 27 J4 36 M6 47 PB1 VO FT_la USART3_RTS_DE pb ue QUADSPI BK1 100 LCD 6 LPTIM2_IN1 EVENTOUT RTC OUT LPTIM1 OUT I2C3 SMBA 28 J3 37 L6 48 PB2 FT a DFSDM CKINO COMP1 INP EVENTOUT K6 49 PF11 EVENTOUT J7 50 PF12 FMC A6 EVENTOUT 51 VSS S 52 VDD S DFSDM DATING K7 53 PF13 FMC A7 EVENTOUT DFSDM_CKIN6 J8 54 PF14 TSC G8 01 A8 EVENTOUT TSC G8 102 A9 J9 55 PF15 EVENTOUT TSC G8 A10 H9 56 PGO EVENTOUT TSC G8 104 A11 G9 57 PG1 EVENTOUT TIM1 ETR DFSDM DATIN2 38 M7 58 PE7 FMC_D4 SAM SD EVENTOUT 64 231 00 10025977 Rev 4 Ky STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions continued Pin Number Pin functions Pin name 32 function after reset Additional Alternate functions I functions LQFP64 WLCSP72 LQFP100
131. CB design rules 0 5 mm pitch BGA Dimension Recommended values Pitch 0 5 mm Dpad 0 280 mm 0 370 typ depends the soldermask registration tolerance Stencil opening 0 280 mm Stencil thickness Between 0 100 mm and 0 125 mm Pad trace width 0 100 mm Ball diameter 0 280 mm 214 231 DoclD025977 Rev 4 STM32L486xx Package information Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location Figure 53 UFBGA132 marking package top view Product identification Date code Ball A1 indentifier 25 Revision code MSv36852V3 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity q DocID025977 Rev 4 215 231 Package information STM32L486xx 7 3 216 231 LQFP100 package information Figure 54 LQFP100 100 pin 14 x 14 mm low profile quad flat package outline SEATING PLANE IDENTIFICATION 0 25 mm GAU
132. Conditions Class Mmm Unit value T TA 25 C conforming Vail D to ANSI ESDA JEDEC 2 2000 voltage human body model JS 001 V Electrostatic discharge TA 25 C VEsp cpM Voltage charge device conforming to ANSI ESD 250 model STM5 3 1 1 Guaranteed by characterization results DoclD025977 Rev 4 141 231 Electrical characteristics STM32L486xx 6 3 13 142 231 Static latch up Two complementary static tests are required on six parts to assess the latch up performance A Supply overvoltage is applied to each power supply pin e A current injection is applied to each input output and configurable pin These tests are compliant with EIA JESD 78A IC latch up standard Table 56 Electrical sensitivities Symbol Parameter Conditions Class LU Static latch up class 105 C conforming to JESD78A II level AM 1 Negative injection is limited to 30 mA for PFO PF1 PG6 PG7 PG8 PG12 PG13 PG14 current injection characteristics As a general rule current injection to the I O pins due to external voltage below Vss or above Vppiox for standard 3 3 V capable I O pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional suscept
133. DMA debug and CPU data read write and erase are strictly prohibited One area per bank can be selected with 64 bit granularity An additional option bit PCROP RDP allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0 DoclD025977 Rev 4 17 231 Functional overview STM32L486xx 3 5 3 6 18 231 The whole non volatile memory embeds the error correction code ECC feature supporting e single error detection and correction e double error detection e The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L486xx devices feature 128 Kbyte of embedded SRAM This SRAM is split into two blocks e 96 Kbyte mapped at address 0x2000 0000 SRAM1 e 32 Kbyte located at address 0x1000 0000 with hardware parity check SRAM2 This block is accessed through the ICode DCode buses for maximum performance These 32 Kbyte SRAM can also be retained in Standby mode The SRAM2 can be write protected with 1 Kbyte granularity The memory can be accessed in read write at CPU clock speed with 0 wait states Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas Each illegal access generates a reset which kills immediately the detected intrusion The Firewall main features are the following e Three segments be protected and defined thanks to
134. FF 1 KB FIREWALL 0x4001 0800 0x4001 1BFF 5 KB Reserved 0x4001 0400 0x4001 07FF 1 KB EXTI 0 4001 0200 0x4001 O3FF COMP 0x4001 0030 0x4001 1 KB VREFBUF 0x4001 0000 0x4001 002F SYSCFG DoclD025977 Rev 4 91 231 Memory mapping STM32L486xx 92 231 Table 18 STM32L486xx memory map and peripheral register boundary addresses continued Bus APB1 Boundary address 0x4000 9800 0x4000 FFFF 26 KB Reserved 0x4000 9400 0x4000 97FF 1 KB LPTIM2 0x4000 8 00 0x4000 93FF 2KB Reserved 0x4000 8800 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 0x4000 87FF 1 Reserved 0x4000 8000 0x4000 83FF 1 KB LPUART1 0x4000 7 00 0x4000 7FFF 1 KB LPTIM1 0x4000 7800 0x4000 7BFF 1 KB OPAMP 0x4000 7400 0x4000 77FF 1 KB DAC 0x4000 7000 0x4000 73FF 1 KB PWR 0x4000 6800 0x4000 6FFF 1 KB Reserved 0x4000 6400 0x4000 67FF 1 KB CAN1 0x4000 6000 0x4000 63FF 1 KB Reserved 0x4000 5C00 0x4000 5FFF 1 I2C3 0x4000 5800 0x4000 5BFF 1 KB I2C2 0x4000 5400 0x4000 57FF 1 KB I2C1 0x4000 5000 0x4000 53FF 1 KB UART5 0x4000 4 00 0x4000 4FFF 1 KB UART4 DoclD025977 Rev 4 q STM32L486xx Memory mapping Table 18 STM32L486xx memory map and peripheral register boundary addresses continued Bus Boundary address 0x4000 4800 0
135. FS DP EVENTOUT PA13 OTG_FS_NOE E EVENTOUT PA14 EVENTOUT PA15 Mn TSC G3 101 LCD SEG17 SAI2_FS_B EVENTOUT XX987 1ZEINLS uonduosep uid pue sjnouid 12 28 y ed 2 6 20 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PBO i QUADSPI BK1 101 LCD_SEG5 COMP1 OUT 2 EVENTOUT PB1 QUADSPI BK1 100 LCD SEG6 LPTIM2 IN1 EVENTOUT PB2 EVENTOUT PB3 LCD SEG SAM SCK B B EVENTOUT PB4 TSC G2 101 LCD SEG8 17 EVENTOUT PB5 UART5 CTS TSC G2 102 LCD_SEG9 COMP2 OUT SAM SD B TIM16 BKIN EVENTOUT PB6 gt TSC_G2_103 TIME SEI Ne SAM FS B TIM16 CH1N EVENTOUT COMP2 TIM8 BKIN 7 UARTA CTS TSC G2 104 LCD 5 21 FMC NL COMP4 17 1 EVENTOUT PortB PB8 CAN1 RX LCD SEG16 SDMMC1 D4 TIM16 CH1 EVENTOUT PB9 CAN1 TX LCD SDMMC1 D5 SAM FS A 17 CH1 EVENTOUT PB10 ik j QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A EVENTOUT PB11 LPUART1 TX i QUADSPI_NCS LCD_SEG11 COMP2_OUT EVENTOUT LPUART1 PBi2 ors pe 180201101 i LCD_SEG
136. FT fl Notes Pin functions Alternate functions TIM2 CH3 I2C2 SCL SPI2 SCK DFSDM DATINT USARTS3 TX LPUART1 RX QUADSPI CLK LCD SEG10 COMP1 OUT SAI1 SCK A EVENTOUT Additional functions 30 48 L11 70 PB11 1 0 FT fl TIM2 I2C2 SDA DFSDM CKINT USART3 RX LPUART1 TX QUADSPI NCS LCD 5 11 COMP2 OUT EVENTOUT 31 J2 49 F12 71 VSS 32 J1 33 H1 50 51 G12 L12 72 73 VDD PB12 VO TIM1_BKIN TIM1_BKIN_COMP2 I2C2 SMBA SPI2 55 DFSDM DATIN1 USART3 CK LPUART1 RTS DE TSC G1 101 LCD SEG12 SWPMI IO SAI2 FS A TIM15 BKIN EVENTOUT 34 H2 52 K12 74 PB13 1 0 FT fl TIM1 CH1N 2 2 SCL SPI2 SCK DFSDM 1 CTS LPUART1 CTS G1 102 LCD SEG13 SWPMI1 TX SAI2 SCK A TIM15 CH1N EVENTOUT 66 231 DoclD025977 Rev 4 q STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions continued Pin Number Pin functions Pin name 32 function after reset Additional Alternate functions I functions LQFP64 WLCSP72 LQFP100 UFBGA1 LQFP144 Pin type I O structure Notes TIM1_CH2N TIM8_CH2N I2C2 SDA SPI2_MISO DFSDM DATIN2 RTS DE 35 G2 53 K11 75 PB14 vO FTA TSC_G1_103 5 LCD SEG14 SWPMI1_RX SAI2 MCLK A TIM15 CH1 EVENTOU
137. GE PLANE 1L ME V5 1 Drawing is not to scale Table 107 LQPF100 100 pin 14 x 14 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 DoclD025977 Rev 4 q STM32L486xx Package information q Table 107 LQPF100 100 pin 14 x 14 mm low profile quad flat package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max D3 12 000 0 4724 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 4724 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 59 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 55 LQFP100 100 pin 14 x 14 mm low profile quad flat recommended footprint 75 51 oono C76 2550 0 5 cS Y O ca A co 0 3
138. I1CLK SYSCLK USART1 PLLUSB2CLK IR PLLADC1CLK MSI 48 MHz clock to USB RNG SDMMC PLLSAI2 SAM EXTCLK SAI2 EXTCLK gt SYSCLK to ADC Tpl PLLSAI2CLK to SAM PLLADC2CLK gt to SAI2 gt MS32440V2 34 231 DoclD025977 Rev 4 Ly STM32L486xx Functional overview 3 12 3 13 q General purpose inputs outputs GPIOs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared with digital or analog alternate functions Fast I O toggling can be achieved thanks to their mapping on the AHB2 bus The I Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I Os registers Direct memory access controller DMA The device embeds 2 DMAs Refer to Table 7 DMA implementation for the features implementation Direct memory access DMA is used in order to provide high speed data transfer between peripherals and memory as well as memory to memory Data can be quickly moved by DMA without any CPU actions This keeps CPU resources free for other operations The two DMA controller
139. IM1 TIM2 TIM1 TIM2 USART1 SYS AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PBO TIM1_CH2N TIM3_CH3 TIM8 CH2N USART3 CK PB1 TIM1 CH3N TIM3 4 TIM8 CH3N DFSDM DATINO Midi c PB2 RTC OUT LPTIM1 OUT I2C3 SMBA DFSDM CKINO JTDO USART1 _ TRACESWO TIM2 CH2 SPI1 SCK SPI3 SCK DE PB4 NJTRST TIM3 CH1 SPI1 MISO SPI3 MISO 1 CTS PB5 LPTIM1 IN1 TIM3 CH2 2 1 SMBA SPI1 MOSI SPI3 MOSI USART1 CK PB6 LPTIM1 ETR 4 1 TIM8 BKIN2 12 1 SCL DFSDM DATIN5 USART1 TX PB7 LPTIM1_IN2 TIM4_CH2 TIM8_BKIN 12C1_SDA DFSDM CKIN5 USART1_RX Port B PB8 4 CH3 2 1 SCL DFSDM DATING PB9 IR OUT TIM4_CH4 2 1 SDA SPI2 NSS DFSDM CKIN6 PB10 TIM2 CH3 2 2 SCL SPI2 SCK DFSDM DATIN7 USART3 TX PB11 TIM2 CH4 2 2 SDA DFSDM CKIN7 USART3 RX PB12 1 BKIN 1262 SMBA SPI2 NSS DFSDM_DATIN1 USART3 CK PB13 TIM1 CH1N 2 2 SCL SPI2 SCK DFSDM CKIN1 USART3 CTS PB14 TIM1 CH2N TIM8 CH2N 2 2 SDA SPI2 MISO DFSDM_DATIN2 i a PB15 RTC REFIN TIM1 CH3N TIM8 CH3N SPI2 MOSI DFSDM CKIN2 XX987 1ZEINLS uonduosep uid pue sjnouid 1556 94 y ed 2 6 20 Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USAR
140. IOx_LCKR register In order to save the full GPIOx current consumption the GPIOx clock should be disabled in the RCC when all port I Os are used in alternate function or analog mode clock is only required to read or write into GPIO registers and is not used in AF or analog modes The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1 4 The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2 6 3 6 Wakeup time from low power modes and voltage scaling transition times The wakeup times given in Table 41 are the latency between the event and the execution of the first user instruction The device goes in low power mode after the WFE Wait For Event instruction Table 41 Low power mode wakeup timings Symbol Parameter Conditions Typ Max Unit t Wakeup time from Sleep 6 6 WUSLEEP mode to Run mode Nb of CPU Wakeup time from Low Wakeup in Flash with Flash in power down during cycles twurPsLEEP Power sleep mode to Low low power sleep mode SLEEP PD 1 in 6 9 3 power run mode FLASH ACR and with clock MSI 2 MHz Wakeup clock MSI 48 MHz 5 6 10 9 Range 1 Wakeup clock HSI16 16 MHz 4 7 10 4 Wake up time from Stop 0 modeto Run mode in Flash Wakeup clock MSI 24 MHz 5 7 11 1 Range 2 Wakeup clock HSI16 16 MHz 4 5 10 5 Wakeup clock MSI 4 MHz 6 6 14 2 t us Wakeup clock MSI 48 MHz 0 7 2 05 Range
141. K ta CLKL NWEL FMC_CLK low to FMC_NWE low 2 taCLKH NWEH FMC_CLK high to FMC_NWE high 1 T tacLKL apv FMC CLK low to FMC_AD 15 0 valid 4 low to FMC_AD 15 0 invalid 0 taccLKL DaTay FMC_A D 15 0 valid data after FMC_CLK low 5 5 ta CLKL NBLL FMC_CLK low to FMC_NBL low 2 5 ta CLKH NBLH FMC_CLK high to FMC_NBL high 1 tsu NWAIT CLKH FMC_NWAIT valid before FMC_CLK high 0 FMC_NWAIT valid after FMC_CLK high 4 1 CL 30 pF 2 Guaranteed by characterization results DoclD025977 Rev 4 203 231 Electrical characteristics STM32L486xx Figure 42 Synchronous non multiplexed NOR PSRAM read timings tw CLK T4 5 tw CLK i i i a 1 1 1 1 1 1 a 1 1 1 1 1 t a 1 1 1 1 t z d CLKL NExL gt NEM NExH 1 1 1 1 _ 1 1 1 1 ta CLKL NADVL td CLKL NADVH i NADV i M id cUKL AV td CLKH AIV FMC_A 25 0 i 1 ta CLKL NOEL 1 _ D 15 0 NWAIT WAITCFG 1b WAITPOL 0b FMC_NWAIT WAITCFG 0b WAITPOL 0b MS32759V1 Table 100 Synchronous non multiplexed NOR PSRAM read timings Symbol Parameter Min Max Unit tw CLk FMC_CLK period 2THCLK ta CLKL NExL FMC_CLK low to FMC_NEx low x 0 2 2 5 ta CLKH NExH
142. NTOUT PG4 FMC A14 EVENTOUT PG5 _ 15 SAI2 SD B EVENTOUT LPUART1 PG6 RTS DE EVENTOUT LPUART1 TX FMC INT3 EVENTOUT Port G LPUART1_ _ EVENTOUT RX FMC NCE3 PG9 NE2 SAI2 SCK A TIM15_CH1N EVENTOUT PG10 FMC NE3 SAI2 FS A TIM15 CH1 EVENTOUT PG11 dir TIM15 CH2 EVENTOUT PG12 FMC_NE4 SAI2_SD_A EVENTOUT PG13 FMC_A24 EVENTOUT PG14 FMC_A25 EVENTOUT PG15 EVENTOUT XX987 1ZEINLS uonduosep uid pue sjnouid 12 88 y ed 2 6 20 Table 17 Alternate function AF8 to AF15 for to AF7 see Table 16 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 COMP1 TIM2 TIM15 UART5 1 5 OTG FS QUADSPI LCD 2 FMC SAI2 TIM16 17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PHO EVENTOUT Port H PH1 EVENTOUT uonduosep uid pue sjnouid XX987 1ZEINLS STM32L486xx Memory mapping 5 Memory mapping Figure 9 STM32L486 memory map TM Reserved 2 0xA000 1400 7 Internal QUADSPI registers 0 000 1000 Peripheral registers 0 000 0000 Ox5FFF FFFF 0x5006 0 00 AHB2 0x4002 4400 FMC and AHB1 5 QUADSPI 0x4002 0000 0x4001 6400 APB2 QUADSPI Flash 0x4001 0000 0x4000 9800 4 0 900
143. Range 7 18 5 25 Range 8 62 80 Range 9 85 110 Range 10 110 130 Range 11 155 190 Guaranteed by characterization results of MSI 948 MHz clock 5 Only accumulated jitter of MSI 48 MHz is extracted over 28 cycles For next transition min and max jitter of 2 consecutive frame of 28 cycles of the MSI 48 MHz for 1000 captures over 28 cycles This is a deviation for an individual part once the initial frequency has been measured Sampling mode means Low power run Low power sleep modes with Temperature sensor disable Average period of MSI 48 MHz is compared to a real 48 MHz clock over 28 cycles It includes frequency tolerance jitter For paired transitions min and max jitter of 2 consecutive frame of 56 cycles of the MSI 48 MHz for 1000 captures over 56 cycles 6 Guaranteed by design 136 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Figure 20 Typical current consumption versus MSI frequency uA Range 0 to 3 Range 4 to 7 Range 8 to 11 256 48MHz 8 16MHz 64 32 8MHz 16 8 1MHz 4 2 100KHz 800KHz 1 0 5 0 1 0 2 0 4 0 8 1 6 3 2 6 4 12 8 25 6 Freq MHz Low speed internal LSI RC oscillator Table 49 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 3 0 V 30 C 31 04 32 96 fi si LSI Frequency kHz Vpp 1 62 to 3 6 V 40 to 125
144. SE and the backup registers Three anti tamper detection pins are available in VBAT mode VBAT operation is automatically activated when Vpp is not present An internal VBAT battery charging circuit is embedded and can be activated when Vpp is present Note When the microcontroller is supplied from VBAT external interrupts and RTC alarm events do not exit it from VBAT operation q DocID025977 Rev 4 29 231 Functional overview STM32L486xx 3 10 Interconnect matrix Several peripherals have direct connections between them This allows autonomous communication between peripherals saving CPU resources thus power supply consumption In addition these hardware connections allow fast and predictable latency Depending on peripherals these interconnections can operate in Run Sleep low power run and sleep Stop 0 Stop 1 and Stop 2 modes Table 6 STM32L486xx peripherals interconnect matrix 30 231 DoclD025977 Rev 4 512 es sia 0 Interconnect source Interconnect Interconnect action 5 destination o 2 a 9 o TIMx Timers synchronization or chaining Y ADCx DACx Conversion triggers us DFSDM DMA Memory to memory transfer trigger Y Y Y Comparator output blanking Y Y Y TIM1 8 Timer input channel trigger break from y y ylyl TIM2 3 analog signals co
145. STM32L486xx Multi speed internal MSI RC oscillator Table 48 MSI oscillator characteristics Symbol fusi Atemp MSI Parameter MSI frequency after factory calibration done at Vpp 3 V and 30 C MSI oscillator frequency drift over temperature MSI mode PLL mode XTAL 32 768 kHz MSI mode Conditions Min Typ Max Unit Range 0 99 100 101 Range 1 198 200 202 kHz Range 2 396 400 404 Range 3 792 800 808 Range 4 0 99 1 1 01 Range 5 1 98 2 2 02 Range 6 3 96 4 4 04 Range 7 7 92 8 8 08 MHz Range 8 15 8 16 16 16 Range 9 23 8 24 24 4 Range 10 31 7 32 32 32 Range 11 47 5 48 48 48 Range 0 98 304 Range 1 196 608 kHz Range 2 393 216 Range 3 786 432 Range 4 1 016 Range 5 1 999 Range 6 3 998 Range 7 7 995 MHz Range 8 15 991 Range 9 23 986 Range 10 32 014 Range 11 48 005 0 to 85 C 3 5 3 40 to 125 C 8 6 134 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 48 MSI oscillator characteristics continued Symbol Parameter Conditions Min Typ Unit Vpp 1 62 V to 3 6 V 12 i Range 0 to 3 0 5 Vpp 224V gg _ to 3 6 V MSI oscillator Mono V 25 _ 3 Aypo Msiy2 freauency drit MSi m
146. SUPPIY bypass mode 100kHz 0 12 0 15 0 25 0 41 0 75 0 15 0 21 0 39 0 74 145 Ipp Run current in mA Run mod m 80MHz 10 2 10 3 10 5 10 7 11 1 11 22 11 57 11 86 12 07 13 11 za peripherals disable 72MHz 925 9 31 946 9 68 10 1 10 18 10 41 10 55 10 76 11 80 64 MHz 825 8 31 846 8 67 9 08 9 08 9 37 9 66 9 87 10 91 Range 1 48 MHz 6 26 6 33 6 48 6 69 7 11 6 89 7 11 7 25 7 67 8 50 32MHz 4 22 4 28 442 4 63 5 03 464 4 86 5 15 5 56 6 19 24MHz 3 20 3 25 3 38 3 59 3 99 3 52 3 70 3 84 426 5 09 16 MHz 2 18 2 22 2 35 2 55 2 94 240 2 55 2 84 325 4 09 2MHz 242 275 384 562 924 300 380 573 927 1677 Suppl fusi 1MHz 130 162 269 445 809 180 243 435 810 1560 Ipp LPRun all peripherals disable Maris FLASH in power down 400 kHz 61 90 197 374 734 95 160 353 728 1478 100kHz 26 56 163 339 702 55 122 314 679 1429 1 Guaranteed by characterization results unless otherwise specified 98 1C IN LS sonsioj2eJeuo e21329 3 Electrical characteristics STM32L486xx Table 29 Typical current consumption in Run and Low power run modes with different codes running from Flash ART enable Cache ON Prefetch OFF Symbol Ipp Run Ipp LPRun Par
147. Start up time in continuous mode 8 15 HS terARnT 7 Start up time when entering in continuous mode 70 120 us ts temp sampling time when reading the temperature 5 us Temperature sensor consumption from Vpp when 1 DD Ipo TS selected by ADC 4 HA Guaranteed by design 2 Guaranteed by characterization results Measured at Vppa 3 0 V 10 mV The ADC conversion result is stored in the TS_CAL1 byte Refer to Table 8 Temperature sensor calibration values 4 Continuous mode means Run Sleep modes or temperature sensor enable in Low power run Low power sleep modes 6 3 23 Vpar monitoring characteristics Table 75 monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for 39 kQ Q Ratio on Vgar measurement 3 Er Error on Q 10 10 ts veat ADC sampling time when reading the VBAT 12 us 1 Guaranteed by design Table 76 Vgar charging characteristics Symbol Parameter Conditions Min Typ Max Unit Battery VBRS 0 5 ag VBRS 1 5 15 5 is 174 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics 6 3 24 LCD controller characteristics The devices embed a built in step up converter to provide a constant LCD reference voltage independently from the Vpp voltage An external capacitor must be connected to the VLCD pin to
148. T REFIN TIM1_CH3N TIM8_CH3N SPI2 MOSI DFSDM CKIN2 TSC_G1_104 36 G1 54 K10 76 PB15 FT I LCD SEG15 SWPMI1 SUSPEND SAI2 SD A TIM15 CH2 EVENTOUT TX 55 K9 77 PD8 FT LCD SEG28 013 EVENTOUT USART3 RX LCD SEG29 FMC_D14 56 K8 78 PD9 VO FTI SAI2 MCLK I EVENTOUT USART3 CK TSC G6 101 57 12 79 PD10 VO FTI SEG30 SAI2_SCK_A EVENTOUT USART3 CTS TSC G6 102 58 441 80 PD11 VO LCD SEG31 FMC_A16 SAI2 SD A LPTIM2_ETR EVENTOUT TIM4 CHI USART3 RTS DE TSC G6 103 59 J10 81 PD12 VO FT cep sEG32 17 SAI2 FS A LPTIM2_IN1 EVENTOUT TIM4 CH2 TSC G6 104 60 H12 82 PD13 FT I LCD SEGS33 A18 LPTIM2 OUT EVENTOUT E qe 83 VSS e VDD s Ly DoclD025977 Rev 4 67 231 Pinouts and pin description STM32L486xx Table 15 STM32L486xx pin definitions continued Pin Number LQFP64 WLCSP72 LQFP100 32 UFBGA1 I LQFP144 function after reset PD14 Pin functions Alternate functions Pin type structure Notes TIM4 CH3 LCD SEG34 DO EVENTOUT Additional functions o N H10
149. T disable 106 Current consumption in Run and Low power run modes code with data processing running from SRAMT sues ene s ee eee RC RR Rn 107 Typical current consumption in Run and Low power run modes with different codes running from Flash ART enable Cache ON Prefetch OFF 108 Typical current consumption in Run and Low power run modes with different codes running from Flash ART disable 109 Typical current consumption in Run and Low power run modes with different codes running from 1 2 109 Current consumption in Sleep and Low power sleep modes Flash ON 110 Current consumption in Low power sleep modes Flash in power down 111 Current consumption in Stop 2 111 Current consumption in Stop 1 114 Current consumption in Stop 0 116 Current consumption in Standby mode 117 Current consumption in Shutdown 118 Current consumption VBAT mode 120 Peripheral current consumption 122 Low power mode wakeup timings
150. T1 SYS AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PCO LPTIM1_IN1 2 3 SCL DFSDM_DATIN4 PC1 LPTIM1_OUT 2 3 SDA DFSDM 4 PC2 LPTIM1 IN2 SPI2 MISO DFSDM_CKOUT PC3 LPTIM1 ETR SPI2 MOSI PC4 USART3_TX PC5 USART3_RX PC6 TIM3 CH1 TIM8 CH1 DFSDM PC7 TIM3 CH2 TIM8 CH2 DFSDM DATIN3 PC8 TIM3 CH3 TIM8 CH3 Port C PC9 TIM8 BKIN2 TIM3 CH4 TIM8 4 PC10 SPI3 SCK USART3 TX PC11 SPI3 MISO USART3 RX PC12 SPI3 MOSI USART3 CK PC13 PC14 PC15 uonduosep uid pue XX987 1ZEINLS y ed 2 6 20 186 11 Table 16 Alternate function AF0 to AF7 for AF8 to AF15 see Table 17 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port 2 TIM1 TIM2 USART1 SYS AF 5 8 TIM3 TIM4 TIM8 I2C1 I2C2 2C3 SPM SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PDO 2 2 SPI2 NSS DFSDM DATIN7 PD1 2 SPI2 SCK DFSDM CKIN7 PD2 TIM3 ETR ss DE PD3 SPI2 MISO DFSDM DATINO USART2 CTS PD4 I SPI2_MOSI DFSDM CKINO id c PD5 USART2 TX PD6 s DFSDM DATIN1 USART2 RX PotD PD7 2
151. TP at low common _ _ 0 8 1 1 TRIMLPOFFSETP voltage 0 1 x mV Offset trim step TRIMOFFSETN at high common _ _ 1 1 35 TRIMLPOFFSETN input voltage 0 9 x VppA i Normal mode y 5 500 rive current 2 FM Low power mode 100 pA Drive current in Normal mode Un 22 V 450 LOAD_PGA DDA PGA mode Low power mode 50 Resistive load Normal mode 4 connected to FLOAD VSSA or to Vopa lt 2 V VDDA Low power mode 20 kQ Resistive load in PGA mode Normal mode 4 5 PGA connected to VppA lt 2 V VSSA or to Low power mode 40 VppA CLOAD Capacitive load gt 50 pF CHRR Common mode Normal mode 85 di rejection ratio ow power mode 90 Ly DoclD025977 Rev 4 171 231 Electrical characteristics STM32L486xx Table 73 OPAMP characteristics continued Symbol Parameter Conditions Min Typ Max Unit Normal mode CLOAD 50 pf 70 85 PSRR Power supply Rioap 2 4 DC rejection ratio C lt 50 pf LOAD Low power mode RLoap gt 20 DC 72 90 Normal mode Vppa gt 2 4 V 550 1600 2200 Gain Bandwidth Low power mode RANGE 1 400 420 600 xus Product Normal mode 24 V 250 700 950 Low power mode RANGE 0 40 180 280 Normal mode 700 Slew rate
152. Table 34 Current consumption in Stop 2 mode Conditions TYP MAX Symbol Parameter Unit 25 55 C 85 105 125 C 25 C 55 C 85 C 105 C 125 C 18V 1 14 377 147 347 77 2 7 9 37 87 193 24V 115 386 15 355 79 1 27 10 38 89 198 LCD disabled 1 18 3 97 154 364 813 28 10 39 91 203 Supply current in 3 6V 126 411 16 38 851 30 10 40 952 213 Ipp Stop 2 Stop 2 mode disabled 18V 1 43 3 98 15 35 773 3 2 10 38 88 193 LCD enabled 2 24V 149 407 153 358 794 32 10 38 90 199 clocked by LSI 3V 1 54 424 157 367 816 3 3 11 39 92 204 36V 175 447 161 383 854 35 11 40 96 214 98 1C IN LS sonsioj2eJeuo e21329 3 sonsiuoj2eJeuo e2129 3 Table 34 Current consumption in Stop 2 mode continued N N Conditions TYP 1 Symbol Parameter Unit 25 55 C 85 C 105 125 25 C 55 C 85 C 105 C 125 C 18V 1 42 404 15 349 772 34 10 38 87 193 RTC clocked by LSI 24V 15 4 22 154 357 79 2 32 11 39 89 198 LCD disabled 3V 1 64 437 158 367 814 34 11 40 92 204 3 6V 179 465 166 384 854 36 12 42 96 214 18V 1 53 4 07 151 351 774 33 10 38 88 194 RTC clocked by LSI 24V 1 62 4 32 155 359 79 5 34 11
153. U is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks It is usually managed by an RTOS real time operating system If a program accesses a memory location that is prohibited by the MPU the RTOS can detect it and take action In an RTOS environment the kernel can dynamically update the MPU area setting based on the process to be executed The MPU is optional and can be bypassed for applications that do not need it q DocID025977 Rev 4 STM32L486xx Functional overview 3 4 q Embedded Flash memory STM32L486xx devices feature 1 Mbyte of embedded Flash memory available for storing programs and data The Flash memory is divided into two banks allowing read while write operations This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank The dual bank boot is also supported Each bank contains 256 pages of 2 Kbyte Flexible protections can be configured thanks to option bytes e Readout protection RDP to protect the whole
154. UF z OPAMPXx x 1 2 c f E COMPx 1 2 Temperature sensor O O O O Timers TIMx Low power timer 1 LPTIM1 Low power timer 2 LPTIM2 Independent watchdog IWDG 9 9 B o o Window watchdog WWDG E SysTick timer O 3 2 gt Touch sensing controller TSC o 9 o I i I d 7 7 Random number _ _ _ _ _ _ _ generator RNG 28 231 DocID025977 Rev 4 Ly STM32L486xx Functional overview Table 5 Functionalities depending on the working mode continued Stop 0 1 Stop 2 Standby Shutdown 2 2 2 2 E Low Low 5 5 8 8 Sleep power power 2 8 Q 8 VBAT run sleep 5 5 5 5 o o 5 5 5 5 s s s s AES hardware _ _ I _ I I accelerator CRC calculation _ _ _ I unit 5 GPIOs o pns pins 10 10 1 Legend Y Yes Enable O Optional Disable by default Can be enabled by software Not available 2 The Flash can be configured in power down mode By default it is not in power down mode 3 The SRAM clock can be gat
155. Vpp Supply voltage 1 62 3 6 V VBoosT Boost supply 2 7 4 tsu goosr Booster startup time 240 HS Booster consumption for 250 1 62 V lt Vpp S 20V Booster consumption for 500 DD BOOST 20 lt lt 2 7 I Booster consumption for 900 2 7 V lt Vpp S 3 6 V 1 Guaranteed by design DoclD025977 Rev 4 q STM32L486xx Electrical characteristics 6 3 17 Analog to Digital converter characteristics Unless otherwise specified the parameters given in Table 63 are preliminary values derived from tests performed under ambient temperature fpc frequency and VppA supply voltage conditions summarized in Table 22 General operating conditions Note It is recommended to perform a calibration after each power up Table 63 ADC characteristics 2 Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1 62 3 6 V gt 2 V 2 VppA V VREF Positive reference voltage lt 2 V VppA V Negative reference VREF voltage Vssa V Range 1 80 fADC ADC clock frequency MHz Range 2 26 Resolution 12 bits 5 33 Sampling rate for FAST Resolution 10 bits 6 15 channels Resolution 7 8 bits 7 27 Resolution 6 bits 8 88 fs Msps Resolution 12 bits 4 21 Sampling rate for SLOW Resolution 10 bits 4 71 channels Resolution 8 bits i 5
156. age Rising edge 1 61 1 665 1 69 Won V monitoring Falling edge 1 6 164 1 68 VppA Peripheral voltage Rising edge 1 78 1 82 1 86 Hori V monitoring Falling edge 177 181 1 85 Vnyst PVM3 hysteresis 10 mV Vhyst_Ppvma hysteresis 10 E mV 1 and PVM2 PVM1 PVM2 0 2 2 consumption from Vpp lop PVM3 and PVM4 PVM3 PVM4 2 pA 2 consumption from Vpp Continuous mode means Run Sleep modes or temperature sensor enable in Low power run Low power sleep modes Guaranteed by design BORO is enabled in all modes except shutdown and its consumption is therefore included in the supply current characteristics tables DoclD025977 Rev 4 101 231 Electrical characteristics STM32L486xx 6 3 4 Embedded voltage reference The parameters given in Table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22 General operating conditions Table 25 Embedded internal voltage reference Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage 40 lt TA lt 130 C 1 182 1 212 1 232 V ADC sampling time when 15 vrefint 1 reading the internal reference 40 Hs voltage Start time of reference voltage start_vrefint buffer when ADC is enable 7 8 12 HS Vrerint buffer consumption from Vpp when
157. als Results stored into 3 data register or in RAM with DMA controller support Data pre processing left right alignment and per channel offset compensation Built in oversampling unit for enhanced SNR Channel wise programmable sampling time Three analog watchdog for automatic voltage monitoring generating interrupts and trigger for selected timers A Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor TS generates a voltage Vrs that varies linearly with temperature The temperature sensor is internally connected to the ADC1 IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement As the offset of the temperature sensor varies from chip to chip due to process variation the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only DoclD025977 Rev 4 37 231 Functional overview STM32L486xx 3 15 2 3 15 3 3 16 38 231 To improve the accuracy of the temperature sensor measurement each device is individually factory calibrated by ST The temperature sensor factory calibration data are stored by ST in the system memory area accessible in read only mode Table 8 Temperature sensor cali
158. alues When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device are monitored while a simple application is executed toggling 2 LEDs through the ports This emission test is compliant with IEC 61967 2 standard which specifies the test board and the pin loading Table 54 EMI characteristics Monitored Max vs fuse fucud Symbol Parameter Conditions equencv band 4 Unit 24 MHz 8 MHz 80 MHz 0 1 to 30 MHz 9 2 3 6 V TA 25 LQFP144 package 30 to 130 MHz 8 3 dBuV SEMI Peak level compliant with IEC 130 MHz to 1 GHz 10 14 61967 2 EMI Level 1 5 3 5 6 3 12 Electrical sensitivity characteristics q Based on three different tests ESD LU using specific measurement methods the device is stressed in order to determine its performance in terms of electrical sensitivity Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts x n 1 supply pins This test conforms to the ANSI JEDEC standard Table 55 ESD absolute maximum ratings Symbol Ratings
159. ameter Supply current in Run mode Supply current in Low power run Conditions TYP TYP Unit Unit Voltage Code 25 C 25 C scaling Reduced code 2 9 111 I lt gt Coremark 3 1 118 o 2 Dhrystone 2 1 3 1 mA 119 pA MHz f f y Do a p m Fibonacci 29 112 included bypass While 1 2 8 108 mode PLL ON above 48 MHz Reduced code 10 2 127 all peripherals _ Coremark 10 9 136 disable oo 2 0 Dhrystone 2 1 11 0 mA 137 5 Fibonacci 10 5 131 Em While 1 9 9 124 Reduced code 272 136 Coremark 291 145 fuck fusi 2 MHz all peripherals disable Dhrystone 2 1 302 151 2 Fibonacci 269 135 While 1 269 135 1 Reduced code used for characterization results provided in Table 26 Table 27 Table 28 108 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 30 Typical current consumption in Run and Low power run modes with different codes running from Flash ART disable Conditions TYP TYP Symbol Parameter Volt Unit Unit Code 25 C 25 C scaling Reduced codel 3 1 119 2 Coremark 2 9 111 fucik fuse up to E Dhrystone 2 1 2 8 mA 111 2 48 MHz included X Fibonacci 2 7 104 Supply bypass mode
160. applied on any pin 3 3 V Ta 25 C VrFESD 80 MHz 3B to induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 3 3 V Ta 25 C Verte applied through 100 pF on Vss 80 MHz 4A pins to induce a functional disturbance conforming to IEC 61000 4 4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical Data corruption control registers q DocID025977 Rev 4 STM32L486xx Electrical characteristics Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification v
161. bration values Calibration value name Description Memory address TS ADC raw data acquired at a TS_CAL1 temperature of 30 C 5 C Ox1FFF 75A8 Ox1FFF 75A9 VppA VREF 3 0V 10 mV TS ADC raw data acquired at a TS CAL2 temperature of 110 C 5 Ox1FFF 75CA Ox1FFF 75CB VppA Vrer 3 0 V 10 mV Internal voltage reference The internal voltage reference VREFINT provides a stable bandgap voltage output for the ADC and Comparators VREFINT is internally connected to the ADC1 INO input channel The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area It is accessible in read only mode Table 9 Internal voltage reference calibration values Calibration value name Description Memory address Raw data acquired at a VREFINT temperature of 30 C x 5 C Ox1FFF 75AA Ox1FFF 75AB VppA Vrer 3 0 V 10 mV battery voltage monitoring This embedded hardware feature allows the application to measure the battery voltage using the internal ADC channel ADC1 IN18 or ADC3 IN18 As the voltage may be higher than VDDA and thus outside the ADC input range the VBAT pin is internally connected to a bridge divider by 3 As a consequence the converted digital value is one third the voltage Digital to analog converter DAC Two 12 bit buffered DAC channels can be
162. compliant implementation of AES encryption decryption algorithm e 128 bit and 256 bit register for storing the encryption decryption or derivation key 4 32 bit registers e Electronic codebook ECB Cipher block chaining CBC Counter mode CTR Galois Counter Mode GCM Galois Message Authentication Code mode GMAC and Cipher Message Authentication Code mode CMAC supported e Key scheduler e Key derivation for decryption e 128 bit data block processing e 128 bit 256 bit key length e 1x32 bit INPUT buffer and 1x32 bit OUTPUT buffer e Register access supporting 32 bit data width only e One 128 bit Register for the initialization vector when AES is configured in CBC mode or for the 32 bit counter initialization when CTR mode is selected GCM mode or CMAC mode e Automatic data flow control with support of direct memory access DMA using 2 channels one for incoming data and one for outcoming data e Suspend a message if another message with a higher priority needs to be processed Timers and watchdogs The STM32L486 includes two advanced control timers up to nine general purpose timers two basic timers two low power timers two watchdog timers and a SysTick timer The table below compares the features of the advanced control general purpose and basic timers DoclD025977 Rev 4 43 231 Functional overview STM32L486xx Table 10 Timer feature comparison Co
163. consumption in Standby mode Conditions TYP MAX Symbol Parameter Unit 25 55 C 85 C 105 125 C 25 C 55 C 85 C 105 125 18V 114 355 1540 4146 10735 176 888 3850 10365 26838 24 138 407 1795 4828 12451 223 1018 4488 12070 31128 Supply current no independent watchdog 150 486 2074 5589 14291 263 1215 5185 13973 35728 mode backup 3 6V 198 618 2608 6928 17499 383 1545 6520 43748 Ipp Standby nA registers retained 18V 317 E E i li RTC disabled with independent 24 391 watchdog 3V 438 5 3 6V 566 18V 377 621 1873 4564 11318 491 1207 4250 10867 27537 RTC clocked by LSI no 24 464 756 2210 5348 13166 614 1436 4986 12694 31986 independent watchdog 572 913 2599 6219 15197 770 1727 5815 14729 36815 3 6V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184 A n 1 8 V 456 I RTC clocked by LSI with 24 V 557 Supply current independent watchdog 3V 663 i n in Standby Ipp Standby mode backup 3 6 V 885 x 7 I x with RTC registers 18V 289 527 1747 4402 11009 E retained RTC P us RTC clocked by LSE 2 44V
164. converted by 12 5 200 Ipp VREFINTBUF ADC Internal reference voltage AVREFINT spread over the temperature Vpp 3 V 5 7 52 mV range Average temperature 2 coefficient 40 lt Ty lt 130 C 30 50 ppm C Long term stability 1000 hours T 25 C TBD ppm Average voltage coefficient 3 0 V lt Vpp lt 3 6 V 250 1200 ppm V VREFINT 1 4 reference voltage 24 25 26 0 VREFINT piv2 1 2 reference voltage 49 50 51 V REFINT VREFINT piv3 3 4 reference voltage 74 75 76 1 The shortest sampling time can be determined in the application by multiple iterations 2 Guaranteed by design 102 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Figure 14 Veerint versus temperature V 1 235 1 23 1 225 Lone 1 22 1 215 121 2 77 1 205 1 2 1 195 1 185 40 20 0 20 40 60 80 100 120 C Min MSv40169V1 q DocID025977 Rev 4 103 231 Electrical characteristics STM32L486xx 6 3 5 104 231 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage ambient temperature I O pin loading device software configuration operating frequencies I O pin switching rate program location in memory and executed binary code
165. d external crystal LSE supporting four drive capability modes The LSE can also be configured in bypass mode for an external clock 32 kHz low speed internal RC LSI also used to drive the independent watchdog The LSI clock accuracy is 5 accuracy Peripheral clock sources Several peripherals USB SDMMC RNG SAI USARTS I2Cs LPTimers ADC SWPMI have their own independent clock whatever the system clock Three PLLs each having three independent outputs allowing the highest flexibility can generate independent clocks for the ADC the USB SDMMC RNG and the two SAls Startup clock after reset the microcontroller restarts by default with an internal 4 MHz clock MSI The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts Clock security system CSS this feature can be enabled by software If a HSE clock failure occurs the master clock is automatically switched to HSI16 and a software q DocID025977 Rev 4 STM32L486xx Functional overview interrupt is generated if enabled LSE failure can also be detected and generated an interrupt e Clock out capability microcontroller clock output it outputs one of the internal clocks for external use by the application LSCO low speed clock output it outputs LSI or LSE in all low power modes except VBAT Several prescalers allow to configure the AHB frequency the high speed APB APB2 and th
166. d filter parameters with up to 24 bit final ADC resolution DoclD025977 Rev 4 41 231 Functional overview STM32L486xx The DFSDM peripheral supports e 8 multiplexed input digital serial channels configurable SPI interface to connect various SD modulator s configurable Manchester coded 1 wire interface support PDM Pulse Density Modulation microphone input support maximum input clock frequency up to 20 MHz 10 MHz for Manchester coding clock output for SD modulator s 0 20 MHz e alternative inputs from 8 internal digital parallel channels to 16 bit input resolution internal sources device memory data streams DMA e 4 digital filter modules with adjustable digital signal processing Sinc filter filter order type 1 5 oversampling ratio up to 1 1024 integrator oversampling ratio 1 256 e up to 24 bit output data resolution signed output data format e automatic data offset correction offset stored in register by user e continuous or single conversion e sStart of conversion triggered by software trigger internal timers external events start of conversion synchronously with first digital filter module DFSDMO e analog watchdog feature low value and high value data threshold registers dedicated configurable Sincx digital filter order 1 3 oversampling ratio 1 32 input from final output data or from selected input digital serial channels co
167. d in Table 19 Voltage characteristics and the sum of the currents sourced or sunk by all the I Os I O ports and control pins must always respect the absolute maximum ratings 2 TTL and CMOS outputs are compatible with standards JESD36 and JESD52 Guaranteed by design 146 231 Input output AC characteristics The definition and values of input output AC characteristics are given in Figure 22 and Table 60 respectively Unless otherwise specified the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22 General operating conditions DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 60 I O AC characteristics 2 Speed Symbol Parameter Conditions Min Max Unit C 50 pF 2 7 lt lt 3 6 V 5 C 50 pF 1 62 lt lt 2 7 V 1 Fmax Maximum frequency i MHz C 10 pF 2 7 VSVppioxS3 6 V 10 C 10 pF 1 62 VXVppjoX2 7 V 1 5 C 10 pF 1 08 VsVppjo31 62 V 0 1 C 50 pF 2 7 lt lt 3 6 V 25 C 50 pF 1 62 lt lt 2 7 V 52 Tr Tf Output rise and fall time ns C 10 pF 2 7 VSVppjoxS3 6 V 17 C 10 pF 1 62 lt 52 7 V 37 C 10 pF 1 08 lt lt 1 62 V 110 C 50 pF 2 7 lt lt 3 6 V 25 C 50 pF 1
168. e an interrupt and wakeup the device from the low power modes DoclD025977 Rev 4 47 231 Functional overview STM32L486xx 3 27 Inter integrated circuit interface 12C The device embeds 3 I2C Refer to Table 11 I2C implementation for the features implementation The 12 bus interface handles communications between the microcontroller and the serial 2 bus It controls all 2 bus specific sequencing protocol arbitration and timing The I2C peripheral supports e l C bus specification and user manual rev 5 compatibility Slave and master modes multimaster capability Standard mode Sm with a bitrate up to 100 kbit s Fast mode Fm with a bitrate up to 400 kbit s Fast mode Plus Fm with a bitrate up to 1 Mbit s and 20 mA output drive I Os T bit and 10 bit addressing mode multiple 7 bit slave addresses Programmable setup and hold times Optional clock stretching e System Management Bus SMBus specification rev 2 0 compatibility A Hardware PEC Packet Error Checking generation and verification with ACK control A Address resolution protocol ARP support SMBus alert e Power System Management Protocol PMBus specification rev 1 1 compatibility e Independent clock a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming Refer to Figure 3 Clock tree e Wakeup from Stop mode on address match e Progra
169. e below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22 General operating conditions All Os are CMOS TTL compliant FT OR TT unless otherwise specified Table 59 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VoL Output low level voltage for an CMOS port 0 4 8 Output high level voltage for an I O pin Vppiox gt 2 7 V Vppiox 0 4 Vo Output low level voltage for an I O TTL port 0 4 8 mA Vou Output high level voltage for an I O pin Vppiox 2 2 7 V 24 Vo Output low level voltage for an I O pin 20 mA 1 3 Output high level voltage for an I O pin Vppiox 2 2 7 V Vppiox 1 3 VoL Output low level voltage for an pin lol 4 mA 0 45 Von Output high level voltage for an I O pin Vppiox 2 1 62 V Vppiox 0 45 Output low level voltage for pin 2 mA 0 35xVDDIOx Vou Output high level voltage for an pin 1 62 V 2 Vppiox 2 1 08 V 0 65 Vopiox llio 20 mA _ Vppiox gt 2 7 V om V Output low level voltage for an FT I O 10 mA pin in FM mode FT I O with f 0 4 option DDIOx lio 2 _ 0 4 1 62 V gt Vppiox 2 1 08 V 1 The current sourced or sunk by the device must always respect the absolute maximum rating specifie
170. e booster is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG_CFGR1 when VppaA lt 2 4 V It is disable when VppA gt 2 4 V No oversampling 156 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 66 ADC accuracy limited test conditions 2 1 2 3 Sym parameter bol Total ET unadjusted error EO Offset error EG Gain error Differential ED linearity error Integral EL linearity error Effective of bits Signal to noise and SINAD distortion ratio SNR Signal to noise ratio q ADC clock frequency lt 80 MHz Sampling rate lt 5 33 Msps 2V lt VDDA Conditions Min Typ Max Unit Single Fast channel max speed 4 6 5 ended Slow channel max speed 4 6 5 Fast channel max speed 3 5 5 5 Differential Slow channel max speed 3 5 5 5 Single Fast channel max speed 1 4 5 ended Slow channel max speed 1 5 Fast channel max speed 15 3 Differential Slow channel max speed 15 3 Single Fast channel max speed 2 5 6 ended Slow channel max speed 2 5 6 Fast channel max speed 2 5 3 5 Differential Slow channel maxspeed 2 5 3 5 Single Fast channel max speed 1 1 5 ended Slow channel max speed 1 1
171. e conditions summarized in Table 22 General operating conditions The provided curves are characterization results not tested in production High speed internal HSI16 RC oscillator Table 47 HSI16 oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fusiie HSI16 Frequency Vpp 3 0 V Ta 30 C 15 88 16 08 MHz Trimming code is not a multiple of 64 55 52 HS116 user trimming step Trimming code is a _4 6 8 multiple of 64 DuCy HSI16 Duty Cycle I 45 55 HSI16 oscillator frequency Ta 0 to 85 C 1 7 1 5116 drift over temperature o p 40 to 125 C 2 1 5 95 HS116 oscillator frequency Avpp HSM6 over Vo Vpp 1 62 V to 3 6 V 0 1 0 05 tey HS116 2 HSI16 oscillator start up _ _ 08 1 2 us time 2 HSI16 oscillator I I tsa HS116 stabilization time B HS 150 99116 2 HS116 oscillator power _ I 155 190 UA consumption 1 Guaranteed by characterization results 2 Guaranteed by design 132 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Figure 19 HSI16 frequency versus temperature MHz 16 4 EVE EN MOM nee rem 1 essent escis tibiis HEP M RUN RR 16 2 1 16 1 40 20 0 20 40 60 80 100 120 Mean min MSv39299V2 Ly DoclD025977 Rev 4 133 231 Electrical characteristics
172. e low speed APB APB1 domains The maximum frequency of the AHB and the APB domains is 80 MHz q DocID025977 Rev 4 33 231 Functional overview STM32L486xx Figure 3 Clock tree to IWDG LSI RC 32 kHz LSCO to RTC and LCD OSC32 OUT LSE OSC 32 768 kHz 82 OSC32 IN LSE LSI Ey 11 16 iem gt to PWR SYSCLK HS o AHB bus core memory and DMA Clock source control AHB HCLK FCLK Cortex free running clock OSC OUT HSE OSC PRESC gt 11 2 512 4 48 MHz HSE to Cortex system timer e 18 gt Clock MSI detector HSI SYSCLK APB1 PCLK1 PRESC 11 2 4 8 16 to APB1 peripherals xlorx2 ME 4 to TIMx z 2 7 to USARTx SYSCLK X 2 5 to LPUART1 1 MSI RC HSI z SYSCLK to I2Cx 100 kHz 48 MHz 1 2 3 I LSI LSE to LPTIMx HSI 1 2 HSI n 4 to SWPMI MSI PCLK2 PEE 4 IM HSN HSE PREBE 2 peripherals to peripherals p PLLSAI3CLK 11 2 4 8 16 PLLUSB1CLK 2 EM o x IR PLLCLK x 1 8 15 16 17 LSE gt PLLSAI1 o HSI 4 to PLLSA
173. ed on or off 4 SRAM2 content is preserved when the bit RRS is set PWR_CR3 register 5 Some peripherals with wakeup from Stop capability can request HSI16 to be enabled In this case HSI16 is woken up by the peripheral and only feeds the peripheral which requested it HSI16 is automatically put off when the peripheral does not need it anymore 6 UART and LPUART reception is functional in Stop mode and generates a wakeup interrupt on Start address match or received frame event 7 2C address detection is functional in Stop mode and generates a wakeup interrupt in case of address match 8 Voltage scaling Range 1 only 9 I Os can be configured with internal pull up pull down or floating in Standby mode 10 The I Os with wakeup from Standby Shutdown capability are PAO PC13 PE6 PA2 PC5 11 I Os can be configured with internal pull up pull down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode 3 9 5 Reset mode In order to improve the consumption under reset the I Os state under and after reset is analog state the I O schmitt trigger is disable In addition the internal reset pull up is deactivated when the reset source is internal 3 9 6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery an external supercapacitor or from Vpp when no external battery and an external supercapacitor are present The VBAT pin supplies the RTC with L
174. ed running from SRAM Flash memory Off 80 MHz in Range 1 26 MHz in Range 2 2 MHz in LPRun LPSleep The Flash memory can be put in power down and its clock can be gated off when executing from SRAM The SRAM1 and SRAM 2 clocks be gated on or off independently U S ART and LPUART reception is functional in Stop mode and generates a wakeup interrupt on Start address match or received frame event I2C address detection is functional in Stop mode and generates a wakeup interrupt in case of address match OTG FS wakeup by resume from suspend and attach detection protocol event SWPMI1 wakeup by resume from suspend 0 The I Os with wakeup from Standby Shutdown capability are PAO PC13 PE6 PA2 PC5 1 I Os can be configured with internal pull up pull down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode euon5ounq 987 1C IN LS STM32L486xx Functional overview By default the microcontroller is in Run mode after a system or a power Reset It is up to the user to select one of the low power modes described below e Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interrupt event occurs e Low power run mode This mode is achieved with VCORE supplied by the low power regulator to minimize the regulator s operating current The code can be executed from SRAM or from Flash and the CPU frequenc
175. er are the following e Interface with static memory mapped devices including Static random access memory SRAM NOR Flash memory OneNAND Flash memory PSRAM 4 memory banks Flash memory with ECC hardware to check up to 8 Kbyte of data e 8 16 bit data bus width e Independent Chip Select control for each memory bank e Independent configuration for each memory bank e Write FIFO e The Maximum FMC_CLK frequency for synchronous accesses is HCLK 2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers It supports the Intel 8080 and Motorola 6800 modes and is flexible enough to adapt to specific LCD interfaces This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration q DocID025977 Rev 4 STM32L486xx Functional overview 3 37 Quad SPI memory interface QUADSPI The Quad SPI is a specialized communication interface targeting single dual or quad SPI flash memories It can operate in any of the three following modes e Indirect mode all the operations are performed using the QUADSPI registers e Status polling mode the external flash status register is periodically read and an interrupt can be generated in case of flag setting e mode the external flash is me
176. eristics STM32L486xx 206 231 Table 101 Synchronous non multiplexed PSRAM write timings 1 Symbol Parameter Min Max FMC CLK period 2 0 5 taCLKL NExL CLK low to NEx low 0 2 2 ta CLKH NExH FMC_CLK high to FMC_NEx high 0 2 Tucik 0 5 taCcLKL NADVL FMC_CLK low to FMC_NADV low 2 ta CLKL NADVH FMC_CLK low to FMC_NADV high 2 5 ta CLKL AV FMC_CLK low to FMC_Ax valid x 16 25 5 FMC_CLK high to FMC_Ax invalid x 16 25 TuciK 1 ta CLKL NWEL FMC_CLK low to FMC_NWE low 2 ta CLKH NWEH FMC_CLK high to FMC_NWE high 1 ta cLKL Data D 15 0 valid data after low 4 5 low to FMC_NBL low 1 5 ty CLKH NBLH FMC_CLK high to FMC_NBL high Tucik 1 tsu NWAIT CLKH FMC_NWAIT valid before FMC_CLK high 0 thicLKH NWAIT FMC_NWAIT valid after high 4 CL 30 pF 2 Guaranteed by characterization results NAND controller waveforms and timings Unit ns Figure 44 through Figure 47 represent synchronous waveforms and Table 102 and Table 103 provide the corresponding timings The results shown in these tables are obtained with the following FMC configuration COM FMC_SetupTime 0x02 COM FMC_WaitSetupTime 0x03 COM FMC_HoldSetupTime 0x02 COM FMC_HiZSetupTime 0x03 ATT FMC_SetupTime 0x01 ATT
177. erwise specified by a note all I Os are set as analog inputs during and after reset Alternate Pin functions Functions selected through GPIOx AFR registers functions Additional functions Functions directly selected enabled through peripheral registers gv d o qe c 60 231 The related I O structures in Table 15 are The related I O structures in Table 15 are The related I O structures in Table 15 are DoclD025977 Rev 4 The related I O structures in Table 15 are FT f FT fa FT fl FT fla FT_ FT_fl FT lu FT FT lu FT a FT la The related I O structures in Table 15 are FT s fs FT fla TT a TT la q STM32L486xx Pinouts and pin description Table 15 STM32L486xx pin definitions Pin Number Pin functions i 5 2 5 I Main E Alternate functions Additional reset gt Y 9 functions c S S 5 9 2 TRACECK TIM3 ETR TSC G7 101 1 B2 1 PE2 VO 1 LCD SEG38 A23 SAI1 MCLK A EVENTOUT TRACEDO TIM3 1 TSC G7 102 mee Los PES Mc PY ss LCD SEG39 A19 I SAI1 SD B EVENTOUT TRACED1 TIM3 CH2 DFSDM DATIN3 ES ESL E e pr TSC G7 103 A20 I SAI1 FS A EVENTOUT TRACED2 TIM3 CH3 DFSDM CKIN3 PES is PT 7 TSC G7 104 21 SAI1 SCK A EVENTOUT TRACED3 TIM3
178. eset gt v 9 functions 9959 amp 9 2 TIM8_BKIN2 TIM3_CH4 TIM8_CH4 TSC_G4_104 OTG FS NOE LCD SEG27 40 E1 66 D12 99 PC9 FT 1 SDMMC1_D1 SAI2_EXTCLK 8 2 1 EVENTOUT MCO TIM1 CH1 USART1 41 E2 67 D11 100 PA8 OTG FS SOF LCD COMO LPTIM2 OUT EVENTOUT TIM1 CH2 USART1 TX 42 E3 68 010 101 PA9 VO FT lu LCD 1 15 BKIN OTG FS VBUS EVENTOUT TIM1_CH3 USART1 RX 43 D2 69 C12 102 PA10 VO FT lu OTG FS ID LCD 2 TIM17 BKIN EVENTOUT TIM1 CH4 TIM1 BKIN2 USART1 CTS CAN1 RX 44 D1 70 B12 103 PA11 OTG FS DM TIM1 BKIN2 COMP 1 EVENTOUT TIM1 ETR USART1 RTS DE 45 1 71 A12 104 PA12 TX OTG FS DP EVENTOUT PA13 JTMS SWDIO IR_OUT 46 2 72 A11 105 OTG FS NOE JTMS SWDIO AP Bi vss s 2 48 A1 73 C11 106 VDDUSB S 74 F11 107 VSS S 75 611 108 VDD S PA14 3 JTCK SWCLK 49 B2 76 A10 109 JTCK SWCLK EVENTOUT ky DoclD025977 Rev 4 69 231 Pinouts and pin description STM32L486xx Table 15 STM32L486xx pin definitions continued Pin Number LQFP64 51 52 WLCSP72 D3 C3 LQFP100 78 79 32 UFBGA1 B11 C10 LQFP144 111 112 Pin name function after reset PA15 JTDI
179. f each SAI audio sub block DoclD025977 Rev 4 51 231 Functional overview STM32L486xx 3 32 3 33 52 231 Table 13 SAI implementation SAI features SAM SAI2 12 LSB or MSB justified PCM DSP TDM AC 97 X X Mute mode X X Stereo Mono audio frame capability X X 16 slots X X Data size configurable 8 10 16 20 24 32 bit X X FIFO Size X 8 Word X 8 Word SPDIF X X 1 X supported Single wire protocol master interface SWPMI The Single wire protocol master interface SWPMI is the master interface corresponding to the Contactless Frontend CLF defined in the ETSI TS 102 613 technical specification The main features are e full duplex communication mode e automatic SWP bus state management active suspend resume e configurable bitrate up to 2 Mbit s e automatic SOF EOF and CRC handling SWPMI can be served by the DMA controller Controller area network CAN The CAN is compliant with specifications 2 0A and B active with a bit rate up to 1 Mbit s It can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers It has three transmit mailboxes two receive FIFOs with 3 stages and 14 scalable filter banks The CAN peripheral supports e Supports CAN protocol version 2 0 A B Active e Bitrates up to 1 Mbit s q DocID025977 Rev 4 STM32L486xx Functional overview 3 34 3 35 q e Transmi
180. fferential Slow channel max speed 10 8 10 9 Single Fast channel max speed 64 4 65 ended Slow channel max speed 64 4 65 Fast channel max speed 66 8 67 4 Differential Slow channel max speed 66 8 67 4 dB Single Fast channel max speed 65 66 ended Slow channel max speed 65 66 Fast channel max speed 67 68 Differential Slow channel max speed 67 68 DoclD025977 Rev 4 155 231 Electrical characteristics STM32L486xx Table 65 ADC accuracy limited test conditions 1 1 2 3 continued Sym bol THD Parameter Total harmonic distortion Conditions Min Typ Max Unit ADC clock frequency s Single Fast channel max speed 74 73 ee Mhz ended Slow channel max speed 74 73 Sampling rate lt 5 33 Msps dB VgEr 3 V Fast channel max speed 79 76 TA 25 C Slow channel max speed 79 76 1 Guaranteed by design 2 ADC DC accuracy values are measured after internal calibration ADC accuracy vs negative Injection Current Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative current 4 The I O analog switch voltag
181. for each audio sub block e Synchronous or asynchronous mode between the audio sub blocks e Master or slave configuration independent for both audio sub blocks e Clock generator for each audio block to target independent audio frequency sampling when both audio sub blocks are configured in master mode e Data size configurable 8 10 16 20 24 32 bit e Peripheral with large configurability and flexibility allowing to target as example the following audio protocol 125 LSB or MSB justified PCM DSP TDM AC 97 and SPDIF out e Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame Number of bits by frame may be configurable e Frame synchronization active level configurable offset bit length level e First active bit position in the slot is configurable e first or MSB first for data transfer e Mute mode e Stereo Mono audio frame capability e Communication clock strobing edge configurable SCK e Error flags with associated interrupts if enabled respectively Overrun and underrun detection Anticipated frame synchronization signal detection in slave mode Late frame synchronization signal detection in slave mode Codec not ready for the AC 97 mode in reception e Interruption sources when enabled Errors FIFO requests DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO o
182. fter FMC_NWE high 1 twBL_NE FMC_NEx low to FMC BL valid 1 5 nwe FMC BL hold time after NWE high 0 5 tv Data ne Data to NEx low to Data valid 4 th Data_NWeE Data hold time after FMC_NWE high 1 tyNADV NE FMC_NEx low to FMC_NADV low 1 twNApv NADV low time 0 5 1 CL 30 pF 2 Guaranteed by characterization results DoclD025977 Rev 4 195 231 Electrical characteristics STM32L486xx Table 93 Asynchronous non multiplexed SRAM PSRAM NOR write NWAIT timings Symbol Parameter Min Max Unit tw NE FMC_NE low time 8THcLKtO 5 8THcLKtO 5 tw NWE FMC_NWE low time 6TycLK 0 5 6TucLKt0 5 ns tsu NWAIT_NE FMC_NWAIT valid before FMC_NEx high 6Tucik 2 gt th NE_NWAIT FMC_NEx hold time after FMC_NWAIT invalid 4Tucik 2 1 CL 30 pF 2 Guaranteed by characterization results Figure 38 Asynchronous multiplexed PSRAM NOR read waveforms tw NE FMC_ NE FMC NOE FMC NWE nuc 1 lv BL NE th BL NOE e h Data NE AD 15 0 tv NADV NE NADV FMC_NWAIT tsu Data_ tsu Data_N ih Data NOE ty cm t w NADV th NE_NWAIT tSu NWAIT NE MS32755V1 196 231 q DocID025977 Rev 4 STM32L486xx Electrical characteristics Table 94 Asynchronous multiplexed PSRAM NOR read timings
183. g 500 18 30 load 4 mA 35 50 Unit 1 Guaranteed by design unless otherwise specified drop voltage Guaranteed by test in production In degraded mode the voltage reference buffer can not maintain accurately the output voltage which will follow To well control inrush current of VREFBUF during start up phase and scaling change voltage should be in the range 2 4 V to 3 6 V and 2 8 V to 3 6 V respectively for Vas 0 and Vgs 0 q DocID025977 Rev 4 169 231 Electrical characteristics STM32L486xx 6 3 20 Comparator characteristics Table 72 COMP characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1 62 3 6 Comparator input voltage VIN range 0 VppA V Vac Scaler input voltage VREFINT Vsc Scaler offset voltage 5 10 mV i BRG_EN 0 bridge disable 200 300 nA IDDA SCALER Scaler static consumption from VppA BRG_EN 1 bridge enable 0 8 1 tsTART_SCALER Scaler startup time 100 200 us High speed Vppa 2 2 7 V 5 mode gt Comparator startup time to Vppa lt 2 7 V teTART reach propagation delay gt 2 7 V 15 us ificati Medium mode specification lt 2 7 V _ 25 Ultra low power mode 80 High speed Vppa 2 2 7 V i 55 80 mode Propagation delay for
184. gral EL linearity error Effective of bits Signal to noise and SINAD distortion ratio SNR Signal to noise ratio q ADC clock frequency lt 80 MHz Sampling rate lt 5 33 Msps VppA VREF 3 V TA 25 C Conditions Min Typ Max Unit Single Fast channel max speed 4 5 ended Slow channel max speed 4 5 Fast channel max speed 3 5 4 5 Differential Slow channel max speed 3 5 4 5 Single Fast channel max speed 1 2 5 ended Slow channel max speed 1 2 5 Fast channel max speed 1 5 2 5 Differential Slow channel max speed 1 5 2 5 Single Fast channel max speed 2 5 4 5 ended Slow channel speed 2 5 4 5 Te Fast channel max speed 2 5 3 5 Differential Slow channel max speed 2 5 3 5 Single Fast channel max speed 1 1 5 ended Slow channel max speed 1 1 5 Fast channel max speed 1 1 2 Differential Slow channel max speed 1 1 2 Single Fast channel max speed 1 5 2 5 ended Slow channel 1 5 2 5 Fast channel max speed 1 2 Differential Slow channel max speed 1 2 Single Fast channel max speed 10 4 10 5 ended Slow channel max speed 10 4 10 5 its Fast channel max speed 10 8 10 9 Di
185. haracterization results DoclD025977 Rev 4 201 231 STM32L486xx Electrical characteristics Figure 41 Synchronous multiplexed PSRAM write timings 0 BUSTURN d CLKH NExH d CLKH AIV t MSv38001V1 Ky d LKH NWEH t ta cLKL Data Data latency 0 NExL ta cLKL FMC_CLK ta cLKuLNADVH gt Q lt 5 iB lt o z z LL FMC A 25 16 NWEL eee ee SL 1 a ee d GLKH NBLH t 3 2 E4 5 N EJ El E Z gt N 5 z a o 4 8 4 K a gt a lt a4 2 E geo o z Z a z O o gt Q SEE lt lt N N STM32L486xx Electrical characteristics q Table 99 Synchronous multiplexed PSRAM write timings Symbol Parameter Min Max Unit tw CLk FMC_CLK period 2Tucuc 1 taCLKL NExL FMC_CLK low to FMC_NEx low x 0 2 2 taCLKH NExH high to FMC_NEx high 0 2 Tucik 0 5 ta cLKL NApvL FMC_CLK low to FMC_NADV low 2 5 taCLKL NADVH CLK low to FMC_NADV high 1 ta CLKL AV FMC CLK low to FMC_Ax valid x 16 25 3 5 tacLKH Alv FMC_CLK high to Ax invalid x 16 25 THCL
186. he ARM Cortex M4 with 32 bit RISC processor features exceptional code efficiency delivering the high performance expected from an ARM core in the memory size usually associated with 8 and 16 bit devices The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution Its single precision FPU speeds up software development by using metalanguage development tools while avoiding saturation With its embedded ARM core the STM32L486xx family is compatible with all ARM tools and software Figure 1 shows the general block diagram of the STM32L486xx family devices Adaptive real time memory accelerator ART Accelerator The ART Accelerator is a memory accelerator which is optimized for STM32 industry standard ARM Cortex M4 processors It balances the inherent performance advantage of the ARM Cortex M4 over Flash memory technologies which normally requires the processor to wait for the Flash memory at higher frequencies To release the processor near 100 DMIPS performance at 80 2 the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 64 bit Flash memory Based on CoreMark benchmark the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz Memory protection unit The memory protection unit MP
187. i oAD 20 pF 40 Voltage Range 1 1 71 lt Vpp lt 3 6 V Cj oAp 15 pF 45 Voltage Range 1 Quad SPI clock frequency MHz 1 2 7 lt lt 3 6 Croan 15 pF _ _ Voltage Range 1 1 71 lt Vpp lt 3 6 V 20 pF 26 Voltage Range 2 lwcKH QuadSPlclockhighand 0 cky22 2 i AHBCLK 2 2 2 Voltage Range 1 4 ts IN Data input setup time Voltage Range 2 3 5 Voltage Range 1 5 5 th IN Data input hold time A r r r ns Voltage Range 2 6 5 Voltage Range 1 2 5 5 tv OUT Data output valid time Voltage Range 2 3 5 Voltage Range 1 1 5 thiouT Data output hold time en Voltage Range 2 2 1 Guaranteed by characterization results 184 231 q DocID025977 Rev 4 STM32L486xx Electrical characteristics Table 85 QUADSPI characteristics in DDR mode Symbol Parameter Conditions Min Typ Max Unit 1 71 lt Vpp lt 3 6 V Ci oAp 20 pF 40 Voltage Range 1 2 lt Vpp lt 3 6 V Cj gap 20 pF 48 Fck Quad SPI clock Voltage Range 1 Wi 1 t ck frequency 1 71 lt Vpp lt 3 6 V Ci gap 15 pF a Voltage Range 1 1 71 lt Vpp lt 3 6 V Cj 20 pF 26 Voltage Range 2 w CKH Quad SPI clock high faugcik 48 MHz 0 CK CK tw CKL and low time 2 2 2 t it Data input setup time 3 5 SIUN e
188. ibility to I O current injection While a simple application is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit higher than 5 LSB TUE out of conventional limits of induced leakage current on adjacent pins out of the 5 0 pA range or other functional failure for example reset occurrence or oscillator frequency deviation The characterization results are given in Table 57 Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection Table 57 I O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on BOOTO pin 0 ling Injected current on pins except PA4 PAS BOOTO 5 NA mA Injected current on PA4 5 pins 5 0 1 NA not applicable q DocID025977 Rev 4 STM32L486xx Electrical characteristics 6 3 14 port characteristics General input output characteristics Unless otherwise specified the parameters given in Table 58 are derived from tests performed under the conditions summarized in Table
189. ification and with the OTG 2 0 specification It has software configurable endpoint setting and supports suspend resume The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator MSI automatically trimmed by 32 768 kHz external oscillator LSE This allows to use the USB device without external high speed crystal HSE DoclD025977 Rev 4 53 231 Functional overview STM32L486xx 3 36 54 231 The major features are e Combined Rx and Tx FIFO size of 1 25 KB with dynamic FIFO sizing e Supports the session request protocol SRP and host negotiation protocol HNP e 1 bidirectional control endpoint 5 IN endpoints 5 OUT endpoints e 8 host channels with periodic OUT support e inside no need for any external resistor e Software configurable to OTG 1 3 and OTG 2 0 modes of operation 2 0 Supports ADP Attach detection Protocol e USB 2 0 LPM Link Power Management support e Battery Charging Specification Revision 1 2 support e Internal FS PHY support For OTG Host modes a power switch is needed in case bus powered devices are connected Flexible static memory controller FSMC The Flexible static memory controller FSMC includes two memory controllers e The NOR PSRAM memory controller e The NAND memory controller This memory controller is also named Flexible memory controller FMC The main features of the FMC controll
190. ility critmax gm LSEDRV 1 0 10 Medium high drive capability LSEDRV 1 0 11 High drive capability 250 630 pA tuse Startup time Vpp is stabilized 2 S 130 231 DoclD025977 Rev 4 Ly STM32L486xx Electrical characteristics Guaranteed by design 2 Refer to the note and caution paragraphs below the table and to the application note AN2867 Oscillator design guide for ST microcontrollers 3 tsu Lse is the startup time measured from the moment it is enabled by software to a stabilized 32 768 kHz oscillation is reached This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note For information on selecting the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Figure 18 Typical application with a 32 768 kHz crystal Resonator with integrated capacitors Drive programmable amplifier 1 32 768 kHz resonator MS30253V2 Note An external resistor is not required between OSC32 IN and OSC32 OUT and it is forbidden to add one q DocID025977 Rev 4 131 231 Electrical characteristics STM32L486xx 6 3 8 Internal clock source characteristics The parameters given in Table 47 are derived from tests performed under ambient temperature and supply voltag
191. ion measurement scheme 96 VREFINT versus temperature 103 High speed external clock source AC timing diagram 127 Low speed external clock source AC timing diagram 128 Typical application with 8 MHz 130 Typical application with a 32 768 kHz 131 HSI16 frequency versus 133 Typical current consumption versus MSI frequency 137 input characteristics 145 AC characteristics definition 149 Recommended pin protection 150 ADC accuracy 163 Typical connection diagram using the 163 12 bit buffered non buffered 166 SPI timing diagram slave mode and 0 182 SPI timing diagram slave mode 1 183 SPI timing diagram master 183 Quad SPI timing diagram SDR
192. istics STM32L486xx 198 231 Figure 39 Asynchronous multiplexed PSRAM NOR write waveforms tw NE FMC_NOE th NE_NWE FMC_NWE A 25 16 Address NE th BL_NWE tv A_NE BE tv Data_NADV h Data_NWE 0 15 0 Address B Data 4 tv NADV NE a th AD_NADV FMC_NADV FMC_NWAIT th NE_NWAIT tsu NWAIT_NE MS32756V1 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics q Table 96 Asynchronous multiplexed PSRAM NOR write timings 1 2 Symbol Parameter Min Max Unit FMC NE low time 0 5 4Tucuk 2 tyNwE NE FMC_NEx low to NWE low 0 5 1 twNwE FMC_NWE low time 2xTucuc1 5 2xThoLk 1 thine nwe FMC_NWE high to NE high hold time 0 5 twa NEx low to FMC A valid 3 NE FMC_NEx low to FMC_NADV low 0 1 twNApv FMC low time 0 5 1 ns arene chev valid hold time after Tucuc2 _ tha nwe Address hold time after FMC_NWE high 1 tni NwE BL hold time after NWE high 0 5 tig NEx low to FMC BL valid 1 5 FMC_NADV high to Data valid 4 tn Data Data hold time after FMC_NWE high 0 5 1 CL 30 pF 2 Guaranteed by characterization result
193. l characteristics All I Os are CMOS TTL compliant no software configuration required Their characteristics cover more than the strict CMOS technology or TTL parameters The coverage of these requirements is shown in Figure 21 for standard I Os and in Figure 21 for 5 V tolerant I Os Figure 21 I O input characteristics 25 0 5 Vil Vih all IO except BOOTO TTL requirement Vih min 2V vil spec 30 vih spec 70 vil spec ttl vih spec ttl Vil_rule Vih_rule TTL requirement Vil max 0 8V MSv37613V1 q Output driving current The GPIOs general purpose input outputs can sink or source up to 8 mA and sink or source up to 20 mA with a relaxed Vol In the user application the number of I O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6 2 e The sum of the currents sourced by all the I Os on Vppiox plus the maximum consumption of the MCU sourced on Vpp cannot exceed the absolute maximum rating Zlypp see Table 19 Voltage characteristics e The sum of the currents sunk by all the I Os on Vas plus the maximum consumption of the MCU sunk on Vgg cannot exceed the absolute maximum rating Xlyss see Table 19 Voltage characteristics DoclD025977 Rev 4 145 231 Electrical characteristics STM32L486xx Output voltage levels Unless otherwise specified the parameters given in the tabl
194. l main supply voltage including V V 0 3 4 0 V DDX 88 Vb Vppa Vppio2 Vico Vear _ min Vopa Vppiq2 VDDUSB Input voltage on FT xxx pins Vgg 0 3 Viso 40 Vin Input voltage on TT_xx pins Vss 0 3 4 0 V Input voltage on BOOTO pin Vss 9 0 Input voltage on any other pins Vgs 0 3 4 0 Variations between different Vppx power AVpxl pins of the same domain I a id Variations between all the different ground IMssxVssl ping 9 50 mV 1 All main power Vppio2 VppusB Vi cp Vear and ground Vss pins must always be connected to the external power supply in the permitted range 96 231 DoclD025977 Rev 4 Ly STM32L486xx Electrical characteristics 2 Vin maximum must always be respected Refer to Table 20 Current characteristics for the maximum allowed injected current values This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table 4 To sustain a voltage higher than 4 V the internal pull up pull down resistors must be disabled Include VREF pin Table 20 Current characteristics Symbol Ratings Max Unit gt Total current into sum of all Vpp power lines source 7 150 Total current out of sum of all Vss ground lines sink 150 IVpp PIN Maximum current into each Vpp power pin source 100 IVss PIN Maximum current out of each Vss
195. ltiMediaCards Interface SDMMC 53 3 35 Universal serial bus on the go full speed OTG 5 53 3 36 Flexible static memory controller FSMC 54 3 37 Quad SPI memory interface QUADSPI 55 3 38 Development support 56 3 38 1 Serial wire JTAG debug port 5 56 3 38 2 Embedded Trace Macrocell 56 4 Pinouts and pin description 57 Ky DoclD025977 Rev 4 3 231 Contents STM32L486xx 5 Memory 89 6 Electrical characteristics 94 6 1 Parameter conditions 94 6 1 1 Minimum and maximum values 94 6 1 2 Typical values bee eed T dE ee ee 94 6 1 3 Typical CUPVES cs u u ee ERE e Ed a 94 6 1 4 Loading capacitor 94 6 1 5 Pin input voltage 94 6 1 6 Power supply scheme 95 6 1 7 Current consumption measurement 96 6 2 Absolute maximum ratings 96 6 3 Operating conditions 98 6 3 1 General operating conditions
196. marking package top view 221 LQFP64 64 10 x 10 mm low profile quad flat package outline 222 LQFP64 64 pin 10 x 10 mm low profile quad flat package recommended 223 LQFP64 marking package top 224 LOFP64 Pp max VS heec nte g a bua Rave F ahua AR RR ara Ra Rc a 227 q DocID025977 Rev 4 STM32L486xx Introduction q Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L486xx microcontrollers This document should be read in conjunction with the STM32L4x6 reference manual RM0351 The reference manual is available from the STMicroelectronics website www st com For information on the ARM Cortex M4 core please refer to the Cortex M4 Technical Reference Manual available from the www arm com website Cortex Intelligent Processors by ARM DoclD025977 Rev 4 11 231 Description STM32L486xx 2 Description The STM32L486xx devices are the ultra low power microcontrollers based on the high performance Cortex M4 32 bit RISC core operating at a frequency of up to 80 MHz The Cortex M4 core features a Floating point unit FPU single precision which supports all ARM single precision data processing instructions and data types It also implements
197. memory Three levels are available Level 0 no readout protection Level 1 memory readout protection the Flash memory cannot be read from or written to if either debug features are connected boot in RAM or bootloader is selected Level 2 chip readout protection debug features Cortex M4 JTAG and serial wire boot in RAM and bootloader selection are disabled JTAG fuse This selection is irreversible Table 3 Access status versus readout protection level and execution modes er xecution Debug boot from RAM or boot A Protection from system memory loader rga level Read Write Erase Read Write Erase Main 1 Yes Yes Yes No No No memory 2 Yes Yes Yes N A N A N A System 1 Yes No No Yes No No memory 2 Yes No No N A N A N A Option 1 Yes Yes Yes Yes Yes Yes bytes 2 Yes No No N A N A N A Backup 1 Yes Yes N AC No No N AC registers 2 Yes Yes N A N A N A N A 1 Yes Yes Yes No No 1 SRAM2 2 Yes Yes Yes N A N A N A 1 Erased when RDP change from Level 1 to Level 0 e Write protection WRP the protected area is protected against erasing and programming Two areas per bank can be selected with 2 Kbyte granularity e Proprietary code readout protection PCROP a part of the flash memory can be protected against read and write from third parties The protected area is execute only it can only be reached by the STM32 CPU as an instruction code while all other accesses
198. mm low profile quad flat package outline SEATING PLANE 0 25 mm GAUGE PLANE IDENTIFICATION 1A ME V4 1 Drawing is not to scale DoclD025977 Rev 4 209 231 Package information STM32L486xx 210 231 Table 104 LQFP144 144 pin 20 x 20 mm low profile quad flat package mechanical data millimeters inches 1 Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 21 800 22 000 22 200 0 8583 0 8661 0 8740 D1 19 800 20 000 20 200 0 7795 0 7874 0 7953 D3 17 500 0 6890 E 21 800 22 000 22 200 0 8583 0 8661 0 8740 E1 19 800 20 000 20 200 0 7795 0 7874 0 7953 E3 17 500 0 6890 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 72 0 080 0 0031 1 Values in inches are converted from mm rounded to 4 decimal digits DoclD025977 Rev 4 q STM32L486xx Package information Figure 49 LQFP144 144 pin 20 x 20 mm low profile quad flat package recommended footprint k o oO 1 0 35 o a F 722 144
199. mmable analog and digital noise filters e 1 byte buffer with DMA capability Table 11 I2C implementation 12C features I2C1 I2C2 I2C3 Standard mode up to 100 kbit s Fast mode up to 400 kbit s Fast mode Plus with 20mA output drive I Os up to 1 Mbit s Programmable analog and digital noise filters SMBus PMBus hardware support Independent clock x x x x Wakeup from Stop 0 Stop 1 mode on address match gt x XxX XxX x x Wakeup from Stop 2 mode on address match 1 X supported q 48 231 DocID025977 Rev 4 STM32L486xx Functional overview 3 28 Universal synchronous asynchronous receiver transmitter USART The STM32L486xx devices have three embedded universal synchronous receiver transmitters USART1 USART2 and USART3 and two universal asynchronous receiver transmitters UART4 UART5 These interfaces provide asynchronous communication IrDA SIR ENDEC support multiprocessor communication mode single wire half duplex communication mode and have LIN Master Slave capability They provide hardware management of the CTS and RTS signals and RS485 Driver Enable They are able to communicate at speeds of up to 10Mbit s USART1 USART2 and USART3 also provide Smart Card mode ISO 7816 compliant and SPI like communication capability All USART have a clock domain independent from the CPU clock allowing the USARTx x 1 2 3 4 5 to wake
200. mory mapped and is seen by the System as if it were an internal memory The Quad SPI interface supports e Three functional modes indirect status polling and memory mapped SDRand DDR support e Fully programmable opcode for both indirect and memory mapped mode e Fully programmable frame format for both indirect and memory mapped mode e Each of the 5 following phases can be configured independently enable length single dual quad communication Instruction phase Address phase Alternate bytes phase Dummy cycles phase Data phase e Integrated FIFO for reception and transmission e 8 16 and 32 bit data accesses are allowed DMA channel for indirect mode operations e Programmable masking for external flash flag management e Timeout management e Interrupt generation on FIFO threshold timeout status match operation complete and access error q DocID025977 Rev 4 55 231 Functional overview STM32L486xx 3 38 3 38 1 3 38 2 56 231 Development support Serial wire JTAG debug port SWJ DP The ARM SWJ DP interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target Debug is performed using 2 pins only instead of 5 required by the JTAG JTAG pins could be re use as GPIO with alternate function the JTAG TMS and TCK pins are shared with SWDIO and SWCLK respectively and a specific sequence
201. mparison COMPx LPTIMERx Low power timer triggered by analog Y Y vlvv i signals comparison ADCx TIM1 8 Timer triggered by analog watchdog Y Y Y Y TIM16 Timer input channel from RTC events Y Y I Y Y I RTC LPTIMERx Low power timer triggered by RTC alarms Y Y vlvv d or tampers All clocks sources internal TIM2 Clock source used as input channel for vivivivi i and external TIM15 16 17 RC measurement and trimming USB TIM2 Timer triggered by USB SOF Y Y j CSS CPU hard fault RAM parity error Flash memory ECC error TIM4 8 COMPx i Timer break Y Y Y Y TIM15 16 17 PVD DFSDM analog watchdog short circuit detection q Functional overview STM32L486xx Table 6 STM32L486xx peripherals interconnect matrix continued c 2 210 Interconnect S s 9 06 Interconnect source Adern Interconnect action 5 o 2 destination Cy al s s 122 External trigger Y Y Y Y LPTIMERx External trigger Y Y Y Y Y di GPIO ADCx DACx Conversion external trigger Y Y Y Y DFSDM 1 LPTIM 1 only 31 231 q DocID025977 Rev 4 Functional overview STM32L486xx 3 11 Clocks and startup The clock controller see Figure 3 distributes the clocks coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness
202. mum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 30 Typical values Unless otherwise specified typical data are based on TA 25 Vpp Vppa V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 20 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11 Figure 10 Pin loading conditions Figure 11 Pin input voltage MCU pin MCU pin C 50 pF MS19210V1 MS19211V1 00 10025977 Rev 4 Ly STM32L486xx Electrical characteristics 6 1 6 Power supply scheme Figure 12 Power supply scheme 1 55 3 6V n x 100 nF 1x4 7 UF m x100 nF 44 7 uF 10 nF 1 UF al Power switch Backup circuitry LSE RTC Backup registers Vcore nx VDD SS Regulator
203. n unit is used to get a CRC code using a configurable generator polynomial value and size Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the EN IEC 60335 1 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at a given memory location Power supply management Power supply schemes e 1 71 to 3 6 V external power supply for I Os Vppio1 the internal regulator and the system analog such as reset power management and internal clocks It is provided externally through Vpp pins e 1 62 V ADCs COMPs 1 8 DACs OPAMPs to 3 6 V external analog power supply for ADCs DACs OPAMPs Comparators and Voltage reference buffer The Vppa voltage level is independent from the Vpp voltage e VppusB 3 0 to 3 6 V external independent power supply for USB transceivers The Vppuss Voltage level is independent from the Vpp voltage e Vppio2 1 08 to 3 6 V external power supply for 14 I Os PG 15 2 The Vppio2 voltage level is independent from the Vpp voltage e Vicp7 2 5 to 3 6 V the LCD controller can be powered either externally through VLCD pin or internally from an internal voltage generated by the embedded step up converter e Vgar 1 55 to 3 6 V power supply for RTC e
204. nal source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO The external clock signal has to respect the I O characteristics in Section 6 3 14 However the recommended clock input waveform is shown in Figure 15 High speed external clock source AC timing diagram Table 43 High speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit Voltage scaling _ 8 48 1 fuse ext User external clock source frequency MHz Voltage scaling _ 8 26 2 OSC IN input pin high level voltage 2 0 7 Vppiox Vppiox y Vusg input pin low level voltage Vss i 0 3 Vppiox Voltage scaling Range 1 I I tw HSEH OSC_IN high or low time ns tw HSEL Voltage scaling 18 Range 2 1 Guaranteed by design Figure 15 High speed external clock source AC timing diagram VHSEH VHSEL j THsE MS19214V2 q DocID025977 Rev 4 127 231 Electrical characteristics STM32L486xx Low speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO The external clock signal has to respect the I O characteristics in Section 6 3 14 However the recommended clock input waveform is shown in Figure 16 Table 44 Low speed external user clock characteristics
205. nalog filter Refer to the table below for the analog filter characteristics Table 82 I2C analog filter characteristics Symbol Parameter Min Max Unit Maximum pulse width of spikes tar that are suppressed by the analog 5002 2609 ns filter 1 Guaranteed by design 2 Spikes with widths below tAF min are filtered 3 Spikes with widths above tAF max are not filtered q DocID025977 Rev 4 STM32L486xx Electrical characteristics SPI characteristics Unless otherwise specified the parameters given in Table 83 for SPI are derived from tests performed under the ambient temperature fpc frequency and supply voltage conditions summarized in Table 22 General operating conditions Output speed is set to OSPEEDRy 1 0 11 e Capacitive load C 30 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO for SPI Table 83 SPI characteristics Symbol Parameter Conditions Min Typ Max Unit Master mode receiver full duplex 2 7 lt Vpp lt 3 6 V 24 Voltage Range 1 Master mode receiver full duplex 1 71 lt Vpp lt 3 6 V 13 Voltage Range 1 Master mode transmitter 1 71 lt Vpp lt 3 6 V 40 Voltage Range 1 fsck Slave mode receiver osa SPI clock frequency 1 71 lt Vpp lt
206. ndependent from the CPU clock and can wakeup the system from Stop mode The wake up events from Stop mode are programmable and can be e Start bit detection e received data frame specific programmed data frame Only a 32 768 kHz clock LSE is needed to allow LPUART communication up to 9600 baud Therefore even in Stop mode the LPUART can wait for an incoming frame while having an extremely low energy consumption Higher speed clock can be used to reach higher baudrates LPUART interface can be served by the DMA controller q DocID025977 Rev 4 STM32L486xx Functional overview 3 30 3 31 q Serial peripheral interface SPI Three SPI interfaces allow communication up to 40 Mbits s in master and up to 24 Mbits s slave modes in half duplex full duplex and simplex modes The 3 bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits The SPI interfaces support NSS pulse mode TI mode and Hardware CRC calculation All SPI interfaces can be served by the DMA controller Serial audio interfaces SAI The device embeds 2 SAI Refer to Table 13 SAI implementation for the features implementation The SAI bus interface handles communications between the microcontroller and the serial audio protocol The SAI peripheral supports e Two independent audio sub blocks which can be transmitters or receivers with their respective FIFO e 8 word integrated FIFOs
207. ne 209 DoclD025977 Rev 4 9 231 List of figures STM32L486xx Figure 49 Figure 50 Figure 51 Figure 52 LQFP144 144 pin 20 x 20 mm low profile quad flat package recommended 211 LQFP144 marking package top 212 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package 213 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint214 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 10 231 UFBGA132 marking package top view 215 LQFP100 100 pin 14 x 14 mm low profile quad flat package outline 216 LQFP100 100 pin 14 x 14 mm low profile quad flat recommended 217 LQFP100 marking package top 218 WLCSP72 72 ball 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package 219 WLCSP72 72 ball 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package recommended 220 WLCSP72
208. network values PGA Gain 8 _ 140 _ Gain 16 bs 10 Resistance Delta R variation R1 or 15 15 R2 PGA gain error PGA gain error 1 1 Gain 2 GBW 2 E GBW PGA bandwidth Gain 4 5 4 i PGA BW for different non MHz inverting gain Gain 8 2 odd 1 SM GBW Gain 16 16 at 1 kHz Output Mera mo loaded with 4 kQ eee at 1 kHz Output Low power mode loaded with 20 kQ 600 Voltage noise en 2 So Normal mode at 10 kHz Output 180 loaded with 4 kO at 10 kHz Output Low power mode ced with 20 299 OPAMP Normal mode ne oad aussen 120 260 Ippa OPAMP consumption from VppA Low power mode Mode 45 100 Guaranteed by characterization results Mostly I O leakage when used in analog mode Refer to lig parameter in Table 58 I O static characteristics of ON R2 is the internal resistance between OPAMP output and OPAMP inverting input R1 is the internal resistance between OPAMP inverting input and ground The PGA gain 1 R2 R1 q DocID025977 Rev 4 173 231 Electrical characteristics STM32L486xx 6 3 22 Temperature sensor characteristics Table 74 TS characteristics Symbol Parameter Min Typ Max Unit T Vtg linearity with temperature 1 2 Avg Slope 2 Average slope 2 3 2 5 2 7 mV C Voltage at 30 C 5 C 9 0 742 0 76 0 785 V tSTART T 4 _ TS BUF Sensor Buffer
209. nnel max speed 4 5 5 5 Single Fast channel max speed 2 5 ended Slow channel 2 5 5 Fast channel max speed 2 3 5 Differential Slow channel 2 5 3 Single Fast channel max speed 4 5 7 ended Slow channel max speed 3 5 6 Fast channel speed 3 5 4 Differential Slow channel maxspeed 3 5 5 Single Fast channel max speed 1 2 1 5 ended Slow channel 1 2 1 5 Fast channel max speed 1 1 2 Differential Slow channel max speed 1 1 2 Single Fast channel max speed 3 35 ended Slow channel max speed 2 5 3 5 Fast channel max speed 2 2 5 Differential Slow channel max speed 2 2 5 Single Fast channel max speed 10 10 4 ended Slow channel max speed 10 10 4 its Fast channel max speed 10 6 10 7 Differential Slow channel max speed 10 6 10 7 Single Fast channel max speed 62 64 ended Slow channel max speed 62 64 Fast channel max speed 65 66 Differential Slow channel max speed 65 66 dB Single Fast channel max speed 63 65 ended Slow channel max speed 63 65 Fast channel max speed 66 67 Differential Slow channel max speed 66 67 DoclD025977 Rev 4 159 231 Electrical characteristics STM32L486xx Table 67 ADC accuracy limited test conditio
210. ns 3123 continued Sym bol THD Parameter Total harmonic distortion ADC clock frequency lt 80 MHz Sampling rate lt 5 33 Msps 1 65 V lt VppA VREF lt 3 6 V Voltage scaling Range 1 Conditions Min Typ Max Unit Single Fast channel max speed 69 67 ended Slow channel max speed 71 67 Fast channel max speed 72 71 dB Differential Slow channel max speed 72 71 1 Guaranteed by design 2 ADC DC accuracy values are measured after internal calibration ADC accuracy vs negative Injection Current Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative current 4 The analog switch voltage booster is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG_CFGR1 when VppA lt 2 4 V It is disable when 2 2 4 V No oversampling 160 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 68 ADC accuracy limited test conditions 4 1 2 3 Sym parameter bol Total ET unadjusted error EO Offset error EG Gain error Differential ED linearity error Integral EL linearity error Effective
211. ntinuous monitoring independently from standard conversion e short circuit detector to detect saturated analog input values bottom and top range up to 8 bit counter to detect 1 256 consecutive 0 s or 1 s on serial data stream monitoring continuously each input serial channel e break signal generation on analog watchdog event or on short circuit detector event e extremes detector storage of minimum and maximum values of final conversion data refreshed by software e DMA capability to read the final conversion data e interrupts end of conversion overrun analog watchdog short circuit input serial channel clock absence e regular or injected conversions regular conversions can be requested at any time or even in continuous mode without having any impact on the timing of injected conversions injected conversions for precise timing and with high conversion priority q 42 231 DocID025977 Rev 4 STM32L486xx Functional overview 3 23 3 24 3 25 q Random number generator RNG All devices embed an RNG that delivers 32 bit random numbers generated by an integrated analog circuit Advanced encryption standard hardware accelerator AES The devices embed an AES hardware accelerator can be used to both encipher and decipher data using AES algorithm The AES peripheral supports e using AES Rijndael Block Cipher algorithm e NIST FIPS 197
212. ode Range 4 to 7 07 over Vpp Vpp 2 4 V reference is 3 V to 3 6 V 0 8 Vpp 1 62 V 5 E to 3 6 V Range 8 to 11 1 Vpp 2 4 V 1 6 to 3 6 V AF Frequency 40 to 85 C 1 2 variation in MSI mode MSI sampling mode Ta 40 to 125 C 2 4 amp 3 458 P USB Period jitter for mode transition Jitter MSI USB clock Range 11 for paired ive 3 916 transition for next _ _ _ 2 MT USB Medium term PLL mode transition Jitter MSI for USB clock Range 11 for paired transition I I I CC cycle to bii mode Range 11 60 ps cycle jitter 51 9 RMS Period jitter PLL mode Range 11 50 ps Range 0 10 20 Range 1 5 10 ts MS1 9 MSI oscillator Range 2 E 4 8 S4 start up time Range 3 E 3 Range 4 to 7 3 6 Range 8 to 11 2 5 6 P 10 of final 5 _ 0 25 0 5 frequency 6 MSl oscillator PLL mode 5 of final _ _ tsraB MSI stabilization time Range 11 frequency wh ms 0 1 of final I _ _ 25 frequency DoclD025977 Rev 4 135 231 Electrical characteristics STM32L486xx Table 48 MSI oscillator characteristics continued Symbol Parameter Conditions Min Typ Unit Range 0 0 6 1 Range 1 0 8 1 2 Range 2 1 2 1 7 Range 3 1 9 2 5 Range 4 4 7 6 pu A A Range 5 6 5 9 consumption Range 6 11 15
213. on the TMS pin is used to switch between JTAG DP and SW DP Embedded Trace Macrocell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L486xx through a small number of ETM pins to an external hardware trace port analyzer TPA device Real time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software TPA hardware is commercially available from common development tool vendors The Embedded Trace Macrocell operates with third party debugger software tools q DocID025977 Rev 4 STM32L486xx Pinouts and pin description 4 Pinouts and pin description Figure 4 STM32L486Zx LQFP144 pinout O PC10 110 1 PA15 109 1 PA14 a a gt x 143 D VSS 142 D 141 PEO 140 PB9 139 1 PB8 138 1 137 PB7 136 D PB6 135 134 PB4 133 D PB3 n N 8 131 VDDIO2 130 VSS TON 929494940 Dnnnmnr c hn 124 PG9 123 D 122 PD6 121 O VDD 120 VSS 119 PD5 118 PD4 117 D 116 D PD2 115 D PD1 114 PDO Ne aa on 2 PE4 PC13 PC14 OSC32 IN PC15 OSC32 OUT PFO PF1 PF2 PF3 PF4 PF5 vss VDD PF6 x LQFP144 PF8
214. one with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors 4 The supply current in Standby with SRAM2 mode is Ipp Standby Ipp SRAM2 The supply current in Standby with RTC with SRAM2 mode is Ipp Standby RTC Ipp SRAM2 5 Wakeup with code execution from Flash Average value given for a typical wakeup time as specified in Table 41 Low power mode wakeup timings Table 38 Current consumption in Shutdown mode Conditions TYP MAX Symbol Parameter Unit Vpp 25 C 55 85 C 105 125 25 C 55 C 85 C 105 C 125 Supply current 1 8V 29 8 194 1110 3250 9093 75 485 2775 8125 22733 c 2 44V 44 3 237 1310 3798 10473 111 593 3275 9495 26183 mode Ipp Shutdown backup 64 1 293 1554 4461 12082 160 733 3885 11153 30205 registers retained RTC 3 6V 112 420 2041 5689 15186 280 1050 5103 14223 37965 disabled sonsiuoj2eJeuo e2129 3 XX987 1ZEINLS y ed 2 6 20 LEC 6LL Table 38 Current consumption in Shutdown mode continued Conditions TYP MAX Symbol Parameter Unit 25 C 55 85 C 105 125 C 25 C 55 C 85 C 105 125 1 8V 210 378 1299 3437 9357 I I F Supply current RTC clocked by LSE 24V 303 499 1577 4056 10825
215. op and Standby modes It can be used either as a watchdog to reset the device when a problem occurs or as a free running timer for application timeout management It is hardware or software configurable through the option bytes The counter can be frozen in debug mode System window watchdog WWDG The window watchdog is based on a 7 bit downcounter that can be set as free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode SysTick timer This timer is dedicated to real time operating systems but could also be used as a standard down counter It features e A 24 bit down counter e Autoreload capability e Maskable system interrupt generation when the counter reaches 0 e Programmable clock source q DocID025977 Rev 4 STM32L486xx Functional overview 3 26 q Real time clock RTC and backup registers The RTC is an independent BCD timer counter It supports the following features e Calendar with subsecond seconds minutes hours 12 or 24 format week day date month year in BCD binary coded decimal format e Automatic correction for 28 29 leap year 30 and 31 days of the month e Two programmable alarms e On the fly correction from 1 to 32767 RTC clock pulses This can be used to synchronize it with a master clock e Reference clock detection
216. ower consumption on VCO freq 96 MHz 200 260 1 VCO freq 192 MHz 380 VCO freq 344 MHz 520 650 1 Guaranteed by design 2 Take care of using the appropriate division factor M to obtain the specified PLL input clock values The M factor is shared between the 3 PLLs q 138 231 DocID025977 Rev 4 STM32L486xx Electrical characteristics 6 3 10 Flash memory characteristics Table 51 Flash memory characteristics Symbol Parameter Conditions Typ Max Unit torog 64 bit programming time 81 69 90 76 us one row 32 double normal programming 2 61 2 90 torog row d i i E word programming time fast programming 1 91 2 12 i one page 2 Kbyte normal programming 20 91 23 24 ms prog_Pag programming time fast programming 15 29 16 98 terase Page 2 KB erase time 22 02 24 47 i one bank 512 Kbyte normal programming 5 35 5 95 5 Prog_pank programming time fast programming 3 91 4 35 Mass erase time tue one or two banks 22 13 24 59 ms Average consumption Write mode 3 4 from Vpp Erase mode 34 155 mA Write mode 7 for 2 us Maximum current peak Erase mode 7 for 41 us 1 Guaranteed by design Table 52 Flash memory endurance and data retention Symbol Parameter Conditions Min Unit Nenp Endurance TA 40 to 105 C 10 kcycles 1 kcycle at T4 85 C 30 1 2 at TA
217. perating conditions Table 61 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit NRST input low level VIL NRST voltage 0 3xVppiox V NRST input high level VIH NRST voltage eg a 0 7xVppiox E NRST Schmitt trigger Vhys NRST voltage hysteresis I I 290 I mv Weak pull up equivalent resistor Vin Vss 29 40 55 NRST input filtered VF NRST pulse 70 ns NRST input not filtered VNF NRST pulse P 1 71 V lt Vpp S 3 6 V 350 ns 1 Guaranteed by design 2 The pull up is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance is minimal 10 order Ly DoclD025977 Rev 4 149 231 Electrical characteristics STM32L486xx 6 3 16 150 231 Figure 23 Recommended NRST pin protection External reset circuit 1 lt Internal reset 52 Filter R NRST in 7 MS19878V2 1 The reset network protects the device against parasitic resets 2 The user must ensure that the level on the NRST pin can go below the Vi max level specified in Table 61 NRST pin characteristics Otherwise the reset will not be taken into account by the device Analog switches booster Table 62 Analog switches booster characteristics Symbol Parameter Min Typ Max Unit
218. r event chaining DoclD025977 Rev 4 q STM32L486xx Functional overview 3 25 2 3 25 3 3 25 4 q General purpose timers TIM2 TIM3 TIM4 TIM5 TIM15 TIM16 TIM17 There are up to seven synchronizable general purpose timers embedded in the STM32L486 see Table 10 for differences Each general purpose timer can be used to generate PWM outputs or act as a simple time base e TIM2 TIM4 and TIM5 They are full featured general purpose timers TIM2 and TIM5 have 32 bit auto reload up downcounter and 32 bit prescaler TIM3 have 16 bit auto reload up downcounter 16 bit prescaler These timers feature 4 independent channels for input capture output compare PWM or one pulse mode output They can work together or with the other general purpose timers via the Timer Link feature for synchronization or event chaining The counters can be frozen in debug mode All have independent DMA request generation and support quadrature encoders e TIM15 16 and 17 They are general purpose timers with mid range features They have 16 bit auto reload upcounters and 16 bit prescalers 15 has 2 channels and 1 complementary channel TIM16 and TIM17 have 1 channel 1 complementary channel All channels can be used for input capture output compare PWM or one pulse mode output The timers can work together via the Timer Link feature for synchronization or event chaining
219. requency ratio 4 3 tw CKL Clock low time fpp 50 MHz 8 10 ns tw CKH Clock high time fpp 50 MHz 8 10 ns CMD D inputs referenced to CK in eMMC mode tisu Input setup time HS fpp 50 MHz 0 ns Input hold time HS fpp 50 MHz 5 ns CMD D outputs referenced to CK in eMMC mode tov Output valid time HS fpp 50 MHz 13 5 15 5 ns tou Output hold time HS fpp 50 MHz 9 ns 1 Guaranteed by characterization results 2 Ci oAD 20pF Figure 34 SDIO high speed mode CK D CMD output D CMD input tf tr 14887 DoclD025977 Rev 4 189 231 Electrical characteristics STM32L486xx Figure 35 SD default mode CK D CMD output ai14888 190 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics USB characteristics The STM32L486xx USB interface is fully compliant with the USB specification version 2 0 and is USB IF certified for Full speed device operation Table 89 USB electrical characteristics Symbol Parameter Conditions Min Typ Max Unit Vppuss _ USB transceiver operating voltage 3 00 2 3 6 V Rpui Embedded USB DP pull up value during idle 900 1250 1600 i Q Hans Embedded USB DP pull up value during 4400 2300 3200 reception 2 3 Driving high ZDRV Output driver impedance and low 28 36 44 Q 1 The STM32L486xx USB functionality is
220. ri Voltage Range 1 and 2 hr IN Data input hold time 6 5 ns Voltage Range 1 11 12 t Data output valid time VS Mt Voltage Range 2 15 19 Voltage Range 1 6 t St Data output hold time MOST AOUT Voltage Range 2 8 1 Guaranteed by characterization results Figure 30 Quad SPI timing diagram SDR mode tw CKH Data output Data input Clock MSv36878V1 Figure 31 Quad SPI timing diagram DDR mode Data output Data input Clock tw CKH tw CKL lick MSv36879V1 q DocID025977 Rev 4 185 231 Electrical characteristics STM32L486xx 186 231 SAI characteristics Unless otherwise specified the parameters given in Table 86 for SAI are derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 22 General operating conditions with the following configuration Output speed is set to OSPEEDRy 1 0 10 e Capacitive load 30 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics CK SD FS Table 86 SAI characteristics Symbol Parameter Conditions Min Max Unit fMCLK SAI Main clock output 50 MHz Master transmitter 2 7 lt Vpp lt 3 6 18 5 Voltage Range 1 Master transmitter 1 71
221. rmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application The main features of the touch sensing controller are the following e Proven and robust surface charge transfer acquisition principle e Supports up to 24 capacitive sensing channels e Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time e Spread spectrum feature to improve system robustness in noisy environments Full hardware management of the charge transfer acquisition sequence e Programmable charge transfer frequency e Programmable sampling capacitor pin e Programmable channel I O e Programmable max count value to avoid long acquisition when a channel is faulty e Dedicated end of acquisition and max count error flags with interrupt capability e One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components e Compatible with proximity touchkey linear and rotary touch sensor implementation e Designed to operate with STMTouch touch sensing firmware library The number of capacitive sensing channels is dependent on the size of the packages and subject to I O availability q DocID025977 Rev 4 STM32L486xx Functional overview 3 21 3 22 q Liquid crystal display controller LCD The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels e Internal step up conver
222. rt G PG9 SPI3 SCK USART1_TX PG10 LPTIM1 IN1 SPI3 MISO USART1 RX PG11 LPTIM1 IN2 SPI3 MOSI USART1 CTS PG12 LPTIM1 ETR SPI3 NSS ani ic PG13 I2C1 SDA USART1 CK PG14 1261 SCL PG15 LPTIM1 OUT I2C1 SMBA PHO Port H PH1 uonduosep uid pue 987 1ZEINLS y ed 2 6 20 LEZ LS Table 17 Alternate function AF8 to AF15 for AF0 to AF7 see Table 16 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UART4 SDMMC1 COMP1 TIM2 TIM15 UARTS CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 UART4 TX SAM EXTCLK TIM2 ETR EVENTOUT PA1 UART4_RX LCD SEGO TIM15 CH1N EVENTOUT PA2 F LCD SEG1 SAI2 TIM15 CH1 EVENTOUT PA3 LCD SEG2 TIM15 CH2 EVENTOUT PA4 SAM FS B LPTIM2 OUT EVENTOUT PA5 gt 2 ETR EVENTOUT PAG QUADSPI_BK1_103 LCD SEG3 TIM16 CH1 EVENTOUT PA7 3 QUADSPI BK1 102 LCD_SEG4 TIM17 1 EVENTOUT pag OTG FS SOF LCD COMO LPTIM2 OUT EVENTOUT PA9 LCD COMI TIM15 BKIN EVENTOUT PA10 OTG FS ID LCD COM2 TIM17 BKIN EVENTOUT PA11 CAN1_RX OTG_FS_DM MS EVENTOUT PA12 OTG
223. s Table 97 Asynchronous multiplexed PSRAM NOR write NWAIT timings 1 2 Symbol Parameter Min Max Unit tw NE FMC_NE low time 9THcLK 0 5 9THcLKt2 tw NWE FMC NWE low time TTucuc1 5 7 1 5 Hs tsu NWAIT_NE FMC_NWAIT valid before FMC_NEx high 6Tucik 2 FMC_NEx hold time after FMC_NWAIT invalid 4TuciK 3 1 CL 30 pF 2 Guaranteed by characterization results Synchronous waveforms and timings Figure 40 through Figure 43 represent synchronous waveforms and Table 98 through Table 107 provide the corresponding timings The results shown in these tables are obtained with the following FMC configuration e BurstAccessMode BurstAccessMode Enable e MemoryType e WriteBurst FMC WriteBurst Enable e CLKDivision 1 DataLatency 1 for NOR Flash DataLatency 0 for PSRAM DoclD025977 Rev 4 199 231 Electrical characteristics STM32L486xx In all timing tables the is the HCLK clock period Figure 40 Synchronous multiplexed NOR PSRAM read timings tw CLK e a tw CLk BUSTURN 0 i FMC_CLK Li i 1 Data latency 0 Id CLIKL NExL td CLKH NExH 1 1 l 1 1 1 1 _ i 1 1 1 td CLKL NADVL ta CLIKL NADVH 1 1 1 1 1 NADV 1 ta CLIKL AV td CUKH AIV FMC A 25 16 1 1 ta CLKL NOEL td CLKH NOEH
224. s have 14 channels in total each dedicated to managing memory access requests from one or more peripherals Each has an arbiter for handling the priority between DMA requests The DMA supports e 14 independently configurable channels requests e Each channel is connected to dedicated hardware DMA requests software trigger is also supported on each channel This configuration is done by software e Priorities between requests from channels of one DMA are software programmable 4 levels consisting of very high high medium low or hardware in case of equality request 1 has priority over request 2 etc e Independent source and destination transfer size byte half word word emulating packing and unpacking Source destination addresses must be aligned on the data size e Support for circular buffer management 3 event flags DMA Half Transfer DMA Transfer complete and DMA Transfer Error logically ORed together in a single interrupt request for each channel e Memory to memory transfer Peripheral to memory and memory to peripheral and peripheral to peripheral transfers e Access to Flash SRAM APB and AHB peripherals as source and destination e Programmable number of data to be transferred up to 65536 Table 7 DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 DocID025977 Rev 4 35 231 Functional overview STM32L486xx 3 14 3 14 1 3 14 2 36 231 Interrup
225. ssion Three transmit mailboxes Configurable transmit priority e Reception Tworeceive FIFOs with three stages 14 Scalable filter banks Identifier list feature Configurable FIFO overrun e Time triggered communication option Disable automatic retransmission mode 16 bit free running timer Time Stamp sent in last two data bytes e Management Maskable interrupts Software efficient mailbox mapping at a unique address space Secure digital input output and MultiMediaCards Interface SDMMC The card host interface SDMMC provides an interface between the APB peripheral bus and MultiMediaCards MMCs SD memory cards and SDIO cards The SDMMC features include the following e Full compliance with MultiMediaCard System Specification Version 4 2 Card support for three different databus modes 1 bit default 4 bit and 8 bit e Ful compatibility with previous versions of MultiMediaCards forward compatibility e Full compliance with SD Memory Card Specifications Version 2 0 e Full compliance with SD I O Card Specification Version 2 0 card support for two different databus modes 1 bit default and 4 bit e Data transfer up to 48 MHz for the 8 bit mode e Data write and read with DMA capability Universal serial bus on the go full speed OTG FS The devices embed an USB OTG full speed device host OTG peripheral with integrated transceivers The USB OTG FS peripheral is compliant with the USB 2 0 spec
226. supply scheme The 10 nF capacitor should be ceramic good quality and it should be placed as close as possible to the chip q DocID025977 Rev 4 163 231 Electrical characteristics STM32L486xx 6 3 18 Digital to Analog converter characteristics Table 69 DAC characteristics Symbol Parameter Conditions Min Typ Max Unit Analog supply voltage for VppA DAC ON 1 8 3 6 VREF Positive reference voltage 1 8 VDDA V V Negative reference _ V REF voltage SSA connected to Vss 5 RL Resistive load DAC output i buffer ON connected to 25 Ro Output Impedance DAC output buffer OFF 9 6 11 7 13 8 kQ Output impedance sample Vpp 2 7 V 2 hold mode output kQ buffer ON Vpp 2 0 V 2 3 5 Output impedance sample Vpp 2 7 V 16 5 Rporr and hold mode output 2 kQ buffer OFF Vpp 20V 18 0 C DAC output buffer ON 50 pF Capacitive load Sample hold mode 0 1 1 Voltage on DAC OUT DAC output buffer ON 0 2 i VpAC OUT output i V DAC output buffer OFF 0 VREF 0 5 LSB 1 7 3 Settling time full scale for Normal mode a 12 bit code transition DAC output 1 LSB 1 6 2 9 between the lowest and buffer ON 2 LSB i 1 55 2 85 the highest input codes CL lt 50 pF SETTLING when DAC OUT reaches gt 5 kO 4 LSB 1 48 2 8 final value 0 5LSB
227. synchronous NWAIT mode DataSetupTime 0x5 BusTurnAroundDuration 0 0 In all timing tables the THCLK is the HCLK clock period q DocID025977 Rev 4 STM32L486xx Electrical characteristics Figure 36 Asynchronous non multiplexed SRAM PSRAM NOR read waveforms tw NE FMC_NOE FMC_NWE A 25 0 1 0 D 15 0 tv NADV NE tw NADV FMC_NADV 1 FMC_NWAIT th NE_NOE tsu Data_NE th NE_NWAIT tsu NWAIT_NE 532753 1 q DocID025977 Rev 4 193 231 Electrical characteristics STM32L486xx Table 90 Asynchronous non multiplexed SRAM PSRAM NOR read timings Symbol Parameter Min Max Unit FMC NE low time 2 0 5 2 0 5 l NOE NE NEx low to NOE low 0 1 tw NOE FMC_NOE low time 2THcLK 0 5 2THcLK 1 th NE_NOE FMC_NOE high to FMC_NE high hold time 0 NEx low to valid 3 5 th A_NOE Address hold time after FMC_NOE high 0 tw BL_NE FMC_NEx low to FMC_BL valid 2 th BL_NOE FMC_BL hold time after FMC_NOE high 0 tsu Data_NE Data to high setup time 1 tsu Data NOE Data to high setup time 0 5 th Data Data hold time after NOE high 0 th Data_NE Data hold time after FMC_NEx high 0 tvNADV_NE FMC_NEx low to
228. ted currents instantaneous values Table 21 Thermal characteristics Symbol Ratings Value Unit Storage temperature range 65 to 150 Tj Maximum junction temperature 150 q DocID025977 Rev 4 97 231 Electrical characteristics STM32L486xx 6 3 Operating conditions 6 3 1 General operating conditions Table 22 General operating conditions Symbol Parameter Conditions Min Max Unit fucik Internal AHB clock frequency 0 80 Internal APB1 clock frequency 0 80 MHz Internal APB2 clock frequency 0 80 Vpp _ Standard operating voltage 3 6 V At least one I O in PG 15 2 used 1 08 3 6 Vppio2 PG 15 2 I Os supply voltage PG 15 2 not used 0 3E V ADC or COMP used 1 62 DAC or OPAMP used 1 8 VppA Analog supply voltage VREFBUF used 24 3 6 V ADC DAC OPAMP COMP 0 VREFBUF not used Vpgar Backup operating voltage 1 55 3 6 V USB used 3 0 3 6 Vppusa USB supply voltage TP 35 V TT_xx I O 0 3 0 3 BOOTO 0 9 Vin input voltage MIN MIN Vpp Vppa V All O except BOOTO and TT xx 0 3 koc rr 5 5 9 LQFP144 625 Power dissipation at LQFP100 476 P 85 C for suffix 6 LOFP64 5 444 mW 105 C for suffix 7 UFBGA132 363 WLCSP72 434 LQFP144 156 LQFP100 119 eo mo jw UFBGA132 90 WLCSP7
229. ter to guarantee functionality and contrast control irrespective of Vpp This converter can be deactivated in which case the VLCD pin is used to provide the voltage to the LCD e Supports static 1 2 1 3 1 4 and 1 8 duty e Supports static 1 2 1 3 and 1 4 bias e Phase inversion to reduce power consumption and EMI e Integrated voltage output buffers for higher LCD driving capability e Upto 8 pixels can be programmed to blink e Unneeded segments and common pins can be used as general I O pins e LCD RAM can be updated at any time owing to a double buffer e The LCD controller can operate in Stop mode Digital filter for Sigma Delta Modulators DFSDM The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels transceivers or alternately 8 internal parallel inputs support The DFSDM peripheral is dedicated to interface the external 2A modulators to microcontroller and then to perform digital filtering of the received data streams which represent analog value on 2A modulators inputs DFSDM can also interface Pulse Density Modulation microphones and perform PDM to PCM conversion and filtering in hardware DFSDM features optional parallel data stream inputs from microcontrollers memory through DMA CPU transfers into DFSDM DFSDM transceivers support several serial interface formats to support various 2A modulators DFSDM digital filter modules perform digital processing according user selecte
230. the Firewall registers Code segment located in Flash or SRAM1 if defined as executable protected area Non volatile data segment located in Flash Volatile data segment located SRAM1 e start address and the length of each segments are configurable code segment up to 1024 Kbyte with granularity of 256 bytes Non volatile data segment up to 1024 Kbyte with granularity of 256 bytes Volatile data segment up to 96 Kbyte with a granularity of 64 bytes e Specific mechanism implemented to open the Firewall to get access to the protected areas call gate entry sequence e Volatile data segment can be shared or not with the non protected code e Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection q DocID025977 Rev 4 STM32L486xx Functional overview 3 7 3 8 3 9 3 9 1 Note Note Note q Boot modes At startup BOOTO pin and BOOT1 option bit are used to select one of three boot options e Boot from user Flash e Boot from system memory e Boot from embedded SRAM The boot loader is located in system memory It is used to reprogram the Flash memory by using USART I2C SPI CAN and USB OTG FS in Device mode through DFU device firmware upgrade Cyclic redundancy check calculation unit CRC The CRC cyclic redundancy check calculatio
231. tion Figure 7 STM32L486Jx WLCSP72 ballout WLCSP72 wmm mmm mim wmm TN mm 21 15 14 OSC32 OUT OSC32 IN PH1 BOOTO OUT PH0 OSC id inl OT MSv35083V7 1 The above figure shows the package top view Figure 8 STM32L486Rx LQFP64 pinout VBAT VDDUSB PC13 vss PC14 OSC32_IN PA13 PC15 OSC32_OUT PA12 PH0 OSC_IN PA11 PH1 OSC_OUT PA10 NRST PA9 PC0 PA8 1 LOFP64 PCO PC2 PC8 PC3 PC7 VSSANREF PC6 VDDA VREF PB15 PAO PB14 PA1 PB13 PA2 PB12 MS31272V4 1 The above figure shows the package top view DoclD025977 Rev 4 59 231 Pinouts and pin description STM32L486xx Table 14 Legend abbreviations used in the pinout table Name Abbreviation Definition Pinname Unless otherwise specified in brackets below the pin name the pin function during and after reset is the same as the actual pin name S Supply pin Pin type Input only pin Input output pin FT 5 V tolerant I O TT 3 6 V tolerant I O B Dedicated BOOTO pin RST Bidirectional reset pin with embedded weak pull up resistor Option for TT or FT I Os Fm capable 409 with LCD function supplied by Vi _u with USB function supplied by Vppusg with Analog switch function supplied by _s supplied only by Vppioz Notes Unless oth
232. ts and events Nested vectored interrupt controller NVIC The devices embed a nested vectored interrupt controller able to manage 16 priority levels and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex 4 The benefits are the following e Closely coupled NVIC gives low latency interrupt processing e interrupt entry vector table address passed directly to the core e Allows early processing of interrupts e Processing of late arriving higher priority interrupts e Support for tail chaining e Processor state automatically saved e Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency Extended interrupt event controller EXTI The extended interrupt event controller consists of 36 edge detector lines used to generate interrupt event requests and wake up the system from Stop mode Each external line can be independently configured to select the trigger event rising edge falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The internal lines are connected to peripherals with wakeup from Stop mode capability The EXTI can detect an external line with a pulse width shorter than the internal clock period Up to 114 GPIOs can be connected to the 16 external interrupt lines q DocID025977 Rev 4 STM32L
233. unter Counter Prescaler Capturel Complementary Timer type Timer request compare resolution type factor outputs generation channels Any integer 2 1 TIM8 16 bit s pd between 1 Yes 4 3 P and 65536 Any integer 2 2 5 32 bit T s between 1 Yes 4 No purp P and 65536 Any integer TIM3 TIM4 16 bit yis s between 1 Yes 4 No purp P and 65536 Any integer 2 15 16 bit Up between 1 Yes 2 1 purp and 65536 Any integer TIM16 17 16 bit Up between 1 Yes 1 1 EE and 65536 Any integer Basic TIM6 TIM7 16 bit Up between 1 Yes 0 No and 65536 3 25 1 Advanced control timer TIM1 TIM8 44 231 The advanced control timer can each be seen as a three phase PWM multiplexed on 6 channels They have complementary PWM outputs with programmable inserted dead times They can also be seen as complete general purpose timers The 4 independent channels can be used for e Input capture e Output compare e PWM generation edge or center aligned modes with full modulation capability 0 100 e One pulse mode output In debug mode the advanced control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs Many features are shared with those of the general purpose TIMx timers described in Section 3 25 2 using the same architecture so the advanced control timers can work together with the TIMx timers via the Timer Link feature for synchronization o
234. up source Consumption Wakeup time Range 1 All 112 2 Run Yes ON Any N A N A Range2 All except OTG FS RNG 100 uA MHz Any to R 1 4 LPRun LPR Yes ON ON except AllexceptOTG FS RNG N A 136 pa MHz 9 8709 s BS PLL to Range 2 64 us Range 1 All i 37 uA MHz 6 cycles Sleep 0 9 Any Range 2 All except OTG FS RNG event 35 uA MHZ 6 cycles Any interrupt LPSleep LPR No except All except OTG FS RNG ny 2 x 40 pA MHz 6 cycles PLL Range 1 BOR PVD PVM RTC LCD IWDG Reset pin all I Os COMPx 1 2 BOR PVD PVM DACx x 1 2 RTC LCD IWDG OPAMPx x 1 2 COMPx 1 2 LSE USARTx 1 5 6 USARTx 1 5 6 0 7 us in SRAM St N Off ON 108 uA i Range 2 LSI LPUART1 LPUART109 ads 4 5 us in Flash I2Cx xe1 3 I2Cx x 1 3 LPTIMx x 1 2 LPTIMx x 1 2 tee FS All other peripherals are swPMti19 frozen XX987 1ZEINLS y ed 2 6 20 LEC ES Table 4 STM32L486 modes overview continued Mode Regulator CPU SRAM Clocks DMA amp Peripherals Wakeup source Consumption Wakeup time BOR PVD PVM RTC LCD IWDG Reset pin all I Os COMPx 1 2 BOR PVD PVM DACx x 1 2 RTC LCD IWDG OPAMPx x 1 2 COMPx x71 p LSE USARTx 1 5 6 1 5 6 6 uA RTC 4 us SRAM PED P L oen LSI UE 1 RAP w RTC ate in Flash I2Cx x
235. up the MCU from Stop mode The wake up events from Stop mode are programmable and can be Start bit detection e received data frame e specific programmed data frame All USART interfaces can be served by the DMA controller Table 12 STM32L4x6 USART UART LPUART features USART modes features USART1 USART2 USART3 UART4 UART5 LPUART1 Hardware flow control for modem X X X X X X Continuous communication using DMA X X X X X X Multiprocessor communication X X X X X X Synchronous mode X X X Smartcard mode X X X Single wire half duplex communication X X X X X X IrDA SIR ENDEC block X X X X X LIN mode X X X X X Dual clock domain X X X X X X Wakeup from Stop 0 Stop 1 modes X X X X X X Wakeup from Stop 2 mode X Receiver timeout interrupt X X X X X Modbus communication X X X X X Auto baud rate detection X 4 modes Driver Enable X X X X X X LPUART USART data length 7 8 and 9 bits 1 X supported DoclD025977 Rev 4 49 231 Functional overview STM32L486xx 3 29 50 231 Low power universal asynchronous receiver transmitter LPUART The device embeds one Low Power UART The LPUART supports asynchronous serial communication with minimum power consumption It supports half duplex single wire communication and modem operations CTS RTS It allows multiprocessor communication The LPUART has a clock domain i
236. utline Updated Table 105 UFBGA132 132 ball 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data DoclD025977 Rev 4 q STM32L486xx IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved q DocID025977 Rev 4 231 231
237. values are measured after internal calibration ADC accuracy vs negative Injection Current Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative current 4 The I O analog switch voltage booster is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG_CFGR1 when VppaA lt 2 4 V It is disable when VppA gt 2 4 V No oversampling 158 231 DoclD025977 Rev 4 q STM32L486xx Electrical characteristics Table 67 ADC accuracy limited test conditions 3 1 02 3 Sym parameter bol Total ET unadjusted error EO Offset error EG Gain error Differential ED linearity error Integral EL linearity error Effective of bits Signal to noise and SINAD distortion ratio SNR Signal to noise ratio q ADC clock frequency lt 80 MHz Sampling rate lt 5 33 Msps 1 65 V lt VDDA VREF lt 3 6 V Voltage scaling Range 1 Conditions Min Typ Max Unit Single Fast channel max speed 5 5 7 5 ended Slow channel max speed 4 5 6 5 Fast channel max speed 4 5 7 5 Differential Slow cha
238. x4000 4 1 USART3 0x4000 4400 0x4000 47FF 1 KB USART2 0x4000 4000 0x4000 43FF 1 KB Reserved 0x4000 3C00 0x4000 3FFF 1 SPI3 0x4000 3800 0x4000 3BFF 1 KB SPI2 0x4000 3400 0x4000 37FF 1KB Reserved 0x4000 3000 0x4000 33FF 1 KB IWDG 0 4000 2 00 0x4000 2FFF 1 KB WWDG APB1 0x4000 2800 0x4000 2BFF 1KB RTC 0x4000 2400 0x4000 27FF 1 KB LCD 0x4000 1800 0x4000 23FF 3 KB Reserved 0x4000 1400 0x4000 17FF 1 0 4000 1000 0x4000 13FF 1 TIM6 0 4000 0 00 0x4000 OFFF 1 TIM5 0x4000 0800 0x4000 OBFF 1 TIM4 0x4000 0400 0x4000 07FF 1 TIM3 0 4000 0000 0x4000 1 TIM2 1 The gray color is used for reserved boundary addresses Ky DoclD025977 Rev 4 93 231 Electrical characteristics STM32L486xx 6 6 1 94 231 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referenced to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and TAmax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maxi
239. xternal clock 32 kHz oscillator and backup registers through power switch when Vpp is not present When the functions supplied by Vppa Vppioa are not used these supplies should preferably be shorted V pp If these supplies are tied to ground the I Os supplied by these power supplies are not 5 tolerant refer to Table 19 Voltage characteristics Vppiox S the I Os general purpose digital functions supply Vppjox represents Vppjo4 or Vppio2 With Vppio1 Vpp Vppio2 Supply voltage level is independent from Vppjo4 DoclD025977 Rev 4 19 231 Functional overview STM32L486xx 3 9 2 20 231 Figure 2 Power supply overview Vppa domain 3 x A D converters Vopa 2 x comparators V 2 x D A converters SSA 2 x operational amplifiers Voltage reference buffer LCD Vi Ac USB transceivers ss Vppi02 domain Vppio2 ring Vss PG 15 2 Vpp domain uo ring Reset block Vcore domain Temp sensor 3 x PLL HSI MSI Core V Standby circuitry ds SS Wakeup logic dd IWDG Digital VcoRE peripherals Voltage regulator ri Low voltage detector Flash memory Backup domain LSE crystal 32 K osc BKP registers RCC BDCR register RTC
240. xx List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 6 231 Device summaty iluie led eek 6 EX e dads adie daa 1 STM32L486xx family device features and peripheral 13 Access status versus readout protection level and execution modes 17 STM32L486 modes 22 Functionalities depending on the working 27 STM32L486xx peripherals interconnect matrix 30 DMA implementation 35 Temperature sensor calibration 38 Internal voltage reference calibration values 38 Timer feature 44 I2C 48 STM32L4x6 USART UART LPUART
241. y is limited to 2 MHz The peripherals with independent clock can be clocked by HSI16 e Low power sleep mode This mode is entered from the low power run mode Only the CPU clock is stopped When wakeup is triggered by an event or an interrupt the system reverts to the low power run mode e Stop 0 Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers All clocks in the VCORE domain are stopped the PLL the MSI RC the HSI16 RC and the HSE crystal oscillators are disabled The LSE or LSI is still running The RTC can remain active Stop mode with RTC Stop mode without RTC Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition Three Stop modes are available Stop 0 Stop 1 and Stop 2 modes In Stop 2 mode most of the VCORE domain is put in a lower leakage mode Stop 1 offers the largest number of active peripherals and wakeup sources a smaller wakeup time but a higher consumption than Stop 2 In Stop 0 mode the main regulator remains ON allowing a very fast wakeup time but with much higher consumption The system clock when exiting from Stop 0 Stop1 or Stop2 modes can be either MSI up to 48 MHz or HS116 depending on software configuration e Standby mode The Standby mode is used to achieve the lowest power consumption with BOR The internal regulator is switched off so that the VCORE domain is powered off The PLL
242. y touch sensors 16x timers 2 x 16 bit advanced motor control 2 x 32 bit and 5 x 16 bit general purpose 2x 16 bit basic 2x low power 16 bit timers available in Stop mode 2x watchdogs SysTick timer Up to 114 fast I Os most 5 V tolerant up to 14 I Os with independent supply down to 1 08 V Datasheet production data WLCSP72 M LQFP144 20 x 20 LQFP100 14 x 14 BOR LQFP64 10 x 10 7 7 UFBGA132 Memories 1 Flash 2 banks read while write proprietary code readout protection 128 KB of SRAM including 32 KB with hardware parity check External memory interface for static memories supporting SRAM PSRAM NOR and NAND memories Quad SPI memory interface 4x digital filters for sigma delta modulator Rich analog peripherals independent supply 3x 12 bit ADC 5 Msps up to 16 bit with hardware oversampling 200 uA Msps 2x 12 bit DAC low power sample and hold 2xoperational amplifiers with built in PGA 2x ultra low power comparators 18x communication interfaces USB OTG 2 0 full speed LPM and BCD 2 SAls serial audio interface 126 FM 1 Mbit s SMBus PMBus 6x USARTs ISO 7816 LIN IrDA modem SPls 4x SPIs with the Quad SPI CAN 2 0B Active and SDMMC interface SWPMI single wire protocol master I F 14 channel DMA controller True random number generator CRC calculation unit 96 bit unique ID AES 128 256 bit key encr
243. yption hardware accelerator Development support serial wire debug SWD JTAG Embedded Trace Macrocell Table 1 Device summary Reference STM32L486xx Part number STM32L486JG STM32L486QG STM32L486RG STM32L486VG STM32L486ZG DoclD025977 Rev 4 1 231 This is information on a product in full production www st com Contents STM32L486xx Contents 1 Introduction 11 2 Description cose e ER orre 12 3 Functional overview 16 3 1 Cortex M4 core with FPU 16 3 2 Adaptive real time memory accelerator ART Accelerator 16 3 3 Memory protection 16 3 4 Embedded Flash memory 17 3 5 Embedded 18 3 6 Firewalle OD dde qe re AC aec Pit dia 18 3 7 Boot modes iode ed obe ite ERE ren eal pe S id 19 3 8 Cyclic redundancy check calculation unit CRC 19 3 9 Power supply management 19 3 9 1 Power supply schemes 19 3 9 2 Power supply supervisor 20 3 9 3 Voltage regulator 21 3 9 4 Low power modes

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