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1. 5 5 give initial values for extension registers initialize system clock and LDAB 50 point EK to bank for register access LDAB 500 point XK to bank 0 TBYK point YK to bank 0 TBZK point ZK to bank 0 LDD 50003 at reset the CSBOOT block size is 512k STD CSBARBT this line sets the block size to 64k LDD 53830 async both byte R W AS Zero WS S U SP IPL all AVEC off STD CSORBT LDAA 57 w 0 1 111111 STAA SYNCR set system clock to 16 78 Mhz CLR SYPCR turn COP software watchdog off Since is on after reset E 1 5 INITRAM ASM m Title INITRAM Description Initialize the HC16 s 1K internal SRAM put SRAM in memory map at 510000 bank 1 and set the stack inside it OC Ck C KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KK KK ko ko kx kx kx Xo INITRAM initialize internal SRAM and stack LDD 50001 STD RAMBAH store high ram array bank 1 LDD 50000 M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL E 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc STD RAMBAL store low ram array CLR RAMMCR enable ram LDAB 501 TBSK set SK to bank 1 for syste
2. PPD DDD 25 2 DDD DD DD DDD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD 2 D D 2 2 HUM MH MH MH MH MH MH HHH MH MH MH MH MH MH HHH MH MH HHH MH MH MH MH MH MH HHH MH MH HHH MH MH MN MM HMM MH MH MH MMH MH MH MH MH MH MMH MH MH MH MH MH HHH MH MH MH HHH MH MH MMH MH YH MH MH MH MH HM MH MH MH MH MH MH MH MH MH MH MN MH MM p u uq up q 42 ee ee eee ed ee eee ee ge ee up ub OG Sg CR SPS GPG IP Sg GPG CoP Seg H CPR tue Gr eb UG I Sum ee ues eb F4 F4 F4 F4 F4 Fd HbA ALR CR ee ee A HRA R A ee ee RA H H ee FH FH FH FH O O Os OO Os O O 70 O O Os OSs Os O O O O O 70 O 7O O O GO OOO O O 20 O OO 0 0 O O O CO Gm cg ug Ue m ug B g u a Gy edo eed sel nnb rte cel cn eet ce eed tre cel moe eel set cel ocn o0 snb
3. 11 6 PWM Frequency Ranges REFERO E FEE ERE REG ON a OS eC NU 11 18 Maximum PUR iue ctr nere Stn ania ne tpm dude deiner cendi A 1 Typical Ratings 2 7 to 3 6V 16 78 MHz Operation A 2 M68HC16 Z SERIES For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc LIST OF TABLES Continued Table Title Page A 3 Typical Ratings 5V 16 78 MHz Operation aia dcionsernpcieasundemeremicntscroannienaiantacnnns A 3 A 4 Typical Ratings 20 97 MHz uiuis aen uat ne erri a Ea EH kia 3 5 cg toxins and do A 4 A 6 Thermal ird cit E T TM A 5 A 7 Low Voltage Clock Control Timing ausu aei aita ine anna ttti iid ao A 6 A 8 1 78 7 Glock Conirol A 7 A 9 20 97 MHz Clock Control HERE REFER ER EDEN A 8 A10 2517 MHz Clock Control Timing 9 11 Low Voltage 16 78 MHz DC A 10 A12 16 78 M Zz DC A 12 CU NE Cr ur accesses A 14
4. D 0 17 0 27 E 0 45 0 75 F 0 17 0 23 G 0 50 BSC J 0 09 0 20 K 0 50 REF P 0 25 5 R1 0 13 0 20 R2 0 13 0 20 5 22 00 5 51 11 00 BSC 22 00 5 11 00 5 0 25 REF 7 1 00 REF 0 09 0 16 8 09 61 09 TE 62 11 13 Figure B 6 Case 918 144 Pin Package Dimensions M68HC16 ZSERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL Go to www freescale com For More Information On This Product B 7 Freescale Semiconductor Inc B 1 Obtaining Updated M68HC16 Z Series MCU Mechanical Information Although all devices manufactured by Freescale conform to current JEDEC standards complete mechanical information regarding M68HC16 Z series microcontrollers is available through Motorola s Design Net To download updated package specifications perform the following steps 1 Visit the Design Net case outline database search engine at http design net com cgi bin cases 2 Enter the case outline number located in Figure B 3 without the revision code for example 831A not 831A 01 in the field next to the search button 3 Download the file with the new package diagram B 2 Ordering Information Use the information in Table B 1 to specify the appropriate device when placing an order Table B 1 M68HC16 Z Series Ordering Information Shaded cells indicate preliminary part numbers P
5. O O CY v E CC Y CY CX era ava C A CY CX CY C Aa ere CY C CX CX CY CY CX Y C CY CY CX CX Y A M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL For More Information On This Product E 10 Go to www freescale com Freescale Semiconductor Inc DC W BD 7241 User Defined Interrupt Vector 186 DC W BD 242 User Defined Interrupt Vector 187 DC W BD 7243 User Defined Interrupt Vector 188 DC W BD 244 User Defined Interrupt Vector 189 DC W BD 7245 User Defined Interrupt Vector 190 DC W BD 7246 User Defined Interrupt Vector 191 DC W BD 247 User Defined Interrupt Vector 192 DC W BD 7248 User Defined Interrupt Vector 193 DC W BD 7249 User Defined Interrupt Vector 194 DC W BD 7250 User Defined Interrupt Vector 195 DC W BD 7251 User Defined Interrupt Vector 196 DC W BD 7252 User Defined Interrupt Vector 197 DC W BD 7253 User Defined Interrupt Vector 198 DC W BD 7254 User Defined Interrupt Vector 199 DC W BD 7255 User Defined Interrupt Vector 200 E 1 4 INITSYS ASM m Title INITSYS T Description Initialize amp configure system including x the Software Watchdog and System Clock
6. TR7 EQU SFD2E 7 SPI TXD RAM 7 TR8 EQU SFD30 SPI TXD RAM 8 TR9 EQU FD32 SPI TXD RAM 9 EQU SFD34 7SPI TXD RAM A TRB EQU SFD36 SPI TXD RAM B TRC EQU SFD38 SPI TXD RAM TRD EQU SFD3A SPI TXD RAM D TRE EQU SFD3C TXD RAM E TRF EQU SFD3E SPI TXD RAM CRO EQU SFD40 SPI CMD RAM 0 CRI EQU FD41 SPI CMD RAM 1 CR2 EQU FD42 SPI CMD RAM 2 CR3 EQU FD43 SPI CMD RAM 3 CR4 EQU FD44 SPI CMD RAM 4 CR5 EQU 5 45 SPI CMD RAM 5 CR6 EQU SFD46 SPI CMD RAM 6 CR7 EQU 5 47 SPI CMD RAM 7 CR8 EQU SFD48 SPI CMD RAM 8 CR9 EQU SFD49 SPI CMD RAM 9 CRA EQU SFD4A 7SPI CMD RAM A CRB EQU SFD4B SPI CMD RAM B CRC EQU SFD4C SPI CMD RAM CRD EQU SFD4D 7SPI CMD RAM D CRE EQU SFD4E SPI CMD RAM E EQU SFD4F SPI CMD RAM MCCI MODULE REGISTERS MCR EQU SFCOO MCCI MODULE CONFIGURATION REGISTER MTEST EQU S FCO2 MCCI TEST REGISTER ILSCI EQU FC04 SCI INTERRUPT LEVEL REGISTER MIVR EQU FC05 MCCI INTERRUPT VECTOR REGISTER ILSPI EQU SFCO6 SPI INTERRUPT LEVEL REGISTER MPAR EQU SFCO9 MCCI PIN ASSIGNMENT REGISTER DDR EQU SFCOB MCCI DATA DIRECTION REGISTER PORTMC EQU SFCOD MCCI PORT DATA REGISTER PORTMCP EQU SFCOF MCCI PORT PIN STATE REGISTER SCCROA EQU SFC18 SCIA CONTROL REGISTER 0 SCCR1A EQU SFC1A SCIA CONTROL REGISTER 1 SCSRA EQU SFC1C SCIA STATUS REGISTER SCDRA EQU SFCIE SCIA DATA REGISTE SCCROB EQU F
7. 10 13 10 4 1 2 10 16 10 4 1 3 5 5 10 16 10 4 2 10 16 10 4 3 Receive Data Pins AXDA RXDB 10 17 10 4 4 Transmit Data Pins TXDA TXDB 10 17 10 4 5 capes ce ea UR UNTER 10 17 10 4 5 1 10 17 10 4 5 2 Seral eae HE 10 18 10 4 5 3 Bawd OCK MT 10 18 10 4 5 4 Rep 10 19 10 4 5 5 Transmiter eT UU 10 19 10 4 5 6 Receiver Operation 0 2 4 10 20 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 10 4 5 7 si iP liri 10 21 10 4 5 8 Receiver Wake Up 10 22 10 4 5 9 10 22 10 5 MCCI Initialization 10 23 SECTION 11 GENERAL PURPOSE TIMER 11 1 E E I EPE E E a 11 1 11 2 GPT Registers and Address 11 2 113 Special Modes of Operation 040 11 3 11 3
8. A 64 A 36 ADC AC Characteristics 5 A 65 A 37 Low Voltage ADC Conversion Characteristics Operating A 66 A 38 Conversion Characteristics 2 A 67 B 1 68 16 Z Series Ordering 200 8 D 1 Module Address 20 244440 00 100 D 1 D 2 E D 4 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Table D 12 Freescale Semiconductor Inc LIST OF TABLES Continued Title Page Show yele BiS E D 6 PU EEEE A EANET D 10 Pon F PN ASSIER tea e ER D 11 Software Watchdog Divide Ballo rie oia deep crt D 12 Porod 0 13 Pit Assignment Field D 16 CSPARO Pin Assignments a ER OE RE HRK D 16 GSFPARI Pirn 0 17 Reset Pin Function 5 10 6 D 17 Block Size Field Bil D 18 Field i ate eee ee D 19 R
9. 9 9 9 3 5 1 Mater MOUS 9 16 9 3 5 2 Master Wrap Around 9 19 9 3 5 3 loco Me T HR 9 20 9 3 5 4 Slave Wrap Around da in E RE RES 9 21 9 3 6 Peripheral Chip Selects Liu ceu aur netter EE anne Exec at ERR 9 21 9 4 Serial Communication Interface 9 21 9 4 1 SCI Loo p M E 9 24 9 4 1 1 e ii MM UU m Uu ntl 9 24 9 4 1 2 Ica MNT 9 24 9 4 1 3 Data Register NEP 9 24 9 4 2 cdd ui mem 9 25 9 4 3 9 25 9 4 3 1 9 25 9 4 3 2 eed 9 25 9 4 3 3 cade idit 9 26 9 4 3 4 ariak 9 26 9 4 3 5 Transmitter 9 27 9 4 3 6 Receiver Operator iini 9 28 9 4 3 7 fie LATS EE 9 29 9 4 3 8 Ne dos Mtm M 9 29 9 4 3 9 Internal Loop Mode 0444222 1 9 30 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page SECTION 10 MULTICHANNEL COMMUNICATION INTERFACE 10 1 pr RERO TTE 10 1 10 2 MCCI Registe
10. MMAM OE OE O V O O O CY v E CC Y CY CX era ava C A CY CX CY C Aa ere CY C CX CX CY CY CX Y C CY CY CX CX Y A M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL For More Information On This Product E 8 Go to www freescale com Freescale Semiconductor Inc CQ c OC OO s LO SO c4 CN OO s 1 SO O00 CO c4 CN OO si 10 OM cc SO O00 CO c4 CN OO O00 CO CO CO CO cd c c c c c oc c oc c CN CN CV CV CN CN CN CN CN CN 0 000000000000000000000 O1 O1 O1 ON Oh cH cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd c H u HH MMH MH MH NH NH MH MH MH MN MH MH MH MH MH NH HHH YH HN NH MH
11. TXD PQS7 ADDR1 FC2 COS PC2 ADDR2 FCLCS4 PC1 VDD VDD VSS VSS ADDR3 FCO CSSIPCO ADDR4 CfsodT ADDR5 DATAO ADDR6 DATAL ADDR7 DATA2 ADDR8 DATA3 VSS VSS ADDR DATA4 ADDR10 DATAS ADDR11 MC68HC16Z1 1 DATA6 ADDR12 68 1671 1 ADDR13 MC68CM16Z1 1 DATA8 ADDR14 MC68HC16Z2 DATA9 ADDR15 MC68HC16Z3 VDD ADDR16 VSS ADDR17 DATA10 ADDR18 ATWLYYWW DATA VDD DATA12 VSS DATA13 VDDA DATA14 VSSA DATA15 ANO PADAO ADDRO 1 DSACROPEO AN2 PADA2 DSACRT PE1 AN3 PADA3 AN4 PADA4 BS PE4 ANS PADAS AS PES VRH VDD BEER 2 n EE 5 NOTES 1 MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATIO N YEAR WEEK HC16Z1 CKZ1 CMZ1 Z2 Z3 132 PIN Figure 3 4 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments for 132 Pin Package M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 7 Go to www freescale com Freescale Semiconductor Inc NmsnonM i MERN Z S E EEEE Eedi HE 54 m dE TET UE TE BESESSATSRRARRAFHATRBRERHSHARRLRRELKRR VRHP R5ppES 11 ANS PADAS AN4 PADA4 metre AN3 PADA3 AN2 PADA2 DSACROPEO 11 1 ADDRO 11 ANO PADAO 15 11 VSSA DATA 11 VDDA DATA13 11 VSS DATA22 11 VDD 1 ADDR18
12. 8 16 8 8 4 Accommodating Positive Negative Stress Conditions 8 18 8 8 5 Analog Input Considerations 2 8 19 8 8 6 Pu 8 21 8 8 6 1 Settling Time for the External Circuit 2 2222 8 22 8 8 6 2 Error Resulting from Leakage 8 23 M68HC16 Z SERIES Freescale Semiconductor Inc USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page SECTION 9 QUEUED SERIAL MODULE 9 1 i LI RN RR NETTE 9 1 9 2 QSM Registers and Address Map nomme ces 9 2 QSM Global Registers CE 9 2 Low Power Stop Mode Operation 9 2 9 2 1 2 9 3 9 2 1 3 QSM Interrupts ies e P een 9 3 9 2 2 GSM Pin Control REgIStErS oe 9 4 9 3 Queued Serial Peripheral Interface 4222 011 9 5 9 3 1 9 6 EUN PN Control T TM 9 6 9 3 1 2 arene 9 7 9 3 2 S lI Rm 9 7 9 3 2 1 Receive RAM 9 7 9 3 2 2 MP S 9 7 9 3 2 3 Command wT 9 8 9 3 3 NEN Rn cemento MINUS 9 8 9 3 4 ro SIRE UT 9 8 9 3 8 QSPI Operating Modes Loir nemen
13. 101010 172 1 34375 3 2 6875 5 375 101011 176 1 375 3 2 75 5 5 101100 180 1 40625 3 2 8125 5 625 101101 184 1 4375 3 2 875 15 79 8 6 4 2 0 8 101110 188 1 46875 376 2 9375 5 875 110000 196 1 53125 392 3 0625 6 125 408 4 2 6 4 2 8 6 4 32 110100 212 1 65625 4 3 3125 848 6 625 110110 220 1 71875 4 3 4375 880 6 875 111000 228 1 78125 4 3 5625 912 7 125 111010 236 1 84375 4 3 6875 944 7 375 44 4 976 52 6 0 0 8 0 111100 2 1 90625 3 8125 7 625 111110 2 1 96875 5 3 9375 1008 7 875 2 3 4 5 6 6 7 8 9 0 110010 204 1 59375 0 3 1875 816 6 375 208 1 625 3 25 8 6 5 2 3 4 4 5 6 7 8 8 9 0 SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 10 For More Information On This Product USER S MANUAL Go to www freescale com escale Semiconductor Inc Table 5 3 20 97 MHz Clock Control Multipliers Shaded cells represent values that exceed 20 97 MHz specifications Modulus Y 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 W X 00 fuco 22x Value a 2 a 2 s T i 2 s s Z s 7 80 625 s s x 112 875 68 16 Z SERIES USER S MANUAL Prescalers
14. ada ener 8 2 8 2 2 Analog Reference Pins Pee T 8 3 8 2 3 Analog Supply PING sani 8 3 8 3 Programmer s Model c 8 3 8 4 ADG BUS uno CTI 8 3 8 5 Special Operating Modes 0 0044 4 nnn 8 3 8 5 1 Low Power Stop ModE auos dud tu baie 8 3 8 5 2 di P0 RU TM 8 4 8 6 Analog SS ee 8 4 8 6 1 i piri TE 8 4 8 6 2 Sample Capacitor and Buffer Amplifier 8 5 8 6 3 RO DAC ARIY T 8 5 8 6 4 seismine 8 6 8 7 Digital Control 8 6 8 7 1 Control Status Registers 8 6 8 7 2 Clock and Prescaler COPION Louisa cen porri Rao a die EE HE a OH ei 8 6 8 7 3 cr ale TME M RI 8 7 8 7 4 eec T 8 7 8 7 5 Conversion Control fee ca 8 7 8 7 5 1 Conversion Paralfilel S 8 8 8 7 5 2 Conversion Modes ku a EH EDU IE a SR GR UE 8 8 8 7 6 res TNI omm 8 12 8 7 7 Successive Approximation Register 8 13 8 7 8 e clic een ener neces S 8 13 8 8 g mee T 8 14 8 8 1 Analog Reference 8 14 8 8 2 8 14 8 8 3 Analog Supply Filtering and Grounding
15. 68 16 Z SERIES USER S MANUAL Freescale Semiconductor 27 222 523 724 25 26 27 420 29 730 31 32 233 734 35 36 29 7 738 739 740 741 742 743 744 745 746 747 748 749 750 251 22 53 754 255 756 758 259 60 564 62 763 64 65 66 767 768 769 770 2 2712 74 Hales Spurious Interrupt DA nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned nassigned Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved In Defi fi rru fi rru rru rru II rru rru rru rru TI rru
16. INIT TEMP EQU 0006 SCCNT EQU 0004 MNCNT EQU 0002 HRCNT EQU 0000 INITSYS LDAB 50 LDAB 500 TBZK LDD 500 STD SIMMCR LDAA 57 STAA SYNCR LDAB 5 0 STAB SYPCR INCLUDE INCLUDE LDD 0638 STD PICR LDD 0110 STD PITR LDD SFFF9 STD CSBAR3 LDD 7801 Autovector STD CSOR3 LDAB SFF STAB PFPAR LDAB 01 TBZK LDZ 0000 LDD 0000 STD SCCNT Z STD MNCNT Z STD HRCNT Z STD TEMP Z LDAB RSR INITSCI start program after interrupt table initialization stuff variable space used in hex to asc routine Stores the current number of seconds stores the current number of minutes Stores the current number of hours following section is normally part of INCLUDE INITSYS ASM but we want to leave the COP on tj point EK to bank F for register access point XK to bank 0 point YK to bank 0 point ZK to bank 0 initialize the SIM MCR this is redundant it happens at reset Set system clock to 16 78 Mhz enable the watchdog COP and set time out period to 8 seconds ASM turn on internal SRAM at 10000 set stack in bank 1 SK 1 SP 03FE ASM set SCI baud rate at 9600 baud enable SCI transmitter and receiver the periodic interrupt at request level 6 amp assign vector 456 address 00070 to it initialize PITR to interrupt every 1 sec initialize Chip Sel Base Reg for Autovector
17. rru rru rru TJ PP OD DPD OD OD JS OD OD VP VP OD e DP YP 23 3S J 5 HH HH HH HH HH HH HH 9 92 092 9 DU Fh p Q O00 00000000000000070 Hd Hi Hi H H HH HH HH p rrup P CLP pf oe CD CU DT n n n n n n n n n n n n n n n n n n n rru CT CT CI CE CF CL CE CT CF Ct CF CL Ct CL CL CF CF CT cr CI Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Vec Level 5 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector COT COT INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product Go to www freescale com E 7 Freescale Semiconductor Inc ANMTN SO CN OO si OM 000 OO si 1 SO si 1
18. 3 1 8 1 3 Standby RAM Ero 0 MT p 3 1 3 1 4 Masked ROM Module MRM MC68HC16Z2 Z3 Only 3 2 3 1 8 Analog to Digital Converter ADC 4 2211 3 2 3 1 6 Queued Serial Module 3 2 3 4 4 Multichannel Communication Interface MCCI MC68HC16Z4 CKZ4 Only visesevsnarcrekserccoanasssanncstenneeeiadaninarnerenenerns 3 2 3 1 8 General Purpose Timer GP T 3 2 3 2 Intermodule Bus A X H 3 2 33 System Block Diagram and Pin Assignment Diagrams 3 2 3 4 Pin Mere 3 11 5 5 zB PR DERE REC EXE D a Far n 3 13 3 6 PERO 3 16 3 7 Address Space Maps Lessossceceqekqeh aen 3 19 SECTION 4 CENTRAL PROCESSOR UNIT 4 1 EET E TR 4 1 4 2 Regeo TAGE sprer nea 4 1 4 2 1 gt ue oo NE 4 3 4 2 2 Maar ete PTT 4 3 4 2 3 Slack PONI Lausanne ter seme tere reiten nil tni idis aree nnb pneu 4 3 4 2 4 Program COUMEN Fete 4 3 4 2 5 Condition Code Register 4 4 4 2 6 Address Extension Register and Address Extension Fields 4 5 M68HC16 Z SERIES USER S MANUAL For More Informat
19. Cycles S MV H EV N Z V C STAB Store B IND8 X 0 IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT E X Y 2 STD Store D IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT Y 2 Se We 0 5 Store IND16 IND16 IND16 2 STED Store Concatenated gt 1 DandE D gt M 2 M 3 DI MDAMDAMDNDAMDAAONADAAHALAARAMWADOAH STS Store Stack Pointer SP gt M M 1 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT STX Store IX gt M M 1 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT STY Store IV gt 1 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT STZ IZ M M 1 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT SUBA Subtract from A IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT Y 2 4 4 4 6 6 6 6 4 4 4 6 6 6 6 4 4 4 6 6 6 6 4 4 4 6 6 6 6 6 6 6 2 6 6 6 6 6 6 6 CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 26 USER S MANUAL For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition C
20. FO Cy CX aaa a aa ae Aaa A G aa Aa a CX O O0 a O A A AAA Aa aA aA Aa AAA a Aaa Aa a Aa a a a HMM HHH MH MH HH MH MH MH MH HHH MH MH MH HHH MH MH MH HHH MH MH MH MH MH HYMN MH MH MH MH MH MH MH MH MH MH MH MH MH HM MM 0 2 2 2 2 2 2 2 2 2 2 2 D ed sf LO SO CN OO s 1 SO s 1 SO CN OO SO si 1 OM c4 CN 0O STW 00 00 00 00 00 00 00 00 lt SP SP SP SP SP SP SP MPO SP LO 0 XO XO iO F F F CO CO CO Cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd c Cr As 36 Y EX 2h Y AG Cs TY A 2s A AG EY As TY Os Cs OQ AO EY An asa
21. 5 7 5 6 SIM LPSTOP PESO 5 22 5 7 SIMLLPSTOP MI ERN 5 23 5 8 System Protection sata DU FREE enn FER HORN 5 24 5 9 Periodic Interrupt Timer and Software Watchdog Timer 5 27 5 10 MCU Basic System ttc 5 30 5 11 5 34 M68HC16 2 SERIES USER S MANUAL For More Information On This Product Go to www freescale com 9 10 9 11 10 1 10 2 10 3 10 4 10 5 Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Title Word Read Cycle Flowchart Write Cycle Flowchart CPU Space Address Encoding Breakpoint Operation Flowchart LPSTOP Interrupt Mask Laval ce titu Bus Arbitration Flowchart for Single Request Preferred Circuit for Data Bus Mode Select Conditioning Alternate Circuit for Data Bus Mode Select Conditioning Power On Reset eene eene nnne Basic MCU System Chip Select Circuit Block Diagram CPU Space Encoding for Interrupt Acknowledge ADC Block Diagram Comersion TIMING RT 10 Bit Conversion Timing Analog Input SR S Errors Resulting from Clipping Star Ground at the Point of Power Supply Origin Inp
22. 7 2 EIE CU Nu MER 7 3 ami MATTER 8 4 Multiplexer Channel SOLITOS uua dedi 8 5 Frescal 8 7 pid 8 7 Conversion Parameters Controlled by 8 8 ADG Conversion 8 8 Single Channel Conversions 0 8 10 Multiple Channel Conversions MULT 1 8 11 xcci ix IRI mmm 8 14 External Circuit Settling Time 10 Bit Conversions 8 23 Error Resulting From Input Leakage 8 23 Effect of DDROS QSM Pin FUNCION Sad tct P ERI 9 4 QSPI PINE MR RM 9 8 Bits Per Tranio Mn mee ee ne nem in Re QUERER dU Fa RT OIRO AP ME 9 18 cafus m 9 26 Effect of Parity Checking on Data Size Luce enr kicker aa aee Ee 9 27 M 10 3 m 18 A 10 4 Sar UR LC errem 10 7 c o is Reenter ean 10 11 10 17 Serial Frame 10 18 Effect of Parity Checking on Data Size 10 19 Cae Fs POR T 11 5
23. D 10 D 2 9 Port F Data Register e seer cease iv D 10 D 2 10 Port P Data Direction Register D 11 D 2 11 Port F Pin Assignment Register 12er errans D 11 D 2 12 System Protection Control Register eet D 12 D 2 13 Periodic Interrupt Control Register D 13 D 2 14 Periodic Interrupt Timer Register 2 4 D 14 D 2 15 Software Watchdog Service Register D 15 D 2 16 Port Data Register KE D 15 D 2 17 Chip Select Pin Assignment Registers D 15 D 2 18 Chip Select Base Address Register D 17 D 2 19 Chip Select Base Address Registers D 17 0 2 20 Chip Select Option Register Boot D 18 0 2 21 Chip Select Option Registers lt D 18 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com TABLE CONTENTS Continued Paragraph Title Page D 2 22 0 22 D223 Test Module Shift Count Register D 22 D 2 24 Test Module Repetition
24. SIZE 89 FORCE PIN DIRECTION OUT PREAMBLE J AM T s TRANSFER Tx BUFFER BREAK J AM Os SHIFT ENABLE J ENABLE TRANSMITTER CONTROL LOGIC aj gt ZEE LOOPS WOMS ILT PT OPEN DRAIN OUTPUT MODE ENABLE DDRQS D7 PIN BUFFER AND CONTROL 5 uL TES 15 SCCR1 CONTROL REGISTER 1 0 15 SCSR STATUS REGISTER 0 INTERNAL DATA BUS A SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 9 10 SCI Transmitter Block Diagram QUEUED SERIAL MODULE 9 22 For More Information On This Product Go to www freescale com 16 32 SCI TX BLOCK M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc RECEIVER BAUD RATE CLOCK DATA PIN BUFFER RECOVERY PARITY DETECT WAKE UP LOGIC B 2 e 15 SCCR1 CONTROL REGISTER 1 0 SBK SCDR Rx BUFFER as READ ONLY sf eles 15 SCSR STATUS REGISTER 0 SCITx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS 16 32 SCI RX BLOCK Figure 9 11 SCI Receiver Block Diagram M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 23 Go to www freescale com Freescale Semiconductor Inc 9 4 1 SCI Registers The SCI programming model includes the QSM global and pin control registers and four SCI registers There are two SCI control regis
25. 5 25 5 4 5 cp Elite de ee EE ane ees keane peace elas 5 25 5 4 6 led rte XU oT 5 27 5 4 7 Interrupt Priority and Vectoring 5 28 5 4 8 Low Power STOP Operation M 5 29 55 External Bus Interface 5 29 5 5 1 SNS MR 5 31 5 9 1 1 Address BUS M t 5 31 55 1 Address SODE P 5 31 55 1 3 Pra e T E M 5 31 5 5 1 4 Dala Stope MOMENT CUP MERC 5 31 5 5 1 9 Reddite ME 5 32 5 9 1 8 civili 5 32 M68HC16 Z SERIES Freescale Semiconductor Inc USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page na Lr A s sic T 5 32 5 5 1 8 Data Size Acknowledge Signals 5 32 55 1 9 Bus Eror naa EEE R 5 33 5 5 1 10 Aat Signal 5 33 25 1 11 Autovector Sianal 5 33 5 5 2 BUS 5 33 54 3 KREEAR 5 35 5 5 4 Pees 5 35 5 5 5 Dperand Tiranelel FOS 5 35 5 6 PUS 5 36 5 6 1 Synchronization to CLKOUT 5 36 5 6 2 Regular Bus Cycle 5 37 5 6 2 1 Med E S A
26. Eom O O C i E CC Y CY CX ara ava Y CY CX CX CY CY CY CX CX CY ea CX CY CX Ora GG CX Y C CY QA INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES USER S MANUAL E 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ed ON 0 si CN OO si 1 OM O00 CN OO si 1 SO CN OO si 1 SO O00 CO CN OO OM 000 OO c4 GN 0O sr 40 00 00 00 00 00 00 00 OO SP SP SP SP SP SP MPO MP LO dO 0 XO XO iO F F CO CO C cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd c cn H u uuu MH MH MH MH NH MH MH MH MH NH MH MH MH HH NH MH MH HH MH NH MH MH MH MH NH HN MH MH MH MN MH MH MH MH HN MH MH MH HN NH MH MH MH MN MN UM
27. REQUEST INTERRUPT INCREMENT WORKING QUEUE POINTER IS WRAP ENABLE BIT ASSERTED RESET WORKING QUEUE POINTER TO NEWQP OR 0000 DISABLE 05 IS HALT HALT QSPI AND OR FREEZE ASSERT HALTA ASSERTED IS INTERRUPT ENABLE BIT HMIE ASSERTED REQUEST INTERRUPT IS HALT OR FREEZE ASSERTED QSPIMSTR3 FLOW 4 Figure 9 7 Flowchart of QSPI Master Operation Part 3 M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 13 Go to www freescale com 9 14 Freescale Semiconductor Inc QSPI CYCLE BEGINS SLAVE MODE IS QSPI DISABLED HAS NEWQP BEEN WRITTEN QUEUE POINTER CHANGED TO NEWQP READ TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS IS SLAVE SELECT PIN ASSERTED EXECUTE SERIAL TRANSFER WHEN SCK RECEIVED STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS WRITE QUEUE POINTER TO CPTQP STATUS BITS QSPISLV1 FLOW 5 Figure 9 8 Flowchart of QSPI Slave Operation Part 1 QUEUED SERIAL MODULE For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc IS THIS THE LAST COMMAND IN THE QUEUE ASSERT SPIF STATUS FLAG IS INTERRUPT ENABLE BIT SPIFIE ASSERTED REQUEST INTERRUPT INCREMENT WORKIN
28. 1 ADDR12 1 ATWLYYWW2 ADDR11 DATA5 1 ADDR10 1 ADDR NCC NC vss 1 VSS 0133 NC 1 ADDR8 DATA2 1 ADDR DATALL _11 ADDR6 DATAO 11 ADDR5 1 ADDR4 FCO CSSiPCO 01 ADDR3 vss 1 VSS VDD 1 VDD FcuCSaPC1 1 ADDR2 FC2 CSSIPC2 01 ADDR1 TXDA PMC7 ERS SSERSESERR ESE 420002092 IY 9 000 00000 225722 run 4 B i 9 NOTES 1 MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK 1674 1674 144 PIN QFP Figure 3 7 MC68HC16Z4 CKZ4 Pin Assignments for 144 Pin Package OVERVIEW M68HC16 Z SERIES 3 10 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 4 Pin Descriptions The following tables are a summary of the functional characteristics of M68HC16 Z series MCU pins Table 3 1 shows all inputs and outputs Digital inputs and outputs use CMOS logic levels An entry in the Discrete I O column indicates that a pin can also be used for general purpose input output or both The I O port designation is giv en when it applies Refer to Figure 3 1 for port organization Table 3 2 shows types of output drivers Table 3 3 shows characteristics of power pins Table 3 1 M68HC16 Z Series Pin Characteristics Pin Output Input Input Discrete Port Mnemonic Driver Synchronized
29. 4 13 2 Exception Stack Frame During exception processing the contents of the program counter and condition code register are stacked at a location pointed to by SK SP Unless it is altered during ex ception processing the stacked PK PC value is the address of the next instruction in the current instruction stream plus 0006 Figure 4 6 shows the exception stack frame Low Address SP After Exception Stacking Condition Code Register High Address Program Counter SP Before Exception Stacking Figure 4 6 Exception Stack Frame Format CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 38 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 13 3 Exception Processing Sequence Exception processing is performed in four phases Priority of all pending exceptions is evaluated and the highest priority exception is processed first Processor state is stacked then the CCR PK extension field is cleared An exception vector number is acquired and converted to a vector address The content of the vector address is load ed into the PC and the processor jumps to the exception handler routine There are variations within each phase for differing types of exceptions However all vectors except RESET are 16 bit addresses and the PK field is cleared during excep tion processing Consequently exception handlers must be located within bank 0 or vectors must point to a j
30. 68 16 Z SERIES USER S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S 7 JMP ea 2 PK PC EXT20 7A zb hh Il 6 IND20 X 4B 29 9999 8 IND20 5B 29 9999 8 IND20 Z 6B 29 9999 8 JSR Jump to Subroutine Push PC EXT20 FA zb hh Il 10 SK SP 0002 2 SK SP IND20 X 89 zg 9999 12 Push CCR IND20 Y 99 zg 9999 12 SK SP 0002 SK SP 020 2 9 zg 9999 12 ea 2 PK PC LBCC Long Branch if Carry If C 0 branch 3784 rrrr 6 4 Clear LBCS2 Long Branch if Carry If C 1 branch 3785 rrrr 6 4 Set LBEQ Long Branch if Equal If Z 1 branch 3787 rrrr 6 4 to Zero LBEV2 Long Branch if EV Set If EV 1 branch 3791 rrrr 6 4 LBGE _ Long Branch if Greater If N 6 V 0 branch 378C rrrr 6 4 Than or Equal to Zero LBGT Long Branch if Greater If Z N V 0 branch 378E rrrr 6 4 Than Zero LBHI 2 Long Branch if Higher If C Z 0 branch 3782 rrrr 6 4 LBLE2 Long Branch if Less If Z 1 branch 378F rrrr 6 4 Than or Equal to Zero LBLS2 Long Branch if Lower If C Z 1 branch 3783 rrrr 6 4 or Same LBLT L
31. AA 61 Low Voltage 8 Bit ADC Conversion Accuracy A 68 B Bit Conversion AGOUEBDM ei itl malla cid A 69 Low Voltage 10 Bit ADC Conversion Accuracy A 70 10 Bit ADC Conversion AOCUIBOM uisu se aedi tu eios irl uad iactu ln A 71 MC68HC16Z21 CKZ1 CMZ1 Z2 Z3 Pin Assignments Oe er Hx NE D aetna B 2 68 1674 74 Pin Assignments for 132 Pin Package B 3 Case 831 01 132 Pin Package Dimensions B 4 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments Usi cx iu s e B 5 68 1674 74 Pin Assignments for 144 Pin Package B 6 Case 918 144 Pin Package Dimensions B 7 CPU16 Register Model 1acecucece rare dari uu rine D 2 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF TABLES Table Title Page 1 1 4c 1 MOUE 1 1 1 2 Z Series MCU Reference Frequencies 4004222 4 220 1 2 3 1 M68HC16 Z Series Pin 2 3 11 3 2 M68HC16 Z
32. CS 10 6 ADDR 23 19 DATA8 AVEC DS AS PORTE SIZ 1 0 IRQ 7 1 MODCLK PORTI DATA11 Normal Operation Reserved MODCLK VCO System Clock EXTAL System Clock BKPT Background Mode Disabled Background Mode Enabled NOTES 1 DATA11 must remain high during reset to ensure normal operation M68HC16 Z SERIES USER S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product Go to www freescale com 5 49 Freescale Semiconductor Inc 5 7 3 1 Data Bus Mode Selection 5 50 For More Information On This Product All data lines have weak internal pull up devices When pins are held high by the in ternal pull ups the MCU uses a default operating configuration However specific lines can be held low externally during reset to achieve an alternate configuration NOTE External bus loading can overcome the weak internal pull up drivers on data bus lines and hold pins low during reset Use an active device to hold data bus lines low Data bus configuration logic must re lease the bus before the first bus cycle after reset to prevent conflict with external memory devices The first bus cycle occurs ten CLKOUT cycles after RESET is re leased If external mode selection logic causes a conflict of this type an isolation re sistor on the driven lines may be required Figure 5 18 shows a recommended method for conditioning the mode select signals DATA15 OUT8 74HC244 74 244
33. MC68HC681 Ce ASYNC BUS PERIPHERAL ADDR 17 1 DATA 15 0 10 kQ 10 kQ ADDR 15 1 DATA 15 8 ADDR 15 1 DATA T 0 NOTES 1 ALL CHIP SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16 BIT eT EINECIR BUS Figure 5 21 Basic MCU System SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 62 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Chip select assertion can be synchronized with bus control signals to provide output enable read write strobe or interrupt acknowledge signals Logic can also generate DSACK and AVEC signals internally A single DSACK generator is shared by all chip selects Each signal can also be synchronized with the ECLK signal available on ADDR23 When a memory access occurs chip select logic compares address space type ad dress type of access transfer size and interrupt priority in the case of interrupt ac knowledge to parameters stored in chip select registers If all parameters match the appropriate chip select signal is asserted Select signals are active low If a chip select function is given the same address as a microcontroller module or an internal memory array an access to that address goes to the module or array and the chip select sig nal is not asserted The external address and data buses do not reflect the internal ac cess All chip select circuits are c
34. Value 100000 4325 kHz 8651 kHz 17302 kHz 34603 kHz 100001 4456 8913 17826 35652 100011 4719 9437 18874 37749 100101 4981 9961 19923 39846 100111 5243 10486 20972 41943 101001 5505 11010 22020 44040 101011 5767 11534 23069 46137 101101 6029 12059 24117 48234 101111 6291 12583 25166 50332 110001 6554 13107 26214 52428 Y 110101 7078 14156 28312 56623 110111 7340 14680 29360 58720 111001 7602 15204 30409 60817 111011 7864 15729 31457 62915 111101 8126 16253 32506 65011 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 111111 8389 16777 33554 67109 SYSTEM INTEGRATION MODULE M68HC16 7 SERIES 9 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 3 3 External Bus Clock The state of the E clock division bit EDIV in SYNCR determines clock rate for the E clock signal ECLK available on pin ADDR23 ECLK is a bus clock for MC6800 devic es and peripherals ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen The clock is enabled by the CS10PA 1 0 field in chip select pin assignment register 1 CSPAR1 operation during low power stop is described in the following paragraph Refer to 5 9 Chip Se lects for more information about the external bus clock 5 3 4 Low Power Operation Low power operation is initiated by the CPU16
35. MH MH MH MH HHH MH MH HHH MH MH MN MM HMM MH MH MH MMH MH MH MH MH MH MMH MH MH MH MH MH HHH MH MH MH HHH MH MH MMH MH YH MH MH MH MH HM MH MH MH MH MH MH MH MH MH MH MN MH MM p u uq up q 42 ee ee eee ed ee eee ee ge ee up ub OG Sg CR SPS GPG IP Sg GPG CoP Seg H CPR tue Gr eb UG I Sum ee ues eb F4 F4 F4 F4 F4 Fd HbA ALR CR ee ee A HRA R A ee ee RA H H ee FH FH FH FH O O Os OO Os O O 70 O O Os OSs Os O O O O O 70 O 7O O O GO OOO O O 20 O OO 0 0 O O O CO Gm cg ug Ue m ug B g u a Gy edo eed sel nnb rte cel cn eet ce eed tre cel moe eel set cel ocn o0 snb cel snc tte cele sey eel eel onn in cb n H H H H H H H H H H H H H H H H H H H
36. PWM Count Register PWM Buffer Register B PWMBUFB YFF92A YFF92C YFF92E YFF93F GPT Prescaler Register PRESCL Reserved NOTES 1 M111 where is the logic state of the MM bit in the SIMCR D 8 1 GPT Module Configuration Register GPTMCR GPT Module Configuration Register YFF900 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STOP FRZ1 FRZO STOPP INCP 0 0 0 SUPV 0 0 0 IARB RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 The GPTMCR contains parameters for configuring the GPT M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL D 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc STOP Stop Clocks 0 GPT clock operates normally 1 GPT clock is stopped FRZ1 Not Implemented FRZO FREEZE Assertion Response 0 Ignore IMB FREEZE signal 1 FREEZE the current state of the GPT STOPP Stop Prescaler 0 Normal operation 1 Stop prescaler and pulse accumulator from incrementing Ignore changes to input pins INCP Increment Prescaler 0 Has no effect 1 If STOPP is asserted increment prescaler once and clock input synchronizers once SUPV Supervisor Unrestricted Data Space This bit has no effect because the CPU16 always operates in supervisor mode IARB 3 0 Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority Each modul
37. 1 register addresses range from FFFO000 to FFFFFF In M68HC16 Z series MCUs ADDR 23 20 follow the logic state of ADDR19 unless externally driven MM corresponds to IMB ADDR23 If MM is cleared the SIM maps IMB modules into address space 7FF000 7FFFFF which is inaccessible to the CPU16 Modules remain inaccessible until reset occurs The reset state of MM is one but the bit can be written once Initialization software should make certain MM remains set SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 2 2 Interrupt Arbitration Each module that can request interrupts has an interrupt arbitration IARB field Arbi tration between interrupt requests of the same priority is performed by serial conten tion between IARB field bit values Contention will take place whenever an interrupt request is acknowledged even when there is only a single request pending For an interrupt to be serviced the appropriate IARB field must have a non zero value If an interrupt request from a module with an IARB field value of 0000 is recognized the CPU16 processes a spurious interrupt exception Because the SIM routes external interrupt requests to the CPU16 the SIM IARB field value is used for arbitration between internal and external interrupts of the same ority The reset value of IARB for the SIM is 1111 and the re
38. 00 5 0000 5 a 5 0000 SY FFA7F FD0000 YFFBOO SRA Bank 7 00000 YFFB07 CONTROL FE0000 BAKM 77 0000 YFFCOO FF0000 paNK 15 05 O FF0000 YFFDFF INTERNAL REGISTERS FFFFFF L V SEF FFF NOTE 1 THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24 BIT IMB ADDRESSES THE CPU16 ADDRESS BUS IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FROM 080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16 S FLAT 20 BIT ADDRESS SPACE THE CPU16 NEED ONLY GENERATE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE 1671 MEM MAP 5 Figure 3 14 MC68HC16Z1 CKZ1 CMZ1 Separate Program and Data Space M68HC16 Z SERIES OVERVIEW USER S MANUAL 3 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 0000 0 RESET INITIAL ZK SK AND PK BANKO 000000 000008 0002 1 RESET INITIAL PC EXCEPTION VECTORS 000008 0004 2 RESET INITIAL SP 010000 0006 3 RESET INITIAL IZ DIRECT PAGE eae 010000 020000 VECTOR VECTOR YPE OF 020000 ADDRESS NUMBER EXCEPTION 0008
39. 10 15 QSM 9 23 operation 9 28 10 20 wakeup 9 29 10 22 registers 9 24 control register 0 MCCI SCCROA B 10 13 D 59 control register 1 MCCI SCCR1A B 10 16 D 60 control registers QSM SCCR 9 24 data register SCDRA B 10 16 D 63 QSM SCDR 9 24 status register SCSRA B 10 16 D 62 QSM SCSR 9 24 serial formats 10 18 transmitter block diagram 10 14 QSM 9 22 operation 9 27 SCIA B 10 2 SCK 9 16 9 20 actual delay before SCK equation 9 17 baud rate equation 9 17 SCSR 9 24 D 43 SCSRA B 10 16 0 62 Select eight conversion sequence mode S8CM 0 32 Send break 5 9 27 10 20 D 42 D 62 Separate program and data space map MC68HC16Z1 CKZ1 CMZ1 3 23 MC68HC162Z2 Z3 3 24 MC68HC16Z4 CKZA 3 25 Sequence complete flag SCF D 36 Serial clock baud rate SPBR D 48 frequency range 4 44 communication interface SCI 9 1 9 21 10 1 10 13 data word 4 44 formats 9 25 10 18 interface clock signal DSCLK 4 44 mode M bit 9 25 10 18 peripheral interface SPI 10 1 10 4 shifter 9 24 9 27 10 19 Set definition 2 6 Settling time 8 22 SFA 11 18 D 75 SFB 11 18 D 75 SHEN 5 47 D 6 Show cycle enable SHEN 5 3 5 47 D 6 operation 5 47 timing diagram A 35 Signal characteristics 3 13 Signature registers RSIGHI LO 7 1 M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Signed fractions 4 6 SIM 5 1 address map D 4 block diagram
40. Clock Low to Data Bus Driven Show Cycle Data Setup Time to Clock Low Show Cycle leci ps Data Hold from Clock Low Show Cycle tscLDH BKPT Input Setup Time BKPT Input Hold Time ns Mode Select Setup Time DATA 15 0 MODCLK BKPT Mode Select Hold Time DATA 15 0 MODCLK BKPT RESET Assertion Time RESET Rise Time 100 CLKOUT High to Phase 1 Asserted CHP4A 101 CLKOUT High to Phase 2 Asserted 2 102 1 Valid to AS or DS Asserted tpivsa 103 Phase 2 Valid to AS or DS Asserted 4 iP2VSN 104 AS or DS Valid to Phase 1 Negated tsaPin 105 AS or DS Negated to Phase 2 Negated tsnPoN NOTES 1 All AC timing is shown with respect to Vi Vj levels unless otherwise noted 2 When an external clock is used minimum high and low times are based on a 50 duty cycle The minimum allowable lxcyc period is reduced when the duty cycle of the external clock varies The relationship between external clock input duty cycle and minimum lxcyc is expressed Minimum period minimum txcHL 50 external clock input duty cycle tolerance ax 0 5 19 2 m 7 3 19 Data Out Hold from Clock High Clock High to Data Out High Impedance 2 R W Asserted to Data Bus Impedance Change ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 26 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor
41. VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 0 RESET INITIAL ZK SK AND PK 9000000 VECTORS 0002 RESET INITIAL PC 0004 RESET INITIAL SP m 0006 RESET INITIAL IZ DIRECT PAGE 010000 0008 4 BKPT BREAKPOINT 000A 5 BERR BUS ERROR 000C 6 SWI SOFTWARE INTERRUPT 020000 77 000 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012 0016 9 UNASSIGNED RESERVED 001 UNINITIALIZED INTERRUPT 5030000 us 0020 10 UNASSIGNED RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 512 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 8040000 aes eee 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002 16 6 INTERRUPT AUTOVECTOR 050000 guks 77 777777 002 17__ LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032 006 19 37 UNASSIGNED RESERVED 0001FE 060000 harg 77717777777 0070 O1FE 38 FF USER DEFINED INTERRUPTS PROGRAM 070000 lu AND DATA SPACE 07FFFF 5080000 UNDEFINED y F7FFFF F80000 BANK8 90000 UNDEFINED YFF700 Y FF73F ROM YFF820 CONTROL YFF83F YFF900 YFF93F YFFA00 FA0000 Mak n 512 SECODUD t ee SY FFAT7F 5 80 a CONTROL Y FFBO7 1 00 05 gt Y FFDFF 20000 Tere FE0000
42. diu teste aAa 5 70 5 10 1 Pin Assignment Registers 5 70 5 10 2 Data Direction 5 70 5 10 3 Dala FISCI 5 71 58 POSUIT TBI oe REO anor ae 5 71 SECTION 6 STANDBY RAM MODULE 6 1 SRAM Register SEP 6 1 6 2 SRAM Array Address Mapping 2 22 2 2 2222 20 000 0000 6 2 6 3 SRAM Array Address Space Type 6 2 6 4 l ji Ree mem 6 2 6 5 Standby and Low Power Stop Operation 6 2 6 6 2 M 6 3 SECTION 7 MASKED ROM MODULE FA MRM pedillef BIDEN 7 1 fu MRM Array Address Mapping Rav a eK xcu 7 1 7 3 MRM Array Address Space 7 2 7 4 hui P o ia aaia 7 2 73 Low Power Stop Mode Operation 7 3 7 6 ROM 7 3 7 4 7 3 M68HC16 2 SERIES USER S MANUAL For More Information On This Product Go to www freescale com TABLE CONTENTS Continued Paragraph Title Page SECTION 8 ANALOG TO DIGITAL CONVERTER 8 1 nde 8 1 8 2 eee eee Pen 8 1 8 2 1 Analog WUE PING
43. Conversion Parameter Description The value of the channel selection field CD CA ADCTL1 determines which multiplexer inputs are used in a conversion sequence There are 16 possible inputs Seven inputs are external pins AN 6 0 and nine are internal Conversion channel A conversion sequence consists of either four or eight conversions The number of conversions in a sequence is determined by the state of the S8CM bit in ADCTL1 Conversion can be limited to a single sequence or a sequence can be performed continuously The state of the SCAN bit ADCTL1 deter mines whether single or continuous conversion is performed Length of sequence Single or continuous conversion Conversion sequence s can be run on a single channel or on a block of four or eight channels Channel conversion is controlled by the state of the MULT bit in ADCTL1 Single or multiple channel conversion 8 7 5 2 Conversion Modes Conversion modes are defined by the state of the SCAN MULT and 58 bits in ADCTL1 Table 8 6 shows mode numbering Table 8 6 ADC Conversion Modes SCAN MULT S8CM Mode 0 0 0 0 0 0 1 1 0 The following paragraphs describe each type of conversion mode Mode 0 A single four conversion sequence is performed on a single input channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate
44. 1 Serial data output from SCIA NOTES 1 SCK is automatically assigned to the SPI whenever the SPI is enabled when the SPE bit in the SPCR1 is set 2 PMC4 and PMC6 function as general purpose I O pins when the corresponding RE bit in the SCI control register SCCROA or SCCROB is cleared 3 PMC5 and PMC7 function as general purpose pins when the corresponding TE bit in the SCI control register SCCROA or SCCROB is cleared REGISTER SUMMARY M68HC16 Z SERIES D 58 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 7 8 MCCI Port Data Registers PORTMC Port Data Register YFFCOC PORTMCP MCCI Port Pin State Register YFFCOE 15 9 8 7 6 5 4 3 2 1 0 RESET U U U U U U U U U Two registers are associated with port MCCI the MCCI general purpose I O port Pins used for general purpose I O must be configured for that function When using port MCCI as an output port after configuring the pins as I O write the first byte to be out put before writing to the MDDR Afterwards write to the MDDR to assign each as either input or output This outputs the value contained in register PORTMC for all pins defined as outputs To output different data write another byte to PORTMC Writes to PORTMC are stored in the internal data latch If any bit of PORTMC is con figured as discrete output the value latched for that bit is driven o
45. 2 1 TXD PQS7 ADDR1 FC2 CS5 PC2 ADDR2 FCUCS4 PC1 VDD VDD VSS VSS ADDR3 FCO CSSIP CO ADDR4 ADDR5 DATAO ADDR6 DATAL ADDR7 DATA2 ADDR8 DATA3 VSS VSS ADDR DATA4 ADDR10 DATAS ADDR11 MC68HC16Z1 1 DATAG ADDR12 MC68CK16Z1 1 DATAT ADDR13 MC68CM16Z1 1 DATA8 ADDR14 MC68HC 1622 DATA9 ADDR15 MC68HC 1623 VDD ADDR16 VSS ADDR17 MMMMM DATA10 ADDR18 ATWLYYWW DATA VDD DATA12 VSS DATA13 VDDA DATA14 VSSA DATA15 ANO PADAO ADDRO 1 DSACROPEO AN2 PADA2 D ACRIPEL AN3 PADA3 AVET PE2 AN4 P ADA4 D5IPE4 ANS PADAS AS PES VRH VDD NOTES 1 MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK MDI GER Figure 1 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments for 132 Package MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z SERIES B 2 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc a 8050 P OI VARNAR SOs ETT NE y S eso HH GR ea Is 222098 th 4 7 BRICSD ADDR1 15 1 FC2 CSSIPC2 ADDR2 14 L1 FC1 CS4 PC1 VDD 113 L 1 VDD VSS 112L 1 vss ADDR3 111 1 FCO CSSIPCO ADDR4 110 1 C580 ADDR5 109771 DATAO ADDR6 108 71 DATA1 ADDR7 107 ADDR8 106 DATA3 VSS 105 1 vss ADDR9 104 D
46. RESET 0 0 0 0 0 0 0 ADCTL1 is used to initiate an A D conversion and to select conversion modes and conversion channel or channels It can be read or written at any time A write to ADCTL1 initiates a conversion sequence If a conversion sequence is already in progress a write to ADCTL1 aborts it and resets the SCF and CCF flags in the ADC status register SCAN Scan Mode Selection 0 Single conversion 1 Continuous conversions Length of conversion sequence s is determined by S8CM MULT Multichannel Conversion 0 Conversion sequence s run on a single channel selected by CD CA 1 Sequential conversions of four or eight channels selected by CD CA Length of conversion sequence s is determined by S8CM S8CM Select Eight Conversion Sequence Mode 0 Four conversion sequence 1 Eight conversion sequence This bit determines the number of conversions in a conversion sequence Table D 28 displays the different ADC conversion modes REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com D 32 Freescale Semiconductor Inc Table D 28 ADC Conversion Mode SCAN MULT S8CM MODE 0 0 0 Single 4 Conversion Single Channel Sequence 0 0 1 Single 8 Conversion Single Channel Sequence 0 1 0 Single 4 Conversion Multichannel Sequence 0 1 1 Single 8 Conversion Multichannel Sequence 1 0 0 Multiple 4 Conversion Single Channel Sequences 1 0 1
47. 12 ECLK Low to Data Hold Write tepHWw 5 ns E13 CS Negated to Data Hold Write tecHw 0 ns E14 Address Access Time Read tEACC ns E15 Chip Select Access Time Read tEACS 195 ns E16 Address Setup Time teas 1 All AC timing is shown with respect to Vj Vj_ levels unless otherwise noted 2 When previous bus cycle is not an ECLK cycle the address may be valid before ECLK goes low 3 Address access time teap tepsR 4 Chip select access time tecsp tepsr M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc un NIN Nel Naf NP NNT Net Nah OD Ne ECLK lt gt RW ADDR 23 0 S7 DATA 15 0 WRITE ABER n D Figure A 15 ECLK Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 44 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 27 Low Voltage QSPI Timing Vip and Voss 2 7 to 3 6 Vo 0 T T to T Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock SCK High or Low Time Master Slave Sequential Transfer Delay Master Slave Does Not Require Deselect Data Setup Time Inputs Master
48. SEND_MIN LDAB JSR SN_COLON LDAB JSR SEND_SEC M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc SCCNT Z 501 560 MINUTES SCCNT Z DISPLAY SCCNT Z MNCNT Z 501 560 HOURS NCNT Z DISPLAY NCNT Z HRCNT Z HRCNT Z 1 lt n RCNT Z DISPLAY HRCNT Z HEXTOASC 5 SEND_CH NCNT Z HEXTOASC S3A SEND_CH increment of seconds decimal adj ust A compare of seconds to 60 if 4 of sec 60 then branch to minute routine if of sec 60 store new of sec send new time to dummy terminal for display return to main loop amp wait for next interrupt advance counter for minutes set 4 of seconds to 0 increment 4 of minutes decimal adj ust A compare of minutes to 60 if 4 of min 60 then branch to hours routine if of min 60 then store new of min send new time to dummy terminal for display return to main loop amp wait for next interrupt advance counter for hours set 4 of mi increment decimal adj store new 4 nutes to 0 of hours ust A of hours compare of hours to 24 if of hou eif of hou send new ti rs 24 then display new time rs 24 then clear of hours me to dummy terminal for display return to m Send Time to Dummy Terminal Routine this routin ain loop amp wait for next interrupt KKKKK e takes what
49. 01 0 0 CLRD Clear D 0000 D 2 9 _ 2 te ue xa 0000 275 2 F 0 100 Clear 000000000 AM 35 0 INH 2787 2 0 0 CLRW Clear a Word in 0000 2 1 IND16 6 0 1 0 0 IND16 6 IND16 2 6 6 IND8 X 6 SS A IND8 Y 6 IND8 Z 6 IMM8 2 IND16 X 6 IND16 Y 6 IND16 Z 6 6 6 6 6 CMPB B to Memory 6 A AAA 6 6 2 IND16 X 6 IND16 Y 6 IND16 Z 6 6 6 6 6 COM One s Complement FF M M or M M 8 0 1 8 8 8 IND16 Y 8 IND16 Z 8 EXT 8 One s Complement A FF A or M gt A EAS SO vd COMB Complement B FF gt or gt 0 1 COMD One s Complement D FFFF D gt D or D gt 2 0 1 COME One s Complement FFFF E or E gt E 2 A 0 1 COMW One s Complement 1 IND16 8 A 0 1 Word M M 1 or M M 1 IND16 Y 8 M M 1 IND16 Z 8 8 M68HC16 Z SERIES USER S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S
50. 01yF T MUXOUT Cin CSAMPLE CsoURCE El C FILTER CMUXIN 1 R 2 R 2 SOURCE FILTER 1 T 0 1 uF sin CsouRCE C FILTER CMUXIN R SOURCE R FILTER CO a 1 T 0 1 uF AL C SOURCE C FILTER CMUXIN R SOURCE R FILTER es l T T 0 1 uF C SOURCE C FILTER MUXIN R SOURCE R FILTER T T C FILTER MUXIN R SOURCE R FILTER AJ pe SIE C FILTER 1 TYPICAL VALUE Cin CSAMPLE 2 Reiter TYPICALLY 10KO 20K O ADC EXT MUX EX Figure 8 9 External Multiplexing of Analog Signal Sources ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 8 8 6 Analog Input Pins Analog inputs should have low AC impedance at the pins Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part Ideally that capacitor should be as large as possible within the practi cal range of capacitors that still have good high frequency characteristics This capac itor has two effects First it helps attenuate any noise that may exist on the input Second it sources charge during the sample period when the analog signal source is a high impedance source Series resistance can be used with the capacitor on an input pin to implement a simple
51. 14 FF0000 gas INTERNAL REGISTERS sFFFFFF NOTE 1 THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24 BIT IMB ADDRESSES THE CPU16 ADDRESS BUS IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FROM 5080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMORY BANKS 15 APPEAR FULLY CONTIGUOUS IN THE CPU16 S FLAT 20 BIT ADDRESS SPACE THE CPU16 NEED ONLY GENERATE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE HC18 22 23 MEM MAP Figure 3 12 MC68HC16Z2 Z3 Combined Program and Data Space Map M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 21 Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 0000 0 RESET INITIAL ZK SK AND PK 000000 VECTORS 0002 RESET INITIAL PC 0004 RESET INITIAL SP BOUM 0006 RESET INITIAL IZ DIRECT PAGE 010000 0008 4 BKPT BREAKPOINT 000A 5 BERR BUS ERROR 000C 6 SWI SOFTWARE INTERRUPT 020000 77 000 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012 001C 9 UNASSIGNED RESERVED 001 F UNINITIALIZED INTERRUPT 5030000 0020 10 UNASSIGNED RESERVED 0022 11__ LEVEL 1 INTERRUPT AUTOVECTOR 512 0024 12 LEVEL2 INTERRUPT AUTO
52. 40 to 85 C MCM16Z3RMFC20 MCM16Z3RMFC20B1 TQFP SPMCM16Z3RCPV16 MCM16Z3RCPV16 MCM16Z3RCPV16B1 SPMCM16Z3RCPV20 25 MHz 2 MCM16Z3RCPV20 MCM16Z3RCPV20B1 SPMCM16Z3RCPV25 MCM16Z3RCPV25 MCM16Z3RCPV25B1 MECHANICAL DATA AND ORDERING INFORMATION For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers Crystal Operating Package Frequency Device Input Voltage Type Temperature MHz Guay 5V MC68HC16Z3 4 MHz 144 Pin 40 to 105 C Order Number RTOS TQFP SPMCM16Z3RVPV16 MCM16Z3RVPV16 MCM16Z3RVPV16B1 SPMCM16Z3RVPV20 MCM16Z3RVPV20 MCM16Z3RVPV20B1 SPMCM16Z3RVPV25 MCM16Z3RVPV25 40 to 125 C MCM16Z3RVPV25B1 SPMCM16Z3RMPV16 MCM16Z3RMPV16 MCM16Z3RMPV16B1 SPMCM16Z3RMPV20 MCM16Z3RMPV20 68 1624 32 kHz 5V 132 Pin 4010 85 C PQFP MCM16Z3RMPV20B1 SPMCK16Z4CFC16 MCK68HC16Z4CFC16 MCK16Z4CFC16B1 SPMCK16Z4CFC20 MCK68HC16Z4CFC20 MCK16Z4CFC20B1 SPMCK16Z4CFC25 40 to 105 C MCK68HC16Z4CFC25 1674 25 1 SPMCK16Z4VFC16 MCK68HC16Z4VFC16 MCK16Z4VFC16B1 SPMCK16Z4VFC20 MCK68HC16Z4VFC20 MCK16Z1VFC20B1 SPMCK16Z4VFC25 MCK68HC16Z4VFC25 40 to 125 C MCK16Z4VFC25B1
53. IN8 TIE INPUTS TIE INPUTS HIGH OR LOW HIGH OR LOW AS NEEDED AS NEEDED DATA BUS SELECT CONDITIONING Figure 5 18 Preferred Circuit for Data Bus Mode Select Conditioning SYSTEM INTEGRATION MODULE M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The mode configuration drivers are conditioned with R W and DS to prevent conflicts between external devices and the MCU when reset is asserted If external RESET is asserted during an external write cycle R W conditioning as shown in Figure 5 18 prevents corruption of the data during the write Similarly DS conditions the mode configuration drivers so that external reads are not corrupted when RESET is asserted during an external read cycle Alternate methods can be used for driving data bus pins low during reset Figure 5 19 shows two of these options The simplest is to connect a resistor in series with a diode from the data bus pin to the RESET line A bipolar transistor can be used for the same purpose but an additional current limiting resistor must be connected between the base of the transistor and the RESET If a MOSFET is substituted for the bipolar transistor only the 1 kO isolation resistor is required These simpler circuits do not of fer the protection from potential memory corruption during RESET assertion as does the circuit shown in Figure 5 18 DATA PIN 9 gt DATA PIN
54. Index register X extension field Index register Y extension field Index register Z extension field Modulo addressing index register X mask Modulo addressing index register Y mask Stop disable control bit overflow indicator carry indicator extended overflow indicator Negative indicator Zero indicator Two s complement overflow indicator Carry borrow indicator Interrupt priority field Saturation mode control bit Program counter extension field Bit not affected Bit changes as specified Bit cleared Bit set Memory location used in operation Result of operation Source data Addition Subtraction or negation two s complement Multiplication Division Greater Less Equal Equal or greater Equal or less Not equal CENTRAL PROCESSING UNIT For More Information On This Product X M M 1 M M 1 X 2 Y 2 20 IMM8 IMM16 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z IND20 X IND20 Y IND20 Z INH IXP REL8 REL16 b ff 9999 Register used operation Address of one memory byte Address of byte at M 0001 Address of one memory word Contents of address pointed to by IX Contents of address pointed to by IY Contents of address pointed to by IZ IX with E offset IY with E offset IZ with E off
55. YFFC1E SCIA Data Register SCDRA 1 Not Used YFFC28 SCIB Control Register 0 SCCROB YFFC2A SCIB Control Register 1 SCCR1B YFFC2C SCIB Status Register SCSRB YFFC2E SCIB Data Register SCDRB 1 Not Used YFFC38 SPI Control Register SPCR YFFC3A Not Used YFFC3C SPI Status Register SPSR YFFC3E SPI Data Register SPDR NOTES 1 M111 where M is the logic state of the module mapping bit in the SIMCR D 7 1 MCCI Module Configuration Register MMCR MCCI Module Configuration Register YFFCOO 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 STOP NOT USED SUPV NOT USED IARB 3 0 RESET 0 1 0 0 0 0 MMCR bits enable stop mode establish the privilege level required to access certain MCCI registers and determine the arbitration priority of MCCI interrupt requests REGISTER SUMMARY M68HC16 Z SERIES 0 54 For More Information This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc STOP Low Power Stop Mode Enable 0 MCCI clock operates normally 1 MCCI clock is stopped When STOP is set the MCCI enters low power stop mode The system clock input to the module is disabled While STOP is set only MMCR reads and writes are guaran teed to be valid Only writes to other MCCI registers are guaranteed valid The SCI re ceiver and transmitter must be disabled before STOP is set To stop the SPI set the HALT bit in SPCRS3 wait until the HALTA flag is set then set ST
56. 0 the current opera tion continues until the final bit in the frame is sent then the preamble is transmitted The TC bit is set at the end of preamble transmission The SBK bit in SCCR1 is used to insert break frames a transmission A non zero integer number of break frames is transmitted while SBK is set Break transmission begins when SBK is set and ends with the transmission in progress at the time either SBK or TE is cleared If SBK is set while a transmission is in progress that transmis sion finishes normally before the break begins To assure the minimum break time toggle SBK quickly to one and back to zero The TC bit is set at the end of break trans mission After break transmission at least one bit time of logic level one mark idle is transmitted to ensure that a subsequent start bit can be detected M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 27 Go to www freescale com Freescale Semiconductor Inc If TE remains set after all pending idle data and break frames are shifted out TDRE and TC are set and TXD is held at logic level one mark When TE is cleared the transmitter is disabled after all pending idle data and break frames are transmitted The TC flag is set and control of the TXD pin reverts to PQSPAR and DDRQS Buffered data is not transmitted after TE is cleared To avoid losing data in the buffer do not clear TE until TDRE is set Some serial co
57. 11 Total operating current is the sum of the appropriate Ipp Isp and Ippa 12 Current measured at maximum system clock frequency all modules active M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 17 Go to www freescale com Freescale Semiconductor Inc 13 The base configuration of the MC68HC16Z1 MC68CK16Z1 MC68HC16Z4 and the MC68CK16Z4 requires 32 768 kHz crystal reference The base configuration of the MC68CM16Z1 MC68HC16Z2 and the MC68HC16Z3 requires a 4 194 MHz crystal reference 14 The RAM module will not switch into standby mode as long as does not exceed Vpp by more than 0 5 volts The RAM array cannot be accessed while the module is in standby mode 15 When is more than 0 3 V greater than Vpp current flows between the Vpp pins which causes standby current to increase toward the maximum transient condition specification System noise on the Vpp and pin can contribute to this condition 16 Power dissipation is measured with the appropriate system clock frequency all modules active Power dissipation can be calculated using the following expression Pp Maximum Vpp Ibp IDDSYN Isp Maximum Ippa lpp includes supply currents for all device modules powered Vpp pins ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 18 USER S MANUAL For More Information On This Produc
58. 4 Current measured at maximum system clock frequency with ADC active 5 Maximum leakage occurs at maximum operating temperature Current decreases by approximately one half A 64 for each 10 C decrease from maximum temperature ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 36 ADC AC Characteristics Operating and 5 0 Vdc 5 for 20 25 MHz 10 for 16 MHz Vss 0 TA within operating temperature range Num Parameter Symbol Min Max Unit 1 ADC Clock Frequency fADCLK 0 5 2 1 MHz 8 Bit Conversion Time 2 faDcLK 1 0 MHz tconv 15 2 us faDcLk 2 1 MHz 7 6 10 Bit Conversion Time 3 fADCLK 1 0 MHz tconv 17 1 us TADCLK 2 1 MHz 8 6 4 Stop Recovery Time ten 10 us NOTES 1 Conversion accuracy varies with rate Reduced conversion accuracy occurs at maximum M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 65 Go to www freescale com Freescale Semiconductor Inc Table A 37 Low Voltage ADC Conversion Characteristics Operating Vpp and Vopa 2 7 to 3 6 Vdc 5 Vss 0 to fADCLK 1 05 MHz Num Parameter Symbol Typical Max Unit 1 8 Bit Resolution 1 Count 12 mV 2 8 Differential Nonlinearity DNL Coun
59. M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 51 Go to www freescale com Freescale Semiconductor Inc DATAS determines the function of the DSACK 1 0 AVEC DS AS and SIZE pins If DATAS is held low during reset these pins are assigned to I O port E determines the function of interrupt request pins IRQ 7 1 and the clock mode select pin MODCLK When DATAS is held low during reset these pins are assigned to I O port F 5 7 3 2 Clock Mode Selection The state of the clock mode MODCLK pin during reset determines what clock source the MCU uses When MODCLK is held high during reset the clock signal is generated from a reference frequency using the clock synthesizer When MODCLK is held low during reset the clock synthesizer is disabled and an external system clock signal must be applied Refer to 5 3 System Clock for more information NOTE The MODCLK pin can also be used as parallel I O pin PFO To pre vent inadvertent clock mode selection by logic connected to port F use an active device to drive MODCLK during reset 5 7 3 3 Breakpoint Mode Selection Background debug mode BDM is enabled when the breakpoint BKPT pin is sam pled at a logic level zero at the release of RESET Subsequent assertion of the BKPT pin or the internal breakpoint signal for instance the execution of the CPU16 BKPT instruction will place the CPU16 in BDM If BKPT is sample
60. Not Implemented LOOPS Loop Mode 0 Normal SCI operation no looping feedback path disabled 1 Test SCI operation looping feedback path enabled The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter When LOOPS is set SCI transmitter output is fed back into the receive serial shifter The TXD pin is asserted idle line Both transmitter and receiver must be enabled prior to entering loop mode WOMS Wired OR Mode for SCI Pins 0 If configured as an output TXD is a normal CMOS output 1 If configured as an output TXD is an open drain output ILT Idle Line Detect Type 0 Short idle line detect start count on first one 1 Long idle line detect start count on first one after stop bit s PT Parity Type 0 Even parity 1 Odd parity PE Parity Enable 0 SCI parity disabled 1 SCI parity enabled M Mode Select 0 10 bit SCI frame 1 start bit 8 data bits 1 stop bit 1 11 bit SCI frame 1 start bit 9 data bits 1 stop bit WAKE Wake Up by Address Mark 0 SCI receiver awakened by idle line detection 1 SCI receiver awakened by address mark last data bit set TIE Transmit Interrupt Enable 0 SCI TDRE interrupts disabled 1 SCI interrupts enabled TCIE Transmit Complete Interrupt Enable 0 SCI TC interrupts disabled 1 SCI interrupts enabled RIE Receiver Interrupt Enable 0 SCI RDRF OR interrupts disabled 1
61. PCS 3 0 Peripheral Chip Select Use peripheral chip select bits to select one or more external devices for serial data transfers More than one peripheral chip select may be activated at a time and more than one peripheral chip can be connected to each PCS pin provided proper fanout is observed PCSO shares a pin with the slave select SS signal which initiates slave mode serial transfers If SS is taken low when the QSPI is in master mode a mode fault occurs M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 53 Go to www freescale com Freescale Semiconductor Inc D 7 Multichannel Communication Interface Module MCCI is used only in the MC68HC16Z4 and the 68 1674 Table D 37 shows the MCCI address map Table D 37 MCCI Address Map Address 15 8 7 0 YFFCOO MCCI Module Configuration Register MMCR YFFCO2 MCCI Test Register MTEST YFFC04 SCI Interrupt Level Register ILSCI MCCI Interrupt Vector Register MIVR YFFCO6 SPI Interrupt Level Register ILSPI Not Used YFFCO8 Not Used MCCI Pin Assignment Register MPAR YFFCOA Not Used Data Direction Register MDDR YFFCOC Not Used MCCI Port Data Register PORTMC YFFCOE Not Used MCCI Port Pin State Register PORTMCP 4 Not Used YFFC18 SCIA Control Register 0 SCCROA 1 SCIA Control Register 1 6 1 YFFC1C SCIA Status Register SCSRA
62. The spurious interrupt monitor asserts internal BERR when an interrupt re quest is acknowledged and no IARB contention occurs BERR assertion termi nates a cycle and causes the MCU to process a bus error exception External devices can assert to indicate an external bus error Halt signal HALT HALT can be asserted by an external device to cause single bus cycle opera tion HALT is typically used for debugging purposes To control termination of a bus cycle for a bus error condition properly DSACK BERR and HALT must be asserted and negated synchronously with the rising edge of CLKOUT This ensures that setup time and hold time requirements are met for the same falling edge of the MCU clock when two signals are asserted simultaneously Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information Ex ternal circuitry that provides these signals must be designed with these constraints in mind or the internal bus monitor must be used Table 5 17 is a summary of the acceptable bus cycle terminations for asynchronous cycles in relation to DSACK assertion M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 43 Go to www freescale com Freescale Semiconductor Inc Table 5 17 DSACK BERR and HALT Assertion Results Type of Control Asserted on Rising Description Termination Signal Edge of State of Result
63. WCOL Write Collision 0 No attempt to write to the SPDR happened during the serial transfer 1 Write collision occurred Clearing WCOL is accomplished by reading the SPSR while WCOL is set and then either reading the SPDR prior to SPIF being set or reading or writing the SPDR after SPIF is set M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 65 Go to www freescale com Freescale Semiconductor Inc MODF Mode Fault Flag 0 Normal operation 1 Another SPI node requested to become the network SPI master while the SPI was enabled in master mode SS input taken low The SPI asserts MODF when the SPI is in master mode MSTR 1 and the SS input pin is negated by an external driver D 7 15 SPI Data Register SPDR SPI Data Register YFFC3E 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 UPPB 7 0 LOWB 7 0 RESET U U U U U U U U U U U U U U U U UPPB Upper Byte In 16 bit transfer mode the upper byte contains the most significant eight bits of the transmitted or received data Bit 15 of the SPDR is the MSB of the 16 bit data LOWB Lower Byte In 8 bit transfer mode the lower byte contains the transmitted or received data MSB in 8 bit transfer mode is bit 7 of the SPDR In 16 bit transfer mode the lower byte holds the least significant eight bits of the data REGISTER SUMMARY M68HC16 Z SERIES D 66 For More Information On This Product USER S MANUAL Go to www frees
64. 11 4 2 GPT Interrupts The GPT has 11 internal sources that can cause it to request interrupt service refer to Table 11 2 Setting bits in TMSK1 and 5 2 enables specific interrupt sources TMSK1 and TMSK are 8 bit registers that can be addressed individually or as one 16 bit register The registers are initialized to zero at reset For each bit in TMSK1 and TMSk2 there is a corresponding bit in TFLG1 and TFLG2 the same bit position TMSk2 also controls the operation of the timer prescaler Refer to 11 7 Prescaler for more information The value of the interrupt priority level IPL 2 0 field in the interrupt control register ICR determines the priority of GPT interrupt requests IPL 2 0 values correspond to MCU interrupt request signals IRQ 7 1 IRQ7 is the highest priority interrupt request signal IRQ1 is the lowest priority signal A value of 96111 causes IRQ7 to be asserted when a GPT interrupt request is made lower field values cause corresponding lower priority interrupt request signals to be asserted Setting field value to 96000 disables interrupts M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL For More Information On This Product 11 5 Go to www freescale com 11 6 For More Information On This Product Freescale Semiconductor Inc Table 11 2 GPT Interrupt Sources Mme Source 0000 Adjusted channel IVBA 0000 0001 Input capture 1 IVBA 0001 2 0010 In
65. 3 22 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 000000 0000 RESET INITIAL ZK SK AND PK BANK 0 5000000 5000009 0002 T RESET INITIAL PC EXCEPTION VECTORS 000008 0004 2 RESET INITIAL SP 010000 3 RESET INITIAL Iz DIRECT PAGE OE COMPONE ee a 010000 020000 VECTOR VECTOR YPE OF 020000 ADDRESS NUMBER EXCEPTION 0008 BKPT BREAKPOINT so3000 rr 830 512 000 TLLEGAL INSTRUCTION 0010 DIVISION BY ZERO 0012 001C UNASSIGNED RESERVED 040000 UNINITIALIZED INTERRUPT BANKS 040000 0020 UNASSIGNED RESERVED 0022 LEVEL T INTERRUPT AUTOVECTOR 050000 0024 LEVEL 2 INTERRUPT AUTOVECTOR 9050000 0026 LEVEL INTERRUPT AUTOVECTOR 0028 LEVEL 4 INTERRUPT AUTOVECTOR 5060000 feaa TT 060000 002E LEVEL 7 INTERRUPT AUTOVECTOR DATA DRRSSICRED RESERVED SPACE 070000 0070 01 38 FF USER DEFINED INTERRUPTS 070000 07FFFF 07FFFF 080000 UNDEFINED UNDEFINED 080000 UNDEFINED UNDEFINED Y FF 700 FTFFFF ADC F7FFFF 80000 YFF73F BANK 8 F80000 F 90000 Banka 7777 F 90000 FA0000 Y FF 900 BANK 10 F A0000 SY FF 93F FB0000 BANK 11 FB0000 512 KBYTE
66. 32 110100 212 1 65625 4 3 3125 848 6 625 110110 220 1 71875 4 3 4375 880 6 875 111000 228 1 78125 4 3 5625 912 7 125 111010 236 1 84375 4 3 6875 944 7 375 44 4 976 52 6 0 0 8 0 111100 2 1 90625 3 8125 7 625 111110 2 1 96875 5 3 9375 1008 7 875 2 3 4 5 6 6 7 8 9 0 110010 204 1 59375 0 3 1875 816 6 375 208 1 625 3 25 8 6 5 2 3 4 4 5 6 7 8 8 9 0 SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 12 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 4 25 17 MHz Clock Control Multipliers Shaded cells represent values that exceed 25 17 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fuco 2 Value Value fuco 22x Value fuco Value Slow Fast Slow Fast 000000 03125 000001 0625 125 32 25 125 09375 000010 000011 125 1875 128 15625 000100 000101 3125 160 1 25 1875 192 000110 000111 128 21825 5625 144 1 125 001000 001001 3125 34375 160 1 25 6875 176 1 375 001010 001011 21875 ERE 4375 112 1 75 192 1 5 001100 001101 40625 104 8125 1 625 4375 112 1 75 001110 001111 46875 120 9375 1 875 128 2 010000 010001 53125 136 1 0625 2 125 5625 144 1 125 2 25 010010 010011 59375 152 1 1875 2 375 160 1 25 2 5 010100 010101 65625 168 1 31
67. Active ERIP NOTES 1 All AC timing is shown with respect to Vi Vj levels unless otherwise noted A 38 ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc CLKOUT FREEZE BKP DSCLK IPIPET DSI 0 050 16 BDM SER Figure A 13 Background Debug Mode Timing Diagram Serial Communication CLKOUT FREEZE IPIPET DSI 16 BDM FRZ TIM Figure A 14 Background Debug Mode Timing Diagram Freeze Assertion M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 39 Go to www freescale com Freescale Semiconductor Inc Table A 23 Low Voltage ECLK Bus Timing Vg and V sgh 2 7 to 3 6 Vdc Vos 0 Vdc T to TuH Num Characteristic Unit E1 ECLK Low to Address Valid ns E2 ECLK Low to Address Hold ns Low to CS Valid CS Delay ns E4 ECLK Low to CS Hold ns E5 CS Negated Width ns E6 Read Data Setup Time ns E7 Read Data Hold Time ns E8 ECLK Low to Data High Impedance ns 9 CS Negated to Data Hold Read ns E10 CS Negated to Data High Impedance teyc E11 ECLK Low to Data Valid Write teyc E12 ECLK Low to Data Hold Write ns E13 CS Negated to Data Hold Write ns E14 Address Access Time Read ns E15 Chip Select Access Time Read ns E16 Address Set
68. Assuming Vay Vn 5 12 V 1 count assuming 10 bit resolution corresponds to 5 mV of input voltage A typical input leakage of 50 nA acting through 100 kO of external series resistance results in an error of less than 1 count 5 0 mV If the source imped ance is 1 and a typical leakage of 50 nA is present an error of 10 counts 50 mV is introduced In addition to internal junction leakage external leakage e g if external clamping di odes are used and charge sharing effects with internal capacitors also contribute to the total leakage current Table 8 11 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance The error is listed in terms of 10 bit counts CAUTION Leakage from the part of 10 nA is obtainable only within a limited tem perature range Table 8 11 Error Resulting From Input Leakage IOFF Source Leakage Value 10 Bit Conversions Impedance 10 nA 50 nA 100 nA 1000 nA 1kQ 0 2 counts 10 KQ 0 1 counts 0 2 counts 2 counts 100 0 2 counts 1 count 2 counts 20 counts M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 23 Go to www freescale com Freescale Semiconductor Inc ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 9 QUEUED SERIAL MODULE This sect
69. BDM the CPU16 ceases to fetch instructions through the data bus and communicates with the development system through a dedicated serial interface 4 14 4 1 Enabling BDM The CPU16 samples the BKPT input during reset to determine whether to enable BDM When BKPT is asserted at the rising edge of the RESET signal BDM operation is enabled BDM remains enabled until the next system reset If BKPT is at logic level one on the trailing edge of RESET BDM is disabled BKPT is relatched on each rising transition of RESET BKPT is synchronized internally and must be asserted for at least two clock cycles before negation of RESET 4 14 4 2 BDM Sources When BDM is enabled external breakpoint hardware and the BGND instruction can cause the CPU16 to enter BDM If BDM is not enabled when a breakpoint occurs breakpoint exception is processed 4 14 4 3 Entering BDM When the CPU16 detects a breakpoint or decodes a BGND instruction when BDM is enabled it suspends instruction execution and asserts the FREEZE signal Once FREEZE has been asserted the CPU16 enables the BDM serial communication hard ware and awaits a command Assertion of FREEZE causes opcode tracking signals IPIPEO and IPIPE1 to change definition and become serial communication signals DSO and DSI FREEZE is asserted at the next instruction boundary after the assertion CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 42 USER S MANUAL For More Information On This Pr
70. Continued Mnemonic Operation Description Address Mode Instruction Condition Codes Opcode Operand XGDZ Exchange D with IZ XGEX Exchange E with IX E IX INH XGEY Exchange E with E XGEZ Exchange E with IZ NOTES 1 CCR 15 4 change according to the results of the operation The PK field is not affected 2 Cycle times for conditional branches are shown in taken not taken order 3 CCR 15 0 change according to the copy of the CCR pulled from the stack 4 PK field changes according to the state pulled from the stack The rest of the CCR is not affected M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 29 Go to www freescale com 4 30 CCR XMSK YMSK MV EV D gt WA Vm Freescale Semiconductor Inc Table 4 3 Instruction Set Abbreviations and Symbols Accumulator A Accumulator M Accumulator B Condition code register Accumulator D Accumulator E Extended addressing extension field MAC multiplicand register MAC multiplier register Index register X Index register Y Index register Z Address extension register Program counter Program counter extension field Stack pointer extension field Multiply and accumulate sign latch Stack pointer
71. DI LDED Load Concatenated 1 and D 2 3 0 LDHI Initialize H and M M 1 x gt HR M M 1 y gt 1R LDS Load SP M M 1 SP IND16 X IND16 Y IND16 Z EXT IMM16 LDX M M 1 gt IX IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT LDY Load IY M M 1 gt 1Y IND16 X IND16 Y IND16 Z EXT LDZ 1 12 IND8 IND8 IND8 2 16 IND16 IND16 IND16 2 68 16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL 4 21 For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S 1 7 LPSTOP Low Power Stop If S 4 20 then STOP else NOP LSR Logical Shift Right IND8 X 8 0 A A IND8 Y 8 IND8 Z 8 IND16 X 8 IND16 Y 8 IND16 Z 8 EXT 8 LSRA Logical Shift Right A INH 2 0 A A LSRB Logical Shift Right B 0 A A LSRD Logical Shift Right D 0 A A LSRE Logical Shift Right E 0 A A LSRW Logical Shift R
72. IO IO O IO O IO COC c E OIL QIV SCC Scc SCS SCD PD PA DD PC PC PC PC PS RO R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC R a Pl Ei Ed EH E Dd PH BH EH pH D pH op RO R1 R2 R3 R4 R5 R6 H H HHHHHUWV WV V VVV Eti Ed Dd Dd Ed DH eL Bi MO IO IO O IO O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO lt Freescale Semiconductor REGISTERS 5 00 MODULE CONFIGURATION REGISTER SFBO2 RAM TEST REGISTER 5 04 RAM BASE ADDRESS HIGH REGISTER 5 06 RAM BASE ADDRESS LOW REGISTER DULE REGISTERS SF820 MASKED ROM MODULE CONFIGURATION REGISTER SF824 ROM ARRAY BASE ADDRESS REGISTER HIGH SF826 ROM ARRAY BASE ADDRESS REGISTER LOW SF828 SIGNATURE REGISTER HIGH SF82A SIGNATURE REGISTER LOW SF830 BOOTSTRAP WORD 0 F832 ROM BOOTSTRAP WORD 1 SF834 BOOTSTRAP WORD 2 SF836 ROM BOOTSTRAP WORD 3 DULE REGISTERS SFCOO QSM MODULE CONFIGURATION REGISTER SFCO2 QSM TEST REGISTER SF
73. IPL 2 0 Interrupt Priority Level This field specifies the priority level of interrupts generated by the GPT IVBA 3 0 Interrupt Vector Base Address Most significant nibble of interrupt vector numbers generated by the GPT Refer to Ta ble D 43 D 8 4 Port GP Data Direction Register Data Register DDRGP PORTGP Port GP Data Direction Register Data Register YFF906 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDGP 7 0 PORTGP RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When GPT pins are used as an 8 bit port DDRGP determines whether pins are input or output and PORTGP holds the 8 bit data DDGP 7 0 Port GP Data Direction Register 0 Input only 1 Output D 8 5 OC1 Action Mask Register Data Register OC1M OC1D OC1 Action Mask Register OC1 Action Data Register YFF908 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OC1M 5 1 0 0 0 OCID 5 1 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All OC outputs can be controlled by the action of OC1 OC1M contains a mask that determines which pins are affected OC1D determines what the outputs are M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 69 Go to www freescale com Freescale Semiconductor Inc OC1M 5 1 OC1 Mask Field OC1M 5 1 correspond to OC 5 1 0 Corresponding output compare pin is not affected by OC1 compare 1 Corresponding output compare pin is affected by OC1 compare OC1D 5 1 OC1 Data Field OC1D 5
74. If Vp is less than the sample am plifier can never transfer a zero value Figure 8 5 shows the results of reference voltages outside the range defined by and At the top of the input signal range is 10 mV lower than This results in a maximum obtainable 10 bit conversion value of 3FE At the bottom of the signal range Vssa is 15 mV higher than Vg resulting in a minimum obtainable 10 bit conversion value of three M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 15 Go to www freescale com Freescale Semiconductor Inc 10 BIT RESULT 0 010 400 230 5100 5110 5120 54130 INPUT IN VOLTS 5 120 V Va 0 V ADC CLIPPING Figure 8 5 Errors Resulting from Clipping 8 8 3 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding Generally digital circuits use bypass capacitors on every Vpp Vss pin pair This applies to analog subsystems or submodules also Equally important as bypassing is the distribution of power and ground Analog supplies should be isolated from digital supplies as much as possible This ne cessity stems from the higher performance requirements often associated with analog circuits Therefore deriving an analog supply from a local digital supply is not recom mended However if for economic reasons digital and analog p
75. In either function each pin must also be programmed as input or output The MCCI data direction register MDDR assigns each MCCI pin as either input or output The MCCI pin assignment register MPAR assigns the MOSI MISO and SS pins as either SPI pins or general purpose I O The fourth pin SCK is automatically assigned to the SPI whenever the SPI is enabled for example when the SPE bit in the SPI control register is set The receiver enable RE and transmitter enable TE bits in the SCI control registers SCCROA SCCROB automatically assign the associ ated pin as an SCI pin when set or general purpose I O when cleared Table 10 2 summarizes how pin function and direction are assigned Table 10 2 Pin Assignments Pin Function Assigned By Direction Assigned By TXDA PMC7 TE bit in SCCROA MMDR7 RE bit in SCCROA MMDR6 TXDB PMC5 TE bit in SCCROB MMDR5 RE bit in SCCROB MMDR4 SS PMC3 SS bit in MPAR MMDR3 SPE bit in SPCR MMDR2 MOSI PMC1 MOSI bit in MPAR MMDR1 MISO bit in MPAR MMDRO 10 3 Serial Peripheral Interface SPI The SPI submodule communicates with external peripherals and other MCUs via a synchronous serial bus The is fully compatible with the serial peripheral interface systems found on othe Freescale devices such as the M68HC11 and M68HC05 fam ilies The SPI can perform full duplex three wire or half duplex two wire transfers Se rial transfer of eight or sixteen bits can begin with the MSB
76. Inc 3 Parameters for an external clock signal applied while the internal PLL is disabled MODCLK pin held low dur ing reset do not pertain to an external reference applied while the PLL is enabled MODCLK pin held high during reset When the PLL is enabled the clock synthesizer detects successive transitions of the reference signal If transitions occur within the correct clock period rise fall times and duty cycle are not critical 4 Address access time 2 5 WS tcHav toicL Chip select access time 2 WS toi sA tpicL Where WS number of wait states When fast termination is used 2 clock bus WS 1 5 Specification 9A is the worst case skew between AS and DS or CS The amount of skew depends on the relative loading of these signals When loads are kept within specified limits skew will not cause AS and DS to fall outside the limits shown in specification 9 6 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles 7 Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads The user is free to use either hold time 8 Maximum value is equal to 2 25 ns
77. OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT MSB OUT 16 QSPI MAST 0 PCS 3 0 OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT 16 QSPI MAST 1 Figure 17 QSPI Timing Master CPHA 1 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 47 Go to www freescale com Freescale Semiconductor Inc 55 INPUT SCK CPOL 0 MSB OUT MOSI INPUT MSB IN LSB IN MSB IN 16 QSPI SLV CPHAO OUTPUT 16 QSPI SLV CPHA1 Figure 19 QSPI Timing Slave CPHA 1 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com A 48 Freescale Semiconductor Inc Table A 29 Low Voltage SPI Timing Vin and Voss 2 7 to 3 6 Vo 0 T T to Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock SCK High or Low Time Master Slave Sequential Transfer Delay Master Slave Does Not Require Deselect Data Setup Time Inputs Master Slave Data Hold Time Inputs Master Slave Slave MISO Disable Time Data Valid after SCK Edge Master Slave Data Hold Time Outputs Master Slave Rise Tim
78. PWMA and PWMB can be used for discrete output but are not part of an I O port Table 3 2 M68HC16 Z Series Driver Types Type 1 0 Description A Three state capable output signals Aw Type A output with weak p channel pull up during reset Three state output that includes circuitry to pull up output before high impedance is established to ensure rapid rise time Bo output that be operated an open drain mode OVERVIEW M68HC16 Z SERIES 3 12 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 3 M68HC16 Z Series Power Connections Pin Mnemonic Description VsTBY Standby RAM power VDDSYN Clock synthesizer power Vppa Vssa A D converter power A D reference voltage Vss Vpp Microcontroller power 3 5 Signal Descriptions The following tables define the M68HC16 Z series MCU signals Table 3 4 shows sig nal origin type and active state Table 3 5 describes signal functions Both tables are sorted alphabetically by mnemonic MCU pins often have multiple functions More than one description can apply to a pin Table 3 4 M68HC16 Z Series Signal Characteristics Signal MCU Signal Active Name Module Type State ADDR 23 0 SIM Bus Serial Clock Serial Data Serial Data 0 CPU16 Output Output IRQ 7 1 SIM Input M68HC16 Z SERIES OVERV
79. Refer to 5 9 4 Chip Select Reset Operation for more detailed information The CSBOOT signal is enabled out of reset The state of the DATAO line during reset determines what port width CSBOOT uses If DATAO is held high either by the weak internal pull up driver or by an external pull up device 16 bit port size is selected If DATAO is held low 8 bit port size is selected A pin programmed as a discrete output drives an external signal to the value specified in the port C register No discrete output function is available on CSBOOT BR BG or BGACK ADDR23 provides the output rather than a discrete output signal When a pin is programmed for discrete output or alternate function internal chip select logic still functions and can be used to generate DSACK or AVEC internally on an ad dress and control signal match 5 9 1 2 Chip Select Base Address Registers Each chip select has an associated base address register A base address is the low est address in the block of addresses enabled by a chip select Block size is the extent of the address block above the base address Block size is determined by the value contained in BLKSZ 2 0 Multiple chip selects assigned to the same block of address es must have the same number of wait states BLKSZ 2 0 determines which bits in the base address field are compared to corre sponding bits on the address bus during an access Provided other constraints deter mined by option re
80. SO 000 CO CN OO si i OM O00 c4 CN 0O sr 40 CI CN CN CV CN CV 00 00 00 00 00 00 00 0 0 sP SP SP SP SP SP 101010 010 10 01 XO XO OO D H u uu MH MH MH MH MH MN MH MH MH MH HN MH MH MH HH NH MH MH MH HN MH MH MH MH MH HN HHH HN MH MH MH MH HN MH MH MH HN NH MH MY MH MN MN YM OM OO0OOO0000000000000000000000000000000000000000000000000000 19 p S97 SES Ser SIS age NE ure epus qoo pu SED sep aper eps depen opea opu TENS spe epus 2 opu tat opu sper Eg ope 9 42 399 29 utc YHOO YD VD gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt pq 426 4339 qo 436 42 0 aq 9420 4D 49 ce up d op BS 492949 cg 430 420 0 0 49
81. SPMCK16Z4MFC16 MCK68HC16Z4MFC16 MCK16Z4MFC16B1 20 MHz 2 SPMCK16Z4MFC20 36 MCK68HC16Z4MFC20 180 MCK16Z4MFC20B1 M68HC16 ZSERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL B 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers uantity 68 1674 5V 144 Pin 40 to 85 C SPMCK16Z4CPV16 MCK16Z4CPV16B1 MCK68HC16Z4CPV20 SPMCK16Z4CPV25 MCK16Z4CPV25B1 MCK68HC16Z4VPV16 SPMCK16Z4VPV20 MCK16Z4VPV20B1 MCK68HC16Z4VPV25 40 to 125 C SPMCK16Z4MPV16 MCK16Z4MPV16B1 MCK68HC16Z4MPV20 2 7V 40 to 85 C SPMCCK16Z4CFC16 MCCK16Z4CFC16B1 MC68CK16Z4CPV16 MECHANICAL DATA AND ORDERING INFORMATION 68 16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX C DEVELOPMENT SUPPORT This section serves as a brief reference to Freescale development tools for M68HC16 Z series microcontrollers Information provided is complete as of the time of publication but new systems and software are continually being developed In addition there is a growing number of third party tools available The FreescaleMicrocontroller Development Tools Directory MCUDEVTLDIR D Revision 3 provides an up to date list of development tools Con
82. Slave Data Hold Time Inputs Master Slave Slave MISO Disable Time Data Valid after SCK Edge Master Slave Data Hold Time Outputs Master Slave Rise Time Input Output Fall Time Input Output NOTES 1 Refer to notes in Table A 28 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 45 Go to www freescale com Freescale Semiconductor Inc Table A 28 QSPI Timing and V 5 0 Vdc 5 for 16 78 MHz 10 for 20 25 MHz Vaa 0 Vdc T T to T y DD 55 A DDSYN Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock SCK High or Low Time Master Slave Sequential Transfer Delay Master Slave Does Not Require Deselect Data Setup Time Inputs Master Slave Data Hold Time Inputs Master Slave Slave MISO Disable Time Data Valid after SCK Edge Master Slave Data Hold Time Outputs Master Slave Rise Time Input Output Fall Time Input Output NOTES 1 All AC timing is shown with respect to Vi Vij levels unless otherwise noted 2 For high time n External SCK rise time for low time n External SCK fall time ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 46 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc PCS 3 0
83. The SCK signal remains inactive for the first half of the first SCK cycle Data is latched on the first and each succeeding odd clock edge and the SPI shift register is left shifted on the second and succeeding even clock edg es SPIF is set at the end of the eighth SCK cycle When CPHA equals zero the SS line must be negated and reasserted between each successive serial byte If the slave writes data to the SPI data register while SS is as serted low a write collision error results To avoid this problem the slave should read bit three of PORTMCP which indicates the state of the SS pin before writing to the SPDR again M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL For More Information On This Product 10 9 Go to www freescale com Freescale Semiconductor Inc 10 3 4 2 CPHA 1 Transfer Format Figure 10 4 is a timing diagram of an 8 bit MSB first SPI transfer in which CPHA equals one Two waveforms are shown for SCK one for CPOL equal to zero and an other for CPOL equal to one The diagram may be interpreted as a master or slave timing diagram since the SCK MISO and MOSI pins are directly connected between the master and the slave The MISO signal shown is the output from the slave and the MOSI signal shown is the output from the master The SS line is the slave select input to the slave SCK CYCLE _ 2 o s egre SCK CPOL 0 t SCK CPOL 1 AR FROM MASTER X6 X5 X
84. W X 01 W X 10 W X 11 fuco Value fuco 2 x Value fvco Value Slow Fast Slow Fast 8 625 16 125 32 25 5 32 25 64 5 128 1 40 3125 80 625 160 1 25 48 375 96 75 192 1 5 72 5625 144 1 125 288 2 25 80 625 160 1 25 320 2 5 88 6875 176 1 375 352 2 75 112 1875 224 1 75 448 3 5 240 1 875 480 3 75 288 2 25 576 4 5 304 2 375 608 4 75 320 2 5 640 5 368 2 875 736 5 75 200 1 5625 400 3 125 800 6 25 224 1 75 448 3 5 896 7 232 1 8125 464 3 625 928 7 25 256 2 512 4 1024 8 SYSTEM INTEGRATION MODULE 5 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 3 20 97 MHz Clock Control Multipliers Continued Shaded cells represent values that exceed 20 97 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fuco 2 x Value fyco Value fuco 2 x Value fuco Value Y Slow Fast Slow Fast 100000 132 1 03125 264 2 0625 528 4 125 100010 140 1 09375 280 2 1875 560 4 375 100100 148 1 15625 296 2 3125 592 4 675 100110 156 1 21875 312 2 4375 624 4 875 101000 164 1 28125 3 2 5625 656 5 125 688 704 720 736 752 3 768 784 800 101010 172 1 34375 3 2 6875 5 375 101011 176 1 375 3 2 75 5 5 101100 180 1 40625 3 2 8125 5 625 101101 184 1 4375 3 2 875 15 79 8 6 4 2 0 8 101110 188 1 46875 376 2 9375 5 875 110000 196 1 53125 392 3 0625 6 125 408 4 2 6 4 2 8 6 4
85. and fields 8 7 2 Clock and Prescaler Control 8 6 The ADC clock is derived from the system clock by a programmable prescaler ADC clock period is determined by the value of the PRS field in ADCTLO The prescaler has two stages The first stage is a 5 bit modulus counter It divides the system clock by any value from two to 32 PRS 4 0 00000 to 11111 The second stage is a di vide by two circuit Table 8 3 shows prescaler output values ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 8 3 Prescaler Output Minimum Maximum PRS 4 0 ADC Clock System Clock System Clock 9500000 Reserved 9600001 System Clock 4 2 0 MHz 8 4 MHz 2600010 System Clock 6 3 0 MHz 12 6 MHz 960001 1 System Clock 8 4 0 MHz 16 8 MHz 9611101 System Clock 60 30 0 MHz 9611110 System Clock 62 31 0 MHz 9611111 System Clock 64 32 0 MHz ADC clock speed must be between 0 5 MHz and 2 1 MHz The reset value of the PRS field is 9600011 which divides a nominal 16 78 MHz system clock by eight yielding maximum ADC clock frequency There are a minimum of four IMB clock cycles for each ADC clock cycle 8 7 3 Sample Time The first two portions of all sample periods require four ADC clock cycles During the third portion of a sample period the selected channel is connected directly to the RC DAC array for a specifi
86. before the first instruction of the exception handler is executed 2 When one or more bus errors occur before the first instruction after a RESET exception is executed Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed Immediately after assertion of a second BERR the MCU halts and drives the HALT line low Only a reset can restart a halted MCU However bus arbitration can still oc cur Refer to 5 6 6 External Bus Arbitration for more information A bus error or ad dress error that occurs after exception processing has been completed during the execution of the exception handler routine or later does not cause a double bus fault The MCU continues to retry the same bus cycle as long as the external hardware re quests it 5 6 5 3 Halt Operation When HALT is asserted while BERR is not asserted the MCU halts external bus ac tivity after negation of DSACK The MCU may complete the current word transfer in progress For a long word to byte transfer this could be after S2 or S4 For a word to byte transfer activity ceases after S2 Negating and reasserting HALT according to timing requirements provides single step bus cycle to bus cycle operation The HALT signal affects external bus cycles only so that a program that does not use external bus can continue executing During dy namically sized 8 bit transfers external bus a
87. equate external bypass capacitors should be placed as close as possible to the VppsvN Pin to assure a stable operating frequency When an external system clock signal is applied and the PLL is disabled Vppsyn should be connected to the Vpp supply A voltage controlled oscillator VCO in the PLL generates the system clock signal To maintain 50 clock duty cycle the VCO frequency fyco is either two or four times the system clock frequency depending on the state of the X bit in SYNCR The clock signal is fed back to a divider counter The divider controls the frequency of one input to a phase comparator The other phase comparator input is a reference signal either from the crystal oscillator or from an external source The comparator generates a con trol signal proportional to the difference in phase between the two inputs This signal is low pass filtered and used to correct the VCO output frequency Filter circuit implementation can vary depending upon the external environment and required clock stability Figure 5 5 shows two recommended system clock filter net works XFC pin leakage must be kept as low as possible to maintain optimum stability and PLL performance NOTE The standard filter used in normal operating environments is a single 0 1 uf capacitor connected from the XFC to the Vppsyy supply pin An alternate filter can be used in high stability operating environ ments to reduce PLL jitter under noisy system conditi
88. except for CSBTPA 1 0 are shown in Table D 8 M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 15 Go to www freescale com Freescale Semiconductor Inc Table D 8 Pin Assignment Field Encoding CSxPA 1 0 Description 00 Discrete output 01 Alternate function 10 Chip select 8 bit port 11 Chip select 16 bit port NOTES 1 Does not apply to the CSBOOT field This register contains seven 2 bit fields that determine the function of corresponding chip select pins Bits 15 14 are not used These bits always read zero writes have no effect CSPARO bit 1 always reads one writes to CSPARO bit 1 have no effect The alternate functions can be enabled by data bus mode selection during reset This reg ister may be read or written at any time After reset software may enable one or more pins as discrete outputs Table 0 9 shows CSPARO pin assignments Table D 9 CSPARO Pin Assignments CSPARO Field Chip Select Signal Alternate Signal Discrete Output CS5PA 1 0 CS5 PC2 CS4PA 1 0 CS4 FC1 1 CS3PA 1 0 CS3 PCO CS2PA 1 0 CS2 BGACK CSOPA 1 0 CSO CSBTPA 0 CSBOOT CSPAR1 Chip Select Pin Assignment Register 1 YFFA46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CS10PA 1 0 CS9PA 1 0 CS8PA 1 0 57 1 0 CS6PA 1 0 DATA DATA DATA DATA 7 6 7 5 7 4 7 3 0 0 0 0 0 0 DAT 1 NOTES 1 Refer to Ta
89. follow the state of ADDR19 in the MCU 5 5 4 Misaligned Operands The CPU16 uses a basic operand size of 16 bits An operand is misaligned when it overlaps a word boundary This is determined by the value of ADDRO When ADDRO 0 an even address the address is on a word and byte boundary When ADDRO 1 an odd address the address is on a byte boundary only A byte operand is aligned at any address a word or long word operand is misaligned at an odd address The largest amount of data that can be transferred by a single bus cycle is an aligned word If the MCU transfers a long word operand through a 16 bit port the most signif icant operand word is transferred on the first bus cycle and the least significant oper and word is transferred on a following bus cycle The CPU16 can perform misaligned word transfers This capability makes it compati ble with the M68HC11 CPU CPU16 treats misaligned long word transfers as two misaligned word transfers 5 5 5 Operand Transfer Cases Table 5 16 shows how operands are aligned for various types of transfers OPn en tries are portions of a requested operand that are read or written during a bus cycle and are defined by 171 5120 and ADDRO for that bus cycle M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 35 Go to www freescale com Freescale Semiconductor Inc Table 5 16 Operand Alignment Current Cycle 1 Byte to 8 b
90. in base 10 and Vector Description DC W BD 74 Breakpoint BKPT DC W BD 75 Bus Error BERR DC W BD 76 Software Interrupt SWI DC W BD 7 11 1 Instruction DC W BD 8 Divide by Zero DC W BD 9 Unassigned Reserved DC W BD 10 Unassigned Reserved DC W BD 11 Unassigned Reserved DC W BD 12 Unassigned Reserved DC W BD 713 Unassigned Reserved DC W BD 714 Unassigned Reserved DC W BD 215 Uninitialized Interrupt DC W BD 21 6 Unassigned Reserved DC W BD Level 1 Interrupt Autovector DC W BD 718 Level 2 Interrupt Autovector DC W BD 219 Level 3 Interrupt Autovector DC W BD 720 Level 4 Interrupt Autovector INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 6 USER S MANUAL For More Information On This Product Go to www freescale com DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC gt gt gt gt gt 2222 22 22222 222 22 222 22222 222282 UJ UU UJ UJ UJ UJ UU UJ UJ UU UJ UU UJ UJ UU UJ UU UU UJ UU UJ UJ UU UJ UU UU UJ UU UJ UU CU UJ UU UJ 5 5 5 5 5 5 OOO OS Oe OOO OOS Oe OOS tS
91. is determined by SYNCR W and Y bit values The SYNCR X bit controls a di vide by two circuit that is not in the synthesizer feedback loop When X 0 the divider is enabled and fsys fyco 4 When X 1 the divider is disabled and fsys fyco 2 X must equal one when operating at maximum specified fsys 7 This parameter is periodically sampled rather than 100 tested 8 Assumes that a low leakage external filter network is used to condition clock synthesizer input voltage Total external resistance from the XFC pin due to external leakage must be greater than 15 MQ to guarantee this specification Filter network geometry can vary depending upon operating environment 9 Proper layout procedures must be followed to achieve specifications 10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi mum fys Measurements are made with the device powered by filtered supplies and clocked by a stable exter nal clock signal Noise injected into the PLL circuitry via Vppsyw and Vgg and variation in crystal oscillator frequency increase the Jak percentage for a given interval When jitter is a critical constraint on control system operation this parameter should be measured during functional testing of the final system M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 9 Go to www freescale com Freescale Semiconductor Inc Table A
92. on an IACK cycle A24 A11 SFFF8 sz 8K initialize Chip Sel Option Reg for asynchronous any Interrupt Priority Level Set port F pins to be IRQ pins this is redundant it happens at reset set zk nibble to bank 1 for variable access index those variables from 10000 clear sccnt register clear mncnt register clear hrent register clear save variable space find out who caused the last reset M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL Go For More Information On This Product E 19 to www freescale com Freescale Semiconductor Inc choose which string start address to load caused the reset did not cause the reset print the string to the screen Set interrupt priority mask level to 0 on looping until watchdog causes a reset or we get some other interrupt subroutine to send out the entire ASCII get next byte in string as pointed to by IX if B 00 then we re don go send out the byte increment IX to point to the next byte loop back and do next byte in string go back to whence we came subroutine to send out one byte to SCI read SCI status reg to check clear TDRE check only the TDRE flag bit if TDR is not empty go back bit to check it clear to send a full word to SCDR transmit one ASCII character SFFCOI to the screen Ir test
93. the multiplexer output is connected to the sample capacitor at the input of the sample buffer amplifier for the first two ADC clock cycles of the sampling period The sample amplifier buffers the input channel from the relatively large capacitance of the RC DAC array During the second two clock cycles of a sampling period the sample capacitor is dis connected from the multiplexer and the sample buffer amplifier charges the RC DAC array with the value stored in the sample capacitor During the third portion of a sampling period both sample capacitor and buffer ampli fier are bypassed and multiplexer input charges the DAC array directly The length of this third portion of a sampling period is determined by the value of the STS field in ADCTLO 8 6 3 RC DAC Array The RC DAC array consists of binary weighted capacitors and a resistor divider chain The array performs two functions it acts as a sample hold circuit during conversion and it provides each successive digital to analog comparison voltage to the compara tor Conversion begins with MSB comparison and ends with LSB comparison Array switching is controlled by the digital subsystem M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 5 Go to www freescale com Freescale Semiconductor Inc 8 6 4 Comparator The comparator indicates whether each approximation output from the RC DAC array during resolution is higher or lower
94. wn eH gt wn a gt CLKOUT ADDR 23 0 FC 2 0 1Z 1 0 as HHE in 2 RAV A DATA 15 0 pc pss IPIPEO PHASE 2 c gt to m 1 of al Je Ime cS NEIN qt 16 FAST RD CYC Figure A 6 Fast Termination Read Cycle Timing Diagram M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product Go to www freescale com A 31 32 Freescale Semiconductor Inc CLKOUT ADDR 23 0 FC 1 0 SIZ 1 0 m wl RAV DATA 15 0 E IPIPEO 16 FAST WR CYC TIM Figure A 7 Fast Termination Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc wn gt wn wn w gt wn a wn o gt gt gt CLKOUT ADDR 23 0 DATA 15 0 Teig JL DSACK1 0 5 1 5 2 0095 00 l 16 BUS ARB TIM Figure A 8 Bus Arbitration Timing Diagram Active Bus Case M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 33 Go to www freescal
95. www freescale com Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers MC68HC16Z1 40 to 85 C SPMCCM16Z1CPV16 1621 1681 68 1622 40 to 85 C ROM MC68HC16Z2CFC16 NA NA MC68HC16Z2CFC25 A A A A A 40 to 105 C N N MC68HC16Z2VFC20 N NA MC68HC16Z2MFC16 NA NA MC68HC16Z2CPV16 NA NA MC68HC16Z2CPV25 MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers Crystal Operating Package Frequency Device Input Voltage Type Temperature MHz 5V MC68HC16Z2 4 MHz 144 Pin 40 to 105 C Order Number ROM or TQFP 32 kHz A MC68HC16Z2VPV16 N NA MC68HC16Z2VPV20 NA MC68HC16Z2VPV25 40 to 125 C NA MC68HC16Z2MPV16 A N MC68HC16Z2MPV20 MC68HC16Z2 4 MHz 5V 132 Pin 40 to 85 C No ROM PQFP NA SPMCM16Z2BCFC16 MCM16Z2BCFC16 MCM16Z2BCFC16B1 SPMCM16Z2BCFC20 MCM16Z2BCFC20 MCM16Z2BCFC20B1 SPMCM16Z2BCFC25 40 to 105 C MCM16Z2BCFC25 MCM16Z2BCFC25B1 SPMCM16Z2BVFC16 MCM16Z2BVFC16 MCM16Z2BV
96. 0 Standby operation 1 0 8 Power Dissipation Pp 555 mW ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 6 Thermal Characteristics Num Characteristic Symbol Value Unit Thermal Resistance 1 Plastic 132 Pin Surface Mount OJA 38 C W Plastic 144 Pin Surface Mount 49 The average chip junction temperature Tj in C can be obtained from Ty Ta Ppx Oya 1 where Ta Ambient Temperature C a Package Thermal Resistance Junction to Ambient C W Pint Pint lpp Vpp Watts Chip Internal Power Power Dissipation on Input and Output Pins User Determined For most applications lt and be neglected An approximate relationship between Pp and Ty if Pyo is neglected is Pp K Ty 273 C 2 Solving equations 1 and 2 for K gives Pp x Ty 273 C Ox Pp 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known Using this value of K the values of Pp and Ty can be obtained by solving equations 1 and 2 iteratively for any value of T4 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 7 Low Voltage
97. 1 BKPT BREAKPOINT 0004 5 BERR BUSERROR 030000 000 SOFTWARE INTERRUPT BANK 3 030000 512 KBYTE 000 7 TLLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 040000 0012 001C 9 UNASSIGNED RESERVED ncaa 040000 001 F UNINITIALIZED INTERRUPT 0020 10 UNASSIGNED RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 050000 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR BANC 050000 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVELSINTERRUPTAUTOVECTOR ___ 060000 002 16 LEVEL6 INTERRUPT AUTOVECTOR BANK 6 060000 002E 17 LEVEL7INTERRUPTAUTOVECTOR DATA 0030 18 SPURIOUS INTERRUPT SPACE 0032 006E 19 37 UNASSIGNED RESERVED 0 070000 0070 01FE 38 FF USER DEFINED INTERRUPTS BANK 7 070000 SO7F FFF SO7FFFF 080000 UNDEFINED UNDEFINED 080000 1 UNDEFINED UNDEFINED Y FF 700 Y FTFFFF ADC F7FFFF F 80000 Y FF 73F BANK 8 F 80000 1 4 F 90000 ROM F 90000 CONTROL d FA0000 YFF900 BANK 10 F A0000 SY FF 93F de 0000 BANK 11 FB0000 512 KBYTE 00 0000 51 0000 SY FFA7F FD0000 YFFBOO SRA BRE SES FD0000 0000 7777 0000 Y FFC00 FF0000 paNK 15 05 BANKAS sid FF 0000 YFFDFF INTERNAL REGISTERS Y FFFFFF LOT SF FFF NOTE 1 THE ADDRESSES DISPLAYED IN THIS MEMORY ARE THE FULL 24 BIT IMB ADDRESSES THE 16
98. 1 L w Power Sop Mode 11 3 11 3 2 di 7 2 70 99 c 11 3 11 3 3 Single Step DOE Lo cin oni REPE EFE 11 4 11 3 4 11 4 11 4 Polled and Interrupt Driven Operation 11 4 11 4 1 ui rio e Era RAER 11 4 11 4 2 GPT g c T I 11 5 eec 11 7 11 5 1 MEUL e dal Nom 11 7 11 5 2 Input Capture Output Compare Pin Loue sexe rcr rere Fe ere 11 7 11 5 3 RENE QNNM 11 7 11 5 4 Pulse Accumulator Input PIN iaces eibi 11 7 11 5 5 M T 11 8 11 5 6 Auxiliary Timer Clock 11 8 11 6 General Purpose I O c 11 8 a aan 11 8 11 10 11 8 1 11 10 11 8 2 SEUNG FUNCIONS PN 11 10 11 8 3 Compare FUNCIONS 11 13 11 8 3 1 COTE Compare e 11 14 11 8 3 2 Forced Output Compare acida odere ERR 11 14 11 9 Input Capture 4 Output Compare 5 11 14 11 10 Pulse Accumulator gt lt lt retina tite dnce 11 14 11 11 P ls Width Mod lati
99. 100 pF Group 3 I O Pins 130 Group 4 I O Pins 200 NOTES 1 Refer to notes in Table A 14 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 15 Go to www freescale com Freescale Semiconductor Inc Table A 14 25 17 MHz DC Characteristics Vg ANd Vppsyn 5 0 5 Veg 0 T T to T Characteristic Input High Voltage Input Low Voltage Input Hysteresis 2 Input Leakage Current Vin Vpp Vss High Impedance Off State Leakage Current Vin OF Vss CMOS Output High Voltage 9 7 lou 10 0 CMOS Output Low Voltage 8 lot 10 0 HA Output High Voltage 6 7 lou 0 8 mA Output Low Voltage 8 lot 1 6mA lot 5 3 12mA Three State Control Input High Voltage Data Bus Mode Select Pull Up Current 10 11 Vin Vit lusp 120 Vin Vin 15 MC68HC16Z1 Vpp Supply Current 12 13 12 Run 140 mA LPSTOP crystal VCO Off STSIM 0 BD 350 uA LPSTOP external clock input frequency maximum fsys 5 mA MC68HC16Z2 Z3 Vpp Supply Current 17 12 13 12A Run 140 mA LPSTOP crystal VCO Off STSIM 0 DD 2 mA LPSTOP external clock input frequency maximum fsys 10 mA 13 Clock Synthesizer Operating Voltage 4 75 5 25 V MC68HC16Z1 Vppsyw Supply Current 13 VCO on crystal reference maximum fsys 2 14 Ex
100. 11 Low Voltage 16 78 MHz DC Characteristics Vip and V nevi 2 7 to 3 6Vdc Vos 0 Vdc T to T Characteristic Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current 2 Vin Or Vss Input only pins High Impedance Off State Leakage Current Vin Vpp or All input output and output pins CMOS Output High Voltage 3 lop 710 0 pA Group 1 2 4 input output and output pins CMOS Output Low Voltage loy 10 0 uA Group 1 2 4 input output and output pins Output High Voltage 3 0 4 mA Group 1 2 4 input output and output pins Output Low Voltage loi 0 8 mA Group 1 pins CLKOUT FREEZE QUOT IPIPEO lo 2 6 mA Group 2 and group 4 I O pins CSBOOT BG CS lo 6 mA Group Three State Control Input High Voltage Data Bus Mode Select Pull up Current 4 Vin Vi Vin Vpp Supply Current Run LPSTOP 4 194 MHz crystal VCO Off STSIM 0 LPSTOP 32 768 kHz crystal VCO Off STSIM 0 LPSTOP external clock input frequency max fsys WAIT Clock Synthesizer Operating Voltage MC68CM16Z1Vppsyn Supply Current VCO on crystal reference maximum External clock maximum fsys IDDSYN LPSTOP 4 194 MHz crystal reference VCO off STSIM 0 Vpp powered down MC68CK16Z1 Z4 Supply Current VCO on crystal reference maximum fy External clock maximum IppsvN LPSTOP 32 768 kHz crystal reference
101. 14 11 16 D 70 PAEN D 70 PAI 11 1 11 15 PAI pin state PAIS D 70 PAIF 11 15 D 74 D 73 PAIS D 70 PAMOD D 70 PAOVF 11 15 D 74 PAOVI D 73 Parallel ports 5 70 Parasitic devices 8 18 Parentheses definition 2 6 Parity checking 9 26 10 19 enable PE D 42 D 61 error PF flag 9 28 10 21 D 44 D 63 type PT 9 26 10 19 D 42 D 61 PC 4 3 PCLK 11 1 11 8 pin state PCLKS D 71 PCLKS D 71 PCS D 53 to SCK delay DSCK D 53 PCSO SS 9 20 PE D 42 D 61 PEDGE 11 16 D 70 PEPAR 5 70 D 10 Periodic interrupt modulus counter 5 28 priority 5 29 request level PIRQL D 13 timer 5 27 components 5 27 modulus PITM field 5 28 D 14 PIT period calculation 5 28 D 14 vector PIV D 13 timer prescaler control PTP 5 28 D 14 Peripheral chip selects PCS 9 21 D 53 PF 9 28 10 21 PFPAR 5 70 D 11 Phase locked loop PLL 1 1 PICR 5 60 D 13 Go to www freescale com Freescale Semiconductor Inc Pin characteristics 3 11 considerations 8 14 electrical state 5 53 function 5 53 reset states 5 54 Pipeline multiplexing 4 41 PIRQL D 13 PITM 5 28 D 14 PITR 5 28 D 14 PIV D 13 PK 4 4 4 5 D 3 PLL 1 1 5 6 Pointer 9 6 Polled operation 11 4 Port C data register PORTC 5 67 E data direction register DDRE 5 70 data register PORTE 5 71 pin assignment register PEPAR 5 70 data direction register DDRF 5 70 data register PORTF 5 71 pin assignment register PFPAR 5 70 parallel I O in SIM 5 70 replacem
102. 16 78 MHz 5 15 20 97 MHz 5 17 25 17 MHz 5 19 integration module See SIM 5 1 reset SYS D 8 test register SIMTR D 7 E SIMTRE D 9 em TC 9 27 10 19 D 43 D 62 TCIE 9 28 10 20 D 42 D 61 TCNT 11 1 11 10 D 70 TCTL D 72 TDR 9 24 TDRE 9 27 10 19 D 43 D 62 TE 10 4 10 13 D 42 D 62 Test submodule reset TST D 8 TFLG D 74 TFLG1 11 12 TFLG2 11 10 Thermal characteristics A 5 Three state control TSC 5 56 TI4 O5 D 72 TIC D 71 TIE 9 28 10 20 D 42 D 61 Timer counter 11 10 overflow flag TOF 11 10 D 74 interrupt enable bit D 73 prescaler PCLK select CPR field D 73 TMSK D 72 TMSK1 11 12 5 2 11 10 D 71 TOF D 74 11 10 0 73 TR 0 52 Transfer length options 9 17 Transistion sensitivity 5 58 Transmit complete TC flag MCCI 10 19 D 62 QSM 9 27 D 43 interrupt enable TCIE MCCI 10 20 D 61 QSM 9 28 D 42 M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc data TXD pin QSM 9 25 TXDA B pins 10 17 register empty TDRE flag MCCI 10 19 D 62 QSM 9 27 D 43 enable TE MCCI 10 4 10 13 10 19 D 62 QSM 9 27 D 42 interrupt enable TIE MCCI 10 20 D 61 QSM 9 28 D 42 RAM 9 7 TSC 5 54 5 56 TST D 8 TSTMSRA B D 22 TSTRC D 22 TSTSC D 22 Two three wire transfers 10 4 Two s complement 4 6 TXD QSM 9 25 TXDA B 10 16 10 17 Typical ratings 2 7V to 3 6V 16 78 MHz A 2 20 97 MHz A 3 25 17 MHz
103. 18 D 76 0 9 2 0 39 QIVR 9 2 0 39 QSM address map 9 2 D 38 block diagram 9 1 features 3 2 general 9 1 interrupts 9 3 pin function 9 4 D 46 QSPI 9 5 operating modes 9 9 operation 9 8 pins 9 8 RAM 9 7 registers 9 6 reference manual 9 1 M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc registers command RAM CR D 52 global registers 9 2 interrupt level register QILR 9 2 D 39 vector register QIVR 9 2 D 39 test register QTEST 9 2 module configuration register QSMCR D 38 pin control registers 9 4 port QS data direction register DDRQS D 45 register PORTQS D 44 data direction register DDRQS 9 4 data register PORTQS 9 4 pin assignment register PQSPAR D 45 QSPI control register 0 SPCRO D 46 control register 1 SPCR1 D 48 control register 2 SPCR2 D 49 control register 3 SPCR3 D 50 status register SPSR D 50 receive data RAM RR D 51 SCI control register 0 SCCRO D 40 control register 1 SCCR1 D 41 data register SCDR D 44 status register SCSR D 43 test register QTEST D 39 transmit data RAM TR D 52 types 9 2 SCI 9 21 operation 9 25 pins 9 25 registers 9 24 QSMCR D 38 QSPI 9 1 9 5 block diagram 9 5 command RAM 9 8 enable SPE D 48 finished flag SPIF D 51 initialization operation 9 10 loop mode LOOPQ D 50 master operation flow 9 11 operating modes 9 9 master mode 9 9 9 16 wraparound mode 9 19 slave mode 9 9 9 2
104. 2 TOC2 LO PGP4 BIT4 loczioc1 16 BIT COMPARATOR TOC3 HI TOC3 LO PGP5 BIT5 locsioci 16 BIT COMPARATOR LO PGP6 BIT6 0 4 0 1 FOC4 16 BIT COMPARATOR PGP7 BIT 7 4 0 5 TM O5 HI 05 LO 4 14 05F FOCS OCI 16 BIT LATCH CLK 14 05 TFLG1 CFORC TMSK1 PARALLEL PORT STATUS FORCE OUTPUT INTERRUPT PIN CONTROL FLAGS COMPARE ENABLES 16 32 CC BLOCK Figure 11 3 Capture Compare Unit Block Diagram M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL For More Information On This Product 11 11 Go to www freescale com Freescale Semiconductor Inc Edge detection logic consists of control bits that enable edge detection and select a transition to detect The bits in timer control register 2 TCTL2 determine whether the input capture functions detect rising edges only falling edges only or both rising and falling edges Clearing both bits disables the input capture function Input capture functions operate independently of each other and can capture the same TCNT value if individual input edges are detected within the same timer count cycle Input capture interrupt logic includes a status flag which indicates that an edge has been detected and an interrupt enable bit An input capture event sets the ICxF bit in the timer interrupt flag register 1 TFLG1 and causes the GPT to make an inter
105. 32 shows possible baud rates for a 16 78 MHz system clock The maximum baud rate with this system clock speed is 524 kbaud Table D 32 Examples of SCI Baud Rates BRE Percent Error Value of SCBR 500 00 00 524 288 00 4 86 1 38 400 00 37 449 14 2 48 14 32 768 00 32 768 00 0 00 16 19 200 00 19 418 07 1 14 27 9 600 00 9 532 51 0 70 55 4 800 00 4 809 98 0 21 109 2 400 00 2 404 99 0 21 218 1 200 00 1 199 74 0 02 437 600 00 599 87 0 02 874 300 00 299 94 0 02 1 748 110 00 110 01 0 01 4 766 64 00 64 00 0 01 8 191 More accurate baud rates can be obtained by varying the system clock frequency with the VCO synthesizer Each VCO speed increment adjusts the baud rate up or down by 1 64 or 1 56 D 6 5 SCI Control Register 1 SCCR1 SCI Control Register 1 YFFCOA 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 NOTUSED LOOPS WOMS ILT PT PE M WAKE TIE TCIE RIE ILIE TE RE RWU SBK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCCR1 contains SCI configuration parameters including transmitter and receiver en able bits interrupt enable bits and operating mode enable bits SCCRO can be read or written at any time The SCI can modify the RWU bit under certain circumstances Changing the value of SCCR1 bits during a transfer operation disrupts operation Bit 15 Not Implemented LOOPS Loop Mode 0 Normal SCI operation no looping fe
106. 4 mso FROM SLAVE c a B i w 55 TO SLAVE NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER 1 5 TRANSFER Figure 10 4 1 SPI Transfer Format For a master writing to the SPDR initiates the transfer For a slave the first edge SCK indicates the start of a transfer The SPI is left shifted on the first and each suc ceeding odd clock edge and data is latched on the second and succeeding even clock edges SCK is inactive for the last half of the eighth SCK cycle For a master SPIF is set at the end of the eighth SCK cycle after the seventeenth SCK edge Since the last SCK edge occurs in the middle of the eighth SCK cycle however the slave has no way of knowing when the end of the last SCK cycle occurs The slave therefore considers the transfer complete after the last bit of serial data has been sampled which corresponds to the middle of the eighth SCK cycle When CPHA is one the SS line may remain at its active low level between transfers This format is sometimes preferred in systems having a single fixed master and only one slave that needs to drive the MISO data line MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 10 3 5 SPI Serial Clock Baud R
107. 5 9 e e 1 iE EE eA SS 5 ri lt at LE A 6 d A 5 ZEB 7 RY 9 A p fa ES ne t P po 8 TRANSFER CURVE No CIRCUIT ERROR 0 20 40 60 INPUT IN mV Vay VRL 73 072 V A 1 2 COUNT 6 mV INHERENT QUANTIZATION ERROR B CIRCUIT CONTRIBUTED 12 mV ERROR C 18 mV ABSOLUTE ERROR 1 5 8 BIT COUNTS ADC 8 BIT ACCURACY LV Figure A 34 Low Voltage 8 Bit ADC Conversion Accuracy ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product Go to www freescale com USER S MANUAL DIGITAL OUTPUT Freescale Semiconductor Inc F N IDEAL TRANSFER CURVE I BIT TRANSFER CURVE NO CIRCUIT ERROR 60 INPUT IN mV Vay 5 120V A 1 2 COUNT 10 mV INHERENT QUANTIZATION ERROR CIRCUIT CONTRIBUTED 10mV ERROR 20 mV ABSOLUTE ERROR ONE 8 BIT COUNT Figure A 35 8 Bit ADC Conversion Accuracy M68HC16 Z SERIES USER S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com ADC 8 BIT ACCURACY A 69 Freescale Semiconductor Inc 2 DEAL TRANSFER CURVE 472722 NYOBIT TRANSFER CURVE NO CIRCUIT ERROR DIGITAL OUTPUT 60 INPUT IN mV Vay VRL 23 072 V A 5 1 5 mV INHERENT QUANTIZATION ERROR B CIRCUIT CONTRIBUTED 410 5 mV ERROR C 12 mV ABSOLUTE ERROR 4 10 BIT COU
108. 55575 111111 8389 16777 33554 67109 SYSTEM INTEGRATION MODULE M68HC16 7 SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 7 System Clock Frequencies for a 25 17 MHz System Shaded cells represent values that exceed 25 17 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2xValue fyco Value fyco 22xValue Value 000000 131 kHz 262 kHz 524 kHz 1049 kHz 000001 524 1049 2097 000011 1049 2097 4194 000101 786 1573 3146 6291 000111 1049 2097 4194 8389 001001 1811 2621 5243 10486 001011 1573 3146 6291 12583 001101 1835 3670 7340 14680 001111 2097 4194 8389 16777 010001 2359 4719 9437 18874 Y 010101 2884 5767 11534 23069 010111 3146 6291 12583 25166 011001 3408 6816 13631 27263 011011 3670 7340 14680 29360 011101 3932 7864 15729 31457 011111 4194 8389 16777 33554 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 7 System Clock Frequencies for a 25 17 MHz System Continued Shaded cells represent values that exceed 25 17 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2xValue Value fyco 22xValue
109. 6 control multipliers 16 78 MHz 5 9 20 97 MHz 5 11 25 17 MHz 5 13 frequency calculation D 7 mode pin MODCLK 5 52 selection 5 52 modes fast reference option 4 194 MHz 5 4 5 5 slow reference option 32 768 kHz 5 4 5 5 output CLKOUT 5 36 phase CPHA 10 8 D 47 0 transfer format 10 9 1 transfer format 10 10 polarity CPOL 10 8 D 47 synthesizer operation 5 6 timing 16 78 MHz A 7 20 97 MHz A 8 25 17 MHz A 9 low voltage A 6 Closed loop control routines 4 45 CLp 4 37 4 37 Coherency 11 10 11 12 Combined program and data space map MC68HC16Z1 CKZ1 CMZ1 3 20 68 1622 73 3 21 68 1674 74 3 22 Command RAM 9 8 Comparator 8 6 Completed queue pointer CPTQP D 51 Condition code register CCR 4 4 11 6 CONT D 52 Contention 5 60 Continue CONT D 52 Continuous transfer mode 9 6 Conventions 2 6 Conversion complete flags CCF D 36 control logic 8 7 modes 8 8 multiple channel conversions 8 11 parameters 8 8 single channel conversions 8 10 counter CCTR D 36 M68HC16 Z SERIES USER S MANUAL timing 8 12 CPHA 9 17 10 8 10 9 10 10 D 47 CPOL 9 17 10 8 D 47 CPR 0 73 CPROUT 11 10 D 73 CPTQP 9 8 D 51 CPU space 5 68 address encoding 5 41 cycles 5 40 5 68 encoding for interrupt acknowledge 5 68 CPU16 4 1 accumulators 4 3 address extension register 4 5 addressing modes 4 8 accumulator offset 4 10 extended 4 10 immediate 4 9 indexed 4 10 inherent 4 10 post modified index 4 10 relativ
110. 7 Function Codes for more information concerning address space types and program data space access Refer to 4 6 Addressing Modes for more in formation on addressing modes 6 4 Normal Access The array can be accessed by byte word or long word A byte or aligned word access takes one bus cycle or two system clocks A long word or misaligned word access re quires two bus cycles Refer to 5 6 Bus Operation for more information concerning access times 6 5 Standby and Low Power Stop Operation Standby and low power modes should not be confused Standby mode maintains the RAM array when the main MCU power supply is turned off Low power stop mode al lows the CPU16 to control MCU power consumption by disabling unused modules Relative voltage levels of the MCU Vpp and Vsrpy pins determine whether the SRAM is in standby mode SRAM circuitry switches to the standby power source when Vpp drops below specified limits If specified standby supply voltage levels are maintained during the transition there is no loss of memory when switching occurs The RAM ar ray cannot be accessed while the SRAM module is powered from If standby operation is not desired connect the to Vss STANDBY RAM MODULE M68HC16 Z SERIES 6 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Isp SRAM standby current values may vary while Vpp transitions occur Refer to AP PENDIX
111. 9600 baud NOTE These programs and others can be obtained from the Freescale web site at http www freescale com M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL For More Information On This Product 1 to www freescale com E 1 1 EQUATES ASM Freescale Semiconductor Inc DESCRIPTION THIS IS A TABLE OF EQUATES FOR ALL M68HC16 Z SERIES REGISTERS SIM MODULE REGISTERS SIMMCR EQU FA00 SIM MODULE CONFIGURATION REGISTER SIMTR EQU S FA02 SYSTEM INTEGRATION TEST REGISTER SYNCR EQU FA04 CLOCK SYNTHESIZER CONTROL REGISTER RSR EQU FA07 RESET STATUS REGISTER SIMT
112. A 4 5V 16 78 MHz A 3 U UART 10 2 10 13 Universal asynchronous receiver transmitter UART 10 2 10 13 N V 4 4 D 3 Vcr 8 22 VCO 5 6 Vpp 5 55 6 1 ramp time 5 56 Vppa 8 1 8 3 8 14 Vppsyn 5 6 5 55 Vector sources D 56 V 8 22 8 2 Vy 8 2 Voltage controlled oscillator VCO 5 6 frequency fyco 5 6 frequency ramp time 5 56 limiting diodes 8 19 Vpp C 2 5 53 8 1 8 3 8 14 8 23 Vn 5 53 8 1 8 3 8 14 8 23 Vsnc 8 22 Vaga 8 1 8 3 8 14 6 2 M68HC16 Z SERIES USER S MANUAL For More Information On This Product W W D 8 WAIT 7 3 D 26 Wait states field WAIT D 26 WAKE 9 30 10 22 D 42 D 61 Wakeup address mark WAKE 9 30 10 22 D 42 D 61 functions 9 2 WCOL D 65 Wired OR mode for QSPI pins WOMQ D 47 for SCI pins WOMS 10 19 D 61 QSM 9 27 D 41 open drain outputs 10 11 WOMC 10 16 WOMP 10 11 WOMQ D 47 WOMS 9 27 10 19 D 41 D 61 Word composition 4 7 Wrap enable WREN D 50 to WRTO D 50 Wraparound mode 9 6 master 9 19 slave 9 21 WREN D 50 Write collision WCOL 10 12 D 65 cycle 5 38 flowchart 5 39 timing diagram A 30 WRTO D 50 X D 8 bit in SYNCR 5 6 XK 4 3 4 5 XTAL 5 5 XTRST external reset 5 48 Y Y D 8 YK 4 8 4 5 272 24 4 Zero flag 2 4 4 7 4 3 4 5 15 Go to www freescale com 16 Freescale Semiconductor Inc For More Information On This Product Go to www freescale com M68HC16 Z SERIES U
113. ADDR19 1 1 csio CS9 css 57 56 1 510 CS9 CS8 ADDR20 ADDR19 1 0 510 ADDR22 ADDR21 ADDR20 ADDR19 D 2 18 Chip Select Base Address Register Boot CSBARBT Chip Select Base Address Register Boot YFFA48 15 13 12 1 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR BLKSZ12 0 23 2 21 20 19 18 17 16 15 4 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D 2 19 Chip Select Base Address Registers CSBAR 0 10 Chip Select Base Address Registers YFFA4C YFFA74 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR Kj ADDR ADDR ADDR 1 52 2 0 23 22 21 20 19 18 17 16 15 4 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 17 Go to www freescale com Freescale Semiconductor Inc Each chip select pin has an associated base address register A base address is the lowest address in the block of addresses enabled by a chip select CSBARBT contains the base address for selection of a boot memory device Bit and field definitions for CSBARBT and CSBAR 0 10 are the same but reset block sizes differ These regis ters may be read or written at any time ADDR 23 11 Base Address This field sets the starting address of a particular chip select s address space The ad dress comp
114. Acknowledge for more information Chip select address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the exter nal bus following IARB contention All interrupts from internal modules have their as sociated IACK cycles terminated with an internal DSACK Thus user vectors instead of autovectors must always be used for interrupts generated from internal modules If an internal module makes an interrupt request of a certain priority and the appropriate chip select registers are programmed to generate AVEC or DSACK signals in re sponse to an interrupt acknowledge cycle for that priority level chip select logic does not respond to the interrupt acknowledge cycle and the internal module supplies a vector number and generates internal cycle termination signals For periodic timer interrupts the PIRQ 2 0 field in the periodic interrupt control register PICR determines PIT priority level A PIRQ 2 0 value of 96000 means that PIT inter rupts are inactive By hardware convention when the CPU16 receives simultaneous interrupt requests of the same level from more than one SIM source including external devices the periodic interrupt timer is given the highest priority followed by the IRQ pins 5 8 4 Interrupt Processing Summary A summary of the entire interrupt processing sequence follows When the sequence begins a valid interrupt service request has been detected and is pending A The CPU16 finis
115. Address Strobe Address strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals 5 5 1 3 Data Bus Signals DATA 15 0 form a bidirectional non multiplexed parallel bus that transfers data to or from the MCU A read or write operation can transfer eight or sixteen bits of data in one bus cycle For a write cycle all sixteen bits of the data bus are driven re gardless of the port width or operand size 5 5 1 4 Data Strobe Data strobe DS is a timing signal For a read cycle the MCU asserts DS to signal an external device to place data on the bus DS is asserted at the same time as AS during a read cycle For a write cycle DS signals an external device that data on the bus is valid M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 31 Go to www freescale com Freescale Semiconductor Inc 5 5 1 5 Read Write Signal The read write signal R W determines the direction of the transfer during a bus cycle This signal changes state when required at the beginning of a bus cycle and is valid while AS is asserted R W only transitions when a write cycle is preceded by a read cycle or vice versa The signal may remain low for two consecutive write cycles 5 5 1 6 Size Signals Size signals SIZ 1 0 indicate the number of bytes remaining to be transferred during an operand cycle They are valid while AS is asserted Table
116. Although the QSPI inherently supports multi master operation no special arbitration mechanism is provided A mode fault flag MODF indicates a request for SPI master arbitration System software must provide arbitration Note that unlike previous SPI systems MSTR is not cleared by a mode fault being set nor are the QSPI pin output drivers disabled The QSPI and associated output drivers must be disabled by clearing SPE in SPCR1 Figure 9 4 shows QSPI initialization Figures 9 5 through 9 9 show QSPI master and slave operation The CPU16 must initialize the QSM global and pin registers and the QSPI control registers before enabling the QSPI for either mode of operation The command queue must be written before the QSPI is enabled for master mode opera tion Any data to be transmitted should be written into transmit RAM before the QSPI is enabled During wrap around operation data for subsequent transmissions can be written at any time M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 9 Go to www freescale com 9 10 Freescale Semiconductor Inc BEGIN GLOBAL REGISTERS INITIALIZE PQSPAR INITIALIZE QSM PORTQS AND DDRQS IN THIS ORDER QSPI INITIALIZATION CONTROL REGISTERS INITIALIZE QSPI RAM ENABLE 05 INITIALIZE QSPI QSPIFLOW 1 Figure 9 4 Flowchart of QSPI Initialization Operation QUEUED SERIAL MODULE For Mor
117. Asserted tswa 100 ns 14A DS CS Width Asserted Write tswaw 45 ns 14B AS CS and DS Read Width Asserted Fast Cycle tswow 40 ns 15 AS DS CS Width Negated tsn 40 ns 16 Clock High to AS DS R W High Impedance 59 ns 17 AS DS CS Negated to R W High tsnAN 15 ns 18 High to R W High tcHRH 0 29 ns 20 Clock High to R W Low 0 29 ns 21 R W High to AS CS Asserted tRAAA 15 ns 22 R Low to DS CS Asserted Write 70 ns 23 Clock High to Data Out Valid tcupo 29 ns 24 Data Out Valid to Negating Edge of AS CS Fast Write Cycle 15 ns 25 65 CS Negated to Data Out Invalid Data Out Hold tSNDOI 15 ns 26 Data Out Valid to DS CS Asserted Write ipvsA 15 ns 27 Data In Valid to Clock Low Data Setup tpicL 5 ns 27A Late BERR HALT Asserted to Clock Low Setup Time 20 ns 28 AS DS Negated to DSACK 1 0 BERR HALT AVEC Negated ns 29 05 CS Negated to Data In Invalid Data In Hold teNDI 0 ns 29A 05 CS Negated to Data In High Impedance 8 tsHDI 55 ns M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 16 16 78 MHz AC Timing Continued Vio and 5 0 Vdo 10 96 0 Vdo T T to DDSYN Num Characteristic Symbol Min Max Unit 30 CLKOUT Low to Data In
118. B D 55 ILSPI 10 2 D 56 D 57 ILT 9 29 10 21 D 42 D 61 IMB 11 1 IMM16 4 9 8 4 9 Immediate addressing modes 4 9 Impedance 8 21 In circuit debugger ICD16 ICD32 C 2 INCP D 68 Increment prescaler INCP D 68 Indexed addressing modes 4 10 Inductors 8 14 Inherent addressing modes 4 10 Initialization programs E 1 INITRAM ASM 11 INITSCI ASM 12 INITSYS ASM E 11 Input capture IC pins 11 7 output compare IC4 OC5 pin 11 7 4 output compare 5 11 14 14 05 bit D 71 flag I4 O5F D 74 interrupt enable bit I4 O5 D 73 conditioning signals 11 12 edge control bit field EDGE D 72 flags ICF D 74 functions 11 10 interrupt enable ICI bit D 73 logic 11 12 timing example 11 13 leakage errors 8 23 M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Instruction execution model 4 35 fetches 4 7 pipeline 4 35 set for CPU16 4 11 timing 4 36 Intermodule bus IMB 3 2 11 1 Internal bus error BERR 5 24 5 25 monitor 5 24 register map 3 16 VCO frequency 5 8 Interrupt acknowledge and arbitration 5 59 bus cycles 5 61 arbitration 5 3 9 3 11 6 IARB field GPT D 68 D 55 QSM D 39 SIM 5 59 D 7 exception processing 5 58 level IL for QSPI ILQSPI D 40 for SCI ILSCI D 40 priority adjust IPA D 68 and recognition 5 58 level field IPL 5 67 D 21 mask IP field 4 4 5 58 9 3 11 6 D 3 processing summary 5 60 vector D 56 number 9 3 11 6 field INTV D 4
119. CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the conversion sequence is complete Mode 1 A single eight conversion sequence is performed on a single input channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the conversion sequence is complete ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Mode 2 A single conversion is performed on each of four sequential input channels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the last conversion is complete Mode 3 A single conversion is performed on each of eight sequential input chan nels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the last conver sion is complete Mode 4 Continuous four conversion sequences are performed on a single input channel specified by the value in CD CA Each result is s
120. Clock Control Timing Vpp and VDDSYN 2 7 to 3 6 Vdc Vss 0 to Ty Characteristic PLL Reference Frequency Range 68 1671 PLL Reference Frequency Range 68 1671 68 1674 20 System Frequency dc On Chip PLL System Frequency Slow On Chip PLL System Frequency 4 fret Fast On Chip PLL System Frequency 4 fret 128 External Clock Operation dc PLL Lock Timet 8 9 Changing W or Y in SYNCR or exiting from LPSTOP Warm Start Up Cold Start Up fast reference option only VCO Frequency Limp Mode Clock Frequency SYNCR X bit 0 SYNCR bit 1 CLKOUT Jitter 8 9 10 7 Short term 5 us interval 0 5 0 5 Long term 500 us interval 0 05 0 05 NOTES 1 Refer to notes in Table A 10 ELECTRICAL CHARACTERISTICS M68HC16 7 SERIES A 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 8 16 78 MHz Clock Control Timing Vip and Vppsyy 5 0 410 Veg 0 T T to T Characteristic Minimum Maximum PLL Reference Frequency Range MC68HC16Z1 MC68HC16Z2 MC68HC16Z3 System Frequency On Chip PLL System Frequency Slow On Chip PLL System Frequency Fast On Chip PLL System Frequency 4 128 External Clock Operation dc PLL Lock Time 7 8 9 Changing W or Y in SYNCR or exiting from LPSTOP Warm Start Up Cold Start Up fast reference option on
121. Clock High to Data Out High Impedance 23 ns 55 R W Asserted to Data Bus Impedance Change ns 70 Clock Low to Data Bus Driven Show Cycle tscLDD 23 ns 71 Data Setup Time to Clock Low Show Cycle tscLps ns 72 Data Hold from Clock Low Show Cycle tsCLDH ns 73 BKPT Input Setup Time ns 74 BKPT Input Hold Time ns 75 Mode Select Setup Time DATA 15 0 MODCLK BKPT pins 76 Mode Select Hold Time DATA 15 0 MODCLK pins ns 77 RESET Assertion Time M 78 RESET Rise Time 10 love 100 CLKOUT High to Phase 1 Asserted 1 40 ns 101 CLKOUT High to Phase 2 Asserted 4 tCHP2A 40 ns 102 1 Valid to AS or DS Asserted tpivsa ns 103 Phase 2 Valid to AS or DS Asserted tpovsn ns 104 AS or DS Valid to Phase 1 Negated 4 tsaPiNn a ns 105 AS or DS Negated to Phase 2 Negated teNP2N ns NOTES 1 Refer to notes in Table A 18 A 24 ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 18 25 17 MHz AC Timing Vop and Vopsyn 5 0 5 V 0 Vdc T T to Characteristic Symbol Mi Frequency of Operation f Clock Period lcyc tEcyc 39 7 318 Max Unit 25 166 MHz ECLK Period External Clock Input Period txcyc 39 7 Clock Pulse Width TENE 155 2B 3B External Clock Input H
122. Compare Timer compare force register CFORC is used to make forced compares The action taken as a result of a forced compare is the same as when an output compare match occurs except that status flags are not set Forced channels take programmed actions immediately after the write to CFORC The CFORC register is implemented as the upper byte of a 16 bit register which also contains the PWM control register C PWMC It can be accessed as eight bits or a word access can be used Reads of force compare bits FOC have no meaning and always return zeros These bits are self negating 11 9 Input Capture 4 Output Compare 5 The IC4 OC5 pin can be used for input capture output compare or general purpose A function enable bit 14 05 the pulse accumulator control register PACTL configures the pin for input capture 4 or output compare function OC5 Both bits are cleared during reset configuring the pin as an input but also enabling the OC5 function IC4 OC5 I O functions are controlled by DDGP7 in the port GP data direction register DDRGP 16 bit register 4 5 used with the IC4 OC5 function acts as an input capture register or as an output compare register depending on which function is selected When used as the input capture 4 register it cannot be written to except in test or freeze mode 11 10 Pulse Accumulator The pulse accumulator counter PACNT is an 8 bit read write up counter PACNT can operate
123. Control Pin 5 56 24 8 Reset Processing SUITImalV assise ite ncn HEEL eS mei oS LR abis 5 57 5 7 10 eset Status MEM 5 57 2 9 rli PAM MIL o DOE 5 58 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 5 8 1 interrupt Exception Processing 5 58 5 8 2 Interrupt Priority and Recognition 5 58 5 8 3 Interrupt Acknowledge and Arbitration 5 59 5 8 4 Interrupt Processing 2 5 60 5 8 5 Interrupt Acknowledge Bus Cycles 5 61 5 9 5 61 ns Chip Select Registers oo xor axe eae 5 63 58 1 1 Chip Select Pin Assignment Registers 5 64 5 9 1 2 Chip Select Base Address Registers 5 65 5 9 1 3 Chip Select Option Registers aute rotate cese 5 66 5 9 1 4 PORTO Data Register 441222 221 5 67 5 9 2 Chip Select Operation m 5 67 59 3 Using Chip Select Signals for Interrupt Acknowledge 5 68 5 9 4 Chip Select Reset Operation lt 5 69 5 10 au
124. E TEE 5 37 5 6 2 2 E E ra EEEREN ARRE 5 38 5 6 3 Fast Termination 9w X 5 39 5 6 4 OPU rr ilo o c 5 40 5 6 4 1 Breakpoint Acknowledge Cycle 5 41 5 6 4 2 LPSTOP Broadcast GOD 5 42 56 5 Bus Exception Control Cycles iius eei euin 5 43 5 6 5 1 Ble 2j 5 44 5 6 5 2 Double Bus Faults 4444222 00 5 45 5 6 5 3 gt PR E 5 45 5 6 6 External Bus uu aea cada ep supp 5 46 5 6 6 1 du r4 5 47 5 7 icc 5 48 Reset Exception Processing 1er ren tonne reper rr rat anta rhe rS 5 48 2 7 2 lac Connal LOU 5 48 5 7 3 Reset Mode Selection 2 280 4 5 49 5 7 3 1 Data Bus Mode Selection esu ie mendaci daa ome mti c 5 50 5 7 2 Clock Mode Selecion 5 52 Bars Breakpoint Mode Selection 5 52 5 7 4 MCU Module Pin Function During Reset 5 52 5 7 5 Pin Stale Dunng Roset acosada aa 5 53 9 7 5 1 States of SIM adien 5 54 5 7 5 2 Reset States of Pins Assigned to Other MCU Modules 5 54 5 7 6 Reset TENE 5 55 5 74 Gil ous 5 55 5 7 8 Use of the Three State
125. High 3 VRH Vppa 2 VDDA V 7 Vger Differential Voltage Vnu VRL 2 7 3 6 V 8 Input Voltage ViNDC VssA 9 Input High Port ADA Vin 0 7 Vppa Vppa 0 3 10 Input Low Port ADA VssA 0 3 0 2 VppA V Analog Supply Current 11 Normal Operation IDDA 1 0 mA Low Power Stop 200 uA 12 Reference Supply Current IREF 120 uA 13 Input Current Channel 150 nA 14 Total Input Capacitance Not Sampling 10 pF 15 Total Input Capacitance Sampling Cins 15 pF NOTES 1 Refers to operation over full temperature and frequency range 2 To obtain full scale full range results Vssa lt Vni lt lt lt 3 Accuracy tested and guaranteed at Vg 2 7 V 8 6 Vac 4 Current measured at maximum system clock frequency with ADC active 5 Maximum leakage occurs at maximum operating temperature Current decreases by approximately one half for each 10 C decrease from maximum temperature Table A 34 Low Voltage ADC AC Characteristics Operating Vpp and Vona 2 7 to 3 6 Vss 0 within operating temperature range Num Parameter Symbol Min Max Unit 1 ADC Clock Frequency fADCLK 0 5 1 05 MHz mal 2 8 Bit Conversion Time ony 15 2 us fADCLK 1 05 MHz 10 Bit Conversion Time fADCLK 1 05 MHz tconv 17 1 E us 4 Stop Recovery Time ten 50 us NOTES 1 Conversion accuracy varies
126. High Impedance icusz 0 59 ns 17 5 DS CS Negated to R W High teNRN 15 ns 18 High to High tcHRH 0 30 ns 20 Clock High to R W Low tcHRL 0 30 ns 21 R W High to AS CS Asserted tRAAA 15 ns 22 R W Low to DS CS Asserted Write 70 ns 23 High to Data Out Valid tcHDo 30 ns 24 Data Out Valid to Negating Edge of AS CS Fast Write Cycle tovasn 15 ns 25 65 CS Negated to Data Out Invalid Data Out Hold tsNDOI 15 ns 26 Data Out Valid to DS CS Asserted Write tovsa 15 ns 27 Data In Valid to Clock Low Data Setup tpicL 5 ns 27A Late BERR HALT Asserted to Clock Low Setup Time 20 ns 29 05 CS Negated to Data In Invalid Data In Hold tsNDI 0 ns 29A DS CS Negated to Data In High Impedance 9 55 ns M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL A 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 15 Low Voltage 16 78 MHz AC Timing Continued and V 2 7 to 3 6Vdc V 0 T T to T DDSYN Num Characteristic Symbol Min Max Unit 30 CLKOUT Low to Data In Invalid Fast Cycle Hold tci pi 15 ns 30A CLKOUT Low to Data In High Impedance 90 ns 31 DSACK 1 0 Asserted to Data In Valid tDADI 50 ns 33 Clock Low to BG Asserted Negated 30 5 35 Asserte
127. High Z DSACKO Input PE1 DSACK1 PE1 High Z DSACK1 Input CS 5 3 FC 2 0 PC 2 0 Vpp CS 5 3 FC 2 0 Unknown HALT High Z HALT HALT Input IRQ 7 1 PF 7 1 High Z IRQ 7 1 PF 7 1 Input MODCLK PFO Mode Select MODCLK PFO Input RAN Output RESET input SIZ 1 0 PE 7 6 High Z SIZ 1 0 Unknown PE 7 6 Input TSC Mode select TSC Input TSC Input 5 7 5 2 Reset States of Pins Assigned to Other MCU Modules As a rule module pins that are assigned to general purpose ports go into a high impedance state following reset However during power on reset module port pins may be in an indeterminate state for a short period Refer to 5 7 7 Power On Reset for more information SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 54 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 7 6 Reset Timing The RESET input must be asserted for a specified minimum period for reset to occur External RESET assertion can be delayed internally for a period equal to the longest bus cycle time or the bus monitor time out period in order to protect write cycles from being aborted by reset While RESET is asserted SIM pins are either in an inactive high impedance state or are driven to their inactive states When an external device asserts RESET for the proper period reset control logic clocks the signal into an internal latch The control logic drives the RESET pin low
128. Hysteresis Designation ADDR23 CS10 ECLK A Y N ADDR 22 19 CS 9 6 A Y N PC 6 3 ADDR 18 0 A 7 0 PADA 7 0 PE5 PE2 lt 2 BKPT DSCLK CLKOUT DATA 15 0 DS gt gt w w DSACK 1 0 DSO IPIPEO FC 2 0J CS b 3 HALT Special PGP7 11 PGP 2 0 IRQ 7 1 PF 7 1 MISO Bo PQSO MISO Bo PMCO MODCLK PFO MOSI PQS1 MOS PMC1 OC 4 1 PGP 6 3 Y Y M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 11 Go to www freescale com Freescale Semiconductor Inc Table 3 1 M68HC16 Z Series Pin Characteristics Continued Pin Output Input Input Discrete Port Mnemonic Driver Designation PCLK PCSO SS PCS 8 1 PWMA 53 5 6 4 2 lt 2 lt me RXDA RXDB PMC6 PMC4 SCK SCK PMC2 52 SIZ 1 0 553 PE 7 6 5 TXD TXDB PMC7 PMC5 XFC XTAL Special Special NOTES 1 DATA 15 0 are synchronized during reset only MODCLK QSM MCCI and ADC pins are synchronized only when used as input port pins 2 EXTAL XFC and XTAL are clock reference connections 3 pins used only on the 68 1674 1674 4 PAl and PCLK can be used for discrete input but are not part of an I O port 5
129. Interrupt Vector Register D 55 D 7 4 MCCI Interrupt Vector Register 2 D 56 75 SPI Interpt Level Register 1 2 uec D 56 D 7 6 MCCI Pin Assignment Register D 57 D 7 7 MCCI Data Direction Register Luise re rehab iae cie D 58 D 7 8 MEGI Pe Data 0 59 0 7 9 f 0 59 0 7 11 SCI SAS oo m D 62 D 7 12 SCI Data Register D 63 D 7 13 SPI Control Register neers D 64 D 7 14 lee D 65 D 7 15 SPI Data Register a a D 66 D 8 General Purpose HT D 67 0 8 1 GPT Module Configuration Register D 67 D 8 2 GPT Pm 0 68 0 8 3 GPT Interrupt Configuration Register D 68 D 8 4 Port GP Data Direction Register Data Register D 69 D 8 5 OC1 Action Mask Register Data Register D 69 D 8 6 Timer Counter Register 44 1221 D 70 D 8 7 Pulse Accumulator Control Register Counter D 70 D 8 8 Input Capture Registers 1 3 senes acit ed D 71 D 8 9 Output Compare Registers 1 4 D 71 D 8 10 Input Capture 4 Output Compare 5 Register D 72 D 8 11 Timer Control Regist
130. MODULE USER S MANUAL For More Information On This Product 9 3 Go to www freescale com Freescale Semiconductor Inc 9 2 2 QSM Pin Control Registers 9 4 The QSM uses nine pins Eight of the pins can be used for serial communication or for parallel I O Clearing a bit in the port QS pin assignment register PQSPAR assigns the corresponding pin to general purpose I O setting a bit assigns the pin to the QSPI PQSPAR does not affect operation of the SCI The port QS data direction register DDRQS determines whether pins are inputs or outputs Clearing a bit makes the corresponding pin an input setting a bit makes the an output DDRQS affects both QSPI function and I O function DDQS7 deter mines the direction of the TXD pin only when the SCI transmitter is disabled When the SCI transmitter is enabled the TXD pin is an output The port QS data register PORTQS latches data PORTQS writes drive pins de fined as outputs PORTQS reads return data present on the pins To avoid driving un defined data first write PORTQS then configure DDRQS PQSPAR and DDRGS are 8 bit registers located at the same word address Refer to Table 9 1 for a summary of QSM pin functions Table 9 1 Effect of DDRQS on QSM Pin Function QSM Pin QSPI Mode DDRQS Bit Bit State Pin Function MISO Master DDQSO 0 Serial data input to QSPI 1 Disables data input Slave 0 Disables data output 1 Serial data out
131. MOSI OUTPUT 16 MAST 1 Figure A 21 SPI Timing Master CPHA 1 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product 51 Go to www freescale com Freescale Semiconductor Inc 55 INPUT SCK CPOL 0 50 MSB OUT MOSI INPUT MSB IN LSB IN MSB IN 16 MCCI SLV CPHAO MISO OUTPUT MOSI INPUT 16 MCCI SLV CPHA1 Figure A 23 SPI Timing Slave CPHA 1 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES 52 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 31 General Purpose Timer AC Characteristics Num Parameter Symbol M Max Unit in 1 Operating Frequency Fclock 0 16 78 MHz 0 1 PCLK Frequency 4 Fclock MHz Pulse Width Input Capture PWtim 2 Fclock PWM Resolution 2 Fclock 2 3 4 5 IC OC Resolution 4 Fclock 6 7 8 PCLK Width PWM 4 Fclock PCLK Width IC OC 4 Fclock PAI Pulse Width 2 Fclock PES EXT PIN p NOTES 1 PHILIS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 A INPUT SIGNAL AFTER THE SYNCHRONIZER 3 B AFTER THE DIGITAL FILTER INPUT SIG CONDITIONER TIM Figure A 24 Input Signal Conditioner Timing M68HC16 Z SERIES ELECTRICAL CHARACTER
132. More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 20 Module Pin Functions Module Pin Mnemonic Function PADA 7 OJ AN 7 0 Discrete input ADC Reference voltage VRL Reference voltage DSI IPIPE1 DSI IPIPE1 CPU DSO IPIPEO DSO IPIPEO BKPT DSCLK BKPT DSCLK PGP7 IC4 OC5 Discrete input PGP 6 3 OC 4 1 Discrete input PGP 2 0 IC 3 1 Discrete input GPT PAI Discrete input PCLK Discrete input PWMA PWMB Discrete output PQS7 TXD Discrete input PQS 6 4 PCS 3 1 Discrete input PQS3 PCS0 SS Discrete input QSM PQS2 SCK Discrete input PQS1 MOSI Discrete input PQSO MISO Discrete input RXD RXD PMC7 TXDA Discrete input PMC6 RXDA Discrete input PMC5 TXDB Discrete input FMGSIRADB SES PMC3 SS Discrete input PMC2 SCK Discrete input PMC1 MOSI Discrete input PMCO MISO Discrete input NOTES 1 Module port pins may be in an indeterminate state for up to 15 milliseconds at power up 5 7 5 Pin State During Reset It is important to keep the distinction between pin function and pin electrical state clear Although control register values and mode select inputs determine pin function a pin driver can be active inactive or in high impedance state while reset occurs During power on reset pin state is subject to the constraints discussed in 5 7 7 Power On Reset M68HC16 Z SERIES USER S MANUAL SYSTEM INTEGR
133. OCx COMPARE REGISTER THE OCx FLAG IS SET FOLLOWED BY THE OCx PIN CHANGING STATE OUTPUT COMPARE Figure A 29 Output Compare Toggle Pin State M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product 57 Go to www freescale com Freescale Semiconductor Inc PHI1 COMPARE CAPTURE CLOCK TCNT 0101 X 0102 ICx EXTERNAL PIN CONDITIONED INPUT2 ICx CAPTURE REGISTER 0102 ICXF NOTES 1 PHIL IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 THE CONDITIONED INPUT SIGNAL CAUSES THE CURRENT VALUE OF THE TCNT TO BE LATCHED BY THE ICx CAPTURE REGISTER THE ICXF FLAG IS SET AT THE SAME TIME INPUT CAPTURE Figure A 30 Input Capture Capture on Rising Edge ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 58 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BUS STATES Pu PDDRx EXTERNAL PIN INPUT CONDITIONED INPUT INTERNAL DATA BUS IMB READ CYCLE READ BIT AS 1 IMB READ CYCLE READ BIT AS 1 IMB READ CYCLE READ BIT AS 0 NOTES 1 PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING GENERAL PURPOSE INPUT Figure A 31 General Purpose Input M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For M
134. OM OOO0000000000000000000000000000000000000000000000000000 I9 52097 ae opus 42 SE SEE S994 oper opo pen Spa ge 559p epus quo pa Spe os EDS c 229 53 7 peu epus qo p sat 599 sper 3 992 t pru Fe 0 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt pq X i dE 426 439 qo ce 0 qp R3 aq 42 045 4D 4p ud up d up ud 49 04 0432 ce 0 d D 49 200 PPD DDD 25 2 DDD DD DD DDD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD 2 D D 2 2 HUM MH MH MH MH MH MH HHH MH MH MH MH MH MH HHH MH MH HHH MH MH MH MH MH MH HHH MH MH HHH MH MH MN MM HMM MH MH MH MMH MH MH MH MH MH MMH MH MH MH MH MH HHH MH MH MH HHH MH MH MMH MH Y
135. On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NOTE When TSC assertion takes effect internal signals are forced to val ues that can cause inadvertent mode selection Once the output driv ers change state the MCU must be powered down and restarted before normal operation can resume 5 7 9 Reset Processing Summary To prevent write cycles in progress from being corrupted a reset is recognized at the end of a bus cycle and not at an instruction boundary Any processing in progress at the time a reset occurs is aborted After SIM reset control logic has synchronized an internal or external reset request the MSTRST signal is asserted The following events take place when MSTRST is asserted A Instruction execution is aborted B The condition code register is initialized 1 The IP field is set to 7 disabling all interrupts below priority 7 2 The S bit is set disabling LPSTOP mode 3 The SM bit is cleared disabling MAC saturation mode C The K register is cleared NOTE All CCR bits that are not initialized are not affected by reset Howev er out of power on reset these bits are indeterminate The following events take place when MSTRST is negated after assertion A The CPU16 samples the BKPT input B The CPU16 fetches RESET vectors in the following order Initial ZK SK and PK extension field values Initial PC Initial SP Initial IZ value Bmw Vectors can
136. PROGRAMMING EXAMPLES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc E 1 2 ORG00000 ASM Title 06600000 Description This file is included to set up the reset d vector 00000 00006 0000 put the following reset vector information at address 00000 of the memory map DC W 0010 PZk 0 sk 1 pk 0 DC W 0200 pc 200 initial program counter DC W SO3FE sp 03fe initial stack pointer DC W 0000 iz 0 direct page pointer E 1 3 ORG00008 ASM Title 08600008 Description This file initializes the interrupt exception vectors 50008 01 m If an interrupt occurs requiring the use of any of these vectors program flow will continue at the label which must added the programmer to his her code to put the program into background debug mode or some other appropriate routine Ck CK kk Ck CK CI Ck KC CK CI C CK C CK CI Ck CK CC CK CIC CK C CC Ck KC Ck CI Ck CK C Ck I Ck S x Mk ko ko ko ko ORG 0008 put the following code in memory starting at address 0008 of the map after the reset vector there is a total of 252 of these DC W BDM lines Vector Number
137. PWMB is not used until the end of a complete cycle This prevents spurious short or long pulses when register values are changed The current duty cycle value is stored in the appropriate PWM buffer register PWMBUFA or PW MBUFB The new value is transferred from the PWM register to the buffer register at the end of the current cycle Registers PWMA PWMB and PWNC are reset to 00 during reset These registers may be written or read at any time PWMC is implemented as the lower byte of a 16 bit register The upper byte is the CFORC register The buffer registers PWMBUFA and PWMBUFB are read only at all times and may be accessed as separate bytes or as one 16 bit register Pins PWMA and PWMB can also be used for general purpose output The values of the F1A and F1B bits in PWMC are driven out on the corresponding PWM pins when normal PWM operation is disabled When read the F1A and F1B bits reflect the states of the PWMA and PWMB pins M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL For More Information On This Product 11 19 Go to www freescale com Freescale Semiconductor Inc GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 20 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc APPENDIX A ELECTRICAL CHARACTERISTICS Table A 1 Maximum Ratings Num Rating Symbol Value Unit 1 Supply Voltage 2 3 0 3 to 6 5 Input Voltage 2 34 5 7 0 3 to 6 5 Inst
138. Product D 63 Go to www freescale com Freescale Semiconductor Inc D 7 13 SPI Control Register SPCR SPI Control Register YFFC38 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 SPIE SPE WOMP MSTR CPOL CPHA LSBF SIZE SPBR 7 0 RESET 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 SPCR contains parameters for configuring the SPI The register can be read or written at any time SPIE SPI Interrupt Enable 0 SPI interrupts disabled 1 SPI interrupts enabled SPE SPI Enable 0 SPI is disabled 1 is enabled WOMP Wired OR Mode for SPI Pins 0 Outputs have normal CMOS drivers 1 Pins designated for output by MDDR have open drain drivers regardless of whether the pins are used as SPI outputs or for general purpose and re gardless of whether the SPI is enabled MSTR Master Slave Mode Select 0 SPI is a slave device 1 SPI is system master CPOL Clock Polarity 0 The inactive state value of is logic level zero 1 The inactive state value of SCK is logic level one CPOL is used to determine the inactive state of the serial clock SCK It is used with CPHA to produce a desired clock data relationship between master and slave devices CPHA Clock Phase 0 Data captured on the leading edge of SCK and changed on the trailing edge of SCK 1 Data is changed on the leading edge of SCK and captured on the trailing edge of SCK CPHA determines which edge of SCK causes data to ch
139. RC filter The maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input Simple RC filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog signal to be measured Refer to 8 8 6 2 Error Resulting from Leakage In some cases the size of the capac itor at the pin may be very small Figure 8 10 is a simplified model of an input channel Refer to this model in the follow ing discussion of the interaction between the user s external circuitry and the circuitry inside the ADC EXTERNAL CIRCUIT INTERNAL CIRCUIT MODEL S1 RF 52 53 54 i 1 2 SOURCE VOLTAGE Rr FILTER IMPEDANCE SOURCE IMPEDANCE INCLUDED FILTER CAPACITOR Cs INTERNAL CAPACITANCE FOR A BYPASSED CHANNEL THIS IS THE CAPACITANCE Cpac CAPACITOR ARRAY INTERNAL VOLTAGE SOURCE FOR PRECHARGE Vppa 2 ADC SAMPLE MODEL Figure 8 10 Electrical Model of an A D Input Pin M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 21 Go to www freescale com Freescale Semiconductor Inc In Figure 8 10 Re and comprise the user s external filter circuit Cs is the internal sample capacitor Each channel has its own capacitor Cs is never precharged it re tains the value of the last sample V i
140. Reset is the highest priority CPU16 exception Unlike all other exceptions a reset oc curs at the end of a bus cycle and not at an instruction boundary Handling resets in this way prevents write cycles in progress at the time the reset signal is asserted from being corrupted However any processing in progress is aborted by the reset excep tion and cannot be restarted Only essential reset tasks are performed during excep tion processing Other initialization tasks must be accomplished by the exception handler routine Refer to 5 7 9 Reset Processing Summary for details on exception processing 5 7 2 Reset Control Logic SIM reset control logic determines the cause of a reset synchronizes request signals to CLKOUT and asserts reset control signals Reset control logic can drive three dif ferent internal signals EXTRST external reset drives the external reset pin CLKRST clock reset resets the clock module MSTRST master reset goes to all other internal circuits All resets are gated by CLKOUT Asynchronous resets are assumed to be catastroph ic An asynchronous reset can occur on any clock edge Synchronous resets are timed to occur at the end of bus cycles The SIM bus monitor is automatically enabled for synchronous resets When a bus cycle does not terminate normally the bus monitor terminates it Table 5 18 is a summary of reset sources SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 48 For More Information On This
141. Semiconductor Inc D 2 15 Software Watchdog Service Register SWSR Software Watchdog Service Register YFFA26 19 8 1 6 5 4 3 2 1 0 NOT USED SWSR 7 0 RESET 0 0 0 0 0 0 0 0 NOTES 1 This register is shown with a read value This register can be read or written at any time Bits 15 8 are unimplemented and will always read zero To reset the software watchdog 1 Write 55 to SWSR 2 Write AA to SWSR Both writes must occur in the order specified before the software watchdog times out but any number of instructions can occur between the two writes D 2 16 Port C Data Register PORTC Port C Data Register YFFA40 15 8 7 6 5 4 3 2 1 0 NOT USED 0 PC6 PC5 4 PCO RESET 0 1 1 1 1 1 1 1 This register latches data for chip select pins configured as discrete outputs This reg ister can be read or written at any time Bits 15 8 are unimplemented and will always read zero D 2 17 Chip Select Pin Assignment Registers CSPARO Chip Select Pin Assignment Register 0 YFFA44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 010 CS5PA 1 0 4 1 0 CS3P A 1 0 CS2PA 1 0 CS1PA 1 0 CSOPA L 0 5 01 RESET 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATAO Chip select pin assignment registers configure the chip select pins for discrete an alternate function or as an 8 bit or 16 bit chip select The possible encodings for each 2 bit field in CSPAR 0 1
142. T T T T TI TS EC EI EV AP CPU16 CCR bits differ from M68HC 1 1 CPU16 interrupt priority scheme differs from M68HC1 1 PA CPU16 CCR bits differ from M68HC 1 1 CPU16 interrupt priority scheme differs from M68HC1 1 SX Adds two to SK SP before transfer to XK IX SY XS XY YS YX BHS BSR CLI DES Replaced by AIS DEY INX JMP JSR Adds two to SK SP before transfer to YK IY T Subtracts two from XK IX before transfer to SK SP Transfers XK field to YK field Subtracts two from YK IY before transfer to SK SP Transfers YK field to XK field Waits indefinitely for interrupt or reset Generates a different stack frame T WAI NOTES 1 Freescale assemblers automatically translate ASL mnemonics CENTRAL PROCESSING UNIT M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 9 Instruction Format CPU16 instructions consist of an 8 bit opcode that can be preceded by an 8 bit prebyte and followed by one or more operands Opcodes are mapped in four 256 instruction pages Page 0 opcodes stand alone Page 1 2 and 3 opcodes are pointed to by a prebyte code on page 0 The prebytes are 17 page 1 27 page 2 and 37 page 3 Operands can be four bits eight bits or sixteen bits in length Since the CPU16 fetches 16 bit instruction words from even byte boundaries each instruction must cont
143. The SRAM is especially useful for system stacks and variable storage Table 6 1 SRAM Configuration Z Series Device Array Size 68 1671 1 Kbyte 68 1671 68 1671 68 1674 68 1674 68 1672 2 Kbytes 68 16273 4 Kbytes The SRAM can be mapped to any address that is a multiple of the array size so long as SRAM boundaries do not overlap the module control registers overlap makes the registers inaccessible Data can be read written in bytes words or long words SRAM is powered by Vpp in normal operation During power down SRAM contents can be maintained by power from the input Power switching between sources is auto matic 6 1 SRAM Register Block There are four SRAM control registers the RAM module configuration register RAM MCR the RAM test register RAMTST and the RAM array base address registers RAMBAH RAMBAL The module mapping bit MM in the SIM configuration register SIMCR defines the most significant bit ADDR23 of the IMB address for each M68HC16 M68CK16 and M68CM16 Z series module Because ADDR 23 20 are driven to the same value as ADDR 19 MM must be set to one If MM is cleared IMB modules are inaccessible For more information about how the state of MM affects the system refer to 5 2 1 Module Mapping The SRAM control register consists of eight bytes but not all locations are implement ed Unimplemented register addresses are read as zer
144. VCO off STSIM 0 32 768 kHz Vpp powered down RAM Standby Voltage Specified Vpp applied Vpp Vss MC68CK16Z1 Z4 RAM Standby Current 9 10 T Normal RAM operation Vbp gt Vgg 0 5 V 10 Transient condition 0 5 V 2 Vgg 2 Vgg 0 5 V SB 3 mA Standby operation lt Vss 0 5 V d 50 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 11 Low Voltage 16 78 MHz DC Characteristics Continued and V 2 7 to 3 6Vdc Ve 0 T T to T DDSYN Num Characteristic Symbol Min Max Unit 17 68 1621 24 Power Dissipation Pp 191 mW Input Capacitance 7 18 All input only pins Cin 10 pF All input output pins 20 Load Capacitance Group 1 I O Pins CLKOUT FREEZE QUOT IPIPEO 90 19 Group 2 I O Pins and CSBOOT BG CS CL 100 pF Group 3 Pins 100 Group 4 I O Pins 100 NOTES 1 Applies to Port ADA 7 0 AN 7 0 Port E 7 4 SIZ 1 0 AS DS Port F 7 0 IRQ 7 1 MODCLK Port GP 7 0 IC4 0C5 0C1 IC 3 1 OC 4 1 OC1 Port MCCI 7 0 TXD PCS 3 1 PCSO SS SCK MOSI MISO BKPT DSCLK DSI IPIPE1 PAI PCLK RESET RXD TSC 2 Input Only Pins EXTAL TSC BKPT DSCLK PAI PCLK RXD Output Only Pins CSBOOT BG CS1 CLKOUT FREEZE QUOT DSO IPIPEO PWMA PWMB Input Output Pins Gro
145. Voltage Limiting Diodes in a Negative Stress Circuit Another method for minimizing the impact of stress conditions on the ADC is to stra tegically allocate ADC inputs so that the lower accuracy inputs are adjacent to the in puts most likely to see stress conditions Finally suitable source impedances should be selected to meet design goals and min imize the effect of stress conditions 8 8 5 Analog Input Considerations The source impedance of the analog signal to be measured and any intermediate fil tering should be considered whether external multiplexing is used or not Figure 8 9 shows the connection of eight typical analog signal sources to one ADC analog input pin through a separate multiplexer chip Also an example of an analog signal source connected directly to a ADC analog input channel is displayed M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 19 Go to www freescale com Freescale Semiconductor Inc FILTERING AND TYPICAL MUX CHIP MC54HC 4051 MC74HC 4051 ANALOG SIGNAL SOURCE INTERCONNECT MC54HC4052 MC74HC4052 INTERCONNECT ADC MC54HC 4053 ETC R SOURCE R FILTER Ver I D C SOUR C FILTER CMUXIN R SOURCE R FILTER Sei 1 T 0 1 uF AE EB C SOURCE m C FILTER CMUXIN R SOURCE R FILTER ola T R MUXOUT C Tm SOURCE M FILTER MUXIN R SOURCE R FILTER IE T TE 1 _
146. abling frequency multiplication by a factor from one to eight Three Y bits and the X bit are located in the VCO clock output path to provide the ability to slow the system clock without disturbing the PLL When using a fast reference the clock frequency is determined by SYNCR bit settings as follows f fsys 15514 100268 9 The reset state of SYNCR 3F00 results a power on fsys of 8 388 MHz when fref is 4 194 MHZ For the device to perform correctly both the clock frequency and VCO frequency se lected by the W X and Y bits must be within the limits specified for the MCU In order for the VCO frequency to be within specifications less than or equal to the maximum system clock frequency multiplied by two the X bit must be set for system clock fre quencies greater than one half the maximum specified system clock Internal VCO frequency is determined by the following equations or On both slow and fast reference devices when an external system clock signal is ap plied MODCLK 0 during reset the PLL is disabled The duty cycle of this signal is critical especially at operating frequencies close to maximum The relationship be tween clock signal duty cycle and clock signal period is expressed as follows Minimum External Clock Period Minimum External Clock High Low Time 50 Percentage Variation of External Clock Input Duty Cycle Tables 5 2 5 3 and 5 4 show clock control multipliers for all possible co
147. and then write transmit data to the SCDR This clears the TDRE and TC indicators in the SCSR a SCI control register 0 SCCRO b Write a baud rate value into the BR field 2 Configure SCCR1 a Select 8 or 9 bit frame format M b Determine use PE and type PT of parity generation or detection To receive set the RE and HIE bits in SCCR1 Select use RWU and type WAKE of receiver wakeup Select idle line detection type ILT and enable or disable idle line interrupt ILIE d To transmit set TE and TIE bits in SCCR1 and enable or disable WOMC and TCIE bits Disable break transmission SBK for normal operation M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL For More Information On This Product 10 23 Go to www freescale com Freescale Semiconductor Inc MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 24 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 11 GENERAL PURPOSE TIMER This section is an overview of the general purpose timer GPT function Refer to the GPT Reference Manual GPTRM AD for complete information about the GPT mod ule 11 1 General The 11 channel general purpose timer GPT is used in systems where a moderate level of CPU control is required The GPT consists of a capture compare unit a pulse accumulator and two pulse width modulators A bus interface unit connects the GPT
148. array is driven by the sample buffer amp During final sampling time the sample capacitor and amplifier are bypassed and the multiplexer input charges the RC DAC array directly During resolution time the voltage in the RC DAC array is converted to a digital value and the value is stored in the SAR Initial sample time and transfer time are fixed at two ADC clock cycles each Final sam ple time can be 2 4 8 or 16 ADC clock cycles depending on the value of the STS field in ADCTLO Resolution time is ten cycles for 8 bit conversion and twelve cycles for 10 bit conversion Transfer and resolution require a minimum of 16 ADC clocks 8 us with a 2 1 MHz ADC clock for 8 bit resolution or 18 ADC clocks 9 us with a 2 1 MHz ADC clock for 10 bit resolution If maximum final sample time 16 ADC clocks is used total conversion time is 15 us for an 8 bit conversion or 16 us for a 10 bit conversion with a 2 1 MHz ADC clock Figures 8 2 and 8 3 illustrate the timing for 8 and 10 bit conversions respectively These diagrams assume a final sampling period of two ADC clocks TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF INITIAL FINAL SAMPLE TRANSFER SAMPLE RESOLUTION TIME 2 ADC CLOCKS 1 16 1 1 1 1 1 1 1 CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE SAR5 SAR4 SAR3 SAR2 SAR1 SARO EOC 2 6 CYCLES CYCLES SAR7 HM SAMP
149. as possible analog ground should be isolated from the digital ground This be done by cutting a separate ground plane for the analog ground Non minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground power points Minimum distance for trace runs when possible 8 8 4 Accommodating Positive Negative Stress Conditions Positive or negative stress refers to conditions which exceed nominally defined oper ating limits Examples include applying a voltage exceeding the normal limit on an input for example voltages outside of the suggested supply reference ranges or causing currents into or out of the pin which exceed normal limits ADC specific con siderations are voltages greater than Vpp4 Van or less than Vssa applied to an analog input which cause excessive currents into or out of the input Refer to APPENDIX A ELECTRICAL CHARACTERISTICS on exact magnitudes Both stress conditions can potentially disrupt conversion results on neighboring inputs Parasitic devices associated with CMOS processes can cause an immediate disrup tive influence on neighboring pins Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate Vss Vssa ground Under stress conditions current introduced on an adjacent pin can cause er rors on adjacent channels by developing a voltage drop across the adjacent external channel sourc
150. as the clock source for the capture compare unit or the PWM unit in place of one of the prescaler outputs PCLK has hysteresis Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored This pin can also be used as a general purpose input pin Refer to 11 7 Prescaler for more information 11 6 General Purpose I O Any GPT pin can be used for general purpose when it is not used for another pur pose Capture compare pins are bidirectional others can be used only for output or input I O direction is controlled by a data direction bit in the port GP data direction reg ister DDRGP Parallel data is read from and written to the port GP data register PORTGP Pin data can be read even when pins are configured for a timer function Data read from PORT GP always reflects the state of the external pin while data written to PORTGP may not always affect the external pin Data written to PORTGP does not immediately affect pins used for output compare functions but the data is latched When an output compare function is disabled the last data written to PORTGP is driven out on the associated pin if it is configured as an output Data written to PORTGP can cause input captures if the corresponding pin is configured for input capture function The pulse accumulator input PAI and the external clock input PCLK pins provide general purpose input The state of these pins can be read
151. at logic level one during QSPI interrupt A write to INTVO has no effect Reads of INTVO return a value of one At reset QIVR is initialized to 0F the uninitialized interrupt vector number To use interrupt driven serial communication a user defined vector number must be written to QIVR D 6 4 SCI Control Register SCCRO SCI Control Register 0 YFFCO8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED SCBR 12 0 RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 SCCRO contains the SCI baud rate selection field Baud rate must be set before the SCI is enabled The CPU16 can read and write SCCRO at any time Changing the val ue of SCCRO bits during a transfer operation disrupts operation Bits 15 13 Not Implemented SCBR 12 0 SCI Baud Rate SCI baud rate is programmed by writing a 13 bit value to this field Writing a value of zero to SCBR disables the baud rate generator The baud clock rate is calculated as follows fs E EE 5 Baud Rate 39 SGBRITO or f sys 32 x SCI Baud Rate Desired where SCBR 12 0 is in the range of 1 to 8191 SCBR 12 0 REGISTER SUMMARY M68HC16 Z SERIES D 40 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Writing a value of zero to SCBR disables the baud rate generator There are 8191 dif ferent bauds available The baud value depends on the value for SCBR and the sys tem clock as used in the equation above Table D
152. clamp values then use the larger of the calcu lated values 5 This parameter is periodically sampled rather than 100 tested Applies to single pin only 7 The values of external system components can change the maximum input current value and affect operation A voltage drop may occur across the external source impedances of the adjacent pins impacting conversions on these adjacent pins The actual maximum may need to be determined by testing the complete design 8 Current coupling is the ratio of the current induced from overvoltage positive or negative through an external series coupling resistor divided by the current induced on adjacent pins A voltage drop may occur across the external source impedances of the adjacent pins impacting conversions on these adjacent pins ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com A 62 Freescale Semiconductor Inc Table A 33 Low Voltage ADC DC Electrical Characteristics Operating Vss 0 Vdc ADCLK 1 05 MHz T within operating temperature range Num Parameter Symbol Min Max Unit 1 Analog Supply VDDA 2 7 3 6 V 2 Internal Digital Supply Vppi 2 7 3 6 V 3 Vgg Differential Voltage Vssi VssA 1 0 1 0 4 Vpp Differential Voltage Vppi VppA 0 6 0 6 V 5 Reference Voltage Low 3 VRL Vssa VppA 2 V 6 Reference Voltage
153. cleared single channel modes Table 8 8 is a summary of ADC operation when MULT is set multi channel modes Number of conversions per channel is determined by SCAN Channel num bers are given in order of conversion M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 9 Go to www freescale com 8 10 Freescale Semiconductor Inc Table 8 7 Single Channel Conversions MULT 0 S8CM CD CC CB CA Input Result Register 0 0 0 0 0 ANO RSLT 0 3 0 0 0 0 1 AN1 RSLT 0 3 0 0 0 AN2 RSLT 0 3 0 0 0 1 1 AN3 RSLT 0 3 0 0 0 AN4 RSLT 0 3 0 0 1 0 1 AN5 RSLT 0 3 0 0 0 AN6 RSLT 0 3 0 0 1 1 1 AN7 RSLT 0 3 0 1 0 Reserved RSLT 0 3 0 1 0 0 1 Reserved RSLT 0 3 0 1 0 Reserved RSLT 0 3 0 1 0 1 1 Reserved RSLT 0 3 0 1 1 0 0 RSLT 0 3 0 1 1 0 1 RSLT 0 3 0 1 1 1 0 Vn 2 RSLT 0 3 0 1 1 1 1 Test Reserved RSLT 0 3 1 0 0 ANO RSLT 0 7 1 0 0 0 1 AN1 RSLT 0 7 1 0 0 AN2 RSLT 0 7 1 0 0 1 1 RSLT 0 7 1 0 0 AN4 RSLT 0 7 1 0 1 0 1 AN5 RSLT 0 7 1 0 0 AN6 RSLT 0 7 1 0 1 1 1 AN7 RSLT 0 7 1 1 0 Reserved RSLT 0 7 1 1 0 0 1 Reserved RSLT 0 7 1 1 0 Reserved RSLT 0 7 1 1 0 1 1 Reserved RSLT 0 7 1 1 1 0 0 RSLT 0 7 1 1 1 Vn RSLT 0 7 1 1 1 1 0 Vn 2 RSLT 0 7 1 1 1 1 1 Test Reserved RSLT 0 7 NOTES 1 Result register is either RJURRX LJSRRX or LJURRX depend
154. during the interrupt acknowledge cycle and re spond if the priority of the service request corresponds to the mask value However before modules or external devices respond interrupt arbitration takes place Arbitration is performed by means of serial contention between values stored in indi vidual module interrupt arbitration IARB fields Each module that can make an inter rupt service request including the SIM has an IARB field in its configuration register IARB fields can be assigned values from 0000 to 1111 In order to implement an arbitration scheme each module that can request interrupt service must be assigned a unique non zero IARB field value during system initialization Arbitration priorities range from 960001 lowest to 961111 highest If the CPU16 recognizes an interrupt service request from a source that has an IARB field value of 960000 a spurious inter rupt exception is processed WARNING Do not assign the same arbitration priority to more than one module When two or more IARB fields have the same nonzero value the CPU16 interprets multiple vector numbers at the same time with un predictable consequences Because the EBI manages external interrupt requests the SIM IARB value is used for arbitration between internal and external interrupt requests The reset value of IARB for the SIM is 961111 and the reset IARB value for all other modules is 960000 M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MA
155. edge increments counter 1 PAI rising edge increments counter 1 0 Zero on PAI inhibits counting 1 1 One on PAI inhibits counting PCLKS PCLK Pin State Read Only 14 05 Input Capture 4 Output Compare 5 0 Output compare 5 enabled 1 Input capture 4 enabled PACLK 1 0 Pulse Accumulator Clock Select Gated Mode Table D 45 shows the PACLK 1 0 bit field effects Table D 45 PACLK 1 0 Effects PACLK 1 0 Pulse Accumulator Clock Selected 00 System clock divided by 512 01 Same clock used to increment TCNT 10 TOF flag from TCNT 11 External clock PCLK PACNT Pulse Accumulator Counter Eight bit read write counter used for external event counting or gated time accumula tion D 8 8 Input Capture Registers 1 3 TIC 1 3 Input Capture Registers 1 3 YFF9OE YFF912 The input capture registers are 16 bit read only registers used to latch the value of TCNT when a specified transition is detected on the corresponding input capture pin They are reset to FFFF D 8 9 Output Compare Registers 1 4 TOC 1 4 Output Compare Registers 1 4 YFF914 YFF91A The output compare registers are 16 bit read write registers which can be used as out put waveform controls or as elapsed time indicators For output compare functions they are written to a desired match value and compared against TCNT to control spec ified pin actions They are reset to FFFF M68HC16 Z SERIES REGISTER SUM
156. either left set or cleared Each successive bit is set or left cleared in descending order until all eight or ten bits have been resolved When conversion is complete the content of the SAR is transferred to the appropriate result register Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration 8 7 8 Result Registers Result registers are used to store data after conversion is complete The registers can be accessed from the IMB under ABIU control Each register can be read from three different addresses in the ADC memory map The format of the result data depends on the address from which it is read Table 8 9 shows the three types of formats M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 8 9 Result Register Formats Result Data Format Description Conversion result is unsigned right justified data Bits 9 0 are used for 10 bit resolution bits 7 0 are used for 8 bit conversion bits 9 8 are zero Bits 15 10 always return zero when read Unsigned right justified format Conversion result is signed left justified data Bits 15 6 are used for 10 bit resolution bits 15 8 are used for 8 bit conversion bits 7 6 are zero Although the ADC is unipolar it is assumed that the zero point is VRH VRL 2 when this format is used The value read from the register is an offset two s
157. enter freeze mode Refer to 4 14 4 Background Debug Mode for more information Freeze mode freezes the current state of the timer The prescaler and the pulse accu mulator do not increment and changes to the pins are ignored input pin synchronizers are not clocked All of the other timer functions that are controlled by the CPU operate normally For example registers can be written to change pin directions force output compares and read or write pins While the FREEZE signal is asserted the CPU has write access to registers and bits that are normally read only or write once The write once bits can be written to as often as needed The prescaler and the pulse accumulator remain stopped and the input pins are ignored until the FREEZE signal is negated the CPU is no longer in BDM the FRZO bit is cleared or the MCU is reset Activities that are in progress before FREEZE assertion are completed For example if an input edge on an input capture pin is detected just as the FREEZE signal is as serted the capture occurs and the corresponding interrupt flag is set M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL For More Information On This Product 11 3 Go to www freescale com Freescale Semiconductor Inc 11 3 3 Single Step Mode Two bits in GPTMCR support GPT debugging without using BDM When the STOPP bit is asserted the prescaler and the pulse accumulator stop counting and changes at input pins are ignored Reads
158. exception vector table are to be used for MCCI interrupts The SPI and both SCI interfaces have separate interrupt vectors adja cent to one another When initializing the MCCI program INTV 7 2 so that INTV 7 0 cor respond to three of the user defined vectors 40 FF INTV 1 0 are determined by the serial interface causing the interrupt and are set by the MCCI At reset MIVR is initialized to 0F which corresponds to the uninitialized interrupt vector in the exception table INTV 7 2 Interrupt Vector INTV 7 2 are the six high order bits of the three MCCI interrupt vectors for the MCCI as programmed by the user INTV 1 0 Interrupt Vector Source INTV 1 0 are the two low order bits of the three interrupt vectors for the MCCI They are automatically set by the MCCI to indicate the source of the interrupt Refer to Table D 38 Table D 38 Interrupt Vector Sources INTV 1 0 Source of Interrupt 00 SCIA SCIB SPI Writes to INTVO and INTV1 have no meaning or effect Reads of INTVO and INTV1 return a value of one D 7 5 SPI Interrupt Level Register ILSPI SPI Interrupt Level Register YFFCO6 13 2000000 8 7 6 5 4 3 2 1 0 15 14 1 9 NOT USED ILSPI 2 0 NOT USED NOT USED RESET 0 0 0 The ILSPI determines the priority level of interrupts requested by the SPI Bits 15 14 Not Implemented REGISTER SUMMARY M68HC16 Z SERIES D 56 For More Information On This Product USER S MANUAL Go to www fr
159. finish sending out byte The STRINGS STRING_IC1 DC W Input capture 1 caught a transition 0a 0d 00 STRING IC2 DC W Input capture 2 caught a rising edge 0a 0d 00 STRING IC3 DC W Input capture 3 caught a falling edge 0a 0d 00 STRING OC2 DC W 0a Output compare 2 just toggled 0a 0d 00 STRING PAOV DC W Pulse Accum has overflowed 10 times 07 0d 00 Exceptions Interrupts Note that every one of the GPT interrupt service routines clears its flag bit at the end of the routine before the RTI instruction EVEN IC1_ROUTINE execute when senses a transition LDX STRING_IC1 JSR SEND_STRING print the message BCLR TFLG1 01 clear the flag bit RTI 2 execute when IC2 senses a rising edge LDX STRING_IC2 JSR SEND_STRING print the message BCLR TFLG1 02 clear the IC2 flag bit RTI IC3 ROUTINE execute when IC3 senses a falling edge LDX STRING_IC3 JSR SEND_STRING print the message BCLR TFLG1 504 clear the flag bit RTI OC2 ROUTINE execute when OC2 does a toggle LDX STRING_OC2 JSR SEND_STRING print the message BCLR TFLG1 510 clear the OC2 flag bit RTI PAOV_ROUTINE 7execute on Pulse Accumulator Counter overflow if PAI pin tied bell approx every 5 sec if PAI pin tied PWMB bell approx every 10 min INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES 28 For More
160. for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven to guarantee this length of reset to the entire system If an internal source asserts a reset signal the reset control logic asserts the RESET pin for a minimum of 512 cycles If the reset signal is still asserted at the end of 512 cycles the control logic continues to assert the RESET pin until the internal reset sig nal is negated After 512 cycles have elapsed the RESET pin goes to an inactive high impedance state for ten cycles At the end of this 10 cycle period the RESET input is tested When the input is at logic level one reset exception processing begins If however the RESET input is at logic level zero reset control logic drives the pin low for another 512 cycles At the end of this period the pin again goes to high impedance state for ten cycles then it is tested again The process repeats until external RESET is released 5 7 7 Power On Reset When the SIM clock synthesizer is used to generate system clocks power on reset involves special circumstances related to application of the system and the clock syn thesizer power Regardless of clock source voltage must be applied to clock synthe sizer power input pin Vppsyw for the MCU to operate The following discussion assumes that Vppsyn is applied before and during reset which minimizes crystal start up time When Vppsyn is applied at power on
161. has not been transferred to the shifter Writing to SCDR again overwrites the data TDRE is set when the data in the TDR is trans ferred to the shifter Before new data can be written to the SCDR however the pro cessor must clear TDRE by writing to SCSR If new data is written to the SCDR without first clearing TDRE the data will not be transmitted The transmission complete TC flag in SCSR shows transmitter shifter state When 0 the shifter is busy TC is set when all shifting operations are completed TC is not automatically cleared The processor must clear it by first reading SCSR while TC is set then writing new data to SCDR M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL 10 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The state of the serial shifter is checked when the TE bit is set If TC 1 an idle frame is transmitted as a preamble to the following data frame If TC 0 the current opera tion continues until the final bit in the frame is sent then the preamble is transmitted The TC bit is set at the end of preamble transmission The SBK bit in SCCR1 is used to insert break frames a transmission A non zero integer number of break frames is transmitted while SBK is set Break transmission begins when SBK is set and ends with the transmission in progress at the time either SBK or TE is cleared If SBK is set while a transmission is i
162. in PITR A zero value turns off the periodic timer When the modulus counter value reaches zero an interrupt is generated The modulus counter is then reloaded with the value in PITM 7 0 and counting repeats If a new val ue is written to PITR it is loaded into the modulus counter when the current count is completed The following equation calculates the PIT period when a slow reference frequency is used PIT Period ref The following equation calculates the PIT period when a fast reference frequency is used fret PIT Period The following equation calculates the PIT period for an externally input clock frequen cy on both slow and fast reference frequency devices f sys PIT Period 5 4 7 Interrupt Priority and Vectoring Interrupt priority and vectoring are determined by the values of the periodic interrupt request level PIRQL 2 0 and periodic interrupt vector PIV fields in the periodic in terrupt control register PICR SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 28 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The PIRQL field is compared to the CPU16 interrupt priority mask to determine wheth er the interrupt is recognized Table 5 12 shows PIRQL 2 0 priority values Because of SIM hardware prioritization a PIT interrupt is serviced before an external interrupt request of the same priority The periodic timer continues to run when
163. in external event counting or gated time accumulation modes Figure 11 5 is a block diagram of the pulse accumulator GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 14 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2G INTERRUPT REQUESTS PAIF TMSK2 TFLG2 SYNCHRONIZER EDGE OVERFLOW PAI amp DETECT DIGITAL FILTER LOGIC 21 D PACNT MUX 8 BIT COUNTER ENABLE 2 M u IEEE PACTL 034 INTERNAL DATA BUS PCLK TCNT OVERFLOW CAPTURE COMPARE CLK MUX PRESCALER 512 16 32 PULSE ACC BLOCK Figure 11 5 Pulse Accumulator Block Diagram In event counting mode the counter increments each time a selected transition of the pulse accumulator input PAI pin is detected The maximum clocking rate is the sys tem clock divided by four In gated time accumulation mode a clock increments PACNT while the PAI pin is in the active state There are four possible clock sources Two bits in the TFLG2 register show pulse accumulator status The pulse accumulator flag PAIF indicates that a selected edge has been detected at the PAI pin The pulse accumulator overflow flag PAOVF indicates that the pulse accumulator count has rolled over from FF to 00 This can be used to extend the range of the counter be yond eight bits M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL
164. kHz 3 07 kHz 16 0 Hz 20 0 Hz 010 Div8 2 2 10 MHz Div 8 2 62 MHz Div 8 3 15 MHz 8 19 kHz 10 2 kHz 011 Div 16 1 05 MHz Div 16 1 31 MHz Div 16 1 57 MHz 4 09 kHz 5 15 kHz i i 10 0 Hz 12 Hz 1 54 2 8 0 Hz 110 Div 128 131 kHz Div 128 164 kHz 512 Hz 641 Hz 770 Hz 4 0 Hz 5 0 Hz 6 Hz 111 PCLK PCLK PCLK 256 PCLK 256 PCLK 256 PCLK 32768 PCLK 32768 PCLK 32768 F1A B Force Logic Level One on PWMA B 0 Force logic level zero output on pin 1 Force logic level one output on PWMA B pin 101 Div 64 262 kHz Div 64 328 kHz Div 64 393 kHz 1 02 kHz 1 28 kHz Div 128 197 kHz PCLK D 8 15 PWM Registers A B PWMA PWM Register A YFF926 PWMB PWM Register B YFF927 The value in these registers determines pulse width of the corresponding PWM output A value of 00 corresponds to continuously low output a value of 80 to 50 duty cy cle Maximum value FF selects an output that is high for 255 256 of the period Writes to these registers are buffered by PWMBUFA and PWMBUFB D 8 16 PWM Count Register PWMCNT PWM Count Register YFF928 PWMCNT is the 16 bit free running counter used for GPT PWM functions D 8 17 PWM Buffer Registers A B PWMBUFA PWM Buffer Register A YFF92A PWMBUFB PWM Buffer Register B YFF92B To prevent glitches when PWM duty cycle is changed the contents of PWMA and PWMB are transferred to these
165. leakage is a function of input source impedance conversion rate change in voltage between successive conversions and the size of the decoupling capacitor used Error levels are best determined empirically In general continuous conversion of the same channel may not be compatible with high source impedance ELECTRICAL CHARACTERISTICS For More Information On This Product M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 38 ADC Conversion Characteristics Operating Vbo and 5 0 5 for 20 25 MHz 10 for 16 MHz 0 T4 T to Ty 0 5 MHz Xfapcik lt 1 0 MHz 2 clock input sample time Num Symbol Typical Max Unit 1 8 Bit Resolution 1 Count 20 2 8 Differential Nonlinearity DNL 0 5 Counts 3 8 Bit Integral Nonlinearity INL 1 1 Counts 4 8 Bit Absolute Error AE 1 1 Counts 5 10 Bit Resolution 1 Count ee 6 10 Bit Differential Nonlinearity DNL 1 1 Counts 7 10 Bit Integral Nonlinearity INL 2 0 2 0 Counts 8 10 Bit Absolute Error AE Counts 9 Impedance at Input Rs 20 NOTES 1 At Van 5 12 V one 10 bit count 5 mV and one 8 bit count 20 mV 2 8 bit absolute error of 1 count 20 mV includes 1 2 count 10 mV inherent quantization error and 1 2 count 10 mV circuit differential integral and offset error 3 Conversi
166. logic level of DATAO during reset selects the boot ROM port size When DATAO is held low during reset port size is eight bits When DATAO is held high during reset port size is 16 bits DATAO has a weak internal pull up driver so that a 16 bit port is selected by default M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 69 Go to www freescale com Freescale Semiconductor Inc However the internal pull up driver can be overcome by bus loading effects To en sure a particular configuration out of reset use an active device to put DATAO ina known state during reset The base address field in the boot chip select base address register CSBARBT has a reset value of all zeros so that when the initial access to address 000000 is made an address match occurs and the CSBOOT signal is asserted The block size field in CSBARBT has a reset value of 512 Kbytes Table 5 26 shows CSBOOT reset values Table 5 26 CSBOOT Base and Option Register Reset Values Fields Reset Values Base address 000000 Block size 512 Kbyte Async sync mode Asynchronous mode Upper lower byte Both bytes Read write Read write AS DS AS DSACK 13 wait states Address space Supervisor space IPL Any level Autovector Interrupt vector externally NOTES 1 These fields are not used unless Address space is set to CPU space 5 10 Parallel Input Output Ports Sixteen SIM pins can be conf
167. negated When CPHA 1 a transfer begins at the edge of the first SCK cycle and ends when SPIF is set Refer to 10 3 4 SPI Clock Phase and Polarity Controls for more infor mation on transfer periods and on avoiding write collision errors When a write collision occurs the WCOL bit in the SPSR is set To clear WCOL read the SPSR while WCOL is set and then either read the SPDR either before or after SPIF is set or write the SPDR after SPIF is set Writing the SPDR before SPIF is set results in a second write collision error This process clears SPIF as well as WCOL 10 3 9 Mode Fault When the SPI system is configured as a master and the SS input line is asserted a mode fault error occurs and the MODF bit in the SPSR is set Only an SPI master can experience a mode fault error caused when a second SPI device becomes a master and selects this device as if it were a slave To avoid latchup caused by contention between two pin drivers the MCU does the fol lowing when it detects a mode fault error Forces the MSTR control bit to zero to reconfigure the SPI as a slave Forces the SPE control bit to zero to disable the SPI system Sets the MODF status flag and generates an SPI interrupt if SPIE 1 Clears the appropriate bits in the MDDR to configure all SPI pins except the SS pin as inputs After correcting the problems that led to the mode fault clear MODF by reading the SPSR while MODF is set and then writing to the SPCR Control
168. ns 103 2 Valid to AS or DS Asserted tpovsn ns 104 AS or DS Valid to Phase 1 Negated tsaPiNn ns 105 AS or DS Negated to Phase 2 Negated 4 SNP2N ns NOTES 1 Refer to notes in Table A 18 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 22 For More information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 17 20 97 MHz AC Timing Vpp 5 0 5 0 T T to T y Num Characteristic Symbol Min Max Unit s 1A Period tEcyc 381 ns 2A Pulse Width tecw 183 ns 4A 5A Rise and Fall Time All Outputs except CLKOUT tet 8 ns 4B 5B External Clock Input Rise and Fall Time 5 ns 7 Clock High to ADDR Data FC SIZE High Impedance CHAZx 0 47 ns 9A AS to DS or CS Asserted Read tstsa 10 10 ns 11 ADDR FC SIZE Valid to AS CS and DS Read Asserted tAVSA 10 ns 13 5 DS CS Negated to ADDR FC SIZE Invalid Address Hold 10 ns 14 AS CS and DS Read Width Asserted tswa 80 ns 14A 05 CS Width Asserted Write tewAW 36 ns 14B 5 CS and DS Read Width Asserted Fast Cycle tswow 32 ns 15 AS DS CS Width Negated tsn 32 ns 17 AS DS CS Negated to R W High teNRN 10 ns 21 R W High to AS CS Asserted tRAAA 10 ns 22 R W Low to DS CS Asserted Write 54 ns 24 Data Out Valid
169. of reset However the internal pull up drivers can be overcome by bus loading effects To ensure a particular configuration out of reset use an active device to put the data lines in a known state during reset The base address fields in chip select base ad dress registers CSBAR 0 10 and chip select option registers CSOR 0 10 have the set values shown in Table 5 25 The BYTE fields of CSOR 0 10 have a reset value of disable so that a chip select signal cannot be asserted until the base and option reg isters are initialized Table 5 25 Chip Select Base and Option Register Reset Values Fields Reset Values Base address 000000 Block size 2 Kbyte Async sync mode Asynchronous mode Upper lower byte Disabled Read write Disabled AS DS AS DSACK No wait states Address space CPU space IPL Any level Autovector External interrupt vector Following reset the MCU fetches the initial stack pointer and program counter values from the exception vector table beginning at 000000 in supervisor program space The CSBOOT chip select signal is used to select an external boot device mapped to a base address of 000000 The MSB of the CSBTPA field in CSPARO has a reset value of one so that chip select function is selected by default out of reset The BYTE field in chip select option register CSORBT has a reset value of both bytes so that the select signal is enabled out of reset The LSB of the CSBOOT field determined by the
170. of the mechanism the CPU16 uses to fetch and execute instructions The functional divisions in the model do not necessarily correspond to physical subunits of the microprocessor As shown in Figure 4 5 there are three functional blocks involved in fetching decod ing and executing instructions These are the microsequencer the instruction pipe line and the execution unit These elements function concurrently All three may be active at any given time CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 34 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc IPIPEO IPIPE1 MICROSEQUENCER INSTRUCTION PIPELINE DATA BUS EXECUTION UNIT 16 EXEC UNIT MODEL Figure 4 5 Instruction Execution Model 4 10 1 Microsequencer The microsequencer controls the order in which instructions are fetched advanced through the pipeline and executed It increments the program counter and generates multiplexed external tracking signals IPIPEO and IPIPE1 from internal signals that con trol execution sequence 4 10 2 Instruction Pipeline The pipeline is a three stage FIFO that holds instructions while they are decoded and executed Depending upon instruction size as many as three instructions can be in the pipeline at one time single word instructions one held in stage C one being exe cuted in stage B and one latched in stage A 4 10 3 Exe
171. only pins can be put in a known state by external pull up resistors external logic on input output or output only pins during this time must condition the lines Active drivers require high impedance buffers or isolation resistors to prevent conflict Figure 5 20 is a timing diagram for power on reset It shows the relationships between RESET Vpp and bus signals CLKOUT LOCK 2 0 5 2 lt gt lt 512 0 5 gt 10 10 5 5 7 BUS CYCLES BUS STATE ADDRESS AND UNKNOWN CONTROL SIGNALS PE THREE STATED NOTES 1 INTERNAL START UP TIME 2 FIRST INSTRUCTION FETCHED 16 POR TIM Figure 5 20 Power On Reset 5 7 8 Use of the Three State Control Pin Asserting the three state control TSC input causes the MCU to put all output drivers in a disabled high impedance state The signal must remain asserted for approxi mately ten clock cycles in order for drivers to change state When the internal clock synthesizer is used MODCLK held high during reset synthe sizer ramp up time affects how long the ten cycles take Worst case is approximately 20 milliseconds from TSC assertion When an external clock signal is applied MODCLK held low during reset pins go to high impedance state as soon after TSC assertion as approximately ten clock pulses have been applied to the EXTAL pin SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 56 For More Information
172. operation of the submodule M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product Go to www freescale com D 57 Freescale Semiconductor Inc D 7 7 MCCI Data Direction Register MDDR MCCI Data Direction Register YFFCOA 15 8 7 6 5 4 3 2 1 0 NOT USED DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 0081 DDRO RESET 0 0 0 0 0 0 0 0 MDDR determines whether pins configured for general purpose are inputs or out puts MDDR affects both SPI function and I O function During reset all MCCI pins are configured as inputs Table D 40 shows the effect of MDDR on pin function Table D 40 Effect of MDDR on MCCI Pin Function MCCI Pin Mode MDDR Bit Bit State Pin Function MISO Master DDRO 0 Serial data input to SPI 1 Disables data input Slave 0 Disables data output 1 Serial data output from SPI MOSI Master DDR1 0 Disables data output 1 Serial data output from SPI Slave 0 Serial data input to SPI 1 Disables data input SCK Master DDR2 Clock output from SPI Slave Clock input to SPI SS Master DDR3 0 Assertion causes mode fault 1 General purpose I O Slave 0 SPI slave select input 1 Disables slave select input RXDB2 DDR4 0 General purpose I O 1 Serial data input to SCIB TXDB DDR5 0 General purpose 1 Serial data output from SCIB RXDA DDR6 0 General purpose 1 Serial data input to SCIA DDR7 0 General purpose
173. or LSB The system can be configured as a master or slave device Figure 10 2 shows a block diagram of the SPI MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc INTERNAL MCU CLOCK MODULUS M3 SE COUNTER CLOCK SPI CLOCK MASTER SELECT y 5 2 BAUD SPI CONTROL 8 E SPI STATUS REGISTER SPIINTERRUPT INTERNAL REQUEST DATA BUS MCCI SPI BLOCK MSTR SPE WOMP ID SPI CONTROL REGISTER Figure 10 2 SPI Block Diagram Clock control logic allows a selection of clock polarity and a choice of two clocking pro tocols to accommodate most available synchronous serial peripheral devices When the SPI is configured as a master software selects one of 254 different bit rates for the serial clock During an SPI transfer data is simultaneously transmitted shifted out serially and re ceived shifted in serially A serial clock line synchronizes shifting and sampling of the information on the two serial data lines A slave select line allows individual selection of a slave SPI device Slave devices which are not selected do not interfere with SPI bus activities On a master SPI device the slave select line can optionally be used to indicate a multiple master bus contention M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANU
174. r4 nj n aaa FE 383 i 5 NOTES 1 MMMMM MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK HCIZUCKZUCNZIZ23 144 PIN QFP Figure 4 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments for 144 Pin Package M68HC16 Z SERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL For More Information On This Product BS Go to www freescale com Freescale Semiconductor Inc lt gt BKPT DSCLK e VRHP AS PES ANS PADAS DS PE4 AN4 PADA4 MPT PER AN3 PADA3 DSACRIPE1 AN2 PADA2 DSACROPEO 1 ADDRO ANO PADAO DATA15 VSSA DATA14 VDDA DATA13 VSS DATA12 VDD DATA11 ADDR18 DATA10 ADDR17 VSS ADDR16 NC ADDR15 6 1 68 1674 phi 1 ADDR12 DATA6 1 ATWLYYWW2 ADDR11 DATAS L_ 1 ADDR10 DATA4 ADDR NC NC VSS VSS NC NC DATA3 ADDR8 DATA2 ADDR DATA1 ADDR6 DATAO ADDR5 ADDR4 FCO CS3 P CO ADDR3 VSS VSS VDD VDD FC1CS4 PC1 ADDR2 FC2 CS3 PC2 ADDR1 BR CSO TXDA PMC7 Rao SE 0 Q TW 0 QM 2 MED IIO Le e b A 9 i 2 A R H i 9 NOTES 1 MASK OPTION NUMBER 7 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK 16241 1624 144 PIN QFP Figure 5 MC68HC16Z4 CKZ4 Pin Assignments for 144 Package MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z SERIES B 6 For More Infor
175. serial shifting to and from the data register begins with the LSB LSBF 1 or MSB LSBF 0 M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL 10 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 3 8 Write Collision A write collision occurs if an attempt is made to write the SPDR while a transfer is in progress Since the SPDR is not double buffered in the transmit direction a successful write to SPDR would cause data to be written directly into the SPI shift register Be cause this would corrupt any transfer in progress a write collision error is generated instead The transfer continues undisturbed the data that caused the error is not writ ten to the shifter and the WCOL bit in SPSR is set No SPI interrupt is generated A write collision is normally a slave error because a slave has no control over when a master initiates a transfer Since a master is in control of the transfer software can avoid a write collision error generated by the master The SPI logic can however de tect a write collision in a master as well as in a slave What constitutes a transfer in progress depends on the SPI configuration For a mas ter a transfer starts when data is written to the SPDR and ends when SPIF is set For a slave the beginning and ending points of a transfer depend on the value of CPHA When CPHA 0 the transfer begins when SS is asserted and ends when it is
176. set NF Noise Error 0 No noise detected in the received data 1 Noise detected in the received data FE Framing Error 0 No framing error detected in the received data 1 Framing error or break detected in the received data PF Parity Error 0 No parity error detected in the received data 1 Parity error detected in the received data D 7 12 SCI Data Register SCDRA SCIA Data Register YFFC1E SCDRB SCIB Data Register YFFC2E 15 9 8 7 6 5 4 3 2 1 0 NOT USED R8 T8 R7 T7 8616 5 75 R3 T3 8212 ROMO RESET U U U U U U U U U SCDR consists of two data registers located at the same address The receive data register RDR is a read only register that contains data received by the SCI serial in terface Data comes into the receive serial shifter and is transferred to RDR The trans mit data register TDR is a write only register that contains data to be transmitted Data is first written to TDR then transferred to the transmit serial shifter where addi tional format bits are added before transmission R 7 0 T 7 0 contain either the first eight data bits received when SCDR is read or the first eight data bits to be transmitted when SCDR is written R8 T8 are used when the SCI is configured for nine bit opera tion When the SCI is configured for 8 bit operation R8 T8 have no meaning or effect M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This
177. signals at the same time more than one bit in RSR may be set This register can be read at any time a write has no effect Bits 15 8 are unimple mented and always read zero EXT External Reset Reset caused by the RESET pin REGISTER SUMMARY M68HC16 Z SERIES D 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc POW Power Up Reset Reset caused by the power up reset circuit SW Software Watchdog Reset Reset caused by the software watchdog circuit HLT Halt Monitor Reset Reset caused by the halt monitor SYS System Reset The CPU16 does not support this function This bit will never be set TST Test Submodule Reset Reset caused by the test submodule Used during factory test reserved operating mode only D 2 5 System Integration Test Register E SIMTRE System Integration Test Register E YFFA08 Used for factory test only D 2 6 Port E Data Register PORTEO Port EO Data Register YFFA10 PORTE1 Port E1 Data Register YFFA12 15 8 7 6 5 4 3 2 1 0 RESET U U U U U U U U This register can be accessed in two locations and can be read or written at any time A write to this register is stored in an internal data latch and if any pin in the corre sponding port is configured as an output the value stored for that bit is driven out on the pin A read of this data register returns the value at the pin only if the pin is config ure
178. start up time is affected by spe cific crystal parameters and by oscillator circuit design Vpp ramp up time also affects pin state during reset Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and timing specifications During power on reset an internal circuit in the SIM drives the IMB internal MSTRST and external EXTRST reset lines The power on reset circuit releases the internal re set line as Vpp ramps up to the minimum operating voltage and SIM pins are initial ized to the values shown in Table 5 21 When Vpp reaches the minimum operating voltage the clock synthesizer VCO begins operation Clock frequency ramps up to specified limp mode frequency fimp The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse NOTE Vppsyn and all Vpp pins must be powered Applying power to VppsvN Only will cause errant behavior of the MCU M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 9 55 Go to www freescale com Freescale Semiconductor Inc The SIM clock synthesizer provides clock signals to the other MCU modules After the clock is running and MSTRST is asserted for at least four clock cycles these modules reset Vpp ramp time and VCO frequency ramp time determine how long the four cy cles take Worst case is approximately 15 milliseconds During this period module port pins may be in an indeterminate state While input
179. td ae een A 47 Pele SP Slave ben EHE HERR dr E paci hada A 48 Pele OSPI ming Slave DPA S T A 48 A20 SPI Timing Master CPHA eJ A 51 A 21 SPI Timing Master GPISA m A 51 A 22 SPI Timing Slave 0 sese pr rnnt iex rk ec ica enia A 52 A23 T A 52 A 24 Input Signal Conditioner A 53 A 25 Pulse Accumulator Event Counting Mode Leading Edge A 54 A 26 Pulse Accumulator Gated Mode Count While Pin High A 55 A 27 Pulse Accumulator Using TOF as Gated Mode Clock A 56 28 PWMx Register 01 Fast Mode A 56 A 29 Output Compare Toggle Pin State 1 A 57 A 30 Input Capture Capture on Rising Edge 2 A 58 A 31 General Purpose Input A 59 A 32 General Purpose Output Causes Input Capture A 60 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com D 1 Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Title Page
180. than the sampled input voltage Comparator output is fed to the digital control logic which sets or clears each bit in the successive approx imation register in sequence MSB first 8 7 Digital Control Subsystem The digital control subsystem includes control and status registers clock and prescal er control logic channel and reference select logic conversion sequence control logic and the successive approximation register The subsystem controls the multiplexer and the output of the RC array during sample and conversion periods stores the results of comparison in the successive approxi mation register then transfers results to the result registers 8 7 1 Control Status Registers There are two control registers ADCTLO ADCTL1 and one status register ADCSTAT ADCTLO controls conversion resolution sample time and clock prescal er value ADCTL1 controls analog input selection conversion mode and initiation of conversion A write to ADCTLO aborts the current conversion sequence and halts the ADC Conversion must be restarted by writing to ADCTL1 A write to ADCTL1 aborts the current conversion sequence and starts a new sequence with parameters altered by the write ADCSTAT shows conversion sequence status conversion channel sta tus and conversion completion status The following paragraphs are a general discussion of control function D 5 Analog to Digital Converter Module shows the ADC address map and discusses register bits
181. the QSPI relinquishes control of these pins and PORTQS drives them to logic zero from the inactive SCK and PCSO states of logic one Before master mode operation is initiated QSM register DDRQS is written last to di rect the data flow on the QSPI pins used Configure the SCK MOSI and appropriate chip select pins PCS 3 0 as outputs The MISO pin must be configured as an input After pins are assigned and configured write appropriate data to the command queue If data is to be transmitted write the data to transmit RAM Initialize the queue pointers as appropriate QUEUED SERIAL MODULE M68HC16 Z SERIES 9 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Data transfer is synchronized with the internally generated serial clock SCK Control bits CPHA CPOL in SPCRO control clock phase and polarity Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing data from the MOSI pin and to latch incoming data from the MISO pin Baud rate is selected by writing a value from two to 255 into SPBR 7 0 in SPCRO The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system clock The following expressions apply to the SCK baud rate or f sys SPBR 7 0 53 SCK Baud Rate Desired Giving SPBR 7 0 a value of zero or one disables the baud rate generator and SCK assumes its inactive state The DSCK bit in each command R
182. the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part freescale semiconductor Motorola Inc 1997 User s Manual M68HC16Z Series 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Paragraph Title Page SECTION 1 INTRODUCTION SECTION 2 NOMENCLATURE 2 1 Symbols and OPa atore ERE ERN 2 1 2 2 Register pue 2 2 2 3 Register Mnemonics GRON URN HIREUE 2 3 2 4 At 2 6 3 OVERVIEW 3 1 M68HC16 Z Series MCU Features 3 1 3 1 1 Central Processor Unit CPU16 CPUI6L 3 1 3 1 2 System Integration Module SIM SIML
183. the interrupt is disabled Table 5 12 Periodic Interrupt Priority PIRQL 2 0 Priority Level 000 Periodic Interrupt Disabled 010 Interrupt priority level 2 100 Interrupt priority level 4 110 Interrupt priority level 6 The PIV field contains the periodic interrupt vector The vector is placed on the IMB when an interrupt request is made The vector number is used to calculate the address of the appropriate exception vector in the exception vector table The reset value of the PIV field is 0F which corresponds to the uninitialized interrupt exception vector 5 4 8 Low Power STOP Operation When the CPU16 executes the LPSTOP instruction the current interrupt priority mask is stored in the clock control logic internal clocks are disabled according to the state of the STSIM bit in the SYNCR and the MCU enters low power stop mode The bus monitor halt monitor and spurious interrupt monitor are all inactive during low power stop During low power stop mode the clock input to the software watchdog timer is dis abled and the timer stops The software watchdog begins to run again on the first rising clock edge after low power stop mode ends The watchdog is not reset by low power stop mode A service sequence must be performed to reset the timer The periodic interrupt timer does not respond to the LPSTOP instruction but continues to run during LPSTOP To stop the periodic interrupt timer PITR must be loaded with a zer
184. the memory map Although the base address loaded into ROMBAH and ROMBAL during reset is mask programmed as user specified these registers can be written after reset to change the default array address if the base address lock bit LOCK in MRMCR is not masked to a value of one NOTE In the CPU16 ADDR 23 20 follow the logic state of ADDR19 The MRM array must not be mapped to addresses 7FF000 7FFFFF which are inaccessible to the CPU16 If mapped to these addresses the array remains inaccessible until a reset occurs or it is remapped outside of this range M68HC16 Z SERIES MASKED ROM MODULE USER S MANUAL For More Information On This Product 7 1 Go to www freescale com Freescale Semiconductor Inc The MRM array can be mapped to any 8 Kbyte boundary in the memory map but must not overlap other module control registers overlap makes the registers inaccessible If the array overlaps the MRM register block addresses in the register block are ac cessed instead of the corresponding ROM array addresses ROMBAH and ROMBAL can only be written while the ROM is in low power stop mode MRMCR STOP 1 and the base address lock MRMCR LOCK 0 is disabled LOCK can be written once only to a value of one subsequent writes are ignored This prevents accidental remapping of the array 7 3 MRM Array Address Space Type ASPO 1 0 in MRMCR determines ROM array address space type The module can respond to both program and data space acc
185. the system clock as used in the equa tion above Table D 41 shows possible baud rates for a 16 78 MHz system clock The maximum baud rate with this system clock speed is 524 kbaud Table D 41 Examples of SCI Baud Rates a B is p Percent Error Value of SCBR 500 00 00 524 288 00 4 86 1 38 400 00 37 449 14 2 48 14 32 768 00 32 768 00 0 00 16 19 200 00 19 418 07 1 14 27 9 600 00 9 532 51 0 70 55 4 800 00 4 809 98 0 21 109 2 400 00 2 404 99 0 21 218 1 200 00 1 199 74 0 02 437 600 00 599 87 0 02 874 300 00 299 94 0 02 1 748 110 00 110 01 0 01 4 766 64 00 64 00 0 01 8 191 D 7 10 SCI Control Register 1 SCCR1A SCIA Control Register 1 YFFC1A SCCR1B SCIB Control Register 1 YFFC2A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOOPS WOMS ILT PT PE M WAKE TIE TCIE RIE ILIE TE RE RWU SBK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 contains SCI configuration parameters including transmitter and receiver en able bits interrupt enable bits and operating mode enable bits SCCRO can be read or written at any time The SCI can modify the RWU bit under certain circumstances Changing the value of SCCR1 bits during a transfer operation can disrupt the transfer REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com D 60 Freescale Semiconductor Inc Bit 15
186. to the MPAR to assign the following pins to the SPI MISO MOSI and SS MISO is used for serial data output in slave mode and MOSI is used for serial data input Either or both may be necessary depending on the particular application SCK is the input serial clock SS selects the SPI when asserted 3 Write to the MDDR to direct the data flow on SPI pins Configure the SCK MOSI and SS pins as inputs Configure MISO as an output 4 Write to the SPCR to assign values for CPHA CPOL SIZE LSBF WOMP and SPIE Set the MSTR bit to select master operation Set the SPE bit to enable the SPI The BAUD field in the SPCR of the slave device has no effect on SPI operation When SPE is set and MSTR is clear a low state on the SS pin initiates slave mode operation The SS pin is used only as an input After a byte or word of data is transmitted the SPI sets the SPIF flag If the SPIE bit in SPCR is set an interrupt request is generated when SPIF is asserted Transfer is synchronized with the externally generated SCK The CPHA and CPOL bits determine the SCK edge on which the slave MCU latches incoming data from the MOSI pin and drives outgoing data from the MISO pin 10 3 4 SPI Clock Phase and Polarity Controls Two bits in the SPCR determine SCK phase and polarity The clock polarity CPOL bit selects clock polarity high true or low true clock The clock phase control bit CPHA selects one of two transfer formats and affects the timing of
187. to the intermodule bus IMB Figure 11 1 is a block diagram of the GPT The capture compare unit features three input capture channels four output compare channels and one channel that can be selected as input capture or output compare These channels share a 16 bit free running counter TCNT that derives its clock from nine stage prescaler or from the external clock input signal PCLK Pulse accumulator channel logic includes an 8 bit counter The pulse accumulator can operate in either event counting mode or gated time accumulation mode Pulse width modulator outputs are periodic waveforms whose duty cycles can be in dependently selected and modified by user software The PWM circuits share a 16 bit free running counter that can be clocked by the same nine stage prescaler used by the capture compare unit or by the PCLK input All GPT pins can also be used for general purpose input output The input capture and output compare pins form a bidirectional 8 bit parallel port port GP PWM pins are outputs only PAI and PCLK pins are inputs only M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL 11 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc OC1 PGP3 IC1 PGP0 OC2 OC1 PGP4 IC2 PGP 1 CAPTURE COMPARE UNIT OC3 OC1 PGP5 2 OC4 OC1 PGP6 IC4 OC5 OC1 PGP7 PULSE ACCUMULATOR PAI PRESCALER PCLK PWMA PWM UNIT PWMB BUS INTERFACE GPT BLOCK Figure 11 1 GPT Bloc
188. two successive byte transfer operations Figure 4 3 shows how each CPU16 data type is organized in memory Consecutive even addresses show size and alignment M68HC16 Z SERIES CENTRAL PROCESSOR UNIT USER S MANUAL For More Information On This Product 47 Go to www freescale com Freescale Semiconductor Inc Address Type 0000 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 15 14 13 12 11110 9 8 7 6 5 4 3 2 1 0 0002 BYTEO BYTE1 0004 X OFFSET Y OFFSET OFFSET Y OFFSET 0006 BCD1 BCDO BCD1 BCDO 0008 WORD 0 000A WORD 1 000C MSW LONG WORD 0 000E LSW LONG WORD 0 0010 MSW LONG WORD 1 0012 LSW LONG WORD 1 0014 lt Radix Point 16 BIT SIGNED FRACTION 0 0016 lt Radix Point 16 BIT SIGNED FRACTION 1 0018 lt Radix Point MSW 32 BIT SIGNED FRACTION 0 001A LSW 32 BIT SIGNED FRACTION 0 0 001C lt Radix Point MSW 32 BIT SIGNED FRACTION 1 001E LSW 32 BIT SIGNED FRACTION 1 0 MAC Data Types 35 32 31 16 lt Radix Point MSW 32 BIT SIGNED FRACTION 15 0 I LSW 32 BIT SIGNED FRACTION 16 BIT SIGNED FRACTION Radix Point Address Data Type 16 15 4 Bit Address Extension 16 Bit Byte Address Figure 4 3 Data Types and Memory Organization 4 6 Addressing Modes The CPU16 uses nine types of ad
189. vectors are stored in a vector table located in the first 512 bytes of address bank 0 The CPU16 uses vector numbers to calculate displacement into the table Re fer to 4 13 Exceptions for more information 5 8 2 Interrupt Priority and Recognition The CPU16 provides for seven levels of interrupt priority 1 7 seven automatic terrupt vectors and 200 assignable interrupt vectors All interrupts with priorities less than seven can be masked by the interrupt priority IP field in the condition code register There are seven interrupt request signals IRQ 7 1 These signals are used internally on the IMB and there are corresponding pins for external interrupt service requests The CPU16 treats all interrupt requests as though they come from internal modules external interrupt requests are treated as interrupt service requests from the SIM Each of the interrupt request signals corresponds to an interrupt priority level IRQ1 has the lowest priority and IRQ7 the highest The IP field consists of three bits CCR 7 5 Binary values 96000 to 96111 provide eight priority masks Masks prevent an interrupt request of a priority less than or equal to the mask value except for IRQ7 from being recognized and processed When IP contains 96000 no interrupt is masked During exception processing the IP field is set to the priority of the interrupt being serviced Interrupt recognition is determined by interrupt priority level and inter
190. with fapc_ rate Reduced conversion accuracy occurs at maximum M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 63 Go to www freescale com Freescale Semiconductor Inc Table A 35 5V ADC DC Electrical Characteristics Operating Vss 0 Vdc ADCLK 2 1 MHz T T to T Num Parameter Symbol Min Max Unit 1 Analog Supply VDDA 4 5 5 5 V 2 Internal Digital Supply Vppi 4 5 5 5 V 3 Differential Voltage Vssi VssA 1 0 1 0 4 Vpp Differential Voltage Vppi VppA 1 0 1 0 V 5 Reference Voltage Low VRL Vssa VppA 2 V 6 Reference Voltage High VRH Vppa 2 VDDA V 7 Vger Differential Voltage VRH Vn 4 5 5 5 V 8 Input Voltage ViNDC VssA V 9 Input High Port ADA 0 7 Vppa Vppa 0 3 V 10 Input Low Port ADA VssA 0 3 0 2 VppA V Analog Supply Current 11 Normal Operation IDDA 1 0 mA Low Power Stop 200 uA 12 Reference Supply Current IREF 250 uA 13 Input Current Channel 150 nA 14 Total Input Capacitance Not Sampling 10 pF 15 Total Input Capacitance Sampling Cins 15 pF NOTES 1 Refers to operation over full temperature and frequency range 2 To obtain full scale full range results Vssa lt Vni lt lt lt 3 Accuracy tested and guaranteed at Vg 5 0 V 5 for 20 25 MHz 10 for 16 MHz
191. 0 Interrupts Exceptions BDM BGND exception vectors point here and put the user into background debug mode E 2 1 4 Example 4 Software Watchdog Periodic Interrupt and Autovector Demo E 18 Description demonstrates the sof interrupt and an autovector interrupt runs a clock which is updated on the dummy terminal Every eight seconds the COP will force a reset unless IRQ6 is grounded When IRQ6 is pulled low an autovectored interrupt routine will feed the watchdog with 55 and AA and the clock will run without being reset on the dummy terminal This program the periodic The periodic tware watchdog ACKCkCk kCk ck ckCk ck kCk ck kk ck kck ck ck ck ck ckck ck ck ck ck ck ck ck ck ck kCk ck kCk ck ck k ck kk ck kk ck ck ck k ck ck k ck ck k ck k kk k k k kk INCLUDE EQUATES ASM table of EQUates for common registers INCLUDE ORGOO000 ASM initialize reset vectors INCLUDE ORGOO008 ASM initialize interrupt vectors ORG 002C put address of autovector routine DC W AUTOV at the level 6 vector IRQ6 ORG 0070 put address of periodic interrupt routine DC W VECRT jat lst user defined interrupt vector INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc ORG 0200 xx Initialize
192. 0 Interrupts GPT 11 5 MCCI 10 3 QSM 9 3 SIM 5 58 Inter transfer delay 9 6 INTV D 40 D 56 lout 8 19 IP 4 4 9 3 D 3 IPA D 68 IPIPEO 4 43 IPIPE1 4 43 IPIPE1 0 5 53 IPL D 21 5 58 5 60 Isp 6 3 IX 4 3 4 3 IZ 4 3 Junction leakage 8 23 M68HC16 Z SERIES USER S MANUAL For More Information On This Product lis Leakage error 8 23 Length of delay after transfer DTL D 49 Level sensitivity 5 58 LJSRR D 36 LJURR D 37 LOC D 8 LOCK 7 3 D 26 Lock registers LOCK D 26 Logic analyzer pod connectors C 2 levels definition 2 6 Loop mode LOOPS D 41 D 61 LOOPQ D 50 LOOPS D 41 D 61 Loss of clock reset LOC D 8 Low power broadcast cycle 5 42 CPU space cycle 5 42 interrupt mask level 5 42 operation SIM 5 29 stop mode enable STOP ADC 8 3 D 30 GPT 11 3 D 68 MCCI 10 2 D 55 MRM 7 3 D 25 QSM 9 2 D 39 SRAM 6 2 D 23 LPSTOP 5 21 5 29 LSB 2 6 LSBF 10 11 LSW 2 6 M 9 25 10 18 D 42 D 61 M68HC11 instructions compared to CPU16 instructions 4 31 M68HC16Z1EVB evaluation board E 1 M68MEVB1632 modular evaluation board MEVB C 2 M68MMDS1632 modular development system MMDS C 1 MAC 4 5 4 9 4 45 Masked ROM module MRM See MRM 7 1 Master slave mode select MSTR D 46 Maximum ratings electricals A 1 MCCI address map D 54 address map information 10 2 block diagram 10 1 features 3 2 general 10 1 general purpose 10 4 initialization 10 23 interrupts 10 3 pin function D 58 referen
193. 0 Zero or Minus TSTB Test B for 2 A 0 0 Zero or Minus TSTD Test D for 2 SS Se A A 00 Zero or Minus TSTE Test E for 2 0 0 Zero or Minus TSTW Test for M M 1 0000 IND16 X 6 7 0 0 Zero or Minus Word IND16 Y 6 IND16 Z 6 6 TSX Transfer SP to X SK SP 0002 XK IX 2 TSY Transfer SP to Y SK SP 0002 2 YK IY 2 TSZ Transfer SPtoZ SP 0002 2 ZK IZ j eme TXKB Transfer XK to B B 3 0 2 0 B 7 4 TXS Transfer X to SP XK IX 0002 2 SK SP 2 TXY Transfer X to Y XK IX 2 YK IY 2 TXZ Transfer X to Z XK IX gt ZK IZ 2 TYKB Transfer YK to B gt B 3 0 2 0 B 7 4 TYS Transfer Y to SP YK 0002 2 SK SP 2 TYX Transfer Y to X 2 XK IX 2 TYZ Transfer Y to Z IY gt ZK IZ 2 TZKB Transfer ZK to B ZK gt B 3 0 2 0 2 B 7 4 TZS Transfer Zto ZK IZ 0002 2 SK SP 376E TZX Transfer Z to X ZK IZ 2 XK IX NH 274E za TZY Transfer Z to Y ZK IZ 2 IY 275E 2 WAI Wait for Interrupt WAIT NH 27F3 8 XGAB Exchange A with B B NH 371A m 2 XGDE Exchange D with E D amp E NH 277A m 2 XGDX Exchange D with IX D lt gt IX NH 37CC 2 CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 28 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary
194. 0 wraparound mode 9 21 operation 9 8 peripheral chip selects 9 21 pins 9 8 RAM 9 7 receive RAM 9 7 transmit RAM 9 7 registers 9 6 control registers 9 6 status register 9 7 timing A 46 M68HC16 Z SERIES USER S MANUAL master CPHA 0 CPHA 1 A 47 slave CPHA 0 CPHA 1 A 48 low voltage A 45 QTEST 9 2 D 39 Queue pointers completed queue pointer CPTQP 9 8 end queue pointer ENDQP 9 8 new queue pointer NEWQP 9 8 Queued serial module QSM See QSM 9 1 peripheral interface QSPI See QSPI 9 1 9 5 5 32 field 5 66 D 19 RAF D 43 D 63 RAM array space RASP D 23 base address lock RLCK bit D 23 RAMBAH BAL 6 1 D 24 RAMMCR 6 1 D 23 RAMTST 6 1 D 24 RASP 6 2 D 23 encoding 6 2 D 23 RC DAC array 8 5 low pass filter 8 16 RDR 9 24 RDRF 9 28 10 21 D 43 D 63 RE 9 28 10 4 10 13 10 20 D 42 D 62 Read write signal R W 5 32 cycle 5 37 timing diagram A 29 Receive data RXD pin QSM 9 25 RXDA B pins MCCI 10 17 register full RDRF D 43 D 63 RAM 9 7 time sample clock RT 9 26 9 28 10 18 10 21 Receiver active RAF D 43 D 63 data register RDRF flag 9 28 10 21 enable RE 9 28 10 4 10 13 10 20 D 42 D 62 interrupt enable RIE D 42 D 61 wakeup RWU 9 30 10 22 D 42 D 62 Register bit and field mnemonics 2 3 Relative addressing modes 4 10 RES10 8 7 D 31 RESET 5 48 5 50 5 54 5 55 Reset and mode select timing A 36 exception processing 5 48 module pin funct
195. 000 ASM initialize reset vector INCLUDE ORG00008 ASM initialize exception vectors ORG 00200 Start program right after exception vectors KKKKK Initialize ckckck ck INCLUDE INITSYS ASM Pinitially set EK F XK 0 0 ZK 0 set sys clock at 16 78MHz disable COP INCLUDE INITRAM ASM turn on internal SRAM at 10000 set stack in bank 1 SK 1 SP 03FE LDAB 500 STAB PEPAR define the Port E pins as I O pins STAB PFPAR define the Port F pins as I O pins LDAB 500 STAB PORTEO clear the Port E data register STAB PORTFO clear the Port data register LDAB SFF STAB DDRE initialize Port E pins as outputs note that Port E pin 3 does not exist LDAB SFF M68HC16 Z SERIES USER S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product Go to www freescale com STAB DDRF LDAB 501 LDAA 500 START STAB PORTFO STAA PORTFO BRA START reescale Semiconductor Inc Port F pins 0 7 as outputs force 3 7 to 0 A store counter into Port E data register load A register with Port F data register go back and start the counting again at zero Exceptions Interrupts BDM BGND exception vectors point here and will put user into background mode E 2 1 2 Example 2 Using Chip Selects INCLUDI addresses INCLUDI INCLUDI Gl ORG Descr
196. 1 correspond to OC 5 1 0 If OC1 mask bit is set clear the corresponding output compare on OC1 match 1 If OC1 mask bit is set the set corresponding output compare pin on OC1 match D 8 6 Timer Counter Register TCNT Timer Counter Register YFF90A TCNT is the 16 bit free running counter associated with the input capture output com pare and pulse accumulator functions of the GPT module D 8 7 Pulse Accumulator Control Register Counter PACTL PACNT Pulse Accumulator Control Register Counter YFF90C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAIS PAEN PAMOD PEDGE PCLKS 14 05 PACLK 1 0 PULSE ACCUMULATOR COUNTER RESET U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PACTL enables the pulse accumulator and selects either event counting or gated mode In event counting mode PACNT is incremented each time an event occurs In gated mode it is incremented by an internal clock PAIS PAI Pin State Read Only PAEN Pulse Accumulator Enable 0 Pulse accumulator disabled 1 Pulse accumulator enabled PAMOD Pulse Accumulator Mode 0 External event counting 1 Gated time accumulation PEDGE Pulse Accumulator Edge Control The effects of PAMOD and PEDGE are shown in Table D 44 REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com D 70 Freescale Semiconductor Inc Table D 44 PAMOD and PEDGE Effects PAMOD PEDGE Effect 0 PAI falling
197. 10 11 ADDR17 vss 1 ADDR16 MC68HC16Z1 ADDR15 VDD 1 MC68CK16Z1 NC 11 68 1671 ADDR14 DATA8 01 MC68HC16Z2 ADDR13 DATA7L_ 1 MC68HC16Z3 ADDR12 DATA6 1 1 ADDR11 3 MMMMM s DATAS ADDR10 DATA4 11 ATWLYYWW ADDRO NC vss 1 VSS NC 133 NC DATA3L 1 ADDR8 DATA2 1 ADDR7 DATALL_ 1 ADDR6 DATAO L 1 ADDR5 ADDR4 FCO CSSiPCO 01 ADDR3 vss 1 VSS vD j VDD 1 1 i ADDR2 2 2 01 ADDR1 1 TXD PQS7 oog8danisnsSnS88 amp gNRARAHSRNRRREHRm RSRS WISER PT OR GSS SES 522955555002 0 2000052 5552555 PU BGS 11000 2400000 r4 nj n aaa FE 383 i 5 NOTES 1 MMMMM MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK HCIZUCKZUCNZIZ2I3 144 PIN QFP Figure 3 5 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments for 144 Pin Package OVERVIEW M68HC16 Z SERIES 3 8 For More information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SS PMC3 SCK PMC2 MOSI PMC1 MISO PMCO 2 1 ICYPGP2 OCYPGP3 OC2 OCYPGPA NC RXDA PMC6 TXDA PMC7 BRICSD ADDR1 115 L1 2 2 ADDR2 14 L1 FC1 CS4 PC1 VDD 113 L 1 VDD VSS 112L 1 vss ADDR3 1117711 FCO CSSIP CO ADDR4 110 1 ADDR5 109771 DATAO ADDR6 108 1 1 ADDR7 107 ADDR8 106 DATA3 VSS 105 1 vss ADDR9 104 DATA4 ADDR10 103L 1 DATAS um ADD
198. 1001 3125 34375 160 1 25 6875 176 1 375 001010 001011 21875 ERE 4375 112 1 75 192 1 5 001100 001101 40625 104 8125 1 625 4375 112 1 75 001110 001111 46875 120 9375 1 875 128 2 010000 010001 53125 136 1 0625 2 125 5625 144 1 125 2 25 010010 010011 59375 152 1 1875 2 375 160 1 25 2 5 010100 010101 65625 168 1 3125 2 625 6875 176 1 375 2 75 010110 010111 71875 184 1 4375 2 875 192 1 5 011000 100 011001 104 78125 1 5625 3 125 8125 1 625 416 3 25 011010 108 011011 112 84375 216 1 6875 3 375 1 75 3 5 011100 116 011101 120 90625 1 8125 3 625 1 875 3 75 9375 011110 124 011111 128 M68HC16 Z SERIES USER S MANUAL 512 4 196875 pete 1 9375 3 875 SYSTEM INTEGRATION MODULE For More Information On This Product 5 9 Go to www freescale com Freescale Semiconductor Inc Table 5 2 16 78 MHz Clock Control Multipliers Continued Shaded cells represent values that exceed 16 78 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fuco 2 x Value fyco Value fuco 2 x Value fuco Value Y Slow Fast Slow Fast 100000 132 1 03125 264 2 0625 528 4 125 100010 140 1 09375 280 2 1875 560 4 375 100100 148 1 15625 296 2 3125 592 4 675 100110 156 1 21875 312 2 4375 624 4 875 101000 164 1 28125 3 2 5625 656 5 125 688 704 720 736 752 3 768 784 800
199. 2 62 MHz Div 8 3 15 MHz 8 19 kHz 10 2kHz 12 3 kHz 64 0 Hz 80 0 Hz 96 Hz 100 Div 32 524 kHz Div 32 655 kHz Div 32 787 kHz 2 05 kHz 2 56 kHz 3 07 kHz 16 0 Hz 20 0 Hz 24 Hz Div 64 393 kHz 1 02 kHz 1 28 kHz 1 54 kHz 111 PCLK PCLK PCLK PCLK 256 PCLK 256 PCLK 256 PCLK PCLK PCLK 32768 32768 32768 11 11 2 PWM Function The pulse width values of the PWM outputs are determined by control registers PWMA and PWMB PWMA and PWMB are 8 bit registers implemented as two bytes of a 16 bit register PWMA and PWMB can be accessed as separate bytes or as one 16 bit register A value of 00 loaded into either register causes the corresponding output pin to output a continuous logic level zero signal A value of 80 causes the corresponding output signal to have a 5096 duty cycle and so on to the maximum value of FF which corresponds to an output which is at logic level one for 255 256 of the cycle Setting the F1A for PWMA or F1B for PWMB bits in the CFORC register causes the corresponding pin to output a continuous logic level one signal The logic level of the associated pin does not change until the end of the current cycle F1A and F1B are the lower two bits of CFORC but can be accessed at the same word address as PWMC GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Data written to PWMA
200. 2 EQU 714 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 2 RJURR3 EQU SF716 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 3 RJURRA EQU 718 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 4 RJURR5 EQU 5 71 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 5 RJURR6 EQU 5 71 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 6 RJURR7 EQU 71 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 7 LJSRRO EQU 5 720 LEFT JUSTIFIED SIGNED RESULT REGISTER 0 LJSRR1 EQU 5 722 LEFT JUSTIFIED SIGNED RESULT REGISTER 1 475 2 EQU F724 LEFT JUSTIFIED SIGNED RESULT REGISTER 2 LJSRR3 EQU 5 726 LEFT JUSTIFIED SIGNED RESULT REGISTER 3 LJSRRA EQU 5 728 bLEFT JUSTIFIED SIGNED RESULT REGISTER 4 LJSRR5 EQU 5 72 LEFT JUSTIFIED SIGNED RESULT REGISTER 5 LJSRR6 EQU 5 72 LEFT JUSTIFIED SIGNED RESULT REGISTER 6 LJSRR7 EQU SF72E LEFT JUSTIFIED SIGNED RESULT REGISTER 7 LJURRO EQU 5 730 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 0 LJURR1 EQU 5 732 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 1 LJURR2 EQU SF734 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 2 LJURR3 EQU 5 736 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 3 LJURRA EQU 5 738 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 4 LJURR5 EQU SF73A LEFT JUSTIFIED UNSIGNED RESULT REGISTER 5 LJURR6 EQU 5 73 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 6 LJURR7 EQU 5 7 LEFT JUSTIFIED UNSIGNED RESULT REGISTER 7 M68HC16 Z SERIES INITIALIZATION AND
201. 23 ECLK Table 5 23 shows pin assignment field encoding Pins that have no discrete output function must not use the 00 encoding as this will cause the alternate function to be selected For instance 00 for CSO BR will cause the pin to perform the BR function Table 5 23 Pin Assignment Field Encoding Discrete output Alternate function Chip select 8 bit port Chip select 16 bit port SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 64 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Port size determines the way in which bus transfers to an external address are allo cated Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip select Port size and transfer size affect how the chip select signal is asserted Refer to 5 9 1 3 Chip Select Option Registers for more information Out of reset chip select pin function is determined by the logic level on a correspond ing data bus pin The data bus pins have weak internal pull up drivers but can be held low by external devices Refer to 5 7 3 1 Data Bus Mode Selection for more informa tion Either 16 bit chip select function 11 or alternate function 01 can be select ed during reset All pins except the boot ROM select pin CSBOOT are disabled out of reset There are twelve chip select functions and only eight associated data bus pins There is not a one to one correspondence
202. 25 spurious interrupt monitor 5 25 system clock block diagram 5 4 protection 5 24 system clock 5 4 synthesizer operation 5 6 SIMCR 5 2 8 3 D 6 SIMTR D 7 SIMTRE D 9 Single channel conversions D 34 step mode 11 4 SIZ 5 54 SIZE 10 11 Size signals SIZ 5 32 5 35 5 47 SK 4 3 4 5 Slave select signal SS See SS 9 20 SLOCK D 8 Slow reference circuit 5 5 SM 4 4 D 3 Software watchdog 5 25 block diagram 5 27 clock rate 5 26 enable SWE 5 25 D 12 prescale SWP 5 26 D 12 ratio of SWP and SWT bits 5 26 reset SW D 8 timeout period calculation 5 26 D 12 timing field SWT 5 26 D 12 Source voltage level 8 22 SP 4 3 SPACE address space select 5 67 D 21 SPBR D 48 SPCR 10 6 D 64 SPCRO D 46 SPCR1 0 48 SPCR2 D 49 D 50 SPDR 10 6 D 66 SPE 9 6 D 48 SPI 10 1 block diagram 10 5 clock phase polarity controls 10 8 finished flag SPIF D 65 interrupt level ILSPI D 57 mode fault 10 12 operating modes master mode 10 7 slave mode 10 8 pins 10 6 registers control register SPCR 10 6 D 64 data register SPDR 10 6 D 66 status register SPSR 10 6 D 65 serial clock baud rate 10 11 timing A 50 master CPHA 0 CPHA 1 A 51 slave CPHA 0 CPHA 1 A 52 For More Information On This Product l 13 Go to www freescale com Freescale Semiconductor Inc low voltage A 49 transfer data flow 10 5 size and direction 10 11 write collision 10 12 SPI finished interr
203. 25 17 2 Characteristics A 16 A 15 Low Voltage 16 78 MHz Timing A 19 AUS 16 78 MHz AC Timing 21 23 A 148 25 17 MHz AC Timing uere beret tinea daa rage A 25 A 19 Low Voltage 16 78 MHz Background Debug Mode Timing A 37 A 20 16 78 Background Debug Mode Timing A 37 21 20 97 2 Background Debug Mode A 38 A 22 25 17 2 Background Debug Mode Timing A 38 A23 Voltage ECLK Bus TIMING etree cee eeu ipe dnas A 40 A24 B s TIMING A 41 A 25 20 97 Bus Timing 42 A 26 25 1 7 MAZ ECL Bus Timing adorti ice iiie A 43 A27 A 45 ac MEN MUI A 46 CT MESS SOS NILUM A 49 c M I RR A 50 A 31 General Purpose Timer AC Characteristics A 53 Ax ADGO Maximum A 62 A 33 Low Voltage ADC DC Electrical Characteristics Operating A 63 A 34 Low Voltage ADC AC Characteristics A 63 A 35 5V DC Electrical Characteristics
204. 25 2 625 6875 176 1 375 2 75 010110 010111 71875 184 1 4375 2 875 192 1 5 011000 100 011001 104 78125 1 5625 3 125 8125 1 625 416 3 25 011010 108 011011 112 84375 216 1 6875 3 375 1 75 3 5 011100 116 011101 120 90625 1 8125 3 625 1 875 3 75 9375 011110 124 011111 128 M68HC16 Z SERIES USER S MANUAL 512 4 196875 pete 1 9375 3 875 SYSTEM INTEGRATION MODULE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 4 25 17 MHz Clock Control Multipliers Continued Shaded cells represent values that exceed 25 17 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fuco 2 x Value fyco Value fuco 2 x Value fuco Value Y Slow Fast Slow Fast 100000 132 1 03125 264 2 0625 528 4 125 100010 140 1 09375 280 2 1875 560 4 375 100100 148 1 15625 296 2 3125 592 4 675 100110 156 1 21875 312 2 4375 624 4 875 101000 164 1 28125 3 2 5625 656 5 125 688 704 720 736 752 3 768 784 800 101010 172 1 34375 3 2 6875 5 375 101011 176 1 375 3 2 75 5 5 101100 180 1 40625 3 2 8125 5 625 101101 184 1 4375 3 2 875 5 75 8 6 4 2 0 8 101110 188 1 46875 376 2 9375 5 875 110000 196 1 53125 392 3 0625 6 125 408 4 2 6 4 2 8 6 4 32 110100 212 1 65625 4 3 3125 848 6 625 110110 220 1 71875 4 3 4375 880 6 875 111000 2
205. 26 5 10 Software Watchdog Divide 5 27 5 11 M ODCLK Pin and F IF Bit at nates 5 28 512 du div dui m 5 29 EE og a E ER 5 32 5 14 Address Space 5 32 Signals iced ios ane 5 34 5 16 5 36 5 17 DSACK BERR HALT Assertion Results 5 44 S16 Source uni 5 49 5 19 Reset Mode 5 49 520 Mod le Fin MID 5 53 5 21 5 54 522 cece cena lu ald 5 64 5 23 Pin Assignment Field 5 64 a ee eee 5 65 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Table 5 25 5 26 8 10 8 11 9 1 8 2 9 3 9 5 10 1 10 2 10 3 10 4 10 5 10 6 10 7 1 2 Freescale Semiconductor Inc LIST OF TABLES Continued Title Page Chip Select Base and Option Register Reset Values 5 69 CSBOOT Base and Option Register Reset 5 70 SRAM Bang vp Mee acura 6 1 SRAM Array Address Space Type ce eiae cse rena damn netto 6 2 ROM Array Space Field Lose ertet oii DERE FERREA
206. 28 1 78125 4 3 5625 912 7 125 111010 236 1 84375 4 3 6875 944 7 375 44 4 976 52 6 0 0 8 0 111100 2 1 90625 3 8125 7 625 111110 2 1 96875 5 3 9375 1008 7 875 2 3 4 5 6 6 7 8 9 0 110010 204 1 59375 0 3 1875 816 6 375 208 1 625 3 25 8 6 5 2 3 4 4 5 6 7 8 8 9 0 SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 5 16 78 MHz System Clock Frequencies Shaded cells represent values that exceed 16 78 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2x Value fyco Value fyco 2 x Value Value 000000 131 kHz 262 kHz 524 kHz 1049 kHz 000001 524 1049 2097 000011 1049 2097 4194 000101 786 1573 3146 6291 000111 1049 2097 4194 8389 001001 1311 2621 5243 10486 001011 1573 3146 6291 12583 001101 1835 3670 7340 14680 001111 2097 4194 8389 16777 010001 2359 4719 9437 18874 Y 010101 2884 5767 11534 23069 010111 3146 6291 12583 25166 011001 3408 6816 13631 27263 011011 3670 7340 14680 29360 011101 3932 7864 15729 31457 011111 4194 8389 16777 33554 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product Go to www freescale com 5 16 Freesc
207. 3 13 function 3 15 MDDR 10 2 10 4 For More Information On This Product Mechanical data and ordering information B 1 Memory maps combined program and data MC68HC16Z1 CKZ1 CMZ1 3 20 MC68HC162Z2 Z3 3 21 MC68HC16Z4 CKZA 3 22 internal register map 3 16 separate program and data MC68HC162Z1 CKZ1 CMZ1 3 23 68 1672 23 3 24 MC68HC16Z4 CKZA 3 25 Microcontroller Development Tools Directory MCUDE VTLDIR D Rev 3 C 1 Microsequencer 4 35 Misaligned operand 5 35 MISO 9 16 9 20 MIVR 10 2 D 56 MM 6 1 7 1 D 7 MMCR 10 2 D 54 MMDS C 1 Mnemonics range definition 2 6 specific definition 2 6 MODCLK 5 5 5 6 5 56 MODE 5 66 D 19 Mode fault flag MODF 9 9 10 12 D 51 D 66 select M D 42 D 61 MODF 9 9 D 51 D 66 Modular platform board C 2 Module mapping MM bit 5 2 6 1 7 1 11 2 D 1 D 7 pin functions 5 53 Modulus counter 9 26 10 18 Monotonicity 8 1 MOSI 9 16 9 20 MPAR 10 2 10 4 D 57 MPB C 2 MRM 7 1 address map D 25 array address mapping 7 1 features 3 2 normal access 7 2 registers module configuration register MRMCR 7 1 D 25 ROM array base address registers BAH BAL 7 1 D 27 bootstrap words ROMBS 7 1 D 28 signature registers RSIGHI LO 7 1 D 27 reset 7 3 ROM signature 7 3 MRMCR 7 1 D 25 MSB 2 6 MSTR 10 7 10 8 D 46 MSTRST master reset 5 48 5 55 5 56 5 57 MSW 2 6 MTEST 10 2 D 55 MULT D 32 ROM M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semicon
208. 3 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR Se Bele Blane a Ch in 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 060000 BANK 6 002C 16 LEVEL 6 INTE AUTOVECTOR 060000 PROGRAM 002 17 LEVEL7INTE AUTOVECTOR SPACE 0030 18 SPURIO ERRUPT 5070000 7 4 77 WITGIFE 38 87 USER DEFINED INTERRUPTS 5070000 07FFFF 07FFFF 5080000 UNDEFINED UNDEFINED 080000 UNDEFINED UNDEFINED Y FF 700 F7FFFF ADC SETFFFF F80000 Banks 7 F80000 F90000 F90000 FA0000 f Ankio YFF900 5 0000 piace Sete Y FF 93F FB0000 eank 11 F B0000 512 KBYTE Y FFA00 SINE 0000 FD0000 YFFBOO SRA FD0000 YFFBO7 CONTROL FE0000 Jeankig 777777 5 0000 YFFCOO MCCI 5 0000 Jeankis YFFC3F FF0000 sv FEDFF Y FFFFFF FFFFFF NOTE 1 THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24 BIT IMB ADDRESSES THE CPU16 ADDRESS BUS IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FROM 080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16 S FLAT 20 BIT ADDRESS SPACE THE CPU16 NEED ONLY GENERATE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE HCIGZAICKZA MEM MAP 5 Figure 3 16 MC68HC16Z4 CKZ4 Separate Program and Data Space M68HC16 Z SERIES USER S MANUAL OVERVIEW For More Information On This P
209. 33 4 10 acceda ines RE m 4 34 4 10 1 Microsequencer 4424 4 004 0 000 4 35 4 10 2 m 4 35 4 10 3 Executori 4 35 4 11 Execimon Dn 4 36 4 11 1 Changes in Programi FION 4 36 4 12 renee 4 36 4 13 E Dr RE aid 4 37 4 13 1 Exception Vectors F v 4 37 4 13 2 Exception Stak acs eaten tices a 4 38 4 13 3 Exception Processing 4 39 4 13 4 Types of p pp DR REX EA 4 39 4 13 4 1 Asynchronous 4 39 4 13 4 2 Synchronous 4 39 4 13 5 4 40 4 13 6 4 40 4 14 Development Support ded aded ea Un eH e EHI HE HG Rt a ads 4 40 4 14 1 Deterministic Opcode 4 40 4 14 1 1 IPIPEO IPIPE1 Multiplexing 4 41 4 14 1 2 Combining Opcode Tracking with Other Capabilities 4 41 4 14 2 4 41 4 14 3 Opcode Tracking and Breakpolnis 4 42 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com TABLE CONTENTS Co
210. 5 13 shows SIZO and SIZ1 encoding Table 5 13 Size Signal Encoding 0 0 Long Word 5 5 1 7 Function Codes The CPU generates function code signals FC 2 0 to indicate the type of activity oc curring on the data or address bus These signals can be considered address exten sions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle Because the CPU16 always operates in supervisor mode FC2 1 address spaces 0 to 3 are not used Address space 7 is designated CPU space CPU space is used for control information not normally associated with read or write bus cycles Function codes are valid while AS is asserted Table 5 14 shows address space encoding Table 5 14 Address Space Encoding FC2 FC1 FCO Address Space 1 0 0 Reserved 1 0 1 Data space 1 1 0 Program space 1 1 1 CPU space 5 5 1 8 Data Size Acknowledge Signals During normal bus transfers external devices assert the data size acknowledge sig nals DSACK 1 0 to indicate port width to the MCU During a read cycle these sig nals tell the MCU to terminate the bus cycle and to latch data During a write cycle the signals indicate that an external device has successfully stored data and that the cycle can terminate DSACK 1 0 can also be supplied internally by chip select logic Refer to 5 9 Chip Selects for more information SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 32 For
211. 5 2 bus operation 5 36 chip selects 5 61 external bus interface 5 29 features 3 1 functional blocks 5 1 halt monitor 5 25 interrupt arbitration 5 3 interrupts 5 58 parallel I O ports 5 70 periodic interrupt timer 5 27 reference manual 5 67 register access 5 3 registers chip select base address register boot CSBARBT D 17 registers CSBAR 5 64 5 65 D 17 option register boot CSORBT D 18 registers CSOR 5 64 5 66 D 18 pin assignment registers CSPAR 5 64 D 15 clock synthesizer control register SYNCR D 7 master shift registers A B TSTMSRA TSTM SRB D 22 module configuration register SIMCR 5 2 D 6 periodic interrupt control register PICR D 13 timer register PITR 5 28 D 14 port C data register PORTC 5 67 D 15 port E data direction register DDRE 5 70 D 9 data register PORTE 5 71 D 9 pin assignment register PEPAR 5 70 D 10 port F data direction register DDRF 5 70 D 11 data register PORTF 5 71 data registers PORTF D 10 pin assignment register PFPAR 5 70 D 11 reset status register RSR D 8 software service register SWSR D 15 system protection control register SYPCR D 12 test register SIMTR D 7 E SIMTRE D 9 test module control register CREG D 22 distributed register DREG D 22 repetition count register TSTRC D 22 shift count register TSTSC D 22 reset 5 48 state of pins 5 54 software watchdog 5 25 M68HC16 Z SERIES USER S MANUAL block diagram with PIT 5
212. 5 BSC 0 013 REF S 1 080 BSC 51 0 540 BSC 0 025 REF V 1 080 BSC Vi 0 540 BSC w 0 006 0 008 oe 8 Figure B 3 Case 831A 01 132 Pin Package Dimensions MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z SERIES B 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NmsnonM i MERN Z S E EEEE Eedi HE 54 m dE TET UE TE BESESSATSRRARRAFHATRBRERHSHARRLRRELKRR VRHP R5ppES 11 ANS PADAS AN4 PADA4 metre AN3 PADA3 AN2 PADA2 DSACROPEO 11 1 ADDRO 11 ANO PADAO 15 11 VSSA DATA 11 VDDA DATA13 11 VSS DATA22 11 VDD 1 ADDR18 10 11 ADDR17 vss 1 ADDR16 MC68HC16Z1 ADDR15 VDD 1 MC68CK16Z1 NC 11 68 1671 ADDR14 DATA8 01 MC68HC16Z2 ADDR13 DATA7L_ 1 MC68HC16Z3 ADDR12 DATA6 1 1 ADDR11 3 MMMMM s DATAS ADDR10 DATA4 11 ATWLYYWW ADDRO NC vss 1 VSS NC 133 NC DATA3L 1 ADDR8 DATA2 1 ADDR7 DATALL_ 1 ADDR6 DATAO L 1 ADDR5 ADDR4 FCO CSSiPCO 01 ADDR3 vss 1 VSS vD j VDD 1 1 i ADDR2 2 2 01 ADDR1 1 TXD PQS7 oog8danisnsSnS88 amp gNRARAHSRNRRREHRm RSRS WISER PT OR GSS SES 522955555002 0 2000052 5552555 PU BGS 11000 2400000
213. 51 6 2 NORMAL DSACK 2 Normal cycle terminate and continue BERR 3 NA UADT NA HALT NA x5 HALT DSACK A RA Normal cycle terminate and halt BERR NA NA Continue when HALT is negated HALT A RA RA BUS ERROR DSACK NA A X Terminate and take bus error exception 1 BERR A RA HALT NA X BUS ERROR DSACK A X Terminate and take bus error exception 2 BERR A RA HALT NA NA BUS ERROR DSACK NA A X Terminate and take bus error exception 3 BERR A RA HALT A S RA BUS ERROR DSACK A X Terminate and take bus error exception 4 BERR NA A HALT NA A NOTES 1 S2 The number of current even bus state for example S2 S4 etc 2 A Signal is asserted in this bus state 3 NA Signal is not asserted in this state 4 RA Signal was asserted in previous state and remains asserted in this state 5 X Don t care 5 6 5 1 Bus Errors The CPU16 treats bus errors as a type of exception Bus error exception processing begins when the CPU16 detects assertion of the IMB BERR signal BERR assertions do not force immediate exception processing The signal is synchro nized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle in which it was asserted Because bus cycles can overlap instruction boundaries bus error exception processing may not occur at the end of the instruction in which the bus cycle begins Timing of BERR detection acknowledge is dependent upon several factors Which bus cycle of an i
214. 6 Y IND16 Z EXT 2 IND8 IND8 IND8 Z 16 IND16 IND16 IND16 2 E Y E Z IMM16 IND16 X IND16 Y IND16 Z EXT IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT Y 2 CENTRAL PROCESSING UNIT For More Information On This Product Go to www freescale com A A A A A A A A A A A A A A A A A A M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV N Z V C ADDB Add to B IND8 X 6 IND8 Y 6 IND8 2 6 IMM8 2 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 6 6 E Z 6 ADDD Add to D IND8 X 6 Sea A IND8 Y 6 IND8 Z 6 IMM8 2 IMM16 4 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 6 6 E Z 6 ADDE Add to E IMM8 2 A IMM16 4 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 ADE Add D to E D gt INH 2 ADX Add D to IX IX 20 D gt INH 2 XK IX ADY POS D ta Ey YK 20 0 2 YK 1Y ADE Ada Dilog ZK IZ 20
215. 89 001001 1311 2621 5243 10486 001011 1573 3146 6291 12583 001101 1835 3670 7340 14680 001111 2097 4194 8389 16777 010001 2359 4719 9437 18874 Y 010101 2884 5767 11534 23069 010111 3146 6291 12583 25166 011001 3408 6816 13631 27263 011011 3670 7340 14680 29360 011101 3932 7864 15729 31457 011111 4194 8389 16777 33554 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product Go to www freescale com 5 18 Freescale Semiconductor Inc Table 5 6 System Clock Frequencies for a 20 97 MHz System Continued Shaded cells represent values that exceed 20 97 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2 x Value Value fyco 2 x Value fyco Value 100000 4325 kHz 8651 kHz 17302 kHz 34603 kHz 100001 4456 8913 17826 35652 100011 4719 9437 18874 37749 100101 4981 9961 19923 39846 100111 5243 10486 20972 41943 101001 5505 11010 22020 44040 101011 5767 11534 23069 46137 101101 6029 12059 24117 48234 101111 6291 12583 25166 50332 110001 6554 13107 26214 52428 Y 110101 7078 14156 28312 56623 110111 7340 14680 29360 58720 111001 7602 15204 30409 60817 111011 7864 15729 31457 62915 111101 8126 16253 32506 65011 110011 6816 13631 27263 54526 110100 6947 13894 27787
216. 9 If the asynchronous setup time specification 47A requirements are satisfied the DSACK 1 0 low to data setup time specification 31 and DSACK 1 0 low to BERR low setup time specification 48 can be ignored The data must only satisfy the data in to clock low setup time specification 27 for the following clock cycle must satisfy only the late low to clock low setup time specification 27A for the following clock cycle 10 To ensure coherency during every operand transfer BG is not asserted in response to BR until after all cycles of the current operand transfer are complete 11 In the absence of DSACK 1 0 BERR is an asynchronous input using the asynchronous setup time specifi cation 47 12 After external RESET negation is detected a short transition period approximately 2 elapses then the SIM drives RESET low for 512 13 External logic must pull RESET high during this period in order for normal MCU operation to begin 14 Eight pipeline states are multiplexed into IPIPE 1 0 The multiplexed signals have two phases M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product Go to www freescale com A 27 Freescale Semiconductor Inc CLKOUT 16 CLKOUT TIM Figure A 1 CLKOUT Output Timing Diagram EXTAL NOTE TIMING SHOWN WITH RESPECT TO Vip LEVELS PULSE WIDTH SHOWN WITH RESPECT TO 50 Vpp 16 E
217. 9 Chip Selects for more information Bus control signal timing as well as chip select signal timing are specified in APPENDIX A ELECTRI CAL CHARACTERISTICS Refer to the S M Reference Manual SIMRM AD for more information about each type of bus cycle 5 6 1 Synchronization to CLKOUT External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints Although bus cycles are classified as asynchronous they are interpreted relative to the MCU system clock output CLKOUT SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 9 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Descriptions are made in terms of individual system clock states labelled 50 51 S2 SN The designation state refers to the logic level of the clock signal and does not correspond to any implemented machine state A clock cycle consists of two successive states Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information on clock control timing Bus cycles terminated by DSACK assertion normally require a minimum of three CLKOUT cycles To support systems that use CLKOUT to generate DSACK and other inputs asynchronous input setup time and asynchronous input hold times are speci fied When these specifications are met the MCU is guaranteed to recognize the ap propriat
218. A 16 16 0 RCV DATA LATCH COMMAND LATCH 051 SERIAL IN PARALLEL IN PARALLEL OUT SERIAL OUT 050 PARALLEL IN SERIAL IN SERIAL OUT PARALLEL OUT 1 UNIT 16 SYNCHRONIZE MICROSEQUENCER STATUS DATA CONTROL PN CONTROL SERIAL LOGIC LOGIC CLOCK BDM SER COM BLOCK Figure 4 7 BDM Serial Block Diagram The development system serves as the master of the serial link and is responsible for the generation of the serial interface clock signal DSCLK Serial clock frequency range is from DC to one half the CPU16 clock frequency If is derived from the CPU16 system clock development system serial logic can be synchronized with the target processor The serial interface operates in full duplex mode Data transfers occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK Data is trans mitted MSB first and is latched on the rising edge of DSCLK The serial data word is 17 bits wide which includes 16 data bits and a status control bit Bit 16 indicates status of CPU generated messages Command and data transfers initiated by the development system must clear bit 16 All commands that return a result return 16 bits of data plus one status bit CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 44 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 15 Recommended BDM Connection In o
219. A ELECTRICAL CHARACTERISTICS for standby switching and power con sumption specifications 6 6 Reset Reset places the SRAM in low power stop mode enables program space access and clears the base address registers and the register lock bit These actions make it pos sible to write a new base address into the ROMBAH and ROMBAL registers When a synchronous reset occurs while a byte or word SRAM access is in progress the access is completed If reset occurs during the first word access of a long word operation only the first word access is completed If reset occurs during the second word access of a long word operation the entire access is completed Data being read from or written to the RAM may be corrupted by an asynchronous reset For more in formation refer to 5 7 Reset M68HC16 Z SERIES STANDBY RAM MODULE USER S MANUAL For More Information On This Product 6 3 Go to www freescale com 6 4 Freescale Semiconductor Inc STANDBY RAM MODULE For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc SECTION 7 MASKED ROM MODULE The masked ROM module MRM is only available with the MC68HC16Z2 and the MC68HC16Z3 The MRM consists of a fixed location control register block and an 8 Kbyte mask programmed read only memory array that can be mapped to any 8 Kbyte boundary in the system memory map The MRM can be programmed to insert wait states to match s
220. ACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX 38 32 768 2 CRYSTAL SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT 32 OSCILLATOR Figure 5 3 Slow Reference Crystal Circuit A 4 194 MHz crystal is typically used for a fast reference but the frequency may vary between one MHz up to six MHz Figure 5 4 shows a typical circuit R1 ee XTAL R2 Mo 1 i EXTAL C2 27 PF 7 Vssi RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH KDS041 18 4 194 MHz CRYSTAL SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT 16 OSCILLATOR 4M Figure 5 4 Fast Reference Crystal Circuit M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 5 to www freescale com Freescale Semiconductor Inc If a fast or slow reference frequency is provided to the PLL from a source other than a crystal or an external system clock signal is applied through the EXTAL pin the XTAL pin must be left floating 5 3 2 Clock Synthesizer Operation 5 6 Vppsvw is used to power the clock circuits when the system clock is synthesized from either a crystal or an externally supplied reference frequency A separate power source increases MCU noise immunity and can be used to run the clock when the MCU is powered down A quiet power supply must be used as the Vppsyw source Ad
221. ADDR ADDR ADDR ADDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESET 0 0 0 0 0 0 RAMBAL Array Base Address Register Low 2K SRAM 22 YFFBO6G 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 RAMBAL Array Base Address Register Low 4K SRAM Z3 6 15 14 13 12 1 10 9 8 T 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 15 14 13 12 10 9 8 1 6 5 4 3 2 1 0 RESET 0 0 0 0 RAMBAH and RAMBAL specify the SRAM array base address in the system memory map They can only be written while the SRAM is in low power stop mode STOP 1 the default out of reset and the base address lock is disabled RLCK 0 the default out of reset This prevents accidental remapping of the array Because the CPU16 drives ADDR 23 20 to the same logic level as ADDR19 the values of RAMBAH ADDR 23 20 must match the value of ADDR19 for the array to be accessible These registers may be read at any time RAMBAH 15 8 are unimplemented and will always read zero REGISTER SUMMARY M68HC16 Z SERIES D 24 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 4 Masked ROM Module The is used only the MC68HC16Z2 and the MC68HC 1623 Ta
222. ADDRESS BUS IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FROM 080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMORY BANKS 15 APPEAR FULLY CONTIGUOUS IN THE CPU16 S FLAT 20 BIT ADDRESS SPACE THE CPU16 NEED ONLY GENERATE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE Figure 3 15 MC68HC16Z2 Z3 Separate Program and Data Space OVERVIEW M68HC16 Z SERIES 3 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR 0 ADDRESS NUMBER EXCEPTION 5000000 SANKO 0000 RESET INITIAL ZK SK AND PK BANKO 3000000 9000008 0002 1 RESET INITIAL EXCEPTION VECTORS 000008 0004 2 RESET INITIAL SP 010000 7777 0006 3 RESET INITIAL IZ DIRECT PAGE 010000 020000 7 7770777 VECTOR VECTOR YPEO 020000 ADDRESS NUMBER EXCEPTION 0008 4 BKPT BREAKPOINT PEEN PEE 000A 5 BERR BUS ERROR 5030000 SWI SOFTWARE INTERRUPT 030000 512 KBYTE 000 7 ILLEGAL INSTRUCTION 0010 DIVISION BY ZERO UNASSIGNED RESERVED 5040000 0020 10 UNASSIG RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 050000 7777777 050000 0026 1
223. AL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 5 MCCI Initialization After reset the MCCI remains in an idle state Several registers must be initialized be fore serial operations begin A general sequence guide for initialization follows A Global 1 Configure MMCR a Write an interrupt arbitration number greater than zero into the IARB field b Clear the STOP bit if it is not already cleared 2 Interrupt vector and interrupt level registers MIVR ILSPI and ILSCI a Write the SPI SCI interrupt vector into MIVR b Write the SPI interrupt request level into the ILSPI and the interrupt re quest levels for the two SCI interfaces into the ILSCI 3 Port data register a Write a data word to PORTMC b Read a port pin state from PORTMCP 4 Pin control registers a Establish the direction of MCCI pins by writing to the MDDR b Assign pin functions by writing to the MPAR B Serial Peripheral Interface 1 Configure SPCR a Write a transfer rate value into the BAUD field b Determine clock phase CPHA and clock polarity CPOL c Specify an 8 or 16 bit transfer SIZE and MSB or LSB first transfer mode LSBF d Select master or slave operating mode MSTR e Enable or disable wired OR operation WOMP Enable or disable SPI interrupts SPIE g Enable the SPI by setting the SPE bit C Serial Communication Interface SCIA SCIB 1 Totransmit read the SCSR
224. AL For More Information On This Product 10 5 Go to www freescale com Freescale Semiconductor Inc Error detection logic is included to support interprocessor interfacing A write collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress A multiple master mode fault detector automatically dis ables SPI output drivers if more than one MCU simultaneously attempts to become bus master 10 3 1 SPI Registers SPI control registers include the SPI control register SPCR the SPI status register SPSR and the SPI data register SPDR Refer to D 7 13 SPI Control Register D 7 14 SPI Status Register and D 7 15 SPI Data Register for register bit and field definitions 10 3 1 1 SPI Control Register SPCR The SPCR contains parameters for configuring the SPI The register can be read or written at any time 10 3 1 2 SPI Status Register SPSR The SPSR contains SPI status information Only the SPI can set the bits in this regis ter The CPU reads the register to obtain status information 10 3 1 3 SPI Data Register SPDR The SPDR is used to transmit and receive data on the serial bus A write to this register in the master device initiates transmission or reception of another byte or word After a byte or word of data is transmitted the SPIF status bit is set in both the master and slave devices A read of the SPDR actually reads a buffer If the first SPIF is n
225. AM byte inserts either a standard DSCK 0 or user specified DSCK 1 delay from chip select assertion until the leading edge of the serial clock The DSCKL field in SPCR1 determines the length of the user defined delay before the assertion of SCK The following expression determines the actual de lay before SCK PCS to SCK Delay DSCKLS 0 Sys where DSCKL 6 0 equals 1 2 3 127 When DSCK equals zero DSCKL 6 0 is not used Instead the PCS valid to SCK transition is one half the SCK period There are two transfer length options The user can choose a default value of eight bits or a programmed value from eight to sixteen bits inclusive The programmed val ue must be written into BITS 3 0 in SPCRO The BITSE bit in each command RAM byte determines whether the default value BITSE 0 or the BITS 3 0 value BITSE 1 is used Table 9 3 shows BITS 3 0 encoding M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 17 Go to www freescale com 9 18 For More Information On This Product Freescale Semiconductor Inc Table 9 3 Bits Per Transfer BITS 3 0 Bits Per Transfer 0000 16 0001 0070 Reserved Reserved Reserved Reserved or m 8 HW r p c der o ta 1111 9 10 11 12 13 14 15 Delay after transfer can be used to provide a peripheral deselect interval A delay can also be inserted between consecutive tr
226. ATA4 ADDR10 103L 1 DATAS ADDR11 MC68HC16Z4 102 1 DATAG NCBBCKIEZ4 TE ADDR 14 99 DATA9 1 ATWLYYWW ADDR15 98 11 VDD ADDR16 97 L1 vss ADDR17 96 DATA10 ADDR18 95 DATA11 VDD 94 _ DATA12 VSS 93 DATA13 VDDA VSSA 91 _ DATA15 ANO PADAO ADDRO 1 89 DSACRO PEO AN2 PADA2 88 1 DSACRIPE1 AN3 PADA3 87 AVET PE2 AN4 PADA4 86 1 DS PE4 ANS PADAS 85 AS PES VRH 84771 VDD nand5nsanedemnmeoecgo do cBOdReERHRRORPRERPRPOSSSS a mox 2 U 9 04 TM NA OWEN OH gE 3g PIT 5 2 n EE 5 NOTES 1 MMMMM MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK MENU Figure 2 MC68HC16Z4 CKZ4 Pin Assignments for 132 Package M68HC16 ZSERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL B 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc AAA A z VIEW BASE METAL D lt 02 1 PLATING SECTION id zt m 0 lt 0 MENSIONING AND TOLERANCING PER ASME 4 5M 1982 MENSIONS IN INCHES MENSIONS A B J AND P DO NOT INCLUDE OLD PRO
227. ATION MODULE For More Information On This Product Go to www freescale com 5 53 Freescale Semiconductor Inc NOTE Pins that are not used should either be configured as outputs or if configured as inputs pulled to the appropriate inactive state This de creases additional Ipp caused by digital inputs floating near mid sup ply level 5 7 5 1 Reset States of SIM Pins Generally while RESET is asserted SIM pins either go to an inactive high impedance state or are driven to their inactive states After RESET is released mode selection occurs and reset exception processing begins Pins configured as inputs must be driven to the desired active state Pull up or pull down circuitry may be necessary Pins configured as outputs begin to function after RESET is released Table 5 21 is a sum mary of SIM pin states during reset Table 5 21 SIM Pin Reset States Pin State After RESET Released Pin State Pin s While RESET Default Function Alternate Function Asserted pin Function Pin State Pin Function Pin State CS10 ADDR23 ECLK C810 Vpp ADDR23 Unknown CS 9 6 ADDR 22 19 PC 6 3 CS 9 6 Vpp ADDR 22 19 Unknown ADDR 18 0 ADDR 18 0 Unknown ADDR 18 0 Unknown ASPES 2 Input BERR Input CS1 BG Vpp CS2 BGACK Input CSO BR Input CLKOUT CLKOUT CLKOUT Output CSBOOT CSBOOT CSBOOT Vss DATA 15 0 Mode select DATA 15 0 DATA 15 0 Input 5 4 High Input DSACKO PEO
228. C28 SCIB CONTROL REGISTER 0 SCCR1IB EQU FC2A SCIB CONTROL REGISTER 1 SCSRB EQU 5 2 SCIB STATUS REGISTER SCDRB EQU 5 2 SCIB DATA REGISTER SPCR EQU FC38 7SPI CONTROL REGISTER SPSR EQU SFC3C SPI STATUS REGISTER SPDR EQU 5 SPI DATA REGISTER GPT MODULE REGISTERS GPTMCR EQU 900 GPT MODULE CONFIGURATION REGISTER GPTMTR EQU 902 GPT MODULE TEST REGISTER RESERVED ICR EQU 904 GPT INTERRUPT CONFIGURATION REGISTER PDDR EQU SF906 PARALLEL DATA DIRECTION REGISTER GPTPDR EQU 5 907 PARALLEL DATA REGISTER EQU 908 OC1 ACTION MASK REGISTER OC1D EQU SF909 OC1 ACTION DATA REGISTER TCNT EQU SF90A TIMER COUNTER REGISTER INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 4 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PACTL EQU SF90C PULSE ACCUMULATOR CONTROL REGI
229. CL 100 pF Group 3 I O Pins 130 Group 4 I O Pins 200 NOTES 1 Applies to Port ADA 7 0 AN 7 0 Port E 7 4 SIZ 1 0 AS DS Port F 7 0 IRQ 7 1 MODCLK Port GP 7 0 IC4 OC5 OCt1 IC 3 1 OC 4 1 OC1 Port QS 7 0 TXD PCS 3 1 50 55 SCK MOSI 5 BKPT DSCLK DSI IPIPE1 PAI PCLK RESET RXD TSC EXTAL when PLL enabled 2 This parameter is periodically sampled rather than 100 tested 3 Applies to all input only pins except ADC pins 4 Input Only Pins EXTAL TSC BKPT DSCLK PAI PCLK RXD Input Output CSBOOT BG CS1 CLKOUT FREEZE QUOT DSO IPIPEO PWMA PWMB Output Only Pins Group 1 Port GP 7 0 IC4 OC5 OC1 IC 3 1 OC 4 1 OC1 DATA 15 0 DSI IPIPE1 Group 2 Port C 6 0 ADDR 22 19 CS 9 6 FC 2 0 CS 5 3 Port E 7 0 SIZ 1 0 AS DS AVEC DSACK 1 0 Port F 7 0 IRQ 7 1 MODCLK Port QS 7 3 TXD PCS 3 1 50 55 ADDR23 CS10 ECLK ADDR 18 0 R W BERR 50 BGACK CS2 Group 3 HALT RESET Group 3 MISO MOSI SCK 5 Applies to all input output and output pins 6 Does not apply to HALT and RESET because they are open drain pins Does not apply to port QS 7 0 TXD PCS 3 1 50 55 SCK MOSI MISO in wired OR mode 7 Applies to Group 1 2 4 input output and all output pins 8 Applies to Group 1 2 3 4 input output pins BG CS CLKOUT CSBOOT FREEZE QUOT and IPIPEO 9 Applies to DATA 15 0 10 Use of an active pulldown device is recommended
230. COA QSM INTERRUPT LEVELS REGISTER 5 05 QSM INTERRUPT VECTOR REGISTER SFCO8 SCI CONTROL REGISTER 0 SFCOA SCI CONTROL REGISTER 1 SFCOC 7SCI STATUS REGISTER SFCOE SCI DATA REGISTER FULL WORD NOT LAST 8 BITS SFC15 5 PORT DATA REGISTER SFC16 7QOSM PIN ASSIGNMENT REGISTER SFC17 7QSM DATA DIRECTION REGISTER SFC18 QSPI CONTROL REGISTER 0 1 7QSPI CONTROL REGISTER 1 SFC1C QSPI CONTROL REGISTER 2 SFCIE QSPI CONTROL REGISTER 3 SFCIF QSPI STATUS REGISTER SFDOO SPI REC RAM 0 SFDO2 SPI REC RAM 1 5 04 SPI REC RAM 2 SFD06 SPI REC RAM 3 5 08 SPI REC RAM 4 SFDOA REC RAM 5 SFDOC 5 REC RAM 6 SFDOE SPI REC RAM 7 SFDOO SPI REC RAM 8 SFDO2 SPI REC RAM 9 5 04 7SPI A SFD06 SPI REC RAM B SFDO8 SPI REC RAM SFDOA SPI REC RAM D SFDOC SPI REC RAM E SFDOE SPI REC RAM SFD20 SSPI TXD RAM 0 SFD22 7 SPI TXD RAM 1 SFD24 5 TXD RAM 2 SFD26 SPI TXD RAM 3 SFD28 SPI TXD RAM 4 SFD2A SPI TXD RAM 5 SFD2C SPI TXD RAM 6 M68HC16 Z SERIES USER S MANUAL INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
231. CPU16 Reference Manual CPU16RM AD for detailed information 4 4 Data Types The CPU16 uses the following types of data Bits 4 bit signed integers 8 bit byte signed and unsigned integers 8 bit 2 digit binary coded decimal BCD numbers 16 bit word signed and unsigned integers 32 bit long word signed and unsigned integers 16 bit signed fractions 32 bit signed fractions 36 bit signed fixed point numbers 20 bit effective addresses There are eight bits in a byte and 16 bits in a word Bit set and clear instructions use both byte and word operands Bit test instructions use byte operands Negative integers are represented in two s complement form Four bit signed integers packed two to a byte are used only as X and Y offsets in MAC and RMAC operations 32 bit integers are used only by extended multiply and divide instructions and by the associated LDED and STED instructions BCD numbers are packed two digits per byte BCD operations use byte operands Signed 16 bit fractions are used by the fractional multiplication instructions and as multiplicand and multiplier operands in the MAC unit Bit 15 is the sign bit and there is an implied radix point between bits 15 and 14 There are 15 bits of magnitude The range of values is 1 8000 to 1 2715 7FFF Signed 32 bit fractions are used only by the fractional multiplication and division in structions Bit 31 is the sign bit An implied radix po
232. CTR 2 0 CCF 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCSTAT contains information related to the status of a conversion sequence SCF Sequence Complete Flag 0 Sequence not complete 1 Sequence complete SCF is set at the end of the conversion sequence when SCAN is cleared and at the end of the first conversion sequence when SCAN is set SCF is cleared when ADCTL1 is written and a new conversion sequence begins CCTR 2 0 Conversion Counter This field reflects the contents of the conversion counter pointer in either four or eight count conversion sequence The value corresponds to the number of the next result register to be written and thus indicates which channel is being converted CCF 7 0 Conversion Complete Flags Each bit in this field corresponds to an A D result register for example CCF7 to RSLT7 A bit is set when conversion for the corresponding channel is complete and remains set until the associated result register is read D 5 7 Right Justified Unsigned Result Register RJURR Right Justified Unsigned Result Register YFF710 YFF71F 15 10 9 8 1 6 5 4 3 2 1 0 NOT USED 10 10 8 10 8 10 8 10 8 10 8 10 8 10 8 10 8 10 Conversion result is unsigned right justified data Bits 9 0 are used for 10 bit resolu tion For 8 bit conversions bits 7 0 contain data and bits 9 8 are zero Bits 15 10 always return zero when read D 5 8 Left Justified Signed Result Register LJSRR Left Justified Signed Res
233. Condition Code Register 15 14 13 12 10 9 8 1 6 5 4 3 2 1 0 5 MV H EV N Z 2 0 5 PK 3 0 The CCR contains processor status flags the interrupt priority field and the program counter address extension field The CPU16 has a special set of instructions that ma nipulate the CCR S STOP Enable 0 Stop CPU16 clocks when LPSTOP instruction is executed 1 Perform NOPs when LPSTOP instruction is executed MV Accumulator M overflow flag Set when overflow into AM35 has occurred H Half Carry Flag Set when a carry from A3 or B3 occurs during BCD addition EV Accumulator M Extension Overflow Flag EV is set when an overflow into 1 has occurred N Negative Flag N is set under the following conditions When the MSB is set in the operand of a read operation When the MSB is set in the result of a logic or arithmetic operation Z Zero Flag Z is set under the following conditions When all bits are zero in the operand of a read operation When all bits are zero in the result of a logic or arithmetic operation V Overflow Flag Set when two s complement overflow occurs as the result of an operation C Carry Flag Set when carry or borrow occurs during arithmetic operation Also used during shifts and rotates IP 2 0 Interrupt Priority Field The priority value in this field 0 to 7 is used to mask low priority interrupts SM Saturate Mode Bit When SM is set if ei
234. Count Register D 22 0 2 25 Test Module Control Register 4 4 22 D 22 D 2 26 Test Module Distributed Register D 22 D 3 RAM MOUIS D 23 D 3 1 RAM Module Configuration Register D 23 D 3 2 RAM Test REJISIGI D 24 D 3 3 Array Base Address Register High D 24 D 3 4 Array Base Address Register LOW D 24 D 4 Masked ROM Module 2020 10 4 4 000 0 nnne D 25 0 4 1 Masked ROM Module Configuration Register D 25 D 4 2 ROM Array Base Address Registers D 27 D 4 3 ROM Signature Registers 02222222 D 27 D 4 4 Bootstrap Words 0 28 D 5 Analog to Digital Converter Module D 29 D 5 1 ADC Module Configuration Register D 30 D 5 2 ADG Tos PESI D 30 D 5 3 Port ADA Data Register eosdebet nnper iaa tad aa I Kex D 30 D 5 4 ADG Control Regisier Q M D 31 D 5 5 ADC Control Register 1 D 32 D 5 6 ADC Status Regle D 36 D 5 7 Right Justified Unsigned Result Register D 36 D 6 1 NR
235. D can be used as 1 SCI transmitter enabled TXD pin dedicated to SCI transmitter RE Receiver Enable 0 SCI receiver disabled 1 SCI receiver enabled RWU Receiver Wake Up 0 Normal receiver operation received data recognized 1 Wake up mode enabled received data ignored until receiver is awakened SBK Send Break 0 Normal operation 1 Break frame s transmitted after completion of the current frame REGISTER SUMMARY M68HC16 Z SERIES D 42 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 6 6 SCI Status Register SCSR SCI Status Register YFFCOC 15 9 8 7 6 5 4 3 2 1 0 NOT USED TDRE TC RDRF RAF IDLE OR NF FE PF RESET 1 1 0 0 0 0 0 0 0 SCSR contains flags that show SCI operating conditions These flags are cleared ei ther by SCI hardware or by a read write sequence The sequence consists of reading SCSR then reading or writing SCDR If internal SCI signal for setting a status bit comes after reading the asserted status bits but before writing or reading SCDR the newly set status bit is not cleared SCSR must be read again with the bit set and SCDR must be read or written before the status bit is cleared A long word read can consecutively access both SCSR and SCDR This action clears receive status flag bits that were set at the time of the read but does not clear TDRE or TC flags Reading either byte of
236. D 2 ZK IZ XK IX 20 E XK 1X sey YK 20 E 2 IY AEZ AOI ZK IZ 20 E gt ZK IZ AIS Add Immediate Data SK SP 20 IMM 2 to Stack Pointer SK SP 4 AIX Add Immediate Value IX 20 IMM 2 A to IX XK IX 4 Add Immediate Value YK IY 20 IMM 2 A to IY YK IY 4 AIZ Add Immediate Value ZK IZ 20 IMM gt 2 A to IZ ZK IZ 4 ANDA 6 A 0 6 6 IMM8 2 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 E X 6 Y 6 E Z 6 M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 13 Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT EY E Z IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT Y 2 16 IND16 IND16 IND16 2 AND CCR CCR IMM16 CCR IMM16 Arithmetic Shift Left IND8 X 4 IND8 IND8 Z IND16 X IND16 Y IND16 Z EXT Arithmetic Shift Left A INH EHO N Arithmetic Shift Left B Coo Arithmetic Shift Left D Arithmeti
237. D 47 Exampies or OG no aan ER Dna mas a D 48 MOGI BRIN Map D 54 interrupt Vector D 56 D 57 Effect of MDDR on MCCI Pin Function D 58 Examples or SCI Baud Ratos D 60 GPT Address E n D 67 DET asa etre reece adopter D 69 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF TABLES Continued Table Title Page 0 44 and PEDGE Effects D 45 PACLK 1 0 Effects 0 46 OM OL 5 2 Effects 07 TENGO 0 48 CPR 2 O Prescaler Select Field ura MT 0 50 Frequency Ranges M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SECTION 1 INTRODUCTION M68HC16 Z series microcontrollers including the MC68HC16Z1 MC68CM16Z1 MC68CK16Z1 68 1672 MC68HC16Z3 MC68HC16Z4 and 68 1674 are high speed 16 bit control units that are upwardl
238. EXT EY E Z IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT E X Y 2 Opcode Operand Cycles 5 2 222 A A vic 0 IND8 IND8 Y 1408 Z 16 IND16 IND16 Y IND16 Z EXT Y 2 16 IND16 IND16 IND16 2 PSHA PSHB PSHM OR Condition Code Register Push Multiple Registers Mask bits 0 D 1 2 1 3 1 4 12 6 CCR 7 Reserved CCR IMM16 CCR SK SP 0001 SK Push A SK SP 0002 2 SK SK SP 0001 2 SK Push B SK SP 0002 2 SK For mask bits 0 to 7 If mask bit set Push register SK SP 2 gt SK SP IMM16 3708 3718 PSHMAC Push MAC Registers MAC Registers Stack INH 27B8 PULA PULB M68HC16 Z SERIES USER S MANUAL SK SP 0002 2 SK SP Pull A SK SP 0001 SK SP SK SP 0002 2 SK SP Pull B SK SP 0001 2 SK SP 3709 3719 CENTRAL PROCESSING UNIT PL number of registers pushed For More Information On This Product Go to www freescale com 4 23 Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnem
239. FC16B1 SPMCM16Z2BVFC20 MCM16Z2BVFC20 1672 20 1 SPMCM16Z2BVFC25 MCM16Z2BVFC25 40 to 125 C MCM16Z2BVFC25B1 SPMCM16Z2BMFC16 MCM16Z2BMFC16 MCM16Z2BMFC16B1 20 MHz 2 SPMCM16Z2BMFC20 36 MCM16Z2BMFC20 180 MCM16Z2BMFC20B1 M68HC16 ZSERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers Crystal Operating Package Frequency Device Input Voltage Type Temperature MHz Order Number MC68HC16Z2 5V No ROM 5V MCM16Z2BVPV16 SPMCM16Z2BVPV20 MCM16Z2BVPV20B1 MCM16Z2BVPV25 40 to 125 C SPMCM16Z2BMPV16 MCM16Z2BMPV16B1 MCM16Z2BMPV20 68 1623 40 to 85 NA NA MC68HC16Z3CFC20 NA NA 144 Pin 40 to 85 C 2 SPMCM16Z2BCPV16 MCM16Z2BCPV16B1 MCM16Z2BCPV20 SPMCM16Z2BCPV25 MCM16Z2BCPV25B1 MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers Crystal Operating Package Frequency Device Input Type Temperature
240. For More Information On This Product to www freescale com Freescale Semiconductor Inc An interrupt request can be made when each of the status flags is set However op eration of the PAI interrupt depends on operating mode In event counting mode an interrupt is requested when the edge being counted is detected In gated mode the request is made when the PAI input changes from active to inactive state Interrupt re quests are enabled by the PAOVI bits in the TMSK register Bits in the pulse accumulator control register PACTL control the operation of PACNT The PAMOD bit selects event counting or gated operation In event counting mode the PEDGE control bit determines whether a rising or falling edge is detected In gated mode PEDGE specifies the active state of the gate signal Bits PACLK 1 0 select the clock source used in gated mode PACTL and PACNT are implemented as one 16 bit register but can be accessed with byte or word access cycles Both registers are cleared at reset but the PAIS and PCLKS bits show the state of the PAI and PCLK pins The PAI pin can also be used for general purpose input The logic state of the PAIS bit in PACTL shows the state of the pin 11 11 Pulse Width Modulation Unit The pulse width modulation PWM unit has two output channels PWMA and PWMB A single clock output from the prescaler multiplexer drives a 16 bit counter that is used to control both channels Figure 11 6 is
241. Freesca le Semiconductor Ord EE 16 M68HC 162 Series MC 68HC 1621 MC 68C K16Z1 MC 68C M1621 MC 68HC 1622 MC 68HC 1623 MC 68HC 16 4 MC 68C 1624 User s Manual 2 2 2 gt freescale semiconductor Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Users
242. G QUEUE POINTER IS WRAP ENABLE BIT ASSERTED RESET WORKING QUEUE POINTER TO NEWQP OR 0000 DISABLE 05 IS HALT HALT QSPI AND OR FREEZE ASSERT HALTA ASSERTED IS INTERRUPT ENABLE BIT HMIE ASSERTED REQUEST INTERRUPT IS HALT Y OR FREEZE ASSERTED QSPISLV2 FLOW 6 Figure 9 9 Flowchart of QSPI Slave Operation Part 2 M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 15 Go to www freescale com Freescale Semiconductor Inc Normally the SPI bus performs synchronous bidirectional transfers The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data Four possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCRO Data is transferred with the most significant bit first The number of bits transferred per command defaults to eight but can be set to any value from eight to sixteen bits inclu sive by writing a value into the BITS 3 0 field in SPCRO and setting BITSE in the com mand RAM Typically SPI bus outputs not open drain unless multiple SPI masters are in the system If needed the WOMQ bit in SPCRO can be set to provide wired OR open drain outputs An external pull up resistor should be used on each output line WOMQ affects all QSPI pins regardless of whether they are assigned to the QSPI or used as general p
243. GATE AS AND DS 55 TERMINATE CYCLE 55 Y 1 REMOVE DATA FROM DATA BUS START NEXT CYCLE 50 2 NEGATE DSACK RD CYC FLOW Figure 5 12 Word Read Cycle Flowchart 5 6 2 2 Write Cycle During a write cycle the MCU transfers data to an external memory or peripheral de vice If the instruction specifies a long word or word operation the MCU attempts to write two bytes at once For a byte operation the MCU writes one byte The portion of the data bus upon which each byte is written depends on operand size peripheral ad dress and peripheral port size Refer to 5 5 2 Dynamic Bus Sizing and 5 5 4 Misaligned Operands for more infor mation Figure 5 13 is a flowchart of a write cycle operation for a word transfer Refer to the SIM Reference Manual SIMRM AD for more information SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 38 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc MCU PERIPHERAL ADDRESS DEVICE S0 1 SET R W TO WRITE 2 DRIVE ADDRESS ON ADDR 23 0 3 DRIVE FUNCTION CODE ON FC 2 0 4 DRIVE SIZ 1 0 FOR OPERAND SIZE ASSERT AS 51 PLACE DATA DATA 15 0 52 ASSERT DS AND WAIT FOR DSACK S3 ACCEPT DATA 52 53 1 DECODE ADDRESS 2 LATCH DATA FROM DATA BUS OPTIONAL STATE S4 3 ASSERT DSACK SIGNALS NO CHANGE Y TERMINATE OUTPUT TRANSFER S5 1 NE
244. GATE DS AND AS 2 REMOVE DATA FROM DATA BUS TERMINATE CYCLE NEGATE DSACK START NEXT CYCLE Figure 5 13 Write Cycle Flowchart WR CYC FLOW 5 6 3 Fast Termination Cycles When an external device can meet fast access timing an internal chip select circuit fast termination option can provide a two cycle external bus transfer Because the chip select circuits are driven from the system clock the bus cycle termination is in herently synchronized with the system clock If multiple chip selects are to be used to provide control signals to a single device and match conditions occur simultaneously all MODE STRB and associated DSACK fields must be programmed to the same value This prevents a conflict on the internal bus when the wait states are loaded into the DSACK counter shared by all chip se lects M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 39 Go to www freescale com Freescale Semiconductor Inc Fast termination cycles use internal handshaking signals generated by the chip select logic To initiate a transfer the MCU asserts an address and the SIZ 1 0 signals When AS DS and R W are valid a peripheral device either places data on the bus read cycle or latches data from the bus write cycle At the appropriate time chip select logic asserts data size acknowledge signals The DSACK option fields in the chip select option registers determine whether int
245. Go to www freescale com Freescale Semiconductor Inc Table 3 5 M68HC16 Z Series Signal Function Continued Mnemonic Signal Name Function PF 7 0 Port F Port digital I O port signals PQS 7 0 Port QS QSM digital I O port signals QUOT Quotient Out Provides the quotient bit of the polynomial divider RESET Reset System reset RXDA SCI A Receive Data Serial input from SCI A Serial input from SCI B SCK Serial Clock QSPI m from QSPI in master mode clock input to QSPI in Clock output from SPI in master mode clock input to SPI in slave mode SCK Serial Clock SPI Indicates the number of bytes to be transferred during a bus cycle 55 Slave Select QSPI Causes serial transmission when QSPI is in slave mode causes mode fault in master mode Ss Slave Select SPI Causes serial transmission when the SPI is in slave mode causes mode fault in master mode TSC Three State Control Places all output drivers in a high impedance state TXD FC SIZ 1 0 Size SCI Transmit Data Serial output from the SCI TXDB SCI B Transmit Data Serial output from SCI B External Filter Capacitor Connection for external phase locked loop filter capacitor NOTES 1 MCCI signals present only in 68 1624 1674 3 6 Internal Register Map In Figures 3 8 3 9 and 3 10 IMB ADDR 23 20 are represented by the letter Y The value represented by Y determines the base address of MCU module control regis ters Y i
246. H MH MH MH MH HM MH MH MH MH MH MH MH MH MH MH MN MH MM p u uq up q 42 ee ee eee ed ee eee ee ge ee up ub OG Sg CR SPS GPG IP Sg GPG CoP Seg H CPR tue Gr eb UG I Sum ee ues eb F4 F4 F4 F4 F4 Fd HbA ALR CR ee ee A HRA R A ee ee RA H H ee FH FH FH FH O O Os OO Os O O 70 O O Os OSs Os O O O O O 70 O 7O O O GO OOO O O 20 O OO 0 0 O O O CO Gm cg ug Ue m ug B g u a Gy edo eed sel nnb rte cel cn eet ce eed tre cel moe eel set cel ocn o0 snb cel snc tte cele sey eel eel onn in cb n H H H H H H H H H H H H H H H H H H H FO Cy CX aaa a aa ae Aaa A G aa Aa a CX O O0 a O A A AAA Aa aA aA Aa AAA a Aaa Aa a Aa a a a HMM H
247. HH MH MH MH MH MH MH MH MH MH MH MH MH MH MH HHH MH MH MH HHH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MM 2 D 2 2 2 2 2 2 XO OO OY CO SO 4 CN OO si 1 SO COO CN OO si OM si SO 0001 CN OO DMO O1 O1 O1 O1 O1 O1 O1 CO QOO OO CO OO OO cd c c c oc oc oc oc ce oc CN CON CN CV CJ 00 00 00 00 00 00 00 00 c cd coco coc coc c OON CN CN CX CN CN CV CN CN CV CN CN CV CN CN CON CON CY OY CN 36 AA es EX 2h Y AG Cs Ae 24 EY EY As QAO As TY Os As OQ AQ EY a MMAM OE OE O V O
248. IEW USER S MANUAL For More Information On This Product 3 13 Go to www freescale com Freescale Semiconductor Inc Table 3 4 M68HC16 Z Series Signal Characteristics Continued Signal MCU Signal Active Name Module Type State MISO QSM Input Output MISO MCCI Input Output MODCLK SIM Input MOSI QSM Input Output MOSI MCCI Input Output OC 5 1 GPT Output PAI GPT Input PE 7 0 SIM Input Output PGP 7 0 GPT Input Output PQS 7 0 QSM Input Output PCLK GPT Input PCS 3 0 QSM Input Output PWMA PWMB GP Output L QUOT SIM Output 1 0 0 RX RXDA Input RXDB Input SC QSM Input Output SCK MCCI Input Output TS X SIZ 1 0 SS TXD RESET SIM Input Output D QSM Input K 1 Output XFC Input XTAL SIM Output NOTES 1 Used only in the 68 16274 1674 OVERVIEW M68HC16 Z SERIES 3 14 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 5 M68HC16 Z Series Signal Function Mnemonic Signal Name Function ADDR 19 0 Address Bus 20 bit address bus used by CPU16 AS Address Strobe Indicates that a valid address is on the address bus BERR Bus Error Indicates that a bus error has occurred Acknowledge BKPT Breakpoint Signals a hardware breakpoint to the CPU CLKOUT System Clockout System clock output CSBOOT Boot Chip Select Chip select for externa
249. ISTICS USER S MANUAL For More Information On This Product 53 Go to www freescale com Freescale Semiconductor Inc EXT PIN PAI PACNT F F 00 PAIF PAOVF NOTES 1 PHI1 15 THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 A SIGNAL AFTER THE SYNCHRONIZER 3 B A AFTER THE DIGITAL FILTER 4 THE EXTERNAL LEADING EDGE CAUSES THE PULSE ACCUMULATOR TO INCREMENT AND THE PAIF FLAG TO BE SET 5 THE COUNTER TRANSITION FROM FF TO 00 CAUSES THE PAOVF FLAG TO BE SET PULSE ACCUM ECM LEAD EDGE Figure A 25 Pulse Accumulator Event Counting Mode Leading Edge ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com A 54 Freescale Semiconductor Inc 1 PHIL PAEN EXT PIN PAI PACNT PAIF NOTES 1 PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 1 4 CLOCKS PACNT WHEN GT PAIF IS ASSERTED 3 A PAI SIGNAL AFTER THE SYNCHRONIZER 4 B A AFTER THE DIGITAL FILTER 5 PAIF IS ASSERTED WHEN PAI IS NEGATED PULSE ACCUM GATED MODE Figure A 26 Pulse Accumulator Gated Mode Count While Pin High M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information O
250. Inc 3 1 4 Masked ROM Module MRM MC68HC1622 Z3 Only 8 Kbyte array accessible as bytes or words User selectable default base address User selectable bootstrap ROM function User selectable ROM verification code 3 1 5 Analog to Digital Converter ADC Eight channels eight result registers Eight automated modes Three result alignment modes 3 1 6 Queued Serial Module QSM Enhanced serial communication interface Queued serial peripheral interface One 8 bit dual function port 3 1 7 Multichannel Communication Interface MC68HC16Z4 CKZ4 Only Two channels of enhanced SCI UART One channel of SPI 3 1 8 General Purpose Timer GPT Two 16 bit free running counters with prescaler Three input capture channels Four output compare channels One input capture output compare channel One pulse accumulator event counter input Two pulse width modulation outputs Optional external clock input 3 2 Intermodule Bus The intermodule bus IMB is a standardized bus developed to facilitate the design of modular microcontrollers It contains circuitry that supports exception processing ad dress space partitioning multiple interrupt levels and vectored interrupts The stan dardized modules in M68HC16 Z series MCUs communicate with one another via the IMB Although the full IMB supports 24 address and 16 data lines M68HC16 Z series MCUs use only 20 address lines ADDR 23 20 foll
251. Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc DEC 2 PAOV_DONE skip print routine if not finished counting down from ten LDX STRING_PAOV JSR SEND_STRING print the message LDAB 50 STAB 2 reload the counter so we do it again PAOV DONE BCLR TFLG2 520 clear the PAOV flag bit RTI all done BDM BGND all other exception vectors point here and put the user in background mode M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL For More Information On This Product E 29 Go to www freescale com Freescale Semiconductor Inc INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 30 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc INDEX ABIU 8 3 AC timing 16 78 MHz A 21 20 97 MHz A 23 25 17 MHz A 25 low voltage 16 78 MHz A 19 Accumulator M overflow flag MV 4 4 D 3 offset addressing mode 4 10 ADC 8 1 AC characteristics A 65 low voltage A 63 address map D 29 analog subsystem 8 4 block diagram 8 2 bus interface unit ABIU 8 3 clock 8 6 conversion accuracy diagram 10 bit A 71 8 bit A 69 low voltage 10 bit A 70 8 bit A 68 control logic 8 7 modes 8 8 multiple channel conversions 8 11 parameters 8 8 single channel conversions 8 10 timing 8 12 DC electrical characteristics 5 V A 64 low
252. Invalid Fast Cycle Hold tci pI 15 ns 30A CLKOUT Low to Data In High Impedance ns 31 DSACK 1 0 Asserted to Data In Valid tDADI 50 ns 33 Clock Low to BG Asserted Negated ns 35 BR Asserted to BG Asserted tey 37 Asserted to BG Negated 1 2 39 BG Width Negated tau 2 39A BG Width Asserted 46 R W Width Asserted Write or Read 150 ns 46A R W Width Asserted Fast Write or Read Cycle trwas 90 ns Asynchronous Input Setup Time BR BGACK DSACK 1 0 BERR AVEC HALT 47B Asynchronous Input Hold Time 48 DSACK 1 0 Asserted to BERR HALT Asserted 53 Data Out Hold from Clock High 54 Clock High to Data Out High Impedance 47 ns ns ns ns ns 55 R W Asserted to Data Bus Impedance Change ns 70 Clock Low to Data Bus Driven Show Cycle tscLDD ns 71 Data Setup Time to Clock Low Show Cycle teci ps ns 72 Data Hold from Clock Low Show Cycle tscLDH ns 73 BKPT Input Setup Time 74 BKPT Input Hold Time ns ns 75 Mode Select Setup Time DATA 15 0 MODCLK BKPT pins 76 Mode Select Hold Time DATA 15 0 MODCLK pins ns 77 RESET Assertion 2 teya 78 RESET Rise 3 toyo 100 CLKOUT High to Phase 1 CHP1A ns 101 CLKOUT High to Phase 2 Asserted 4 CHP2A ns 102 1 Valid to AS or DS Asserted 4 tP4VSA
253. KKKKK DELAY LOOP4 M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc SEND STRING STD SCCR1 enable SCI receiver and transmitter LDAB 501 TBZK point ZK at bank 1 the SRAM LDZ 50000 for indexing the variables CNT DLY EQU 0000 loop counter EQU 0002 delay counter Main Program LDAB 7 clock speed to 16 777MHz STAB SYNCR w 0 x 1 y 111111 BRCLR 1 8 1 wait until synthesizer lock bit is set LDD 501 5 STD SCCRO set baud rate to 1200 JSR DELAY delay for modulus counter of SCI to flush LDX STRING load address of string into IX JSR SEND STRING subroutine to send string to dummy terminal LDAB 05 up loop counter STAB CNT Z LDX SEC STR load address of string into IX JSR SEND STRING subroutine to send string to dummy terminal DEC CNT Z decrement loop counter BNE OOP1 loop 5 times LDAB S4F change clock frequency to 4 194MHz STAB SYNCR w 0 x 1 001111 BRCLR SYNCR 1 8 LOOP2 wait until synthesizer lock bit is set LDD 5006 STD SCCRO set BAUD rate back to 1200 JSR DELAY delay for modulus counter of SCI to flush LDX STRING2 load address of string into JSR SEND STRING subroutine to send string to dummy terminal LDAB 05 set up of loops for loop counter to 5 STAB CNT Z LDX SEC STR load address of string into IX JSR SEND STRING subroutine to send stri
254. KKKKKKKKKKAKKKKKK INCLUD INCLUD INCLUD becaus Gl EQUATES ASM table of EQUates for common register addresses ORGOO000 ASM initialize reset vector ORGOO008 ASM initialize interrupt vectors We are choosing User Defined Interrupt Vector 9 interrupt vector 64 at address 0080 to be the base vector number VBA for the GPT F Xx ORG DC DC DC DC DC DC DC DC DC DC DC DC gt gt gt gt gt gt 2 ORG the least significant nibble in the address must be a 50 The VBA should be reflected in the GPT Interrupt Configuration Register ICR at 5 904 0080 Address for interrupt vector 64 PAOV_ROUTINE Adjusted Priority Channel PAC input Capture 1 IC2 ROUTINE input Capture 2 IC3 ROUTINE Input Capture 3 BD Output Compare 1 OC2 ROUTINE Output Compare 2 BD Output Compare 3 BD Output Compare 4 BD Input Capture 4 Output Compare 5 BD Timer Overflow BD Pulse Accumulator Overflow elevated BD Pulse Accumulator Input 0200 Start program after interrupt vectors Tnitialization Routines INCLUD COP INCLUD INCLUD Set up LDD STD LDD STD LDAB STAB LDAB E 26 s s s INITSYS ASM initially set EK F 0 0 2 0 Set sys clock at 16 78 MHz disable INITRA
255. LE AND TRANSFER SUCCESSIVE APPROXIMATION END PERIOD SEQUENCE CH1 CH2 CH 3 CH4 CH5 CH 6 CH7 CH 8 SCF FLAG SET HERE AND SEQUENCE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4 CHANNEL MODE ENDS IF IN THE 8 CHANNEL MODE 16 ADC 8 BIT TIM 1 Figure 8 2 8 Bit Conversion Timing ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF INITIAL FINAL SAMPLE TRANSFER SAMPLE TIME TIME TIME RESOLUTION TIME 2 ADC CLOCKS 16 1 2 1 1 1 1 1 1 1 1 1 1q 6 CYCLES CYCLES it CYCLE CYCLE CYCLE sit CYCLE CYCLE CYCLE 9 SARB 5 7 SAR6 SAR5 SAR4 SAR3 SAR2 SARI SARO EOC SAMPLE AND SUCCESSIVE APPROXIMATION END PERIO SEQUENCE c CH2 CH 3 CH 4 CH5 CH6 CH7 CH8 SCF FLAG SET HERE AND SEQUENCE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4 CHANNEL MODE ENDS IF IN THE 8 CHANNEL MODE 16 ADC 10 BIT TIM Figure 8 3 10 Bit Conversion Timing 8 7 7 Successive Approximation Register The successive approximation register accumulates the result of each conver sion one bit at a time starting with the most significant bit At the start of the resolution period the MSB of the SAR is set and all less significant bits are cleared Depending on the result of the first comparison the MSB is
256. M ASM turn on 1k internal SRAM at 10000 set stack in bank 1 SK 1 SP 03FE INITSCI ASM set SCI baud rate at 9600 enable SCI transmitter and receiver the interrupts 5008 Give the GPT IARB of SE GPTMCR SO we can generate interrupts SA640 elevate interrupt priority of PAOV ICR set GPT IRQ level to 6 amp assign vector 64 User vector 9 of the interrupt exception vector table as the GPT s Interrupt Vector Base Address 517 2 IC2 to generate interrupts TMSK1 525 Overflows to generate interrupts INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc STAB TMSK2 amp set the TCNT s prescale to sysclock 128 Set up Input Capture and Output Compare LDAB 527 Input Captures STAB TCTL2 TICl either TIC2 rise 11 TIC4 off LDAB 501 Output Compares STAB TCTL1 lOC2 toggle TOC3 off TOC4 off TOC5 off LDD 51000 set OC2 to toggle every time that STD TOC2 TCNT is 1000 Set up the Pulse Width Modulators A and B LDD 50064 set PWM prescaler to div by 128 STD PWMC set fast 512 Hz and PWMB slow 4 Hz LDAB 580 50 duty cycle STAB PWMA in STAB PWMB in PWMB Set up the Pulse Accumulator LDD 55000 set to sense rising edges in STD PACTL event counting mo
257. M Bootstrap Word 0 YFF830 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED ZK 3 0 SK 3 0 PK 3 0 ROMBS1 ROM Bootstrap Word 1 YFF832 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 PC 15 0 ROMBS2 ROM Bootstrap Word 2 YFF834 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 15 0 ROMBS3 ROM Bootstrap Word YFF836 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 12 15 0 Typically CPU16 reset vectors reside in non volatile memory and are fetched when the CPU16 comes out of reset These four words can be used as reset vectors with the contents specified at mask time The content of these words cannot be changed On generic blank ROM MC68HC16Z2 and MC68HC16Z3 devices ROMBS 0 3 masked to 0000 When the ROM on the MC68HC16Z2 and MC68HC16Z3 is masked with customer specific code ROMBS 0 3 respond to system addresses 00000 to 00006 during the reset vector fetch if BOOT O REGISTER SUMMARY M68HC16 Z SERIES D 28 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 5 Analog to Digital Converter Module Table D 24 ADC Module Address Map Address 150 187 9 YFF700 ADC Module Configuration Register ADCMCR YFF702 ADC Test Register ADCTEST YFF704 Not Used YFF706 Not Used Port ADA Data Register PORTADA YFF708 Not Used YFF70A Control Register 0 ADCTLO YFF70C Control Register 1 ADCTL1 YFF70E Statu
258. M Test Register E SPCR O0 3 QSM SPI Control Registers 0 3 SPSR QSM SPI Status Register SWSR SIM Software Watchdog Service Register SYPCR SIM System Protection Control Register TCTL 1 2 GPT Timer Control Registers 1 2 TI4 O5 GPT Timer Input Capture 4 Output Compare 5 Register TMSK 1 2 GPT Timer Mask Register 1 2 TR O F QSM Transmit RAM 0 F TSTMSRB SIM Test Module Master Shift Register B TSTSC SIM Test Module Shift Count Register M68HC16 Z SERIES NOMENCLATURE USER S MANUAL For More Information On This Product Go to www freescale com 2 5 Freescale Semiconductor Inc 2 4 Conventions Logic level one is the voltage that corresponds to a Boolean true 1 state Logic level zero is the voltage that corresponds to a Boolean false 0 state Set refers specifically to establishing logic level one on a bit or bits Clear refers specifically to establishing logic level zero on a bit or bits Asserted means that a signal is in active logic state An active low signal changes from logic level one to logic level zero when asserted and an active high signal chang es from logic level zero to logic level one Negated means that an asserted signal changes logic state An active low signal changes from logic level zero to logic level one when negated and an active high sig nal changes from logic level one to logic level zero A specific mnemonic within a range is referred to by mnemon
259. M array ROMBAL ROM Array Base Address Register Low YFF826 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 ROMBAH ROMBAL specify the ROM array base address The reset state of these registers is specified at mask time They can only be written when STOP 1 and LOCK 0 This prevents accidental remapping of the array Because the 8 Kbyte ROM array in the MC68HC16Z2 and the MC68HC16Z3 must be mapped to 8 Kbyte boundary ROMBAL bits 12 0 always contain 0000 ROMBAH ADDR 15 8 read zero D 4 3 ROM Signature Registers High RSIGHI ROM Signature Register High YFF828 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 RESET 0 0 0 RSIGLO ROM Signature Register Low YFF82A 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 RSP15 RSP14 RSP13 RSP12 RSP10 RSP9 5 8 RSP7 RSP6 RSP5 RSP4 RSP3 RSP2 RSPO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Signature registers RSIGHI and RSIGLO contain a user specified mask programmed signature pattern A user specified signature algorithm provides the capability to verify ROM array contents M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 27 Go to www freescale com Freescale Semiconductor Inc D 4 4 ROM Bootstrap Words 0 RO
260. MARY USER S MANUAL D 71 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 8 10 Input Capture 4 Output Compare 5 Register TI4 O5 Input Capture 4 Output Compare 5 Register YFF91C This register serves either as input capture register 4 or output compare register 5 de pending on the state of 14 05 in It is reset to FFFF D 8 11 Timer Control Registers 1 and 2 TCTL1 TCTL2 Timer Control Registers 1 2 YFF91E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCTL1 determines output compare mode and output logic level TCTL2 determines the type of input capture to be performed OM OL 5 2 Output Compare Mode Bits and Output Compare Level Bits Each pair of bits specifies an action to be taken when output comparison is successful Refer to Table D 46 Table D 46 OM OL 5 2 Effects OM OL 5 2 Action Taken 00 Timer disconnected from output logic 01 Toggle OCx output line 10 Clear OCx output line to zero 11 Set OCx output line to one EDGE 4 1 Input Capture Edge Control Each pair of bits configures input sensing logic for the corresponding input capture Refer to Table D 47 Table D 47 EDGE 4 1 Effects EDGE 4 1 Configuration 00 Capture disabled 01 Capture on rising edge only 10 Capture on falling edge only 11 Capture on any rising or falling edge D 8 12 Timer Interrupt Mask Registers 1 and 2 TMSK1 TMSK2 Timer Interr
261. MH MH MH MH MH MH MH HN MH MH MH MH HN MH MH MH HN NH MH MH MH MN MN MM 127 qe SEEMS S999 op NE EEN epus qo poa Spe Shs opu 259953 spur O OU OU OU U OU U U U OU U U U U U U U U U U U U U U U U OU U U U U U U U U 000 000 0 0 000 00 0000 0 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt pq 426 4339 qo 436 42 0 aq 9420 4D 49 ce up d op BS 492949 cg 430 420 0 0 49 PPD DDD 25 2 DDD DD DD DDD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD 2 D D 2 2 HUM MH MH MH MH MH MH HHH MH MH MH MH MH MH HHH MH MH HHH MH MH
262. MHz Order Number MC68HC16Z3 4 MHz 5V 132 Pin 40 to 105 C NA ROM or PQFP M HC16Z3CFC1 32 kHz C68HC16Z3CFC16 NA NA MC68HC16Z3VFC20 NA NA MC68HC16Z3VFC25 NA NA NA A A A A A 40 to 125 C N N MC68HC16Z3CPV16 N NA MC68HC16Z3CPV25 NA NA MC68HC16Z3VPV20 A A A A A 144 Pin 4010 85 C 40 to 105 C N N MC68HC16Z3MPV16 20 MHz 2 N s 300 NA 40 to 125 C M68HC16 ZSERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL For More Information On This Product Go to www freescale com Device MC68HC16Z3 RTOS Crystal Input 4 MHz Freescale Semiconductor Inc Shaded cells indicate preliminary part numbers Operating Package Voltage Temperature 5V 132 Pin 40 to 85 C Package Order Quantity Frequency MHz Table B 1 M68HC16 Z Series Ordering Information Continued Order Number PQFP SPMCM16Z3RCFC16 MCM16Z3RCFC16 MCM16Z3RCFC16B1 SPMCM16Z3RCFC20 MCM16Z3RCFC20 MCM16Z3RCFC20B1 SPMCM16Z3RCFC25 MCM16Z3RCFC25 40 to 105 C MCM16Z3RCFC25B1 SPMCM16Z3RVFC16 MCM16Z3RVFC16 MCM16Z3RVFC16B1 SPMCM16Z3RVFC20 MCM16Z3RVFC20 MCM16Z3RVFC20B1 SPMCM16Z3RVFC25 40 to 125 C MCM16Z3RVFC25 MCM16Z3RVFC25B1 SPMCM16Z3RMFC16 MCM16Z3RMFC16 MCM16Z3RMFC16B1 SPMCM16Z3RMFC20 144 Pin
263. MV H EV N Z VI C CPD Compare D to Memory IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT Y 2 Compare to Memory IMM16 IND16 X IND16 Y IND16 Z EXT 5 Compare Stack IND8 X Pointer to Memory IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT CPX Compare IX to IND8 Memory IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT CPY Compare IY to IND8 X Memory IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT CPZ Compare IZ to IND8 X Memory IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT DAA Decimal Adjust A INH DEC Decrement Memory IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT DECA Decrement A 01 A INH DECB Decrement B 01 INH DECW Decrement Memory M M 1 0001 IND16 X Word gt 1 IND16 IND16 2 EDIV Extended Unsigned 0 IX INH 3728 24 A AAA Integer Divide Quotient IX Remainder gt D N CENTRAL PROCESSING UNIT M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Contin
264. Manual Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which
265. More Information On This Product 9 29 Go to www freescale com Freescale Semiconductor Inc A receiver is placed in wake up mode by setting the RWU bit in SCCR1 While RWU is set receiver status flags and interrupts are disabled Although the CPU16 can clear RWU it is normally cleared by hardware during wake up The WAKE bit in SCCR1 determines which type of wake up is used When WAKE 0 idle line wake up is selected When WAKE 1 address mark wake up is selected Both types require a software based device addressing and recognition scheme Idle line wake up allows a receiver to sleep until an idle line is detected When an idle line is detected the receiver clears RWU and wakes up The receiver waits for the first frame of the next transmission The byte is received normally transferred to RDR and the RDRF flag is set If software does not recognize the address it can set RWU and put the receiver back to sleep For idle line wake up to work there must be a minimum of one frame of idle line between transmissions There must be no idle time between frames within a transmission Address mark wake up uses a special frame format to wake up the receiver When the MSB of an address mark frame is set that frame contains address information The first frame of each transmission must be an address frame When the MSB of a frame is set the receiver clears RWU and wakes up The byte is received normally trans ferred to the and th
266. More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 5 1 9 Bus Error Signal The bus error signal BERR is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion It can also be asserted in conjunction with DSACK to indicate a bus error condition provided it meets the appropriate timing requirements Refer to 5 6 5 Bus Exception Control Cycles for more information The internal bus monitor can generate the BERR signal for internal to internal and in ternal to external transfers In systems with an external bus master the SIM bus mon itor must be disabled and external logic must be provided to drive the BERR pin because the internal BERR monitor has no information about transfers initiated by an external bus master Refer to 5 6 6 External Bus Arbitration for more information 5 5 1 10 Halt Signal The halt signal HALT can be asserted by an external device for debugging purposes to cause single bus cycle operation or in combination with BERR a retry of a bus cy cle in error The HALT signal affects external bus cycles only As a result a program not requiring use of the external bus may continue executing unaffected by the HALT signal When the MCU completes a bus cycle with the HALT signal asserted DATA 15 0 is placed a high impedance state and bus control signals are driven in active the address function code size and read write si
267. Multiple 8 Conversion Single Channel Sequences 1 1 0 Multiple 4 Conversion Multichannel Sequences 1 1 1 Multiple 8 Conversion Multichannel Sequences CD CA Channel Selection Bits in this field select input channel or channels for A D conversion Conversion mode determines which channel or channels are selected for conversion and which result registers are used to store conversion results Tables D 29 and D 30 contain a summary of the effects of ADCTL1 bits and fields M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 33 Go to www freescale com Freescale Semiconductor Inc Table D 29 Single Channel Conversions MULT 0 S8CM CD CC CB Input Result Register 0 0 0 0 0 ANO RSLT 0 3 0 0 1 AN1 RSLT 0 3 0 0 0 1 0 AN2 RSLT 0 3 0 0 1 AN3 RSLT 0 3 0 0 1 0 0 4 RSLT 0 3 0 0 1 AN5 RSLT 0 3 0 0 1 1 0 AN6 RSLT 0 3 0 0 1 AN7 RSLT 0 3 0 1 0 0 0 Reserved RSLT 0 3 0 1 1 Reserved RSLT 0 3 0 1 0 1 0 Reserved RSLT 0 3 0 1 1 Reserved RSLT 0 3 0 1 1 0 0 RSLT 0 3 0 1 1 0 1 VRL RSLT 0 3 0 1 1 1 0 Vn 2 RSLT 0 3 0 1 1 1 1 Test Reserved RSLT 0 3 1 0 0 ANO RSLT 0 7 1 0 0 0 1 AN1 RSLT 0 7 1 0 0 AN2 RSLT 0 7 1 0 0 1 1 RSLT 0 7 1 0 0 AN4 RSLT 0 7 1 0 1 0 1 AN5 RSLT 0 7 1 0 0 6 RSLT 0 7 1 0 1 1 1 AN7 RSLT 0 7 1 1 0 Reserved RSLT 0 7 1 1 0 0 1 Reserved RSLT 0 7 1 1 0 Reser
268. NDIX C DEVELOPMENT SUPPORT for more information on the MEVB E 1 Initialization Programs The following initialization routines accompany the programming examples used in this manual For information on assembler commands and directives refer to the M68HC16Z1EVB Evaluation Board User s Manual M68HC16Z1EVB D e EQUATES ASM This program lists of all the MC68HC16 registers equated to their memory address This allows programmers to use the register name in their programs and then the assembler selects the correct memory address for that register e ORGO00000 ASM This program consists of five lines of code that set the reset vector information into the proper locations e ORGO00008 ASM This program initializes the interrupt exception vectors 0008 01FE If an interrupt occurs requiring the use of any of these vectors program flow continues at the label BDM The programmer must add code at the label location to put the program running on the EVB16 into background de bug mode or some other appropriate routine e INITSYS ASM This program consists of ten to twelve lines of code that initial ize the system clock set the extension registers and chip selects It also turns off the COP software watchdog that is set to on after reset INITRAM ASM This program initializes the 1 Kbyte internal SRAM at 10000 and sets the stack inside it e INITSCLASM This program initializes the SCI to transmit and receive at
269. NTS ADC 10 BIT ACCURACY LV Figure A 36 Low Voltage 10 Bit ADC Conversion Accuracy ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 70 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 2 DEAL TRANSFER CURVE 472722 NYOBIT TRANSFER CURVE NO CIRCUIT ERROR DIGITAL OUTPUT INPUT IN mV Vay VRL 75 120 V A 5 COUNT 2 5 mV INHERENT QUANTIZATION ERROR B CIRCUIT CONTRIBUTED 10 mV ERROR 12 5 mV ABSOLUTE ERROR 2 5 10 BIT COUNTS ADC 10 BIT ACCURACY Figure A 37 10 Bit ADC Conversion Accuracy M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product 71 to www freescale com Freescale Semiconductor Inc ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 72 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION M68HC16 Z series microcontrollers are available in both 132 and 144 pin packages This appendix provides package pin assignment drawings dimensional drawings and ordering information M68HC16 ZSERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL For More Information On This Product 1 Go to www freescale com Freescale Semiconductor Inc PCS3 PQS6 PCS2 PQS5 PCS1 PQS4 lt gt PCSO SS PQS3 SCK PQS2 MISO PQSO ICYPGP2 OCYPGP3 OCZ OCYVPGPA4
270. NUAL For More Information On This Product 5 59 Go to www freescale com Freescale Semiconductor Inc Although arbitration is intended to deal with simultaneous requests of the same inter rupt level it always takes place even when a single source is requesting service This is important for two reasons the EBI does not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention and failure to contend causes the interrupt acknowledge bus cycle to be terminated early by a bus error When arbitration is complete the module with both the highest asserted interrupt level and the highest arbitration priority must terminate the bus cycle Internal modules place an interrupt vector number on the data bus and generate appropriate internal cy cle termination signals In the case of an external interrupt request after the interrupt acknowledge cycle is transferred to the external bus the appropriate external device must respond with a vector number then generate data size acknowledge DSACK termination signals or it must assert the autovector AVEC request signal If the de vice does not respond in time the SIM bus monitor if enabled asserts the bus error signal BERR and a spurious interrupt exception is taken Chip select logic can also be used to generate internal AVEC or DSACK signals in re sponse to interrupt acknowledgment cycles Refer to 5 9 3 Using Chip Select Sig nals for Interrupt
271. OP Bits 14 8 Not Implemented SUPV Supervisor Unrestricted This bit has no effect because the CPU16 in the MCU operates only in supervisor mode Bits 6 4 Not Implemented IARB 3 0 Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority Each module that can generate interrupt requests must be assigned a unique non zero IARB field value D 7 2 MCCI Test Register MTEST MCCI Test Register YFFCO2 Used for factory test only D 7 3 SCI Interrupt Level Register MCCI Interrupt Vector Register ILSCI SCI Interrupt Level Register YFFCOA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED ILSCIB 2 0 ILSCIA 2 0 MIVR RESET 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bits 15 14 Not Implemented ILSCIA 2 0 ILSCIB 2 0 Interrupt Level for SCIA SCIB The values of ILSCIA 2 0 and ILSCIB 2 0 in ILSCI determine the interrupt request levels of SCIA and SCIB interrupts respectively Program this field to a value from 0 interrupts disabled through 7 highest priority M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 55 Go to www freescale com Freescale Semiconductor Inc D 7 4 MCCI Interrupt Vector Register MIVR MCCI Interrupt Vector Register YFFCO5 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 ILSCI INTV 7 2 INTV 1 0 RESET 0 0 0 0 1 1 1 1 The MIVR determines which three vectors in the
272. OSE TIMER M68HC16 Z SERIES 11 12 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ww LI Lf LJ LJ LJ Lg _ CAPTURE COMPARE CLOCK TCNT 0101 X 0102 NENNEN EXTERNAL PIN SYNCHRONIZER OUTPUT CAPTURE REGISTER FLAG NOTES PHIL IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 16 32 IC TIM Figure 11 4 Input Capture Timing Example An input capture occurs every time a selected edge is detected even when the input capture status flag is set This means that the value read from the input capture regis ter corresponds to the most recent edge detected which may not be the edge that caused the status flag to be set 11 8 3 Output Compare Functions Each GPT output compare pin has an associated 16 bit compare register and a 16 bit comparator Each output compare function has an associated status flag and can cause the GPT to make an interrupt service request Output compare logic is designed to prevent false compares during data transition times When the programmed content of an output compare register matches the value in TCNT an output compare status flag bit in TFLG1 is set If the appropriate in terrupt enable bit in TMSK1 is set an interrupt request is made when a ma
273. PCS3 PCS2 51 pcsot COMMAND CONTROL PERIPHERAL CHIP SELECT NOTES 1 The 50 bit represents the dual function PCSO SS Command RAM is used by the QSPI when in master mode The CPU16 writes one byte of control information to this segment for each QSPI command to be executed The QSPI cannot modify information in command RAM Command RAM consists of 16 bytes Each byte is divided into two fields The periph eral chip select field enables peripherals for transfer The command control field pro vides transfer options A maximum of 16 commands can be in the queue Queue execution proceeds from the address in NEWQP through the address in ENDQP both of these fields are in SPCR2 CONT Continue 0 Control of chip selects returned to PORTQS after transfer is complete 1 Peripheral chip selects remain asserted after transfer is complete This allows for transfers greater than 16 bits to peripherals without negation of their chip selects BITSE Bits per Transfer Enable 0 Eight bits 1 Number of bits set in BITS field of SPCRO REGISTER SUMMARY M68HC16 Z SERIES D S2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc DT Delay after Transfer 0 Delay after transfer is 17 fs 1 SPCR1 DTL 7 0 specifies delay after transfer DSCK PCS to SCK Delay 0 PCS valid to SCK delay is one half SCK 1 SPCR1 DSCKL 6 0 specifies delay from PCS valid to SCK
274. PQS7 is the TXD output D 6 10 QSPI Control Register 0 SPCRO Control Register 0 YFFC18 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 5 3 0 CPOL 7 0 RESET 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 SPCRO contains parameters for configuring the QSPI and enabling various modes of operation SPCRO must be initialized before QSPI operation begins Writing a new val ue to SPCRO while the QSPI is enabled disrupts operation MSTR Master Slave Mode Select 0 QSPI is a slave device 1 QSPI is the system master REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com D 46 Freescale Semiconductor Inc WOMQ Wired OR Mode for QSPI Pins 0 Pins designated for output by DDRQS operate in normal mode 1 Pins designated for output by DDRQS operate in open drain mode BITS 3 0 Bits Per Transfer In master mode when BITSE is set in a command RAM byte BITS 3 0 determines the number of data bits transferred When BITSE is cleared eight bits are transferred Reserved values default to eight bits In slave mode the command RAM is not used and the setting of BITSE has no effect on QSPI transfers Instead the BITS 3 0 field determines the number of bits the QSPI will receive during each transfer before storing the received data Table D 35 shows the number of bits per transfer Table D 35 Bits Per T
275. PT AUTOVECTOR 050000 guks 77 777777 002 17__ LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032 006 19 37 UNASSIGNED RESERVED 0001FE 060000 harg 77717777777 0070 O1FE 38 FF USER DEFINED INTERRUPTS PROGRAM 070000 lu AND DATA SPACE I 07FFFF 080000 UNDEFINED UNDEFINED YFF700 F80000 pa 90000 ee FA0000 777 SY FF 93F 0000 tegen oe oe eee 512 KBYTE SECODUD t ee SY FFAT7F ese SYFFBOO CONTROL YFFB07 05 n Y FFDFF NOTE 1 THE ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24 BIT IMB ADDRESSES THE CPU16 ADDRESS BUS 15 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FROM 080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16 S FLAT 20 BIT ADDRESS SPACE THE CPU16 NEED ONLY GENERATE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE FE0000 1 4 14 FF0000 INTERNAL REGISTERS sFFFFFF HC16Z1 CK CM MEM MAP C Figure 3 11 MC68HC16Z1 CKZ1 CMZ1 Combined Program and Data Space Map OVERVIEW M68HC16 Z SERIES 3 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc
276. PTQP increments the working queue pointer and loads the next data for transfer from transmit RAM The command pointed to by the incremented working queue pointer is executed next unless a new value has been written to If a new queue pointer value is written while a transfer is in progress that transfer is completed normally When the CONT bit in command RAM byte is set PCS pins are continuously driven to specified states during and between transfers If the chip select pattern changes during or between transfers the original pattern is driven until execution of the follow ing transfer begins When CONT is cleared the data in register PORTQS is driven be tween transfers The data in PORTQS must match the inactive states of SCK and any peripheral chip selects used When the QSPI reaches the end of the queue it sets the SPIF flag SPIF is set during the final transfer before it is complete If the SPIFIE bit in SPCR2 is set an interrupt request is generated when SPIF is asserted At this point the QSPI clears SPE and stops unless wrap around mode is enabled 9 3 5 2 Master Wrap Around Mode Wrap around mode is enabled by setting the WREN bit in SPCR2 The queue can wrap to pointer address 0 or to the address pointed to by NEWQP depending on the state of the WRTO bit in SPCR2 In wrap around mode the QSPI cycles through the queue continuously even while the QSPI is requesting interrupt service SPE is not cleared when t
277. PWMC D 74 count register PWMCNT D 76 registers A B PWMA PWMB D 76 status registers timer interrupt flag register 1 TFLG1 11 12 timer control registers TCTL D 72 counter register TCNT D 70 interrupt flag registers TFLG D 74 mask registers TMSK D 72 single step mode 11 4 special operation modes 11 3 status flags 11 5 test mode 11 4 timer counter register TCNT 11 2 GPTMCR D 67 GPTMTR D 68 Grounding 8 17 4 4 D 3 Half carry flag H 4 4 D 3 HALT 5 25 5 33 5 37 5 43 5 45 Halt acknowledge flag HALTA D 51 monitor enable HME 5 25 D 13 reset HLT D 8 operation 5 45 negating reasserting 5 45 QSPI HALT D 51 HALT QSPI D 51 HALTA D 51 HALTA MODF interrupt enable HMIE bit D 51 Handshaking 5 36 Hardware breakpoints 5 41 HCMOS 1 2 High density complementary metal oxide semiconductor 5 1 2 HLT D 8 HME 5 25 D 13 HMIE D 51 Hysteresis 5 59 11 8 14 05 11 14 D 71 D 73 I4 O5F 0 74 For More Information On This Product IARB GPT 11 6 D 68 MCCI 10 3 D 55 QSM 9 3 D 39 SIM 5 3 5 59 D 7 IC4 11 14 ICD16 ICD32 C 2 ICF D 74 ICI D 73 ICR D 68 Ipp 5 54 IDLE 9 29 10 21 D 43 D 63 Idle frame 9 25 10 17 line detect type ILT D 42 D 61 detected IDLE 9 29 10 21 D 43 D 63 detection process 9 29 10 21 interrupt enable ILIE 9 29 10 22 D 42 D 61 type ILT 10 21 type ILT bit 9 29 lin 8 19 ILIE 9 29 10 22 D 42 D 61 ILQSPI D 40 ILSCI 10 2 D 40 D 55 ILSCIA
278. Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 18 Reset Source Summary Timing Cause Reset Lines Asserted by Coniroller RESET pin___ MSTAST CLKRST EXTRST Software watchdog Monitor Asynch Time out MSTRST CLKRST EXTRST HALT Monitor Asynch Internal HALT assertion MSTRST CLKRST EXTRST e g double bus fault Loss of clock Clock Synch Loss of reference MSTRST CLKRST EXTRST Test Test Synch Test mode MSTRST EXTRST Internal single byte or aligned word writes are guaranteed valid for synchronous re sets External writes are also guaranteed to complete provided the external configu ration logic on the data bus is conditioned as shown in Figure 5 18 5 7 3 Reset Mode Selection The logic states of certain data bus pins during reset determine SIM operating config uration In addition the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint as sertions Table 5 19 is a summary of reset mode selection options Table 5 19 Reset Mode Selection Default Function Alternate Function Mode Select Pin Pin Left High Pin Pulled Low DATAO CSBOOT 16 Bit CSBOOT 8 Bit CSO BR DATA1 CS1 BG CS2 BGACK CS3 FCO DATA2 54 55 2 DATA3 CS6 ADDR19 DATA4 CS 7 6 ADDR 20 19 DATAS5 CS 8 6 ADDR 21 19 DATA6 CS 9 6 ADDR 22 19
279. R IF EXOFF 1 THE CLKOUT PIN IS ALWAYS IN A HIGH IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP IF EXOFF 0 CLKOUT IS CONTROLLED BY STEXT IN LPSTOP SIM LPSTOPFLOW Figure 5 6 SIM LPSTOP Flowchart SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 22 For More Information On This Product USER S MANUAL Go to www freescale com SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP LEAVE IMBCLK ON IN LPSTOP SET STOP BITS FOR MODULES THAT WILL NOT BE ACTIVE IN LPSTOP SET STCPU2 1 fimbcik sys IN LPSTOP USING EXTERNAL CLOCK WANT CLKOUT ON IN LPSTOP SET STEXT 1 faut f clkout sys fsys IN LPSTOP Freescale Semiconductor Inc NO SET STCPU2 0 0 Hz IN LPSTOP NO USE SYSTEM CLOCK AS SIMCLK IN LPSTOP SET STSIM 1 SET STSIM 0 fsys het IN LPSTOP IN LPSTOP NO WANT CLKOUT ONIN LPSTOP SET STEXT 0 SET STEXT 1 SET STEXT 0 ferou 0Hz fret 0 Hz feck 0 Hz feck 0 Hz feck 0 Hz IN LPSTOP IN LPSTOP IN LPSTOP ae ENTER LPSTOP M68HC16 Z SERIES USER S MANUAL NOTES 1 IMBCLK IS THE CLOCK USED BY THE CPUI6L SIML ADC MCCI AND THE GPT 2 WHEN STCPU 1 THE CPU16L IS SHUT DOWN IN LPSTOP ALL OTHER MODULES WILL REMAIN ACTIVE UNLESS THE STOP BITS IN THEIR MODULE CONFIGURATION REGISTERS ARE SET PRIOR TO ENTERING LPSTOP 3
280. R 2 0 is driven out PWMA pin PPR 2 0 PWM Prescaler PCLK Select This field selects one of seven prescaler taps or PCLK to be PWMCNT input Refer to Table D 49 Table D 49 PPR 2 0 Field PPR 2 0 System Clock Divide By Factor 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 PCLK SFA PWMA Slow Fast Select 0 PWMA period is 256 PWMCNT increments long 1 PWMA period is 32768 PWMCNT increments long SFB PWNB Slow Fast Select 0 PWMB period is 256 PWMCNT increments long 1 PWMB period is 32768 PWMCNT increments long Table D 50 shows a range of PWM output frequencies using 16 78 MHz 20 97 MHz and 25 17 MHz system clocks M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 75 Go to www freescale com Freescale Semiconductor Inc Table D 50 PWM Frequency Ranges PPR 2 0 16 78 MHz Prescaler Tap 25 17 MHz 16 78 MHz SFA B 0 20 97 MHz 25 17 MHz 16 78 MHz 1 25 17 2 000 01 Div 2 8 39 MHz 20 97 MHz Div 2 10 5 MHz Div 2 12 6 MHz 32 8 kHz 41 kHz 0 Div 4 4 19 MHz Div 4 5 25 MHz Div 4 6 29 MHz 16 4 kHz 20 5 kHz 24 6 kHz 49 2 kHz 12 3 kHz 256 Hz 20 97 MHz 320 Hz 384 Hz 128 Hz 160 Hz 192 Hz 64 0 Hz 80 0 Hz 96 Hz 6 13 kHz 32 0 Hz 40 0 Hz 48 Hz 100 Div 32 524 kHz Div 32 655 kHz Div 32 787 kHz 2 05 kHz 2 56
281. R13 100 DATAS ADDR14 MMMMM 9 DATA9 ADDR15 ATWLYYWW 98 ADDR16 97 L1 vss ADDR17 96 DATA10 ADDR18 95 DATA11 VDD 94 _ DATA12 VSS 93 DATA13 VDDA VSSA DATA15 ANO PADAO ADDRO 1 89 1 AN2 PADA2 88 1 DSACRIPE1 AN3 PADA3 87 1 AVET PE2 AN4 PADA4 86 1 DS PE4 ANS PADAS 85 AS PES VRH 84 1 VDD nand5nsanedemnmeoecgo do cBOdReERHRRORPRERPRPOSSSS CPREAEAHRL SRS HRA L LEC RE LED EY s PPP DAR FE jg EE 1 NOTES 1 MMMMM MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK Moved Figure 3 6 MC68HC16Z4 CKZ4 Pin Assignments for 132 Pin Package M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 9 Go to www freescale com Freescale Semiconductor Inc THE T on voDIPDPPLE 2 gee ce had iu Ne t 1 TEAN EME ES yeu eg ET dE TET UE TE SEI UE E D IAE 555088888885 355288803 VDD 1109 VRHP R5ppES 11 ANS PADAS AN4 PADA4 metre AN3 PADA3 AN2 PADA2 DSACROPEO 11 1 ADDRO 11 ANO PADAO DATAI5 11 VSSA DATAM L VDDA DATA33 11 VSS DATA22 VDD DATAIL_ 1 ADDR18 DATA10 _ 1 ADDR17 vss 1 ADDR16 ADDR15 1 NC 1 68 1674 1 Datas 68 1674
282. RAM is not used in slave mode the CONT BITSE DT DSCK and peripheral chip select bits have no effect The 50 55 pin is used only as an in put SPBR DT and DSCKL fields in SPCRO and SPCR1 bits are not used in slave mode The QSPI drives neither the clock nor the chip select pins and thus cannot con trol clock rate or transfer delay Because the BITSE option is not available in slave mode the BITS field in SPCRO specifies the number of bits to be transferred for all transfers in the queue When the number of bits designated by BITS 3 0 has been transferred the QSPI stores the working queue pointer value in CPTQP increments the working queue pointer and loads new transmit data from transmit RAM into the data serializer The working queue pointer address is used the next time PCSO SS is asserted unless the CPU16 writes to first The QSPI shifts one bit for each pulse of SCK until the slave select input goes high If SS goes high before the number of bits specified by the BITS field is transferred the QSPI resumes operation at the same pointer address the next time SS is asserted The maximum value that the BITS field can have is 16 If more than 16 bits are trans mitted before SS is negated pointers are incremented and operation continues QUEUED SERIAL MODULE M68HC16 Z SERIES 9 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The QSPI transmit
283. RE EQU FA08 5 5 INTEGRATION TEST REGISTER E CLOCK PORTEO EQU FA11 PORTE DATA REGISTER SAME DATA AS PORTEL 1 EQU FA13 PORTE DATA REGISTER SAME DATA AS PORTEO DDRE EQU FA15 DATA DIRECTION REGISTER PEPAR EQU FA17 PORTE PIN ASSIGNMENT REGISTER PORTFO EQU FA19 PORT DATA REGISTER SAME DATA AS PORTF1 PORTF1 EQU FA1B DATA REGISTER SAME DATA AS PORTFO DDRF EQU FAID PORT F DATA DIRECTION REGISTER PFPAR EQU PORT PIN ASSIGNMENT REGISTER EQU FA21 5 5 PROTECTION CONTROL REGISTER PICR EQU FA22 PERIODIC INTERRUPT CONTROL REGISTER PITR EQU FA24 INTERRUPT TIMING REGISTER SWSR EQU FA27 SOFTWARE SERVICE REGISTER TSTMSRA EQU FA30 MASTER SHIFT REGISTER TSTMSRB EQU FA32 5 SHIFT REGISTER TSTSC EQU FA34 5 MODULE SHIFT COUNT TSTRC EQU FA36 5 MODULE REPETITION COUNT CREG EQU FA38 5 SUBMODULE CONTROL REGISTER DREG EQU FA3A DISTRIBUTED REGISTER CSPDR EQU FA41 PORT C DATA REGISTER CSPARO EQU FA44 CHIP SELECT PIN ASSIGNMENT REGISTER 0 CSPAR1 EQU FA46 CHIP SELECT PIN ASSIGNMENT REGISTER 1 CSBARBT EQU FA48 5 BOOT BASE ADDRESS REGISTER CSORBT EQU FA4A 5 BOOT OPTION REGISTER CSBARO EQU FA4C 5 0 BASE ADDRESS REGISTER CSORO EQU FA4E SELECT 0 OPTION REGISTER CSBAR1 EQU FA50 5 1 BASE ADDRE
284. RMODULE BUS IMB BUS INTERFACE UNIT 5 5 SERIAL PERIPHERAL INTERFACE SPI e gt PMCIMOSI PMC2 SCK 3 55 PORT PMC4 RXDB SERIAL COMMUNICATION INTERFACE SCIB gt Z NN PMC6 RXDA SERIAL COMMUNICATION INTERFACE SCIA gt PMCTITXDA MCCI BLOCK Figure 10 1 Block Diagram SPI provides easy peripheral expansion or interprocessor communication via full duplex synchronous three line bus data in data out and a serial clock Serial transfer of eight or sixteen bits can begin with the most significant bit MSB or least significant bit LSB The MCCI module can be configured as a master or slave device Clock control logic allows a selection of clock polarity and a choice of two clocking pro tocols to accommodate most available synchronous serial peripheral devices When the SPI is configured as a master software selects one of 254 different bit rates for the serial clock M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL For More Information On This Product 10 1 Go to www freescale com Freescale Semiconductor Inc The SCI is a universal asynchronous receiver transmitter UART serial interface with a standard non return to zero NRZ mark space format It operates in either full or half duplex mode It also contains separate transmit and receive enable bits and a double transmit buffer A modulus type baud rate generator provi
285. RR 0 38 0 6 1 0 38 0 6 2 QSM Test Register 0 39 0 6 3 QSM Interrupt Level Register Interrupt Vector Register D 39 D 6 4 SCI Control Register D 40 D 6 5 oie Bis eee D 41 D 6 6 REJSO 0 43 D 6 7 SGI Data Registe Ae RT D 44 D 6 8 US D 44 D 6 9 Port QS Pin Assignment Register Data Direction Register D 45 D 6 10 Control Registi U mm D 46 D 6 11 QSPI Control Register 1 D 48 D 6 12 QSPI Control Register D 49 D 6 13 Control gt ER I UU T D 50 D 6 14 Receive Data RAM MMC n D 51 D 6 15 hI Dala RAM aca ene ie ited a D 52 D 6 16 Command RAM m D 52 D 7 Multichannel Communication Interface Module D 54 M68HC16 Z SERIES Freescale Semiconductor Inc USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page D 7 1 MCCI Module Configuration Register D 54 D 7 2 MCCI Test Register eee D 55 0 7 3 SCI Interrupt Level Register MCCI
286. SCDR transmit one ASCII character to the screen TC LOOP LDAB SCSR t 1 ANDB 580 test the TC bit transfer complete BEQ TC LOOP continue to wait until TC is set RTS finish sending out byte STRING DC AM A HAPPY EVB16 RUNNING YOUR CODE 0A 0D 00 Interrupts Exceptions BDM BGND exception vectors point here and put the user in background debug mode Reserve data and stack space ORG 510000 start of internal SRAM for data amp stack COUNTER DS 2 Space for delay counter E 2 4 GPT Programming Example The following programming example involves demonstrating basic general purpose timer module GPT functions Refer to SECTION 11 GENERAL PURPOSE TIMER for more information on the GPT E 2 4 1 Example 7 Basic GPT Functions Description This program demonstrates some basic GPT functions H he 1st demo requires that the pins OC2 IC2 nd IC3 be tied together so that OC2 may drive IC2 amp IC3 In the second demo the pin should be connected to the PWMA pin A bell on the dummy terminal will ring when the Pulse Accumulator Counter X FF X F F M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL E 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc has overflowed ten times KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK
287. SCI RDRF and OR interrupts enabled ILIE Idle Line Interrupt Enable 0 SCI IDLE interrupts disabled 1 SCI IDLE interrupts enabled M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 61 Go to www freescale com Freescale Semiconductor Inc TE Transmitter Enable 0 SCI transmitter disabled TXD can be used as 1 SCI transmitter enabled TXD pin dedicated to SCI transmitter RE Receiver Enable 0 SCI receiver disabled 1 SCI receiver enabled RWU Receiver Wake Up 0 Normal receiver operation received data recognized 1 Wake up mode enabled received data ignored until receiver is awakened SBK Send Break 0 Normal operation 1 Break frame s transmitted after completion of the current frame D 7 11 Status Register SCSRA SCIA Status Register YFFC1C SCSRB SCIB Status Register YFFC2C 15 9 8 7 6 5 4 3 2 1 0 NOT USED TDRE TC RDRF RAF IDLE OR NF FE PF RESET 1 1 0 0 0 0 0 0 0 SCSR contains flags that show SCI operating conditions These flags are cleared ei ther by SCI hardware or by a read write sequence The sequence consists of reading SCSR then reading or writing SCDR If an internal SCI signal for setting a status bit comes after reading the asserted status bits but before writing or reading SCDR the newly set status bit is not cleared SCSR must be read again with the bit set and SCDR must be read or writte
288. SCSR causes all 16 bits to be accessed and any status bit already set in either byte is cleared on a subsequent read or write of SCDR Bits 15 9 Not implemented TDRE Transmit Data Register Empty 0 Transmit data register still contains data to be sent to the transmit serial shifter 1 A new character can now be written to the transmit data register TC Transmit Complete 0 SCI transmitter is busy 1 SCI transmitter is idle RDRF Receive Data Register Full 0 Receive data register is empty or contains previously read data 1 Receive data register contains new data RAF Receiver Active 0 SCI receiver is idle 1 SCI receiver is busy IDLE Idle Line Detected 0 SCI receiver did not detect an idle line condition 1 SCI receiver detected an idle line condition OR Overrun Error 0 Receive data register is empty and can accept data from the receive serial shifter 1 Receive data register is and cannot accept data from the receive serial shifter Any data in the shifter is lost and RDRF remains set M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 43 Go to www freescale com Freescale Semiconductor Inc NF Noise Error 0 No noise detected in the received data 1 Noise detected in the received data FE Framing Error 0 No framing error detected in the received data 1 Framing error or break detected in the received dat
289. SER S MANUAL Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products Th
290. SM register PQSPAR must be written to assign necessary pins to the QSPI The pins necessary for slave mode operation are MISO MOSI SCK and 50 55 MISO is used for serial data output in slave mode and MOSI is used for serial data input Either or both may be necessary depending on the particular application SCK is the serial clock input in slave mode and must be as signed to the QSPI for proper operation Assertion of the active low slave select signal SS initiates slave mode operation Before slave mode operation is initiated DDRQS must be written to direct data flow on the pins used Configure the MOSI SCK and 50 55 pins as inputs MISO pin must be configured as an output After pins are assigned and configured write data to be transmitted into transmit RAM Command RAM is not used in slave mode and does not need to be initialized Set the queue pointers as appropriate When SPE is set and MSTR is clear a low state on the slave select 50 55 pin be gins slave mode operation at the address indicated by NEWQP Data that is received is stored at the pointer address in receive RAM Data is simultaneously loaded into the data serializer from the pointer address in transmit RAM and transmitted Transfer is synchronized with the externally generated SCK The CPHA and CPOL bits determine upon which SCK edge to latch incoming data from the MISO pin and to drive outgoing data from the MOSI pin Because the command
291. SS REGISTER CSOR1 EQU FA52 CHIP SELECT 1 OPTION REGISTER CSBAR2 EQU FA54 5 2 BASE ADDRESS REGISTER CSOR2 EQU FA56 CHIP SELECT 2 OPTION REGISTER CSBAR3 EQU FA58 CHIP SELECT 3 BASE ADDRESS REGISTER CSOR3 EQU FA5A 5 3 OPTION REGISTER CSBAR4 EQU FA5C 5 4 BASE ADDRESS REGISTER CSOR4 EQU FASE CHIP SELECT 4 OPTION REGISTER CSBAR5 EQU FA60 CHIP SELECT 5 BASE ADDRESS REGISTER CSOR5 EQU FA62 CHIP SELECT 5 OPTION REGISTER CSBAR6 EQU FA64 CHIP SELECT 6 BASE ADDRESS REGISTER CSOR6 EQU FA66 CHIP SELECT 6 OPTION REGISTER CSBAR7 EQU FA68 7 BASE ADDRESS REGISTER CSOR7 EQU FA6A CHIP SELECT 7 OPTION REGISTER CSBAR8 EQU FA6C CHIP SELECT 8 BASE ADDRESS REGISTER CSOR8 EQU FA6E 5 8 OPTION REGISTER CSBAR9 EQU FA70 CHIP SELECT 9 BASE ADDRESS REGISTER CSOR9 EQU FA72 CHIP SELECT 9 OPTION REGISTER CSBAR10 EQU FA74 5 10 BASE ADDRESS REGISTER CSOR10 EQU FA76 CHIP SELECT 10 OPTION REGISTER INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 2 USER S MANUAL For More Information On This Product Go to www freescale com SRAM MODULE RAMMCR RAM RAM RAM ROM ROM SIG SIG ROM ROM ROM RO QMC QTE TST BAH BAL MR CR BAH BAL HI LO 50 51 BS2 BS3 OS R ST IO IO O IO lt Ei Ed EH EH EH DH Db Db BH
292. STER PACNT EQU SF90D PULSE ACCUMULATOR COUNTER EQU 90 INPUT CAPTURE REGISTER 1 IIC2 EQU 910 INPUT CAPTURE REGISTER 2 EQU 912 INPUT CAPTURE REGISTER 3 EQU 914 OUTPUT COMPARE REGISTER 1 TOC2 EQU 916 OUTPUT COMPARE REGISTER 2 TOC3 EQU 918 OUTPUT COMPARE REGISTER 3 TOCA EQU SF91A OUTPUT COMPARE REGISTER 4 405 EQU 91 INPUT CAPTURE 4 OR OUTPUT COMPARE 5 TCTL1 EQU 91 TIMER CONTROL REGISTER 1 TCTL2 EQU 91 TIMER CONTROL REGISTER 2 TMSK1 EQU 920 TIMER INTERRUPT MASK REGISTER 1 TMSK2 EQU 921 TIMER INTERRUPT MASK REGISTER 2 TFLG1 EQU F922 INTERRUPT FLAG REGISTER 1 TFLG2 EQU F923 TIMER INTERRUPT FLAG REGISTER 2 CFORC EQU 924 COMPARE FORCE REGISTER PWMC EQU 924 CONTROL REGISTER PWMA EQU SF926 PWM REGISTER A PWMB EQU F927 PWM REGISTER B PWMCNT EQU SF928 PWM COUNTER REGISTER PWMBUFA EQU SF92A BUFFER REGISTER PWMBUFB EQU S F92B BUFFER REGISTER PRESCL EQU 5 92 GPT PRESCALER ADC MODULE REGISTERS ADCMCR EQU 700 MODULE CONFIGURATION REGISTER ADTEST EQU F702 ADC TEST REGISTER ADCPDR EQU SF706 ADC PORT DATA REGISTER ADCTLO EQU SF70A A D CONTROL REGISTER 0 ADCTL1 EQU SF70C A D CONTROL REGISTER 1 ADSTAT EQU SF70E ADC STATUS REGISTER RJURRO EQU 710 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 0 RJURR1 EQU F712 RIGHT JUSTIFIED UNSIGNED RESULT REGISTER 1 RJURR
293. Semiconductor Inc 5 00 PAI ADDR23 CS 10 ECLK gt IC4 OC5 0C1 PGP7 IC4 0C5 0C1 OC4 0C1 PGP6 0 4 0 1 ADDR22 C5 9 PC6 OC3 0C1 PGP5 0C3 0C1 OczocuPcP4 7 8 2 77 0 20 1 O E ADDRIQ CSO PC3 CIPGP3 em Jl E JE FCA CSSIPC2 IC3IPGP2 P18 13 E x 54 1 IC2 PGP1 IC1 PGPO 9 FCO CS3IPCO BGACK CS2 BG CS1 gt TXDAIPMC7 BRICSO RXDAIPMC6 TXDB PMCS ADDR 18 0 RXDB PMC4 SIZ1 PE7 5170 MOSI PMC1 5 5 DS PE4 Ak 9 AVEC PE2 DSACKI PE1 DSACKO PEO DATA 15 0 RW AN7 PADA7 RESET AN6 PADA6 HALT ANS PADAS BERR 4 ROTPr AN2 PADA2 IRQU1 IRQSIPF5 AN1 PADA1 9l IRQ4 PF4 ANO PADAO ROPES IRQ2 PF2 MODCLK IRQUPFI MODCLK PFO CLKOUT gt EXTAL BKPT IPIPEO Ven BKPT DSCLK IPIPEI IPIPE1 DS 051 TSC TSC 0 050 9 rik QUOT FREEZEIQUOT _ FREEZE 1674 1674 BLOCK Figure 3 3 MC68HC16Z4 CK16Z4 Block Diagram OVERVIEW M68HC16 Z SERIES 3 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc PCS3 PQS6 PCS2 PQS5 PCS1 PQS4 gt PCSO SS PQS3 SCK PQS2 MOSI PQS1 MISO PQSO 2 1 IC3 PGP2 OCYPGP3 OC2 OC1 PGP4
294. Serial data input to SCIB RE 1 PMC4 10 4 3 Receive Data Pins RXDA RXDB RXDA and RXDB are the serial data inputs to the SCIA and SCIB interfaces respec tively Each pin is also available as a general purpose pin when the RE bit in 1 of the associated SCI submodule is cleared When used for general purpose RXDA and RXDB may be configured either as input or output as determined by the RXDA and RXDB bits in the MDDR 10 4 4 Transmit Data Pins TXDA TXDB When used for general purpose I O TXDA and TXDB can be configured either as in put or output as determined by the TXDA and TXDB bits in the MDDR The TXDA and TXDB pins are enabled for SCI use by setting the TE bit in SCCR1 of each SCI inter face 10 4 5 SCI Operation SCI operation can be polled by means of status flags in the SCSR or interrupt driven operation can be employed by means of the interrupt enable bits in SCCR1 10 4 5 1 Definition of Terms Data can be transmitted and received in a number of formats The following terms con cerning data format are used in this section e Bit Time The time required to transmit or receive one bit of data which is equal to one cycle of the baud frequency e Start Bit One bit time of logic zero that indicates the beginning of a data frame A start bit must begin with a one to zero transition and be preceded by at least three receive time samples of logic one Stop Bit One bit time of logic one t
295. Series Driver TVDOB u eines te o onis ttd adea ens baddns 3 12 3 3 M68HC16 Z Series Power 3 13 3 4 68 16 Z Series Signal 3 13 3 5 M68HC16 Z Series Signal FUNCOM 3 15 4 1 n uius Side di Moa a 4 9 4 2 Laid rene Set UU aha 4 12 4 3 Instruction Set Abbreviations and 4 02222 002 4 30 4 4 CPU16 Implementation of M68HC1 1 CPU Instructions 4 32 4 5 Exception Vector Table Gus esr pr Eni RR GHEREHERPUER A AT GRDERPREHREREE LUNO GR GERNE REN 4 38 4 6 IPIPEOIFIFET EACOGIMO RE REFERRING M RHEINE 4 41 4 7 Command 4 43 5 1 Snow Cyel Enaple IDE serseri inini E BA 5 3 5 2 16 78 MHz Clock Control 5 5 9 5 3 20 97 MHz Clock 5 11 5 4 25 17 MHz Clock Control MORIDEGES 5 13 5 5 16 78 MHz System Clock Freguenclaa ieu ate tace prn vance 5 15 5 6 System Clock Frequencies for a 20 97 MHz 5 17 5 7 System Clock Frequencies for a 25 17 2 System 5 19 5 8 Bus as d Ocenia Tm 5 25 5 9 MODCLK Pin and SWP Bit During Reset iius rer rere 5
296. TAL CONVERTER USER S MANUAL For More Information On This Product 8 3 Go to www freescale com Freescale Semiconductor Inc STOP is set during system reset and must be cleared before the ADC can be used Because analog circuit bias currents are turned off during low power stop mode the ADC requires recovery time after STOP is cleared Execution of the CPU16 LPSTOP command places the entire modular microcontroller in low power stop mode Refer to 5 3 4 Low Power Operation for more information 8 5 2 Freeze Mode When the CPU16 in the modular microcontroller enters background debug mode the FREEZE signal is asserted The type of response is determined by the value of the FRZ 1 0 field in the ADCMCR Table 8 1 shows the different ADC responses to FREEZE assertion Table 8 1 FRZ Field Selection FRZ 1 0 Response Ignore FREEZE continue conversions Reserved Finish conversion in process then freeze Freeze immediately When the ADC freezes the ADC clock stops and all sequential activity ceases Contents of control and status registers remain valid while frozen When the FREEZE signal is negated ADC activity resumes If the ADC freezes during a conversion activity resumes with the next step in the con version sequence However capacitors in the analog conversion circuitry discharge while the ADC is frozen as a result the conversion will be inaccurate Refer to 4 14 4 Background Debug Mode for more informatio
297. THE SIMCLK IS USED BY THE IR AND INPUT BLOCKS OF THE SIML 4 CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SIMCR IF EXOFF 1 THE CLKOUT PIN IS ALWAYS IN A HIGH IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP IF EXOFF 0 CLKOUT IS CONTROLLED BY STEXT IN LPSTOP WHEN STCPU 1 THE CPU16L IS DISABLED IN LPSTOP BUT ALL OTHER MODULES REMAIN ACTIVE OR STOPPED ACCORDING TO THE SETTING SIML LPSTOP FLOWCHART Figure 5 7 SIML LPSTOP Flowchart SYSTEM INTEGRATION MODULE For More Information On This Product 5 23 Go to www freescale com Freescale Semiconductor Inc 5 4 System Protection The system protection block preserves reset status monitors internal activity and pro vides periodic interrupt generation Figure 5 8 is a block diagram of the submodule MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG TIMER RESET REQUEST CLOCK 29 PRESCALER PERIODIC INTERRUPT TIMER SYS PROTECT BLOCK Figure 5 8 System Protection 5 4 1 Reset Status The reset status register RSR latches internal MCU status during reset Refer to 5 7 10 Reset Status Register for more information 5 4 2 Bus Monitor The internal bus monitor checks data size acknowledge DSACK or autovector AVEC signal response times during normal bus cycles The monitor asserts the in ternal bus error BERR signal when the r
298. TOR FILTER a FEEDBACK DIVIDER gt SYSTEM CLOCK CONTROL n NOTES 1 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR Z SERIES PLL BLOCK Figure 5 2 System Clock Block Diagram SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 3 1 Clock Sources The state of the clock mode MODCLK pin during reset determines the system clock source When MODCLK is held high during reset the clock synthesizer generates a clock signal from an external reference frequency The clock synthesizer control reg ister SYNCR determines operating frequency and mode of operation When MOD CLK is held low during reset the clock synthesizer is disabled and an external system clock signal must be driven onto the EXTAL pin The input clock referred to as 1 can be either a crystal or an external clock source The output of the clock system is referred to as Ensure that fref and fs are within normal operating limits To generate a reference frequency using the crystal oscillator a reference crystal must be connected between the EXTAL and XTAL pins Typically a 32 768 kHz crys tal is used for a slow reference but the frequency may vary between 25 kHz to 50 kHz Figure 5 3 shows a typical circuit Cl Rl 22 pF 330K XTAL R2 Li 10M i EXTAL C2 22 pF Vss RESISTANCE AND CAP
299. TRUSION ALLOWABLE MOLD ROTRUSION FOR DIMENSIONS A AND B IS 0 007 DIMENSIONS J AND P IS 0 010 UM PLANE H IS LOCATED AT THE UNDERSIDE LEADS WHERE LEADS EXIT PACKAGE BODY MS L M AND N TO BE DETERMINED WHERE ER LEADS EXIT PACKAGE BODY AT DATUM H NSIONS S AND V TO BE DETERMINED AT NG PLANE DATUM T NSIONS A B J AND P TO BE DETERMINED AT M PLANE H NSION F DOES NOT INCLUDE DAMBAR RUSIONS DAMBAR PROTRUSION SHALL CAUSE THE LEAD WIDTH TO EXCEED 0 019 0 010 T L M N 4x33 TIPS m 0 012 H L M N 4x gt m gt 0 004 T 432x SEATING PLANE 7 gt 2 gt 38 132x D1 5 DIM MIN A 1 400BSC 1 0 550 BSC B 1 10085 B1 0 550 BSC Y C 0 160 0 180 K1 0 020 0 040 H C2 0 135 0 145 x 4 Gace D 0008 0 012 u B B B B PLANE Di 0 012 0 016 02 0 008 0011 0 W E 0 006 0 008 K 0 E1 0 005 0 007 132x D 0 014 0 014 0 008 T G 0 025BSC 0 008 0 T L M D J 0 95088 Ji 0 475 BSC SECTION AA AA K 0 034 0 044 Ki 0 010BSC P 0 950 BSC 0 47
300. Table A 19 Low Voltage 16 78 MHz Background Debug Mode Timing and V 2 7 to 3 6Vdc V 0 T T to T DDSYN Num Characteristic Symbol BO DSI Input Setup Time tosisu B1 DSI Input Hold Time B2 DSCLK Setup Time B3 DSCLK Hold Time B4 DSO Delay Time B5 DSCLK Cycle Time B6 CLKOUT High to FREEZE Asserted Negated B7 CLKOUT High to IPIPE1 High Impedance B8 CLKOUT High to IPIPE1 Valid B9 DSCLK Low Time B10 B11 NOTES 1 All AC timing is shown with respect to Vi Vi levels unless otherwise noted Table A 20 16 78 MHz Background Debug Mode Timing Vp and 5 0 10 Vos 0 Vdc T to Characteristic Symbol Min Max Unit BO DSI Input Setup Time tpsisu 15 ns B1 DSI Input Hold Time ns 2 DSCLK Setup Time tpscsu ns B3 DSCLK Hold Time tpscH ns B4 DSO Delay Time tpsop ns 5 DSCLK Cycle Time tpsccvc 6 CLKOUT High to FREEZE Asserted Negated tERZAN ns B7 CLKOUT High to IPIPE1 High Impedance ns B8 CLKOUT High to IPIPE1 Valid ns B9 DSCLK Low Time B10 IPIPE1 High Impedance to FREEZE Asserted teyc B11 FREEZE Negated to IPIPE 0 1 Active teRIP 1 All AC timing is shown with respect to Vi Vi levels unless otherwise noted M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL A 37 For More Information On This Product Go to www frees
301. The reset value of the IARB field is 0 which prevents the MCCI from arbitrating during an interrupt acknowledge cycle The IARB field should be initialized by system software to a value from F highest priority through 1 low est priority Otherwise the CPU identifies any interrupts generated as spurious and takes a spurious interrupt exception If the MCCI wins the arbitration it generates an interrupt vector that uniquely identifies the interrupting serial interface The six MSBs are read from the interrupt vector INTV field in the MCCI interrupt vector register MIVR The two LSBs are assigned by the MCCI according to the interrupting serial interface as indicated in Table 10 1 Table 10 1 MCCI Interrupt Vectors Interface INTV 1 0 SCIA 00 SCIB 01 SPI 10 M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL For More Information On This Product 10 3 Go to www freescale com Freescale Semiconductor Inc Select a value for INTV so that each MCCI interrupt vector corresponds to one of the user defined vectors 40 FF Refer to the CPU16 Reference Manual CPU16RM AD for additional information on interrupt vectors 10 2 2 Pin Control and General Purpose I O The eight pins used by the SPI and SCI subsystems have alternate functions as gen eral purpose pins Configuring the MCCI submodule includes programming each pin for either general purpose or its serial interface function
302. To reduce power consumption selec tively the CPU can set the STOP bits in each module configuration register To mini mize overall microcontroller power consumption the CPU can execute the LPSTOP instruction which causes the SIM to turn off the system clock When individual module STOP bits are set clock signals inside each module are turned off but module registers are still accessible When the CPU executes LPSTOP a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic The SIM brings the MCU out of low power stop mode when one of the following exceptions occur e RESET Trace e SIM interrupt of higher priority than the stored interrupt mask Refer to 5 6 4 2 LPSTOP Broadcast Cycle for more information During a low power stop mode unless the system clock signal is supplied by an ex ternal source and that source is removed the SIM clock control logic and the SIM clock signal SIMCLK continue to operate The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK The SIM can also continue to gen erate the CLKOUT signal while in low power stop mode During low power stop mode the address bus continues to drive the LPSTOP instruc tion and bus control signals are negated I O pins configured as outputs continue to hold their previous state pins configured as inputs will be in a high impedance state STSIM and STEXT bits in SYNCR determin
303. U space CPU space is used for control information not normally associated with read or write bus cycles Function codes are valid only while AS is asserted Refer to 5 5 1 7 Function Codes for more information on codes and encoding During a CPU space access ADDR 19 16 are encoded to reflect the type of access being made Three encodings are used by the MCU as shown in Figure 5 14 These encodings represent breakpoint acknowledge type 0 cycles low power stop broad cast type 3 cycles and interrupt acknowledge type F cycles Type 0 and type 3 cycles are discussed in the following paragraphs Refer to 5 8 Interrupts for infor mation about interrupt acknowledge bus cycles SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 40 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc CPU SPACE CYCLES FUNCTION ADDRESS BUS CODE 2 0 2 4 210 111 000000000 2 0 23 16 0 LOWPOWER 111 000 0011 1111111111111110 STOP BROADCAST 2 0 2 li sl 1 0 Mer Neve ACKNOWLEDGE CPU SPACE TYPE FIELD CPU SPACE CYC TIM Figure 5 14 CPU Space Address Encoding 5 6 4 1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development In M68HC16 Z series MCUs breakpoints are treated as a type of exception process ing Breakpoints can
304. U16 performs a CPU space write to ad dress 3FFFE This write puts a copy of the interrupt mask value in the clock control logic The mask is encoded on the data bus as shown in Figure 5 16 The LPSTOP CPU space cycle is shown externally if the bus is available as an indi cation to external devices that the MCU is going into low power stop mode The SIM provides an internally generated DSACK response to this cycle The timing of this bus cycle is the same as for a fast termination write cycle If the bus is not available arbi trated away the LPSTOP broadcast cycle is not shown externally NOTE BERR during the LPSTOP broadcast cycle is ignored SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 42 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 15 14 13 2 1 10 9 8 7 6 5 4 3 2 1 0 o o 0 0 0 0 0 0 0 0 0 0 prask LPSTOP MASK LEVEL Figure 5 16 LPSTOP Interrupt Mask Level 5 6 5 Bus Exception Control Cycles An external device or a chip select circuit must assert at least one of the DSACK 1 0 signals or the AVEC signal to terminate a bus cycle normally Bus exception control cycles are used when bus cycles are not terminated in the expected manner There are two sources of bus exception control cycles e Bus error signal BERR When neither DSACK nor AVEC is asserted within a specified period after as sertion of AS the internal bus monitor asserts internal BERR
305. UPPORT USER S MANUAL For More Information On This Product C 1 Go to www freescale com Freescale Semiconductor Inc C 2 M68MEVB1632 Modular Evaluation Board The M68MEVB1632 Modular Evaluation Board MEVB is a development tool for eval uating M68HC16 and M68300 MCU based systems The MEVB consists of the M68MPFB1632 modular platform board an MCU personality board MPB an in cir cuit debugger ICD16 or ICD32 and development software MEVB features include An economical means of evaluating target systems incorporating M68HC16 and M68300 HCMOS MCU devices Expansion memory sockets for installing RAM EPROM or EEPROM Data RAM 32K x 16 128K x 16 or 512K x 16 EPROM EEPROM 32K x 16 64K x 16 128K x 16 256K x 16 or 512K x 16 Fast RAM 32K x 16 or 128K x 16 Background mode operation for detailed operation from a personal computer platform without an on board monitor Integrated assembly editing evaluation programming environment for easy de velopment AS many as seven software breakpoints Re usable ICD hardware for your target application debug or control e Two RS 232C terminal input output I O ports for user evaluation of the serial communication interface Logic analyzer pod connectors e Port replacement unit PRU to rebuild I O ports lost to address data control On board Vpp 12 VDC generation for MCU and flash EEPROM programming On board wire wrap area NOTE MC68HC16
306. VECTOR oof vee die 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 5040000 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVELS INTERRUPT AUTOVECTOR 002 16 LEVEL 6 INTERRUPT AUTOVECTOR 050000 guks 77 777777 002 17__ LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032 006 19 37 UNASSIGNED RESERVED 060000 litt 0070 01 38 FF USER DEFINED INTERRUPTS PROGRAM 070000 gk AND DATA SPACE y 07FFFF 080000 UNDEFINED UNDEFINED YFF700 y F7FFFF F80000 BANK 8 YFF73F F90000 gukg 777777 5 0000 BANK 10 pr on YFF900 YFF93F FB0000 BANK 11 EE 512 KBYTE 00 FC0000 gaz 77 7777777 SY FFAT7F 00000 777 7070077 YFFBOO CONTROL SYFFBO feaa 77 14 YFFC00 MCCI FF0000 gawas YFFC3F INTERNAL REGISTERS YFFDFF sFFFFFF NOTE 1 ADDRESSES DISPLAYED IN THIS MEMORY MAP ARE THE FULL 24 IMB ADDRESSES THE CPU16 ADDRESS BUS IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FROM 080000 TO F 7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMORY BANKS 0 TO 15 APPEAR FULLY CONTIGUOUS IN THE CPU16 S FLAT 20 BIT ADDRESS SPACE THE CPU16 NEED ONLY GENERATE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCATION IN THIS RANGE HC16Z4 CKZ4 MEM MAP C Figure 3 13 MC68HC16Z4 CKZ4 Combined Program and Data Space Map OVERVIEW M68HC16 Z SERIES
307. XT CLK INPUT TIM Figure A 2 External Clock Input Timing Diagram ECLK NOTE TIMING SHOWN WITH RESPECT TO Viy LEVELS 16 ECLK OUTPUT TIM Figure A 3 ECLK Output Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 28 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CLKOUT ADDR 23 0 FC 2 0 SIZ 1 0 ASYNCHRONOUS INPUTS IPIPEO IPIPE1 25254 AJJ UJ y a Ade T s Gries 103 OB 16 RD CYC TIM Figure 4 Read Cycle Timing Diagram M68HC16 Z SERIES USER S MANUAL ELECTRICAL CHARACTERISTICS For More Information On This Product A 29 Go to www freescale com Freescale Semiconductor Inc gt wn co gt CLKOUT OU Ji lo di ENS E NS AL JEH C SZ ADDR 23 20 FC 2 0 SIZ 1 0 1 RAV DATA 15 0 AS a PHASE 2 Co Y 5 p pe 16 WR CYC TIM Figure A 5 Write Cycle Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 30 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc gt
308. YFF73F YFF900 YFF93F 00 YFFATF 00 YFFB07 YFFCOO YFFC3F FFFFFF Freescale Semiconductor Inc ADC 64 BYTES ROM CONTROL 32 BYTES GPT 64 BYTES SIM 128 BYTES D SRAM CONTROL 8 BYTES 05 512 BYTES 8K ROM ARRAY MAPPED TO 8K BOUNDARY 2K SRAM ARRAY MAPPED TO 2K BOUNDARY 72 ONLY 4K SRAM ARRAY MAPPED TO 4K BOUNDARY Z3 ONLY HC1622 73 ADDRESS MAP Figure 3 9 MC68HC16Z2 Z3 Address Map ADC 64 BYTES GPT 64 BYTES SIML 128 BYTES SRAM CONTROL 8 BYTES 64 5 1K SRAM ARRAY MAPPED TO 1K BOUNDARY HC16Z4 CKZ4 ADDRESS MAP Figure 3 10 MC68HC16Z4 CKZ4 Address 3 18 OVERVIEW For More Information On This Product M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 3 7 Address Space Maps Figures 3 11 through 3 16 show CPU16 address space for M68HC16 Z series MCUs Address space can be split into physically distinct program and data spaces by decod ing the MCU function code outputs Figures 3 11 3 12 and 3 13 show the memory map of a system that has combined program and data spaces Figures 3 14 3 15 and 3 16 show the memory map when MCU function code outputs are decoded Reset and exception vectors are mapped into bank 0 and cannot be relocated The CPU16 program counter stack pointer and Z index register can be initialized to any address in pseudoline
309. Z1 and the MC68HC16Z2 Z3 both utilize the M68HC16MPFB however each MCU uses a different personality board M68MPB16Z1 on the MC68HC16Z1 M68MPB16Z2 Z3 on the MC68HC16Z2 Z3 DEVELOPMENT SUPPORT M68HC16 Z SERIES C 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX D REGISTER SUMMARY This appendix contains address maps register diagrams and bit field definitions for M68HC16 Z series MCUs More detailed information about register function is provid ed in the appropriate sections of the manual Except for central processing unit resources information is presented in the intermod ule bus address order shown in Table D 1 Table D 1 Module Address Map Size Base Bytes Address SIM 128 SRAM 8 YFFBOO MRM 68 1622 68 1623 only 52 ADC 64 YFF700 5 512 68 1624 68 1674 only Sy 64 YFF900 Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping MM bit in the SIM module configuration reg ister SIMCR determines where the control registers block is located in the system memory map When 0 register addresses range from 7 000 to 7FFFFF when MM 1 register addresses range from FFF000 to FFFFFF With the CPU16 ADDR 23 20 follow the logic state of ADDR19
310. a PF Parity Error 0 No parity error detected in the received data 1 Parity error detected in the received data D 6 7 SCI Data Register SCDR SCI Data Register YFFCOE 15 9 8 7 6 5 4 3 2 1 0 NOT USED 88 8 R7 T7 616 5 75 R373 8212 ROMO RESET U U U U U U U U U SCDR consists of two data registers located at the same address The receive data register RDR is a read only register that contains data received by the SCI serial in terface Data comes into the receive serial shifter and is transferred to RDR The trans mit data register TDR is a write only register that contains data to be transmitted Data is first written to TDR then transferred to the transmit serial shifter where addi tional format bits are added before transmission R 7 0 T 7 0 contain either the first eight data bits received when SCDR is read or the first eight data bits to be transmitted when SCDR is written R8 T8 are used when the is configured for nine bit opera tion When the SCI is configured for 8 bit operation R8 T8 has no meaning or effect D 6 8 Port QS Data Register PORTQS Port QS Data Register YFFC14 15 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 PORTQS latches data Writes drive pins defined as outputs Reads return data present on the pins To avoid driving undefined data first write a byte to PORTQS then configure DDRQS REGISTER SUMMARY M68HC16 Z SERIES D 44 For More I
311. a address manipulation To increase throughput the CPU16 performs effective address calculations and data prefetches during MAC operations In addition the MAC unit provides modulo addressing to im plement circular DSP buffers efficiently Refer to the CPU16 Reference Manual CPU16RM AD for detailed information con cerning the MAC unit and execution of DSP instructions M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 45 Go to www freescale com Freescale Semiconductor Inc CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 46 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 5 SYSTEM INTEGRATION MODULE This section is an overview of the system integration module SIM Refer to the 5 Reference Manual SIMRM AD for a comprehensive discussion of SIM capabilities Refer to D 2 System Integration Module for information concerning the SIM address map and register structure 5 1 General The SIM consists of six functional blocks Figure 5 1 shows a block diagram of the SIM The system configuration block controls MCU configuration parameters The system clock generates clock signals used by the SIM other IMB modules and external devices The system protection block provides bus and software watchdog monitors In addi tion it also provides a periodic interrupt timer to support execution of time critical con tr
312. a block diagram of the pulse width modulation unit GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 16 BIT DATA BUS PWMA REGISTER PWMB REGISTER PWMBUFA REGISTER PWMBUFB REGISTER PARATOR PARATOR PWMA n PIN LATCH 5 FIA ZERO DETECTOR ZERO DETECTOR amp BIT amp BIT a 27 5 U SFB MULTIPLEXER B MULTIPLEXER BIT 16 87 COUNTER ee FROM PRESCALER CLOCK 16 32 PWM BLOCK Figure 11 6 PWM Block Diagram The PWM unit has two operational modes Fast mode uses a clocking rate that equals 1 256 of the prescaler output rate slow mode uses a rate equal to 1 32768 of the pres caler output rate The duty cycle ratios of the two PWM channels can be individually controlled by software The PWMA pin can also output the clock that drives the PWM counter PWM pins can also be used as output pins M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL Go to www freescale com For More Information On This Product 11 17 Freescale Semiconductor Inc 11 11 1 PWM Counter The 16 bit counter in the PWM unit is similar to the timer counter in the capture com pare unit During reset the GPT is configured to use the system clock divided by two to drive the counter Initialization software can reconf
313. a few clock cycles after BGACK transition However if bus requests are still pending after BG is negated the MCU asserts BG again within a few clock cycles This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus Refer to Figure 5 17 which shows bus arbitration for a single device The flowchart shows BR negated at the same time BGACK is asserted SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 46 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc MCU REQUESTING DEVICE REQUEST THE BUS 1 ASSERT BUS REQUEST B 25 GRANT BUS ARBITRATION 1 ASSERT BUS GRANT BG ACKNOWLEDGE BUS MASTERSHIP 1 EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2 NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3 NEXT BUS MASTER ASSERTS BGACK 1 NEGATE BG AND WAIT FOR BGACK TO BE NEGATED OPERATE AS BUS MASTER 1 PERFORM DATA TRANSFERS READ AND WRITE CYCLES ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP 1 NEGATE BGACK RE ARBITRATE OR RESUME PROCESSOR OPERATION BUS ARB FLOW Figure 5 17 Bus Arbitration Flowchart for Single Request 5 6 6 1 Show Cycles The MCU normally performs internal data transfers without affecting the external bus but it is possible to show these transfers during debugging AS is not asserte
314. abled execution begins at queue address 0 unless another value has been written into NEWQP is ini tialized to 0 at reset but should be changed to show the last queue entry before the QSPI is enabled NEWQP and ENDQP can be written at any time When NEWQP changes the internal pointer value also changes However if NEWQP is written while a transfer is in progress the transfer is completed normally Leaving NEWQP and ENDOP set to 0 transfers only the data in transmit RAM location 0 9 3 5 QSPI Operating Modes The QSPI operates in either master or slave mode Master mode is used when the MCU initiates data transfers Slave mode is used when an external device initiates transfers Switching between these modes is controlled by MSTR in SPCRO Before entering either mode the appropriate QSM and QSPI registers must be initialized properly In master mode the QSPI executes a queue of commands defined by control bits in each command RAM queue entry Chip select pins are activated data is transmitted from the transmit RAM and received by the receive RAM In slave mode operation proceeds in response to SS pin activation by an external SPI bus master Operation is similar to master mode but no peripheral chip selects are generated and the number of bits transferred is controlled in a different manner When the QSPI is selected it automatically executes the next queue transfer to exchange data with the external device correctly
315. ackage Crystal Operating Package Frequency Device Input Voltage Type Temperature MHz Ta Order Number MC68HC1621 132 Pin 40 to 85 C SPMCK16Z1CFC16 MCK16Z1CFC16B1 MCK68HC16Z1CFC20 SPMCK16Z1CFC25 1671 25 1 MCK68HC16Z1VFC16 SPMCK16Z1VFC20 MCK16Z1VFC20B1 MCK68HC16Z1VFC25 MECHANICAL DATA AND ORDERING INFORMATION 68 16 Z SERIES 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table B 1 M68HC16 Z Series Ordering Information Continued Shaded cells indicate preliminary part numbers Crystal Operating Package Frequency Device Input Voltage Type Temperature MHz Order Number MC68HC1621 5V 132 Pin 40 to 125 C SPMCK16Z1MFC16 MCK16Z1MFC16B1 68 1621 20 MC68HC1621 5V 144 Pin 40 to 85 C SPMCK16Z1CPV16 MCK16Z1CPV16B1 68 1671 20 SPMCK16Z1CPV25 1671 25 1 MCK68HC16Z1VPV16 SPMCK196Z1VPV20 MCK16Z1VPV20B1 MCK68HC16Z1VPV25 40 to 125 C SPMCK16Z1MPV16 MCK16Z1MPV16B1 MCK68HC16Z1MPV20 MC68HC1621 40 to 85 C SPMCCK16Z1CFC16 MCCK16Z1CFC16B1 68 1671 16 MC68HC16Z1 i 40 to 85 C SPMCCM16Z1CFC16 180 MCCM16Z1CFC16B1 M68HC16 Z SERIES MECHANICAL DATA AND ORDERING INFORMATION USER S MANUAL For More Information On This Product B 9 Go to
316. actory test only D 5 3 Port ADA Data Register PORTADA Port ADA Data Register YFF706 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PADAT PADAG PADAS PADA4 PADA3 PADA1 PADAO RESET REFLECTS STATE OF THE INPUT PINS Port ADA is an input port that shares pins with the A D converter inputs REGISTER SUMMARY M68HC16 Z SERIES D 30 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc PADA 7 0 Port ADA Data Pins A read of PADA 7 0 returns the logic level of the port ADA pins If an input is not at an appropriate logic level that is outside the defined levels the read is indeterminate Use of a port ADA pin for digital input does not preclude its simultaneous use as analog input D 5 4 ADC Control Register 0 ADCTLO ADC Control Register 0 YFF70A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 1 1 ADCTLO is used to select 8 or 10 bit conversions sample time and ADC clock fre quency Writes to it have immediate effect RES10 10 Bit Resolution 0 8 bit conversion 1 10 bit conversion Conversion results are appropriately aligned in result registers to reflect the number of bits STS 1 0 Sample Time Selection Total conversion time is the sum of initial sample time transfer time final sample time and resolution time Initial sample time is fixed at two ADC clocks Transfer time is fixe
317. address must be stored so that execution of the original instruction stream can resume after the change in flow When an instruction that causes a change in program flow executes PK PC point to the address of the first word of the instruction 0006 During execution of the instruc tion PK PC is loaded with the address of the first instruction word in the new instruc tion stream However stages A and B still contain words from the old instruction stream Extra processing steps must be performed before execution from the new in struction stream 4 12 Instruction Timing The execution time of CPU16 instructions has three components Bus cycles required to prefetch the next instruction e Bus cycles required for operand accesses e Time required for internal operations A bus cycle requires a minimum of two system clock periods If the access time of a memory device is greater than two clock periods bus cycles are longer However all bus cycles must be an integer number of clock periods CPU16 internal operations are always an integer multiple of two clock periods Dynamic bus sizing affects bus cycle time The integration module manages all ac cesses Refer to SECTION 5 SYSTEM INTEGRATION MODULE for more informa tion The CPU16 does not execute more than one instruction at a time The total time re quired to execute a particular instruction stream can be calculated by summing the in dividual execution times of each instruction i
318. ain an even number of bytes Operands are organized as bytes words or a combination of bytes and words Oper ands of four bits are either zero extended to eight bits or packed two to a byte The largest instructions are six bytes in length Size order and function of operands are evaluated when an instruction is decoded A page 0 opcode and an 8 bit operand can be fetched simultaneously Instructions that use 8 bit indexed immediate and relative addressing modes have this form Code written with these instructions is very compact Figure 4 4 shows basic CPU16 instruction formats M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 33 Go to www freescale com Freescale Semiconductor Inc 8 Bit Opcode with 8 Bit Operand 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 Opcode Operand 8 Bit Opcode with 4 Bit Index Extensions 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 8 Bit Opcode Argument s 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 Opcode Operand Operand s 8 Bit Opcode with 8 Bit Prebyte No Argument 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 Bit Opcode with 8 Bit Prebyte Argument s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prebyte Opcode Operand s 2 8 Bit Opcode with 20 Bit Argument 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode 0 Extension Figure 4 4 Basic Instruction Formats 4 10 Execution Model This description builds up a conceptual model
319. ale Semiconductor Inc Table 5 5 16 78 MHz System Clock Frequencies Continued Shaded cells represent values that exceed 16 78 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2xValue fyco Value fyco 22xValue fyco Value 100000 4325 kHz 8651 kHz 17302 kHz 34603 kHz 100001 4456 8913 17826 35652 100011 4719 9437 18874 37749 100101 4981 9961 19923 39846 100111 5243 10486 20972 41943 101001 5505 11010 22020 44040 101011 5767 11534 23069 46137 101101 6029 12059 24117 48234 101111 6291 12583 25166 50332 110001 6554 13107 26214 52428 Y 110101 7078 14156 28312 56623 110111 7340 14680 29360 58720 111001 7602 15204 30409 60817 111011 7864 15729 31457 62915 111101 8126 16253 32506 65011 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 111111 8389 16777 33554 67109 SYSTEM INTEGRATION MODULE M68HC16 7 SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 6 System Clock Frequencies for a 20 97 MHz System Shaded cells represent values that exceed 20 97 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2x Value Value fyco 2 x Value fyco Value 000000 131 kHz 262 kHz 524 kHz 1049 kHz 000001 524 1049 2097 000011 1049 2097 4194 000101 786 1573 3146 6291 000111 1049 2097 4194 83
320. and HALT are asserted simultaneously the CPU16 acts as though only BERR is asserted When enabled the SIM bus monitor asserts BERR when DSACK response time exceeds a predetermined limit The bus monitor time out period is determined by the BMT 1 0 field in SYPCR The maximum bus monitor time out period is 64 system clock cycles 5 6 2 1 Read Cycle During a read cycle the MCU transfers data from an external memory or peripheral device If the instruction specifies a long word or word operation the MCU attempts to read two bytes at once For a byte operation the MCU reads one byte The portion of the data bus from which each byte is read depends on operand size peripheral ad dress and peripheral port size Figure 5 12 is a flowchart of a word read cycle Refer to 5 5 2 Dynamic Bus Sizing 5 5 4 Misaligned Operands and the S M Reference Manual SIMRM AD for more information M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 37 Go to www freescale com Freescale Semiconductor Inc MCU PERIPHERAL ADDRESS DEVICE S0 1 SET R W TO READ 2 DRIVE ADDRESS ON ADDR 23 0 3 DRIVE FUNCTION CODE ON FC 2 0 4 DRIVE SIZ 1 0 FOR OPERAND SIZE ASSERT 5 AND DS 51 PRESENT DATA 52 1 DECODE ADDR 512 1 0 05 2 PLACE DATA ON DATA 15 0 OR DATA 15 8 IF 8 BIT DATA 3 DRIVE DSACK SIGNALS DECODE DSACK 53 LATCH DATA S4 NE
321. ange and which edge causes data to be captured CPHA is used with CPOL to produce a desired clock data rela tionship between master and slave devices LSBF Least Significant Bit First 0 Serial data transfer starts with LSB 1 Serial data transfer starts with MSB REGISTER SUMMARY M68HC16 Z SERIES D 64 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SIZE Transfer Data Size 0 8 bit data transfer 1 16 bit data transfer SPBR 7 0 Serial Clock Baud Rate The SPI uses a modulus counter to derive the SCK baud rate from the MCU system clock Baud rate is selected by writing a value from 2 to 255 into SPBR 7 0 The following expressions apply to SCK baud rate or f sys SPBR 7 0 5x SCK Baud Rate Desired Giving SPBR 7 0 a value of zero or one disables SCK disable state determined by CPOL At reset the SCK baud rate is initialized to one eighth of the system clock frequency D 7 14 SPI Status Register SPSR SPI Status Register YFFC3C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPIF WCOL 0 MODF 0 0 0 0 0 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPSR contains information concerning the current serial transmission Only the SPI can set bits in SPSR The CPU16 reads SPSR to obtain SPI status information and writes it to clear status flags SPIF SPI Finished Flag 0 SPI is not finished 1 SPI is finished
322. ansfers to allow serial A D converters to com plete conversion Writing a value to DTL 7 0 in SPCR1 specifies a delay period The DT bit in each command RAM byte determines whether the standard delay period DT 0 or the user specified delay period DT 1 is used The following expression is used to calculate the delay 32 x DTL 7 0 if DT sys Delay after Transfer 1 where DTL equals 1 2 3 255 A zero value for DTL 7 0 causes a delay after transfer value of 8192 5 Standard Delay after Transfer us if DT 20 Sys Adequate delay between transfers must be specified for long data streams because the QSPI requires time to load a transmit RAM entry for transfer Receiving devices need at least the standard delay between successive transfers If the system clock is operating at a slower rate the delay between transfers must be increased proportion ately QUEUED SERIAL MODULE M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc QSPI operation is initiated by setting the SPE bit in SPCR1 Shortly after SPE is set the QSPI executes the command at the command RAM address pointed to by Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted Data that is simultaneously received is stored at the pointer address in receive RAM When the proper number of bits have been transferred the QSPI stores the working queue pointer value in C
323. antaneous Maximum Current 25 Single Pin Limit applies to all pins 3 5 6 Operating Maximum Current Digital Input Disruptive Current 5 6 7 8 0 3 V 0 3 V Operating Temperature Range Tj to Ty Suffix 40 to 85 V Suffix 40 to 105 M Suffix 40 to 125 Storage Temperature Range T 55 to 150 NOTES 1 Permanent damage can occur if maximum ratings are exceeded Exposure to voltages or currents in excess of recommended values affects device reliability Device modules may not operate normally while being exposed to electrical extremes 2 Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields take normal precautions to avoid exposure to voltages higher than maximum rated voltages 3 This parameter is periodically sampled rather than 100 tested 4 All pins except TSC 5 Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values 6 Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current 7 All functional non supply pins are internally clamped to Vss All functional pins except EXTAL TSC and XFC are internally clamped to Vpp 8 Total input current for all d
324. ar memory but exception vectors are limited to 16 bit address es To access locations outside of bank 0 during exception handler routines including interrupt exceptions a jump table must be used Refer to SECTION 4 CENTRAL PROCESSOR UNIT for more information concerning memory management extend ed addressing and exception processing Refer to SECTION 5 SYSTEM INTEGRA TION MODULE for more information concerning function codes address space types resets and interrupts M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 19 Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 0 RESET INITIAL ZK SK AND PK 9000000 VECTORS 0002 RESET INITIAL PC 0004 RESET INITIAL SP m 0006 RESET INITIAL IZ DIRECT PAGE 010000 0008 4 BKPT BREAKPOINT 000A 5 BERR BUS ERROR 000C 6 SWI SOFTWARE INTERRUPT 020000 77 000 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012 0016 9 UNASSIGNED RESERVED 001 UNINITIALIZED INTERRUPT 5030000 us 0020 10 UNASSIGNED RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 512 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR 8040000 aes eee 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002 16 6 INTERRU
325. are logic uses only the most significant bits to match an address within a block The value of the base address must be an integer multiple of the block size Base address register diagrams show how base register bits correspond to address lines BLKSZ 2 0 Block Size Field This field determines the size of the block that is enabled by the chip select Table D 12 shows bit encoding for the base address registers block size field Table D 12 Block Size Field Bit Encoding BLKSZ 2 0 Block Size Address Lines Compared 000 2 Kbytes ADDR 23 11 001 8 Kbytes ADDR 23 13 010 16 Kbytes ADDR 23 14 011 64 Kbytes ADDR 23 16 100 128 Kbytes ADDR 23 17 101 256 Kbytes ADDR 23 18 110 512 Kbytes ADDR 23 19 111 512 Kbytes ADDR 23 20 NOTES 1 ADDR 23 20 are the same logic level as ADDR19 during normal operation D 2 20 Chip Select Option Register Boot CSORBT Chip Select Option Register Boot YFFA4A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE BYTE 1 0 R W L 0 STRB DSACKI 3 0 1 0 2 01 AVEC RESET 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 D 2 21 Chip Select Option Registers CSOR 0 10 Chip Select Option Registers 76 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE BYTE 1 0 R W 1 0 STRB DSACK 3 0 1 0 IP L 2 0 AVEC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER SUMMARY M68HC16 Z SERIES D 18 USER S MANUAL For More Information On Thi
326. at determines the logic level for each bit time This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter A receive time clock is used to control sampling and synchronization Data is shifted into the receive serial shifter according to the most recent synchronization of the re ceive time clock with the incoming data stream From this point on data movement is synchronized with the MCU system clock Operation of the receiver state machine is detailed the QSM Reference Manual QSMRM AD The number of bits shifted in by the receiver depends on the serial format However all frames must end with at least one stop bit When the stop bit is received the frame is considered to be complete and the received data in the serial shifter is transferred to RDR The receiver data register flag RDRF is set when the data is transferred Noise errors parity errors and framing errors can be detected while a data stream is being received Although error conditions are detected as bits are received the noise flag NF the parity flag PF and the framing error FE flag in SCSR are not set until data is transferred from the serial shifter to RDR QUEUED SERIAL MODULE M68HC16 Z SERIES 9 28 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc RDRF must be cleared before the next transfer from th
327. ata latch and if any pin in the corresponding port is configured as an output the value stored for that bit is driven out on the pin A read of a data register returns the value at the pin only if the pin is configured as a discrete input Otherwise the value read is the value stored in the register Both data registers can be accessed in two locations and can be read or written at any time 5 11 Factory Test The test submodule supports scan based testing of the various MCU modules It is in tegrated into the SIM to support production test Test submodule registers are intend ed for Freescale use only Register names and addresses are provided in APPENDIX D REGISTER SUMMARY to show the user that these addresses are occupied The QUOT pin is also used for factory test M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 71 Go to www freescale com Freescale Semiconductor Inc SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 72 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 6 STANDBY RAM MODULE The standby RAM SRAM module consists of a fixed location control register block and an array of fast two clock static RAM that may be mapped to a user specified location in the system memory map Array size depends on the M68HC16 M68CK16 and 68 16 Z series version Refer to Table 6 1 for appropriate SRAM array size
328. ate Baud rate is selected by writing a value from two to 255 into SPBR 7 0 in the SPCR of the master MCU Writing an SPBR 7 0 value into the SPCR of the slave device has no effect The SPI uses a modulus counter to derive SCK baud rate from the MCU sys tem clock The following expressions apply to SCK baud rate fs ys SCK Baud Rate zs O Or fsys SPBRI7 0 2 x SCK Baud Rate Desired Giving SPBR 7 0 a value of zero or one disables the baud rate generator SCK is dis abled and assumes its inactive state value SPBR 7 0 has 254 active values Table 10 4 lists several possible baud values and the corresponding SCK frequency based on a 16 78 MHz system clock Table 10 4 SCK Frequencies System Clock Required Division Frequency Ratio 16 78 MHz 4 19 MHz 2 10 MHz 1 05 MHz 493 kHz 100 kHz 33 kHz Value of SPBR Actual SCK Frequency 10 3 6 Wired OR Open Drain Outputs Typically bus outputs are not open drain unless multiple masters are in the system If needed the WOMP bit in SPCR can be set to provide wired OR open drain outputs An external pull up resistor should be used on each output line WOMP af fects all SPI pins regardless of whether they are assigned to the SPI or used as gen eral purpose 10 3 7 Transfer Size and Direction The SIZE bit in the SPCR selects a transfer size of eight SIZE 0 or sixteen SIZE 1 bits The LSBF bit in the SPCR determines whether
329. ay is required 5 0 Frequency Control Counter The Y field controls the modulus down counter in the synthesizer feedback loop caus ing it to divide by a value of Y 1 VCO relock delay is required EDIV E Clock Divide Rate 0 frequency is system clock divided by eight 1 ECLK frequency is system clock divided by sixteen SLOCK Synthesizer Lock Flag 0 VCO is enabled but has not locked 1 VCO has locked on the desired frequency or VCO is disabled The MCU remains in reset until the synthesizer locks but SLOCK does not indicate synthesizer lock status until after the user first writes to SYNCR STSIM Stop Mode SIM Clock 0 When LPSTOP is executed the SIM clock is driven from the external crystal oscillator and the VCO is turned off to conserve power 1 When LPSTOP is executed the SIM clock is driven from the internal VCO STEXT Stop Mode External Clock 0 When LPSTOP is executed the CLKOUT signal is held negated to conserve power 1 When LPSTOP is executed and EXOFF 1 in SIMCR the CLKOUT signal is driven from the SIM clock as determined by the state of the STSIM bit D 2 4 Reset Status Register RSR Reset Status Register YFFA06 15 8 7 6 5 4 3 2 1 0 NOT USED EXT POW SW HLT 0 RSVD SYS TST RSR contains a status bit for each reset source in the MCU RSR is updated when the MCU comes out of reset A set bit indicates what type of reset occurred If multiple sources assert reset
330. be fetched from internal RAM or from external ROM enabled by the CSBOOT signal C The CPU16 begins fetching instructions pointed to by the initial PK PC 5 7 10 Reset Status Register The reset status register RSR contains a bit for each reset source in the MCU When a reset occurs a bit corresponding to the reset type is set When multiple causes of reset occur at the same time more than one bit in RSR may be set The reset status register is updated by the reset control logic when the RESET signal is released Refer to APPENDIX D REGISTER SUMMARY M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 57 Go to www freescale com Freescale Semiconductor Inc 5 8 Interrupts Interrupt recognition and servicing involve complex interaction between the SIM the CPU16 and a device or module requesting interrupt service This discussion provides an overview of the entire interrupt process Chip select logic can also be used to re spond to interrupt requests Refer to 5 9 Chip Selects for more information 5 8 1 Interrupt Exception Processing The CPU16 handles interrupts as a type of asynchronous exception An exception is an event that preempts normal processing Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an excep tion Each exception has an assigned vector that points to an associated handler rou tine These
331. be used alone or in conjunction with background debug mode M68HC16 Z series MCUs have only one source and type of breakpoint This is a hard ware breakpoint initiated by assertion of the BKPT input Other modular microcontrol lers may have more than one source or type The breakpoint acknowledge cycle discussed here is the bus cycle that occurs as a part of breakpoint exception process ing when a breakpoint is initiated while background debug mode is not enabled BKPT is sampled on the same clock phase as data BKPT is valid the data is tagged as it enters the CPU16 pipeline When BKPT is asserted while data is valid during an instruction prefetch the acknowledge cycle occurs immediately after that instruction has executed When BKPT is asserted while data is valid during an operand fetch the acknowledge cycle occurs immediately after execution of the instruction during which it is latched If BKPT is asserted for only one bus cycle and a pipe flush occurs before BKPT is detected by the CPU16 no acknowledge cycle occurs To ensure detection BKPT should be asserted until a breakpoint acknowledge cycle is recognized When BKPT assertion is acknowledged by the CPU16 the MCU performs a word read from CPU space address 00001E This corresponds to the breakpoint number field ADDR 4 2 and the type bit T being set to all ones source 7 type 1 If this bus cycle is terminated by BERR or by DSACK the MCU performs breakpoint excep
332. bits and operating mode enable bits The CPU16 can read and write this register at any time The SCI can modify the RWU bit under certain circumstances Changing the value of SCI control bits during a transfer may disrupt operation Before changing register values allow the SCI to complete the current transfer then disable the receiver and transmitter 10 4 1 2 SCI Status Register The SCSR contains flags that show operating conditions These flags are cleared either by SCI hardware or by a read write sequence To clear SCI transmitter flags read the SCSR and then write to the SCDR To clear SCI receiver flags read the SCSR and then read the SCDR A long word read can consecutively access both the SCSR and the SCDR This action clears receiver status flag bits that were set at the time of the read but does not clear TDRE or TC flags If an internal SCI signal for setting a status bit comes after the CPU has read the as serted status bits but before the CPU has written or read the SCDR the newly set sta tus bit is not cleared The SCSR must be read again with the bit set and the SCDR must be written to or read before the status bit is cleared Reading either byte of the SCSR causes all 16 bits to be accessed and any status bit already set in either byte will be cleared on a subsequent read or write of the SCDR 10 4 1 3 SCI Data Register The SCDR contains two data registers at the same address The RDR is a read only registe
333. bits SPE and MSTR may be restored to their original set state during this clearing sequence or after the MODF bit has been cleared Hardware does not allow the user to set the SPE and MSTR bits while MODF is a logic one except during the proper clearing sequence AON MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 12 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 4 Serial Communication Interface SCI The SCI submodule contains two independent SCI systems Each is a full duplex uni versal asynchronous receiver transmitter UART This system is fully compatible with SCI systems found on other Freescale devices such as the M68HC11 and M68HCO05 families The SCI uses a standard non return to zero NRZ transmission format An on chip baud rate generator derives standard baud rate frequencies from the MCU oscillator Both the transmitter and the receiver are double buffered so that back to back char acters can be handled easily even if the CPU is delayed in responding to the comple tion of an individual character The SCI transmitter and receiver are functionally independent but use the same data format and baud rate Figure 10 5 shows a block diagram of the SCI transmitter Figure 10 6 shows a block diagram of the SCI receiver The two independent SCI systems are called SCIA and SCIB These SCls are identi cal in register set and hardware configurat
334. ble 0 11 for CSPAR1 reset state information CSPAR 1 contains five 2 bit fields that determine the functions of corresponding chip select pins Bits 15 10 are not used These bits always read zero writes have no ef fect Table D 10 shows CSPAR 1 pin assignments including alternate functions that can be enabled by data bus mode selection during reset REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com D 16 Freescale Semiconductor Inc Table 0 10 CSPAR1 Pin Assignments 1 Field Chip Select Signal Alternate Signal Discrete Output 10 0 CS10 ADDR23 ECLK CS9PA 1 0 ADDR22 CS8PA 1 0 ADDR21 CS7PA 1 0 C57 ADDR20 PC4 CS6PA 1 0 CS6 ADDR19 PC3 NOTES 1 On the CPU16 ADDR 23 20 follow the logic state of ADDR19 unless externally driven The reset state of DATA 7 3 determines whether pins controlled by CSPAR 1 are ini tially configured as high order address lines or chip selects Table D 11 shows the correspondence between DATA 7 3 and the reset configuration of CS 10 6 ADDR 23 19 This register may be read or written at any time After reset software may enable one or more pins as discrete outputs Table D 11 Reset Pin Function of CS 10 6 Data Bus Pins at Reset Chip Select Address Bus Pin Function CS10 CS9 CS8 CS7 CS6 DATAS 4 DATAS ADDR23 ADDR22 ADDR21 ADDR20
335. ble 0 21 shows the MRM address map The reset states shown for the MRM registers are for the generic blank ROM ver sions of the device Several MRM register bit fields can be user specified on a custom masked ROM device Contact a Freescale sales representative for information on or dering a custom ROM device Table D 21 MRM Address Map Address 15 0 YFF820 Masked ROM Module Configuration Register MRMCR YFF822 Not Used YFF824 ROM Array Base Address Register High ROMBAH YFF826 ROM Array Base Address Register Low ROMBAL YFF828 Signature Register High SIGHI YFF82A Signature Register Low SIGLO YFF82C Not Used YFF82bE Not Used YFF830 ROM Bootstrap Word 0 ROMBSO YFF832 ROM Bootstrap Word 1 ROMBS1 YFF834 ROM Bootstrap Word 2 ROMBS2 YFF836 ROM Bootstrap Word 3 ROMBS3 YFF838 Not Used YFF83A Not Used YFF83C Not Used YFF83E Not Used D 4 1 Masked ROM Module Configuration Register MRMCR Masked ROM Module Configuration Register YFF820 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STOP 0 0 BOOT LOCK EMUL ASPC 1 0 WAIT 1 0 NOT USED RESET DATA14 0 0 1 0 0 1 1 1 1 STOP Low Power Stop Mode Enable The reset state of the STOP bit is the complement of DATA14 state during reset The ROM array base address cannot be changed unless the STOP bit is set 0 ROM array operates normally 1 ROM array operates in low power stop mode The ROM array cannot be read i
336. branch or Equal to Zero BGND Enter Background If BDM enabled Debug Mode begin debug else illegal instruction trap BGT Branch if Greater Than If Z 0 branch BE rr 6 2 Zero BHI Branch if Higher If C Z 0 branch REL8 B2 rr 6 2 BITA Bit Test A M IND8 49 ff 6 A 0 IND8 Y 59 ff 6 IND8 Z 69 ff 6 IMM8 79 ii 2 IND16 X 1749 999g 6 IND16 Y 1759 999g 6 IND16 Z 1769 9999 6 1779 hh Il 6 2749 6 2759 6 E Z 2769 6 M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL 4 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV N Z V C BITB Bit Test B IND8 X 6 0 IND8 Y 6 IND8 2 6 IMM8 2 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 6 Y 6 2 6 BLE Branch if Less Than or If Z N V 1 branch REL8 BF rr 6 2 Equal to Zero BLS2 Branch if Lower or If C Z 1 branch Same BLT Branch if Less Than If N 6 V 1 branch Zero BM Branch if Minus If N 1 branch BNE Branch if Not Equal If Z 0 branch BPL Branch if Plus If N 0 branch BRA Branch Always If 1 2 1 branch BRCLR Branch if Bit s Clear If M Mask 0 bran
337. by accessing the PAIS and PCLKS bits in the pulse accumulator control register PACTL Pulse width modulation A and B PWMA B output pins can serve as general purpose outputs The force PWM value FPWMx and the force logic one F1x bits in the com pare force PWM control PWMC registers respectively control their operation 11 7 Prescaler Capture compare and PWM units have independent 16 bit free running counters as a main timing component These counters derive their clocks from the prescaler or from the PCLK input Figure 11 2 is a prescaler block diagram GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SYSTEM CLOCK DIVIDER TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR m CPR2 CPRIICPRO 256 128 e 64 TO CAPTURE 32 COMPARE 16 SELECT o EA e 8 4 e EXT 128 x PWM UNIT SELECT PCLK SYNCHRONIZER AND EE DIGITAL FILTER PPR2 PPRI PPRO Figure 11 2 Prescaler Block Diagram GPT PRE BLOCK In the prescaler the system clock is divided by a nine stage divider chain Prescaler outputs equal to system clock divided by 2 4 8 16 32 64 128 256 and 512 are pro vided Connected to these outputs are two multiplexers one for the capture compare unit the other for the PWM unit Multiplexers can each select on
338. c Shift Left E Arithmetic Shift Left AM Arithmetic Shift Left IND16 X Word d IND16 Y IND16 Z EXT Arithmetic Shift Right IND8 X D IND8 Y L LLL dH IND8 Z IND16 X IND16 Y IND16 Z EXT CO CENTRAL PROCESSING UNIT M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV N Z VI C ASRA Arithmetic Shift Right ASRB Arithmetic Shift Right ASRD Arithmetic Shift Right D ASRE Arithmetic Shift Right ASRM Arithmetic Shift Right ASRW Arithmetic Shift Right IND16 X Word IND16 Y IND16 Z EXT 2 REL BCC Branch if Carry Clear If C 0 branch 8 BCLR Clear Bit s Mask IND8 8 A 0 IND8 Y 8 IND8 Z 8 ND16 X 8 ND16 Y 8 ND16 Z 8 EXT mm hh Il 8 BCLRW Clear Bit s in a Word 1 Mask 016 X 9090 10 LL LEE ME E M M 1 mmmm ND16 Y 0099 10 mmmm ND16 Z 9999 mmmm EXT hh Il mmmm BCS Branch if Carry Set If C 1 branch REL8 rr Branch if Equal If Z 1 branch REL8 BGE Branch if Greater Than If N 6 V 0
339. cale com Freescale Semiconductor Inc Table A 21 20 97 MHz Background Debug Mode Timing Vpp and 9 0 5 Vo 0 T to Characteristic Symbol Min Max Unit BO DSI Input Setup Time tpsisu ns B1 DSI Input Hold Time ipsis ns B2 DSCLK Setup Time tpscsu 15 ns B3 DSCLK Hold Time ipscH ns B4 DSO Delay Time incon ns B5 DSCLK Cycle Time tpsccvc 2 6 CLKOUT High to FREEZE Asserted Negated tERZAN ns B7 CLKOUT High to IPIPE1 High Impedance m ns B8 High to IPIPE1 Valid tir EE 50 ns B9 DSCLK Low Time tpscLo lcyc 10 IPIPE1 High Impedance to FREEZE Asserted B11 FREEZE Negated to IPIPE 0 1 Active TBD NOTES 1 All AC timing is shown with respect to Vj Vj_ levels unless otherwise noted Table A 22 25 17 MHz Background Debug Mode Timing Vip 5 0 5 Vo 0 T T to Tl Num Characteristic Unit BO DSI Input Setup Time ns B1 DSI Input Hold Time ns B2 DSCLK Setup Time tpscsu ns B3 DSCLK Hold Time tpscH ns B4 DSO Delay Time tpsop ns B5 DSCLK Cycle Time tpsccvc lcyc B6 CLKOUT High to FREEZE Asserted Negated teERZAN ns B7 CLKOUT High to IPIPE1 High Impedance ns B8 High to IPIPE1 Valid ns B9 DSCLK Low Time B10 IPIPE1 High Impedance to FREEZE Asserted B11 FREEZE Negated to IPIPE 0 1
340. cale com Freescale Semiconductor Inc D 8 General Purpose Timer Table D 42 GPT Address Map Address 15 YFF900 YFF902 YFF904 GPT Module Configuration Register GPTMCR GPT Module Test Register GPTMTR GPT Interrupt Configuration Register ICR Port GP Data Direction Register DDRGP Output Compare 1 Action Mask Register 1 Timer Counter Register TCNT Pulse Accumulator Control Register Pulse Accumulator Counter Register PACTL PACNT Timer Input Capture Register 1 TIC1 YFFEO6 YFF908 YFF90A Port GP Data Register PORTGP Output Compare 1 Action Data Register OC1D YFF90C YFF90E YFF910 YFF912 YFF914 Timer Input Capture Register 2 TIC2 Timer Input Capture Register 3 TIC3 Timer Output Compare Register 1 TOC1 YFF916 Timer Output Compare Register 2 TOC2 YFF918 Timer Output Compare Register 3 TOC3 Timer Output Compare Register 4 TOC4 YFF91A YFF91C Timer Control Register 1 TCTL1 Timer Input Capture 4 Output Compare Register 5 TI4 O5 Timer Control Register 2 TCTL2 Timer Mask Register 1 TMSK1 Timer Flag Register 1 TFLG1 YFF91E YFF920 Timer Mask Register 2 TMSK2 Timer Flag Register 2 TFLG2 YFF922 YFF924 Compare Force Register CFORC PWM Control Register A PWMA PWM Control Register C PWMC PWM Control Register B PWMB YFF926 YFF928 PWM Buffer Register A
341. caler PCLK Select Field This field selects one of seven prescaler taps or PCLK to be TCNT input Refer to Ta ble D 48 Table D 48 CPR 2 0 Prescaler Select Field CPR 2 0 System Clock Divide By Factor 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 PCLK M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 73 Go to www freescale com Freescale Semiconductor Inc D 8 13 Timer Interrupt Flag Registers 1 and 2 TFLG1 TFLG2 Timer Interrupt Flag Registers 1 2 YFF922 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 05F OCF 4 1 ICF 3 1 TOF 0 PAIF 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 These registers show condition flags that correspond to GPT events If the corre sponding interrupt enable bit in TMSK1 TMSK is set an interrupt occurs I4 O5F Input Capture 4 Output Compare 5 Flag When 14 O5 in PACTL is zero this flag is set each time TCNT matches the TOC5 val ue in TI4 O5 When 14 O5 in PACTL is one the flag is set each time a selected edge is detected at the 14 05 pin OCF 4 1 Output Compare Flags An output compare flag is set each time TCNT matches the corresponding TOC reg ister OCF 4 1 correspond to 4 1 ICF 3 1 Input Capture Flags A flag is set each time a selected edge is detected at the corresponding input capture pin ICF 3 1 correspond to IC 3 1 TOF Timer Overflow Flag This flag is set ea
342. ce manual 10 1 registers Go to www freescale com Freescale Semiconductor Inc data direction register MDDR 10 4 global registers data direction register DDRM D 58 data direction register MDDR 10 2 interrupt vector register MIVR 10 2 D 56 module configuration register MMCR 10 2 D 54 pin control registers pin assignment register MPAR 10 2 D 57 port data register PORTMO 10 2 D 59 pin state register PORTMCP 10 2 D 59 SCI interrupt level register ILSCI 10 2 D 55 SPI interrupt level register ILSPI 10 2 D 56 test register MTEST 10 2 D 55 pin assignment register MPAR 10 4 SCI control register 0 SCCROA B 10 13 D 59 control register 1 SCCR1A B 10 16 0 60 data register SCDRA B 10 16 D 63 status register SCSRA B 10 16 D 62 SPI control register SPCR 10 6 D 64 data register SPDR 10 6 D 66 status register SPSR 10 6 D 65 types 10 2 SCI 10 13 interrupt level ILSCIA B D 55 SPI 10 4 MCU 132 pin assignment package MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 3 7 2 MC68HC162Z4 CKZ4 3 9 B 3 144 pin assignment package MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 3 8 B 5 68 1674 74 3 10 B 6 address maps MC68HC16Z1 CKZ1 CMZ1 3 17 68 1 622 43 3 18 MC68HC16Z4 CKZA 3 18 basic system 5 30 block diagram MC68HC16Z1 CKZ1 CMZ1 3 4 68 1672 23 3 5 MC68HC16Z4 CKZA 3 6 components 1 1 overview 1 1 personality board MPB C 2 pin characteristics 3 11 power connections 3 13 signal characteristics
343. ce or the pin can be tied low and the CPU16 generates an autovector number corresponding to interrupt priority 4 The bus monitor asserts BERR and the CPU16 generates the spurious in terrupt vector number F The vector number is converted to a vector address G The content of the vector address is loaded into the PC and the processor transfers control to the exception handler routine 5 8 5 Interrupt Acknowledge Bus Cycles Interrupt acknowledge bus cycles are CPU space cycles that are generated during ex ception processing For further information about the types of interrupt acknowledge bus cycles determined by AVEC or DSACK refer to APPENDIX A ELECTRICAL CHARACTERISTICS and the S M Reference Manual SIMRM AD 5 9 Chip Selects Typical microcontrollers require additional hardware to provide external chip select signals The MCU includes 12 programmable chip select circuits that can provide from two to 16 clock cycle access to external memory and peripherals Address block sizes of 2 Kbytes to 512 Kbytes can be selected However because ADDR 23 20 follow the state of ADDR19 512 Kbyte blocks are the largest usable size Figure 5 21 is a dia gram of a basic system that uses chip selects M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 61 to www freescale com Freescale Semiconductor Inc Vpp Vpp Vpp Vpp Vpp Vpp 10ko wko 0 8 1002 10 8
344. ceiver clears RWU and wakes up The receiver waits for the first frame of the next transmission The byte is received normally transferred to the RDR and the RDRF flag is set If software does not recognize the address it can set RWU and put the receiver back to sleep For idle line wake up to work there must be a min imum of one frame of idle line between transmissions There must be no idle time be tween frames within a transmission Address mark wake up uses a special frame format to wake up the receiver When the MSB of an address mark frame is set that frame contains address information The first frame of each transmission must be an address frame When the MSB of a frame is set the receiver clears RWU and wakes up The byte is received normally trans ferred to the RDR and the RDRF flag is set If software does not recognize the ad dress it can set RWU and put the receiver back to sleep Address mark wake up allows idle time between frames and eliminates idle time between transmissions How ever there is a loss of efficiency because of an additional bit time per frame 10 4 5 9 Internal Loop The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter When LOOPS is set the SCI transmitter output is fed back into the receive serial shifter TXD is asserted idle line Both transmitter and receiver must be enabled before entering loop mode MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 22 USER S MANU
345. cel snc tte cele sey eel eel onn in cb n H H H H H H H H H H H H H H H H H H H FO Cy CX aaa a aa ae Aaa A G aa Aa a CX O O0 a O A A AAA Aa aA aA Aa AAA a Aaa Aa a Aa a a a HMM MH HH MH MH MH HHH MH MH MH MH MH MH MH MH HHH MH MH MH HHH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MH MN MH MM 2 D 2 D 2 2 D 2 2 D 2 gt gt 2 OC OD s LO SO O CO c4 CN OO SO CO c4 CN OO FM OM ODO XO 000 0 c CN 0 SO c4 CN OO 1 SO CO CO CO CO CCC cd c c c c c oc oc c CC CN CN CN CN CN CN CN CN r 000000000000000000000 O1 OY OY OY OY OV cH cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd cd c 36 AA es EX 2h Y AG Cs Ae 24 EY EY As QAO As TY Os As OQ AQ EY a
346. ch IND8 Y IND8 Z IND16 X IND16 Y IND16 Z BRN Branch Never If 1 2 0 branch BRSET Branch if Bit s Set If M Mask 0 branch IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT mm hh II rrr BSET Set Bit s IND8 X 8 A 0 A IND8 Y mm ff 8 IND8 Z mm ff 8 ND16 X mm 9999 8 ND16 Y mm gggg 8 ND16 Z mm 9999 8 EXT mm hh II 8 BSETW Set Bit s in Word M M 1 Mask ND16 X 9999 10 0 A gt 1 mmmm ND16 Y 9090 10 mmmm ND16 Z 9999 hh Il mmmm CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S 1 7 BSR Branch to Subroutine PK PC 2 PK PC 36 rr 10 Push PC SK SP 2 gt SK SP Push CCR SK SP 2 SK SP PK PC Offset 2 PK PC BVC2 Branch if Overflow If V 0 branch REL8 Clear 52 Branch if Overflow Set If V 1 branch REL8 CBA Compare A to B A B INH 2 A CLR Clear a Byte in 00 2 M IND8 X 4 4 0 1 0 0 Memory IND8 Y 4 IND8 Z 4 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 CLRA Clear A 00 A INH 305 2 E 0 0 CLRB Clear B 00 B INH 315 2
347. ch time TCNT advances from a value of FFFF to 0000 PAOVF Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of FF to 00 PAIF Pulse Accumulator Flag In event counting mode this flag is set when an active edge is detected on the PAI pin In gated time accumulation mode it is set at the end of the timed period D 8 14 Compare Force Register PWM Control Register C CFORC Compare Force Register PWM Control Register YFF924 15 10 9 8 1 6 4 3 2 1 0 FOC 0 FPWMA FPWMB PPROUT PPR SFA SFB F1B RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting a bit in CFORC causes a specific output on OC or PWM pins PWMC sets PWM operating conditions REGISTER SUMMARY M68HC16 Z SERIES D 74 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc FOC 5 1 Force Output Compare FOC 5 1 correspond to OC 5 1 0 Has no effect 1 Causes pin action programmed for corresponding OC pin but the OC flag is not set FOC 5 1 correspond to OC 5 1 FPWMA B Force PWM Value 0 PWM is used for PWM functions normal operation 1 PWM pin is used for discrete output The value of the F1A B bit will be driv en out on the PWMA B pin This is true for PWMA regardless of the state of the PPROUT bit PPROUT PWM Clock Output Enable 0 Normal PWM operation on PWMA 1 Clock selected by PP
348. ck Control Timing Vpp and VDDSYN 5 0 5 Vss 0 to Ty Characteristic PLL Reference Frequency Range 68 1671 20 68 1672 3 2 MC68HC16Z3 3 2 System Frequency On Chip PLL System Frequency Slow On Chip PLL System Frequency 4 fret Fast On Chip PLL System Frequency 4 128 External Clock Operation dc PLL Lock Time 8 9 Changing W or Y in SYNCR or exiting from LPSTOP Warm Start Up Cold Start Up fast reference option only VCO Frequency Limp Mode Clock Frequency SYNCR X bit 0 SYNCR X bit 1 CLKOUT 7 8 10 Short term 5 us interval Long term 500 us interval NOTES 1 The base configuration of the MC68HC16Z1 MC68CK16Z1 MC68HC16Z4 and the 68 16274 requires a 32 768 kHz crystal reference The base configuration of the MC68CM16Z1 M68HC16Z2 and the MC68HC1623 requires a 4 194 MHz crystal reference 2 All internal registers retain data at 0 Hz 3 Assumes that Vppsyw and Vpp are stable that an external filter is attached to the XFC pin and that the crystal oscillator is stable 4 Assumes that Vppsyn is stable that an external filter is attached to the XFC pin and that the crystal oscillator is stable followed by Vpp ramp up Lock time is measured from Vpp at specified minimum to RESET negated 5 Cold start is measured from Vppsyn and Vpp at specified minimum to RESET negated 6 Internal VCO frequency fyco
349. complement number for positive input bit 15 equals zero for negative input bit 15 equals one Bits 5 0 always return zero when read Signed left justified format Conversion result is unsigned left justified data Bits 15 6 are used for 10 bit resolution bits 15 8 are used for 8 bit conversion bits 7 6 are zero Bits 5 0 always return zero when read Unsigned left justified format Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration 8 8 Pin Considerations The ADC requires accurate noise free input signals for proper operation The follow ing sections discuss the design of external circuitry to maximize ADC performance 8 8 1 Analog Reference Pins No A D converter can be more accurate than its analog reference Any noise in the reference can result in at least that much error in a conversion The reference for the ADC supplied by pins Vay and Vg should be low pass filtered from its source to ob tain a noise free clean signal In many cases simple capacitive bypassing may suf fice In extreme cases inductors or ferrite beads may be necessary if noise or RF energy is present Series resistance is not advisable since there is an effective DC cur rent requirement from the reference voltage by the internal resistor string in the RC DAC array External resistance may introduce error in this architecture under certain conditions Any series devices in the filter network should contain a mi
350. cremented or decremented by word address it is possible to push and pull byte sized data Setting the stack pointer to an odd value causes data misalignment which reduces performance 4 2 4 Program Counter The CPU16 program counter PC is 16 bits wide An associated 4 bit extension field PK provides 20 bit program addressing CPU16 instructions are fetched from even word boundaries Address line 0 always has a value of zero during instruction fetches to ensure that instructions are fetched from word aligned addresses M68HC16 Z SERIES CENTRAL PROCESSOR UNIT USER S MANUAL For More Information On This Product 4 3 Go to www freescale com Freescale Semiconductor Inc 4 2 5 Condition Code Register The 16 bit condition code register is composed of two functional blocks The eight MSB which correspond to the CCR on the M68HC11 contain the low power stop con trol bit and processor status flags The eight LSB contain the interrupt priority field the DSP saturation mode control bit and the program counter address extension field Figure 4 2 shows the condition code register Detailed descriptions of each status in dicator and field in the register follow the figure 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 MV H EV N 2 2 0 5 PK 3 0 Figure 4 2 Condition Code Register S STOP Enable 0 Stop clock when LPSTOP instruction is executed 1 Perform NOP when LPSTOP instruction is executed MV Accumula
351. crystal reference maximum fsys 1 mA 14 External clock maximum fsys IppsvN 5 mA LPSTOP crystal reference VCO off STSIM 0 150 Vpp powered down 100 MC68HC16Z2 Z3 Supply Current 1 13 VCO on crystal reference maximum fsys m 2 mA 14A External clock maximum fsys IDDSYN 7 mA LPSTOP crystal reference VCO off STSIM 0 2 mA Vpp powered down 2 mA RAM Standby Voltage 15 Specified Vpp applied Vsp 0 0 5 5 V Vpp Vss 3 0 5 5 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 12 For More Information On This Product USER S MANUAL Go to www freescale com Table 12 16 78 MHz DC Characteristics Continued Vip and Vppsyy 5 0 Vdc 10 Veg 0 T T to T Freescale Semiconductor Inc DDSYN Characteristic 14 Transient condition Standby operation 4 MC68HC16Z1 RAM Standby Current Normal RAM operation Transient condition Standby operation MC68HC16Z2 Z3 RAM Standby Current Normal RAM operation MC68HC16Z1 Power Dissipation Vpp gt Vsp 0 5V Vsp 0 5V2 Vpp 2 Vas 0 5V lt Vss 0 5V Vpp gt Vsp 0 5V Vsp 0 5 gt Vpp 2 Vss 0 5V Vpp Vss 0 5V MC68HC16Z2 Z3 Power Dissipation Pp Input Capacitance 13 1 18 All input only pins except ADC pins Cin 20 pF All input output pins Load Capacitance Group 1 I O Pins CLKOUT FREEZE QUOT IPIPEO 90 19 Group 2 I O Pins CSBOOT BG CS CL 100
352. ct Option Address Register 3 CSOR3 YFFA5C Chip Select Base Address Register 4 CSBAR4 YFFASE Chip Select Option Address Register 4 CSOR4 YFFA60 Chip Select Base Address Register 5 CSBARS5 YFFA62 Chip Select Option Address Register 5 CSORS5 YFFA64 Chip Select Base Address Register 6 CSBAR6 YFFA66 Chip Select Option Address Register 6 CSOR6 YFFA68 Chip Select Base Address Register 7 CSBAR7 YFFAGA Chip Select Option Address Register 7 CSOR7 YFFA6C Chip Select Base Address Register 8 CSBAR8 YFFAGE Chip Select Option Address Register 8 CSOR8 YFFA70 Chip Select Base Address Register 9 CSBAR9 YFFA72 Chip Select Option Address Register 9 CSOR9 YFFA74 Chip Select Base Address Register 10 CSBAR10 YFFA76 Chip Select Option Address Register 10 CSOR10 YFFA78 Not Used YFFA7A Not Used YFFA7C Not Used YFFA7E Not Used NOTES 1 Y M111 where M is the logic state of the module mapping MM bit in the SIMCR M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 2 1 SIM Module Configuration Register SIMCR SIM Module Configuration Register 15 14 B 11 10 9 8 7 6 5 4 3 2 1 0 EXOFF FRZSW 0 RSVD 0 sHEN LO supv MM 0 0 IARB 3 0 ESET 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 NOTES 1 This bit must be left at zero Pulling DATA11 high during reset ens
353. ctivity may not stop at the next cycle boundary Occurrence of a bus error while HALT is asserted causes the CPU16 to pro cess a bus error exception When the MCU completes a bus cycle while the HALT signal is asserted the data bus goes into a high impedance state and the AS and DS signals are driven to their inac tive states Address function code size and read write signals remain in the same state M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 45 to www freescale com Freescale Semiconductor Inc The halt operation has no effect on bus arbitration However when external bus arbi tration occurs while the MCU is halted address and control signals go into a high im pedance state If HALT is still asserted when the MCU regains control of the bus address function code size and read write signals revert to the previous driven states The MCU cannot service interrupt requests while halted 5 6 6 External Bus Arbitration The MCU bus design provides for a single bus master at any one time Either the MCU or an external device can be master Bus arbitration protocols determine when an ex ternal device can become bus master Bus arbitration requests are recognized during normal processing HALT assertion and when the CPU has halted due to a double bus fault The bus controller in the MCU manages bus arbitration signals so that the MCU has the lowest priority Ex
354. cution Unit The execution unit evaluates opcodes interfaces with the microsequencer to advance instructions through the pipeline and performs instruction operations M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 35 Go to www freescale com Freescale Semiconductor Inc 4 11 Execution Process Fetched opcodes are latched into stage A then advanced to stage B Opcodes are evaluated in stage B The execution unit can access operands in either stage A or stage B stage B accesses are limited to 8 bit operands When execution is complete opcodes are moved from stage B to stage C where they remain until the next instruc tion is complete A prefetch mechanism in the microsequencer reads instruction words from memory and increments the program counter When instruction execution begins the program counter points to an address six bytes after the address of the first word of the instruc tion being executed The number of machine cycles necessary to complete an execution sequence varies according to the complexity of the instruction Refer to the CPU16 Reference Manual CPU16RM AD for details 4 11 1 Changes in Program Flow When program flow changes instructions are fetched from a new address Before ex ecution can begin at the new address instructions and operands from the previous in struction stream must be removed from the pipeline If a change in flow is temporary a return
355. d CS Delay tecsp ns E4 ECLK Low to CS Hold tecsH 10 ns E5 5 Negated Width tECSN 25 ns E6 Read Data Setup Time tEDSR 25 ns E7 Read Data Hold Time tEDHR 5 ns E8 ECLK Low to Data High Impedance tEDuz ns E9 5 Negated to Data Hold Read tECDH 0 ns E10 CS Negated to Data High Impedance tecpz teyc E11 ECLK Low to Data Valid Write EDD 58 E12 Low to Data Hold Write tepHw 10 ns E13 CS Negated to Data Hold Write tecHw 0 ns E14 Address Access Time Read tEACC ns E15 Chip Select Access Time Read tEACS ns E16 Address Setup Time teas teyc NOTES 1 Refer to notes in Table A 26 A 42 ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 26 25 17 MHz ECLK Bus Timing and 5 0 5 Vos 0 Vdc T to TM Num Characteristic Symbol Min Max Unit E1 ECLK Low to Address Valid tEAD 40 ns Low to Address Hold ien ns E3 ECLK Low to CS Valid CS Delay tecsp ns E4 ECLK Low to CS Hold 1 5 10 ns E5 CS Negated Width tECSN 20 ns E6 Read Data Setup Time tEDSR 25 ns E7 Read Data Hold Time tEDHR 5 ns E8 ECLK Low to Data High Impedance tEDuz ns E9 5 Negated to Data Hold Read tECDH 0 ns E10 CS Negated to Data High Impedance tecpz lcyc E11 ECLK Low to Data Valid Write EDD
356. d as a discrete input Otherwise the value read is the value stored in the register Bits 15 8 are unimplemented and will always read zero D 2 7 Port E Data Direction Register DDRE Port E Data Direction Register YFFA14 15 8 7 6 5 4 3 2 1 0 NOT USED DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 00 1 DDEO RESET 0 0 0 0 0 0 0 0 Bits in this register control the direction of the port E pin drivers when pins are config ured for I O Setting a bit configures the corresponding pin as an output clearing a bit configures the corresponding pin as an input This register can be read or written at any time Bits 15 8 are unimplemented and will always read zero M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 9 Go to www freescale com Freescale Semiconductor Inc NOTE When changing a port E pin from an output to an input the pin will drive high for approximately four milliseconds This ensures that the shared bus control signal will be in a negated state before the pin be comes an input D 2 8 Port E Pin Assignment Register PEPAR Port E Pin Assignment YFFA16 15 8 7 6 5 4 3 2 1 0 NOT USED 5 PEPA4 2 1 PEPAO RESET DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 This register determines the function of port E pins Setting a bit assigns the corre sponding pin to a bus control signal clear
357. d at a logic level one at the rising edge of RESET BDM is disabled Assertion of the BKPT pin or execution of the BKPT instruction will result in normal breakpoint exception processing BDM remains enabled until the next system reset BKPT is relatched on each rising transition of RESET BKPT is internally synchronized and must be held low for at least two clock cycles prior to RESET negation for BDM to be enabled BKPT assertion logic must be designed with special care If BKPT assertion extends into the first bus cycle following the release of RESET the bus cycle could inadvertently be tagged with a breakpoint Refer to 4 14 4 Background Debug Mode and the CPU16 Reference Manual CPU16RM AD for more information on background debug mode Refer to the S M Reference Manual SIMRM AD and APPENDIX A ELECTRICAL CHARACTERIS TICS for more information concerning BKPT signal timing 5 7 4 MCU Module Pin Function During Reset Usually module pins default to port functions and input output ports are set to input state This is accomplished by disabling pin functions in the appropriate control regis ters and by clearing the appropriate port data direction registers Refer to individual module sections in this manual for more information Table 5 20 is a summary of mod ule pin function out of reset Refer to APPENDIX D REGISTER SUMMARY for register function and reset state SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 52 For
358. d at two ADC clocks Resolution time is fixed at ten ADC clocks for an 8 bit con version and twelve ADC clocks for a 10 bit conversion Final sample time is deter mined by the STS 1 0 field Refer to Table D 26 Table D 26 Sample Time Selection STS 1 0 Sample Time 2 ADC Clock Periods 4 ADC Clock Periods 8 ADC Clock Periods 16 ADC Clock Periods PRS 4 0 Prescaler Rate Selection The ADC clock is derived from the system clock by a programmable prescaler ADC clock period is determined by the value of the PRS field in ADCTLO The prescaler has two stages The first stage is a 5 bit modulus counter It divides the system clock by any value from two to 32 PRS 4 0 9600000 to 9611111 The second stage is a di vide by two circuit Refer to Table D 27 M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 31 Go to www freescale com Freescale Semiconductor Inc Table D 27 Prescaler Output Minimum Maximum PRS 4 0 ADC Clock System Clock System Clock 9500000 Reserved 9600001 System Clock 4 2 0 MHz 8 4 MHz 2600010 System Clock 6 3 0 MHz 12 6 MHz 960001 1 System Clock 8 4 0 MHz 16 8 MHz 9611101 System Clock 60 30 0 MHz 9611110 System Clock 62 31 0 MHz 9611111 System Clock 64 32 0 MHz D 5 5 ADC Control Register 1 ADCTL1 ADC Control Register 1 YFF70C 15 7 6 5 4 3 2 1 0 NOT USED SCAN MULT S8CM CD CC CB CA
359. d exter nally during show cycles Show cycles are controlled by the SHEN 1 0 in SIMCR This field is set to 00 by re set When show cycles are disabled the address bus function codes size and read write signals reflect internal bus activity but AS and DS are not asserted externally and external data bus pins are in high impedance state during internal accesses Refer to 5 2 3 Show Internal Cycles and the S M Heference Manual SIMRM AD for more information When show cycles are enabled DS is asserted externally during internal cycles and internal data is driven out on the external data bus Because internal cycles normally continue to run when the external bus is granted one SHEN 1 0 encoding halts inter nal bus activity while there is an external master SIZ 1 0 signals reflect bus allocation during show cycles Only the appropriate portion of the data bus is valid during the cycle During a byte write to an internal address the portion of the bus that represents the byte that is not written reflects internal bus con ditions and is indeterminate During a byte write to an external address the data mul tiplexer in the SIM causes the value of the byte that is written to be driven out on both bytes of the data bus M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 9 47 Go to www freescale com Freescale Semiconductor Inc 5 7 Reset Reset occurs when an active low logic le
360. d is concatenated with the program counter to form a 20 bit address 4 2 6 Address Extension Register and Address Extension Fields There are six 4 bit address extension fields EK XK YK and ZK are contained by the address extension register K PK is part of the CCR and SK stands alone Extension fields are the bank portions of 20 bit concatenated bank byte addresses used in the CPU16 linear memory management scheme All extension fields except EK correspond directly to a register XK YK and ZK extend registers IX IY and IZ PK extends the PC and SK extends the SP EK holds the four MSB of the 20 bit address used by the extended addressing mode 4 2 7 Multiply and Accumulate Registers The multiply and accumulate MAC registers are part of a CPU submodule that per forms repetitive signed fractional multiplication and stores the cumulative result These operations are part of control oriented digital signal processing There are four MAC registers Register H contains the 16 bit signed fractional multipli er Register contains the 16 bit signed fractional multiplicand Accumulator M is a specialized 36 bit product accumulation register XMSK and YMSK contain 8 bit mask values used in modulo addressing The CPU16 has a special subset of signal processing instructions that manipulate the MAC registers and perform signal processing calculations 4 3 Memory Management The CPU16 provides a 1 Mbyte address space There are 16 ban
361. d to BG Asserted tBRAGA 1 toyo 37 Asserted to BG Negated tGAGN 1 2 hee 39 BG Width Negated tau 2 teye 39A BG Width Asserted 1 pese 46 R W Width Asserted Write or Read 150 E ns 46A R W Width Asserted Fast Write or Read Cycle tRwas 90 ns Asynchronous Input Setup Time 47 BGACK 1 0 BERR AVEC HALT 47 Asynchronous Input Hold Time 5 48 DSACK 1 0 Asserted to BERR HALT Asserted 30 ns 53 Data Out Hold from Clock High ns 54 Clock High to Data Out High Impedance 28 ns 55 R W Asserted to Data Bus Impedance Change ns 70 Low to Data Bus Driven Show Cycle tecLDD 30 ns 71 Data Setup Time to Clock Low Show Cycle teci ps ns 72 Data Hold from Clock Low Show Cycle tSCLDH ns 73 Input Setup Time ns 74 Input Hold Time ns 75 Mode Select Setup Time DATA 15 0 MODCLK BKPT pins toc 76 Mode Select Hold Time DATA 15 0 MODCLK BKPT pins ns 77 RESET Assertion 2 tye 78 RESET Rise 3 10 tae 100 CLKOUT High to Phase 1 Asserted 4 tCHP1A 40 ns 101 CLKOUT High to Phase 2 Asserted 4 tCHP2A 40 ns 102 1 Valid to AS or DS Asserted tP1VSN ns 103 2 Valid to AS or DS Negated tpovsn ns 104 ASor DS Valid to Phase 1 Negated tsaPiNn ns 105 AS or DS Negated
362. de Other Initializations LDAB 00 TBXK set XK to bank 0 for STRING access PAOV_CNT EQU 0 counter variable for PAOV_ROUTINE LDAB 501 TBZK LDZ 0000 PAOV CNT will be indexed off ZK IZ LDAB 0A STAB PAOV CNT Z load a 10 into the variable ANDP SFFIF interrupt priority mask level to 0 KKKKK Start of main program KKKKK GO NOP BRA GO Let s loop until we re interrupted Subroutines SEND_STRING EVEN subroutine to send out the entire ASCII string LDAB 0 get next byte in string as pointed to by BEQ STRING_DONE if B 00 then the string is done JSR SEND CH go send out the byte AIX 501 increment IX to point to the next byte BRA SEND STRING loop back and do next byte in string STRING DONE RTS go back to whence we came SEND CH subroutine to send out one byte to SCI LDAA SCSR read SCI status reg to check clear TDRE bit M68HC16 Z SERIES INITIALIZATION AND PROGRAMMING EXAMPLES USER S MANUAL E 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ANDA 501 check only the TDRE flag bit BEQ SEND_CH if TDR is not empty go back to check it again LDAA 500 clear to send a full word to SCDR SFFCOE STD SCDR transmit one ASCII character to the screen TC LOOP LDAB SCSR t 1 ANDB 580 the TC bit transfer complete BEQ TC_LOOP continue to wait until is set RTS
363. des rates from 64 baud to 524 kbaud with a 16 78 MHz system clock Word length of either eight or nine bits is software selectable Optional parity generation and detection provide either even or odd parity check capability Advanced error detection circuitry catches glitches of up to 1 16 of a bit time in duration Wakeup functions allow the CPU to run uninter rupted until meaningful data is received 10 2 MCCI Registers and Address Map The address map occupies 64 bytes from address YFFCOO to YFFCSF It consists of MCCI global registers and SPI and SCI control status and data registers Writes to unimplemented register bits have no effect and reads of unimplemented bits always return zero The MM bit in the system integration module configuration register SIMCR defines the most significant bit ADDR23 of the IMB address for each module Because ADDR 23 20 are driven to the same bit as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible Refer to 5 2 1 Module Mapping for more in formation about how the state of MM affects the system 10 2 1 MCCI Global Registers MCCI module configuration register contains bits and fields to place the MCCI in low power operation establish the privilege level required to access MCCI registers and establish the priority of the MCCI during interrupt arbitration The MCCI test register MTEST is used only during factory test of the MCCI The SCI interru
364. dressing There are one or more addressing modes within each type Table 4 1 shows the addressing modes CENTRAL PROCESSOR UNIT For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table 4 1 Addressing Modes Mnemonic Mode Description Index register X with accumulator E offset Index register Y with accumulator E offset Index register Z with accumulator E offset Extended 20 bit extended 8 bit immediate 16 bit immediate IND8 X Index register X with unsigned 8 bit offset Indexed 8 Bit IND8 Y Index register Y with unsigned 8 bit offset IND8 Z Index register Z with unsigned 8 bit offset IND16 X Index register X with signed 16 bit offset Indexed 16 Bit IND16 Y Index register Y with signed 16 bit offset IND16 Z Index register Z with signed 16 bit offset IND20 X Index register X with signed 20 bit offset IND20 Y Index register Y with signed 20 bit offset IND20 Z Index register Z with signed 20 bit offset INH Inherent Signed 8 bit offset added to index register X after effective address is used 8 bit relative 16 bit relative Accumulator Offset Extended Immediate Indexed 20 Bit Inherent Post Modified Index IXP REL8 REL16 Relative All modes generate ADDR 15 0 This address is combined with ADDR 19 16 f
365. ductor Inc Multichannel communication interface module MCCI See MCCI 10 1 conversion MULT D 32 Multimaster operation 9 9 Multiple channel conversion D 35 exceptions 4 40 Multiplexer 8 4 11 9 channels 8 4 outputs 11 10 Multiply and accumulate MAC 4 45 MV 4 4 D 3 N N 4 4 Negated definition 2 6 Negative flag N 4 4 integers 4 6 stress 8 18 New queue pointer value NEWQP D 50 9 8 9 21 D 50 NF 9 28 10 21 D 44 D 63 Nine stage divider chain 11 9 Noise 8 14 error NF flag 9 28 10 21 D 44 D 63 Non maskable interrupt 5 58 NRZ 9 2 10 2 10 13 11 14 D 70 OC1M 11 14 D 70 5 11 14 OCF D 74 OCI D 73 11 13 1 11 13 OM OL D 72 OP 1 through 3 5 34 Opcode tracking 4 40 breakpoints 4 42 combining with other capabilities 4 41 deterministic 4 40 Operand alignment 5 35 byte order 5 34 misaligned 5 35 transfer cases 5 35 Operators 2 1 OR D 43 D 63 Ordering information B 8 ORGO00000 ASM 6 ORGO00008 ASM 6 Output capture pins 11 7 compare M68HC16 Z SERIES USER S MANUAL For More Information On This Product 1 single comparison operation 11 14 flags OCF D 74 functions 11 13 11 14 interrupt enable OCI bit D 73 mode bits output compare level bits OM OL D 72 status flag OCxF bit 11 13 Overflow flag V 4 4 D 3 Overrun error OR D 43 D 63 Overview information 3 1 PACLK D 71 PACNT 11 14 11 16 D 70 D 71 PACTL 11 8 11
366. dular Microcontroller Family follows the modular construc tion of the devices in the product line Each device has a comprehensive user s man ual that provides sufficient information for normal operation of the device The user s manual is supplemented by module reference manuals that provide detailed informa tion about module operation and applications Refer to Freescale publication Advanced Microcontroller Unit AMCU Literature BR1116 D for a complete list of documenta tion to supplement this manual INTRODUCTION M68HC16 Z SERIES For More Information On This Product USER S MANUAL to www freescale com Freescale Semiconductor Inc SECTION 2 NOMENCLATURE The following tables show the nomenclature used throughout the M68HC16 Z series manual 2 1 Symbols and Operators Symbol Function Addition Subtraction two s complement or negation i Multiplication Division gt Greater lt Less Equal Equal or greater x Equal or less AND E e Exclusive OR EOR OT Complementation Concatenation Exchanged Sign extension Binary value Hexadecimal value M68HC16 Z SERIES NOMENCLATURE USER S MANUAL 2 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 2 CPU16 Register Mnemonics Mnemonic Register Accumulator A Accumulator B D Accumulator D Extended addressing extensio
367. dule control system tasks that must be performed within time constraints The timer consists of a prescaler a modulus counter and registers that determine interrupt timing priority and vector as signment Refer to 4 13 Exceptions for further information about interrupt exception processing M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 27 Go to www freescale com Freescale Semiconductor Inc The periodic interrupt timer modulus counter is clocked by one of two signals When the PLL is enabled MODCLK 1 during reset fref is used with a slow reference os cillator fa 128 is used with fast reference oscillator When the PLL is disabled MOD CLK 0 during reset fref is used The value of the periodic timer prescaler bit in the periodic interrupt timer register PITR determines system clock prescaling for the periodic interrupt timer One of two options either no prescaling or prescaling by a factor of 512 can be selected The value of PTP is affected by the state of the MOD CLK pin during reset as shown in Table 5 11 System software can change PTP val ue Table 5 11 MODCLK Pin and PTP Bit at Reset MODCLK PTP 0 External Clock 1 Internal Clock Either clock signal selected by the PTP is divided by four before driving the modulus counter The modulus counter is initialized by writing a value to the periodic interrupt timer modulus PITM 7 0 field
368. e m T 2 RESET 2N3906 1N4148 V RESET ALTERNATE DATA BUS CONDITION CIRCUIT Figure 5 19 Alternate Circuit for Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC TERISTICS Do not confuse pin function with pin electrical state Refer to 5 7 5 Pin State During Reset for more information Unlike other chip select signals the boot ROM chip select CSBOOT is active at the release of RESET During reset exception processing the MCU fetches initialization vectors beginning at address 000000 in supervisor program space An external memory device containing vectors located at these addresses can be enabled by CSBOOT after a reset The logic level of DATAO during reset selects boot ROM port size for dynamic bus al location When DATAO is held low port size is eight bits when DATAO is held high either by the weak internal pull up driver or by an external pull up port size is 16 bits Refer to 5 9 4 Chip Select Reset Operation for more information DATA1 and determine the functions of CS 2 0 and CS 5 3 respectively DATA 7 3 determine the functions of an associated chip select and all lower num chip selects down through CS6 For example if DATAS is pulled low during reset CS 8 6 are assigned alternate function as ADDR 21 19 and CS 10 9 remain chip selects Refer to 5 9 4 Chip Select Reset Operation for more information
369. e Hardware prevents the vector number from changing while it is being driven out on the IMB Vector number assign ment is shown in Table 11 2 At reset IVBA 3 0 is initialized to 0 To enable interrupt driven timer operation the upper nibble of a user defined vector number 40 FF must be written to IVBA and interrupt handler routines must be located at the addresses pointed to by the corre sponding vector NOTE IVBA 3 0 must be written before GPT interrupts are enabled or the GPT could supply a vector number 00 to 0F that corresponds to an assigned or reserved exception vector The internal GPT interrupt priority hierarchy is shown in Table 11 2 The lower the in terrupt source number the higher the priority A single GPT interrupt source can be given priority over all other GPT interrupt sources by assigning the priority adjust field IPA 3 0 in the ICR a value equal to its source number GENERAL PURPOSE TIMER M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Interrupt requests are asserted until associated status flags are cleared Status flags must be cleared in a particular sequence The status register must first be read for set flags then zeros must be written to the flags that are to be cleared If a new event oc curs between the time that the register is read and the time that it is written the asso ciated flag is not cleared For more information on interrupts re
370. e Input Output Fall Time Input Output NOTES 1 Refer to notes in Table A 30 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 49 Go to www freescale com Freescale Semiconductor Inc Table A 30 SPI Timing and V 5 0 Vdc 10 for 16 78 MHz 5 for 20 25 MHz Vaa 0 Vdc T T to T y DD 55 A DDSYN Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock SCK High or Low Time Master Slave Sequential Transfer Delay Master Slave Does Not Require Deselect Data Setup Time Inputs Master Slave Data Hold Time Inputs Master Slave Slave MISO Disable Time Data Valid after SCK Edge Master Slave Data Hold Time Outputs Master Slave Rise Time Input Output Fall Time Input Output NOTES 1 All AC timing is shown with respect to Vi Vij levels unless otherwise noted 2 For high time n External SCK rise time for low time n External SCK fall time ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES 50 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT 16 MCCI MAST CPHAO SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT
371. e 4 10 breakpoints 4 41 compatibility with M68HC11 4 1 condition code register CCR 4 4 data types 4 6 extension fields 4 6 features 3 1 general information 4 1 index registers 4 3 instruction 4 11 comparison to M68HC11 4 31 execution model 4 34 set abbreviations and symbols 4 30 summary 4 12 timing 4 36 levels of interrupt priority 5 58 memory management 4 5 organization 4 7 program counter PC 4 3 reference manual 4 1 register model 4 2 D 2 registers condition code register CCR D 3 mnemonics 2 2 multiply and accumulate MAC registers 4 5 stack pointer SP 4 3 CR 0 52 CREG D 22 Cross correlation 4 45 CSBAR D 17 CSBARBT D 17 CSBOOT 5 57 5 63 5 65 5 66 5 69 5 70 7 3 reset values 5 70 CSOR D 18 CSORBT D 18 CSPARO0 1 0 15 For More Information On This Product l 3 Go to www freescale com Freescale Semiconductor Inc D DAC capacitor array 8 22 DATA 5 31 Data and size acknowledge DSACK See DSACK 5 24 bus mode selection 5 50 signals DATA 5 31 frame 9 25 10 17 multiplexer 5 35 strobe DS See DS 5 31 DATA definition 2 6 DC characteristics 16 78 MHz A 12 20 97 MHz A 14 25 17 MHz A 16 low voltage 16 78 MHz A 10 DDRE 5 70 D 9 DDRF 5 70 0 11 DDRGP 11 8 11 14 D 69 DDRM D 58 DDRQS 9 4 9 16 9 20 D 45 Delay after transfer DT 9 18 D 53 before SCK DSCKL D 49 Designated CPU space 5 32 Design Net database B 8 Development support for CPU16 4 40 tools and support C 1 D
372. e Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc QSPI CYCLE BEGINS MASTER MODE IS QSPI DISABLED HAS NEWQP BEEN WRITTEN WORKING QUEUE POINTER CHANGED TO NEWQP READ COMMAND CONTROL AND TRANSMIT DATA FROM RAM USING QUEUE POINTER ADDRESS ASSERT PERIPHERAL CHIP SELECT S IS PCS TO SCK DELAY PROGRAMMED EXECUTE PROGRAMMED DELAY EXECUTE STANDARD DELAY EXECUTE SERIAL TRANSFER STORE RECEIVED DATA IN RAM USING QUEUE POINTER ADDRESS Figure 9 5 Flowchart of QSPI Master Operation Part 1 QSPIFLOW 2 M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 11 to www freescale com 9 12 Freescale Semiconductor Inc WRITE QUEUE POINTER TO CPTQP STATUS BITS IS CONTINUE BIT ASSERTED NEGATE PERIPHERAL CHIP SELECT S IS DELAY AFTER TRANSFER ASSERTED EXECUTE PROGRAMMED DELAY EXECUTE STANDARD DELAY QSPIMSTR2 FLOW 3 Figure 9 6 Flowchart of QSPI Master Operation Part 2 QUEUED SERIAL MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc IS THIS THE LAST COMMAND IN THE QUEUE ASSERT SPIF STATUS FLAG IS INTERRUPT ENABLE BIT SPIFIE ASSERTED
373. e Information On This Product 9 25 Go to www freescale com 5 26 For More Information On This Product Freescale Semiconductor Inc Both writes must occur before time out in the order listed Any number of instructions can be executed between the two writes Watchdog clock rate is affected by the software watchdog prescale SWP bit and the software watchdog timing SWT 1 0 field in SYPCR SWP determines system clock prescaling for the watchdog timer and determines that one of two options either no prescaling or prescaling by a factor of 512 can be select ed The value of SWP is affected by the state of the MODCLK pin during reset as shown in Table 5 9 System software can change SWP value Table 5 9 MODCLK Pin and SWP Bit During Reset MODCLK SWP 0 External Clock 1 512 1 Internal Clock 0 1 SWT 1 0 selects the divide ratio used to establish the software watchdog time out period The following equation calculates the time out period for a slow reference frequency where fre is equal to the EXTAL crystal frequency Divide Ratio Specified by SWP and SWT 1 0 ref Time Out Period The following equation calculates the time out period for a fast reference frequency where fre is equal to the EXTAL crystal frequency 128 Divide Ratio Specified by SWP and SWT 1 0 Time Out Period ref The following equation calculates the time out period for an externally input clock fre que
374. e RDRF flag is set If software does not recognize the ad dress it can set RWU and put the receiver back to sleep Address mark wake up allows idle time between frames and eliminates idle time between transmissions How ever there is a loss of efficiency because of an additional bit time per frame 9 4 3 9 Internal Loop Mode The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter When LOOPS is set the SCI transmitter output is fed back into the receive serial shifter TXD is asserted idle line Both transmitter and receiver must be enabled before entering loop mode QUEUED SERIAL MODULE M68HC16 Z SERIES 9 30 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 10 MULTICHANNEL COMMUNICATION INTERFACE This section is an overview of the multichannel communication interface MCCI mod ule Refer to the Reference Manual MCCIRM AD for more information on MCCI capabilities Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for MCCI timing and electrical specifications Refer to D 7 Multichannel Communication Interface Module for register address mapping and bit field definitions 10 1 General The MCCI contains three serial interfaces a serial peripheral interface and two serial communication interfaces SCI Figure 10 1 is a block diagram of the MCCI The MCCI is present only on 68 1674 MC68CK16Z4 microcontrollers INTE
375. e clock operation during low power stop mode The flowchart shown in Figure 5 6 summarizes the effects of the STSIM and STEXT bits when MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 and MC68HC16Z3 MCUs enter normal low power stop mode Any clock in the off state is held low If the synthesizer VCO is turned off during low power stop mode there is a PLL relock delay after the VCO is turned back on Figure 5 7 summarizes the effects of the STSIM and STEXT bits when MC68HC16Z4 and MC68CK16Z4 MCUs enter normal low power stop mode M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 21 Go to www freescale com Freescale Semiconductor Inc NOTE The internal oscillator which supplies the input frequency for the PLL always runs when a crystal is used SET UP INTERRUPT TO WAKE UP MCU FROM LPSTOP NO USING EXTERNAL CLOCK NO USE SYSTEM CLOCK AS SIMCLK IN LPSTOP SET STSIM 1 SET STSIM 0 fet IN LPSTOP IN LPSTOP NO WANT CLKOUT ON IN LPSTOP WANT CLKOUT ON IN LPSTOP SET STEXT 1 SET STEXT 20 SET STEXT 1 SET STEXT 20 fau fau 0 Hz ferkout fref fou 0Hz feck feck 0 Hz feck 0 Hz feck 0 Hz IN LPSTOP IN LPSTOP IN LPSTOP INLPSTOP ENTER LPSTOP NOTES 1 THE SIMCLK IS USED BY THE PIT TQ AND INPUT BLOCKS OF THE SIM 2 CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SIMC
376. e com Freescale Semiconductor Inc 0 5 5 A2 A3 A0 CLKOUT DATA 15 0 16 BUS ARB TIM IDLE Figure A 9 Bus Arbitration Timing Diagram Idle Bus Case ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 34 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc CLKOUT lt gt ADDR 23 0 15 ub DATA 15 0 1 JE cj gt E IPIPEO pl 2 1 2 SHOW CYCLE gt lt start OF EXTERNAL CYCLE 3 NOTE SHOW CYCLES CAN STRETCH DURING CLOCK PHASE 542 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT STATE INSERTION 16 SHW CYC TIM Figure A 10 Show Cycle Timing Diagram M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 35 Go to www freescale com Freescale Semiconductor Inc CLKOU SS ADDR 23 0 FC 2 0 1Z 1 0 lt gt CLL n DATA 15 0 16 CHIP SEL Figure 11 Chip Select Timing Diagram RESET DATA 15 0 MODCLK BKPT 16 RST MODE SEL TIM Figure A 12 Reset and Mode Select Timing Diagram ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc
377. e com Freescale Semiconductor Inc Blocks of addresses are assigned to each chip select function Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register CSBAR 10 0 and CSBARBT However because the logic state of ADDR20 is al ways the same as the state of ADDR19 in the MCU the largest usable block size is 512 Kbytes Multiple chip selects assigned to the same block of addresses must have the same number of wait states Chip select option registers CSORBT and CSOR 0 10 determine timing of and con ditions for assertion of chip select signals Eight parameters including operating mode access size synchronization and wait state insertion can be specified Initialization software usually resides in a peripheral memory device controlled by the chip select circuits A set of special chip select functions and registers CSORBT and CSBARBT is provided to support bootstrap operation Comprehensive address maps and register diagrams are provided in APPENDIX D REGISTER SUMMARY 5 9 1 1 Chip Select Pin Assignment Registers The pin assignment registers contain twelve 2 bit fields that determine the functions of the chip select pins Each pin has two or three possible functions as shown in Table 5 22 Table 5 22 Chip Select Pin Functions Alternate Discrete Function Output CSBOOT CSBOOT Chip Select ADDR20 CS8 ADDR21 PC5 CS9 ADDR22 PC6 CS10 ADDR
378. e guar anteed to be valid but only writes to the QSPI RAM and other QSM registers are guar anteed valid The SCI receiver and transmitter and the QSPI should be disabled before STOP is set To stop the QSPI set the HALT bit in SPCR3 wait until the HAL TA flag is set then set STOP To stop the SCI clear the TS and RE bits in SCCR1 FRZ1 FREEZE Assertion Response FRZ1 determines what action is taken by the QSPI when the IMB FREEZE signal is asserted 0 Ignore the IMB FREEZE signal 1 Halt the QSPI on a transfer boundary FRZO Not Implemented Bits 12 8 Not Implemented SUPV Supervisor Unrestricted This bit has no effect because the CPU16 in the MCU operates only in supervisor mode Bits 6 4 Not Implemented IARB 3 0 Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority Each module that can generate interrupt requests must be assigned a unique non zero IARB field value in order to request an interrupt D 6 2 QSM Test Register QTEST QSM Test Register YFFCO2 Used for factory test only D 6 3 QSM Interrupt Level Register Interrupt Vector Register QILR QSM Interrupt Levels Register YFFCOA QIVR QSM Interrupt Vector Register YFFCO5 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 NOT USED ILQSPI 2 0 ILSCI 2 0 INTV 7 0 RESET 0 0 0 0 0 0 0 0 0 0 1 1 1 1 The values of ILQSPI 2 0 and ILSCI 2 0 in QILR determine the pri
379. e impedances Figure 8 7 shows an active parasitic bipolar when an input pin is subjected to negative stress conditions Positive stress conditions do not activate a similar parasitic device NEGATIVE R OUT PIN UNDER STRESS e _ STRESS PARASITIC W VDD DEVICE V 17 C ADJACENT R ADJACENT PINS ADC PAR STRESS CONN Figure 8 7 Input Pin Subjected to Negative Stress ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 18 For More information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The current out of the lour under negative stress is determined by the following equation _ Vstress Veel OUT R STRESS where Vstress Adjustable voltage source Vege Parasitic bipolar base emitter voltage refer to in APPENDIX A ELECTRICAL CHARACTERISTICS Rstress Source impedance 10K resistor in Figure 8 7 on stressed channel The current into liy the neighboring pin is determined by the 1 Ky Gain of the para sitic bipolar transistor 1 Ky lt lt 1 One way to minimize the impact of stress conditions on the ADC is to apply voltage limiting circuits such as diodes to supply and ground However leakage from such cir cuits and the potential influence on the sampled voltage to be converted must be con sidered Refer to Figure 8 8 VDD kR R EXTERNAL VOLTAGE gt NN TO DEVICE vss ADC NEG STRESS CONN Figure 8 8
380. e of seven prescaler taps or an external input from the PCLK pin Multiplexer output for the timer counter TCNT is selected by bits CPR 2 0 in timer interrupt mask register 2 TMSK2 Multiplexer output for the PWM counter PWMCNT is selected by bits PPR 2 0 in PWM control register C PWMC After re set the GPT is configured to use system clock divided by four for TCNT and system clock divided by two for PWMCNT Initialization software can change the division fac tor The PPR bits can be written at any time but the CPR bits can only be written once after reset unless the GPT is in test or freeze mode M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL For More Information On This Product 11 9 to www freescale com 1 1 Freescale Semiconductor Inc The prescaler can be read at any time In freeze mode the prescaler can also be writ ten Word accesses must be used to ensure coherency If coherency is not needed byte accesses can be used The prescaler value is contained in bits 8 0 while bits 15 9 are unimplemented and are read as zeros Multiplexer outputs including the PCLK signal can be connected to external pins The CPROUT bit in the TMSK2 register configures the OC1pin to output the TCNT clock and the PPROUT bit in the PWMC register configures the PWMA pin to output the PWMC clock CPROUT and PPROUT can be written at any time Clock signals on OC1 and PWMA do not have a 50 duty cycle They have the period of t
381. e register must be config ured to match ADDR 23 11 as the address is compared to an address generated by the CPU ADDR 23 20 follow the state of ADDR19 in this MCU The states of base register bits 15 12 must match that of bit 11 Figure 5 23 shows CPU space encoding for an interrupt acknowledge cycle FC 2 0 are set to 111 designating CPU space access ADDR 3 1 indicate interrupt priority and the space type field ADDR 19 16 is set to 1111 the interrupt acknowledge code The rest of the address lines are set to one FUNCTION ADDRESS BUS CODE INTERRUPT 2 E 0 VS CPU SPACE TYPE FIELD CPU SPACE IACK TIM Figure 5 23 CPU Space Encoding for Interrupt Acknowledge Because address match logic functions only after the EBI transfers an interrupt ac knowledge cycle to the external address bus following IARB contention chip select logic generates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins If an internal module makes an interrupt request of a certain priority and the chip select base address and option registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level chip select logic does not respond to the interrupt acknowledge cycle and the internal module supplies a vector number and generates an internal DSACK signal to terminate the cycle Perform the following o
382. e shifter can take place If RDRF is set when the shifter is full transfers are inhibited and the overrun error OR flag in SCSR is set OR indicates that RDR needs to be serviced faster When OR is set the data in RDR is preserved but the data in the serial shifter is lost Because framing noise and parity errors are detected while data is in the serial shifter FE NF and PF cannot occur at the same time as OR When the CPU16 reads SCSR and SCDR in sequence it acquires status and data and also clears the status flags Reading SCSR acquires status and arms the clearing mechanism Reading SCDR acquires data and clears SCSR When RIE in SCCR1 is set an interrupt request is generated whenever RDRF is set Because receiver status flags are set at the same time as RDRF they do not have separate interrupt enables 9 4 3 7 Idle Line Detection During a typical serial transmission frames are transmitted isochronally and no idle time occurs between frames Even when all the data bits in a frame are logic ones the start bit provides one logic zero bit time during the frame An idle line is a sequence of contiguous ones equal to the current frame size Frame size is determined by the state of the M bit in SCCR1 The SCI receiver has both short and long idle line detection capability Idle line detec tion is always enabled The idle line type ILT bitin SCCR1 determines which type of detection is used When an idle line condition is detected
383. e signal on a specific edge of the CLKOUT signal 5 6 2 Regular Bus Cycle The following paragraphs contain a discussion of cycles that use external bus control logic Refer to 5 6 3 Fast Termination Cycles for information about fast termination cycles To initiate a transfer the MCU asserts an address and the SIZ 1 0 signals The SIZ signals and ADDRO are externally decoded to select the active portion of the data bus Refer to 5 5 2 Dynamic Bus Sizing When AS DS and R W are valid a peripheral device either places data on the bus read cycle or latches data from the bus write cycle then asserts a DSACK 1 0 combination that indicates port size The DSACK 1 0 signals can be asserted before the data from a peripheral device is valid on a read cycle To ensure valid data is latched into the MCU a maximum period between DSACK assertion and DS assertion is specified There is no specified maximum for the period between the assertion of AS and DSACK Although the MCU can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK the MCU inserts wait cycles in clock period incre ments until either DSACK signal goes low If bus termination signals remain unasserted the MCU will continue to insert wait states and the bus cycle will never end If no peripheral responds to an access or if an access is invalid external logic should assert the BERR or HALT signals to abort the bus cycle when BERR
384. e that can generate interrupt requests must be assigned a unique non zero IARB field value D 8 2 GPT Test Register GPTMTR GPT Module Test Register YFF902 Used for factory test only D 8 3 GPT Interrupt Configuration Register ICR GPT Interrupt Configuration Register YFF904 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 IPA 3 0 0 IPL 2 0 IVBA 3 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICR fields determine internal and external interrupt priority and provide the upper nib ble of the interrupt vector number supplied to the CPU when an interrupt is acknowl edged IPA 3 0 Interrupt Priority Adjust This field specifies which GPT interrupt source is given highest internal priority Refer to Table D 43 REGISTER SUMMARY M68HC16 Z SERIES D 68 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 43 GPT Interrupt Sources Name Source Number Source Vector Number 0000 Adjusted Channel IVBA 0000 IC1 Input Capture 1 IVBA 0001 IC2 0010 Input Capture 2 IVBA 0010 IC3 Input Capture 3 IVBA 0011 OC1 0100 Output Compare 1 IVBA 0100 OC2 Output Compare 2 IVBA 0101 OC3 0110 Output Compare 3 IVBA 0110 Output Compare 4 0111 IC4 OC5 1000 Input Capture 4 Output Compare 5 IVBA 1000 TO Timer Overflow IVBA 1001 PAOV 1010 Pulse Accumulator Overflow IVBA 1010 PAI Pulse Accumulator Input IVBA 1011
385. ead PC and SP RPCSP Read contents of program counter and stack pointer Write PC and SP WPCSP Write to program counter and stack pointer Read byte from specified 20 bit address in data space Write Data Memory WDMEM Write byte to specified 20 bit address in data space Read word from specified 20 bit address in program space Write word to specified 20 bit address in program space Read Data Memory RDMEM Read Program Memory RPMEM Write Program Memory WPMEM Execute from Current Instruction pipeline flushed and refilled instructions PK PC executed from current PC 0006 Null Operation NOP Null command performs no operation 4 14 4 5 Returning from BDM BDM is terminated when a resume execution GO command is received GO refills the instruction pipeline from address PK PC 0006 FREEZE is negated before the first prefetch Upon negation of FREEZE the BDM serial subsystem is disabled and the DSO DSI signals revert to IPIPEO IPIPE1 functionality M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 43 Go to www freescale com Freescale Semiconductor Inc 4 14 4 6 BDM Serial Interface The BDM serial interface uses a synchronous protocol similar to that of the Freescale serial peripheral interface SPI Figure 4 7 is a diagram of the serial logic required to use BDM with a development system CPU DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS 5 DAT
386. ead Write Field Bit Encoding D 19 Field D 20 Memory Access Times at 16 78 20 97 25 17 2 D 20 Address NR Ea D 21 Interrupt Priority Level Field D 21 aac cr lace ello me D 23 SRAM Array Address Space D 23 MRM Address naa D 25 ROM Array Space D 26 Wat otates Fold eke D 26 ADG Mod le Address Map sod am pa inu ds DB D 29 Freeze D 30 Sample Time Selection Lasesaset 0 31 i E Mcd e D 32 ADG Conversion ak OUO WATER RES TRA EXE VERE RM D 33 Single Channel Conversions 0 2 1 D 34 Multiple Channel Conversions 1 40 D 35 siamese ER D 38 Examples of SGI Baud isis D 41 decer in apo dadas 0 45 Effect of DDRUS on OSM Pin FUNTION D 46 e 1 E N
387. ecting data strobe causes the chip select to be asserted synchro nized with data strobe Data strobe timing is used to create a write strobe when needed 0 Address strobe 1 Data strobe DSACK 3 0 Data Strobe Acknowledge This field specifies the source of DSACK in asynchronous mode as internally generat ed or externally supplied It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to opti mize bus speed in a particular application Table 0 15 shows the DSACK 3 0 field en coding The fast termination encoding 1110 effectively corresponds to 1 wait states M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 19 Go to www freescale com Freescale Semiconductor Inc Table D 15 DSACK Field Encoding ee ences 0000 3 9 0001 4 1 0010 5 2 0011 6 3 0100 7 ii 0101 8 0110 9 2 0111 10 f 1000 11 8 1001 12 2 1010 13 19 1011 14 1100 15 12 1101 16 Ls 1110 2 Fast Termination 1111 External DSACK External memories are purchased with guaranteed access times on speed in nano seconds Table D 16 relates wait states selected by DSACK 3 0 to the memory de vice access time NOTE Table D 16 assumes a system configuration that minimizes power consumption and the number of chip selects employed Other ac cess tech
388. ed number of clock cycles The value of the STS field in ADCTLO determines the number of cycles Refer to Table 8 4 The number of clock cycles required for a sample period is the value specified by STS plus four Sample time is determined by PRS value Table 8 4 TS Field Selection STS 1 0 Sample Time 00 2 A D clock periods 4 A D clock periods 8 A D clock periods 11 16 A D clock periods 8 7 4 Resolution ADC resolution can be either eight or ten bits Resolution is determined by the state of the RES10 bit in ADCTLO Both 8 bit and 10 bit conversion results are automatically aligned in the result registers 8 7 5 Conversion Control Logic Analog to digital conversions are performed in sequences Sequences are initiated by any write to ADCTL1 If a conversion sequence is already in progress a write to either control register will abort it and reset the SCF and CCF flags in the A D status register There are eight conversion modes Conversion mode is determined by ADCTL1 con trol bits Each conversion mode affects the bits in status register ADCSTAT differently Result storage differs from mode to mode M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 8 7 Go to www freescale com Freescale Semiconductor Inc 8 7 5 1 Conversion Parameters Table 8 5 describes the conversion parameters controlled by bits in ADCTL1 Table 8 5 Conversion Parameters Controlled by ADCTL1
389. edback path disabled 1 Test SCI operation looping feedback path enabled WOMS Wired OR Mode for SCI Pins 0 If configured as an output TXD is a normal CMOS output 1 If configured as an output TXD is an open drain output M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 41 Go to www freescale com Freescale Semiconductor Inc ILT Idle Line Detect Type 0 Short idle line detect start count on first one 1 Long idle line detect start count on first one after stop bit s PT Parity Type 0 Even parity 1 Odd parity PE Parity Enable 0 SCI parity disabled 1 SCI parity enabled Mode Select 0 10 bit SCI frame 1 start bit 8 data bits 1 stop bit 1 11 bit SCI frame 1 start bit 9 data bits 1 stop bit WAKE Wake Up by Address Mark 0 SCI receiver awakened by idle line detection 1 SCI receiver awakened by address mark last data bit set TIE Transmit Interrupt Enable 0 SCI TDRE interrupts disabled 1 SCI interrupts enabled TCIE Transmit Complete Interrupt Enable 0 SCI TC interrupts disabled 1 SCI interrupts enabled RIE Receiver Interrupt Enable 0 SCI RDRF and OR interrupts disabled 1 SCI RDRF and OR interrupts enabled ILIE Idle Line Interrupt Enable 0 SCI IDLE interrupts disabled 1 SCI IDLE interrupts enabled TE Transmitter Enable 0 SCI transmitter disabled TX
390. eescale com Freescale Semiconductor Inc ILSPI 2 0 Interrupt Level for SPI ILSPI 2 0 determine the interrupt request levels of SPI interrupts Program this field to a value from 0 interrupts disabled through 7 highest priority If the interrupt request level programmed in this field matches the interrupt request level pro grammed for one of the SCI interfaces and both request an interrupt simultaneously the SPI is given priority Bits 10 8 Not Implemented D 7 6 MCCI Pin Assignment Register MPAR MCCI Pin Assignment Register YFFCO8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT NOT USED MPA3 USED MPA1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 The MPAR determines which of the SPI pins with the exception of the SCK pin are actually used by the SPI submodule and which pins are available for general purpose I O The state of SCK is determined by the SPI enable bit in SPCR1 Clearing a bit in MPAR assigns the corresponding pin to general purpose l O setting a bit assigns the pin to the SPI Refer to Table D 39 Table D 39 MPAR Pin Assignments MPAR Field MPAR Bit Pin Function 0 PMCO MPAO 1 5 0 PMC1 1 4 RXDB 224 NOTES 1 MPA 7 4 MPA2 are not implemented Bits 15 8 7 4 2 Not Implemented SPI pins designated by the MPAR as general purpose are controlled only by MDDR and PORTMC The SPI has no effect on these pins The MPAR does not affect the
391. eiver enable bits and dual data buffers A modulus type baud rate generator provides rates from 110 baud to 781 kbaud with a 25 17 MHz system clock Word length of either eight or nine bits is software selectable Optional parity generation and detection provide either even or odd parity check capability Advanced error detection circuitry catches glitches of up to 1 16 of a bit time in duration Wake up functions allow the CPU16 to run unin terrupted until meaningful data is available 9 2 QSM Registers and Address Map There are four types of QSM registers QSM global registers QSM pin control regis ters QSPI registers and SCI registers Refer to 9 2 1 QSM Global Registers and 9 2 2 QSM Pin Control Registers for a discussion of global and pin control registers Refer to 9 3 1 QSPI Registers and 9 4 1 SCI Registers for further information about QSPI and SCI registers Writes to unimplemented register bits have no effect and reads of unimplemented bits always return zero Refer to D 6 Queued Serial Module for a QSM address map and register bit and field definitions Refer to 5 2 1 Module Mapping for more information about how the state of MM affects the system 9 2 1 QSM Global Registers The QSM configuration register QSMCR controls the interface between the QSM and the intermodule bus The QSM test register QTEST is used during factory test of the QSM The QSM interrupt level register QILR determines the priority of inter rupts requ
392. elect 0 upper byte write only INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com EA GY Et tied Fay E Ed 7 69 00 T On On The Main Program MAIN XLOOP LDD PRINT LDAB TBXK LDX JSR BRA Freescale Semiconductor Inc 3030 CSOR1 0303 CSBAR2 7830 CSOR2 3FFF CSPARO 00 STRING 03 0000 2 500 PRINT 500 XLOOP 503 50000 SEND_STRING PRINT ARKH SUBLOUESNES SEND_STRING LDAB BEQ JSR AIX BRA STRING_DONE RTS SEND_CH time LDAA ANDA M68HC16 Z SERIES USER S MANUAL 0 X STRING DON SEND CH 1 SEND_STRING GI KKKKK set Chip Select 1 lower byte write only set Chip Select 2 to fire at base addr 30000 Chip Select 2 both bytes read and write set Chip Selects 0 1 2 to 16 bit ports Move data from another place in memory into the Ul and U3 RAM slots set XK to bank 0 for access to the STRING load the starting address of STRING into ZK to bank 3 for access to Ul amp U3 during write in XLOOP clear IZ so ZK IZ 30000 load two bytes from 10000 into accum D Store accum D into 01 U3 RAM the chip select logic takes care of us increment X index register to next word incre
393. emory C 1 Bus arbitration for a single device 5 46 timing active A 33 timing idle A 34 cycle regular 5 37 terminations for asynchronous cycles 5 44 error exception processing 5 44 signal BERR See BERR 5 24 timing of 5 44 exception control cycles 5 43 grant BG See BG 5 46 grant acknowledge BGACk See BGACK 5 46 monitor 5 24 external enable BME D 13 timeout period 5 25 timing BMT 5 24 D 13 request BR See BR 5 46 state analyzer 4 40 BYTE upper lower byte option 5 66 D 19 4 4 D 3 Capture compare unit 11 1 block diagram 11 11 clock output enable CPROUT bit D 73 Carry flag C 4 4 D 3 Case outlines 132 pin package B 4 144 pin package B 7 CCF D 36 CCR 4 4 D 3 CCTR D 36 CD CA D 33 Cpac 8 22 Central processing unit CPU16 See CPU16 4 1 Cr 8 22 CFORC 11 8 11 13 11 14 D 74 Channel selection for A D conversion D 33 Charge sharing 8 23 Chip select base address registers CSBAR 5 64 5 65 reset values 5 69 operation 5 67 option registers CSOR 5 64 5 66 D 18 reset values 5 69 pin assignment registers CSPAR 5 63 D 17 field encoding 5 64 M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc reset operation 5 69 signals for interrupt acknowledge 5 68 timing diagram A 36 Clear definition 2 6 CL 4 37 Clipping errors 8 16 CLKOUT 5 36 5 48 output timing diagram A 28 CLKRST clock reset 5 48 CLo 4 37 Clock ADC 8
394. ent unit PRU C 2 size 5 65 PORTADA 8 1 D 30 PORTC D 15 PORTE 5 71 D 9 PORTF 5 71 PORTFO 1 D 10 PORTGP 11 8 D 69 PORTMC 10 2 D 59 PORTMCP 10 2 D 59 PORTQS 9 4 D 44 Positive stress 8 18 Post modified index addressing mode 4 10 POW D 8 Power connections 3 13 up reset POW D 8 PPR D 75 PPROUT D 75 PQSPAR 9 4 9 16 9 20 D 45 Prescaler 11 1 11 8 block diagram 11 9 rate selection field PRS D 31 PRESCL D 77 Program counter address extension field PK 4 4 D 3 flow changes 4 36 Programming examples E 12 CPU16 E 23 GPT E 25 QSM SCI E 24 SIM E 13 PROUT 11 10 PRS D 31 10 For More Information On This Product PRU C 2 PSHM 4 9 PT 9 26 10 19 D 42 D 61 PTP D 14 PULM 4 9 Pulse accumulator 11 1 block diagram 11 15 clock select PACLK D 71 select mux 11 10 counter PACNT D 71 edge control PEDGE D 70 enable PAEN D 70 flag PAIF 11 15 D 74 input PAI pin 11 7 11 8 11 15 interrupt enable PAII bit D 73 mode PAMOD D 70 overflow flag PAOVF 11 15 D 74 interrupt enable PAOVI bit D 73 width modulation 1 1 1 pins PWMA PWMB 11 8 unit PWM 11 16 block diagram 11 17 buffer register PWMBUFA B 11 19 counter 11 18 duty cycle ratios 11 17 frequency ranges 11 18 D 76 function 11 18 PWM 11 16 clock output enable PPROUT D 75 prescaler PCLK select PPR field D 75 slow fast select SFA bit D 75 SFB bit D 75 11 8 0 76 PWMBUFA B 11 19 0 76 PWMC 11 8 D 74 PWMCNT 11
395. er nally generated DSACK or externally generated DSACK is used The external DSACK lines are always active regardless of the setting of the DSACK field in the chip select option registers Thus an external DSACK can always terminate a bus cycle Holding a DSACK line low will cause essentially all external bus cycles to be three cycle zero wait states accesses unless the chip select option register specifies fast accesses NOTE There are certain exceptions to the three cycle rule when one or both DSACK lines are asserted Check the current device and mask set errata for details For fast termination cycles the fast termination encoding 1110 must be used Re fer to 5 9 1 Chip Select Registers for information about fast termination setup To use fast termination an external device must be fast enough to have data ready within the specified setup time for example by the falling edge of S4 Refer to AP PENDIX A ELECTRICAL CHARACTERISTICS for information about fast termination timing When fast termination is in use DS is asserted during read cycles but not during write cycles The STRB field in the chip select option register used must be programmed with the address strobe encoding to assert the chip select signal for a fast termination write 5 6 4 CPU Space Cycles Function code signals FC 2 0 designate which of eight external address spaces is ac cessed during a bus cycle Address space 7 is designated CP
396. er Detects bus master mode fault 10 3 3 SPI Operating Modes The SPI operates in either master or slave mode Master mode is used when the MCU originates data transfers Slave mode is used when an external device initiates serial transfers to the MCU The MSTR bit in SPCR selects master or slave operation 10 3 3 1 Master Mode Setting the MSTR bit in SPCR selects master mode operation In master mode the SPI can initiate serial transfers but cannot respond to externally initiated transfers When the slave select input of a device configured for master mode is asserted a mode fault occurs When using the SPI in master mode include the following steps 1 Write to the MMCR and ILSPI Refer to 10 5 MCCI Initialization for more information 2 Write to the MPAR to assign the following pins to the SPI MISO MOSI and optionally SS MISO is used for serial data input in master mode and MOSI is used for serial data output Either or both may be necessary depending on the particular application SS is used to generate a mode fault in master mode If this SPI is the only possible master in the system the SS pin may be used for general purpose 3 Write to the MDDR to direct the data flow on SPI pins Configure the SCK serial clock and MOSI pins as outputs Configure MISO and optionally SS as in puts 4 Write to the SPCR to assign values for BAUD CPHA CPOL SIZE LSBF WOMP and SPIE Set the MSTR b
397. eration during LPSTOP 5 21 signal 5 21 interface 5 29 control signals 5 31 circuit settling time 8 23 M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc clock input signal PCLK 11 1 input timing diagram A 28 off EXOFF bit D 6 leakage 8 23 multiplexing of analog signal sources 8 20 reset EXT D 8 EXTRST external reset 5 55 z F1A B D 76 bits 11 8 Factory test 5 71 Fast mode 11 17 reference 5 4 reference circuit 5 5 termination cycles 5 36 5 39 read cycle timing diagram A 31 write cycle timing diagram A 32 FC 5 32 FE 9 28 10 21 D 44 D 63 Ferrite beads 8 14 flimp 5 55 FOC 11 14 D 75 Force compare bits FOC 11 14 logic level one on F1A B bit D 76 output compare FOC bit D 75 FPWMx 11 8 Frame 9 25 10 17 size 9 29 10 21 Framing error FE flag 9 28 10 21 D 44 D 63 Free running counter TONT 11 1 FREEZE 4 43 assertion response FRZ ADC 8 4 D 30 GPT 11 3 D 68 QSM 9 3 D 39 SIM 5 3 bus monitor FRZBM 5 3 D 6 software enable FRZSW 5 3 D 6 fret 5 5 5 7 Frequency control bits counter Y D 8 prescaler X D 8 VCO W D 8 FRZ 8 4 11 3 D 30 D 39 D 68 FRZBM 5 3 D 6 FRZSW 5 3 D 6 fsys 5 5 D 7 F term encoding 5 40 Function code FC signals 5 32 5 40 fyco 5 7 M68HC16 Z SERIES USER S MANUAL For More Information On This Product G Gain 8 19 Gated time accumulation mode 11 15 General purp
398. ere are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase
399. ernal phase locked loop circuit synthesizes the sys tem clock from a slow typically 32 768 kHz or fast typically 4 194 MHz reference or uses an external frequency source Refer to Table 1 2 for information on which refer ence frequency is applied to a particular MCU x indicates the reference frequency applicable to the MCU M68HC16 Z SERIES INTRODUCTION USER S MANUAL For More Information On This Product 1 1 Go to www freescale com Freescale Semiconductor Inc Table 1 2 Z Series MCU Reference Frequencies Nominal Reference Frequency Slow Fast 32 768 kHz 4 194 MHz MC68HC16Z1 X 68 1671 MC68CK16Z1 X MC68HC16Z3 X 68 1674 NOTES 1 The nominal slow reference frequency is 32 768 kHz but can range from 20 to 50 kHz The nominal fast reference frequency is 4 194 MHz but can range from 1MHz to 6 25 MHz System hardware and software allow changes in clock rate during operation Because the MCUs are a fully static design register and memory contents are not affected by clock rate changes High density complementary metal oxide semiconductor HCMOS architecture makes the basic power consumption low Power consumption can be minimized by stopping the system clocks The M68HC16 instruction set includes a low power stop LPSTOP command that efficiently implements this capability Individual stop bits in each module allow for selective power reduction Documentation for the Mo
400. ers 1 and 2 1 eene D 72 D 8 12 Timer Interrupt Mask Registers 1 and 2 D 72 D 8 13 Timer Interrupt Flag Registers 1 2 D 74 D 8 14 Compare Force Register PWM Control Register C D 74 D 8 15 PYM 470 032 9 D 76 D 8 16 PWM Count re pu eT D 76 D 8 17 PWM Buffer Registers A B D 76 D 8 18 GP T Fe D 77 APPENDIX E INITIALIZATION AND PROGRAMMING EXAMPLES E 1 1 1 1 edt ql cm coo Q E 2 Ed TOP MSc RUN P E 6 E 1 3 ot mM PE E 6 E 1 4 INTSYS ASM ME E E 11 M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title E35 Ri le 1 6 proe Fono 2 Programming TG ES SIM Programming Examples E214 Example 1 Using Pons E and uaa tee Etna ESLZ Example 2 Using Chip Selects E213 Example Changing Clock Frequencies E 2 1 4 Examp
401. esponse time is excessively long DSACK and AVEC response times are measured in clock cycles Maximum allowable response time can be selected by setting the bus monitor timing 0 field in the system protection control register SYPCR Table 5 8 shows the periods allowed SYSTEM INTEGRATION MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com 5 24 Freescale Semiconductor Inc Table 5 8 Bus Monitor Period BMT 1 0 Bus Monitor Time Out Period 64 system clocks 32 system clocks 16 system clocks 8 system clocks The monitor does not check DSACK response on the external bus unless the CPU16 initiates a bus cycle The BME bit in SYPCR enables the internal bus monitor for inter nal to external bus cycles If a system contains external bus masters an external bus monitor must be implemented and the internal to external bus monitor option must be disabled When monitoring transfers to an 8 bit port the bus monitor does not reset until both byte accesses of a word transfer are completed Monitor time out period must be at least twice the number of clocks that a single byte access requires 5 4 3 Halt Monitor The halt monitor responds to an assertion of the HALT signal on the internal bus caused by a double bus fault A flag in the reset status register RSR can indicate that the last reset was caused by the halt monitor Halt monitor reset can be inhibi
402. esses or to program space accesses only The default value of ASPC 1 0 is established during mask programming but the value can be changed after reset if the LOCK bit in the MRMCR has not been masked to a value of one Because the CPU16 operates in supervisor mode only ASPC1 has no effect Table 7 1 shows ASPC 1 0 field encodings Table 7 1 ROM Array Space Field ASPC 1 0 State Specified X0 Program and data accesses X1 Program access only Refer to 5 5 1 7 Function Codes for more information concerning address space types and program data space access Refer to 4 6 Addressing Modes for more in formation on addressing modes 7 4 Normal Access 7 2 The array can be accessed by byte word or long word A byte or aligned word access takes a minimum of one bus cycle two system clocks A long word or misaligned word access requires a minimum of two bus cycles Access time can be optimized for a particular application by inserting wait states into each access The number of wait states inserted is determined by the value of WAIT 1 0 in the MRMCR Two three four or five clock accesses can be specified The default value WAIT 1 0 is established during mask programming but field value can be changed after reset if the LOCK bit in the MRMCR has not been masked to a value of one Table 7 2 shows WAIT 1 0 field encodings MASKED ROM MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to ww
403. ested by the QSM and the vector used when an interrupt is acknowledged The QSM interrupt vector register QIVR contains the interrupt vector for both QSM submodules QILR and QIVR are 8 bit registers located at the same word address 9 2 1 1 Low Power Stop Mode Operation When the STOP bit in QSMCR is set the system clock input to the QSM is disabled and the module enters low power stop mode QSMCR is the only register guaranteed to be readable while STOP is asserted The QSPI RAM is not readable in low power stop mode However writes to RAM or any register are guaranteed valid while STOP is asserted STOP can be set by the CPU16 and by reset The QSPI and SCI must be brought to an orderly stop before asserting STOP to avoid data corruption To accomplish this disable QSM interrupts or set the interrupt priority level mask in the CPU16 condition code register to a value higher than the IRQ level requested by the QSM The SCI receiver and transmitter should be disabled after transfers in progress are complete The QSPI can be halted by setting the HALT bit in SPCRS and then setting STOP after the HALTA flag is set Refer to 5 3 4 Low Power Operation for more information about low power stop mode QUEUED SERIAL MODULE M68HC16 Z SERIES 9 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 9 2 1 2 Freeze Operation The freeze FRZ 1 0 bits in 5 are used to determine what act
404. ever is set Because receiver status flags are set at the same time as RDRF they do not have separate interrupt enables 10 4 5 7 Idle Line Detection During a typical serial transmission frames are transmitted isochronally and no idle time occurs between frames Even when all the data bits in a frame are logic ones the start bit provides one logic zero bit time during the frame An idle line is a sequence of contiguous ones equal to the current frame size Frame size is determined by the state of the M bit in SCCR1 SCI receiver has both short and long idle line detection capability Idle line detec tion is always enabled The idle line type ILT bit in SCCR1 determines which type of detection is used When an idle line condition is detected the IDLE flag in SCSR is set For short idle line detection the receiver bit processor counts contiguous logic one bit times whenever they occur Short detection provides the earliest possible recognition of an idle line condition because the stop bit and contiguous logic ones before and after it are counted For long idle line detection the receiver counts logic ones after the stop bit is received Only a complete idle frame causes the IDLE flag to be set M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL 10 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc In some applications software overhead can cause a b
405. fer to 5 8 Interrupts For more information on exceptions refer to 4 13 4 Types of Exceptions 11 5 Pin Descriptions The GPT uses 12 of the MCU pins Each pin can perform more than one function De scriptions of GPT pins divided into functional groups follow 11 5 1 Input Capture Pins Each input capture pin is associated with a single GPT input capture function Each pin has hysteresis Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored Each pin has an associated 16 bit capture register that holds the captured counter value These pins can also be used for general purpose I O Refer to 11 8 2 Input Capture Functions for more in formation 11 5 2 Input Capture Output Compare Pin The input capture output compare pin can be configured for use by either an input cap ture or an output compare function It has an associated 16 bit register that is used for holding either the input capture value or the output match value When used for input capture the pin has the same hysteresis as other input capture pins The pin can be used for general purpose I O Refer to 11 8 2 Input Capture Functions and 11 8 3 Output Compare Functions for more information 11 5 3 Output Compare Pins Output compare pins are used for GPT output compare functions Each pin has an as sociated 16 bit compare register and a 16 bit comparator Pins OC2 OC3 and OC4 are associated with a specific outp
406. frequency REGISTER SUMMARY M68HC16 Z SERIES D 12 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 128 Divide Ratio Specified by SWP and SWT 1 0 Time out Period ref The following equation calculates the time out period for an externally input clock fre quency on both slow and fast reference frequency devices when fsys is equal to the system clock frequency Divide Ratio Specified by SWP and SWTT 1 0 f sys Time out Period HME Halt Monitor Enable 0 Halt monitor is disabled 1 Halt monitor is enabled BME Bus Monitor External Enable 0 Disable bus monitor for external bus cycles 1 Enable bus monitor for external bus cycles BMT 1 0 Bus Monitor Timing This field selects the bus monitor time out period Refer to Table D 7 Table D 7 Bus Monitor Time Out Period BMT 1 0 Bus Monitor Time Out Period 64 system clocks 32 system clocks 16 system clocks 11 8 system clocks D 2 13 Periodic Interrupt Control Register PICR Periodic Interrupt Control Register YFFA22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PICR sets the interrupt level and vector number for the periodic interrupt timer PIT Bits 10 0 can be read or written at any time Bits 15 11 are unimplemented and al ways read zero PIRQL 2 0 Periodic Interrupt Request Le
407. g the freeze software watchdog FRZSW bit dis ables the software watchdog and the periodic interrupt timer when FREEZE is asserted M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 3 Go to www freescale com Freescale Semiconductor Inc 5 3 System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus Because the MCU is a fully static design register and memory contents are not affected when the clock rate changes System hardware and software support changes in clock rate during operation The system clock signal can be generated from one of three sources An internal phase locked loop PLL can synthesize the clock from a fast reference a slow refer ence or the clock signal can be directly input from an external frequency source NOTE Whether the PLL can use a fast or slow reference is determined by the device A particular device cannot use both a fast and slow refer ence The fast reference is typically a 4 194 MHz crystal the slow reference is typically 32 768 kHz crystal Each reference frequency may be generated by sources other than a crystal Keep these sources in mind while reading the rest of this section Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for clock specifications Figure 5 2 is a block diagram of the clock submodule CRYSTAL 1 128 PHASE LOW PASS OSCILLATOR us COMPARA
408. ge signals for an ex ternal device Refer to 5 9 Chip Selects for more information M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 33 Go to www freescale com Freescale Semiconductor Inc Table 5 15 Effect of DSACK Signals DSACK1 DSACKO Result 1 1 Insert wait states in current bus cycle 1 0 Complete cycle Data bus port size is eight bits 0 1 Complete cycle Data bus port size is sixteen bits 0 0 Reserved If the CPU is executing an instruction that reads a long word operand from a 16 bit port the MCU latches the 16 bits of valid data and then runs another bus cycle to ob tain the other 16 bits The operation for an 8 bit port is similar but requires four read cycles The addressed device uses the DSACK signals to indicate the port width For instance a 16 bit external device always returns DSACK for a 16 bit port regardless of whether the bus cycle is a byte or word operation Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed A 16 bit port must reside on data bus bits 15 0 and an 8 bit port must reside on data bus bits 15 8 This minimizes the number of bus cycles needed to transfer data and ensures that the MCU transfers valid data The MCU always attempts to transfer the maximum amount of data on all bus cycles For a word operation it is assumed that the
409. gister fields are also satisfied when a match occurs the associated chip select signal is asserted Table 5 24 shows BLKSZ 2 0 encoding Table 5 24 Block Size Encoding BLKSZ 2 0 Block Size Address Lines Compared 000 ADDR 23 11 001 ADDR 23 13 010 16 Kbytes ADDR 23 14 011 64 Kbytes ADDR 23 16 100 128 Kbytes ADDR 23 17 101 256 Kbytes ADDR 23 18 110 ADDR 23 19 111 ADDR 23 20 NOTES 1 ADDR 23 20 are the same logic level as ADDR19 during normal op eration M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 65 Go to www freescale com Freescale Semiconductor Inc The chip select address compare logic uses only the most significant bits to match an address within a block The value of the base address must be an integer multiple of the block size Because the logic state of ADDR 23 20 follows that of ADDR19 in the CPU16 maxi mum block size is 512 Kbytes and addresses from 080000 to F7FFFF are inacces sible After reset the MCU fetches the initialization routine from the address contained in the reset vector located beginning at address 000000 of program space To support bootstrap operation from reset the base address field in the boot chip select base ad dress register CSBARBT has a reset value of 000 which corresponds to a base ad dress of 000000 and a block size of 512 Kbytes A memory device containing the reset vector and initia
410. gnals remain in the same state If HALT is still asserted once bus mastership is returned to the MCU the ad dress function code size and read write signals are again driven to their previous states The MCU does not service interrupt requests while it is halted Refer to 5 6 5 Bus Exception Control Cycles for further information 5 5 1 11 Autovector Signal The autovector signal AVEC can be used to terminate external interrupt acknowledg ment cycles Assertion of AVEC causes the CPU16 to generate vector numbers to lo cate an interrupt handler routine If AVEC is continuously asserted autovectors are generated for all external interrupt requests AVEC is ignored during all other bus cy cles Refer to 5 8 Interrupts for more information AVEC for external interrupt re quests can also be supplied internally by chip select logic Refer to 5 9 Chip Selects for more information The autovector function is disabled when there is an external bus master Refer to 5 6 6 External Bus Arbitration for more information 5 5 2 Dynamic Bus Sizing The MCU dynamically interprets the port size of an addressed device during each bus cycle allowing operand transfers to or from 8 bit and 16 bit ports During a bus transfer cycle an external device signals its port size and indicates com pletion of the bus cycle to the MCU through the use of the DSACK inputs as shown in Table 5 15 Chip select logic can generate data size acknowled
411. hat indicates the end of a data frame Frame A complete unit of serial information The SCI can use 10 bit or 11 bit frames Data Frame A start bit a specified number of data or information bits and at least one stop bit Idle Frame A frame that consists of consecutive ones An idle frame has no start bit Break Frame A frame that consists of consecutive zeros A break frame has no stop bits M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL 10 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 4 5 2 Serial Formats All data frames must have a start bit and at least one stop bit Receiving and transmit ting devices must use the same data frame format The SCI provides hardware sup port for both 10 bit and 11 bit frames The M bit in SCCR1 specifies the number of bits per frame The most common data frame format for NRZ serial interfaces is one start bit eight data bits LSB first and one stop bit a total of ten bits The most common 11 bit data frame contains one start bit eight data bits a parity or control bit and one stop bit Ten bit and eleven bit frames are shown in Table 10 6 Table 10 6 Serial Frame Formats 10 Bit Frames Start Data Parity Control Stop 1 7 2 1 7 1 1 1 8 1 11 Bit Frames Start Data Parity Control Stop 1 7 1 2 1 8 1 1 10 4 5 3 Baud Clock The SCI baud rate is prog
412. he last command in the queue is executed New receive data overwrites previously received data in re ceive RAM Each time the end of the queue is reached the SPIF flag is set SPIF is not automatically reset If interrupt driven QSPI service is used the service routine must clear the SPIF bit to end the current interrupt request Additional interrupt re quests during servicing can be prevented by clearing SPIFIE but SPIFIE is buffered Clearing it does not end the current request Wrap around mode is exited by clearing the WREN bit or by setting the HALT bit in SPCR3 Exiting wrap around mode by clearing SPE is not recommended as clearing SPE may abort a serial transfer in progress The QSPI sets SPIF clears SPE and stops the first time it reaches the end of the queue after WREN is cleared After HALT is set the QSPI finishes the current transfer then stops executing commands After the QSPI stops SPE can be cleared M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 19 Go to www freescale com Freescale Semiconductor Inc 9 3 5 3 Slave Mode Clearing the MSTR bit in SPCRO selects slave mode operation In slave mode the QSPI is unable to initiate serial transfers Transfers are initiated by an external SPI bus master Slave mode is typically used on a multi master SPI bus Only one device can be bus master operate in master mode at any given time Before QSPI operation is initiated Q
413. he reset vector consist of one word and reside in data space The reset vector consists of four words that reside in program space Refer to SECTION 5 SYSTEM INTEGRATION MODULE for information concerning address space types and the function code outputs There are 52 predefined or reserved vectors and 200 user defined vectors Each vector is assigned an 8 bit number Vector numbers for some exceptions are generated by external devices others are supplied by the processor There is a direct mapping of vector number to vector table address The processor left shifts the vector number one place multiplies by two to convert it to an address M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 37 Go to www freescale com Freescale Semiconductor Inc Table 4 5 Exception Vector Table Vector Vector Address Type of Number Address Space Exception 0 0000 P Reset Initial ZK SK and PK 0002 Reset Initial PC 0006 Reset Initial IZ Direct Page 000A Bus Error i 000E Illegal Instruction 9 0012 001C Unassigned Reserved 10 0020 Unassigned Reserved ae 9 12 0024 Level 2 Interrupt Autovector 14 0028 Level 4 Interrupt Autovector eae ot 16 002C Level 6 Interrupt Autovector 18 0030 Spurious Interrupt 38 FF 0070 01FE D User Defined Interrupts
414. he selected clock but are high for only one system clock time The prescaler also supplies three clock signals to the pulse accumulator clock select mux These are the system clock divided by 512 the external clock signal from the PCLK pin and the capture compare clock signal 8 Capture Compare Unit The capture compare unit contains the timer counter TCNT the input capture IC functions and the output compare OC functions Figure 11 3 is a block diagram of the capture compare unit 11 8 1 Timer Counter The timer counter TCNT is the key timing component in the capture compare unit The timer counter is a 16 bit free running counter that starts counting after the proces sor comes out of reset The counter cannot be stopped during normal operation After reset the GPT is configured to use the system clock divided by four as the input to the counter The prescaler divides the system clock and provides selectable input fre quencies User software can configure the system to use one of seven prescaler out puts or an external clock The counter can be read any time without affecting its value Because the GPT is in terfaced to the IMB and the IMB supports a 16 bit bus a word read gives a coherent value If coherency is not needed byte accesses can be made The counter is set to 0000 during reset and is normally a read only register In test mode and freeze mode any value can be written to the timer counter When the counter r
415. hen the first command in a queue is executing CPTQP 3 0 con tains either the reset value 0 or a pointer to the last command completed in the previous queue D 6 14 Receive Data RAM RR 0 F Receive Data RAM YFFDOO YFFD1F Data received by the QSPI is stored in this segment The CPU16 reads this segment to retrieve data from the QSPI Data stored in receive RAM is right justified Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the indi vidual queue entry Receive RAM data can be accessed using byte word or long word addressing M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 51 Go to www freescale com Freescale Semiconductor Inc D 6 15 Transmit Data RAM TR 0 F Transmit Data RAM YFFD20 YFFD3F Data that is to be transmitted by the QSPI is stored in this segment The CPU16 nor mally writes one word of data into this segment for each queue command to be exe cuted Information to be transmitted must be written to the transmit data RAM right justified format The QSPI cannot modify information in the transmit data RAM The QSPI copies the information to its data serializer for transmission Information re mains in the transmit RAM until overwritten D 6 16 Command RAM CR 0 F Command RAM YFFD40 YFFD4F 7 6 5 4 3 2 1 0 CONT BITSE DT DSCK PCS3 PCS2 51 pcsot CONT BITSE DSCK
416. hes higher priority exception processing or reaches an instruc tion boundary B Processor state is stacked then the CCR PK extension field is cleared C The interrupt acknowledge cycle begins 1 FC 2 0 are driven to 96111 CPU space encoding 2 The address bus is driven as follows ADDR 23 20 961111 ADDR 19 16 961111 which indicates that the cycle is an interrupt acknowledge CPU space cycle ADDR 15 4 111111111111 ADDR 3 1 the priority of the interrupt request being acknowledged and ADDRO 1 SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 60 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 3 Request priority is latched into the CCR IP field from the address bus D Modules or external peripherals that have requested interrupt service decode the priority value in ADDR S 1 If request priority is the same as acknowledged priority arbitration by IARB contention takes place E After arbitration the interrupt acknowledge cycle is completed in one of the fol lowing ways 1 When there is no contention IARB 960000 the spurious interrupt monitor asserts BERR and the CPU16 generates the spurious interrupt vector number 2 The dominant interrupt source supplies a vector number and DSACK sig nals appropriate to the access The CPU16 acquires the vector number 3 The AVEC signal is asserted the signal can be asserted by the dominant interrupt sour
417. hese instruc tions contain a 20 bit effective address that is zero extended to 24 bits to give the in struction an even number of bytes 4 6 3 Indexed Addressing Modes In the indexed modes registers IX IY and IZ together with their associated extension fields are used to calculate the effective address For 8 bit indexed modes an 8 bit unsigned offset contained in the instruction is added to the value contained in an index register and its extension field For 16 bit modes a 16 bit signed offset contained in the instruction is added to the val ue contained in an index register and its extension field For 20 bit modes a 20 bit signed offset zero extended to 24 bits is added to the val ue contained in an index register These modes are used for JMP and JSR instructions only 4 6 4 Inherent Addressing Mode Inherent mode instructions use information directly available to the processor to deter mine the effective address Operands if any are system resources and are thus not fetched from memory 4 6 5 Accumulator Offset Addressing Mode Accumulator offset modes form an effective address by sign extending the content of accumulator E to 20 bits then adding the result to an index register and its associated extension field This mode allows use of an index register and an accumulator within a loop without corrupting accumulator D 4 6 6 Relative Addressing Modes Relative modes are used for branch and long branch instruction
418. hronously us ing the microcontroller CLKOUT signal Refer to the CPU16 Reference Manual CPU16RM AD for more information on the CLKOUT signal state signals and state signal demux logic 4 14 1 2 Combining Opcode Tracking with Other Capabilities Pipeline state signals are useful during normal instruction execution and execution of exception handlers The signals provide a complete model of the pipeline up to the point a breakpoint is acknowledged Breakpoints are acknowledged after an instruction has executed when it is in pipeline stage C A breakpoint can initiate either exception processing or background debug mode IPIPEO IPIPE1 are not usable when the CPU16 is in background debug mode 4 14 2 Breakpoints Breakpoints are set by assertion of the microcontroller BKPT pin The CPU16 supports breakpoints on any memory access Acknowledged breakpoints can initiate either ex ception processing or background debug mode After BDM has been enabled the CPU16 will enter BDM when the BKPT input is asserted e If BKPT assertion is synchronized with an instruction prefetch the instruction is tagged with the breakpoint when it enters the pipeline and the breakpoint occurs after the instruction executes If BKPT assertion is synchronized with an operand fetch breakpoint processing occurs at the end of the instruction during which BKPT is latched M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On Th
419. ic and number A15 is bit 15 of accumulator A ADDR7 is line 7 of the address bus CSORO is chip select op tion register 0 A range of mnemonics is referred to by mnemonic and the numbers that define the range VBR 4 0 are bits four to zero of the vector base register CSORJ 0 5 are the first six chip select option registers Parentheses are used to indicate the content of a register or memory location rather than the register or memory location itself For example A is the content of accumu lator M 1 is the content of the word at address M LSB means least significant bit or bits MSB means most significant bit or bits Refer ences to low and high bytes are spelled out LSW means least significant word or words MSW means most significant word or words ADDR is the address bus ADDR 7 0 are the eight LSB of the address bus DATA is the data bus DATA 15 8 are the eight MSB of the data bus NOMENCLATURE M68HC16 Z SERIES 2 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 3 OVERVIEW This section provides general information on M68HC16 Z series MCUs It lists fea tures of each of the modules shows device functional divisions and pin assignments summarizes signal and pin functions discusses the intermodule bus and provides system memory maps Timing and electrical specifications for the entire microcontrol ler and for individual modules are
420. ift Count Used for factory test only D 2 24 Test Module Repetition Count Register TSTRC Test Module Repetition Count Used for factory test only D 2 25 Test Module Control Register CREG Test Module Control Register Used for factory test only D 2 26 Test Module Distributed Register DREG Test Module Distributed Register Used for factory test only REGISTER SUMMARY D 22 For More Information On This Product Go to www freescale com YFFA30 YFFA32 YFFA34 YFFA36 YFFA38 YFFA3A M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc D 3 Standby RAM Module Table D 19 shows the SRAM address map Table D 19 SRAM Address Map Address 15 0 YFFBOO RAM Module Configuration Register RAMMCR YFFBO2 RAM Test Register RAMTST YFFB04 RAM Array Base Address Register High RAMBAH YFFBOG RAM Array Base Address Register Low RAMBAL NOTES 1 Y 2 M111 where M is the logic state of the module mapping MM bit in the SIMCR D 3 1 RAM Module Configuration Register RAMMCR RAM Module Configuration Register YFFBOO 15 11 9 8 0 STOP 0 0 0 RLCK 0 RASP 1 0 NOT USED RESET 1 0 0 0 0 0 1 1 STOP Low Power Stop Mode Enable 0 SRAM operates normally 1 SRAM enters low power stop mode This bit controls whether SRAM operates normally or enters low power stop mode In low power stop mode the array retains its contents but ca
421. igh Low Time 2 4 2A Pulse Width CLKOUT Rise and Fall Time txcHL 19 8 Clock High to ADDR FC SIZ Valid m 1 1 3 5 7 8 1 1 9 2 4A 5A Rise Fall Time All Outputs except CLKOUT 4B 5B External Clock Input Rise and Fall Time Clock High to ADDR Data FC SIZ High Impedance Clock High to ADDR FC SIZ Invalid Clock Low to AS DS CS Asserted 1 tCHAZx tCHAZn 12 Clock Low to AS DS CS Negated AS 55725 14 DS CS Negated to ADDR FC SIZ Invalid Address Hold S and DS Read Width Asserted 14A DS CS Width Asserted Write 2 AS CS and DS Read Width Asserted Fast Cycle tswow 15 AS DS CS Width Negated teN 0 0 0 2 A AS to DS or CS Asserted Read tstsa 1 11 ADDR FC SIZE Valid to AS CS and DS Read Asserted 2 8 2 2 Clock High to AS DS R W High Impedance 0 5 5 2 2 0 tsNRN 1 16 17 18 20 1 AS DS CS Negated to R W High Clock High to R W High Clock High to R W Low 21 R W High to AS CS Asserted 0 0 tRAAA 10 22 R Low to DS CS Asserted Write 23 Clock High to Data Out Valid 24 Data Out Valid to Negating Edge of AS CS Fast Write Cycle 2 13 14 ES ER ES EN tRASA 40 tcHDO tbvasN 25 05 CS Negated to Data Out Invalid Data Out Hold 26 Data Out Valid to DS CS Asserted Write 27 Data I
422. ight IND16 X 0 A A Word IND16 Y IND16 Z EXT MAC Multiply and HR IR gt E D A A A Accumulate E D Signed 16 Bit Qualified IX gt IX Fractions Qualified IY IY HR IZ M M 1 x HR M M 1 y S IR MOVB Move Byte Mi 2 Mo IXP to EXT ff hh Il AO EXT to IXP ff hh Il EXT to hh Il hh Il EXT MOVW Move Word 1 1 gt IXP to EXT ff hh Il 0 EXT to IXP ff hh Il EXT to hh Il hh Il EXT MUL Multiply INH 10 A NEG Negate Memory IND8 X 8 AAA IND8 Y 8 IND8 Z 8 IND16 X 8 IND16 Y 8 IND16 Z 8 EXT 8 NEGA Negate A INH 2 A AAA NEGB Negate B 00 B B INH 3712 A AAA NEGD Negate D 0000 D D INH 27F2 mr JA AAA NEGE Negate E 0000 E 2 E INH 2772 a A A NEGW Negate Memory Word 0000 M M 1 IND16 X 2702 999g 8 A gt 1 14016 Y 2712 9999 8 IND16 2 2722 9999 8 2732 hh Il 8 NOP Null Operation INH 274C 2 CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 22 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic ORAA ORAB Operation Description Address Instruction Condition Codes Mode IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z
423. igital control subsystem 8 6 signal processing DSP 4 45 Divider counter 5 6 Double buffered 9 27 9 28 10 19 10 20 bus fault 5 45 DREG D 22 Driver types 3 12 DS 4 41 5 31 5 37 5 40 5 45 5 47 5 51 DSACK 5 24 5 32 5 37 5 41 5 43 5 54 5 60 5 65 5 66 5 67 5 68 external internal generation 5 40 option fields 5 40 signal effects 5 34 source specification in asynchronous mode 5 66 D 19 DSCK D 53 DSCKL D 49 DSCLK 4 44 5 53 DSI 5 53 DSO 5 53 DSP 4 45 DT D 53 DTL D 49 Dynamic bus sizing 5 33 For More Information On This Product Es EBI 5 60 ECLK 5 21 bus timing 16 78 MHz A 41 20 97 MHz A 42 25 17 MHz A 43 low voltage A 40 output timing diagram A 28 timing diagram A 44 EDGE D 72 Edge detection logic 11 12 EDGExAPB 11 12 EDIV 5 21 D 8 EK 4 5 Electrical characteristics A 1 EMUL D 26 Emulation mode control EMUL D 26 Ending queue pointer ENDQP D 50 9 8 D 50 EQUATES ASM E 2 Error conditions 9 28 10 21 detection circuitry 9 2 EV 4 4 Event counting mode 11 15 Exception asynchronous 4 39 definition 4 37 multiple 4 40 processing 5 48 sequence 4 39 stack frame 4 38 format 4 38 synchronous 4 39 types 4 39 vector 4 37 5 48 table 4 38 Execution process 4 36 unit 4 35 EXOFF D 6 EXT D 8 EXTAL 5 5 5 56 Extended addressing modes 4 10 Extension bit overflow flag EV 4 4 field SK 4 3 fields 4 6 External bus arbitration 5 46 clock division bit EDIV 5 21 D 8 op
424. igital input only and all digital input output pins must not exceed 10 mA Exceeding this limit can cause disruption of normal operation 500 to 500 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 2 Typical Ratings 2 7 to 3 6V 16 78 MHz Operation Num Rating Symbol Value Unit 1 Supply Voltage Vpp 3 0 V 2 Operating Temperature Ta 25 Vpp Supply Current 3 RUN 38 LPSTOP VCO off 70 LPSTOP External clock max fsys 1 mA 4 Clock Synthesizer Operating Voltage Vopsyn 3 0 V Vppsvu Supply Current 4 194 MHz VCO on maximum fsys TBD mA 32 768 kHz VCO on maximum fsys 200 4 194 MHz External Clock maximum fsys TBD 5 32 768 kHz External Clock maximum fsys IppsvN 1 mA 4 194 MHz LPSTOP VCO off TBD mA 32 768 kHz LPSTOP VCO off 20 4 194 MHz powered down TBD 32 768 kHz Vpp powered down 10 uA 6 RAM Standby Voltage Vsp 3 V RAM Standby Current 7 Normal RAM operation Isp 3 Standby operation 3 8 Power Dissipation Pp 120 mW ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 3 Typical Ratings 5V 16 78 MHz Operation Num Rating Symbol Value Unit Supply Voltage Operating Temperature Vpp S
425. igure a peripheral chip select set the appropriate bit in PQSPAR then config ure the chip select pin as an output by setting the appropriate bit in DDRQS The value of the bit in PORTQS that corresponds to the chip select pin determines the base state of the chip select signal If base state is zero chip select assertion must be active high PCS bit in command RAM must be set if base state is one assertion must be active low PCS bit in command RAM must be cleared PORTQS bits are cleared during re set If no new data is written to PORTQS before pin assignment and configuration as an output the base state of chip select signals is zero and chip select pins should thus be driven active high 9 4 Serial Communication Interface The serial communication interface SCI communicates with external devices through an asynchronous serial bus The SCI uses a standard non return to zero NRZ trans mission format The SCI is fully compatible with other Freescale SCI systems such as those on M68HC11 and M68HC05 devices Figure 9 10 is a block diagram of the SCI transmitter Figure 9 11 is a block diagram of the SCI receiver M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 21 Go to www freescale com Freescale Semiconductor Inc WRITE ONLY SCDR Tx BUFFER TRANSMITTER BAUD RATE CLOCK H H 10 11 BIT Tx SHIFT REGISTER 5 L 7 65 43 2100 PARITY GENERATOR
426. igure the counter to use one of seven prescaler outputs or an external clock input from the PCLK pin The PWM count register PWMCNT can be read at any time without affecting its val ue A read must be a word access to ensure coherence but byte accesses can be made if coherence is not needed The counter is cleared to 0000 during reset and is a read only register except in freeze or test mode Fifteen of the sixteen counter bits are output to multiplexers A and B The multiplexers provide the fast and slow modes of the PWM unit Mode for PWMA is selected by the SFA bit in the PWM control register C PWMC Mode for PWMB is selected by the SFB bit in the same register PWMA PWMB and PPR 2 0 bits in PWMC control PWM output frequency In fast mode bits 7 0 of PWMCNT are used to clock the PWM logic in slow mode bits 14 7 are used The period of a PWM output in slow mode is 128 times longer than the fast mode period Table 11 3 shows a range of PWM output frequencies using 16 78 MHz 20 97 MHz and 25 17 MHz system clocks Table 11 3 PWM Frequency Ranges PPR Prescaler Tap SFA B 0 SFA B 1 2 0 16 78 MHz 20 97 MHz 25 17 MHz 16 78 MHz 20 97 MHz 25 17 MHz 16 78 MHz 20 97 MHz 25 17 MHz 000 Div 2 8 32 MHz Div2 10 5 MHz Div2 12 6 MHz 32 8 kHz 41 kHz 49 2 kHz 256 Hz 320 Hz 384 Hz 001 Div42 4 19 MHz Div4 5 25 MHz Div4 6 29MHz 16 4kHz 20 5kHz 24 6 kHz 128 Hz 160 Hz 192 Hz 010 Div8 2 10 MHz Div8
427. igured for general purpose discrete input and output Al though these pins are organized into two ports port E and port F function assignment is by individual pin PE3 is not connected to a pin PE3 returns zero when read and writes have no effect Pin assignment registers data direction registers and data reg isters are used to implement discrete 5 10 1 Pin Assignment Registers Bits in the port E and port F pin assignment registers PEPAR and PFPAR control the functions of the pins on each port Any bit set to one defines the corresponding pin as a bus control signal Any bit cleared to zero defines the corresponding as an I O returns one when read and writes have no effect 5 10 2 Data Direction Registers Bits in the port E and port F data direction registers DDRE and DDRF control the di rection of the pin drivers when the pins are configured as I O Any bit in a register set to one configures the corresponding pin as an output Any bit in a register cleared to zero configures the corresponding pin as an input These registers can be read or writ ten at any time DDES returns zero when read Writes have no effect SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 9 70 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 10 3 Data Registers A write to the port E and port F data registers PORTE 0 1 PORTF 0 1 is stored in an internal d
428. imum Vpp Ipp IDDSYN Isp Maximum Ippa 156 includes supply currents for all device modules powered by Vpp pins M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 11 Go to www freescale com Freescale Semiconductor Inc Table A 12 16 78 MHz DC Characteristics Vg and Vppsyy 5 0 10 Veg 0 T T to T Characteristic Input High Voltage Input Low Voltage Input Hysteresis 2 Input Leakage Current Vin Vpp Or Vss 14 5 High Impedance Off State Leakage Curren Vin Vss CMOS Output High Voltage 6 7 lou 10 0 CMOS Output Low Voltage 8 lot 10 0 HA Output High Voltage 9 7 lou 0 8 mA Output Low Voltage 9 lot 1 6mA lot 5 3 12mA Three State Control Input High Voltage Data Bus Mode Select Pull Up Current 10 11 Vin lusp 120 MC68HC16Z1 Vpp Supply Current 12 13 12 Run 110 LPSTOP crystal VCO STSIM 0 DD 350 LPSTOP external clock input frequency maximum zu 5 mA MC68HC16Z2 Z3 Vpp Supply Current 12 13 12A Run 113 mA LPSTOP crystal VCO Off STSIM 0 DD 2 mA LPSTOP external clock input frequency maximum fsys 10 mA 13 Clock Synthesizer Operating Voltage 4 5 5 5 V MC68HC16Z1 Vppsyw Supply Current 13 VCO on
429. ing a bit assigns the pin to I O port E PE3 is not connected to a pin can be read and written but has no function Bits 15 8 are unimplemented and will always read zero Table D 4 displays port E pin assignments Table D 4 Port E Pin Assignments PEPAR Bit Port E Signal Bus Control Signal PEPA7 PE7 171 PEPA6 PE6 SIZO PEPA5 PE5 AS PEPA4 PE4 DS 2 2 PEPA1 PE1 DSACK1 PEPAO PEO DSACKO NOTES 1 The CPU16 does not support the RMC function for this pin This bit is not connected to a pin for I O usage D 2 9 Port F Data Register PORTFO Port F Data Register 0 YFFA18 PORTF1 Port F Data Register 1 YFFA1A 15 8 7 6 5 4 3 2 1 0 NOT USED 4 PF2 1 PFO RESET U U U U U U U U This register can be accessed in two locations and can be read or written at any time A write to this register is stored in an internal data latch and if any pin in the corre REGISTER SUMMARY M68HC16 Z SERIES D 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc sponding port is configured as an output the value stored for that bit is driven out on the pin A read of this data register returns the value at the pin only if the pin is config ured as a discrete input Otherwise the value read is the value stored in the register Bits 15 8 are unimplemented and wi
430. ing a bus state analyzer a simple serial interface and a terminal 4 14 1 Deterministic Opcode Tracking The CPU16 has two multiplexed outputs IPIPEO and IPIPE1 that enable external hardware to monitor the instruction pipeline during normal program execution The sig nals IPIPEO and IPIPE1 can be demultiplexed into six pipeline state signals that allow a state analyzer to synchronize with instruction stream activity CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 40 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 14 1 1 IPIPEO IPIPE1 Multiplexing Six types of information are required to track pipeline activity To generate the six state signals eight pipeline states are encoded and multiplexed into IPIPEO and 1 The multiplexed signals have two phases State signals are active low Table 4 6 shows the encoding scheme Table 4 6 IPIPEO IPIPE1 Encoding Phase IPIPE1 State IPIPEO State State Signal Name START and FETCH FETCH START NULL INVALID ADVANCE EXCEPTION NULL IPIPEO and IPIPE1 are timed so that a logic analyzer can capture all six pipeline state signals and address data or control bus state in any single bus cycle Refer to AP PENDIX A ELECTRICAL CHARACTERISTICS for specifications State signals can be latched asynchronously on the falling and rising edges of either address strobe AS or data strobe DS They can also be latched sync
431. ing exception processing of a previous exception are processed before the first instruction of that exception s han routine The converse is not true If an interrupt occurs during bus error exception processing for example the first instruction of the exception handler is executed be fore interrupts are sensed This permits the exception handler to mask interrupts dur ing execution Refer to SECTION 5 SYSTEM INTEGRATION MODULE for detailed information con cerning interrupts and system reset For information concerning processing of specific exceptions refer to the CPU16 Reference Manual CPU16RM AD 4 13 6 RTI Instruction The return from interrupt instruction RTI must be the last instruction in all exception handlers except the RESET handler RTI pulls the exception stack frame that was pushed onto the system stack during exception processing and restores processor state Normal program flow resumes at the address of the instruction that follows the last instruction executed before exception processing began RTI is not used in the RESET handler because RESET initializes the stack pointer and does not create a stack frame 4 14 Development Support The CPU16 incorporates powerful tools for tracking program execution and for system debugging These tools are deterministic opcode tracking breakpoint exceptions and background debug mode Judicious use of CPU16 capabilities permits in circuit emu lation and system debugging us
432. ing on the address read ANALOG TO DIGITAL CONVERTER For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table 8 8 Multiple Channel Conversions MULT 1 S8CM CD CC CB CA Input Result Register 0 0 0 X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 0 0 1 X X AN4 RSLTO AN5 RSLT1 AN6 RSLT2 AN7 RSLT3 0 1 0 X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 0 1 1 X X RSLTO VRL RSLT1 VRL 2 RSLT2 Test Reserved RSLT3 1 0 X X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 AN4 RSLT4 AN5 RSLT5 AN6 RSLT6 AN7 RSLT7 1 1 X X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 RSLT4 VRL RSLT5 Vn 2 RSLT6 Test Reserved RSLT7 NOTES 1 Result register RSLT is either RJURRX LJSRRX or LJURRX depending on the address read M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 7 6 Conversion Timing 8 12 Total conversion time is made up of initial sample time transfer time final sample time and resolution time Initial sample time is the time during which a selected input chan nel is connected to the sample buffer amplifier through a sample capacitor During transfer time the sample capacitor is disconnected from the multiplexer and the RC DAC
433. int lies between bits 31 and 30 There are 31 bits of magnitude The range of values is 1 80000000 to 1 2 7FFFFFFF CENTRAL PROCESSOR UNIT M68HC16 Z SERIES 4 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Signed 36 bit fixed point numbers are used only by the MAC unit Bit 35 is the sign bit Bits 34 31 are sign extension bits There is an implied radix point between bits 31 and 30 There are 31 bits of magnitude but use of the extension bits allows representation of numbers in the range 16 800000000 to 15 999969482 7FFFFFFFF 4 5 Memory Organization Both program and data memory are divided into sixteen 64 Kbyte banks Addressing is linear A 20 bit extended address can access any byte location in the appropriate address space A word is composed of two consecutive bytes A word address is normally an even byte address Byte 0 of a word has a lower 16 bit address than byte 1 Long words and 32 bit signed fractions consist of two consecutive words and are normally accessed at the address of byte 0 in word 0 Instruction fetches always access word addresses Word operands are normally ac cessed at even byte addresses but can be accessed at odd byte addresses with a substantial performance penalty To permit compatibility with the M68HC1 1 misaligned word transfers and misaligned stack accesses are allowed Transferring a misaligned word requires
434. ion providing an application with full flexi bility in using the dual SCI system References to SCI registers in this section do not always distinguish between the two SCI systems A reference to SCCR1 for example applies to both SCCR1A SCIA control register 1 and SCCR1B SCIB control register 1 10 4 1 SCI Registers The SCI programming model includes the MCCI global and pin control registers and eight SCI registers Each of the two SCI units contains two SCI control registers one status register and one data register Refer to D 7 9 SCI Control Register 0 D 7 11 SCI Status Register and D 7 12 SCI Data Register for register bit and field defini tions All registers may be read or written at any time by the CPU Rewriting the same value to any SCI register does not disrupt operation however writing a different value into an SCI register when the SCI is running may disrupt operation To change register val ues the receiver and transmitter should be disabled with the transmitter allowed to fin ish first The status flags in the SCSR may be cleared at any time When initializing the SCI set the transmitter enable TE and receiver enable RE bits in SCCR1 last A single word write to SCCR1 can be used initialize the SCI and en able the transmitter and receiver 10 4 1 1 SCI Control Registers SCCRO contains the baud rate selection field The baud rate must be set before the SCI is enabled The CPU16 can read and write thi
435. ion Control Register SYPCR System Protection Control Register YFFA20 15 8 7 6 5 4 3 2 1 0 NOT USED SWE SWP SWT 1 0 HME BME BMT 1 0 RESET 1 MODCLK 0 0 0 0 0 0 This register controls system monitor functions software watchdog clock prescaling and bus monitor timing This register can be written once following power on or reset Bits 15 8 are unimplemented and will always read zero SWE Software Watchdog Enable 0 Software watchdog is disabled 1 Software watchdog is enabled SWP Software Watchdog Prescaler This bit controls the value of the software watchdog prescaler 0 Software watchdog clock is not prescaled 1 Software watchdog clock is prescaled by 512 The reset value of SWP is the complement of the state of the MODCLK pin during reset SWT 1 0 Software Watchdog Timing This field selects the divide ratio used to establish the software watchdog time out pe riod Refer to Table D 6 Table D 6 Software Watchdog Divide Ratio SWP SWT 1 0 Divide Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 The following equation calculates the time out period for a slow reference frequency where is equal to the EXTAL crystal frequency Divide Ratio Specified by SWP and SWTT 1 0 Time out Period ref The following equation calculates the time out period for a fast reference frequency where is equal to the EXTAL crystal
436. ion On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 4 2 7 Multiply and Accumulate Registers 4 5 4 3 Memory Management 4 5 4 3 1 een ne ee eterna m 4 6 4 3 2 Extension Fields Lune cues elediedesun creo bc embaidodoniedcuebuib reped duse biis 4 6 4 4 T M 4 6 4 5 Memory p m RR E Tm 4 7 4 6 Addressing PROCUL 4 8 4 6 1 Immediate Addressing Modes siascsenicsctisedscsrcedessssnasdennnaranivarnnedencsnnes 4 9 4 6 2 Extended Addressing Modes 4 10 4 6 3 Indexed Addressing Modes 4 10 4 6 4 Inherent Addressing Mode 4 00242 221 4 10 4 6 5 Accumulator Offset Addressing 4 10 4 6 6 Relative Addressing Modes das 4 10 4 6 7 Post Modified Index Addressing 4 10 4 6 8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode 4 11 4 7 Lic gere Soe OT 4 11 4 7 1 instruction GET 4 11 4 8 Comparison of CPU16 and M68HC11 CPU Instruction Sets 4 31 4 9 nk HRHREEREH RH OR ARA UN ER EHEREERRO GER CURRERE HER DRO RR EUER Ki 4
437. ion is an overview of the queued serial module QSM Refer to the QSM Hef erence Manual QSMRM AD for complete information about the QSM 9 1 General The QSM contains two serial interfaces the queued serial peripheral interface QSPI and the serial communication interface SCI Figure 9 1 is a block diagram of the QSM QSM is present the MC68HC16Z1 MC68CK16Z1 68 1671 MC68HC16Z2 and MC68HC16Z3 microcontrollers 50 050 MOSI PQS1 SCK PQS2 50 55 053 51 054 52 055 53 056 INTERFACE LOGIC 5 L TXD PQS7 5 RXD QSM BLOCK Figure 9 1 QSM Block Diagram The QSPI provides peripheral expansion or interprocessor communication through a full duplex synchronous three line bus Four programmable peripheral chip selects can select up to sixteen peripheral devices by using an external 1 of 16 line selector A self contained RAM queue allows up to sixteen serial transfers of eight to sixteen bits each or continuous transmission of up to a 256 bit data stream without CPU16 in tervention A special wrap around mode supports continuous transmission reception of data M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 1 Go to www freescale com Freescale Semiconductor Inc The SCI provides a standard non return to zero NRZ mark space format It operates in either full or half duplex mode There are separate transmitter and rec
438. ion is taken by the QSM when the IMB FREEZE signal is asserted FREEZE is asserted when the CPU16 enters background debug mode At the present time FRZO has no effect setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE asser tion Refer to 4 14 4 Background Debug Mode for more information about back ground debug mode 9 2 1 3 QSM Interrupts Both the QSPI and SCI can generate interrupt requests Each has a separate interrupt request priority register A single vector register is used to generate exception vector numbers The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and SCI interrupt requests The values in these fields correspond to internal interrupt re quest signals IRQ 7 1 A value of 96111 causes IRQ7 to be asserted when a QSM in terrupt request is made Lower field values cause correspondingly lower numbered interrupt request signals to be asserted Setting the ILOSPI or ILSCI field values to 96000 disables interrupts for the QSPI and the SCI respectively If ILQSPI and ILSCI have the same non zero value and the QSPI and SCI make simultaneous interrupt requests the QSPI has priority When the CPU16 acknowledges an interrupt request it places the value in the condi tion code register interrupt priority IP mask ADDR 3 1 The QSM compares the IP mask value to the priority of the interrupt request to determine whether it should contend for arbitration QSM a
439. ion out of reset 5 52 operation in SIM 5 48 control logic 5 48 mode selection 5 49 power on 5 55 For More Information On This Product l 11 Go to www freescale com Freescale Semiconductor Inc processing summary 5 57 states of pins assigned to other MCU modules 5 54 status register RSR 5 24 5 57 timing 5 55 Resistor divider chain 8 5 Resolution 8 7 Result registers 8 13 Return from interrupt instruction RTI 4 40 8 22 RF energy 8 14 RIE D 42 D 61 RJURR D 36 RLCK 6 2 D 23 RMAC 4 9 ROM array space ASPC D 26 ROMBAH BAL 7 1 D 27 ROMBS 7 1 ROMBS0 3 D 28 RR D 51 RS 232C terminal C 2 RSIGHI LO 7 1 7 3 D 27 RSR 5 24 D 8 RT 9 28 10 21 RTI 4 40 RWU 9 30 10 22 D 42 D 62 RXD QSM 9 25 RXDA B 10 16 10 17 S S 4 4 D 3 S8CM D 32 Sample capacitor 8 5 time 8 7 time selection STS field D 31 SAR 8 13 Saturate mode SM bit 4 4 D 3 SBK 9 27 10 20 D 42 D 62 SCAN D 32 Scan mode selection SCAN D 32 SCBR D 40 D 59 SCCR 9 24 SCCRO D 40 SCCROA B 10 13 D 59 SCCR1 D 41 SCCR1A B 10 16 D 60 SCDR 9 24 D 44 SCDRA B 10 16 D 63 SCF D 36 SCI 9 1 9 2 9 16 9 21 10 1 baud clock 9 26 10 18 rate 10 18 D 40 D 59 idle line detection 9 29 10 21 internal loop 9 30 10 22 interrupt level ILSCIA B D 55 operation 9 25 10 17 parity checking 9 26 10 19 pins MCCI 10 16 1 12 For More Information On This Product pins QSM 9 25 receiver block diagram
440. iption 0 Inpytralization INIT INCLUDI COP INCLUDI INCLUDI CSINIT LDD STD STD LDD STD E 14 GI 50303 CSBARO CSBAR1 55030 CSORO Demo of how to set up the 01 and U3 RAM slots with two 32Kx8 RAM chips using the Chip Selects The new memory will start at address 30000 and will be both byte and word readable writable This program assumes that the RAM to be installed such as MCM60L256AP85 or MCM6206P85 have access times of 85 ns and require no wait states The DSACK field of the Chip Select Option Registers may need to be adjusted for chips that have faster or slower access times EQUATES ASM table of EQUates for common register ORGOO000 ASM initialize reset vector ORGOO008 ASM initialize exception vector table 200 start program right after vector table KKKKK sInrtializatrion Stuff INITSYS ASM initially set EK F 0 0 2 0 Set sys clock at 16 78 MHz disable INITRAM ASM turn on 1k internal SRAM at 10000 set stack in bank 1 SK 1 SP 03FE INITSCI ASM set SCI baud rate at 9600 baud enable SCI transmitter and receiver Initialize the Chip Selects set Ul RAM base addr to 530000 bank 3 64k set U3 RAM base addr to 530000 bank 3 64k set Chip S
441. is Product 4 41 to www freescale com Freescale Semiconductor Inc Breakpoints on instructions that are flushed from the pipeline before execution are not acknowledged Operand breakpoints are always acknowledged There is no break point acknowledge bus cycle when BDM is entered Refer to 5 6 4 1 Breakpoint Ac knowledge Cycle for more information about breakpoints 4 14 3 Opcode Tracking and Breakpoints Breakpoints are acknowledged after a tagged instruction has executed that is when the instruction is copied from pipeline stage B to stage C Stage C contains the opcode of the previous instruction when execution of the current instruction begins When an instruction is tagged IPIPEO IPIPE1 reflect the start of execution and the ap propriate number of pipeline advances and operand fetches before the breakpoint is acknowledged If background debug mode is enabled these signals model the pipe line before BDM is entered 4 14 4 Background Debug Mode Microprocessor debugging programs are generally implemented in external software CPU16 BDM provides a debugger implemented in CPU microcode BDM incorporates a full set of debug options Registers can be viewed and altered memory can be read or written and test features be invoked BDM is an alternate CPU16 operating mode While the CPU16 is BDM normal instruction execution is suspended and special microcode performs debugging functions under external control While in
442. is stored in scont mncnt and hrcnt converts them to ASCII characters terminal output the and then sends them to a dummy hours convert hex number into ASCII and print output a co ASCII numbe send charac output the convert hex output anot ASCII send charac output the lon r for a colon ter to terminal minutes number to ASCII and print her colon r for a colon ter to terminal seconds INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product E 21 Go to www freescale com LDAB JSR LINE_FD CARRIAGE LDAB JSR LDAB JSR RTS Freescale Semiconductor Inc SCCNT Z HEXTOASC 50 SEND_CH S0D SEND_CH convert hex number to ASCII and print output a linefeed load ASCII number for line feed send character to terminal output a carriage return ASCII number for carriage return send character to terminal done with display routine Hexadecimal to ASCII conversion HEXTOASC PRTMSB PRTLSB NOTAF Autovector Routine AUTOV reset STD JSR LDD ANDB BRA LSRB LSRB LSRB LSRB ADDB CMPB BLS ADDB JSR RTS LDAB STAB LDAB STAB LDX JSR RTI KKKKK Other BDM E 22 BGND 55 SWS SA SWS EMP Z RTMSB EMP Z SOF RTLSB UE HUH 530 539 507 SEND_CH 5 R A the follo
443. ister SIM Port F Pin Assignment Register ICR GPT Interrupt Configuration Register ILSCI MCCI SCI Interrupt Register M68HC16 Z SERIES NOMENCLATURE USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Mnemonic Register PICR SIM Periodic Interrupt Control Register PORTADA ADC Port ADA Data Register PORTE SIM Port E Data Register 0 1 PORTGP GPT Port GP Data Register MCCI Port Pin State Register PORTQS PQSPAR QSM Port QS Pin Assignment Register PWMA GPT PWM Control Register A PWMBUFA GPT PWM Buffer Register A PWMC GPT PWM Control Register C QILR QSM Interrupt Level Register QIVR QSM Interrupt Vector Register QSMCR QSM Module Configuration Register RAMBAH RAM Array Base Address Register High RAMMCR RAM Module Configuration Register RJURR 0 7 ADC Right Justified Unsigned Result Registers 0 7 ROMBAL ROM Array Base Address Register Low RR O F QSM Receive Data RAM 0 F SCCR 0 1 QSM SCI Control Registers 0 1 SCCR1 A B MCCI SCIA B Control Registers 1 A B SCDR A B MCCI SCIA B Data Registers A B NOMENCLATURE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Mnemonic Register SCSR QSM SCI Status Register SIGHI ROM Signature Register High SIMCR SIM Module Configuration Register SIMTRE SI
444. it dais a 0 1 0 1 1 2 1 3 Byte to 16 bit 0 0 4 Byte to 16 bit port odd 0 Word to 8 bit port 5 2 aligned Word to 8 bit port 6 1 misaligned Word to 16 bit port Transfer Case 5121 SIZO ADDRO DSACK1 DSACKO aligned Word to 16 bit port 8 3 misaligned 9 Long word to 8 bit port 13 aligned 10 Long word to 8 bit port 1 misaligned Long word to 16 bit port 11 7 aligned 12 Long word to 16 bit port 3 misaligned 13 Three byte to 8 bit port 1 1 1 0 5 NOTES 1 Operands in parentheses are ignored by the CPU16 during read cycles 2 The CPU16 treats misaligned long word transfers as two misaligned word transfers 3 Three byte transfer cases occur only as a result of an aligned long word to 8 bit port transfer 5 6 Bus Operation Internal microcontroller modules are typically accessed in two system clock cycles Regular external bus cycles use handshaking between the MCU and external periph erals to manage transfer size and data These accesses take three system clock cy cles with no wait states During regular cycles wait states can be inserted as needed by bus control logic Refer to 5 6 2 Regular Bus Cycle for more information Fast termination cycles which are two cycle external accesses with no wait states use chip select logic to generate handshaking signals internally Refer to 5 6 3 Fast Termination Cycles and 5
445. it time of logic level one to oc cur between frames This bit time does not affect content but if it occurs after a frame of ones when short detection is enabled the receiver flags an idle line When the bit in SCCR1 is set an interrupt request is generated when the IDLE flag is set The flag is cleared by reading SCSR and SCDR in sequence IDLE is not set again until after at least one frame has been received RDRF 1 This prevents an extended idle interval from causing more than one interrupt 10 4 5 8 Receiver Wake Up The receiver wake up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message Hardware activates each receiver in a system under certain conditions Resident software must process address information and enable or disable receiver operation A receiver is placed in wake up mode by setting the RWU bit in SCCR1 While RWU is set receiver status flags and interrupts are disabled Although the CPU32 can clear RWU it is normally cleared by hardware during wake up The WAKE bit in SCCR1 determines which type of wake up is used When WAKE 0 idle line wake up is selected When WAKE 1 address mark wake up is selected Both types require a software based device addressing and recognition scheme Idle line wake up allows a receiver to sleep until an idle line is detected When an idle line is detected the re
446. it to select master operation Set the SPE bit to enable the SPI 5 Enable the slave device 6 Write appropriate data to the SPI data register to initiate the transfer When the SPI reaches the end of the transmission it sets the SPIF flag in the SPSR If the SPIE bit in the SPCR is set an interrupt request is generated when SPIF is as serted After the SPSR is read with SPIF set and then the SPDR is read or written to the SPIF flag is automatically cleared M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL For More Information On This Product Go to www freescale com 10 7 Freescale Semiconductor Inc Data transfer is synchronized with the internally generated serial clock 5 Control bits CPHA and CPOL in SPCR control clock phase and polarity Combinations of CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing data from the MOSI pin and latches incoming data from the MISO pin 10 3 3 2 Slave Mode Clearing the MSTR bit in SPCR selects slave mode operation In slave mode the SPI is unable to initiate serial transfers Transfers are initiated by an external bus master Slave mode is typically used on a multimaster SPI bus Only one device can be bus master operate in master mode at any given time When using the SPI in slave mode include the following steps 1 Write to the MMCR and interrupt registers Refer to 10 5 MCCI Initialization for more information 2 Write
447. ithin the CPU16 during operations simplifies 32 bit arithmetic and digital signal processing and provides a practical 16 bit accumulator offset indexed addressing mode 4 2 2 Index Registers CPU16 has three 16 bit index registers IX IY and IZ Each index register has an associated 4 bit extension field XK and ZK Concatenated registers and extension fields provide 20 bit indexed addressing and support data structure functions anywhere in the CPU16 address space IX and can perform the same operations as M68HC11 registers of the same names but the CPU16 instruction set provides additional indexed operations IZ can perform the same operations as and IY IZ also provides an additional in dexed addressing capability that replaces M68HC1 1 direct addressing mode Initial IZ and ZK extension field values are included in the RESET exception vector so that ZK IZ can be used as a direct page pointer out of reset 4 2 3 Stack Pointer The CPU16 stack pointer SP is 16 bits wide An associated 4 bit extension field SK provides 20 bit stack addressing Stack implementation in the CPU16 is from high to low memory The stack grows downward as it is filled SK SP are decremented each time data is pushed on the stack and incremented each time data is pulled from the stack SK SP point to the next available stack address rather than to the address of the latest stack entry Although the stack pointer is normally in
448. ity Vor will equal Vsnc This assumes no internal leakage With 10 bit resolution 1 2 of a count is equal to 1 2048 full scale value Assuming worst case full scale Table 8 10 shows the required time for Cp to charge to within 1 2 of a count of the actual source voltage during 10 bit conversions Table 8 10 is based on the RC network in Figure 8 10 NOTE The following times are completely independent of the A D converter architecture assuming the ADC is not affecting the charging ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 8 10 External Circuit Settling Time 10 Bit Conversions Filter Capacitor Source Resistance 1000 1 10 100 1 uF 760 us 7 6 ms 76 ms 760 ms The external circuit described in Table 8 10 is a low pass filter A user interested in measuring an AC component of the external signal must take the characteristics of this filter into account 8 8 6 2 Error Resulting from Leakage A series resistor limits the current to a pin therefore input leakage acting through a large source impedance can degrade A D accuracy The maximum input leakage cur rent is specified in APPENDIX A ELECTRICAL CHARACTERISTICS Input leakage is greatest at high operating temperatures and as a general rule decreases by one half for each 10 C decrease in temperature
449. ized with the MCU system clock The number of bits shifted in by the receiver depends on the serial format However all frames must end with at least one stop bit When the stop bit is received the frame is considered to be complete and the received data in the serial shifter is transferred to the RDR The receiver data register flag RDRF is set when the data is transferred Noise errors parity errors and framing errors can be detected while a data stream is being received Although error conditions are detected as bits are received the noise flag NF the parity flag PF and the framing error flag FE in SCSR are not set until data is transferred from the serial shifter to the RDR RDRF must be cleared before the next transfer from the shifter can take place If RDRF is set when the shifter is full transfers are inhibited and the overrun error OR flag in SCSR is set OR indicates that the RDR needs to be serviced faster When OR is set the data in the RDR is preserved but the data in the serial shifter is lost Be cause framing noise and parity errors are detected while data is in the serial shifter FE NF and PF cannot occur at the same time as OR When the CPU16 reads SCSR and SCDR in sequence it acquires status and data and also clears the status flags Reading SCSR acquires status and arms the clearing mechanism Reading SCDR acquires data and clears SCSR When RIE in SCCR1 is set an interrupt request is generated when
450. k Diagram 11 2 GPT Registers and Address Map The GPT programming model consists of a configuration register GPTMCR parallel I O registers DDRGP PORTGP capture compare registers TCNT TCTL1 TCTL2 TIC 1 3 TOC 1 4 14 05 CFORC pulse accumulator registers pulse width modulation registers PWMA PWMB PWMC PWMCNT PWMBUFA PWMBUFB status registers TFLG1 TFLG2 and interrupt control registers TMSK1 2 Functions of the module configuration register are discussed in 11 3 Special Modes of Operation and 11 4 Polled and Interrupt Driven Operation Other regis ter functions are discussed in the appropriate sections All registers can be accessed using byte or word operations Certain capture compare registers and pulse width modulation registers must be accessed by word operations to ensure coherency If byte accesses are used to read a register such as the timer counter register TCNT there is a possibility that data in the byte not being accessed will change while the other byte is read Both bytes must be accessed at the same time The modmap MM bit in the system integration module configuration register SIMCR defines the most significant bit ADDR23 of the IMB address for each regis ter in the MCU Because the CPU16 drives ADDR 23 20 to the same logic state as ADDR 19 0 MM must equal one GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 2 USER S MANUAL For More Information On This Prod
451. ks within the address space Each bank is made up of 64 Kbytes addressed from 0000 to FFFF Banks are selected by means of the address extension fields associated with individual CPU16 registers In addition address space can be split into discrete 1 Mbyte program and data spaces by externally decoding the MCU s function code outputs When this technique is used instruction fetches and reset vector fetches access program space while exception vector fetches other than for reset data accesses and stack accesses are made in data space M68HC16 Z SERIES CENTRAL PROCESSOR UNIT USER S MANUAL For More Information On This Product 4 5 Go to www freescale com Freescale Semiconductor Inc 4 3 1 Address Extension All CPU16 resources used to generate addresses are effectively 20 bits wide These resources include the index registers program counter and stack pointer All address ing modes use 20 bit addresses Twenty bit addresses are formed from a 16 bit byte address generated by an individ ual CPU16 register and a 4 bit address extension contained in an associated exten sion field The byte address corresponds to ADDR 15 0 and the address extension corresponds to ADDR 19 16 4 3 2 Extension Fields Each of the six address extension fields is used for a different type of access All but EK are associated with particular CPU16 registers There are several ways to manip ulate extension fields and the address map Refer to the
452. l bits except the SPE bit in SPCR1 Control registers must be initialized before the QSPI is enabled to ensure proper operation SPCR1 must be written last because it contains the QSPI enable bit SPE Writing a new value to any control register except SPCR2 while the QSPI is enabled disrupts operation SPCR2 is buffered New SPCR2 values become effective after completion of the current serial transfer Rewriting NEWQP in SPCR2 causes execu tion to restart at the designated location Reads of SPCR2 return the current value of the register not of the buffer Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect on QSPI operation QUEUED SERIAL MODULE M68HC16 Z SERIES 9 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 9 3 1 2 Status Register SPSR contains information concerning the current serial transmission Only the QSPI can set the bits in this register The CPU16 reads SPSR to obtain QSPI status infor mation and writes SPSR to clear status flags 9 3 2 QSPI RAM The QSPI contains an 80 byte block of dual ported static RAM that can be accessed by both the QSPI and the CPU16 The RAM is divided into three segments receive data RAM transmit data RAM and command data RAM Receive data is information received from a serial device external to the MCU Transmit data is information stored for transmission to an external device C
453. l boot start up ROM om pem During a read cycle indicates that an external device should DS Data Strobe place valid data on the data bus During a write cycle indicates that valid data is on the data bus Acknowledge DSI DSO Development Serial In DSCLK Out Clock Serial and clock for background debug mode EXTAL XTAL Crystal Oscillator Connections for clock synthesizer circuit reference a crystal or an external oscillator can be used FC 2 0 Function Codes Identify processor state and current address space HALT Halt Suspend external bus activity IPIPE 1 0 Instruction Pipeline Indicate instruction pipeline activity MISO Master In Slave Out Serial input to QSPI in master mode serial output from QSPI in slave mode MISO Master In Slave Out Serial input to SPI in master mode serial output from SPI in slave mode Clock Mode Select Selects the source and type of system clock Serial output from QSPI in master mode serial input to QSPI in Master Out Slave In slave mode Serial output from SPI in master mode serial input to SPI in slave mode PADA 7 0 Port ADA ADC digital input port signals PAI Pulse Accumulator Input Input to the GPT pulse accumulator PC 6 0 Port C Port C digital output port signals PE 7 0 Port E Port E digital I O port signals MOSI Master Out Slave In M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 15
454. l voltage between the true analog ground and the microcontroller s ground pin The end result is that the ground observed by the analog circuit is no longer true ground and often ends in skewed results Two similar approaches designed to improve or eliminate the problems associated with grounding excess transient currents involve star point ground systems One ap proach is to star point the different grounds at the power supply origin thus keeping the ground isolated Refer to Figure 8 6 ANALOG POWER SUPPLY DIGITAL POWER SUPPLY AGND PGND ADC POWER SCHEM Figure 8 6 Star Ground at the Point of Power Supply Origin Another approach is to star point the different grounds near the analog ground pin on the microcontroller by using small traces for connecting the non analog grounds to the analog ground The small traces are meant only to accommodate DC differences not AC transients M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc NOTE This star point scheme still requires adequate grounding for digital and analog subsystems in addition to the star point ground Other suggestions for PCB layout in which the ADC is employed include the following analog ground must be low impedance to all analog ground points in the cir cuit Bypass capacitors should be as close to the power pins
455. le 4 Software Watchdog Periodic Interrupt and Autovactor Demo tod retra ei 22 Programming EXSITIBIB 2 2 1 Example 5 Indexed and Extended Addressing Eg QSM SCI Programming Example ern E 2 Example e Using an SC E 2 4 GPT Programming Example EHE HIA FEE EH EEG E 2 4 1 Example 7 Basic GPT uuu cucina tiec M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M68HC16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Figure Title Page 3 1 MC68HC16Z1 CK16Z1 CM16Z1 Block Diagram iiie reiten nbn ni 3 4 3 2 MC68HC16Z2 Z3 Block Diagram 3 5 3 3 MC68HC16Z4 CK16Z4 Block Diagram 1st nente dtes e kn 3 6 3 4 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments IB SS PIC 3 7 3 5 MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 Pin Assignments for 144 Pin Package 3 8 3 6 MC68HC16Z4 CKZ4 Pin Assignments for 132 Pin Package 3 9 3 7 MC68HC16Z4 CKZA4 Pin Assignments for 144 Pin Package 3 10 3 8 MC68HC16Z1 CKZ1 CMZ1 Address uec terne rien 3 17 3 9 MCOSHCTITGZAZ3 Addross Map 3 18 3 10 MC68HC16Z4 CKZ4 Address rt
456. lear the RE and TE bits Complete transfers in progress before disabling the SPI and SCI interfaces Once the STOP bit is asserted it can be cleared by system software or by reset 10 2 1 2 Privilege Levels The supervisor bit SUPV in the MMCR has no effect since the CPU16 operates only in the supervisor mode 10 2 1 3 MCCI Interrupts The interrupt request level of each of the three MCCI interfaces can be programmed to a value of zero interrupts disabled through seven highest priority These levels are selected by the ILSCIA and ILSCIB fields in the SCI interrupt level register ILSCI and the ILSPI field in the SPI interrupt level register ILSPI In case two or more MCCI submodules request an interrupt simultaneously and are assigned the same interrupt request level the SPI submodule is given the highest priority and SCIB is given the lowest When an interrupt is requested which is at a higher level than the interrupt mask in the CPU status register the CPU initiates an interrupt acknowledge cycle During this cy cle the MCCI compares its interrupt request level to the level recognized by the CPU If a match occurs arbitration with other modules begins Interrupting modules present their arbitration number on the IMB and the module with the highest number wins The arbitration number for the MCCI is programmed into the interrupt arbitration IARB field of the MMCR Each module should be assigned a unique arbitration number
457. lers that support sep arate user and supervisor operating modes ASPC1 has no effect because the CPU16 operates in supervisor mode only This bit may be read or written at any time The reset state of ASPC 1 0 is specified at mask time Table D 22 shows ASPC 1 0 en coding Table D 22 ROM Array Space Field ASPC 1 0 State Specified X0 Program and data accesses X1 Program access only WAIT 1 0 Wait States Field WAIT 1 0 specifies the number of wait states inserted by the MRM during ROM array accesses The reset state of WAIT 1 0 is user specified The field can be written only if LOCK 0 and STOP 1 Table D 23 shows the wait states field Table D 23 Wait States Field Number of Wait States WAIT 1 0 Clocks per Transfer 11 1 2 REGISTER SUMMARY M68HC16 Z SERIES For More information On This Product USER S MANUAL Go to www freescale com D 26 Freescale Semiconductor Inc D 4 2 ROM Array Base Address Registers ROMBAH ROM Array Base Address Register High YFF824 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 23 22 21 20 19 18 17 16 RESET 1 1 1 1 1 1 1 1 The reset value of the shaded bits is user specified but the bits can be written after reset to change the base address If the values of ROMBAH bits ADDR 23 20 do not match that of ADDR19 the CPU16 cannot access the RO
458. lization routine can be automatically enabled by CSBOOT after a reset Refer to 5 9 4 Chip Select Reset Operation for more information 5 9 1 3 Chip Select Option Registers Option register fields determine timing of and conditions for assertion of chip select signals To assert a chip select signal and to provide DSACK or autovector support other constraints set by fields in the option register and in the base address register must also be satisfied The following paragraphs summarize option register functions Refer to D 2 21 Chip Select Option Registers for register and bit field information The MODE bit determines whether chip select assertion simulates an asynchronous bus cycle or is synchronized to the M6800 type bus clock signal ECLK available on ADDR23 Refer to 5 3 System Clock for more information on ECLK BYTE 1 0 controls bus allocation for chip select transfers Port size set when a chip select is enabled by a pin assignment register affects signal assertion When an 8 bit port is assigned any BYTE field value other than 00 enables the chip select signal When a 16 bit port is assigned however BYTE field value determines when the chip select is enabled The BYTE fields for CS 10 0 are cleared during reset However both bits in the boot ROM chip select option register CSORBT BYTE field are set 11 when the RESET signal is released R W 1 0 causes chip select signal to be asserted only for a read only for a w
459. ll always read zero D 2 10 Port F Data Direction Register DDRF Port F Data Direction Register YFFA1C 15 8 7 6 5 4 3 2 1 0 NOT USED DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDFO RESET 0 0 0 0 0 0 0 0 This register controls the direction of the port F pin drivers when pins are configured for I O Setting a bit configures the corresponding pin as an output clearing a bit con figures the corresponding pin as an input This register can be read or written at any time Bits 15 8 are unimplemented and will always read zero D 2 11 Port F Pin Assignment Register PFPAR Port F Pin Assignment Register YFFA1E 15 8 7 6 5 4 3 2 1 0 NOT USED 5 4 PFPA3 PFPA2 PFPA1 PFPAO RESET DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 This register determines the function of port F pins Setting a bit assigns the corre sponding pin to a control signal clearing a bit assigns the pin to port F Bits 15 8 are unimplemented and will always read zero Refer to Table D 5 Table D 5 Port F Pin Assignments PFPAR Field Port F Signal Alternate Signal PFPA7 PF7 IRQ7 PF6 IRQ6 PFPA5 PF5 IRQ5 PFPA4 PF4 IRQ4 PFPA3 PF3 IRQ3 PFPA2 PF2 IRQ2 PFPA1 PF1 IRQ1 PFPAO PFO MODCLK M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 2 12 System Protect
460. lock Diagram uei rmt ntn 11 15 FOM LBA Met 11 17 1 CLKOUT Output Timing aaa A 28 A 2 External Clock Input Timing Diagram A 28 A 3 Output cerusa a A 28 A 4 Read Cycle Timing A 29 A 5 Write Cycle Timing Diagram A 30 A 6 Fast Termination Read Cycle Timing Diagram A 31 A 7 Fast Termination Write Cycle Timing Diagram A 32 A 8 Bus Arbitration Timing Diagram Active Bus Case A 33 A 9 Bus Arbitration Timing Diagram Idle Bus Case A 34 7 10 Show Cycle Timing Diagram uiuere eterne tX kane A 35 Timing Diagram PERI A 36 A 12 Reset and Mode Select Timing A 36 A 13 Background Debug Mode Timing Diagram Serial Communication A 39 A 14 Background Debug Mode Timing Diagram Freeze Assertion A 39 A 15 Timing Diagram eH Ri A 44 A16 QSPITiming Master 0 iussis E etl da A 47 A 17 Timing Master T sse dmi kar et rd
461. lower external development memory Access time depends upon the number of wait states specified but can be as fast as two clock cycles The MRM can be used for program accesses only or for program and data accesses Data can be read in bytes words or long words The MRM can be configured to support system bootstrap during reset 7 1 MRM Register Block There are three MRM control registers the masked ROM module configuration regis ter MRMCR and the ROM array base address registers ROMBAH and ROMBAL In addition the MRM register block contains the signature registers RSIGHI and RSIGLO and ROM bootstrap words ROMBS 0 3 The module mapping bit MM in the SIM configuration register defines the most significant bit ADDR23 of the IMB address for each M68HC16 68 16 and 68 16 Z series module Because ADDR 23 20 are driven to the same value as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible For more information about how the state of MM affects the system refer to 5 2 1 Module Mapping The MRM control register block consists of 32 bytes but not all locations are imple mented Unimplemented register addresses are read as zeros and writes have no ef fect Refer to D 4 Masked ROM Module for the register block address map and register bit field definitions 7 2 MRM Array Address Mapping Base address registers ROMBAH and ROMBAL are used to specify the ROM array base address in
462. ltage meets Vi and specifications When used as digital inputs the pins are organized into an 8 bit port PORTADA and referred to as PADA 7 0 There is no data direction register because port pins are input only ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 8 2 2 Analog Reference Pins Separate high Vay and low Vp analog reference voltages are connected to the an alog reference pins The pins permit connection of regulated and filtered supplies that allow the ADC to achieve its highest degree of accuracy 8 2 3 Analog Supply Pins Pins and supply power to analog circuitry associated with the RC DAC Other circuitry in the ADC is powered from the digital power bus pins Vpp and Dedicated analog power supplies are necessary to isolate sensitive ADC circuitry from noise on the digital power bus 8 3 Programmer s Model The ADC module is mapped into 32 words of address space Five words are control status registers one word is digital port data and 24 words provide access to the re sults of AD conversion eight addresses for each type of converted data Two words are reserved for expansion The ADC module base address is determined by the value of the MM bit in the SIM configuration register SIMCR The base address is normally FFF700 Internally the ADC has both a differential da
463. ltiplexer inputs the eight analog inputs can be used as a gen eral purpose digital input port port ADA provided signals are within logic level spec ification A port data register PORTADA is used to access input data 8 2 External Connections The ADC uses 12 pins on the MCU package Eight pins are analog inputs which can also be used as digital inputs two pins are dedicated analog reference connections and Vg and two pins are analog supply connections and M68HC16 Z SERIES ANALOG TO DIGITAL CONVERTER USER S MANUAL For More Information On This Product 81 Go to www freescale com Freescale Semiconductor Inc VppA Da Veca SUPPLY V Var REFERENCE RC DAC ARRAY AND ANTIPADAT COMPARATOR ANG PADAG ANALOG AN5 PADA5 MUX AN4 PADA4 AND SAMPLE AN3 PADA3 BUFFER AMP AN2 PADA2 ANI PADAI ANO PADAO SAR RESERVED RESERVED RESERVED gt RESULTO RESERVED INTERNAL CONNECTIONS RESERVED L RESULT 2 pa PORT ADA DATA H RESULT 3 REGISTER BE RESULT 5 o RESULT 6 gt RESULT7 CLK SELECT PRESCALE ADC BUS INTERFACE UNIT INTERMODULE BUS IMB 16 ADC BLOCK 2 Figure 8 1 ADC Block Diagram 8 2 1 Analog Input Pins Each of the eight analog input pins AN 7 0 is connected to a multiplexer in the ADC The multiplexer selects an analog input for conversion to digital data Analog input pins can also be read as digital inputs provided the applied vo
464. ly VCO Frequency Limp Mode Clock Frequency SYNCR X bit 0 SYNCR X bit 1 CLKOUT Jitter 8 9 10 Short term 5 us interval Long term 500 us interval NOTES 1 Refer to notes in Table A 10 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 7 Go to www freescale com Freescale Semiconductor Inc Table A 9 20 97 MHz Clock Control Timing and 5 0 5 Veg 0 Vdc T4 to Ta Num Characteristic Maximum Unit PLL Reference Frequency 1 MC68HC16Z1 50 kHz 68 1672 5 2 MHz MC68HC16Z3 5 2 MHz System Frequency 20 97 On Chip PLL System Frequency 2 Slow On Chip PLL System Frequency 20 97 MHz Fast On Chip PLL System Frequency 4 128 20 97 External Clock Operation dc 20 97 PLL Lock Time 7 8 9 Changing W or Y in SYNCR or exiting from 3 LPSTOP 20 ms Warm Start Up 50 Cold Start Up fast reference option only 75 4 VCO Frequency 2 max MHz Limp Mode Clock Frequency 5 SYNCR X bit 0 f fsys max 2 MHz SYNCR X bit 1 max CLKOUT Jitter 7 8 9 10 6 Short term 5 us interval 1 0 Long term 500 us interval 0 5 NOTES 1 Refer to notes in Table A 10 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 10 25 17 MHz Clo
465. ly affects the response of chip selects and does not affect in terrupt recognition by the CPU Encoding 96000 in the IPL field causes a chip select signal to be asserted regardless of interrupt acknowledge cycle priority provided all other constraints are met The AVEC bit is used to make a chip select respond to an interrupt acknowledge cy cle If the AVEC bit is set an autovector will be selected for the particular external interrupt being serviced If AVEC is zero the interrupt acknowledge cycle will be ter minated with DSACK and an external vector number must be supplied by an external device 5 9 1 4 PORTC Data Register The PORTO data register latches data for PORTC pins programmed as discrete out puts When a pin is assigned as a discrete output the value in this register appears at the output PC 6 0 correspond to CS 9 3 Bit 7 is not used Writing to this bit has no effect and it always reads zero 5 9 2 Chip Select Operation When the MCU makes an access enabled chip select circuits compare the following items Function codes to SPACE fields and to the IP mask if the SPACE field encoding is not for CPU space Appropriate address bus bits to base address fields Read write status to R W fields ADDRO and or SIZ 1 0 bits to BYTE field 16 bit ports only e Priority of the interrupt being acknowledged ADDR S 1 to IPL fields when the access is an interrupt acknowledge cycle When a match
466. m stack LDS 503 put SP at top of 1k internal SRAM E 1 6 INITSCI ASM Title INITSCI Description Initialize the SCI to transmit and receive at 9600 baud INITSCI initialize the SCI LDD 50037 STD SCCRO set the SCI baud rate to 9600 baud LDD 5000 STD SCCR1 enable the SCI receiver and transmitter E 2 Programming Examples The following programming examples use different M68HC16 Z series modules All programs were written to run on the M68HC16Z1EVB evaluation board Refer to the M68HC1621EVB Evaluation Board User s Manual M68HC16Z1EVB D for further in formation NOTE These programs will also work on the modular evaluation board MEVB using a microcontroller personality board for the appropriate Z series derivative See APPENDIX C DEVELOPMENT SUPPORT for more information on the MEVB Several of these programs send status messages using the SCI in the QSM on the MC68HC16Z1 MC68CK16Z1 MC68CM16Z1 MC68HC16Z2 and MC68HC16Z3 These programs can be made to function with SCIA in the MCCI on the MC68HC16Z4 and MC68CKZA as follows Replace SCCRO with SCCROA e Replace SCCR1 with SCCR14A Replace SCSR with SCSRA Replace SCDR with SCDRA INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 12 USER S MANUAL For More Information O
467. match an interrupt acknowledge strobe will be generated on the particular chip select pin provided other option register condi tions are met Table 0 18 shows IPL 2 0 field encoding Table D 18 Interrupt Priority Level Field Encoding IPL 2 0 Interrupt Priority Level Any Level 001 1 010 100 101 110 111 NOTES 1 Any level means that chip select is assert ed regardless of the level of the interrupt acknowledge cycle AVEC Autovector Enable This field selects one of two methods of acquiring an interrupt vector during an inter rupt acknowledge cycle This field is not applicable wnen SPACE 1 0 00 0 External interrupt vector enabled 1 Autovector enabled If the chip select is configured to trigger on an interrupt acknowledge cycle SPACE 1 0 00 and the AVEC field is set to one the chip select automatically generates AVEC and completes the interrupt acknowledge cycle Otherwise the vec tor must be supplied by the requesting external device to complete the IACK read cycle M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 21 Go to www freescale com Freescale Semiconductor Inc D 2 22 Master Shift Registers TSTMSRA Test Module Master Shift Register A Used for factory test only TSTMSRB Test Module Master Shift Register B Used for factory test only D 2 23 Test Module Shift Count Register TSTSC Test Module Sh
468. mation On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc ax O 0 20 1 36 TIPS 0 20 T L M N A1 6 151 F ej VIEW AB 0 1 T 144 SEATING PLANE Pe TS ee TEE TEES Bem hd dd dd dde PLATING J dn AA C2 0 05 0 25 GAGE PLANE BASE METAL 0 08 L M N SECTION J1 J1 ROTATED 90 144 PL VIEW AB er X X L MORN L 140X G VIEW 5 DA soooogoxo gt 20 MENSIONS AND TOLERANCING PER ASME 4 5M 1994 MENSIONS IN MILLIMETERS L M BE DETERMINED AT THE NG PLANE DATUM T MENSIONS AND V TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS A AND DO NOT INCLUDE MOLD RUSION ALLOWABLE PROTRUSION IS PER SIDE DIMENSIONS A AND B DO CLUDE MOLD MISMATCH AND ARE ETERMINED AT DATUM PLANE H MENSION D DOES NOT INCLUDE DAMBAR RUSION ALLOWABLE DAMBAR RUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 35 a zm ovyo MILLIMETERS DIM MIN A 20 00BSC At 10 0085 B 20 00BSC 1 1000BSC C 140 150 c 005 015 C2 135 145
469. mbinations of SYNCR bits To obtain clock frequency find the counter modulus in the leftmost col umn then multiply the reference frequency by the value in the appropriate prescaler cell Shaded areas indicate which values exceed the specifications for a device rated at a particular operating frequency Refer to APPENDIX A ELECTRICAL CHARAC TERISTICS for maximum allowable clock rate Tables 5 5 5 6 and 5 7 show actual clock frequencies for the same combinations of SYNCR bits To obtain clock frequency find the counter modulus in the leftmost col umn then refer to appropriate prescaler cell Shaded areas indicate which values ex ceed the specifications for a device rated at a particular operating frequency Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for maximum system frequency SYSTEM INTEGRATION MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 2 16 78 MHz Clock Control Multipliers Shaded cells represent values that exceed 16 78 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fuco 2 Value Value fuco 22x Value fuco Value Slow Fast Slow Fast 000000 03125 000001 0625 125 32 25 125 09375 000010 000011 125 1875 128 15625 000100 000101 3125 160 1 25 1875 192 000110 000111 128 21825 5625 144 1 125 001000 00
470. ment Z index register to next word end xloop if the end of the string 00 is detected in either accumulator A or B This loop reads its string from the 01 U3 Slots and prints it at the dummy terminal XK IX index to point to bank 3 point to the beginning of the ASCII string go output the ASCII string loop back and print again subroutine to send out the entire ASCII string get next char in string as pointed to by if 00 then message is done go send out a character increment IX to point to the next ASCII char loop back go back to whence we came subroutine to send out one character at a SCSR read the SCI status reg to check TDRE bit 01 check only the tdre flag bit INITIALIZATION AND PROGRAMMING EXAMPLES E 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BEQ SEND_CH if TDR is not empty go back to check it again CLRA STD SCDR transmit one ASCII character to the screen TC_LOOP LDAB SCSR t 1 ANDB 580 test the TC bit transfer complete BEQ TC_LOOP continue to wait until TC is set RTS finish sending out one character Exceptions Interrupts BDM BGND exception vectors point here and put the user in background mode KKKKK The string KKKKK ORG 0310 STRING DC I LIKE MY NEW MEMORY 0A 0D 00 E 2 1 3 Example 3 Changing Clock Frequencies De
471. mmunication systems require a mark on the TXD pin even when the transmitter is disabled Configure the TXD pin as an output then write a one to PQS7 When the transmitter releases control of the TXD pin it will revert to driving a logic one output To insert a delimiter between two messages to place non listening receivers in wake up mode between transmissions or to signal a retransmission by forcing an idle line clear and then set TE before data in the serial shifter has shifted out The transmitter finishes the transmission then sends a preamble After the preamble is transmitted if TDRE is set the transmitter will mark idle Otherwise normal transmission of the next sequence will begin Both TDRE and TC have associated interrupts The interrupts are enabled by the transmit interrupt enable TIE and transmission complete interrupt enable TCIE bits SCCR1 Service routines can load the last byte of data in a sequence into SCDR then terminate the transmission when a TDRE interrupt occurs 9 4 3 6 Receiver Operation The RE bit in SCCR1 enables RE 1 and disables RE 0 the receiver The receiv er contains a receive serial shifter and a parallel receive data register RDR located in the SCI data register SCDR The serial shifter cannot be directly accessed by the CPU16 The receiver is double buffered allowing data to be held while other data is shifted in Receiver bit processor logic drives a state machine th
472. n 8 6 Analog Subsystem The analog subsystem consists of a multiplexer sample capacitors a buffer amplifier an RC DAC array and a high gain comparator Comparator output sequences the successive approximation register SAR The interface between the comparator and the SAR is the boundary between ADC analog and digital subsystems 8 6 1 Multiplexer The multiplexer selects one of 16 sources for conversion Eight sources are internal and eight are external Multiplexer operation is controlled by channel selection field CD CA in register ADCTL1 Table 8 2 shows the different multiplexer channel sources The multiplexer contains positive and negative stress protection circuitry This circuitry prevents voltages on other input channels from affecting the current con version ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 84 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 8 2 Multiplexer Channel Sources CD CA Value Input Source 0000 ANO 0001 AN1 0010 AN2 0011 0100 4 0101 5 0110 AN6 0111 AN7 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 1101 VRL 1110 2 1111 Test Reserved 8 6 2 Sample Capacitor and Buffer Amplifier Each of the eight external input channels is associated with a sample capacitor and share a single sample buffer amplifier After a conversion is initiated
473. n 9 3 AS 4 41 5 31 5 40 5 43 5 45 5 47 5 54 ASPC 7 2 7 3 D 26 Asserted definition 2 6 Asynchronous exceptions 4 39 Autocorrelation 4 45 Autovector enable AVEC See AVEC 5 24 Auxiliary timer clock input PCLK 11 8 AVEC 5 24 5 33 5 43 5 54 5 60 5 65 5 67 5 68 D 21 Background debug mode 4 40 4 42 5 41 commands 4 43 connector pinout 4 45 enabling 4 42 entering 4 42 recommended connection 4 45 serial block diagram 4 44 interface 4 44 sources 4 42 timing 16 78 MHz A 37 20 97 MHz A 38 25 17 MHz A 38 freeze assertion A 39 low voltage 16 78 MHz A 37 serial communication A 39 Basic operand size 5 35 Baud clock 9 26 10 18 rate generator 9 2 BCD 4 6 BERR 5 33 5 37 5 41 5 43 5 44 5 45 5 54 5 60 BG 5 46 5 49 5 54 5 65 BGACK 5 46 5 49 5 54 5 65 Binary coded decimal BCD 4 6 weighted capacitors 8 5 BITS D 47 encoding field 9 18 Bits per transfer enable BITSE D 52 field BITS D 47 BITSE 9 20 D 52 Bit time 9 25 10 17 BKPT 4 41 5 41 5 49 5 52 5 53 5 57 Block size BLKSZ 5 65 D 18 encoding 5 65 D 18 BME 5 25 D 13 BMT 5 24 D 13 BOOT D 26 Boot ROM control BOOT 7 3 D 26 Bootstrap words ROMBS 7 1 BR 5 46 5 49 5 54 5 64 5 65 Break frame 9 25 10 17 For More Information On This Product Breakpoint acknowledge cycle 5 41 exceptions 4 40 hardware breakpoints 5 41 mode selection 5 52 operation 5 42 Breakpoints 4 41 Buffer amplifier 8 5 Built in emulation m
474. n On This Product 3 3 Go to www freescale com Freescale Semiconductor Inc PWMA PAI ADDR23 CS 10 ECLK gt IC4 OC5 0C1 PGP7 IC4 0C5 0C1 Bul OC4 0C1 PGP6 0 4 0 1 CST ADDR22 C5 9 PC6 OC3 0C1 PGP5 0C3 0C1 ELECT OczocupGP4 8 07 oczoci E J ADDR19 C56 PC3 3 em ae JE amp rC2 CSSIPC2 IC3IPGP2 P18 13 259 lt FCI CSAIPCI IC2 PGP1 ICUPGPO FCOCSSIPCO ADDR 23 19 5 BR CSO TXD PQS7 53 056 26522055 PCS2 ADDR 18 0 51 054 98 51 PCSOSSIPQS3 5 50 Q5M 5171 SIZ1 PE7 lt 052 5120 5120 6 MOSI PQS1 5 5 MISO PQSO DS DS PE4 PE3 2 AVEC ole AVEC PE2 4 5 DSACKI PE1 i JaAC RA s DSACKO DSACKO PEO DATA L5 0 7 7 RESET ANG PADAG aie septi ANSIPADAS S BERR 4 AN1 PADA1 Olu TRO4 PF4 ANO PADAO ROPES IRQ2 PF2 MODCLK RQIPFI MODCLK PFO CLKOUT XTAL EXTAL BKPT a IPIPEO mms BKPT DSCLK IPIPE1 IPIPE1 DS 051 TSC TSC 050 OL 9 TEST QUOT FREEZE QUOT an FREEZE HC16Z1 CKZ1 CMZ1 BLOCK Figure 3 1 MC68HC16Z1 CK16Z1 CM16Z1 Block Diagram OVERVIEW M68HC16 Z SERIES 3 4 For More Information On This Product Go to w
475. n This Product 55 to www freescale com Freescale Semiconductor Inc PHI1 42 EXT PIN PAI TCNT FFFE F FFF 0000 PACNT 77 78 NOTES 1 PHI1 HAS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 TCNT COUNTS AS A RESULT OF PHI1 4 PACNT COUNTS WHEN TCNT OVERFLOWS FROM FFFF TO 0000 AND THE CONDITIONED PAI SIGNAL IS ASSERTED PULSE ACCUM TOF GATED MODE Figure A 27 Pulse Accumulator Using TOF as Gated Mode Clock 1 21 PWMCNT 7 0 EXT PIN PMWx NOTES 1 PHIL IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 WHEN THE COUNTER ROLLS OVER FROM FF TO 00 THE PWM PIN IS SET TO LOGIC LEVEL ONE WHEN THE COUNTER EQUALS THE PWM REGISTER THE PWM PIN IS CLEARED TO A LOGIC LEVEL ZERO PWMx FAST MODE Figure 28 PWMx Register 01 Fast Mode ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com A 56 Freescale Semiconductor Inc PHI1 COMPARE CAPTURE CLOCK OCx COMPARE 0102 REGISTER TCNT 0101 0102 0103 OCx MATCH OCxF EXT PIN OCx NOTES 1 PHIL IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 WHEN THE TCNT MATCHES THE
476. n This Product Go to www freescale com E 2 1 SIM Programming Examples Freescale Semiconductor Inc The following programming examples involve using the system integration module SIM The prog rams include Using ports E F e Setting up U1 and U3 RAM slots with two 32K X 8 RAM chips using chip selects e Demonstrating the ability of the M68HC16 to change clock frequencies on the fly Demonstrating the software watchdog the periodic interrupt and an autovector Refer to SECTION 5 SYSTEM INTEGRATION MODULE for more information on the SIM E 2 1 1 Example 1 Using Ports E and F Description This program demonstrates si Ports with Port read that Port a number F through a number from E will be incremented E and F with a loop that pass that number over to he M68HC16Z1EVB hardwire of t the Port F da ac ta register h loop mple I O usage of will load Port E B and then The hardwire of the M68HC16Z1EVB is from DSACKO to MODCLK AVEC to IRQ2 The numbers start at 00 and go to 07 from DSACK1 to IRQ1 and from INCLUDE EQUATES ASM table of EQUates for common register addresses INCLUDE ORG00
477. n Valid to Clock Low Data Setup tsNDOI iDVSA 27A Late BERR HALT Asserted to Clock Low Setup Time 28 AS DS Negated to DSACK 1 0 BERR HALT AVEC Negated 29 DS CS Negated to Data In Invalid Data In Hold tBELCL tsNDN tsnbI Be 9A DS M68HC16 Z SERIES USER S MANUAL 5 Negated to Data In High Impedance 7 8 ns ns 8 ns 39 ns 15 ns ns ns ns ns ns ns ns tsHDI ELECTRICAL CHARACTERISTICS For More information On This Product A 25 Go to www freescale com Freescale Semiconductor Inc Table A 18 25 17 MHz AC Timing Continued Vip Vo pgyy 5 0 5 Veg 0 Vdc T T to T N Characteristic Symbol Min M Unit CLKOUT Low to Data In Invalid Fast Cycle Hold teipi CLKOUT Low to Data In High Impedance 6 i 3 8 0 Asserted to Data In Valid tDADI Clock Low to BG Asserted Negated 2 Asserted to BG Negated R W Width Asserted Write Read 90 Asynchronous Input Setup Time BR BGACK DSACK 1 0 BERR AVEC HALT Asynchronous Input Hold Time 2 30 ns 3 ns 31 ns 33 ns 35 1 37 1 t 39 1 46 ns ns 47A ns 47B ns 48 0 Asserted to BERR HALT Asserted ns 53 ns 54 ns 55 ns 70 ns 71 ns 72 ns 73 ns 74 75 76 77 78 35 BR Asserted to BG Asserted
478. n before the status bit is cleared A long word read can consecutively access both SCSR and SCDR This action clears receive status flag bits that were set at the time of the read but does not clear TDRE or TC flags Reading either byte of SCSR causes all 16 bits to be accessed and any status bit already set in either byte is cleared on a subsequent read or write of SCDR Bits 15 9 Not Implemented TDRE Transmit Data Register Empty 0 Transmit data register still contains data to be sent to the transmit serial shifter 1 new character can now be written to the transmit data register TC Transmit Complete 0 SCI transmitter is busy 1 SCI transmitter is idle REGISTER SUMMARY M68HC16 Z SERIES D 62 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc RDRF Receive Data Register Full 0 Receive data register is empty or contains previously read data 1 Receive data register contains new data RAF Receiver Active 0 SCI receiver is idle 1 SCI receiver is busy IDLE Idle Line Detected 0 SCI receiver did not detect an idle line condition 1 SCI receiver detected an idle line condition OR Overrun Error 0 Receive data register is empty and can accept data from the receive serial shifter 1 Receive data register is and cannot accept data from the receive serial shifter Any data in the shifter is lost and RDRF remains
479. n field MAC multiplicand register Index register Y Address extension register Program counter extension field Stack pointer Index register Y extension field Modulo addressing index register X mask LPSTOP mode control bit Half carry flag Negative flag Two s complement overflow flag Interrupt priority field NOMENCLATURE M68HC16 Z SERIES 2 2 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 3 Register Mnemonics Mnemonic Register ADCMCR ADC Module Configuration Register ADCTL 0 1 ADC Control Registers 0 1 CFORC GPT Compare Force Register CR O F QSM Command RAM 0 F CSBAR 0 10 SIM Chip Select Base Address Registers 0 10 CSORBT SIM Chip Select Option Register Boot CSOR 0 10 SIM Chip Select Option Registers 0 10 SIM Chip Select Pin Assignment Registers 0 1 DDRE SIM Port E Data Direction Register DDRGP GPT Port GP Data Direction Register DDRQS QSM Port QS Data Direction Register GPTMCR GPT Module Configuration Register IL SPI MCCI SPI Interrupt Register LJURR 0 7 ADC Left Justified Unsigned Result Registers 0 7 MMCR Module Configuration Register MRMCR Masked ROM Module Configuration Register OC1D GPT Output Compare 1 Action Data Register PACNT GPT Pulse Accumulator Counter Register GPT Pulse Accumulator Control Register PEPAR SIM Port E Pin Assignment Reg
480. n polled or interrupt driven mode Status flags in SCSR reflect SCI conditions regardless of the operating mode chosen The TIE TCIE RIE and ILIE bits in SCCR1 enable interrupts for the conditions indicated by the TDRE TC RDRF and IDLE bits in SCSR respectively 9 4 3 1 Definition of Terms Bit Time The time required to transmit or receive one bit of data which is equal to one cycle of the baud frequency e Start Bit One bit time of logic zero that indicates the beginning of a data frame A start bit must begin with a one to zero transition and be preceded by at least three receive time samples of logic one Stop Bit One bit time of logic one that indicates the end of a data frame Frame A complete unit of serial information The SCI can use 10 bit or 11 bit frames e Data Frame A start bit a specified number of data or information bits and at least one stop bit Idle Frame A frame that consists of consecutive ones An idle frame has no start bit Break Frame A frame that consists of consecutive zeros A break frame has no stop bits 9 4 3 2 Serial Formats All data frames must have a start bit and at least one stop bit Receiving and transmit ting devices must use the same data frame format The SCI provides hardware sup port for both 10 bit and 11 bit frames The M bit in SCCR1 specifies the number of bits per frame The most common data frame format for NRZ serial interfaces is one s
481. n progress that transmis sion finishes normally before the break begins To assure the minimum break time toggle SBK quickly to one and back to zero The bit is set at the end of break trans mission After break transmission at least one bit time of logic level one mark idle is transmitted to ensure that a subsequent start bit can be detected If TE remains set after all pending idle data and break frames are shifted out TDRE and TC are set and TXD is held at logic level one mark When TE is cleared the transmitter is disabled after all pending idle data and break frames are transmitted The TC flag is set and control of the TXD pin reverts to MPAR and MDDR Buffered data is not transmitted after TE is cleared To avoid losing data in the buffer do not clear TE until TDRE is set Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled Configure the TXD pin as an output then write a one to PQS7 When the transmitter releases control of the TXD pin it reverts to driving a logic one output To insert a delimiter between two messages to place non listening receivers in wake up mode between transmissions or to signal a retransmission by forcing an idle line clear and then set TE before data in the serial shifter has shifted out The transmitter finishes the transmission then sends a preamble After the preamble is transmitted if TDRE is set the transmitter will mark idle Other
482. n the stream CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Total execution time is calculated using the expression CLp CLo Where CL1 Total clock periods per instruction Clock periods used for internal operation CLp Clock periods used for program access CLo Clock periods used for operand access Refer to the CPU16 Reference Manual CPU16RM AD for more information on this topic 4 13 Exceptions An exception is an event that preempts normal instruction processing Exception pro cessing makes the transition from normal instruction execution to execution of a rou tine that deals with the exception Each exception has an assigned vector that points to an associated handler routine Exception processing includes all operations required to transfer control to a handler routine but does not include execution of the handler routine itself Keep the distinc tion between exception processing and execution of an exception handler in mind while reading this section 4 13 1 Exception Vectors An exception vector is the address of a routine that handles an exception Exception vectors are contained in a data structure called the exception vector table which is lo cated in the first 512 bytes of bank 0 Refer to Table 4 5 for the exception vector table All vectors except t
483. n this mode This bit may be read or written at any time M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 25 Go to www freescale com Freescale Semiconductor Inc BOOT Boot ROM Control Reset state of BOOT is specified at mask time This is a read only bit 0 ROM responds to bootstrap word locations during reset vector fetch 1 ROM does not respond to bootstrap word locations during reset vector fetch Bootstrap operation is overridden if STOP 1 at reset LOCK Lock Registers The reset state of LOCK is specified at mask time If the reset state of the LOCK is Zero it can be set once after reset to allow protection of the registers after initialization Once the LOCK bit is set it cannot be cleared again until after a reset LOCK protects the ASPC and WAIT fields as well as the ROMBAL and ROMBAH registers ASPC ROMBAL and ROMBAH are also protected by the STOP bit 0 Write lock disabled Protected registers and fields can be written 1 Write lock enabled Protected registers and fields cannot be written EMUL Emulation Mode Control 0 Normal ROM operation 1 Accesses to the ROM array are forced external allowing memory selected by the CSM pin to respond to the access Because the MC68HC16Z2 and the MC68HC16Z3 do not support ROM emulation mode this bit should never be set ASPC 1 0 ROM Array Space The ASPC field limits access to the SRAM array in microcontrol
484. ncy on both slow and fast reference frequency devices when fey is equal to the system clock frequency Divide Ratio Specified by SWP and SWT 1 0 f sys Time Out Period Table 5 10 shows the divide ratio for each combination of SWP SWT 1 0 bits When SWT 1 0 are modified a watchdog service sequence must be performed be fore the new time out period can take effect SYSTEM INTEGRATION MODULE M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 10 Software Watchdog Divide Ratio SWP SWT 1 0 Divide Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 Figure 5 9 is a block diagram of the watchdog timer and the clock control for the riodic interrupt timer EXTAL XTAL FREEZE MODCLK CRYSTAL 128 29 PRESCALER SWP OSCILLATOR CLOCK SELECT CLOCK AND DISABLE SELECT PTP SOFTWARE SOFTWARE WATCHDOG TIMER PERIODIC INTERRUPT TIMER WATCHDOG 213 DIVIDER CHAIN 4 TAPS 8 BIT MODULUS COUNTER PIT RESET mem INTERRUPT LPSTOP SWE SWTI SWTO NOTES 1 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR PIT WATCHDOG BLOCK 16 Figure 5 9 Periodic Interrupt Timer and Software Watchdog Timer 5 4 6 Periodic Interrupt Timer The periodic interrupt timer PIT allows the generation of interrupts of specific priority at predetermined intervals This capability is often used to sche
485. nd the changed interrupt stack frame refer to Transporting M68HC11 Code to M68HC16 Devices Freescale Pro gramming Note M68HC16PN0O1 D for more information 4 7 1 Instruction Set Summary Table 4 2 is a quick reference to the entire CPU16 instruction set Refer to the CPU16 Reference Manual CPU16RM AD for detailed information about each instruction as sembler syntax and condition code evaluation Table 4 3 provides a key to the table nomenclature M68HC16 Z SERIES CENTRAL PROCESSOR UNIT USER S MANUAL For More Information On This Product 4 11 to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Mnemonic ABA ABX Operation Add B to A Add B to IX Description Address Instruction Condition Codes Mode INH Opcode Cycles S se MV H EV N Z V C A A A A ABY Add B to IY 000 B 5 YK IY ABZ Add B to IZ ZK IZ 000 B gt ZK IZ ACE Add E to AM 31 16 E gt ACED Add E D to AM AM E D gt ADCA ADCB ADCD ADCE ADDA Add with Carry to A Add with Carry to B Add with Carry to D Add with Carry to E Add to A M D M M 1 C3D E M M 1 C5E IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT E Y E Z IND8 X IND8 Y IND8 Z IMM8 IND16 X IND1
486. nformation On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 6 9 Port QS Pin Assignment Register Data Direction Register PQSPAR PORT QS Pin Assignment Register YFFC16 DDRQS PORT QS Data Direction Register YFFC17 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 NOT Paspas PQSPAS PQSPA4 PQSPA3 PQSPAL 5 0 00057 00056 00055 00054 00053 00052 20051 00050 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clearing a bit in PQSPAR assigns the corresponding pin to general purpose I O Set ting a bit assigns the pin to the QSPI PQSPAR does not affect operation of the SCI Table D 33 displays PQSPAR pin assignments Table D 33 PQSPAR Pin Assignments PQSPAR Field PQSPAR Bit Pin Function 0 50 PQSPAO MISO 0 PQS1 PQSPA1 MOSI E 2 SCK 0 PQS3 POSPAS 1 PCSO SS 0 54 PQSPA4 0 55 5 PCS2 0 PQS6 PQSPA6 PCS3 _ PQS7 TXD NOTES 1 52 is a digital pin unless the SPI is enabled SPE set in SPCR1 in which case it becomes the QSPI serial clock SCK 2 PQS7 is a digital I O pin unless the SCI transmitter is enabled TE set in SCCR1 in which case it becomes the SCI serial output TXD DDRQS determines whether pins configured for general purpose I O are inputs or out puts Clearing a bit makes the corresponding pin an input setting a bit makes the pin an output DDRQS affects both QSPI func
487. ng points to the proper positions within the bit period 9 4 3 4 Parity Checking The PT bit in SCCR1 selects either even PT 0 or odd PT 1 parity PT affects received and transmitted data The PE bit in SCCR1 determines whether parity check ing is enabled PE 1 or disabled PE 0 When PE is set the MSB of data in a frame is used for the parity function For transmitted data a parity bit is generated for received data the parity bit is checked When parity checking is enabled the PF bit in the SCI status register SCSR is set if a parity error is detected Enabling parity affects the number of data bits in a frame which can in turn affect frame size Table 9 5 shows possible data and parity formats QUEUED SERIAL MODULE M68HC16 Z SERIES 9 26 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 5 Effect of Parity Checking on Data Size M Result 0 8 data bits A L1 o 8 data bits 1 parity bit 9 4 3 5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register TDR located in the SCI data register SCDR The serial shifter cannot be directly accessed by the CPU16 The transmitter is double buffered which means that data can be loaded into TDR while other data is shifted out The TE bit in SCCR1 enables TE 1 and dis ables TE 0 the transmitter The shifter output is connec
488. ng to dummy terminal DEC CNT Z decrement loop counter BNE loop 5 times LBRA MAIN branch back to main Subroutines LDD SFFFE delay loop STD DLY Z DEC DLY Z BNE LOOP4 RTS subroutine to send out the entire ASCII string LDAB 0 get next byte string as pointed to by BEQ STRING_DONE if B 00 then message is done INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product E17 Go to www freescale com Freescale Semiconductor Inc JSR SEND_CH send out the byte AIX 501 increment to point to the next byte BRA SEND STRING loop back and do next byte in string STRING DONE JSR DELAY wait for a moment RTS go back to whence we came SEND CH subroutine to send out one byte to SCI LDAA SCSR read SCI status reg to check clear TDRE bit ANDA 01 check only the TDRE flag bit SEND_CH if TDR is not empty go back to check it again LDAA 00 clear A to send full word to SCDR S FFCOE STD SCDR transmit one ASCII character to the screen LOOP5 LDAB SCSR 1 ANDB 80 test the bit transfer complete BEQ LOOP5 continue to wait until is set RTS return to send string subroutine KKKKK The STRINGS KKKKK STRING DC System Clock is now running at 16 777 MHz 0a 0d 00 SEC_STR DC check this out 0a 0d 00 00 STRING2 DC System Clock is now running at 4 194 MHz 0a 0d 0
489. nimum amount of DC resistance For accurate conversion results the analog reference voltages must be within the lim its defined by Vppa and as explained in the following subsection 8 8 2 Analog Power Pins The analog supply pins Vssa define the limits of the analog reference volt ages and Vg and of the analog multiplexer inputs Figure 8 4 is a diagram of the analog input circuitry ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Ven SAMPLE AMP COMPARATOR 8 CHANNELS TOTAL NOTES 1 TWO SAMPLE AMPS EXIST ON THE ADC WITH EIGHT CHANNELS ON EACH SAMPLE AMP ADC 8CH SAMPLE AMP Figure 8 4 Analog Input Circuitry Since the sample amplifier is powered by and it can accurately transfer input signal levels up to but not exceeding Vpp4 and down to but not below Vasa If the input signal is outside of this range the output from the sample amplifier is clipped In addition Vay and Vg must be within the range defined by Vpp4 and As long as is less than or equal to VppA and Vg is greater than or equal to Vssa and the sample amplifier has accurately transferred the input signal resolution is ratiomet ric within the limits defined by Vg and Vay If Vay is greater than Vppa the sample amplifier can never transfer a full scale value
490. niques can provide the same access times with slower memory devices but require more chip selects to be used and will subsequently increase system power consumption Table D 16 Memory Access Times at 16 78 20 97 and 25 17 MHz D 20 For More Information On This Product Go to www freescale com Speed Fast Termination Access Time 0 Wait State 1 Wait State 16 78 MHz 62 5 ns 30 0 ns 95 0 ns 155 0 ns 20 97 MHz 50 0 ns 20 0 ns 70 0 ns 120 0 ns 25 17 MHz 40 0 ns 15 0 ns 55 0 ns 95 0 ns REGISTER SUMMARY M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc SPACE 1 0 Address Space Select Use this option field to select an address space for chip select assertion or to configure a chip select as an interrupt acknowledge strobe for an external device The CPU16 normally operates in supervisor mode only but interrupt acknowledge cycles take place in CPU space Table D 17 shows address space bit encodings Table D 17 Address Space Bit Encodings SPACE 1 0 Address Space 00 CPU Space 01 User Space 10 Supervisor Space 11 Supervisor User Space IPL 2 0 Interrupt Priority Level When SPACE 1 0 is set for CPU space 00 chip select logic can be used as interrupt acknowledge strobe for an external device During an interrupt acknowledge cycle the interrupt priority level is driven on address lines ADDR 3 1 and is then com pared to the value in IPL 2 0 If the values
491. nnot be read or written This bit can be read or written at any time RLCK RAM Base Address Lock 0 SRAM base address registers can be written 1 SRAM base address registers are locked and cannot be modified RLCK defaults to zero on reset it can be written once to a one and may be read at any time RASP 1 0 RAM Array Space The RASP field limits access to the SRAM array in microcontrollers that support sep arate user and supervisor operating modes RASP1 has no effect because the CPU16 operates in supervisor mode only This bit may be read or written at any time Refer to Table D 20 Table D 20 SRAM Array Address Space Type RASP 1 0 Space Program and data accesses Program access only M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 23 Go to www freescale com Freescale Semiconductor Inc D 3 2 RAM Test Register RAMTST RAM Test Register YFFBO2 Used for factory test only D 3 3 Array Base Address Register High RAMBAH Array Base Address Register High Z1 Z2 Z3 and Z4 YFFBOA 15 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 23 22 21 20 19 18 16 NOT USED RESET D 3 4 Array Base Address Register Low RAMBAL Array Base Address Register Low 1K SRAM 21 24 YFFBO6G 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
492. nstruction is terminated by assertion of The number of bus cycles in the instruction during which BERR is asserted The number of bus cycles in the instruction following the instruction in which BERR is asserted Whether BERR is asserted during a program space access or a data space access Because of these factors it is impossible to predict precisely how long after occur rence of a bus error the bus error exception is processed 5 44 For More Information On This Product SYSTEM INTEGRATION MODULE M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NOTE The external bus interface does not latch data when an external bus cycle is terminated by a bus error When this occurs during an in struction prefetch the IMB precharge state bus pulled high or FF is latched into the CPU16 instruction register with indeterminate re sults 5 6 5 2 Double Bus Faults Exception processing for bus error exceptions follows the standard exception process ing sequence Refer to 4 13 Exceptions for more information However two special cases of bus error called double bus faults can abort exception processing BERR assertion is not detected until an instruction is complete The BERR latch is cleared by the first instruction of the BERR exception handler Double bus fault occurs in two ways 1 When bus error exception processing begins and a second BERR is detected
493. nters wraparound mode control bits and an interrupt enable bit SPCR2 is buffered New SPCR2 values become effective only after com pletion of the current serial transfer Rewriting NEWQP in SPCR2 causes execution to restart at the designated location Reads of SPCR2 return the value of the register not the buffer SPIFIE SPI Finished Interrupt Enable 0 QSPI interrupts disabled 1 QSPI interrupts enabled WREN Wrap Enable 0 Wraparound mode disabled 1 Wraparound mode enabled WRTO Wrap To 0 Wrap to pointer address 0 1 Wrap to address in NEWQP Bit 12 Not Implemented ENDQP 3 0 Ending Queue Pointer This field contains the last QSPI queue address Bits 7 4 Not Implemented NEWQP 3 0 New Queue Pointer Value This field contains the first QSPI queue address D 6 13 QSPI Control Register 3 SPCR3 QSPI Control Register YFFC1E SPSR QSPI Status Register YFFC1F 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 NOT USED LOOPQ HMIE HALT SPIF MODF HALTA NOT CPTQP 3 0 USED RESET 0 0 0 0 0 0 0 0 0 0 SPCRS contains the loop mode enable bit halt and mode fault interrupt enable and the halt control bit SPCR3 must be initialized before QSPI operation begins Writing a new value to SPCR3 while the QSPI is enabled disrupts operation SPSR contains information concerning the current serial transmission Bits 15 11 Not Implemented LOOPQ QSPI Loop Mode 0 Feedback pa
494. ntinued Paragraph Title Page 4 14 4 Background Debug Mode 4 42 4 14 4 1 Enabling BDM ena 4 42 4 14 4 2 cR bon Benen eae arene ene ene EEEa 4 42 4 14 4 3 Entering g 4 42 4 14 4 4 aig 4 43 4 14 4 5 Henning BON 4 43 4 14 4 6 BDM Serial Interface 4 44 4 15 Recommended BDM Connection 4 45 Digital Signal gt Rm 4 45 SECTION 5 SYSTEM INTEGRATION MODULE 5 1 ERE a edi HD UH Ond pner cd ba ador DEDERE DE 5 1 5 2 5 2 ine Module Mapping 5 2 5 2 2 Ligure Site 5 3 5 2 3 Show Internal Cycles 5 3 5 2 4 cin T ACCESE 5 3 5 2 5 ege Tem 5 3 5 3 ul eo dent 5 4 5 3 1 des Rog oo D M 5 5 5 3 2 Clock Synthesizer Operation E 5 6 5 3 3 Be nid s Gee 5 21 5 3 4 Low Power Operation 5 21 5 4 vc puc o m 5 24 5 4 1 oce RR TR 5 24 5 4 2 BUS NION ER 5 24 5 4 3 las usu Slammed oe 5 25 5 4 4 Spurious Interrupt MONITO uaa addio pr reci dato a Rr
495. nto the pin Reads of PORTMC return the value of the pin only if the pin is configured as a discrete input Otherwise the value read is the value of the latch Reads of PORTMCP always return the state of the pins regardless of whether the pins are configured for input or output Writes to PORTMCP have no effect D 7 9 SCI Control Register 0 SCCROA SCIA Control Register 0 YFFC18 SCCROB SCIB Control Register 0 YFFC28 15 13 12 10 9 8 1 6 5 4 3 2 1 0 NOT USED SCBR 12 0 RESET 0 0 0 0 0 0 0 0 0 0 1 0 0 SCCRO contains the SCI baud rate selection field Baud rate must be set before the SCI is enabled The CPU16 can read and write SCCRO at any time Changing the val ue of SCCRO bits during a transfer operation can disrupt the transfer Bits 15 13 Not Implemented SCBR 12 0 SCI Baud Rate SCI baud rate is programmed by writing a 13 bit value to this field Writing a value of zero to SCBR disables the baud rate generator Baud clock rate is calculated as fol lows M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 59 Go to www freescale com Freescale Semiconductor Inc fsys SCI Baud Rate 32 x SCBR 12 0 or fsys SCBR 12 0 32 x SCI Baud Rate Desired where SCBR 12 0 is in the range of one to 8191 Writing a value of zero to SCBR dis ables the baud rate generator There are 8191 different baud rates available The baud value depends on the value for SCBR and
496. o value before the LPSTOP instruction is executed A PIT interrupt or an external interrupt request can bring the MCU out of the low power stop mode if it has a higher priority than the interrupt mask value stored in the clock control logic when low power stop mode is initiated LPSTOP can be terminated by a reset 5 5 External Bus Interface The external bus interface EBI transfers information between the internal MCU bus and external devices Figure 5 10 shows a basic system with external memory and peripherals M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 29 Go to www freescale com Freescale Semiconductor Inc Vpp Vpp Vpp Vpp Vpp Vpp 10ko wko 0 8 1002 10 8 MC68HC681 Ce ASYNC BUS PERIPHERAL ADDR 17 1 DATA 15 0 10 kQ 10 kQ ADDR 15 1 DATA 15 8 ADDR 15 1 DATA T 0 NOTES 1 ALL CHIP SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16 BIT eT EINECIR BUS Figure 5 10 MCU Basic System SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 30 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The external bus has 24 address lines and 16 data lines ADDR 19 0 are normal ad dress outputs ADDR 23 20 follow the output state of ADDR19 The EBI provides dy namic sizing between 8 bit and 16 bit data accesses It supports by
497. occurs the chip select signal is asserted Assertion occurs at the same time as AS or DS assertion in asynchronous mode Assertion is synchronized with ECLK in synchronous mode In asynchronous mode the value of the DSACK field de termines whether DSACK is generated internally DSACK 3 0 also determines the number of wait states inserted before internal DSACK assertion The speed of an external device determines whether internal wait states are needed Normally wait states are inserted into the bus cycle during S3 until a peripheral as serts DSACK If a peripheral does not generate DSACK internal DSACK generation must be selected and a predetermined number of wait states can be programmed into the chip select option register Refer to the S M Reference Manual SIMRM AD for further information M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 67 Go to www freescale com Freescale Semiconductor Inc 5 9 3 Using Chip Select Signals for Interrupt Acknowledge Ordinary bus cycles use supervisor or user space access but interrupt acknowledge bus cycles use CPU space access Refer to 5 6 4 CPU Space Cycles and 5 8 Inter rupts for more information There are no differences in flow for chip selects in each type of space but base and option registers must be properly programmed for each type of external bus cycle During a CPU space cycle bits 15 3 of the appropriate bas
498. ock at 16 78 MH turn on internal SRAM at set stack 5 1 SP 03FE the SCI baud rate to enable the SCI receiver a YK 0 ZK 0 z disable COP 10000 9600 baud nd transmitter set XK to bank 0 for STRING access Set ZK to bank 1 for delay counter access clear IZ for later use wi point to the beginning of th delay counter ASCII string go output the ASCII string branch back to main subroutine to send out the entire ASCII string get next byte in string as pointed to by IX if 00 then goto delay between 7go send out the byte INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product Go to www freescale com messages M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc AIX 501 increment IX to point to the next byte BRA SEND STRING loop back and do next byte in string STRING DONE subroutine to implement delay between messages LDE SFFFF load accumulator E with the delay time STE 0 7 Set up the counter LOOP DECW O Z decrement the counter BNE LOOP count down to zero RTS finish delay loop go back to main SEND CH subroutine to send out one byte to SCI LDAA SCSR read SCI status reg to check clear TDRE bit ANDA 501 check only the TDRE flag bit BEQ SEND CH if TDR is not empty go back to check it again LDAA 00 clear A to send a full word to SCDR SFFCOE STD
499. ock synthesizer is used SYNCR determines the system clock frequency and certain operating parameters The W and Y 5 0 bits are located in the PLL feed back path enabling frequency multiplication by a factor of up to 256 When the W or Y values change VCO frequency changes and there is a VCO relock delay The SYN CR X bit controls a divide by circuit that is not in the synthesizer feedback loop When X 0 reset state a divide by four circuit is enabled and the system clock frequency is one fourth the VCO frequency fyco When X 1 a divide by two circuit is enabled and system clock frequency is one half the VCO frequency fyco There is no relock delay when clock speed is changed by the X bit When slow reference is used one W bit and six Y bits are located in the PLL feed back path enabling frequency multiplication by a factor of up to 256 The X bit is lo cated in the VCO clock output path to enable dividing the system clock frequency by two without disturbing the PLL When using a slow reference the clock frequency is determined by SYNCR bit set tings as follows lo 4a eor m The reset state of SYNCR 3F00 results in a power on fsys of 8 388 MHz when fref is 32 768 kHz M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 7 Go to www freescale com Freescale Semiconductor Inc When a fast reference is used three W bits are located in the PLL feedback path en
500. odes Mode Opcode Cycles S MV H EV N Z VI C SUBB Subtract from B IND8 X 6 AAA IND8 Y 6 IND8 Z 6 IMM8 2 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 6 6 E Z 6 SUBD Subtract from D IND8 X 6 AAA IND8 Y 6 IND8 Z 6 IMM16 4 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 E X 6 E Y 6 E Z 6 SUBE Subtract from E IMM16 4 AAA IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 SWI Software Interrupt PK PC 0002 2 PK PC INH 16 Push PC SK SP 0002 2 SK SP Push CCR SK SP 0002 2 SK SP 0 PK SWI Vector 2 PC SXT Sign Extend B into A If B7 2 1 then FF gt A else 00 gt A TAB Transfer A to B A 2 com gt AU Transfer to CCR 7 0 2 CCR 15 8 NH 4 A A A A A TBA Transfer B to A 3707 A 0 Transfer to B 3 0 27FA TBSK Transfer B to SK B 3 0 SK NH 3779F 2 Transfer to XK B 3 0 gt XK NH 379C TBYK Transfer B to YK B 3 0 NH 379D j vem pom 395 1 TBZK Transfer B to ZK B 3 0 ZK NH 379E TDE Transfer D to E gt 277 2 C mex VO TDMSK Transfer D to D 15 8 2 X MASK 372F 2 XMSK YMSK D 7 0 2 Y MASK Transfer D to D 2 CCR 15 4 NH 372D EE A A A A A TED Transfer E to D 2D 27FB 2 Ne ae TEDM Transfer E and D
501. oduct Go to www freescale com Freescale Semiconductor Inc of BKPT or execution of the BGND instruction IPIPEO and IPIPE1 change function be fore an exception signal can be generated The development system must use FREEZE assertion as an indication that BDM has been entered When BDM is exited FREEZE is negated before initiation of normal bus cycles IPIPEO and IPIPE1 are valid when normal instruction prefetch begins 4 14 4 4 BDM Commands Commands consist of one 16 bit operation word and can include one or more 16 bit extension words Each incoming word is read as it is assembled by the serial interface The microcode routine corresponding to a command is executed as soon as the com mand is complete Result operands are loaded into the output shift register to be shift ed out as the next command is read This process is repeated for each command until the CPU returns to normal operating mode The BDM command set is summarized in Table 4 7 Refer to the CPU16 Reference Manual CPU16RM AD for a BDM com mand glossary Table 4 7 Command Summary Command Mnemonic Description Read Registers Read contents of registers specified by command RREGM from Mask word register mask Write Registers Write to registers specified by command word from Mask register mask Read contents of entire multiply and accumulate Read MAC Registers register set Write MAC Registers Write to entire multiply and accumulate register set R
502. of the GPT pins return the state of the pin when STOPP was set After STOPP is set the INCP bit can be set to increment the prescaler and clock the input synchronizers once The INCP bit is self negating after the prescaler is incremented INCP can be set repeatedly The INCP bit has no effect when the STOPP bit is not set 11 3 4 Test Mode Test mode is used during Freescale factory testing The GPT has no dedicated test mode control register all GPT testing is done under control of the system integration module 11 4 Polled and Interrupt Driven Operation Normal GPT function can be polled or interrupt driven All GPT functions have an as sociated status flag and an associated interrupt The timer interrupt flag registers TFLG1 and TFLG2 contain status flags used for polled and interrupt driven opera tion The timer mask registers TMSK1 and 5 2 contain interrupt control bits Con trol routines can monitor GPT operation by polling the status registers When an event occurs the control routine transfers control to a service routine that handles that event If interrupts are enabled for an event the GPT requests interrupt service when the event occurs Using interrupts does not require continuously polling the status flags to see if an event has taken place However to disable the interrupt request status flags must be cleared after an interrupt is serviced 11 4 1 Polled Operation When an event occurs in the GPT that event set
503. ol routines The external bus interface handles the transfer of information between IMB modules and external address space The chip select block provides 12 chip select signals Each chip select signal has an associated base address register and option register that contain the programmable characteristics of that chip select The system test block incorporates hardware necessary for testing the MCU It is used to perform factory tests and its use in normal applications is not supported M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 1 to www freescale com Freescale Semiconductor Inc SYSTEM CONFIGURATION CLOCK SYNTHESIZER SYSTEM PROTECTION CHIP SELECTS p CHIP SELECTS EXTERNAL BUS INTERFACE RESET TSC FREEZE QUOT FACTORY TEST ZSERIES SIM BLOCK Figure 5 1 System Integration Module Block Diagram 5 2 System Configuration The SIM configuration register SIMCR governs several aspects of system operation The following paragraphs describe those configuration options controlled by SIMCR 5 2 1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping MM bit in the SIM configuration register SIMCR determines where the control register block is located in the system memory map When 0 register addresses range from 7 000 to 7FFFFF when
504. olls over from FFFF to 0000 the timer overflow flag TOF in tim er interrupt flag register 2 TFLG2 is set An interrupt can be enabled by setting the corresponding interrupt enable bit TOI in timer interrupt mask register 2 TMSK2 Refer to 11 4 2 GPT Interrupts for more information 11 8 2 Input Capture Functions All GPT input capture functions use the same 16 bit timer counter TCNT Each input capture pin has a dedicated 16 bit latch and input edge detection selection logic Each input capture function has an associated status flag and can cause the GPT to make an interrupt service request When a selected edge transition occurs on an input capture pin the associated 16 bit latch captures the content of TCNT and sets the appropriate status flag An interrupt request can be generated when the transition is detected GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SYSTEM CLOCK PRESCALER DIVIDE BY 4 8 16 32 64 128 256 8 SELECT 16 BIT FREE RUNNING CPR2 CPR1 CPRO COUNTER INTERRUPT REQUESTS 16 BIT TIMER BUS PIN FUNCTIONS 16 BIT LATCH CLK 16 B 2 16 B TIC3 H 16 BIT COMPARATOR TOC1 HI TOC1 LO 16 BIT COMPARATOR
505. ommand control data defines transfer param eters Refer to Figure 9 3 which shows RAM organization QSPI RAM MAP Figure 9 3 QSPI RAM 9 3 2 1 Receive RAM Data received by the QSPI is stored in this segment to be read by the CPU16 Data stored in the receive RAM is right justified Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry The CPU16 can access the data using byte word or long word transfers The CPTQP value in SPSR shows which queue entries have been executed The CPU16 can use this information to determine which locations in receive RAM contain valid data before reading them 9 3 2 2 Transmit RAM Data that is to be transmitted by the QSPI is stored in this segment and must be written by the CPU16 in right justified form QSPI cannot modify information in the trans mit RAM The QSPI copies the information to its data serializer for transmission Infor mation remains in the transmit RAM until overwritten M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 7 Go to www freescale com Freescale Semiconductor Inc 9 3 2 3 Command RAM Command RAM is used by the QSPI in master mode The CPU16 writes one byte of control information to this segment for each QSPI command to be executed The QSPI cannot modify information in command RAM Command RAM consists of 16 bytes Each byte is divided into two fields The
506. on 11 16 qe 11 18 Titi A A 11 18 68 16 Z SERIES USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION B 1 Obtaining Updated M68HC16 Z Series MCU Mechanical Information B 8 B 2 piii Rm B 8 APPENDIX C DEVELOPMENT SUPPORT C 1 M68MMDS1632 Modular Development System C 1 C 2 M68MEVB1632 Modular Evaluation Board C 2 APPENDIX D REGISTER SUMMARY 0 1 Processing BEN UU TMMMT D 1 0 1 1 Condition Code Register orae 0 3 0 2 System Integration Module D 4 D 2 1 SIM Module Configuration Register D 6 D 2 2 System Integration Test Register D 7 D 2 3 Glock Synthesizer Control Register rk nnn D 7 D 2 4 Reset Status Register Mec D 8 D 2 5 System Integration Test Register D 9 D 2 6 Porn E D amp A D 9 D 2 7 Port E Data MBOBIBE D 9 D 2 8 Port Pin Assignment Register
507. on accuracy varies with rate Reduced conversion accuracy occurs at maximum AS sumes that minimum sample time 2 ADC clocks is selected 4 10 bit absolute error of 2 5 counts 12 5 mV includes 1 2 count 2 5 mV inherent quantization error and 2 counts 10 mV circuit differential integral and offset error 5 Maximum source impedance is application dependent Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge sharing with internal capacitance Error from junction leakage is a function of external source impedance and input leakage current Expected error in result value due to junction leakage is expressed in voltage impedance M68HC16 Z SERIES USER S MANUAL Venn loff where is a function of operating temperature as shown in Table A 35 Charge sharing leakage is a function of input source impedance conversion rate change in voltage between successive conversions and the size of the decoupling capacitor used Error levels are best determined empirically In general continuous conversion of the same channel may not be compatible with high source ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com A 67 68 Freescale Semiconductor Inc 4 S 2 Y SS Qu ZEE ee n2 UN z 47 2 IDEAL TRANSFER CURVE 9 92 7 V P
508. onductor Inc Mnemonic Operation RORW Rotate Right Word 3 RTI Return from Interrupt Return from Subrou 4 RTS tine SBA SBCA Subtract B from A Subtract with Carry from A SBCB Subtract with Carry from B SBCD Subtract with Carry from D SBCE Subtract with Carry from E Description SP 2322 SK Pull CCR SP 2322 SK Pull PC PO 6 PK SP 222 SK Pull PK SP 222 SK Pull PC PK PC 22 PK D M M 1 C3D E M M 1 CS E Address Instruction Condition Codes Mode IND16 X IND16 Y IND16 Z EXT IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT EX EZ IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT Y 2 IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT X E Y E Z IMM16 IND16 X IND16 Y IND16 Z EXT Opcode Operand Cycles gt gt gt 5 gt 2 SDE Subtract D from E INH STAA Store A IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT X ESY 2 M68HC16 Z SERIES USER S MANUAL CENTRAL PROCESSING UNIT For More Information On This Product 4 25 Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode
509. onfigured for operation out of reset However all chip se lect signals except CSBOOT are disabled and cannot be asserted until the BYTE 1 0 field in the corresponding option register is programmed to a non zero value to select a transfer size The chip select option register must not be written until a base address has been written to a proper base address register Alternate functions for chip select pins are enabled if appropriate data bus pins are held low at the release of RESET Refer to 5 7 3 1 Data Bus Mode Selection for more information Figure 5 22 is a functional diagram of a single chip select circuit INTERNAL SIGNALS BASE ADDRESS REGISTER ADDRESS gt ADDRESS COMPARATOR TIMING AND CONTROL BUS CONTROL gt OPTION COMPARE OPTION REGISTER PIN ASSIGNMENT REGISTER PIN DATA REGISTER DSACK GENERATOR AVEC AVEC GENERATOR DSACK CHIP SEL BLOCK Figure 5 22 Chip Select Circuit Block Diagram 5 9 1 Chip Select Registers Each chip select pin can have one or more functions Chip select pin assignment reg isters CSPAR 1 0 determine functions of the pins Pin assignment registers also de termine port size 8 or 16 bit for dynamic bus allocation A pin data register PORTC latches data for chip select pins that are used for discrete output M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 63 Go to www freescal
510. ong Branch if Less If N V 1 branch 378D rrrr 6 4 Than Zero LBMI2 Long Branch if Minus If N 1 branch 378B LBMV Long Branch if MV Set If MV 1 branch LBNE2 Long Branch if Not 12 0 branch Equal to Zero LBPL2 Long Branch if Plus If N 0 branch LBRA Long Branch Always If 1 1 branch LBRN Long Branch Never If 1 2 0 branch LBSR Long Branch to Push PC 27F9 Subroutine SK SP 22 SK SP Push CCR SK SP 2 gt SK SP PK PC Offset 2 PK PC LBVC2 Long Branch if If V 0 branch 3788 rrr 6 4 Overflow Clear LBVS Long Branch if If V 1 branch REL16 3789 rrrr 6 4 Overflow Set LDAA Load A gt IND8 X 45 ff 6 EE EA Ae CQ IND8 Y 55 ff 6 IND8 Z 65 ff 6 IMM8 75 ii 2 IND16 X 1745 9999 6 IND16 Y 1755 0099 6 IND16 2 1765 9999 6 1775 hh II 6 2745 E 6 E Y 2755 6 2 2765 6 CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 20 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S N Z VI C LDAB IND8 X A 0 A IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT EY E Z LDD IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT E X E Y E Z LDE IMM16 IND16 X IND16 Y IND16 Z EXT
511. onic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 1 7 PULM Pull Multiple Registers For mask bits 0 to 7 4 2 N 1 A A A AJA A A Mask bits If mask bit set N 0 CCR 15 4 SK SP 2 SK SP number of 1 K Pull register registers 2 12 pulled 4 5 6 D 7 Reserved PULMAC Pull MAC State Stack MAC Registers RMAC Repeating Repeat until E 0 6 12 Multiply and AM H I per Accumulate Qualified IX iteration Signed 16 Bit Qualified IY IY Fractions M M 1 x H 1 1 15 Until lt 0000 ROL Rotate Left IND8 X AAA IND8 Y IND8 Z IND16 X IND16 Y IND16 Z EXT ROLA Rotate Left A AAA ROLB Rotate Left B AAA ROLD Rotate Left D AAA ROLE Rotate Left E AAA ROLW Rotate Left Word IND16 X 8 SS A AN IND16 Y 8 IND16 Z 8 EXT 8 ROR Rotate Right Byte IND8 X 8 AAA IND8 Y 8 IND8 Z 8 IND16 X 8 IND16 Y 8 IND16 Z 8 EXT 8 RORA Rotate Right A INH 2 A RORB Rotate Right B A AAA RORD Rotate Right D AAA RORE Rotate Right E AAA CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4 24 USER S MANUAL For More Information On This Product to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semic
512. ons Current systems that are operating correctly may not require this filter If the PLL is not enabled MODCLK 0 at reset the XFC filter is not re quired Versions of the SIM that are configured for either slow or fast reference use the same filter component values An external filter network connected to the XFC pin is not required when an external system clock signal is applied and the PLL is disabled MODCLK 0 at reset The XFC pin must be left floating in this case SYSTEM INTEGRATION MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NORMAL OPERATING ENVIRONMENT HIGH STABILITY OPERATING ENVIRONMENT 1 MAINTAIN LOW LEAKAGE ON THE NODE REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION 2 RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE NORMAL HIGH STABILITY XFC CONN Figure 5 5 System Clock Filter Networks The synthesizer locks when the VCO frequency is equal to fre Lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs Whenever a comparator input changes the synthesizer must relock Lock sta tus is shown by the SLOCK bit in SYNCR During power up the MCU does not come out of reset until the synthesizer locks Crystal type characteristic frequency and lay out of external oscillator circuitry affect lock time When the cl
513. or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part 2 freescale semiconductor
514. ore Information On This Product 59 Go to www freescale com Freescale Semiconductor Inc BUS STATES B1 B2 B3 B4 B1 B2 B3 B4 Bl B2 B3 B4 B2 B3 B4 INTERNAL DATA BUS PDRx EXTERNAL PIN OUTPUT CONDITIONED INPUT COMPARE REGISTER PDDRX 0 0101 1 0102 IMB WRITE CYCLE NOTES 1 PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING 2 WHEN THE BIT VALUE IS DRIVEN ON THE PIN THE INPUT CIRCUIT SEES THE SIGNAL AFTER IT IS CONDITIONED IT CAUSES THE CONTENTS OF THE TCNT TO BE LATCHED INTO THE ICx COMPARE REGISTER GENERAL PURPOSE OUTPUT Figure A 32 General Purpose Output Causes Input Capture ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com A 60 Freescale Semiconductor Inc BUS STATES Bl B2 Bl B4 Bl B2 Bl B2 COMPARE COMPARE CLOCK TCNT 0101 0102 0103 TOCx FOCx NOT SET EXTERNAL PIN OCx IMB WRITE CYCLE NOTES 1 1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK HOWEVER IT DOES NOT HAVE THE SAME TIMING FORCE COMPARE Figure A 33 Force Compare CLEAR M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product 61 Go to www freescale com Free
515. ority of QSPI and SCI interrupt requests QIVR determines the value of the interrupt vector number the QSM supplies when it responds to an interrupt acknowledge cycle M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 39 Go to www freescale com Freescale Semiconductor Inc ILQSPI 2 0 Interrupt Level for QSPI When an interrupt request is made the ILQSPI value determines the priority level of all QSPI interrupts When a request is acknowledged the QSM compares this value to a mask value supplied by the CPU16 to determine whether to respond ILQSPI must have a value in the range 0 interrupts disabled to 7 highest priority ILSCI 2 0 Interrupt Level for SCI When an interrupt request is made the ILSCI value determines the priority level of all SCI interrupts When a request is acknowledged the QSM compares this value to a mask value supplied by the CPU16 to determine whether to respond The field must have a value in the range 0 interrupts disabled to 7 highest priority If ILQSPI 2 0 and ILSCI 2 0 have the same non zero value and both submodules si multaneously request interrupt service the QSPI takes priority over the SCI INTV 7 0 Interrupt Vector Number The value of INTV 7 1 is used for both QSPI and SCI interrupt requests the value of INTVO used during an interrupt acknowledge cycle is supplied by the QSM INTVO is at logic level zero during an SCI interrupt and
516. os and writes have no effect Refer to D 3 Standby RAM Module for the register block address map and register bit field definitions M68HC16 Z SERIES STANDBY RAM MODULE USER S MANUAL For More Information On This Product 6 1 Go to www freescale com Freescale Semiconductor Inc 6 2 SRAM Array Address Mapping Base address registers RAMBAH and RAMBAL are used to specify the SRAM array base address in the memory map RAMBAH and RAMBAL can only be written while the SRAM is in low power stop mode RAMMCR STOP 1 and the base address lock RAMMCR RLCK 0 is disabled RLCK can be written once only to a value of one subsequent writes are ignored This prevents accidental remapping of the array NOTE In the CPU16 ADDR 23 20 follow the logic state of ADDR19 The SRAM array must not be mapped to addresses 080000 7FFFFF which are inaccessible to the CPU16 If mapped to these addresses the array remains inaccessible until a reset occurs or it is remapped outside of this range 6 3 SRAM Array Address Space Type The RASP 1 0 in RAMMCR determine the SRAM array address space type The SRAM module can respond to both program and data space accesses or to program space accesses only Because the CPU16 operates in supervisor mode only RASP 1 has no effect Table 6 2 shows RASP 1 0 encodings Table 6 2 SRAM Array Address Space Type RASP 1 0 Space X0 Program and data accesses X1 Program access only Refer to 5 5 1
517. ose timer GPT See GPT 11 1 GPT address map D 67 block diagram 11 2 capture compare unit 11 10 block diagram 11 11 features 3 2 general information 11 1 purpose 11 8 interrupt sources 11 6 D 69 interrupts 11 5 pins 11 7 polled and interrupt driven operation 11 4 prescaler 11 8 pulse accumulator 11 14 block diagram 11 15 width modulation unit PWM 11 16 block diagram 11 17 counter 11 18 reference manual 11 1 registers 11 2 capture compare registers action data register OC1D 11 14 mask register OC1M 11 14 timer compare force register CFORC 11 13 11 14 D 74 interrupt flag register 2 TFLG2 11 10 input capture 4 output compare 5 registers TI4 O5 0 72 capture registers TIC D 71 interrupt configuration register ICR D 68 control registers timer interrupt mask registers TMSK 11 10 11 12 module configuration register GPTMCR 0 67 test register GPTMTR D 68 OC1 action data register OC1D D 69 mask register OC1M D 69 output compare registers TOC D 71 parallel I O registers port GP data direction register DDRGP 11 8 11 14 D 69 register PORTGP 11 8 D 69 prescaler register PRESCL D 77 pulse accumulator registers Go to www freescale com Freescale Semiconductor Inc control register PACTL 11 8 11 14 11 16 D 70 counter register PACNT 11 14 D 70 width modulation registers counter register PWMCNT 11 18 PWM buffer registers PWMBUFA PWMBUFB D 76 control register C
518. ot cleared by the time a second transfer of data from the shift register to the read buffer is initiated an over run condition occurs In cases of overrun the byte or word causing the overrun is lost A write to the SPDR is not buffered and places data directly into the shift register for transmission 10 3 2 SPI Pins Four bidirectional pins are associated with the SPI The MPAR configures each pin for either SPI function or general purpose I O The MDDR assigns each as either input or output The WOMP bit in the SPI control register SPCR determines whether each SPI pin that is configured for output functions as an open drain output or a normal CMOS output The MDDR and WOMP assignments are valid regardless of whether the pins are configured for SPI use or general purpose I O The operation of pins configured for SCI use depends on whether the SCI is operating as a master or a slave determined by the MSTR bit in the SPCR Table 10 3 shows SPI pins and their functions MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 10 3 SPI Pin Functions Pin Name Mode Function Master in slave out MISO Master Provides serial data input to the SPI Master out slave in MOSI Master Provides serial output from the SPI Serial clock 5 Master Provides clock output from the SPI Slave select SS Mast
519. ow the state of ADDR19 3 3 System Block Diagram and Pin Assignment Diagrams Figure 3 1 is a functional diagram of the MC68HC16Z1 CKZ1 CMZ1 MCU Refer to Figure 3 2 for a functional diagram of the MC68HC16Z2 Z3 MCU Figure 3 3 is a functional diagram of the MC68HC16Z4 CKZ4 MCU Although diagram blocks repre sent the relative size of the physical modules there is not a one to one correspon dence between location and size of blocks in the diagram and location and size of integrated circuit modules OVERVIEW M68HC16 Z SERIES 3 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc M68HC16 Z series microcontrollers are available in both 132 and 144 pin packages Figure 3 4 shows MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 pin assignment drawing based on a 132 pin plastic surface mount package Figure 3 5 shows an MC68HC16Z1 CKZ1 CMZ1 Z2 Z3 pin assignment drawing based on a 144 pin plastic surface mount package Figure 3 6 shows 68 1674 74 pin assignment drawing based on 132 pin plastic surface mount package Figure 3 7 shows an 68 1674 274 pin assignment drawing based on a 144 pin plastic surface mount package Refer to APPENDIX B MECHANICAL DATA AND ORDERING IN FORMATION for information on how to obtain package dimensions Refer to subse quent paragraphs in this section for pin and signal descriptions M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Informatio
520. ower are derived from a common regulator filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned For example an RC low pass filter could be used to isolate the digital and analog supplies when generated by a common reg ulator If multiple high precision analog circuits are locally employed such as two A D converters the analog supplies should be isolated from each other as sharing sup plies introduces the potential for interference between analog circuits ANALOG TO DIGITAL CONVERTER M68HC16 Z SERIES 8 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Grounding is the most important factor influencing analog circuit performance in mixed signal systems or in stand alone analog systems Close attention must be paid to avoid introducing additional sources of noise into the analog circuitry Common sourc es of noise include ground loops inductive coupling and combining digital and analog grounds together inappropriately The problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle If the digital ground is not able to handle the large transients the current from the large transients can return to ground through the analog ground It is the excess current overflowing into the analog ground which causes performance degradation by developing a differentia
521. pF Group 3 I O Pins 130 Group 4 I O Pins 200 NOTES 1 Refer to notes in Table A 14 M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL A 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 13 20 97 MHz DC Characteristics Vip and Vsus 5 0 5 Veg 0 T T to T Characteristic Symbol Input High Voltage Input Low Voltage Input Hysteresis 2 Vuvs Input Leakage Current 4 Vin OF Vss High Impedance Off State Leakage Current Vin Vss loz CMOS Output High Voltage 7 F 10 0 uA VoL VoH CMOS Output Low Voltage 8 lot 10 0 Output High Voltage 7 lou 0 8 mA Output Low Voltage lot 1 6 mA lo 5 3 mA VoL 12 Three State Control Input High Voltage Data Bus Mode Select Pull Up Current 10 11 Vin ViL 120 uA MC68HC16Z1 Vpp Supply Current 12 13 12 Run 140 mA LPSTOP crystal VCO Off STSIM 0 DD 350 uA LPSTOP external clock input frequency maximum fsys 5 mA MC68HC16Z2 Z3 Vpp Supply Current 12 13 12A Run 140 mA LPSTOP crystal VCO Off STSIM 0 DD 2 mA LPSTOP external clock input frequency maximum fsys 10 mA 13 Clock Synthesizer Operating Voltage VpDsYN 4 75 5 25 MC68HC16Z1 Vppsyn Supply Current 13 VCO on crystal reference maxim
522. peration by setting up a queue of QSPI commands in com mand RAM writing transmit data into transmit RAM then enabling the QSPI The QSPI executes the queued commands sets a completion flag SPIF and then either interrupts the CPU16 or waits for intervention There are four queue pointers The CPU16 can access three of them through fields in QSPI registers The new queue pointer NEWQP contained in SPCR2 points to the first command in the queue An internal queue pointer points to the command currently being executed The completed queue pointer CPTQP contained in SPSR points to the last command executed The end queue pointer ENDQP contained in SPCR2 points to the final command in the queue QUEUED SERIAL MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The internal pointer is initialized to the same value as NEWQP During normal opera tion the command pointed to by the internal pointer is executed the value in the inter nal pointer is copied into CPTQP the internal pointer is incremented and then the sequence repeats Execution continues at the internal pointer address unless the value is changed After each command is executed ENDQP and CPTQP are compared When a match occurs the SPIF flag is set and the QSPI stops and clears SPE unless wrap around mode is enabled At reset NEWQP is initialized to 0 When the QSPI is en
523. perations before using a chip select to generate an interrupt ac knowledge signal 1 Program the base address field to all ones 2 Program block size to no more than 64 Kbytes so that the address comparator checks ADDR 19 16 against the corresponding bits in the base address regis ter The CPU16 places the CPU space bus cycle type on ADDR 19 16 3 Set the R W field to read only An interrupt acknowledge cycle is performed as a read cycle SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 68 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 Set the BYTE field to lower byte when using a 16 bit port as the external vector for a 16 bit port is fetched from the lower byte Set the BYTE field to upper byte when using an 8 bit port If an interrupting device does not provide a vector number an autovector acknowledge must be generated either by asserting the AVEC pin or by generating AVEC internally using the chip select option register This terminates the bus cycle 5 9 4 Chip Select Reset Operation The least significant bit of each of the 2 bit chip select pin assignment fields in CSPARO and CSPAR1 each have a reset value of one The reset values of the most significant bits of each field are determined by the states of DATA 7 1 during reset There are weak internal pull up drivers for each of the data lines so that chip select operation is selected by default out
524. periph eral chip select field enables peripherals for transfer The command control field pro vides transfer options A maximum of 16 commands can be in the queue Queue execution by the QSPI pro ceeds from the address in NEWQP through the address in ENDQP both of these fields are in SPCR2 9 3 3 QSPI Pins The QSPI uses seven pins These pins be configured for general purpose when not needed for QSPI application Table 9 2 shows QSPI input and output pins and their functions Table 9 2 QSPI Pins Pin Names Mnemonics Mode Function Master Serial data input to QSPI Master IM SIEVE Out MISO Slave Serial data output from QSPI Master Serial data output from QSPI Master Oui Slaven MOSI Slave Serial data input to QSPI Master Clock output from QSPI SCK Slave Clock input to QSPI Peripheral Chip Selects 5 3 1 Master Select peripherals Master Selects peripherals Slave Select 50 55 Master Causes mode fault Slave Initiates serial transfer 9 3 4 QSPI Operation The QSPI uses a dedicated 80 byte block of static RAM accessible by both the QSPI and the CPU16 to perform queued operations The RAM is divided into three seg ments There are 16 command bytes 16 transmit data words and 16 receive data words QSPI RAM is organized so that one byte of command data one word of trans mit data and word of receive data correspond to one queue entry 0 F The CPU16 initiates QSPI o
525. pheral chip select pins The following equation determines the actual delay before SCK PCS to SCK Delay DSCKLS 0 Sys where DSCKL 6 0 is in the range of one to 127 When DSCK is zero in a command RAM byte then DSCKL 6 0 is not used Instead the PCS valid to SCK transition is one half the SCK period DTL 7 0 Length of Delay after Transfer When the DT bit is set in a command RAM byte this field determines the length of the delay after a serial transfer The following equation is used to calculate the delay 32 x DTL 7 0 sys Delay after Transfer where DTL is in the range of one to 255 A zero value for DTL 7 0 causes a delay after transfer value of 8192 fsys If DT is zero in a command RAM byte a standard delay is inserted Standard Delay after Transfer 5 5 Delay after transfer can be used to provide a peripheral deselect interval delay also be inserted between consecutive transfers to allow serial A D converters to com plete conversion This is controlled by the DT bit in a command RAM byte D 6 12 QSPI Control Register 2 SPCR2 QSPI Control Register 2 YFFC1C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPIFIE WREN 0 ENDQP 3 0 0 0 0 0 NEWQP 3 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M68HC16 7 SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 49 Go to www freescale com Freescale Semiconductor Inc SPCR2 contains QSPI queue poi
526. plays a block diagram of the QSPI QUEUE CONTROL BLOCK QUEUE 4 POINTER A D COMPARATOR DONE E 5 5 80 BYTE END QUEUE POINTER R QSPI RAM E G CONTROL 5 LOGIC d E R STATUS REGISTER CONTROL R GISTERS jm CHIP SELECT DELAY jem COMMAND COUNTER M Ng LSB 5 8 16 BIT SHIFT REGISTER MOSI 50 55 PROGRAMMABLE E J LOGIC ARRAY RX TX DATA REGISTER DATA REGISTER PCSD2 1 BAUD RATE GENERATOR 5 50 QSPIBLOCK Figure 9 2 QSPI Block Diagram M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 5 Go to www freescale com Freescale Semiconductor Inc The serial transfer length is programmable from eight to sixteen bits inclusive An in ter transfer delay of 17 to 8192 system clocks can be specified default is 17 system clocks A dedicated 80 byte RAM is used to store received data data to be transmitted and a queue of commands The CPU16 can access these locations directly The command queue allows the QSPI to perform up to 16 serial transfers without CPU16 intervention Each queue entry contains all the information needed by the QSPI to independently complete one serial transfer A pointer identifies the queue location containing the data and command for the next serial transfer Normally the pointer address is incremented after each serial transfer but the CPU16 can change the pointer value at any time Suppor
527. port is 16 bits wide when the bus cycle begins Operand bytes are designated as shown in Figure 5 11 OP 0 3 represent the order of access For instance OPO is the most significant byte of a long word operand and is accessed first while the least significant byte is accessed last The two bytes of a word length operand are OPO most significant and OP1 The single byte of a byte length operand is OPO OPERAND BYTE ORDER LONG WORD THREE BYTE WORD BYTE OPERAND BYTE ORDER Figure 5 11 Operand Byte Order SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 34 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 5 3 Operand Alignment The EBI data multiplexer establishes the necessary connections for different combi nations of address and data sizes The multiplexer takes the two bytes of the 16 bit bus and routes them to their required positions Positioning of bytes is determined by the size and address outputs 5141 SIZO indicate the number of bytes remaining to be transferred during the current bus cycle The number of bytes transferred is equal to or less than the size indicated by 51271 and SIZO depending on port width ADDRO also affects the operation of the data multiplexer During a bus transfer ADDR 23 1 indicate the word base address of the portion of the operand to be ac cessed and ADDRO indicates the byte offset from the base NOTE ADDR 23 20
528. provided in APPENDIX A ELECTRICAL CHARAC TERISTICS Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY 3 1 M68HC16 Z Series MCU Features The following paragraphs highlight capabilities of each of the MCU modules Each module is discussed separately in a subsequent section of this manual 3 1 1 Central Processor Unit CPU16 CPU16L 16 bit architecture Full set of 16 bit instructions Three 16 bit index registers Two 16 bit accumulators Control oriented digital signal processing capability Addresses up to 1 Mbyte of program memory 1 Mbyte of data memory Background debug mode Fully static operation Expanded LPSTOP operation on CPU16L MC68HC16Z4 MC68CK16Z4 only 3 1 2 System Integration Module SIM SIML External bus support Programmable chip select outputs System protection logic Watchdog timer clock monitor and bus monitor Two 8 bit dual function input output ports One 7 bit dual function output port Phase locked loop PLL clock system Expanded LPSTOP operation SIML MC68HC16Z4 MC68CK16Z4 only 3 1 3 Standby RAM SRAM e 1 Kbyte static RAM MC68HC16Z1 Z4 only e 2 Kbyte static RAM MC68HC16Z2 only e 4 Kbyte static RAM MC68HC16Z3 only External standby voltage supply input M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product 3 Go to www freescale com Freescale Semiconductor
529. pt level register ILSCI determines the level of interrupts requested by each SCI Sepa rate fields hold the interrupt request levels for SCIA and SCIB The MCCI interrupt vector register MIVR determines which three vectors in the exception vector table are to be used for MCCI interrupts The SPI and both SCI interfaces have separate interrupt vectors adjacent to one another The SPI interrupt level register ILSPI de termines the priority level of interrupts requested by the SPI The MCCI port data reg isters PORTMC and PORTMCP are used to configure port MCCI for general purpose I O The MCCI pin assignment register MPAR determines which of the SPI pins with the exception of SCK are used by the SPI and which pins are available for general purpose I O The MCCI data direction register MDDR configures each as an input or output 10 2 1 1 Low Power Stop Mode When the STOP bit in the MMCR is set the IMB clock signal to most of the MCCI mod ule is disabled This places the module in an idle state and minimizes power consump tion MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc To ensure that the MCCI stops in a known state assert the STOP bit before executing the CPU LPSTOP instruction Before asserting the STOP bit disable the SPI clear the SPE bit and disable the SCI receivers and transmitters c
530. ption processing but are left pending Pending requests are pro cessed at instruction boundaries or when exception processing of higher priority inter rupts is complete The CPU16 does not latch the priority of a pending interrupt request If an interrupt source of higher priority makes a service request while a lower priority request is pend ing the higher priority request is serviced If an interrupt request with a priority equal to or lower than the current IP mask value is made the CPU16 does not recognize the occurrence of the request If simultaneous interrupt requests of different priorities are made and both have a priority greater than the mask value the CPU16 recognizes the higher level request 5 8 3 Interrupt Acknowledge and Arbitration When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value it places the interrupt request level on the address bus and initiates a CPU space read cycle The request level serves two purposes it is de coded by modules or external devices that have requested interrupt service to deter mine whether the current interrupt acknowledge cycle pertains to them and it is latched into the interrupt priority mask field in the CPU16 condition code register to preclude further interrupts of lower priority during interrupt service Modules or external devices that have requested interrupt service must decode the IP mask value placed on the address bus
531. pts are detected Because of pipelining the value of PK PC at the time a synchronous exception exe cutes is equal to the address of the instruction that causes the exception plus 0006 Because RTI always subtracts 0006 upon return the stacked PK PC must be ad justed by the instruction that caused the exception so that execution resumes with the following instruction For this reason 0002 is added to the PK PC value before it is stacked M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 39 Go to www freescale com Freescale Semiconductor Inc 4 13 5 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation Asynchronous exceptions have higher priorities than synchronous excep tions Exception processing for multiple exceptions is completed by priority from high est to lowest Priority governs the order in which exception processing occurs not the order in which exception handlers are executed Unless a bus error a breakpoint or a reset occurs during exception processing the first instruction of all exception handler routines is guaranteed to execute before an other exception is processed Because interrupt exceptions have higher priority than synchronous exceptions the first instruction in an interrupt handler is executed before other interrupts are sensed Bus error breakpoint and reset exceptions that occur dur
532. put capture 2 IVBA 0010 0011 Input capture 3 IVBA 0011 0100 Output compare 1 IVBA 0100 OC2 Output compare 2 IVBA 0101 Output compare 3 IVBA 0110 OC4 Output compare 4 IVBA 0111 IC4 OC5 Input capture 4 output compare 5 IVBA 1000 1001 1001 PAOV 1010 Pulse accumulator overflow IVBA 1010 PAI 1011 Pulse accumulator input IVBA 1011 The CPU16 recognizes only interrupt request signals of a priority greater than the con dition code register interrupt priority IP mask value When the CPU acknowledges an interrupt request the priority of the acknowledged request is written to the IP mask and driven out on the IMB address lines When the IP mask value driven out on the address lines is the same as the IRL value the GPT contends for arbitration priority GPT arbitration priority is determined by the value of IARB 3 0 in GPTMCR Each MCU module that can make interrupt requests must be assigned a non zero IARB value to implement an arbitration scheme Arbitra tion is performed by serial assertion of IARB 3 0 bit values When the GPT wins interrupt arbitration it responds to the CPU interrupt acknowledge cycle by placing an interrupt vector number on the data bus The vector number is used to calculate displacement into the CPU16 exception vector table Vector num bers are formed by concatenating the value in ICR IVBA 3 0 with a 4 bit value sup plied by the GPT when an interrupt request is mad
533. put from QSPI MOSI Master DDQS1 0 Disables data output 1 Serial data output from QSPI Slave 0 Serial data input to QSPI 1 Disables data input SCK Master DDQS2 Clock output from QSPI Slave Clock input to QSPI 50 55 Master DDQS3 0 Assertion causes mode fault 1 Chip select output Slave 0 QSPI slave select input 1 Disables slave select input PCS 1 3 Master DDQS 4 6 0 Disables chip select output 1 Chip select output Slave 0 Inactive 1 Inactive TXD DDQS7 X Serial data output from SCI RXD None NA Serial data input to SCI NOTES 1 PQS2 is a digital I O pin unless the SPI is enabled SPE set in SPCR1 in which case it becomes the QSPI serial clock SCK 2 PQS7 is a digital I O pin unless the SCI transmitter is enabled TE set in SCCR1 in which case it becomes the SCI serial data output TXD QUEUED SERIAL MODULE M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 9 3 Queued Serial Peripheral Interface The queued serial peripheral interface QSPI is used to communicate with external devices through a synchronous serial bus The QSPI is fully compatible with SPI sys tems found on other Freescale products but has enhanced capabilities The QSPI can perform full duplex three wire or half duplex two wire transfers A variety of transfer rates clocking and interrupt driven communication options is available Figure 9 2 dis
534. r byte of SCSR causes all 16 bits to be accessed and any status bit al ready set in either byte is cleared on a subsequent read or write of SCDR 9 4 1 3 Data Register SCDR contains two data registers at the same address The receive data register RDR is a read only register that contains data received by the SCI Data enters the receive serial shifter and is transferred to RDR The transmit data register TDR is a write only register that contains data to be transmitted Data is first written to TDR then transferred to the transmit serial shifter where additional format bits are added before transmission R 7 0 T 7 0 contain either the first eight data bits received when SCDR is read or the first eight data bits to be transmitted when SCDR is written R8 T8 are used when the SCI is configured for 9 bit operation When the SCI is configured for 8 bit operation they have no meaning or effect QUEUED SERIAL MODULE M68HC16 Z SERIES 9 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 9 4 2 SCI Pins Two unidirectional pins TXD transmit data and RXD receive data are associated with the SCI TXD can be used by the SCI or for general purpose I O TXD function is controlled by PQSPA7 in the port QS pin assignment register PQSPAR and TE in SCI control register 1 SCCR1 The receive data pin is dedicated to the SCI 9 4 3 SCI Operation The SCI can operate i
535. r that contains data received by the SCI serial interface The data comes into the receive serial shifter and is transferred to the RDR The TDR is a write only register that contains data to be transmitted The data is first written to the TDR then trans ferred to the transmit serial shifter where additional format bits are added before transmission 10 4 2 SCI Pins Four pins are associated with the SCI TXDA TXDB RXDA and RXDB The state of the TE or RE bit in SCI control register 1 of each SCI submodule SCCR1A SCCR1B determines whether the associated pin is configured for SCI operation or general pur pose I O The MDDR assigns each pin as either input or output The WOMC bit in SCCR14A SCCR1B determines whether the associated RXD and TXD pins when configured as outputs function as open drain output pins or normal CMOS outputs The MDDR and WOMC assignments are valid regardless of whether the pins are con figured for SPI use or general purpose SCI pins are listed in Table 10 5 MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 10 5 SCI Pins Pin Mode SCI Function Port I O Signal Serial data output SCIA TE 1 PMC7 Transmit data E TXDB Serial data output from SCIB TE 1 PMC5 RXDA Serial data input to SCIA RE 1 PMC6 Receive data 3 RXDB
536. rammed by writing a 13 bit value to the SCBR field in SCI control register zero SCCRO The baud rate is derived from the MCU system clock by a modulus counter Writing a value of zero to SCBR 12 0 disables the baud rate generator Baud rate is calculated as follows fsys SCI Baud Rate 32 x SCBR 12 0 or fsys SCBR 12 0 32 x SCI Baud Rate Desired where SCBR 12 0 is in the range 1 2 3 8191 The SCI receiver operates asynchronously An internal clock is necessary to synchro nize with an incoming data stream The SCI baud rate generator produces a receive time sampling clock with a frequency 16 times that of the SCI baud rate The SCI de termines the position of bit boundaries from transitions within the received waveform and adjusts sampling points to the proper positions within the bit period MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 10 4 5 4 Parity Checking The PT bit in SCCR1 selects either even PT 0 or odd PT 1 parity PT affects received and transmitted data The PE bit in SCCR1 determines whether parity check ing is enabled PE 1 or disabled PE 0 When PE is set the MSB of data frame is used for the parity function For transmitted data a parity bit is generated for received data the parity bit is checked When parity checking is enabled the PF bit in the SCI s
537. ransfer BITS 3 0 Bits Per Transfer 0000 16 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 CPOL Clock Polarity 0 The inactive state of SCK is logic zero 1 The inactive state of SCK is logic one CPOL is used to determine the inactive state of the serial clock SCK It is used with CPHA to produce a desired clock data relationship between master and slave devices CPHA Clock Phase 0 Data is captured on the leading edge of SCK and changed on the trailing edge of SCK 1 Data is changed on the leading edge of SCK and captured on the trailing edge of SCK CPHA determines which edge of SCK causes data to change and which edge causes data to be captured CPHA is used with CPOL to produce a desired clock data rela tionship between master and slave devices M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 47 Go to www freescale com Freescale Semiconductor Inc SPBR 7 0 Serial Clock Baud Rate The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system clock Baud rate is selected by writing a value from two to 255 into SPBR 7 0 The following equation determines the SCK baud rate fsys or fsys SPBR 7 0 2 x SCK Baud Rate Desired Giving SPBR 7 0 a value of zero or one disables the baud ra
538. rbitration enabled 01 Show cycles enabled external arbitration disabled 10 Show cycles enabled external arbitration enabled 11 Show cycles enabled external arbitration enabled internal activity is halted by a bus grant SUPV Supervisor User Data Space This bit has no effect because the CPU16 always operates in the supervisor mode REGISTER SUMMARY M68HC16 Z SERIES D 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc MM Module Mapping 0 Internal modules are addressed from 7FF000 7FFFFF 1 Internal modules are addressed from FFF000 FFFFFF The logic state of the MM determines the value of ADDR23 for IMB module addresses Because ADDR 23 20 are driven to the same state as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible to the CPU16 This bit can be written only once after reset IARB 3 0 Interrupt Arbitration ID Each module that can generate interrupts including the SIM has an IARB field Each IARB field can be assigned a value from 0 to F During an interrupt acknowledge cycle IARB permits arbitration among simultaneous interrupts of the same priority level The reset value of the SIM IARB field is F the highest priority This prevents SIM interrupts from being discarded during system initialization D 2 2 System Integration Test Register SIMTR System Integration Test Register YFFA02 Used for factory
539. rbitration priority is determined by the value of the IARB field in QOMCR Each module that can generate interrupt requests must have a non zero IARB value otherwise the CPU16 will identify any such interrupt requests as spu rious and take a spurious interrupt exception Arbitration is performed by means of se rial contention between values stored in individual module IARB fields When the QSM wins interrupt arbitration it responds to the CPU16 interrupt acknowl edge cycle by placing an interrupt vector number on the data bus The vector number is used to calculate displacement into the CPU16 exception vector table SCI and QSPI vector numbers are generated from the value in the QIVR INTV field The values of bits INTV 7 1 are the same for both the QSPI and the SCI The value of INTVO is supplied by the QSM when an interrupt request is made INTVO 0 for SCI interrupt requests INTVO 1 for QSPI interrupt requests At reset INTV 7 0 is initialized to 0F the uninitialized interrupt vector number To en able interrupt driven serial communication a user defined vector number must be writ ten to QIVR and interrupt handler routines must be located at the addresses pointed to by the corresponding vector Writes to INTVO have no effect Reads of INTVO return a value of one Refer to SECTION 4 CENTRAL PROCESSOR UNIT and SECTION 5 SYSTEM IN TEGRATION MODULE for more information about exceptions and interrupts M68HC16 Z SERIES QUEUED SERIAL
540. rder to use BDM development tools when an MCU is installed in a system Freescale recommends that appropriate signal lines be routed to a male Berg connector or double row header installed on the circuit board with the MCU Refer to Figure 4 8 BKPT DSCLK FREEZE IPIPE1 DSI 0 050 BDM CONN Figure 4 8 BDM Connector Pinout 4 16 Digital Signal Processing The CPU16 performs low frequency digital signal processing DSP algorithms in real time The most common DSP operation in embedded control applications is filtering but the CPU16 can perform several other useful DSP functions These include auto correlation detecting a periodic signal in the presence of noise cross correlation de termining the presence of a defined periodic signal and closed loop control routines selective filtration in a feedback path Although derivation of DSP algorithms is often a complex mathematical task the algo rithms themselves typically consist of a series of multiply and accumulate MAC operations The CPU16 contains a dedicated set of registers that perform MAC oper ations As a group these registers are called the MAC unit DSP operations generally require a large number of MAC iterations The CPU16 in struction set includes instructions that perform MAC setup and repetitive MAC opera tions Other instructions such as 32 bit load and store instructions can also be used in DSP routines Many DSP algorithms require extensive dat
541. read only registers at the end of each duty cycle Re set state is 0000 M68HC16 Z SERIES USER S MANUAL REGISTER SUMMARY D 76 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 8 18 GPT Prescaler PRESCL GPT Prescaler YFF92C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNUSED POWER ON RESET ONLY 0 0 0 0 0 0 0 0 0 The 9 bit prescaler value can be read from bits 8 0 at this address Bits 15 9 always read as zeros Reset state is 0000 M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL D 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc REGISTER SUMMARY M68HC16 Z SERIES D 78 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX E INITIALIZATION AND PROGRAMMING EXAMPLES This section contains basic initialization programs and several programming exercises using different M68HC16 Z series modules The purpose of these exercises is to pro vide the designer and programmer with a means to shorten design time All of the pro grams were written to run on the M68HC16Z1EVB evaluation board Refer to the M68HC1621EVB Evaluation Board User s Manual M68HC16Z1EVB D for further in formation NOTE These programs will also work on the Modular Evaluation Board MEVB using a microcontroller personality board for the appropriate Z series derivative See APPE
542. ription of each register M68HC16 Z SERIES CENTRAL PROCESSOR UNIT USER S MANUAL For More Information On This Product 4 1 Go to www freescale com 4 2 Freescale Semiconductor Inc BIT POSITION ACCUMU ACCUMU LATORS A AND B LATOR D A B ACCUMULATOR E DEX REG DEX REG DEX REG STER X STER Y STERZ K SK HR IR A A XMSK YMSK STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK ADDRESS EXTENSION REGISTER K STACK EXTENSION FIELD SK AC MULT AC MULT AC ACCU P P AC ACCU Figure 4 1 CPU16 Register Model CENTRAL PROCESSOR UNIT For More Information On This Product Go to www freescale com LIER REGISTER HR LICAND REGISTER IR ULATOR MSB 35 16 AM ULATOR LSB 15 0 AM AC XY MASK REGISTER CPU16 REGISTER MODEL M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc 4 2 1 Accumulators The CPU16 has two 8 bit accumulators A and B and one 16 bit accumulator E In addition accumulators A and B can be concatenated into a second 16 bit double ac cumulator D Accumulators A B and D are general purpose registers that hold operands and re sults during mathematical and data manipulation operations Accumulator E which can be used in the same way as accumulator D also extends CPU16 capabilities It allows more data to be held w
543. rite or for both read and write Use this field in conjunction with the STRB bit to generate asynchronous control signals for external devices The STRB bit controls the timing of a chip select assertion in asynchronous mode Se lecting address strobe causes a chip select signal to be asserted synchronized with the address strobe Selecting data strobe causes a chip select signal to be asserted synchronized with the data strobe This bit has no effect in synchronous mode DSACK 3 0 specifies the source of DSACK in asynchronous mode It also allows the user to optimize bus speed in a particular application by controlling the number of wait states that are inserted NOTE The external DSACK pins are always active SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 66 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SPACE 1 0 determines the address space in which chip select is asserted An ac cess must have the space type represented by the SPACE 1 0 encoding in order for a chip select signal to be asserted IPL 2 0 contains an interrupt priority mask that is used when chip select logic is set to trigger on external interrupt acknowledge cycles When SPACE 1 0 is set to 00 CPU space interrupt priority ADDR 3 1 is compared to the IPL field If the values are the same and other option register constraints are satisfied a chip select signal is asserted This field on
544. roduct Go to www freescale com 3 25 Freescale Semiconductor Inc OVERVIEW M68HC16 Z SERIES 3 26 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 4 CENTRAL PROCESSOR UNIT This section is an overview of the central processor unit CPU16 For detailed infor mation refer to the CPU16 Reference Manual CPU16RM AD 4 1 General The CPU16 provides compatibility with the M68HC11 CPU and also provides addition al capabilities associated with 16 and 32 bit data sizes 20 bit addressing and digital signal processing CPU16 registers are an integral part of the CPU and not ad dressed as memory locations The 16 treats all peripheral and memory locations as parts of a linear one Megabyte address space There no special instructions for I O that are separate from instructions for addressing memory Address space is made up of sixteen 64 Kbyte banks Specialized bank addressing techniques and support registers provide transparent access across bank boundaries The CPU16 interacts with external devices and with other modules within the micro controller via a standardized bus and bus interface There are bus protocols used for memory and peripheral accesses as well as for managing a hierarchy of interrupt priorities 4 2 Register Model Figure 4 1 shows the CPU16 register model Refer to the paragraphs that follow for a detailed desc
545. rogramming example involves using a port of the serial communication interface one of the serial interfaces of the queued serial module QSM to dis play a message on a dummy terminal Refer to SECTION 9 QUEUED SERIAL MODULE for more information on the QSM or the SCI E 2 3 1 Example 6 Using an SCI Port Description This program uses the SCI port to display a shameless message on a dummy terminal a subroutine to print a single and a subroutine that uses the subroutine to print an entire string INCLUDE EQUATES ASM addresses INCLUDE ORGOO000 ASM INCLUDE ORGOO008 ASM ORG 0200 Initialize INCLUDE INITSYS ASM INCLUDE INITRAM ASM INCLUDE INITSCI ASM LDAB 500 TBX LDAB 501 TBZ LDZ 50000 L J B in DX SR RA Program 5 STRING MAIN END_STRING Subroutines L B J E 24 SEND_STRING DAB 0 X EQ STRING DONI SR SEND CH It includes character to the SCI single character table of EQUates for common register initialize reset vector initialize interrupt vectors Start program after exception vector table initially set EK F XK 0 Set sys cl
546. rom an operand or an extension field to form a 20 bit effective address NOTE Access across 64 Kbyte address boundaries is transparent AD DR 19 16 of the effective address are changed to make an access across a bank boundary Extension field values will not change as a result of effective address computation 4 6 1 Immediate Addressing Modes In the immediate modes an argument is contained in a byte or word immediately fol lowing the instruction For IMM8 and IMM16 modes the effective address is the ad dress of the argument There are three specialized forms of IMM8 addressing The AIS AIX AIY AIZ ADDD and ADDE instructions decrease execution time by sign extending the 8 bit immediate operand to 16 bits then adding it to an ap propriate register The MAC and RMAC instructions use an 8 bit immediate operand to specify two signed 4 bit index register offsets The PSHM and PULM instructions use an 8 bit immediate mask operand to indi cate which registers must be pushed to or pulled from the stack M68HC16 Z SERIES CENTRAL PROCESSOR UNIT USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 4 6 2 Extended Addressing Modes Regular extended mode instructions contain ADDR 15 0 in the word following the op code The effective address is formed by concatenating the EK field and the 16 bit byte address EXT20 mode is used only by the JMP and JSR instructions T
547. rs and Address Map uic inen atn ctt 10 2 10 2 1 MCCI Global Registers gc 10 2 10 2 1 1 Lon POST 10 2 10 2 1 2 10 3 10 2 1 3 MCCI Interrupts 10 3 10 2 2 Pin Control and General Purpose 10 4 10 3 Serial Peripheral Interface 10 4 10 3 1 SEI tel iniu 10 6 10 3 1 1 SPI Control Register SPCR 10 6 10 3 1 2 SPI Status CSPISPL user reda acr lx bcr ern th Ra dae ci k EE ERA 10 6 10 3 1 3 SPI Data Register SPDR bsucibu pim R IM HERD RM MM 10 6 10 3 2 cci NN reenact 10 6 10 3 3 SP lOperating s vtt 10 7 10 3 3 1 Master Mode M 10 7 10 3 3 2 coctis P 10 8 10 3 4 SPI Glock Phase and Polarity Controls 10 8 10 3 4 1 CPHA 0 Transfer Format 10 9 10 3 4 2 POMA na 10 10 10 3 5 SPI Serial Clock Baud Rate accept cestode 10 11 10 3 6 Wired OR Open Drain Outputs 10 11 10 3 7 Transier Size and DAE CN o 10 11 10 3 8 Write 10 12 10 3 9 NR E E 10 12 10 4 Serial Communication Interface 10 13 10 4 1 10 13 10 4 1 1 SCI
548. rupt request if the corresponding bit is set in the timer interrupt mask register 1 TMSK1 If the ICxl bit is cleared software must poll the status flag to determine that an event has occurred Refer to 11 4 Polled and Interrupt Driven Operation for more information Input capture events are generally asynchronous to the timer counter Because of this input capture signals are conditioned by a synchronizer and digital filter Events are synchronized with the system clock and digital filter Events are synchronized with the system clock so that latching of TCNT content and counter incrementation occur on opposite half cycles of the system clock Inputs have hysteresis Capture of any tran sition longer than two system clocks is guaranteed any transition shorter than one system clock has no effect Figure 11 4 shows the relationship of system clock to synchronizer output The value latched into the capture register is the value of the counter several system clock cycles after the transition that triggers the edge detection logic There can be up to one clock cycle of uncertainty in latching of the input transition Maximum time is determined by the system clock frequency The input capture register is a 16 bit register A word access is required to ensure co herency If coherency is not required byte accesses can be used to read the register Input capture registers can be read at any time without affecting their values GENERAL PURP
549. rupt Vector Register QIVR YFFCO6 Not Used YFFCO8 SCI Control 0 Register SCCRO YFFCOA SCI Control 1 Register SCCR1 YFFCOC SCI Status Register SCSR YFFCOE SCI Data Register SCDR YFFC10 Not Used YFFC12 Not Used YFFC14 Not Used Port QS Data Register PORTQS YFFC16 Fores Register QS Data Direction Register DDRQS YFFC18 SPI Control Register 0 SPCRO 1 SPI Control Register 1 SPCR1 YFFC1C SPI Control Register 2 SPCR2 YFFC1E SPI Control Register 3 SPCR3 SPI Status Register SPSR Not Used DIE Receive RAM RR O F DOS Transmit RAM TR O F Command CR O F 1 M111 where M is the logic state the module mapping MM bit in the SIMCR D 6 1 QSM Configuration Register QSMCR QSM Configuration Register YFFCOO 15 14 13 12 1 10 9 8 1 6 5 4 3 2 1 0 STOP FRZ1 FRZO NOT USED SUPV NOT USED IARB 3 0 RESET 0 0 0 1 0 0 0 0 QSMCR bits enable stop and freeze modes determine the arbitration priority of QSM interrupt requests M68HC16 Z SERIES USER S MANUAL REGISTER SUMMARY D 38 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc STOP Low Power Stop Mode Enable 0 QSM clock operates normally 1 QSM clock is stopped When STOP is set the QSM enters low power stop mode The system clock input to the module is disabled While STOP is set only reads and writes ar
550. rupt priority IP mask value The interrupt priority mask consists of three bits in the CPU16 condition code register CCR 7 5 Binary values 96000 to 96111 provide eight priority masks Masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed IRQ7 however is always recognized even if the mask value is 96111 IRQ 7 1 are active low level sensitive inputs The low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected IRQ7 is transition sensitive as well as level sensitive a level 7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line This prevents redundant servicing and stack overflow A non maskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask is written while IRQ7 is asserted If IRQ7 is asserted and the IP mask is written to any new value including 96111 IRQ7 will be recognized as new IRQ7 SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5 58 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Interrupt requests are sampled on consecutive falling edges of the system clock terrupt request input circuitry has hysteresis To be valid a request signal must be as serted for at least two consecutive clock periods Valid requests do not cause immediate exce
551. s If a branch condition is satisfied a byte or word signed two s complement offset is added to the concatenat ed PK field and program counter The new PK PC value is the effective address 4 6 7 Post Modified Index Addressing Mode Post modified index mode is used by the MOVB and MOVW instructions A signed 8 bit offset is added to index register X after the effective address formed by XK IX is used CENTRAL PROCESSOR UNIT M68HC16 Z SERIES 4 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 6 8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode In M68HC11 systems the direct addressing mode can be used to perform rapid ac cesses to RAM or I O mapped from 0000 to 00FF The CPU16 uses the first 512 bytes of bank 0 for exception vectors To provide an enhanced replacement for the M68HC1 1 s direct addressing mode the ZK field and index register Z have been as signed reset initialization vectors By resetting the ZK field to a chosen page and using indexed mode addressing a programmer can access useful data structures anywhere in the address map 4 7 Instruction Set The CPU16 instruction set is based on the M68HC11 instruction set but the opcode map has been rearranged to maximize performance with a 16 bit data bus Most M68HC11 code can run on the CPU16 following reassembly The user must take into account changed instruction times the interrupt mask a
552. s Product Go to www freescale com Freescale Semiconductor Inc CSORBT and CSOR 0 10 contain parameters that support operations from external memory devices Bit and field definitions for CSORBT and CSOR 0 10 are the same MODE Asynchronous Synchronous Mode 0 Asynchronous mode is selected 1 Synchronous mode is selected and used with peripherals In asynchronous mode chip select assertion is synchronized with AS and DS In synchronous mode the chip select signal is asserted with ECLK BYTE 1 0 Upper Lower Byte Option This field is used only when the chip select 16 bit port option is selected in the pin as signment register This allows the usage of two external 8 bit memory devices to be concatenated to form a 16 bit memory Table D 13 shows upper lower byte options Table D 13 BYTE Field Bit Encoding BYTE 1 0 Description 00 Disable 01 Lower byte 10 Upper byte 11 Both bytes R W 1 0 Read Write This field causes a chip select to be asserted only for a read only for a write or for both read and write Table D 14 shows the options Table D 14 Read Write Field Bit Encoding R W 1 0 Description 00 Disable 01 Read only 10 Write only 11 Read Write STRB Address Strobe Data Strobe This bit controls the timing for assertion of a chip select in asynchronous mode only Selecting address strobe causes the chip select to be asserted synchronized with ad dress strobe Sel
553. s Register ADCSTAT YFF710 Right Justified Unsigned Result Register 0 RJURRO YFF712 Right Justified Unsigned Result Register 1 RJURR1 YFF714 Right Justified Unsigned Result Register 2 RJURR2 YFF716 Right Justified Unsigned Result Register 3 RJURR3 YFF718 Right Justified Unsigned Result Register 4 RJURR4 YFF71A Right Justified Unsigned Result Register 5 RJURR5 YFF71C Right Justified Unsigned Result Register 6 RJURR6 YFF71E Right Justified Unsigned Result Register 7 RJURR7 YFF720 Left Justified Signed Result Register 0 LJSRRO YFF722 Left Justified Signed Result Register 1 LJSRR1 YFF724 Left Justified Signed Result Register 2 LJSRR2 YFF726 Left Justified Signed Result Register LJSRR3 YFF728 Left Justified Signed Result Register 4 LUSRR4 YFF72A Left Justified Signed Result Register 5 LJSRR5 YFF72C Left Justified Signed Result Register 6 LJSRR6 YFF72E Left Justified Signed Result Register 7 LJSRR7 YFF730 Left Justified Unsigned Result Register 0 LJURRO YFF732 Left Justified Unsigned Result Register 1 LJURR1 YFF734 Left Justified Unsigned Result Register 2 LJURR2 YFF736 Left Justified Unsigned Result Register LJURR3 YFF738 Left Justified Unsigned Result Register 4 LJURR4 YFF73A Left Justified Unsigned Result Register 5 LJURR5 YFF73C Left Justified Unsigned Result Register 6 LJURR6 YFF73E Left Justified Unsigned Result Register 7 LJURR7 NOTES 1 Y M111 where M is the logic
554. s a status flag in TFLG1 or TFLG2 The GPT sets the flags they cannot be set by the CPU TFLG1 and TFLG2 are 8 bit registers that can be accessed individually or as one 16 bit register The registers are initialized to zero at reset Table 11 1 shows status flag assignment GENERAL PURPOSE TIMER M68HC16 Z SERIES 11 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 11 1 GPT Status Flags Tus Source IC1F TFLG1 Input capture 1 IC2F TFLG1 Input capture 2 ICSF TFLG1 Input capture 3 TFLG1 Output compare 1 OC2F TFLG1 Output compare 2 OC3F TFLG1 Output compare 3 TFLG1 Output compare 4 4 TFLG1 Input capture 4 output compare 5 TOF TFLG2 Timer overflow PAOVF TFLG2 Pulse accumulator overflow PAIF TFLG2 Pulse accumulator input For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2 in the same bit position If a mask bit is set and an associated event occurs a hard ware interrupt request is generated In order to re enable a status flag after an event occurs the status flags must be cleared Status registers are cleared in a particular sequence The register must first be read for set flags then zeros must be written to the flags that are to be cleared If a new event occurs between the time that the register is read and the time that it is written the associated flag is not cleared
555. s an internal voltage source used to precharge the DAC capacitor array before each sample The value of this supply is 2 or 2 5 volts for 5 volt operation The following paragraphs provide a simplified description of the interaction between the ADC and the user s external circuitry This circuitry is assumed to be a simple RC low pass filter passing a signal from a source to the ADC input pin The following sim plifying assumptions are made The source impedance is included with the series resistor of the RC filter The external capacitor is perfect no leakage no significant dielectric absorption characteristics etc All parasitic capacitance associated with the input pin is included in the value of the external capacitor Inductance is ignored resistance of the internal switches is zero ohms and the off resistance is infinite 8 8 6 1 Settling Time for the External Circuit The values for Re and Cp in the user s external circuitry determine the length of time required to charge Cr to the source voltage level Vsnc At time t 2 0 S1 in Figure 8 10 closes S2 is open disconnecting the internal circuitry from the external circuitry Assume that the initial voltage across CF is zero As CF charges the voltage across it is determined by the following equation where t is the total charge time n Vcr Venc 1 e When t 0 the voltage across 0 As t approaches infin
556. s as many bits as it receives at each queue address until the BITS 3 0 value is reached or SS is negated SS does not need to go high between transfers as the QSPI transfers data until reaching the end of the queue whether SS remains low or is toggled between transfers When the QSPI reaches the end of the queue it sets the SPIF flag If the SPIFIE bit in SPCR2 is set an interrupt request is generated when SPIF is asserted At this point the QSPI clears SPE and stops unless wrap around mode is enabled 9 3 5 4 Slave Wrap Around Mode Slave wrap around mode is enabled by setting the WREN bit in SPCR2 The queue can wrap to pointer address 0 or to the address pointed to by NEWQP depending on the state of the WRTO bit in SPCR2 Slave wrap around operation is identical to mas ter wrap around operation 9 3 6 Peripheral Chip Selects Peripheral chip select signals are used to select an external device for serial data transfer Chip select signals are asserted when a command in the queue is executed Signals are asserted at a logic level corresponding to the value of the PCS 3 0 bits in each command byte More than one chip select signal can be asserted at a time and more than one external device can be connected to each PCS pin provided proper fanout is observed PCSO shares pin with the slave select SS signal which initiates slave mode serial transfer If SS is taken low when the QSPI is in master mode a mode fault occurs To conf
557. s equal to M111 where M is the logic state of the module mapping MM bit in the system integration module configuration register SIMCR Since the CPU16 uses only ADDR 19 0 and ADDR 23 20 follow the logic state of ADDR19 when CPU driv en the CPU cannot access IMB addresses from 080000 to F7FFFF In order for the MCU to function correctly MM must be set Y must equal F If M is cleared internal registers are mapped to base address 700000 and are inaccessible until a reset oc curs The SRAM array is positioned by a base address register in the SRAM CTRL block Unimplemented blocks are mapped externally OVERVIEW M68HC16 Z SERIES 3 16 For More Information On This Product USER S MANUAL Go to www freescale com 5000000 Y FF 700 Y FF73F Y FF 900 YFF93F YFFA00 YFFATF Y FF B00 YFFBO7 YFFCOO YFFDFF FFFFFF Freescale Semiconductor Inc ADC 64 BYTES GPT 64 BYTES SIM 128 BYTES SRAM CONTROL 1 SRAM ARRAY 8 BYTES MAPPED TO 1K BOUNDARY QSM 512 BYTES HC16Z1 CKZ1 CMZ1 ADDRESS Figure 3 8 MC68HC16Z1 CKZ1 CMZ1 Address M68HC16 Z SERIES USER S MANUAL OVERVIEW For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 000000 Y FF700 Y FF73F Y FF820 Y FF83F Y FF900 YFF93F 00 YFFATF 00 YFFBO7 YFFCO0 Y FFDFF FFFFFF 000000 YFF700
558. s register at any time M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL For More Information On This Product 10 13 Go to www freescale com Freescale Semiconductor Inc TRANSMITTER BAUD RATE CLOCK WRITE ONLY SCDR TX BUFFER MooR PIN BUFFER 9 AND CONTROL PARITY GENERATOR SIZE 8 9 BREAK J 5 SHIFT ENABLE OPEN DRAIN OUTPUT MODE ENABLE TRANSFER TX BUFFER FORCE PIN DIRECTION OUT SCCR1 CONTROL REGISTER 1 SR STATUS REGISTER TDRE SCIRX REQUESTS S MEQUER UE T INTERNAL DATA BUS MCCI SCI TX BLOCK Figure 10 5 SCI Transmitter Block Diagram MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc RECEIVER BAUD RATE CLOCK ALL ONES PARITY DETECT SCDR RX BUFFER READ ONLY SCITX REQUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS MCCI SCI RX BLOCK Figure 10 6 SCI Receiver Block Diagram M68HC16 Z SERIES MULTICHANNEL COMMUNICATION INTERFACE USER S MANUAL 10 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc contains a number of SCI configuration parameters including transmitter and receiver enable bits interrupt enable
559. scale Semiconductor Inc Table A 32 ADC Maximum Ratings Parameter Symbol EA Internal Digital Supply with reference to Vas 0 3 Reference SPEY with reference to Vas VRL Vpp Differential Voltage 6 5 Vrer Differential ee VRH VRL 6 5 Disruptive Input Current VNeGcLamp 0 3 V Veosciamp 8 V Positive Overvoltage Current Coupling Ratio 9 9 9 1 5 6 8 Negative Overvoltage Current Coupling Ratio Maximum Input Current 346 12 VNeGcLamp 0 3 V 25 25 mA 8 V NOTES 1 Below disruptive current conditions a stressed channel will store the maximum conversion value for analog inputs greater than Vay and the minimum conversion value for inputs less than Vp This assumes that Vay lt Vppa and Vg gt Vssa due to the presence of the sample amplifier Other channels are not affected by non disruptive conditions 2 Input signals with large slew rates or high frequency noise components cannot be converted accurately These signals also interfere with conversion of other channels 3 Exceeding limit may cause conversion error on stressed channels and on unstressed channels Transitions within the limit do not affect device reliability or cause permanent damage 4 Input must be current limited to the value specified To determine the value of the required current limiting re sistor calculate resistance values using positive and negative
560. scription This program demonstrates the ability of the 68HC16 to change clock frequencies on the fly n this particular case we alternate between frequency of 16 78MHz and 4 194MHz Note that because we are writing to the screen we also need to correct the BAUD rate 1200 each time we change the frequency Make sure that your terminal has been set up to receive at 1200 baud oscilloscope may be connected to the CLKOUT pin on the EVB to observe the frequency change lt INCLUDE EQUATES ASM table of EQUates for common registers INCLUDE ORGOO000 ASM initialize reset vectors INCLUDE ORGOO008 ASM initialize interrupt vectors ORG 0200 Start program after the exception vector table Initialize KkKKKK INIT INCLUDE INITSYS ASM initially set EK F 0 0 2 0 sys clock at 16 78 MHz disable COP INCLUDE INITRAM ASM turn on internal 1K SRAM at 10000 set stack in bank 1 SK 1 SP 03FE LDD 5000 INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES E 16 For More Information On This Product USER S MANUAL Go to www freescale com CNT DLY KKKKK MAIN NOT_L LOOP1 LOOP2 LOOP3
561. set Extended 20 bit extended 8 bit immediate 16 bit immediate IX with unsigned 8 bit offset IY with unsigned 8 bit offset IZ with unsigned 8 bit offset IX with signed 16 bit offset IY with signed 16 bit offset IZ with signed 16 bit offset IX with signed 20 bit offset IY with signed 20 bit offset IZ with signed 20 bit offset Inherent Post modified indexed 8 bit relative 16 bit relative 4 bit address extension 8 bit unsigned offset 16 bit signed offset High byte of 16 bit extended address 8 bit immediate data High byte of 16 bit immediate data Low byte of 16 bit immediate data Low byte of 16 bit extended address 8 bit mask 16 bit mask 8 bit unsigned relative offset 16 bit signed relative offset index register X offset index register Y offset 4 bit zero extension AND Inclusive OR OR Exclusive OR EOR Complementation Concatenation Transferred Exchanged Sign bit also used to show tolerance Sign extension Binary value Hexadecimal value M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 8 Comparison of CPU16 and M68HC11 CPU Instruction Sets Most M68HC11 CPU instructions are a source code compatible subset of the CPU16 instruction set However certain M68HC11 CPU instructions have been replaced by functionally equivalent CPU16 instructions and some CPUf16 instructions with the same mnemonics as M68HC11 CPU instructions operate differen
562. set IARB value for all other modules is 0000 which prevents SIM interrupts from being discarded during initialization Refer to 5 8 Interrupts for a discussion of interrupt arbitration 5 2 3 Show Internal Cycles A show cycle allows internal bus transfers to be monitored externally The SHEN field in SIMCR determines what the external bus interface does during internal transfer op erations Table 5 1 shows whether data is driven externally and whether external bus arbitration can occur Refer to 5 6 6 1 Show Cycles for more information Table 5 1 Show Cycle Enable Bits Action Show cycles disabled external arbitration enabled 01 Show cycles enabled external arbitration disabled 10 Show cycles enabled external arbitration enabled 11 Show cycles enabled external arbitration enabled internal activity is halted by a bus grant 5 2 4 Register Access M68HC16 Z series MCUs always operate at the supervisor level The state of the SUPV bit has no meaning 5 2 5 Freeze Operation The FREEZE signal halts MCU operations during debugging FREEZE is asserted in ternally by the CPU16 if a breakpoint occurs while background mode is enabled When FREEZE is asserted only the bus monitor software watchdog and periodic interrupt timer are affected The halt monitor and spurious interrupt monitor continue to operate normally Setting the freeze bus monitor FRZBM bit in SIMCR disables the bus mon itor when FREEZE is asserted Settin
563. state of the MM bit in the SIMCR M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL D 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 5 1 ADC Module Configuration Register ADCMCR ADC Module Configuration Register YFF700 15 14 13 12 8 7 6 0 STOP FRZ NOT USED SUPV NOT USED RESET 1 0 0 1 ADCMCR controls ADC operation during low power stop mode background debug mode and freeze mode STOP Low Power Stop Mode Enable 0 Normal operation 1 Low power operation STOP places the ADC in low power state Setting STOP aborts any conversion in progress STOP is set to logic level one during reset and may be cleared to logic level zero by the CPU16 Clearing STOP enables normal ADC operation However be cause analog circuitry bias current has been turned off there is a period of recovery before output stabilization FRZ 1 0 Freeze Assertion Response The FRZ field determines ADC response to assertion of the FREEZE signal when the device is placed in background debug mode Refer to Table D 25 Table D 25 Freeze Encoding FRZ 1 0 Response 00 Ignore FREEZE continue conversions 01 Reserved 10 Finish conversion in process then freeze 11 Freeze immediately SUPV Supervisor Unrestricted This bit has no effect because the CPU16 always operates in supervisor mode D 5 2 ADC Test Register ADCTEST Test Register YFF702 Used for f
564. t Go to www freescale com Freescale Semiconductor Inc Table A 15 Low Voltage 16 78 MHz AC Timing Vip Voss 2 7 to 3 6 0 T T to Num Characteristic Symbol Min Max Unit 1 Frequency of Operation f 16 78 MHz 1 Clock Period 59 6 ns 1A ECLK Period 476 ns 1B External Clock Input Period lxcyc 64 ns E 2 Pulse Width tecw 236 ns 2B External Clock Input High Low Time 32 ns 4 5 CLKOUT Rise and Fall Time tort 9 ns 4A 5A Rise and Fall Time All outputs except CLKOUT tet 0 8 ns 4B 5B External Clock Input Rise and Fall Time 0 5 ns 6 Clock High to ADDR FC SIZ Valid 0 35 ns 7 Clock High to ADDR Data FC SIZ High Impedance toHazx 2 59 ns 8 Clock High to ADDR FC SIZ Invalid lCHAZn 0 ns 9 Clock Low to AS DS CS Asserted tcLsa 2 25 ns 9A AS to DS or CS Asserted Read tstsa 15 15 ns 11 ADDR FC SIZ Valid to AS CS and DS Read Asserted tavsa 15 ns 12 Clock Low to AS DS CS Negated 2 29 ns 13 AS DS CS Negated to ADDR FC SIZ Invalid Address Hold ns 14 5 CS and DS Read Width Asserted ns 14A 05 CS Width Asserted Write tewAW 45 ns 14B 5 CS and DS Read Width Asserted Fast Cycle tswow 40 ns 15 AS DS CS Width Negated ton 40 ns 16 Clock High to AS DS R W
565. t for multiple tasks can be provided by segmenting the queue The QSPI has four peripheral chip select pins The chip select signals simplify inter facing by reducing CPU16 intervention If the chip select signals are externally decod ed 16 independent select signals can be generated Wrap around mode allows continuous execution of queued commands In wrap around mode newly received data replaces previously received data in the receive RAM Wrap around mode can simplify the interface with A D converters by continu ously updating conversion values stored in the RAM Continuous transfer mode allows an uninterrupted bit stream of eight to 256 bits in length to be transferred without CPU16 intervention Longer transfers are possible but minimal intervention is required to prevent loss of data A standard delay of 17 system clocks is inserted between the transfer of each queue entry 9 3 1 QSPI Registers The programmer s model for the QSPI consists of the QSM global and pin control reg isters four QSPI control registers SPCR 0 3 the status register SPSR and the 80 byte QSPI RAM Registers and RAM can be read and written by the CPU16 Refer to D 6 Queued Serial Module for register bit and field definitions 9 3 1 1 Control Registers Control registers contain parameters for configuring the QSPI and enabling various modes of operation The CPU16 has read and write access to all control registers The QSM has read access only to al
566. t tnn thea eina 3 18 3 11 MC68HC16Z1 CKZ1 CMZ1 Combined Program and Data Space E E 3 20 3 12 68 16 2 3 Combined Program and Data Space Map 3 21 3 13 MC68HC16Z4 CKZ4 Combined Program and Data Space Map 3 22 14 MC68HC16Z1 CKZ1 CMZ1 Separate Program ana Darr opace ACD oM Tro Pm SMS 3 23 MC68HC16Z22 Z3 Separate Program and Data Space Map 3 24 MC68HC16Z4 CKZ4 Separate Program and Data Space Map 3 25 4 1 gt Mm 4 2 4 2 Condition Code Register 0 4088 4 4 4 3 Data Types and Memory Organization 2 2404 11 4 8 4 4 Basic Bruce BO PONO ausa kde ep Mp epit alid iod iiw 4 34 4 5 Insiruction Execution Model 4 35 4 6 Exception Stack Frame Format 4 38 4 7 BDM VO 4 44 4 8 BDM Connector PINON EEN E 4 45 5 1 System Integration Module Block Diagram 5 2 5 2 Block 5 4 5 3 Slow Reference Crystal Circuit 2 4 40450000 5 5 5 4 Fast Crystal COUI suae deir e a nea n La Sri itte madii 5 5 5 5 System Clock Filter Networks
567. ta bus and a buffered IMB data bus Reg isters not directly associated with conversion functions such as the configuration reg ister the test register and the port data register reside on the buffered bus while conversion registers and result registers reside on the differential bus Registers that reside on the buffered bus are updated immediately when written How ever writes to ADC control registers abort any conversion in progress 8 4 ADC Bus Interface Unit The ADC is designed to act as a slave device on the intermodule bus The ADC bus interface unit ABIU provides IMB bus cycle termination and synchronizes internal ADC signals with IMB signals The ABIU also manages data bus routing to accommo date the three conversion data formats and controls the interface to the module differ ential data bus 8 5 Special Operating Modes Low power stop mode and freeze mode are ADC operating modes associated with as sertion of IMB signals by other microcontroller modules or by external sources These modes are controlled by the values of bits in the ADC module configuration register ADCMCR 8 5 1 Low Power Stop Mode When the STOP bit in ADCMCR is set the IMB clock signal to the ADC is disabled This places the module in an idle state and power consumption is minimized The ABIU does not shut down and ADC registers are still accessible If a conversion is in progress when STOP is set it is aborted M68HC16 Z SERIES ANALOG TO DIGI
568. tact your Freescale representative for further information C 1 M68MMDS1632 Modular Development System The M68MMDS1632 Freescale modular development system MMDS is a develop ment tool for evaluating M68HC16 and M68300 MCU based systems The 1632 is an in circuit emulator which includes a station module and active probe A separately purchased MPB and PPB completes MMDS functionality with re gard to a particular MCU or MCU family The many MPBs and PPBs available let the MMDS emulate a variety of different MCUs Contact your Freescale sales representa tive who will assist you in selecting and configuring the modular system that fits your needs A full featured development system the MMDS provides both in circuit emula tion and bus analysis capabilities including Real time in circuit emulation at maximum speed of 16 MHz Built in emulation memory 1 Mbyte main emulation memory three clock bus cycle 256 Kbyte fast termination two clock bus cycle 4 Kbyte dual port emulation memory three clock bus cycle Real time bus analysis Instruction disassembly State machine controlled triggering Four hardware breakpoints bitwise masking e Analog digital emulation Synchronized signal output Built in AC power supply 90 264 V 50 60 Hz FCC and EMI compliant RS 232 connection to host capable of communicating at 1200 2400 4800 9600 19200 38400 or 57600 baud M68HC16 Z SERIES DEVELOPMENT S
569. tart bit eight data bits LSB first and one stop bit a total of ten bits The most common 1 1 bit data frame contains one start bit eight data bits a parity or control bit and one stop bit Ten bit and 11 bit frames are shown in Table 9 4 M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For More Information On This Product 9 25 Go to www freescale com Freescale Semiconductor Inc Table 9 4 Serial Frame Formats 10 Bit Frames Start Data Parity Control Stop 1 7 2 SE 11 Bit Frames Start Data Parity Control Stop 1 7 1 2 13 14 9 4 3 3 Baud Clock The SCI baud rate is programmed by writing a 13 bit value to the SCBR field in SCI control register 0 SCCRO The baud rate is derived from the MCU system clock by a modulus counter Writing a value of zero to SCBR 12 0 disables the baud rate gener ator Baud rate is calculated as follows Ius SCI Baud Rate 32 x SCBH 12 0 or fsys SCBR 12 0 32 x SCI Baud Rate Desired where SCBR 12 0 is in the range 1 2 3 8191 The SCI receiver operates asynchronously An internal clock is necessary to synchro nize with an incoming data stream The SCI baud rate generator produces a receive time sampling clock with a frequency 16 times that of the SCI baud rate The SCI de termines the position of bit boundaries from transitions within the received waveform and adjusts sampli
570. tatus register SCSR is set if a parity error is detected Enabling parity affects the number of data bits in a frame which can in turn affect frame size Table 10 7 shows possible data and parity formats Table 10 7 Effect of Parity Checking on Data Size M Result 0 8 data bits Era iT pa 31 o pow 8 data bits 1 parity bit 10 4 5 5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register TDR located in the SCI data register SCDR The serial shifter cannot be directly accessed by the CPU16 The transmitter is double buffered which means that data can be loaded into the TDR while other data is shifted out The TE bit in SCCR1 enables TE 1 and disables TE 0 the transmitter Shifter output is connected to the TXD pin while the transmitter is operating TE 1 or TE 0 and transmission in progress Wired OR operation should be specified when more than one transmitter is used on the same SCI bus The WOMS bit in SCCR1 determines whether TXD is an open drain wired OR output or a normal CMOS output An external pull up resistor on TXD is necessary for wired OR opera tion WOMS controls TXD function whether the pin is used by the SCI or as a general purpose pin Data to be transmitted is written to SCDR then transferred to the serial shifter The transmit data register empty TDRE flag in SCSR shows the status of TDR When TDRE 0 the TDR contains data that
571. tch occurs Refer to 11 4 2 GPT Interrupts for more information Operation of output compare 1 differs from that of the other output compare functions OC1 control logic can be programmed to make state changes on other OC pins when an OC1 match occurs Control bits in the timer compare force register CFORC allow for early forced compares M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL 11 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 11 8 3 1 Output Compare 1 Output compare 1 can affect any or all of OC 5 1 when an output match occurs In addition to allowing generation of multiple control signals from a single comparison op eration this function makes it possible for two or more output compare functions to control the state of a single OC pin Output pulses as short as one timer count can be generated in this way The OC1 action mask register OC 1M and the OC1 action data register OC1D con trol OC1 function Setting a bit in OC1M selects a corresponding bit in the GPT parallel data port Bits in OC 1D determine whether selected bits are to be set or cleared when an OC1 match occurs Pins must be configured as outputs in order for the data in the register to be driven out on the corresponding pin If an 1 match and another output match occur at the same time and both attempt to alter the same pin the OC1 function controls the state of the pin 11 8 3 2 Forced Output
572. te word and long word transfers Port width is the maximum number of bits accepted or provided by the external memory system during a bus transfer Widths of eight and sixteen bits are ac cessed through the use of asynchronous cycles controlled by the size SIZ1 5140 and data size acknowledge DSACK1 and pins Multiple bus cycles may be required for dynamically sized transfers To add flexibility and minimize the necessity for external logic MCU chip select logic is synchronized with EBI transfers Refer to 5 9 Chip Selects for more information 5 5 1 Bus Control Signals The address bus provides addressing information to external devices The data bus transfers 8 bit and 16 bit data between the MCU and external devices Strobe signals one for the address bus and another for the data bus indicate the validity of an ad dress and provide timing information for data Control signals indicate the beginning of each bus cycle the address space the size of the transfer and the type of cycle External devices decode these signals and re spond to transfer data and terminate the bus cycle The can operate an asyn chronous mode for any port width 5 5 1 1 Address Bus Bus signals ADDR 19 0 define the address of the byte or the most significant byte to be transferred during a bus cycle The MCU places the address on the bus at the beginning of a bus cycle The address is valid while AS is asserted 5 5 1 2
573. te generator SCK is dis abled and assumes its inactive state value No serial transfers occur At reset the SCK baud rate is initialized to one eighth of the system clock frequency SPBR has 254 ac tive values Table D 36 lists several possible baud values and the corresponding SCK frequency based on a 16 78 MHz system clock Table D 36 Examples of SCK Frequencies Required Actual SCK fsys Division Ratio Value of SPBR Frequency 16 78 MHz 4 2 4 19 MHz 8 4 2 10 MHz 16 8 1 05 MHz 34 17 493 kHz 168 84 100 kHz 510 255 33 kHz 0 6 11 QSPI Control Register 1 SPCR1 QSPI Control Register 1 YFFC1A 15 14 13 12 10 9 8 1 6 5 4 3 2 1 0 SPE DSCKL 6 0 DTL 7 0 RESET 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 SPCR1 enables the QSPI and specifies transfer delays SPCR1 must be written last during initialization because it contains SPE Writing a new value to SPCR1 while the QSPI is enabled disrupts operation SPE QSPI Enable 0 QSPI is disabled QSPI pins can be used for general purpose I O 1 QSPI is enabled Pins allocated by PQSPAR are controlled by the QSPI REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com D 48 Freescale Semiconductor Inc DSCKL 6 0 Delay before SCK When the DSCK bit is set a command RAM byte this field determines the length of the delay from PCS valid to SCK transition PCS can be any of the four peri
574. ted by the halt monitor enable HME bit in SYPCR Refer to 5 6 5 2 Double Bus Faults for more information 5 4 4 Spurious Interrupt Monitor During interrupt exception processing the CPU16 normally acknowledges an interrupt request arbitrates among various sources of interrupt recognizes the highest priority source and then acquires a vector or responds to a request for autovectoring The spurious interrupt monitor asserts the internal bus error signal BERR if no interrupt arbitration occurs during interrupt exception processing The assertion of BERR caus es the CPU16 to load the spurious interrupt exception vector into the program counter The spurious interrupt monitor cannot be disabled Refer to 5 8 Interrupts for further information For detailed information about interrupt exception processing refer to 4 13 Exceptions 5 4 5 Software Watchdog The software watchdog is controlled by the software watchdog enable SWE bit in SYPCR When enabled the watchdog requires that a service sequence be written to the software watchdog service register SWSR on a periodic basis If servicing does not take place the watchdog times out and asserts the RESET signal Each time the service sequence is written the software watchdog timer restarts The sequence to restart the software watchdog consists of the following steps Write 55 to SWSR Write AA to SWSR M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For Mor
575. ted to the TXD pin while the transmitter is operating TE 1 or TE 0 and transmission in progress Wired OR operation should be specified when more than one transmitter is used on the same SCI bus The WOMS bit in SCCR1 determines whether TXD is an open drain wired OR output or a normal CMOS output An external pull up resistor on TXD is necessary for wired OR opera tion WOMS controls TXD function whether the pin is used by the SCI or as a general purpose pin Data to be transmitted is written to SCDR then transferred to the serial shifter The transmit data register empty TDRE flag in SCSR shows the status of TDR When TDRE 0 contains data that has not been transferred to the shifter Writing to SCDR again overwrites the data TDRE is set when the data in TDR is transferred to the shifter Before new data can be written to SCDR however the processor must clear TDRE by writing to SCSR If new data is written to SCDR without first clearing TDRE the data will not be transmitted The transmission complete TC flag in SCSR shows transmitter shifter state When TC 0 the shifter is busy TC is set when all shifting operations are completed TC is not automatically cleared The processor must clear it by first reading SCSR while TC is set then writing new data to SCDR The state of the serial shifter is checked when the TE bit is set If TC 1 an idle frame is transmitted as a preamble to the following data frame If TC
576. ternal clock maximum fsys IppsvN 7 mA LPSTOP crystal reference VCO off STSIM 0 150 Vpp powered down 100 MC68HC16Z2 Z3 Supply Current t 13 VCO on crystal reference maximum fsys 2 5 14 External clock maximum fsys IppsvN 8 75 mA LPSTOP crystal reference VCO off STSIM 0 2 mA Vpp powered down 2 mA RAM Standby Voltage 15 Specified Vpp applied Vsp 0 0 5 25 V Vpp Vss 3 0 5 25 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 14 25 17 MHz DC Characteristics Continued Vip ANd Vsus 5 0 5 Veg 0 T T to T Characteristic MC68HC16Z1 RAM Standby Current Normal RAM operation Vpp gt 0 5 V Transient condition Vsg 0 5 V gt Vpp2 Vss 0 5 V Standby operation lt Vss 0 5 V MC68HC16Z2 Z3 RAM Standby Current Normal RAM operation Vpp gt Vgg 0 5 V Transient condition Vgg 0 5 gt Vpp gt Vss 0 5 V Standby operation lt Vss 0 5 V 17 MC68HC16Z1 Power Dissipation Pp 777 mW 17A 68 1622 23 Power Dissipation Pp 787 mW Input Capacitance 13 Ex m 18 All input only pins except ADC pins E 20 pF All input output pins Load Capacitance Group 1 I O Pins CLKOUT FREEZE QUOT IPIPEO 90 19 Group 2 I O Pins and CSBOOT BG CS
577. ternal devices that need to obtain the bus must assert bus arbi tration signals in the sequences described in the following paragraphs Systems that include several devices that can become bus master require external cir cuitry to assign priorities to the devices so that when two or more external devices at tempt to become bus master at the same time the one having the highest priority becomes bus master first The protocol sequence is 1 An external device asserts the bus request signal BR 2 The MCU asserts the bus grant signal BG to indicate that the bus is available 3 An external device asserts the bus grant acknowledge BGACK signal to indi cate that it has assumed bus mastership BR can be asserted during a bus cycle or between cycles BG is asserted in response to BR To guarantee operand coherency BG is only asserted at the end of operand transfer If more than one external device can be bus master required external arbitration must begin when a requesting device receives BG An external device must assert BGACK when it assumes mastership and must maintain BGACK assertion as long as it is bus master Two conditions must be met for an external device to assume bus mastership The de vice must receive BG through the arbitration process and BGACK must be inactive indicating that no other bus master is active This technique allows the processing of bus requests during data transfer cycles BG is negated
578. ters SCCRO SCCH1 one sta tus register SCSR and one data register SCDR Refer to D 6 Queued Serial Mod ule for register bit and field definitions 9 4 1 1 Control Registers SCCRO contains the baud rate selection field Baud rate must be set before the SCI is enabled This register can be read or written SCCHR 1 contains a number of SCI configuration parameters including transmitter and receiver enable bits interrupt enable bits and operating mode enable bits This regis ter can be read or written at any time The SCI can modify the RWU bit under certain circumstances Changing the value of SCI control bits during a transfer may disrupt operation Before changing register values allow the SCI to complete the current transfer then disable the receiver and transmitter 9 4 1 2 Status Register SCSR contains flags that show SCI operating conditions These flags are cleared ei ther by SCI hardware or by reading SCSR then reading or writing SCDR A long word read can consecutively access both SCSR and SCDR This action clears receiver sta tus flag bits that were set at the time of the read but does not clear TDRE or TC flags If an internal SCI signal for setting a status bit comes after reading the asserted status bits but before reading or writing SCDR the newly set status bit is not cleared SCSR must be read again with the bit set and SCDR must be read or written before the sta tus bit is cleared Reading eithe
579. test only D 2 3 Clock Synthesizer Control Register SYNCR Clock Synthesizer Control Register YFFA04 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 W X 5 0 EDIV 0 0 RSVD 510 rsvp STSIM STEXT RESET 0 0 1 1 1 1 1 1 0 0 0 0 U 0 0 0 NOTES 1 Ensure that the software does not change the value of these bits They should always be zero This register determines system clock operating frequency and operation during low power stop mode With a slow reference frequency between 25 and 50 kHz typically a 32 768 kHz crystal the clock frequency is determined by the following equation f 1 2 5 1 sys fret With a fast reference frequency between 1 and 6 MHz typically a 4 194 MHz crystal the reference frequency is divided by 128 before it is passed to the PLL system The clock frequency is determined by the following equation f f teh A CY oe Sys 128 21 M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 7 Go to www freescale com Freescale Semiconductor Inc W Frequency Control VCO This bit controls a prescaler tap in the synthesizer feedback loop Setting this bit in creases the VCO speed by a factor of four VCO relock delay is required X Frequency Control Prescaler This bit controls a divide by two prescaler that is not in the synthesizer feedback loop Setting the bit doubles clock speed without changing the VCO speed No VCO relock del
580. th disabled 1 Feedback path enabled LOOPQ controls feedback on the data serializer for testing REGISTER SUMMARY M68HC16 Z SERIES 0 50 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc HALTA and MODF Interrupt Enable 0 HALTA and interrupts disabled 1 HALTA and MODF interrupts enabled HMIE enables interrupt requests generated by the HALTA status flag or the MODF status flag in SPSR HALT Halt QSPI 0 operates normally 1 QSPI is halted for subsequent restart When HALT is set the QSPI stops on a queue boundary It remains in a defined state from which it can later be restarted SPIF QSPI Finished Flag 0 QSPl is not finished 1 QSPI is finished SPIF is set after execution of the command at the address in ENDQP 3 0 MODF Mode Fault Flag 0 Normal operation 1 Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode The QSPI asserts when the QSPI is in master mode MSTR 1 and the SS input pin is negated by an external driver HALTA Halt Acknowledge Flag 0 QSPI is not halted 1 is halted HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit Bit 4 Not Implemented CPTQP 3 0 Completed Queue Pointer 3 0 points to the last command executed It is updated when the current com mand is complete W
581. the IDLE flag in SCSR is set For short idle line detection the receiver bit processor counts contiguous logic one bit times whenever they occur Short detection provides the earliest possible recognition of an idle line condition because the stop bit and contiguous logic ones before and after it are counted For long idle line detection the receiver counts logic ones after the stop bit is received Only a complete idle frame causes the IDLE flag to be set In some applications software overhead can cause a bit time of logic level one to oc cur between frames This bit time does not affect content but if it occurs after a frame of ones when short detection is enabled the receiver flags an idle line When the bit in SCCR1 is set an interrupt request is generated when the IDLE flag is set The flag is cleared by reading SCSR and SCDR in sequence IDLE is not set again until after at least one frame has been received RDRF 1 This prevents an extended idle interval from causing more than one interrupt 9 4 3 8 Receiver Wake Up The receiver wake up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message Hardware activates each receiver in a system under certain conditions Resident software must process address information and enable or disable receiver operation M68HC16 Z SERIES QUEUED SERIAL MODULE USER S MANUAL For
582. the TC bit continue to wait until finish sending out byte transfer complete TC is set Software Watchdog just caused a reset 0a 0d 00 last reset was not caused by the COP 0a 0d 00 CMPB 520 NO DOG LDX dDOG STRING BRA PRINT NO DOG LDX fNO DOG STR PRINT JSR SEND STRING ANDP SFFLE The Main Program MAIN NOP BRA MAIN ASKER Subroutunes VERKA SEND_STRING string LDAB 0 STRING_DONE JSR SEND_CH 501 SEND_STRING STRING_DONE RTS SEND_CH LDAA SCSR ANDA 501 SEND_CH again LDAA 500 STD SCDR TC LOOP LDAB SCSR t1 ANDB 580 TC_LOOP RTS STRINGS DOG_STRING DC NO_DOG_STR DC AUTOV_STRING DC Periodic VECRT SECONDS E 20 Feeding the dog 0a 0d 00 Interrupt Vector Routine INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product KKKKK When the processor is interrupted by the periodic timer it will run this routine This routine simply increments a clock every time it is interrupted and prints the clock out on the dummy terminal advance the counter for seconds M68HC16 Z SERIES USER S MANUAL Go to www freescale com DAA MINUT GI pn HD HOURS CLR LDAA ADDA DAA STD CMPA BNE CLR RETURN JSR RTI KKKKK DISPLAY SEND_HR LDAB JSR SEND_COL LDAB JSR
583. the transfer The clock phase and polarity should be the same for the master and slave devices In some cases the phase and polarity may be changed between transfers to allow a master device to communicate with slave devices with different requirements The flexibility of the SPI system allows it to be directly interfaced to almost any existing synchronous serial peripheral MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 10 3 4 1 CPHA 0 Transfer Format Figure 10 3 is a timing diagram of an 8 bit MSB first SPI transfer in which CPHA equals zero Two waveforms are shown for SCK one for CPOL equal to zero and an other for CPOL equal to one The diagram may be interpreted as a master or slave timing diagram since the SCK MISO and MOSI pins are directly connected between the master and the slave The MISO signal shown is the output from the slave and the MOSI signal shown is the output from the master The SS line is the chip select input to the slave SCK CYCLE roe 2 2 3 5 s b s ALU MOSI FROM MASTER MISO FROM SLAVE SS TO SLAVE CPHA 0 SPI TRANSFER Figure 10 3 CPHA 0 SPI Transfer Format For a master writing to the SPDR initiates the transfer For a slave the falling edge of SS indicates the start of a transfer
584. ther EV or MV is set data read from AM using TMER or TMET is given maximum positive or negative value depending on the state of the AM sign bit before overflow PK 3 0 Program Counter Address Extension Field This field is concatenated with the program counter to form a 20 bit address M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 3 Go to www freescale com Freescale Semiconductor Inc D 2 System Integration Module Table D 2 shows the SIM address map Table D 2 SIM Address Map Address 15 8 7 0 YFFAOO SIM Module Configuration Register SIMCR YFFAO2 SIM Test Register SIMTR YFFA04 Clock Synthesizer Control Register SYNCR YFFAO6 Not Used Reset Status Register RSR YFFA08 SIM Test Register E SIMTRE YFFAOA Not Used Not Used YFFAOC Not Used Not Used YFFAOE Not Used Not Used YFFA10 Not Used Port E Data Register 0 PORTEO YFFA12 Not Used Port E Data Register 1 PORTE1 YFFA14 Not Used Port E Data Direction Register DDRE YFFA16 Not Used Port E Pin Assignment Register PEPAR YFFA18 Not Used Port F Data Register 0 PORTFO YFFA1A Not Used Port F Data Register 1 PORTF1 YFFA1C Not Used Port F Data Direction Register DDRF YFFA1E Not Used Port F Pin Assignment Register PFPAR YFFA20 Not Used System Protection Control Register SYPCR YFFA22 Periodic Interrupt Control Register PICR YFFA24 Periodic Interrupt Timer Register PITR YFFA26 Not Used Soft
585. tion and I O function Table 0 34 shows the effect of DDRQS on QSM pin function M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 45 Go to www freescale com Freescale Semiconductor Inc Table D 34 Effect of DDRQS on QSM Pin Function QSM Pin Mode DDRQS Bit Bit State Pin Function MISO Master DDQSO 0 Serial data input to QSPI 1 Disables data input Slave 0 Disables data output 1 Serial data output from QSPI MOSI Master DDQS1 0 Disables data output 1 Serial data output from QSPI Slave 0 Serial data input to QSPI 1 Disables data input SCK Master DDQS2 Clock output from QSPI Slave Clock input to QSPI 50 55 Master DDQS3 0 Assertion causes mode fault 1 Chip select output Slave 0 QSPI slave select input 1 Disables slave select Input PCS 1 3 Master DDQS 4 6 0 Disables chip select output 1 Chip select outputs enabled Slave 0 No effect 1 No effect TXD2 DDQS7 X Serial data output from SCI RXD None NA Serial data input to SCI NOTES 1 PQS2 is a digital I O pin unless the SPI is enabled SPE set SPCR1 in which case it becomes the QSPI serial clock SCK 2 PQS7 is a digital I O pin unless the SCI transmitter is enabled TE set SCCR1 in which case it becomes the SCI serial data output TXD DDQS7 determines the direction of PQS7 only when the SCI transmitter is disabled When the SCI transmitter is enabled
586. tion pro cessing Refer to Figure 5 15 for a flowchart of the breakpoint operation Refer to the SIM Reference Manual SIMRM AD for further information M68HC16 Z SERIES SYSTEM INTEGRATION MODULE USER S MANUAL For More Information On This Product 5 41 Go to www freescale com Freescale Semiconductor Inc BREAKPOINT OPERATION FLOW CPU16 PERIPHERAL ACKNOWLEDGE BREAKPOINT 1 SET R W TO READ 2 SET FUNCTION CODE TO CPU SPACE 3 PLACE CPU SPACE TYPE 0 ON ADDR 19 16 4 PLACE ALL ONES ON ADDR 4 2 5 SET ADDR1TO ONE 6 SET SIZE TO WORD 7 ASSERT AS AND DS ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING NEGATE AS or DS NEGATE DSACK or BERR INITIATE HARDWARE BREAKPOINT PROCESSING Figure 5 15 Breakpoint Operation Flowchart CPU16 BREAKPOINT OPERATION FLOW 5 6 4 2 LPSTOP Broadcast Cycle Low power stop mode is initiated by the CPU16 Individual modules can be stopped by setting the STOP bits in each module configuration register The SIM can turn off system clocks after execution of the LPSTOP instruction When the CPU16 executes LPSTOP the LPSTOP broadcast cycle is generated The SIM brings the MCU out of low power mode when either an interrupt of higher priority than the interrupt mask lev el in the CPU16 condition code register or a reset occurs Refer to 5 3 4 Low Power Operation and SECTION 4 CENTRAL PROCESSOR UNIT for more information During an LPSTOP broadcast cycle the CP
587. tly Table 4 4 shows the M68HC11 CPU instructions that either have been replaced by CPU16 instructions or that operate differently on the CPU16 Replacement instruc tions are not identical to M68HC11 CPU instructions M68HC1 1 code must be altered to establish proper preconditions All CPU16 instruction execution times differ from those of the M68HC11 Transporting M68HC11 Code to M68HC16 Devices M68HC16PN01 D contains detailed infor mation about differences between the two instruction sets Refer to the CPU16 Refer ence Manual CPU16RM AD for further details about CPU operations M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL For More Information On This Product 4 31 Go to www freescale com 4 32 Freescale Semiconductor Inc Table 4 4 CPU16 Implementation of M68HC11 CPU Instructions M68HC11 Instruction CPU16 Implementation BCC only BCS only Generates a different stack frame Replaced by ANDP Replaced by ANDP Replaced by ANDP Replaced by Replaced by AIX IND8 and EXT addressing modes replaced by IND20 and EXT20 modes IND8 and EXT addressing modes replaced by IND20 and EXT20 modes Generates a different stack frame LSL LSLD Use ASL instructions PSHX Replaced by PSHM PSHY Replaced by PSHM PULX Replaced by PULM PULY Replaced by PULM R Reloads PC and CCR only R Uses two word stack frame 5 Replaced by ORP 5 Replaced by ORP 5 Replaced by ORP STOP Replaced by LPSTOP T
588. to 2 AM 31 16 NH 27 1 4 0 0 AM 31 0 D 2 AM 15 0 Sign Extend AM AM 35 32 AM31 TEKB Transfer EK to B EK 2 B 3 0 27BB 2 0 B 7 4 TEM Transfer E to E AM 31 16 27B2 4 0 0 AM 31 16 00 AM 15 0 Sign Extend 35 32 AM31 Clear AM LSB TMER Transfer Rounded AM Rounded AM Temp 27B4 6 A to E If SM EV MV then Saturation Value gt E else Temp 31 16 2 E M68HC16 Z SERIES CENTRAL PROCESSING UNIT USER S MANUAL 4 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand MV H EV N Z V C TMET Transfer Truncated If SM EV MV 27B5 m to E then Saturation Value gt E else AM 31 16 E TMXED Transfer AM to AM 35 32 IX 3 0 27B3 IX E D 5 1 15 4 AM 31 16 AM 15 0 2 TPA Transfer CCR to A CCR 15 8 2 Sue 2 TPD Transfer CCR to D CCR D 372C TSKB Transfer SK to B SK 3 0 NH 0 7 4 TST Test Byte 00 IND8 6 0 0 Zero or Minus IND8 Y 6 IND8 Z 6 IND16 X 6 IND16 Y 6 IND16 Z 6 EXT 6 TSTA Test A for 2 0
589. to Negating Edge of AS CS Fast Write Cycle tpyasn 10 ns 25 DS CS Negated to Data Out Invalid Data Out Hold tsNDOI 10 ns 26 Data Out Valid to DS CS Asserted Write tovsa 10 ns 27 Data In Valid to Clock Low Data Setup tpicL 5 ns 27A Late BERR HALT Asserted to Clock Low Setup Time 15 ns 29 05 CS Negated to Data In Invalid Data In Hold tsNDI 0 ns 29A 55 CS Negated to Data In High Impedance 8 tsHDI 48 ns M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product A 23 Go to www freescale com Freescale Semiconductor Inc Table A 17 20 97 MHz AC Timing Continued Vg and VopsyN 5 0 5 Ves 0 Vdc T to Characteristic Symbol Min Max Unit 30 CLKOUT Low to Data In Invalid Fast Cycle Hold ns 30A CLKOUT Low to Data In High Impedance 72 ns 31 0 Asserted to Data In Valid 46 ns uw 37 BGACK Asserted to BG Negated 1 2 39 BG Width Negated 46 R W Width Asserted Write or Read 115 5 46 Width Asserted Fast Write or Read Cycle trwas 70 E ns A7A Asynchronous Input Setup Time ng BR BGACK DSACK 1 0 BERR AVEC HALT 47B Input Hold Time ns 48 DSACK 1 0 Asserted to BERR HALT Asserted 30 ns 53 Data Out Hold from Clock High ns 54
590. to Phase 2 Negated teNP2N ns NOTES 1 Refer to notes in Table A 18 A 20 ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 16 16 78 MHz AC Timing aNd Vingyy 5 0 10 Ve 0 T T to Num Characteristic Symbol Min Max Unit 1 Frequency of Operation f 16 78 MHz 1 Clock Period 59 6 m ns 1A Period 476 ns 1B External Clock Input Period txcyc 59 6 ns 2 3 Clock Pulse Width tew 24 ns 2A 3A ECLK Pulse Width tecw 236 mE ns 2B 3B External Clock Input High Low Time txcHL 29 8 ns 4 5 CLKOUT Rise and Fall Time ns 4A 5A Rise and Fall Time All Outputs except CLKOUT 8 ns 4B 5B External Clock Input Rise and Fall Time txcrt 5 ns 6 Clock High to ADDR FC SIZE 0 29 ns 7 Clock High to ADDR Data FC SIZE High Impedance 7 0 59 ns 8 Clock High to ADDR FC SIZE Invalid tenaz 0 ns 9 Clock Low to AS DS CS Asserted tcLsa 2 24 ns 9A AS to DS or CS Asserted Read tstsa 15 15 ns 11 ADDR FC SIZE Valid to AS CS and DS Read Asserted tavsa 15 ns 12 Clock Low to AS DS CS Negated 2 29 ns 13 AS DS CS Negated to ADDR FC SIZE Invalid Address Hold 15 ns 14 AS CS and DS Read Width
591. tor M overflow flag MV is set when an overflow into AM35 has occurred H Half Carry Flag H is set when a carry from A3 or B3 occurs during BCD addition EV Accumulator M Extension Overflow Flag EV is set when an overflow into 1 has occurred N Negative Flag N is set under the following conditions When the MSB is set in the operand of a read operation When the MSB is set in the result of a logic or arithmetic operation Z Zero Flag Z is set under the following conditions When all bits are zero in the operand of a read operation When all bits are zero in the result of a logic or arithmetic operation V Overflow Flag V is set when a two s complement overflow occurs as the result of an operation C Carry Flag C is set when a carry or borrow occurs during an arithmetic operation This flag is also used during shift and rotate to facilitate multiple word operations IP 2 0 Interrupt Priority Field The priority value in this field 0 to 7 is used to mask interrupts CENTRAL PROCESSOR UNIT M68HC16 Z SERIES T4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SM Saturate Mode Bit When SM is set and either EV or MV is set data read from AM using TMER or is given maximum positive or negative value depending on the state of the AM sign bit before overflow PK 3 0 Program Counter Address Extension Field This fiel
592. tored in a separate result reg ister RSLTO to RSLT3 Previous results are overwritten when a sequence repeats The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the first four conversion sequence is complete Mode 5 Continuous eight conversion sequences are performed on a single input channel specified by the value in CD CA Each result is stored in a separate result reg ister RSLTO to RSLT7 Previous results are overwritten when a sequence repeats The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the first eight conversion sequence is complete Mode 6 Continuous conversions are performed on each of four sequential input channels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the first four conversion sequence is complete Mode 7 Continuous conversions are performed on each of eight sequential input channels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADCSTAT is set as each register is filled The SCF bit in ADCSTAT is set when the first eight Conversion sequence is complete Table 8 7 is a summary of ADC operation when MULT is
593. ts 3 8 Bit Integral Nonlinearity INL 1 0 1 0 Counts 4 8 Bit Absolute Error AE 1 5 Counts 5 10 Resolution 1 Count lt lt d 841 mV 6 10 Bit Differential Nonlinearity DNL 1 1 Counts 7 10 Bit Integral Nonlinearity INL 2 0 2 0 Counts 8 10 Bit Absolute Error AE Counts 9 Source Impedance at Input Rs 20 kQ NOTES A 66 1 At Vay Vn 3 072 V one 10 bit count 3 mV and one 8 bit count 12 mV 2 8 bit absolute error of 1 5 counts 18 mV includes 1 2 count 6 mV inherent quantization error and 1 count 12 mV circuit differential integral and offset error 3 Conversion accuracy varies with fApc rate Reduced conversion accuracy occurs at maximum Assumes that minimum sample time 2 ADC clocks is selected 4 10 bit absolute error of 4 0 counts 12 mV includes 1 2 count 1 5 mV inherent quantization error and 3 5 counts 10 5 mV circuit differential integral and offset error 5 Maximum source impedance is application dependent Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge sharing with internal capacitance Error from junction leakage is a function of external source impedance and input leakage current Expected error in result value due to junction leakage is expressed in voltage Verns Venn loff where is a function of operating temperature as shown in Table A 35 Charge sharing
594. uct Go to www freescale com Freescale Semiconductor Inc Refer to D 8 General Purpose Timer for a GPT address map and register bit field de scriptions Refer to 5 2 1 Module Mapping for more information about how the state of MM affects the system 11 3 Special Modes of Operation The GPT module configuration register GPTMCR is used to control special GPT op erating modes These include low power stop mode freeze mode single step mode and test mode Normal GPT operation can be polled or interrupt driven Refer to 11 4 Polled and Interrupt Driven Operation for more information 11 3 1 Low Power Stop Mode Low power stop operation is initiated by setting the STOP bit in GPTMCR In stop mode the system clock to the module is turned off The clock remains off until STOP is negated or a reset occurs All counters and prescalers within the timer stop counting while the STOP bit is set Only the module configuration register GPTMCR and the interrupt configuration register ICR should be accessed while in the stop mode Ac cesses to other GPT registers cause unpredictable behavior Low power stop can also be used to disable module operation during debugging 11 3 2 Freeze Mode The freeze FRZ 1 0 bits in GPTMCR are used to determine what action is taken by the GPT when the IMB FREEZE signal is asserted FREEZE is asserted when the CPU enters background debug mode At the present time FRZ1 is not implemented FRZO causes the GPT to
595. ued Mnemonic Operation EDIVS Extended Signed Integer Divide EMUL Extended Unsigned Multiply Extended Signed Multiply EMULS Description E D IX Quotient Remainder gt D D E D Address Instruction Condition Codes Mode INH Opcode Operand 5 2 SS Ae gt gt IND8 IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT X EY E Z EORB Exclusive OR B IND8 X IND8 Y IND8 Z IMM8 IND16 X IND16 Y IND16 Z EXT Y 2 A 0 EORD Exclusive OR D IND8 X IND8 Y IND8 Z IMM16 IND16 X IND16 Y IND16 Z EXT Y 2 A 0 EORE Exclusive OR E FDIV Fractional Unsigned Divide D IX 2 IX Remainder gt D IMM16 IND16 X IND16 Y IND16 Z EXT FMULS Fractional Signed Multiply IDIV Integer Divide D 2 E 0 31 1 0 DI0 D IX 2 IX Remainder gt D NH INC Increment Memory 01 5 08 X IND8 Y IND8 2 IND16 X IND16 Y IND16 Z EXT INCA Increment A A 01 gt A INH INCB INCW Increment B Increment Memory Word 01 gt B 1 0001 gt 1 IND16 IND16 IND16 Z EXT 2703 2713 2723 2733 j M N
596. ult Register YFF720 YFF72F 15 14 13 12 11 10 9 8 7 6 5 0 Conversion result is signed left justified data Bits 15 6 are used for 10 bit resolution For 8 bit conversions bits 15 8 contain data and bits 7 6 are zero Although the ADC is unipolar itis assumed that the zero point is halfway between low and high reference when this format is used Vay 2 For positive input bit 15 0 For negative in put bit 15 1 Bits 5 0 always return zero when read REGISTER SUMMARY M68HC16 Z SERIES D 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 5 9 Left Justified Unsigned Result Register LJURR Left Justified Unsigned Result Register YFF730 YFF73F 15 14 13 12 1 10 9 8 1 6 5 0 810 eno eno eno eno eno eno eno 10 10 NOT USED Conversion result is unsigned left justified data Bits 15 6 are used for 10 bit resolu tion For 8 bit conversions bits 15 8 contain data and bits 7 6 are zero Bits 5 0 al ways return zero when read M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 37 Go to www freescale com Freescale Semiconductor Inc D 6 Queued Serial Module Table D 31 QSM Address Map Address 15 8 7 0 YFFCOO QSM Module Configuration Register QSMCR YFFCO2 QSM Test Register QTEST YFFC04 QSM Interrupt Level Register QILR QSM Inter
597. um fsys 2 14 External clock maximum IppsvN 6 LPSTOP crystal reference VCO off STSIM 0 150 Vpp powered down 100 MC68HC16Z2 Z3 Vppsyn Supply Current 13 VCO on crystal reference maximum fsys 2 5 mA 14A External clock maximum fsys IppsvN 8 75 mA LPSTOP crystal reference VCO off STSIM 0 2 mA Vpp powered down 2 mA RAM Standby Voltage 15 Specified Vpp applied Vsp 0 0 5 25 V Vpp Vss 3 0 5 25 ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A 14 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 13 20 97 MHz DC Characteristics Vip ANd Vppsyy 5 0 5 Veg 0 T T to T Characteristic MC68HC16Z1 RAM Standby Current Normal RAM operation gt Vgg 0 5 V Transient condition Vsp 0 5 gt Vpp 2 Vss 0 5 V Standby operation lt Vss 0 5 V MC68HC16Z2 Z3 RAM Standby Current Normal RAM operation Vpp gt Vgg 0 5 V Transient condition 0 5 V 2 Vpp2 Vss 0 5 V Standby operation lt Vss 0 5 V 17 MC68HC16Z1 Power Dissipation Pp 772 mW 17A MC68HC1622 Z3 Power Dissipation Pp 787 mW Input Capacitance 13 u 10 18 All input only pins except ADC pins Cin pF 20 All input output pins Load Capacitance Group 1 I O Pins CLKOUT FREEZE QUOT IPIPEO 90 19 Group 2 I O Pins and CSBOOT BG CS C
598. ump table in bank 0 4 13 4 Types of Exceptions Exceptions can be either internally or externally generated External exceptions which are defined as asynchronous include interrupts bus errors breakpoints and resets Internal exceptions which are defined as synchronous include the software interrupt SWI instruction the background BGND instruction illegal instruction exceptions and the divide by zero exception 4 13 4 1 Asynchronous Exceptions Asynchronous exceptions occur without reference to CPU16 or IMB clocks but excep tion processing is synchronized For all asynchronous exceptions except RESET ex ception processing begins at the first instruction boundary following recognition of an exception Refer to 5 8 1 Interrupt Exception Processing for more information con cerning asynchronous exceptions Because of pipelining the stacked return PK PC value for all asynchronous excep tions other than reset is equal to the address of the next instruction in the current in struction stream plus 0006 The RTI instruction which must terminate all exception handler routines subtracts 0006 from the stacked value to resume execution of the interrupted instruction stream 4 13 4 2 Synchronous Exceptions Synchronous exception processing is part of an instruction definition Exception pro cessing for synchronous exceptions is always completed and the first instruction of the handler routine is always executed before interru
599. unless driven exter nally MM corresponds to IMB ADDR23 If it is cleared the SIM maps IMB modules into address space 7FF000 7FFFFF which is inaccessible to the CPU16 Mod ules remain inaccessible until reset occurs The reset state of MM is one but the bit is can be written once Initialization software should make certain it remains set D 1 Central Processing Unit CPU16 registers are not part of the module address map Figure D 1 is a functional representation of CPU resources M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 1 Go to www freescale com Freescale Semiconductor Inc BIT POSITION ACCUMU ACCUMU LATORS A AND B LATOR D A B ACCUMULATOR E DEX REG DEX REG DEX REG STER X STER Y STERZ K SK HR IR A A XMSK YMSK STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK ADDRESS EXTENSION REGISTER K STACK EXTENSION FIELD SK AC MULTIPLIER REGISTER HR AC MULTIPLICAND REGISTER IR AC ACCUMULATOR MSB 35 16 AM AC ACCUMULATOR LSB 15 0 AM AC XY MASK REGISTER CPU16 REGISTER MODEL Figure D 1 CPU16 Register Model REGISTER SUMMARY For More Information On This Product M68HC16 Z SERIES USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 1 1 Condition Code Register CCR
600. up 1 Port GP 7 0 IC4 OC5 OC1 IC 3 1 OC 4 1 OC1 DATA 15 0 DSI IPIPE1 Group 2 Port C 6 0 ADDR 22 19 CS 9 6 FC 2 0 CS 5 3 Port E 7 0 SIZ 1 0 AS DS AVEC DSACK 1 0 Port F 7 0 IRQ 7 1 MODCLK Port MCCI 7 3 TXD PCS 3 1 50 55 ADDR23 CS10 ECLK Group 3 HALT RESET Group 4 MISO MOSI SCK 3 Does not apply to HALT and RESET because they are open drain pins Does not apply to port MCCI 7 0 TXD PCS 3 1 50 55 SCK MOSI MISO in wired OR mode 4 Use of an active pulldown device is recommended 5 Total operating current is the sum of the appropriate Ipp Ippsyn Isp and Ippa 6 Current measured with system clock frequency of 16 78 MHz all modules active 7 This parameter is periodically sampled rather than 100 tested 8 CPU16 in WAIT all other modules inactive 9 The RAM module will not switch into standby mode as long as Vgp does not exceed Vpp by more than 0 5 Volt The RAM array cannot be accessed while the module is in standby mode 10 When Vpp is transitioning during a power up or power down sequence and is applied current flows between the Vstpy and Vpp pins which causes standby current to increase toward the maximum transient condition spec ification System noise on the Vpp and Vsrpy pins can contribute to this condition 11 Power dissipation measured at specified system clock frequency all modules active Power dissipation can be calculated using the expression Pp Max
601. up Time NOTES 1 Refer to notes in Table A 26 A 40 ELECTRICAL CHARACTERISTICS For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table A 24 16 78 MHz ECLK Bus Timing 5 0 Vdc 10 0 T T to T Voo and Vopsyn Characteristic E1 E2 Low to Address ECLK Low to Address Hold ECLK Low to CS Valid CS Delay E4 E5 E6 ECLK Low to CS Hold CS Negated Width Read Data Setup Time E7 E8 E9 Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold Read E10 E11 CS Negated to Data High Impedance ECLK Low to Data Valid Write E12 ECLK Low to Data Hold Write ns E13 CS Negated to Data Hold Write E14 Address Access Time Read E15 Chip Select Access Time Read ns ns ns NOTES E16 Address Setup Time 1 Refer to notes in Table A 26 M68HC16 Z SERIES USER S MANUAL For More Information On This Product ELECTRICAL CHARACTERISTICS Go to www freescale com teyc A 41 Freescale Semiconductor Inc Table A 25 20 97 MHz ECLK Bus Timing Vp and 5 0 Vdc 5 Ves 0 Vdc T to Characteristic Symbol Min Unit E1 ECLK Low to Address Valid ns 2 Low to Address Hold m ns E3 ECLK Low to CS Vali
602. upply Current RUN LPSTOP VCO off LPSTOP External clock maximum fsys Clock Synthesizer Operating Voltage Vppsvw Supply Current VCO on maximum y External Clock maximum fsys LPSTOP VCO off Vpp powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation Table A 4 Typical Ratings 20 97 MHz Operation Rating M Value Unit Ligen 7 fe Vpp Supply Current RUN LPSTOP VCO off LPSTOP External clock maximum fsys Clock Synthesizer Operating Voltage Vppsvw Supply Current VCO on maximum y External Clock maximum fsys LPSTOP VCO off Vpp powered down RAM Standby Voltage RAM Standby Current Normal RAM operation Standby operation Power Dissipation M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 5 Typical Ratings 25 17 MHz Num Rating Symbol Unit 1 Supply Voltage Vpp V 2 Temperature TA Vpp Supply Current mA 3 RUN LPSTOP VCO off DD LPSTOP External clock max fsys 4 Clock Synthesizer Operating Voltage VDDSYN V VppsvN Supply Current VCO on maximum 1 0 mA 5 External Clock maximum fsys lDDSYN 5 0 mA LPSTOP VCO off 100 Vpp powered down 50 6 RAM Standby Voltage RAM Standby Current 7 Normal RAM operation Isp 1
603. upt Mask Registers 1 2 YFF920 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 14 051 OCI 4 1 ICI 3 1 TOI 0 PAOVI CPROUT CPR 2 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER SUMMARY M68HC16 Z SERIES D 72 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 1 enables OC and IC interrupts TMSK2 controls pulse accumulator interrupts and TCNT functions 14 051 Input Capture 4 Output Compare 5 Interrupt Enable 0 IC4 OC5 interrupt disabled 1 1C4 OC5 interrupt requested when 14 O5F flag in TFLG1 is set OCI 4 1 Output Compare Interrupt Enable OCI 4 1 correspond to OC 4 1 0 OC interrupt disabled 1 OC interrupt requested when OC flag set ICI 3 1 Input Capture Interrupt Enable ICI 3 1 correspond to IC 3 1 0 IC interrupt disabled 1 IC interrupt requested when IC flag set TOI Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled 1 Interrupt requested when TOF flag is set PAOVI Pulse Accumulator Overflow Interrupt Enable 0 Pulse accumulator overflow interrupt disabled 1 Interrupt requested when PAOVF flag is set Pulse Accumulator Input Interrupt Enable 0 Pulse accumulator interrupt disabled 1 Interrupt requested when PAIF flag is set CPROUT Capture Compare Unit Clock Output Enable 0 Normal operation for OC1 pin 1 TONT clock driven out pin CPR 2 0 Timer Pres
604. upt enable SPIFIE D 50 SPIF D 51 D 65 SPIFIE D 50 SPSR 10 6 D 50 D 65 SRAM address map D 23 array address mapping 6 2 features 3 1 normal access 6 2 registers array base address register high RAMBAH 6 1 low RAMBAL 6 1 array base address registers high low RAMBAH BAL D 24 module configuration register RAMMCR 6 1 D 23 test register RAMTST 6 1 D 24 reset 6 3 standby and low power stop operation 6 2 SS 9 20 10 8 10 9 10 10 10 12 Standard non return to zero NRZ 9 2 10 2 10 13 Star point ground system 8 17 Start bit beginning of data frame 9 25 10 17 State machine 9 28 10 20 STEXT 5 21 D 8 STOP 6 2 7 3 8 3 9 2 10 2 11 3 D 23 D 25 D 30 D 39 D 55 D 68 enable S 4 4 D 3 Stop mode external clock STEXT 5 21 D 8 SIM clock STSIM 5 21 D 8 prescaler STOPP D 68 SCI end of data frame bit 9 25 10 17 STOPP 11 4 D 68 STRB address strobe data strobe bit 5 40 5 66 D 19 Stress conditions 8 18 STS D 31 STSIM 5 21 D 8 Successive approximation register SAR 8 13 Supervisor unrestricted data space SUPV ADC D 30 GPT D 68 MCCI 10 3 D 55 QSM D 39 SIM 5 3 D 6 SUPV 10 3 D 6 D 30 D 39 D 55 D 68 SW D 8 SWE 5 25 D 12 SWP 5 26 D 12 SWSR D 15 SWT 5 26 D 12 Symbols 2 1 14 For More Information On This Product Synchronous exceptions 4 39 SYNCR 5 5 D 7 Synthesizer lock flag SLOCK D 8 D 12 SYS D 8 System clock 5 4 output CLKOUT 5 36 sources 5 5 frequencies
605. ures this bit remains zero A one in this bit could allow the MCU to enter an unsupported operating mode SIMCR controls system configuration SIMCR can be read or written at any time ex cept for the module mapping MM bit which can only be written once after reset and the reserved bit which is read only Write has no effect EXOFF External Clock Off 0 The CLKOUT pin is driven during normal operation 1 The CLKOUT pin is placed in a high impedance state FRZSW Freeze Software Enable 0 When FREEZE is asserted the software watchdog and periodic interrupt timer continue to operate allowing interrupts during background debug mode 1 When FREEZE is asserted the software watchdog and periodic interrupt timer are disabled preventing interrupts during background debug mode FRZBM Freeze Bus Monitor Enable 0 When FREEZE is asserted the bus monitor continues to operate 1 When FREEZE is asserted the bus monitor is disabled SHEN 1 0 Show Cycle Enable The SHEN field determines how the external bus is driven during internal transfer op erations A show cycle allows internal transfers to be monitored externally Table D 3 indicates whether show cycle data is driven externally and whether exter nal bus arbitration can occur To prevent bus conflict external devices must not be se lected during show cycles Table D 3 Show Cycle Enable Bits SHEN 1 0 Action 00 Show cycles disabled external a
606. urpose 9 3 5 1 Master Mode Setting the MSTR bit in SPCRO selects master mode operation In master mode the QSPI can initiate serial transfers but cannot respond to externally initiated transfers When the slave select input of a device configured for master mode is asserted a mode fault occurs Before QSPI operation begins QSM register PQSPAR must be written to assign the necessary pins to the QSPI The pins necessary for master mode operation are MISO MOSI SCK and one or more of the chip select pins MISO is used for serial data input in master mode and MOSI is used for serial data output Either or both may be nec essary depending on the particular application SCK is the serial clock output in mas ter mode and must be assigned to the QSPI for proper operation The PORTQS data register must next be written with values that make the PQS2 SCK and PQS 6 3 PCS 3 0 outputs inactive when the QSPI completes a series of trans fers Pins allocated to the QSPI by PQSPAR are controlled by PORTQS when the QSPI is inactive PORTQS I O pins driven to states opposite those of the inactive QSPI signals can generate glitches that momentarily enable or partially clock a slave device For example if a slave device operates with an inactive SCK state of logic one CPOL 1 and uses active low peripheral chip select PCSO the PQS 3 2 bits in PORTQS must be set to 11 If PQS 3 2 9600 falling edges will appear on PQS2 SCK and PQS3 PCS0 as
607. ut Pin Subjected to Negative Stress Voltage Limiting Diodes in a Negative Stress Circuit External Multiplexing of Analog Signal Sources Electrical Model of an A D Input Pin QSM Block DAAD srren E QSPI Block Diagram CEP TRAN sotone A Flowchart of QSPI Initialization Operation Flowchart of QSPI Master Operation Part 1 Flowchart of QSPI Master Operation Part 2 Flowchart of QSPI Master Operation Part 3 Flowchart of QSPI Slave Operation Part 1 Flowchart of QSPI Slave Operation Part 2 SCI Transmitter Block Diagram SCI Receiver Block Diagram Lauer aieo rtr MOGI clase MP LE m T SPI Block Diagram 0 SPI Transfer Format 1 SPI Transfer Format SCI Transmitter Block Diagram iuuenes For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued Figure Title Page EE 01 5 0 10 15 RR T T 11 2 Prescaler BIO 11 9 Capture Compare Unit Block Diagram 4 ec net nnde nato 11 11 11 13 Pulse Accumulator B
608. ut compare function The OC1 function can affect the output of all compare pins If the OC1 pin is not needed for an output compare function it can be used to output the clock selected for the timer counter register Any of these pins can also be used for general purpose I O Refer to 11 8 3 Output Com pare Functions for more information 11 5 4 Pulse Accumulator Input Pin The pulse accumulator input PAI pin connects a discrete signal to the pulse accumu lator for timed or gated pulse accumulation PAI has hysteresis Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored It can be used as a general purpose input pin Refer to 11 10 Pulse Accumulator for more information M68HC16 Z SERIES GENERAL PURPOSE TIMER USER S MANUAL For More Information On This Product 11 7 Go to www freescale com Freescale Semiconductor Inc 11 5 5 Pulse Width Modulation Pulse width modulation PWMA B pins carry pulse width modulator outputs The modulators can be programmed to generate a periodic waveform of variable frequen cy and duty cycle PWMA can be used to output the clock selected as the input to the PWM counter These pins can also be used for general purpose output Refer to 11 11 Pulse Width Modulation Unit for more information 11 5 6 Auxiliary Timer Clock Input The auxiliary timer clock input PCLK pin connects an external clock to the GPT The external clock can be used
609. ved RSLT 0 7 1 1 0 1 1 Reserved RSLT 0 7 1 1 1 0 0 RSLT 0 7 1 1 1 0 1 VRL RSLT 0 7 1 1 1 1 0 Vn 2 RSLT 0 7 1 1 1 1 1 Test Reserved RSLT 0 7 D 34 NOTES 1 Result register RSLT is either RJURRX LJSRRX or LJURRX depending on the address read For More Information On This Product REGISTER SUMMARY Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc Table D 30 Multiple Channel Conversions MULT 1 S8CM CD Input Result Register 0 0 0 X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 0 0 1 X X AN4 RSLTO AN5 RSLT1 ANG RSLT2 AN7 RSLT3 0 1 0 X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 0 1 1 X X VRH RSLTO VRL RSLT1 Vn 2 RSLT2 Test Reserved RSLT3 1 0 X X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 AN4 RSLT4 AN5 RSLT5 AN6 RSLT6 AN7 RSLT7 1 1 X X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 RSLT4 VRL RSLT5 2 RSLT6 Test Reserved RSLT7 NOTES 1 Result register RSLT is either RJURRX LJSRRX or LJURRX depending on the address read M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 35 Go to www freescale com Freescale Semiconductor Inc D 5 6 ADC Status Register ADCSTAT ADC Status Register YFF70E 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 SCF NOT USED C
610. vel This field determines the priority of periodic interrupt requests A value of 000 dis ables PIT interrupts M68HC16 Z SERIES REGISTER SUMMARY USER S MANUAL For More Information On This Product D 13 Go to www freescale com Freescale Semiconductor Inc PIV 7 0 Periodic Interrupt Vector This field specifies the periodic interrupt vector number supplied by the SIM when the CPU16 acknowledges an interrupt request D 2 14 Periodic Interrupt Timer Register PITR Periodic Interrupt Timer Register YFFA24 Contains the count value for the periodic timer This register can be read or written at any time PTP Periodic Timer Prescaler 0 Periodic timer clock not prescaled 1 Periodic timer clock prescaled by a value of 512 PITM 7 0 Periodic Interrupt Timing Modulus This field determines the periodic interrupt rate Use the following equations to calcu late timer period The following equation calculates the PIT period when a slow reference frequency is used fref PIT Period The following equation calculates the PIT period when a fast reference frequency is used PIT Period The following equation calculates the PIT period for externally input clock frequen cy on both slow and fast reference frequency devices f sys PIT Period REGISTER SUMMARY M68HC16 Z SERIES D 14 USER S MANUAL For More Information On This Product Go to www freescale com Freescale
611. vel on the RESET pin is clocked into the SIM The RESET input is synchronized to the system clock If there is no clock when RESET is asserted reset does not occur until the clock starts Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted Reset procedures handle system initialization and recovery from catastrophic failure The MCU performs resets with a combination of hardware and software The SIM de termines whether a reset is valid asserts control signals performs basic system con figuration and boot ROM selection based on hardware mode select inputs then passes control to the CPU16 5 7 1 Reset Exception Processing The CPU16 processes resets as a type of asynchronous exception An exception is an event that preempts normal processing and can be caused by internal or external events Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception Each exception has an assigned vector that points to an associated handler routine These vectors are stored in the ex ception vector table The exception vector table consists of 256 four byte vectors and occupies 512 bytes of address space The exception vector table can be relocated in memory by changing its base address in the vector base register VBR The CPU16 uses vector numbers to calculate displacement into the table Refer to 4 13 Excep tions for more information
612. voltage A 63 digital control subsystem 8 6 external connections 8 1 features 3 2 maximum ratings A 62 operating characteristics A 67 low voltage A 66 overview 8 1 prescaler 8 6 programmer s model 8 3 registers control registers ADCTL 8 6 D 31 D 32 left justified signed LUSRR D 36 unsigned LUURR D 37 module configuration register ADCMCR 8 3 D 30 M68HC16 Z SERIES USER S MANUAL port ADA data register PORTADA D 30 result registers 8 13 right justified unsigned RJURR D 36 status register ADCSTAT 8 6 D 36 test register ADCTEST D 30 special operating modes 8 3 ADCMCR 8 1 8 3 D 30 ADCSTAT D 36 ADCTEST D 30 ADCTL D 31 D 32 ADCTST 8 1 ADDD 4 9 ADDE 4 9 ADDR bus signals 5 31 definition 2 6 signal 5 35 starting address D 18 Address bus ADDR 5 31 extension 4 6 fields 4 5 register 4 5 map 3 18 mark wakeup 9 30 10 22 space encoding 5 32 maps 3 19 strobe AS 5 31 Addressing modes 4 8 accumulator offset 4 10 extended 4 10 immediate 4 9 indexed 4 10 inherent 4 10 post modified index 4 10 relative 4 10 replacing direct mode 4 11 AIS 4 9 AIX Y Z 4 9 Analog input circuitry 8 15 considerations 8 19 pins 8 2 8 21 electrical model 8 21 power pins 8 14 reference pins 8 3 8 14 subsystem 8 4 supply filtering and grounding 8 16 For More Information On This Product l 1 Go to www freescale com Freescale Semiconductor Inc pins 8 3 to digital converter ADC See ADC 8 1 Arbitratio
613. w freescale com Freescale Semiconductor Inc Table 7 2 Wait States Field Number of Wait States WAIT 1 0 Clocks per Transfer 11 1 2 Refer to 5 6 Bus Operation for more information concerning access times 7 5 Low Power Stop Mode Operation Low power stop mode minimizes MCU power consumption Setting the STOP bit in MRMCR places the MRM in low power stop mode In low power stop mode the array cannot be accessed The reset state of STOP is the complement of the logic state of DATA14 during reset Low power stop mode is exited by clearing STOP 7 6 ROM Signature Signature registers RSIGHI and RSIGLO contain a user specified mask programmed signature pattern A user specified signature algorithm provides the capability to verify ROM array contents 7 7 Reset The state of the MRM following reset is determined by the default values programmed into the MRMCR BOOT LOCK ASPC 1 0 WAIT 1 0 bits The default array base address is determined by the values programmed into ROMBAL and ROMBAH When the mask programmed value of the MRMCR BOOT bit is zero the contents of MRM bootstrap words ROMBS 0 3 are used as reset vectors When the mask pro grammed value of the MRMCR BOOT bit is one reset vectors are fetched from exter nal memory and system integration module chip select logic is used to assert the boot ROM select signal CSBOOT Refer to 5 9 4 Chip Select Reset Operation for more information concerning e
614. ware Watchdog Service Register SWSR YFFA28 Not Used YFFA2A Not Used YFFA2C Not Used YFFA2E Not Used YFFA30 Test Module Master Shift A Register TSTMSRA YFFA32 Test Module Master Shift B Register TSTMSRB YFFA34 Test Module Shift Count Register TSTSC YFFA36 Test Module Repetition Counter Register TSTRC YFFA38 Test Module Control Register CREG Test Module Distributed Register DREG YFFA3C Not Used YFFASE Not Used YFFA40 Not Used Port C Data Register PORTC YFFA42 Not Used Not Used YFFA44 Chip Select Pin Assignment Register 0 CSPARO YFFA46 Chip Select Pin Assignment Register 1 CSPAR1 YFFA48 Chip Select Base Address Register Boot CSBARBT YFFA4A Chip Select Option Register Boot CSORBT Chip Select Base Address Register 0 CSBARO REGISTER SUMMARY M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 2 SIM Address Map Continued Address 15 8 7 0 YFFA4E Chip Select Option Address Register 0 CSORO YFFA5O Chip Select Base Address Register 1 CSBAR1 YFFA52 Chip Select Option Address Register 1 CSOR1 YFFA54 Chip Select Base Address Register 2 CSBAR2 YFFA56 Chip Select Option Address Register 2 CSOR2 YFFA58 Chip Select Base Address Register 3 CSBAR3 YFFA5A Chip Sele
615. wing code takes a number or character stored in register D assumes it s in its hexadecimal form and converts it to an ASCII equivalent It also sends that character to the screen store the hex number temporarily into TEMP reload value of hex number into D register get rid of upper 4 bits in hex number shift high 4 bits down to low 4 bits position the actual conversion process add 30 to the hex number check for digithood go print now if it s a digit 0 9 it s a letter A F so add 07 before printing 7send the character to the SCI done with hex to ascii conversion when IRQ6 is low this autovector routine starts These four lines reset the watchdog and keep it from causing a system reset by writing to the SWSR By writing a 55 and a SAA to the SWSR before the end every time out period the watchdog will be AUTOV_STRING 5 D_STRING return to the main loop exception interrupts all other exception vectors point here and put the user into background mode INITIALIZATION AND PROGRAMMING EXAMPLES M68HC16 Z SERIES For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc E 2 2 CPU16 Programming Example The following programming example involves using the CPU16 indexed and extended addressing modes Refer to SECTION 4 CENTRAL PROCESSOR UNIT for more information on the CPU16 E 2 2 1 E
616. wise normal transmission of the next sequence will begin Both TDRE and TC have associated interrupts The interrupts are enabled by the transmit interrupt enable TIE and transmission complete interrupt enable TCIE bits in SCCR1 Service routines can load the last byte of data in a sequence into SCDR then terminate the transmission when a TDRE interrupt occurs 10 4 5 6 Receiver Operation The RE bit in SCCR1 enables RE 1 and disables RE 0 the receiver The receiv er contains a receive serial shifter and a parallel receive data register RDR located in the SCI data register SCDR The serial shifter cannot be directly accessed by the CPU16 The receiver is double buffered allowing data to be held in the RDR while oth er data is shifted in Receiver bit processor logic drives a state machine that determines the logic level for each bit time This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter MULTICHANNEL COMMUNICATION INTERFACE M68HC16 Z SERIES 10 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc A receive time clock is used to control sampling and synchronization Data is shifted into the receive serial shifter according to the most recent synchronization of the re ceive time clock with the incoming data stream From this point on data movement is synchron
617. ww freescale com USER S MANUAL Freescale Semiconductor Inc PWMA PAI ADDR23 CS 10 ECLK gt IC4 OC5 0C1 PGP7 IC4 0C5 0C1 OC4 0C1 PGP6 OC4 0C1 CST10 0 ADDR22 C5 9 PC6 6 3 0 1 5 0 3 0 1 OczocupGP4 8 07 oczoci 2 ADDRIS CS6PC3 OC1 PGP3 GPT c 516 E FC2 CSSIPC2 IC3 PGP2 210 IC3 Ca 7 IL x 54 1 IC2 PGP1 IC2 T53 ICUPGPO FCOCSSIPCO 52 ADDR 23 19 BG CS1 gt BR CSO TXD PQS7 PCS3 PQS6 PCS2 PQS5 ADDR 18 0 PCS1 PQS4 50 55 053 5171 SIZ1 PE7 5170 5170 MOSI PQS1 15 KSIPES MISO PQSO DS DSIPEA 2 AVEC oye AVEC PE2 Vop 4 DSACKI DSACKI PE1 i DSACKL s DSACKO DSACKO PEO DATA 15 0 RW gt AN7 PADA7 RESET AN6 PADA6 HALT SNSPADIS p MRM CPU16 Ve KZ 4 d AN2 PADA2 IRQU1 IRQSIPF5 AN1 PADA1 Olu IRQ4 PF4 ANO PADAO ROPES oje IRQ2 PF2 IRQIIPFI MODCLK PFO CLKOUT gt EXTAL BKPT 7 IPIPEO ps BKPT DSCLK IPIPEI IPIPE 1 DSI 051 TSC TSC 050 OL Dso TEST QUOT FREEZEIQUOT _ an FREEZE 72 03 BLOCK Figure 3 2 MC68HC16Z2 Z3 Block Diagram M68HC16 Z SERIES OVERVIEW USER S MANUAL For More Information On This Product Go to www freescale com Freescale
618. xample 5 Indexed and Extended Addressing Description This program demonstrates indexed and extended addressing Ck CK ck kk kk Ck kk Ck Ck Ck Ck Ck Ck Ck Ck kk Ck kk kk Ck kk Ck kk Ck kk kk Ck kk ko kk Sk kk Sk Sk ko Sk Sk ko ko kv ko kx kv ko ko ko koc INCLUDE EQUATES ASM table of EQUates for common register addresses INCLUDE ORGOO000 ASM initialize reset vector INCLUDE ORGOO008 ASM initialize interrupt vectors ORG 0200 start program after interrupt vectors KkKKKK OFFSET GO KkKKKK BDM M68HC16 Z SERIES Initialization Routines INCLUDE INCLUDE Start of See Oe eae oe So BGND USER S MANUAL INITSYS ASM initially set EK F 0 YK 0 set sys clock at 16 78MHz disable INITRAM ASM initialize and turn on SRAM set stack SK 4 1 SP 4 03FE main program 00 point ZK to bank 0 SFFFE set IZ SFFFE 02 SET OFFSET 02 01 point EK to bank 1 00 0000 write 00 to 10000 extended SFF OFFSET 7 write ff to 510000 indexed GO Exceptions Interrupts exception vectors point here and put the user in background mode INITIALIZATION AND PROGRAMMING EXAMPLES For More Information On This Product E 23 Go to www freescale com Freescale Semiconductor Inc E 2 3 QSM SCI Programming Example The following p
619. xternal boot ROM selection M68HC16 Z SERIES MASKED ROM MODULE USER S MANUAL For More Information On This Product 7 3 Go to www freescale com 7 4 Freescale Semiconductor Inc MASKED ROM MODULE For More Information On This Product Go to www freescale com M68HC16 Z SERIES USER S MANUAL Freescale Semiconductor Inc SECTION 8 ANALOG TO DIGITAL CONVERTER This section is an overview of the analog to digital converter module ADC Refer to the ADC Reference Manual ADCRM AD for a comprehensive discussion of ADC ca pabilities Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for ADC timing and electrical specifications Refer to D 5 Analog to Digital Converter Module for register address mapping and bit field definitions 8 1 General The ADC is a unipolar successive approximation converter with eight modes of oper ation It has selectable 8 or 10 bit resolution Monotonicity is guaranteed in both modes A bus interface unit handles communication between the ADC and other microcontrol ler modules and supplies IMB timing signals to the ADC Special operating modes and test functions are controlled by a module configuration register ADCMCR factory test register ADCTST ADC module conversion functions can be grouped into three basic subsystems an an alog front end a digital control section and result storage Figure 8 1 is a functional block diagram of the ADC module In addition to use as mu
620. y code compatible with M68HC1 1 controllers All are members of the M68HC16 Family of modular microcontrollers M68HC16 microcontroller units MCUs are built from standard modules that interface via a common internal bus Standardization facilitates rapid development of devices tailored for specific applications M68HC16 Z series MCUs incorporate a number of different modules Refer to Table 1 1 for information on the contents of a specific Z series MCU x indicates that the module is used in the MCU All of these modules are interconnected by the intermod ule bus IMB Table 1 1 M68HC16 Z Series MCUs 68 1671 Modules MC68CK16Z1 MC68HC16Z2 MC68HC16Z3 68 16271 Central Processor Unit CPU16 X X X Low Power Central Processor __ __ X Unit CPU16L System Integration Module SIM X X X Low Power System Integration __ E X Module SIML Standby RAM SRAM 1 Kbyte 2 Kbytes 4 Kbytes 1 Kbyte Masked ROM Module MRM 8 Kbytes 8 Kbytes Analog to Digital Converter ADC X X X X Queued Serial Module QSM Multichannel Communication Interface MCCI General Purpose Timer GPT NOTES 1 C designator indicates a 2 7V to 3 6V part M indicates a fast reference frequency and K indicates a slow reference frequency HC stands for HCMOS 68 1674 MC68CK16Z4 The maximum system clock for M68HC16 Z series MCUs can be either 16 78 MHz 20 97 MHz or 25 17 MHz An int

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