Universal VLSI Protoboard
Contents
1. sea Py cue ssedig T T WDyd asn WDdd wn O om o a o D q c o O s A 8 eIpu taung JAd 2160 TU tke var pug s zw 2PEH pwe Aetay AS z Azis r 7 segment Displays oz a In xx SZIX zagua LI TAIHA sr 4 yeg Istq BUTITOJ 0 1 Tey Regulators 14 3 d Universal Protoboard component legend diagram 140d Butwwe 46014 LvI lt x Jasa 659 uoTrJjeuNBIJUOJ van tar AA 3 JVO JOV SINPOW SOB ov 6s ni logic Pvt Ltd Pune Universal VLSI Protoboard Chapter 4 Precautions Verify the power on LED status after applying power to the trainer Connect the 9 pin D connector of the cable to the trainer only after confirming the above During downloading make sure that the jumper selections are proper Select the proper configuration mode during programming else programming can fail Take care for adaptor position before plugging on the board Insert the PLD adaptor by looking at the circle marks given on the baseboard and adaptor card Before implementation it is necessary to lock the pins in user constraint file UCF as per the design and I Os used For downloading the bit stream the downloading circuit requires a stable Supply hence it is recommended to use power supply given along with the trainer board2. I Verity I Read Protect TDI T Write Protect p Virtex ll Pro 39572 P Se ide adder jed TO Program Key FT Use DA for CF TDO JE PRUM CodRurner4l Usercode 8 Hex Chars FFFFFFFF JU XPLA UES Enter upto 13 characters m a REM en Heb GUI Add one device GUI 1x09572 IAXilinx testladderjed x x INFO iMPACT 501 1 Added I Configuration Mode Boundary Scan No Connection For Help press F1 Step 13 After erasing the CPLD the programming would start and will configure the particular device S untitled Configuration Mode iMPACT lal xj File Edit Mode Operations Output View Help DSR SSR Ex mn 5 OE jaso gl Boundary Scan Slave Serial SelectMAP Desktop Configuration Programming Succeeded Programming devices in concurrent mode I Programming device Programming completed successfully PROGRESS_END End Operation Elapsed time 4sec gt x D For Help press F1 Configuration Mode Boundary 5can PParallel PC3 pti Z Now check the functionality on the board and verify it by applying different inputs ni logic Pvt Ltd Pune Universal VLSI Protoboard Design Flow for Quartus Il series of software of Altera Install Ouartus il version 3 0 amp above software on your machine the Supported platforms are windows NT XP 2000 We take the same example for implementing on the Altera MA
3. E demo 3 use IEEE STD_LOGIC_ARITH ALL S E c9572 15pc84 XST VHDL 4 use IFEE STD LOGIC UNSIGNED ALL TY adder adder vha 5 5 entity adder is 7 Port a t dn std logic e in std logic a sun out std logic ha carry out std logic 11 ena adder h2 13 architecture Behavioral of adder is ha h5 begin he z He sum Ce a xor bi XOR Gate Sum o p s he NG Module view tea Snapshot view D Library View o carry lt a and b AND Gate carry o p el pi izixi 22 end Behavioral Processes for Current Source ie Design Eny Ule s User Constraints s Synthesice Implement Design BO Generate Progamming Fie k si eg e O OOOO Hierarchy isup to date nade f za ni logic Pvt Ltd Pune 18 Universal VLSI Protoboard Step 6 Create new source file for implementation constraint file Name it adder UCF and associate with the corresponding design file z lalag 21 isixi OSES FEE EAR Bal la alsa anlo EF ibrar z Sources in Project demo 5 c9572 15pc84 XST VHDL IN acer adder yn Z Add to project Lent las Fu T iprocess vew Baj ZZ E For Helo oress FL ZZ haas O Step 7 To assign the pin location of the design open the UCF file to run the constraint editor where we have to lock the I Os of design to a particular pin number RE vigator I X
4. Kindly remove the cables from holding its headers only Removing the cables from holding its wires may cause damage to cable joints ni logic Pvt Ltd Pung 15 Universal VLSI Protoboard Design Entry Implementation ni logic Pvt Ltd Pune Chapter 5 Design Flow HDL Verilog VHDL Hardware Description Language Very High speed Integrated circuit HDL Verilog having C based constructs Functional Verification Functional simulation of the design No timings are considered Process for converting design specifications into gate level netlist Needs synthesis library containing target technology information Combined name for processes like for translation floorplanning mapping place amp route bit file generation For locking input and output signal to the particular pins of the device user must write UCF User Constraint File before implementation Output of implementation is BIT for FPGA and ED file for CPLD which can be directly program into the target device This is the process by which user can physically download the design programming files from PC to target device using programming cable To program CPLD select Boundary scan TAG mode To program FPGA select Boundary scan slave serial mode or Master serial Mode Universal VLSI Protoboard Using EDA Tools In this chapter we will see how a project can be created in Xilinx and Altera EDA t
5. Universal VLSI Protoboard Another key benefit of using PLDs is that during the design phase customers can change the circuitry as often as they want until the design operates to their satisfaction That s because PLDs are based on re writable memory technology to change the design the device is simply reprogrammed Once the design is final customers can go into immediate production by simply programming as many PLDs as they need with the final software design file CPLDs and FPGAs The two major types of programmable logic devices are field programmable gate arrays FPGAs and complex programmable logic devices CPLDs Of the two FPGAs offer the highest amount of logic density the most features and the highest performance The largest FPGA provides millions of system gates the relative density of logic These advanced devices also offer features such as builtin hardwired IP cores such as the IBM Power PC PCI cores microcontrollers peripherals etc substantial amounts of memory clock management systems and support for many of the latest very fast device to device signaling technologies FPGAs are used in a wide variety of applications ranging from data processing and storage to instrumentation telecommunications and digital signal processing CPLDs by contrast offer much smaller amounts of logic up to about 10 000 gates But CPLDs offer very predictable timing characteristics and are therefore ideal for critical contro
6. ni2 designs Universal VLSI Protoboard ni logic Pvt Ltd 25 B5 Bandal Complex Paud Road Kothrud Pune 411 038 Maharashtra Tele Fax 91 20 2528 6948 info ni2designs com www ni2designs com Universal VLSI Protoboard Universal VLSI Protoboard User Manual Table of contents 1 0 ni logic Pvt Ltd Pune Introduction a Introduction to Programmable logic and PLDs b Product Introduction Features and Specifications Diagrams a 1 0 Connections for Xilinx FPGA b 1 0 Connections for Altera FPGA c 1 0 Connections for CPLDs d Baseboard legend diagram Precautions Design Flow a PLD design flow b Xilinx webpack design flow c Altera Quartus Il design flow Configuration Downloading a Types of Modes b Jumper setting for mode selection Pin Assignments J umper settings Sample Codes Glossary Universal VLSI Protoboard Chapter 1 Introduction 1 a What is Programmable Logic In the world of digital electronic systems there are three basic kinds of devices memory microprocessors and logic Memory devices store random information such as the contents of a spreadsheet or database Microprocessors execute software instructions to perform a wide variety of tasks such as running a word processing program or video game Logic devices provide specific functions including device to device interfacing data communication signal processing data display timing and control operations and almost every
7. dh 45 0 N Start Analysis amp Elaboration mf compilation Report cr a Start Compilation amp Simulation Ha sat Ha CI Compilation Hierarchies ap Start Assembler D Start Simulation Ctrl adder x ng Start Timing Analyzer Ctrl Shift L Simulation Debug Oe eerie rt er Simulation Report Ctrl Shift4 R Gai es eM Pag start Design Assistant Pr start Software Ctr geo ALILA AA Compile Current File end adder architecture Behaviore begin sum lt a xor b carry lt a and b end Behavioral IN Compite Simulate 7 ni logic Pvt Ltd Pune R Start SignalProbe Compilation Ctrl Shift45 hy Start 1 0 Assignment Analysis Start Minimum Timing Analysis Start VOM Writer Start Test Bench Template Writer Start EDA Resynthesis AND Gate carry o p Universal VLSI Protoboard lax zlelxi baa nat maa Gi AG YA reece ES eeeoo 77 2 FM29 Analysis amp Synthese Status Successful Sun Oct 12 20 00 52 2003 Compiler Setting adder Toplevel Entity Name adder Family Max70005 Total macrocells 2 Total pine 4 4 Compile A Simulate 4 oj Step 9 For performing simulation we need to create stimuli file from where we can apply input signals and watch the o p waveforms Goto file menu and click new file goto other files tab and select vector waveform file option Device Design Files Software Files Other Files AHDL Include File Block
8. Hierarchies Compiler Settings Wizard Simulator Settings Wizard 0 Software Build Settings Wizard U g dare Editor CtrltshifttA _ pe nts Ping Ib Boc Annotate Assignments Processing Total 1 Import MAX PLUS II Assignments gt Last Compilation Floorplan Timing Closure Floorplan G Chip Editor ab A LogicLock Regions Window AlkHL 83 Import LogicLock Regions 88 Export LogicLock Regions 4 Compile Sinus ni logic Pvt Ltd Pune Universal VLSI Protoboard Step 12 Now goto simulator setting then to mode and in the right hand side window select the simulation mode to Functional C3 Compilation Hierarchie adder User Libraries Select the simulation mode Toolset Directories 8 wee ge m Changes apply to Simulator settings adder input Verilog HDL Input Simulation mode Mi 4 EDA Tool Settings Descriptor M saa Pela Logi Option Setings meeer e HE s Default Parameter Settings Dang Hi nl UG smele o Gel Wi Z ME hon This netist can be a post smi rl bare mb estimated timing or a ist that actual timing information You can use Tel commands and aan AI a a e aeni maga a a Pil pu This ype ct liches ar SEE i karta a od maka asi tol brk totalna number Ni nodes in ree design Module Processing Total E Full Compilation Analysis amp Synthesi Fiter Assembler Timing Analyze
9. Logic Arrays EDIF Electronic Design Interchange Format A standard representation format for describing electronic circuits used to allow the interchange of circuit design information between EDA tools FPGA Field Programmable Gate Array An integrated circuit containing a large number of logic cells or gates that can be programmably configured after the IC has been manufactured Some FPGAs use fuses for this programming and others store the configuration in an on chip EEPROM or RAM memory Fuse programmed parts cannot be reprogrammed so they can only be configured once EEPROM based FPGAs can be erased and reprogrammed so they can be configured many times RAM based FPGAs can be reconfigured quickly even while the circuit is in operation HDL Hardware Description Language A synthetic computer based language used for the formal description of electronic circuits An HDL can describe a circuit s operation its design and a set of tests to verify circuit operation through simulation The two most popular digital HDLs are VHDL and Verilog An analog HDL called AHDL is under development by many vendors HDLs make it easier to develop very large designs through formal software engineering methods that define ways hitlogic PvtLtds Pune oe eee oe Ga 43 Universal VLSI Protoboard to divide a large team project into smaller pieces that can be implemented by individual team members Moore s Law An empirical law developed and later revis
10. and XC9500 series of devices from Xilinx and ACEX 1K and MAX7000s series of devices from Altera The Universal VLSI Protoboard has not limited himself for 1 0 requirement in designs it supports packages like PLCC 84 TQ144 and PO208 ni logic Pvt Ltd Pune 6 Universal VLSI Protoboard Chapter 2 Features amp Specifications 2 a Features and Specifications Technical specs Multi vendor device support for Xilinx and Altera PLDs Packages supported PLCC84 TQ144 and PQ208 Upto 140 user I Os Four Multiplexed 7 Segment displays Interface to RS232 with 9 pin D type connector User selectable configuration modes using either SPROM JTAG Slave Serial Byte blaster cable interface for configuration of Altera FPGAs On board 8 MHz Clock oscillator user selectable 2 Configurable 24 switches as I P or O P 16 digital LED indicated outputs 2 Poweron Reset and configuration reset key 2 Poweron Reset and configuration reset key Support for different I O Standards 2 Complaint with Xilinx ISE series software 2 Complaint with Altera Quartus design software ni logic Pvt Ltd Pune Universal VLSI Protoboard 2 b Individual Module Specification Xilinx CPLD Module o XC9572 PC84 15C containing 72 macrocells with 1 600 usable gates Xilinx FPGA Module o 30 000 gate density XC2530 PQ208 5 FPGA from Xilinx Altera CPLD Module o EPM7128SLC84 15C device containing 128 macroce
11. click New and select VHDL File in the device design files tab Click OK sessing Tools Window Help a ED DO VGO POV za 5BV x2 sn Universal VLSI Protoboard Step 6 Write the VHDL code for half adder design and save the file as adder vhd W Quartus IT c quartus demo adder adder vhdll vhd 3 File Edt View Project Assignments Processing Tools Window Help PMP 218 x OSG SJ MGC LkDSRBES KeunaBe COOOD vo Gal SAO xx AND Gate carry o p courier New zlo z 50 A ROS B ely library IEEE use TEEE STD_LOGIC_1164 ALL Sy aala sare use IEEE STD LOGICARITH ALL NG si use IEEE STD LOGIC UNSIGNED ALL entity adder is Port a in atd_logies p 1 dn std logic sum out std logic Carey oi our srd logic end adder architecture Behavioral of adder is begin sum lt axor b XOR Gate Sun o p Ss Hierarchies carry lt a and b Sr end Benevioral mo come SET Processing A System For Help press F1 nz cle ah Tle now Step 7 Now goto processing menu then start click start analysis and synthesis juartus II c quartus demo adder adder adder vhd File Edit View Project Assignments Processing Tools Window Help EEDIEE TE Graf xena e IJ ge gt Start Compilation Ctrl Lensa aiba Courier New v 10
12. goto processing menu and click start compilation process Which will fit the design in CPLD and generate the programming file jemo adder adder Vhdl1 vhd 215 x 18 x Dari Ginn EI SO KeNDAHeS mov x Courernew zlo zi Spa 1164 ALL Start Compilation amp Simulation PARITH ALL D Start Sdin crit Ponteng ant Simulation Debug Db simulation Report Ctrl Shift R Start Software Buld Ctri Q end adder architecture Behavioral of adder is begin sum lt 2 a xor bi XOR Gate Sum o p carry lt aandb AND Gate carry o p end Behavioral N compie Ksm 7 la F ia Starts a new compilation ins colt Mensa ide TO um Step 17 Once the compilation process is over user can check the reports and see the floorplan window Quartus II c quartus demo adder adder adder Compilation Report E o zleixi File Edit View Project Assignments Processing Tools Window Help 18 x DESUS daulat T NI seuvpaje evovo zda pad iu x ES compilation Report SB Legal Notice SE Flow Summary EE Flow Settings BES Flow Elapsed Time GOD Analysis amp Synthesis 286300 SE Fitter Summary EE Fitter Settings E Fitter Device Options ob Fitter Equations BE Forlan view Fitter Status Successful Sun Oct 12 20 31 01 2003 Gm Pin Out File Compiler S N ide JE gE Resource Section pola Sep Nana gatang Processing Total Zw Fitter Messages
13. more programming details refer the respective device datasheet ni logic Pvt Ltd Pune Universal VLSI Protoboard Chapter 7 Pin Assignment For Xilinx Devices Spartan ll FPGA XC2530PQ208 XC9500 CPLD XC95xx PC84 Clock and Reset O P LEDs 7 segment Display FPGA CPLD FPGA CPLD FPGA CPLD FPGA CPLD Reset 206 74 L15 45 35 L7 61 45 Saga 21 34 Clock 80 10 L14 46 36 Lb 62 46 SegB 29 33 L13 47 37 L5 63 47 SegC 30 32 L12 48 39 4 67 48 SegD 31 31 L11 49 40 L3 68 50 SegE 33 26 L10 57 41 L2 69 51 SegF 34 25 L9 58 43 L1 70 52 SegG 35 24 L8 59 44 LO 71 53 JSegDP 36 23 RS 232 Port DISPEnl 37 19 FPGA CPLD DISP En2 41 17 RXD 193 NA DISP En3 42 15 TXD 192 NA DISP En4 43 14 NA Not Available ni logic Pvt Ltd Pune Universal VLSI Protoboard For Xilinx Devices Spartan ll FPGA XC2530PQ208 XC9500 CPLD XC95xx PC84 Configurable Switches O FPGA CPLD I O FPGA CPLD WO FPGA CPLD 23 73 54 S515 87 65 S7 99 15 s22 74 55 S514 88 66 S56 100 76 S21 75 56 513 89 67 S5 101 11 S20 81 57 SI2 90 68 S4 102 19 S19 2 58 S11 94 69 53 108 80 18 83 61 S10 95 10 2 109 81 S17 84 62 S9 96 11 51 110 82 S16 86 63 S8 98 12
14. other function a system must perform Fixed Logic versus Programmable Logic Logic devices can be classified into two broad categories fixed and programmable As the name suggests the circuits in a fixed logic device are permanent they perform one function or set of functions once manufactured they cannot be changed On the other hand programmable logic devices PLDs are standard off the shelf parts that offer customers a wide range of logic capacity features speed and voltage characteristics and these devices can be changed at any time to perform any number of functions With fixed logic devices the time required to go from design to prototypes to a final manufacturing run can take from several months to more than a year depending on the complexity of the device And if the device does not work properly or if the requirements change a new design must be developed The up front work of designing and verifying fixed logic devices involves substantial non recurring engineering costs or NRE These NRE costs can run from a few hundred thousand to several million dollars With programmable logic devices designers use inexpensive software tools to quickly develop simulate and test their designs Then a design can be quickly programmed into a device and immediately tested in a live circuit There are no NRE costs and the final design is completed much faster than that of a custom fixed logic device ni logic Pvt Ltd Pune
15. 10 80 14 S2 90 17 S17 68 64 S9 81 15 51 91 16 S16 69 65 S8 82 16 0 92 15 NA Not Available Note Lock the listed I Os of entity in Quartus Il assignment organizer before downloading the configuration file in the respective PLD ni logic Pvt Ltd UNG AG eR NAN RA NA IANG 39 Universal VLSI Protoboard Chapter 8 Header and J umper settings Clock Jumper Setting Clock 1 2 8 MHz 2 3 GND Clock GCKO Gnd Note The GCKO pin of FPGA is used for applying clock Mode Selection Header JP1 JTAG Short 1 2 Slave Serial Short 2 3 TDI DIN TCK CCLK TMS PROG TDO DONE Mode Selection Switch MO M1 M2 JTAG 1 J0 1 Slave Serial 1 1 1 Master Serial 0 0 10 J umper selection for PROM Bypass PROM Use PROM J P2 Short 1 2 Short 2 3 JP3 Short 1 2 Keep open ni logic Pvt Ltd Pune Configurable I Os 1 0 number Input Output 523 50 Short 1 2 Keep open Output LEDs JLOJL7 JL8 JL15 Header Name Ident FPGA Header JHL J H2 J H3 J H4 Power supply P6 ni logic Pvt Ltd Pune Universal VLSI Protoboard Universal VLSI Protoboard Chapter 9 Sample Codes User can use sample codes to work on Universal trainer board provided along with the kit The list of sample
16. A tools in addition to the Quartus II software that you will use on this project esign processing Click next EDA tools Tool name Formal verification Resynthesis lt None gt lt None gt None None None Tool settings Tool type Design entry synthesis Tool name lt None gt z JE Run this tool automatic ally to synthesize the current desian Settings Back Finish Cancel Step 3 Select MAX7005 device family in the next window Click next New Project Wizard Device Family page 4 of 6 x Which device family do you wish to target Do you want to assign a specific device Yes C No want to allow the Compiler to choose a device Back Next Finish Cancel ni logic Pvt Ltd Pune Universal VLSI Protoboard Step 4 In the next window select the device as EPM7128SLC84 15 Click next New Project Wizard Select a Target Device page 5 of 6 og Use the Filters settings to control the devices that are displayed in the Available devices list Select a device in the list and click Next to continue Available devices Filters Package rice z Pin count fes z Speed grade fis FI Voltage 5 0v Back Nea Finish Cancel Step 5 Click Finish And the new project would be created Now we need to make and add new design file in the project So goto File menu and
17. Behavioral a OA lu vi i T Procese view D adder in zo colaz Process Generate Programming Fie is up to date ni logic Pvt Ltd Ne Olgi 20 Universal VLSI Protoboard Step 10 After the all the three processes are successfully over run the configure device impact option to open the impact programmer After opening impact add Xilinx device design file for CPLD itis jed file and for FPGA itis bit file 051 x C untitled Configuration Mode iMPACT Fis Edt Mods Operations Output View Help ga Do ee Ha o gN Boundary Scan Stave Serial SeleciMAP Desktop Configuration ax Look in TJ Xilinx test gt e xE Open Files of type Al Design Files z Cancel VA Configuration Mode Boundary Scan No Connection lo SERU Do ul SME Desktop Configuration Verify Erase Functional Test Blank Check Readback Boundary Scz Program PLA UES Get Device ID Get Device Checksum Get Device Signature Usercode PLA device UES Programs the selected devices Configuration Mode Boundary Scan No Connection Z ni logic Pvt Ltd Pune 21 Universal VLSI Protoboard Step 12 Keep the erase option enabled and click OK C untitled Configuration Mode iMPACT 5 a loj x File Edit Mode Operations Output View Help JO H reg EE LACE TY Boundary Scan Slave s Hae 21 I Erase Before Programming J Functional T
18. S0 111 83 NA Not Available Note Lock the listed I Os of entity in User Constraints File UCF with the above pin numbers before going for implementation process hitlogic Pyt Ltd Pune sa ek AA NG 37 For Altera Devices ACEX 1K FPGA EP1k50 TQ144 2 MAX7000S CPLD EPM7125SLC84 Universal VLSI Protoboard Clock and Reset O P LEDs 7 segment Display FPGA CPLD FPGA CPLD FPGA CPLD FPGA CPLD Reset 122 1 L15 31 35 7 43 46 Sega 17 25 Clock 55 83 L14 32 36 L6 44 48 SegB 18 27 L13 33 37 L5 46 49 SegC 19 28 L12 36 39 L4 47 50 SegD 20 29 L11 37 40 L3 48 51 SegE 21 30 L 10 38 41 L2 49 52 SegF 22 31 L9 39 44 L1 51 54 SegG 23 33 L8 41 45 LO 59 55 SegDP 26 34 RS 232 Port DISP Enl 27 20 FPGA CPLD DISPEn2 28 21 RXD 124 NA DISP En3 29 4 TXD 140 NA DISP En4 30 5 NA Not Available ni logic Pvt Ltd Pune ee eR tet tet tal 38 Universal VLSI Protoboard For Altera Devices ACEX1K FPGA EP1k50 TQ144 MAX7000S CPLD EPM7125SLC84 Configurable Switches O FPGA CPLD I O FPGA CPLD WO FPGA CPLD 23 60 56 S515 70 67 S7 83 11 s22 62 57 S514 72 68 S6 86 79 S21 63 58 513 73 69 S5 87 80 S20 64 60 S12 78 10 S4 88 81 19 65 61 S11 79 73 S3 89 18 18 67 63
19. Symbol File Chain Description File Hexadecimal Intel Format File Memory Initialization File SignalT ap II File Tel Script File Text File Vector Waveform File ni logic Pvt Ltd Pune 27 NEA Baan NN AG BABAE NIT RE SA AAP a RE PRENO Universal VLSI Protoboard Step 10 Add the entity signals in the waveform window and apply different sets of value to check the functionality Save the file as the same name of entity adder vwf E Quartus II c quartus demo adder adder adder vwf j x dn File Edit View Project Assignments Processing Tools Window Help isixi osu a rejo r rD Lege Kena e BOovvj sGe ASN ih A Master Time Bar 1055ns Pointer 845ns Intervat 21ns Start End ni at E Compilation Hierarchies Lg adder 2 Module Progress Processing Total 1007 Analysis amp Synthesis 4 Compile A Simulate Step 11 In Altera Quartus ll software you can perform Functional and Timing simulation For simulation mode settings for to assignments menu and click settings E Quartus II c quartus demo adder adder adder vwf er TT zlaixi dr Ele Edt view Project Assignments Processing Tools Window Help lal x BEE B x BY orto balse ic mn ins KO WDB AS maymay a BBO XX Ye Tool Settings e HEN Sns s 5 Poiec Tan Intervak 915n5 Stat End VA Compilation
20. Toplevel Entity Name adder 5 Full Compilation HES Assembler Family MAX70005 Analysis amp Synthesis BEB Assembler Summary Device EPM7128SLC84 15 Fitter EO BEB Assembler Settings Total macrocells 2 128 1 Assembler BEB Assembler Generated Files Total pins 8 68 11 Timing Analyzer II GOES Assembler Device Options adder pof EFD Assembler Messages HES Timing Analyzer QE Timing Analyzer Settings BEB Timing Analyzer Summary gA tod SE Minimum tod EBD Timing Analyzer Messages 4 A Compite ni logic Pvt Ltd Pune 31 Universal VLSI Protoboard Step 18 Now we need to program CPLD for this goto tools menu and click programmer Which will open the programmer the software will automatically add the programming file adder pof In the opened window select the program configure option Now we need to select the programming hardware for which click the hardware tab on the LHS of programming window s Sergeo 28208 FOS Tadia lase PTI Mede mas Pipes z Gi CERBEREXE tz Step 19 In the opened window Click add hardware tab and select the hardware type as pi or ByteBlaster Il and port as LPTI pi TI g x gt Hardware Settings JTAG Setings Select a programming hardware setup to use when programming devices This programi ki hardw
21. X7000s CPLD Step 1 Start Quartus ll version 3 0 amp above software Step 2 For new project creation go to File option and select new project wizard In the opened window specify project location and design and entity name For eg Entiy name adder and top design name also adder Click next New Project Wizard Directory Name and Top Level Entity page 1 of 6 What is the working directory for this project This directory will contain design files and other related files associated with this project If you type a directory name that does not exist Quartus Il can create it for you C quartus demo adder ons What is the name of this project If you wish you can use the name of the project s top level design entity What is the name of the top level design entity in your project The Quartus Il software will automatically create Compiler and Simulator settings for the top level entity you specify in this wizard After you create a project you can add more top level entities and create Compiler and Simulator settings for them with commands on the Assignments menu Back Net Finish Cancel ni logic Pvt Ltd Pune Universal VLSI Protoboard Step 3 Click next button till you reach EDA tool settings window there keep all options as none which in default will select the inbuilt design tools and softwares for the d New Project Wizard EDA Tool Settings page 3 of 6 e x Specify the other ED
22. are setup apples on to the curent programer window 4 cem xi r tie Hardware type ByteBlasterMV or ByteBlaster Il z adware m Pott LPTI z zl ke til Baud tale zii Ce IB cae pe ni logic Pvt Ltd Pune 32 Universal VLSI Protoboard Step 20 Come back to hardware setup window and click the select hardware tab and close the window Da CE EEE zisix BEE IMETI KITI KONDE vije DOVO s IVA BRD xa ll Had Noas Mode TaS z Poses ll ri Se p Hari zl SI Compilation Hierarchies LO s E Ga x als Hardware Settings JTAG Settings Pa mg hardware setup to use when programming devices This programming a tup applies only to the current programmer window 2 Currently selected hardware No Hardware 1 Pa MENI e Aa IT Io 4 H Sma Hi Select Hardware 5 Simulator Total ma Local LPT NUNE Nata aC EA MEH ES Remove Hardware 4 Siman a Ta Devke HY San Ow aLTERESO F Into poganning 7 dove Info Device 1 LES code is FFFF E inte DONE E Irto Successtuly perfomed operations E Info Successfully performed operation s For Help press Fi mrasa ide O Nmf Step 21 Now click the start programming button play symbol on the top LHS of the programming window keep the program configure option selected ul zi lxi UE Fie Edt view mo rn pres ii Windo
23. codes provided is mentioned below for more information and getting new examples and code user can visit our website www ni2designs com Digital logic code o Combination circuits RRRRRRRRRRRRA Dm o Sequ RRRRARA ni logic Pvt Ltd Pune Basic logic gates Binary to gray converter 7 segment decoder 3 8 decoder Demultiplexer Multiplexer Parity generator Full adder behavioral model Full adder structural model Half adder 4 bit ALU Model of IC 74xx245 Model of IC 74181 4 bit ALU ntial Logic 4 bit binary counter 4 bit universal binary counter D F F with asynchronous reset D F F with synchronous reset SRAM model 16 bytes 4 bit shift register with enable load and parallel o ps Universal VLSI Protoboard Chapter 10 Glossary of Terms ASIC Application Specific Integrated Circuit A custom integrated circuit designed specifically for one end product or a closely related family of end products Concurrency The ability of an electronic circuit to do several or at least two different things at the same time Contrast with computer programs which usually execute only one instruction at a time unless the program is running on a processor with multiple concurrent execution units CPLD Complex Programmable Logic Device A programmable IC which is more complex than the original Programmable Logic Devices such as AMD s originally MMI s PALs but somewhat less complex than Field Programmable
24. ed by Intel s Gordon Moore which predicts that the IC industry is capable of doubling the number of transistors on a silicon chip every 18 months originally every year resulting in declining IC prices and increasing performance Most design cycles in the electronics industry including embedded system development firmly rely on Moore s law Net List or Netlist A computer file sometimes a printed listing containing a list of the signals in an electronic design and all of the circuit elements transistors resistors capacitors ICs etc connected to that signal in the design PLCC Plastic Leaded Chip Carrier A low cost IC package usually square PLCCs have interconnection leads on either two usually only for memory chips or all four sides for logic and ASIC chips PLD Programmable Logic Device The generic term for all programmable logic ICs including PLAs programmable logic arrays PALs CPLDs complex PLDs and FPGAs field programmable gate arrays PROM Programmable Read Only Memory An integrated circuit that stores programs and data in many embedded systems PROM stores retains information even when the power is off but it can only be programmed or initialized once RTL Register Transfer Level or Register Transfer Logic A register level description of a digital electronic circuit Registers store intermediate information between clock cycles in a digital circuit so an RTL description describes what intermediate info
25. entory Customers who use fixed logic devices often end up with excess inventory which must be scrapped or if demand for their product surges they may be caught short of parts and face production delays PLDs can be reprogrammed even after a piece of equipment is Shipped to a customer In fact thanks to programmable logic devices a number of equipment manufacturers now tout the ability to add new features or upgrade products that already are in the field To do this they simply upload a new programming file to the PLD via the Internet creating new hardware logic in the system Conclusion The value of programmable logic has always been its ability to shorten development cycles for electronic equipment manufacturers and help them get their product to market faster As PLD suppliers continue to integrate more functions inside their devices reduce costs and increase the availability of time saving IP cores programmable logic is certain to expand its popularity with digital designers ni logic Pvt Ltd Pune Universal VLSI Protoboard 1 b Product Information The Universal VLSI Protoboard is a low cost universal platform for testing and verifying designs based on the Xilinx and Altera PLDs Using this protoboard the user can verify his PLD designs with practical concepts of HDL designing Universal VLSI Protoboard supports multiple vendor devices from Xilinx and Altera who are world leader in PLD manufacturing It supports Spartan 2
26. escription language developed in the 1980s by IBM Texas Instruments and Intermetrics under US government contract for the Department of Defense s VHSIC Very High Speed Integrated Circuit program VHDL enjoys a growing popularity with ASIC designers as VHDL development tools mature ni logic Pvt Ltd Pune Universal VLSI Protoboard www ni2designs com ni logic pvt Itd 25 B 5 Bandal Complex Bhusari Colony Paud Road Kothrud Pune 411 038 Maharashtra Tele fax 91 20 2528 6948 Email info ni2designs com www ni2designs com ni logic Pvt Ltd Pune 46
27. i vhd ea t Assignments Processing Tools Window Help 18 x Keng 129 Tin aaa Eny Timing Weard Gi Compilation Hierarchies Compler Settings Wizard HP adder Simulator Settings Wizard amp Last Compilation Floorplan 9 Timing Closure Floorplan Tae as Hierarchies Bri Setkan Window att O hay lagak agre f 88 Export Logiclock Regions Z TES zi al Processing A System Assian Pins fin Colt Masa ida CO NM Step 15 Looking at the pin assignment chapter lock the MAX7000s CPLD I O with the particular pin no for this select the I O number on the LHS name the design l O in the bottom pin name option and then click add the gi signal m be BAG to that pin number zl lxi la x ip usia xe WERE xi lem ni sigrment you wish to make You can also make pin assignments in the Assignment Editor and the ping on a devico vide basis wih ihe Unused Pins teb In the Device amp Pin Option dialog box design bef 19 SignalProbe signals Nu Name Sa Vo Sanda ye Spans sance Nene Enid Sa Ga ET WA vo of inom For Help press F1 nai La Universal VLSI Protoboard Step 16 Once the pin assignment is over come back to main window Now we need to implement the design on the particular device So
28. ided on this header and other end to PCs parallel port to configure the PLDs Note Kindly remove the cables by its headers only Removing the cables by handling its wire may cause damage to its joints ni logic Pvt Ltd Pune 10 Universal VLSI Protoboard 16 O P LEDs Config Reset 7 Seg Displays Chapter 3 Diagrams Functional neo PO208 24 configurable switches 3 a System Connection Diagram Xilinx FPGA ni logic Pvt Ltd Pune Universal VLSI Protoboard Config Reset ACEX1K Functional FPGA TQ144 7 Seg Displays 16 O P LEDs 24 configurable switches 3 b System Connection Diagram Altera FPGA ni logic Pvt Ltd Pune Universal VLSI Protoboard Functional Reset CPLD PLCC84 7 Seg Displays 16 O P LEDs 3 c System Connection Diagram CPLDs 24 configurable switches ni logic Pvt Ltd Me ooo 13 Universal VLSI Protoboard Configuration Mode Selection 01 1727 t1 vl S1 91 21 B1 61 OMTITIZIISTIPTISTI CXXXXXXXI CXXXXXXX dstq 1 dsig E Baga spo TETOS tar ane pra Il we Yeo so Ya anoa oa Soda SWL a709 Mal NIG 1a zar
29. ilinx_test demo npl adder laj xj 8 Fie Edt dow Help gt lal x OSEG HVE NSA EAR tae sca ajlsaanlo nn sala 2 use IEEE STD LOGIC 1164 ALI use TEER STD LOGIC ARITE ALL 5 MET ban ata tags 5 8 ka hi te mitt Mode view tem Snapshot Ha Kirm Toggle Paths D me Processes for Current Source 18 sum lt a xor b XOR Gate Sum 0 p af User Constants se lazy lt n end bs am Gate carey o p bi ba lai timers ven J a sf ni logic Pvt Ltd Pune 19 Universal VLSI Protoboard Step 8 Once the constraint editor is open goto ports tab and assign the pins by referring the Pin assignment chapter Fo net A loc ae ie zlelxi Port Direction i es TO VO Configuration Options Group Name PadtoS Prohibit 1 0 Locations aa ef stup Clock to Pad Global Ports Advanced Misc a UCF Constraints read write UCF Constraints read only Step 9 Save the UCF file and come back to project navigator Now selecting the adder design file run the synthesis process there after Implementation and finally run generate programming file option x Project Navi zlelxi 18 Fie Edt View zom 2 2181 x Deag uvs ith view ta srna view IP Ubay vew zal 7 Processes ja om XOR Gate Sun oh ee carry cea and b AID Gace carry o p 3k ANA 22 end
30. l applications Low power CPLDs are also available and are very inexpensive making them ideal for cost sensitive battery operated portable applications such as mobile phones and digital handheld assistants The PLD Advantage Fixed logic devices and PLDs both have their advantages Fixed logic devices for example are often more appropriate for large volume applications because they can be mass produced more economically For certain applications where the very highest performance is required fixed logic devices may also be the best choice However programmable logic devices offer a number of important advantages over fixed logic devices including ni logic Pvt Ltd Pune Universal VLSI Protoboard PLDs offer customers much more flexibility during the design cycle because design iterations are simply a matter of changing the programming file and the results of design changes can be seen immediately in working parts PLDs do not require long lead times for prototypes or production parts the PLDs are already on a distributor s shelf and ready for shipment PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets PLD suppliers incur those costs when they design their programmable devices and are able to amortize those costs over the multi year lifespan of a given line of PLDs PLDs allow customers to order just the number of parts they need when they need them allowing them to control inv
31. lls with 2 500 usable gates Altera FPGA Module o 50 000 gate density EP1K50 TQ144 3C FPGA from Altera Note Above module are optional with the product ni logic Pvt Ltd Pune oe An A AA NAN RK NA TG 8 Universal VLSI Protoboard Power supply The 3 3V and 2 5V are generated onboard through regulators other supply voltages are applied from external power supply Here is the list of voltages on board used V 5V 12V 3 3V 2 5V Note The above specifications and features of product are subject to change with new versions of product Connectors Header Name Ident FPGA Header H1 H2 H3 H4 Powersupply P6 umpers J umpers are provided on baseboard for selection of 1 Configuration mode pins 2 Bypassing the PROM 3 Selecting configurable Input or Output 4 Selecting the O P LEDs o JP1 Mode selection header o JP2 PROM bypass o JP3 PROM bypass o 50 57 SW1 o 58 515 SW2 o 516 523 SW3 o JLOJL7 O P LEDs o JL8JL15 O P LEDs ni logic Pvt Ltd Pune Universal VLSI Protoboard Downloading cable For Xilinx PLDs For configuration of Xilinx FPGA and CPLD from PC a 9 pins D Type connector is provided on baseboard The Universal Protoboard can be connected to PC s parallel port with cable provided having 25 pins D Type connector on other end For Altera PLDs Altera PLD adaptors have onboard J TAG header User has to connect the programming TAG cable prov
32. ools and how we can proceed to use Universal Protoboard to perform our experiments We take the example of half adder and implement on both vendor devices Design flow for Xilinx ISE series softwares Step 1 Open ISE webpack software Step 2 Create new project Caleb w Heh KL 2E seemne rejsej eja aAssan v EF ce vin Hierarchy is upto date na BERI sear NN r Universal VLSI Protoboard Step 4 Select VHDL source file name it adder click next and enter entity I Os as A B Sum amp Carry Project Navigator IAXilinx testidemo npl Mew Project Source Process Window Help Duger Hana ste se jalT H4535 0 FF Sources in Project 0957215p084 XST VHDL Entity Name adder Architecture Name Behavioral Port Name Direction mse tse a m l l b in sm m iL cary odide view feu Sraetat View TE Lorry view ja REZ JJ in Processes for Curent Source HI g Design Enty Unies ba in in Dixilinx Project Navigator IAXilinx test demo npl adder g File Edt View Project Source Process Window Help 2 a Dawgs A o H4aa1 9 EF T library IEEE a 2 use TEEE 3TD LOGIC 1164 ALL
33. r on Sister Set ings General Mode TimeNectors E Software Build Settings Stati GX Registaion 3 si pe NO mal Ha how Step 13 After clicking OK come back to main window and goto processing window and click start simulation the Quartus ll will start the simulation the result would appear in couple of minutes Observe the results if found bugs then change VHDL code and start simulation again Quartus TI c quartus demo adder adder adder Simulation Report E a Fie Edt View um mmm Processing Tools Window Help l x SESTER ITI TIK IZI Menga levee ses pav sal nal SJ set Report Bi daa Master Time Bar 50na a Pointer 32m ntewat 18n Stat Ops End 1000ne nito for addr Samat Value at PPE SG Dd Simulation Waveforms BBD Messages pa KB Fra processng time D b Bo ak sum BT ZG S cay BO XE ye ae it XE XS X i Be at ZI Tro Design adder Simulation was success 0 erors waring Processing K System 7 For Help press Fi ura ji Ide m JI ni logic Pvt Ltd Pune 29 Universal VLSI Protoboard Step 14 Once the simulation results found correct then we need to implement the design in the target device For this we need to lock our design Os with the Kit I O pin details Goto assignment menu click assign pin option jemo adder adder Vhdl
34. rmation is stored where it is Stored within t he design and how that information moves through the design as it operates Simulation Modeling of an electronic circuit or any other physical system using computer based algorithms and programming Simulations can model designs at many levels of abstraction system gate transistor etc Simulation allows ni logic Pvt Ltd Pune Universal VLSI Protoboard engineers to test designs without actually building them and thus can help speed the development of complex electronic systems However the simulations are only as good as the mathematical models used to describe the systems inaccurate models lead to inaccurate simulations Therefore accurate component models are essential for accurate simulations Synthesis also Logic Synthesis A computer process that transforms a circuit description from one level of abstraction to a lower level usually towards some physical implementation Synthesis is to hardware design what compilation is to software development In fact logic synthesis was originally called hardware compilation User Constraints File UCF A user created ASCII file for storing timing constraints and location constraints for a design implementation Verilog A hardware description language developed by Gateway Design Automation now part of Cadence in the 1980s which became very popular with ASIC and IC designers VHDL VHSIC Hardware Description Language A hardware d
35. w Help 2 8 x Oasis Aura EE 238a Beea m paj ee MM ee fa 2 KT ni Compil Hietarchi i Program Blank Security h E ai x be PE alls ar ERE 3 Info Successfully performed operaton s 4 Info Successfully performed operaton s Start Programming uro ziji Tile nom ni logic Pvt Ltd Pune 33 Universal VLSI Protoboard Step 22 The programmer will start programming and in couple of seconds the device would be configured Check the DONE indication in the bottom console window Step 23 Check the design functionality on the board by applying signal from switches or other points ni logic Pvt Ltd Pune Olgo oo 34 Universal VLSI Protoboard Chapter 6 Configuration Downloading For Xilinx devices Mode Selection Header J P1 Mode Selection Switch JTAG Short 1 2 Slave Serial Short 2 3 MO M1 M2 TDI DIN JTAG 1 0 1 TCK CCLK Slave Serial 1 1 1 TMS PROG Master Serial 0 0 0 TDO DONE The serial PROM is connected with FPGA through jumpers While configuring the PLD from PC the PROM has to be bypassed JTAG amp Slave serial modes J umper selection for PROM Bypass PROM Use PROM J P2 Short 1 2 Short 2 3 JP3 Short 1 2 Keep open EEPROM Note Altera device adaptors can be programmed only in J TAG mode For
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