PDIUSBD12 Evaluation Board (PC Kit) User`s Manual
Contents
1. B Ra BK 8 B A BWbP8 B t p Hcr e Page 14 of 14 REV 2 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com2. N Pin 18 RESET N Pin 14 2 RD N Pin 15 2 WAIT Pin 16 CS D12 Pin 17 WR 273 Pin 18 IRD 2 44 Pin 19 DIR 245 Logic Equations IDIR 245 IAD EN amp DACK st IOR RESET REV 2 1 IRD 244 IAD EN IADDR2 amp ADDR1 amp ADDRO IOR IWR 273 AD EN ADDR2 amp ADDR1 amp ADDRO IOW ICS D12 AD EN IADDR2 amp ADDR1 IOW amp IOR RESET N RESET IRQ INT N amp INT EN WAIT OE CS D12 WAIT RESET RD N IOR Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 12 of 14 REV 2 1 PDIUSBD12 Evaluation Board PC Kit User s Manual Schematics Schematics for PDIUSBD12 evaluation board v
3. 515 Ai ADDRIS A i RQ Ow ADDR18 8 9 18 vec B13 A13 Q7 25 JOR zi A13 ADDRI7 7 L0 16 Qr DACK3 ADDR16 6 11 14 Ct Shell to GND B15 A15 Q5 a DRA 1 ADDR15 5 12 12 EE B16 A16 7 04 DACKL B17 A17 ARDR14 Q3 DRQ1 ADDR13 3 14 7 B18 A18 4 Q2 DACKO ADDR12 2 15 5 B19 A19 4 Qi CLOCK 850 A20 ADDR 1 E Les 313 IRQS a as IRQ7 ADDR10 IRQ7 D u gei B21 A21 JP2 ROS ga A22 DDE9 17 p7 IRQS ADDR amp 15 B23 A23 P6 IRQS aa Aos ADDRZ ie ae IRQS ADDRG 1 DRQ1 5 B25 A25 P4 o0 6 JP3 DACK2 BS Ape ADDS 8 153 DROS D 5 rc ADDR4 6 DACKi o XA B27 A27 P2 Q 4 i5 VCC ALE ADDR3 4 DACK3 o o nV B28 A28 2 Pi 19 JP6 B29 A29 Po P Q OSC mes B30 A30 B31 A31 7 74HCT688 CON AT62 ADDR O 2 voc VCC T C ale c4 c c5 4T 4 gu 0 P5424 0 I Title D12 ISA BRIDGING BOARD Size Document Number Rev A D12 ISA 200 2 00 Date Tuesday February 24 1998 Sheet 1 of 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity PDIUSBD12 Evaluation Board PC Kit User s Manual Bill of Materials Bill of materials of the PDIUSBD12 evaluation board C2 C1 4 7 TANT 2 B8 03C8C9 CIOCTt C12 C14 C16 es Jine Gerais 8 2 GREEN 9 4 D2 D3 D4 D5 RED Bill of materials of the PDIUSBD12 ISA bridging board 3 PIJP2JPSJPAJPSJP6 JUMPER
4. PDIUSBD12 Evaluation Board PC Kit User s Manual REV 2 1 Installation of firmware INF and driver The firmware D12FW EXE runs on the device PC under DOS mode When D12FW starts it lights up test LEDs on the evaluation board for 1 second This means that the I O address setting is correct And the evaluation board is disconnected and re connected to USB by SoftConnect If this is the first time that the evaluation board is connected to host PC host OS Device Manager will prompt installation of INF and driver Select the location of D12TEST INF and D12TEST SYS and complete installation procedure Some useful key command is supported when the firmware is running Key Operation ESC Disconnect USB and quit PDIUSBD12 firmware ENTER Reconnect USB using SoftConnect Display firmware status information V Switch on off verbose mode normally turned off for faster operation Using the Host Applet The test applet D12TEST EXE exercises all PDIUSBD12 endpoints Testing of control endpoints can be further done by standard USB Chapter 9 test programs cA PDIUSBD12 Test Application X Interrupt In Endpoint 1 Generic Out Endpoint 1 p4 p3 D2 D1 Scan Test Endpoint 2 r Print Test Endpoint 2 Bytes Transfered Bytes Transfered Current Rate Current Rate Average Rate Average Rate Maximal Rate Maximal Rate Start BIOP Buffer Size 64
5. sccssscssssssssessssecssecsssecsssesssscsssssscssserssssensessnsscsssscsssesssssssscesssesscssssenssessossssssssonseosoeee 11 Address and command decodet ss ccccesseceeeeeceeeeeneececeeaeeeceneneeeceseeceseeaeeeceeeneeeseeueeesseaeeeessnneeeseeneeeeeeas 11 Schematics eerie eee eese eee eee en setenta stent aeta setas etas etes aerasi se tense tensa tensa tasse tss OSN oea Da soaa essa e sai 12 Schematics for PDIUSBDI2 evaluation board eesssssssssssseeeeeeeeenee enne nennen rennes 12 Schematic for PDIUSBDI2 ISA bridging board eseesssseeeseeeneeeeen nne nennen eene nere 13 Bill of Materials eeeeeeee esee eene e eee eene netta setis attesa setas sets setas sten s sessen soies sosiaa 14 Bill of materials of the PDIUSBDI2 evaluation board sse 14 Bill of materials of the PDIUSBDI2 ISA bridging board eene nennen 14 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 4 of 14 PDIUSBD12 Evaluation Board PC Kit User s Manual REV 2 1 INSTALLATION OF PDIUSBD12 EVALUATION BOARD Introduction The PDIUSBD12 evaluation kit uses 2 PC as a complete USB development environment a host PC with USB host capability and a device PC running PDIUSBD12 s firmware The PDIUSBD12 ISA bridging board is plugged inside the device PC and connects to the evaluation board
6. These pipes are defined as Bulk In Out endpoints Test applet and the Main Out PDIUSBD12 evaluation board supports 3 test modes loop back mode print mode and scan mode The firmware uses DMA for data transfer on these endpoints Main endpoints support 3 different test modes 1 2 3 Scan mode The PDIUSBD12 evaluation board acts like a scanner It sends data packets to the host PC as fast as possible This mode is used to evaluate the maximal Bulk In transfer rate Print mode The PDIUSBD12 evaluation board acts like a printer It receives data packets from the host PC as fast as possible This mode is used to evaluate the maximal Bulk Out transfer rate Loop back mode In this mode the PDIUSBD12 evaluation board receives data packets on Main Out endpoint and sends them back to the host PC on Main In endpoint This mode is used to test the data integrity of transfers The Buffer Size setting on the test applet is determined by the firmware and hardware ability of the evaluation board For PC kit the maximal size is limited to 64000 On USB EPP kit this is limited to 16384 The Repeat Times for loop back test controls the numbers of iterations of loop back which is useful for debugging 1 means it is infinite Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 9 of 14 PDIUSBD12 Evaluation Board PC Kit User s Manual REV 2 1 HARDWA
7. using a 25 wire cable So the device PC behaves as a big USB device Features evaluation of PDIUSBD12 firmware and product prototype development can be easily done with this setup without the resource limitation of a micro controller Customers can also connect the evaluation board to their own CPU and bus through the 25 wire cable for final product development The firmware is carefully developed for high rate data transmission and is written in C that supports Borland Turbo C for x86 and Keil C51 for 8031 currently Supporting to other CPU platforms will be available soon System Requirements PDIUSBD12 evaluation board and ISA bridging board 25 wire shielding data switch cable Host PC with USB motherboard or add on card Microsoft Windows 98 or Windows NT 5 0 Beta 2 Device PC running Microsoft DOS 6 x PDIUSBD12 evaluation diskette o 0i e on For firmware development 1 X86 CPU platform Borland Turbo C 3 0 or above 2 8031 Keil C51 4 0 or above PDIUSBD12 Evaluation Disk I aem USB Lo Eos 25 Wire Cable DEAE Ae YU Bee OC CT D CQ EC m n id L n Ma Device PC with PDIUSBD12 ISA Bridging Board PDIUSBD12 Evaluation Board Host PC with USB host Controller Philips Sem
8. 000 Start Buffer Size 64000 r Loopback Endpoint 2 zs Passed Failed Bytes Compared Start 2 Repeat Times Buffer Size e4000 PHILIPS The operation of each endpoint is designed according to its nature that is supported in PDIUSBD12 Generic in and generic out endpoints has max packet size of 16 bytes and supports I O access only So they are suitable for small size and low rate data transfer like keyboard and logic controls The main endpoints have max packet size of 64 bytes or 128 bytes with double buffering and DMA support So they are suitable for high data rate large size data transfer Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity PDIUSBD12 Evaluation Board PC Kit User s Manual Page 8 of 14 REV 2 1 See the table below for the description of endpoints operations on PDIUSBD12 evaluation board Endpoint Endpoint Operations Number Type 1 Generic This pipe is defined as Interrupt In pipe The PDIUSBD12 evaluation In board sends key press release data packet to the host when test keys are pressed or released The firmware uses l O accesses on this endpoint 1 Generic This pipe is defined as Interrupt Out pipe Data packet received from Out host is interpreted as LED control and the D12 evaluation board firmware will light up the corresponding LED The firmware uses I O accesses on this endpoint 2 Main In
9. DMA Number DMA1 DMA3 Jumper s Setting JP3 JP5 JP4 JP6 Default OFF OFF ON ON Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity PDIUSBD12 Evaluation Board PC Kit User s Manual Possible conflict table Page 6 of 14 IRQ or DMA Possible Conflict Number IRQ5 Creative SoundBlaster and compatible sound cards always occupy this IRQ by default If this kind of sound card is installed you should check its settings or remove it Some network cards may also use this IRQ IRQ7 Used by parallel port by default May cause printing problem on device PC DMA1 Creative SoundBlaster and compatible sound cards always occupy this DMA by default If this kind of sound card is installed you should check its settings or remove it DMA3 No conflict Location of key components on the PDIUSBD12 evaluation board D5 D4 D3 D2 0000 See the table below for the list of connectors Connector Descriptions J1 USB upstream connector J2 DB25 data bus connector J3 Extension board connector See the table below for the list of switch and LEDs Name Descriptions S1 S2 3 84 Test switches D1 GoodLink LED D2 D3 D4 D5 Test LEDs Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com REV 2 1 Interconnectivity Page 7 of 14
10. DUCTORS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 3 of 14 PDIUSBD12 Evaluation Board PC Kit User s Manual REV 2 1 TABLE OF CONTENTS DISCLAIMER 2 TABLE OF CONTENTS uuusxiiumiuidmE uisum Rater ak iSeries ou uray xn uid E duun EE ade 3 INSTALLATION OF PDIUSBD12 EVALUATION BOARD 4 Hingrniirerto M 4 System Requirements so sicscsscccnsscacicceccesaccedesecscssasasasseaccsascencasessceusasscecendesssasccesuvasocensesesscesesassssssaccsaasececenaaees 4 arie Et RR n 5 Jumper s setting on PDIUSBDI2 ISA bridging board sese nennen 5 Location of key components on the PDIUSBDI2 evaluation board sseseeeeeeeeeenne 6 Installation of firmware INF and driver cccccccccccccccscecesecccceceeesesecececssecusseeusseesseeuseseeececssseeeeesessseesceeseeeess 7 Using the Host Applet 7 HARDWARE DESCRIPTION sssssssnnsnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nna 9 Block Diagram ssosssdsssrsssososrdssosierdieesseods sansene saasa H 9 HISP niis 9 LOCO TITO CO C PE EEEE E EEE EEE ERRE 10 PAL Equations
11. PHILIPS Philips Semiconductors Interconnectivity 1 September 1998 PDIUSBD12 Evaluation Board PC Kit User s Manual Rev 2 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 2 of 14 PDIUSBD12 Evaluation Board PC Kit User s Manual Rev 2 1 This is a legal agreement between you either an individual or an entity and Philips Semiconductors By accepting this product you indicate your agreement to the disclaimer specified as follows DISCLAIMER PRODUCT IS DEEMED ACCEPTED BY RECIPIENT THE PRODUCT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW PHILIPS SEMICONDUCTORS FURTHER DISCLAIMS ALL WARRANTIES INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANT ABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS WITH THE RECIPIENT TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL INCIDENTAL DIRECT INDIRECT SPECIAL PUNITIVE OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF BUSINESS PROFITS BUSINESS INTERRUPTION LOSS OF BUSINESS INFORMATION OR OTHER PECUNIARY LOSS ARISING OUT OF THIS AGREEMENT OR THE USE OF OR INABILITY TO USE THE PRODUCT EVEN IF PHILIPS SEMICON
12. RE DESCRIPTION System Block Diagram of D12 Evaluation Kit Customer s System CPU Memory and DMA Controller 25 Pin Interface 1 VCC GND USB Host PC 2 D0 D7 3 ADDRESS ENABLE 4 IOW IOR IRQ RESET 5 DREQ DACK EOT D12 Evaluation Board USB Device PC Command and Address Decoder Test General Key L Input port USBD USB Host Controller Test General LED Output port Driver Bi direction JA em Transceiver USB Host Controller DIP Switches and Jumpers Block Diagram Above block diagram shows 5 main components on the PDIUSBD12 evaluation board Beside bus transceiver address command decoder and PDIUSBD12 a general input port and a general output port are included in the design These input and output ports are designed for test purposes such as test switches and test LEDs They also act as glue logic to adapt the PDIUSBD12 to the ISA bus For example ISA interrupt is edge triggered but PDIUSBD12 interrupt is level triggered The MSB of the general output port is used as interrupt enable to convert level triggered interrupt to edge triggered VO Mapping PDIUSBD12 evaluation board uses 8 I O addresses Offset Usage 0 D12 data register R W 1 D12 command register W only 2 General input port R only 3 General output port W only 4to7 Reserved for expansion board Phili
13. SE GE OW U4A 7asos x x X 74LS05 po 3th aH 3 4 Di 4 5 p 7 2 e We 73 s10 Q8 He 74LS05 13 D4 HED 5 6 E D5 Q5 x Ds 14 15 pe 17 0S e 16 13 12 pri o 7 9 Q 9 8 T U4F p CLK 74LS05 U4D CLR 74LSO 10 1 2 Us U4E 3 4 74HCT273 74LS05 p 5 6 AD EN C8 C9 C10 CH Ci2 vec Da l 3 JOW 10 01 01 04 04 01 lt D3 i 12 JOR ee 4 Title Do 14 ADDR2 D12 EVALUATION BOARD DL 15 16 ARDR1 dec Do 17 18 ADDRO T 10 TANT Size Document Number Rev Bs 20 Lee 1 1 es ee ee A DI2 EVAL 200 2 00 noo Date Thursday April 23 1998 Sheet 1 of 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 13 of 14 REV 2 1 PDIUSBD12 Evaluation Board PC Kit User s Manual Schematic for PDIUSBD12 ISA bridging board J2 JA VCC Dos GND VCC RESET EI M 1 2 ZERO WAIT E B2 A2 o 3 4 IROZ B3 A3 5 6 PX Qe ga A4 20K 7 8 SV B5 A5 9 10 ADEN DROZ Be AB RESET VCC 12V O anwnaon 11 12 Tow GET B7 A7 13 14 ZERO WAIT JOR B8 A8 15 16 412V gg A9 17 18 e m GND VO CH RDY pus Ut ADDR2 DACK 10K B10 A10 Sw DIP 8 n 5 MEMW AEN 1 DR B11 A11 0 G 21 22 MEMB
14. and is active high 13 O DATA2 14 IOW This command line instructs an I O device to read the data on the data bus It may be driven by the processor or the DMA controller This signal is active low 15 O DATA1 16 IOR This command line instructs an I O device to drive its data onto the data bus It may be driven by the processor or the DMA controller This signal is active low Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Page 11 of 14 Interconnectivity PDIUSBD12 Evaluation Board PC Kit User s Manual 17 1 0 DATAO 18 T C Terminal Count This line provides a pulse when terminal count for any DMA channel is reached This signal is active high 19 ADDR2 20 DACK This line is used to acknowledge DMA request and is active low 21 ADDR1 22 O DRQ This line is asynchronous channel request used by peripheral devices to gain DMA service A DMA request is generated by bringing DRQ line to an active high 23 ADDRO 24 O IRQ This line is raising edge triggered An interrupt request is generated by raising this line high and hold until it is acknowledged by the processor 25 POWER GND PAL Equations Address and command decoder Inputs Pin 1 ADDR2 Pin 2 ADDR1 Pin 3 ADDRO Pin 4 IOW Pin 5 IOR Pin 6 IDACK Pin 7 AD EN Pin 8 RESET Pin 9 2 INT N Pin 11 INT E Outputs Pin 12 2 IRQ
15. ec Ct C13 vBUs 5 vec RI Jp A7 TANT Y ra T 47 TG V BUS IK BUS POWERED ei ator LC 1 J2 E 470P Ceramic Ww T 4 7 TANT gt VBUS DB25 E Ut PDIUSBD12 GREEN 4 D R4 RS ERA Do 1 28 AppRo gt AU E 1 2 ATKATK Di 2 DATAO A0 57 R2 5 GND o pul C WI 3 4 DATA1 VOUT3 3 221 SHIELD 5 6 FX vec D2__3 DATA D 28 CLKOUT D3 4 L25 7 8 AD EN DATA3 DLE e UP_CONN 9 10 exer 1 Tope GND VG 53 maid Y 6MH7 R3 Ferrite Bead 11 12 DATA4 XTAL2 H JOW D5 7 20 XTALI C16 18 14 DR bee DATAS XTALI 51 221 eu 15 16 gt DATA6 GLN 59 1 cs T 01 17 18 ve D7 9 DATA7 RESETN 04 19 20 DACK 10 ALE EOTN 19 AZP R7 R8 R9 R10 21 22 DBQ CS D12 11 oS N DMACK N 8 DACK FT e 10K 10K 10K 10K vec RQ SUSPEND 12 CSJ CN 717 DRO 2P pea 23 24 T 13 SUSPEND DMREQ 4s JOW 25 i 4 CLKOUT WR N 15 1 Shell to GND T i INT N RD N 23 32309R OSC1 4 6 ols T vec 4 o0 o i 2 18 DO NV 3 B 17 Di Do 18 2 T wm 1 s2 A2 B2 1Y1 1A1 es 4 16 D2 Di 16 4 1 S 9 4 5 A3 83 4555 Dz 14 1Y2 1A2 Fe 3 5 A4 B4 42 pi Da i2 1 3 1A9 3 mise A5 B5 1Y4 1A4 o 7 13 D5 DA 9 11 V BUS 6 86 12 56 D 7 2Y 2A1 13 9 7 B7 11 p7 De 5 2Y2 2A2 15 I OSCl is optional rep A8 B8 p73 2 3 2A3 17 for Yl C5 and C6 1S8 c T 2Y4 2A4 1 1 R11 R12 2 R13 R14 RIS ae DIR 74LS245 1 ia ps 1K 470 470 Q 470 470 DIR 245 S US D2 D3 D4 D5 74HCT244 7 HE RED RED RED RED ADDR2 1 1M im
16. iconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity PDIUSBD12 Evaluation Board PC Kit User s Manual Installation Jumper s setting on PDIUSBD12 ISA bridging board Page 5 of 14 REV 2 1 The PDIUSBD12 ISA bridging board is plugged inside the device PC It will occupy I O IRQ and DMA resources of the device PC To avoid possible conflicts in settings we suggest removal of all the unnecessary cards from the device PC Sound card and network card may cause conflict in IRQ and DMA setting i JP1 JP2 JP5 JP6 M UB JP3 JP4 Switch S1 sets the base I O address for the D12 evaluation board Default base address is 0x368 The D12 evaluation board occupies 8 I O locations AO to A2 are decoded on the D12 evaluation board Switch S1 sets the address decoding of A3 to A9 Please notice that a switch ON is logic 0 SW n 1 2 3 4 5 6 7 8 Address X A3 A4 A5 A6 A7 A8 A9 Default OFF OFF ON OFF OFF ON OFF OFF Jumpers JP1 and JP2 set the IRQ number for the D12 evaluation board Default setting is IRQ5 or JP1 is shorted IRQ Number IRQ5 IRQ7 Jumper s Setting JP1 JP2 Default ON OFF Jumpers JP3 to JP6 set the DMA number for the D12 evaluation board Default setting is DMA3 or JP4 and JP6 are shorted Please note that a respective pair of jumpers is needed to set a particular DMA channel
17. ps Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Interconnectivity Page 10 of 14 PDIUSBD12 Evaluation Board PC Kit User s Manual REV 2 1 Bit description for general input port Bit Usage 0 Key S1 0 for pressed 1 Key S2 0 for pressed 2 Key S3 0 for pressed 3 Key S4 0 for pressed 4 5 6 7 D12 GoodLink pin state USB bus power state 1 for USB VBUS present D12 SUSPEND pin state D12 INT_N pin state Bit description for general output port Usage LED De 1 lights up LED LED D3 1 lights up LED LED D4 1 lights up LED LED D5 1 lights up LED Reserved Reserved Suspend control 1 forces D12 SUSPEND pin low Interrupt enable 1 enables interrupt Connectors 25 wire connector for PDIUSBD12 evaluation board Pin Type Description 1 POWER VCC 2 POWER GND 3 V O DATA7 4 O Zero Wait State 5 V O DATA6 6 1 0 Reserved 7 1 0 DATA5 8 O CLKOUT This line is connected to PDIUSBD12 CLKOUT pin 9 V O DATA4 10 AD_EN This line is the decoder output for address decoding A3 to A9 This signal is active low when PDIUSBD12 evaluation board I O address is selected 11 O DATA3 12 RESET This line is used to reset or initialize system logic upon power up
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