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bdiGDB User Manual

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1. ssssssseeneeeenne ne 16 2 7 TFTP server for WiNdOWS em te mm 16 e PSN n a E E E E E 17 3 1 Principle Of Oper tori iissa iad teed gee tenets eee ENSE KaR ESSEEN 17 3 2 eoe 18 321 Id eer 19 322 Part M ciu 22 9 2 9 Pam dn ed RN OE RE o reer ooo ERES 27 3 2 4 Parn ELASH e 29 32 5 Part REGS E EO Qo AERE 0 DoD 0 E 33 3 3 Debugging with GDB gone T 35 331 Target sl om 35 3 3 2 Connecting to the TANQEN i dcdeecdeinescicesanssccecensseentseresdetneisiactenieeldeneideussecneeidniendecetemtens 35 3 3 3 GDB monitor COMING RR 35 3 3 4 Target serial WO via BD iretur toe rnnt hnnc res auum ra aoa rina ba ea Comma ca 36 3 3 5 Embedded Linux MMU SUpDOLL uiuit arp pert neo Chr parnm rit res veau cs d ead beesi pde 37 STEP apicurc Taee c t 39 3 5 n Merge T 42 LE iD 45 5 Environmental nol GB sia accru tls En ERE DEAS EAEE SEE PEADUMASK EX E URURDIAMEASE SKIN NAE EERATUNNESK ER 46 6 Declaration of Conformity GE iioaaccu crine nti enne anat tonno tu cc utR onc cm aU po anc nap daa DERiRARRER RAN a MmEEdE 46 7 Warranty and Support Tenis m nnn 47 7 1 S eR T eter 47 T2 SOUWANS e HY 47 7 3 Warranty and Disclaimer co eins unio d etestuqu conn ci
2. i define the core ID the x without any holes no need that core ID matches the core number A valid example is 1 CPUTYPE P4080 5 0 LII Core 0 parameters active core after reset 0 CPUTYPE P4080 0 0 Core0 SOCO 0 STARTUP STOP 5000 let U boot setup the system 0 MEMACCESS CORE 0 CGROUP OxOf GDB continue core group resume Core l parameters 1 CPUTYPE P4080 1 0 Corel SOCO 1 STARTUP RUN xet core run 1 MEMACCESS CORE 1 CGROUP 0x02 GDB continue core group prepare Core 2 parameters 2 CPUTYPE P4080 2 0 Core2 SOCO 2 STARTUP RUN let core run 2 MEMACCESS CORE 2 CGROUP 0x04 GDB continue core group prepare Core 3 parameters 3 CPUTYPE P4080 3 0 Core3 SOCO 3 STARTUP RUN let core run 3 MEMACCESS CORE 3 CGROUP 0x08 GDB continue core group prepare HOST 0 PROMPT P4080 0 gt 1 PROMPT P4080 1 gt 2 PROMPT P4080 2 gt 3 PROMPT P4080 3 gt Note Be aware that via Telnet you select the core thread by its BDI core ID n This BDI core ID is not necessary the core thread number within the SOC Assuming there are two P4040 daisy chained you may use BDI core ID 4 to select core 0 in the second P4040 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 User Manual 43 Multi Core related Telne
3. Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 20 RMB8 address value RM16 address value RM32 address value RM64 address value TSZ1 start end TSZ2 start end TSZ4 start end TSZ8 start end MMAP start end EXEC n opcode data Read a byte 8bit from the selected memory place address the memory address Example RM8 0x00000000 Read a half word 16bit from the selected memory place address the memory address Example RM16 0x00000000 Read a word 32bit from the selected memory place address the memory address Example RM32 0x00000000 Read a double word 64bit from the selected memory place address the memory address Example RM64 0x00000000 Defines a memory range with 1 byte maximal transfer size Normally when the BDI reads or writes a memory block it tries to access the memory with a burst access The TSZx entry allows to define a maxi mal transfer size for up to 8 address ranges start the start address of the memory range end the end address of the memory range Example TSZ1 OxFF000000 OxFFFFFFFF PCI ROM space Defines a memory range with 2 byte maximal transfer size Defines a memory range with 4 byte maximal transfer size Defines a memory range with 8 byte maximal transfer size Because a memory access to an invalid memory space via JTAG can lead to a deadlock this entry can be used to define up to 32 valid memory rang es
4. TXD 4 DTR 5 GROUND 6 DSR 7 RTS 8 CTS 9 RI XXX BDI Output A EE Ethernet 10 BASE T The configuration parameter SIO is used to enable this serial I O routing The used framing parameters are 8 data 1 stop and not parity The BDI asserts RTS and DTR when a TCP connection is established BDI2000 TARGET SIO 7 9600 Enable SIO via TCP port 7 at 9600 baud Warning Once SIO is enabled connecting with the setup tool to update the firmware will fail In this case either disable SIO first or disconnect the BDI from the LAN while updating the firmware Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 37 3 3 5 Embedded Linux MMU Support The bdiGDB system supports Linux kernel debugging when MMU is on The MMU configuration pa rameter enables this mode of operation In this mode all addresses received from GDB are assumed to be virtual Before the BDI accesses memory it translates this address into a physical one based on information found in the TLB s or kernel user page table If PTBASE is not defined the BDI does TLB1 TLBO and if enabled default translation in this order In order to search the page tables the BDI needs to know the start addresses of the first level page table The configuration parameter PTBASE defines the physical address where the BDI looks for the virtual physic
5. There is no need for a target configuration file and no TFTP server is needed on the host e f not already done connect the BDI2000 system to the network Power up the BDI2000 Start a Telnet client on the host and connect to the BDI2000 the IP address you entered dur ing initial configuration e If everything is okay a sign on message like BDI Debugger for Embedded PowerPC and a list of the available commands should be displayed in the Telnet window 2 7 TFTP server for Windows The bdiGDB system uses TFTP to access the configuration file and to load the application program Because there is no TFTP server bundled with Windows Abatron provides a TFTP server application tftpsrv exe This WIN32 console application runs as normal user application not as a system ser vice Command line syntax tftpsrv p w dRootDirectory Without any parameter the server starts in read only mode This means only read access request from the client are granted This is the normal working mode The bdiGDB system needs only read access to the configuration and program files The parameter p enables protocol output to the console window Try it The parameter w enables write accesses to the host file system The parameter d allows to define a root directory tftpsrv p Starts the TFTP server and enables protocol output tftpsrv p w Starts the TFTP server enables protocol output and write accesses are allowed tftpsrv dcC
6. FORMAT ELF FORMAT ELF 0x10000 LOAD mode In Agent mode this parameters defines if the code is loaded automatically after every reset mode AUTO MANUAL Example LOAD MANUAL START address The address where to start the program file If this value is not defined and the core is not in ROM the address is taken from the image file If this val ue is not defined and the core is already in ROM the PC will not be set before starting the program file This means the program starts at the nor mal reset address OxFFFO00100 address the address where to start the program file Example START 0x1000 PROMPT string This entry defines a new Telnet prompt The current prompt can also be changed via the Telnet interface Example PROMPT P4080 0 gt DUMP filename The default file name used for the Telnet DUMP command filename the filename including the full path Example DUMP dump bin Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 28 TELNET mode By default the BDI sends echoes for the received characters and supports command history and line editing If it should not send echoes and let the Telnet client in line mode add this entry to the configuration file mode ECHO default NOECHO or LINE Example TELNET NOECHO use old line mode DEBUGPORT port RECONNECT The TCP port GDB uses to access the target If the RECONNECT param eter is present an open TCP IP connecti
7. UNLOCK lt addr gt delay addr This is the address of the sector block to unlock delay A delay time in milliseconds the BDI waits after sending the unlock com mand to the flash For example clearing all lock bits of an Intel J3 Strata flash takes up to 0 7 seconds If unlock is used without any parameter all sectors in the erase list with the UNLOCK option are processed To clear all lock bits of an Intel J3 Strata flash use for example BDI unlock OxFF000000 1000 For MIRRORX16 and S29GLSX16 the unlock command erases the PPB bits Use this command only for Spansion devices where Persistent Protection Bits PPB are implemented To erase or unlock multiple continuous flash sectors blocks of the same size the following Telnet commands can be used ERASE lt addr gt lt step gt lt count gt UNLOCK lt addr gt lt step gt lt count gt addr This is the address of the first sector to erase or unlock step This value is added to the last used address in order to get to the next sec tor In other words this is the size of one sector in bytes count The number of sectors to erase or unlock The following example unlocks all 256 sectors of an Intel Strata flash 28F256K3 that is mapped to 0x00000000 In case there are two flash chips to get a 32bit system double the step parameter BDI unlock 0x00000000 0x20000 256 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 Qorl
8. tftp Starts the TFTP server and allows only access to files in C tftp and its subdirectories As file name use relative names For example bdi mpc750 cfg accesses C tftp bdi mpc750 cfg You may enter the TFTP server into the Startup group so the server is started every time you login Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 17 3 Using bdiGDB 3 1 Principle of operation The firmware within the BDI handles the GDB request and accesses the target memory or registers via the JTAG interface There is no need for any debug software on the target system After loading the code via TFTP debugging can begin at the very first assembler statement Whenever the BDI system is powered up the following sequence starts initial configuration valid no activate BDI2000 loader Get configuration file via TFTP or from Flash Reset System and Power OFF Process target init list Process GDB requests Process Telnet commands Power OFF Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 18 3 2 Configuration File The configuration file is automatically read by the BDI after every power on The syntax of this file is as follows comment part name identifier parameterl parameter2 parameterN comment identifier paramet
9. AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 13 4 Transmit the initial configuration parameters With bdisetup c the configuration parameters are written to the flash memory within the BDI The following parameters are used to configure the BDI BDI IP Address The IP address for the BDI2000 Ask your network administrator for as signing an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Subnet Mask The subnet mask of the network where the BDI is connected to A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask If the BDI and the host are in the same subnet it is not necessary to enter a subnet mask Default Gateway Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Config Host IP Address Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI after every start up via TFTP If the host IP is 255 255 255 255 then the setup tool stores the configura tion read from the file into the BDI internal flash memory In this case no TFTP server is necessary Configuration file Enter the full path and name of the configuration file This file is read by the setup tool or via TFTP Keep in mi
10. If at least one memory range is defined the BDI checks against this range s and avoids accessing of not mapped memory ranges start the start address of a valid memory range end the end address of this memory range Example MMAP OxFFEO00000 OxFFFFFFFF Boot ROM This entry causes the processor to execute one instruction If a load in struction should get the data from the JTAG port instead from normal memory the optional n and data parameters are used n 0 load data from normal memory 1 load 8 16 32 bit data from JTAG port 2 load 64 bit data from JTAG port opcode the opcode of the PowerPC instruction data the data to present to the instruction Example EXEC 0_0x3c60aba4 load GPR 3 via lui EXEC 1 0x80c00000 1234 load GPR 6 via Iwz EXEC 2 0xc8c00000 0 clear FPR 6 via Idf Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 User Manual 21 WTLB mas1_mas2 mas0 mas7_mas3 Adds an entry to the TLBO or TLB1 array The two 64 bit values of an init list entry are used to define MASO upper 16 bits MAS1 MAS2 MAS3 and MAS7 lower 16 bits before a tlowe instruction is executed If other MASx registers need a special value use the WSPR init list entry A TLB entry can also be addd via a Telnet command enter WTLB at the Telnet for a description mas1 mas2 mas3 masO mas7 Some examples how to write TLB entries Setup WTLB WTLB WTLB WTLB TLB1
11. MAS1 MAS2 0x80000700_0xfe00000a 0x80000900_0xe000000a 0x80000a00_0x00000000 0x80000a00_0x40000000 0x80000500_0x80000000 TLBO MAS1 MAS2 0x80000100_0xc0000000 0x80000100_0xc0001000 0x80000100_0xc0002000 0x80000100_0xc0003000 MASO MAS7 MAS3 0x10010000 0xfe00003f 0x10020000 0xe000003 0x10030000 0x0000003 f 0x10040000_0x4000003 0x10050000_0x8000003f MASO MAS7 MAS3 0x00000000 0x0000003 f 0x00000000 0x0000103f 0x00000000_0x0000203f 0x00000000_0x0000303f sals 1 2 ELG 71 4 145 WAYO WAYO WAYO WAYO value to load into MAS1 value to load into MAS2 only lower 32 bits value to load into MASS value to load into upper 16 bits of MASO value to load into lower 16 bits of MAS7 fe000000 gt 0_fe000000 e 0000000 gt 0_e0000000 25 00000000 gt 0_00000000 40000000 gt 0_40000000 80000000 gt 0_80000000 c0000000 gt 0_00000000 c0001000 gt 0_00001000 c0002000 gt 0_00002000 c0003000 gt 0_00003000 6M 1G 1G 1M Bob aS am 16MB I G RWXRWX B I G RWXRWX Bo RWXRWX B SSsS RWXRWX E RWXRWX e RWXRWX KB s RWXRWX Bassas RWXRWX Be 2 RWXRWX In order to set the upper 32 bits of MAS2 in 64 bit mode write directly to MAS2 WREG WTLB MAS2 0x80000700 0xff00000a 0x00000064_0x00000000 0x10060000 0xff00003f Set MAS2 upper word sisi 64_ff000000 gt 0_ff000000 MAS2 is a predefined register name but WSPR will also work WSPR WTLB 626 0x80000700_0x
12. count gt calculates a checksum over a memory range MV verifies the last calculated checksum RD lt name gt display general purpose or user defined register RDUMP lt file gt dump all user defined register to a file RDFPR display floating point registers RDVR display vector registers RDSPR lt number gt display special purpose register RDPMR lt number gt display performance monitor register R lt nbr gt lt name gt value modify general purpose or user defined register RMSPR number value modify special purpose register RMPMR number value modify performance monitor register RMVR nbr val val val val modify vector register four 32bit values RDCSR lt addr gt lt count gt display register s in DCSR space Run Control WDCSR lt addr gt lt value gt write to a register in DCSR space Run Control DCACHE lt addr set gt display L1 data cache content ICACHE addr set display L1 inst cache content L2CACHE set lt bank gt XOR display L2 cache content TLBO from lt to gt display L2 TLBO entry TLB1 from lt to gt display L2 TLB1 entry WTLBO way lt epn gt lt rpn gt write to a L2 TLBO entry WTLB1 idx lt epn gt lt rpn gt write to a L2 TLB1 entry EXEC inst lt r0 gt r1 execute an instruction RESET HAL RUN time reset the target system change startup mode BREAK SOF HARD display or se
13. it pro cesses the next entry ERASE Oxff040000 erase sector 4 of flash ERASE Oxff060000 erase sector 6 of flash ERASE Oxff000000 CHIP erase whole chip s ERASE Oxff010000 UNLOCK 100 unlock wait 100ms ERASE Oxff000000 0x10000 7 erase 7 sectors The size of one flash chip in bytes e g AM29F010 0x20000 The width of the flash memory bus in bits 8 16 32 64 workspace in dual port RAM erase sector 4 erase sector 5 erase sector 6 erase sector 7 the above erase list maybe replaces with ERASE OxFF900000 E gnu demo ads8260 bootrom hex The file to program of flash SIMM LH28F016SCT of flash SIMM of flash SIMM of flash SIMM 0x40000 4 erase sector 4 to 7 of flash SIMM Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 31 Supported standard parallel NOR Flash Memories There are different flash algorithm supported Almost all currently available parallel NOR flash mem ories can be programmed with one of these algorithm The flash type selects the appropriate algo rithm and gives additional information about the used flash On our web site www abatron ch gt Debugger Support gt GNU Support gt Flash Support there is a PDF document available that shows the supported parallel NOR flash memories Some newer Spansion MirrorBit flashes cannot be programmed with the MIRRORX16 algorithm be cause of the used unlock a
14. other information Also some basic debug commands can be executed Telnet Debug features Display and modify memory locations e Display and modify general and special purpose registers e Single step a code sequence e Set hardware breakpoints Load a code file from any host e Start Stop program execution Programming and Erasing Flash memory During debugging with GDB the Telnet is mainly used to reboot the target generate a hardware re set and reload the application code It may be also useful during the first installation of the bdiGDB system or in case of special debug needs Example of a Telnet session P4080 0 gt info Target CPU P4080 Core 0 Core state halted Debug entry cause device event Current PC Oxfffffffc Current CR 0x00000000 Current MSR 0x00000000 Current LR 0x00000000 Current CCSRBAR OxO fe000000 P4080 0 gt rd GPR00 cllbc002 06278553 80028188 aba40000 GPR04 609db195 ad1944b2 deadbeef 002883a6 GPR08 20119520 2032dc90 94110404 29038003 GPR12 9422cf8e 0c105000 61350050 4e0d4548 GPR16 0f15d163 3820d4a3 806b42d8 4c005402 GPR20 50010949 846310d8 c0d53502 4c41d854 GPR24 c0602409 4443cd98 a8911575 e0021810 GPR28 200842c0 c890cc15 2c2390ce 604bc0c1 CR 00000000 MSR 00000000 P4080 0 gt md 0 0 00000000 deadbeef deadbeef deadbeef deadb 0_00000010 deadbeef deadbeef deadbeef deadb 0 00000020 deadbeef deadbeef deadbeef deadb 0 00000030 deadbeef deadbee
15. running out of reset This allows to setup the Cross Trigger logic also in this case Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 45 4 Specifications Operating Voltage Limiting Power Supply Current RS232 Interface Baud Rates Data Bits Parity Bits Stop Bits Network Interface Serial Transfer Rate between BDI and Target Supported target voltage Operating Temperature Storage Temperature Relative Humidity noncondensing Size Weight without cables Host Cable length RS232 5 VDC 0 25 V typ 500 mA max 1000 mA 9 600 19 200 38 400 57 600 115 200 8 none 1 10 BASE T up to 16 Mbit s 1 8 5 0 V 3 0 5 0 V with Rev B 5 C 60 C 20 C 65 C 90 rF 190 x 110 x 35 mm 420g 2 5m Specifications subject to change without notice Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 46 5 Environmental notice Disposal of the equipment must be carried out at a designated disposal site 6 Declaration of Conformity CE CC DECLARATION OF CONFORMITY This declaration is valid for following product Type of device BDM JTAG Interface Product name BDI2000 The signing authorities state that the above mentioned equipment meets the requirements for emission and immunity according to EMC Directive 89 336 EEC The evaluation p
16. selected cores as bitmap 0 CGROUP OxOf GDB continue core group restart 1 CGROUP 0x02 GDB continue core group prepare Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 26 Daisy chained JTAG devices The BDI can also handle systems with multiple devices connected to the JTAG scan chain In order to put the other devices into BYPASS mode and to count for the additional bypass registers the BDI needs some information about the scan chain layout Enter the number count and total instruction register irlen length of the devices present before the PowerPC chip Predecessor Enter the ap propriate information also for the devices following the PowerPC chip Successor SCANPRED countirlen This value gives the BDI information about JTAG devices present before the PowerPC chip in the JTAG scan chain count The number of preceding devices irlen The sum of the length of all preceding instruction regis ters IR Example SCANPRED 1 8 one device with an IR length of 8 SCANSUCC count irlen This value gives the BDI information about JTAG devices present after the PowerPC chip in the JTAG scan chain count The number of succeeding devices irlen The sum of the length of all succeeding instruction reg isters IR Example SCANSUCC 2 12 two device with an IR length of 8 4 Overriding Reset Configuration Word RCW The BDI supports overriding the RCW Source and a
17. the print Check that the LEDs align with the holes in the back panel 5 2 Push carefully the front panel and the red elastig sealing on the casing Check that the LEDs align with the holes in the front panel and that the position of the sealing is as shown in the figure below casing N elastic sealing back panel front panel 5 3 Mount the screws do not overtighten it 5 4 Mount the two plastic caps that cover the screws 5 5 Plug the cables A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 51 C Trademarks All trademarks are property of their respective holders Copyright 1997 2014 by ABATRON AG Switzerland V 1 08
18. this simple enter 0 0 0 0 as the BDI s IP address see following chapters If present the subnet mask and the default gateway router is taken from the BOOTP vendor specific field as defined in RFC 1533 With the Linux setup tool simply use the default parameters for the c option root LINUX_1 bdisetup bdisetup c p dev ttySO0 b57 The MAC address is derived from the serial number as follows MAC 00 0C 01 xx xx xx replace the xx xx xx with the 6 left digits of the serial number Example SN 93123457 gt gt 00 0C 01 93 12 34 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 12 2 5 1 Configuration with a Linux Unix host The firmware logic update and the initial configuration of the BDI2000 is done with a command line utility In the ZIP Archive bdisetup zip are all sources to build this utility More information about this utility can be found at the top in the bdisetup c source file There is also a make file included Starting the tool without any parameter displays information about the syntax and parameters A To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 Following the steps to bring up a new BDI2000 1 Build the setup tool The setup tool is delivered only as source files This allows to build the tool on any Linux Unix host T
19. up 16 GROUND For BDI TARGET B connector signals see table on next page Note For critical designs long traces on the target board there is a shorter target cable available p n 90020 S This may improve JTAG communication reliability But best is to keep the JTAG traces on the board as short as possible Warning Before you can use the BDI2000 with an other target processor type e g PPC lt gt ARM a new setup has to be done see chapter 2 5 During this process the target cable must be disconnected from the target system To avoid conflicts between data lines the BDI2000 must be disconnected from the target sys tem while programming a new firmware for an other target CPU Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 User Manual 6 BDI TARGET B Connector Signals JTAG Test Data Out This input to the BDI2000 connects to the target TDO pin 102 General purpose I O Currently not used TDI JTAG Test Data In This output of the BDI2000 connects to the target TDI pin TRST JTAG Test Reset This output of the BDI2000 resets the JTAG TAP controller on the target INO General purpose Input Currently not used Pin ae ps EE ES di 13 14 Copyright 1997 2014 by ABATRON AG Switzerland Vcc Target 1 8 5 0V This is the target reference voltage It indicates that the target has power and it is also used to create the logic level refe
20. 0 is defined then all cores within an SOC will be halted immediatelly out of reset STOP In this mode the BDI lets the target execute code for runtime milliseconds after reset This mode is useful when monitor code should initialize the target system RUN After reset the target executes code until stopped by the Telnet halt command Example STARTUP STOP 3000 let the CPU run for 3 seconds BREAKMODE mode This parameter defines how breakpoints are implemented The current mode can also be changed via the Telnet interface SOFT This is the normal mode Breakpoints are implemented by replacing code with a DNH instruction HARD In this mode the target breakpoint hardware is used Only 2 breakpoints at a time is supported LOOP In this mode breakpoints are implemented by replacing code with an endless loop 0x48000000 Maybe useful for special debug tasks The processor does not auto matically enter debug mode it has to be halted manually via Telnet or GDB Example BREAKMODE HARD STEPMODE mode This parameter defines how single step instruction step is implemented The alternate step mode HWBP may be useful when stepping instruc tions that causes a TLB miss exception In case BREAKMODE LOOP is selected this parameter is ignored and single step is implemented by replacing the code of the next instruction s with an endless loop 0x48000000 ICMP This is the mode single step is implemented via the in struction complete
21. ICMP debug event HWBP In this mode a hardware breakpoint on the next instruc tion is used to implement single stepping Example STEPMODE HWBP Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 24 MMU XLAT kb PTBASE addr 64BIT SIO port baudrate In order to support Linux kernel debugging when MMU is on the BDI translates effective virtual to physical addresses This translation is done based on the current MMU configuration page tables If this configuration line is present the BDI translates the addresses received from GDB be fore it accesses physical memory The optional parameter defines the ker nel virtual base address default is 0xC0000000 and is used for default address translation For more information see also chapter Embedded Linux MMU Support Addresses entered at the Telnet are never translat ed Translation can be probed with the Telnet command PHYS If not zero the 12 lower bits of kb defines the position of the page present bit in a page table entry By default 0x800 is assumed for the page present bit The position may depend on the Linux kernel version A kb value of OXFFFFFFFF disables the default translation kb The kernel virtual base address KERNELBASE Example MMU XLAT enable address translation MMU XLAT 0xC0000800 page present bit is 0x800 This parameter defines the physical memory address where the BDI looks for
22. In this case no TFTP server is necessary Enter the full path and name of the configuration file This file is read by the setup tool or via TFTP Click on this button to store the configuration in the BDI2000 flash memory 2 5 3 Recover procedure In rare instances you may not be able to load the firmware in spite of a correctly connected BDI error of the previous firmware in the flash memory Before carrying out the following procedure check the possibilities in Appendix Troubleshooting In case you do not have any success with the tips there do the following Switch OFF the power supply for the BDI and open the unit as described in Appendix Maintenance Place the jumper in the INIT MODE position Connect the power cable or target cable if the BDI is powered from target system Y e Switch ON the power supply for the BDI again and wait untilthe c LED MODE blinks fast i o E INIT MODE Wi Turn the power supply OFF again EN DEFAULT Return the jumper to the DEFAULT position Reassemble the unit as described in Appendix Maintenance Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 16 2 6 Testing the BDI2000 to host connection After the initial setup is done you can test the communication between the host and the BDI2000
23. Q P3 P4 P5 T1 T2 TA User Manual 33 3 2 5 Part REGS In order to make it easier to access target registers via the Telnet interface the BDI can read ina register definition file In this file the user defines a name for the register and how the BDI should access it e g as memory mapped memory mapped with offset The name of the register defi nition file and information for different registers type has to be defined in the configuration file The register name type address offset number and size are defined in a separate register definition file An entry in the register definition file has the following syntax name type addr size SWAP name The name of the register max 15 characters type The register type GPR General purpose register SPR Special purpose register PMR Performance monitor register CCSR Relative to CCSRBAR memory mapped register DCSR Memory mapped register in DCSR space MM Absolute direct memory mapped register DMM1 DMM4_ Relative direct memory mapped register IMM1 IMM4 Indirect memory mapped register addr The address offset or number of the register size The size 8 16 32 of the register default is 32 SWAP If present the bytes of a 16bit or 32bit register are swapped This is useful to access little endian ordered registers e g PCI bridge configuration reg isters The following entries are supported in the REGS part of the configuration file FILE filename The name of the regi
24. YPE P4080 1 0 Corel SOCO 1 STARTUP HALT halt at the reset vector r HOST IP 151 120 25 112 FILE E temp dump1024k bin FORMAT BIN 0x10000 F 0 PROMPT P4080 0 gt 1 PROMPT P4080 1 gt Fr FLASH only to test execution of target code WORKSPACE 0x80001000 workspace in CPC1 SRAM CHIPTYPE AM2 9BX16 Flash type CHIPSIZE 0x00200000 The size of one flash chip in bytes BUSWIDTH 16 The width of the flash memory bus in bits FILE E temp dump16k bin FORMAT BIN 0x00300000 REGS FILE SregP4080 def Based on the information in the configuration file the target is automatically initialized after every re set Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 5 2 Installation 2 1 Connecting the BDI2000 to Target The cable to the target system is a 16 pin flat ribbon cable In case where the target system has an appropriate connector the cable can be directly connected The pin assignment is in accordance with the COP connector specification In order to ensure reliable operation of the BDI EMC runtimes etc the target cable length must not exceed 20 cm 8 Target System 1 15 gt n meeten tale lt COP JTAG Connector 7 1 TDO 2 16 3 TDI 4 TRST 6 Vcc Target 7 TCK 9 TMS 11 SRESET 12 GROUND 13 HRESET The green LED TRGT marked light up when target is powered
25. al 11 2 5 Initial configuration of the bdiGDB system On the enclosed CD you will find the BDI configuration software and the firmware logic required for the BDI2000 For Windows users there is also a TFTP server included The following files are on the CD b20qp4gd exe Configuration program b20qp4gd xxx Firmware for the BDI2000 copjed20 xxx JEDEC file for the BDI2000 Rev B logic device when working with a COP target copjed21 xxx JEDEC file for the BDI2000 Rev C logic device when working with a COP target tftpsrv exe TFTP server for Windows WIN32 console application cfg Configuration files def Register definition files bdisetup zip ZIP Archive with the Setup Tool sources for Linux UNIX hosts Overview of an installation configuration process Create a new directory on your hard disk Copy the entire contents of the enclosed CD into this directory Linux only extract the setup tool sources and build the setup tool Use the setup tool to load update the BDI firmware logic Note A new BDI has no firmware logic loaded Use the setup tool to transmit the initial configuration parameters IP address of the BDI IP address of the host with the configuration file Name of the configuration file This file is accessed via TFTP Optional network parameters subnet mask default gateway Activating BOOTP The BDI can get the network configuration and the name of the configuration file also via BOOTP For
26. al address of an array with two virtual physical addresses of first level page tables The first one points normally to the kernel page table the second one can point to the current user page table As long as the base pointer or the first entry is zero the BDI does only L2 CAM L2 TLB1 and default translation Default translation maps a 256 Mbyte range starting at KERNELBASE to 0x00000000 The second page table is only searched if its address is not zero and there was no match in the first one The pointer structure is as follows PTBASE physical address gt PTE pointer pointer virtual or physical address gt PTE kernel pointer virtual or physical address PTE user pointer virtual or physical address The pointers are assumed virtual if they are gt KERNELBASE In that case default translation is ap plied to get the physical address Newer versions of arch ppc kernel head S support the automatic update of the BDI page table in formation structure Search head S for abatron and you will find the BDI specific extensions Extract from the configuration file INIT WM32 0x000000f0 0x00000000 invalidate page table bas TARGET MMU XLAT translate effective to physical address PTBASE 0x000000f0 here is the pointer to the page table pointers Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 38 To debug the Linux kern
27. ash sectors FLASH lt type gt lt size gt lt bus gt change flash configuration DELAY lt ms gt delay for a number of milliseconds MEMACC CORE SAP lt attr gt select memory access mode normally SAP SELECT lt core gt change the current core HOST lt ip gt change IP address of program file host PROMPT lt string gt defines a new prompt string QUERY lt core gt display target configuration CONFIG display or update BDI configuration CONFIG lt file gt lt hostIP gt lt bdiIP gt lt gateway gt lt mask gt UPDATE reload the configuration without a reboot HELP display command list JTAG switch to JTAG command mode BOOT loader reboot the BDI and reload the configuration QUIT terminate the Telnet session There are two memory access modes implemented The default is via System Access Port SAP Via SAP physical addresses are used and the access does not make use of any of the cores SAP accesses memory like an additional bus master If memory access CORE is selected the current core executes load store instructions in its current context In this mode MMU translation takes place unless the use of real addresses is forced For memory accesses via core the lt attr gt parameter in the Telnet MEMACC command has the fol lowing meaning default is 0 R 1 Real Addressing Mode no MMU translation WIMGE Page attributes for load
28. ble A For error free operation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics POWER Connector GND 3 1 Vcc 1 Vcc 5V 3 GROUND The green LED BDI marked light up when 5V power is connected to the BDI2000 Please switch on the system in the following sequence 1 gt external power supply e 2 gt target system Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 o bd for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 8 2 3 Status LED MODE The built in LED indicates the following BDI states MODE LED BDI STATES The BDI is ready for use the firmware is already loaded The power supply for the BDI2000 is lt 4 75VDC BLINK The BDI loader mode is active an invalid firmware is loaded or loading firmware is active Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 o bd for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 9 2 4 Connecting the BDI2000 to Host 2 4 1 Serial line communication Serial line communication is only used for the initial configuration of the bdiGDB system The host is connected to the BDI through the serial interface COM1 COM4 The communication cable included between BDI and Host is a serial cable There is the same connector pinout for the BDI and for the Host side Refe
29. cement for defective storage mediums Update and Support The agreement includes free software maintenance update and support for one year from date of purchase After this period the client may purchase software maintenance for an additional year 7 3 Warranty and Disclaimer ABATRON AND ITS SUPPLIERS HEREBY DISCLAIMS AND EXCLUDES TO THE EXTENT PERMITTED BY APPLICABLE LAW ALL WARRANTIES EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION ANY WARRANTIES OF MERCHANTABILITY FITNESS FORA PARTICULAR PURPOSE TITLE AND NON INFRINGEMENT 7 4 Limitation of Liability IN NO EVENT SHALL ABATRON OR ITS SUPPLIERS BE LIABLE TO YOU FOR ANY DAMAGES INCLUDING WITHOUT LIMITATION ANY SPECIAL INDIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE HARDWARE AND OR SOFTWARE INCLUDING WITHOUT LIMITATION LOSS OF PROFITS BUSINESS DATA GOODWILL OR ANTICIPATED SAVINGS EVEN IF ADVISED OF THE POSSIBILITY OF THOSE DAMAGES The hardware and software product with all its parts copyrights and any other rights remain in pos session of ABATRON Any dispute which may arise in connection with the present agreement shall be submitted to Swiss Law in the Court of Zug to which both parties hereby assign competence Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 48 Appendices A Troubleshooting Problem The firmware can not be load
30. d a 10Base T Ethernet connector The firmware and the programmable logic of the BDI2000 can be updated by the user with a simple Windows based con figuration program The BDI2000 supports 1 8 5 0 Volts target systems 3 0 5 0 Volts target sys tems with Rev B Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 4 1 2 BDI Configuration As an initial setup the IP address of the BDI2000 the IP address of the host with the configuration file and the name of the configuration file is stored within the flash of the BDI2000 Every time the BDI2000 is powered on it reads the configuration file via TFTP Following parts of an example of a typical configuration file bdiGDB configuration file for P4080 DS INIT Initialize LAWBAR s WM32 Oxfe000c00 0x00000000 LAWBARO Flash 80 e0000000 WM32 Oxfe000c04 0xe0000000 WM32 Oxfe000c08 0x81f0001b LAWARO eLBC 256MB Release cores for booting WM32 OxfeOEO00EA 0x00000003 BRR release core 0 and 1 r i TARGET common parameters POWERUP 5000 start delay after power up detected in ms JTAGCLOCK 1 use 8 MHz JTAG clock WAKEUP 1000 give reset time to complete d CoreID 0 parameters active vCPU after reset 0 CPUTYPE P4080 0 0 Core0 SOCO O0 STARTUP HALT halt at the reset vector this halts all cores i CoreID 1 parameters 1 CPUT
31. ddress offset Use S29M32X16 for these flashes The AMD and AT49 algorithm are almost the same The only difference is that the AT49 algorithm does not check for the AMD status bit 5 Exceeded Timing Limits Only the AMD and AT49 algorithm support chip erase Block erase is only supported with the AT49 algorithm If the algorithm does not support the selected mode sector erase is performed If the chip does not support the selected mode erasing will fail The erase command sequence is different only in the 6th write cycle Depending on the selected mode the following data is written in this cycle see also flash data sheets Ox10 for chip erase 0x30 for sector erase 0x50 for block erase To speed up programming of Intel Strata Flash and AMD MirrorBit Flash an additional algorithm is implemented that makes use of the write buffer The Strata algorithm needs a workspace otherwise the standard Intel algorithm is used Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 32 Note Some Intel flash chips e g 28F800C3 28F160C3 28F320C3 power up with all blocks in locked state In order to erase program those flash chips use the init list to unlock the appropriate blocks WM16 OxFFF00000 0x0060 unlock block 0 WM16 OxFFF00000 0x00DO WM16 OxFFF10000 0x0060 unlock block 1 WM16 OxFFF10000 0x00D0 WM16 OxFFF00000 OxFFFF select read mod or use the Telnet unlock command
32. ed This button is only active if there is a newer firmware or logic version pres ent in the execution directory of the bdiGDB setup software Press this but ton to write the new firmware and or logic into the BDI2000 flash memory programmable logic Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 o bd for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 15 BDI IP Address Subnet Mask Default Gateway Config Host IP Address Configuration file Transmit Enter the IP address for the BDI2000 Use the following format XXX XXX XXX xXxx e g 151 120 25 101 Ask your network administrator for assigning an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Enter the subnet mask of the network where the BDI is connected to Use the following format xxx Xxx xxx xxxe g 255 255 255 0 A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI after every start up via TFTP If the host IP is 255 255 255 255 then the setup tool stores the configura tion read from the file into the BDI internal flash memory
33. ed Possible reasons The BDI is not correctly connected with the target system see chapter 2 The power supply of the target system is switched off or not in operating range 4 75 VDC 5 25 VDC MODE LED is OFF or RED The built in fuse is damaged gt MODE LED is OFF The BDI is not correctly connected with the Host see chapter 2 A wrong communication port Com 1 Com 4 is selected Problem No working with the target system loading firmware is ok Possible reasons Wrong pin assignment BDM JTAG connector of the target system see chapter 2 Target system initialization is not correctly gt enter an appropriate target initialization list An incorrect IP address was entered BDI2000 configuration e BDM JTAG signals from the target system are not correctly short circuit break The target system is damaged Problem Network processes do not function loading the firmware was successful Possible reasons The BDI2000 is not connected or not correctly connected to the network LAN cable or media converter An incorrect IP address was entered BDI2000 configuration Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 49 B Maintenance The BDI needs no special maintenance Clean the housing with a mild detergent only Solvents such as gasoline may damage it If the BDI is connected correctly and it is still not respond
34. el when MMU is enabled you may use the following load and startup se quence Load the compressed linux image e Set a hardware breakpoint with the Telnet at a point where MMU is enabled For example at start_kernel BDI gt BI 0xC0061550 e Start the code with GO at the Telnet The Linux kernel is decompressed and started The system should stop at the hardware breakpoint e g at start kernel Disable the hardware breakpoint with the Telnet command CI f not automatically done by the kernel setup the page table pointers for the BDI e Start GDB with vmlinux as parameter Attach to the target Now you should be able to debug the Linux kernel To setup the BDI page table information structure manually set a hardware breakpoint at start kernel and use the Telnet to write the address of swapper pg dir to the appropriate place BDI bi 0xc0061550 BDI gt go BDI ci BDI mm OxfO0 0xc00000f8 BDI mm Oxf8 0xc0057000 BDI mm Oxfc 0x00000000 set breakpoint at start kernel target stops at start kernel Let PTBASE point to an array of two pointers write address of swapper pg dir to first pointer clear second user pointer Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 3 4 Telnet Interface A Telnet server is integrated within the BDI The Telnet channel is used by the BDI to output error messages and
35. er Example WSPR 27 0x00001002 SRR1 MERI WREG name value Write value to the selected register memory by name name the case sensitive register name from the reg def file value the value to write to the register memory Example WREG pc 0x00001000 WDCSR address value Write value to the selected register in DCSR space address address offset in DCSR space value the value to write into the register Example WDCSR 0x2220c 0x0000000e CGCR1 Core Group 1 DELAY value Delay for the selected time A delay may be necessary to let the clock PLL lock again after a new clock rate is selected value the delay time in milliseconds 1 30000 Example DELAY 500 delay for 0 5 seconds WM68 address value Write a byte 8bit to the selected memory place address the memory address value the value to write to the target memory Example WM8 OxFFFFFA21 0x04 SYPCR watchdog disable WM16 address value Write a half word 16bit to the selected memory place address the memory address value the value to write to the target memory Example WM16 0x02200200 0x0002 TBSCR WM32 address value Write a word 32bit to the selected memory place address the memory address value the value to write to the target memory Example WM32 0x02200000 0x01632440 SIUMCR WM64 address value Write a double word 64bit to the selected memory place address the memory address value the value to write to the target memory Example WM64 OxFFF00000 0x123456789abcdefO
36. erl parameter2 parameterN part name identifier parameterl parameter2 parameterN identifier parameterl parameter2 parameterN etc Numeric parameters can be entered as decimal e g 700 or as hexadecimal 0x80000 Note about how to enter 64bit values The syntax for 64 bit parameters is high word low word Hex values may also be entered as Oxnnnnnnnnnnnnnnnn The high word optional and low word can be entered as decimal or hexadecimal They are han dled as two separate values concatenated with an underscore Examples 0x0123456789abcdef gt gt 0x0123456789abcdef 0x01234567_0x89abcdef gt gt 0x0123456789abcdef 10 gt gt 0x0000000100000000 256 gt gt 0x0000000000000100 3 0x1234 gt gt 0x0000000300001234 0x80000000_0 gt gt 0x8000000000000000 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 19 3 2 1 Part INIT The part INIT defines a list of commands which should be executed every time the target comes out of reset The commands are used to get the target ready for loading the program file WGPR register value Write value to the selected general purpose register register the register number 0 31 value the value to write into the register Example WGPR 0 5 WSPR register value Write value to the selected special purpose register register the register number value the value to write into the regist
37. es maybe snooped default or not snooped CORE Memory access via current core The optional attr pa rameter is explained in the Telnet chapter Example MEMACCES CORE access via core MEMACCES SAP 100 access via SAP 100us delay Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 25 REGLIST list SDCRESP response CGROUP cores This parameter defines the transferred GDB registers packet By default STD and FPR are read and transferred in 32 bit mode The following names are use to select a register group and register size STD FPR 64BIT Example The standard register block The FP registers are not read from the target Placeholders are transferred The floating point registers are read and transferred The register packet is sent as expected by GDB for a 64 bit PowerPC target REGLIST STD standard registers in 32 bit mode REGLIST STD FPR 64BIT use 64 bit mode If this parameter is present the BDI tries to open JTAG debugging via the challenge response operation of the secure debug controller SDC response Example The 64 bit response value the BDI writes to the Secure Debug Response register in order to allow JTAG debug ging SDCRESP 0x01aa00bbcafeca77 This parameter gives the BDI information about how to restart multiple cores at the same time in response to a GDB continue command See chapter Multi Core Support cores Example The
38. es umm Fera ados otii sie beu Raus e ep sU DES 47 1 4 Limitation Of Liabilty Pet 47 Appendices A TOURS SIO OU Me 48 B MECN AING Sissies 49 ui jur e 51 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 3 1 Introduction bdiGDB enhances the GNU debugger GDB with JTAG COP debugging for QorlQ P4 based tar gets With the built in Ethernet interface you get a very fast code download speed No target commu nication channel e g serial line is wasted for debugging purposes Even better you can use fast Ethernet debugging with target systems without network capability The host to BDI communication uses the standard GDB remote protocol An additional Telnet interface is available for special debug tasks e g force a hardware reset program flash memory The following figure shows how the BDI2000 interface is connected between the host and the target Target System P4080 COP Interface UNIX PC Host GNU Debugger GDB Ethernet 10 BASE T 1 1 BDI2000 The BDI2000 is the main part of the bdiGDB system This small box implements the interface be tween the JTAG pins of the target CPU an
39. f deadbeef deadb 0 00000040 deadbeef deadbeef deadbeef deadb Notes The DUMP command uses TFTP to write a binary image to a host file Writing via TFTP on a Linux Unix system is only possible if the file already exists and has public write access Use man tftpd to get more information about the TFTP server on your host Copyright 1997 2014 by ABATRON AG Switzerland User Manual ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 User Manual 40 The Telnet commands PHYS lt address gt converts an effective to a physical address MD lt address gt lt count gt display target memory as word 32bit MDD lt address gt lt count gt display target memory as double word 64bit MDH lt address gt lt count gt display target memory as half word 16bit MDB lt address gt lt count gt display target memory as byte 8bit DUMP lt addr gt size lt file gt dump target memory to a file u addr value lt cnt gt modify word s 32bit in target memory MMD addr value lt cnt gt modify double word s 64bit in target memory MMH addr value cnt modify half word s 16bit in target memory MMB addr value cnt modify byte s 8bit in target memory MT lt addr gt lt count gt lt loop gt memory test MC lt address gt lt
40. ff00000a 0x00000064_0x00000000 0x10060000_0xff00003f Set MAS2 upper word LiL Copyright 1997 2014 by ABATRON AG Switzerland 64_ff000000 gt 0_ff000000 16MB I G RWXRWX 16MB I G RWXRWX V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 22 3 2 2 Part TARGET The part TARGET defines some target specific values CPUTYPE type core soc This value gives the BDI information about the connected CPU core JTAGCLOCK value POWERUP delay RESET type time EDBCRO list type P2040 P3041 P4040 P4080 B4860 B4420 P5010 P5020 P5021 P5040 T1020 T1040 T2080 T4240 T4160 core the core thread number within the SOC 0 n SOC the SOC number 0 3 Example CPUTYPE P4080 0 0 CoreO SOCO CPUTYPE P40801 Core1 SOCO With this value you select the JTAG clock frequency value The JTAG clock frequency in Hertz or an index value from the following table 0 16 6 MHz 4 500 kHz 7 50 kHz 1 8 3MHz 5 200 kHz 8 20 kHz 2 4 1 MHz 6 100 kHz 9 10 kHz 3 1 0 MHz 10 5 kHz Example CLOCK 1 JTAG clock is 8 3 MHz When the BDI detects target power up HRESET is forced immediately This way no code from a boot ROM is executed after power up The value entered in this configuration line is the delay time in milliseconds the BDI waits before it begins JTAG communication This time should be longer than the on board reset circuit asserts HRESET delay the power up start delay in millisec
41. flicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 BDI2000 Update Setup r Connect BDI2000 Loader r Channel SN 95111242 C Port cOM2 z MAC 000001951112 Speed 115200 v gt BDI2000 Firmware Logic Current Newest Loader 1 05 Current Firmware 1 04 1 04 Logic 1 05 1 05 UBGate r Configuration BDI IP Address 151 120 25 101 Subnet Mask 255 255 255 255 Default Gateway 255 255 255 255 Config Host IP amp ddress 151 120 25 118 Configuration file E cygwin home bdidemo e500 cds8548 cig Cancel Ok Transmit Writing setup data passed dialog box BDI2000 Update Setup Before you can use the BDI2000 together with the GNU debugger you must store the initial config uration parameters in the BDI2000 flash memory The following options allow you to do this Port Speed Connect Current Update Select the communication port where the BDI2000 is connected during this setup session Select the baudrate used to communicate with the BDI2000 loader during this setup session Click on this button to establish a connection with the BDI2000 loader Once connected the BDI2000 remains in loader mode until it is restarted or this dialog box is closed Press this button to read back the current loaded BDI2000 software and logic versions The current loader firmware and logic version will be display
42. ing then the built in fuse might be damaged in cases where the device was used with wrong supply voltage or wrong polarity To exchange the fuse or to perform special initialization please proceed according to the following steps A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF 1 1 Unplug the cables jJ pm Ex 2 1 Remove the two plastic caps that cover the screws on target front side e g with a small knife 2 2 Remove the two screws that hold the front panel BDI TRGT MODE BDI MAIN BDI OPTION 3 1 While holding the casing remove the front panel and the red elastig sealing casing N elastic sealing front panel Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 50 4 1 While holding the casing slide carefully the print in position as shown in figure below Jumper settings me fom DEFAULT INIT MODE 4 Fuse Position Fuse Position Version B e Version A o v N Pull out carefully the fuse and replace it Type Microfuse MSF 1 6AF Manufacturer Schurter Reinstallation 5 1 Slide back carefully
43. ldi JTAG debug interface for GNU Debugger QorlQ P3 PA P5 T1 TZ T4 User Manual Manual Version 1 08 for BDI2000 cboebconm 1997 2014 by Abatron AG tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 2 1 introduction 3 d BDI2000 aptat reer a E a ee ee eee renee ree re eee ere 3 1 2 BAO MR ERE I o M 4 2 installation iik d RE REIR YE REXEERIRUEUARRESVAERENEAXERU AN MUR ERUIT HUN UR FULL DAE EE ODER AN REDUPIE LARA EE ESO 5 2 1 Connecting the BDI2000 to TArgel uon eee tibiam COR qu rei oon E a Ioui nudi ssis 5 2 2 Connecting the BDI2000 to Power Supply sssseeeeeeenennneenneenen nre 7 2 3 Status LED enlm ere eee ee eee ees ee eer ae 8 2 4 Connecting the BDI2000 to HOSt eee cece cece eee eeee eee nennen nnne enne nennen 9 2 4 1 Senal line Gomibinibaltlbri sicui cas tui ende aa eR beu tbt Hp ERE ieu UR tco QUU QUE E MEU He pan RUNE 9 242 Ethernet communication oues degit nnea epe dee Ra nre guai cute cam Ex acus UR pu I nunana eneen naa 10 2 5 Initial configuration of the bdiGDB system ssessssseeeenmneeen menn 11 2 5 1 Configuration with a Linux Unix host sssssseeeneeeenenee emen 12 2 5 2 Configuration with a Windows host raieee eee tinto ttr n tnit Ra Re Ee ko e Ru EE Rohan et 14 2 5 3 Recover MOCO rae dicono testet n E Ehe ep p Inici ee Isa adus 15 2 6 Testing the BDI2000 to host connection
44. locked via the Telnet interface In order to make erasing of multiple flash sectors easier you can enter an erase list All entries in the erase list will be processed if you enter ERASE at the Telnet prompt without any parameter This list is also used if you enter UNLOCK at the Telnet without any parameters With the in crement and count option you can erase multiple equal sized sectors with one entry in the erase list address increment count mode wait Example Example for the ADS8260 flash memory FLASH HIPTYPE HIPSIZE USWIDTH ORKSPAC ILE RASE RASE RASE RASE Ae Ed Ed tj zi UJ O00 A E Ej bd 128BX8 0x200000 32 0x04700000 OxFF900000 OxFF940000 OxFF980000 OxFF9c0000 Flash type Address of the flash sector block or chip to erase If present the address offset to the next flash sector If present the number of equal sized sectors to erase BLOCK CHIP UNLOCK Without this optional parameter the BDI executes a sec tor erase If supported by the chip you can also specify a block or chip erase If UNLOCK is defined this entry is also part of the unlock list This unlock list is processed if the Telnet UNLOCK command is entered without any parameters Note Chip erase does not work for large chips because the BDI time outs after 3 minutes Use block erase The wait time in ms is only used for the unlock mode Af ter starting the flash unlock the BDI waits until
45. lso overriding individual RCW values If there is no valid RCW present at the currently via pin selected RCW Source a Hard coded RCW should be selected RCWSRC source Defines a new RCW Source to be used source The RCW Source number 0x000 OX1FF Example RCWSRC 0x18 Hard Coded RCW 1 1000 RCWOVR index data Override the value of an individual 32 bit RCW index The RCW index 0 15 means RCW1 RCW16 data The new RCW value Example RCWOVR 11 0x00830000 RCW bits 352 383 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 27 3 2 3 Part HOST The part HOST defines some host specific values IP ipaddress The IP address of the host ipaddress the IP address in the form XXX XXX XXX XXX Example IP 151 120 25 100 FILE filename The default name of the file that is loaded into RAM using the Telnet load command This name is used to access the file via TFTP If the filename starts with a this is replace with the path of the configuration file name filename the filename including the full path or for relative path Example FILE F gnu demo ppc test elf FILE Stest elf FORMAT format offset The format of the image file and an optional load address offset If the im age is already stored in ROM on the target select ROM as the format The optional parameter offset is added to any load address read from the im age file format SREC BIN ELF or ROM Example
46. n be accessed by name via the Telnet interface BDI gt rd csrrO0 BDI rm brO 0x00000801 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 35 3 3 Debugging with GDB Because the GDB server runs within the BDI no debug support has to be linked to your application There is also no need for any BDI specific changes in the application sources 3 3 1 Target setup Target initialization may be done at two places First with the BDI configuration file second within the application The setup in the configuration file must at least enable access to the target memory where the application will be loaded Disable the watchdog and setting the CPU clock rate should also be done with the BDI configuration file Application specific initializations like setting the timer rate are best located in the application startup sequence 3 3 2 Connecting to the target As soon as the target comes out of reset BDI initializes it and optionally loads your application code BDI now waits for GDB request from the debugger running on the host After starting the debugger it must be connected to the remote target This can be done with the fol lowing command at the GDB prompt gdb target remote bdi2000 2001 bdi2000 This stands for an IP address The HOST file must have an appropriate entry You may also use an IP address in the form xxx Xxx XXX XXX 2001 This is the TCP port used to communicate
47. nd that TFTP has it s own root direc tory usual tftpboot root LINUX_1 bdisetup bdisetup c p dev ttyS0O b57 gt 1151 120 25 101 gt hl5I1 120 25 118 N gt fp4080 cfg Connecting to BDI loader Writing network configuration Writing init list and mode Configuration passed 5 Check configuration and exit loader mode The BDI is in loader mode when there is no valid firmware loaded or you connect to it with the setup tool While in loader mode the Mode LED is flashing The BDI will not respond to network requests while in loader mode To exit loader mode the bdisetup v s can be used You may also power off the BDI wait some time 1min and power on it again to exit loader mode root LINUX_1 bdisetup bdisetup v p dev ttySO0 b57 s BDI Type BDI2000 Rev C SN 92152150 Loader o0NL05 Firmware V1 00 bdiGDB for P4080 Logic V1 05 PPC6xx PPC7xx MAC 00 0c 01 92 15 21 IP Addr 151 120 25 101 Subnet 1 7255 255 255 255 Gateway 255 255 255 255 Host IP 151 120 25 118 Config p4080 cfg The Mode LED should go off and you can try to connect to the BDI via Telnet root LINUX_1 bdisetup telnet 151 120 25 101 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 User Manual 14 2 5 2 Configuration with a Windows host First make sure that the BDI is properly connected see Chapter 2 1 to 2 4 A To avoid data line con
48. o build the tool simply start the make utility root LINUX_1 bdisetup make ee 02 c o bdisetup o bdisetup c cc 02 c o bdicnf o bdicnf c cc 0O2 c o bdidll o bdidll c cc s bdisetup o bdicnf o bdidll o o bdisetup 2 Check the serial connection to the BDI With bdisetup v you may check the serial connection to the BDI The BDI will respond with infor mation about the current loaded firmware and network configuration Note Login as root otherwise you probably have no access to the serial port root LINUX_1 bdisetup bdisetup v p dev ttySO0 b57 BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware unknown Logic unknown MAC 00 0c 01 92 15 21 TP Addr z 255 255 255 255 Subnet f 255 255 255 255 Gateway 255 255 255 255 Host IP 255 255 255 255 Config 0 2 2 7 2 2 7 2 3 Load Update the BDI firmware logic With bdisetup u the firmware is loaded and the CPLD within the BDI2000 is programmed This con figures the BDI for the target you are using Based on the parameters a and t the tool selects the correct firmware logic files If the firmware logic files are in the same directory as the setup tool there is no need to enter a d parameter rootGQLINUX 1 bdisetup bdisetup u p dev ttySO0 b57 aGDB tP4080 Connecting to BDI loader Erasing CPLD Programming firmware with b20qp4gd 100 Programming CPLD with copjed21 102 Copyright 1997 2014 by ABATRON
49. on Telnet GDB will be closed if there is a connect request from the same host same IP address port the TCP port number default 2001 Example DEBUGPORT 2001 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 29 3 2 4 Part FLASH The Telnet interface supports programming and erasing of flash memories The bdiGDB system has to know which type of flash is used how the chip s are connected to the CPU and which sectors to erase in case the ERASE command is entered without any parameter CHIPTYPE type CHIPSIZE size BUSWIDTH width FILE filename FORMAT format offset WORKSPACE address This parameter defines the type of flash used It is used to select the cor rect programming algorithm format AM29F AM29BX8 AM29BX16 I28BX8 I28BX16 AT49 AT49X8 AT49X16 STRATAX8 STRATAX16 MIRROR MIRRORX8 MIRRORX16 S29M32X16 S29GLSX16 S29VSRX16 M58X32 AM29DX16 AM29DX32 Example CHIPTYPE AM29F The size of one flash chip in bytes e g AM29F010 0x20000 This value is used to calculate the starting address of the current flash memory bank size the size of one flash chip in bytes Example CHIPSIZE 0x80000 Enter the width of the memory bus that leads to the flash chips Do not en ter the width of the flash chip itself The parameter CHIPTYPE carries the information about the number of data lines connected to one flash chip For example enter 16 if you a
50. onds Example POWERUP 5000 start delay after power up Normally the BDI drives the HRESET line during startup If reset type is NONE the BDI does not assert a hardware reset during startup This entry can also be used to change the default reset time type NONE HARD default KEEP keep HRESET assert during target power up time The time in milliseconds the BDI assert the reset signal Example RESET NONE no reset during startup RESET HARD 1000 assert RESET for 1 second This parameter allows to change the default EDBCRO value By default the EDM DNH and EFT bits are set list Example defines the bits to set EDM DN EFT DNI CTH EDBCRO EDM DNH EFT this is the default EDBCRO EDM DNH do not freeze timers EDBCRO DNH do not halt on debug events Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 e A for BDI2000 QorlQ P3 P4 P5 T1 T2 TA User Manual 23 WAKEUP time This entry in the init list allows to define a delay time in ms the BDI inserts between releasing the COP HRESET line and starting communicating with the target This init list entry may be necessary if COP HRESET is de layed on its way to the PowerPC reset pin time the delay time in milliseconds Example WAKEUP 3000 insert 3sec wake up time STARTUP mode runtime This parameter selects the target startup mode The following modes are supported HALT This mode forces the target to debug mode immediately out of reset If HALT for core number
51. one is actually a special case of the sec ond one Debug only one core via GDB but make sure that always all cores are either halted or running For this only one CGROUP for the debugged core is necessary The core mask defines all the cores Debug multiple cores not necessary all cores with different GDB sessions Here one core will be let s say the master core with the attached master GDB session Always continue all other GDB session cores before entering the continue command in the master GDB ses sion For the master core define the CGROUP mask with all cores For other cores set only the bit in the core mask that represents the core itself INIT setup device trigger debug halt always all cores WREG cgcr0 0x0000000f CGCRO Core Group 0 0 1 2 3 WREG cgcrl 0x0000000f CGCR1 Core Group 1 0 1 2 3 WREG cgcr2 0x0000000f CGCR2 Core Group 2 0 1 2 3 WREG csttacrO 4 0x00020001 CSTTACRO trigger if a core from group 1 enter debug halt i use device event 4 to halt cores WREG cgacrd4 0x00000022 CGACRD4 if device event halt cores in group 2 or use an EPU event to halt cores WREG epsmcrl13 0x53000000 EPSMCRI3 ISELO 83 RCPM Concerntrator 0 Event WREG epecr13 0x80000000 EPECRI3 ICO 2 Input 0 is sufficient WREG cgacrel3 0x00000022 CGACRE13 if EPU event halt cores in group 2 Writing to the DSCR space via the init list is possible even when all cores are
52. r to Figure below Target System P4080 5 GROUND l BDI2000 RS232 Connector for PC host 2 RXD data from host 3 TXD data to host Host RS232 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 o bd for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 10 2 4 2 Ethernet communication The BDI2000 has a built in 10 BASE T Ethernet interface see figure below Connect an UTP Un shilded Twisted Pair cable to the BD2000 For thin Ethernet coaxial networks you can connect a commercially available media converter BNC gt 10 BASE T between your network and the BDI2000 Contact your network administrator if you have questions about the network Target System 10 BASE T Connector 1 TD 2 TD 3 RD LI TX RX 10 BASE T BDI2000 PC Unix Host Ethernet 10 BASE T C The following explains the meanings of the built in LED lights LED Name Description LI Link When this LED light is ON data link is successful between the UTP port of the BDI2000 and the hub to which it is connected TX Transmit When this LED light BLINKS data is being transmitted through the UTP port of the BDI2000 RX Receive When this LED light BLINKS data is being received through the UTP port of the BDI2000 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manu
53. re 1 running Core 2 running Core 3 running Core 4 running Core 5 running Core 6 halted OxfffffOf8 debug halt Core 7 halted OxfffffOf8 debug halt P4080 0 gt Copyright 1997 2014 by ABATRON AG Switzerland A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 44 Multi Core Restart via GDB continue Then core specific parameter CGROUP allows to define a group of cores that should be restarted when GDB sends the continue command to the BDI This has the same effect as the Telnet cont command To halt a group of cores use the Cross Trigger functions of the processor Have a look at the configuration example below There are two alternatives one using a device event and the other more complex one using an EPU event Via the new CGROUP parameter you define what the BDI does in response to the GDB continue command e If there is no CGROUP defined then the core is restarted as usual e If the CGROUP core mask defines only the actual core then this core is prepared for restart but the final step to actually restart is made pending To actually restart it a continue com mand from the master GDB session see next or the Telnet cont command is necessary e f the CGROUP core mask includes other cores beside the actual one then all cores in the mask are prepared for restart if not already done and finally the whole core group is restarted at the same time This supports two different debug scenarios where the first
54. re using two AM29F 010 to build a 16bit flash memory bank with the width of the flash memory bus in bits 8 16 32 64 Example BUSWIDTH 16 The default name of the file that is programmed into flash using the Telnet prog command This name is used to access the file via TFTP If the file name starts with a this is replace with the path of the configuration file name This name may be overridden interactively at the Telnet interface filename the filename including the full path or for relative path Example FILE F gnu ppc bootrom hex FILE bootrom hex The format of the file and an optional address offset The optional param eter offset is added to any load address read from the program file You get the best programming performance when using a binary format BIN or ELF format SREC BIN or ELF Example FORMAT BIN 0x10000 If a workspace is defined the BDI uses a faster programming algorithm that runs out of RAM on the target system Otherwise the algorithm is pro cessed within the BDI The workspace is used for a 1kByte data buffer and to store the algorithm code There must be at least 2kBytes of RAM avail able for this purpose address the address of the RAM area Example WORKSPACE 0x00000000 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 30 ERASE addr increment count mode wait The flash memory may be individually erased or un
55. rence for the input comparators It also controls the output logic levels to the target It is normally connected to Vdd I O on the target board 3 0 5 0V with Rev B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm or less TCK JTAG Test Clock This output of the BDI2000 connects to the target TCK pin 108 General purpose I O This output of the BDI2000 connects to the target CKSTP_IN pin Currently not used TMS JTAG Test Mode Select This output of the BDI2000 connects to the target TMS line 1010 SRESET GROUND General purpose I O Currently not used Soft Reset This open collector output of the BDI2000 connects to the target HRESET pin HRESET lt reseved gt GROUND System Ground Hard Reset This open collector output of the BDI2000 connects to the target PORESET pin General purpose Input This input to the BDI2000 connects to the target CKSTP_OUT pin Currently not used System Ground V 1 08 tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 7 2 2 Connecting the BDI2000 to Power Supply The BDI2000 needs to be supplied with 5 Volts max 1A via the POWER connector The available power supply from Abatron option or the enclosed power cable can be directly connected In order to ensure reliable operation of the BDI2000 keep the power supply cable as short as possi
56. rocedure of conformity was assured according to the following standards EN 50081 2 EN 50082 2 This declaration of conformity is based on the test report no QNL E853 05 8 a of QUINEL Zug accredited according to EN 45001 Manufacturer ABATRON AG St ckenstrasse 4 CH 6221 Rickenbach Authority IC EY uu Max Vock Ruedi Dummermuth Marketing Director Technical Director Rickenbach May 30 1998 Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 A for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 47 7 Warranty and Support Terms 7 1 Hardware ABATRON Switzerland warrants the Hardware to be free of defects in materials and workmanship for a period of 3 years following the date of purchase when used under normal conditions In the event of notification within the warranty period of defects in material or workmanship ABATRON will repair or replace the defective hardware The cost for the shipment to Abatron must be paid by the customer Failure in handling which leads to defects are not covered under this warranty The war ranty is void under any self made repair operation 7 2 Software License Against payment of a license fee the client receives a usage license for this software product which is not exclusive and cannot be transferred Copies The client is entitled to make copies according to the number of licenses purchased Copies exceeding this number are allowed for storage purposes as a repla
57. ster definition file This name is used to access the file via TFTP The file is loaded once during BDI startup filename the filename including the full path Example FILE C bdi regs regP4080 def DMMn base This defines the base address of direct memory mapped registers This base address is added to the individual offset of the register base the base address Example DMM 1 0x01000 IMMn addr data This defines the addresses of the memory mapped address and data reg isters of indirect memory mapped registers The address of a IMMn regis ter is first written to addr and then the register value is access using data as address addr the address of the Address register data the address of the Data register Example DMM 1 0x04700000 Remark The registers msr cr pc pc64 iar iar64 and fpscr and are predefined Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 ldi for BDI2000 QorlQ P3 P4 P5 T1 T2 T4 User Manual 34 Example for a register definition Entry in the configuration file REGS FILE regP4080 def The register definition file name type addr sp GPR 1 atbl SPR 526 atbu SPR JAT bucsr SPR 1013 csrrO SPR 58 esrrl SPR 59 tlb0cfg SPR 688 tlblcfg SPR 689 tsr SPR 336 usprgO SPR 256 xer SPR UN 7 Local Bus Controller bro CCSR 0x124000 bri CCSR 0x124008 br2 CCSR 0x124010 br3 CCSR 0x124018 fcr CCSR 0x1240E8 fbar CCSR 0x1240EC fpar CCSR 0x1240F0 fbcr CCSR 0x1240F4 Now the defined registers ca
58. store instruction only used if R 1 For example to access the real address Ox3 8400 0000 with and G set via the current core BDI memacc core 0x94 BDI md 0x384000000 1 For memory accesses via SAP the lt attr gt defines a delay sometimes necessary when accessing slow memory The following example define a 100us delay during memory accesses via SAP BDI memacc sap 100 Memory access mode is a global selection It is not possible to select different modes for different cores Note For information about the registers in DCSR space please contact Freescale Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 42 3 5 Multi Core Support The bdiGDB system supports concurrent debugging of up to 8 cores threads For every core you can start its own GDB session The default port numbers used to attach the remote targets are 2001 2008 In the Telnet you switch between the cores with the command select lt 0 7 gt In the configu ration file simply begin the line with the appropriate core number If there is no n in front of a line the BDI assumes core 0 The following example defines 4 cores for debugging For a complete example look at the configu ration examples TARGET common parameters POWERUP 5000 start delay after power up detected in ms JTAGCLOCK 16000000 use 16 MHz JTAG clock WAKEUP 200 give reset time to complete
59. t commands STATE SELECT lt core gt CONT lt cores gt HALT lt cores gt Display information about all cores Change the current Telnet core Restart one or multiple cores lt cores gt core bit map Example cont 0x000d restart core 0 2 3 Force one or multiple cores to debug mode If there is no lt cores gt param eter the currently selected core is forced to debug mode lt cores gt Example Telnet session P4080 0 gt info Target CPU P4080 Core 0 core bit map halt OxOOff halt 8 cores 0 7 Core state halted Debug entry cause debug halt Current PC Ox7 74c34 Current CR 0x22000084 Current MSR 0x00029200 Current LR Ox7ff74c38 Current CCSRBAR OxO fe000000 P4080 0 gt state Core 0 halted 0x7ff74c34 debug halt Core 1 running Core 2 running Core 3 running Core 4 running Core 5 running Core 6 running Core 7 running P4080 0 gt halt Oxf0 TARGE core 4 has entered debug mode TARGE core 5 has entered debug mode TARGE core 6 has entered debug mode TARGE core 7 has entered debug mode P4080 0 gt state Core 0 halted 0x7ff74c34 debug halt Core 1l running Core 2 running Core 3 running Core 4 halted OxfffffO0f8 debug halt Core 5 halted OxfffffOf8 debug halt Core 6 halted OxfffffOf8 debug halt Core 7 halted OxfffffOf8 debug halt P4080 0 gt cont 0x30 P4080 0 gt state Core 0 halted 0x7ff74c34 debug halt Co
60. t current breakpoint mode GO lt pc gt set PC and start current core CONT cores restart multiple cores lt cores gt core bit map UTI pc trace on instruction single step TTC lt pc gt trace on change of flow HALT lt cores gt force core s to debug mode lt cores gt core bit map BI lt addr gt set instruction hardware breakpoint CI lt id gt clear instruction hardware breakpoint s BD R W lt addr gt set data watchpoint CD lt id gt clear data watchpoint s INFO display information about the current core STATE display information about all cores LOAD lt offset gt lt file gt lt format gt load program file to target memory VERIFY lt offset gt lt file gt lt format gt verify a program file to target memory PROG lt offset gt lt file gt lt format gt program flash memory format SREC BIN AOUT or ELF Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 41 The Telnet commands cont ERASE lt address gt lt mode gt erase a flash memory sector chip or block T mode CHIP BLOCK or SECTOR default is sector ERASE lt addr gt step count erase multiple flash sectors UNLOCK lt addr gt lt delay gt unlock a flash sector UNLOCK lt addr gt lt step gt lt count gt unlock multiple fl
61. the virtual physical address of the array with the two page table point ers For more information see also chapter Embedded Linux MMU Sup port If this parameter is not defined the BDI searches TLBO in order to translate a virtual address TLB1 is always searched If the additional 64BIT option is present the BDI assume a 64 bit PTE addr Physical address of the memory used to store the virtual address of the array with the two page table pointers Example PTBASE Oxf0 When this line is present a TCP IP channel is routed to the BDI s RS232 connector The port parameter defines the TCP port used for this BDI to host communication You may choose any port except 0 and the default Telnet port 23 On the host open a Telnet session using this port Now you should see the UART output in this Telnet session You can use the normal Telnet connection to the BDI in parallel they work completely in dependent Also input to the UART is implemented port The TCP IP port used for the host communication baudrate The BDI supports 2400 115200 baud Example SIO 7 9600 TCP port for virtual IO MEMACCES mode attr SNOOP NOSNOOP There are two possible ways to access memory Via the current core by executing Id st instructions or via the System Access Port SAP See also Telnet chapter The following modes are supported SAP Memory access via SAP default The attr is a delay sometimes necessary when accessing slow memory Access
62. with the BDI If not already suspended this stops the execution of application code and the target CPU changes to background debug mode Remember every time the application is suspended the target CPU is freezed During this time no hardware interrupts will be processed Note For convenience the GDB detach command triggers a target reset sequence in the BDI gdb detach Wait until BDI has resetet the target and reloaded the image gdb target remote bdi2000 2001 3 3 3 GDB monitor command The BDI supports the GDB V5 x monitor command Telnet commands are executed and the Telnet output is returned to GDB This way you can for example switch the BDI breakpoint mode from within your GDB session gdb target remote bdi2000 2001 Remote debugging using bdi2000 2001 Ox10b2 in start gdb monitor break Breakpoint mode is SOFT gdb mon break hard gdb mon break Breakpoint mode is HARD gdb Copyright 1997 2014 by ABATRON AG Switzerland V 1 08 tdi for BDI2000 QorlQ P3 P4 P5 T 1 T2 T4 User Manual 36 3 3 4 Target serial I O via BDI A RS232 port of the target can be connected to the RS232 port of the BDI2000 This way it is possible to access the target s serial I O via a TCP IP channel For example you can connect a Telnet session to the appropriate BDI2000 port Connecting GDB to a GDB server stub running on the target should also be possible Target System RS232 Connector 1 CD 2 RXD 3

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