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addressing the acc-65e

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1. Station I O Node 2 3 6 7 10 11 Ring Controller I O Node 2 3 6 7 10 11 24 bit X 78420 X 78424 X 78428 X 7842C X 78430 X 78434 16 bit X 78421 X 78425 X 78429 X 7842D X 78431 X 78435 16 bit X 78422 X 78426 X 7842A X 7842E X 78432 X 78436 16 bit X 78423 X 78427 X 7842B X 7842F X 78433 X 78437 Turbo Ring Controller MACRO IC 1 Node Registers Station I O Node 2 3 6 7 10 11 Ring Controller I O Node 18 19 22 23 26 27 24 bit X 79420 X 79424 X 79428 X 7942C X 79430 X 79434 16 bit X 79421 X 79425 X 79429 X 7942D X 79431 X 79435 16 bit X 79422 79426 7942 X 7942E X 79432 X 79436 16 bit X 79423 X 79427 X 7942B X 7942F X 79433 X 79437 Turbo Ring Controller MACRO IC 2 Node Registers Station I O Node 2 3 6 7 10 11 Ring Controller I O Node 34 35 38 39 42 43 24 bit X 7A420 X 7A424 X 7A428 X 7A42C X 7A430 X 7A434 16 bit 7 421 X 7A425 X 7A429 7 42 X 7A431 X 7A435 16 bit 7 422 7 426 X 7A42A X 7A42E X 7A432 X 7A436 16 bit X 7A423 X 7A427 X 7A42B X 7A42F X 7A433 X 7A437 Turbo Ring Controller MACRO IC 3 Node Registers Station I O Node 2 3 6 7 10 11 Ring Controller I O Node 50 51 54 55 58 59 24 bit X 7B420 X 7B424 X 7B428 X 7B42C X 7B430 X 7B434
2. Appendix B Schematics Opto Gnd Plane 62 Accessory 65E APPENDIX C USING THE ACC 65E IN C This section shows how the ACC 65E can be programmed and used via the C programming language in Power PMAC ACC 65E C Library Include the following header file acc65e h into the Project include lt gplib h gt include lt RtGpShm h gt Global Rt Gp Shared memory pointers ff parc The following is a projpp created file from the User defines include Include pp proj h define ON 1 Assumes that logic high true define OFF 0 Assumes that logic low false void ACC65E_SetControlWord unsigned int CardNumber unsigned int ACC65E GetInputState unsigned int CardNumber unsigned int InputNumber unsigned int ACC65E GetOutputState unsigned int CardNumber unsigned int OutputNumber void ACC65E SetOutputState unsigned int CardNumber unsigned int OutputNumber unsigned int State Then put the following source code file acc65e c into the same folder as the header above include lt gplib h gt include RtGpShm h Global Rt Gp Shared memory pointers
3. 1 4 zJ 5 2 El 1 00 1 BPO x 1 RP11 2 UB10 PS2705 1NEC INO1 gu e i P M 24 1 4 VN YAN ACIN1 C1 INO2 ae 3 03 7 8 7 8 PLIME NIC 1 2 1 2K 4 UC10 PS2705 1NEC 1 1 MMBESVdALT MMBESV6ALTI MMBESVOALT MMBESV ALTI 1 4 025 3 D27 2 3 2 2 C10 ow os 7 os HARE RONS ES 0 1UF UD10 PS2705 1NEC MMBZ33VALT1G MMBZS3VALTIG 1 4 1 1 0 1UF 0 1UF RP12 27 AGING p26 D28 cia pi 4 E ai 2 2K BONA 21 2 0 1UF 12 PS2705 1NEC 1 4 colo teu MMBZ33VALTiG MMBZS3VALTIG 1 F isi et ga ACIN2 El 1 04 1 6 2 i BPi7 9 UB12 PS2705 1NEC INOS AP i YNN VN ACIN1 C1 1406 AA SAN 3 iNO7 7 8 2 p 12 1 2K 4 UC12 PS2705 1NEC 1 1 MMBESVdALT1 MMBESV6ALTI MMBESVOALT MMBESV ALTI poem t D29 D31 Le 3 RA 4 oJ oJ 2 2 c15 D53 D54 D55 D56 dall SEINE Ei 0 1UF UD12 PS2705 1NEC MMBZ33VALT1G MMBZS3VALTIG C16 Gaz 1 4 1 1 0 1UF 0 1UF RP18 2 AGIN 017 amp D32 C18 a a E d 2 2K ASING 21 2 4 0 1UF NEG 1 MMBZ3SVALTiG MMBZSSVALTIG 1 J 2 ae 2 AGING IN08 1 0 2 amp 1 RP31 2 UBi4 PS2705 iNEC INO9 gr cu 3 4 1 4 IN 10 n Wr r 2 N 3 YN VN ACIN2 E1 IN11 7 8 7 Mb 12 1 2K 4 UC1
4. m 0 0 e e Connector Pinouts and Wiring 12 24VDC Power Supply 12 24V Q N DMY O DOD N N e Bottom Outputs COM Output 1 Output 7 Output 8 Output 10 Output 11 Output 12 24V E 24 RET 24V Output 13 Output 14 Output 15 Output 16 Output 17 Output 18 Output 19 Output 21 on U A N QOQOQVOOVOO QO Q SSS A N e o NINI JAJA NG 6606 B P Accessory 65E D Sub Connectors Top Inputs J1 J2 Top D sub DA 15F Mating D sub DA 15M 00000000 06000000 Pin Function Jl J2 1 Input Input 1 Input 13 2 Input Input 3 Input 25 3 Input Input 5 Input 17 4 Input Input 7 Input 19 5 Input Input 9 Input 21 6 Input Input 11 Input 423 7 Return Inputs Return 1 8 8 Return Inputs Return 17 24 9 Input Input 2 Input 14 10 Input Input 4 Input 16 11 Input Input 6 Input 18 12 Input Input 8 Input 20 13 Input Input 10 Input 22 14 Input Input 12 Input 24 15 Return Inputs Return 9 16 Bottom Outputs J1 J2 Top D sub DA 15F Mating D sub DA 15M 0006000000 6000000 Pin Function Jl J2 1 Outpu
5. The following is projpp created file from the User defines F m finclude Include pp proj h include acc65e h void ACC65E SetControlWord unsigned int CardNumber CardNumber Power PMAC I O Card Index of this card 0 15 volatile unsigned int ioptr ioptr piom pshm OffsetCardlO CardNumber 4 7 ioptr 7 lt lt 8 Shift 7 up 8 and write the value return unsigned int ACC65E GetInputState unsigned int CardNumber unsigned int InputNumber CardNumber Power PMAC I O Card Index of this card 0 15 InputNumber Input Pin Number 1 24 volatile unsigned int ioptr InputNumber ioptr piom pshm OffsetCardIO CardNumber 4 ioptr InputNumber 8 Shift all bits above the desired bit out Then shift down to bit 0 and return return unsigned int ioptr lt lt 31 InputNumber 8 8 gt gt 31 unsigned int ACC65E GetOutputState unsigned int CardNumber unsigned int OutputNumber CardNumber Power PMAC I O Card Index of this card 0 15 OutputNumber Input Pin Number 1 24 volatile unsigned int ioptr OutputNumber ioptr piom pshm OffsetCardIO CardNumber 4 Appendix C Using The ACC 65E in C 63 Accessory 65E ioptr OutputNumber 8 3 Shift all bits above the desired bit out Then shift down to bit 0 and return return unsigned int ioptr lt lt 31 OutputNumber 8 8
6. 5 sure that the Build Action for acc65e c under z gt ja n acc65e h Properties is set to Compile The Solution ants oscar Explorer should then look something like the H Configuration Documentation Build Action screenshot to the right Log How the file relates to the build and deployment PMAC Script Language process Then in the Background Program include the header file with the following preprocessor directive include Libraries acc65e acc65e h Appendix C Using The ACC 65E in C 64 Accessory 65E Background CPLCs BGCPLCs and Real Time CPLCs RTICPLCs To use the above code a Background CPLC put acc65e h and 5 into the same folder as the BGCPLC For example when using BGCPLCOO Solution Explorer might look like the following Solution Explorer Solution PowerPmac2 2 x Properties ES bgcplc c File Properties od Solution PowerPmac 2 1 project Ej C PowerPmac2 192 168 0 200 5 zy C Language E 8 Background Programs Build Action Content 5 CPLCs B 5 By bgcplc00 File Name bgcplc c acc65e c Full Path C Users gregs Documents P4 n acc65e h bgcplc c a Li rticplc y Include pp proj h B ay Libraries 5 acc65e c n acc65e h Realtime Routines Configuration H 3 Documentation Loa Then include the heade
7. oo oo oa 0 OG OO a O a O DO DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg DataReg oa 00 00 N N N N N N N N N oU 5 NN P Q N F O 2 ong Outputs Outputl1 ACC65E 0 DataReg Output2 ACC65E 0 DataReg Output3 ACC65E 0 DataReg Output4 ACC65E 0 DataReg Output5 ACC65E 0 DataReg Output6 ACC65E 0 DataReg Output7 ACC65E 0 DataReg Output8 2ACC65E 0 DataReg Output9 ACC65E 0 DataReg Outputl10 ACC65E 0 DataReg Outputl11 ACC65E 0 DataReg Output12 ACC65E 0 DataReg Output13 ACC65E 0 DataReg Output14 ACC65E 0 DataReg Output15 gt ACC65E 0 DataReg Outputl16 ACC65E 0 DataReg Outputl17 ACC65E 0 DataReg Output18 ACC65E 0 DataReg Output19 ACC65E 0 DataReg Output20 ACC65E 0 DataReg Output21 ACC65E 0 DataReg Output22 ACC65E 0 DataReg Output23 ACC65E 0 DataReg Output24 ACC65E 0 DataReg CO CO CO CO CO CO CO CO aS a a CO 5 N F O Typically these pointers would b
8. Bank B Bank A Data Inputs Outputs Inputs Outputs Register Gate3 i MacroInB j 0 Gate3 MacroOutB j 0 Gate3 i MacroInA j 0 Gate3 i MacroOutA 0 24 bit Gate3 i MacroInB j 1 Gate3 i MacroOutB j 1 Gate3 i MacroInA j 1 Gate3 i MacroOutA j 1 17 16 bit Gate3 i MacroInB j 2 Gate3 i MacroOutB j 2 Gate3 i MacroInA j 2 Gate3 i MacroOutA j 2 2 16 bit Gate3 i MacroInB j 3 Gate3 i MacroOutB j 3 Gate3 i MacroInA j 3 Gate3 i MacroOutA j 3 3 16 bit Where gt iisthe PMAC3 Style MACRO IC index gt jis the I O node number Note Bitwise mapping into the PMAC3 Style MACRO structure elements requires Power PMAC firmware version 1 5 8 215 or newer Below are example tables showing I O Node numbers of the first 4 PMAC3 Style MACRO ICs Gate3 0 Bank B Station Nodes 1011123 n 12 Ring Controller 1 Node j 26 27 Gate3 1 Bank A Bank B Station 2 3 6 7 110 11 2 3 6 7 111 12 Ring Controller I O Node j 34 35 38 39 42 43 50 51 54 55 58 59 Gate3 2 Bank A Bank B Station Node 2 316171101112 31647 12 Ring Controller I O Node 66 67 70 71 74 75 82 83 86 87 90 91 Gate3 3 Bank A Bank B Station Node 2
9. P Pel 8 1 19 1 220 1 21 1 22 1 23 1 24 1 25 23 26 1 XT 285 13 28 1 20 15 31 17 j BW Bd Hd Hd d kd xb dud 50 xb kg j j 9 J e Node 3 16 bit Reg 3 23 i Outputs Outputl1 Gate3 0 MacroOutA Output2 Gate3 0 MacroOutA Output3 Gate3 0 MacroOutA Output4 Gate3 0 MacroOutA Output5 gt Gate3 0 MacroOutA Output6 gt Gate3 0 MacroOutA Output7 Gate3 0 MacroOutA Output8 Gate3 0 MacroOutA Output9 Gate3 0 MacroOutA Outputl10 Gate3 0 MacroOutA Outputl11 Gate3 0 MacroOutA Output12 Gate3 0 MacroOutA Output13 gt Gate3 0 MacroOutA Output14 gt Gate3 0 MacroOutA Output15 gt Gate3 0 MacroOutA Outputl16 Gate3 0 MacroOutA Output17 gt Gate3 0 MacroOutA Output18 gt Gate3 0 MacroOutA Output19 gt Gate3 0 MacroOutA Output20 gt Gate3 0 MacroOutA Output21 gt Gate3 0 MacroOutA Output22 gt Gate3 0 MacroOutA Output23 gt Gate3 0 MacroOutA Output24 gt Gate3 0 MacroOutA CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO oo 0000000 oo OO 000000000200 0 Bud 9 1 10 oi 12 2135 14 15 16 du 8 19 20 21 222 2 24 25 26 sata 28 29 230 31 With Power the outputs can be directly bitwise mapped written to and reported Mi
10. MACRO Station ACC 65E 8800 MS2 MI160 10C0A0008800 Node 2 24 bit Register Ring Controller Having downloaded the above settings into the 16 station the inputs can be read and outputs can be transferred from the ring controller side I O node 2 in the following bit fields Turbo I O Node Data Address Bits Power Structure Data Structure Data Element PMAC2 Bits Element PMAC3 Bits Inputs Outputs X 78420 23 00 Gate2 0 Macro 2 0 23 00 1 31 08 Gate3 0 MacroInA 2 0 Gate3 0 MacroOutA 2 0 Using the ACC 65E With MACRO 27 Accessory 65E MI160 example 2 Transferring I O data for two ACC 65Es at consecutive base addresses 8800 and 9800 over nodes 2 and 3 of MACRO IC 0 MS2 MI19 4 MS2 MI160 20C0A0008800 MS2 MI975 C MACRO Station ACC 65E 8800 ACC 65E 9800 52 1160 520 040008800 Node 2 24 bit Register Node 3 24 bit Register Ring Controller Having downloaded the above settings into the 16 station the inputs can be read and outputs can be transferred from the ring controller side I O nodes 2 and 3 in the following bit fields Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits Inputs Gate3 0 MacroInA 2 0 1 ACC 65E X 78420 23 00 Ga
11. gt gt 31 void ACC65E SetOutputState unsigned int CardNumber unsigned int OutputNumber unsigned int State B CardNumber Power PMAC I O Card Index of this card 0 15 OutputNumber Input Pin Number 1 24 State 1 0 volatile unsigned int ioptr unsigned int HighBitInCorrectLocation OutputNumber HighBitInCorrectLocation 1 lt lt OutputNumber 8 8 ioptr piom pshm OffsetCardIO CardNumber 4 ioptr OutputNumber 8 3 if State 1 If the user wants the pin to be ON high true Logical OR with the bit the user desires to activate ioptr HighBitInCorrectLocation else Logical AND the register with 0 in the desired location to bring the pin s state low right shift to push out garbage in lowest 8 bits then shift back up 8 bits to have data in the proper location ioptr amp 0 HighBitInCorrectLocation gt gt 8 lt lt 8 return Locations for the C Files Background C Programs To use the above ACC 65E code in a Properties acc65e c File Properties Background C Program make a new folder called acc65e in the C PowerPmac2 192 168 0 200 5 5 C Language 4 Language Libraries folder under the Bal Background Programs Compile Solution Explorer in the Power PMAC IDE ilic ed Then put the code into this folder and make 5 By Libraries perm CAUsers gregs Documents Po E
12. 24 using values stored 200 223 respectively The states of output pins 1 24 are read and then stored P300 P323 respectively for sake of comparison or demonstration purposes include lt gplib h gt include lt stdio h gt include lt dlfcn h gt include Include pp proj h include acc65e h fdefine ACC65E CardNumber 1 for base offset of B00000 void user plcc unsigned int ChannelNumber ArrayIndex for ChannelNumber 1 ChannelNumber lt 25 ChannelNumber Cycle through all 24 channels ArrayIndex ChannelNumber 1 Convert channel number to array index Get the states of input pins 1 24 and store the states in P100 P123 pshm gt P 100 ArrayIndex double ACC65E GetInputState ACC65E CardNumber ChannelNumber Set the states of output pins 1 24 to the values stored in P200 P223 ACC65E SetOutputState ACC65E CardNumber ChannelNumber unsigned int pshm gt P 200 ArrayIndex Get the states of output pins 1 24 and store the states in P300 P323 pshm gt P 300 ArrayIndex double ACC65E GetOutputState 65 Channe1Number return Appendix C Using The ACC 65E in C 67
13. Update data register Close The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register Note Using the ACC 65E With MACRO 45 Accessory 65E Power 2 MI71 Mapping Example is used to transfer ACC 65E data to MACRO IC 0 nodes 2 and 3 of the ring controller which places the 24 bits of inputs in the 24 bit register of node 2 and the 24 bits of outputs in the 24 bit register of node 3 Node 2 I O Node Node 2 16 bit Reg 1 Node 3 16 bit Reg 1 Node 2 16 bit Reg 2 Node 3 16 bit Reg 2 x Node 2 16 bit Reg 3 Node 3 16 bit Reg 3 23 15 7 The inputs are mapped into the 24 bits of node 2 0 23 15 7 PTR Inputl gt Gate2 0 Macro 2 0 0 1 PTR Input2 gt Gate2 0 Macro 2 0 1 1 PTR Input3 gt Gate2 0 Macro 2 0 2 1 PTR Input4 gt Gate2 0 Macro 2 0 3 1 PTR Input5 gt Gate2 0 Macro 2 0 4 1 PTR Input6 gt Gate2 0 Macro 2 0 5 1 PTR Input7 gt Gate2 0 Macro 2 0 6 1 PTR Input8 gt Gate2 0 Macro 2 0 7 1 PTR Input9 gt Gate2 0 Macro 2 0 8 1 PTR Input10 gt Gate2 0 Macro 2 0 9 1 PTR Input11 gt Gate2 0 Macro 2 0 Qo PTR Input12 gt Gate2 0 Macro 2 0 1 PTR Input13 gt Gate2 0 Macro 2 0 2 13 PTR Input14 gt Gate2 0 Macro 2 0 22 PTR Input15 gt Gate2 0 Macro 2 0 4 1 PT
14. 16 bit X 7B421 X 7B425 X 7B429 X 7B42D X 7B431 X 7B435 16 bit X 7B422 X 7B426 X 7B42A X 7B42E X 7B432 X 7B436 16 bit X 7B423 X 7B427 X 7B42B X 7B42F X 7B433 X 7B437 Using the ACC 65E With MACRO 2 Accessory 65E Power 2 Node Addressing The Power PMAC can interface with the ACC 5E which carries PMAC2 Style MACRO ICs The PMAC2 Style MACRO IC I O node data registers reside in the bit fields illustrated on the right PMAC2 Style IJO Node 24 bit Register 16 bit Register 1 16 bit Register 2 16 bit Register 3 23 15 7 And the corresponding structure elements Structure Element Data Register Gate2 i Macro j 0 24 bits Gate2 i Macro j 1 16 bits Gate2 i Macro j 2 16 bits Gate2 i Macro j 3 16 bits Where iisthe PMAC2 Style MACRO IC index gt jis the I O node number Bitwise mapping into the PMAC2 Style MACRO structure elements requires Power PMAC firmware version 1 5 8 215 or newer Note Using the ACC 65E With MACRO o N M Accessory 65E The tables below show Node numbers of the 4 PMAC2 Style MACRO Gate2 0 Station 6 7 10 11 Ring Controller I O Node J 2 3 6 7 10 11 Gate2 1 Station I O 2
15. PTR Output21 gt U USER 4 20 1 PTR Output22 gt U USER 4 21 1 PTR Output23 gt U USER 4 22 1 Output24 gt U USER 4 23 1 Bitwise mapping to user memory structure elements is not allowed Structure Address Explicit syntax with offset address must be used The offset address is Element Offset found by multiplying the element structure index by 4 To the right is an Sys Udata 1 U USER 4 example of the first 4 unsigned open memory structure elements and their Sys Udata 2 U USER 8 corresponding address offsets Sys Udata 3 U USER 12 Sys Udata 4 U USER 16 Power PMAC use Sys Udata 0 therefore it is highly advised NOT A large number of self addressed default Sys pushm pointers to use it as general purpose user memory Note The following PLC which should be executing constantly will copy the outputs into node 3 PTR N3Twenty4 Gate2 0 Macro 3 0 24 bit register node 3 PTR OutMirror gt U USER 4 0 24 Mirror Word shared user memory OutMirror 0 Save initialize to zero or desired state Open PLC 1 N3Twenty4 OutMirror Update data register Close The output states now reported and can be toggled individually using the bitwise assignments to the open memory register Note Using the ACC 65E With MACRO 47 Accessory 65E Power PMAC2 MI69 70 Mapping Example MI69 MI7O is used to transfer ACC 65E data thr
16. gt Y S10FF 17 define Output19 M7043 Output19 gt Y S10FF 18 define Output20 M7044 Output20 gt Y S10FF 19 define Output21 M7045 Output21 gt Y S10FF 20 define Output22 M7046 Output22 Y 10FF 21 define Output23 M7047 Output23 gt Y S10FF 22 define Output24 M7048 Output24 gt Y S10FF 23 The following mirror image PLC which should be executing constantly will copy the outputs into node 3 define N3Twenty4 M7049 Node 3 24 bit register define OutMirror M7050 Mirror word open memory N3Twenty4 gt Y 78424 0 24 24 bit register node 3 OutMirror gt Y S10FF 0 24 Open memmory register OutMirror 0 Save Initialize to zero or desired state Open PLC 1 Clear N3Twenty4 OutMirror Update data register Close The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register u Note Using the ACC 65E With MACRO Accessory 65E Turbo 2 MI69 70 Mapping Example MI69 MI70 is used to transfer ACC 66E data through MACRO IC 0 node 2 of the ring controller which places the I O Node 2 data in registers as illustrated on the right Node 2 24 bit Register The lower 16 bits of the 24 bits of inputs reside in the first 16 used this example bit register and the upper 8 bits of the 24 bits of inputs reside in the lower byte of the second 16 bit register The lower 8 bits of the 2
17. 08 Outputs Gate3 0 MacroOutA 6 0 Using the ACC 65E With MACRO 29 Accessory 65E MS anynode MI71 transfers all 48 bits 24 in 24 out of an ACC 65E into 2 x consecutive I O node 24 bit data registers It handles up to 3 x ACC 65Es at consecutive base addresses e g Y 8800 Y 8900 Y 8A00 and places the data in 6 x consecutive 24 bit I O node data registers is a 48 bit variable represented as 12 hexadecimal digits which set up as follows digit 1 is leftmost when constructing the word No of consecutive node pairs 1 for 2 1 0 nodes 2 for 4 1 0 nodes No of 24 bit banks per board 3 for 6 1 0 nodes max Always 2 smelt I7Is oe Reserved 0 Reserved 1 Starting I O node register Starting ACC 65E base address SCOXX i e 8800 For multiple ACC 65E transfers with MI71 consecutive cards must be under the same chip select Note Using the ACC 65E With MACRO 30 Accessory 65E MI71 example 1 Transferring I O data for one ACC 65E at address 8800 over nodes 2 and 3 of MACRO IC 0 MS2 MI19 4 MS2 MI71 2 10C0A0218800 MS2 MI975 C MACRO Station ACC 65E 8800 MS2 MI71 10C0A0218800 Ring Controller Having downloaded the above settings into the MACRO16 station the inputs and outputs are now available to access from the ring controller side e g I O nodes 2 3 in the following bit fields
18. 1 PTR Outputl11 U USER 4 10 1 PTR Output12 U USER 4 Pi PTR Output13 gt U USER 4 12 1 PTR Output1l4 gt U USER 4 13 1 PTR Output15 gt U USER 4 14 1 PTR Output1l6 gt U USER 4 15 1 PTR Output17 gt U USER 4 16 1 PTR Output18 gt U USER 4 17 1 PTR Output19 gt U USER 4 18 1 PTR Output20 gt U USER 4 19 1 PTR Output21 gt 0 USER 4 20 1 PTR Output22 gt U USER 4 21 1 PTR Output23 gt U USER 4 22 1 PTR Output24 gt U USER 4 23 1 Bitwise mapping to user memory structure elements is not allowed Structure Address Explicit syntax with offset address must be used The offset address is Element Offset found by multiplying the element structure index by 4 To the right is an Sys Udata 1 U USER 4 example of the first 4 unsigned open memory structure elements and their Sys Udata 2 U USER 8 corresponding address offsets Sys Udata 3 U USER 12 Sys Udata 4 U USER 16 Power PMAC use Sys Udata 0 therefore it is highly advised NOT A large number of self addressed default Sys pushm pointers to use it as general purpose user memory Note The following mirror image PLC which should be executing constantly will copy the outputs into node 2 PTR N2Twenty4 gt Gate2 0 Macro 2 0 node 2 shared with inputs PTR OutMirror gt U USER 4 0 24 Mirror Word shared user memmory OutMirror 0 Save initialize to zero or desired state Open PLC 1 N2Twenty4 OutMirror
19. 16 bit X C0A2 X COA6 X COAA X COAE X COB2 X COB6 16 bit X C0A3 0 7 X COAB X COAF X COB3 X COB7 MACRO Station IC 1 Node 2 3 6 7 10 11 24 bit X COEO X COE4 X COE8 X COEC X COFO X COF4 16 bit X COE1 X COES X COE9 X COED X COFI 0 5 16 bit X COE2 X COE6 X COEA X COEE X COF2 X COF6 16 bit X COE3 X COE7 X COEB X COEF X COF3 X COF7 I O nodes which will be chosen to transfer the ACC 65E s data are E configurable and chosen by the user depending on availability and I O node management in the MACRO station Note Non Turbo 2 Ultralite legacy node addresses are the same as MACRO Station 0 node registers For instance addresses the ring controller start at COAO instead of at 578420 as seen in the Note following section Using the ACC 65E With MACRO 19 Accessory 65E Ring Controller Node Addressing Turbo 2 Node Addressing Turbo ring controllers interface with PMAC2 Style MACRO ICs The data resides in the bit fields illustrated on the right Turbo ring controllers can be populated with up to 4 PMAC2 style MACRO reported by 14902 Below are the I O node addresses 7XXXX for each of the PMAC2 Style MACRO ICs Turbo PMAC2 1 Node 24 bit Register 16 bit Register 1 16 bit Register 2 16 bit Register 3 N w 15 7 o Turbo Ring Controller MACRO IC 0 N ode Registers
20. 2 2 30 PTR Input8 gt Gate3 0 MacroInA 2 23 PTR Output8 gt Gate3 0 MacroOutA 2 2 31 PTR Input9 gt Gate3 0 MacroInA 2 24 PTR Output9 Gate3 0 MacroOutA 2 3 16 PTR Inputl0 Gate3 0 MacroInA 2 25 PTR Output1l0 gt Gate3 0 MacroOutA 2 3 17 PTR Inputll Gate3 0 MacroInA 2 26 PTR Outputll Gate3 0 MacroOutA 2 3 18 PTR Input12 gt Gate3 0 MacroInA 2 27 PTR Output12 gt Gate3 0 MacroOutA 2 3 19 PTR Input13 gt Gate3 0 MacroInA 2 28 PTR Output13 gt Gate3 0 MacroOutA 2 3 20 PTR Input14 gt Gate3 0 MacroInA 2 29 PTR Outputl4 Gate3 0 MacroOutA 2 3 21 PTR Input15 gt Gate3 0 MacroInA 2 90 PTR Output15 gt Gate3 0 MacroOutA 2 3 22 PTR Input16 gt Gate3 0 MacroInA 2 sols PTR Outputl6 gt Gate3 0 MacroOutA 2 3 23 PTR Input17 gt Gate3 0 MacroInA 2 2 16 PTR Outputl17 Gate3 0 MacroOutA 2 3 24 PTR Input18 gt Gate3 0 MacroInA 2 2 17 PTR Output18 gt Gate3 0 MacroOutA 2 3 25 PTR Input19 gt Gate3 0 MacroInA 2 2 18 PTR Output19 gt Gate3 0 MacroOutA 2 3 26 PTR Input20 gt Gate3 0 MacroInA 2 2 19 PTR Output20 gt Gate3 0 MacroOutA 2 3 27 PTR Input21 gt Gate3 0 MacroInA 2 2 20 PTR Output21 gt Gate3 0 MacroOutA 2 3 28 PTR Input22 gt Gate3 0 MacroInA 2 2 21 PTR Output22 gt Gate3 0 MacroOutA 2 3 29 PTR Input23 gt Gate3 0 MacroInA 2 2 22 PTR Output23 gt Gate3 0 MacroOutA 2 3 30 PTR Input24 gt Gate3 0 MacroInA 2 2 23 PT
21. S QO N O j gt wor F 20 F 21 F 22 F 23 The following mirror image PLC which should be executing constantly will copy the outputs into node 2 define N2Secondl6 M7049 define N2Thirdl16 M7050 define OutMirror M7051 N2Second16 gt X 78422 8 16 N2Third16 gt X 78423 8 16 OutMirror gt Y S10FF 0 24 OutMirror 0 Open PLC 1 Clear N2Second16 OutMirror amp 0000FF F N2Thirdl6 OutMirror amp SFFFF00 100 Close Node 2 Node 2 Mirror word Second 16 bit register Third 16 bit register Open memory Save Initialize to zero or desired state Mask with lower 8 bits Mask OutMirror with upper 16 bits and shift to lower 16 Second 16 bit register third 16 bit register open memory node 2 node 2 E Note The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register Using the ACC 65E With MACRO 43 Accessory 65E Power 2 160 Mapping Example MI160 is used to transfer ACC 65E data through MACRO IC 0 node 2 of the ring controller which places the 24 bits of inputs and 24 bits of outputs in the same 24 bit data register The inputs are mapped into the 24 bits of node 2 Node 2 Node 2 16 bit Reg 1 nputl Gate2 nput2 gt Gate2 nput3 gt Gate2 nput4 gt Gate2 nput5 gt Gate2 nput6 gt Gat
22. X 78420 6 define Input8 M7008 nput8 gt X 78420 7 define Input9 M7009 nput9 gt X 78420 8 define Input10 M7010 nput10 gt X 78420 9 1 define 11 M7011 nputll 2X 78420 10 define Input12 M7012 nputl2 X 78420 11 define Input13 M7013 nputi3 5X 378420 12 define Inputl4 M7014 nput14 gt X 78420 13 define Input15 M7015 15 gt 578420 14 define Inputl16 M7016 nputli6 X 78420 15 define Inputl7 M7017 nputl7 X 78420 16 define Input18 M7018 nputl8 X 9 78420 17 define Input19 M7019 nputl9 X 9 78420 18 define Input20 M7020 nput20 gt X 78420 19 define Input21 M7021 nput21 gt X 78420 20 define Input22 M7022 nput22 gt X 78420 21 define Input23 M7023 nput23 gt X 78420 22 define Input24 M7024 Input24 gt X 78420 23 1 Using the ACC 65E With MACRO 15 38 Accessory 65E The outputs require an image word We will use Y 10FF 24 bits open memory register therefore the bitwise mapping of the outputs should point to the open memory define Outputl M7025 Outputl Y 10FF 0 define Output2 M7026 Output2 gt Y S10FF 1 define Output3 M7027 Output3 gt Y S10FF 2 define Output4 M7028 Output4 gt Y S10FF 3 define Output5 M7029 Output5 Y 10FF 4 define Output6 M7030 Output6 gt Y 10FF 5 define Output7 M7031 Output7 gt Y S10FF 6 define Output8 M7032 Output8 gt Y S10FF 7 define Output9 M7033 Output9 gt Y S 1
23. a aaa aa aa aaa aa aaa aa E a aa a aa a a a aaa a a 18 Ring Controller 4 551 senine sanan ar an aaa na aaa na Pena kana ga Ra bana kae en 20 Turbo PMAC2 I O Node Addressing 20 Power PMAC2 1 0 Node Addressing 21 Power I O Node Addressing 23 Configuring MACRO I O Transfers 25 MS anynode 60 1 1 26 MS farrynode MI7 1 30 MIOU MIZ 34 Accessing the Transferred 37 Outputs Mirror Image 37 Turbo PMAC2 MII160 Mapping 38 Turbo PMAC2 MI71 Mapping 40 Turbo PMAC2 MI69 70 Mapping 007 42 Power PMAC2 MII60 Mapping 44 Power PMAC2 MI71 Mapping Example 46 Power PMAC2 MI69 70 Mapping 46 Power MII60 Mapping Example enne eene eene 50 Table of Contents Accessory 65E Power MI71 Mapping 51 Power MI69 70 Mapping eene
24. 0FF 8 define Output10 M7034 Output10 gt Y S10FF 9 1 define Outputll1 M7035 Output11 gt Y S10FF 10 define Output12 M7036 Outputl12 Y 10FF 11 define Output13 M7037 Outputl13 Y 10FF 12 define Outputl4 M7038 Outputl4 Y 10FF 13 define Output15 M7039 Output15 gt Y S10FF 14 define Output16 M7040 Output16 gt Y S10FF 15 define Output17 M7041 Output17 gt Y S10FF 16 define Output18 M7042 Output18 gt Y S10FF 17 define Output19 M7043 Output19 gt Y S10FF 18 define Output20 M7044 Output20 gt Y S10FF 19 define Output21 M7045 Output21 gt Y S10FF 20 define Output22 M7046 Output22 Y 10FF 21 define Output23 M7047 Output23 gt Y S10FF 22 define Output24 M7048 Output24 gt Y S10FF 23 The following mirror image PLC which should be executing constantly will copy the outputs into node 2 define N2Twenty4 M7049 Node 2 24 bit data register define OutMirror M7050 Mirror word open memory N2Twenty4 gt Y 78420 0 24 Node 2 24 bit data register OutMirror gt Y S10FF 0 24 Open memmory register OutMirror 0 Save Initialize to zero or desired state Open PLC 1 Clear N2Twenty4 OutMirror Update data register Close The output states are now reported and can now be toggled E individually using the bitwise assignments to the open memory register Note Using the ACC 65E With MACRO Accessory 65E Turbo PMAC2 MI71 Mapping Example
25. 153 6 7 10 11 2 3 6 7 11 12 Ring Controller I O Node j 98 99 102 103 106 107 114 115 118 119 122 123 Using the ACC 65E With MACRO 24 Accessory 65E Configuring MACRO Transfers Having set up the following Ring Controller MACRO communication for ASCII and MS commands 16840 with Turbo PMAC2 Gate2 i MacroMode with Power PMAC2 Gate3 i MacroModeA and Gate3 i MacroModeB with Power PMAC3 MACRO Station MACRO communication for ASCII and MS commands MI996 Enabled the chosen I O nodes on the ring controller 16841 with Turbo PMAC2 Gate2 i MacroEnable with Power PMAC2 Gate3 i MacroEnableA and Gate3 i MacroEnableB with Power PMAC3 Enabled the corresponding I O nodes on the MACRO station IC MS anynode MI975 Typically masked with the enabled I O node s E g MS2 MI975 4 enables transfers using I O node number 2 Set up the I O Data Transfer Period MS anynode MI19 Typically 4 The ACC 65E s I O data should now be available to transfer to from the ring controller Each ACC 65E possesses 48 bits 24 in 24 out of data to be transferred Depending on the number of cards in the MACRO station and I O nodes available one or more of the following methods can be used stated in the order of simplicity gt gt gt MS anynode MI160 48 bit transfer into a 1 x 24 bit data register uses 1 x I O node MS anynode MI71 48 bit transfer into 2 x 24 bit data re
26. 2 6 define Output23 M7047 Output23 Y 078C05 6 define Input24 M7024 nput24 gt Y 078C02 7 define Output24 M7048 Output24 gt Y 078C05 7 To address a different card replace the xx digits in the address 7 locations 07xx00 to 07xx05 to correspond to the base address configured by the dip switch settings ote Configuring the Control Word With Turbo PMAC the control word must be set to 7 This is done by writing once on power up to the control register which is at base address 7 bits 7 0 7000 gt 5078 07 0 8 For base address 578 00 Open PLC 1 Clear M7000 7 Disable PLC 1 Close Using the ACC 65E with Turbo UMAC 16 Accessory 65E USING THE ACC 65E WITH MACRO In a MACRO configuration the ACC 65E resides typically in a UMAC MACRO Station with a MACROS legacy or MACRO16 CPU The ring controller can be either a Turbo or a Power PMAC UMAC MACRO Station 2 wo gt Turbo PMAC ring controllers D D Turbo Brick family Oo Turbo UMAC with 5 lt lt Turbo UltraLite IN gt Power PMAC ring controllers Bine cono Power Brick family Power UMAC with ACC 5E OUT Power UMAC with ACC 5E3 Power EtherLite MACRO16 ACC 65E ACC 65E UMAC MACRO Station 1 Generally the user s goal is to transfer the ACC 65E I O data 48 bits per card from to the ring controller by reading the 24 bits of inputs and writ
27. 21 DATS5 BD20 14 BD23 SEL5 BD22 15 BS1 DAT6 BSO 16 BAOI SEL6 BAOO 17 BAO3 DAT7 02 18 SEL7 04 19 CS3 06 CS2 20 BAO05 07 54 21 CS12 BAO08 510 22 516 BAO9 CS14 23 BAI3 BAIO 12 24 BRD BAII BWR 25 BS3 MEMCSO BS2 26 WAIT MEMCSI RESET 27 5 IREQI SERVO 28 PHASE IREQ2 SERVO 29 ANALOG GND IREQ3 ANALOG GND 30 15 Vdc PWRGND 15 Vdc 31 GND GND GND 32 5 Vdc 5 Vdc 5 Vdc 59 Connector Pinouts and Wiring Accessory 65E APPENDIX A E POINT JUMPERS Jumper Configuration Default Fl 6 gt 1 to 2 Turbo Power MACRO CPUs Revision 104 or newer Factory 2103 for Legacy MACRO CPUs Rev 103 or older Set gt 1 to2 to sample at Servo Rate ex E 1 2 gt 2 to 3 to sample at Phase Rate Appendix A E Point Jumpers 60 Accessory 65E APPENDIX B SCHEMATICS UA10 82705 1
28. 3 2 23 16 mE X 78426 23 16 Gate2 0 Macro 3 2 23 16 Gate3 0 MacroOutA 3 2 31 24 UMS X 78427 23 08 Gate2 0 Macro 3 3 23 08 Gate3 0 MacroOutA 3 3 31 16 Using the ACC 65E With MACRO 36 Accessory 65E Accessing the Transferred Data Having transferred the ACC 65E I O data to and from the MACRO station and into the ring controller s registers mentioned above bitwise mapping is the final step gt With the PMAC2 style MACRO IC The inputs can be bitwise mapped and read The output state is not reported and writing to two separate bits simultaneously without using the full word is not possible thus an image word is required gt With the PMAC3 style MACRO IC The inputs can be bitwise mapped and read The outputs can be directly bitwise mapped written to and reported Outputs Mirror Image Concept A mirror image is a memory location on the ring controller typically open or scratch memory that mimics the state of the ACC 65E outputs residing in the MACRO station This can be done in a PLC program The following are recommended memory registers to use gt Turbo PMAC Open Memory Registers 24 bits 10F0 10FF X and Y Power PMAC Open Memory Registers 32 bits unsigned Sys Udata i Use Sys Udata 1 Sys Udata 2 Sys Udata 3 single bits of open memory User writes to reads to
29. 3 6 7 11 12 Ring Controller I O Node J 18 19 22 23 26 27 Gate2 2 Station I O 2 3 6 7 10 11 Ring Controller I O Node j 34 35 38 39 42 43 Gate2 3 Station I O Node 2 3 6 7 11 12 Ring Controller I O Node 7 50 51 54 55 58 59 22 Using the ACC 65E With MACRO Accessory 65E Power Node Addressing PMAC3 style MACRO IC consists of 32 nodes 4 auxiliary 16 servo and 12 I O nodes One or more of these ICs can be found in the following hardware gt Power Brick Family gt Power UMAC with ACC 5E3 Power EtherLite I O Nodes 1 0 Nodes Node 31 30 L Auxiliary Nodes Servo Nodes Auxiliary Nodes Servo Nodes h EEEE Bank The Power PMAC can have up to 16 PMAC3 Style MACRO ICs ICs present are reported by the variable Macro IC3s gt Note A PMAC3 Style MACRO IC I O node consists of 4 data registers 1 x 24 bit and 3 x 16 bit residing in the following bit fields Style I O Node 24 bit Register 4 4 1 1 42 3 16 bit Register 1 16 bit Register 2 16 bit Register 3 23 Using the ACC 65E With MACRO 23 Accessory 65E With the PMAC3 Style MACRO ICs the I O node data registers are typically accessed using structure elements which can be inputs or outputs for either bank
30. 4 PS2705 1NEC 1 1 MMBESV4ALT1 MMBEZSVdALT MMBESVOALT MMBESV ALTI 4 D33 D35 2 3 x4 x4 joa oa oJ 2 2 C20 D57 D58 D59 D60 sl 0 1UF 0014 PS2705 1NEC MMBZ33VALT1G MMBZS3VALTIG C22 e ans 1 f 1 0 1UF RP32 Baja EUT 031 D36 X 4 2 2K Bein El 2 4 2 4 0 1UF UA16 PS27051NEC 1 i 4 colcol MMBZ33VALT1G MMBZSSVALTI GJ 4 j 1 13413 P AGING EM ACIN2 El IN12 t 1 RP37 2 16_ 52705 1 IN13 ao d 3 1 4 INTA E YN ali 5 YAN 2 Ci 5 NAAS s YAN ACIN2 E1 IN15 7 8 4 7 8 12 1 2K i UC16_PS2705 1NEC 1 1 MMBESV4ALT1 MMBESV6ALTI MMBESVOALT MMBESV ALTI 4 7 7 D39 2 3 2 f 2 c25 pe pez pes Zoe ED 0 1UF 0016 82705 1 MMBZ33VALT1G MMBZS3VALTIG C26 1 1 1 0 1UF RP38 ou AINT E 40 C28 Bi d Bi Ki 2 2K AINE 2 4 2 0 1UF UA18 PS2705 1NEC 1 4 colo teu RET 2 MMBZ33VALTIG _ MMBZ33VALTIG 1 1 4 2 ei 01 5 ACIN2 El IN16 1 APSO 2 1 RP51 2 UB18 52705 1 IN17 3 s L 5 4 1 4 WA ACIN1 C1 F3 IN18 SANE 4 RAP UNES 2 3 19 777 s ri 2 12 1 2K il UC18 PS2705 1NEC 1 1 MMBESV4ALT1 MMBESV6ALTI MMBESVOALT MMBESV ALTI Rr 041 1 2 3 2 2 pes pee pez nes RH s jan BOING Ei 0 1UF UD18 PS2705 1NE
31. 4 bits of outputs reside in the upper 00 byte of the second 16 bit register and the upper 16 bits of the 24 bits of outputs reside in the third 16 bit register ror E N w The inputs are mapped into 16 bit registers of node 2 define Inputl M7001 nputl X 78421 8 1 define Input2 M7002 nput2 X 78421 9 1 define Input3 M7003 nput3 5X 78421 10 1 define Input4 M7004 nput4 gt X 78421 11 1 define Input5 M7005 nput5 X 78421 12 1 define Input6 7006 nput6 X 78421 13 1 define Input 7 M7007 nput7 X 78421 14 1 define Input8 M7008 nput8 X 78421 15 1 define Input9 7009 nput9 gt X 78421 16 1 define Input10 M7010 nputl0 gt X 78421 17 define Input11 M7011 11 gt 578421 18 define Input12 M7012 12 gt 578421 19 define Input13 M7013 nputl3 gt X S78421 20 define Input14 M7014 14 gt 578421 21 define Input15 M7015 nputi5 X 9 78421 22 define Inputl6 M7016 ngputl6 X 978421 23 define Input17 M7017 nputl7 X 978422 8 1 define Input18 M7018 nputl8 X 9 78422 9 1 define Input19 M7019 nputi9 X 9 78422 10 define Input20 M7020 20 878422 11 define Input21 7021 nput21 gt 78422 12 define Input22 M7022 nput22 X 878422 13 define Input23 M7023 nput23 X 978422 14 define Input24 M7024 nput24 X 9 78422 15 Using the ACC 65E With MACRO 42 Accessory 65E The outp
32. 78C03 6 define Input8 M7008 nput8 gt Y 078C00 7 define Output8 M7032 Output8 gt Y 078C03 7 define Input9 M7009 nput9 gt Y 078C01 0 define Output9 M7033 Output9 gt Y 078C04 0 define Inputl10 M7010 nputl0 52Y 5078C01 1 define Outputl10 M7034 Outputl0 5Y 078C04 1 define Inputl11 M7011 nputl11 5 5Y 078C01 2 define Outputl11 M7035 Outputll1 5Y 078C04 2 define Input12 M7012 12 gt 5078 01 3 define Output12 M7036 Outputl2 5Y 078C04 3 define Input13 M7013 nputl3 5Y 078C01 4 define Output13 M7037 Outputl13 5Y 078C04 4 define Inputl14 M7014 nputl4 5Y 5078C01 5 define Outputl4 M7038 Outputl4 5Y 078C04 5 define Input15 M7015 nput15 gt Y 5078C01 6 define Output15 M7039 Outputl15 5Y 078C04 6 define Input1l6 M7016 nputl6 52Y 5078C01 7 define Outputl16 M7040 Outputl6 2Y 078C04 7 define Inputl17 M7017 17 gt 5078 02 0 define Outputl7 7041 Outputl7 2Y 078C05 0 define Input18 M7018 nput18 Y 078C02 1 define Output18 M7042 Outputl18 5Y 078C05 1 define Inputl19 M7019 nputl9 gt 8078C02 2 define Output19 M7043 Outputl19 5Y 078C05 2 define Input20 M7020 nput20 gt Y 078C02 3 define Output20 M7044 Output20 gt Y 078C05 3 define Input21 M7021 nput21 Y 98078002 4 define Output21 M7045 Output21 Y 078C05 4 define Input22 M7022 nput22 Y 9 078C02 5 define Output22 M7046 Output22 Y 078C05 5 define Input23 M7023 nput23 gt 8078C0
33. A 2 0 20 1 PTR Input14 gt Gate3 0 MacroInA 2 0 21 1 PTR Outputl4 5Gate3 0 MacroOutA 2 0 21 1 PTR Input15 gt Gate3 0 MacroInA 2 0 22 1 PTR Output15 gt Gate3 0 MacroOutA 2 0 22 1 PTR Input16 gt Gate3 0 MacroInA 2 0 23 1 PTR Outputl6 gt Gate3 0 MacroOutA 2 0 23 1 PTR Inputl17 gt Gate3 0 MacroInA 2 0 24 1 PTR Outputl7 gt Gate3 0 MacroOutA 2 0 24 1 PTR Input18 gt Gate3 0 MacroInA 2 0 25 1 PTR Output18 gt Gate3 0 MacroOutA 2 0 25 1 PTR Input19 gt Gate3 0 MacroInA 2 0 26 1 PTR Outputl19 gt Gate3 0 MacroOutA 2 0 26 1 PTR Input20 gt Gate3 0 MacroInA 2 0 27 1 PTR Output20 gt Gate3 0 MacroOutA 2 0 27 1 PTR Input21 gt Gate3 0 MacroInA 2 0 28 1 PTR Output21 gt Gate3 0 MacroOutA 2 0 28 1 PTR Input22 gt Gate3 0 MacroInA 2 0 29 1 PTR Output22 gt Gate3 0 MacroOutA 2 0 29 1 PTR Input23 gt Gate3 0 MacroInA 2 0 30 1 PTR Output23 gt Gate3 0 MacroOutA 2 0 30 1 PTR Input24 gt Gate3 0 MacroInA 2 0 31 1 PTR Output24 gt Gate3 0 MacroOutA 2 0 31 1 With Power PMAC3 the outputs can be directly bitwise mapped written to and reported Mirror word is not required Using the ACC 65E With MACRO 50 Accessory 65E Power MI71 Mapping Example MIT is used to transfer ACC 65E data through MACRO IC 0 Bank A nodes 2 and 3 of the ring controller which places
34. Accessory 65E DELTA TAU Data Systems Inc C e UL us NEW IDEAS IN MOTION Single Source Machine Control BAaRRsRASESAEASSTRARARRERSSRAARSSSZOSSSSSARSSSSSOSSASASSARESSSSTSSSSSESASERHHEUR Power Flexibility of Use 21314 Lassen St Chatsworth CA 91311 Tel 818 998 2095 Fax 818 998 7807 www deltatau com Accessory 65E Copyright Information 2015 Delta Tau Data Systems Inc All rights reserved This document is furnished for the customers of Delta Tau Data Systems Inc Other uses are unauthorized without written permission of Delta Tau Data Systems Inc Information contained in this manual may be updated from time to time due to product improvements etc and may not conform in every respect to former issues To report errors or inconsistencies call or email Delta Tau Data Systems Inc Technical Support Phone 818 717 5656 Fax 818 998 7807 Email support deltatau com Website http www deltatau com Operating Conditions All Delta Tau Data Systems Inc motion controller products accessories and amplifiers contain static sensitive components that can be damaged by incorrect handling When installing or handling Delta Tau Data Systems Inc products avoid contact with highly insulated materials Only qualified personnel should be allowed to handle this equipment In the case of industrial applications we expect our products to be protected from hazardous or conductive mat
35. C MMBZ33VALT1G MMBZS3VALTIG c31 c32 1 4 1 1 0 1UF 0 1UF RP52 2 AGANTI GTI paz D44 Ki 4 p J 2 2K AGINA ET 2 2 4 0 1UF UA20 82705 1 1 4 colcol MMBZ33VALT1G _MMBZ33VALT1G d Joa 31434 2 9 017 ACIN2 E1 IN20 1 RP56 2 1 57 2 x UB20 PS2705 iNEC IN21 S a 3 4 1 4 YN 2 YAN ACIN1 C1 IN22 5 4 SAN 2 3 IN23 7 8 2 Er 12 1 2K il UC20 PS2705 1NEC 1 1 MMBESV4ALT1 MMBESV6ALTI MMBESVOALT MMBESV ALTI 4 ACIN1 C1 KA pas x 4 D kan 4 12 2 2 2 cas D69 D70 D71 D72 0 1UF UD20 PS2705 1NEC MMBZ33VALT1G MMBZS3VALTIG c36 C37 1 1 0 1UF 0 1UF RP58 a cb Edu x 046 D48 698 A 4 2 RA 2 2K ET 24 24 0 1UF RET MMBZ33VALT1G MMBZ3SVALTIG j 134334 Appendix B Schematics 61 Accessory 65E PLANE
36. MBZ33VALT I Zener diodes Output Drivers The output drivers use the Diodes Inc Zetex ZXMS6006DG chip The current drawn from each output line should be limited to 600 mA at voltage levels between 12 VDC and 24 VDC and no more than 8 Amps total for all outputs simultaneously Specifications Accessory 65E Physical Specifications Terminal Block Layout 5 08 D Sub Layout TL Specifications Accessory 65E Description Specification Notes Length 16 256 cm 6 4 in Dimensions Height 10 cm 3 94 in Width 2 03 cm 0 8 in Weight w o Option 1A 180 g Front Plate included FRONT MC1 5 12 ST3 81 Terminal Block Connectors FRONT MC1 5 5 ST3 81 2 TUE FRONT MC1 5 3 ST3 81 DB Option Connectors DB15 Female UL 94V 0 The width is the width of the front plate The length and height are E the dimensions of the PCB See Layout section for physical dimensions Note Agency Approval and Safety Item Description CE Mark Full Compliance N55011 Class A Group 1 N61000 3 2 Class A N61000 3 3 N61000 4 2 N61000 4 3 N61000 4 4 N61000 4 5 N61000 4 6 N61000 4 11 EMC pri pri pri j pri tri ri t Safety N 61010 1 UL UL 61010 1 File E314517 cUL CAN CSA C22 2 No 1010 1 92 File E314517 Specifications 10 Accessory 65E Application of Council Directive 89 336 EEC 72 23 EEC Manufacturers Name
37. Manufacturers Address Delta Tau Data Systems Inc 21314 Lassen Street Chatsworth CA 91311 USA We Delta Tau Data Systems Inc hereby declare that the product Product Name Model Number And all of its options conforms to the following standards EN61326 55011 1997 1998 EN61010 1 EN61000 3 2 1995 A14 1998 EN61000 3 3 1995 EN61000 4 2 1995 Al 1998 EN61000 4 3 Al EN61000 4 4 EN61000 4 5 EN61000 4 6 EN61000 4 11 1995 1998 1995 1995 1996 1994 Date Issued Place Issued Mark of Compliance C Specifications Accessory 65E 603575 Electrical equipment for measurement control and laboratory use EMC requirements Limits and methods of measurements of radio disturbance characteristics of information technology equipment Electrical equipment for measurement control and laboratory use Safety requirements Limits for harmonic current emissions Criteria A Limitation of voltage fluctuations and flicker in low voltage supply systems for equipment with rated current lt 16A Criteria B Electro Static Discharge immunity test Criteria B Radiated radio frequency electromagnetic field immunity test Criteria A Electrical fast transients burst immunity test Criteria B Surge Test Criteria B Conducted immunity test Criteria A Voltage dips test Criteria B and C 11 May 2006 Chatsworth California USA Accessory 65E ADDRESSING THE ACC 65E Addr
38. R Input16 gt Gate2 0 Macro 2 0 5 1 PTR Input17 gt Gate2 0 Macro 2 0 PTR Input18 gt Gate2 0 Macro 2 0 dd PTR Input19 gt Gate2 0 Macro 2 0 PTR Input20 gt Gate2 0 Macro 2 0 Sulis PTR Input21 gt Gate2 0 Macro 2 0 20 1 PTR Input22 gt Gate2 0 Macro 2 0 21 1 PTR Input23 gt Gate2 0 Macro 2 0 22 1 PTR Input24 gt Gate2 0 Macro 2 0 23 1 u Note Bitwise mapping with PMAC2 style MACRO IC is supported starting with Power PMAC firmware version 1 5 8 215 Using the ACC 65E With MACRO 46 Accessory 65E The outputs require an image word We will use Sys Udata 1 open memory register to copy the 24 bits of node 3 to create the image word Therefore the bitwise mapping of the outputs Outputl U USER 4 0 1 Output2 gt U USER 4 1 1 PTR Output3 U USER 4 2 1 Output4 gt U USER 4 3 1 PTR Output5 gt U USER 4 4 1 PTR Output6 gt U USER 4 5 1 PTR Output7 gt U USER 4 6 1 PTR Output8 gt U USER 4 7 1 PTR Output9 gt U USER 4 8 1 PTR Output1l0 gt U USER 4 9 1 PTR Outputl11 U USER 4 10 1 PTR Output12 U USER 4 PTR Output13 gt U USER 4 12 1 PTR Output14 U USER 4 13 1 PTR Output15 gt U USER 4 14 1 PTR Output1l6 gt U USER 4 15 1 PTR Outputl17 U USER 4 16 1 PTR Output18 gt U USER 4 17 1 PTR Output19 gt U USER 4 18 1 PTR Output20 gt U USER 4 19 1
39. R Output24 gt Gate3 0 MacroOutA 2 131 31 With Power the outputs can be directly bitwise mapped written to and reported Mirror word is not required Using the ACC 65E With MACRO Accessory 65E Configuring the Control Word for MACRO The control word is configured automatically with MACRO16 CPU firmware version 1 204 and newer The setup below is for older firmware versions The control word be configured with MACRO using 98 and MI199 gt Set MII98 to 540000 base address 7 gt Set MI199 7 Configuring the Control Word must be done on every power up reset such as in the following example PLC which performs the configuration and then disables itself Example With ACC 65E at base addresses 8800 and using node 2 for MACRO Station communication Turbo PMAC ring controllers Open PLC Clear I5111 250 8388608 I10 WHILE 15111 gt 0 EndW CMD MS2 MI198 408807 Point to control word of Card 1 at address 8800 CMD MS2 MI199 7 Write to control word I5111 250 8388608 I10 WHILE I5111 gt 0 EndW Disable PLC 1 Close Power PMAC ring controllers Open PLC 1 CALL Timer 0 250 250 msec delay Requires loading the Timer subprogram CMD MACROSTATION2 MI198 408807 Point to control word of Card 1 at address 8800 CMD MACROSTATION2 MI199 7 Write to control word CALL Timer 0 250 Disable PLC 1 Disable this PLC Cl
40. Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits Inputs X 78420 23 00 Gate2 0 Macro 2 0 23 00 Gate3 0 MacroInA 2 0 31 08 Using the ACC 65E With MACRO 31 Accessory 65E MI71 example 2 Transferring I O data for two ACC 65Es at consecutive base addresses 8800 and 8900 over nodes 2 3 6 and 7 of MACRO IC 0 MS2 MI19 4 MS2 MI71 20C0A0218800 MS2 MI975 CC MACRO Station ACC 65E 8800 ACC 65E 9800 MS2 MI71 20C0A0218800 Ring Controller Having downloaded the above settings into the MACRO16 station the inputs and outputs are now available to access from the ring controller side e g I O nodes 2 3 6 and 7 in the following bit fields Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits 1 acc Inputs X 78420 23 00 Gate2 0 Macro 2 0 23 00 Gate3 0 MacroInA 2 0 31 08 65 Outputs X 78424 23 00 Gate2 0 Macro 3 0 23 00 Gate3 0 MacroOutA 3 0 31 08 514 Acc Inputs X 78428 23 00 Gate2 0 Macro 6 0 23 00 Gate3 0 MacroInA 6 0 31 08 9E Outputs X 7842C 23 00 Gate2 0 Macro 7 0 23 00 Gate3 0 MacroOutA 7 0 31 08 Using the ACC 65E With MACRO 32 Accessory 65E MI71 example 3 Transferring I O data for three ACC 65Es at consecuti
41. anae nennen 52 Configuring the Control Word for MACRO cbt aaa a RR aa na na 53 CONNECTOR PINOUTS AND WIRING 5 inane 54 Terminal Block 8 54 WI a 54 Bottom Outpils isse eiae ue nee eee Sieh ee ete eee E a a A 55 TB T TBI 56 D Sub 57 PODS TT iC PRIMERS EE Ep 57 Bottoni OUlputs ssa d ed hum 57 D Sub Wiring diagram a a aa aaa ea 58 UMAC Bus UBUS HEHEHE 59 APPENDIX X E POINT JUMPERS tede Ve ga pa eg NA 60 APPENDIX B s DENM NUMEN 61 APPENDIX USING THE ACC 65E IN s 63 ACC OIE CG Tibia 63 Locations the C E 64 Tunctton DescripllOns se cscs odd e RE 66 Example E 67 Table of Contents vi Accessory 65E INTRODUCTION The accessory 65E 65 is a general purpose digital input and output card It provides 24 inputs and 24 outputs of self protected optically isolated sinkin
42. appropriate node Bitwise mapping to user memory structure elements in Power PMAC is not allowed Explicit syntax with offset address must be used The offset address is found by multiplying the element structure index by 4 To the right is an example of the first 4 unsigned open memory structure elements and their corresponding address offsets Power PMAC use Sys Udata 0 therefore it is highly advised NOT A large number of self addressed default Sys pushm pointers fN to use it as a general purpose user memory Note Using the ACC 65E With MACRO Structure Address Element Offset Sys Udata 1 U USER 4 Sys Udata 2 U USER 8 Sys Udata 3 U USER 12 Sys Udata 4 U USER 16 37 Accessory 65E Turbo PMAC2 MI160 Mapping Example MI160 is used to transfer ACC 65E data through MACRO IC 0 node 2 of the ring controller which places the 24 bits of inputs and 24 bits of outputs in the same 24 bit data register Node 2 16 bit Reg 1 Node 2 16 bit Reg 2 Node 2 16 bit Reg 3 23 The inputs are mapped into the 24 bit register of node 2 define Inputl 7001 nputl X 78420 0 define Input2 M7002 nput2 X 78420 1 define Input3 M7003 nput3 gt X 78420 2 define Input4 M7004 nput4 gt X 78420 3 define Input5 M7005 nput5 gt X 78420 4 define Input6 M7006 nput6 gt X 78420 5 define Input7 M7007 nput7 gt
43. ards can share base addresses with Type B analog I O cards however in this case Type B cards naturally use the middle high bytes default so Type A cards should be set to the low byte of the selected base address Select of the Type B cards i e 578 00 578100 78E00 and 78F00 Conflicts can more simply be avoided by using only the Note second to fourth addresses of each Chip Select The above conflicts only occur with the first base address in each Chip Addressing The ACC 65E 14 Accessory 65E USING THE ACC 65E WITH POWER UMAC Using the ACC 65E with Power UMAC requires Knowing and configuring the index address offset of the card gt Declaring pointers with user given names to the appropriate I O structure elements Declaring Pointers to I O Structure Elements Mapping an ACC 65E at index 0 for example with user configurable pointer names Inputs PT 2 2 2 Z 9 9 9 WW nputl ACC65E nput2 gt ACC65E nput3 gt ACC65E nput4 gt ACC65E nput5 gt ACC65E nput6 gt ACC65E nput7 gt ACC65E nput8 gt ACC65E nput9 gt ACC65E nput1l0 gt ACC65E nput11 gt ACC65E nput1l2 gt ACC65E nput13 gt ACC65E nput14 gt ACC65E nput15 gt ACC65E nput1l6 gt ACC65E 7 gt ACC65E nput18 gt ACC65E nput19 gt ACC65E nput20 gt ACC65E nput21 gt ACC65E nput22 gt ACC65E nput23 gt ACC65E nput24 gt ACC65E nput oo o 0 00
44. cro 2 2 15 08 Gate3 0 MacroInA 2 2 23 16 X 78422 23 16 Gate2 0 Macro 2 2 23 16 Gate3 0 MacroOutA 2 2 31 24 SAIS X 78423 23 08 Gate2 0 Macro 2 3 23 08 Gate3 0 MacroOutA 2 3 31 16 Using the ACC 65E With MACRO 35 Accessory 65E MI69 70 example 2 Transferring I O data for two ACC 65Es at consecutive base addresses 8800 and 9800 over nodes 2 and 3 of MACRO IC 0 MS2 MI19 4 52 169 520 041318800 MS2 MI975 C Node 2 24 bit Reg M Having downloaded the above settings into the 16 station the inputs and outputs are now available to access on the ring controller side I O nodes 2 and 3 in the following bit fields 20C0A1318800 ACC 65E 8800 Ring Controller MACRO Station MS2 MI69 ACC 65E 9800 Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits X 78421 23 08 Gate2 0 Macro 2 1 23 08 Gate3 0 MacroInA 2 1 31 16 1 ACC X 78422 16 08 Gate2 0 Macro 2 2 16 08 Gate3 0 MacroInA 2 2 23 16 65 X 78422 23 16 Gate2 0 Macro 2 2 23 16 Gate3 0 MacroOutA 2 2 31 24 PS X 78423 23 08 Gate2 0 Macro 2 3 23 08 Gate3 0 MacroOutA 2 3 31 16 X 78425 23 08 Gate2 0 Macro 3 1 23 08 Gate3 0 MacroInA 3 1 31 16 2 ACC PM X 78426 15 08 Gate2 0 Macro 3 2 15 08 Gate3 0 MacroInA
45. e g Y 8800 Y 8900 Y 8A00 and places the data in 9 x consecutive 16 bit I O node data registers MI69 70 are 48 bit variables represented as 12 hexadecimal digits which are set up as follows digit 1 is leftmost when constructing the word No of consecutive nodes 1 for 110 node 2 for 2 10 nodes of 16 bit banks per board 3 for 3 IO nodes max Always 3 gt Reserved 0 Reserved 1 Starting I O node register Starting ACC 68E base address SCOXX i e 8800 For multiple ACC 65E transfers with 69 70 consecutive cards must be under the same chip select Note Using the ACC 65E With MACRO 34 Accessory 65E MI69 70 example 1 Transferring I O data for one ACC 65E at address 8800 over node 2 of MACRO IC 0 MS2 MI19 4 MS2 MI69 10C0A1318800 MS2 MI975 4 Node 2 24 bit Reg e 00 A m A lt Q A 65 8800 Ring Controller MACRO Station MS2 MI69 Having downloaded the above settings into the 16 station the inputs and outputs are now available to access on the ring controller side I O node 2 in the following bit fields Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits 78421 23 08 Gate2 0 Macro 2 1 23 08 Gate3 0 MacroInA 2 1 31 16 Inputs X 78422 15 08 Gate2 0 Ma
46. e put in a Global Includes file To switch add definitions to a different card change the ACC65E 0 E to ACC65E n where is the card index set by the dip switch settings Note With Power PMAC the control word is set up automatically by the EN firmware with ACC6SE n CtrIReg 7 Note Using the ACC 65E with Power UMAC 15 Accessory 65E USING THE ACC 65E WITH TURBO UMAC Using the ACC 65E with Turbo UMAC requires Assigning M Variables to I O Memory Locations Knowing configuring the base address of the card Pointing M Variables to the appropriate I O memory locations Configuring the control word Mapping an ACC 65E at 78 00 for example with user configurable M Variable numbers and name substitutions Inputs Outputs define Inputl M7001 nputl Y 078C00 0 define Outputl M7025 Outputl gt Y 078C03 0 define Input2 M7002 nput2 Y 078000 1 define Output2 M7026 Output2 gt Y 078C03 1 define Input3 M7003 nput3 gt Y 078C00 2 define Output3 M7027 Output3 gt Y 078C03 2 define Input4 M7004 nput4 Y 078C00 3 define Output4 M7028 Output4 gt Y 078C03 3 define Input5 M7005 nput5 gt Y 078C00 4 define Output5 M7029 Output5 gt Y 078C03 4 define Input6 M7006 nput6 Y 078000 5 define Output6 M7030 Output6 gt Y 078C03 5 define Input7 M7007 nput7 2Y 078000 6 define Output7 M7031 Output7 gt Y 0
47. e2 nput7 gt Gate2 nput8 gt Gate2 nput9 gt Gate2 nputl0 Gate2 nputll1 Gate2 nputli2 Gate2 nputl3 Gate2 nputl4 Gate2 nput15 gt Gate2 nputl6 Gate2 nputl7 Gate2 nput18 gt Gate2 nput19 gt Gate2 nput20 Gate2 nput21 gt Gate2 nput22 gt Gate2 nput23 Gate2 nput24 gt Gate2 oo o 0 000 oo 0000000000 2 Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro N N N N N N S DN N N N N N N N N N N S NNN N oo lt lt WW N F O oOo 00000000 Bitwise mapping with PMAC2 style MACRO IC is supported starting with Power PMAC firmware version 1 5 8 215 Note Using the ACC 65E With MACRO 44 Accessory 65E The outputs require an image word We will use Sys Udata 1 open memory register to create the image word therefore the bitwise mapping of the outputs Outputl U USER 4 0 1 Output2 gt U USER 4 1 1 PTR Output3 gt U USER 4 2 1 PTR Output4 gt U USER 4 3 1 PTR Output5 gt U USER 4 4 1 PTR Output6 gt U USER 4 5 1 PTR Output7 gt U USER 4 6 1 PTR Output8 gt U USER 4 7 1 PTR Output9 gt U USER 4 8 1 PTR Output1l0 gt U USER 4 9
48. erials and or environments that could cause harm to the controller by damaging components or causing electrical shorts When our products are used in an industrial environment install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture abnormal ambient temperatures and conductive materials If Delta Tau Data Systems Inc products are directly exposed to hazardous or conductive materials and or environments we cannot guarantee their operation A Warning identifies hazards that could result in personal injury or death It precedes the discussion of interest WARNING A Caution identifies hazards that could result in equipment damage It precedes the discussion of interest Caution Note identifies information critical to the understanding or use of d the equipment It follows the discussion of interest Note Accessory 65E REVISION HISTORY REV DESCRIPTION DATE CHG APPVD 1 Added CE Declaration 06 07 06 CP SF 2 Revs To J1 J2 Pins 8 15 05 11 07 CP AO 3 Reformatted Schematics 01 18 08 CP SF 4 Updated Max Current Output 01 29 08 CP SM 5 Added UL seal updated agency approval 10 01 09 CP SF 6 Added Power PMAC MACRO 02 24 14 RN RN Reformatted manual 7 Corrected DIP switch settings 02 03 15 RN RN Accessory 65E Table of Contents INTRODUC TH N rcar a deen 7 BPECIEICAT IONS aa aa nan
49. ess Select DIP Switch SW1 The switch SWI selects the starting address location for the first I O gate on the ACC 65E The following table shows the dip switch settings for the Turbo Power and MACRO Station settings Base Address SWI Positions Chip POWER Select TURBO MACRO Index 6 5 4 3 2 1 Base Offset ACC 65E n Y 78C00 Y 8800 A00000 0 ON ON ON ON ON ON asi Y 79C00 Y 9800 A08000 4 ON ON ON OFF ON ON Y 7ACOO Y A800 A10000 8 ON ON OFF ON ON 7 00 Y B800 A18000 12 ON ON OFF OFF ON ON Y 78D00 Y 8840 B00000 1 ON ON ON OFF Y 79D00 Y 9840 B08000 5 ON ON ON OFF ON OFF m Y 7AD00 Y A840 B10000 9 ON ON OFF ON ON OFF Y 7BD00 Y B840 B18000 13 ON ON OFF OFF ON OFF Y 78E00 Y 8880 C00000 ON ON ON OFF ON a Y 79E00 Y 9880 C08000 ON ON ON OFF OFF ON Y 7AE00 Y A880 C10000 10 ON ON OFF ON OFF ON Y 7BE00 Y B880 C 18000 14 ON ON OFF OFF OFF ON Y 78F00 Y 88CO D00000 3 ON ON ON ON OFF OFF dee Y 79F00 Y 98CO D08000 7 OFF OFF OFF Y S 7AF00 Y A8CO D10000 11 ON ON OFF ON OFF OFF Y 7BF00 Y B8CO D18000 15 ON ON OFF OFF OFF OFF ON designates Closed OFF designates Ope
50. g inputs and sourcing outputs The ACC 65E is a 3U Euro style card intended to plug into the UMAC BUS backplane It can be used with the Turbo UMAC CPU Power UMAC CPU MACRO UMAC Station MACRO16 CPU PMAC2 or Style Introduction 7 Accessory 65E SPECIFICATIONS Environmental Specifications Description Specification Notes Operating Temperature 0 C to 45 C Storage Temperature 25 C to 70 C Humidity 10 to 95 96 Non Condensing Electrical Specifications Power Requirements Whether providing the ACC 65E with power from the 3U backplane bus or externally standalone mode through TBI the power requirements 10 are 45V Board Logic Input 24 V 0 60 A Per Output Pin 24 V 8 00 A Maximum current when using all outputs simultaneously operation not to be confused with the 12 pin TB1 connector on either TB1 is a 2 pin 5V connector on the base board used for standalone Ey of the I O mezzanine boards Note Fuse Manufacturer Specification Delta Tau Part Number Brosnan 125 V 20A MDA 20A Input Drivers The inputs to the ACC 65E have an activation range from 12V to 24V Due to the self protecting circuitry the inputs can only be configured as sinking Although self protecting no more than 33VDC should be applied to any I O pin This is a limitation of the protective circuitry which includes M
51. g pana naen a DEDE MIRARI ERR NEM MM MNA NNNM OMM PME 8 Environmental Specifications aa Ke Na E 8 Electrical Speciicatioms iv ale aa aa 8 Power ZA REM 8 n anaa anana aana anaa aaa aaa aaa aaa a aaa a aaa aana a aaa aana a aaa a aaa a aaa a aa 8 Input DAVET Sersan er Ee 8 8 Physical Specifications uini eS ERU E CAS EUR CAE a RUE CAE AERE CHR FAR REO R 9 Terminal Block Layout 9 D Sub Layout iui weni san AA NA GG ARE AN NA A ENE E nai ai anan na india inan 9 Agency Approval and Safety KG AN 10 ADDRESSING THE AlCl LAI eee 12 Address Select DIP Switch 12 Legacy MACRO Dip Switch SENIN IS 13 Hardware Address Limitations 13 USING THE ACC 65E WITH POWER UMAC i ccccsccosescssssscssescscsesescssaccseseccsesescssacaseseccsenenosence 15 Declaring Pointers to I O Structure Elements sees enne nnne nennen nnne nnns 15 USING THE ACC 65E WITH TURBO UMAC 16 Assigning M Variables to Memory 16 Configuring the Control 2 GENG enne nennen 16 USING THE AC COSE WITH MACRO 17 16 VO Node Addressthg o o ETE aaa
52. gisters uses 2 x I O nodes MS anynode MI69 MI70 48 bit transfer into 3 x 16 bit data registers uses 1 x I O nodes anynode refers to any activated node on a particular MACRO IC Note MS anynode MI160 requires MACRO16 CPU firmware 1 204 or newer Note Using the ACC 65E With MACRO 25 Accessory 65E MS anynode MI160 MI160 transfers all 48 bits 24 in 24 out of an ACC 65E into a single read write 24 bit data register It handles up to 3 x ACC 65Es at consecutive base addresses e g Y 8800 Y 9800 Y A800 and places the data in 3 x consecutive 24 bit data registers MI160 is a 48 bit variable represented as 12 hexadecimal digits which are set up as follows digit 1 is leftmost when constructing the word No of consecutive nodes 1 for 11 0 node 2 for 2 1 0 nodes 3 for 3 1 0 nodes max sms 2 36 sa Reserved 0 Starting I O node register Starting ACC 65E base address COXX i e 58800 MI160 requires MACRO16 CPU firmware 1 204 or higher Note AN For multiple ACC 65E transfers with MI160 consecutive cards must d be under the same chip select Note Using the ACC 65E With MACRO 26 Accessory 65E 160 example 1 Transferring I O data for one ACC 65E at address 8800 over node 2 of MACRO IC 0 52 119 4 MS2 MI160 10C0A0008800 MS2 MI975 4 Data transfer period msec MI160 transfer Enable Mask I O node 2
53. he IN 24 bit data register of node 2 and the 24 bits of outputs in the OUT 24 bit data register of node 2 I O Node 2 Node 2 16 bit Reg 1 Node 2 16 bit Reg 2 Node 2 16 bit Reg 3 31 23 15 7 0 Inputs Outputs Inputl Gate3 0 MacroInA 2 0 8 1 PTR Outputl gt Gate3 0 MacroOutA 2 0 8 1 PTR Input2 gt Gate3 0 MacroInA 2 0 9 1 PTR Output2 Gate3 0 MacroOutA 2 0 9 1 PTR Input3 gt Gate3 0 MacroInA 2 0 10 1 PTR Output3 Gate3 0 MacroOutA 2 0 10 1 PTR Input4 gt Gate3 0 MacroInA 2 0 11 1 PTR Output4 Gate3 0 MacroOutA 2 0 11 1 PTR Input5 gt Gate3 0 MacroInA 2 0 12 1 PTR Output5 gt Gate3 0 MacroOutA 2 0 12 1 PTR Input6 gt Gate3 0 MacroInA 2 0 13 1 PTR Output6 Gate3 0 MacroOutA 2 0 13 1 PTR Input7 gt Gate3 0 MacroInA 2 0 14 1 PTR Output7 Gate3 0 MacroOutA 2 0 14 1 PTR Input8 Gate3 0 MacroInA 2 0 15 1 PTR Output8 Gate3 0 MacroOutA 2 0 15 1 PTR Input9 gt Gate3 0 MacroInA 2 0 16 1 PTR Output9 Gate3 0 MacroOutA 2 0 16 1 PTR Input10 gt Gate3 0 MacroInA 2 0 17 1 PTR Output1l0 gt Gate3 0 MacroOutA 2 0 Taly PTR Inputll gt Gate3 0 MacroInA 2 0 18 1 PTR Outputll 5Gate3 0 MacroOutA 2 0 8 1 PTR Input12 gt Gate3 0 MacroInA 2 0 19 1 PTR Outputl2 gt Gate3 0 MacroOutA 2 0 19 1 PTR Input13 gt Gate3 0 MacroInA 2 0 20 1 PTR Output13 gt Gate3 0 MacroOut
54. ing to the 24 bits of outputs This I O data transfer is accomplished using I O nodes therefore it is essential to know Which I O nodes are used Which MACRO station I O node addresses correspond to which Ring Controller I O node addresses Using the ACC 65E With MACRO 17 Accessory 65E 16 Node Addressing A MACRO IC consists of a number of auxiliary servo and I O nodes Auxiliary nodes are Master Control registers and are for internal firmware use gt Servo nodes carry information such as feedback commands and flags for motor control gt I O nodes are by default unoccupied and are configurable for transferring miscellaneous data The MACRO16 CPU is populated with two PMAC2 style MACRO ICs each consisting of 16 nodes 2 auxiliary 8 servo and 6 I O nodes the legacy MACROS has only one IC Nodes Auxiliary Nodes Servo Nodes Each I O node consists of one 24 bit and three 16 bit upper data registers AN The MACROS CPU is populated with only 1 PMAC2 Style MACRO EN Note Using the ACC 65E With MACRO 18 Accessory 65E The I O node data register addresses COXX for the two MACRO ICs on a station are MACRO Station IC 0 Node 2 3 6 T 10 11 24 bit X C0A0 X COA4 X COA8 X COAC X COBO X COB4 16 bit X COAI X C0A5 X C0A9 X COAD X COB1 X COBS
55. is used to transfer ACC 65E data through MACRO IC 0 nodes 2 and 3 of the ring controller which places the 24 bits of inputs in the 24 bit register of node 2 and the 24 bits of outputs in the 24 bit register of node 3 Node 2 I O Node Node 2 16 bit Reg 1 Node 3 16 bit Reg 1 Node 2 16 bit Reg 2 Node 3 16 bit Reg 2 x Node 2 16 bit Reg 3 Node 3 16 bit Reg 3 23 15 0 23 The inputs are mapped into the 24 bit register of node 2 define define define define define define define define define define define define define define define define define define define define define define define define nputl nput2 nput3 nput4 nput5 nput6 nput7 nput8 nput9 nput nput nput nput nput nput nput nput nput nput nput20 nput21 nput22 nput23 nput24 Q N H CO M7001 M7002 M7003 M7004 M7005 M7006 M7007 M7008 M7009 M70 0 M7011 M70 M70 M70 M70 M70 M70 M70 M70 1 Q 9 7020 7021 M7022 M7023 M7024 15 nputl X nput2 X nput3 X nput4 X nput5 X nput6 X nput7 X nput8 X nput9 X nput nput nput nput nput nput nput nput nput nput 0 gt gt 2 gt 3 gt 4 gt 5 gt 6 gt 7 gt 8 gt 9 gt nput20 gt X nput21 gt X nput22 gt X nput23 gt X nput24 g
56. n Factory default is all EN ON Note Addressing The ACC 65E 12 Accessory 65E Legacy MACRO Dip Switch Settings Chip Base Address SWI Positions Select Alternate 6 5 4 3 2 1 10 Y B800 Y FFEO ON OFF ON OFF OFF OFF ON ON 12 Y B840 5 8 ON OFF ON OFF OFF OFF ON OFF 14 Y B880 Y FFFO ON OFF ON OFF OFF OFF OFF ON 16 8 0 Y FFF8 ON OFF ON OFF ON ON OFF OFF Note The Legacy Macro base addresses are double mapped Set SW1 positions 5 amp 6 to OFF if the alternate addressing is desired Hardware Address Limitations Historically two types of accessory cards have been designed for the UMAC 3U bus type rack type A and type B cards They can be sorted out as follows Name Type Category Possible Number Maximum Number of Base Addresses of cards in 1 rack ACC 9E A General I O 4 ACC 10E A General I O 4 10 ACC 11E A General I O 4 ACC 12E A General I O 4 ACC 53E B Feedback 12 ACC 57E B Feedback 12 12 58 B Feedback 12 ACC 59E B Analog I O 12 ACC 14E B General I O 16 28 Analog 16 ACC 36E B Analog I O 16 ACC 65E B General I O 16 16 ACC 66E B General I O 16 ACC 67E B General I O 16 ACC 68E B General I O 16 ACC 84E B Feedback 12 12 Addressing The ACC 65E 13 Accessory 65E Addressing Type A and Type B accessory ca
57. o 2 2 13 PTR Input23 gt Gate2 0 Macro 2 2 14 PTR Input24 gt Gate2 0 Macro 2 2 15 Bitwise mapping with PMAC2 style MACRO IC is supported starting with Power firmware version 1 5 8 215 Note Using the ACC 65E With MACRO Accessory 65E The outputs require an image word We will use Sys Udata 1 open memory register to create the image word Therefore the bitwise mapping of the outputs PTR Outputl R Output2 gt Output3 Output4 gt Output5 gt Output6 Output7 Output8 Output9 Output10 Outputll Output12 Output13 Outputl4 Output15 8 9 Output Output Output Output Output20 Output21 Output22 Output23 Output24 U U U U U U U U U gt gt gt gt gt 2 gt 2 gt zi Wd 5d dd 5d uj 9 sd sU 9 9 fu m d USE a ti bi 5d De Q 5d ju Hj md id Hd md 5d wee Ud ond 9 x a GS GS GS aS ab S DB A BR BR BR BR e QQ N HO 1 9 20 421 522 229 Bitwise mapping to user memory corresponding address offsets structure elements is not allowed Explicit syntax with offset address must be used The offset address is found by multiplying the elemen
58. ose Using the ACC 65E With MACRO 53 Accessory 65E CONNECTOR PINOUTS AND WIRING Terminal Block Connectors Top Inputs TB2 Top Inputs Pin Function Description 1 Input Input 1 13 2 Input Input 2 14 3 Input Input 3 15 4 Input Input 4 16 5 Input Input 5 17 6 Input Input 6 18 7 Input Input 7 19 8 Input Input 8 20 9 Input Input 49 21 10 Input Input 10 22 11 Input Input 11 23 12 Input Input 12 24 123 TB3 Top Inputs Reference Return Pin Function Description 1 Inputs Return 01 08 2 Inputs Return 09 16 3 Inputs Return 17 24 Connector Pinouts and Wiring 54 Accessory 65E Bottom Outputs 1234 5 788101112 TB2 Bottom Outputs Pin Function Description 1 Output Output 1 13 2 Output Output 2 14 3 Output Output 3 15 4 Output Output 4 16 5 Output Output 5 17 6 Output Output 6 18 7 Output Output 7 19 8 Output Output 8 20 9 Output Output 9 21 10 Output Output 10 22 11 Output Output 11 23 12 Output Output 12 24 TB3 Bottom Outputs Power Pin Function Description 1 24 2 24V RETURN 3 24V Connector Pinouts and Wiring Accessory 65E TB Wiring Diagram Top Inputs 412 24V 12 24VDC Power Supply COM
59. ough MACRO IC 0 node 2 of the ring I O controller which places the data as illustrated on the right Node2 24 bit Register The lower 16 bits of the 24 bits of inputs reside in the first 16 bit register and the upper 8 bits of the 24 bits of inputs reside in the lower byte of the second 16 bit register The lower 8 bits of the 24 bits of outputs reside in the upper byte of the second 16 bit register and the upper 16 bits of the 24 bits of outputs reside in the third 16 bit register w The inputs are mapped into 16 bit registers of node 2 PTR Inputl gt Gate2 0 Macro 2 8 1 PTR Input2 gt Gate2 0 Macro 2 9 1 PTR Input3 Gate2 0 Macro 2 10 1 PTR Input4 gt Gate2 0 Macro 2 sist PTR Input5 gt Gate2 0 Macro 2 12 1 PTR Input6 gt Gate2 0 Macro 2 313 1 PTR Input7 gt Gate2 0 Macro 2 214 1 PTR Input8 gt Gate2 0 Macro 2 15 1 PTR Input9 gt Gate2 0 Macro 2 16 1 PTR Input10 gt Gate2 0 Macro 2 Ts PTR Inputll Gate2 0 Macro 2 8 PTR Input12 gt Gate2 0 Macro 2 22 PTR Input13 gt Gate2 0 Macro 2 20 PTR Inputl4 Gate2 0 Macro 2 21 PTR Input15 gt Gate2 0 Macro 2 e225 PTR Inputl6 gt Gate2 0 Macro 2 23 PTR Input17 gt Gate2 0 Macro 2 2 8 1 PTR Input18 gt Gate2 0 Macro 2 2 9 1 PTR Input19 gt Gate2 0 Macro 2 2 10 PTR Input20 gt Gate2 0 Macro 2 2 11 PTR Input21 gt Gate2 0 Macro 2 2 12 PTR Input22 gt Gate2 0 Macr
60. r file with the following preprocessor directive include acc65e h The same is true for RTICPLCs 1 Properties rticplc c File Properties od Solution PowerPmac2 1 project PowerPmac2 192 168 0 200 d C Language Background Programs Build Action 3 CPLCs B a bgcplc00 File Name rticplc c Full Path C Users gregs Documents P acc65e c n acc65e h sa Include n pp_proj h Libraries 4 gj 5 H 3g Realtime Routines Configuration Lj Documentation Log PMAC Script Language Appendix C Using The ACC 65E in C 65 Accessory 65E Function Descriptions ACC65E_SetControlWord Description This function sets the control word of ACC 65E Input Arguments CardNumber The Power PMAC I O Card Index of this card given in the table in the Addressing ACC 65E section of this manual corresponding to this card s I O base address offset Range 0 15 Return Value None returns void ACC65E_GetInputState Description This function returns the state of the input pin specified Input Arguments CardNumber The Power PMAC I O Card Index of this card given in the table in the Addressing ACC 65E section of this manual corresponding to this card s I O base address offset Range 0 15 InputNumber The pin number of the input pin whose state the user desires to read Inputs on ACC 65E are numbered 1 24 which i
61. rds in a UMAC or MACRO station rack requires attention to the following set of rules Populating Rack with Type A Cards Only no conflicts In this case the card s can potentially use any available Address Chip Select The type A cards have only one base address per chip select CS10 CS12 and CS14 Each card can be set up jumper settings to use the low middle or high byte of a specific base address This makes it possible to populate a single rack with 9 3 bases x 3 byte locations Type accessory cards A fourth address is available at CS16 in which only the high byte can be used thus making the maximum 10 Type A accessory cards Note Populating Rack with Type B Cards Only no conflicts In this case the card s can potentially use any available Address Chip Select Populating Rack with Type A amp Type B Cards possible conflicts Typically Type A and Type B cards should not share the same Chip Select If this configuration is possible then the following rules apply gt A Type B Feedback Cards Type A cards cannot share the same base address as Type B Feedback cards gt Type B General Cards Type A cards can share base addresses with Type B general I O cards however in this case Type B cards naturally use the lower byte default and Type A cards must be set to the middle high byte of the selected base address gt Cards and Type B Analog Cards Type A c
62. rror word is not required Using the ACC 65E With MACRO 51 Accessory 65E Power MI69 70 Mapping Example MI69 MI70 is used to transfer ACC 65E data through MACRO IC 0 Bank A node 2 of the ring controller which places the data as illustrated on the right The lower 16 bits of the 24 bits of inputs reside in the first 16 bit register and the upper 8 bits of the 24 bits of inputs reside in the lower byte of the second 16 bit register All in In registers The lower 8 bits of the 24 bits of outputs reside in the upper byte of the second 16 bit register and the upper 16 bits of the 24 bits of outputs reside in the third 16 bit register All in Out registers Node 2 Node 2 24 bit Register 31 23 15 7 Inputs Outputs PTR Inputl Gate3 0 MacroInA 2 164 PTR Outputl Gate3 0 MacroOutA 2 2 24 PTR Input2 gt Gate3 0 MacroInA 2 PUN PTR Output2 Gate3 0 MacroOutA 2 2 25 PTR Input3 Gate3 0 MacroInA 2 lt 18 PTR Output3 Gate3 0 MacroOutA 2 2 26 PTR Input4 gt Gate3 0 MacroInA 2 19 PTR Output4 Gate3 0 MacroOutA 2 2 27 PTR Input5 gt Gate3 0 MacroInA 2 20 PTR Output5 Gate3 0 MacroOutA 2 2 28 PTR Input6 gt Gate3 0 MacroInA 2 21 PTR Output6 gt Gate3 0 MacroOutA 2 2 29 PTR Input7 gt Gate3 0 MacroInA 2 22 PTR Output7 Gate3 0 MacroOutA
63. s the range for this argument Return Value Returns the state of the input pin 0 False Low Off 1 True High On ACC65E_GetOutputState Description This function returns the state of the output pin specified Input Arguments CardNumber The Power PMAC I O Card Index of this card given in the table in the Addressing ACC 65E section of this manual corresponding to this card s I O base address offset Range 0 15 OutputNumber The pin number of the output pin whose state the user desires to read Outputs on ACC 65E are numbered 1 24 which is the range for this argument Return Value Returns the state of the input pin 0 False Low Off 1 True High On ACC65E_SetOutputState Description This function sets the state of the output pin specified Input Arguments CardNumber The Power PMAC I O Card Index of this card given in the table in the Addressing ACC 65E section of this manual corresponding to this card s I O base address offset Range 0 15 Appendix C Using The ACC 65E in C 66 Accessory 65E OutputNumber The pin number of the output pin whose state the user desires to set Outputs on ACC 65E are numbered 1 24 which is the range for this argument Return Value None returns void Example Getting Inputs and Setting Outputs in a BGCPLC For a single ACC 65E at I O base offset B00000 this BGCPLC reads inputs 1 24 storing the values in P100 P123 respectively and writes to outputs 1
64. t Output 1 Output 13 2 Output Output 3 Output 15 3 Output Output 5 Output 17 4 Output Output 7 Output 19 5 Output Output 9 Output 21 6 Output Output 11 Output 23 7 Input 24V 8 Input 24 9 Output Output 2 Output 14 10 Output Output 4 Output 16 11 Output Output 6 Output 18 12 Output Output 8 Output 20 13 Output Output 10 Output 22 14 Output Output 12 Output 24 15 Return 24V RETURN Connector Pinouts and Wiring 57 Accessory 65E D Sub Wiring diagram Top Inputs 24 VDC Power Supply aa 6 O 43 42 4 49 9 Connector Pinouts Wiring Bottom Outputs 24 VDC Power Supply 12 24V api Output 11 23 Output 12 24 24V RET M 24VDC 6 4 43 42 4 49 9 58 Accessory 65E P1 UMAC Bus UBUS Connector P1 UBUS 96 Pin Header B322 1DOOOOOOOOOOO0O0O00000000000000000001lB1 Pin Row A Row B Row C 1 5 5 5 2 GND GND GND 3 01 DATO BD00 4 BD03 SELO BD02 5 BD05 DATI BD04 6 BD07 SELI BD06 7 BD09 DAT2 BD08 8 BDI1 SEL2 BD10 9 BD13 DAT3 BD12 10 BD15 SEL3 BD14 11 BD17 DAT4 BD16 12 BD19 SEL4 BD18 13 BD
65. t X 78420 0 78420 1 78420 2 78420 3 78420 4 78420 5 78420 6 78420 7 78420 8 784 784 784 784 784 784 784 784 784 784 784 784 784 784 784 20 9 1 20 10 20 11 20 12 20 13 20 14 20 15 6 7 8 20 20 20 20 19 20 20 20 21 20 22 20 23 Using the ACC 65E With MACRO 40 Accessory 65E The outputs require an image word We will use Y 10FF 24 bits open memory register to copy the 24 bits of node 3 therefore the bitwise mapping of the outputs should point to the open memory define Outputl M7025 Outputl Y 10FF 0 define Output2 M7026 Output2 gt Y S10FF 1 define Output3 M7027 Output3 gt Y S10FF 2 define Output4 M7028 Output4 gt Y S10FF 3 define Output5 M7029 Output5 Y 10FF 4 define Output6 M7030 Output6 gt Y 10FF 5 define Output7 M7031 Output7 gt Y S10FF 6 define Output8 M7032 Output8 gt Y S10FF 7 define Output9 M7033 Output9 gt Y S 10FF 8 define Output10 M7034 Output10 gt Y S10FF 9 1 define Outputll1 M7035 Output11 gt Y S10FF 10 define Output12 M7036 Outputl12 Y 10FF 11 define Output13 M7037 Outputl13 Y 10FF 12 define Outputl4 M7038 Outputl4 Y 10FF 13 define Output15 M7039 Output15 gt Y S10FF 14 define Output16 M7040 Output16 gt Y S10FF 15 define Output17 M7041 Output17 gt Y S10FF 16 define Output18 M7042 Output18
66. t structure index by 4 the right is an example of the first 4 unsigned open memory structure elements and their Structure Element Sys Udata 1 Sys Udata 2 Sys Udata 3 Sys Udata 4 Address Offset U USER 4 U USER 8 U USER 12 U USER 16 A large number of self addressed default Sys pushm pointers in Power PMAC use Sys Udata 0 therefore it is highly advised NOT E to use it as general purpose user memory Note The following mirror image PLC which should be executing constantly will copy the outputs into node 2 PTR N2Second16 gt Gate2 0 Macro 2 2 Node 2 Second 16 bit register upper 8 bits PTR N2Third16 gt Gate2 0 Macro 2 3 Node 2 Third 16 bit register upper 16 bits PTR OutMirror gt U USER 4 0 24 Mirror Word shared user memory OutMirror 0 Save initialize to zero or desired state Open PLC 1 N2Second16 OutMirror amp 0000FF lt lt 16 Update 2nd 16 bit reg shift to upper 16 bits N2Third16 OutMirror amp SFFFFOO Update node 2 third 16 bit register Close 15 Note The output states are now reported and can be toggled individually using the bitwise assignments to the open memory register Using the ACC 65E With MACRO 49 Accessory 65E Power MI160 Mapping Example MI160 is used to transfer ACC 65E data through MACRO IC 0 Bank A node 2 of the ring controller which places the 24 bits of inputs in t
67. te2 0 Macro 2 0 23 00 T 31 08 Outputs Gate3 0 MacroOutA 2 0 Inputs Gate3 0 MacroInA 3 0 2 ACC 65E X 78424 23 00 Gate2 0 Macro 3 0 23 00 31 08 Outputs Gate3 0 MacroOutA 3 0 Using the ACC 65E With MACRO 28 Accessory 65E 160 example 3 Transferring I O data for three ACC 65Es at consecutive base addresses 8800 9800 and A800 over nodes 2 3 and 6 MS2 MI19 4 52 1160 530 040008800 MS2 MI975 4C MACRO Station ACC 65E 8800 ACC 65E 9800 ACC 65E A800 Ring Controller MS2 MI160 30C0A0008800 Node 2 24 bit Register Node 3 24 bit Register Node 6 24 bit Register Having downloaded the above settings into the MACRO16 station the inputs can be read and outputs can be transferred from the ring controller side I O nodes 2 3 and 6 in the following bit fields Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits Inputs Gate3 0 MacroInA 2 0 1 ACC 65E X 78420 23 00 Gate2 0 Macro 2 0 23 00 31 08 Outputs Gate3 0 MacroOutA 2 0 Inputs Gate3 0 MacroInA 3 0 2 ACC 65E X 78424 23 00 Gate2 0 Macro 3 0 23 00 31 08 Outputs Gate3 0 MacroOutA 3 0 Inputs Gate3 0 MacroInA 6 0 3 65 X 78428 23 00 Gate2 0 Macro 6 0 23 00 31
68. the 24 bits of inputs in the In 24 bit data register of node 2 and the 24 bits of outputs in the Out 24 bit register of node 3 I O Node 2 I O Node Node 2 16 bit Reg 1 Node 3 16 bit Reg 1 Node 2 16 bit Reg 2 Node 3 16 bit Reg 2 31 tg tg g rg g rg g g iQ rg g rg PQ tQ 3 ded ded ded ded ded ded ded ded ded ded de ded ded ded ded Oed ded Oed ed ded ded Hi 5 Node 2 16 bit Reg 3 23 i Inputs nputl Gate3 0 Macro nput2 gt Gate3 0 Macro nput3 gt Gate3 0 Macro nput4 gt Gate3 0 Macro nput5 gt Gate3 0 Macro nput6 gt Gate3 0 Macro nput7 gt Gate3 0 Macro nput8 gt Gate3 0 Macro nput9 gt Gate3 0 Macro nput10 gt Gate3 0 Macro nput1l1 gt Gate3 0 nputi2 Gate3 0 Macro nputi3 Gate3 0 Macro nputl4 Gate3 0 Macro nputi5 Gate3 0 Macro nputl6 gt Gate3 0 Macro nputl7 gt Gate3 0 Macro nput18 gt Gate3 0 Macro nput19 gt Gate3 0 Macro nput20 gt Gate3 0 Macro nput21 gt Gate3 0 Macro nput22 gt Gate3 0 Macro nput23 gt Gate3 0 Macro nput24 gt Gate3 0 Macro N N N N N DN N N N N N N BN N N N N N N DN N N Oo C DO Q Cy C C O vel 9 1 10 wal 12 13 14 25 16
69. uts require an image word We will use Y 10FF open memory register to create an image word therefore the bitwise mapping of the outputs should point to the open memory define define define define define define define define define define define define define define define define define define define define define define define define Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output 1 2 3 4 5 6 7 8 9 0 1 2 3 4 9 6 8 9 20 21 22 23 24 M7025 M7026 M7027 M7028 M7029 M7030 M7031 M7032 M7033 M7034 M7035 M7036 M7037 M7038 M7039 M704 M704 M704 M704 M704 M704 M704 M704 M704 0 1 2 3 4 9 6 7 8 Outputl Y Output2 Y Output3 Y Output4 Y Output5 Y Output6 Y Output7 Y Output8 Y Output9 Y 0 Y l Y 2 gt 3 Y 4 Y 5 Y 6 gt Y 7 gt 8 Y 9 Y Output20 Y Output21 Y Output22 Y Output23 Y Output24 Y Output Output Output Output Output Output Output Output Output Output Xr Xo X 42 42 Xo rod Xo Xr Xr Xr X X X X X X X dX dX O O oo o zj 1 1 1 1 1 1 Tj QI
70. ve base addresses 8800 9800 and A800 over nodes 2 3 6 7 10 and 11 MS2 MI19 4 MS2 MI71 30C0A0218800 52 975 5 MACRO Station ACC 65E 8800 ACC 65E 9800 ACC 65E A800 MS2 MI71 30C0A0218800 Ring Controller Having downloaded the above settings into the 16 station the inputs and outputs are now available to access on the ring controller side I O nodes 2 3 6 7 10 and 11 in the following bit fields Turbo Power I O Node Data Structure Data Structure Data Address Bits Element PMAC2 Bits Element PMAC3 Bits 1t acc Inputs X 78420 23 00 Gate2 0 Macro 2 0 23 00 Gate3 0 MacroInA 2 0 31 08 95E Outputs X 78424 23 00 Gate2 0 Macro 3 0 23 00 Gate3 0 MacroOutA 3 0 31 08 24 Acc Inputs X 78428 23 00 Gate2 0 Macro 6 0 23 00 Gate3 0 MacroInA 6 0 31 08 6E Outputs X 7842C 23 00 Gate2 0 Macro 7 0 23 00 Gate3 0 MacroOutA 7 0 31 08 34 ACC Inputs X 78430 23 00 Gate2 0 Macro 10 0 23 00 Gate3 0 MacroInA 10 0 31 08 6E Outputs X 78434 23 00 Gate2 0 Macro 11 0 23 00 Gate3 0 MacroOutA 11 0 31 08 Using the ACC 65E With MACRO 33 Accessory 65E MS anynode MI69 MI70 MI69 MT70 transfers all 48 bits 24 in 24 out of an ACC 65E into x I O node 16 bit data registers It handles up to 3 x ACC 65Es at consecutive base addresses

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