Building Integrated ARINC 429 Interfaces using an FPGA
Contents
1. sfraddr for Core429 CPU address 7 0 parameter 6 0 WRITE ADDRESSO 7 h40 sfraddr for Core429 CPU address 8 and control bits parameter 6 0 WRITE ADDRESS1 7 h41 sfraddr for data written to Core429 parameter 6 0 WRITE DATA 7 h42 sfraddr for data read from Core429 parameter 6 0 READ DATA 7 43 In addition any application code running on the 8051 that requires communication with the 429 Bus Interface must follow some sort of communication protocol For the system shown in Figure 4 the protocol used is as follows Writing to ARINC 429 Core from 8051 Host 1 Write 8 bits of the 32 bit ARINC 429 data to WRITE DATA Mohan Land 4 2 Write lower 8 bits of 9 bit Core429 internal address to WRITE ADDRESSO 3 Write to WRITE ADDRESS with bit 0 MSB of 9 bit address bit 1 2 1 0 2 read 1 write 4 Wait until bit 2 of WRITE ADDRESSI 0 0 done 1 busy 5 Repeat steps 1 4 three more times until all 32 bits of ARINC 429 data 1s written Reading from ARINC 429 Core 1 Write lower 8 bits of 9 bit Core429 internal address to WRITE_ADDRESSO 2 Write to WRITE ADDRESSI with bit 0 MSB of 9 bit address bit 1 0 0 read 1 write 3 Wait until bit 2 of WRITE_ADDRESSI 0 0 done 1 busy 4 Read data from READ DATA 5 Repeat steps 1 4 three more times until all 32 bits of ARINC 429 data is read Note The 429 core s control and status registers as well as the label mem2. To write 32 bits of data the code above will be written within a loop as below rw 1 for byte 0 byte lt 4 byte if byte 0 else arinc data data out data out data out gt gt 8 arinc data data out arinc_addr byte reg tx rx channel arinc_wait Reading from Core429 To read 8 bits of data the following code can be used r w 0 arinc_addr byte reg tx_rx channel arinc_wait val RDATA To read 32 bits of data the following implementation can be used Mohan Land 17 P236 MAPLD 2005 r w 0 lim 4 for byte 0 byte lt lim byte arinc_addr byte reg tx_rx channel arinc_wait tmp RDATA data_i data_i tmp amp OxFF if byte lim 1 data i2 data i lt lt 8 Mohan Land 13 P236 MAPLD 2005 Appendix III Full size Illustrations RxHi RxLo DE EE DE nic TxLo Host CPU Core4 9 ARINC 429 BUS TxHi TxLo Er dmn mE Peripheral and 140 Devices Figure 1 General Core429 to Host Processor System Line Receiver ces ed e Interface a A hi Core429 Line Driver Figure 2 FPGA Based ARINC 429 IP Core Mohan Land 14 P236 MAPLD 2005 Core8051 8051 Main Engine Memory Control Timer 0 1 Interrupt Service RAM SFR Control Special Function Register Bus Fetch Instr Cycle Arithmetic Logic Unit Power d Management Serial Channel Clock Control Figure 3
3. clk reset n Notes i The following signals are active low attack ids uds as and VE MESE Address and Data Bus MESK CPU Glue Logic FPGA Core429 L e LLL mr H CPU IF Up ta 16 Tx and Rx Channals me TE Lx HET RxHi RxLo TxHi TxLa RxHi RxLo TxHi TxLa Figure 10 ARINC 429 IP Interfaced to the M68K Bus Address and Data Buses Glue Logic as r w cpu add 8 0 uds cpu din i 1 0 lds cpu dout i 1 0 dtack cpu wen data 15 0 cpu_ren addr 23 1 SRI 2 CPU DATA WIDTH 1 3 CAY DATA WIDTH should match the width of the MEGK data assumed here to be T6 bits 4 in 16 bit mode the M68K address bus ranges from addr 23 1 otherwise it would be adoar 23 0 Mohan Land Cored20 RxHi RxLa TxHi Tlo CPU I F 16 Tx and Rx Max RxHi RxLo me k MR MELN E l e HA ete Figure 11 Core429 to M68K Glue Logic 20 P236 MAPLD 2005 Sources Actel Corp ARINC 429 Bus Interface Datasheet Online document 2005 May v3 1 Available HTTP http www actel com ipdocs CoreARINC429 DS pdf Actel Corp Core8051 Datasheet Online document 2005 January v5 0 Available HTTP http www actel com ipdocs Core8051_DS pdf Motorola Inc M68000 8 16 32 Bit Microprocessors User s Manual Online document 1993 Ninth Edition Available HTTP http www freescale com files 32bit doc ref manual MC68000UM pdf Mohan Land 21 P236 MAPLD 2
4. 8051 Host CPU IP Core Block Diagram Mohan Land 15 P236 MAPLD 2005 RxHi RxLo TxHi TxLo Core8051 8051 CPU sr DR m mw A SFR I F Upto 16 Tx and Rx Channels RxHi RxLo TxHi TxLo e ME vwe O Peripheral and O Devices Figure 4 429 to 8051 Example System Glue Logic cpu add 8 0 sfraddr 6 0 cpu din i 1 0 sfrwa cpu dout i 1 0 SFR I F CPU I F sfrdataa 7 0 cpu wan sfrdatai 7 0 cpu ren cpu wait clk_ 16 reset n CLK 1MHZ Note CPU DATA WIDTH 1 Figure 5 Core429 to Core8051 Glue Logic Mohan Land 16 P236 MAPLD 2005 Processor Status hIC6GS0o Peripheral Control System antro Mec ADDRESS _GND 2 Bus Y CLK A23 A1 DATA BUS D15 D0 AS RAN Asynchronous a Bus Control FC1 DI FC OTAR E Zh Bus WMA Di Arbitration VPA Control BERR FLO 4 4 Interrupt RESET i e Control 4 HALT Figure 6 M68K Input and Output Signals 16 15 B 7 0 DO DI D2 D3 Eight DA Data DS Registers DE D7 16 15 D A Al A2 Seven A3 Address AJ Registers AS Ab Ay User Stack USP Pointer 31 Counter 7 0 Register Mohan Land Figure 7 M68K User Programmers Model 17 P236 MAPLD 2005 BUS MASTER ADDRESS THE DEVICE 1 Set RAN to READ 2 Place Function Code on FC2 FCU SLAVE 3 Place Address on 423 41 4 Assert Address Stroba AS 5 Assert Upper D
5. Figure 6 M68K Input and Output Signals For a visual representation of the M68K User Programmer s Model see Figure 7 31 16 15 B 7 0 D3 Eight Data 1 Registers E 31 16 15 Seven 143 Address AA Registers USF Polnter lnc Program Counter 7 D CER Status Register Figure 7 User Programmer s Model P236 MAPLD 2005 The registers DO D7 are used as data registers for byte word and long word operations The registers AO A7 are used as address registers that can be used for word and long word operations Each address register holds a full 32 bit address When an address register is used as a source operand either the low order word or the entire long word operand is used depending on the operation size When an address register is used as the destination operand the entire register is affected regardless of the operation size If the operation size is word operands are sign extended to 32 bits before the operation is performed Note that A7 is the User Stack Pointer and is used to keep track of the address of the top of the user stack In the following section the M68K 16 bit bus operation will be described in more detail For a more detailed description of the Motorola 68000 family of processors refer to the M68000 Microprocessor User s Manual and the corresponding Programmer s Reference Manual M68K 16 Bit Bus Operation Data transfer between devices involves the M68K address
6. 4 4 Assert Address Strobe m 5 Assert Upper Data Strobe QUDZ A and Lower Data Strobe LD5 SLANE INPUT THE DATA 13 Decode Address 2 Place Data an D 15 Do 353 Assert Data Transfer Acknowledge DTACE ACQUIRE THE DATA 1 Latch Data 2 Num TDs and TES 3 Negate 43 TERMINATE THE CYCLE 1 Remove Data from D15 Do 2 Negate DTACE START NEXT CYCLE Figure 8 68000 Word Read Cycle Flowchart BUS MASTER SLAVE ADDRESS THE DEVICE 1 Place Funcion Code on FC2 FCO SI Place Data on DIS D0 INPUT THE DATA 6 Assert Upper Data Strobe LDS and Lower Data Strobe fee Tj Decode Address 2 Store pu DE Dp15 Do 3 Assert Data Transfer Acknowledge IDTACK 1 Negate ODS and DS 2 Negate A5 zi Remove Data rm D15 D 4 Set RA to Rea TERMIMATE THE CYCLE 1 Negate DTACE START NEXT CYCLE Figure 9 68000 Word Write Cycle Flowchart ARINC 429 IP Interfaced to M68K When interfacing the 429 IP to a M68K host processor several considerations must taken into account For example if using a 20 MHz M68K processor it would be convenient to configure the 429 IP to also operate at 20 MHz which is one of its supported operating speeds Another configuration setting that should not be overlooked 1s the Data Bus Width If using an M68K with a 16 bit data bus the CPU_DATA_WIDTH parameter in the 429 IP should be set to 16 bits Although there are many configurations possible interfacing ARINC 429 and th
7. Name Type Description been physically implemented in the Actel Core429 cpu_ren In Development Kit on which both cores operate off a active low common 16 MHz clock This is the typical operating CPU write enable frequency of the 8051 core when implemented in an ni active low Actel ProASICE4 FPGA and it is also one of the four cpu_add 8 0 CPU address selectable clock speeds supported by the ARINC 429 cpu_din i 1 0 CPU data input Bus Interface IP core cpu dout i 1 0 CPU data output intel Out Interrupt to CPU active high Indicates that the Mohan Land 3 P236 MAPLD 2005 CPU should hold cpu_ren or cpu_wen active while the core completes the read or write operation Note i CPU DATA WIDTH Table 3 CPU Interface Signals Glue Logic In the ARINC 429 system depicted in Figure 4 the 8051 SFR Interface is tied to the 429 CPU Interface by glue logic Figure 5 shows a block diagram of this logic Glue Logic cpu add 8 6 sfraddr 6 0 cpu din 1 1 0 stre cpu_dout 1 1 0 SFR IF sirdatao 7 0 cpu wen strdatal 7 0 cpu ren cpu walt ck 16 CLK_1MHZ reset_n Figure 5 Core429 to Core8051 Glue Logic As previously mentioned the sfraddr is a 7 bit value which is used to address each of the four SFRs implemented This can be done in verilog by creating parameters to which the sfraddr input can be compared For example the following can be used to decode the sfraddr input
8. busy 1 bO cpu count lt PULSE WIDTH delay to ensure inter write timing end if cpu_ren 1 bO amp amp cpu waitm 1 bO wait for read to complete begin cpu ren lt 1 b1 cpu busy 1 bO datalatch 2 cpu dout latch the data from the ARINC core cpu count lt PULSE WIDTH end end nd Provide data read back to the SFR system For test reasons provide full read back on the register set Note decoding only uses the lowest 2 bits to select from the 4 registers ensure that this matches the bit encodings set above always sfraddr cpu_din cpu_address cpu_busy cpu_write datalatch int_out beg in case sfraddr 1 0 2 b00 sfrdatai cpu_address 7 0 2 b01 sfrdatai 4 b0 int out cpu_busy cpu write cpu address 8 2 b10 sfrdatai cpu din default sfrdatai datalatch endcase end Mohan Land 10 P236 MAPLD 2005 Appendix II 8051 Application Code for a 429 to 8051 System In the C program the SFRs used in the current implementation are declared as follows sfr ADDR1 0xC0 address for Core429 to decode bits 7 0 sfr ADDR2 OxCl bit 0 msb of 429 addr bit 1 R W bit 2 Done Busy sfr DATA OUT 0xC2 data written to Core429 sfr RDATA 0xC3 data read from Core429 For this particular system implementation and communication protocol a few low level C Functions can be used to read and write to Core429 Examples of this can be found be
9. connected the blocks but did not see a handshake between the 8051 and the ARINC 429 IP A logic analyzer was used to investigate the problem focusing on the SFR interface because we suspected that was where the problem would reside After a minor bit of redesign of the glue logic and application code we were able to achieve a handshake between cores Once the handshake was completed we could then test the setup in a series of tests from a basic loop back test to tests agains an ARINC 429 standard tester A Hotek Datair 400 was used to verify operation against the ARINC 429 standard We have found that standard testers are excellent tools to objectify the development of a core or subsystem This effort was no exception and our resulting subsystem is documented in the Core429 Development Kit The kit is used for demonstration evaluation prototyping and verification purposes It contains the application code used in testing which can be used as is or as a template When used as delivered the 8051 application code included provides the user with an automatic demonstration of ARINC 429 data being transmitted via a 429 bus using the supplied DB9 cable This could be used to interface with another ARINC 429 device via the 429 bus and cable provided The demonstration includes a command mode with a terminal interface that operates via a PC s serial port Example 2 ARINC 429 Interfaced to a Motorola 68000 Host MPU The following secti
10. internal or external to the FPGA To overcome the restricted memory map it was necessary to create an indirect addressing capability This was done by using memory mapped registers to hold the address and the corresponding P236 MAPLD 2005 data This method has been used in the 429 to 8051 system described below In fact four byte sized registers are used These registers were conveniently mapped to the 8051 SFR address space EXAMPLE 1 ARINC 429 IP Core Interfaced to 8051 Host ARINC 429 can be interfaced to an 8051 host by using the external SFR interface mentioned above One implementation of this ARINC 429 System can be Figure 4 429 to 8051 Example System seen in Figure 4 This system requires the use of four SFRs In order to interface these cores consideration must be taken when specifying the particular Core429 Core8051 configuration For example the 429 IP used supports SER 8 Bit SFR 7 Bit CPU data bus widths of 8 16 and 32 bits In this Address Address system an 8 bit width is used to match the 8051 bus width Also note that the 429 IP core s internal registers LL a x are addressed by a 9 bit CPU address which is described E OxCl 0x41 bit 0 MSB of Core429 in Table 1 register address bit 1 1 Write O Read bit 2 1 Busy 0 Done bits 3 7 Not used byte of data written to Core429 Table 1 ARINC 429 IP Core 9 Bit CPU Address byte di dead em Since the SFR Interface has an 8 bit data width Core4
11. logic 0 6 When UDS LDS and AS are de asserted stop driving data 15 0 and de assert DTACK Note The above description is for a 16 bit read write For 8 bit operations on Core429 control registers status registers and label memory only one of either UDS or LDS will be asserted at a time Refer to Appendix I for an example of control signals and parameters such as IGNORE_WAIT and cpu_waitm that might be useful considerations when implementing glue logic for a 429 M68K system Another important consideration when designing an ARINC 429 to M68K system is the application and use of this system There are many applications that would be more efficiently implemented by using M68K interrupts to indicate to the program in execution that an ARINC 429 event has occurred In the 8051 application discussed earlier the ARINC 429 system was part of a terminal interface that continually waited for a user to issue commands via a keyboard and the polling approach P236 MAPLD 2005 was an acceptable solution In fact most applications benefit from the use of interrupts including with an 8051 controller over the register polling approach used in Example 1 because it frees up the processor to run other applications Therefore to completely specify the glue logic that would interface the ARINC 429 IP to a M68K processor the interrupt lines IPLO IPL1 and IPL2 would have to be interfaced with Core429 Refer to the Motorola M68000 Micropr
12. 005
13. 2 two SFRs are required to hold the 429 9 bit CPU address In addition one SFR is required for data written to the 429 Bus Interface by the 8051 and one SFR for External Function Pape NN ae ee ee MSB Bit Positions LSB Table 2 SFR Usage for the 429 to 8051 System data read from the 429 by the 8051 Furthermore since CPU Interface only one bit is required for the MSB of the 9 bit CPU address it only occupies bit O of the SFR This leaves The CPU interface allows access to the 429 bits 1 to 7 available for control handshaking functions core s internal registers FIFO and internal memory In this implementation bit 1 of this SFR is used to This allows the system CPU Core8051 to read write indicate whether the requested operation is a read or a ARINC data to the FIFO to access the ARINC 429 write Bit 2 is used to indicate when the 429 core is busy control and status registers and to write to the 429 or done processing the request The SFRs implemented internal label memory Table 3 provides a signal are summarized in Table 2 description of the Actel ARINC 429 CPU Interface This interface is synchronous to the 429 core s Another advantage of this approach is that a master clock Note that CPU data out is asynchronous small amount of glue logic can be used to implement to the CPU clock for all register reads any interface logic required if the 8051 and the ARINC _ 429 cores are in the same clock domain This system has
14. Building Integrated ARINC 429 Interfaces using an FPGA R Mohan I Land Actel Corporation Mountain View California ABSTRACT The demand for custom logic within today s avionics industry has led to the increase of Field Programmable Gate Arrays FPGAs in aircraft electronic systems This demand along with technological advances in size and speed are resulting in the integration of multiple electronic functions into one chip ARINC 429 a mature avionics standard and still a very popular communications bus in commercial aircraft is one such system that is now being integrated with other functions in one chip To accomplish this designers are starting to look to pre built Intellectual Property IP to build these System on a Chip SOC FPGA designs also known as Programmable System Chips PSC An ARINC 429 bus interface is used in systems that require a host processor This paper discusses the integration of a host processor with an ARINC 429 intellectual property core The bus interface and its host processor functions can both be implemented within one FPGA using pre built IP to ease integration and shorten the system design process This paper discusses two examples of ARINC 429 with a host processor The first example incorporates a high performance 8 bit 8051 microcontroller The second generalizes that result to an ARINC 429 to Motorola 68000 system INTRODUCTION Bus interfaces such as ARINC 429 MIL STD 1553 and Ethern
15. ata Strobe UDS and Lower Data Strobe LD5 INPUT THE DATA 2 Decode Address Place Data on D15 DO 3 Assart Data Transfer Acknowledge DTACK ACQUIRE THE DATA Latch Data 2 Negate UDS and LDS 3 Negate 45 TERMINATE THE CYCLE gt Remove Data from D 15 DO 2 Negate DTACK START NEXT CYCLE Figure 8 68000 Word Read Cycle Flowchart BUS MASTER SLAVE ADDRESS THE DEVICE 1 Place Function Code on FC2 FCO 2 Place Address on 423 A1 Fi Assert Address Strobe A5 4 Set RAW to Write 5 Place Data on DISDO 6 Assert Upper Data Strobe UDS and Lower Data Strobe LDS 1 Decode Address 2 Store Data on D15 D0 3 Assert Data Transfer Acknowledge TERMINATE OUTPUT TRANSFER 1 Negate UDS and LDS 2 Negate AS i Remove Data from D15 00 4 Set R N to Read TERMINATE THE CYCLE 1 Negate DTACK START NEXT CYCLE Figure 9 68000 Word Write Cycle Flowchart Mohan Land 18 P236 MAPLD 2005 50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 515051 2 53 54 W W WWW 5556 57 CLE FC2 FCO a AAA A La c L Ta cc HN auc A mx a MM S TS TA NS ee a AIIIIAmA uiuaAAI TP_JLJLJ RA SONATA fT 915 08 25 22 97 00 A O pe i 2 WAIT STATE READ READ WRITE Supplemental Figure 68000 Read and Write Cycle Timing Diagram Mohan Land 19 P236 MAPLD 2005 Peripherals VO Devices RAM etc
16. bus Al to A23 the data bus DO to D15 and the associated asynchronous bus control signals The M68K address bus is a 23 bit unidirectional three state bus capable of addressing 16 MB of data The data bus is a 16 bit bidirectional three state bus that provides the general purpose data path for M68K data transfer During a read cycle the processor receives either one or two bytes of data from the peripheral device or from memory When the instruction specifies a word or a long word operation both the upper and lower bytes are read which requires assertion of both upper and lower data strobes UDS and LDS respectively For a byte sized operation the M68K uses the internal AO bit to determine which byte to read If AO is zero the upper data strobe is used and if AO is one the lower data strobe is used See Figure 8 for a flowchart of the M68K word read cycle During a write cycle the processor sends bytes of data to the peripheral device or to memory When a word operation is specified both UDS and LDS are asserted and both bytes are written For byte operations when the internal bit AO is 0 UDS is asserted and when AO is 1 LDS is asserted See Figure 9 for a flowchart of the M68K word write cycle For more information about M68K bus operation and timing refer to the M68000 Microprocessor User s Manual Mohan Land 6 BLIS MASTER ADDRESS THE DEVICE 1 Set RAW to READ 2 Place Function Code on d FCO 3 Place Address on 423
17. e M68K can be accomplished by directly mapping the internal 9 bit CPU address to the relatively large M68K address bus See Figure 10 for an example 429 M68K system P236 MAPLD 2005 Peripherals UC Darco RAM etc Mesh CFU 33 Ex ER je ww HA Up to 16 Tx and Rx Channels 33 EE ET pa E A ww DOTA Figure 10 ARINC 429 IP Interfaced to the M68K Bus Address and Data Buses This interface requires that a 9 bit address space in the M68K memory map be reserved for communication with the 429 Bus Interface IP For example one could reserve addresses 0x00000000 Ox000001FF for 429 communications unless this address space is pre reserved by the M68K Note that if there are less than 8 Tx and 8 Rx ARINC 429 channels implemented the MSB of the 9 bit 429 address will always be zero Refer to Table 1 for a more detailed explanation of this 9 bit address The approach described above also requires a small amount of glue logic to connect the 429 CPU Interface to the M68K address and data buses CPU Interface The 429 CPU Interface performs the same function as it does when interfacing to the 8051 However based on the variation of M68K used the width of the cpu_dout and cpu_din signals will be different See Table 3 for more information Glue Logic In the 429 M68K system depicted above the glue logic block is used to interface the 429 CPU Interface to the M68K address and data bus A block dia
18. ented in hardware as below always posedge clk 16 or negedge reset n begin if reset n 1 b0 begin cpu write lt 1 bO cpu wen lt 1 b1 cpu ren lt 1 b1 cpu_din lt 8 b0 cpu_address lt 9 b0 datalatch lt 8 b0 cpu busy lt 1 bO cpu start lt 1 bO cpu count lt 0 end else begin Firstly capture the SFR Writes to local registers if sfraddr WRITE DATA amp amp sfrwe 1 b1 begin cpu din lt sfrdatao end if sfraddr WRITE ADDRESSO amp amp sfrwe 1 b1 begin cpu address 7 0 sfrdatao end if sfraddr WRITE ADDRESS 1 amp amp sfrwe 1 b1 amp amp cpu busy 1 b0 begin cpu address 8 lt sfrdatao 0 cpu write sfrdatao 1 1 indicates a write O indicates a read cpu start 1 b1 start the cycle cpu busy lt 1 b1 end Now do the Access Cycle Must wait for count to get to zero before starting to make sure ARINC core sees inactive strobe if cpu start 1 b1 amp amp cpu count 0 assert cpu ren or cpu wen and hold asserted begin cpu wen lt cpu write cpu ren cpu write cpu count lt PULSE WIDTH Miniumn cycle of 31 clocks cpu start lt 1 b0 Mohan Land 9 P236 MAPLD 2005 e end end if cpu_count 0 begin cpu_count lt cpu_count 1 end else begin if cpu_wen 1 b0 amp amp cpu waitm 1 bO wait for write completes begin cpu wait is active high cpu wen lt 1 b1 cpu
19. et MAC are used in systems in which there is a host processor controller The external CPU requirement for the ARINC 429 Bus Interface IP core is necessary to set up the core s control registers and initialize the label memory Since ARINC 429 operates at either 12 5 KHz or 100 KHz an 8 bit microprocessor such as an 8051 can fulfill the host requirement The following sections will provide a brief overview of ARINC 429 accompanied by background information on the FPGA based 429 IP core Actel Core429 and 8051 CPU IP core Core8051 Similarly the second design example begins with a description of the Motorola 68000 Both examples start with a high level system block diagram discuss interfaces on the ARINC 429 IP and the respective host CPU and outlines the logic used to connect these blocks together Mohan Land 1 Along with the hardware considerations a brief discussion of the CPU to 429 communication protocol 1s provided Lastly a few notes on application software for each respective CPU are included to depict a complete solution Figure 1 shows a high level block diagram of the general system being described Depending on the specific configuration and host CPU both the ARINC 429 and the host CPU can reside within one FPGA as shown in Figure 4 Cored25 Peripheral and VO Devices Figure 1 General 429 to Host Processor System ARINC 429 Overview ARINC 429 is a two wire point to point data bus that is application s
20. face to allow the 429 IP to communicate with the 8051 SFR Interface the external SFRs implemented within the 429 core must be addressed by this 7 bit address For example an SFR implemented in the 8051 at address 0xCO is addressed by the external peripheral at 0x40 Mohan Land 2 Core8051 8051 Maln Engine Timer Q 1 Interrupt Service Spedal Function Register Bus Arithmetic Logic Unit Serial ls Channel i Clock fel Control Figure 3 8051 Host CPU IP Core Power Management One important consideration is the memory map configuration used by the 8051 CPU There are four separate memory regions used in the 8051 IP core DATA CODE XDATA and SFR memory regions DATA memory is 256 bytes and is used for dynamic storage of program data such as register stack and variable data Although this memory is 256 bytes typically only the lower 128 bytes are directly addressable for program data When the upper 128 bytes of DATA memory are addressed this points to the SFR memory region which is a combination of internal core memory and external memory for Special Function Registers CODE space is 64 kb and is used for program storage and interrupt vectors Lastly XDATA memory is 64 kb and is used for storage of large data sets custom designed peripherals and extended stack space if necessary CODE DATA and XDATA memory spaces are not part of 8051 IP core and must therefore be implemented by the user either
21. gram of this logic can be seen in Figure 11 This glue logic maps signals to the protocol described in this section as well as ensures the appropriate control signals are implemented for Core429 timing Figure 11 Core429 to M68K Glue Logic Mohan Land 7 Notes for Figure 11 1 The following signals are active low dtack lds uds as kw 2 i CPU DATA WIDTH 1 3 CPU DATA WIDTH should match the width of the MOSK data assumed here to be 16 bits 4 In 16 bit mode the M68K address bus ranges from addr 23 1 otherwise it would be addr 23 0 Writing to ARINC 429 IP Core Ensure that addr 23 1 is within the range of addresses reserved for Core429 communication that the AS input is a logic 0 and that R W is 0 to indicate a write 2 If UDS and LDS are logic 0 along with R W then assert cpu wen and assign addr 9 1 to cpu add 8 0 and data 15 0 to cpu din Wait until cpu wait is a logic 0 Drive DTACK to a logic 0 When UDS LDS and AS are de asserted and R W is no longer set to write de assert DTACK Un DB VW Reading from ARINC 429 IP Core 1 Ensure that R W is set to read that addr 23 1 is within the range of addresses reserved for Core429 communication and that the AS input is a logic 0 2 If UDS and LDS are logic 0 with R W set for read then assert cpu_ren 3 Assign addr 9 1 to cpu_add 8 0 4 Wait until cpu_wait is a logic O and pass cpu_dout to data 15 0 5 Drive DTACK to a
22. h performance single chip 8 bit microcontroller Figure 3 shows a visual representation of the primary blocks of this 8051 CPU The core contains internal Special Function Registers SFRs which are used to hold various data and control bits For example Timer Control Interrupt Enables and Serial Port control are some of the uses of the internal SFR memory map The 8051 IP also contains an SFR Interface which can be used to service up to 101 External SFRs The External SFRs can be used to interface with an off core peripheral such as an ARINC 429 bus interface Off core peripherals use addresses from the SFR address space range 0x80 to OxFF except those that are already implemented inside the core When a read instruction occurs with an SFR address that has been implemented both inside and outside the core the read will return the contents of the internal SFR When a write instruction occurs with an SFR that has been implemented both inside and outside the core the value of the external SFR is overwritten Furthermore read access to unimplemented addresses will return undefined data while write access will have no effect Note that the SFR address space contains 8 bit addresses but that the external SFR interface uses a 7 bit bus to transmit the external SFR address called sfraddr The MSB of the 8 bit 8051 internal SFR address is not used by the External SFR Interface instead it is used to access RAM When designing the CPU inter
23. int for the design and implementation of an ARINC 429 system The design considerations made for the Actel Core429 Core8051 demonstration design lead into the discussion of interfacing ARINC 429 to a M68K host processor an unverified effort The obvious next step would be to build the system and test its operation Conclusion The Actel ARINC 429 IP core Core429 can be interfaced with other Actel IP such as Core8051 to create an ARINC 429 system within one FPGA This can be extended to a generalized 429 M68K system It also provides a template for how one might integrate other host processors with an ARINC 429 core Since integration reduces system cost and complexity it does not have to stop with a 429 to host CPU system more logic can be added to the FPGA to possibly include a backend application or communication between multiple systems This is especially important when trying to integrate the fast communication standards of today with pre existing technology and standards P236 MAPLD 2005 Appendix I Hardware Implementation of Communication Protocol for a 429 to 8051 System The following control signals and parameters were used in the glue logic parameter CPU_DATA_WIDTH 8 Sets the CPU data width parameter 7 0 PULSE WIDTH 1 l Sets how long the write read pulse is parameter IGNORE_WAIT 0 Set to use cpu_wait input from Core429 wire cpu waitm cpu wait amp amp IGNORE_WAIT This protocol can be implem
24. is useful to keep in mind that the ARINC 429 data width is 32 bits which requires one long word operation to read write At the same time operations involving the 429 core s control and status Mohan Land 8 registers and the label memory require byte sized operations However depending on the version of M68K being used the data bus size can vary between 8 16 and 32 bits For M68K data bus widths less than 32 bits reads writes performed on the ARINC 429 Data Registers will have to be repeated until the full 32 bits of data are written This is controlled by the 9 bit CPU address which includes a map of the byte index for the data being read or written For a 16 bit data bus the 429 IP core s data width parameter should be set to 16 and word sized operations should be used This would require two successive writes or reads for operations on ARINC 429 32 bit data This is accomplished by writing to register 0 of the corresponding Tx or Rx channel with the first 16 bits of ARINC 429 data sent to byte index O in the 9 bit CPU address The last 16 bits of data are sent to the address used above but incremented by 1 to correspond to byte index I A similar argument applies for an 8 bit M68K in which 4 read write byte sized operations are necessary Results for ARINC 429 to M68K The previous discussion of the Motorola 68000 family of processors and its features coupled with the 429 M68K system generalization serve as a starting po
25. low Note r_w is a global value declared as bit r_w void arinc_addr short byte short reg short tx_rx uint16 chan xdata short addr_pkt1 xdata short addr_pkt2 if reg gt 0 assemble 9 bit Core429 internal address reg reg 4 if chan gt 0 tx_rx tx rx 16 chan chan 32 addr_pkt1 chan tx rx reg byte 8 OxOOFF addr_pkt2 chan tx_rx reg byte amp OxFFOO addr_pkt2 addr_pkt2 gt gt 8 if r w 0 a read operation ADDR1 addr_pktt ADDR2 addr_pkt2 else if r_w 1 write operation addr pkt2 addr_pkt2 0x02 set bit 1 1 to indicate a write ADDR 1 addr_pkt1 ADDR2 addr_pkt2 void arinc_data long data_ol puts 8 bits of ARINC 429 word into SFR xdata short data o 0 data_o short data_ol amp 0x000000FF DATA OUT data_o Mohan Land 11 P236 MAPLD 2005 void arinc_wait polls bit 2 of ADDR2 SFR until it is O indicating a done state xdata short rdy 0 rdy ADDR2 rdy rdy amp 0x04 while rdy 0x04 rdy ADDR2 rdy rdy amp 0x04 To enforce the communication protocols discussed above the low level functions arinc_addr arinc_data and arinc_wait are used in the manner described below Writing from Core8051 Application Code to Core429 To write 8 bits of data the following can be used rw 1 arinc_data data_out arinc_addr byte reg tx_rx channel arinc_wait
26. ocessor User s Manual for an explanation of how to implement 68000 interrupts Refer to the ARINC 429 Bus Interface datasheet for information on Core429 interrupt generation Creating M68K Application Code to Communicate with the ARINC 429 IP Core There are several considerations that should be made when creating M68K application code for a 429 M68K system The software protocol used is based upon the hardware connections made in the glue logic discussed above Whether or not the M68K assembly code is part of an Interrupt Subroutine ISR is determined by the glue logic interface used Regardless of the hardware used the 429 core s internal registers and FIFOs can be more easily used if their hex addresses are mapped to labels such as those described below Channel 0 Rx Memory Map DATAO RX equ 00000000 Rx Data Register CNTRLO RX equ 00000004 Rx Control Reg STATO RX equ 00000008 Rx Status Reg LBLO RX equ 0000000C Rx Label Memory Channel 0 Tx Memory Map DATAO TX equ 00000010 Tx Data Register CNTRLO TX equ 00000014 Tx Control Reg STATO TX equ 00000018 Tx Status Reg Channel 15 Rx Memory Map DATAO RX equ 000001E0 Rx Data Register CNTRLO RX equ 000001E4 Rx Control Reg STATO RX equ 000001E8 Rx Status Reg LBLO RX equ 000001EC Rx Label Memory Channel 15 Tx Memory Map DATAO TX equ 000001F0 Tx Data Register CNTRLO TX equ 000001F4 Tx Control Reg STATO TX equ 000001F8 Tx Status Reg It
27. on is a hypothetical example where we discuss integration of a Motorola 68000 device as the host processor The M68000 M68K microprocessors are available in various configurations The supported data bus widths include 8 bits MC68008 16 bits MC68000 and 32 bits MC68020 For the purposes of this discussion it will be assumed that the M68K used has a 16 bit data bus and a 23 bit address bus Other features of the M68K include 16 32 bit Data and Address Registers 16 MB Direct Addressing Range 6 Instruction Types operations on five main Mohan Land 5 Data Types Memory Mapped I O and 14 Addressing Modes The five basic data types that can be operated on include bits binary coded decimal BCD digits 4 bits bytes 8 bits words 16 bits and long words 32 bits Over the various versions of M68K processors the supported clock speeds include 8 10 12 5 16 67 16 and 20 MHz See Figure 6 for a block diagram of the M68K input and output signals Note that this diagram shows the M68K address bus ranging from A23 A1 Based on the version of M68K used this will also be represented as A23 A0 with the restriction that AO is always driven high in 16 bit mode Vegl2 ADDRESS Sui sus gt A23 A1 CLK DATA BUS D15 D0 Asynchronous Processor Bus Control Status MC6800 En Bus Peripheral Ba Arbitration Control VPA BGACK Control SIT System rar MES Interru ET RESET ELI Control n Contro
28. ory are 8 bit registers and thus only require one read write per host processor access For example verilog code illustrating the hardware implementation of the above communication protocol see Appendix I and II Creating 051 Application Code to Communicate with the ARINC 429 IP To successfully create application code that will communicate with Core429 the application code must follow the communication protocol implemented in the hardware Application code for Core8051 can be written in the C programming language and cross compiled into 8051 object code by software such as Keil uVision2 and its C51 compiler and 8051 linkers The software can specifically target the Actel Core8051 In the C program the SFRs used in the current implementation are declared as follows address for Core429 to decode bits If 7 0 Sfr ADDR1 OxCO bit 0 MSB of 429 addr bit 1 R W bit 2 Done Busy sfr ADDR2 0xC1 data written to Core429 sfr DATA OUT 0xC2 data read from Core429 Sfr RDATA 0xC3 P236 MAPLD 2005 Example C code functions for ARINC 429 operations can be found in Appendix II Verification and Results for ARINC 429 with an 8051 Host Each core was verified individually on a simulation test bench Then the cores were integrated as above and verified against a user test bench and in hardware In simulation all tests were passed for each individual core and for the combined entity After simulation we
29. pecific for commercial and transport aircraft The connection wires are twisted pairs Words are 32 bits in length and most messages consist of a single data word ARINC 429 uses a unidirectional data bus standard Tx and Rx are on separate ports known as the Mark33 Digital Information Transfer System DITS Messages are transmitted at either 12 5 or 100 kbps to other system elements that are monitoring the bus messages In addition ARINC 429 data can be sorted by 8 bit labels to ease communication among different systems FPGA Based ARINC 429 IP Core The 429 Bus Interface IP provides a complete Transmitter Tx and Receiver Rx The core consists of the three main blocks shown in Figure 2 Transmit Receive and CPU Interface It can be configured to provide both Tx and Rx functions or either Tx or Rx functions An FPGA based implementation of ARINC 429 requires external ARINC 429 line drivers and line receivers to interface to the ARINC 429 bus The use of FPGA based pre built IP enables the 429 core to be P236 MAPLD 2005 highly configurable in terms of the number of Tx and Rx channels used the clock frequency the CPU data bus width and the size of all FIFO s and memories Line Receiver ewe ti CPU Interface TxHi TW C Tx La Line Driver Core429 Figure 2 FPGA Based ARINC 429 IP Core FPGA Based Host Processor IP Core 8051 The 8051 host used in the first system example is a hig
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