Home

Insider`s Guide STR91x ARM®9

1. dis SES x Ir wg omg wg vm weg weg eg The STR9 requires a main external oscillator of between 4MHz 25MHz and a 32 765Khz watch crystal An additional 48MHz external clock source can be dedicated to the USB peripheral The USB clock may also be derived internally The CPU oscillator can provide the necessary clock signal for the CPU and all the on chip peripherals The only exception is the real time clock which has its own dedicated external oscillator in the form of a 32 768Khz watch crystal The USB peripheral may be clocked from the internal CPU clock or it may be connected to a third dedicated external USB clock running at 48 MHz Finally the STR9 timer blocks may be run from the internal master clock or from an external clock source The internal clock structure of the STR9 is designed to be extremely configurable so that different regions of the chip can be run at different speeds or even halted This allows accurate bit rates to be derived for peripherals such as UARTS USB and CAN The clock control registers may also be changed on the fly for active power management in low power applications gt oe wm RCLK HCLK 25MHz PHY Ch 1 24 The STR9 has a very ES configurable clock 1 2 4 8 16 1024 GE BEEN 1 2 4 8 module that provides qur FMICLK separate clocks for each of the clock domains CPUCLK within the STR9 TIMOICLK LU Be
2. hitex mum DEVELOPMENT TOOLS Th Insider s Guide To The STR91x ARM 9 An Engineer s Introduction To The STR91x Series www hitex co uk Published by Hitex UK Ltd ISBN 0 9549988 5 First Published June 2006 Hitex UK Ltd Sir William Lyons Road University Of Warwick Science Park Coventry CV4 7EZ United Kingdom Credits Authors Trevor Martin amp Michael Beach Illustrator Sarah Latchford Editors Michael Beach Cover Wolfgang Fuller Acknowledgements The authors would like to thank Matt Saunders of ST Microelectronics for his assistance in compiling this book Hitex UK Ltd 26 06 2006 All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical or photocopying recording or otherwise without the prior written permission of the Publisher 1 1 1 2 1 3 1 4 1 5 1 5 1 1 6 1 7 1 7 1 1 7 2 Contents Chapter 1 The ARM9 CPU Core SUI M ATIVSOSE Si ebe iaa CPU architecture PS let ln Re ri helene tits encres ten Re Current Program Status Hegtster esses EXception MOdE m Mdsevensdeebotes dE Raeren daa teal os Qe Rien Branching E ER DUE Data Processing Instructions E ele dl Tee EE 1 7 2 1 Copying Multiple Registers AAA 1 8 1 9 1 10 1 11 1 12 1 13 1 14 2 1 2 2 2 2 1 2 2 2 2 2 3 2 2 4 2 3 2 4 2 5 2 6 2 2 8 2 9 2 10 Swap Ins
3. Recent projects d immart i Save Save as Clase CtrH F7 FF Compile Build Rebuild Al Cancel build WC us Hinga prm 4 E EL am E Finch Pasa marre e STATI 55k Pi i e poca ET Sin Serna EN Processes jirg Ei KA E Cut e Dre Cet JE fige Selina E jet Meret Here hitex mum DEVELOPMENT TO OLE sect he comodes bee hun jet di age GHU G Longer ku SAR gf ai Ends ace ane derecho of Fach wi epic een Tool Seen roto ds Uem sz ef Loud acpkcabonr sutomahcalis at Gsnp Gleis Sms Vorne Diese LI Alias Drui Lei Line pafu nelaime Ewen Hie Rech The applications menu allows you to select the compiler toolchain you are using The default is the GCC compiler but a wide range of commercial compilers are also supported Then you can select the application you want to debug Here you select the ELF file that is output from the compiler linker that you are using Once you have selected the project file and compiler tool the FLASH programming section allows you to select the programming algorithm for the FLASH device you are using This supports the STR9 on chip FLASH memory with its two banks plus a wide range of FLASH memory chips if you are using external FLASH memory In this menu you must specify an area of RAM that the debugger can use for the programming algorithm during download If you check the save and restore RAM contents box
4. 4 13 5 1 3 Signalling Speed Since the USB network is designed to be plug and play the PC will have no knowledge of a new device when it is first plugged onto the network The first thing that the PC needs to determine when a new device is added is the bit rate required to communicate to the new device This is done by adding a pull up resistor to either the D or D line If the D line is pulled up the PC will assume that a full speed device has been added If it is D it means low speed High speed devices will first appear as full speed and then negotiate up to high speed once the connection has been established 4 13 5 1 4 USB Pipes Once a device has been connected to the PC and the signalling speed has been determined the PC can start to transfer data to and from the new device These data packets are transferred over a set of logical connections called pipes A pipe originates from a buffer in the PC and is connected to a remote device with a specific device address The pipe is terminated inside the device at an Endpoint In microcontroller terms the Endpoint may be viewed as a buffer were the data is stored and an interrupt that signals the CPU that a new data packet has arrived EET Drum Each USB slave is characterised by a local address TE Bei and a set of logical endpoint buffers The Host creates logical connections called pipes to each endpoint which are used to transfer packets of information 4 D mg
5. Message valed std frame receive IDI CANO IF1 MCR 0x00000000 clear the message control register CANO IF1 CRR 0x00000002 write to message object two while CANO_IF1 CRR amp 0x8000 Wait for the message object to be written to CANO CR 0x00000080 set into running mode test bit set To configure a a group of message objects as a FIFO you must simply set the message arbitration and mask registers to the same value for a contiguous block of message objects In addition the end of buffer bit EoB in the message object control register for the message object with the highest message object number must be set to one The EoB bit in all the other message objects that are part of the FIFO must be set to zero Once the message objects are configured you can transmit a message by writing data into the message data registers and setting the TXRequest bit in the message control register CANO IF1 CMR 0x00000086 Write data and control register set TXrequest bit CANO IF1 DAIR 0x00000055 load some data CANO IF1 CRR 0x000000015 write to message object one while CANO IF1 CRR amp 0x00008000 Wait for the message object to be written to When CAN messages are received the message identifier will be compared to the message identifiers in the valid message objects If the ID matches the message data will be stored in the message object data registers and the flag corresponding to the message object in the
6. sc Register vi Match Execute Script Emulator State Workspace Enabled up Exit Edit toolbar Debug A 5 v Screen Layout sc Execute Script v Status Bar Customize Change Settings Hitex UK Ltd Page 175 Chapter 5 Tutorial Exercises hitex mum DEVELOPMENT TOOLE Then in the change settings dialog enter a symbolic name for the script and the filename of the HISCRIPT file Change script button settings Toolbar burton ted Pr parel LASH Browse ior script lle SISTA OF Examples ra t HISCRIPTUFLASHScrpE sc Store script path relate to project file directory Ok Cancel The script can then be executed from the toolbar This particular script is used to put the STR9 into a state where Hitop can reprogram the FLASH and a ES T EP needs to be executed before any program is loaded during a Hitop session a PrepareFLASH During the initial program loading the STR9 will be in the correct state so the script is not required 5 3 2 Project Structure The project consists of four source files and four include files as shown below Startup s These files contain the Assembler startup Startup generic s code which configures the processor before you enter your C code Main c This file contains the main function Interrupt c This file contains the default interrupt handlers Main h Include file for Main c LED Control c This file contains functions to drive the LED displays LED Control
7. Each operating mode has an associated interrupt vector When the processor changes mode the PC will jump to the associated vector NB there is a missing vector at 0x00000014 NB There is a gap in the vector table because there is a missing vector at 0x00000014 This location was used on an earlier ARM architecture and has been preserved on ARM7 to ensure software compatibility between different ARM architectures Fr Each of the exception sources has a fixed priority The on chip peripherals are served by FIQ and IRQ interrupts Each peripheral s priority may be assigned Pretetch Abort ande en irrsprumpon S Wi within these groups If multiple exceptions occur then there is a fixed priority as described below Hitex UK Ltd Page 13 KELLER SA I H r e d c S PS 23 Chapter 1 The ARM9 CPU Core hitex m When an exception occurs for example an IRQ exception the following actions are taken First the address of the next instruction to be executed PC 4 is saved into the link register Then the CPSR is copied into the SPSR of the exception mode that is about to be entered i e SPSR moi The PC is then filled with the address of the exception mode interrupt vector In the case of the IRQ mode this is 0x00000018 At the same time the mode is changed to IRQ mode which causes R13 and R14 to be replaced by the IRQ R13 and R14 registers On entry to the IRQ mode the bit in the CPSR is set causing the IRQ inter
8. In each case the peripheral DMA support must be enabled and the DMA configuration register source and destination peripheral fields must be programmed with the required DMA request signals The flow control field Transfer Type Flow Controller 000 Memory to memory DMA 001 Memory to peripheral DMA 010 Peripheral to memory DMA 011 Source peripheral to destination peripheral DMA 100 Source peripheral to destination peripheral Destination peripheral 101 Memory to peripheral Peripheral 110 Peripheral to memory Peripheral 111 Source peripheral to destination peripheral Source peripheral O Hitex UK Ltd Page 78 hitex mm Chapter 3 System Peripherals DEWVELOHP s EM d m Wal D 3 9 7 Scatter Gather Transfer The scatter gather support in the DMA controller allows you to link together any number of unrelated DMA transfers within each of the eight DMA units An area of SRAM must firat be programmed with a DMA item which is a four words long record that contains the Source address Destination address link list address and control word for the next DMA transfer The start address of this DMA item is stored in the DMA unit linked list register and at the end of the current transfer the DMA item pointed too by the link list register is automatically loaded into the channel control registers This loads a new linked list pointer to the next DMA item This allows multiple DMA transfers to be linked together The terminating transfe
9. define Write Bit 7 0x200 define Write Bit All Ox3FC Example of writing to just bit 0 on GPIO9 Disable LED array by Write Bit O0 GPIO9 DATA Write Bit 0 LED disable The type of driver e g open collector or push pull used for any GPIO pin can also be selected via GPIO TYPE 4 3 3 Using Peripherals Via GPIO Ports If any of the STR9 peripherals are to make use of GPIO pins then they must be manually connected to the pin via the SCU GPIO registers The most important is the SCU GPIOOUT which has two bits per pin allowing input or three different peripheral output functions to be selected The SCU GPIOIN register allows the simple IO function and an alternate peripheral input function to be connected to a pin 4 3 4 Peripherals With A Choice Of IO Pins A very useful feature when planning your port pin allocation in your design is that most peripherals can be made to appear on more than one port For example the I2CO peripheral can be configured to appear on GPIOO pins 0 amp 1 as alternate output function 2 on GPIO1 pins 4 and 6 alternate output function 3 or on GPIO2 pins 2 and 2 as alternate function 2 Note the STR9 data book section 4 1 contains a complete matrix of GPIO pins and possible pin functions Hitex UK Ltd Page 85 hitex mum Chapter 4 User Peripherals e z DEVELOPMENT TOOLS 4 4 Synchronous Peripheral Controller The STR9 has two synchronous peripheral controllers Like the VIC EMI and DMA u
10. processing instructions may only be carried out on a central register file f the tion The Registers R13 R15 do Hitex UK Ltd Page 10 Chapter 1 The ARM9 CPU Core hi t el rELOPHE Tr Cid c La H have special functions in the CPU R13 is used as the stack pointer SP R14 is called the link register LR When a call is made to a function the return address is automatically stored in the link register and is immediately available on return from the function This allows quick entry and return into a leaf function a function that is not going to call further functions If the function is part of a branch i e it is going to call other functions then the link register must be preserved on the stack R13 Finally R15 is the program counter PC Interestingly many instructions can be performed on R13 R15as if they were standard user registers The central register file has 16 word wide registers plus an additional CPU register called the current program status register RO R12 are user registers R13 R15 have special functions 15 User registers PC RO R6 R8 R9 RIO H10 R13 is used as the stack pointer R14 is the link register R15 is the Program Counter R15 PC Current Program Status Register CPSR 1 5 1 Current Program Status Register In addition to the register bank there is an additional 32 bit wide register called the current program status register CP
11. Hitex UK Ltd Page 143 hitex mms Chapter 4 User Peripherals DEWVELOUDHP sS EN d m Wal D These logical pipes are implemented on the serial bus as time division multiplexing Every 1msec the PC sends a Start of Frame SOF token to delineate the 12 Mbit sec bus into a series of frames Each pipe is allocated a slot in each frame so it can transfer data as required The USB bus is split into 1msec frames and each pipe is allocated a number of packets per frame USB supports several different types of pipes with different transfer characteristics in order to support different types of application It is possible to design a USB device capable of supporting several different configurations which can be dynamically changed to match the running PC application The types of pipes available are control interrupt bulk and isochronous All of these pipes are unidirectional except the control pipe which is bidirectional The control pipe is reserved for the PC to send and request configuration information to the device and is generally not used by the application software Every device has a control pipe and it is always connected to Endpoint Zero So when a new device is plugged onto the network it will always appear as device zero and the PC can communicate to it by sending control information to Endpoint Zero The remaining types of pipe are used solely for the user application and in the STR9 there are up to 15 user endpoints which are
12. Am pt n M mm OOUNTO FX sn all itl Abc Fin F ou COUNTETX abide uw arm Guter We ex Lea Tx Eacneint Once the endpoint buffers are configured the USB interrupts must then be configured The USB peripheral has two interrupt lines The first is for high priority endpoints Any endpoint enabled as a bulk or isochronous endpoint will be treated as a high priority endpoint All other endpoints and other interrupt sources within the USB peripheral are connected to the second low priority interrupt line When an interrupt is generated the interrupt status register contains flags each interrupt source and an address field for the active endpoint if a USB transaction caused the interrupt 4 13 5 2 3 Endpoint Registers Finally the endpoint register for each active register must be configured In this register as a minimum we must set the address of the endpoint The endpoint type must be set to match the transfer type that will communicate with this endpoint Finally to enable the endpoint the TX or RX status field must be set to 0x03 Cana Toggw cantan Endpoe Lea Tope E wagon Ate An out packet will transfer data to the STR9 USB endpoint were it will be stored in the endpoint buffer The endpoint is disabled generates only NAK s until the data is read and the endpoint is reactivated Now when a USB transaction occurs on an endpoint the data packet will be copied into the endpoint receive buffer and an
13. Chapter 4 User Peripherals 4 14 Summary The STR9 has a comprehensive set of easy to use peripherals that meet the requirement of today s developers If you have worked through the proceeding chapters accessing the peripherals will be straightforward The tutorial programs help you to get each of the peripherals working as quickly as possible In addition the bibliography lists additional tools and resources that assist development of an STR9 based applications O Hitex UK Ltd Page 158 hitex mm B EVELO FE 5 FO LE Chapter 5 Tutorial Exercises Hitex UK Ltd Page 159 Chapter 5 Tutorial Exercises 5 Chapter 5 Tutorial Exercises 5 1 Introduction Having read chapter one you should now have an understanding of the ARM9 CPU In this chapter we will look at some examples of programs that demonstrate the operation of the ARM9 core and the STR9 peripheral set 5 2 Further STR91x Examples The latest versions of these tutorial examples plus further STR91x example programs can be found at http www hitex co uk str91x Hitex UK Ltd Page 160 hitex um Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS 5 3 Exercise 1 The FIRST STR9 Example Program You will find all the example programs in STR910FExamples Each one exists in an appropriately named subdirectory They are all ready built and will run in the STR9 evaluation board under HiTOP If you wish you can modify them and rebuild them all within Hitop using
14. TIM1 OCMP2 Pin 4 TIMO ICAP1 TIM2_ ICAP1 TIM2 OCMP1 Pin 5 TIMO ICAP2 TIM2 ICAP2 TIM2 OCMP2 Pin 6 TIM2 ICAP1 TIM3 ICAP1 TIM3 OCMP1 Pin 7 TIM2_ICAP2 TIM1_OCMP1 TIM3 ICAP2 TIM3 OCMP2 GPIO5 GPIO6 GPIO Mode Alternate Out 3 Alternate In 1 GPIO6 Alternate Out 2 GPIO7 Alternate In 1 Pin 0 X TIMO ICAP1 TIMO_OCMP1 TIMO_ICAP1 Pin 1 X TIMO ICAP2 TIMO_OCMP2 TIMO ICAP2 Pin 2 TIM3 OCMP1 TIM1 ICAP1 TIM1 OCMP1 TIM2 ICAP1 Pin 3 TIM2 OCMP1 TIM1 ICAP2 TIM1 OCMP2 TIM2 ICAP2 Pin 4 X TIM2 ICAP1 TIM2 OCMP1 X Pin 5 X TIM2 ICAP2 TIM2 OCMP2 X Pin 6 X TIM3 ICAP1 TIM3 OCMP1 TIM3_ICAP1 Pin 7 X TIM3 ICAP2 TIM3 OCMP2 TIM3 ICAP2 These timers consist of a free running 16 bit counter with prescaler and a series of capture and compare registers The timer counters have several dedicated operating modes these modes allow easy configuration of the timer counters for common functions such as pulse measurement or PWM generation Timer 0 and Timer 1 may also be DMA flow controllers and allow data to be too and from the capture and compare registers MCLK from SCU SCU SRx 16 Bit Prescaler Ext CLK pin 17 ICAP1 ICAP2 gt OCMP1 OCMP2 Overflow Interrupt Overflow OCMP ICAP PPP UT ME cn san p rn Ve EARS OR NE Ro Me M DR MER PEE EEN The STR9 has four independent 16 bit timer counters with dedicated capture and compare registers The timer clock may be selected from e
15. The text section ensures that the startup code is assigned first so it will be placed on the reset vector Then the remaining application code is assigned locations within the FLASH memory The align command ensures that each relocatable section is placed on the next available word boundary data AT etext used for initialized data __ data start PROVIDE data start data SORT CONSTRUCTORS data end Hitex UK Ltd Page 37 Chapter 2 Software Development PROVIDE data end IntDataRAM ALIGN 4 The data section allocates the user variables into the on chip RAM defined for the STR9 2 12 C support The GCC compiler is a C and C compiler so while the examples in this book concentrate on using the C language it is also possible to build a program using the C language and make use of its richer programming constructs This is really outside the scope of this book but an example is included here to get you started if you want to use the C language O Hitex UK Ltd Page 38 hitex mum Chapter 2 Software Development x DEVELOPMENT TOOLS 2 13 Hardware Debugging Tools ST Microelectronics have designed the STR9 to have the maximum on chip debug support There are several levels of support The simplest is a JTAG debug port This port allows you to connect to the STR9 from the PC for a debug session The JTAG interface allows you to have basic run control of the chi
16. UK Ltd Page 43 hitex mum Chapter 3 System Peripherals SEH DEWVELOHP s EM 3 2 Bus Structure To the programmer the memory of all STR9 devices is one contiguous 4 gigabyte 32 bit wide address range However the device itself is made up of a number of buses The ARM9 core is connected to the Advanced High performance Bus AHB which is a bus structure defined by ARM As its name implies this is a high speed bus running at the same frequency as the ARM9 CPU The high performance peripherals such as the Ethernet controller and the USB controller are connected directly to this bus to allow fast access to their registers by the CPU and the DMA units The most important system peripherals such as the Vector Interrupt Controller VIC General purpose DMA unit and the external memory interface are also connected to the high speed bus for the same reason The remaining user peripherals are located on two additional busses called the advanced peripheral busses APB which like the AHB is a bus structure defined by ARM The APB busses are coupled the AHB by a pair of bridges that provide memory protection and peripheral clock control Programmable Vectored Interrupt Controller Real Time Clock 32ke XTAL 10 8 bit GPIO 4 EFT Timers PLL Power Management and Supervisory Reset AHB to APB CAPCOM PWM mac 10 bit AD C External memory EMI Muxed Address Data or 24 GPIO a Selects acs Shar
17. constants table which follows immediately after the vector table This means that the complete vector table takes the first 64 bytes of memory The startup code contains predefined names for the Interrupt Service Routines ISR You can link your ISR functions to each interrupt vector by using the same name as your C function name The table below shows the constants table symbols and the corresponding C function prototypes that should be used Exception Source Constant C Function Prototype Undefined Instruction Under Handler voidUndef Handler void X attribute interrupt undef Software Interrupt SWI Handler void SWI Handler void X attribute interrupt swi Prefetch Abort PAbt Handler void Pabt Handler void X attribute interrupt undef Data Abort DAbt Handler void Dabt Handler void attribute interrupt undef Fast Interrupt FIQ Handler void FIQ Handler void attribute interrupt fiq As you can see from the table there is no routine defined for the IRQ interrupt source The IRQ exceptions are special cases as we will see later Only the IRQ and FIQ interrupt sources can be disabled The protection exceptions Undefined instruction Prefetch Abort and Data Abort are always enabled Consequently these exceptions must always be trapped As a minimum you should ensure that these interrupt sources are trapped in a tight loop as shown below Pabt Handler B Pabt Handler Branch back to Pabt Handle
18. unsigned short volatile FMI BANK 1 FMI OTPHWAddress FMI OTPData The 30 and 31 bytes are factory programmed with the STR9 silicon revision It is recommended that the SEH 30 bytes are used to hold the Ethernet MAC address if any assigned to the device Hitex UK Ltd Page 53 hitex mmm Chapter 3 System Peripherals DEVELOPMENT TOOLS 3 6 External Memory Interface In addition to the on chip memory the STR9 has an external memory interface that allows access to four external memory pages each of 64Mbytes Each memory page can be configured to use an eight or 16 bit data path in order to conserve the number of pins that are used by the external bus a multiplexed addressing mode is used except in the case of eight bit data were a non multiplexed mode is available for eight bit wide data and 16 bit wide address bus 16 bit Multiplexed CS and control pe STR910 A16 A23 1 6 bit device ADO AD15 8 bit Multiplexed amp BIT CS and control gt Memory Ste bi Device Haut device ADO AD7 gt 8 bit Non Multiplexed EM R Dn CS and control p EMI WEN d A0 A15 8 bit device EMI s n a EE The external memory interface provides four addressing modes for eight and sixteen bit wide external memory and peripherals The initial bus configuration is defined in the system control registers These are a block of regist
19. 1 i GD NET Boo Desen a J i F E RUSSE CRE OE D LE IN Eu ss br I z nf ET mra a Em Mi 5 m a _ ES Lem mr m E E am E EE id Fe E a E oca EO weem ju i E E i i bi bh Ee mms IC L DU a D x a La on og EF GS m Am m span zm Re ae res mco mmy I um ge Sl LE GEN FR er EN GENE mi mu ELE AS i Ll ELLA cm Hem mem a pg pru es Leg Een um i Lm FE Rn Ke E Gg Sa ii 1 le en cm La Ce F P cum rg i I Bech mem cmm 8 m Gum EN gue rg meng Cow um CUu T E 1 mm Beer ent E 1 i ntm k um i P RL LE 1 I m 1 I F za mme GA amm Ll v a ka i VR pt Bag BA Hitex UK Ltd Page 164 hitex Chapter 5 Tutorial Exercises DEVELOPMENT TOOL The Hitop debugger and its main windows are shown below W ox eh de E Prope Pruwam a Se mpe i O i 17 pmm ee ui i CFA i HTDP empoi a KZ Wels Wind Berrig window L EY Tu A TM7 ir deg Pal emos iruli Call Stack esou If you close a HiTOP window it can be reopened by moving the mouse cursor onto an unused section of the toolbar right clicking the mouse and then selecting the window you wish to reopen This menu also allows you to enable and disable the various toolbars D amp Ro Exp Ei 2 v Callstack Register wi Watch Emul
20. 1 Mbit sec Typically this can be achieved over about 40 metres of cable By dropping the bit rate longer cable runs may be achieved In practice you can get at least 1500 metres with the standard drivers at 10 Kbit sec 4 13 1 3 CAN Message Objects The CAN bus has two message objects that may be generated by the application software The message object is used to transfer data around the network The message packet is shown below Control DATA Field Field S R 29 Bit Identifier 0 8 Bytes Data f R Remote transmit request Error control and end of frame Arbitration Field Data length code CAN message packet The message packet if formed by the CAN controller the application software provides the data bytes the message identifier and the RTR bit The message packet starts with a dominant bit to mark the start of frame Next comes the message identifier This may be up to 29 bits long The message identifier is used to label the data being sent in the message packet CAN is a producer consumer protocol A given message is produced from one unique node and then may be consumed by any number of nodes on the network simultaneously It is also possible to do point to point communication by making only one node interested in a given identifier Then a message can be sent from the producer node to one given consumer node on the network In the message packet the RTR bit is always set to zero this field will be discussed in
21. 13 12 11 id B B 7 6 5 E x 2 1 Before the CAN timing parameters can be programmed the CAN controller must be placed into reset by setting the init bit in the control register After reset the CAN controller is held in its initialising mode with the init bit in the Can control register set to one This allows the access to the timing registers once the init bit is set to zero the CAN controller enters its operating mode and the bit timing registers become read only The values calculated above can be programmed into the bit timing register and the baud rate extension register The Timing register has fields for each of the bit timing parameters calculated in the bit timing example Here it is important to note that the values programmed into the timing registers are the calculated values minus one This ensures that a timing segment cannot be programmed to zero length CAN CR 0x000000C1 init config change and test enable CAN BRPR 0x00000000 set extended Baud rate prescaler to 0 CAN BTR 0x000045C3 set bit rate to 500K for FCLK 24 MHz CAN TESTR 0x00000004 set into basic mode CAN_CR 0x00000080 set into running mode test bit set Hitex UK Ltd Page 131 DEVELOPMENT TOOLE Chapter 4 User Peripherals hitex mum 4 13 3 CAN Module IO Pins The CAN module can be freely configured to use the IO pins shown in the table below The CAN TX pin should be set to alternate function however the CAN RX pin should be
22. 15 in order to have the fastest ADC conversion This value must be programmed into the ADC prescaler register 4 8 2 Conversion Modes Once the input pins and the ADC clock are configured the ADC can begin conversions Two conversion modes are available single channel conversion or scan mode At the end of each conversion the ADC result can be checked against a set of analog watchdog registers to check that it is within the bounds defined by your application 4 8 2 1 Single Channel The ADC control register allows you to select a single channel for conversion The channel is selected in the SC field and the scan mode enable bit must be set to 0 Conversion is started by setting the STR bit When the ADC has finished conversion the end of conversion flag in the control register is set Each ADC conversion channel has its own data results register from which you can read the conversion result immediately the conversion has finished 15 d 13 12 A 10 E B F B D H 3 S 1 D Each of the eight analog channels has a results register with a ten bit data field The most significant bit is set when an overflow occurs The ADC result is stored as a 10 bit value in the data register matching the conversion channel The most significant bit in this register is an overflow flag which is set when a new result has been generated before the previous result was read from the register i e a conversion has been lost 4 8 2 2 Scan Mode The ADC can may also co
23. 3 6 External Memory Interface 54 37 S 57 9 9 OleM FP ernpher eege eege ee 58 3 8 1 Power Supplies eene 58 3 6 2 OW Voltage Be EE 59 3 0 9 EE ere rie nt els 59 3 0 4 SONNIE EE 59 ES Ee e 61 SOC E 62 3 8 7 Petiphieral Clock Gating 5 2 ceto ioi uoo sto memes ode aS 63 3 8 8 Low Power Modes 64 3 8 8 1 64 3 8 8 2 Special Interrupt Run Mode AAA 64 9 0 9 9 NONE MOOG coii en Msn di pede 65 3 8 8 4 Sleep Mode 65 38 9 le ie n e 66 SO TOPIC InterrmtiDEbs SSSR nes 67 93 9 14 beaving An GI Bn pis sn es ne ner ns 67 30 12 VeCIOred Te EE 68 3 8 13Leaving An ARG Iter uit sn nr ns 70 3 8 14Non Vectored Interrupts nnn 71 3 8 15Leaving A Non Vectored IRQ Interrupt 71 3 8 15 1 Example Program Non Vectored Interrupt 71 3 8 16Nested Interrupts nennen 72 99 DNA Ee ee TEE 74 9 91 EMA OVETVIEN nisu SN been 74 3 0 2 EM HEEN 75 3 9 3 DMA Arbitration ss 76 3 9 4 Memory To Memory Transfer 77 9 920 BUFSETTASIOE Lee in nissan 77 3 9 6 Peripheral DMA SUPPO cuire oo riporta tnu tec entrent 78 3 9 7 Scatter Gather Transfer 79 Sm eu Gres LT TEE 79 Chapter 4 User Peripherals 81 Lx MENS GUI MCN ETE 81 4 2 General Purpose Peripherals nn 81 4 3 General Purpose I O porte 82 4 9 LG PIC COMIGUIAUON suction n ndum tete de o ieu qui etus 83 A3 2 OPIO POM el 84 4 3 3 Using Peripherals Via GPIO Ports 85 4 3 4 Periphe
24. 6 STDIO libraries The Hello World example in Exercise 1 uses a simple print f routine which will print simple strings to a terminal The GCC compiler has a full ANSI C library which includes the full high level formatted I O functions such as scanf and printf These functions call low level driver functions that can be modified to the I O stream to a given peripheral These functions are stored in a file called syscalls c If you intend to use the STDIO library you should add this module to your project and then tailor the driver functions to match your I O device Bear in mind that the high level STDIO functions are quite bulky and should only be used if your application is very UO driven 2 Accessing Peripherals Once we have built some code and got it running on an STR9 device it will at some point be necessary to access the special function registers SFR in the peripherals As all the peripherals are memory mapped they can be accessed as normal memory locations Each SFR location can be accessed by hardwiring a volatile pointer to its memory location as shown below define SFR volatile unsigned long OxFFFFFO00 StartEasy generates an include file which defines all the SFRs in the different STR9 variants The include file is added to your skeleton project This allows you to directly access any STR9 peripheral SFR directly using the data book naming convention Hitex UK Ltd Page 33 Chapter 2 Software Developmen
25. BRCLK to UART EXTCLK TIMO1 EE EXTCLK TIM23 48MHz To USB After reset the external CPU oscillator is used to derive the STR9 master clock which is used to drive the CPU and peripherals Once out of reset the application firmware can enable the on chip Phase locked loop PLL and multiply the external frequency up to the full 96 MHz Once the PLL has stabilized the the firmware can select the master clock source to be either the external crystal the PLL output or the 32Khz output of the RTC watch crystal Sine the master clock source can be selected dynamically this allows you application the easily switch between three fundamental operating frequencies Hitex UK Ltd Page 61 hitex mum DEVELOPMENT TOGOLE Chapter 3 System Peripherals Selection of the master clock source is made in the MCLKSEL field in the system control unit clock control register d a ZH 8 ET 2 25 i oH d i i PN 18 17 L Le Cem E LSS Z r OD Adone Om MELEDA ML i E The system clock control register contains fields which allow you to dynamically select the MCLK source and program the various clock divider registers The master clock frequency is fed to the CPU via the RCLK divider which can divide down the external oscillator by a factor of 1 2 4 8 16 or 1024 The master clock is also used to clock the UARTs timers and USB peripheral These may be driven at the master clock frequency or in the case of the USB and UART clocks the ma
26. New data register will be set The received data can then be read into the message interface registers and then be made available to the application software if CAN ND1R amp 0x02 if message object 2 has received new data CAN IF1 CMR 0x00000003 Mark all data registers for read CAN IF1 CRR 0x00000002 read message object two while CAN IF1 CRR amp 0x00008000 Wait for the busy bit to clear CAN data O0 1 CAN IF1 DAIR read the data from the message registers CAN data 2 3 CAN IF1 DA2R CAN data 4 5 CAN IF1 DBIR CAN data 6 7 CAN IF1 DB2R It is important to wait for the busy bit to clear this takes several cycles and if you read the data registers too soon you will get old data O Hitex UK Ltd Page 136 hitex DCEVELOPENT TODI Chapter 4 User Peripherals 4 13 4 3 CAN Error Containment The CAN protocol has five methods of error containment built into the silicon If any error is detected it will cause the transmitter to resend the message so the CPU does not need to intervene unless there is a gross error on the bus There are three error detection methods at the packet level form check CRC and acknowledge and two at the bit level bit check error and bit stuffing error Within the Can message there are a number of fields that are added to the basic message On reception the message telegram is checked to see if all these fields are present if not the message is rejected and an error frame is g
27. Outputs Inputs Supported Input Output Capture Compare Hitex UK Ltd Page 83 hitex mum Chapter 4 User Peripherals DEVELOPMENT TOOLS 4 3 2 GPIO Port Registers Data 1020 Data Direction Mode Control Each GPIO port is controlled by two configuration registers and 1020 data registers The offset address of the data register acts as a mask on the port data Each GPIO port is configured with two registers for simple digital IO applications the use of IO pins for peripheral functions UART 12C etc is described in the next section Currently the GPIO mode control register is provided for future expansion of the STR9 and all the bits in this register should be set to zero The data direction register defines each port pin as an input or output and should be programmed to match the System control unit GPIO configuration registers Finally data can be read or written to the GPIO data register or rather the 1020 GPIO data registers As the ARM9 does both have a Boolean processor the GPIO pins can only be addressed word wide This means that reading and writing the selected GPIO pins requires additional logic operations GPIO Mask amp data This take both additional processor cycles and space in the flash memory The STR9 has a register mask built into each GPIO port Rather than have a separate mask register that must be configured each time the mask value changes each GPIO Data register has an address range of 10
28. SRAM is aliased three times in the memory map appearing immediately above the FLASH at 0x04000000 for up to 64K and again at 0x40000000 and again at 0x50000000 Each of these three windows has different characteristics at 0x04000000 the SRAM is located within the D TCM for fast zero waitstate access by the CPU with the D TCM and write buffer At 0x40000000 the SRAM appears on the AHB as buffered memory and finally at 0x50000000 the SRAM appears as non buffered memory an the AHB The DMA can access any of these three SRAM address ranges but in each case all writes are non buffered After reset the size of the on chip SRAM is limited to 32K and a wait state is added to the D TCM and AHB bus address ranges The system configuration register 0 in the system control unit is used to configure the SRAM for maximum performance 13 12 11 10 3 B D 6 T 4 J 2 i 1 P F 2 PF UART IFIDAIZ 2 tu SEG i ff e rm FE E re rm nm Hi ME FE re nm an rm The system configuration 0 register contains fields to adjust the on chip SRAM size The WSR DTCM and WSR AHB can be set to add a waitstate when accessing the DTCM SRAM or accesses over the AHB Hitex UK Ltd Page 49 Chapter 3 System Peripherals In this register the SRAM size field can be programmed to increase the available on chip SRAM to 64K and 96K The additional waitstates within the D TCM and on the AHB bus can be removed by clearing the WSR DTCM and WSR AHB fields All of the STR9 s
29. SWI interrupt vector a SI Handler g gt 0xo0000008 4000064 b SWT_ Handler 5 Continue single stepping to enter the SWI interrupt handler 6 Run the code to the switch statement 7 Observe the contents of the link_ptr This should be the SWI instruction address 4 40 temp lie et Gx000002A0 GE30AGE mov r3 lr aink ptr OxOO0001FC GEIER 043043E2 sub r3 r3 4h Ox 00000248 D 3093E5 Idr r3 r3 8 Observe the contents of the temp variable This should be the value of the ordinal encoded into the SWI instruction Ta aa Ta a LE LE UD LAKE KAL nell AN ie L ER Ee Zem Ox00000001 1 c Ox000002BE 98309FE5 Idr r3 pc Ox0000026 003093E5 Idr r3 r3 9 Run the code to the closing brace of the SWI interrupt handler and observe the ISR exit code OxO0000350 OC40BDES ldmia spl r2 r3 r14 mi Ox00000354 DEF BU E 1 mows pc lr OxO0000356 20020020 dw 20000220h 10 Finally run the program at full soeed to see the LEDs FLASH in a new and interesting way Note The C source for the SWI interrupt handler is in the module Interrupt c Hitex UK Ltd Page 180 hitex mm Chapter 5 Tutorial Exercises DEWVELOHP s EM d m Wal D 5 7 Exercise 5 Clock Configuration and Special Interrupt Mode This exercise demonstrates configuring the STR9 system clocks The Master clock and peripheral clock are configured to 96 MHz with the CPU running at 48MHz 1 Open the HITOP project STR910FExamples CLOCK C
30. Srice Bic All Oxd whilsi i lnzrmmmnri Gun ceisler Hitex UK Ltd Page 187 hitex um Chapter 5 Tutorial Exercises apr DEVELOPMENT TOOLS 5 13 Exercise 11 16 Bit Timers In this exercise 16 bit timer TIMO is used to create an IRQ interrupt that writes a counter to the right hand LED array every second Open the TIMx HTP project in STR910Examples TIMx remember to enter the serial number of your Tantino when asked Ke IT CES c TREE Pinspearbiy ckarbuphi man Iinebase 0 IAQ Serrice Routine Z i Interrzwpt ZamcEtap prototyp void TimenmssEO IBU ise void mrrrihurge i iimrerrupr TIEF i Tubs IXO fecrice Routine valid Tisebane TAQ ter wennt E SWITCH IBS TO ges Z Foe ap Sy TiHU ZXR pe C1000 i d Cipar OCFi Flag te prorenpt further interes Alternately flash the LE SWITCH SES TO IQ Clasar the VIC banal E vicn vagp eo eg Bib im CW ger FS ORCRIRUIS 8 D P S Bert LUE tour FPE SACR Bdcirlbkb BRS Bee ee RRB RR eee LE dette Nee i pe a 1 vim recae finer 270 pande n iti EIE Etes T ci nan um hime ney ms Le LN BTC wore A imp PE ati rufa UT Mb Tem TRD CE T Ce BHIITDEDE amp ekmmcecacscacackca aed ci mo de cj us Ga SR OUR UR o DR GR S Ebbe bam RER cs KEE bm TRA MOREL EATE and opima tape ases recae ihi TE Bam aF PS A8 SCHEIL ELssbtet F E RI aa LR L MR ren Dien dod H irm Bon dA ie al
31. The ADC consists of 14 registers and a group of support registers within the system control unit Ava Te Dill Converter The STR9 ADC has eight analog channels with a 10 bit resolution Each channel has its own results register and threshold watchdog registers The ADC input pins are located on GPIO port 4 and must be configured to be analog inputs before the ADC can be used The analog function is controlled in the system control unit GPIO analog mode register This register contains a bit for each ADC channel which must be set to enable the analog function In addition the matching bits in the GPIOIN 4 and GPlOout 4 registers must be cleared to fully enable the ADC channels Before you can begin to use the ADC you must ensure that it has been powered on by setting the POR bit in the control register Hitex UK Ltd Page 106 hitex mum DEVELOPMENT TOOLS Chapter 4 User Peripherals H A e D ECW AWD rta or T ECwi AVIDI Sr 0 SCE CONT SCE A POR STA n I F gt m Fer Ve Fee Te Fe Fe The ADC control register allows you to enable the interrupt sources EVCI AWDI enable the scan mode SCE and continous conversion CONT and select the channels to be converted SC Like the other peripherals the ADC is clocked by the APB bus clock PCLK This clock must first be divided down by an eight bit prescaler so that the input to the ADC is a maximum of 3 4MHz So for a PCLK of 48 MHz the prescaler must be set to
32. Then depending on this result the following instructions may or may not be carried out The basic Assembler instructions such as MOV or ADD can be prefixed with sixteen conditional mnemonics which define the condition code states to be tested for E E fase rs EE Each ARM 32 bit instruction can LI l MW Lui Lu n be prefixed by one of 16 condition GZ be codes Hence each instruction has ia e 16 different variants EPS P ER eme refus cmm tr RES COURENT Er IER LT EU EU mas Fon Las z m LT PN PS dea RES a mid Ee je dj EZ EE Ka Hitex UK Ltd Page 16 WE L O PA EN ols ae FS Chapter 1 The ARM9 CPU Core hitex So for example EQMOV R1 0x00800000 will only move 0x00800000 into the H1 if the last result of the last data processing instruction was equal and consequently set the Z flag in the CPSR The aim of this conditional execution of instructions is to keep a smooth flow of instructions through the pipeline Every time there is a branch or jump the pipeline is flushed and must be refilled and this causes a dip in overall performance In practice there is a break even point between effectively forcing NOP instructions through the pipeline and a traditional conditional branch and refill of the pipeline This break even point is three instructions so a small branch such as if x lt 100 KT would be most efficient when coded using conditional
33. Tseg1 to Tseg2 adjusts the sample point This allows the CAN protocol to be tuned to the transmission channel If you are using long transmission lines the sample point can be moved backwards If you have drifting oscillators you can bring the sample point forward In addition the receivers can adjust their bit rate to lock onto the transmitter This allows the receivers to adjust to small variations in the transmitter bit rate The amount that each bit can be adjusted is called the synchronous jump width and may be set to between 1 4 time quanta and is again user definable Hitex UK Ltd Page 129 Chapter 4 User Peripherals To calculate the bit timing the formula is Bitrate Ferk BRP x 1 Tseg1 Tseg2 Where BRP Baud rate prescaler and Fcik is the APB1 clock All of the calculated timing values are stored into the STR9 CAN registers as the calculated value 1 This is in order to prevent any timing value being set to zero time quanta This calculation has a lot of unknowns If we assume that we want to reach a bit rate of 125K with a 24 MHz Fark and a sample point of about 70 The total number of time quanta in a bit period is given by 1 Tseg1 Tseg2 If we call this term QUANTA and rearrange the equation in terms of the baud rate prescaler BRP Fox Hz Bit rate x QUANTA Using our known values BRP 24MHz 125K x QUANTA Now we know that we can have between 8 and 25 time quanta in the bit period so using
34. a rotor stop stall and generates an interrupt request to permit the software handling of this state OTC Int GP Tacho Compare Red OVE 16 Bit Tacho Counter CLE on CPT CPT Int TACHO 16 Bit Tacho Capture Reg i wee Tacho Generator Interface 12 Bit Prescaler acho Prescaler Reg If the Tacho input is not required for the motor drive controller then it can be freely used for other purposes 4 6 5 Emergency Stop For Fault Protection In any real drive it is essential for faults to be able to immediately shut down the power stage drivers to prevent damage to the power electronics motor or the plant being driving by the motor Such faults might be overcurrent under or over voltage over temperature plus fault conditions arising in the driven plant itself The ESTOP input will immediately turn of the PWM outputs and generate an interrupt request to the WIU so that software can deal with the fault To prevent the drive being restarted unintentionally the software must write a password 0x4321 to the Emergency Stop Clear register MC ESC The MC peripheral can generate eight different interrupt requests that are collectively routed through VIC vector 14 VICO 14 In addition the Emergency Stop interrupt EST INT a k a EXT INT23 is routed through the WIU Group 2 controlled by the SCU WKUP SEL field and thence to VIC1 12 Exercise 18 Motor Drive Peripheral This exercise contains the core of a 3 phase ind
35. a second editor called Development Assistant for C This is an advanced editor specifically targeted at embedded systems developers As well as having all the features you would expect in a programmer s editor DA C includes a number of advanced features that help you to produce high quality well documented C source code DA C includes a static checker that will analyse your code for common programming errors generate flow charts and calling hierarchies DA C also includes a code browser SO you can easily navigate your code and a metrics module so the source code may be analysed using quality standard measures 2 2 4 TESSY The final item of software included on the CD is a software testing tool suite called TESSY The TESSY toolset automates the functional testing of embedded microcontrollers and their target hardware In many industries especially Aerospace and Medical validation of microcontroller firmware is a lengthy and important process TESSY is especially suitable for testing small footprint microcontrollers which have small amounts of on chip memory Rather than build a test harness that is downloaded into the target memory of the device under test O Hitex UK Ltd Page 28 hitex mm DEE KI LOB B I H rad c Chapter 2 Software Development TESSY makes no changes to the code under test but builds its test harness in the Hiscript language built into the debugger This way the target application can be fully exercised without the
36. a spreadsheet we can substitute in integer values between 8 and 25 for QUANTA until we get an integer value for BRP In this case when QUANTA 16 BRP 12 Then 16 QUANTA 1 Tseg1 Tseg2 So we can adjust the ratio between Tseg1 and Tseg2 to give us the desired sample point Sample point QUANTA x 70 100 Hence 16 0 7 112 Round this to the nearest integer gives the sample point at 11 time quanta The sync segment is always equal to 1 so Tsegi 11 1 10 and Tseg 2 will be equal to 5 Using these values the sample point will be at 68 8 of bit period The value for the synchronous jump width may be calculated by the following rule of thumb Tseg2 gt 5 Ta then program SJW to 4 Tseg2 lt 5 Tq then program SJW to Tseg2 1 Tq In this case SJW 4 Hitex UK Ltd Page 130 hitex mum DEVELOPMENT TOOLE Chapter 4 User Peripherals Remember that the actual values programmed into the timing register are the calculated values minus 1 hence the bit timing register is equal to OXA9CB If the calculated value for the baud rate prescaler is greater than 64 the first six bits are programmed into the CAN DI register and the upper bits minus 1 are programmed into the BRP extension register This allows you to divide the Fci by a maximum of 1023 4 13 2 2 Configuring the CAN Module Now that we have calculated the values for the CAN bit timing values we can perform the initial configuration of the Can module 15 14
37. and any pending IRQ interrupt will be asserted Write 3 Vector Address Register At the end of a vectored IRQ interrupt you must make a dummy write to the Vector Address Register in addition to clearing the peripheral flag to clear the interrupt Clear gt Peripheral Interrupt Register This example is a repeat of the FIQ example but demonstrates how to set up the VIC for a vectored IRQ interrupt The vector table in STARTUP S should contain the instruction to read the VIC vector address as follows Vectors LDR PC Reset_Addr f 0x0000 7 LDR PC Undef Addr 0x0004 LDR PC SWI Addr 0x0008 LDR PC PAbt Addr 0x000C LDR PC DAbt Addr 0x0010 NOP 0x0014 Reserved Vector LDR PC PC xFFO 0x0018 wraps around address space to OxFFFFFF030 Vector from VicVECAddr LDR PC FIQ Addr 0x001C FIQ has no VIC vector slot The C routines to enable the VIC and service the interrupt are shown below Set Up IRQ Watchdog interrupts routed through VICO 0 SCU gt PCGRO SCU gt PCGRO amp 0x00000020 0x00000020 Enable VIC clock SCU gt PRRO 0x00000020 Release VIC reset unsigned int amp Watchdog IRQ isr Load the vector 0 register VICO VAiR O0 VICO VCiR 0 0x0050 Enable VICO 0 interrupt VICO gt INTSR amp 0x0001 NICO 0 uses IRQ This is the second highest LZ priority after FIO VICO gt INTER 0x0001 Enable Ei 1 inte
38. be used to control which slave device can write data onto the bus This removes the need for a master to control slave select pins with GPIO lines or external multiplexers Finally control register 1 can be used to enable a loop back test mode which internally connects the output shift register to the input shift register 15 14 LA 12 11 10 g B D amp 5 J e 1 0 Control register 1 is used to enable the SSP peripheral and define it as Master or slave and optionally enable the Then has gef configuration options can be found in control register 0 This register contains a frame format field which allows you to select between the SPI Microwire and synchronous serial frame formats Depending on the selected protocol the data size field can configure the transmit and receive word size from 4 up to 16 bits If the SPI protocol is selected the CPOL field allows you to select the clock polarity and CPHA selects the clock phase i5 4 83 12 nm 10 9 B 7 66 5 3 2 1 SRCI 0 CPHMA CPOL FRFT IO ossidi FA ne na AJ na na na na na rds Te EW na rd P ne Control register 0 is used to define the serial protocol that the SSP will use to communicate with external devices Hitex UK Ltd Page 87 hitex mum DEVELOPMENT TO OLE Chapter 4 User Peripherals The final field in control register zero controls one of two clock dividers used to define the SSP bit rate Like the other user peripherals the SSP is clocked from the APB bus clock Pclk Th
39. cycle which is a pipeline stall for one cycle LDR RO PC 20 load a memory location into RO ADD R1 RO R2 R1 RO R2 Since this sequence does not adversely effect the ARM7 three stage pipeline it is often used in ARM7 code However it should be avoided in ARM9 code by instruction scheduling which is simply moving the LDR instruction forward an instruction or two in order to prevent the risk of a stall being caused by a data dependency Since most applications will be written in the C language this is a function of the compiler The second case were a programmer can get some unexpected exposure to the pipeline is that the PC is running eight bytes ahead of the current instruction being executed so care must be taken when calculating offsets used in PC relative addressing For example the instruction 0x4000 LDR PC PC 4 will load the contents of the address PC 4 into the PC As the PC is running eight bytes ahead then the contents of address 0x400C will be loaded into the PC and not 0x4004 as you might expect on first inspection 1 5 Registers The ARM7 is a load and store architecture so in order to perform any data processing instructions the data has first to be moved from the memory store into a central set of registers the data processing instruction has to be executed and then the data is stored back into memory Ve M P The ARM7 CPU is a load and Add Aa P fb fa e FE store architecture All data
40. executing from the prefetch queue with a minimal interrupt latency For a real time interrupt driven system this can be a key factor which will effect the overall design performance Although the memory subsystem is fairly complex particularly if you are moving to the STR9 from an eight bit microcontroller the good news is that the operation of the I TCM and D TCM memories are transparent to the programmer and can be considered as part of the ARM9 CPU O Hitex UK Ltd Page 48 Chapter 3 System Peripherals hitex DEWVELOHP s EM TOQdLt 3 4 Memory Map Despite the internal bus structure the STR9 has a completely linear 4GB memory map with the general layout shown below OxFFFF FFFF The ARM9 has a 4 Gbyte address range The STR9 has a address ranges for the TCMs AHB bus and APB busses apa BRIDGE NON BUFFERED Each bus has an address range for buffered and non buffered writes which access the same underlying peripherals ES APB PERIPHERALS REENEN 1 APB BRIDGE 1 BUFFERED WRITES ORDER OF BANKSIS USER DEFINED BUFFERED WRITES D TCM I TCM 0x0000 0000 Flash The principle on chip memory resources start at 0x00000000 with up to 544k of on chip FLASH memory which is available to the CPU via the I TCM interface described above To the user this memory appears as 32 bit wide FLASH arranged in two banks which can be programmed through the FLASH Programming and erase controller FPEC 3 4 1 On Chip SRAM The on chip
41. features for the embedded developer It is a low cost easy to implement peer to peer network with powerful error checking and a high transmission rate of up to 1 Mbit sec Each CAN packet is quite short and may hold a maximum of eight bytes of data This makes CAN suitable for small embedded networks that have to reliably transfer small amounts of critical data between nodes 4 13 1 1 ISO 7 Layer Model In the ISO seven layer model the CAN protocol covers the layer two data link layer that is forming the message packet error containment acknowledgment and arbitration CAN does not rigidly define the layer 1 Physical layer so can messages may be run over many different physical media However the most common physical layer is a twisted pair and standard line drivers are available The other layers in the ISO model are effectively empty and the application code directly addresses the registers of the CAN peripheral In effect the CAN peripheral can be used as a glorified UART without the need for an expensive and complex protocol stack Since CAN is also used in industrial automation there are a number of software standards that define how the CAN messages are used to transfer data between different manufacturers equipment The most popular of these application layer standards are CANopen and DeviceNET The sole purpose of these standards is to provide interoperability between different OEM equipment If you are developing your own closed system
42. forced to ARM 32 bit M and of exception The THUMB instruction set has the more traditional PUSH and POP instructions for stack manipulation They implement a fully descending stack hardwired to R13 Pop je Bs Fi Ge The THUMB instruction set has dedicated PUSH and POP instructions which implement a descending stack using R13 as a stack pointer fi Hitex UK Ltd Page 23 Chapter 1 The ARM9 CPU Core hi te X Se Finally the THUMB instruction set does contain a SWI instruction which works in the same way as in the ARM instruction set but it only contains 8 unused bits to give a maximum of 255 SWI calls 1 14 Summary At the end of this chapter you should have a basic understanding of the ARM9 CPU Please see the bibliography for a list of books that address the ARMS9 in more detail Also included on the CD is a copy of the ARM9 user manual Hitex UK Ltd Page 24 KELLER SA I H ET e 1 c S PS 23 Chapter 1 The ARM9 CPU Core hitex im O Hitex UK Ltd Page 25 Chapter 2 Software Development E LOPA EM ET e 1 c S PS 23 Hitex UK Ltd Page 26 hitex vo Chapter 2 Software Development TEE SY E i OR B I H d m Es D 2 Chapter 2 Software Development 2 1 Outline Having read Chapter One you should now have an understanding of the ARM9 CPU In this chapter we will look at how to write and debug C code for the ARMY The example program
43. interrupt generated When a fresh packet of data is received the endpoint RX status field is set to 0x02 which means any further communication on this endpoint will receive a NAK handshake When the device firmware responds to the interrupt it must copy the data from the receive buffer and re enable the endpoint by setting the status field back to 0x03 Hitex UK Ltd Page 153 DEVELOPMENT TOOLE Chapter 4 User Peripherals hitex um Similarly for an IN transfer the application firmware must fill the endpoint TX buffer with a data packet and then enable the endpoint via the TX status field When the USB host requests the data the packet will be transferred and the endpoint disabled The firmware must then refill and re enable the endpoint ready for the next request When an IN request is made to an STR9 endpoint the contents of the endpoint buffer will be sent to the USB master Further communication from the endpoint is disabled generates only NAKs until the buffer is refilled and the endpoint is reactivated T x Bular This level of buffering is fine for control and interrupt transfers but isochronous transfers potentially have large data packets and bulk endpoints may have several transfers in the one frame In order to support these higher bandwidth endpoints the STR9 USB peripheral has a double buffer option to use both the transmit and receive buffers to store data for a unidirectional endpoint If an endpoint is con
44. keyboard shortcuts as these are the fastest way to control the execution of your code D SetiRemove Breakpoint Ctrl B GA Show PC Location ia Download Ctrl D Upload lel Go F5 Go disable Ctri F5 Hi step Into Fi Step Instruction Fa TP step Over F10 F step Out Ctrl F11 A Go until Shift F10 11 Goto Cursor Ctrl F10 TA Reset Alt R Resek amp ao Ctrl F Breakpoints Hitex UK Ltd Page 167 Chapter 5 Tutorial Exercises hitex mm DEVELOPMENT TOOLE The source window allows you to browse your C code for any module in the project There is also a disassembly window that will show you the actual contents of the program memory Disassembly startup main interrupt main c int main void d Li ines At BEGIN USER CODE MAIN INITZ BEnable IZC module 0 Misco oan2 0x80 dget frequency bits Brzco CR Oxzo enable the IZC module Brzco CR Ox20 E SJ O SCO CR scs ffenable the ITE interrupt Misco CCR Ox c set the bit rate at 50K Bizco Ecen 0x03 J220 oani 0x01 f Set own address 4 lt Ili gt The Project Window allows you to browse your project Double clicking on a module or function name will open the selected file in the source code window Workspace ModuleView first E A interrupt fi GAbt Handler f FIG Handler f patt Handler f SwI Handler f Undet Handler EM LED control MC Variables elf write LED array Ea libifu
45. lb eines 117 442 2 ee EE 118 412 1 2CAQAT SSINQ 2m dass teo ata em cac scans 120 2 12 2Slave le 121 4123120 Master dee EE 122 4 18 ee Ke eut e GE rias ioni iE a IN te nds 124 4 19 1 1 ISO 7 Laver Models ova eot o o vete e ve Ce hv tees 124 4 13 1 2 CAN Node Design 125 4 13 1 3 CAN Message Obecle 126 4 13 1 4 CAN Bus Arbitration i i ieu ree ede etd aetas ies 127 4 19 20 ele TR 128 e Date GE BIL TMN ose tetuer a btt uode P ovato Saa eara 129 4 13 2 2 Configuring the CAN Module 131 4 13 3CAN Module IO Pins ss 132 4 13 4Using the CAN module 132 AAS Ale BASIC ue el 132 4 1942 FUI GAIN MOUe ie occ c E baeo oe tbe rene 134 4 13 4 3 CAN Error Containment 137 4 13 4 4 CAN Bus Error Handling 139 419449 CAN Eer 140 4 13 4 6 Deterministic CAN Protocols 140 4 13 5USB 2 0 Full Speed Slave Peripheral 141 4 13 5 1 Introduction TO LJ SB e mto idee ast paid 141 413 532 XJ SB Peripherdal iei eub e 151 E E Tan ET 158 Chapter 5 Tutorial Exercises 160 Bel eg ele Ter en EE 160 5 2 Further STR91x Examples ire eege 160 5 3 Exercise 1 The FIRST STR9 Example Program 161 oO EANO EES 166 5 925 RN OODEOL ege ee 167 9 9 1 3 VICWING Dalaran marne 171 5 924 HITOP Project Seting S EE 173 5 3 1 5 Advanced KEE e e EE 174 5 9 10 SCHDLLANQUATE uu cundi a und iain Ee 175 Due Project Re EE 176 5 4 Exercise 2 Startu
46. loss of any on chip resources 2 3 Startup Code In our example project we have a number of source files In practice the c files are your source code but the file startup s is an Assembler module provided by Hitex to support the STR9 microcontroller As its name implies the startup code is located to run from the reset vector It provides the exception vector table as well as initialising the stack pointer for the different operating modes It also initialises some of the on chip system peripherals and the on chip RAM before it jumps to the main function in your C code The startup code will vary depending on which ARMS device you are using and which compiler you are using so for your own project it is important to make sure you are using the correct file First of all the startup code provides the exception vector table as shown below RAKKKKKKKKKKKK KKK KKK ck kCkck Ck k k kCk KKK k ck kCkcCkck KKK KKK KKK KKK KK KKK KKK KKK KKK KKK ck ck KKK KK Exception Vectors RKKKKKKKKKKKK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KK ck ck KKK KK Vectors LDR PC Reset_Addr Located at address 0x0000 LDR PC Undef Addr 0Ox0004 LDR PC SWI Addr 0x0008 LDR PC PAbt Addr 0x000C LDR PC DAbt Addr 0x0010 NOP 0x0014 Reserved Vector LDR PC PCy OxF FO 0x0018 wraps around address space to OxFFFFFFO30 Vector from VicVECAddr LDR PC FIQ Addr 0x001C FIQ has no
47. message is sent and then each CAN message is allocated a slot within which it must send its data Using this approach there is no arbitration and each message is guaranteed to be delivered at a regular and known rate However the TTCAN protocol cannot be implemented with a standard CAN controller because if there is a bus error a CAN message would automatically resent This would cause a message to be sent in the next slot and destroy the determinism of the system The STR9 CAN controller has been designed to support the TTCAN protocol by allowing the automatic retransmission of messages to be switched off This ensures that if a bus error occurs the message will be abandoned for this frame and will be resent by software in its correct slot in the next frame The automatic retransmission can be setting by clearing the DAR bit in the control register Exercise 17 CAN loopback This exercise configures the CAN controller in Full CAN mode and uses the loopback test mode to simulate sending and receiving CAN message packets Hitex UK Ltd Page 140 Chapter 4 User Peripherals 4 13 5 USB 2 0 Full Speed Slave Peripheral One of the most complex peripherals available in the STR9 family is the USB peripheral In order to fully understand this peripheral you will also need a clear understanding of how the USB network operates and to build a USB based system you will also need to know how to build a PC application that can access the USB network T
48. of technical information is spread over the first four chapters which should be read in order if you are completely new to the STR9 and the ARMg CPU Throughout these chapters various exercises are listed Each of these exercises is described in detail in Chapter Five the Tutorial section The Tutorial contains a worksheet for each exercise which steps you through an important aspect of the STR9 All of the exercises are based on the Hitex STR9 evaluation kit which comes with an STR912FW44 evaluation board and a JTAG debugger as well as the GCC ARM compiler toolchain It is hoped that by reading the book and doing the exercises you will quickly become familiar with the STR91x family of microcontrollers www hitex co uk hitex mum DEVELOPMENT TOOLS Hitex UK Ltd Sir William Lyons Road Science Park Coventry UK CV4 7EZ Tel 44 0 2476 692066
49. one bus master Host Root Tier The physical USB network is a tiered star with one master node and up to 127 slave nodes and a maximum of five tiers Tier 1 Hitex UK Ltd Page 142 hitex mm Chapter 4 User Peripherals DEWVELOHP s EM d m Wal D 4 13 5 1 2 Logical Network However to the developer the logical USB network appears as a star network The hub components do not introduce any programming complexity are essencially invisible as far as the programmer is concerned So if you develop a USB device by connecting it to a root port on the PC the same device will work when connected to the PC via several intermediate hubs So to the programmer the USB network appears as a star network with the PC at the center and all the USB devices are available as addressable nodes To the programmer the USB network appears as a 8 master slave star network The other key feature of the US network is that it is a master slave network The PC is in control and is the only device on the network that can initiate a data transfer With USB 2 0 peer to peer communication is not possible and the STR9 USB peripheral is a slave device only and cannot act as a master A version of USB called USB on the go is a new addition to the specification and directly supports peer to peer communication allowing for example pictures stored on a camera to be transferred directly onto a USB memory stick without the need for a PC or other USB master
50. or little endian processor That is the MSB is located at the high order bit or the low order bit You may be pleased to hear that the STR9 family fixes the endianess of the MES LSB processor as little endian i e MSB at highest bit address which does make it a lot easier to work with However the ARM9 compiler Ls MT you are working with will be able to compile code as little endian or big endian You must be sure you have it set correctly or the compiled code will be back to front W JI EM The ARM7 CPU is designed to support code compiler in big endian or little endian format The One of the ST silicon is fixed as little endian most B 31 B4 o interesting features of the ARM instruction set is that every instruction may be conditionally executed In a more traditional microcontroller the only conditional instructions are conditional branches and maybe a few others like bit test and set However in the ARM instruction set the top four bits of the operand are compared to the condition codes in the CPSR If they do not match then the instruction is not executed and passes through the pipeline as a NOP no operation Bg endear 31 2H Every ARM 32 bit instruction is conditionally executed The top four bits are ANDed with the CPSR condition codes If they do not match the instruction is executed as a NOP COND So it is possible to perform a data processing instruction which affects the condition codes in the CPSR
51. plus the time taken to read the IRQ status register and decide which routine to run FIQ Interrupt Sync Worst Case Instruction execution Entry to first Instruction FIQ Latency 12 cycles 200 nS 60MHz IRQ Interrupt sync worst case instruction execution Entry to first instruction Nesting IRQ Latency 25 cycles 416nS 60MHz 3 8 16 Nested Interrupts The interrupt structure within the ARM9 CPU and the VIC does not support nested interrupts If your application requires interrupts to be able to interrupt ISRs then you must provide support for this in software Fortunately this is easy to do with a couple of macros Before discussing how nested interrupts work it is important to remember that the IRQ interrupt is disabled when the ARM9 CPU responds to an external interrupt Also on entry to a C function that has been declared as an IRQ interrupt routine the LR_isr is pushed onto the stack IRQ Mode System Mode Once the processor has entered the IRQ interrupt routine we need to execute a few instructions to enable nested interrupt handling First of all the SPSR_irq must be preserved by placing it on the stack This allows us to restore the CPSR correctly when we return to user mode Next we must enable the IRQ interrupt to allow further interrupts and switch to the system mode remember system mode is user mode but the MSR and MRS instructions work In system mode the new link register must again be preserv
52. set to HiZ tristate alternate input 1 for the CAN peripheral to work GPIO one Gpios ep GPIO3 GPIO Mode Alternate Out 2 Alternate Out 3 Alternate In 1 Pin 0 X X X X X Pin 1 X X X X X Pin 2 X X CAN TX X X Pin 3 X X X X CAN RX Pin 4 X X X X X Pin 5 CAN RX X X X X Pin 6 X CAN TX X CAN TX X Pin 7 X X X X X GPIO5 GPIO5 GPIO7 GPIO Mode Alternate In 1 Alternate Out 2 Alternate In 1 Pin 0 CAN RX X X Pin 1 X CAN TX X Pin 2 X X X Pin 3 X X X Pin 4 X X X Pin 5 X X X Pin 6 X X X Pin 7 X X X 4 13 4 Using the CAN module Once the CAN module is fully configured it may be used to send and receive packets of data The STR9 CAN module has two operating modes For simple CAN networks with low data rates there is an easy to use basic CAN mode which has a single transmit and receive buffer For more demanding networks with higher data rates there is a full CAN mode which has multiple transmit and receive buffers In either of these modes the CAN data is accesses via the message interface registers The CAN module has two sets of message interface Message intertace t registers In Basic mode these act as transmit and receive buffers In Full can mode they act as windows Message interlace 1 Ans sce Interace 4 13 4 1 Basic mode The CAN module enters the basic can mode during initialisation by setting the basic bit in the test register Hitex UK Ltd Page 132 hitex mum Chapter 4 User Peripherals DEVE
53. single style transfer must be initiated with the software burst or software single request registers 3 9 2 DMA synchronisation The DMA units can work across all the internal STR9 busses If these busses are running at different speeds the synchronisation bits for the different DMA request signals must be set in the synchronisation register This will eliminate any bus problems but does effect the DMA response time Hitex UK Ltd Page 75 hitex Chapter 3 System Peripherals ELOPAK 3 9 3 DMA Arbitration Within the STR9 the ARM9 CPU Ethernet DMA and the general purpose DMA controller can all be bus masters on the AHB bus For each of these units to work together there has to be an internal arbitration process Generally the CPU can be stalled when it attempts to access the SRAM during a DMA transfer INSTRUCTIONS ARM TDMI PERIPHERALS The STR9 has been designed with custom arbiter hardware that solves this bottleneck problem This hardware arbitrates access to the SRAM between the ARM9 CPU and the internal SRAM and guarantees access to either bus master on every other cycle In addition for high priority DMA transfers it is possible to allow the DMA units to lock the bus and burst transfer blocks of data When a DMA unit has locked the bus it will not de grant its access until its transfer has finished This can be combined with a burst transfer of up to 256 words INSTRUCTIONS ITCM PFQ BC BURST FLASH AR
54. the GNU ARM tools The FIRST program is located in the subdirectory First Start Hitop using the icon A Hitop will start with a blank workspace m dm pee ges md TS es mz es EG Ulf B LF ee ns Se bem T min tq mae La mca decas s O Hitex UK Ltd Page 161 hitex mm Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS Connect the TantinoARM JTAG cable to the JTAG connector on the STR9 board and then attach the TantinoARM to a free USB on your PC using the cable provided Insert the power plug and turn the power supply on Now use the Hitop Project Open project menu to open the FIRST HTP project file in STR910FExamples First You may need to navigate to the required directory Mh DN Ree fmn pee Kid pue nn Lak m L3 Frs Oo Um i a b i s Ze Tea L i DS E Sori E ihi Ce T y Fa rm Sri hag Tin o ke ed F L Once you double click on First htp Hitop will initialise and attempt to connect to your TantinoARM Hitex UK Ltd Page 162 Chapter 5 Tutorial Exercises hitex mms DEVELOPMENT TOOLE Hitop will search for any TantinoARMs connected and then ask you to enter the serial number of your one aliii K LES LIE de ES di De Tantino tar 2270 WOT Found Ust al connected devices LIA 2 Hitop then reports that it cannot connect to TantinoARM 2270 1 Hitop was expecting the default TantinoARM serial number but here it found number
55. the code will be executed until it while 1 reaches this point If you move the mouse pointer further to the left the braces are replaced by a circle BEGIN USER CODE MAIN LOOP If you left click again a breakpoint will be set and will be shown graphically as a red bar across the source E code and a red circle in the margin ri P pla ae ME H A for i 0 1 BLINEY DELAY i IO CLRPORT IO OFF for i 0 1 BLINEY DELAY i END USER CODE MAIN LOOP Te The ARM9 TDMI JTAG module supports two hardware breakpoints When you are debugging from FLASH this requires careful management However the Tantino also supports software breakpoints so building your application to run from RAM will allow additional breakpoints to be set It is also possible to set breakpoints on data variables This allows you to halt code when a variable is read or written too Open the breakpoint menu under debug breakpoint and select the data tab ES pro System window Hep Breakpoints Je Download ctri D i CH Adress Le Type IB Upload LE Go F5 Go disable Chr F5 f Step Into F11 Step Instruction FQ DH Step Over F10 DH step Out Ctrl F11 c Go until Shift F10 1 Gato Cursor Ctrl F10 TR Reset AlE R Reset Go Ctrl F EI SetiRemove Breakpoint Ctrl B n CS Show PC Location Hitex UK Ltd Page 169 hitex mum DEVELOPMENT TOOLS Chapter 5 Tutorial Exercises Now locate the varia
56. the contents of this region will be preserved If you uncheck it you must perform EU ce Ras Dr van e BCE Mas h EI pn wn LEAS Be e STAR ah ol Dae Ei lapion Aneta KE E xc phom l bd gr E onis Ex Sector fet ra e Sab ig E Sh por ze rrj E updas being Shut Sarei Kn Paisi Later PRU Soe be Fly Lh mH p Ful tram Acker ll Fab Sie A8 fe Sone md erie Hd corres rel at Iren Fee i Floride Eppe San SAS ed B NON Chir al add H Tal Ere E E rakim F Lai h Poo groe a target reset after download to restart the application However the download process will be faster O Hitex UK Ltd Page 173 hitex mum Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS 5 3 1 5 Advanced Breakpoints In the emulator settings menu the TAP clock is configured for the ARM9 microcontroller you are using and does not need to be changed However the breakpoint settings menu does have several important options First it is possible to force the JTAG to use software or hardware breakpoints If you are debugging from RAM a software breakpoint will replace the application opcode with a breakpoint instruction although this is hidden from the user reject settings b pnon EN c See Feet Len feed rr boat i P Pe E M Flat AR sicura 5 sie vehe AFF ES parti Eu E STAT ab Ew niat allied EN Demin Autant aloe Inn aite violator occur vi E ececissn E rimi ne Controles z El Emish Sege L5ndho n nav b
57. you do not need these application layer protocols and are free to implement you own proprietary protocol which is what most people do in practice Object layer Application Laver Prioritizer Message Handling Acceptance filtering Presentation Laver Transfer Laver Session Laver Fault confinement Error detection Acknowledgement Message framing Transport Laver Arbitration Network Laver Physical layer Data Link Laver Bit representation Transter rate Physical Laver Signal level and timing Transmission medium Hitex UK Ltd Page 124 Chapter 4 User Peripherals F E LOF LE I Wl a O i 4 13 1 2 CAN Node Design A typical CAN node is shown below Each node consists of a microcontroller and a separate CAN controller The CAN controller may as in the case of the STR9 be fabricated on the same silicon as the microcontroller or it may be a stand alone controller in a separate chip to the microcontroller The CAN controller is interfaced to the twisted pair by a line driver and the twisted pair is terminated at either end by a 120 Ohm resistor The most common mistake with a first CAN network is to forget the terminating resistors and then nothing works Microcontroller CAN node hardware A typical CAN node has a microcontroller CAN controller physical layer and is connected to a twisted pair terminated by 120 Ohm resistors CANL CAN H Ri Fi One important feature about the CAN node design is that the CAN
58. 000000 2 256 11718 75 Deadtime Generator register MC DTQ 1 2us deadtime required for IGBT bridge MC DTG Delay PCLK 2 1 2E 6 96000000 2 Of Initialise PWM System Set PWM Period Carrier Frequency Zero centred mode deadtime enabled Clear PWM counter MC gt PCRO MC DIE Set MC CMS S t MC ODCS Set MC CPC Set Tacho not used yet MC gt PCRIL 0 Enable hardware transfer triggered by repetition counter No interrupts yet MC gt PCR2 0 3 Set Phase Output Polarities MC gt PSR 0x2A High outputs are inverted compare interrupts on up count Setup clocks for approx 12kHz carrier 8 bit resolution Zero centred mode Note PCLK RCLK Fmstr 96MHz MC gt CPRS 16 96000000 2 256 12kHz 15 625 16 gt 11718 75Hz Carrier MC CMP0 256 Set 8 bit resolution PWM PWM counter runs from 0 256 0 Set Deadtime MC gt DTG 57 Set initial deadtime to 1 2us 57 x 2 PCLK Setup repetition rate MC gt REP 0 Update PWM compare registers every PWM carrier O Hitex UK Ltd Page 100 Chapter 4 User Peripherals A drive built along these lines would be a simple open loop Sine PWM drive A refinement of this would be a Space Vector Modulation SVM drive which offers higher torque for the same DC supply voltage Real drives would have to cater for over current and over voltage conditions drive start stop acceleration deceleration ramps
59. 1 In PWM mode the timer starts from OxFFFC A compare event on Compare A register forces the output compare A pin low A compare match on compare B register forces the same pin high and reloads the timer with OxFFFC to restart the cycle At the start of a cycle the timer is reset to OXFFFC and the OCMP1 pin is set high The value loaded into the compare 1 register is the period of the pulse when this match is made the compare event loads logic zero stored in OLV1 into the output compare pin The PWM period is stored in the compare 1 register when this count matches the timer contents the logic one value stored in OLV2 is applied to the output pin and the timer is reset not to zero but to OXFFFC and the cycle is restarted So in order to modulate the pwm signal it is only necessary to write to output capture register 1 Hitex UK Ltd Page 93 hitex mum DEVELOPMENT TOOLS Chapter 4 User Peripherals TIM1 OCAR 0x00000080 Set the capture 1 count pulse falling edge TIM1 OCBR 0x000000FF Set the PWM period TIM1 CNTR 0x000000000 initialise the count TIM1 CR2 0x000008FF enable the capture 2 interrupt and set the prescaler TIMI1 CR1 0x00008150 Timer enable set output levels on compare 1 enable compare 1 and PWM mode 4 5 5 One Pulse Mode The STRO9 timers have an additional useful mode that can generate a pulse that is triggered by an external signal Counter ER jeten OCAR 0x2
60. 1564 yours will be some other number 3 It then stops attempting to connect 4 Hitop then asks you start a new connection procedure Just click Next 5 Enter the serial number of your TantinoARM here it was 1564 and click connect Hitex UK Ltd Page 163 Chapter 5 Tutorial Exercises hitex Ex DEVELOPMENT TO OLE When the licence reminder screen is be displayed click the l want to continue evaluation button You also have the option to purchase a full licence or get a 30 day trial licence that has HOP has not loi amp bull cente lor og tem no code limitations HiTOP allows you lo download applications which are code ie bled to 166 Bytes Upgrade cvalualion license Once you have passed the reminder screen HiTOP will start and ask if you want to download your application to the STR9 FLASH memory Click OK to begin the FLASH download If an error occurs at this point it will most likely be that the boot jumpers are incorrectly set on the evaluation board M Land bo Doro Tull kene Tou can gel a 30 dayr koanta valhiout code sie lent ah rcr he liee o pou may quarc hee Pull ere Download Applications able Plath Programming Veris alie Dioverdoad After the FLASH download has finished your project will be fully loaded and ready for a debug session E BS de Fa Pre Fa Fe F w e wo I o3 s AT j EE FES bee nm A
61. 2 bit to 16 bit code and the THUMB flag in the CPSR ATTN 7 m zZ The T flag is set when you are im Thumb mode Hitex UK Ltd Page 178 hitex mm Chapter 5 Tutorial Exercises e DEVELOPMENT TOOLS 6 Note the contents of the link register single step F11 until you return to the ARM code Check the return address matched the value stored in the link register Note the actual return address in your program might not be identical to that shown here Pe 1F4 ra SRFEFE H ah Fire nj aera i id WFA Aoii n P3 FOFFFFEA hb rib 1s toca nr Cate ra Weg Par Pe E The m rapada slice Ces F3 as the rete address Hitex UK Ltd Page 179 Chapter 5 Tutorial Exercises hitex ES DEVELOPMENT TOOLS 5 6 Exercise 4 Software Interrupt In this exercise we will define an inline Assembler function to call a software interrupt and place the value 0x02 in the calling instruction In the Software Interrupt SWI we will decode the instruction to see which SWI function has been called and then use a case statement to run the appropriate code 1 Open the HiTOP project in EX4 SWI 2 Execute the program up to the first software interrupt call while il d BEGIN USER CODE MAIN LOOP 3 Switch to disassembler mode and examine the SWI opcode and note the address of the instruction 7 SofbnareInterrupti O000001F8 O1O000EF swi 1h 4 Step the software interrupt instruction F11 and see the jump to the
62. 20 words Within this address range each bit of the eight bit address between bits 9 and 2 act as a masking bit on the data written to the port So at the base address of the GPIO data register the address bits are all set to zero and hence any data written to this address will be logically ANDed with zero and the port data will not change By writing to the GPIO data register address plus an address offset equal to the mask value shifted left two places will cause the data to be logically ANDed with the mask address bits and the resulting value will be written to the port pins Bits 2 9 in the GPIO data registers act as mask bits which are ANDed with the input data to derive the final value which is output the port pins Hitex UK Ltd Page 84 Chapter 4 User Peripherals In practice we can set any mask value by simply adding the mask value shifted left two places to the base address of the GPIO DATA register Since this address is calculated at compile time there is both an increase in performance and a reduction in the code size GPIODATA mask lt lt 2 data The example program include some useful definitions for handling this GPIO Mask Definitions Definitions to control which pins get written to or read define Write Bit OU 0x04 define Write Bit 1 0x08 define Write Bit 2 0x10 define Write Bit 3 0x20 define Write Bit 4 0x40 define Write Bit 5 0x80 define Write Bit 6 0x100
63. ADC CE ke Ji f Claar sud of Zobt rti en intarrzup Check Cor amaslog watchdog trigoered E aT IrrepruptrLags D OSS Lowes Irmsta syssasder resale ARS Threshoid Neka e cloba copy of the result Fo Bn 8 mum f mor RAR vs lan mi Ma Jiu 1 cau BA Cire May PRG B amp Lu lies i temp AbC CRR L Ox0001 dear wetrhdem bit Abzc zER Sip Brite whole Fagiater ADcC CE Li F Cl dt Wwatcadey erant pid Hitex UK Ltd Page 189 hitex Chapter 5 Tutorial Exercises DEVELOPMENT TOOL 5 15 Exercise 13 Watchdog This exercise configures and serves the watchdog and demonstrates the problems of trying to debug an application with the watchdog enabled 1 Open the WD HTP project in STR910Examples WD remember to enter the serial number of your Tantino when asked 2 Run the code up to the watchdog enable line D oc BEGIN USER E Mari SIE LI AL en en e C c mos RENI USER CODE MAIN INITZ 3 Start the code running at full speed 4 Press the INT interrupt button on the STR9 board This will force the CPU to execute a tight loop without serving the watchdog 5 Try to halt the program execution The execution will seemed to have stopped but any attempt to restart the program will result in an error 6 When the watchdog times out it resets the processor and the on chip JTAG module This causes the debugger to loose control of the STR9 7 To recover from such a fail
64. BITER DTCM DATA CORE a ENET ARM966 Internally the DMA units have a fixed priority DMA unit O has the highest priority with DMA unit 7 having the lowest priority If a low priority DMA unit is active and a high priority transfer is initiated the low priority unit will complete its transfer before de granting the bus The two lowest priority DMA units will automatically de grant the bus for one cycle every four transfers This ensures that the low priority DMA units do not block the bus For this reason large memory to memory transfers should use either DMA unit 6 or 7 Hitex UK Ltd Page 76 hitex mum DEVELOPMENT TOOLE Chapter 3 System Peripherals 3 9 4 Memory To Memory Transfer Once the DMA unit has been enabled and the interrupts have been configured the channel registers may be configured for individual transfers In the case of a memory to memory transfer the start source and destination addresses are programmed into the eponymous registers The linked list register is used for scatter gather transfers and in a single transfer should be set to zero 31 30 28 26 27 26 28 28 23 22 21 20 18 18 17 16 L ir d 0 E d Hi Each DMA unit has a control register that defines the characteristics of each DMA transfer The control register allows you to set the transfer size on the destination bus when the DMA unit is the flow controller when peripherals are the flow controller this field should
65. CLK Reset WDG RTC CLK Interrupt However if you do not require a this form of protection in your application the watchdog may be used as free running timer that can generate a periodic interrupt for an operating system of scheduler freeing up one of the more complex timer blocks The watchdog interface allows the watchdog to be configured as an on chip watchdog or periodic timer with an end of count interrupt The watchdog timer is a 16 bit count down counter with an eight bit prescaler The prescaler and watchdog counter reload have dedicated registers and the timeout period may be calculated with the following formula Timeout in microseconds Prescaler 1 x reloadvalue 1 x Tpclk2 1000 Once the timer registers have been configured the watchdog may be started by setting the watchdog enable bit in the control register Once this bit is set there is no way other than a hardware reset to disable the watchdog Unlike the other peripherals you cannot stop the peripheral clock to the watchdog in the PRCCU To stop the watchdog from timing out and causing a reset you must write to the watchdog key register this forces a reload of the watchdog timer To ensure that the application software is still running ok the watchdog reload will only occur Hitex UK Ltd Page 109 hitex vo DESI LO RH LU E Wl rFTOJO c Wal D Chapter 4 User Peripherals if the values 0xA55A follows by 0x5AA5 are written consecutively to the Ke
66. EVELOPMENT TOOLS Finally the external memory bus clock can be configured in the clock control register In this register the EMIRATIO bits define the speed of the external bus clock as a ratio of the clock used for peripherals located on the high speed bus HCLK This clock can be applied directly to the external bus or it may be divided by two HCLK itself is derived from the main CPU clock via a divider that can scale down the CPU clock by selectable factor of 1 2 or 4 31 30 e a 427 s 25 ug ZS zi e IR B 17 18 EMIRATION FMISEL EL 15 14 13 12 HM 10 n B T B8 5 4 A 2 U 0 f 2 F LABEL Z APSOL 0 AMONT D RCLKOCVI CO MCLESEL os re rm rm rm rm rnm rm i H Fe m re re m Kl The system clock control register allows you to define the ratio of the EMI clock to the internal clocks with the EMIRATIO field This ratio may be 1 1 or 1 2 Once the basic characteristics of the external bus have been configured the individual chipselects can be configured with the external memory interface registers IDLE Cycie Control n Each chipselect is controlled by six registers These n registers predominantly control the number of Wire Wait Sue Control waitstates in each part of the read write cycle Outpul Enaeie Control Wie Enable Control Each chipselect is configured by six dedicated registers within the EMI register block The register set for each chipselect is identical so configuration of chips
67. FD0 UA OLVLA 0 OCMPA A OLVLB d ovma oma OLVLB 1 lt Compare A One pulse mode uses the two capture registers to define the rise and fall edges of a pulse which can then be triggered by an input capture pin One pulse mode is enabled by setting the OPM bit in control register 1 In this mode the pulse generation is triggered by a capture event on ICAP1 pin This can be a rising or falling edge which is programmed by the IEDG1 bit Once this event is triggered the timer will output a pulse whose characteristics are determined by the two compare registers When the trigger event occurs the timer is reset to OXFFFC and the contents of OLVL2 bit is loaded into output compare pin 1 when the timer matches the contents of output compare register 1the logic level in OLVL1 bit is loaded into output compare pin 1and the timer then waits for the next capture event TIM1 OCAR 0x0000FF00 Set the pulse length TIM1 CR2 OxO000FF set the prescaler LMI CR 0x0008265 Timer enable set the pulse output level on OCMP1 pin enable one pulse mode set capture edge 4 5 6 DMA Support Timer 0 and Timer 1 may be connected to a DMA unit This channel allows the capture and compare registers to act as a DMA source or sink The DMASO and DMAS bits in control register 1 allow you to select the source register for the DMA transfer The source register can be either of the input capture registers ICAP1 ICAP2 or the output compare r
68. GEW 0x400 PC e OxBDOO T 1 The branch exchange and branch link exchange instructions perform the same jumps as branch and branch link but also swap instruction sets from ARM to THUMB and vice versa D A OBO Dx4D PC e ORK F 1 A4 0x400s4 OXBDOO This is the only method you should use to swap instruction sets as directly manipulating the T bit in the CPSR can lead to unpredictable results 1 7 2 Data Processing Instructions The general form for all data processing instructions is shown below Each instruction has a result register and two operands The first operand must be a register but the second can be a register or an immediate value OP code Operands 42 bit shafi T ki The general structure of the data processing instructions allows A a one cycle Conditional execution Enable condition code flags In addition the ARM9 core contains a barrel shifter which allows the second operand to be shifted by a full 32 bits within the instruction cycle The S bit is used to control the condition codes If it is set the condition codes are modified depending on the result of the instruction If it is clear no update is made If however the PC R15 is specified as the result register and the S flag is set this will cause the SPSR of the current mode to be copied to the CPSR This is used at the end of an exception to restore the PC and switch back to the original mode Do not try this when you are in the USER mo
69. IN CO DOUT Pin 2 DC CLKIN GC CLKOUT Pin 3 I2C1 DIN DC DOUT Pin 4 X l2C0 CLKIN 12C0 CLKOUT Pin 5 X X X Pin 6 X CO DIN CO DOUT Pin 7 X X X GPIO2 GPIO2 Pin 0 l2C0 CLKIN 12C0 CLKOUT Pin 1 CO DIN CO DOUT Pin 2 DC CLKIN GC CLKOUT Pin 3 Il2C1 DIN DC DOUT Pin 4 X X Pin 5 X X Pin 6 X X Pin 7 X X The 12C modules support I2C communications up to 400KHz and can operate in both master and slave mode The 12C peripheral also supports multi master communication Each I2C peripheral is interfaced to other DC devices by two pins One of these pins is used to carry the serial clock and the other the serial data 3 3V 3 3V 3 3V Q Q Q R75 me 10k R74 NNNM 10k SDA OND m AT24C04 m a wi 3 E X E CN I 78 x SE dd RE IZL_DATA P31 IZ2C CLK b TEMP ALARM b o o es LM75 O Hitex UK Ltd Page 118 hitex mum Chapter 4 User Peripherals DEVELOPMENT TOOLS Like the SPI protocol I2C is a master slave protocol In a typical system a single master controls all communication and the slaves can only respond to its commands Unlike SPI the I2C protocol is an address based serial networking protocol that allows up to 127 nodes to be connected to a master using only two wires A typical 12C bus transaction is shown below KS e As Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high S START condstion From Slave to Master P STOP condition The transaction begin
70. In addition every new device that is plugged onto the network will be assigned address zero This way the PC knows what bit rate to use and will have one control channel available at address zero endpoint zero This control pipe is then used by the PC to discover the capabilities of the new device and to add it to the network The process the PC uses to gather this information is called Enumeration So in addition to configuring the USB peripheral on the STR9 you need to provide some firmware that responds to the PC enumeration requests The data that the PC requests is held in a hierarchy of descriptors The descriptors are simply arrays of data that must be transferred to the PC in response to enumeration requests As you can see from the picture below it is possible to build complex device configurations because the USB network has been designed to be as flexible and as future proof as possible However the minimum number of descriptors required is a device descriptor configuration descriptor interface descriptor and three endpoint descriptors one control one IN and one OUT pipe CET ETES Dale gece The configuration information for enpa Van spas every USB node is described as a hierarchy of descriptors which are transferred to the PC during the device enumeration procedure nids Vasa Pele TL P DF PIE E EL qum TEE 4 13 5 1 9 Device Descriptor At the top of the descriptor tree is the device descriptor This descriptor contains
71. LOCK HTPr 2 Examine the equate for the clock module which define the internal clock speeds 3 Run the code to main and check the setup in the sfr clock window 4 Runthe code at full speed and the LEDs will be flashed by the CPU 5 Press the S1 interrupt button the CPU will enter the IRQ mode we will look at the interrupt structure later and the special interrupt mode will switch the CPU clock to 96 MHz Observe the increase in the LED update rate Hitex UK Ltd Page 181 Chapter 5 Tutorial Exercises hitex Ex DEVELOPMENT TO OLE 5 8 Exercise 6 IRQ Interrupts This example uses the watchdog to generate an IRQ interrupt This example examines the action of the dual VIC units 1 Open the HITOP project ST910FExamples IRQ IRQ entering the serial number on the base of your Tantino 2 Run the application to main 3 Run the code until it reaches the while 1 loop 4 Examine the interrupt configuration code for the VIC 5 Switch back to the source window and locate the Watchdog_IRQ_ISR function in the code browser and set a breakpoint gl IRQ ou Pr interrupt main fO init f main HI W abchdog IRG isr EE startup Rie Globals Show source 5 NES Properties Search 1 Run the code and the watchdog will generate an interrupt when it times out 2 When the code halts at the entry to the ISR switch to the disassembly window and check that the entry address matches the value stored in
72. LOPMENT TOOLS The test register contains the BASIC bit which switches the CAN controller between Full and Basic CAN modes When basic mode is entered the message interface registers are configured as a transmit and receive buffer The message interface registers are used as transmit and receive buffers in basic mode In full CAN mode they are used to program the 32 message objects in the CAN message RAM In the basic mode the IF1 registers act as the transmit buffers and the IF2 registers act as the receive buffers However both interface blocks have the same register layout To transmit a message in basic mode the message identifier must be programmed into the arbitration registers Next the message data is placed in the data registers and the data length code is programmed into the control register Finally to send the message the busy bit in the command register must be set Now the CAN message will be scheduled for transmission and will begin transmission as soon as the bus enters an idle state When a message is received its identifier is placed in the arbitration registers and the data is available from the data registers and a receive interrupt is generated This potentially means that in basic mode all messages on the network will be received by the STR9 CAN controller This would cause an interrupt on the CPU everytime there was data on the CAN network rapidly loading the CPU To avoid this problem the receive buffer has a message filt
73. MA unit it is best to first look at the simplest type of transfer that is memory to memory transfers this case the DMA unit will gain arbitration of the AHM bus and fetch the source data into its internal FIFO This data is then drained from the internal FIFO to the destination memory locations The fetching and draining of the DMA data can be done as single transfers or burst of several transfers In the case of burst transfers the DMA unit can assert a lock on the internal busses until each stage of the DMA transfer has completed The DMA unit is also capable of fetching and draining different sizes of data This means it is possible to pack and unpack data as part of a DMA transfer For example you could read in four 32 bit words of data from memory and then write out 16 bytes to the UART TX buffer When the DMA has won bus arbitration and is ready to transfer data it will handle the flow control of the fetch and drain transfers However when in the case of a peripheral to memory or memory to peripheral transfer then the peripheral can be the flow controller and will only allow a fetch or drain transfer when it is ready to sink or source data In addition the DMA unit supports scatter gather transfers Within each DMA unit you can define a series of DMA transfers as a series of linked list items These transfers are automatically performed one after another This allows data in non contiguous memory locations to be collected by the DMA unit and transfer to
74. O El 78 OO OF ES 10 FO 21 E3 mode re EN EM e O z00000090 UU DO AU El 40 AD 4D E2 OO 10 OF El 80 10 Cl E3 a startup 132 01 FO 29 Ei 65 10 Ob EB 68 20 Ob ES 65 30 OF EB ba DE EE TRS O Z000000B0 03 OO 52 E1 04 OO 91 34 04 OO 82 34 FB FF FF 34 na ln E startup 1S0 OO OO AO ES 54 10 Ob EB 54 20 GF EB 02 OO 51 El D T 0 r nennnnnnnn Ad nn 81 44 FO FF FF 34 FA nn Aan RA 44 10 GR FC A Ti You can set the address range of the window by double clicking on an entry in the address column and entering an absolute address or a symbolic name The contents of memory locations can be changed by overtyping the values in the data or ASCII window The more advanced options are available by right clicking the mouse The register window gives you access to the active register bank along with a X the CPSR and SPSR In this window you can modify the register contents ro ooooo o FN ri 20000224 z 1 and change the state of the CPSR SPSR flags gt Ee IDE r3 20000000 JI o r4 20000220 F o r5 ES CE004 Ir o ro E24DD004 Js M 1 7 ES 00000 fsz i ra 20000224 fsc o ra 20000224 s I 1 ug Z2000010C sF o ril Ei403000 s T 1 ria X ECO ri3 2000021C la OOO0OZES ri5 OOO00Z9C cpsr 60000010 spar DEADDEAD sp 20000217 Ir KKK B8 pc QOO 9c The watch window allows you to view program variables You can edit the current value contained in the variable by simply double clicking on the current value and entering a new value Hl Ge First oP
75. OL 5 3 1 6 Script Language The HiTOP debugger also contains a script language called HiSCRIPT Edit View Project Debug RTOS Syste This is a C like language that can be used to build software test D wa CrHN Im on c harnesses or simply automate common sequences within HiTOP G Open ctrito Close From the file menu select file logging open and create a file called i ResetGoMain scr in the HiSCRIPT directory of your project Make sure you have selected the scr extension Select the Log mode as ph Commands Only and overwrite the existing file H Save al amp b Print Chip Now select OK and any HiTOP instructions you do within the debugger Print Previews will be saved as HISCRIPT commands Once you have enabled logging Print Setup perform a target reset and a go until main Again select file logging and close option to stop the command logging Execute Script a Edit View Project Debug RTOS Syste This will generate a HiSCHRIPT file that will replay your instructions The actual HISCRIPT file contains some extra instructions but it can be edited down to the following minimal EE CkrH N ton O instructions IS Open CtrhO Close RESET TARGET i GO UNTIL main Save S The HiSCRIPT file can be added to the toolbar by highlighting the script toolbar right clicking and selecting change settings H Save al zz 8 Print Ctrl P SS Callstack Print Preview Ss Memory Frink Setup
76. ON e 4 1 mA MHz All Periph Clocks ON Seas 7 0 45 mA MHz All Periph Clocks OFF SLEEP MODE CPU PLL Peripherals l O STATIC ATC and WU ON Spits ae TZ MERE H NE J Sit Ee Les d D Ek ome Fo Device Quiescent excep far RTC ON k Hitex UK Ltd Page 65 hitex mum DEVELOPMENT TOOLS Chapter 3 System Peripherals 3 8 9 Interrupt Structure The ARM9 CPU has two external interrupt lines for the fast interrupt request FIQ and general purpose interrupt IRQ request modes As a generalisation in an ARM9 system there should only be one interrupt source which generates an FIQ interrupt so that the processor can enter this mode and start processing the interrupt as fast as possible This means that all the other interrupt sources must be connected to the IRQ interrupt In a simple system they could be connected through a large OR gate This would mean that when an interrupt was asserted the CPU would have to check each peripheral in order to determine the source of the interrupt This could take many cycles Clearly a more sophisticated approach is required In order to handle the external interrupts efficiently an on chip module called the Vector Interrupt Controller VIC has been added The VIC units provide additional hardware support for the on chip peripheral interrupts Without the VICs the interrupt response time would be very slow nim kriet Ieg est mt d groer The VIC is a compon
77. P1 P2 Alt In Alt Out Es O Hitex UK Ltd Page 82 hitex mm Chapter 4 User Peripherals DEWVELUDHP s EM d m Wal D 4 3 1 GPIO Configuration Within the System Control Unit SCU ports 0 to 7 each IO port must be initially configured by three registers in the system control register The GPIO type register allows a user to define the type of output driver connected to each pin within a port By default each pin is driven by a push pull output stage By setting bits within the GPIO Type register each pin can be driven as open collector ALT 1 Qutput GPFIO PIN ALT 2 Qutput ALT 3 Qutput Always Connected to ADC Interrupt etc Each STR9 GPIO pin may be configured as input output or two additional alternate outputs can connect the external pin to on chip peripherals The GPIO input register contains eight bits define whether the external pin is to be used as a GPIO pin or is connected to the input of the on chip peripheral associated with the external pin Similarly the GPIO output register configures the external pin to be an input GPIO output or one of two alternate output functions In addition GPIO port 4 has a dedicated analog mode register that connects the external pins to the ADC input channels When using port 4 in analog mode the SCU_GPIOIN4 and SCU_GPIOUT4 registers should be set to zero Pin UO Alternative Modes Peripheral GPIO Input Timer Timer ETM ADC Function Inputs Outputs
78. R9 has three low power modes in addition to its normal run mode These are Special interrupt run mode Idle mode and sleep mode Interrupt Power Lp Reset The STR9 has four different operating modes Exit from Interrupt Normal mode CPU clock RCLK Interrupt mode CPU clock MCLK Made die mode CPU clock lalted sel sleep eripheral clocks Runni 19 Mod Sleep CPU clock Halted Peripheral clocks Halted Wake Up or Reset Idle Mode Interrupt or Reset 3 8 8 2 Special Interrupt Run Mode The first of these modes is not strictly soeaking a low power mode The special interrupt run mode will switch the CPU clock from RCLK to the master clock MCLK when an interrupt occurs This allows you to configure the PLL to generate MCLK at the maximum 96MHz This can be divided down by the RCLK divider Then during normal operation the CPU can be running at say 48MHz but will immediately start processing instructions at the full 96MHz as soon as an interrupt is generated and return back to the normal run mode frequency at the end of the interrupt The special interrupt mode is enabled by setting the CPU INTR bit in the SCU power management register 15 t 1 3 12 11 10 B ri 6 5 T 3 2 1 D x m zi PAR MODEI2 0 3 aul D x C re Ki re The power control register is used to enable the special interrupt mode It can also be used to enter the the idle and sleep modes The FLASH PD DBG bit can be used
79. SH sector have been reset to OxFF Memory Memi Address Data F FFFFFFFF FFFFFFFF F L LLLLLLDL GGG LI x dguggsuiu Tee AAA Page 186 DEVELOPMENT TOOLE Chapter 5 Tutorial Exercises hitex mm 5 12 Exercise 10 General Purpose IO GPIO On the evaluation board the IO lines from ports 8 amp 9 are connected to a pair of seven segment LED displays This example demonstrates configuring these lines to be outputs and then drives the LEDs in a count from zero to ninety nine 1 Open the Hitop project STR910FExamples GPIO GPIO HTP entering the serial number of your Tantino when asked 2 Examine the code that configures the GPIO registers 3 Run the code to see the displays update Le THLE IIT I Dy vteiugrbt man int main roid ff d Bwclagpe Idmcaals unmigmesd int units unsigned int tens unsigned int Gelay i A Inmnklalbms ITA CPU ff All peripherals ciocks are disabled by default d De weet clear av bris ip SCH PED en his ims the SAAN VIE ebe ZA Koala GRID SL B peripheral BloskB Eo rite LEO array SCH RCGEL ISCU SRCGELI L sOx aDc dnbDD De dD MIOOD f DlIass Fee OFT gcU PRRi UXO DCUQUOD vf Farce reset of BUIOBR FP Setup onmtput pins GPIOBR DbDER DxOOFF s Bite O T ars out buts ERIC DDR es Beano dd Bits Col LEE sufputs Make s re both LED apres dre enable ario DATA Ut ita LED Euahle P ina Only i LETC EN d LED EN GPIOR DATA
80. SR The CPSR contains a number of flags which report and control the operation of the ARM7 CPU 31 30 29 28 27 876543210 MIMI MIMI M NIZICIV FIT NAME deet The Current Program Status Register contains condition code flags which indicate the result of data processing operations and User flags which set the operating mode and enable interrupts The T bit is for reference only The top four bits of the CPSR contain the condition codes which are set by the CPU The condition codes report the result status of a data processing operation From the condition codes you can tell if a data processing instruction generated a negative zero carry or overflow result The fifth bit is the Q flag which is used by the dedicated DSP instructions and is called the saturation flag This flag is set when a DSP instruction causes an overflow or saturation during a data processing instruction the Q flag is also unique among the flags in that it is a sticky bit Once it is set by an instruction result it will stay set until it is cleared by the application code Hitex UK Ltd Page 11 B EVELOPMENT TODI Chapter 1 The ARM9 CPU Core hitex The lowest eight bits in the CPSR contain flags which may be set or cleared by the application code Bits 7 and 8 are the and F bits These bits are used to enable and disable the two interrupt sources which are external to the ARM7 CPU All of the STR9 peripherals are connected to these two interrupt lines as we sh
81. SRAM the Data TCM appears at 0x04000000 with a maximum of 96K and can by accessed with zero wait states by the CPU at the full operating frequency of 96MHz As the DMA controller is located on the AHB potentially it could not access the on chip SRAM as it is located as a D TCM within the ARM9 CPU In order to allow the DMA units access to the SRAM and additional arbiter unit is located between the ARM9 core and the SRAM The arbiter is similar to the APB bridges in that is allows access to the SRAM from the AHB bus but As its name implies it also arbitrates access to the SRAM between the DMA units and the CPU 3 3 1 Write Buffer In order for the CPU to write to the SRAM at zero wait state the D TCM contains a write buffer this a FIFO buffer that is used to decouple the CPU from the write time of the SRAM So when the CPU writes to the D TOM it is made through an internal FIFO Since the data is buffered the SRAM is not immediately updated this means that the D TCM is not fully coherent ie a write and immediate read back would yield the wrong result However the SRAM does appear as non buffered memory see Memory map below so global variables that are accessed by interrupt and non interrupt code should be accessed as non buffered memory Similar write buffers are also used for all of the peripherals on the AHB and APB busses Each peripheral has a buffered and non buffered address range The buffered ranges allow the CPU to make a zero waitstate
82. Setup UART Mode H UARTO gt CR Ox0301 RX TX enabled UARTO enabled H UVARTO LCR x 0650 f Set data length to bits no FIFO No p ff Set Baudrate to 115200 Bpa real baud rate is 115354 6 Bpa ff Integer part R ULRTO gt IBRD 312 f UARTO STBRD BCLK i16 19200 312 5 ff Fractional part 312 5 312 0 5 H UARTO IBRD 34 dd UARTO IBRDB INT 0 5 64 0 5 32 dd Interrupt configuration ZA Receive interrupt is disabled f f Transmit interrupt as disabled ff Error interrupt disabled gd Hitex UK Ltd Page 191 hitex mum Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS 5 17 Exercise 15 I2C Using GPIO The evaluation board is fitted with an DC temperature sensor and 24C04 serial EEPROM As the ETM is supported the normal location of the 12C0 peripheral on port 2 is not available The alternative I2CO pins on ports 0 and 1 are taken up with the Ethernet interface so this example uses bit banging techniques to recreate a simple DC interface This requires the direction of the port 3 5 SDA to be changed rapidly between input mode and output mode As this program uses only the basic GPIO functions i e no peripherals only the GPIO DDR register has to be changed These routines can used as is for most serial EEPROM devices or data generating devices like the L M75 1 The example reads the LM75 temperature sensor and prints the temperature of the evaluation board in degrees C on the LED
83. The RTC has a special tamper interrupt This interrupt is triggered when the state of the tamper pin changes This causes the RTC to halt the clock so the time and date of the tamper event is logged in the RTC registers In addition the SRAM standby voltage is cut off to destroy the contents of the internal SRAM The tamper interrupt is enabled in the control register TIE bit The tamper interrupt can be triggered a high or low logic level defined by the TIS bit The tamper mode is defined by the TM bit The tamper interrupt has two modes it can be triggered Hitex UK Ltd Page 104 Chapter 4 User Peripherals when the input pin is driven high or low as defined by the TIS bit Or it may be triggered when the tamper in voltage is removed Hitex UK Ltd Page 105 Chapter 4 User Peripherals hitex um DEVELOPMENT TOOLE 4 8 Analog to Digital Converter The STR9 has a single Analog to Digital Converter ADC The ADC has a 10 bit resolution with 8 multiplexed input channels appearing on port 4 Each input channel is multiplexed with a GPIO pin on port 4 While the GPIO pads are 5V tolerant the maximum input voltage of any input channel is 3 6V AVREF AVDD G d ADC1 ADC Start Stdby Mode Select The Analog to digital converter is an 8 channel 10 bit resolution converter It supports single channel conversion or a continuous round robin scan conversion of selected channels 4 8 1 Configuration
84. VIC vector slot Wi RKKKKKKKKKKKK KKK k ck k KKK KK k k Ck KKK KKK KKK KKK KK KKK KKK KK KK KKK KKK KKK KKK KKK ck ck KKK KK Interrupt Vectors RKKKKKKKKKKKKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK ck k k KKK KK KKK KKK KKK KKK KKK ck ck KKK KK Reset_Addr word Hard Reset CPU reset vector and entry point Undef Addr Word Undef Handler SWI Addr word SWI Handler PAbt Addr Word PAbt Handler DAbt Addr Word DAbt Handler word 0 Reserved Address IRQ Addr word IRQ Handler FIQ Addr word FIO Handler Does not get used due to LDR PC PC OxFFO above The vector table is located at 0x00000000 and provides a jump to interrupt service routines ISR on each vector If your code is located to run from 0x00000000 then the vector table can be made from a series of branch instructions You must remember to pad the unused interrupt vector with a NOP also note the different type of Assembler instruction on the IRQ interrupt vector above This will be discussed in Chapter 3 when we look at the interrupt structure in more detail Using the Branch instruction means that the entry point to our application software and the interrupt routines must be located within the first 32Mb on the STR9 memory map since this is the address range of the branch instruction A more generic way to handle the vector table is to use the LDR instruction to load a 32 bit constant into the PC This method uses more memory but allows you to lo
85. Xy 16x16 64 64 Signed MAC long SMULXxy 16x16 32 Signed multiply SMULWy l0x357 32 Signed multiply long The 16x16 multiply instructions operate on the upper and lower halves of a 32 bit wide register So if you arrange your 16 bit integers in a joining half words a single load can be used to move both operands into the register file The next group of DSP instructions implement saturated addition and subtraction instructions 1 13 THUMB Instruction Set Although the ARMO is a 32 bit processor it has a second 16 bit instruction set called THUMB The THUMB instruction set is really a compressed form of the ARM instruction set The THUMB instruction set is essential for archiving the necessary code density to make small single chip ARM7 micros usable 16 pi Thumb ende This allows instructions to be stored in a 16 bit format expanded into ARM instructions and then executed Although the THUMB instructions will result in lower code performance compared to ARM instructions they will achieve a much higher code density So in order to build a reasonably sized application that will fit on a small single chip microcontroller it is vital to compile your code as a mixture of ARM and THUMB functions This process is called interworking and is easily supported on all ARM compilers By compiling code in the THUMB instruction set you can get a space saving of 3096 while the same code compiled as ARM code will run 4096 faster The THUMB instr
86. a moment The DLC field is the data length code and contains an integer between 0 and 8 that indicates the number of data bytes being sent in this message packet So although you can send a maximum of 8 bytes in the message payload it is possible to truncate the message packet in order to save bandwidth on the CAN bus After the 8 bytes of data there is a 15 bit cyclic redundancy check This provides error detection and correction from the start of frame up to the beginning of the CRC field After the CRC there is an acknowledge slot The transmitting node expects the receiving nodes to assert an acknowledge in this slot within the transmitting CAN packet In practice the transmitter sends a recessive bit and any node that has received the CAN message up to this point will assert a dominant bit on the bus thus generating the acknowledge This means that the transmitter will be happy if just one node acknowledges its message or if 100 nodes generate the acknowledge So when developing your application layer care must be taken to treat the acknowledge as a weak acknowledge rather than confirmation that the message has reached all its destination nodes After the acknowledge slot there is an end of frame message delimiter It is also possible to operate the CAN bus in a master slave mode A CAN node may make a remote request onto the network by sending a message packet which contains no data but has the RTR bit set The remote frame is requesting a message pack
87. a program jump anywhere within the processor address space If the target address is beyond the range of a branch instruction a stored constant can be loaded into the PC 1 7 2 1 Copying Multiple Registers In addition to load and storing single register values the ARM has instructions to load and store multiple registers So with a single instruction the whole register bank or a selected subset can be copied to memory and restored with a second instruction The load and store multiple instructions allow you to save or restore the entire register file or SIN any subset of registers in the one instruction LOM Mie 16 Hitex UK Ltd Page 19 Chapter 1 The ARM9 CPU Core hitex mms DEVELOPMENT TOOLS 1 8 Swap Instruction The ARM instruction set also provides support for real time semaphores with a swap instruction The swap instruction exchanges a word between registers and memory as one atomic instruction This prevents crucial data exchanges from being interrupted by an exception This instruction is not reachable from the C language and is supported by intrinsic functions within the compiler library The swap instruction allows you to exchange the contents of two registers This takes two cycles but is treated as a single atomic instruction so the exchange cannot be corrupted by an interrupt 1 9 Modifying The Status Registers As noted in the ARM9 architecture section the CPSR and the SPSR are CPU registers bu
88. a single block of memory or a peripheral device Similarly a contiguous block of data can be scattered to several different locations by a programmed set of DMA transfers Hitex UK Ltd Page 74 hitex mum DEVELOPMENT TOOLE Chapter 3 System Peripherals The DMA controller contains a global set of configuration and status registers and a set of five registers for each DMA unit Although there are some 48 registers in the DMA unit it can be subdivided into 14 DMA configuration and status flags followed buy five control registers for each DMA unit The general configuration and status registers are principally concerned with enabling the DMA controller and controlling the individual DMA units interrupts The DMA controller is enabled by setting the EN bit in the configuration register Each DMA unit has two interrupt lines a terminal count interrupt which is set at the end of a transfer and an error interrupt which is set if the DMA unit encounters a bus error Each interrupt source is enabled in the channel configuration register within each DMA unit Each interrupt source has an interrupt status register and a raw interrupt status register The raw interrupt status register shows the condition of all interrupt flags regardless of whether they are enabled or not while the interrupt status register only shows the status of DMA interrupts that have been enabled In the case of a DMA transfer were the DMA unit is the flow controller a burst or
89. age 194 hitex mm B EVELOPMENT TOOLE Chapter 5 Tutorial Exercises 4 Next load the full CAN example and examine how it uses the IF message registers to access the CAN message RAM Arb Registers l and Z CAN IFZ Al zE ID 68 16 nua ID 15 0 Oo801 MsqVal Message is Valid Yes i xcd Identifier Standard ll Bit Dir Message Direction Beceive Message Control Register CAN IFZMCBR MewDbar New Data stored res Msglest Message lost No Int End Interrupt is Pending Ho e Mask Use acceptance Mask Ho Txlnt Transmit Int Disabled e Rxlnt Beceive Int Disabled e il EmtEn Remote Enable Ho TxBqst Transmission Requested No EoB Single Obj in Buffer No e DLC Objekt Data Length Code Data AYE Registers CAN IF DA EIR Data Al FFSS Data Az FFFF Data Bl FFFF Data Bz FFFF O Hitex UK Ltd Page 195 hitex mm Chapter 5 Tutorial Exercises DEVELOPMEN 1 Led Bel H 5 20 Exercise 18 Motor Drive Peripheral This is an extract from a real open loop three phase induction motor drive that has been ported to the STR912 It uses a carrier frequency of 12kHz with centre aligned PWM on three channels The complementary outputs are generated using the deadtime generator The sine modulation contains 1696 third harmonic to yield space vector modulation There are 4 voltage frequency characteristics for different types of loads fans pumps etc The si
90. all see later You should be careful when programming these two bits because in order to disable either interrupt source the bit must be set to 1 not 0 as you might expect Bit 5 is the THUMB bit The ARM9 CPU is capable of executing two instruction sets the ARM instruction set which is 32 bits wide and the THUMB instruction set which is 16 bits wide Consequently the T bit reports which instruction set is being executed Your code should not try to set or clear this bit to switch between instruction sets We will see the correct entry mechanism a bit later The last five bits are the mode bits The ARMO has seven different operating modes Your application code will normally run in the user mode with access to the register bank RO R15 and the CPSR as already discussed However in response to an exception such as an interrupt memory error or software interrupt instruction the processor will change modes When this happens the registers RO R12 and R15 remain the same but R13 LR and R14 SP are replaced by a new pair of registers unique to that mode This means that each mode has its own stack and link register In addition the fast interrupt mode FIQ has duplicate registers for R7 R12 This means that you can make a fast entry into an FIQ interrupt without the need to preserve registers onto the stack Each of the modes except user mode has an additional register called the saved program status register If your app
91. allocated as one of the three remaining pipe types 4 13 5 1 4 1 Interrupt Pipe The first of the user pipe types is an interrupt pipe The key thing about an interrupt pipe is that it isn t one Since only the PC can initiate a data transfer no network device can asynchronously communicate to the PC With an interrupt pipe the developer can define how often a data transfer is requested between the PC and the remote device This can be between 1msec and 255msec So really in USB an interrupt pipe has a defined polling rate In the case of a mouse we can guarantee a data transfer every 10 msec for example Defining the polling rate does not guarantee that data will be transferred every 10 msec but rather that the transaction will occur somewhere within the tenth frame So a certain amount of timing jitter is inherent in a USB transaction 4 13 5 1 4 2 Isochronous Pipe The second type of user pipe is called an isochronous pipe Isochronous pipes are used for transferring real time data such as audio data Isochronous pipes have no error detection and an isochronous pipe sends a new packet of data every frame regardless of the success of the last packet So in an audio application a lost or corrupt packet will sound like noise on the line until the next successful packet arrives An important feature of isochronous data is that it must be transferred at a constant rate Like an interrupt pipe an isochronous pipe is also subject to the kind of jitter des
92. ance all the dividers should be set to one so that the CPU AHB and APB busses are all running at the same speed However if you have an application where power consumption is critical you have a great deal of leeway in deciding the operating frequency and hence the power consumption of different areas of the STR9 In addition these different clock can be controlled dynamically to meet the changing processing power and power consumption needs of your application 3 8 6 PLL Once out of reset the CPU is running at the fundamental frequency of the external CPU oscillator The on board PLL is used to multiply this frequency up to a maximum of 96MHz The PLL is controlled with a single register is the system control unit The PLL configuration register contains three fields which must be programmed with the PLL timing characteristics Once these values have been placed in the PLL it can be enabled by setting the PLLEN bit The PLL configuration PLL PONTI register in the system control block enables the PLL and defines its output frequency Fu urere mu Mat TS Hitex UK Ltd Page 62 hitex mm Chapter 3 System Peripherals DEVELOPMENT TOOLS The three timing fields are PDIV NDIV and MDIV and the PLL output frequency is defined by the equation Fpll 2xNxFosc Mx2 p The reset value of the PLL config register configures these fields to generate a 48 MHz output once the PLL is enabled In order to increase this to 96 MHz si
93. and so on Speed feedback is possible via the Tacho generator interface so that sine amplitude can be based on the actual speed of the rotor under low speed heavy load conditions Adding current sensors to the bridges and using the ADC to detect over current is also possible However a discussion of these is outside the scope of this piece You can find an example of a complete STR912 based AC induction motor controller at http www hitex co uk str9 that can be used as a plug in module for your own projects 4 6 4 Tacho Generator Speed Feedback The Tacho input allows the easy measurement of rotor speed from an external tacho generator Here the motor speed is represented by pulsetrain whose frequency is proportional to the motor speed The Tacho input has a dedicated capture register MC TCPT that captures the free running 16 bit Tacho counter On capture the counter is reset to zero and the value held in the Tacho Capture register represents the time between incoming pulses and from this the rotor speed can be calculated A 12 bit prescaler allows the PCLK to be divided down so that the count between tacho edges is in a sensible 16 bit range over the normal motor operating speed range To cope with very low rotor speeds fault conditions and motor stop a Tacho Compare register MC TCMP is provided that allows an 8 bit compare against the MSB of the 16 bit Tacho counter This allows very large Tacho counter values to be detected that would indicate
94. ange the logic on the compare pin Once the timer is initialised and a compare value has been loaded into the output compare A register and Output compare 2 registers the compare interrupts may be enabled by setting the OC1IE and OC2IE bits in control register 2 Timer Counter Register Match Software Maskable Interrupt Request Pulse generation Output Compare Register o T Each timer has two compare registers that may be used for custom pulse generation Now whenever the free running timer matches the contents of either compare register an interrupt will be generated If you want to generate a waveform in addition to switching the GPIO pins to their secondary function you must enable the output compare pins by setting the OC1E and OC2E bits in control register 1 Now whenever a compare event is made the contents of the OLVL1 and OLVL2 bits will be applied to the output pins TIM1_OCAR 0x0000FF00 Set the compare count TIMI CR2 0x000040FF enable the compare 1 interrupt and set the prescaler TIM1 CR1 0x0008100 Timer enable set the output level on OCMP1 pin 4 5 4 PWM Output Like the PWM input mode the STRS9 timers have a special mode to allow easy generation of PWM output waveforms By setting the PWM bit in control register 1 both of the compare registers are used to control the output compare 1 pin Counter FFFC X FFED gt OCAR 0x2 EDO OCMPA ee OLVLB Compare B Compare A Compare B OLVLA 0 SSeS OLVLB
95. anying this book Hitex UK Ltd Page 198 Chapter 6 Bibliography Hitex UK Ltd Page 199 Chapter 6 Bibliography 6 Bibliography 6 1 Publications ARM966E datasheet ARM system on chip architecture Architecture reference manual ARM system developers guide GCC the complete reference STR9 User Manual STR9 USB Library manual Embedded Networking with CAN and CAN open USB Complete Universal Serial Bus System Architecture 6 2 Web URL www arm com www st com www hitex co uk www keil co uk hitex mm n WW Ek KI TR si d m a D ARM Ltd Steve Furber David Seal Andrew N Sloss Domonic Symes Chris Wright Arthur Griffith ST Microelectronics ST Microelectronics Olaf Pfeiffer Christian Keydel Andrew Ayre Jan Axelson ISBN 096508195 8 Don Anderson ISBN 0 201 46137 4 www usb org USB implementers forum www lvr com Website for USB complete with HID source code www thesycon de commercial device driver for USB www hitex co uk USB and STR tools www hitex co uk STR9 Updates to this book and the example programs www keil com STR9 tools Hitex UK Ltd Page 200 This book is intended as a hands on guide for anyone planning to use the STR9 family of microcontrollers in a new design It is laid out both as a reference book and as a tutorial It is assumed that you have some experience in programming microcontrollers for embedded systems and are familiar with the C language The bulk
96. ar on the network as address zero this address must be kept free So after the reset command the PC will assign the new device a unique network address for all further communication Request the device descriptors Once the new address has been assigned the PC will request the full device descriptor followed by the configuration interface and endpoint descriptors Once the PC has finished the enumeration process it will use the vendor and product IDs to assign a matching device driver It can use further control transfers to select which configuration and interface it wants to use to communicate with the new device Then the device is ready for use The USB protocol supports eleven different control commands as summarised below If a device does not support a particular command it should return a STALL handshake to cancel the command and the PC will move on to its next control transfer Operation Get Status Clear Feature Set Feature Set Address Get Descriptor Set Descriptor Get Configuration Set Configuration Get Interface Set Interface Synch Frame Hitex UK Ltd Purpose Requests the status of an interface or endpoint Disables a feature on an interface or endpoint Enables a feature on an interface or endpoint Sets the network address of a new device Requests a specific descriptor Adds or updates a specific device descriptor Requests the current device configuration Sets the desired device configuration Requests the cu
97. ari 2 MD OS mapes irane mcpu arm cdmi w mMehume EE EE EE Weis c WSIOIDUIS CIS ger SO arm hitex elf as exe m armv4t gdwarf2 mthumb interwork o ACD Gees vsrecsdsiebIo ol om Ee 2 rebo 9d 2 s eue draco cde ele cies he Wolo eens Vit ies cr ACER CRC ECO e nostartiiles Map r s e Moon ses speres arm hitex elf ld mode armelf Dioecesi ie objects main o Objecto vat Sg IUe cO ongeccss LED controlo C Programei les Hictcex CoumoolPackadgerrm io dec arm hites EE Eeer EE Progran Piles Hitex GnuloolrPackageArm lib occam hitex EE E EE eer Ee Hitex UK Ltd Page 166 Chapter 5 Tutorial Exercises hitex ENELOOP EM DO LE After the build has finished the new code will be downloaded into the evaluation board Once this has finished right click again in the source window and switch back into debug mode Now you are ready to use HiTOP in its debugging mode 5 3 1 2 Run Control Once the project is loaded the STR9 is reset and the program counter is forced to the reset vector From here it is possible to execute code at full speed or single step line by line The debug toolbar has specific buttons to control execution of code on the ARM9 CPU um Che LI nial Sep mer Goto aren how H b 3 f u 1 di PPa We tr Download Halt Step oto Step out Set breakpoint Target rezsi These functions can also be accessed via the debug menu which also displays the keyboard shortcuts It is worth learning the
98. arrays Please note that there is a self heating effect in the sensor which makes it read a few degrees above ambient 2 It also writes test values to the 24704 EEPROM and then reads them back E LAC DRIVERS Tater mun Li C eis Prepare IZC bus DCH DCL Low F eSCL ic ms talt Settling Delay Maire Far asetrling time EDATE bit tempi Mask all But MESSE Bree chen E es waitilBsttling Delay d Wait for settling time Creste eleeb Bit SCL PEL High d Rising clock edge eo waltiBetrling Delay j Waic for a bis EXT BCL Low Put etock low again val ax T RIFE ber put Feqgiseea end ir ow amd scapturs ACK EL BCL Lew Sp waiticGaketling D lay PF Matt For zatbling tima HbDACHIE BRA High FF Get ES ao that pin pulls tigri se wa itiBettling Delay Wait for settling time BC BCLh High ee waitiDErtling Delay Wait for settiing time LDhagunA for JON being returned Device drives data pin low Bet JNA Ax Input Ehin AH j prr a Ber JDA As Output XDAOCuUt XDA High fet FO ee thet pin pulls high crc wazkiBettling Delay Wait for sethiing time SCH ACL Low Fut clock Job sgain Hitex UK Ltd Page 192 hitex mm mL omg DEWVELOHP s EM EN AO c Chapter 5 Tutorial Exercises 5 18 Exercise 16 12C Peripheral This example connects the two I2C peripherals together and configures them as master and slave The master is then used to initiate the transfer of data between the
99. ated with each character are also stored in the FIFO and can be alongside the data The STR9 UARTS also have flow control support as part of the UART hardware which is not normally found on small microcontrollers In addition the TX and RX pins each UART has a Clear to send CTS and ready to send RTS pin The CTR RTS functions must be enables by setting the CTSEN and RTSEN bits in the Control register 15 14 14 12 11 10 zi H T B 5 d d 2d 1 D When enabled the RTS pin is an output and the CTS is an input When communicating with another UART RTS CTS pins should be connected as shown below UART 1 Rx FIFO arrete warTrts RXFIFO and and flow control flow control Tx FIFO nUARTCTS Tx FIFO and and flow control flow control Each UART supports hardware flow control with dedicated RTC and CTS pins Hitex UK Ltd Page 115 hitex mum Chapter 4 User Peripherals e z DEVELOPMENT TOOLS When flow control is enabled the RTS pin will be held high until the receive FIFO trigger level is reached When the FIFO is full the RTS pin will go low The transmitting UART will send characters while there is a high level on the CTS pin When the RTS line places a low level on the CTS pin the transmitting UART is halted until the receiving UART reads its buffer and the RTS signal is again asserted This is controlled by the UART hardware 15 d 13 Le 11 10 E B rj 6 5 2 3 2 1 T The DAM control register can enable each UART to be a s
100. ation software it is running 4 13 5 1 11 Interface Descriptor The interface descriptor describes a collection of endpoints This interface will support a group of pipes which are suitable for a particular task Each configuration can have multiple interfaces and these interfaces may be active at the same time or can be dynamically selected by the PC O Hitex UK Ltd Page 148 hitex mmm Chapter 4 User Peripherals DEVELOPMENT TOOLS PE RER buen End Poets mind semen iris pacer EL a Cum code o5 Weed o 7 Subciasa code 7 baasem co t CCE 8 eae t index af siring descriptor tor the interface 4 13 5 1 12 Endpoint Descriptor The endpoint descriptor transfers the configuration details of each endpoint supported in a given interface The descriptor carries details of the transfer type supported the maximum packet size the endpoint number and the polling rate if it is an interrupt pipe This is not an exhaustive list of all the possible descriptors that can be requested by the PC but as a minimum the USB device must provide the PC with device configuration interface and endpoint descriptors 4 13 5 1 13 Enumeration The enumeration process takes place over the control channel attached to endpoint zero when the device is first attached The PC will send a series control transfers that request the USB device to transfer its descriptors to the PC Interpretation A typical contr
101. ator State Workspace v QutEput Edit toolbar Se Debug i IDE uency bits v v vi he T20 mod Screen Layout v Execute Script le the ITE v hit rata 3 Status Bar The next sections are a tutorial on how to use the basic features of HITOP to debug and edit your project Hitex UK Ltd Page 165 Chapter 5 Tutorial Exercises 5 3 1 1 Editing Your Project To edit the code in your project do the following 1 Select the main tab in the source window to display the code in this module 2 Nextright click and select Switch to Edit Mode 3 We can change the speed at which the LED arrays count is set by the loop count define Display Delay 10000 atthe beginning of the MAIN C file to match the code shown below define Display Delay 5000 4 To rebuild the code select project build on the main toolbar Project Debug RTOS Sy Open Recent projects d Save Save as Close Settings Compile Ctri F7 Rebuild All Reporting of the build progress is shown in the output build window If there are errors when you build the project you can click on the error report and the offending line of code will be displayed in the source window arm nitex elf gcc ceze C gdwarf 2 MD Os mapes frane mopu arm cdmi w mbi EOC WO r EE Ee LC ohe er o Eea e a Ee e arm hNhitex CRE CCC re Core re 2 MD Os mapes irane mcpu arm cdmi w mthumb IAE SOI E EE eas ON Ee EE vine a ee EE EE ra e arm Mitos elf goc ce C gw
102. background code at the point at which it was interrupted However before you exit the ISR code you must make sure that any interrupt status flags in the peripheral have been cleared If this is not done you will get continuous interrupts until the flag is cleared Again be careful as to clear the flag you will have to write a logic 1 not a logic O At the end of an interrupt the interrupt status flag continuous interrupts Hitex UK Ltd Page 67 hitex mum Chapter 3 System Peripherals zy DEVELOPMENT TOOLS 3 8 12 Vectored IRQ If we have one interrupt source defined as an FIQ interrupt all the remaining interrupt sources must be connected to the remaining IRQ line To ensure efficient and timely processing of these interrupts the VIC provides a programmable hardware lookup table which delivers the address of the C function to run for a given interrupt source The VIC contains 16 slots for vectored addressing Each slot contains a vector address register and a vector control register Vector Address I CL m SE HECNIOEI UL E SEN Di uf Vector Addeoss mi Vector Address 0 For a Vectored IRQ the VIC provides a hardware Y Vector Address 15 lookup table for the address of each ISR The interrupt priority of each peripheral may also be Vector Control 0 controlled Vector Control 15 The Vector Control Register contains two fields a channel field and an enable bit By programming the c
103. bank 1 can be enabled in 8 k pages Care must be taken not to overlap the two FLASH banks as the FMI registers do not provide any protection against an incorrect configuration 16 a D The boot and non boot bank size registers allow you to define the FLASH bank size in block of 32k and 8K The default configuration of the STR9 is to have Bank 0 as the boot bank and bank 1 as the non boot bank This can be reversed by programming the FLASH configuration register to make bank1 the boot bank However the configuration register cannot be accessed by firmware and can only be programmed with a JTAG tool If you plan to have a block of permanent code such as a BIOS or bootloader located at the start of FLASH memory it can be useful to make bank 1 the bootbank in order to locate this code in the first 8K sector which can then be permanently protected rather than having to use a much larger 64k sector in bank O Hitex UK Ltd Page 51 hitex mm Chapter 3 System Peripherals DEWVELOHP s EM d m Wal D 3 4 4 Bootloaders The STR9 has two FLASH banks that can be configured by the user to have a variety of sizes and base addresses In addition the boot bank i e which bank is executed upon exiting reset can be set by the user This allows the user to have an unusually large degree of control over how the STR9 behaves at start up This includes the ability to write completely custom bootstrap loaders Traditionally the user has to make do wi
104. be set to zero As the transfer progresses the contents of this field are decremented however if you need to read this field you should disable the DMA unit in order to get a meaningful value The source and destination width fields allow you to define transfer word size to be fetched into and drained out of the DMA unit the DMA controller allows you to define different source and destination widths and each DMA unit will pack and unpack the data as required Depending on your requirements the source and destination address may be incremented after each transfer by setting the DI and SI bits This allows you to block transfer data from one continuous address range to another or you can copy a block of data to a single non incremented memory location such as a peripheral register The control register also allows you to define several protection options The protO bit can be set to prevent the DMA registers from being accessed by code running in the ARM9 user mode for the duration of the transfer The PROT1 register allows you to define if the DMA destination addresses are buffered address ranges which can be accessed in a single cycle This allows the DMA unit to transfer the data at its fastest rate but may introduce data coherency problems as the buffered data has to be written to the real SRAM The terminal count interrupt enable will generate an interrupt at the end of the DMA transfer which tells the ARM9 CPU that the DMA transfer has finished and the DMA
105. being synchronised by the start of frame bit once the bus becomes idle When this happens the CAN bus arbitration will take place to determine which message wins the bus and is transmitted Node X Node A A NodeB A zm COCO Node C A AO CAN arbitration Message AAA Arbitration phase of message frame rbitrati rarit that l ion n QUIL Remainder of message frame t e dis a eon Ze SE sa e A Schedules Message Tx will win the bus and be sent Start Bit without any delay Stalled Node A es ES a f 1L fF messages will then be sent ll in order of priority lowest INED cA EI value identifier first Node C D Dose Node B loses Node C loses CAN arbitrates its messages by a method called non destructive bit wise arbitration In the diagram above three messages are pending transmission Once the bus is idle and they are synchronised by the start bit they will start to write their identifiers onto the bus For the first two bits all three messages write the same logic and hence read back the same logic so each node continues transmission However on the third bit node A and C write dominant bits and node B writes recessive At this point node B wrote recessive but read back dominant In this case it will back off the bus and start listening Node A and C will continue transmission until node C write recessive and node A writes dominant Now node C stops transmission and starts listening Now node A has won the bus and will send
106. ble you want to break on either in the source window or the project browser then drag and drop it to the breakpoint window By default the break condition is on a write to the variable If you select the local options this can be changed to read or read write The change option gives you full access to programming the breakpoint condition There are some more advanced breakpoint settings that allow the setting of breakpoints Select Al on the fly and conditional breakpoints and these are discussed in the HITOP project settings section at the end of this first tutorial ME B rte You may also position the program counter on any line of code Locate the line of code Read Write were you want to place the program counter with the mouse pointer and left click to locate the cursor Next right click and select set new program counter This will force Disable the Program Counter to this location No other registers are affected so you must use SE Del this option with care Change while 1 d f BEGIN USER CODE MAIN LOOP IO SETPORT IO ON for i 0 il BLINEY DELAY i IO CLRPOR for az Switch to Edit Made CErl T Set Breakpoint AT END USER CODE Run Eo Cursor Line Set Mew Program Counter Show DC Location At BEGIN USER CODE Quick Watch Add watch END USER CODE The Callstack window displays the calling hierarchy of the functions pushed onto the stack If you double click o
107. both interrupt channels so you must provide two interrupt service routines I2CO OAR2 0x00000080 Set frequency bits for 50K bit rate I2C0 CR 0x00000020 enable the I2C module L2UC0 CR 0x00000020 write twice to enable I2C0 CR 0x00000001 enable the ITE interrupt I2CD CR 0x00000004 enable Ack I2CO0 CCR 0x0000002C set the bit rate at 50K I200 ECCR 0x00000003 set the upper clock register bits I2CO OARI 0x00000002 Set own address 4 12 1 12C Addressing The default addressing mode in the DC module is a 7 bit address This address must be placed in the highest seven bits of the own address 1 Register bit zero is not used When a master addresses a node it will place a matching address in the data register and bit zero is used to signify a read or write transaction If bit zero is set to 1 itis a read and zero is a write The I2C peripherals are also capable of using a 10 bit addressing mode In this case the address byte sent after the start bit must start with the pattern 11110 followed by the first two bits of the address The least significant bit is again used to demote a read or write transaction Transmission of the 11110 pattern will cause the ADD10 flag to be set as a request to send a second address byte containing the remaining eight bits of the address Once the address has been sent the data transmission carries on as in the 7 bit mode Hitex UK Ltd Page 120 Chapter 4 U
108. cate your code anywhere in the 4Gb address range of the ARMO O Hitex UK Ltd Page 29 Chapter 2 Software Development Vectors LDR LDR LDR LDR LDR NOP LDR LDR LDR Reset_Addr DD Undef_Addr DD SWI_Addr DD PAbt_Addr DD DAbt Addr DD DD IRQ Addr DD FIQ Addr DD PC Reset Addr PC Undef Addr PC SWI Addr PC PAbt Addr PC DAbt Addr Reserved Vector PC IRQ Addr PC PC 0x0808 PC FIQ Addr Reset Handler Undef Handler SWI Handler PAbt Handler DAbt Handler 0 Reserved Address IRO Handler FIQ Handler The vector table and the constants table take up the first 64 bytes of memory On the STR9 the memory at 0x00000000 may be mapped from a number of different sources either on chip FLASH RAM or external FLASH memory This is discussed more fully later on Whichever method you use you are responsible for managing the vector table in the startup code as it is not done automatically by the compiler The startup code is also responsible for configuring the stack pointers for each of the operating modes DVC Stack 3 oO Sack FIG Stack ABT Stack UNDEF Stack 3 USA Stack Y Top of RAM Y 0x2 000FFFF The six on chip stack pointers R13 are initialised at the top of on chip memory Care must be taken to allocate enough memory for the maximum size of each stack A lt Since each operating mode has a unique R13 there are eff
109. ces the power consumed during the transmission process e 12 A 10 g B d 6 5 E 3 d UART WAS 15 14 13 12 11 10 9 h 7T 8 5 4 3 2 1 o FA ny PA ray n nds FAI ne F e n The IrDA support for each UART is enabled in the system control unit UART IRDA and SIREN bit in the UART control register The SIRLP bit can be used to limit the power used in IrDA transmission IrDA support for each UART is enabled in the system configuration register O in the system control unit The IrDA active pulse width can be further controlled by the SIR EN bit in the UART control register When the UART is in IrDA mode and the SIR EN bit is clear the active portion of each bit period is 3 16 of the UART bit period If the SIRLP bit is set the uart baud rate is ignored and a the contents of the IrDA low power counter divisor register are used to define the IrDA baud rate The IrDA bit rate is defined by the following formulae Fida Fbcik 3 X ILPDVSR ILPDVSR Fera Fir PBaudte Hitex UK Ltd Page 117 hitex mum DEWELOPER GOLES Chapter 4 User Peripherals 4 12 12C Module The STR9 has two DC communications peripherals Like the UARTs and the SPI peripherals the two DC modules are both fully independent modules and are code compatible The I2C IO can be routed to a number of different GPIO ports as shown in the table GPIO Mode Alternate In 1 Alternate Out 2 Alternate In 1 Alternate Out 3 Pin 0 l2C0 CLKIN 12C0 CLKOUT Pin 1 CO D
110. cess the message buffers Messe intartace The CAN protocol registers are principally concerned with configuring the CAN controller and with error containment Hitex UK Ltd Page 128 hitex mum DEVELOPMENT TOOLE Chapter 4 User Peripherals alatus The CAN protocol registers configure the CAN bus parameters and manage the interrupt handling and Error Counter error containment Ba Timing Lier kiani GAP Exseriinn First we will look at the initialising the CAN controller then later we will look at the error registers 4 13 2 1 Bit Timing Unlike many other serial protocols the CAN bit rate is not just defined by a baud rate prescaler The CAN peripheral contains a Baud rate prescaler but it is used to generate a time quanta i e a time slice A number of these time quanta are added together to get the overall bit timing Unlike other serial protocols the CAN bit period is constructed as a number oi segments that allow you to M tune the CAN data Bit Time transmission to the channel being used A Tsegl Sync sample Seg Point The Bit period is split into three segments First is the sync segment which is fixed at one time quanta long The next two segments are Tseg1 and Tseg2 and the user defines the number of time quanta in these regions The minimum number of time quanta in a bit period is 8 and the maximum is 25 The receiving sample point is at the end of Tseg1 so changing the ratio of
111. ck to user mode a modified version of the move instruction is used and this is called MOVS more about this later Hence for a software interrupt the return instruction is MOVS RLS r Move Link register into the PC and switch modes However in the case of the FIQ and IRQ instructions when an exception occurs the current instruction being executed is discarded and the exception is entered When the code returns from the exception the link register contains the address of the discarded instruction plus four In order to resume processing at the correct point we need to roll back the value in the Link register by four In this case we use the subtract instruction to deduct four from the link register and store the results in the PC As with the move instruction there is a form of the subtract instruction which will also restore the operating mode For an IRQ FIQ or Prog Abort the return instruction is SUBS R15 R14 4 In the case of a data abort instruction the exception will occur one instruction after execution of the instruction which caused the exception In this case we will ideally enter the data abort ISR sort out the problem with the memory and return to reprocess the instruction that caused the exception This means we have to roll back the PC by two instructions i e the discarded instruction and the instruction that caused the exception In other words subtract eight from the link register and store the result in the PC For a da
112. configure the UART communication parameters 15 14 13 12 11 10 g B d D 5 3 Fa 1 A The line control register defines the serial data packet format Within the line control register the UART it is possible to configure the number of data bits within each word the number of stop bits and to enable the a parity check and define the parity check as odd or even The line control register also allows you to enable the internal transmit and receive FIFOs Each UART has a 16 word deep transmit FIFO and receive FIFO The transmit FIFO has a word width of 8 bits to support the maximum data width that can be sent in each serial character the receive FIFO is 12 bits wide this allows the FIFO to carry eight bits of data and four status flags for each character received The receive and transmit FIFOs are accessed by reading and writing to the UART data register The status of the FIFOs can be monitored by reading the UART flag register Data can be transmitted by writing each character to the data register were it will be queued in the FIFO until it enters the transmit shift register The flag register contains status bits that allow control of the receive and transmit FIFO Uart 0 has additional fields for the modem status bits The UART flag register contains transmit FIFO full and empty flags which can be used to manage the transmission process Received data will be queued in the receive FIFO The flag register contains receive empty and rece
113. controller generating an acknowledge to any CAN message It is also possible to test the integrity of the physical layer since the TX pin may be controlled by software and the bus level on the RX pin may be read directly The TXO and TX1 bits may write the bus level to dominant or recessive and this can be read back via the RX bit The test register also allows you to configure the CAN controller into silent mode In this mode the CAN controller is not able to transmit any messages and will not generate any acknowledges or error frames It is able to receive messages but does not take any active part on the bus You can also use the combination of the loopback and silent modes to do a self test on a live network without any danger of upsetting the operation of that network 4 13 4 6 Deterministic CAN Protocols Although it is possible to guarantee delivery of a CAN message within a certain maximum delay it is difficult to schedule CAN messages to arrive at regular intervals Most systems that need exchange data on a regular basis rely on having enough bandwidth available to allow any message arbitration to be resolved and still have enough time for a delayed message to reach its target within its time budget In an effort to make CAN more deterministic an extension to the standard CAN protocol called Time Triggered CAN TTCAN uses a time division multiplexing approach to ensure all CAN messages are schedulable In the TTCAN protocol a start of frame
114. controller has separate transmit and receive paths to and from the physical layer device So as the node is writing onto the bus it is also listening back at the same time This is the basis of the message arbitration and for some of the error detection The physical layer is implemented with a dedicated 8 pin line driver 5V TEST CAN TX L Txo Ram S EXI CANI ew SPDT LT 8 ASC CANH O a cm The CAN physical layer is implemented 1 Kg in an external 8 pin package available from ST and second sourced by a number of other manufacturers sn z AE ink M SW SPST The two logic levels are written onto the twisted pair as follows a logic one is represented by bus idle with both wires held half way between 0 and Vcc A logic Zero is represented by both wires being differentially driven V Recessive Dominant Recessive CAN Physical layer signals On the CAN bus logic zero is represented by a maximum voltage difference called dominant logic 1 by bus idle called recessive A dominant bit will overwrite a recessive bit O Hitex UK Ltd Page 125 Chapter 4 User Peripherals In CAN speak a logic one is called a recessive bit and a logic zero is called dominant bit In all cases a dominant bit will overwrite a recessive bit So if ten nodes write recessive and one writes dominant then each node will read back a dominant bit The CAN bus can achieve bit rates up to a maximum of
115. cribed above So in the case of isochronous data no interrupt is generated when the data arrives in the endpoint buffer Instead the interrupt is raised on the start of frame token This guarantees a regular 1 msec interrupt on the isochronous endpoint allowing data to be read at a regular rate 4 13 5 1 4 3 Bulk Pipe The bulk pipe is for all data that is not control interrupt or isochronous Data is transferred in the same manner and packet sizes as with an interrupt pipe but bulk pipes have no defined polling rate A bulk pipe will take up any bandwidth that is left over after the other pipes have finished their transfers If the bus is very busy then a bulk transfer may be delayed Conversely if the bus is idle then multiple bulk transfers can take place in a single 1 msec frame where interrupt and isochronous are limited to a maximum of one packet per frame An example of bulk transfers would be sending data to a printer As long as the data is printed in a reasonable time frame the exact transfer rate is not important Hitex UK Ltd Page 144 hitex Chapter 4 User Peripherals WELIHP E EF M 4 13 5 1 5 Bandwidth Allocation So in terms of bandwidth allocation the control pipes are allocated 10 Interrupt Isochronous is given 90 and bulk makes do with any idle periods on the network These are maximum allocations so on most networks there will be plenty of unused bandwidth The operating system on the PC is responsible for ban
116. crocontrollers in a new design It is laid out both as a reference book and as a tutorial It is assumed that you have some experience in programming microcontrollers for embedded systems and are familiar with the C language The bulk of technical information is spread over the first four chapters which should be read in order if you are completely new to the STR9 and the ARM9 CPU The first chapter gives an introduction to the major features of the ARM9 CPU Reading this chapter will give you enough understanding to be able to program any ARMO device If you want to develop your knowledge further there are a number of excellent books which describe this architecture and some of these are listed in the bibliography Chapter Two is a description of how to write C programs to run on an ARMS9 processor and as such describes specific extensions to the ISO C standard which are necessary for embedded programming Having read the first two chapters you should understand the processor and its development tools Chapter Three then introduces the STR9 system peripherals This chapter describes the system architecture of the STR9 family and how to set the chip up for its best performance In Chapter Four we look at the on chip user peripherals and how to configure them for our application code Throughout these chapters various exercises are listed Each of these exercises are described in detail in Chapter Five the Tutorial section The Tutorial contains a wo
117. ctions and refilled This introduces a processing latency were the pipeline has to be refilled every time the CPU branches to a procedure or interrupt Clearly the longer the pipeline the longer the latency Later on in this chapter we will see how the ARM instruction set minimises these branching latencys and how ST have designed their microcontroller to complement the CPU pipeline The Pipeline is automatically enabled within the CPU and is essentially transparent to the programmer However there are a couple of cases were the developer must be aware of possible pipeline side effects which can effect operation of code running on the CPU The first and most important case is the possibility of data dependencies between instructions In this case if we have two sequential instructions were one instruction depends on the result of another as shown below ADD RO R1 R2 RO R1 R2 OR R3 RO R4 R3 ROLRA The result from the first instruction is not available until it has passed through each stage of the pipeline However the result is required by the second instruction part way through its journey down the pipeline Since the first instruction has not competed this result is not available and the pipeline is stalled In practice the ARM9 five stage pipeline includes forwarding paths that make results immediately available between stages and removes this problem except for a few cases The instruction sequence shown below will cause a pipeline interlock
118. d Each message Data Length Code frame includes a reserved bit D 15 bit CRC l IDE bit D checksum RTR bit D Identifier Field Start of Frame This leads to one of the golden rules in developing a CAN network In a CAN network every identifier must be uniquely generated So you must not have the same identifier sent from two different nodes If this happens it is possible two messages with the same ID are scheduled together both messages will fight for arbitration and both will win as they have the same ID once they have won arbitration they will both start to write their data onto the bus at some point this data will be different and this will cause a bit check error both messages will be rescheduled win arbitration and go into error again Potentially this deadly embrace can lock up the network so beware At the bit level CAN also implements a bit stuffing scheme For every five dominant bits in a row a recessive bit is inserted Arbitration Data n ntl n 2 n 3 n 4 i Bit Stuffing For every five bits of one logic in a row a stuff bit of the opposite logic is inserted The error frame E SE LN A breaks this rule by being six n nt 1 n 2 n 3 n 4 n 7 dominant bits in a row Hitex UK Ltd Page 138 hitex mum DEVELOPMENT TOOLS Chapter 4 User Peripherals This helps to break up DC levels on the bus and provides plenty of edges in the bitstream which are used for resynchronisation An error f
119. d be that of an interrupt pipe or a 64 byte packet every frame or 64Kbytes sec roughly five times the speed of a serial port HID Report Descriptor Table 06h AOh FFh Usage page Vendor Defined 09h A5h Usage Vendor Defined Aih Oth Collection Application 09h 06h Usage Vendor defined Input Report 09h A7h Usage Vendor defined 15h 80h Logical Minimum 128 25 7F Logical Maximum 127 75 08 Report size 8 bits 95 02 Report Count 2 fields 81 02 Input Data variable absolute Output Report 09h A7h Usage Vendor defined 15h 80h Logical Minimum 128 25 7F Logical Maximum 127 75 08 Report size 8 bits 95 02 Report Count 2 fields 91 02 Output data variable absolute COh End Collection Once the USB device has enumerated as a HID device we need to be able to communicate to the USB network from your application software This is done by the WIN32 API that allows you to access many of the functions within the Windows operating system It is possible to use any development tool that can access the API such as Visual C or Visual Basic If you are using visual C you need to order the Windows Driver Development Kit DDK from the Microsoft website which is free but costs 25 for shipping The DDK includes lib and h files that are necessary for accessing the API functions needed to control the HID driver Afs Fap En L Pun iere FAET Chet E nl Faut 3g LET Pet LE Est Fai HOCH Cap Vans Da Cusen Du wei m eu a ven orme ad comes ad
120. d branch cache deliver instructions to the pipeline fast enough to prevent the CPU stalling While the write buffer provides zero waitstate access to the SRAM As we have seen in the introduction the principle factor that limits ARM core performance in a small microcontroller is simply the FLASH access time we cannot get the instructions fast enough to feed the CPU The FLASH access time is limited by the process technology used to make the STR9 and ultimately by the immortal laws of physics On the STR9 the on chip FLASH is arranged not as word wide 32 bits memory but is a 128 bits wide or four instructions This means simply that one FLASH access can read four instructions and pass these on to the I TCM So for a sequential series of instructions the effective instruction access time is one quarter the FLASH access time This also compliments the nature of the ARM instruction set because the conditional execution of all instructions produces code that is much more linear than more traditional microcontrollers When the code branches the burst FLASH must access a new location and a fresh 128 bit chain is fetched from the FLASH This means that after a branch the first instruction is available at the full FLASH access time and the subsequent instructions are available at one quarter the access time O Hitex UK Ltd Page 46 hitex Chapter 3 System Peripherals ENELOOP EM TOOLS The burst FLASH greatly improves the apparent access time
121. d is suitable for most other PC peripheral and finally High speed which runs at 480 Mbits sec and is aimed at video devices that require a high bandwidth The USB specification also defines the physical cabling and connectors This ensures that any user will put the right plug in the right socket The two connectors are shown below PERFORMANCE APPLICATION ATTRIBUTES OW SPEED Keyboard Mouse Lower cost Interactive Devices Game peripherals Hot plugging 10 100kb s Monitor Configuration ULL SPEED Phone Audio i The USB protocol tightly defines the Compressed Video USB physical layer including the 500Kb s 10Mb s Audi network connectors Guaranteed Bandwidth IGH SPEED Video Disk 25 500 Mb s Internally the cable has four shielded wires Two are used to carry power and two are for data The power wires carry 5V which can deliver 500mA of current The data wires are called D and D The maximum length of a shielded full speed cable is 5 meters Since the physical layer transceiver is incorporated into the STRS9 the hardware design consists of connecting the D wire to the D pin and the D wire to the D pin as we shall see later only one other external component is required to complete the design F A standard USB cable contains two data wires D and D and two power wires e P uiti carrying a 5V supply ba pP e Hitex UK Ltd Page 141 Chapter 4 User Peripherals The physical layer signalling uses a Non Return to Ze
122. d the USB device and the Mass storage driver allows the transfer of large amounts of data An understanding of both of these drivers will cover a large range of applications You can make a USB device into a HID class device by setting the class code in the interface descriptor to three as shown below Interface Descriptor 09h Descriptor length 04h Descriptor type 00 Number of interface 00 Alternate setting 01 Number of endpoints 03 Class code 00 Subclass code 00 protocol code 00 Index of string Hitex UK Ltd Page 155 hitex mum DEVELOPMENT TO OLE Chapter 4 User Peripherals When the PC discovers a HID device it will start to request a further set of descriptors called report descriptors The report descriptors define the structure of the data that is to be transferred for this HID device The USB Implementers Forum maintain a set of HID usage tables which define data structures from a number of common devices However it is possible to define a vendor specific structure that matches your requirements The report structure shown below defines a vendor specific report descriptor that configures the HID driver to transfer two 8 bit signed bytes IN to the PC and two 8 bit signed bytes OUT of the PC The IN transfer must be done over an interrupt pipe and the OUT transfer will be made over the control channel by default or it can use an OUT interrupt pipe if one is available The maximum transfer rate for a HID based device woul
123. d then reset to zero immediately with no down counting period This causes the PWM signals to all go to one at the zero count point and yields a waveform that is asymmetric For most purposes the Zero Centred mode is to be preferred as it results in lower harmonic content in 3 phase motor windings with a resultant decrease in acoustic noise and switching losses However if the load is non inductive asymmetric PWM is acceptable Usefully the Classical PWM mode allows a higher resolution for a given carrier frequency To get maximum motor torque most modulation schemes require the ability to generate a true 100 and 0 duty ratio i e PWM signal at one or zero for the entire PWM period The fact that the PWM counter is 10 bit but the Phase Compare registers are 11 bit means that regardless of the PWM Compare 0 register value the Phase Compare value can always be higher and thus ensure that no off event will occur resulting in a 10096 duty ratio IGBT Bridge Phase UH Channel 2 high 220v DC Link _ _ l Channel 2 low jas Phase UL 4 LI LILILII Phase VH _i LI LI LI LI Channel high Pe Ges Phase VL JU UU Ud Channel low Le ae NN 3 Phase Motor m Phase WL Channel 0 low ESTOP STR912 GND Driving a 3 Phase Induction Motor With Complementary PWM Signals Hitex UK Ltd Page 0000000 Chapter 4 User Peripherals hitex mms DEWVELOHP s EM DO LE Although there are only three Phase Compare regist
124. de as there is no SPSR and the result would be unpredictable Mnemonic Meaning AND Logical bitwise AND EOR Logical bitwise exclusive OR SUB Subtract RSB Reverse Subtract ADD Add ADC Add with carry SBC Subtract with carry RSC Reverse Subtract with carry TST Test TEQ Test Equivalence CMP Compare CMN Compare negated ORR Logical bitwise OR Hitex UK Ltd Page 18 conditional execution a logical shift of up to 32 bits and the data operation all in the Chapter 1 The ARM9 CPU Core hitex mm DEVELOPMENT TOOLS MOV Move BIC Bit clear MVN Move negated These features give us a rich set of data processing instructions which can be used to build very efficiently coded programs or to give a compiler designer nightmares An example of a typical ARM instruction is shown below if Z 1 R1 R2 R3x4 Can be compiled to EQADDS R1 R2 R3 LSL 2 Copying Registers The next group of instructions are the data transfer instructions The ARM9 CPU has load and store register instructions that can move signed and unsigned Word Half Word and Byte quantities to and from a selected register Mnemonic Meaning LDR Load Word LDRH Load Half Word LDRSH Load Signed Half Word LDRB Load Byte LRDSB Load Signed Byte STR Store Word STRH Store Half Word DEROA Store Signed Half Word STRB Store Byte DIRIB Store Signed Half Word Since the register set is fully orthogonal it is possible to load a 32 bit value into the PC forcing
125. diting the startup code directly however the StartEasy tool provides a simple window that allows you to easily set the stack sizes Project Ga Project Settings EI Global Settings EI Tool path EI Compiler Options EI Linker Options E RE EI CPU EI Debug Tool EI Build Logfile ea STR Setup 7 Project files UND SWE ABT FII IRU USR Adjust Stack Size words In addition the graphical editor allows you to configure some of the STR9 system peripherals We will see these in more detail later but remember that they can be configured directly in the startup code Exercise 2 Configuring the ARM9 Startup code This exercise focuses on the startup code The CPU stacks are set up and checked in the debugger The other critical areas of the startup code are also examined Hitex UK Ltd Page 31 hitex mum Chapter 2 Software Development DEVELOPMENT TOOLS 2 4 The ARM Procedure Call Standard APCS The ARM procedure calling standard defines how the ARMO register file is used by the compiler during runtime In theory the APCS allows code built in different toolsets to work together so that you can take a library compiled by the ARM compiler and use it with the GCC toolset Parameter Parsing The ARM procedure call standard defines how the user CPU registers should be used by compilers Adhering to this standard allows interworking between different manufacturers tools Scratch Register Stack Register L
126. dwidth management and should not let a new device on to the network if the resources are not available to service it Control Isochronous Bulk FS and HS FS and HS Pre or vendor Stream No structure Stream bn defined Transfer Bi direction Uni direction Either input or Either input or direction output output Packet 8 15 32 1 1023 LS 8 8 16 32 size bytes or 64 FS lt 64 or 64 Bus Best effort lt 90 lt 90 Good effort access guaranteed Periodic 1ms 255ms no guaranteed Data Sequence Setup data and No retry data Retry data Retry data status toggling toggling toggling 4 13 5 1 6 USB Network Transactions As we have seen the data transfer over the USB network is time division multiplexing The bus is delineated into frames by sending a start of frame taken every millisecond and the pipes transfer packets of data within these frames Each data transfer is constructed from a three packet transaction Loris bake rxvkot Phase Lk ik ihi Mk Chats ET Kei Pas k Le m T arm San E aur me Irnauctiari Each USB transaction consists of three packets which are exchanged between the master and slave nodes This consists of a token phase that defines what type of transaction is about to take place Next comes a data phase that transfers the necessary data and finally a handshake phase that establishes that the transfer has been successful Each of these packets is made out of the same basic structure
127. e CAN peripheral in its operating mode and transmit data to a real network 1 Openthe HITOP project in the STR910FExamples CAN directory 2 Run the code so that it initialises the CAN peripheral and examine its settings Arb Registers l and Z CAN IFl Al 2R g ID z8 16 0004 ID 15 0 0000 MsqVal Message is Valid res T ege Segment after Sample Point H EE Standard 11 Bit Bit Timing Register CAN BTR TSegl Seqment before sample Point SIM Synchronisation Jump Width 3 Dir Message Direction Transmit EEF Baud Fate Frescaler Message Control Register CAN IFIMCE HewDat New Data stored FE Test Bengister CAN TESTER z MsgLst Message lost Ho we Ex Ex Pin iz Becessive il IntPnd Interrupt is Pending No UMask Use acceptance Mask No Tx T Pan centr by CAN Core Txlnt Tranzmit Int Disabled LBack Module in L Back Mode Yes Bxlnut Receive Int Disabled Silent Module in Silent Mode No bul EmtEn Remote Enable No TxBRqst Transmission Requested No Basic Module in Basic Mode Yes EoB Single Obj in Buffer Na DLC Objekt Data Length Code EEPE Baud Bate Prese Extension Data B Registers CAN IFl DA BIR Data Al jOOSS Data Az 0000 Data Bl 000 Data Be n0n 3 Send the first message and examine the IF1 TX and IF2 RX message buffers to check that the correct data has been sent and received Hitex UK Ltd P
128. e SSP contains a clock prescaler register that can be used to divide PCLK by any even value between 2 and 254 bit zero in this register is hardwired to zero The serial clock rate field in control register O can then further divide PCLK by a maximum of 256 The SSP serial data rate can be calculated from the following formula SSP bit rate Pclk CPSRDIV x 1 SCR Where CPSRDIV clock prescaler register SCR serial clock rate control register O Two DMA units can be configured to support receive and transmit data transfers to and from each SSP peripheral The DMA support can be enabled by setting the TXDMA and RXDMA bits within the DMA control register In addition you must configure a DMA unit to support each transmit and receive channel see the DMA section in chapter 3 15 14 A 12 11 10 g B D 6 5 a d 1 TEDA FLE LAU FA ne The DMA support allows the allows the synchronous serial peripheral to be a sink or source flow controller for the general purpose DMA units If you are not using the DMA support the SSP peripheral can be used by polling the status register or by enabling the SSP interrupts Data can be transmitted by writing the correct word size to the data register were it will be queued in the transmit FIFO before entering the transmit shift register Received data will enter the receive shift register and then be queued in the receive FIFO which can be accessed be reading the data register The status regist
129. e clock during normal running idle mode and when the ARM9 is under JTAG control idie Mode Gating D die Mode Gating 1 Emulation Gating 0 Emulation Gating 1 Hitex UK Ltd Page 63 Chapter 3 System Peripherals hitex ES DEVELOPMENT TOOLE Within the peripheral clock gating registers each peripheral is represented by a single bit which is used to enable and disable the clock line to the selected peripheral After reset most of the user peripheral clocks and some of the important system peripheral clocks are disabled and held in reset by the peripheral reset register Each peripheral has an bit in the idle mode gating mask register These bits are used to define the behavior of each peripheral clock when the CPU enters its low power idle mode If the idle mode gating bits are cleared the peripheral clock will be halted when the CPU enters its power down mode The third gating register controls the peripheral clocks when the JTAG debugger is active This gating register allows selected peripheral clocks to be halted when the CPU is under JTAG control This does not mean the whole of a JTAG debug session but only when the JTAG is actively controlling the CPU This typically occurs whenever the CPU is halted by the JTAG This breaks the real time performance of the peripherals but allows the debugger to step then in sync with the CPU giving us much greater control of low level debugging for device drivers 3 8 8 Low Power Modes The ST
130. e data packets perform an identical function and the only difference is one bit in the packet header called the data toggle bit which is used for error detection will explain this when we look at the error containment methods used in the USB protocol 4 13 5 1 6 3 Handshake Phase The final phase of a bus transaction is the handshake phase In this phase there are three handshake packets that are used to signal whether a successful transaction has taken place The ACK packet is used to acknowledge a successful transfer of data and will end the bus transaction The PC will then start the next token phase The NAK packet is a not acknowledge This may signal that the transfer has failed because an error checking rule has been violated A NAK may also be generated if the Endpoint buffer is not ready for the transaction So if data from a previous OUT transfer is still in the Endpoint buffer the USB peripheral will generate NAK handshakes until the CPU has read the data If a NAK is generated the PC will attempt to resend the same transaction in the next frame Remember that for isochronous transfers the handshake is ignored If the Endpoint buffer is full and the CPU never removes the data we will get continuous NAK exchanges on the pipe every frame This will start to waste bandwidth For this reason there is a third form of handshake called STALL A STALL handshake is used to tell the PC that USB device can no longer communicate on this pipe For examp
131. ectively six stacks in the ARM9 The strategy used by the compiler is to locate user variables from the start of the on chip RAM and grow upwards The stacks are located at the top of memory and grow downwards The startup code enters each different mode of the ARM9 and loads each H13 with the starting address of the stack Hitex UK Ltd Page 30 Chapter 2 Software Development Switch mode and disable interrupts Load address into the stack pointer Calculate start address of next stack Finally switch to USER mode and enable interrupts Check for ARM or Thumb mode hitex mum D E i Li PF B I H FT D SE S Setup Stack for each mode LDR R0 Top Stack Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR c Mode UNDE Bit F Bit MOV SP RO SUB RO RO UND Stack Size Enter Abort Mode and set its Stack Pointer MSR CPSR c Mode ABTI Bit F Bit MOV ap RO SUB RO RO ABT Stack Size V FIQ IRQ and supervisor stacks Enter User Mode and set its Stack Pointer MSR CPSR_c Mode USR gt MOV SP RO Enter the C code LDR RO C INIT TST RO 1 Bit 0 set INIT is Thumb Load an Exit address into the link register _____ LDREQ LR exit A ARM Mode Jump to the C init routine LDRNE LR exit T Thumb Mode BX RO Like the vector table you are responsible for configuring the stack size This can be done by e
132. ed because it may have values which are being used by the background user mode code so this register is pushed onto the system stack also the user stack Once this is done we can run the ISR code and then execute a second macro that reverses this process The second macro restores the state of the link register Disables the IRQ interrupts and switches back to IRQ mode finally restores the SPSR_irg and then the interrupt can be ended The two macros that perform these operations are shown below Hitex UK Ltd Page 72 DEWVELOHP s EM FO LE Chapter 3 System Peripherals hitex Ess define IENABLE Nested Interrupts Entry asm MRS LR SPSR FF Copy oPSR irg to LR x Two macros asm STMFD SP LR Save SPSR_irg WI can be used to __asm MSR CPSR c 0x1F Enable IRQ Sys Mode Wi allow nested Save LR interrupt processing in the STRO9 for a asm STMFD SP LR define IDISABLE Nested Interrupts Exit very small asm LDMFD GET ALR Restore LR i code and time asm MSR CPSR c 40x92 Disable IRQ IRQ Mode overhead asm LDMFD SP LR Restore SPSE irq to LR __asm MSR SPSR_cxsf LR Copy LR to SPSR irg x The total code overhead is 8 instructions or 32 Bytes for ARM code and execution of both macros takes a total of 230 nanosec This scheme allows any interrupt to interrupt any other interrupt If you need to prioritise interrupt nesting then the macros wo
133. ed w GPIO USB Bus USB 2 0 Full Speed 10 Endpoints with FIFOs Ethernet Ethernet E MAC or i6 Pacaran GPIO Shared wi GPIO AHB bus APB bus a o e e e x gt VREF GND STR91x The STR9 has three internal busses IA high speed bus which connects the CPU to the on chip memory and complex peripherals the remaining peripherals are connected to two separate peripheral busses As the STR9 is designed to be a high performance general purpose controller it can run the ARM9 core at 96MHz Since the ARMS is capable of executing instructions in a single cycle the key design bottleneck is allowing the CPU to access its on chip memory at a fast enough rate to prevent any CPU stalls In the STR9 ARM9 based microcontrollers the on chip SRAM and FLASH are connected directly onto the AHB If this approach was used on the STR9 the maximum speed of the processor would be limited by the FLASH access time over the AHB bus This would give us a CPU limited to around 50 MHz Also the performance of the DMA units would be limited because the available AHB bus bandwidth would be reduced by the frequent accesses of the CPU to the on chip memory via the internal bus So to take advantage of the ARM9 s potential a different approach is required Hitex UK Ltd Page 44 ELDHP LU E Wl FTO OL Chapter 3 System Peripherals 3 3 Memory Structure There are a number of approaches that could have been taken when desi
134. egisters OCMP 1 0CMP2 15 14 13 12 11 10 9 B T B D ps 3 2 D EN FWAI DOMASO ACV pois ove power KSE OCE OFM PWM iEDOS mode ECKXEM EXEDG Control register 1 allows you to select the source register for a DMA transfer Once the DMA source has been selected the DMA transfer can be enabled by setting the DMAIE bit in control register 2 Hitex UK Ltd Page 94 hitex mum DEVELOPMENT TOOLE Chapter 4 User Peripherals 15 B 13 12 n 10 g B D Bb g d J 2 1 CAE otag TOE ICHE otha cs remm CCT GO CCS CA GC Cog Col CO Um bn re Fi rm FA re re rim mw he T rei Once the DMA source is selected the DMIE bit in control register 2 enables the DMA transfer This configures the DMA channel in the timer unit however the DMA transfer has to be fully configured as discussed in chapter 3 Hitex UK Ltd Page 95 hitex mm mL omg DEWVELOHP s EM EN AO c a D Chapter 4 User Peripherals 4 6 The MC 3 Phase Induction Motor Controller The MC Motor Control peripheral is a complete 3 phase power inverter controller that is aimed mainly at 3 phase induction motor control although it can be used for other power control tasks It makes use of Pulse Width Modulation PWM to produce sine waveforms of varying amplitude and phase that are suitable for driving common half bridge power devices To eliminate external hardware it includes an automatic deadtime offset between high side and low s
135. elect 0 is the same as chipselect 3 The first five registers control the number of waitstates used in various phases of the read write cycle The cycle control register defines the number of idle cycles between a read and write cycle the read and write state control registers define the number of wait states present in the read and write accesses to the external memory The output enable control register defines the number of cycles delay in asserting the chipselect signal to enable the external memory device while the write enable control defines the delay in cycles before the write signal is asserted on the external device Hitex UK Ltd Page 56 Chapter 3 System Peripherals hitex mum DEVELOPMENT TOOLE When programming these registers the following timing rules must be observed Read wait states gt Output enable states gt Write wait states gt Write enable wait states gt The final register in the EMI chipselect block is the bank Output enable wait states ALE enable time Write enable wait states ALE enable time control register This register further defines the characteristics of the memory region controlled by a given chipselect 11 10 PLEN 1 0 The EMI bank control registers define the memory width 8 or 16 bit and write protection for each external page If an 8 bit non multiplexed bus is used 4 or 8 byte burst transfers can be enabled by setting the Page mode PM bit and selecting the page len
136. enerated This ensures that a full correctly formatted message has been received Each message must be acknowledged by having a dominant bit inserted in the acknowledge field If no acknowledge is received the transmitter will continue to send the message until an acknowledge is received Iriles Frane v cie i Recgpst i epee oT El wf Fiuu mJ ames d a ee reek ler AARNE WE uus Acknowledge All CAN jive ber Toul Eau WE Shi n fan faang di frames must be iia acknowledged If there is no bem SANT n handshake the message will illi Fs apr Dn rund be re sent Id roi tue Unis Loris xd pls ka TE prane ai hii i geb Leda DLE l i Tii KTR lu iD Laumgd tli E Li Das gi je ei Kaiser Fre Lan Brut The CAN message packet also contains a 15 bit CRC which is automatically generated by the transmitter and checked by the receiver This CRC can detect and correct 4 bits of error in the region from the start of frame to the beginning of the CRC field If the CRC fails and the message is rejected an error frame is generated onto the bus Standard 8 byte Data Frame Inter Frame Space Xn 1 Recessive com 0 Dominant CRC is DL Intermission CRC calculated using End of Frame all previous bits ACK Delimiter A 15 bit CRC is automatically within the frame ACK Slot generated which is a stuff bits are not CRC Delimiter weighted polynomial included CRC Se
137. enerated the exception Eu epe iss The non vectored interrupt has one vector address slot that will jump all non vectored interrupt sources to Vector A dness one default ISR 3 8 15 Leaving A Non Vectored IRQ Interrupt As with the vectored IRQ interrupt you must clear the peripheral flag and write to the vector address register WDG gt SR amp 0x00000001 Clear the Watchdog End of count flag VICO 2VAIR 0 0 Dummy write to clear interrupt pending 3 8 15 1 Example Program Non Vectored Interrupt Within the VIC it is possible for the application software to generate an interrupt on any given channel through the VIC software interrupt registers These registers are nothing to do with the software interrupt instruction SWI but allow interrupt sources to be tested either for power on testing or for simulation during development Software nenun Register Interrupt Channel e Interrupt Source In addition the VIC has a protected mode which prevents any of the VIC registers from being accessed in USER mode If the application code wishes to access the VIC it has to enter a privileged mode This can be in an FIQ or IRQ interrupt or by running a SWI instruction Hitex UK Ltd Page 71 hitex um Chapter 3 System Peripherals DEVELOPMENT TOOLS Typical latencies for interrupt sources using the VIC are shown below In the case of the non vectored interrupts use the latency for the vectored interrupt
138. ent from the ARM prime cell range of modules and as such is a highly optimised interrupt controller The VIC is used to handle all the on chip interrupt sources from peripherals Each of the on chip interrupt sources is connected to the VIC on a fixed channel The VIC provides channels for a maximum of 16 interrupt sources Within the STR9 there are some 31 interrupt sources which all need a fast interrupt structure The simple solution to this problem is to design the STR9 with two separate VIC units that are daisy chained together The two units provide a total of 32 interrupt channels which support all the interrupt sources within the STRS 30 External Interrupts Port 3 Port 5 CC Port 6 b t pe ETC Interrupt LSB Resume Intr Wake Up Event IRO Interrupt FIQ Interrupt DE E e Interrupts The STR9 interrupt structure consists of two chained vector interrupt controller units and a wake up external interrupt module Hitex UK Ltd Page 66 Chapter 3 System Peripherals WELPE H au kd PR 2 Your application software can connect each of these channels to the CPU interrupt lines FIQ IRQ in one of three ways The VIC allows each interrupt to be handled as an FIQ interrupt a vectored IRQ interrupt or a non vectored IRQ interrupt The interrupt response time varies between these three handling methods FIQ is the fastest followed by vectored IRQ with non vectored IRQ being the slowest We will look at each
139. equire complex software and is very application specific so that it would be almost impossible for the silicon manufacturer to include something that would be useful or supportable For users who are happy with conventional bootstrap loaders it is not too difficult to implement a typical UART based system Here a port pin is pulled low to cause the program in the boot bank to enter the bootloader mode It would wait for a zero byte to be received using one start bit 8 data bits and one stop bit By measuring the width of the start bit and the 8 data bits the baudrate is determined and a response byte is sent back at this baudrate The sender would then transmit a simple program of 32 bytes that is loaded into the on chip SRAM and then executed This program itself is able to receive a much larger program of say 1kbytes that would probably be some sort of FLASH programmer that then receives a new main application which it then blows into FLASH bank 0 Variations on this might that the SSP or CAN modules are used to receive programs A conventional serial bootstrap loader for bank 1 boot operation is available from the Hitex website 3 4 6 Configuring The STR9 For User Defined Bootstrap Loaders The key feature that allows user defined bootstrap loaders is the ability to set the boot FLASH bank This is done by writing to a 64 bit configuration register at 0x52000000 0x52000007 via the JTAG interface only interface using a tool such as the ST CAPS uti
140. er provides transmit and receive FIFO flags that allow you to control data flow during polled operation Hitex UK Ltd Page 88 hitex i DEVELOPMENT TOOLS Chapter 4 User Peripherals ESY AFF ANE THF TFE F j l E The status register contains flags for the receive FIFO status RFF RNE and transmit FIFO status TNF TFE and a busy flag The SSP has a single interrupt line connected to a VIC interrupt channel and internally the SSP has transmit and receive interrupts when the FIFO is half empty transmit and half full receive The receive interrupt has an additional receive timeout interrupt which is triggered when no characters have been received for a number of bit periods and there is data in the FIFO This allows your firmware to collect the last few words of data at the end of a transfer that would not trigger a FIFO interrupt The final interrupt source can signal a receive overrun were the receive FIFO is full and further data has been placed on the serial bus Hitex UK Ltd Page 89 hitex mm OPMENTTOOLS Chapter 4 User Peripherals EWE i 4 5 Timer Counters The STR9 has four 16 bit timer counter blocks with IO pins that may be allocated as shown in the table GPIO Mode Alternate In 1 Alternate Out 2 Alternate Out 3 Alternate In 1 Alternate Out 2 Pin 0 TIMO_OCMP1 TIMO ICAP1 TIMO_OCMP1 Pin 1 TIM1_OCMP1 TIMO ICAP2 TIMO OCMP2 Pin 2 TIM1 ICAP1 TIM1 OCMP1 Pin 3 TIM1 ICAP2
141. er that can be set to only accept a specific message or range of messages CAN IF1 AIR 0x00000000 Clear the arbitration register CAN IF1 A2R 0x0000A001 Set the ID for a standard message CAN IF1 MCR 0x00000001 Set the data length code to send just one byte CAN IF1 DA1R 0x00000055 Write the data in data0 register CAN IF1 CRR 0x00008001 Set the busy bit to start transmission In basic mode the IF2 message registers become the receive buffer However it must be enabled by setting the message valid bit in the upper arbitration register CAN IF2 A2R 0x8000 Hitex UK Ltd Page 133 hitex mum DEVELOPMENT TOOLS Chapter 4 User Peripherals When a message is received the new data flag in the message control register will be set and the new message packet may be read from the IF2 registers The new data flag must be cleared to unlock the IF2 registers so another message may be received if CAN IF2 MCR amp 0x8000 id CAN_IF2_A2R gt gt 2 amp 0x000007FF I read the ID 11 bit standard dlc CAN_IF2_MCR amp 0x0x0000000F read the data length code test CAN IF2 DAIR read the message data CAN IF2 MCR amp 0x8000 clear the new data flag 4 13 4 2 Full CAN Mode While basic CAN mode is easy to use it does mean that an interrupt will be generated for every message received and even with the use of the message masks in a medium to heavily loaded network this will put a significant loading o
142. ers the MC peripheral can still generate the 3 base low side and 3 high side complementary drives required for the half bridge configuration show above The complementary outputs are produced by the deadtime generator automatically and appear on Port 6 3 4 5 PAM Counter Prescaler Reg PCLK 8 bit Prescaler 10 bit PWM Counter P Dead Time p DIV 2 42c Int LL ADT Int l 11 bit Compare V Reg CPT 0 11 bit Preload Compare V Reg 8 bit Repetition PER 11 bit Compare U Ll aeu Dead Time Generator 11 bit Preload Compare U Reg Down Counter 11 bit Compare VV Reg pl Generator 8 Bit Repetition 11 bit Preload Compare W Reg Counter Reg Generator Reg rm J Generator D D in Ti D Cr e d Gi c 2 D E o S Inserting The Deadtime Offset Between High And Low Side Outputs To suit any drive electronics configuration the polarity of each of the 6 outputs can be individually set in the Polarity Selection register MC PSR 4 6 2 Adding The Deadtime Offset When using half bridge per motor winding it is necessary to add a small deadtime offset to the rising edges of the high and low pairs of waveforms This is to prevent both the high and low switching devices being momentarily active at the same time as a result of gate turn off delays This would effectively short out the DC Link power supply for up to a few microseconds and is clearly undesirable Typical deadtime
143. ers principally concerned with power and clock control within the STR9 However a number of other functions are controlled within these registers We will look at the system control unit in more detail later however in terms of the external bus the system configuration 0 system external memory interface clock control registers and GPIO output registers are of interest here The system control unit registers contain configuration registers that are used to fully enable the external bus and select its mode Hitex UK Ltd Page 54 hitex mum Chapter 3 System Peripherals e DEVELOPMENT TOOLS The system configuration register allows you to configure the external memory interface as a multiplexed or demultiplexed bus If the bus is configured as multiplexed this register also allows you to configure the characteristics of the Address latch enable ALE The length of the ALR bit can be configured to be 1 or two cycles long with the ALE length bit You may also control its polarity with the ALE POL bit in the same register En as Ed 15 14 13 i2 11 10 g E 7 6 s 4 58 d 4 ol 4 ZS F UART ADAT y Fi y Ki SLT D d g L d d ZZ e re KI re re m KH A re re re re re The EMI can be configured as a multiplexed bus with the EMI MUX field in system control register 0 The behaviour of the ALE signal can be defined in the ALE polarity and length fields The ports 8 and 9 are always used by the external memory i
144. es control of the chip and has to re establish control once the STH9 device comes out of reset This will take a finite number of clock cycles While this is happening any code that is on the chip will be run as normal Once the Tantino gets back control of the chip it performs a soft reset by forcing the PC back to address zero However the on chip peripherals are no longer in the reset condition i e peripherals will be initialised interrupt enabled etc You must bear this in mind if the application you are developing could be adversely affected by this A simple solution is to place a simple delay loop in the startup code or at the beginning of main After a reset occurs the CPU will be trapped in this loop until the Tantino regains control of the chip and none of the application code will have run leaving the STRO in its initialised condition A macro is included in the startup code to provide this delay macro StartupDelay delay value ldr R1 delay value Lar R2 O __ StartDelay sub Rl RL 1 cmp RE R2 bhi __StartDelay endm This macro is called at the entry point to your application It is only required for debugging and should be removed on the released version of the code dpXAXCKCKCKCKCkCKCkCk KC k k ck KKK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK Reset Handler Entry Point RKKKKKKKKKKKKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK k k ck KKK KKK KK KKK KKK KKK KKK ck kc KK KK Hard_R
145. eset app entry StartupDelay 500000 Stark Lars 7 2 15 Embedded Trace Module In addition ST has included the ARM embedded trace module The embedded trace module provides much more powerful debugging options and real time trace code coverage triggering and performance analysis toolsets In addition to more advanced debug tools the ETM allows extensive code verification and software testing which is just not possible with a simple JTAG interface If you are designing for safety critical applications this is a very important consideration PIPESTATE 0 Big Trace dig rer JTAG keim am In addition to the JTAG port ST have included the ARM ETM module for high end debugging tools Hitex UK Ltd Page 40 Chapter 2 Software Development The ETM debugging tools are more expensive than the JTAG tools however if you are working on a safety critical or similar high integrity application the real time trace advanced triggering and code coverage features allow you to validate your code to a high level of confidence Even if you do not intend to use an ETM tool it is worth tracking out the 9 or 10 if the ETM EXTRIG is used signals required for the ETM socket on your development hardware so if you do encounter a complex bug during development you at least have the chance of using such a tool Often such equipment is available for rental as well as purchase The pins to be used for ETM are shared with other peripheral IO funct
146. et to be transmitted with a matching identifier On receiving a remote frame the node which generates the matching message will transmit the corresponding message frame As mentioned the CAN message identifier can be up to 29 bits long There are two standards of CAN protocol the only difference being the length of the message identifier S Remote Transmit Request The RTR O Identifier RTR DLC CRC ACK EOF frame is used to request message F packets from the network as a master slave transaction Hitex UK Ltd Page 126 Chapter 4 User Peripherals hitex mms B EVELO FRE 5 GLS It is possible to mix the two protocol standards on the same bus but you must not send a 29 bit message to a 2 0A device Fins with A psit LU anim V ills LE bat Td VOR Active Ar Ali 3 DUH Passive emare UAN Module g VIDA CAN e ETET eet ie Alralule Dus FERRI 4 13 1 4 CAN Bus Arbitration CAN Type CAN 2 0A CAN 2 0B Passive CAN 2 0B Active Identifier Type 11 bit identifier 11 bit identifier 29 bit identifier If a message is scheduled to be transmitted onto the bus and the bus is idle it will be transmitted and may be picked up by any interested node If a message is scheduled and the bus is active it will have to wait until the bus is idle before it can before transmission If several messages are scheduled while the bus is active they will start transmission simultaneously
147. execution of ARM instructions The main instruction groups of the ARM instruction set fall into six different categories Branching Data Processing Data Transfer Block Transfer Multiply and Software Interrupt 1 7 1 Branching The basic branch instruction as its name implies allows a jump forwards or backwards of up to 32 MB A modified version of the branch instruction the branch link allows the same jump but stores the current PC address plus four bytes in the link register De Cf DD Le UXBOU The branch instruction has several forms The C branch instruction will jump you to a destination UxBIXX address The branch link instruction jumps to the destination and stores a return address in R14 BL Oo yea nn LDA Hz 10 Le HR So the branch link instruction is used as a call to a function storing the return address in the link register The branch instruction can be used to branch on the contents of the link register to make the return at the end of the function By using the condition codes we can perform conditional branching and conditional calling of functions The branch instructions have two other variants called branch exchange and branch link exchange These two instructions perform the same branch operation but also swap instruction operation from ARM to THUMB and vice versa PC Ox8000 314 Onde Hitex UK Ltd Page 17 Chapter 1 The ARM9 CPU Core hitex mm DEVELOPMENT TOOLS a ELX
148. ffer table access register acts as a pointer to the start address of a buffer description block which is held in part of the USB RAM This table can be located on any 8 byte boundary within this memory Euler Table Address The buffer table address register holds the start address of the buffer description block which describes how the USB message RAM is partitioned between the enabled endpoint registers The buffer description block is used to partition the USB RAM into a series of endpoint buffers for each of the enabled endpoints The buffer description block contains the start address and the size of a transmit and receive buffer for each endpoint Since only the control endpoint is bidirectional all the other endpoints need only specify a single buffer for transmit or receive depending on whether they are an IN or OUT endpoint Each endpoint _ register contains both configuration information endpoint address endpoint type and data transfer flags used during communication Hitex UK Ltd Page 152 hitex mum DEVELOPMENT TO OLE Chapter 4 User Peripherals jg COUNTS TX Mi ALEHTI TE Tr are nam COUNTS RA surfe ve h eg Export 1 maj ADOS PS a Le SE ERP NER E The buffer description block defines the start D I COUNT TK address and size of individual buffers allocated nm ADDHI TE e enabled endpoint within the massage xy OOUNTS Mi mci Am pn ees count TK pertinent gm
149. figured as bulk or isochronous the endpoint kind bit can be set to enable double buffering Fi x Gaffer To support the higher data rates of isochronous transfers the USB endpoint buffers can be double buffered Data is alternately buffered in the RX and TX buffers depending on the state of the data toggle bit in the USB packet USB application Device Properties Device Descriptors USB interrupts handlers template files usb prop c usb desc c usb istr c ts will be ndpoint is ering can Protocol Management Layer ll usb core c USB library main lements a files Hardware Abstraction Layer usb regs c Hitex UK Ltd Page 154 hitex PEW ELOPHERT TOI Chapter 4 User Peripherals 4 13 5 2 4 PC Device Drivers and Client Software In addition to understanding the USB network and the STR9 peripheral we also need to know how to access the USB peripheral from some application software on the PC The Windows operating system 98 2000 Millenium and XP supports USB with a built in USB stack and some generic driver support Aix rs acuti SECHER wech Winger L n dr capu him Oabrwes a LB dobre g user obese rtertace hw A chen ice omom hardware Class lunchon diro Laien ftunemon dra Lower Eon Dre GLACES deve IG Cedies Are wen fus sysipms LIB dri vera LSE Hub Cereer UBEHUEB Epi rewire Prat USB Bus Cass Driver IFSB Ss Manages LSA Tranactons Porat Bus rime Host Corna
150. ged by the application firmware 3 8 3 Reset The STR9 has several reset sources and two types of reset system reset and global reset A system reset is caused by a low level on the external reset pin a watchdog timeout or a JTAG reset command IH C3 20pF i POR reset time 10ms Minimum 100ns BI uo T 1 C2 N m 2 o pc G 29 H 3V3 d l i 20pF mm wi SEEEERI toss n TU MMM m d MCU XI MCU X2 RESET IN i 100 pin i RESET SIE d PB 7 Internal RESETO ums j i L 35 5 2 E EMALE Flash signal i 5 EMERD TE Internal RESET1 CI E CPU and peripherals 100nF POR reset Flash memory mins i i initialization phase SET EUM In addition to the power supply pins the STR9 only requires a simple reset circuit and a main oscillator When a system reset is asserted the program counter is forced to zero and the peripheral registers are reset except for the clock control register and the PLL configuration register in the system control unit A global reset is caused by a power on reset or a low voltage detect In this case all the peripheral registers are reset The System control unit status register contains two reset flags that allow you to determine if the cause of the reset was a watchdog timeout or a low voltage reset When either reset does occur an external reset signal is available to external components via the dedicated reset out pin 15 d 13 l2 11 10 9 B D D e The system cont
151. gister is also used to select which fields within the message object will be written to or read from This allows you to initialise the message objects for transmit or receive and initialise the message parameters Then during operation you can selectively read write the data portion of the message objects CANO CR 0x00000041 init and config change enable CANO_BRPR 0x00000000 Clear the extended BRP CANO BTR 0x000045C3 sect bit rat to 500K Configure a transmit object could use the IF2 registers CANO IF1 CMR 0x000000F0 enable write of mask arb and control registers CANO IF1 MIR 0x00000000 Clear the lower mask registers CANO IF1 M2R 0x00000000 Clear the upper CANO IF1 AIR 0x00000000 Clear lower arbitration register CANO IF1 A2R 0x0000A004 Message valed std frame transmit ID1 CANO IF1 MCR 0x00000001 DLC 1 CANO IF1 CRR Os0O00000015 write to message object one while CANO IF1 CRR amp 0x8000 wait for the message object to be written to configure a receive object could use the IF2 registers CANO IF1 CMR 0x000000F0 enable write of mask arb and control registers Hitex UK Ltd Page 135 hitex mum DEVELOPMENT TOOLS Chapter 4 User Peripherals CANO IF1 MIR 0x00000000 Clear the lower mask registers CANO IF1 M2R 0x00000000 Clear the upper CANO_IF1 AIR 0x00000000 Clear lower arbitration register CANO IF1 A2R 0x00008004
152. gning the memory structure of the STR9 To get the maximum performance out of the ARM9 ST could have added features such as an on chip cache and memory management units This would have increased the performance of the CPU and made it suitable for running heavy weight operating systems such as Linux and Windows CE However such an approach would have increased the complexity of the device making it more difficult to use and more importantly would use up valuable silicon area at the expense of user peripherals Also the STR9 is designed for real time control where deterministic execution of application code is vital using an on chip cache would have made the STRO9 inherently non deterministic For these reasons the STR9 has been designed to access its on chip memory through a pair of Tightly Coupled Memories TCM which allow fast access to the on chip memory without compromising the determinacy of the application code FI Bus RS RS To support zero wait state execution up to 96MHz the STR9 has an on chip memory subsystem that includes a burst FLASH prefetch queue with branch cache and an SRAM write buffer with arbiter This subsystem is connected directly to the ARM9 tightly coupled memories The TCMs are in effect a memory sub system located on the internal ARM9 instruction and data busses The TCMs in effect provide local stores of fast memory which are user to hold program instructions I TCM and program data D TCM In the case of the
153. gth Hitex UK Ltd Page 57 hitex mum Chapter 3 System Peripherals DEVELOPMENT TOOLS 3 8 System Peripherals In addition to the memory system the STR9 has a number of system peripherals that must be configured in order to run the microcontroller in its optimal configuration for your application The system peripherals are concerned with the STR9 power management and internal clock configuration the interrupt structure and use of the general purpose DMA unit 3 8 1 Power Supplies The STR9 can be configured with up to four external power supplies The CPU and memories operate from a 1 8V supply that is applied to the Vdd pin The on chip peripherals require a separate supply voltage which is applied to the Vddq pins This supply voltage can be in one of two ranges either 2 7V 3 3V or 3 0V 3 6V The voltage range is selected in the FLASH configuration register which can only be programmed by a JTAG programmer and not the application firmware 128 Pin DISCE i Pan DEVICE RM ot Rd COTES Nr Bs CF Tee E LATINE e The STR9 requires two power supplies 1 8V for the core and 3 3V for the peripherals The 128 pin devices provide an additional pins for an analog supply and ground The RTC and SRAM can be preserved during power down by a battery or suitable capacitor The remaining power supplies are optional and depend on your hardware Firstly the on chip SRAM and real time clock RC can be kept al
154. h peripheral this ensures that the STR9 starts up in a low power configuration You must enable each peripheral clock source before the peripheral can be accessed Hitex UK Ltd Page 81 ELOHRP LE I Wl FTO GLS Chapter 4 User Peripherals 4 3 General Purpose I O ports The STR9 has up to 80 General Purpose IO lines arranged up to 9 ports each containing 8 GPIO pins All of the GPIO pins are 5V tolerant and their output drivers may be configured as open collector or push pull Each of the IO ports may be configured in the same manner The only irregularities are port 4 port 8 and port 9 Port 4 has an analog input function to the ADC Ports 8 and 9 double as the external memory interface and have a separate configuration register in the system control unit Once configured Each GPIO port is controlled by 258 registers which support a clever masking technique that minimises the number of logical operations required to set and clear port pins Port Assignment 10 Mode No Port IO Mode of Unit Assignment 8 P4 Always chann Connected els 1 P1 P3 P5 Alt In Alt out 1 PO P2 P4 P5 Alt In P6 P7 Alt Out Alt Out P2 P5 Alt In Alt Out PO P4 P6 Alt In P7 Alt Out P1 P2 P3 Alt In P5 P6 P7 Alt Out D D Dedicated Ext clk P3 pins P3 P5 P6 Always P Connected Always Connected PO P1 P5 Always Connected Mux P8 P9 P7 P7 Alt Out Non P8 P9 P7 P7 Alt mux Out PO P5 P7 Alt Out 2 P0
155. h Include file for LED Control c STR91x h Include file to define the STR912 SFRs Hitex UK Ltd Page 176 hitex mm Chapter 5 Tutorial Exercises DEWVELOHP s EM d m Wal D 5 4 Exercise 2 Startup Code In this exercise we will configure the compiler startup code to configure the stack for each operating mode of the ARM9 We will also ensure that the interrupts are switched on and that our program is correctly located on the reset vector The example program will be the use used in the previous exercise Open the HiTOP project in the startup directory Open the Startup912 5S file This file contains the assembler startup code that runs before you reach the start of your C code At the beginning of this file there are a number of equates that configure the STR9 These are discussed in chapter 3 Also included in the equate are the definition of the stack sizes equ UND Stack Size 1 4 GOU SVC Stack Size 32 4 GOU ABT Stack Size 1 4 equ FIQ Stack Size 32 4 equ IRQ Stack Size 64 4 equ USR Stack Size 128 4 GOU Top Stack RAM Base RAM Size It is up to the developer to ensure that the stack space allocated for each operating mode is large enough Build and download the project and run it to main Using the SFR ARM processor registers window examine the start address of each stack and check that the correct stack space has been allocated Read through the startup to familiarise yourself with the functions carr
156. hannel field any interrupt channel may be connected to any given slot and then activated using the enable bit The priority of a vectored interrupt is given by its slot number the lower the slot number the more important the interrupt Vector Control n TEES oot n assigned to any peripheral interrupt channel the lower the number of the vector address the higher its priority Chai 4 A Cuno D Each vector address slot may be Lagu 5 Chanel 15 Hitex UK Ltd Page 68 DEVELOPMENT TOOLE Chapter 3 System Peripherals hitex Ra The other register in the VIC slot is the Vector Address Register As its name suggests this register must be initialised with the address of the appropriate C function to run when the interrupt associated with the slot occurs In practice when a vectored interrupt is generated the interrupt channel is routed to a specific slot and the address of the ISR in the slot s Vector Address Register is loaded into a new register called the Vector Address Register So whenever an interrupt configured as a vectored interrupt is generated the address of it s ISR will be loaded into a fixed memory location called the Vector Address Register Weck Address While this is happening in the VIC unit the ARM9 CPU is going through its normal entry into the IRQ mode and will vector the 0x00000018 the IRQ interrupt vector In order to enter the appropriate ISR the address in the VIC Vector Address Register
157. has high performance and low power consumption and it takes a small amount of the available silicon die area 1 2 ARM966E S ARM have designed a wide number of CPU cores which have traditionally been used as IP cores within custom chip designs typically for high volume products such as mobile phones and PDAs However in recent years there a large number of silicon vendors have adopted the use of ARM cores as the CPU for standard general purpose microcontrollers ST Microelectronics already have a comprehensive range of ARM7 based microcontrollers in the shape of the STR71x and STR73x The introduction of the STR9 family introduces an upgrade path that is both instruction set and development tool compatible with these ARM7 TDMI based microcontrollers The attributes of each ARM CPU are designated by the numbers and letters following the ARM name In the case of the STR9 the ARM core used is the ARM966E S The first number refers to the ARM CPU version This can range from the lowest performing core ARM7 up to the current highest performing ARM11 So as you might expect the STR9 has an ARM9 CPU which can run up to 200MHz All ARM CPU s are upwardly code compatible so code which executes on an ARM7 will also run on an ARMO The next two numbers refer to additional memory architectural support The ARM966E S is a minimal implementation of the ARM9 and does not include a memory management unit or on chip cache However it does have a write buffer and tightly c
158. he remaining message objects may be configured as receive objects The message mask and arbitration registers allow each message object to receive a specific CAN identifier or range of identifiers This allows you to use the remaining message objects as dedicated receive buffers When a message arrives at the CAN controller the enabled receive objects are scanned to find an message object that matched the message identifier If a match is found the message is stored and a receive interrupt is generated When the CPU responds to the message it can examine the New data registers to locate the updated message buffer The data can then be read directly without having to examine the message identifier The message objects are particularly suitable if you are running a loose network By this we mean it is not necessary to capture every CAN message For example you may have a CAN message that is sent every 100ms and contains a temperature reading In a process control application it is not necessary to capture every temperature reading i e the trend but it is necessary to know the temperature now In such a system a message object may be configured to receive the temperature message and the data will be refreshed each time the message appears on the CAN network The STR9 can then read the current value of the temperature variable whenever it needs it by accessing the data in the message data registers In effect the receive message data buffers can be thoug
159. herrea Sarai err TL el LAT ZELE Erk x mE Bea brm pru m Gas ba Fim i inti reer as e ibeji rail H papierne baim ge PR faki Ac ELE D OR Ca PL Ling H amp Lj Gef ER Gj rm BELL a i ram ee Lid e CR Cor IB Fee Dmm M ur 27 BEI EAP Pusabjed ATIRE TED sara TP LEB keel ded gE Eddie bed BCLEE linm za LTE b aai Land re ee m TEE OTT sw lu d i Hitex UK Ltd Page 188 hitex mum Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS 5 14 Exercise 12 Analog to Digital Converter This example configures the Analog to Digital Converter ADC to make a continuous conversion of channel 6 which is connected to the potentiometer on the STR9 board The analog watchdog is also enabled on channel 6 and an interrupt will be generated if the analog reading is above 0x380 The current analog reading is divided by 4 and displayed on the LED arrays The result is limited to the 0x380 threshold value 1 Open the ADC HTP project in STR910Examples ADC remember to enter the serial number of your Tantino when asked 2 Goto the MAIN C source window and place a breakpoint on the source line shown This line will only be executed when the analog value read is greater than 0x380 OxEO on the LED displays Move the potentiometer until the program halts Soi Lh Cessssernbhy gespent Tan EE Mars a oi ob ri copy of Ce result foc Lif display i Fail ie dispiar s HmmILIE
160. his requires a lot of background knowledge and some skill with PC programming and the windows operating system which is normally beyond the remit of embedded firmware development 4 13 5 1 Introduction to USB Before we look at the USB peripheral we will give an overview of the complete USB system This can be split into three parts USB theory of operation overview of the STR9 peripheral and introduction to the PC application requirements The USB network was first supported in the Windows operating system by adding additional drivers to Windows 98 The driver support was added as a standard part of the Windows operating system in Windows 2000 The goals of USB was primarily to allow easy expansion of a PC s peripherals with a foolproof plug and play network The USB 1 0 standard was released in 1996 and was soon superseded by version 1 1 The current revision of the standard is 2 0 and is maintained by the USB implementers forum who host a website at www usb org You can download the full specification from this website along with a number of useful utilities which we shall look at later The USB peripheral on the STR9 supports USB2 0 and throughout this is the revision of the specification that we will be working to 4 13 5 1 1 USB Physical Network The USB network supports three communication speeds low speed which runs at 1 5 Mbits sec and is primarily used for simple devices like keyboards and mice full speed which runs at 12 Mbits sec an
161. ht of as virtual network memory Hitex UK Ltd Page 134 Chapter 4 User Peripherals DEVELOPMENT TOOLE In full CAN mode a message transmitted from one node will update all the message buffers configured to receive this message The CAN controller message ram is like a page of virtual memory shared across the network However if your application must capture every message a receive interrupt can be generated for every message that arrives If you have a heavily loaded network particularly if the message traffic occurs in bursts this can create a lot of interrupts for the CPU to service The STR9 CAN module allows several of the message objects to be combined to create a message FIFO for a given message identifier so we can have lossy message objects for process control messages alongside FIFO buffers for critical lossless messages all combined in the same CAN controller The message interface registers are used in the same way as for the basic CAN configuration but once the data has been written to the registers the command register allows you to select the message object to update by writing to the message number field gt j Eh Lh E La Pal c 15b 14 13 12 11 id B B Data may be transferred too and from the CAN message objects by configuring the message mask register and then writing the message object number into the command request register During the data transfer the busy bit is set The command mask re
162. ide transitions There is also a tacho speed input to allow the accurate measurement of rotor speed plus an emergency stop input to allow the outputs to be put into a safe state in the event of a drive electronics or other failure There are a multitude of different ways to configure the MC peripheral for motor control plus there are a variety of higher level waveform control strategies sine modulation space vector modulation etc that can be employed via software but we will concentrate on the most common 3 phase drive approach in this section 4 6 1 Basic Motor Control The core of the MC is a group of three identical 11 bit compare registers Compare Phase U V amp W that are associated with a 10 bit PWM counter These compare registers are connected to GPIO pins Port 6 0 1 2 respectively and carry the low side PWM outputs A fourth 11 bit compare register Compare 0 Register is coupled to the PWM counter The operation of the pulse width 10 bit Preload Compare 0 Reg modulators is based FAN Counter Frescaler Reg 10 bit Compare 0 Reg CMO Int on the count rate and count range of the PWM counter The CMS bit rate at which the PCLK bit Prescaler 10 bit PAM Counter v CPC Hit counter increments is Div 2 usually determined i CMPU In by the RUP Wale 11 bit Compare U Reg gt is derived from the RCLK which is in turn 11 bit Preload Compare LI Reg derived from the JL FMSTR usually CMP Int 96MHz The PCLK i 11 bit Com
163. ied out by this code Hitex UK Ltd Page 177 hitex mum Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS 5 5 Exercise 3 Interworking ARM amp THUMB Instruction Sets In this example we will build a very simple program to run in the ARM 32 bit instruction set and call a 16 bit THUMB function and then return to the 32 bit ARM mode 1 Open the HiTOP project file and download the Interwork application into the STR9 FLASH memory 2 Reset the target and run to main 3 Inthe source window select the disassembly window and check that the instructions are compiler as ARM 32 bit instructions You can also check that the T bit in the CPSR is set to zero for ARM execution Fach ARM I2 But maridan e Four Etes omg ir ooo LED JETTZFEI bx k ERREF L E LEA ger ir ep Fi M T FL oe rit 7 1 LoopODOD EFT DIFFFFTE bi rx ic 1 f Para j I A Domno EF CDFFFFRE l ren pra F D T T The T bit is clear 4 Run the code up to the call to the THUMB function open the disassembly window and single step into this function to observe the switch from ARM to THUMB code In Tham made each mastmaetinm ts fan bytes long sg 5 IOPORTZ PD OxODODFFOD T Ebx ODORE EDI 4A kk rZ pe Al 21ch Ti One E42 wee mov r3 fn T O 000007 14 IPC ld r3 r3 St Te OO 16 1360 etr r3 r 0 F iin e aE ir l bx ir F elurn Lo the ARM calling funcion wilh a branch exchange on the contents of Gre bok reste 5 Observe the switch from 3
164. inally the LBE bit enables the UART loop back self test feature Once the UART has been enabled you must configure the internal baud rate generator Each UART is clocked by the BRCLK signal which is the master clock frequency or master clock frequency divided by 2 This clock signal must be divided down to give sixteen times the desired baud rate In order to accurately generate common baud rate from any value of BRCLK greater than 3 7 MHz well 3 6864MHz each UART has a fractional baud rate generator This is a divider which consists of two registers a 16 bit integer divider and a six bit fractional divider register The following calculations show how to set the baud rate to 9600 BAUD with a BCLK of 48 MHz First calculate the required divider value using the formula Baud rate divider Fbrclk 16 x Fbaud Baud rate divider 48000000 16 x 9600 312 5 Hitex UK Ltd Page 113 hitex mum DEVELOPMENT TOOLE Chapter 4 User Peripherals The integer value from this result can be programmed directly into the integer divider and the remainder can be used to calculate the fractional divider value using M int Remainder x 64 0 5 M int 0 5 x 64 0 5 32 Hence BRDi 312 BRDf 32 The acctual generated baud rate divider will be BRDreal BRDi BRDf 64 312 32 64 312 5 Which in this case gives a 100 accurate baud rate Once the UART is enabled and the baud rate has been configured the line control register is used to
165. ink Register Program Courtes The APCS splits the register file into a number of regions RO to R3 are used for parameter passing between functions If you need to pass more than 16 bytes then spilled parameters are passed via the stack Local variables are allocated R4 R11 and R12 is reserved as a memory location for the intra call veneer code As you select more options for the generated code such as re entrancy and stack checking the compiler adds additional Assembler code to support these features These Assembler veneers effectively add overhead to your code so it is important to only enable features which you intend to use The APCS also defines a stack frame which preserves the context of the CPU registers and also contains a pointer to the previous stack frame This is a very useful software debug task within an operating system such as Linux but it isn t that useful for a JTAG debugger The ARM procedure calling standard has a big impact on the speed of execution and stack size for the final application Consequently for a small embedded microcontroller like the STR9 it is best to stop the compiler from using this standard The compiler switch used to enable the APCS standard is mapcs frame or apcs And to disable it mno apcs frame By default StartEasy generates a project which disables the use of the APCS Hitex UK Ltd Page 32 VELO PARENT TOOLE Chapter 2 Software Development 2 5 Interworking ARM and THUMB O
166. ink or source flow controller for the general purpose DMA units Each UART can be enabled to be a DMA flow controller This allows transfers between memory and each UART and also data transfers between other peripherals and each UART The DMA transfers are triggered by the internal FIFO transmit and receive interrupts which are in turn linked to the user defined FIFO trigger levels The UART transmit and receive DMA support is enabled within the DMA control register a further DMA on Errror bit allows you to automatically disable the receive interrupt when a UART error condition is generated Hitex UK Ltd Page 116 hitex DEVELOFBSFBNTITOIL Chapter 4 User Peripherals 4 11 1 UART IrDA Mode The STR9 UARTS are also designed to support infrared communication using the IrDA standard IrDA is a standard for wireless communication using infrared light and is typically used on consumer products such as television and VCR remote controls IrDA is a widely supported low cost standard that is also free from control by regulatory bodies unlike radio control One big technical advantage of IrDA communication is low power operation making it ideal for hand held devices During normal RS232 communication the logic level of the serial data is asserted for the full duration of the bit period For infrared communication the IrDA standard specifies that the serial data logic level is only asserted for a portion of the bit period this significantly redu
167. interrupt Watch Watchz nx ma Ze ID EHDECSSIOD Value i KE ol i 40000 Ox00009C40 LE fi init Sf main e i EE startup oP Globals Mem Locals Watch Watch Hitex UK Ltd Page 171 Chapter 5 Tutorial Exercises hitex mum DEVELOPMENT TOOLE You can drag and drop variables into this window from the source code and from the project explorer or use the right mouse button and select Add Watch END USER CODE MAIN LOOP f BEGIN USER CODE FUNCTIONS f END USER CODE FUNCTIONS The Watch window supports all C and C data types including complex objects such as classes arrays structures and unions There are also dedicated windows for each of the STR7 peripherals These can be accessed with the view SFR window on the main toolbar The SFR windows show you the configuration of all the STR7 special function registers in the data book format This allows you to quickly confirm that a given peripheral is correctly setup In addition these windows allow you to manually control an on chip peripheral IO SETPORT IO ON for i 0 i BLINEY DELAY i IO CLRPORT IO OFF for i 0 i BLINEY DELAY Switch bo Edit Mode Set Breakpoint Run to Cursor Line Set Mew Program Counter Shaw PC Location Quick Watch a S ARM Processor Register J Configuration Reset and Clock Control Unit RECU J Enhanced Interrupt Controller EIC CA Real Time Clock RTC J Wa
168. ion pipeline The pipeline is used to process instructions taken from the program store On the ARM7 a three stage pipeline is used 5 STAGE PIPELINE DIEM Mr o TE T wr oe ARM TDMI 3 S TAGE PIPELINE F Te EET 2 E F oye CODE AND b EJF D E F COMBINED Von Neumann Architecture The ARM five stage pipeline has independent fetch decode execute memory read and memory write stages A three stage pipeline is the simplest form of pipeline which has independent hardware units for fetch decode and execute The ARMO extends this pipeline with additional memory read and write stages In the three stage ARM7 pipeline the memory and write functions are part of the execute stage The ARMSO pipeline gives these functions their own dedicated hardware as part of the extended pipeline This means that in the ARM9 execution of each instruction is split over more stages with the execute stage split into three simpler sub stages Since these stages each perform a small part of each instruction they can be run at a higher clock rate than the shorter ARM7 O Hitex UK Ltd Page 9 DEVELOPMENT Toti Chapter 1 The ARM9 CPU Core hitex three stage pipeline boosting the overall CPU performance This is true for code which is executed as a sequential series of instructions the code will pass through the pipeline in a linear fashion maximising the effect of the pipeline However when the code branches the pipeline must be flushed of instru
169. ions so at the design stage a decision must be made as to which pins are to be used Fortunately each ETM function appears on multiple GPIO pins and it is possible to take the ETM functions from several GPIO ports at the same time GPlO0 ep GPIO GPIO2 GPIO3 ep GPIO Mode Alternate Out 3 Alternate In 1 Alternate Out 3 Alternate Out 3 X Alternate Out 3 Pin 0 ETM_PCKO ETM_EXTRIG X ETM PCKO X ETM PCKO Pin 1 ETM PCK1 X X ETM PCK1 X ETM PCK1 Pin 2 ETM PCK2 X X ETM PCK2 X ETM PCK2 Pin 3 ETM PCKS X X ETM PCK3 X ETM PCK3 Pin 4 ETM PSTATO X X ETM PSTATO X ETM PSTATO Pin 5 ETM PSTAT 1 X ETM TRCLK ETM PSTAT1 X ETM PSTAT 1 Pin 6 ETM PSTAT2 X X ETM PSTAT2 X ETM PSTAT2 Pin 7 ETM TRSYNC ETM EXTRIG ETM TRCLK ETM TRSYNC X ETM TRSYNC GPIO5 GPIO5 GPIO6 GPIO6 GPIO7 GPIO7 GPIO Mode Alternate In 1 Alternate Out 2 Alternate In 1 Alternate Out 3 Alternate In 1 Alternate Out 3 Pin 0 ETM TRCLK ETM PCKO Pin 1 X ETM PCK1 Pin 2 ETM PCK2 Pin 3 E ETM PCK3 Pin 4 X Pin 5 X X Pin 6 ETM TRCLK X Pin 7 X The above table shows ETM capable pins The ETM alternate function is selected via the SCU GPIOOUT and SCU GPIOIN registers as with any normal peripheral function However some care needs to be taken when choosing the pins due to the very high frequency of the ETM signals Therefore it is best to take the complete ETM PCKO 3 and ETM PSTATO 2 signal set from one GPIO port with the ETM TRCLK from another port as physically close by as possib
170. ister register unsigned link ptr asm r14 When we enter the software interrupt routine we can use this pointer to read the contents of the SWI instruction which generated the interrupt This allows us to read the integer number encoded into the SWI instruction We can then use this number to decide which function to run within the SWI handler temp link ptr 1 amp OxOOFFFFFF The line above takes the contents of the link register and deducts one Remember it is a word wide pointer so we are in fact deducting four bytes This rolls the contents of the link register back by four so it is pointing at the address of the SWI instruction Then the contents of the instruction with the top eight bits masked off the condition codes and the SWI op code are copied into the temp variable The result is that the encoded integer in this case 2 is now stored in the temp variable and we can use its contents to decide which code to run The SWI instruction is a convenient method of leaving User mode to enter the Supervisor mode and run some privileged code The SWI calls can be used as part of a BIOS where all access to the special function registers is made via software interrupt calls This in effect partitions your application code so that all the hardware drivers run in Supervisor mode with their own stack and if necessary their own memory space You do not have to build your code this way but if you want to make use of it the mechanism is the
171. ither the Pclk bus clock which can be further divided by an eight bit prescaler or from an external clock source via the ECKEN bit in control register 1 If the timer is clocked from an external clock source you can select this clock source to be either Mclk or a true external clock source derived from the timer external clock pins The external clock source is selected with the TIMxxSEL bit in the system control unit clock control register If the timer is clocked from an external clock source you can link the external O Hitex UK Ltd Page 90 Chapter 4 User Peripherals hitex mum DEVELOPMENT TOOLS clock pin to the output of a second timer block making it possible to cascade the timers to build more complex timer arrays Each timer counter is controlled by eight registers which allow it to be configured for input capture and output waveform generation Each timer has a regular programmer s interface that allows easy configuration of each operating mode The timer block is a 16 bit counter with an 8 bit prescaler that is managed by two control registers 15 14 13 iz 11 10 B a 7 B 5 d J 2 1 D EN FA CAS PR FCR ous OL KSE RIEF OFM PWN ren erg ECKEN CNR 13 14 13 L n 6 2 4 E s t d 10 i B D ICA cau TOE cae cc ouae ME cc CCS CCS Cl CCD CCS OOI CCD rw e The timer control registers configure the prescaler CCO CC7 and the various capture compare operating modes The clock source is selected with
172. its message Once A has finished nodes B and C will transmit and node C will win and send its message Finally node B will send its message If node A is scheduled again it will win the bus even though the node B and C messages have been waiting In practice the CAN bus will transmit the message with the lowest value identifier Hitex UK Ltd Page 127 hitex mum Chapter 4 User Peripherals DEVELOPMENT TOOLS 4 13 2 CAN Module CAN TX CAN RX The STR9 CAN module is a full Can module with an internal message ram which supports 32 user configurable receive transmit buffers Message Handler BN Message RAM 7 Registers Interrupt Module Interface S S Data IN Data OUT Address 7 0 The STR9 CAN module will support CAN 2 0A and B with bit rates up to the full 1Mbit S It can operate in a basic CAN mode which is easy to use for simple CAN networks but also has a full CAN mode which enables 32 transmit and receive buffers stored in a block of message RAM located within the CAN peripheral The full CAN mode greatly reduces the CPU overhead when you a serving a heavily loaded CAN network The CAN controller register set may split into two halves the protocol registers and the message interface registers The special function registers may be split into two p T halves The protocol registers which configure the gtocol Fiegesiers CAN module and the message interface registers EN which are used to ac
173. ive by a dedicated battery supply when the two main power supplies are removed The STR9 will automatically switch to the standby voltage when the CPU supply Vdd drops below the Vbatt supply The analog to digital converter can also have its own dedicated supply and ground pins which can be isolated from the main supplies to the digital circuitry This prevents any switching noise reaching the ADC during its conversion period and helps increase its accuracy In the 80 pin package the ADC reference is tied to the analog supply voltage and the analog ground is shared with the digital peripheral ground Vssq The CPU peripheral analog and backup power supplies are connected to the STR9 pins as shown here Hitex UK Ltd Page 58 DEVELOPMENT TOOLE Chapter 3 System Peripherals hitex ER 3 8 2 Low Voltage Detector The two digital supplies are monitored by an internal low voltage detector which will generate a global reset as opposed to system reset see below if either supply falls below a critical level If a low voltage reset is triggered the LVD RST flag in the system status register is set when the STR9 comes out of reset A brown out interrupt can also be generated when the supply voltages drop below a defined brown out level This can give you some warning of an potential impending reset and allow you application to perform any remedial actions before it is reset The low voltage detector is configured by the a JTAG tool and cannot be chan
174. ive full flags which can be used to manage the receive queue Each UART has a number of internal interrupt sources which are ORed together and connected to a single channel within the VIC The UARTS have receive and transmit interrupts which can be triggered data queues in the FIFO reaches a user defined level This level is set in the FIFO level select register which defines the both the receive and transmit FIFO trigger levels Hitex UK Ltd Page 114 hitex mum DEVELOPMENT TOGOLE Chapter 4 User Peripherals 15 14 13 12 11 10 d B D D 5 J D 1 The FIFO select register allows you to define the trigger level for the receive and transmit interrupts In addition the receive FIFO has a character time out interrupt which triggers an interrupt when the receive FIFO contains data and no further data has been received for 32 bit periods At the end of a serial data sentence an interrupt will be generated if there is still some data remaining in the receive FIFO allowing you to clear out the final few bytes of data that did not trigger the main receive interrupt In addition to the received serial data the upper four bits of the receive FIFO contain error flags that describe any error conditions that occurred when the current character was received 15 14 13 12 11 10 d B T 6 D J D 1 Writing to the UART data register will enter serial data into the TX FIFO Received data can be read from this register The receive status flags associ
175. l 2 is routed to the ICAP1 pin This allows us to trigger on rising and falling edges for the same signal Counter ICAR 0x2EDO ICBR 0x34E2 ICAPA IEDGA 1 Capture A Capture B Capture A Period ICAPA IEDGB 0 Pulse Length ICAPB The PWM capture mode is synchronised on a pulse edge to reset the timer Capture A The next pulse edge Capture A will be captured into capture register B this is the duty cycle The next capture A event restarts the cycle and the capture A register contains the PWM period In this mode the count for rising edge of the signal is stored in capture register 1 and the falling edge is stored in capture register 2 Thus capture register 2 contains the pulse width and capture register 1 contains the signal period By enabling the capture 1 interrupt we can read both these values each cycle and reset the counter to start a fresh cycle PIMTI CR 0x000008FF enable interrupt on capture 1 event TIM1 CR1 0x0000C004 Timer enable Enable PWMI mode Capture 1 rising edge capture 2 falling edge Hitex UK Ltd Page 92 hitex mum Chapter 4 User Peripherals DEWVELOHP s EM DO LE 4 5 3 Output Compare In addition to the capture registers each of the STR9 timers has two compare registers with matching output pins When a match is made between the free running counter and the contents of the compare register a compare event is triggered This event can be used to generate an interrupt or ch
176. l FLASH access time The prefetch queue still only guarantees maximum performance for sequential code potentially when a branch occurs the queue must be flushed and the CPU will stall In order to reduce this to a minimum the memory subsystem also includes a branch cache which will store the last branches that the CPU has taken Pre Fetch Queue Branch Table 5 Entries The branch cache stores the last four branch destination addresses plus the instruction stored at the IRQ vector address A hit on the branch cache prevents the CPU stalling So when a branch instruction is executed the destination requested is compared to the addresses stored in the branch cache if a match is made the branch cache can immediately provide the required instruction while the Hitex UK Ltd Page 47 Chapter 3 System Peripherals prefetch Queue is being refilled one the branch cache instruction has been executed the prefetch queue is ready to deliver the next set of sequential instructions The worst case is when no match is made in the branch cache this means that the prefetch queue is flushed and must be refilled before the processor can resume execution In addition to the four level branch memory the branch cache has a fifth location which is used to store the contents of the IRQ interrupt vector This means that when an IRQ interrupt is generated the IRQ vector instruction is immediately available to the CPU which can jump to the required ISR and start
177. l need more MIPS than you may initially think O Hitex UK Ltd Page 8 Chapter 1 The ARM9 CPU Core hitex mm FELOPMEHT TOOLE The ARM7 CPU has a maximum operating frequency of 80MHz One features that limits the overall CPU performance of the ARM7 is its internal bus structure The ARM7 has a Von Newman memory architecture with a single address data bus which is used to transfer both instructions and data As the CPU frequency is increased the maximum CPU operating frequency is limited by the available bandwidth of the CPU bus The ARM9 overcomes this limitation by using a Harvard bus architecture which has separate instruction and data busses as shown below Instruction Data TC M A RMOGGE S TEM Interface RISC CPU Core vertace Control Lagic BIU and Wrote Butter AME XA AHE Interace This change of structure is one of the key elements that helps the ARMO9 reach much higher processing rates than the earlier ARM CPU s the number of instruction cycles required for load and store instructions is reduced compared to an ARM7 processor so than an ARM9 CPU is around 30 faster than an ARM7 running at the same clock frequency Being able to efficiently access the memory system is only part of the story if you can access the memory quickly the CPU must be able to process instructions at a similar rate The key to the increased CPU performance is the CPU pipeline 1 4 The Pipeline At the heart of the ARM9 CPU is the instruct
178. lar bank can be simultaneous with erasure or writing to another bank there is no need to go through the usual sequence of copying FLASH programming functions into SRAM for execution The FLASH banks can be protected against unwanted erase and write operations on two levels User programs can apply sector protection via the CUI to get level 1 protection but the JTAG interface is required to set or clear level 2 protection and as such this is a production line only facility To prevent unauthorised downloading of programs contain within the FLASH via JTAG a security lock bit at address 0x52000008 bit 0 can be set However although this prevents any reading of the FLASH from JTAG it still permits a full FLASH bank erase so that the device can be reprogrammed 3 5 One Time Programmable OTP Memory A special OTP block of 30 bytes is provided for the user to hard wire critical data into the STR9 These bits are arranged as half words 16 bit unsigned short and can be written from application or from JTAG Being one time programmable memory means that the user must be careful not to accidentally write to it An OTP lock bit can be used to prevent this even if some locations have already been used void FMI WriteOTPHalfWord unsigned char FMI OTPHWAddress unsigned short FMI OTPData Write a write OTP command to the needed address unsigned short volatile FMI BANK 1 0xCO0 Write the halfword to the destination address
179. le 2 16 Summary By the end of this section you should be able to set up a project with HITOP and GNU C select the compiler options and the variant you want to use configure the startup code be able to interwork the ARM and THUMB instruction sets access the STR9 peripherals and write C functions to handle exceptions With this grounding we can now have a look at the STR9 system peripherals Hitex UK Ltd Page 41 Chapter 3 System Peripherals Hitex UK Ltd Page 42 hitex um Chapter 3 System Peripherals DEVELOPMENT TOOLS 3 Chapter 3 System Peripherals 3 1 Outline Now that we have some familiarity with the ARM9 core and the necessary development tools we can begin to look at the STR9 device itself In this section we will concentrate on the system peripherals that is to say the features which are used to control the performance and functional features of the device This includes the on chip FLASH and SRAM memory Clock and power control subsystem and the on chip DMA control units Finally we will take a look at the STR9 interrupt structure and the advanced support provided by ST to supplement the two CPU interrupt lines IRQ and FIQ This is a key chapter in understanding how ST have integrated the ARM9 CPU into a standard microcontroller architecture All STRSXX dovices have 3 x UART GKB 2560432MB 48 Lan STRSH FMIT2XE 2 x Sp 2xPC 8 x 10b ADC RTC B x OMA 4 x 16b Iph AC MC Hitex
180. le if a printer ran out of paper and its memory became full sending further documents would cause lots of NAK packets on the bus In this case the printer can tell the PC via a stall packet that it is not ready to receive any more data and communication will stop over this pipe The PC could then try to find out why the data pipe is stalled by requesting data packets on an IN pipe which could transfer diagnostic information 4 13 5 1 7 Error Containment Within the USB protocol there are six different methods of error containment There are packet error checks which include a CRC packet ID check and bit stuffing rules When a packet is transferred the protocol can detect a false end of packet bus time loss of activity and babble where a node continues to transmit beyond its end of packet The two data packets also support a data toggle error check where a data one packet must always follow a data zero packet and vice versa So if for example a data one packet gets lost the node receiving the data will get a data zero packet followed by another data zero packet and an error will be raised All of these error handling methods are handled within the USB peripheral and are essentially transparent to the programmer Hitex UK Ltd Page 146 Chapter 4 User Peripherals 4 13 5 1 8 Device Configuration When a device is first connected to the PC its signalling speed is discovered and it will have Endpoint O configured to accept a control pipe
181. lication is running in user mode when an exception occurs the mode will change and the current contents of the CPSR will be saved into the SPSR The exception code will run and on return from the exception the context of the CPSR will be restored from the SPSR allowing the application code to resume execution The operating modes are listed below aper ier Apt Ing Lkakel ati rai ren nan FE Hi n1 ON HS RR ng a The ARM7 CPU has six Pg NM 3 FER operating modes which are Fal Ha D ba used to process exceptions ne fin hr en The shaded registers are Hh ng FR banked memory that is n n nt m switched in when the operating mode changes The na fur ru SPSR register is used to save a ra copy of the CPSR when the Rio Rue Hie Rep switch occurs B Bil tl Aaa a mum NU NI NI UNUM e m5 iP mrs IPC DIS PLI Bug Ci CFSR Hitex UK Ltd Page 12 Chapter 1 The ARM9 CPU Core hitex mum DEVELOPMENT TOOLS 1 6 Exception Modes When an exception occurs the CPU will change modes and the PC will be forced to an exception vector The vector table starts from address zero with the reset vector and then has an exception vector every four bytes Elm est COLE EUR Linie rien anri tri Lire krass Sotware imema S iN PFeeetoh AGG onatrucbon ch memory scit Ard Leen Abr ale access memory aor b IA stenge ie FIC l in keng Fi Cat E ek De UK 9 Od ROODODOCOK Da000000 10 Kante N i Deeg
182. lity As such the boot bank can only realistically be done during development or at the end of the production line Bit 48 of the configuration register sets the allocation of FLASH banks 0 and 1 to the internal chipselects CSO and CS1 As CSO is asserted coming out of RESET setting bit 48 to 0 will cause bank 0 to be the boot bank and setting the bit to 1 will select bank 1 Hitex UK Ltd Page 52 hitex mm Chapter 3 System Peripherals DEWVELOHP s EM d m Wal D 3 4 7 FLASH Programming FLASH programming is possible via the JTAG interface or by programs executing in the STR9 FLASH itself It is very unlikely that users will create their own JTAG based programming tools as this capability is including within the ST CAPS tool and commercial STR9 debuggers such as HITOP The user interface to the FLASH is via the FLASH Command User Interface CUI This provides a very simple method of erasing and programming so that for example erasing a sector is reduced to just void FMI EraseSector unsigned int FMI Sector Write an erase set up command to the sector unsigned short FMI Sector 0x20 Write an erase confirm command to the sector unsigned short FMI Sector OxD0 i e write the Sector Erase command to any address in the sector to be erased and then write the Sector Erase Confirm command to any address in the sector A similar command exits to erase an entire bank As execution from any particu
183. mply change the PDIV value to 2 Once enabled the PLL will take a finite amount of time to lock and then it may be selected as the master clock source The system status register within the system control unit contains two PLL flags 15 d 13 iz 11 10 E B d D 3 3 2 1 D d g d owl wl Ir ei KE wl rm wi m wi The system status register has separate Lock and Lock Lost bits which allow you to monitor the status of the PLL These two bits can also generate interrupts The PLL lock bit is used to indicate when the PLL has locked and the lock lost bit will be set if the PLL lock fails during normal operation Both of these bits can be used to generate an interrupt to the CPU which can be useful if you are changing the operation of the PLL as part of a power management strategy 3 8 7 Peripheral Clock Gating Once the PLL and various dividers are configured the various peripheral clocks pass through a set of gating registers before reaching the on chip peripherals These registers allow the clock lines to individual peripherals to be enabled and disabled By controlling these registers you can effectively switch off unused peripherals and prevent them from consuming any power apart from leakage current Each peripheral is controlled by three gating registers Peripheral Clock Registers Clock Gating 0 The clock for each of the STR9 peripherals passes through three gating registers that Clock Gating 1 enable disable th
184. must be loaded into the PC When an interrupt occurs the vector address slot associated with the interrupt channel will transfer its contents to the vector address register lcrepgiien LDR PC PC 0xFF0 0x0018 wraps around address space to 0xFFFFFF030 Vector from VicVECAddr ari As we are on the IRQ we know the address is 0x00000018 8 for the pipeline If we deduct OxFFO from this it wraps the address round the top of the 32 bit address space and loads the contents of address OXFFFFFF030 the Vector Address Register Execution the IRQ instruction is guaranteed to be a single cycle because the contents of the IRQ vector are permanently stored in the fifth location of the branch cache i j parts TT BS stir capit Weck fait oni When an IRQ exception occurs the CPU Lon PE IPC FF Lat Corien d Lagai executes the instruction LDR PC PC r Cath AFT ni PC OxFF0 which loads the contents of the vector address register into the PC forcing a jump to the ISR ects Akten leit PHF FFF E FF on Hitex UK Ltd Page 69 hitex mum Chapter 3 System Peripherals DEVELOP Eh E M t 3 8 13 Leaving An IRQ Interrupt As in the FIQ interrupt you must ensure that the interrupt status flags are cleared in the peripheral which generated the request In addition at the end of the interrupt you must do a dummy write to the Vector Address Register This signals the end of the interrupt to the VIC
185. n a function name the source will be displayed at the point that the program will return to The local options displayed by a right click also allow you to run the program up to a selected return point ef init 105 mani 145 x 4 ariable Return to Show Source v Docking View Hide Locals WW Hitex UK Ltd Page 170 hitex mm DEVELOFBSEFENTTOULE Chapter 5 Tutorial Exercises Take some time to become proficient with running the code You should be able to reset the target run until main single step the code set breakpoints and reposition the program counter 5 3 1 3 Viewing Data As well as controlling the program execution it is also possible to view the contents of any memory location within ARM7 address range The memory window is the most basic method of viewing and changing the contents of any memory location xX 4 Address Data ASCII a startup 63 Ad 00 OO EA OO OO AO El 08 FS 1F ES 46 OO OO E ResetEntry Ed 10 9F ES 00 20 AQ ES O1 10 41 E2 02 00 51 El vt O 00000030 FC FF FF 64 D4 10 9F ES 8 10 80 EB 00 10 AO E3 startup i10 40 10 80 ES 00 10 AO ES 44 10 80 ES At 00 SF ES Glee Diner O z00000050 DE FO 21 E3 00 DO AO El 838 OO OF ES D3 FO 21 E3 pod ee a ee O z00000060 O0 DO AO El 30 OO 9F ES D FO 21 ES OO DO AO El enr startup 122 88 00 SF EB Di FO 21 ES OO DO AU El 80 OO GF EB EE O Z00000080 D2 FO 21 ES 00 DO A
186. n the CPU The STR9 CAN module has a full CAN mode that enables a block of message RAM This message RAM is configured as 32 message objects which may be individually configured as transmit or receive objects individually configured as Message Interface 1 transmit or receive buffers The two sets of message interface Message Interface 2 oom Message Object n registers can access any of these buffers to send and receive Can messages The message RAM is arranged as 32 message buffers that can be Message Object 1 Message Object 31 The message RAM is accessed by the transmit and receive message buffer registers that were used in the basic CAN mode These two registers sets each become a floating window which can be set to interface to any selected message object in the message RAM to read and write data In full CAN mode the two interface register sets both act as interface windows and unlike Basic CAN mode do not have specific transmit or receive functions They can be used to perform either task Each of the 32 message objects may be configured as a transmit or receive buffer when the CAN controller is initialised The transmit objects can be configured with the message identifier and DLC initialised so to send a given message the CPU simply has to update the data and schedule the message for transmission So if your CAN application generates say 10 different messages onto the bus each message may have its own transmit buffer T
187. ncs EM main G E Variables 0 main EE startupaiz EM Globals E Functions 0 PI Variables ES Insert a new Folder into the 5 LED Control c E interrupt c LEI main c 3 skartupgiz s Insert existing Files into th The current location of the program counter is shown as a yellow arrow in the source window Main Program int main void Declare locals unsigned int units unsigned int tens unsigned int delay Initialise STR912 CPU All peripherals clocks are disabled by default ff Do not clear any bits in SCH PCGRO as this is the SRAM Enable GPIOS amp 9 peripheral clocks to drive LED arrays SCU gt PCGR1 SCU gt PCGR1 Ox00CO00000 Ox00C00000 E SCU gt PRR1 Ox00C00000 Force reset of GPI0a 9 ff Setup output pins H GPIO8 gt DDR OxOOFF Bits 0 7 are outputs H GPIOS gt DDR Ox0003 Bits 0 1 are outputs Hitex UK Ltd Page 168 hitex mum Chapter 5 Tutorial Exercises DEVELOPMENT TOOLS The blue squares at the edge of the source window indicate an executable line of code If there is no blue while 1 square there is no code at this location If you place d the mouse icon over a blue square a pair of braces BEGIN USER CODE MAIN LOOP is displayed A IO SETPORT IO ON for i 0 il BLINEY DELAY i H IO CLRPORT IO OFF i for i 0 i BLINKY DELAY i END USER CODE MAIN LOOP 4 If you now left click
188. ne modulation frequency is controlled by the potentiometer on AN6 The modulation ranges from 1Hz to 150Hz 1 Open the MOTOR HTP project in STR910Examples MOTOR remember to enter the serial number of your Tantino when asked 2 Connect a scope to the IMC connector pins P6 0 UH and P6 1 UL Connect the scope external trigger to port 3 7 this pin toggles at the end of PWM period so that you an see the modulation 3 Run the program and alter the potentiometer to make the modulation frequency and amplitude vary O Hitex UK Ltd Page 196 Chapter 5 Tutorial Exercises 5 21 Exercise 19 SSP This example connects the two SSP peripherals together and configures them as master and slave SPI devices The master is then used to initiate the transfer of data between the two peripherals 1 Onthe evaluation board connect the two SSP peripherals as shown below Master Slave MISOO P2 6 _ MOSI P1 6 MOSIOP P2 5 MISO P1 5 SCLKO P2 4 _ SCLK1 P1 4 The SSL pins should both be pulled high 2 Open the HITOP project in the STR910FExamples SSP directory entering the serial number of your Tantino when asked 3 Run the code so that it initialises both BSPI peripherals and examine their configuration in the SFR windows 4 Run the code and observe the ADC data being sent over the SPI bus and then being copied to the LED array Hitex UK Ltd Page 197 hitex mum Chap
189. ne of the most important features of the ARM9 CPU is its ability to run 16 bit THUMB code and 32 bit ARM code In order to get a reasonably complex application to fit into the on chip FLASH memory it is very important to interwork these two instruction sets so that most of the application code is encoded in the THUMB instruction set and is effectively compressed to take minimal space in the on chip FLASH memory Any time critical routines where the full processing power of the ARM 7 is required need to be encoded in the ARM 32 bit instruction set When generating the code the compiler must be enabled to allow interworking This is achieved with the following switch mTHUMB interwork The GCC compiler is designed to compile a given C module in either the THUMB or ARM instruction set Therefore you must lay out your source code so that each module only contains functions that will be encoded as ARM or THUMB functions By default the compiler will encode all source code in the ARM instruction set To force a module to be encoded in the THUMB instruction set use the following directive when you compile the code mTHUMB This option can be added to a give module either in StartEasy or within the HITOP IDE The linker can then take both ARM and THUMB object files and produce a final executable that interworks both instruction sets Exercise 3 Interworking The next exercise demonstrates setting up a project that interworks ARM and THUMB code 2
190. ng integer multiplication allows two 32 bit quantities to be multiplied together and the 64 bit result is placed in two registers Similarly a long multiply and accumulate is also available Instruction Operation Purpose MUL 32x32 32 Multiply MULA Qu e 32 MAC UMULL 32x32 64 unsigned multiply UMLAL 32x32 64 64 Unsigned MAC SMULL 32x32 64 Signed multiply SMLAL 32x32 64 64 Signed MAC In addition to the 32 bit multiplies the ARM9 has some additional maths instructions designed to support DSP type applications and fast multiplies Hitex UK Ltd Page 21 Chapter 1 The ARM9 CPU Core hi te zx ELO P BA F Mj IT OO E LIT 1 12 DSP extensions The ARMSG instruction set includes an additional group of instructions aimed at increasing the efficency of the ARM CPUs when running complex matamatical algorithms which are required in advanced control applications such as motor drives or consumer electronics such as MP3 players Like all the other ARM instructions the DSP instructions can operate on any register in the CPU register file and with the exception of the saturated instructions they are also conditionally executable The first group of instructions are an additional set of single cycle multiply instructions supported by the enhanced MAC unit These include a single cycle 16 x16 multiply and a 32 x 16 multiply Instruction Operation Purpose SMLAxy lOxl6 32 32 Signed MAC SMLAWy 32x16T32 32 Signed MAC wide SMLAL
191. ning La E we al vDDO The on chip FLASH memory consists of two FLASH banks and a small OTP sector The STR9 can be configured via the JTAG to boot from either bank After reset the STR9 places bank O at location 0x00000000 in the ARM9 address range however it initially appears as 32k in size Also at reset Bank 1 is disabled and cannot be accessed by the CPU After reset the CPU must configure access to the two FLASH banks through the FLASH memory interface registers Hitex UK Ltd Page 50 Chapter 3 System Peripherals buten DEVELOPMENT TOOLE 3 4 3 FLASH Memory Interface The FLASH memory interface FMI registers are separate form the FLASH programming and erase registers FPEC The FMI registers are used solely to set the base address and size of the two FLASH banks after reset Flash Memory interface The FLASH memory interface Boot Bank Size allows you to configure the size and location of the two FLASH banks At reset the boot bank is limited to 32K and the non boot bank is disabled The four FMI registers allow you to set the base address and size of the boot bank FLASH bank O and non boot bank FLASH bank1 Each of the base address registers allows you to set the start address of each bank on any word boundary within the 64MB address range allocated to the FLASH I TCM memory The size registers allow you to enable each sector within each FLASH bank so FLASH bank 0 can be enabled in 64k pages and FLASH
192. nits the SSP units are based on the ARM Prime cell modules which are specifically designed to interface with the ARM bus structure Each synchronous peripheral controller provides a single channel of synchronous serial communication which can be configured as a bus master or slave The SSP can be communicate with most common serial peripherals and supports the Motorola SPI National Microwire and Texas SSI protocols The SSP is interfaced to external devices with either 3 or four external pins depending on the protocol in use The Master out slave in MOSI and master in slave out MISO pins provide for a full duplex serial bus with a third pin used for the serial clock SCK An additional slave select NSS pin is used as a peripheral enable line when the SSP is used in slave mode This pin should be held high when the SSP is used in master mode Internally the SSP has separate transmit and receive FIFOs which can be up to 16 bits wide and eight words deep The serial clock is derived from the internal peripheral clock and the SSP can support data rates of up to 2 MHz The SSP is connected to the VIC by a single interrupt channel which can be triggered by receive of transmit events a receive overrun and a receive timeout For high performance serial connections the SSP can act as a flow controller for any of the DMA units The synchronous serial peripheral supports the SPI Microwire and SSI protocols The SSP can also be a flow controller for the DMA uni
193. nlinked 4 51Mbps CPU Double Buffer 5 59Mbps 46 5 DMA Linked 8 33Mbps CPU Double Buffer 6 14Mbps 51 156 DMA Linked 8 41Mbps The programmers interface for the USB peripheral consists of a register for each endpoint a control and interrupt status register two registers that give the current frame number and the network address and finally a buffer table access register that is used to configure the endpoint buffers Hitex UK Ltd Page 151 hitex mum DEVELOPMENT TOGOLE Chapter 4 User Peripherals Once the clock source has been configured the USB peripheral must be enabled by switching on the analog physical layer by setting the PDWN bit in the control register There is a delay while the transceiver is initialised and then the USB peripheral may be taken out of reset by clearing the FRES reset bit in the control register Finally any spurious interrupt flags must be cleared before the interrupt structure is enabled At this point the USB peripheral is active but any requests from the USB network will only receive a NAK handshake Before the device is ready to communicate on the network the endpoints must be configured The USB module has a surprisingly simple interface which is primarily concerned with handling the endpoint buffers 4 13 5 2 2 USB RAM The USB peripheral contains 512 bytes of RAM that may be allocated to the enabled endpoints to act as transmit and receive buffers The bu
194. nterface and can be switched between the EMI and general purpose IO The configuration of these ports is defined in the system control Emi register that contains one bit which defines the use of these ports After reset the these two ports default to the external memory interface if you are using the STR9 as a single chip device you must clear this bit before using any GPIO on ports 8 and 9 External Memory Interface T When the EMI is fully enabled the CHIPSELECT 0 chipselect registers define the behaviour of each of the four external 64Mbyte pages Each FESTER chipselect is controlled by six CHIPSELECT 1 separate registers CHIPSELECT 2 CHIPSELECT 3 When GPIO port 7 is used as an address port it must be configured as Alternate 2 output function with the GPIO output register SCU GPIOOUT7 Also depending on the EMI configuration the chipselects can appear on port 5 or port7 In either case the same output control registers must configure the relevant pins as Alternate 3 output function 15 14 13 12 11 10 9 B d 6 5 D a e 1 Pot Pn7T Bnp Poe Peds Pa Ped Ped Fraa Pan Poa Pa Pat Pn1 PnD Pop Dui Oui Oui CAO Out Gad Ouni Oui Gun Gu Oui Ged On OuiD Out Gu Each of the GPIO OUT registers allows each GPIO port pin to be defined as an input output or it may be connected to one of two alternate functions Hitex UK Ltd Page 55 hitex mum Chapter 3 System Peripherals D
195. nvert several channels one after the other In this mode you must select the channels you want to be converted in the control register SC field and then to enable the scan mode you must set the SCE bit Now when conversion is started by setting the STR bit the ADC will perform a conversion on each of the selected channels starting with the lowest number channel first As with single channel mode the end of conversion flag is set each time a channel conversion is completed Hitex UK Ltd Page 107 Chapter 4 User Peripherals ELDHP LU E Wl FTO GLS 4 8 2 3 Continuous Conversion The default configuration for the ADC is to perform a single channel or chain of scan mode conversions and then halt However by setting the CONT bit in the control register it is possible to enable the ADC to make continuous conversions in either single channel or scan modes 4 8 3 Analog Watchdogs The ADC has two analog threshold registers which may be set to a high and low threshold The result of an ADC conversion may be checked against one of these threshold registers The analog watchdog is configured by writing the high and low values to the threshold registers and enabling the selected channels in the channel configuration register Each ADC may be compared to either the low threshold register of the high threshold register but not both When a conversion result is out of range the AWD flag in the control register will be set and a flag will be set in the com
196. of the FLASH memory but we still loose performance every time the CPU executes a branch instruction To further increase the performance of the FLASH memory the instructions fetched from the burst FLASH are fed into a custom designed prefetch queue and branch cache COMPARE e Branch Cache BC CURRENT BRANCH ADDRESS BURST FLASH MEMORY ARM966E Pre Fetch Queue PFQ The prefetch queue is only effective for sequential code When the CPU branches the queue and the CPU pipeline must be refilled before execution can continue To minimise the impact of a program branch a local branch cache stores recently executed branch instructions Although a burst FLASH read is 128 bits wide the output of the burst FLASH interface is 32 bits wide This 32 bit bus is connected to the prefetch queue which in turn can buffer eight word wide instructions This queue ensures that at the full operating speed an instruction is always available to the I TCM and hence the ARMS at zero waitstate Since most applications will require the use of constants which are stored in the FLASH memory the prefetch queue has been designed to differentiate between program instructions and data constants stored in the FLASH memory When a constant is being fetched the CPU accesses the burst FLASH directly while the instructions in the prefetch queue if frozen until the next instruction is required This means that access to data constants in the FLASH incur the ful
197. of the motor to prevent overloading the windings iii A periodic interrupt that runs at rate that is equal to or some sub multiple of the PWM carrier frequency i e half qUARTer tenth etc iv Update of the three Phase Compare registers with the next sine value from the sine table with an offset equivalent to one third of a complete period The Repetition counter register controls the update of the Phase Compare registers with the latest values After a set number of PWM periods it causes each Phase Compare Preload register to load is contents into the corresponding Phase Compare register These transfers occur instantaneously and simultaneously at the end of a PWM period and is accompanied by the ADT interrupt request This prevents changes to the required duty ratio part way through a PWM period from upsetting the current PWM output state Such a transfer is called a coherent update and it is essential if 0 or 100 PWM is to be realisable The values placed in the Phase Compare Preload registers must be transferred by software from the sine wave value table by the ADT interrupt service routine In some applications the number of PWM periods between the compare register updates could be used to vary the sine output frequency and hence the motor speed 10 bit Preload Compare 0 Reg i 10 bit Compare 0 Reg CMO Int PM Counter Frescaler Reg D CMS bit FELIS o bit Prescaler p 10 bit PAM Counter a CEC bit 1 UU CMPU In A Int 11 bi
198. ol transaction recorded and decoded by Device to Host evice to Hos a USB bus analyser Standard Device Get descriptor Descriptor index Device descriptor Index Descriptor length Hitex UK Ltd Page 149 Chapter 4 User Peripherals ELOP Bj EF M TOQdLt CR Lu setup ADDR EP Ox00 0 00 MIDATAO DATA 8 80 06 00 01 00 00 40 00 ACK The PC sends a setup packet to initiate the control transfer This is followed by a data packet which contains the command codes for the control action that the PC wants to carry out After a successful handshake packet the PC will send an IN packet and the USB device will return a data packet containing the requested information typically a descriptor So as a minimum the enumeration process will make the following requests Get the first eight bytes of the device descriptor When the device is first connected the PC will use the smallest packet size possible to communicate with endpoint zero This will load the vendor and product ID along with the maximum packet size for endpoint zero For all further transfers the PC can now adjust its data packet size to the maximum supported by endpoint zero thus reducing the number of transfers required to complete the enumeration process Reset the node Once the connection to endpoint zero has been optimised the PC will issue a reset command to the new node to ensure it is in a known state Assign a network address Since all new devices appe
199. on to successfully communicate with other 12C devices on the network Hitex UK Ltd Page 119 hitex mum DEVELOPMENT TO OLE Chapter 4 User Peripherals Dn Status z The I2C module is controlled by 7 registers but has two Ck Carnet interrupt channels One interrupt is used for data handling the other for control and error containment Uer hihi 2 After a reset the I2C peripheral is disabled To configure the peripheral you must first set the bit rate by programming the clock control registers The clock control register and extended clock control register contain a 12 bit prescaler which is used to divide the APB1 clock to give the desired clock rate In addition the clock control register allows you to select either standard DC mode or Fast DC mode If you plan to run the bus faster than 100Kb sec you should select fast mode Once the bit rate has been set the peripheral can be enabled by writing to the PE bit in the control register You must write twice to the PE bit in order to enable the I2C peripheral As the I2C peripheral has to respond to every event on the bus it is generally best make this device interrupt driven Internally each DC peripheral has eleven interrupt sources These are split into the two categories of Bus events and data Transfer Each group of interrupts has an interrupt channel connected to the EIC The interrupts are enabled by setting the ITE bit in the control register This bit enables
200. or these interrupt handling methods in turn E F0 ep Each VIC provides three levels of E ER interrupt service and on chip interrupt li dna VIC vy wed n TE sources may be allocated into each m group Non eei LE 3 8 10 FIQ Interrupt Any interrupt source may be assigned as the FIQ interrupt Within each VIC the Interrupt Select Register has a unique bit for each interrupt Setting this bit connects the selected channel to the FIQ interrupt In an ideal system we will only have one FIQ interrupt However setting multiple bits in the Interrupt Select Register will enable multiple FIQ interrupt sources If this is the case on entry the interrupt source can be determined by examining the VIC FIQ Status register and the appropriate code executed Clearly having several FIQ sources slows entry into the ISR code Once you have selected an FIQ source the interrupt can be enabled in the VIC interrupt enable register As well as configuring the VIC the peripheral generating the interrupt must be configured and its own interrupt registers enabled Once an FIQ interrupt is generated the processor will change to FIQ mode and vector to 0x0000001C the FIQ vector You must place a jump to your ISR routine at this location in order to serve the interrupt 3 8 11 Leaving An FIQ Interrupt As we have seen declaring a C function as an FIQ interrupt will make the compiler use the correct return instructions to resume execution of the
201. oupled memories TCM The TCMs are fast pages of SRAM located within the CPU core which can hold pages of data and instructions that can be accessed very quickly by the CPU greatly improving its performance The E in ARM966E S stands for Enhanced instruction set In addition to the standard ARM instruction set the ARM966E S has some additional instructions aimed to improve the performance of the CPU for DSP applications Finally the S means that the CPU has a synthesisable hardware design which allows it to be transferred between different silicon manufacturing technologies This allows the STR9 family to take advantage of future improvements in manufacturing processes In essence the STR9 uses relatively simple implementation of the ARM9 CPU By keeping the complexity of the CPU low the STRO9 is an easy to use high performance low cost general purpose microcontroller which is suitable for a wide range of real time embedded applications 1 3 CPU architecture Since the ARM CPUs are reduced instruction set computers RISC they have a small instruction set when compared to a complex instruction set CISC computer Generally a RISC CPU will have to execute more instructions than a CISC computer to achieve the same result Consequently the maximum operating frequency of an ARM microcontroller is a key indicator to its performance and although you may have a simple application which may be running on an existing CISC microcontroller with a RISC machine you wil
202. own 3 Run the code and press the S1 button on the evaluation board This will generate a FIQ interrupt via EXTINT4 Port 3 4 and the debugger will stop at the breakpoint 4 Open the view SFR ARM CPU registers window and confirm the CPU is in FIQ mode Mode FIO State APM w Flags nzCv TEQ Disable FIQ Disable 5 Remove the breakpoint run the program at full speed and observe the value on the LED array incrementing every time you press the INT button O Hitex UK Ltd Page 184 hitex mm Chapter 5 Tutorial Exercises DEWVELOHP s EM d m Wal D 5 10 Exercise 8 Memory to Memory DMA transfer This exercise demonstrates configuration of the DMA unit to perform a memory to memory DMA transfer For a block of memory The CPU is then used to repeat the copy so we can see how much faster the DMA unit is 1 Openthe HITOP project in the STR912FExamples DMA directory 2 Run the DMA copy routine the routine will switch on the led at the start of the copy and a second when it finishes 3 Next run the CPU copy routine which repeats the same process but uses the CPU in place of the DMA unit The speed difference between the DMA and CPU routines should be about a factor of four O Hitex UK Ltd Page 185 Chapter 5 Tutorial Exercises hitex DEVELOPMENT TOO 5 11 Exercise 9 FLASH Programming This program demonstrates the basic erase and write routines required to store program code or cons
203. p That is you can single step lines of code run halt and set breakpoints and also view variables and VCC 3 3 VOC 3 3 2 4 5 8 10 12 14 16 18 20 memory locations once the code is halted The JTAG connects to the target through a special debug port which must be added to your target hardware The JTAG socket has a standard layout which is common to all ARM9 based devices The JTAG is brought out of the STR9 by six GPIO pins as secondary functions This means that when you are using the JTAG these pins will be unavailable for your application TEET JUUUU vg GR It is also worth noting that the even pins on the JTAG connector are mostly ground connections This means that if you accidentally plug your JTAG debugger in back to front you will pull all of the signal lines to ground and possibly damage the Tantino For this reason the evaluation board is fitted with a polarised socket to prevent this mishap If you are designing your own hardware it is recommended that you fit the same style of socket rather than just a bare header Hitex UK Ltd Page 39 hitex mum Chapter 2 Software Development B EVELO FREIN DOS 2 14 Important As mentioned above the JTAG port is a simple serial debug connection to the ARMO device It is very important to understand its behaviour during reset If the ARM9 CPU is reset all of the peripherals including the JTAG are reset When this happens the Tantino debugger los
204. p Code 177 5 5 Exercise 3 Interworking ARM amp THUMB Instruction Sets 178 5 6 Exercise 4 Software Interrupt 180 5 7 X Exercise 5 Clock Configuration and Special Interrupt Mode 181 5 8 Exercise 6 IRO Intertupls zeree 182 59 Exercise 7 FIO Interrbl s editio oa Eoi du 184 5 10 Exercise 8 Memory to Memory DMA transfer 185 5 11 Exercise 9 FLASH Programming senseenensensseenrerrrensrrnrrreenn 186 5 12 Exercise 10 General Purpose IO GPIO 187 5 13 Exercise TT TO BIETAITIGES oie ai ha oc iia d menti 188 5 14 Exercise 12 Analog to Digital Converter 189 5 15 Exercise 13 Watchdog nnnnnnennnnennennnnnsnnnnnsennerenrrnrrensnnrerenne 190 5 16 Exercise ME UAR T ie nt trentaine eat 191 5 17 Exercise 15 I2C Using GPIO NN 192 5 18 Exercise 16 I2C Peripheral n00nnnnnn0annnnnnnnnnonennnnnnnennneosnnnerennne 193 5 19 Exercise 17 QUAIN a d doses oie iot tete EE 194 5 20 Exercise 18 Motor Drive Peripheral 196 0 21 Exercise 19 SSP aedi nn nina 197 5 22 Exercise 20 USB ws nn rs e mU D orte re 198 Bibliography 200 6 1 PUPIIGAHONS coe ette e ett E e detti oodd 200 627 Wep URE sc aD uU E aeris 200 Introduction This book is intended as a hands on guide for anyone planning to use the STR9 family of mi
205. pare V Reg 11 bit Preload Compare V Reg to 255 by the PWM 2 Counter Prescaler register CMPW Int j 11 bit Compare WW Reg Once running the 11 bit Preload Compare VV Reg PWM Counter counts from zero up to a maximum count Core PWM Generation Registers In MC Peripheral value set by the Compare 0 register It then immediately starts to counts down again to zero This process repeats forever or until software stops the PWM Counter Throughout the contents of the Compare Phase U V amp W registers are constantly compared with this counter When a value in a compare register matches the PWM counter and the count direction is up the corresponding PWM signal U V or W is set to zero If the count direction was down the PWM signal is set to one These compare events can optionally create an interrupt Hitex UK Ltd Page 96 ELI DO Par Chapter 4 User Peripherals hitex Counter MC CMPO MC CMPU MC CMPV MC CMPW 0000h Time ij Phase W Phase V LP Phase U oo Loans EE Zero Centred PWM Generation The time taken to complete one zero maxcount zero cycle determines the period of the PWM which then sets the carrier frequency As described above the resulting PWM signal waveform will be symmetrical around the maximum count position and is known as the Zero Centred mode Another mode Classical PWM mode has the PWM counter configured to count from zero to the maximum count an
206. pare results register to indicate the out of range channel 4 8 4 Interrupts In addition to the various flags in the control register the ADC has two internal interrupt sources which are connected to a single VIC channel The ADC can generate an interrupt when a conversion has completed or when an analog watchdog threshold is crossed The interrupt are enabled by setting the end of conversion interrupt ECVI and Analog Watchdog Interrupt AWDI bits in the control register 4 8 5 Power Management If you are not using the ADC it should be left in reset were it is fully powered down and consumes zero power The time taken to leave reset and start conversions is approximately 1 msec If the ADC has left reset mode it can also be placed in standby mode by setting the STB bit in the control register in this mode the ADC consumes far less power and when the STB bit is cleared it will resume conversion in 15 usec Exercise 12 Analog to Digital converter This exercise enables the ADC in single channel continuous mode and writes the conversion result to the bank of LEDs on the evaluation board O Hitex UK Ltd Page 108 hitex mum DEVELOPMENT TOOLE Chapter 4 User Peripherals 4 9 Watchdog In common with most microcontrollers the STR9 has an onboard watchdog that provides a hardware recovery mechanism in the event of the application software crashing or being disturbed by a hardware failure such as a power brownout WDG P
207. pecial function registers have buffered and non buffered address ranges and your application must select the appropriate address range for fast access or guaranteed data coherency depending on your requirements The only exception to this rule are the two vector interrupt controllers which can only be accessed as non buffered registers and are located at the top of the 4 Gbyte address range The external memory controller provides pages of external memory each with a 64MB address range Each page of memory can be arranged as 8 or 16 bit wide memory Each of the system peripherals and the high performance user peripherals Ethernet USB and DMA have a similar 64MB address range although their actual registers only occupy a fraction of this space Similarly the peripheral busses APBO and APB1 are each allocated a 64Mb addressing range with each peripheral having a dedicated 4k 3 4 2 On Chip FLASH The STR9 on chip FLASH is arranged in two banks off 32 bit wide memory which can be used to store code and data constants In addition bank 1 has 32 bytes of one time programmable memory OTP which can be programmed by JTAG programming tools The OTP is intended to hold user serial numbers Ethernet MAC addresses and other permanent calibration data The top two bytes of the OTP memory are factory programmed to contain the silicon revision number of the STR9 silicon Address Bus amp Z3 A JTAG Port E FMI Bus LVD Reset to CPU LV War
208. pports ARM THUMB interworking The next section in the script file defines the list of input object files that make up the complete project O Hitex UK Ltd Page 36 Chapter 2 Software Development GROUP objects startup o objects main o objects interrupt o objects THUMB o If you add any additional source modules to your project you must update this list in the LD manually Following the group section is the target memory layout MEMORY For STR9 FLASH execution IntCodeRAM rx ORIGIN 0x00000000 LENGTH 512K this is FLASH IntDataRAM rw ORIGIN 0x40000000 LENGTH 96k This section defines the size and location of the target memory The description above describes the memory configuration of an STR9 used as a single chip device with 512k of FLASH memory starting from address 0x0000000 and 96K of RAM starting from 0x40000000 The final user section describes how the application code should be laid out within the target memory SECTIONS The description of the application code is split into two basic sections text and data The text section contains the executable code and the code constants basically anything that should be located in the FLASH memory The data section allocates all of your volatile variables into the user RAM text __code start objects startup o text Startup code objects ico text ALIGN 4 code end glue 7t glue 7 gt IntCodeRAM U
209. quence checksum that provides Data Field error detection and Each message Data Length Code Correction across the ict a reserved bit D message packet checksum an Ge D RTR bit D Identifier Field Start of Frame Hitex UK Ltd Page 137 Chapter 4 User Peripherals hitex mum DEVELOFBSATFENTTOCLE Once a node has won arbitration it will start to write its message onto the bus As during arbitration as each bit is written onto the bus the CAN controller is reading back the level written onto the bus As the node has won arbitration nothing else should be transmitting so each bit level written onto the bus must match the level read back If the wrong level is read back the transmitter generates an error frame and reschedules the message The message is sent in the next message slot but must still go through the arbitration process with any other scheduled message Standard 8 byte Data Frame Inter Frame Space Se E ge 0 Dominant Transmitting f tht f NN Standard 8 byte Data Frame Inter Frame Space ro 1 Recessive N Intermission Bit check error Once the arbitration has 1 Recessive finished the write and read nl dis back mechanism is use for Xo 0 Dominant bitwise error checking CRC is Intermission calculated using End of Frame all previous bits ACK Delimiter within the frame ACK Slot stuff bits are not CRC Delimiter included CRC Sequence Data Fiel
210. r Hitex UK Ltd Page 34 Chapter 2 Software Development If your code does encounter a memory error and ends up in one of these loops you can examine the contents of the Abort Link Register to determine the address 4 of the instruction which caused the error The SPSR will contain details of the operating mode which the CPU was in when the error occurred From here you can backtrack and also examine the contents of the stack immediately before the application program crashed So the CPU registers can produce some useful post mortem diagnostics if you know what you are looking for 2 9 Software Interrupt The Software Interrupt exception is a special case As we have seen it is possible to encode an integer into the unused portion of the SWI opcode define SoftwareInterrupt2 asm Swi 02 Now when we execute this line of code it will generate a software interrupt and switch the CPU into Supervisor mode and vector the PC to the SWI interrupt vector which will place the application into the SWI handler routine Once we enter this routine we need to determine what code to run It would be possible to read the contents of a global variable and then use a switch statement to run a specific function depending on the contents of the global However there is a more elegant method In the GCC compiler there is a register keyword that allows us to access a CPU register directly from C code The declaration below declares a pointer to the link reg
211. r Handling Error conditions within the STR9 Can controller are reported in the status register 15 14 13 12 11 Un g B 7 B8 an E p a a The status register contains the error warning flags and a Last error code that details the last fault that occurred on the CAN bus This register contains flags for bus off and error passive conditions as well as an early warning error limit which is set when the error counters reach a count of 96 In addition to the error flags there is a last error code field which reports the type of error condition that was last encountered In addition the error counter register allows you to read the current values held in the transmit and receive error counters Hitex UK Ltd Page 139 Chapter 4 User Peripherals hitex DEWVELUDHP s EM TOQdLt 4 13 4 5 CAN Test Modes The test register within the CAN module allows the module to be configured into a number of special modes However before you can write to this register you must set the test bit in the CAN control register The loopback mode can be used for self test routines As its name implies in this mode the TX pin is internally connected to the RX pin so the CAN module receives its own message This allows you to check the integrity of the Can controller The test register can set the CAN controller into loopback mode and is also able to manually control the TX pin and read the RX pin for physical layer testing The silent mode prevents the
212. r Master mode by writing to the start bit in the control register This places a start condition on the bus and places the STHR9 in the role of bus master until the end of the transaction when a stop condition is generated by setting the stop bit in the control register Once the transaction has ended the DC peripheral will revert back to a slave device This is intended to allow another network device to act as a master an initiate a bus transaction The same interrupt framework can be used in master mode you simply need to respond to the additional combination of status bits In master mode the background code must write to the control register to send the start bit and place the 12C peripheral into master mode I2CO CR 0x08 7 Send start bit Hitex UK Ltd Page 122 ELOHP LE I Wl FTO OL Chapter 4 User Peripherals Once the start bit has been sent an ITERR interrupt will be generated This interrupt is used to send the node address you wish to send data too and then send the first byte of data void I2CO ITERR isr void SWITCH IRQ TO SYS switch tx state case 0 while I2CO SRI amp 0x81 wait for bit Start condition to be sent I2CO DR 0x04 tx state 1 break Case 1 while I2CO SR2 amp 0x20 wait for address to be sent I2C0 CR 0x20 Write to Control register I2CO0 DR OxAA Send data tx state 2 break default break Once the start bit has been sent an ITERR in
213. r in a DMA chain should enable the DMA interrupt in the control register so that after the last transfer an interrupt can be generated and a new set of DMA transfers can be initialised 3 10 Conclusion This is an important chapter you must be familiar with the system architecture of the STR9 in order to use it successfully There are many configuration registers that have a fundamental effect on the performance of the STR9 and these must all be fully understood O Hitex UK Ltd Page 79 Chapter 4 User Peripherals Hitex UK Ltd Page 80 hitex mum Chapter 4 User Peripherals DEVELOPMENT TOOLS 4 Chapter 4 User Peripherals 4 1 Outline This chapter presents each of the user peripherals in turn The examples show how to configure and operate each peripheral By working through each peripheral in turn you will gain a good insight into the capabilities of the STR9 The example programs can be used as the basis for more complex programs or additionally there is a driver library available from the ST Microelectronics website 4 2 General Purpose Peripherals As we have seen in Chapter 3 all the user peripherals are located on the Advanced high speed bus and the advanced peripheral bus APB Before reaching the peripherals the system clock passes through the BEETS FROM up E USAT ih IN nam D F configuration registers peripheral control registers After reset these registers disable the individual clocks to eac
214. rals With A Choice Of IO Pins eussssssee 85 4 4 Synchronous Peripheral Controller 86 45 une GOUMICTS EE 90 4 5 1 Input Capture ins 92 452 PWMunput Gap Us nn uen te detecte 92 4 5 3 Output Compare ire 93 4 54 PAV MOU DU le EE 93 4 5 5 One Pulse ModE i e eee 94 ASO EIERE 94 4 6 The MC 3 Phase Induction Motor Controller 96 453 Basic Moon Ee tte ARS nu utto e dt 96 4 6 2 Adding The Deadtime COiteet 98 4 6 3 Applying Sine Wave Modulation nnneennnnnnneennnnneneesrrnn renren 99 4 6 4 Tacho Generator Speed Feedback ssseesuuuss 101 4 6 5 Emergency Stop For Fault Protection 101 Af Real MECOK e 102 4 7 1 Calibration Output 103 4 72 Seund The Rn t acai ivadestce eee costae eee 103 4 7 3 Seting THE Alarm iesen art e e eene e 104 A 7A CIE EES eebe 104 e DE Tamper ie ET d e ete ei 104 4 8 Analog to Digital Converter 106 4 8 1 Ee 110 0 LE e WE 106 4 0 0 2ODVersIOImMOOBS cs orco c en a ar at det reu rra nn RS 107 4982 Single Ghatltiel E 107 48 22 SOS Mode EE 107 4 8 2 3 CONTINUOUS Conversion 108 4 8 3 Analog Watchdogs tt 108 ASA MMCMUDTS mr S 108 4 8 5 Power Management 108 AsO NVANGINGOG EE 109 4 10 Communications Peripherals nnnsssnoeennnnneennnnnnrneeesernrnrneeenee 111 AT WAR pm EE a 112 AAA 2d UART IrDA A MOGS intet iioc eios baie etos iiec eiae
215. rame in the CAN protocol is simply six dominant bits in a row This allows any CAN controller to assert an error onto the bus as soon as the error is detected without having to wait until the end of a message Reset and Configuration l Error counters Error Active The CAN controller moves between a number of error states that allow a node le NM i eset Configuration ege deeg and Reception of to fail in an elegant fashion without IEC gt ER REC lt 127 amp 128 x 11 recessive bits e TEC lt 27 blocking the bus n un TEC gt 255 Error Passive i Bus On il REC Recessive Error Counter TEC Transmit Error Counter Internally each CAN controller has two counters a receive error counter and a transmit error counter These counters will count up when receiving or transmitting an error frame If either counter reaches 128 then the CAN controller will enter an error passive mode In this mode it still responds to error frames but if it generates an error frame it writes recessive bits in place of dominant bits If the transmit error counter reaches 255 then the CAN controller will go into a bus off condition and take no further part in CAN communication The CPU must intervene to reinitialise the controller and put it back onto the bus Both these mechanisms are to ensure that if a node goes faulty it will fail gracefully and not block the bus by continually generating error frames 4 13 4 4 CAN Bus Erro
216. re do ee gom EX Eemer HS LI ER m EE mem mmm eme mmm mr mme Em e pr r ipsia eium tante NA P dees o LE ees Van Ze po Cnr pi io E magum HB Fee FREE nume a ai Day Cie im arid Ju 9 a prenant mil EE Bierg bundle ba a bation wih Pie aen about Saa dear nh ranura feta Sr dance Fur Zeen E dic RE E ee Daedfregnarmae laa Zei mn Diu repart kn Pus amem RS PL EEE Fam s l est MEET Fort ful ener Hitex UK Ltd Page 156 Chapter 4 User Peripherals A full HID programming tutorial is given the book USB Complete by Jan Axelson This is recommended reading if you are just starting out with USB As a brief outline the application software has to find out how many HID drivers are active within Windows then interrogate each one until it discovers the driver associated with your USB peripheral This is done by locating the driver with your vendor and product ID Once the driver is found we can read its capabilities and this will give the report structure to the application Finally we can use read file and write file to transfer our application data A complete client example is included with the MCBSTRS9 evaluation software and all the necessary API function calls are encapsulated into six C functions that you may easily use in your own application Exercise 20 USB This exercise configures the STR9 as a simple human interface device for a PC Hitex UK Ltd Page 157
217. re Exercise 4 Software Interrupt The SWI support in the GCC compiler is demonstrated in this example You can easily partition code to run in either the User mode or in Supervisor mode Hitex UK Ltd Page 35 m E LOPA EN DOS Chapter 2 Software Development 2 10 In Line Functions It is also possible to increase the performance of your code by inlining your functions The inline keyword can be applied to any function as shown below inline void NoSubroutine void When the inline keyword is used the function will not be coded as a subroutine but the function code will be inserted at the point where the function is called each time it is called This removes the prologue and epilogue code which is necessary for a subroutine making its execution time faster However you are duplicating the function every time it is called so it is expensive in terms of your FLASH memory The compiler will not inline functions unless you have set the optimiser to its O2 level 2 10 1 Inline Assembler The compiler also allows you to use ARM or THUMB Assembler instructions within a C file This can be done as shown below asm mov r15 r2 ye This can be useful if you need to use features that are not supported by the C language for example the MRS and MSR instructions as in these macros switch to SYS mode and enabled interrupts define SWITCH IRQ TO SYS asm msr CPSR_c 0x1F Mn stmfd sp lr s
218. rksheet for each exercise which steps you through an important aspect of the STRS9 All of the exercises are based on the Hitex STR91x evaluation kit which comes with an STR9 evaluation board and a JTAG debugger as well as the GCC ARM compiler toolchain It is hoped that by reading the book and doing the exercises you will quickly become familiar with the STR91x family of microcontrollers KELLER SA I H ET e 1 c S PS 23 Chapter 1 The ARM9 CPU Core hitex im O Hitex UK Ltd Page 7 ELOPMENT TOOLS Chapter 1 The ARM9 CPU Core hitex mum 1 Chapter 1 The ARM9 CPU Core 1 1 Outline The CPU at the heart of the STR9 family is an ARMY You do not need to be an expert in ARMY programming to use the STR9 as many of the complexities are taken care of by the C compiler You do need to have a basic understanding of how the CPU is working and its unique features in order to produce a reliable design In this chapter we will look at the key features of the ARM9 core along with its programmers model and we will also discuss the instruction set used to program it This is intended to give you a good feel for the CPU used in the STR9 family For a more detailed discussion of the ARM processors please refer to the books listed in the bibliography The key philosophy behind the ARM design is simplicity The ARMO9 is a RISC computer with a small instruction set and consequently a small gate count This makes it ideal for embedded systems It
219. ro py NRZ inverted encoding scheme This means that the logic D level on the USB network will change state every time it see a logic zero in the datastream This allows remote nodes to extract the data and a clock signal with which to GND synchronise themselves Because the physical layer of the USB network is heavily defined you will not generally need to examine the physical layer signals USB debugging is generally concerned with observing transactions at the data packet level However there is some necessary jargon to be aware of when discussing the bit level signalling on the USB network On a full speed USB cable a logic one is 5v and is called a K state and a Logic zero is 0 V and is called a J state To keep you on your toes the signalling voltages are inverted for low speed communication VEus Lit js GND The physical data signalling is encoded as a non return to zero inverted data stream The physical USB network is implemented as a tiered star network The USB root node must be a PC or other bus master and this provides one attachment port for an external USB peripheral If more than one peripheral is required you can connect a hub to the root port and the hub will provide additional connection ports For large numbers of USB peripherals further hubs may be added in order to provide additional ports for peripherals The USB network can support up to 127 external nodes hubs and devices and six tiers of hubs and requires
220. rol unit status register contains two flags which are set after a watchdog WDG_RST or low voltage detect reset LVD RST 3 8 4 Software reset In addition to the hardware resets the System control unit contains a peripheral reset register that allows the application code to force a reset on all or selected peripherals When the reset bit for a selected peripheral is held Hitex UK Ltd Page 59 Chapter 3 System Peripherals low the peripheral will be held in reset Once the bit is set the peripheral is released and will start to run The default setting for this register is to hold all the peripherals in reset until the application firmware programs this register Thus none of the on chip user peripherals will work until their reset bit is cleared in this register Also the following system peripherals are also held in reset Ethernet MAC USB DMA and interrupt structure In addition to releasing the peripherals from reset you must enable the peripheral clock through the peripheral clock gating registers see below Hitex UK Ltd Page 60 WE L O PA EN Chapter 3 System Peripherals ols a FS 3 8 5 Clocks The STR9 has two main external oscillators The first is the CPU oscillator that is an external crystal between four and 25 MHz The CPU oscillator signal may also be used to provide the Ethernet PHY chip clock this should only be used when a 25MHz oscillator is used XTAL 1 XTAL2 SE pe de STR91xF d TAMPER IN
221. rolier Deer PHI S YS OPEN HASTA EHLILEYSI Correct gen Hrntane The Windows driver model allows your application software to use a class driver This is a USB device driver written to support a generic class of devices such as audio devices printers mass storage devices or you may provide your own If you want to use your own driver this means writing a kernel mode device driver If you know how to do this then fine If not it would involve learning a lot about the Windows operating system There are a number of ready made general purpose device drivers that require no development work other than filling in your Vendor and Product ID s You can download an evaluation version of such a driver from www thesycon com If your USB peripheral can take advantage of one of the Windows class drivers then you can save yourself the trouble and expense of developing your own driver The two most interesting class drivers in Windows are the Human interface device HID class and the Mass Storage class As its name implies the HID class is the driver used by USB keyboards mice joysticks etc However you can also make use of the HID driver to send and receive basic IO data such as front panel data reading switches illuminating LEDs and so on or communicating with remote sensors The second class is the Mass Storage class which allows the USB device to appear as a removable drive Thus the HID driver gives a basic bidirectional connection between the PC an
222. rrent count of the watchdog timer Exercise 13 Watchdog This exercise configures the watchdog as a periodic timer and enables the end of count interrupt Each interrupt is used to toggle the bank of LED s on the evaluation board Hitex UK Ltd Page 110 hitex mm Chapter 4 User Peripherals DEWVELOHP s EM d m Wal D 4 10 Communications Peripherals The STR9 has a very large number of serial communications interfaces comprising 3 UARTS with IrDA option 2 fast DC interfaces 2 synchronous interfaces for SPI SSI or Microwire use full speed USB slave device CAN and 10 100 Ethernet not covered here Hitex UK Ltd Page 111 hitex mm B EVELOPMENT TOOLE Chapter 4 User Peripherals 4 11 UART Most small microcontrollers have al least one UART and some two However the STR9 has three UARTS as On the evaluation board UARTO is brought out to a 9 way D type with RS232 driver peripherals each with DMA support As well as supporting RS232 serial communication each UART has an additional IrDA mode to low cost infrared data interconnection Additionally UARTO has a full modem interface UART IO pins may be allocated as shown in the table below GPIO Mode Alternate In 1 Alternate Out 2 Alternate Out 3 Default Input Pin 0 UART1 TX UARTO CTS Pin 1 sf X X UARTO DSR Pin 2 X UARTO TX UARTO DCD Pin 3 UART2 RX X UARTO RI Pin 4 X X X Pin 5 X X X Pin 6 X X X Pin 7 X X X GPIO Mode Alterna
223. rrent device interface Sets the desired device interface returns the frame number from a given endpoint Page 150 hitex mum DEVELOPMENT TOGOLE Chapter 4 User Peripherals 4 13 5 2 USB Peripheral Now that we have some understanding of the USB network and its protocols we can have a look at the USB peripheral within the STR9 Like all the other STR9 communications peripherals the USB peripheral is located on the AHB Analog Transceiver Il tt E Clock Recovery Suspend Control Timer See Endpoint USB Clock SIE Selection The STR9 USB module is a USB 2 0 full speed module with integral transceiver and packet memory Endpoint Registers Facket Buffer Endpoint Interface Registers AHB Interface Facket Interrupt Arbiter Buffer Mapper Memory Sys Ck AHB bus Interrupt lines The USB peripheral contains the USB physical layer and the USB protocol engine which supports up to eight endpoints which may be double buffered The USB peripheral requires a 48MHz clock frequency which can be derived from the internal PLL or a dedicated external clock signal For maximum sustained performance the USB peripheral may be a flow controller to the general purpose DMA units USB Mode Transfer Direction Bandwidth Performance 12Mbps USB Mode Transfer Direction Bandwidth Performance 12Mbps CPU Single Buffer 4 19Mbps 34 196 DMA Unlinked 5 59Mbps CPU Single Buffer 4 51Mbps 37 5 DMA U
224. rrupts on VICO 0 Service IRQ Simple function that uses the watchdog timer to generate a periodic interrupt void Watchdog IRO isr void attribute interrupt IRO JS void Watchdog IRQ isr void WDG gt SR amp 0x00000001 Clear the Watchdog End of count flag VICO VAiR 0 0 Dummy write to clear interrupt pending O Hitex UK Ltd Page 70 hitex mum DEVELOPMENT TO OLE Chapter 3 System Peripherals 3 8 14 Non Vectored Interrupts Each VIC is capable of handling 16 peripherals as vectored interrupts and at least one as an FIQ interrupt So two units can serve a maximum of 34 interrupt sources on the chip any extra interrupts can be serviced as non vectored interrupts As there are currently a maximum of 31 interrupt sources this mode need not be used However if can be useful if you The non vectored interrupt sources are served by a single ISR The address of this ISR is stored in an additional vector address register called the default vector address register If an interrupt is enabled in the VIC and is not configured as an FIQ or does not have a vectored interrupt slot associated with it then it will act as a non vectored interrupt When such an interrupt is asserted the address in the default vector address is loaded into the vector address register causing the processor to jump to this routine On entry the CPU must read the IRQ status register to see which of the non vectored interrupt sources has g
225. rupt line to be disabled If you need to have nested IRQ interrupts your code must manually re enable the IRQ interrupt and push the link register onto the stack in order to preserve the original return address From the exception interrupt vector your code will jump to the exception ISR The first thing your code must do is to preserve any of the registers RO R12 that the ISR will use by pushing them onto the IRQ stack Once this is done you can begin processing the exception WI nc oo Ld F il link Fraser When an exception occurs the CPU will change Save COPAR imi modes and jump to the associated interrupt We cep vector al el kl a i n dl 2 al lm 1 Once your code has finished processing the exception it must return back to the user mode and continue where it left off However the ARM instruction set does not contain a return or return from interrupt instruction so manipulating the PC must be done by regular instructions The situation is further complicated by there being a number of different return cases First of all consider the SWI instruction In this case the SWI instruction is executed the address of the next instruction to be executed is stored in the Link register and the exception is processed In order to return from the exception all that is necessary is to move the contents of the link register into the PC and processing can continue However in order to make the CPU switch modes ba
226. s Cara n APO K lis card jetra Ce disabled E Update aires 7 ni med d rmm vele cetur E UT Dean 3D Proeertor Sern E peu d Brea iri m Hurt E Late T E aen Clock Le death Tapa Softee E musl Heed enabled E Merry i This does not use the hardware breakpoint registers and enables you to set more than two breakpoints Setting the while running option allows you to set and clear a breakpoint without halting the code This can be extremely useful when you are debugging a complex real time application The condition sensitive breakpoint option allows you to set a breakpoint on an ARM instruction that is conditionally executed If this option is enabled the code will only halt when the instruction s condition codes match the CPSR Again this is extremely useful when debugging real ARM code The JTAG hardware is limited to two hardware breakpoints If you are debugging from RAM you can set multiple breakpoints and the HITOP will use software breakpoints This technique can be extended to code which is being debugged out of FLASH by enabling the Breakpoints in FLASH option This will reprogram the FLASH with software breakpoints prior to starting the code running This is slower but allows you to set as many breakpoints as you want The remaining processor and target options are specific to the STR7 and will not generally need to be changed Hitex UK Ltd Page 174 hitex m Chapter 5 Tutorial Exercises DEVELOPMENT TO
227. s in this chapter will concentrate on demonstrating how to use the unique features of the ARMO discussed in the first chapter Since the ARMS is rapidly becoming an industry standard CPU for general purpose microcontrollers this will allow you to develop code on the STR9 and a number of other microcontrollers Hitex UK Ltd Page 27 FELOPMEHT TOOLE Chapter 2 Software Development 2 2 The Development Tools The CD that comes with the STRO starter kit includes an evaluation toolchain for the STR9 This is complete with a number of example programs demonstrating all the major features of the STR9 microcontroller By reading through the book and running the exercises you will be able to very quickly familiarise yourself with the essential features of the STR9 All of these exercises are detailed in Chapter 5 Once you have read the theory section and reached an exercise turn to the Exercise Worksheet in Chapter 5 and follow the instructions The exercises expand on the basic theory and give you a practical handle on the operation of the STRO9 Exercise 1 Installing The Software Turn to the tutorial chapter and follow the instructions in Exercise 1 which describe setting up the software and hardware toolchain that we will use for the practical examples in this book 2 2 1 HiTOP Debugger amp IDE HiTOP is the front end for all Hitex debuggers and in circuit emulators In the case of the STR9 HiTOP connects the Tantino 7 9 JTAG deb
228. s with the master generating a start condition followed by the address of the node which is to be the destination of the message data The I2C protocol uses a 7 bit address which supports a network of 127 nodes and one global General call address The eighth bit is used to signal a read or write request to the selected device Once the master has sent the start condition and the address byte the slave device will send a handshake in the form of an acknowledge In the case of an error a NotAcknowledge will be sent and the master will start again Once the slave has been selected and the direction of data transfer has been established the actual data transfer will take place with each byte being acknowledged by the receiving node Finally the master will end the transaction by placing a stop condition on the bus Data Register dE SDA Data Control se Data Shift Register Comparator Own Address Registers 1 amp 2 The STR9 contains two DC peripherals wit internal baud rate generators which support master and slave mode SCL Clock Control Clock Control Register Ext Clock Control Register Control Register Status Registers 1 amp 2 Control Logic Interrupt The STR9 I2C peripheral may be thought of as an 12C engine in that it can generate the clock and data signals to send and receive data and also generate the start stop and handshake signals Your software is responsible for managing the data content of the 12C transacti
229. s would be in the order of 0 5us to 5us for typical MOSFET and IGBT bridges The deadtime offset is inserted by the N value placed in the Deadtime Generator register MC DTG and is expressed in units of PCLK periods i e the basic count unit of time used for the PWM Counter register Here the h signal is similar to the input received from the Phase Compare registers but the on edge is delayed by 2 x N x PCLK Period The signal is the inverse of the input except that its rising edge is delayed by the deadtime period The minimum deadtime offset is zero N 0 and the maximum is 63 PCLK N 63 If a deadtime offset is set that is greater than the on time of the PWM output then the output remains off Deadtime Offset E een RS en ee pu LZ Ze Deadtime Offset Input Signal PWM Preventing Half Bridge Short Circuits At Switch on With Deadtime Hitex UK Ltd Page 98 Chapter 4 User Peripherals 4 6 3 Applying Sine Wave Modulation The MC peripheral provides a means to produce 3 pulse width modulated signals with the complementary signals for driving half bridges However this in itself is not enough to drive a motor The three sine waves with their 120 degree phase shift have to be created via software There are a minimum of four software elements required i A table of integer values that represent a complete sine waveform period ii A means of varying the sine amplitude in proportion to the speed
230. ser Peripherals ELOP Bj EF M TOQdLt CR Lu 4 12 2 Slave Mode After reset the STR9 I2C peripherals will be in slave mode and if you intend to make the STR9 a slave device an unique network address must be programmed into own address register Here you can set the local 7 bit address or if you are using 10 bit addressing the additional address bits are placed in the own address register 2 Once the DC peripheral is fully configured it will wait for a master device to start a transaction As soon as the master has placed the start condition on the bus and written the node address of the STR9 onto the bus the STRO9 peripheral will respond with an acknowledge handshake and generate a bus event interrupt In this interrupt the STR9 can read the flags in the status registers d 6 9 4 3 2 1 0 r r r r r r r r Status register 1 contains many of the flags that are used for managing an I2C transaction Depending what part of the I2C transaction has been reached different combinations of the flags will be set and either the bus event or data transfer interrupt will be generated The data register is used to send and receive data directly into the I2C bus as data is received you can read it from this register or write to it when you need to send data When the ITE bit is set in the control register two interrupt channels are enabled to the EIC The ITERR channel will generate an interrupt when any flag in status register 2 is set and when the start bi
231. ster clock may be divided by two before it reaches the peripheral Frequency selection for the Usb and UART peripherals is again made in the clock control register with the BRSEL and USBSEL fields Each of the timer blocks has an optional 16 bit prescaler which can used to divide down the master clock by a 16 bit value defined by the application firmware The TIMxxSEL fields in the clock control register allow your firmware to select between the master clock external clock or master clock divided by the 16 bit prescaler Idf the prescaler is selected the 16 bit divide value must first be programmed into the system configuration registers 1 and 2 which default to 0x00000000 The remaining peripherals are located on the High speed and peripheral busses Each of these busses has its own clock which is derived from the CPU master clock after it has passed through the RCLK divider The resulting RCLK frequency is then passed through an additional divider for the AHB bus and a separate divider for the APB busses This allows the master clock frequency to be further divided by a factor of 1 2 4 or 8 for each of the busses These three dividers are again programmed by the RCLKDIV AHBDIV and APB div fields in the Clock control register The RCLK frequency is also used to clock the FLASH memory interface The FMI clock can be selected via the FMISEI field in t the clock control register to be the same frequency as RCLK or RCLK divided by two Generally for maximum perform
232. t 2 8 Interrupt Service Routines In addition to accessing the on chip peripherals your C code will have to service interrupt requests It is possible to convert a standard function into an ISR as shown below void fiqint void attribute ancerrupt FIO TOSETI 0x00FF0000 Set the LED pins EXTINT 0x00000002 Clear the peripheral interrupt flag The keyword X fiq defines the function as an fast interrupt request service routine and will use the correct return mechanism Other types of interrupt are supported by the keywords IRQ _ SWI and UNDEF As well as declaring a C function as an interrupt routine you must link the interrupt vector to the function Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI Addr LDR PC PAbt_Addr LDR PC DAbt_Addr NOP Reserved Vector LDR PC IRQ Agar LDR PC PC Ox0FFO Vector from VicVectAddr LDR PC RIQ Addr Reset Addr DD Reset Handler Undef Addr DD Undef Handler A SWI Addr DD SWI Handler A PAbt Addr DD PAbt Handler A DAbt Addr DD DAbt Handler A DD 0 Reserved Address IRQ Addr DD IRQ Handler A FIQ Addr DD FIQ Handler A The vector table is in two parts First there is the physical vector table which has a load register instruction LDR on each vector This loads the contents of a 32 bit wide memory location into the PC forcing a jump to any location within the processor s address space These values are held in the second half of the vector table or
233. t SB address match ADSL or 10 bit addressing flags ADD10 in status register 1 are also set The second interrupt channel will generate an interrupt when the Byte transfer finished flag in status register 1 is set This means that the handling of the DC receive is split over two interrupt routines The code below demonstrates the minimum handler you need to receive a single byte Hitex UK Ltd Page 121 Chapter 4 User Peripherals The ITERR routine waits for the I2C peripheral to be addressed and reading status register 1 clears the flags When the data has been sent the stop flag will trigger the ITERR interrupt which reads status register 2 and clears the flags void IZCl ITERR 1sr void unsigned int status SWITCH RO TO SYS if IZ2Cl SRI amp 0x84 node address detected if 12C1_SR2 amp 0x08 J atop bit detected SWITCH_SYS_TO_IRQ clear IRQ Pending bit EIC IPRO CHANNEL 8 Once the node has been addressed the next byte send will be interpreted as data and will trigger the TX_RX interrupt and the data can be read out from the data register void I2C1_IRQ isr void unsigned int dummy SWITCH_IRQ_TO_SYS while I2C1 SR1 amp 0x88 Wait for slave to detect data dummy I2C1_DR read the received data SWITCH SYS TO IRO ZC Clear IRO Pending bit EIC IPRO CHANNEL 16 4 12 3 I2C Master Mode After the I2C peripheral has been configured you can ente
234. t CHO i optet Rep NN rt Ne ir Modifying The Status Registers 0000nnnnn0annnneannnnnnennnnnonennennnne SOMwWale INST EE MAG Ne Es TENDUNT Ru hi D SPEXIENSIONSE E D m T THUMB Instruction Sli breton End buie taie SUR i ere DC Chapter 2 Software Development OGUN NEU ELEC T TEE Tne Developmient TOOlS geseet HITOP Debugger amp IDE otia gea e sedes pets Ten Kane UE SAUD COTES ue eebe The ARM Procedure Call Standard APCS Interworking ARM and THUMD URBI RETE A ETT Aecessing Periplierals divis ibt side as edt ud eda Interrupt Service Routines Sie H Aten UD EE In Line FUNCTIONS es 2 10 11Inline Assembler eese mmm meme 2 11 2 12 2 13 2 14 2 19 2 16 3 1 3 2 3 3 3 3 1 3 4 Biller ee GE Hardware Debugging Tools ccccccccssseeeeeeeeeeeeeeeeeeaeeeeessaeaeeeees MISO tcr ENS Embedded Trace Module lan un TEE Chapter 3 System Peripherals QE IAE PE BUS SUCU LE SR E Memory tte WING SBS TON eenegen eben Momo MaD nn a e Tavs 31 ON hip S HAM A ce 49 944 2 Once Ee 50 3 4 3 FLASH Memory Interface 51 23 44 BoolloadelSs ee 52 3 4 5 User Defined Bootloaders ccccccssssseeeeceeseeeeeseeeeeeeeeseeneeeessaas 52 3 4 6 Configuring The STR9 For User Defined Bootstrap Loaders 52 9 47 FLASH Programming ennuis ra eet net eoo oi eut 53 3 5 One Time Programmable OTP Memonm 53
235. t Compare U Reg gt 11 bit Preload Compare U Reg KI CAP Int QT Int 11 bit Compare Y Reg b CPT 0 11 bit Preload Compare V Reg o bit Repetition agunt Down Counter CME Int 11 bit Compare VY Reg gt S Bit Repetition 11 bit Preload Compare W Reg Counter Reg Repetition Register The Controls Update Of PWM Compare Registers To Apply Sine Modulation A typical drive would use a carrier frequency of around 24kHz to make the winding ringing super sonic and have 8 Hitex UK Ltd Page 99 Chapter 4 User Peripherals bits of PWM resolution i e the sine waveform is described to an accuracy of one part in 256 or 0 296 In fact when using the Zero Centred symmetrical PWM mode the acoustic noise is generated at double the carrier frequency so a 12kHz carrier would yield an inaudiable 24kHz ringing The PWM duty ratio update rate would be at 12kHz i e the same as the PWM period This gives the best waveform accuracy with the ARM9 CPU being easily able to cope with the loading The deadtime for a typical IGBT half bridge would be around 1 2us The calculations for the MC register settings would be PCLK 96MHz set in SCU CLKCNTR register GOU SCU CLKCNTR Val 0x00030000 Repetition Counter register MC REP N 0 Compare 0 Preload register MC CMPO 2 WM Pesoluton _ 256 PWM Counter Prescaler register MC CPRS 16 to give 11718 75Hz carrier as given by MC CPRS PCLK 2 2 Resolution p MC CPRS 96
236. t are not part of the main register bank Only two ARM instructions can operate on these registers directly The MSR and MRS instructions support moving the contents of the CPSR or SPSH to and from a selected register For example in order to disable the IRQ interrupts the contents of the CPSR must be moved to a register the I bit must be set by ANDing the contents with 0x00000080 to disable the interrupt and then the CPSR must be reprogrammed with the new value LES A CSPR SPHR The CPSR and SPSR are not memory mapped or part of the central register file The only instructions A which operate on them are the MSR and MRS instructions These instructions are disabled when E the CPU is in USER mode CSPA SFA The MSR and MRS instructions will work in all processor modes except the USER mode So it is only possible to change the operating mode of the process or to enable or disable interrupts from a privileged mode Once you have entered the USER mode you cannot leave it except through an exception reset FIQ IRQ or SWI instruction Hitex UK Ltd Page 20 Chapter 1 The ARM9 CPU Core hi 1 10 Software Interrupt The Software Interrupt Instruction generates an exception on execution forces the processor into Supervisor mode and jumps the PC to 0x00000008 As with all other ARM instructions the SWI instruction contains the condition execution codes in the top four bits followed by the op code The remainder of the instruc
237. ta abort exception the return instruction iS SUBS R15 R14 8 Once the return instruction has been executed the modified contents of the link register are moved into the PC the user mode is restored and the SPSR is restored to the CPSR Also in the case of the FIQ or IRQ exceptions Hitex UK Ltd Page 14 Chapter 1 The ARM9 CPU Core hitex m DEVELOPMENT TOOLS the relevant interrupt is enabled This exits the privileged mode and returns to the user code ready to continue processing Li H Res Pal is ageicwm foi Ine Hitex UK Ltd Page 15 DEVELOPMENT TOOL Chapter 1 The ARM9 CPU Core hitex 1 7 ARMO Instruction Set Now that we have an idea of the ARMO architecture programmers model and operating modes we need to take a look at its instruction set or rather sets Since all our programming examples are written in C there is no need to be an expert ARM9 assembly programmer However an understanding of the underlying machine code is very important in developing efficient programs Before we start our overview of the ARMO instructions it is important to set out a few technicalities The ARM9 CPU has two instruction sets the ARM instruction set which has 32 bit wide instructions and the THUMB instruction set which has 16 bit wide instructions In the following section the use of the word ARM means the 32 bit instruction set and ARMS refers to the CPU The ARMS is designed to operate as a big endian
238. tants into the STR9 FLASH memory 1 Open Hop project in STR910FExamples FLASH FLASH HTP entering the serial number of your Tantino when asked Run the code to main and set the memory window to 0x00080000 the base of FLASH bank 1 Memory Mem Address Data FEDER x n aggsugzu Dat a d OS O3 Ox naggsuatn Dan adest Dx nagsgstn Dc a d OS UO 7 D Dn susti Dac d d d S 030 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF EEERFBEER FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF BEEEBEBREE FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FEFFFFEFFE FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF Hitex UK Ltd Locals Wakchl1 Mem Wwakchz Set a breakpoint on the second call to the SRAM erase FLASH func function ff ERASE sector d at OxS000 again HE PUT YOUR Er ee ON THE NEET LINE SPAM erase ELASH funci Oxi FLASH OR error status if error status d Run the code until it hits the breakpoint Check in the memory window that the FLASH has been updated with the new pattern Memory Mem Address Data EE FFFFFFFF FFFFFFFF FF Leah wh mach ah T TOITITITITITIT IT TT Das ad OS Ud UO ra Fa aw ra nn eege Run the erase FLASH function a second time and check that the contents of the FLA
239. tchdog Timer WDG J Wake Up System wU J Advanced Peripheral Bus Bridge APB J Extended Function Timers EFT A Standard Timer STIM J Inter Integrated Circuit I2C J Controller Area Network CANO J Controller Area Network CAN1 J Controller Area Network CAN2 C Pulse width Modulator PWM J Serial Communication UART 0 3 J General Purpose IO Ports GPIO J Embedded Trace Macrocell ETM J Info E H H Ee Ee Ee E Ee Ee Ed Ee Ee Ed Re E Ee Ee Ed Rd View Project Debug RTOS i j HM Load screen layout I d eR Save screen layout r LE r L Hitex UK Ltd Source Editor Options Page 172 J Buffered Serial Peripheral Interface BSPI PC 00000Z2 C CPSR 60000010 Mode d lt SE State APM N a E LS Flags IRQ Enable Vv L E FIQ Enable e R08 FFFFFFFF FIQ Disable v ROS FFFFFFFF IRQ Disable v R10 State Thumb v USE SYS FIQ Mode RO6 spsn rooooorr R07 Flags NZCV wei Rll FFFFFFFF Mode sys v f Chapter 5 Tutorial Exercises 5 3 1 4 HITOP Project Settings Once you are familiar with the basic features of HITOP you may want to modify the project settings to begin work on your own project You can change the project settings within HITOP via the Project settings menu Project Debug RTOS Syst New Open
240. te In 1 Alternate Out 2 Alternate Out 3 Alternate In 1 Alternate Out 3 Pin 0 UARTO_RxD UARTO_TX Pin 1 UART2 RxD X X mo UART2 TX Pin 2 UART1 RxD X UARTO DTR UART2 RxD X Pin 3 X UART1 TX UARTO RTS X Pin 4 X X UARTO_TX X Pin 5 X X UART2 TX X Pin 6 X X X X Pin 7 X X X X opge GPIO6 GPIO7 GPIO Mode Alternate In 1 Alternate Out 3 Alternate In 1 X X X Pin 0 Pin 1 X Pin 2 X Pin 3 X Pin 4 X Pin 5 X Pin 6 UARTO RxD X Pin 7 X UARTO TX Hitex UK Ltd Page 112 Chapter 4 User Peripherals hitex m DEVELOPMENT TOOLS The STR9 has three fully independent UARTs which support data rates up to 1 2Mbaud each UART has IrDA support and UART 0 additional control lines for modem Fa Haad Pie etur Bagage support Each UART can also be a flow controller for the DMA units E I E TED Lem 7 Before the UART can be used to UART TX pin must be configured as an Alternate function 2 Output depending on which port you have allocated the function and the UART RX pin must be used as an input Initialisation of the UART peripheral begins with the Control register 15 1 13 12 11 10 B B ri B 5 B A F4 1 D The UART control register enables the UART and configures its TX and RX features This register is used to enable the UART peripheral UART EN and in addition the transmit and receive channels must also be individually enabled This register also allows you to enable and manage the UART flow control F
241. ter 5 Tutorial Exercises re DEVELOPMENT TOOLS 5 22 Exercise 20 USB The USB example demonstrates using the ST USB library to configure the peripheral to enumerate as a HID Human Interface Device device A dedicated HID client for the XP operating system allows you to read write data to the IO ports and display ADC data 1 On the evaluation board check that the x6 USB Clk is fitted 2 Update the project and open the HiTOP project in ST910FExamples USB 3 As the project size exceeds the 16K evaluation limit of HiTOP you must get a 30 day full licence to be able to debug the project The evaluation version will let you download the project but it does not provide debugging symbols 4 Start the code running and plug the evaluation board into a spare USB port on the PC 5 The STR71x will enumerate as a HID device You can check it is correctly installed in the Control Panel System Hardware device Manager USB controllers window 6 Once the STR71x board is installed successfully it may be accessed by starting HID_Client exe in the project root directory J Human Imerlace Device Client x Lies Fr E ira d F E d A E 1 U i r P L Dr B E Dead LEE E L d 3 1 n F K r Firmeica sain This client allows you to access the ADC and read write to the IO Port pins This example is based on the ST USB library The full documentation for the programming API can be found with the ST documentation on the CD accomp
242. terrupt will be generated This interrupt is used to send the node address you wish to send data too and then send the first byte of data void I2C0 IRQ isr void SWITOH IRO TO SYS while I2CO SR1 amp 0x88 wait for data to be sent I2CO0 CR 0x02 send stop condition tx state 0 OWLTCH SYS TO TRO Clear the VIC channel VICO VAR 0 Exercise 15 I2C GPIO This exercise configures two port pins for use as a bit banging i2C interface to access serial EEPROM and temperature sensor on the STR9 board Exercise 16 I2C loop back This exercise configures both I2C modules as master and slave and transfers data between them Hitex UK Ltd Page 123 Chapter 4 User Peripherals ELOP Bj EF M TOQdLt CR Lu 4 13 CAN Controller The STR9 has a single CAN peripheral Although the CAN protocol was originally developed for automotive use it is now widely used as a local network for distributed embedded systems The CAN controller is one of the more complicated peripherals on the STRO In this section we will have a look at the CAN protocol and the STR9 CAN peripherals The Controller Area Network CAN Protocol was developed by Robert Bosch for Automotive Networking in 1982 Over the last 22 Years CAN has become a standard for Automotive networking and has had a wide uptake in non automotive systems where it is required to network together a few embedded nodes CAN has many attractive
243. th whatever bootstrap loader the silicon manufacturer provides Whilst bootstrap loaders that allow the use of UARTS synchronous serial ports CAN etc are common it is often the case that they do not quite do what the user wants They usually require several small programs to be serially and sequentially loaded into the internal SRAM from whence they run 3 4 5 User Defined Bootloaders The STR9 lets the user write whatever sort of bootstrap loader is needed by the application In the majority of cases the ultimate use of the loader will be to allow in application FLASH programming IAP on the production line or for field updates To do this typically the CPU is set to boot into bank 1 32k of FLASH In the absence of any signal from the outside world the user s bootloader would call the main application in bank 0 A spare port pin would be chosen as the means of telling the bootstrap loader to go into a special mode where for example it might receive a new version of the main application and program it into bank O This is possible because the STRO allows execution from one bank while writing the other One of the reasons that the STR9 does not come with an integral bootstrap loader like the STR730 s SystemMemoryBoot mode is that with its USB and Ethernet peripherals users may well want to implement a TCP IP based bootloader so that new programs are downloaded from a network or even the Internet Obviously this type of bootstrap loader would r
244. that contains fields for packet type destination address and endpoint data field if necessary and error checking Each of the USB packets token data or handshake has the same physical structure Hitex UK Ltd Page 145 hitex mm Chapter 4 User Peripherals DEWVELOHP s EM d m Wal D 4 13 5 1 6 1 Token Phase There are five tokens that are available in USB 2 0 We have already seen the Start of Frame SOF token which is used to mark the start of a 1 msec frame This token does not have an associated data or acknowledge packet The IN token starts a transfer of data into the PC and the OUT starts a transfer of data from the PC to the network device All references to data direction are considered relative to the PC i e IN to the PC or OUT of the PC The setup packets are exclusive to the control channel and are used to send commands to the USB device This may be a request for configuration information or a command to set a particular configuration Finally the PREAMBLE packet is used to signal the start of a low speed transaction The PREAMBLE packet causes the full speed and high speed ports on HUBS to close and the low speed ports to open Then a transaction follows and at the end of the low speed transaction the ports revert to their original state 4 13 5 1 6 2 Data Phase Once the token has been sent by the PC it will be followed by a data packet There are two types of data packet called DATAO and DATA1 Thes
245. the ECKEN bit in control register 1 By default this bit is set at zero to select PCLK The timer prescaler value is held in the lower eight bits of control register 2 This prescaler is only applied to the system clock an external clock source is fed directly to the timer If the external clock is used an additional bit EXEDG in Control register 1 allows you to determine if the rising or falling edge will increment the counter Hitex UK Ltd Page 91 hitex mum Chapter 4 User Peripherals BSEViLOPRM ENT THELE 4 5 1 Input Capture Each of the STR9 timers has two input capture registers each with a matching capture pin Each of these registers may be configured to capture the timer count when there is a transition on a matching input capture pin Timer Counter Register ICAP1A Edge Detector Input Capture Register Software Maskable Interrupt Request Eac Each timer counter has two capture registers which may be used for custom edge measurement ning the ED O 00e interrupt by enabling the IC1IE and IC2IE bits in control register 2 TIMO CR2 0x0O00090FF Enable input capture interrupts and set the prescaler TIMO CR1 0x00008004 Timer enable ICAP1 rising edge ICAP2 falling edge 4 5 2 PWM Input Capture Additionally there is a PWM capture mode that allows the measurement of pulse width and period of a signal applied to the ICAP1 pin By setting the PWMI bit in control register 1 the edge detector for channe
246. the basic information about the device Included in this descriptor is a vendor ID and product ID field These are two unique numbers that identify what device has been connected The windows operating system will use these numbers to determine what device driver to load The vendor ID number is the number assigned to each company producing USB based devices The USB implementers forum is in charge of administering the assignment of vendor IDs You can purchase a vendor ID from their website www usb org for 1500 administration charge they must be very heavy or 2500 if you want to use the USB logo on your product Either way you must have a vendor ID if you want to sell a USB product on the open market The product ID is a second 16 bit field which contains a number assigned by the manufacturer to identify a specific product The device descriptor also contains a maximum packet size field Hitex UK Ltd Page 147 Chapter 4 User Peripherals hitex c DEVELOPMENT TOOLE Tha congue DEVICE in Ce Class 5 oDe 0 Seoda 8 LSeespee li LU eege 7 Lmpsoeneanl 1 1 Maam packet gew poag A wee vw 4 13 5 1 10 Configuration Descriptor The configuration descriptor contains information about the device s power requirements and the number of interfaces it supports A device can have multiple configurations and the PC can select the configuration that best matches the requirements of the applic
247. the required interrupt sources Hitex UK Ltd Page 102 hitex mum Chapter 4 User Peripherals DEVELOPMENT TOOLS 4 7 1 Calibration Output The real time clock provides a calibration output pin that can be used to provide a 4096Hz output This output must be enabled by setting the C bit in the control register 41 AD 29 28 Si 25 oo 24 23 22 21 20 18 1B 17 16 A TOE ME AFE PISELP oO The control register is used to configure the periodic interrupt tamper interrupt and alarm interrupt The W bit must be set to allow writing to some of the RTC registers and then cleared to update them 4 7 2 Setting The Time The time and date can be set by simply writing to the time and date registers However the W bit in the control register must be set to allow access to these registers The clock calendar values are held in the time and date registers as BCD values The quantities available are shown below Time register Date Register Date tens Century tens Date units Century units Hour tens Year Tens Hour units Year Units Minuet tens Month tens Minuet units Month units Second tens Weekday units Second units The real time clock also has a milliseconds register which can be initialised when the W bit is set in the control register Hitex UK Ltd Page 103 hitex mum Chapter 4 User Peripherals e z DEVELOPMENT TOOLS 4 7 3 Setting The Alarm The alarm register is a comparator register that allows
248. the vector register Ox000001 14 D4CO2DES str riz sp 4h OxO00000116 DC DOE mo rl sp Ox0000011 Dic pazDE9 strifd spl rz ra rii riz rig pcr OxO00000120 O4604 Ee sub ril riz 4h 60 void 3 Open the View SFR ARM Processor registers and check that the processor has entered IRQ mode and that the IRQ interrupts are disabled Mode TRO State Flags neCyr IB Disable n FIQ Enables Hitex UK Ltd Page 182 hitex mum D E WELOR B E Wl F o Oils Chapter 5 Tutorial Exercises 4 Step the code so the Macro is run and check that the processor has entered system mode and that the IRQ interrupts are enabled Mode sve Stat ei A DH Flags nZCw IE lEnsble ETO Enable 5 Run the code to the exit macro and observe the switch back to IRQ mode Mode IR U w etatse ARM Flags nzCv e IRQ Lisable Ip FI Lr E 5 L im 4 6 Locate the return command and read the value in the link register Calculate the return address then step the code to confirm that you are correct Hitex UK Ltd Page 183 Chapter 5 Tutorial Exercises 5 9 Exercise 7 FIQ Interrupt This project configures External Interrupt line 4 as a Fast Interrupt The interrupt will be generated when the button on the evaluation board is pressed 1 Open HiTOP project STR910FExamples FIQ FIQ HTP 2 Set a breakpoint on the second line of the FIQ service routine in the Interrupt c module as sh
249. tion is empty However it is possible to encode a number into these unused bits On entering the software interrupt the software interrupt code can examine these bits and decide which code to run So it is possible to use the SWI instruction to make calls into the protected mode in order to run privileged code or make operating system calls 31 28 27 24 23 The Software Interrupt Instruction forces the CPU into SUPERVISOR mode and jumps the PC to the SWI vector Bits 0 23 are unused and user defined numbers can be encoded into this space The Assembler Instruction SWI 3 will encode the value 3 into the unused bits of the SWI instruction In the SWI ISR routine we can examine the SWI instruction with the following code pseudo code switch R14 4 amp OxOOFFFFFF roll back the address stored in link reg by 4 bytes Mask off the top 8 bits and switch on result Depending on your compiler you may need to implement this yourself or it may be done for you in the compiler implementation 1 11 MAC Unit In addition to the barrel shifter the ARM9 has an enhanced Multiply Accumulate Unit MAC The MAC supports same integer and long integer multiplication that are available the the ARM9 The integer multiplication instructions support multiplication of two 32 bit registers and place the result in a third 32 bit register modulo32 A multiply accumulate instruction will take the same product and add it to a running total Lo
250. to keep the FLASH memory form powering down during a debug session Hitex UK Ltd Page 64 hitex mum DEVELOPMENT TOGOLE Chapter 3 System Peripherals The remaining two interrupt modes can be entered by setting the appropriate bit pattern in the power mode field of the power management register 3 8 8 3 Idle Mode Writing 0x01 to the power mode field places the CPU in Idle mode This stops the Clock to the ARM9 CPU but the peripherals are still active The CPU will leave idle mode following a reset or when an interrupt is generated by a peripheral 3 8 8 4 Sleep Mode The final low power mode can be entered by writing 0x02 to the power mode field This forces the STHR9 into sleep mode were the CPU oscillator is switched of and all the on chip clocks are halted in addition the PLL is switched off and the FLASH memory enters a low power mode This is the lowest power mode available to the STR9 It is possible to exit sleep mode with an external reset real time clock alarm or a signal from the dedicated wake up unit The wake up unit will be discussed in more detail in the next section on the STR9 interrupt structure but it allows up to 30 of the GPIO port pins to act as wake up pins to the CPU The RTC and USB resume interrupt lines are also connected to the wake up unit so an interrupt from these sources will also wake up the STRQ 1 7 mA MHz All Periph Clocks ON CPU ON PLL ON 1 0 mA MHz All Periph Clocks OFF Sm mo E mm EE E
251. ts Hitex UK Ltd Page 86 Chapter 4 User Peripherals The SSPs may be allocated to the GPIO pins shown in the table below GPIO Mode Pin 0 Pin 1 Pin 2 Pin 3 Pin4 Pin 5 Pin 6 Pin 7 SSP1_SCLK X SSP1 MOSI SSP1 MISO X SSP1 NSS X X X X X X X X SSPO SCLK SSPO MOSI SSPO MISO SSPO_NSS hitex PEW ELOPHERT TOI Alternate In 1 Alternate Out 3 Alternate In 1 Alternate Out 2 X X X X SSPO SCLK SSPO MOSI SSPO MISO SSPO_NSS GPIO Mode Alternate In 1 Alternate Out 2 Alternate In 1 Alternate Out 2 Pin 0 X X X X Pin 1 X X X X Pin 2 X X X X Pin 3 X X X X Pin 4 SSP1_SCLK SSP1 SCLK SSPO SCLK SSPO SCLK Pin 5 SSP1_MOSI SSP1 MOSI SSPO MOSI SSPO MOSI Pin 6 SSP1 MISO SSP1 MISO SSPO MISO SSPO MISO Pin 7 SSP1 NSS SSP1 NSS SSPO_NSS SSPO_NSS The initial configuration of the SSP is made by programming control register 0 and control register 1 After a reset the SSP is disabled and may be enabled by setting the SSP_ENABLE bit in control register 1 The SSP peripheral should be configured and transmit data written into the FIFO before the peripheral is enabled This register also allows you to configure the SSP as a master or slave device If the SSP is configured as a slave device it is also possible to prevent it from writing data onto the bus by setting the slave output disable In a multiple slave system the serial bus can be connected to each slave and the SOD bit may
252. two peripherals As in the SPI example ADC conversion data is sent between the two peripherals and written to the bank of LEDs 1 Onthe evaluation board connect the port header pins as follows SCL Port pin P0 0 POL pin 0 2 SDA Port pin PO ee Cort poin 0 5 Both lines must also be pulled up to 3 3 volts by a 4K7 resistor 2 Open the Hitop project in STR910FExamples l2C entering the serial number of your Tantino when asked 3 Run the code so that it initialises both I2C peripherals and examine their settings Control Register iIzC U CRi PE IFC O Module Enabled ENGC General Call Disabled START Generate Start Cond No m ACK Generate Acknowlege Yes STOP Generate Stop Cond No e ITE Interupts are Enabled Clock Contr Registers IECO CCE ECCE FM SM Operating Mode Standard EILI EbpD CCO6 CCOO Own Address Registers I fC0 OARL OARS System Frequency 4n 53 33 MHz ADD S ADDOS Jg 4DD07 ADDOO 4 Now run the code at full speed and check that the ADC data is sent over the 12C bus Hitex UK Ltd Page 193 Chapter 5 Tutorial Exercises LEE 1 gk I Wl CR E LOPRM TN MARK 5 19 Exercise 17 CAN This example configures the CAN peripheral in loopback mode and demonstrates the configuration of the CAN module and then sends and receives packets of CAN data The code has been tested on a real CAN network so if you have an analyser you may place th
253. uction motor controller Hitex UK Ltd Page 101 hitex mum DEVELOPMENT TO OLE Chapter 4 User Peripherals 4 7 Real Time Clock The STR9 real time clock module provides a daytime clock with alarm a 9999 year calendar with leap year support a periodic timer and tamper detection interrupt The real time clock can be maintained during power down by an external battery STR91xF The real time clock derives its clock source from an external 32KHz watch crystal The TAMPER IN Watch crystal can also be used to clock the CPU in low power modes The real time clock requires a dedicated 32 768kHz watch crystal to be connected externally The internal RTC dividers are preconfigured to generate the accurate millisecond clock tick E l Calibration clk 4096Hz We 32 768KHz Periodic Intr gt Tamper Intr Tamper In VBAT RTC Interrupt The real time clock provides a clock calendar with an alarm interrupt periodic interrupt and external tamper detection interrupt The RTC programmers interface consists of 5 registers as shown below Like the other peripherals these registers are accessed via the advanced peripheral bus and are clocked by the system clock However as the RTC has its own dedicated clock domain the user registers have a write protection mechanism to ensure that they are written too correctly The real time clock requires very little configuration apart from setting the time and enabling
254. uction set is much more like a traditional microcontroller instruction set Unlike the ARM instructions THUMB instructions are not conditionally executed except for conditional branches The data processing instructions have a two address format where the destination register is one of the source registers ARM Instruction THUMB Instruction ADD RO RO RI1 ADD BO DI RO RO RI Hitex UK Ltd Page 22 hitex mum Chapter 1 The ARM9 CPU Core DEVELOPMENT TOOLS The THUMB instruction set does not have full access to all registers in the register file All data processing instructions have access to RO R7 these are called the low registers In the THUMB programmers model all instructions have access to RO R7 Only a Low Asgyslers few instructions may access R8 R12 High Registers However access to R8 R12 the high registers is restricted to a few instructions MOV ADD CMP The THUMB instruction set does not contain MSR and MRS instructions so you can only indirectly affect the CPSR and SPSR If you need to modify any user bits in the CPSR you must change to ARM mode You can change modes by using the BX and BLX instructions Also when you come out of RESET or enter an exception mode you will automatically change to ARM mode After Reset the ARM9 will execute ARM 32 bit instructions The instruction set can be exchanged at any time using BX or BLX If an exception occurs the execution is automatically wech
255. ugger The JTAG allows HiTOP to download code into the STR9 FLASH or RAM and then debug the code as it runs on the microcontroller In addition to its debugging features HiTOP includes a programmers editor and support for various compiler tools and make utilities that allow you to maintain existing STR9 programs 2 2 2 Which Compiler The HITOP development environment can be used with several different compiler tools These include compilers from ARM Keil Greenhills and IAR There is also a port of the GCC compiler available for the ARM series of CPUs The GCC compiler has the advantage of being a free compiler which will compile C and C code for all of the ARM series of CPUs We can see from this simple analysis that the commercial compilers are streets ahead of the GNU tools in terms of code density and speed of execution Increasingly the commercial compilers include direct support for ARM based microcontrollers in the form of debuggers with support for the STR9 and dedicated compiler switches The reasons to use each of the given compilers can be summed up as follows if you want the fastest code and standard tools use the ARM compiler for best code density use the Keil If you have no budget or a simple project use the GNU Delivered with the starter kit is an installation of the GNU compiler which integrates with the HiTOP debugger IDE The examples given use the GNU compiler 2 2 3 DA C Also included with the development toolchain is
256. uld need to block low priority interrupts by disabling the lower priority interrupt sources in the VIC Hitex UK Ltd Page 73 Chapter 3 System Peripherals ELOHP Bj EF M H D C st Li 3 9 DMA Controller Like the Vector interrupt controller the DMA controller is a peripheral from the ARM prime cell library and is highly optimised for the ARM bus structure The General purpose DMA controller is connected to the AHB bus via two ports A slave port through which the ARM9 CPU can across the DMA register set and a master port that the DMA engine uses to gain control of the bus and arbitrate with the ARM9 CPU and the Ethernet DMA unit D DMA Controller FIQ ARM Core ue IRQ AHB BUS t APB EMI USB Bridge External Memory t TIMO 2 External DMA Requests TIM1 Within the DMA controller there are eight general purpose DMA units that can transfer data between memory to memory memory to peripheral peripheral to memory and peripheral to peripheral Within the DMA controller there are eight independent DMA units which can each be configured to make memory to memory transfers memory to peripheral peripheral to memory and peripheral to peripheral transfers At the end of a transfer each DMA controller can raise an interrupt each of these eight DMA unit interrupts are ORed together and connected to a single VIC interrupt channel 3 9 1 DMA Overview In order to examine the operation of the D
257. unit is free for further operations The final field in the control register allows you to define the burst transfer size used by the DAM controller 3 9 5 Burst Transfer Each of the DMA units can fetch a single word into the DMA unit and then drain it to the destination During these operations the DMA unit must win arbitration of the bus from the ARM9 CPU and the other DMA units before it can act as a bus master It is possible to burst fetch and drain multiple words to and from the DMA unit by configuring the destination and source burst fields in the control register Each DMA unit supports burst sizes or up to 256 transfers By setting the lock bit in the channel control register a DMA unit which has won arbitration will not de grant the bus until the transfer has finished Hitex UK Ltd Page 77 Chapter 3 System Peripherals hitex DEVELOPMENT TOOL 3 9 6 Peripheral DMA Support The table below shows which peripherals can be flow controllers for the any of the DMA units DMA Request Signal Associated Peripheral Function USB RX USB has only 1 DMA Req signal TIMO 2 out of 4 TIMs have DMA support TIMH TIM2 and 3 are not supported by DMA UARTO RX LE UARTO TX 2 out of 3 UARTs have DMA support UART2 is not 10 Comments UART1 EX supported by DMA UART1 TX External DMA Req 0 xterna eq Shared with GPIO External DMA Reg 1 l2C0 GE Each 12C has only 1 DMA Reg signal S3PO RX SSPO TX CULMEN EN
258. ure select system eset target system ET H window Help Reset test system Target System Update license Test system infa 8 In the light of the above behaviour when debugging a real application it is best not to enable the watchdog until the final stages of the project Hitex UK Ltd Page 190 hitex mum Chapter 5 Tutorial Exercises re DEVELOPMENT TOOLS 5 16 Exercise 14 UART This example demonstrates the use of the UARTs in a simple polled mode The evaluation board must be connected to a COM port on the PC 1 Open the UART HTP project in STR910FExamples UART remember to enter the serial number of your Tantino when asked 2 Connect UART zero connector X21 RS232 to a COM port on your PC and start Hyperterminal configured for 115200 baud 8 bits no parity one stop bit 3 Start the code running and switch to Hyperterminal 4 Type in some characters and they will be echoed back to you when the receive FIFO is full 5 Examine the UART configuration code and the UART interrupt routine Disassembly startup912 main ff Setup UART clock ff Set baudrate clock source to Fmstr l H SCU CLKCNTR x0200 de Set BR bit BCLK Fmstr i SCU PCGR1 SCU gt PCGR1 amp Ox00000008 Ox00000008 Clock SCU gt PRR1 0x00000008 Force reset of UARTO ff Reset VART E UARTO CR D UARTO LCR D dd Clear Transmit and Receive Buffers UARTO gt DR 0 vd
259. witch back to IRQ mode with IRQ disabled define SWITCH_SYS_TO_IRQ asm ldmfd sp lr n msr CPSR_c 0x12 0x80 2 11 Linker Script Files Once you have written your source code and compiled it to object files these files must be linked together to make the final absolute file The examples supplied contain linker files with the switches as well as a linker script file EXAMPLE LD that describes the target memory layout to the linker so it knows how to build the final application The linker is invoked with the following switches ld ld opt o project name elf where ld opt is D NoDjectevelinker File id Grer t statio lgcc lo lm nostattriles Map lt project_name gt map The linker script file is saved to your project directory and is given the extension Jd It is important to understand the structure of this file as you may need to modify it as your application code grows The linker script file is a structured text file with a number of sections that describe your project to the linker First some search paths are defined for the compiler libraries These search paths must point to the libraries of the GCC installation you are using SEARCH DIR C Program Files Hitex GnuToolPackageARM ARM hitex elf lib interwork SEARCH DIR C Program Files Hitex GnuToolPackageARM lib gcc ARM hitex elf 4 0 0 1nterwork The GCC compiler comes with several builds of the libraries The version selected here su
260. write to a FIFO buffer which then transfers the data to the associated SFH register This speeds up operation of the CPU but has the same data coherency issues as outlined above Each SFH is also addressable as non buffered O Hitex UK Ltd Page 45 Chapter 3 System Peripherals memory however these non buffered registers introduce a delay on the CPU Use of the non buffered registers does guarantee data coherency Afrer reset the AHD APB buffered registers are disabled and can only be enabled via the co processor interface In the case of the instruction TCM I TCM things are a little more complicated The STHR9 has up to 544K of on chip FLASH in which we can store our application program However the ARM9 executes its instructions from the local I TCM So in order to be able to run the ARMO from the I TCM the STHR9 has to be able to feed the correct sequence of instructions from the FLASH memory into the I TCM fast enough to prevent any processor stalls The STR9 a FLASH memory sub system that consists of three units that combine to read the on chip FLASH and deliver the program instructions to the ARMY TCM in a timely manner The ARMO instruction memory sub system consists of a burst FLASH memory which feeds a perfetch que for sequential instructions and a branch cache which reduces the stall effect of processor interrupts and program branches ARM966E 5 STA GE PIPELINE WRITE DATA D TCM BUFFER The burst FLASH prefetch queue an
261. y register It is up to your application software to ensure that the key register is written frequently enough to stop the watchdog from timing out If the watchdog does timeout a reset will be forced o the STR9 and your code will once again start from the reset vector However in watchdog status register contains an end of count flag which is set if a timeout occurs This flag may only be cleared by software so it is possible to tell if the STR9 is starting from a hardware reset or a watchdog timeout WDG PR 0x000000FF Set maximum divide on the prescaler Reset value WDG VR OxOOOOFFFF Set maximum timeout Reset value WDG CR 0x00000003 Start the count and enable watchdog while 1 WDG_KR 0x0000A55A Refresh the watchdog WDG_KR 0x00005AA5 If your application does not need to use the watchdog for software protection it can be used as an additional 16 bit timer which can generate a periodic interrupt If the watchdog enable bit is not set in the control register the counter will count down to zero and can generate an interrupt if the ECM bit is set in the watchdog mask register When the counter reaches zero the interrupt is generated and the watchdog counter is reloaded to begin the next countdown WDG_MR 0x00000001 enable the IRQ interrupt WDG CR 0x00000002 start the count The only other register available in the watchdog peripheral is the counter register which is a read only register containing the cu
262. you to trigger an interrupt when a match is made with the date and time registers The Alarm register can be updated at any time and is not controlled by the W bit 31 30 9 28 27 26 25 24 23 22 21 2D 19 18 17 16 ANTI ADURO Amm teg AMT 1 3 ANGULO The alarm register allows you to define a time and date that will trigger the RTC alarm interrupt 4 7 4 RTC Interrupts Once the RTC date time and alarm registers are set the RTC interrupt sources can be enabled The RTC has three possible interrupt sources which can be enabled in the control register The RTC can generate an Alarm interrupt when the Date time registers match the contents of the alarm register This interrupt is enabled by setting the AIE and AE bits in the control register The RTC can also generate a periodic interrupt by setting the PIE bit in the control register The period of the interrupt may be one of four pre defined periods 1 Hz 8Hz 64Hz or 512Hz which can be selected through the PISEL field Like the other peripherals the RTC has a single interrupt channel which is connected to the VIC units When an interrupt is generated the source can be determined by reading the status register ra ET eb 2g 24 23 22 CA 20 18 1B 17 16 KN 40 u i E k EE M r F T r The real time clock status register provides flags for each of the interrupt sources These include a periodic interrupt Alarm interrupt and tamper interrupt 4 7 5 Tamper Interrupt

Insider`s Guide STR91x ARM®9

Contents

Download Pdf Manuals

Related Search

Related Contents

Insider`s Guide STR91x ARM&reg;9

Contents

Download Pdf Manuals

Related Search

Related Contents

Insider`s Guide STR91x ARM®9