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FastPMC Products FastPMC-DFLEX64 TTL/EIA-485 I/O

1. 64 is not the source of the interrupt BUSMODE Signals BUSMODE signals are used by the FPMC DFLEX64 to announce its presence in a PMC slot and to identify itself as a PMC module The host module will inhibit its bus interface at all times except when a supported BUSMODE 4 2 is presented to it DMA Requests The FPMC DFLEX64 can use the PCI 9080 DMA requests to implement demand DMA transfers Demand DMA transfers are required if the user application needs to configure the DMA controllers either for large buffer sizes for transmit mode or prior to the data being available in receive mode b Tekmicro sii
2. 8 POT eiie te at eten osi date NEED l kaa ea Baka ake ka en deep 8 sO Call BUS 35 side aks ay ae ay vad aske nou av g aaa 9 Butter Memory PEE 9 Serial EEPROM 10 Customizable FPGA lina 11 Clock ArGhite Ctr wiii vi oo beat l s ennan bwe sad saw aaa pwa oule bw sw st ba oke oka pate sd p aj de ko sale ks a 12 EIA 485 Transceivers nennen enne eene ense sese seen sese sese sese tese sese sese seen 13 Nite rimasto i c 13 Modes Of Operation ao kask pave kou ason necat e area 13 COMME CON Interface yet ke mouri aaa 14 Software Interface 15 OVETVIE MH E 15 aaa 16 Initialization Serial EEPROM 4 eee 16 Initialization PCI Address Configuration 19 Initialization Read Serial eee 19 Initialization Download FPGA Program iii 20 Initialization Clock Synthesizer enne enne enne enne 21 Configuration Space ia aaa N ir SEES A 22 and Memory Space PCI 9080 Registers e 22 PCI 9080 PCI Configuration Registers ie 23 PCI 9080 Local Configuration RegistersS nemen 23 PCI 9080 Runtime RegiSt TS c ete erectis iris iere EIE e Da reda 26 PCI 9080 DMA Registets ttr to kn ad kal mate kilti kw
3. E 1 1 E Connecting Point a LI Connect Connector 4 H zi li n n Connecting i Point ti Connect tor Connect tor i 80 Pin Conneci tore E s i Opening O area A The FPMC DFLEX64 card displayed here demonstrates the DFLEX64 interface on the front panel of the card To install the FPMC DFLEX64 card into a host machine the card must be kept upright with the three PMC connectors on the board matching up with the PMC connectors on the carrier Standard SCSI Small Computer Systems Interface 68 pin connectors are used for the FPMC DFLEX64 front panel connector the pinout for which is discussed in the Connector Interface section of this manual The EMI gasket is to be wrapped around the bezel of the 64 before insertion into the host module The card should be inserted into the host by first fitting the bezel into the front panel of the host and then lining up the connectors and applying minimal pressure to the area of the card above the PMC connectors labeled Connector in the above diagram k Tekmicro FPMC DFLEX64 User s Manual Software Download and Installation The software driver and demonstration programs can be downloaded off the Products section of the TEK Microsystems homepage located at http www tekmicro com The driver distribution is in the TAR GZ format and contains all required source and include files To install the files on a Solar
4. s Manual Support Information Warranty Information The FPMC DFLEX64 is warranted against defects in material or workmanship for a period of one year from the original date of purchase If a failure occurs within the warranty period TEK will repair or replace the product at no cost to the user For watranty repair please contact TEK as described below and obtain an RMA number and return shipping instructions Contact Information If technical support or repair assistance is required please contact TEK through one of the following methods Internet http www tekmicro com Email mailto support tekmicro com Telephone 1 781 270 0808 Facsimile 1 781 270 0813 Mail TEK Microsystems Incorporated One North Avenue Burlington MA 01803 3313 b Tekmicro ids FPMC DFLEX64 User s Manual Additional Documentation The FPMC DFLEX64 module uses off the shelf components to implement several key functions including the PCI bus interface Serial EEPROM and the EIA 485 transceiver Review of the following additional documentation may be useful for proper operation and control of the FRMC DFLEX64 PLX Technologies PCI 9080 Data Book Web site http www plxtech com URL Requires registration with PLX Technologies e Fairchild formerly National NM93CS46 Serial EEPROM Web site http www fairchildsemi com URL http www fairchildsemi com ds FM FM93CS46 pdf e Texas Instruments EIA 485 Transceiver Web site http ww
5. LINTo output are typically unused The DMA controller interrupts may be used by the host application if desired Note that the Local DMA Channel Interrupt Enable bits enable the local DMA interrupt and not a PCI interrupt Typically it is only useful for the DMA completion interrupt to drive the PCI interrupt and therefore bit 17 of the DMAMODE register should be set and bits 18 and 19 of the INTCSR register should be cleared e CNTRL Offset 0x6C Serial EEPROM Control PCI Command Codes User I O Control Init Control Register This register provides an assortment of control functions for various PCI 9080 features Bits 15 0 should typically be left at the reset state of 0x767E Bits 27 24 are used to read and write the Serial EEPROM Bits 27 24 and bits 17 16 are used to download the FPGA program Bits 31 28 are used to reset and reinitialize the PCI 9080 In normal operation the INTCSR register is used to enable local interrupts as a part of the FPMC DFLEX64 initialization and then used to determine the source of interrupts by the host software interrupt service procedure The CNTRL register is used for Serial EEPROM access and FPGA download and then typically not accessed further b Tekmicro ae FPMC DFLEX64 User s Manual PCI 9080 DMA Registers The DMA Registers implement a pair of linked list DMA controllers which are integrated into the PCI 9080 PCI to local bus interface Each DMA controller supports a PCI address local add
6. This register may be configured as required by the host application This register affects PCI 9080 performance when performing Direct Master DMA transactions k Tekmicro i FPMC DFLEX64 User s Manual DMCFGA Offset 0x2C EEPROM value 0x00000000 PCI Configuration Address Register for Direct Master to PCI IO Cfg Not used by FPMC DFLEX64 LASIRR Offset 0xF0 EEPROM value 0xFFC00000 Local Address Space 1 Range Register for PCI to Local Bus In the standard configuration bit 0 is cleared to map into PCI memory space and bits 2 1 are set to 00 to allow location anyplace in the 32 bit PCI address space Bit 3 must be cleared to indicate that reads are not prefetchable Bits 31 4 specify the size of the address range the default size is 4 MB When using the user FPGA program the size must be less than 8 MB to ensure that the LA 22 bit is set by the remap register LASIBA Offset 0xF4 EEPROM value 0x00400001 Local Address Space 1 Local Base Address Remap Register In the standard configuration bit 0 is set to enable the space and bit 22 is set to generate local bus cycles to the FIFO space instead of the FPGA control status register space The test FPGA program uses bit 22 to select control status registers vs FIFO accesses LBRDI Offset OXF8 EEPROM value 0x000003C3 Local Address Space 1 Bus Region Descriptor Register The test FPGA program requires that bits 1 0 be set to 11 32 bit local bus width bit 6 be set enables Ready in
7. and processes serial control data on the DATA input for each rising edge of the SCLK inputs The programming sequence requires downloading the following bits in sequence e CD2053 8 bit control word to switch to the reference clock output e CD2053 6 bit control word flag e CD2053 22 bit program word with bit stuffing e CD2053 8 bit control word to accept program word e CD2053 6 bit control word flag k Tekmicro id FPMC DFLEX64 User s Manual e CD2053 8 bit control word to switch to clock synthesizer output e CD2053 6 bit control word flag The FPMC DFLEX64 software drivers include language functions to generate ICD2053 program words and to download the program word to the FPMC DFLEX64 The current release of the FRMC DFLEX64 software drivers is available from TEK s technical support department as well as off of the TEK homepage Configuration Space The FPMC DFLEX64 provides a Type 0 PCI configuration space as required by the PCI 2 1 specification The FPMC DFLEX64 is factory configured with the following parameters e Vendor ID 0x14CF This Vendor ID has been issued by the PCI Special Interest Group to TEK Microsystems Incorporated e Device ID 0x3221 and Memory Space PCI 9080 Registers The PCI 9080 provides a large number of control and status registers which are mapped to the PCI I O space by the BARO configuration register and also to the PCI Memory space by the BARI configuration register Th
8. ba kos a pa a ke lp aru abesse eta 27 PCI 9080 Messaging Queue Registers essen nen enne 28 Memory Space FPGA Resistens solves eee ea en yeu ep YI cH Erro dr Erga 28 IntetrUupts i asciende tete tata ese literae ides tes era e paka eta die ea an 28 BUSMODE ET Hm 28 REQUESIS D M 28 b Tekmicro FPMC DFLEX64 User s Manual Product Description The FastPMC DFLEX64 is an IEEE P1386 1 PMC module which provides a full duplex 16 bit EIA 485 or 32 bit TTL high speed data link or a half duplex 32 bit EIA 485 or 64 bit TTL high speed data link The DFLEX64 bus maximum operational speed will depend upon the user s FPGA and the mode in which the card is used The FPMC DFLEX64 may be used to provide connectivity between two or more carrier boards or between a PMC carrier board and an external system equipped with a TTL or EIA 485 interface The board must be ordered specifically Typical applications include pattern generators pulse measurements and application specific serial interfaces There is a test FPGA available for the board but users will have to generate their own FPGA to get their desired functionality out of the card The test FPGA defines registers which will write to and read from the data pins and provides the state machines for serial communications with the EPLD in order to set the mode in which the hardware will run FPGA programs are downloade
9. memory into linear PCI address space without FIFO semantics Serial EEPROM The PCI 9080 interface controller has a built in interface to a serial EEPROM device The serial EEPROM is used as a source for PCI 9080 configuration information after PCI reset and as a resource for the user to store non volatile configuration information about the PCI PMC card In the 64 the serial EEPROM interface is connected to a Fairchild NM93CS46 or similar part 1 024 bit serial EEPROM organized as 64 sixteen bit words The first 44 words 88 bytes of the EEPROM are used to define the PCI 9080 configuration registers The next 11 words are available for user data and the last 9 words are used for FPMC DFLEX64 configuration information The PCI 9080 Serial EEPROM interface signals are also used to download FPGA program information to the FPGA device The data sheet for the NM93CS46 is available on Fairchild s web site http www fairchildsemi com and is also available on request from TEK s technical support department k Tekmicro ie FPMC DFLEX64 User s Manual Customizable FPGA The FPMC DFLEX64 implements most of the onboard logic using an in system programmable FPGA device The standard FPGA device is an Altera EPF10K50VRC240 3 which provides between 36 000 and 116 000 gates of logic capability along with 20 480 bits of internal RAM memory or an optional device as discussed earlier under the Specification heading of th
10. subsystems is discussed below PCI Interface The PCI PMC interface is implemented using an off the shelf PCI 9080 interface controller from PLX Technologies The PCI 9080 implements all necessary PCI bus interface functions including configuration space EEPROM interface PCI interrupter for local interrupts and two linked list DMA controllers The PCI bus interface is compliant with the PCI 2 1 specification and operates at 33 MHz with a 32 bit data bus The FPMC DFLEX64 is compatible with 3 3V and 5V PCI signal levels Many of the features of FPMC DFLEX64 are implemented through the local bus interface using PCI 9080 resources For example the FPMC DFLEX64 bus mastering capability is implemented using the PCI 9080 DMA controllers To reach a complete understanding of how to use the FPMC DFLEX64 features the user is strongly encouraged to review the PCI 9080 data book along with this manual The data book for the PCI 9080 is available on PLX Technologies web site http www plxtech com and is also available on request from TEK s technical support department b Tekmicro FPMC DFLEX64 User s Manual Local Bus The FPMC DFLEX64 has an internal local bus that is used to communicate between the PCI 9080 the FPGA and the buffer memory The local bus implements a 32 bit multiplexed address data bus and associated control signals The local bus is arbitrated between the PCI 9080 and the FPGA The PCI 9080 acts as th
11. the standard FPGA programs the value must be a multiple of four e DMADPR Offset 0x90 and OXA4 DMA Channel X Descriptor Pointer Register Bit 0 should be set descriptor located in PCI address space and bit 3 should be cleared for DMA channel 0 and set for DMA channel 1 Bits 1 2 and 31 4 are determined by the application e DMATHR Offset 0xB0 DMA Threshold Register This register may be set as desired to optimize DMA transfers and PCI bus utilization for the user application Because of the hysteresis built into the standard FPGA program s DMA request controls and the depth of the onboard buffer memory the threshold register settings are unlikely to have a significant effect on performance b Tekmicro FPMC DFLEX64 User s Manual PCI 9080 Messaging Queue Registers The Messaging Queue Registers implement I20 compatible message queues for communications between a host resident I2O driver and a local processor The FPMC DFLEX64 test FPGA programs do not utilize these registers Memory Space FPGA Registers For a complete listing of FPGA registers consult the test FPGA documentation Interrupts The handling of interrupts is dependent on the host carrier and the operating environment Typically the host software is responsible for identifying the source of the interrupt and clearing the interrupt condition Because PCI interrupts are shared the host software routine is required to properly handle being called when the
12. 4 interface Both of the ICD2053 devices generate synthesized output clocks using a 16 667 MHz reference clock The reference clock is generated by dividing either the PCI bus clock or the optional crystal source both of which are 33 3 MHz by two The accuracy of the synthesized clock will be directly proportional to the accuracy of the reference clock The ICD2053 control signals are listed below control bits in the FPGA register space directly generate all of the control signals SCLK A When a low to high edge occurs on this signal the DATA state is clocked into the ICD2053 control word for clock synthesizer A SCLK B When a low to high edge occurs on this signal the DATA state is clocked into the ICD2053 control word for clock synthesizer B DATA Provides serial data for SCLK A and B rising edge Configuration of the ICD2053 requires two separate operations 1 Generate a program word based on the reference frequency and desired output frequency 2 Download the program word to the ICD2053 The first step is most easily performed using Cypress s BitCalc software BitCalc is a free Windows based program that generates ICD2053 program words based on the reference frequency and desired output frequency BitCalc is available on Cypress s Web site at http www cypress com The second step is performed by toggling the appropriate FPGA control register bits to control the ICD2053 SCLK A and B and DATA inputs The ICD2053 accepts
13. Electromagnetic Interference EMI Gasket e Rev User Manual The FPMC DFLEX64 contains electronic circuits that are susceptible to damage through mishandling or through application of electrostatic discharge ESD The following precautions should be observed when unpacking installing or using an FPMC DFLEX64 card e Whenever the FPMC DFLEX64 is being handled outside of an ESD safe shipping container the user should maintain ESD safe conditions through usage of a grounding wrist strap or other such static preventive measures e The FPMC DFLEX64 should never be installed or removed from the slot when power is being applied to the system or applied directly to the card e The FPMC DFLEX64 should never be forced into the slot during installation Insertion of the card into should require only moderate hand pressure If more pressure is required for the insertion the card should be removed and the connectors examined to determine the source of the problem Like any other electronic circuit card the FPMC DFLEX64 will provide years of reliable operation if handled in accordance with these guidelines k Tekmicro FPMC DFLEX64 User s Manual Installation The front panel view of the FPMC DFLEX64 card along with a host module and DFLEX64 cable is shown below subject to change HOST i MODULE FPMC DFLEX64 SCSI 68 CABLE pem
14. age header file To minimize the memory space required in the host carrier the utility also performs a simple compression of the data The TEK software driver decompresses the resulting file as the image is output to the FPGA device In the 64 the Serial EEPROM and FPGA download interfaces configured as follows PCI 9080 SERIAL EEPROM nCONFIG CONF_DONE In this configuration the Serial EEPROM may be accessed without modifying the FPGA contents provided that the USERO output remains high Likewise the FPGA can be initialized without modifying the Serial EEPROM provided that the EECS output remains low The FPMC DFLEX64 supports the FLEX 10K Passive Serial download method The Passive Serial download algorithm is described in detail in Altera Application Note ANS9 Configuring FLEX 10K Devices The download algorithm is implemented in the tekpciDflex64Load routine in tekpciDflex64Main c k Tekmicro FPMC DFLEX64 User s Manual Initialization Clock Synthesizer The FPMC DFLEX64 uses pair of Cypress ICD2053 clock synthesizers to generate the local bus clock and one of the possible sources of the DFLEX64 data rate clock The local bus clock is designated LCLK and the rate clock is designated SCLKA If the synthesizer clock is used as the data transfer rate for the DFLEX64 the clock synthesizer must be programmed prior to using the DFLEX6
15. am provided that the USERO output is high The procedure for reading and writing the serial EEPROM is as follows first enable the EECS output clock a command code and address out to the serial EEPROM using the EESK and EEDO outputs and then either clock data to the serial EEPROM for a write or clock data from the serial EEPROM for a read The detailed command formats and valid command codes are described in the NM93CS46 data sheet Sample routines that read and write the serial EEPROM are contained in the tekpciPIx9080Eeprom c file Routines that interpret the serial EEPROM values that describe the FPMC DFLEX64 configuration are contained in the tekpciDflex64Info c file b Tekmicro FPMC DFLEX64 User s Manual Initialization Download FPGA Program After the Base Address Registers have been programmed and the serial EEPROM contents have been read the host application can determine the correct FPGA program image to download The FPGA program image is determined both by the part number based on the desired functionality and the FPGA device which selects one of several possible program images The part number for this particular FPGA program is 32221 The PCI 9080 CNTRL register offset 0x6C may then be used to download the FPGA program image into the FPGA The FPGA program image is typically delivered as an Altera TTF file The demonstration software includes a utility that converts an Altera TTF file into a C langu
16. b Tekmicro FastPMC Products FastPMC DFLEX64 TTL EIA 485 I O Module User s Manual RevC TEK TM 322C March 2002 FPMC DFLEX64 User s Manual TEK Microsystems has made every effort to ensure that this manual is accurate and complete However TEK reserves the right to make changes and improvements to the products described in this manual at any time and without notice This product is covered by a limited warranty which is described in the manual Other than the stated limited warranty TEK disclaims all other warranties including the warranties of merchantability and of fitness for a particular purpose In the event of a failure of the hardware or software described in this manual TEK s obligation is limited to repair or replacement of the defective item or if the item cannot be repaired or replaced a refund of the purchase price for the item TEK assumes no liability arising out of the application or use of the hardware or software and assumes no responsibility for direct indirect incidental or consequential damages of any kind The electronic equipment described in this manual generates uses and can radiate radio frequency energy Operation of this equipment in a residential area is likely to cause radio interference in which case the user at his own expense will be required to take whatever measures may be required to correct the interference TEK Microsystems products are not authorized for use as critical components
17. d over the PCI bus allowing the module to be customized for specific applications without hardware changes The test FPGA does not provide a means for bursting data on and off the PCI bus as this was not the intent of this design Users desiring fast I O capabilities should contact TEK Microsystems directly or access the website at www tekmicro com to view products designed for high speed data transfer using similar logic interfaces Alternatively users can decide to incorporate PCI data buffering inside their FPGA designs A block diagram of the FPMC DFLEX64 is shown in the figure below je FRI 06 Bus ky COMTROLLEA INTERFACE A HAam TL a FPGAI SELECTION TREMALETORE INTERFACE nr BPF 100508 10K 1004 SYNTHESEER b Tekmicro ad Specifications I O Interface Clock Rate PCI Bus Interface PCI Throughput FPGA Logic Capacity Memory Capacity Interrupts DMA Power Requirements Operating Temperature Storage Temperature FPMC DFLEX64 User s Manual 32 EIA 485 I O pairs or 64 TTL I O signals DC to X MHz where X is dependent primarily on the user s FPGA PCI 2 1 compatible 32 bit 33 MHz Compatible with 3 3V or 5V signal levels 132 MB s burst Supports zero wait state memory accesses Altera EPF10K50VRC240 3 36K to 116K gates Optional EPF10K100VRC240 3 or 1 devices available Memory function is determined by FPGA program k Tekmicro Page FPMC DFLEX64 User
18. e PCI 9080 registers are loosely divided into five groups of registers by the PCI 9080 data book e PCI Configuration Registers e Local Configuration Registers e Runtime Registers e DMA Registers e Messaging Queue Registers The following discussion reviews the FPMC DFLEX64 specific implementation of PCI 9080 functions for each register group k Tekmicro FPMC DFLEX64 User s Manual PCI 9080 PCI Configuration Registers The PCI Configuration Registers allow the 64 to uniquely identify itself to the host environment and also allow the host in a device independent manner assign memory space to the module The PCI Configuration Registers are defined in the PCI 2 1 specification which is available from the PCI Special Interest Group http www pcisig com PCI 9080 Local Configuration Registers The Local Configuration Registers define the operation of the local bus interface between the PCI 9080 and the test FPGA program as well as tuning the PCI bus interface of the PCI 9080 when operating as a Direct Slave or Direct Master The PCI 9080 supports three types of PCI bus cycles e Direct Slave The PCI 9080 is a Direct Slave when another PCI device performs a read or write cycle with the FPMC DFLEX64 as the target The PCI 9080 Direct Slave logic translates the PCI address into a local address generates appropriate local bus control signals and performs local prefetching and burst accesses depending on the co
19. e bus master to implement transactions between the PCI bus and the FPGA and also to implement DMA transactions between the PCI 9080 internal FIFOs and the FPGA The local bus also implements two DMA request acknowledge signals and a local interrupt which may be used to generate PCI interrupts through the PCI 9080 The local bus protocol is completely defined in the PCI 9080 data book The FPMC DFLEX64 uses the PCI 9080 J bus mode Buffer Memory The FPMC DFLEX64 has a static RAM buffer memory The buffer memory is implemented using two CY7C1041 17ZC 256K x 16 static RAM IC s The memory implementation has additional logic to gate the write control signal from the FPGA allowing the memory subsystem to sustain local bus bursts of single clock read and write cycles A block diagram of the buffer memory implementation is shown below CONTROL SIGNALS CONTROL SIGNALS BUFFER PCI 9080 MEMORY ADDRESS MEMORY LOCAL ADDRESS DATA Local bus transactions may be generated by the PCI 9080 or by the FPGA The PCI 9080 will generate local bus transactions when requested by the PCI bus i e when acting as a PCI Target or when driven by the PCI 9080 internal DMA controllers k Tekmicro im FPMC DFLEX64 User s Manual The standard FPGA programs use the LA 22 bit to determine whether a local bus cycle accesses control status registers LA 22 low or t
20. he FIFO memory LA 22 high Note however that FIFO accesses are not implemented in the test FPGA supplied with this design With the default configuration of the PCI 9080 the address range defined by BARZ2 has the LA 22 bit forced low and the address range defined by BAR3 has the LA 22 bit forced high Therefore all accesses to the BAR2 region will access control status registers and all accesses to the BAR3 region will access the FIFO memory if implemented by the user Because the LA 21 2 address bits are ignored during FIFO accesses the BAR3 memory region can be of arbitrary size depending only on the operating environment s constraints TEK s default configuration defines a 4 MB memory region to support the possibility of large DMA transfers using an external DMA controller that requires incrementing the PCI address If all DMA transfers are performed using the PCI 9080 controllers the BAR3 memory region can be configured for a smaller size as the PCI 9080 DMA controller has a fixed vs incrementing local address option controlled through DMAMODE bit 11 Because the buffer memory address and control signals are controlled by the FPGA alternate memory implementations are possible through FPGA reprogramming Specifically implementations that perform random accesses to memory i e quadrant to raster conversion of incoming frame data or similar functions are quite feasible as are implementations that simply map the buffer
21. ignal lines The card consists of 4 independent blocks that can be set for inputs or outputs in either TTL or EIA 485 mode Blocks can be set up in any direction input or output desired by the user as long as the entire block remains consistent The entire block must be operating in the same direction for EIA 485 mode Logic levels cannot be mixed within a FPMC DFLEX board this is not a supported use for this card The entire board will communicate with either EIA 485 logic levels or with TTL logic levels k Tekmicro ae FPMC DFLEX64 User s Manual Connector Interface The FPMC DFLEX64 Rev A JI connector pinout is shown in the table below L3 L9 Ko A10 2 18 Bi2 47 Am d gt Bis 48 15 49 16 so 35 2 37 Ss 39 e EUN n on 4 9 R to ia 45 42 2 AM 1 2 2 2 k Tekmicro FPMC DFLEX64 User s Manual Software Interface Overview The software interface to the FPMC DFLEX64 is implemented using the PCI PMC bus The FPMC DFLEX64 uses the PLX Technologies PCI 9080 controller to implement the PCI PMC bus interface The PCI 9080 provides the logic required to support operation as both a PCI Master used for bus mastering DMA transfers between the FPMC DFLEX64 and the host memory and a PCI Target used for access to control status registers in the PCI 9080 and the FPMC DFLEX64 FPGA The PCI 9080 is typically configured with four separate PCI address
22. ilize this register to perform Big Endian adjustments in hardware if desired e EROMRR Offset 0x10 EEPROM value OxFFF00000 Expansion ROM Range Register Not used by FPMC DFLEX64 e Offset 0x14 EEPROM value 0x10000010 Expansion ROM Local Base Address Remap Register and BREQo Control The standard FPGA program requires that bit 4 be set to enable the BREQo output e LBRDO Offset 0x18 EEPROM value 0x4FC305C3 Local Address Space 0 Expansion ROM Bus Region Descriptor Register The test FPGA program requires that bits 1 0 be set to 11 32 bit local bus width bit 6 be set enables Ready input for memory space 0 bit 7 be set enables BTERM input for memory space 0 and bit 8 be set disables prefetch for memory space 0 Bits 31 26 and 24 are determined by the application requirements but are usually set to enable bursting Bit 25 is typically set to initialize the LASIRR LASIBA and LBRDI registers from serial EEPROM e DMRR Offset 0 1 EEPROM value 0xFF000000 Local Range Register for Direct Master to PCI Not used by FPMC DFLEX64 e DMLBAM Offset 0x20 EEPROM value 0x40000000 Local Bus Base Address Register for Direct Master to PCI Memory Not used by FPMC DFLEX64 e DMLBAT Offset 0x24 EEPROM value 0x70000000 Local Base Address Register for Direct Master to PCI IO Cfg Not used by FPMC DFLEX64 e DMPBAM Offset 0x28 EEPROM value 0x0000183F PCI Base Address Remap Register for Direct Master to PCI Memory
23. in life support devices or systems without the express written agreement of an officer of TEK Microsystems This manual is Copyright 2001 TEK Microsystems Incorporated All Rights Reserved FastPMC is a trademark of TEK Microsystems Incorporated Other trademarks and registered trademarks used are owned by their respective manufacturers Revision Information This manual describes hardware revision A of the FPMC DFLEX64 Document ordering code and release information URL http www tekmicro com tm322 revC pdf TEK TM 322C March 2002 b Tekmicro Page i FPMC DFLEX64 User s Manual Table of Contents Product Deseriptlohi ada 1 crie fme MR 2 Support InformallOn 10 rar ER ED eR E e ve RISE UII bU NE MM am 3 Warranty Information j iii cepere HD rie aw pk ya ko ou pep be kok oi papa aso aso bio E 3 Contact Information 3 Additional Documentation eene eene nennen nennen eese eese eese ee eren 4 Installation and Setup f 5 cia ei a I OR RR ui fal pasi kle oil Ar 5 Unpacking and Handle acilia 5 Installation rurale 6 Software Download and 7 Theory af ODer amp allOfTus oka ass RR I 8 anular gid isn i dui saw aovwede e ii e
24. is document The FPGA program is downloaded through the PCI bus using the user I O and serial EEPROM signals from the PCI 9080 The local bus is inoperative prior to FPGA download as the local bus acknowledge signals are always inactive until driven by the FPGA The FPGA functionality and memory space registers are described in the FPGA documentation for the test FPGA b Tekmicro d FPMC DFLEX64 User s Manual Clock Architecture A diagram showing the clock architecture of the FPMC DFLEX64 is shown below PCI CLK LCLK NI N N CLOCK SYNTHESIZERS N SCLKB BPCLKo BPCLKo EPLD Div by 2 A CYPRESS ICD2053 CONTROL N XTAL N LCLK FPGA XTAL PCI 9080 CLOCK DRIVER HCLK LCLK 49 CT805A LCLK LCLK 1MB BUFFER MEMORY The details of the internal FPMC DFLEX64 clock domains are primarily of interest to users who are developing their own FPGA programs The clock routing operates as follows e First the PCI bus and the PCI interface portion of the PCI 9080 are synchronous to the PCI bus clock The clock domain is not shown in the diagram above as it does not interact with the rest of the card e The PCI 9080 generates a clock output which is a regenerated version of the PCI bus clock This signal is named BPCL Ko e The sythesizer reference clock is a version of either BPCLKo or a 33 33 MHz crystal oscillator outp
25. is system enter the following commands gunzip dflex64 current tar gz tar xvf dflex64 current tar This will create the required directories and place all the required files in those directories Running the command make in this directory will create the driver object files along with a suite of demonstration programs The FPMC DFLEX64 still requires several initialization procedures before the card can be used which the drivers are designed to perform These procedures are described in detail in the Software Initialization section of this manual After initialization the Manufacturing tests can be run to verify the installation Note the loop test will fail because it requires a loop back cable which is not provided b Tekmicro FPMC DFLEX64 User s Manual Theory of Operation Overview The FPMC DFLEX64 provides a high speed customizable interface between a PCI PMC host system and an external system using either TTL or EIA 485 logic levels The card must be ordered to run in either EIA 485 only mode or in TTL only mode This is a factory configuration option and is not recommended as an option for users to attempt A block diagram of the FRMC DFLEX64 is shown below PO a A a ni mi ge CONTECHLER P FELL PACGRAMMABLE GATE ARENY INTERFACE IAM TTL fi FPGN SELECTION N TRAMELETORE OFF 10K 130A prr MEMORY CLOCK The operation of each of the hardware