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88C196EC Microcontroller

1. 88C196EC Microcontroller Specification Update October 1998 Notice The 88C196EC microcontroller may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are documented in this specification update Order Number 273165 003 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Contact your local Intel sales office or your distributor to obtain the latest
2. Affected Docs 24 Issue Affected Docs 25 Issue Affected Docs 26 Issue 22 Page 10 15 Figure 10 7 EPAPWM Receive Transmit Channel EEPA concatenation does not function on 88C196EC Dotted line entitled Concatenate connecting EN_EPAx_CON to EPAPWM pin should be deleted in Figure 10 7 88C196EC Microcontroller User s Manual Page 10 24 Section 10 7 Generating a 32 Bit Time Value EEPA concatenation does not function on the 88C196EC Remove last sentence in first paragraph on section 10 7 You can also use timers and 2 and any pair of adjacent EPAPWM channels in this same manner 88C196EC Microcontroller User s Manual Page 10 38 Figure 10 25 EPAPWMx Control Register EEPA concatenation does not function on the 88C196EC Change bit 0 definition of EPAPWMx Control register from EMC to Reserved bit EMC in column 2 will change to Column 3 should change to Reserved always write as zero 88C196EC Microcontroller User s Manual Page 13 13 Figure 13 11 RSTSRC Register The reset state of register is not OOh It is xxh e Old Reset state OOh e New Reset state xxh 88C196EC Microcontroller User s Manual Page C 86 RSTSRC Register The reset state of register is not OOh It is xxh e Old Reset state OOh e New Reset state xxh 88C196EC Microcontroller Specification Update
3. Microcontroller User s Manual 88C196EC Microcontroller Specification Update 19 LJ Documentation Changes I ntel 11 Issue Affected Docs 12 Issue Affected Docs 13 Issue Affected Docs 14 Issue Affected Docs 15 Issue Affected Docs 16 Issue Affected Docs 20 Page C 66 Table C 12 Px MODE Addresses and Reset States P6 MODE register address is incorrect It should be 1FE1h not 1FDOh 88C196EC Microcontroller User s Manual Page C 67 Table C 13 Px PIN Addresses and Reset States P6 PIN register address is incorrect It should be 1FE7h not 1FD7h 88C196EC Microcontroller User s Manual Page C 69 Table C 14 Px REG Addresses and Reset States P6 REG register address is incorrect It should be 1FESh not 1FC4h 88C196EC Microcontroller User s Manual Pages C 7 8 Table C 2 Register Name Address and Reset Value The following register addresses need to be corrected P6 DIR should be 1FE3h not 1FD3h P6 MODE should be 1FE1h not 1FDOh P6 PIN should be 1FE7h not 1FD7h P6 REG should be 1FESh not 1FC4h 88C196EC Microcontroller User s Manual Page 2 20 Figure 2 9 CCR1 Register CFD bit definition is incorrect The enable and disable bits are reversed e Old 0 enables clock failure detection circuitry 1 disables clock failure detection circuitry e New 0 disables clock failure detection circuitry 1 enables clock failure detection circuitry 88C196EC Microcont
4. specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1998 Third party brands and names are the property of their respective owners 88C196EC Microcontroller Specification Update intel Contents Revision History EE N EN 5 ae AE EE EE RE OE EEN 6 Summary Table of ChangesS iese Re ee ee ee ee ee RR rna nn nn nn 7 Identification InformatiON esse ee Re RA Re nn ee rna ann 10 EA ET N OE OE N EE 11 Specification CHANGES see ee ee AA ee rr rr rr nn nn rr rna ann 15 Specification Clarifications ee ee ee AR Re nn ee 16 Documentation Change i iese ee enn rr rr r rn nns nr rr non nr nnn 17 88C196EC Microcontroller Specification Update intel Revision History Date Version Description 11 11 98 003 Added Errata 20 Stack Overflow Module 08 12 98 002 Added Errata 18 and 19 and Documentation Changes 25 and 26 03 16 98 001 ie is the new Specification Update document It contains all identified errata published prior to this 88C196EC Microcontroller Specification Update Preface Preface As of July 1996 Intel s Computing Enhancement Group has consolidated available historical device and documentation errata into this new document t
5. to determine the affected stepping s RSTSRC Register Clear on Vcc Power up The four least significant bits in the RSTSRC register CFDRST WDTRST SFWRST and EXTRST are supposed to be cleared when Vcc is powered up The CFDRST WDTRST and SFWRST bits may be erroneously set on Vcc power up and cannot be guaranteed to be cleared Applications that rely on these bits to be cleared on Vcc power up may be adversely affected NoFix Refer to the Summary Table of Changes to determine the affected stepping s Reset During Code RAM Read Operation During the time that the device is reading data from code RAM a code RAM corruption may occur if e a device reset occurs from a falling edge on the RESET pin e a watchdog time out event occurs or e a clock fail detect event occurs Code RAM data corruption may occur as a result of the reset event If code RAM data integrity must be maintained after the reset event prevent external resets watchdog time out events and clock fail detect events from occurring during a code RAM read operation NoFix Refer to Summary Table of Changes to determine the affected stepping s Stack Overflow Module Writing an address to location 001C18h in the Upper Register File that is less than or equal to the lower stack boundary STACK_BOTTOM or greater than or equal to the upper boundary STACK_TOP generates a stack overflow interrupt Inadvertent stack overflow interrupts may occur during normal code exe
6. 7 LJ Documentation Changes I ntel Affected Docs 3 Issue Affected Docs 4 Issue Affected Docs 5 Issue Affected Docs 6 Issue Affected Docs e New Definition IDLE POWERDOWN Depending on the 8 bit value of the KEY operand this instruction causes the device to enter idle mode if KEY 1 enter powerdown mode if KEY 2 execute a reset sequence if KEY any value greater than 3 The bus controller completes any prefetch cycle in progress before the CPU stops or resets If KEY 1 then enter idle else if KEY 2 then enter powerdown else if KEY gt 3 then execute reset PSW Flag Settings Z N C V VT ST Key 1 or 2 Key any value greater than 3 0 0 0 0 0 0 88C196EC Microcontroller User s Manual Page 11 10 Figure 11 5 A D Command AD COMMAND Register Added sentence to GO bit note GO bit must be set to 0 for A D SCAN to work 88C196EC Microcontroller User s Manual Page 11 11 Section 11 5 Determining A D Status and Conversion Results The last sentence of the first paragraph is incorrect Old If you read the AD RESULT or AD RESULTx before the conversion is complete the result is not guaranteed to be accurate e New If you read the AD RESULT register before the conversion is complete the result is not guaranteed to be accurate The AD RESULTx register can be read at any time 88C196EC Microc
7. Access Odd addresses in the Flash could not be accessed This is because the block lock bits which control access to the Flash are only read by the even byte sense amps When programming erasing or executing a flash function the lock bits are read first If the address of the function to be performed was an odd address then the odd byte sense amps were used so the lock bits were not accessed and the read from the even byte sense amps returned a logic 1 This caused the device to think the block lock bits were programmed which disabled the Flash functions Unable to run code from on chip Flash Use external memory option Fixed Refer to Summary Table of Changes to determine the affected stepping s CSO Strong Pull Up Enabled with EA 1 The CSO pin had a strong pull up enabled when running internally and from test ROM execution mode A strong driver is needed to overdrive CSO to a low voltage level to allow entry into certain test ROM execution modes including SIO RISM mode Auto Programming mode Slave Dump Programming mode and Uprom Dump Programming mode Provide a strong driver in application to overdrive the CSO pin to a low voltage Fixed Refer to Summary Table of Changes to determine the affected stepping s 88C196EC Microcontroller Specification Update 11 Errata 5 Problem Implication Workaround Status 6 Status Implication Workaround Status 7 Problem Implication St
8. J l ntel Documentation Changes Documentation Changes 1 Page 6 3 Figure 6 2 Interrupt Service Flow Diagram Issue Interrupt service flow diagram is incorrect A normal interrupt will not be serviced if the PTSSEL x bit is set to 1 To make correct the following change needs to be made Add PTSSEL x bit 0 conditional branch after yes branch of Interrupts Enabled If conditional answer is yes continue to priority resolver block If conditional answer is no then continue to return Affected Docs 88C196EC Microcontroller User s Manual 2 Page A 20 Table A 6 IDLPD Instruction Definition Issue Illegal key definition is incorrect Key 3 is not considered an illegal key by the device and will not cause the device to reset Only keys greater than 3 are considered illegal Old Definition IDLE POWERDOWN Depending on the 8 bit value of the KEY operand this instruction causes the device to e enter idle mode if KEY 1 enter powerdown mode if KEY 2 e execute a reset sequence if KEY any value other than or 2 The bus controller completes any prefetch cycle in progress before the CPU stops or resets If KEY 1 then enter idle else if KEY 2 then enter powerdown else execute reset PSW Flag Settings Z N C V VT ST Key 1or 2 Key any value other than 1or2 0 0 0 0 0 0 88C196EC Microcontroller Specification Update 1
9. a glitch that occurs when the pin output driver is turned off The glitch is caused by the data changing before the output driver is completely turned off The AD15 pin is the farthest pin from the driving logic Under extreme conditions the AD14 pin may also fail May affect applications that use the Ljmp instruction Fixed Refer to Summary Table of Changes to determine the affected stepping s Port Initialization Depending on which phase the device is brought out of reset a race condition may occur between the reset signal and the data input into the port SSEL and DIR registers This affects ports 2 6 7 8 and 9 Instead of the registers being initialized to their default reset settings they may get initialized to whatever was last on the internal PDB May affect applications that depend on the pins on these ports to come up in their defined reset state Fixed Refer to Summary Table of Changes to determine the affected stepping s Odd Uprom Bit Read from TROM The test ROM code used to read the status of the Uprom bits utilizes the Cobra FACE commands The Cobra FACE command for reading the Uprom or block lock bit status outputs the status on ADO However the bus controller only outputs AD8 AD15 when reading from odd addresses Therefore when accessing the odd block lock bit addresses Uprom bits DEI and CLK1 the status will always read as programmed regardless of the state of the bits May affect applic
10. al 18 Doc Page 16 3 Figure 16 2 SDU Functional Block Dia gram i User s Manual 19 Doc Page 16 6 Section 16 3 3 Minimizing Latency 8 User s Manual 19 Doc Page 17 22 Section 17 9 Erasing the Flash Memory Block 9 User s Manual 19 Doc Page C 122 Table C 16 EPA13_TIME SFR 10 User s Manual 19 Doc Page C 65 Table C 11 Px_DIR Addresses and Reset States 11 User s Manual 20 Doc Page C 66 Table C 12 Px_MODE Addresses and Reset States 12 User s Manual 20 Doc Page C 67 Table C 13 Px_PIN Addresses and Reset States 13 User s Manual 20 Doc Page C 69 Table C 14 Px REG Addresses and Re set States 14 User s Manual 20 Doc Pages C 7 8 Table C 2 Register Name Address and Reset Value 15 User s Manual 20 Doc Page 2 20 Figure 2 9 CCR1 Register 16 User s Manual 20 Doc Page 15 19 Figure 15 7 CCR1 Register 17 272889 21 Doc Page 18 Section 6 0 Electrical Characteristics 18 272889 21 Doc Page 18 19 Table 6 1 DC Characteristics 19 User s Manual 21 Doc Page 9 22 Section 9 5 1 Consistent MSB bit length procedure in SSIO 20 User s Manual 21 Doc Page 10 28 Figure 10 21 Timer x Control TxCON TROL Register 21 User s Manual 21 Doc Page 10 7 Figure 10 2 EPA Timer Counters 22 User s Manual 22 Doc Page 10 15 Figure 10 7 EPAPWM Receive Transmit Channel 23 User s Manual 22 Doc Page 10 24 Section 10 7 Generating a 32 Bit Time Value 24 User s Manual 22 Doc Page 10 38 Figure 10 25 EPAPWMx Control Regis ter 25 User s Manual 22 Do
11. ations that program and verify the Uprom bits DEI and CLK1 Read the UPROM Special Function Register 1FF6h to determine the status of the Uprom bits Refer to 88SC196EC Microcontroller User s Manual P 17 40 NoFix Refer to Summary Table of Changes to determine the affected stepping s eEPA Concatenation In the EPAPWM control registers figure 10 25 in User s Manual bit 0 is defined as the Enable Module Concatenation bit This feature does not work on the device This bit should be set to a 0 NoFix Refer to Summary Table of Changes to determine the affected stepping s 88C196EC Microcontroller Specification Update 13 Errata 16 Problem Implication Status 17 Problem Implication Status 18 Status Implication Status 19 Problem Implication Workaround Status 20 Problem Implication Status LJ intel NMIE Interrupt Lost when PIH Interrupt Pending When a PIH interrupt is pending a NMIE interrupt will not be serviced Instead the pending PIH interrupt will be serviced even if it is globally disabled Interrupts will be incorrectly serviced under above described conditions Affects in circuit emulator designs only NOFix Refer to Summary Table of Changes to determine the affected stepping s ICE CSO Functionality CSO functionality is disabled while in ICE mode CSO pin cannot be emulated on emulator NoFix Refer to Summary Table of Changes
12. atus 8 Problem Implication Status 9 Problem Implication Status 10 Problem Implication Status 11 Problem Implication Status LJ intel P5 4 Medium Pull Up Enabled During TROM Execution mode The P5 4 pin had a medium pull up enabled when executing from test ROM execution mode A strong driver is needed to overdrive P5 4 to a low voltage to enter all test ROM execution modes excluding SDU mode Provide strong driver in application to overdrive the P5 4 pin to a low voltage Fixed Refer to Summary Table of Changes to determine the affected stepping s Reset Source CFD Bit The CFD bit was not correctly set in the reset source SFR register The bit was set to a 1 even though a reset due to the oscillator fail detect circuitry did not occur This problem occurred when the power supply ramp from 0 V to 5 V was too fast Affects applications that use the CFD bit to determine application flow Since nodes ND1 and PURS control reset signals which in turn control many different functions in the device other application uses may also be adversely affected Add external capacitors to the Vcc supply to slow the voltage ramp from 0 V to 5 V Fixed Refer to Summary Table of Changes to determine the affected stepping s SCNEN Pin ESD The SCNEN pin did not meet Intel s qualification requirements for ESD protection The SCNEN pin was sensitive to ESD Fixed Refer to Summary Table o
13. c Page 13 13 Figure 13 11 RSTSRC Register 26 User s Manual ee Doc Page C 86 RSTSRC Register 88C196EC Microcontroller Specification Update E Identification Information l ntel Identification Information Markings Bottom mark NG88C196EC 10 88C196EC Microcontroller Specification Update intel Errata Errata 1 Problem Implication Status 2 Problem Implication Status 3 Problem Implication Workaround Status 4 Problem Implication Workaround Status Unable to read EPA eEPA SFR registers During a read of the EPA and eEPA SFR registers there was contention found in the data bus that these two modules share This contention caused the values in both the EPA and eEPA registers to be read simultaneously Therefore the data was invalid Affected applications that read from these registers Fixed Refer to Summary Table of Changes to determine the affected stepping s PLLEN pin not latched on rising edge of reset The target specification for this device stated that the state of the PLLEN pin is latched at the rising edge of reset Thus any transitions during operation will have no effect upon the PLL The A 3 silicon did not contain the necessary logic to behave in this manner Noisy applications could cause the PLLEN pin to switch states during execution Fixed Refer to Summary Table of Changes to determine the affected stepping s Flash High Byte
14. cution NoFix Refer to the Summary Table of Changes to determine the affected stepping s 88C196EC Microcontroller Specification Update intel Specification Changes Specification Changes 1 Issue Implication Affected Docs 2 Issue Affected Docs 3 Issue Affected Docs Flash Program Erase Temperature Spec Operating temperature specifications for programming and erasing the on chip Flash on the 88C196EC has been changed from 40 C 125 C to 0 C 70 C Intel does not guarantee that the Flash programming and erasing capabilities will function correctly above 70 C and below 0 C 88C196EC CHMOS 16 Bit Microcontroller datasheet 272889 lou2 Specification The I op specification has been changed in the following manner e Old 30 HA to 120 HA VOER Vec 1 0 V 75 HA to 240 HA VOER Vcc 2 5 V e New 30 HA to 140 HA Von Vcc 1 0 V 88C196EC CHMOS 16 Bit Microcontroller datasheet 272889 PLLEN pin latched on reset On the 88C196EC A step the PLLEN pin was not latched on reset On the B step a latch was added to the PLLEN pin so that the state of the PLL can only be changed at the time of reset 88C196EC Microcontroller User s Manual 88C196EC Microcontroller Specification Update 15 LJ Specification Clarifications l ntel Specification Clarifications None for this revision of the specification update 16 88C196EC Microcontroller Specification Update L
15. e Status Doc Fix Fixed NoFix Eval Row Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page location of item in this document Document change or update will be implemented This erratum is intended to be fixed in a future step of the component This erratum has been previously fixed There are no plans to fix this erratum Plans to fix this erratum are under evaluation Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document 88C196EC Microcontroller Specification Update 7 Summary Table of Changes Errata Steppings No Page Status ERRATA A3 BO B1 B2 1 X 11 Fixed Unable to read EPA eEPA SFR registers p X 11 Fixed PLLEN pin not latched on rising edge of reset 2 X 11 Fixed Flash High Byte Access 4 X 11 Fixed CSO Strong Pull Up Enabled with EA 1 5 x 12 Fixed Aapa Enabled During TROM 6 X 12 Fixed Reset Source CFD Bit 7 X 12 Fixed SCNEN Pin ESD 8 X 12 Fixed eEPA Transmitter 9 X 12 Fixed PIH Lost Interrupts 10 X 12 Fixed Vi Specification Marginality 11 X 12 Fixed NMI Pull Up Strength 12 X 13 Fixed AD15 Bus Control 13 X X X 13 Fixed Port Ini
16. er RAM do not count in most cases since the CPU directly accesses the register file Therefore it is necessary to understand what the bus controller is doing in the user application at all times to minimize latency Affected Docs 88C196EC Microcontroller User s Manual 8 Page 17 22 Section 17 9 Erasing the Flash Memory Block Issue The second paragraph in section 17 9 is incorrect P2 0 does not go low if an erase failure occurs Old The erase routine has the effect of driving pin P2 6 to a logic 0 if the erase failed and driving pin P2 0 to a logic 0 for a period of 15 state times New The erase routine has the effect of driving pin P2 6 to a logic 0 if the erase failed Affected Docs 88C196EC Microcontroller User s Manual 9 Page C 122 Table C 16 EPA13_TIME SFR Issue Register location for EPA13_TIME is incorrect The correct location is 1F3Eh e Old Register Memory 32 Byte area 64 Byte danser si 128 Byte ao Mnemonic Location WSR mee WSR eel WSR ER Address Address Address EPA13 TIME 1F2Ah 79H EAH 3CH EAH 1EH AAH e New Register Memory 32 Byte derd 64 Byte mees 128 Byte oo Mnemonic Location WSR Address WSR Address WSR Address EPA13 TIME 1F3Eh 79H FEH 3CH FEH 1EH BEH Affected Docs 88C196EC Microcontroller User s Manual 10 Page C 65 Table C 11 Px DIR Addresses and Reset States Issue P6 DIR register address is incorrect It should be 1FE3h not 1FD3h Affected Docs 88C196EC
17. f Changes to determine the affected stepping s eEPA Transmitter An eEPA would not reset its associated pin if a match within the same eEPA occurred simulta neously eEPA events may be missed Fixed Refer to Summary Table of Changes to determine the affected stepping s PIH Lost Interrupts When a read from the PIH interrupt pending register occurred at the same time as an incoming interrupt the new interrupt was lost Interrupts may be lost Fixed Refer to Summary Table of Changes to determine the affected stepping s Vi Specification Marginality Vr was marginal to target specifications causing yield fallout Device may not work with other devices depending on how clean their input low signal is Fixed Refer to Summary Table of Changes to determine the affected stepping s NMI Pull Up Strength NMI Pull Up Strength was not strong enough to meet target specifications NMI pin could cause an interrupt by going low due to weak pull up Fixed Refer to Summary Table of Changes to determine the affected stepping s 88C196EC Microcontroller Specification Update intel 12 Problem Implication Status 13 Problem Implication Status 14 Problem Implication Workaround Status 15 Problem Status Errata AD15 Bus Control Address Data pin 15 may intermittently fail after the execution of a Ljmp instruction This pin may be read as a one instead of a zero because of
18. n 9 5 1 Consistent MSB bit length procedure in SSIO Inserted Disable Interrupts between steps and 2 in procedure for achieving a consistent MSB bit length 88C196EC Microcontroller User s Manual Page 10 28 Figure 10 21 Timer x Control TXCONTROL Register UD bit description incorrectly states that the T2CONTROL direction bit controls the direction of both timers 1 and 2 when in concatenation mode TICONTROL direction bit actually controls the direction of both timers 1 and 2 when in concatenation mode e Old If TZCONTROL 7 is set this bit in T2CONTROL controls the direction of both timers 2 and 1 e New If T2CONTROL 7 is set this bit in TICONTROL controls the direction of both timers 2 and 1 88C196EC Microcontroller User s Manual Page 10 7 Figure 10 2 EPA Timer Counters When timer concatenation is enabled the OVRTM1 signal from timer 1 does not go through the timer 2 prescalar module To fix the diagram the 2x1 multiplexer for T2CONTROL 7 should be switched with the Prescalar module The input to the prescalar module will now be the output from the 2x1 multiplexer for TZCONTROL 4 3 and the output will go into the 2x1 multiplexer for T2CONTROL 7 along with the OVRTMI signal The output of the 2x1 multiplexer for T2CONTROL 7 will go to clock 88C196EC Microcontroller User s Manual 88C196EC Microcontroller Specification Update 21 LJ Documentation Changes l ntel 22 Issue Affected Docs 23 Issue
19. ns describe a specification in greater detail or further highlight a specifications impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the specification Errata remain in the specification update throughout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals etc 88C196EC Microcontroller Specification Update intel Summary Table of Changes Summary Table of Changes The following table indicates the errata specification changes specification clarifications or documentation changes which apply to the 88C196EC microcontroller product Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted This table uses the following notations Codes Used in Summary Table Stepping X No mark or Blank box Page Pag
20. ontroller User s Manual Page 16 1 Figure 16 1 SDU Block Diagram Code RAM size in SDU block diagram is incorrect The diagram should specify 2 75 Kbytes of Code RAM not 3 Kbytes 88C196EC Microcontroller User s Manual Page 16 3 Figure 16 2 SDU Functional Block Diagram Code RAM size and Test ROM size in SDU Functional Block Diagram is incorrect The diagram should specify 2 75 Kbytes of Code RAM not 3 Kbytes and 4 Kbytes of Test ROM not 1 Kbyte 88C196EC Microcontroller User s Manual 88C196EC Microcontroller Specification Update intel Documentation Changes F Page 16 6 Section 16 3 3 Minimizing Latency Issue Entire section is not worded correctly e Old The issue of latency arises when the SDU starts a cycle and the bus controller wants to use the code RAM in the next state If any user application is executing from code RAM when the SDU is attempting to access the code RAM you will incur a significant performance decline in your code RAM accesses Even if the bus controller is idle the SDU cannot access the code RAM without some small effect Because accesses to the code RAM by the SDU require at least two CPU state times it is necessary to understand what the bus controller is doing at all times to ensure that any latency will be minimized New The SDU can only access the code RAM when the bus controller is starting an access to memory other than code RAM i e Flash or external memory Accesses to regist
21. roller User s Manual Page 15 19 Figure 15 7 CCR1 Register CFD bit definition is incorrect The enable and disable bits are reversed e Old 0 enables clock failure detection circuitry 1 disables clock failure detection circuitry e New 0 disables clock failure detection circuitry 1 enables clock failure detection circuitry 88C196EC Microcontroller User s Manual 88C196EC Microcontroller Specification Update E intel 17 Issue Affected Docs 18 Issue Affected Docs 19 Issue Affected Docs 20 Issue Affected Docs 21 Issue Affected Docs Documentation Changes Page 18 Section 6 0 Electrical Characteristics Added Note 4 to Tc under Operating Conditions Note 4 states Flash programming and erase operations only guaranteed to work from 0 C to 70 C 88C196EC CHMOS 16 Bit Microcontroller datasheet 272889 Page 18 19 Table 6 1 DC Characteristics Changed the following DC Characteristic Parameters 1 Ipp Typical changed from 20 HA to 50 uA Max value no longer specified Ton Max with Vox Vcc 1 0 V changed from 120 HA to 140 HA Iona Min with Voy Vcc 2 5 V changed from 75 HA to 65 HA IoH2 Max with Vou Vcc 2 5 V changed from 240 HA to 280 HA Iona Min with Vou Vcc 4 0 V changed from 90 HA to 75 HA 6 IoH2 Max with Voy Vcc 4 0 V changed from 280 HA to 350 HA 88C196EC CHMOS 16 Bit Microcontroller datasheet 272889 Page 9 22 Sectio
22. tialization 14 X X X X 13 NoFix Odd Uprom Bit Read from TROM 15 X X X X 13 NoFix eEPA Concatenation 16 X X X X 14 NoFix NMIE Interrupt Lost when PIH Interrupt Pending 17 X X X 14 NoFix ICE CSO Functionality 18 X X X 14 NoFix RSTSRC Register Clear on VCC Power up 19 X X X 14 NoFix Reset During Code RAM Read Operation 20 X X X 14 NoFix Stack Overflow Module Specification Changes Steppings No Page Status SPECIFICATION CHANGES A3 BO B1 B2 1 X X X X 15 Doc Flash Program Erase Temperature Spec 2 15 Doc Ione Specification 3 X X X 15 Doc PLLEN pin latched on reset Specification Clarifications Steppings No A3 BO B1 B2 Page Status SPECIFICATION CLARIFICATIONS None in this revision 88C196EC Microcontroller Specification Update Documentation Changes Summary Table of Changes No Document Revision Page Status DOCUMENTATION CHANGES 1 User s Manual 17 Doc Page 6 3 Figure 6 2 Interrupt Service Flow Diagram 2 User s Manual 17 Doc Page A 20 Table A 6 IDLPD Instruction Definition 3 User s Manual 18 Doc Page 11 10 Figure 11 5 A D Command AD COMMAND Register 4 User s Manual 18 Doc Page 11 11 Section 11 5 Determining A D Status and Conversion Results 5 User s Manual 18 Doc Page 16 1 Figure 16 1 SDU Block Diagram 6 User s Manu
23. ype called the Specification Update We have endeavored to include all documented errata in the consolidation process however we make no representations or warranties concerning the completeness of the Specification Update This document is an update to the specifications contained in the Affected Documents Related Documents table below This document is a compilation of device and documentation errata specification clarifications and changes It is intended for hardware system manufacturers and software developers of applications operating systems or tools Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents This document may also contain information that was not previously published Affected Documents Related Documents Title Order 88C196EC CHMOS 16 Bit Microcontroller datasheet Automotive 272889 88C196EC Microcontroller User s Manual 272890 Nomenclature Note Errata are design defects or errors These may cause the 88C196EC microcontroller s behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarificatio

88C196EC Microcontroller

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