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ElanSC400 and ElanSC410 Microcontrollers User`s Manual

1. IX XIXIX X X IX XIXIX IX XIX IX IX XIXIX X X X XC IXIXIXIXIX X X X be gt lt gt DX gt gt gt lt gt gt pe gt pe gt lt I lt gt lt pe gt lt pe pe pe pe p gt gt lt gt pe gt gt p gt p gt gt lt gt lt px gt lt gt 54 p p pe pe x lt px x lt x lt gt lt lt gt lt gt pe lt gt pe gt lt gt 54 gt gt lt gt lt lt pe gt pe lt pe gt lt gt lt pe x lt pe lt x lt pe gt lt gt gt pe gt gt pe gt
2. 21 EL 1 Hh soiseg 2 W JS S p LHYN HOd jeues 91 seoepuelu 91 1ndino ndu 81 Jejouo PILED 61 S 10 0 9 Introduction Jo 043u02 soiudeuo OZ pue 159 IZ eoeneju use 4 INOH 8 Jejoguo WVHA 6 suonounj pexejdninw Y uoneuluJ9 uld J9jo4uo OF LL 1u91u02 1 4 1 jenueyy SA SN OLP2SUE 3 009 sasn 0LpOSUe 3 00725 uela xxiv RELATED DOCUMENTS AMD Documentation The following AMD documents provide additional information about the lanSC400 and ElanSC410 microcontrollers In addition to this manual the documentation set for the Elan
3. 3 3 3 5 System Management Mode SMM 3 3 3 5 1 Uses of SMM 3 3 3 5 2 SMM Requirements 3 4 3 5 8 System Management Random Access Memory SMRAM 3 4 3 5 4 System Management Interrupt 5 3 5 3 5 4 1 State 5 3 6 3 5 5 SMM Execution Environment 3 8 3 5 6 Exceptions and Interrupts 3 9 3 5 7 Auto Halt Restart llle 3 10 3 5 8 VO Tapping sf ed ecd eb dae the yas 3 10 3 5 8 1 Restarting I O 1 5 5 3 10 3 5 8 2 Emulating I O 3 11 3 5 9 SMM Base Relocation Example 3 11 3 5 10 SMM Interaction With SRESET 3 17 3 6 CPU Core Identification Using the CPUID Instruction 3 18 3 64 CPUID s date ER pe em eke pem bead 3 18 3 6 2 CPUID Operation 3 19 3 6 8 3 20 SYSTEM INTERFACES 4 1 41 lnilalization RARE BEE x eR AR E nen 4 1 41 1 Types of Reset 4 1 4 1 1 1 Power On 4 2 4 1 1 2 Am486 CPU DX Register at CPU
4. Activity Source Enable 22h 23h Activity source enable CPU access to parallel page 3 74 Register D Index 65h port PC Card Socket A PC Card Socket B internal system registers also enables PC Card Ring Indicate and PC Card INTR Activity Source Status Register A 22h 23h Activity source status CPU access to UART page 3 75 Index 66h internal graphics and memory ROMCS2 ROMCSO and VL bus cycle Activity Source Status Register B 22h 23h Activity source status CPU access to DRAM page 3 76 Index 67h matrix key pressed timer tick interrupt keyboard timer time out and keyboard registers Activity Source Status Register C 22h 23h Activity source status CPU access to external page 3 77 Index 68h VGA controller I O and memory floppy controller registers and IDE hard drive registers DMA request ACIN signal UART RIN pin and UART SIN pin Activity Source Status Register D 22h 23h Activity source status CPU access to parallel page 3 78 Index 69h port PC Card Socket A PC Card Socket B internal system registers also enables PC Card Ring Indicate and PC Card INTR Activity Classification Register A 22h 23h Primary and secondary activity classification page 3 79 Index 6Ah CPU access to UART internal graphics and memory ROMCS2 ROMCSO and any VL bus cycle Activity Classification Register B 22h 23h Primary and secondary activity classification page 3 80 Index 6Bh CPU access to DRAM
5. 4 17 Table 4 8 CFG3 Configuration 2 tees 4 17 Table 4 9 Boundary Scan Function 4 18 Table 4 10 Byte Lanes scs csse eee kx xe 4 19 Table 4 11 Byte Lanes by Access Target and Type 4 20 Table 4 12 ISA Interface Register 5 4 25 Table 4 13 ISA Interface 5 0 5 4 28 Table 4 14 Signals Shared with the ISA Interface 4 28 Table 4 15 ISA DMA Cycle lt 4 30 Table 4 16 Power Management in the ISA Bus 4 34 Table 4 17 VL Bus Register 5 4 35 Table 4 18 VL Bus Data Bus Byte Ordering 4 37 Table 4 19 Special Bus Cycles 4 38 Table 4 20 Power Management in the VL Bus 4 38 Table 5 1 PMU Controller Register 5 5 3 Table 5 2 PMU Wake Up 5 21 Table 5 3 SMI NMI Sources 1 2 0 0 0000 ct teens 5 31 Table 5 4 VO Trap SOUICES 5 32 Table 5 5 Activity Sources 2 5 35 Table 6 1 Clocking Register 5
6. 20 20 20 4 5 3 FON S 2 20 20 20 4 6 Flat Mapped Graphics Modes 20 23 20 4 6 1 Example 640x240 Panel Flat Mapped Mode 20 24 20 4 6 2 Example 640x480 Panel Flat Mapped Mode 20 27 20 4 6 3 Flat Mapped Graphics Mode Data Formats 20 27 20 4 7 Grayscale 20 29 20 4 7 1 Four Color Grayscale Encoding 20 29 20 4 7 2 16 Color Grayscale 20 29 20 4 8 Configuring Graphics Modes 20 32 20 4 8 1 Screen Controller Registers 20 32 20 4 8 2 Dual Scan Panel 20 33 20 4 9 LCD Data Formatting 20 35 20 4 9 1 Monochrome Single Scan Panels 20 36 20 4 9 2 Monochrome Dual Scan Panels 20 37 20 4 9 3 Color STN Single Scan Panels 20 38 20 5 Initialization llle RII 20 38 20 6 Power 20 39 20 6 1 Normal 20 39 20 6 2 Normal Power Down 20 39 20 6 3 Emergency Power Down 20 39 TEST AND DEBUGGING 21 1 21 1 OVerview REID ARE RUPEE TESTEN E ns 21 1 21 2 Boundary Scan Architecture
7. 6 1 Table 6 2 Integrated Peripheral Clock 6 4 Table 6 3 Frequency Selection Control for Graphics Dot Clock 6 6 Table 6 4 Clock Speeds e RYE 6 9 Table 6 5 Bus Cycle Clock Speeds 6 10 Table 6 6 Clock Speed Per PMU 6 12 Table 7 1 Memory Management Unit Register Summary 7 1 Table 8 1 ROM Flash Interface Register 8 1 Table 8 2 Pin Strap Bus Buffer 5 8 8 Table 8 3 ROMCSx Configuration Dependencies 8 11 Table 8 4 Power Management in the ROM Flash 8 11 Table 9 1 DRAM Controller Register Summary 9 3 Table 9 2 System Address to CAS Strobe Mapping 9 6 Table 9 3 Supported DRAM Bank 9 7 Table 9 4 Non Interleaved System Address A to Memory Address MA Mapping 9 8 Table 9 5 Interleaved System Address A to Memory Address MA Mapping 9 10 Table 9 6 Power Management in the DRAM 9 15 Table 10 1 DMA Controller Register Summary 10 3 Table 10 2 8 Bit DMA Ch
8. 5 32 5 4 13 1 Using the Activity Source Flag Registers 5 33 5 4 14 State Options in PMU Modes 5 36 5 4 14 1 Suspend State 5 36 5 4 14 2 Programmable Pull Up and Pull Down Options 5 36 5 5 Initializatlon re x ere eu RARO ERR A 5 36 CLOCK CONTROL 6 1 6 1 OVervIOW geras PRODR E ads 6 1 6 2 cake ges ree RO RO ee Eod 6 1 Block Diagram eeu dates 6 1 6 4 Op ration us e Ro cat RR De M M CR 6 3 6 4 1 Clock Generation 6 3 6 4 1 1 32 KHz Crystal Oscillator 6 5 6 4 1 2 Intermediate and Low Speed 6 5 6 4 1 3 Graphics Dot Clock PLL 6 6 6 4 1 4 High Speed PLL 6 7 6 4 2 Clock Control ad EE 6 8 6 4 2 1 1 6 8 6 4 2 2 Memory 6 8 6 4 2 3 Timer 6 8 6 4 2 4 2 6 8 6 4 2 5 2 6 8 6 4 2 6 aa madaha Daaa ada ea 6 8 6 4 2 7 DMA 6 8 6 5 I
9. Command strobes 38 IOCS16 MCS16 IOCHRDY AEN TC PDACK1 Control DMA PDRQO PDRQ1 Interrupts PIRQO PIRQ1 PIRQ2 Reset RSTDRV System Interfaces 4 27 4 7 4 Table 4 13 Supported ISA Signals The ISA interface on the lanSC400 and lanSC410 microcontrollers uses the signals listed in Table 4 13 The ISA signals shown as optional in Table 4 13 are shared with other functions on the ElanSC400 and ElanSC410 microcontrollers Table 4 14 lists the signals that are traded off for ISA signals The signals are grouped by enable bit ISA control signals IOCHRDY and IOCS16 and MCS16 are available via a programmable option IOCHRDY can be deasserted to extend the length of ISA ROM cycles 516 and MCS16 can be asserted on a cycle basis to generate 16 bit ISA I O or memory transfers respectively 516 and MCS16 are ignored during ROM PC Card or DRAM cycles IOCS16 and MCS16 are also ignored for accesses to internal I O devices and VL bus cycles Signals not supported by the ISA interface include MASTER REFRESH IOCHCHK OSC 14 318 MHz SYSCLK and OWS ISA Interface Signals Function External Signals Data Bus SD15 SD0 Address Bus SA23 SA0 Control Signals BALE IOCS16 MCS16 SBHE IOCHRDY Optional DBUFRDL DBUFRDH DBUFOE Command Strobes IOR IOW MEMR MEMW Dedicated Reset RSTDRV Dedicated
10. 10 4 2 3 Priority nell rete exe Re 10 4 2 4 DMA Cycles 10 4 3 Channel Mapping 10 4 4 Latency 10 5 InitialIgzation a RII 10 6 Power PROGRAMMABLE INTERRUPT CONTROLLER 11 1 Overview hrs IAE 11 3 Block Diagram eh TAA Operation cibis Ee e acis e cen eee a RE PERO E 11 4 1 IRQ 11 4 2 Interrupt 5 11 5 Initialization 0 eee 11 6 Power Management 0 00 ete PROGRAMMABLE INTERVAL TIMER 12 1 Overview amra hse 122 Registers Doe 12 2 1 Direct Mapped Registers 12 3 Block Diagram 22200004404 ee 12 4 Operation 12 4 1 Modes of Operation 12 4 1 1 Mode 0 Interrupt on Terminal Count 12 4 1 2 Mode 1 Hardware Retriggerable One Shot 12 4 1 3 Mode 2 Rate 12 4 1 4 Mode 3 Square Wave Mode 12 4 1 5 Mode 4 S
11. RASi RASO MA11 MAB 4 CFG3 MA CFG2 1 MAO CFGO 015 00 015 00 031 016 gt SA25 SA0 ROMCS1 ROMCSO RSTDRV MCEL BBNDSCN MCEH_A BNDSCN TMS RST A BNDSCN REG A BNDSCN TDOJ 4 BVD1 A BVD2 A 6 _ 4 WE ICDIR GPIO31 STRB MCEL_B GPIO30 AFDT MCEH B GPIO29 SLCTIN RST BJ GPIO28 INIT REG BJ GP1027 ERROR GP1026 PE RDY_B 25 BVD1_B GP1024 BUSY BVD2_B GPIO23 SLCT WP_B GPIO22 PPOEN 1 PPDWE 32KXTAL1 32KXTAL2 LF_INT LF_LS LF VID LF HS RESET VRTC gt BBATSEN SPKR BNDSCN_EN DRAM Interface and Feature Configuration Pins DRAM VL ROM ISA and PC Card Data VL ROM ISA and PC Card Address ROM Flash Control PC Card Command ISA Bus Command and Reset Dedicated Single Slot PC Card and Boundary Scan Interface Parallel Port or Second PC Card or GPIOs 32 KHz Crystal Loop Filters Reset RTC Speaker Boundary Scan Enable Note Two functions available on the at the same time Function during hardware reset Alternative function selected by firmware configuration 1 Alternate function selected by a hardware configuration state at power on reset 4 14 System Interfaces Figure 4 2 VESA Local Bus 8 Pin Serial Port IrDA Interface Power Management Interface G
12. 519114 doo 00t 2SUeI3 preog oy L 10 10 si jeu einjee e sejeoipui pausep Ho m 2 r 1 r r p10M LAVad LAVHG g yueg Xueg yueg 0 Xueg 615 19 2 c Architectural Overview 1 18 troller icrocon th Trade offs lanSC410 lagram WI System D Figure 1 5 20 0 uod dnyoeg yoye7 pue 1ejng Ho Ho DER 01 PEE d 49 4 VS VSI 615 15 H ZHM 25 45 MO sng 1A J9j041u0520J9 IN OLVOSUe A SMOH wo sng LL uBIH MO r l pueoghsy G o 10 PAP 10 jeu enjeaj e pausep 3 yueg yueg yueg 0 1 19 Architectural Overview 1 20 Architectural Overview EN AMD 2 CONFIGURATION BASICS gt 2 1 OVERVIEW This chapter provides basic information about configuring the
13. 7 11 7 7 2 52 Operation 7 11 7 7 3 Memory Mapping and Caching 7 11 7 7 3 1 Caching in System Management Mode 7 12 CHAPTER8 ROM FLASH INTERFACE 8 1 81 Overview ule edle Era dr ee kx Ud e d 8 1 8 2 REJSIE cesse bk set pa 8 1 8 3 Block Diagram eme m tenet 8 2 3 4 Operation Lu ac dO Gb a REG BURG OL TOR LS 8 3 841 Architectural Overview 8 3 8 4 2 Data Bus Usage 8 4 8 5 eren es E ee Ae we ee ee ee ee ee 8 6 8 5 1 Configuring the ROMCSO Interface Using Pin Straps 8 7 8 5 2 Other ROMCSx Interface Configuration Options 8 8 8 5 2 1 Data Width 8 8 8 5 2 2 Access 8 9 8 5 2 3 5 8 10 8 6 Power 8 11 9 DRAM CONTROLLER 9 1 91 System 9 1 9 2 REJSIE E a RUE ee Re Ro V 9 3 9 3 Block Diagram gee PAD ters 9 4 9 4 Operation ciue Rma due xat e RR ADR UR DA 9 5 9 4 1 System Address Decoding 9 5 9 4 1 1 R
14. CGA MDA Character Bit 7 0 CA7 CA6 CA5 CA4 Attribute Byte The attribute byte defines the qualities of a character as displayed on the screen defining the character color intensity blinking etc The attribute byte is defined differently for CGA and MDA modes Following are the byte definitions for CGA and MDA compatible attribute bytes Figure 20 10 CGA Attribute Byte Table 20 5 Bit 7 0 BLINK BAK2 BAK1 BAKO INTEN FOR2 FOR1 FORO Bit Name R W Function 2 0 FORO 2 R W Foreground color 3 INTEN R W Intensity of character 0 Normal Intensity 1 High Intensity 6 4 2 R W Background color 7 BLINK R W Blinking if Port O3D8h bit 5 1 If Port O3D8h bit 5 0 then this is the background intensity bit 0 Not Blinking 1 Blinking CGA Attribute Byte Foreground Color Red Blue Intensity 0 Intensity 1 0 0 Black Dark gray Blue Light Blue Green Light Green Cyan Light Cyan Red Light Red Magenta Light Magenta Brown Yellow Light gray White 0 0 0 0 1 1 1 1 Graphics Controller 20 17 Table 20 6 CGA Attribute Byte Background Color Cea Color Port 03D8h 5 0 Port 03D8h 5 1 or Port 03D8h 5 1 and Blink 0 and Blink z 1 Black Dark gray Blue Light Blue Green Light Green Cyan Light Cyan Red Light
15. 5 14 Table of Contents vii viii CHAPTER 6 5 4 5 5 15 5 4 5 1 Actions Taken During Suspend Mode 5 15 5 4 5 2 Entering Suspend 5 15 5 4 5 8 Leaving Suspend Mode 5 15 5 4 6 Critical Suspend Mode 5 16 5 4 6 1 Actions Taken During Critical Suspend Mode 5 16 5 4 6 2 Entering Critical Suspend Mode 5 16 5 4 6 3 Leaving Critical Suspend Mode 5 16 5 4 7 Temporary Low Speed Mode 5 17 5 4 7 1 Actions Taken During Temporary Low Speed Mode 5 17 5 4 7 2 Entering Temporary Low Speed Mode 5 17 5 4 7 3 Leaving Temporary Low Speed Mode 5 18 5 448 PMU 5 19 5 4 9 Wake Up Sources 5 21 5 4 10 General Purpose I O GPIO Pins 5 24 5 4 10 1 GPIO PMUA GPIO PMUD Signals 5 24 5 4 11 Detect and Battery Low 5 24 ACIN cess dai deae a dro ele o tes 5 25 5 4 11 2 Battery 5 25 5 4 12 SMI NMI 5 30 5 4 12 1 Access 5 5 5 31 5 4 13 Activity
16. 7 Enabled P Routine Finished 4 y 4 d i p P SMI NMI N Z Routine 2 Finished Timer x cd on acd amp Wake up Timer Enabled Time out amp SMI NMI Enabled d amp notWake up ODE N 2 Ne 5 20 Power Management 5 4 9 Table 5 2 AMD Wake Up Sources Several options are available to wake up the system from Suspend mode Table 5 2 shows the wake up sources The Suspend and wake up resume mode flow is diagrammed in Figure 5 4 The wake up trigger is only valid to take the system from Suspend mode to High Speed or Low Speed mode Some of the BL2 BLO signals can limit the PMU modes to Low Speed see Section 5 4 11 2 The wake up trigger has no use in any mode except Suspend If Temporary Low Speed mode was entered from Suspend then wake ups can be detected and the PMU will wake up from Temporary Low Speed it will not go back to Suspend mode to wake up When receiving a wake up in Suspend mode any section of the PMU that has its clock disabled must be clocked again Next the PMU can start up the PLLs if they were programmed to be off gate the clocks and resume the system PMU Wake Up Sources Wake Up Sources Description ACIN signal The ACIN signal rising or falling edge can cause a wake up BL2 BLO signals Any of the BL2 BLO signals rising or falling edge can cause a wake up SUS RES signal The
17. 5 4 7 3 5 18 Leaving Temporary Low Speed Mode The system leaves Temporary Low Speed mode when one of the following occurs Temporary Low Speed mode timer times out Ifthe last mode was Standby the system returns to Standby otherwise it goes to Suspend Programmed directly out with the PMU Force Mode Register go to any other mode The 505 RES signal toggles f enabled and Temporary Low Speed mode was called from Standby mode forces the system to Suspend mode f enabled and Temporary Low Speed was entered as an SMI NMI service routine from Suspend mode the SUS RES signal causes a transition to High Speed or Low Speed mode A primary activity is detected and Suspend was not the last mode Goes back up to High Speed mode 812 goes Low programmable option 812 causes a mode change to Critical Suspend mode if ACIN is not enabled and asserted Wake up detected f Temporary Low Speed mode was entered from Suspend wake ups can be detected and cause a mode change to High Speed or Low Speed mode Power Management 5 4 8 Figure 5 2 AMD PMU Flowcharts The flowcharts in Figure 5 3 Figure 5 8 diagram the flow between modes for each of the major events timers activities wake ups resume BLO and and BL2 with the SMI flows for each The following conventions apply to the flowcharts in this chapter Clock speeds shown in boldf
18. 21 8 21 3 1 14Pause IR 21 8 21 3 1 15Exit2 IR 21 8 21 3 1 16Update IR State 21 8 21 3 2 Order of Scan Cells in Boundary Scan Path 21 8 21 3 2 1 Instruction Path lille 21 8 21 3 2 2 Bypass Path 21 8 21 3 2 3 Main Data Scan Path 21 8 APPENDIX A MULTIPLEXED PIN CONFIGURATION CONTROL A 1 APPENDIXB PIN TERMINATION B 1 INDEX 1 1 Table of Contents xvi LIST OF FIGURES Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 2 1 Figure 2 2 Figure 3 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 7 1 Figure 7 2 Figure 8 1 Figure 8 2 Figure 9 1 Figure 10 1 Figure 11 1 Figure 12 1 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 15 1 Figure 15 2 Figure 16 1 Figure 16 2 Figure 16 3 Figure 17 1 ElanSC400 Microcontroller Block Diagram 1 3 ElanSC410 Microcontroller Block Diagram 1 4 Typical Mobile Terminal Design
19. c ces ye ak o Ri e Manner x et RU RA a 4 39 4 9 2 1 Direct Mapped Registers 4 39 POWER MANAGEMENT 5 1 51 OVervieW sexe a a Pad e RS un 5 1 SLI Terms 5 1 5 2 5 21 PMU Mode Control and Status Registers 5 2 5 3 Block Diagram oem e ee ee enn 5 8 5 4 Operation ecc dee ROB GU er Ae de 5 9 5 4 1 Hyper Speed Mode 5 10 5 4 1 1 Actions Taken During Hyper Speed Mode 5 10 5 4 1 2 Entering Hyper Speed 5 11 5 4 1 3 Leaving Hyper Speed 5 11 5 42 High Speed Mode 5 11 5 4 2 1 Actions Taken During High Speed Mode 5 12 5 4 2 2 Entering High Speed 5 12 5 4 2 3 Leaving High Speed Mode 5 12 5 43 Low Speed Mode 5 13 5 4 3 1 Actions Taken During Low Speed Mode 5 13 5 4 8 2 Entering Low Speed 5 13 5 4 8 3 Leaving Low Speed mode 5 13 5 4 4 Standby Mode 5 14 5 4 4 1 Actions Taken During Standby Mode 5 14 5 4 4 2 Entering Standby 5 14 5 4 4 3 Leaving Standby Mode
20. 16 3 4 Keyboard The XT keyboard interface in the lanSC400 and ElanSC410 microcontrollers is compatible with IBM s PC XT keyboard The interface includes the bidirectional clock and data signals XT CLK and XT DATA These pins are driven by open drain drivers with optional weak internal pull up resistors If a system design requires a reset pin for the XT keyboard interface an additional output pin such as one of the GPIO pins can be used 16 3 4 1 Interrupts When a serial keyboard byte has been assembled an XT Keyboard Byte Received interrupt is generated on IRQ1 The software should respond to the interrupt by reading the byte assembled in the keyboard data shift buffer at Port 0060h The programmer also has the option of driving the clock pin Low as an additional handshake indication After reading the byte at Port 0060h the program clears the keyboard data shift buffer and interrupt by writing Port 0061h 7 High then Low again This action not only clears the shift buffer and interrupt but also releases the data line to be an input again The Keyboard Configuration Register A CSC index COh 4 provides IRQ1 control for the XT keyboard interface Table 16 3 shows the effect of setting this bit on IRQ1 generation Table 16 3 IRQ1 Generation XT Keyboard XTInterrupt Enabled Effect of Setting CSC Index Bit COh 4 External No effect None No effect None No effect None Allows IRQ1 to be generated a
21. 21 1 21 2 1 Enabling the Boundary Scan Interface 21 1 21 2 2 Test Data Registers 21 2 21 2 2 1 Bypass Register 21 2 21 2 2 2 Boundary Scan Register BSR 21 2 21 2 2 3 Device Identification Register DID 21 2 21 2 3 Instruction Register and Implemented Instructions 21 3 21 2 3 1 Test Access Port Instruction 21 3 Table of Contents 21 3 Test Access Port Controller 21 5 21 3 1 TAP Controller States 21 5 21 3 1 1 Test Logic Reset State 21 5 21 3 1 2 Run Test ldle 21 6 21 3 1 3 Select DR Scan 21 6 21 3 1 4 Capture DR State 21 6 21 3 1 5 Shift DR State 21 6 21 3 1 6 Exit1 DR State 21 6 21 3 1 7 Pause DR State 21 6 21 3 1 8 Exit2 DR State 21 7 21 3 1 9 Update DR 21 7 21 3 1 10Select IR Scan State 21 7 21 3 1 11Capture IR State 21 7 21 3 1 12Shift IR State 21 7 21 3 1 13Exit1 IR
22. Table 10 5 ISA DMA Cycle Types one Data Transfer Direction ISA Command DMA Initiator DMA Target DMA Cycle Type Strobes Generated ISA ISA to Memory DMA Write MEMW IOR ISA PC Card I O to Memory DMA Write ISA DRAM to Memory DMA Write PC Card ISA I O to Memory DMA Write ISA ISA Memory to I O DMA Read PC Card ISA Memory to I O DMA Read ISA PC Card Memory to I O DMA Read ISA DRAM Memory to I O DMA Read 10 4 3 DMA Channel Mapping DMA requests may originate from the following sources Infrared port always 8 bits PC Card bus 8 bits or 16 bits using WP A WP B BVD2_A or BVD2 B ElanSC400 microcontroller only ISA bus using PDRQ1 PDRQO and PDACK1 PDACKO 8 bits or 16 bits Note that any channel mapped for use with the infrared port must not be programmed for block mode Table 10 6 shows the microcontroller resource and the DMA channels to which the resource can be mapped All DMA channel mapping in the lanSC400 and lanSC410 microcontrollers is programmable using CSC index DBh and DCh The DMA Resource Channel Map Registers A andB should be programmed consecutively to prevent two resources from being mapped to the same channel Table 10 6 DMA Channel Mapping DMA Channel Microcontroller Resource Infrared Port PC Card Controller Sockets A and B ElanSC400 microcontroller only PDRQO PDACKO Programmable DMA Channel PDRQ1 PDACKT Programmable DMA
23. 5 4 4 5 4 4 1 5 4 4 2 5 4 4 3 5 14 Standby Mode This mode is used when there is no activity in the microcontroller and many clocks can be shut down When an enabled activity occurs the PMU switches to the appropriate mode Actions Taken During Standby Mode The following actions are taken in the ElanSC400 and ElanSC410 microcontrollers during Standby mode B The CPU clock is stopped A summary of clock speeds PMU mode is shown Table 6 6 The internal LCD graphics controller can be programmed to be enabled or disabled The High Speed PLL can be shut off Entering Standby Mode The system goes to Standby mode when any of the following occurs B The Low Speed mode timer times out Programmed directly with the PMU Force Mode Register Return from Temporary Low Speed mode when the Temporary Low Speed timer times out When Temporary Low Speed mode was entered from Standby mode Leaving Standby Mode The system leaves Standby mode when any of the following occurs The Standby mode timer times out Drops to Suspend mode A primary activity is detected Goes back up to High Speed or Low Speed Mode based on BL2 or secondary activity is detected Goes to Temporary Low Speed mode The Standby timer is paused while in Temporary Low Speed mode The count down continues when Standby mode is re entered The timer is not reset by this mode change 812 go
24. 1 1 1 1 1 lanSC400 1 2 1 1 2 lanSC410 1 2 1 2 Architectural 1 5 1 2 1 Low Voltage Am486 CPU 1 6 1 2 2 Power Management 1 6 1 2 3 Clock 1 6 1 24 ROM Flash Interface 1 7 1 25 __ 1 7 1 2 6 Integrated Standard PC AT Peripherals 1 8 1 2 6 1 Dual DMA Controllers 1 8 1 2 6 2 Dual Interrupt Controllers 1 8 1 2 6 3 Programmable Interval Timer 1 9 1 2 6 4 Real Time Clock 1 9 1 2 6 5 PC AT Support 1 9 1 2 7 Bidirectional Enhanced Parallel Port 1 9 1 2 8 Serial ics see ex done em toes E Rx eR d 1 10 1 2 9 Keyboard Interfaces 1 10 1 2 10 Programmable General Purpose Inputs and Outputs 1 11 1 2 41 Infrared Port Rx RE 1 11 1 2 12 Dual PC Card Controller ElanSC400 Microcontroller Only 1 11 1 2 13 Graphics Controller ElanSC400 Microcontroller Only 1 12 1 2 14 JT
25. End of frame detected by receive state machine 10 Received frame complete interrupt occurs 11 Read the byte count latches and the overrun bit this clears the pre bit 12 Invert the byte count it reads out in 1 s complement format from the registers and save it and the overrun status to some variable location 13 Write the 11 bit byte count to 111 1111 1111b as setup for the next frame 14 Starting with Step 4 repeat the steps listed above until the entire sequence is received Transmit Data Transfers For High Speed Infrared mode transmit operations as long as the transmit FIFO is not full i e the number of bytes in the FIFO is less than 16 and the START bit is set an internal infrared port DMA request is generated so that the DMA controller will transfer another byte from the transmit buffer in DRAM to the transmit FIFO The internal infrared port DMA request is deasserted after each write transfer The TC Terminal Count signal from the DMA controller signifies that all bytes indicated by the transfer count programmed into the DMA controller have been transferred into the FIFO When the terminal count has been reached the START bit is automatically cleared Thus the infrared controller will notissue further DMA requests until the START DMA bitis set again even ifthe transmit FIFO is not full Infrared Port 18 4 2 11 AMDA The sequence of events for transmitting data in High Speed Infrared mode
26. into the internal serial port controller SOUT Serial Data is used to transmit the serial data from the internal serial port controller to the external serial device or DCE Keyboard Interfaces KBD COL7 O Matrix Scanned Keyboard Column Outputs drive the matrix keyboard column lines KBD COLO Open Collector Output with programmable termination KBD ROW14 STI Matrix Scanned Keyboard Row Inputs samples the row lines on the matrix keyboard KBD ROWO XT CLK y o XT Keyboard Clock is the clock signal for an external XT keyboard interface Open Collector Output XT DATA y o XT Keyboard Data is the data signal for an external XT keyboard interface Open Collector Output General Purpose Input Output GPIO31 GPIO15 B General Purpose I Os and Programmable Chip Selects ee Each of the GPIOs can be programmed to be an input or an output As outputs all of the GPIOs can be programmed to be High or Low Some of the GPIOs can be programmed to be High or Low for each of the power management modes Also as outputs some of these pins can be individually programmed as chip selects for other external peripheral devices These can be configured as direct memory address decodes or I O decodes qualified or non qualified by the ISA bus command signals Any one of the GPIO CSx signals can be configured as ROMCS2 As inputs all the GPIOs can be read back with a register bit Some of these pins can be individually programmed
27. Figure 5 6 BL1 BLO Mode Flow BLO BLT gt Feature Default SMI NMI Enabled gt Feature Option LO BL1 Hyper Speed Enabled IGH SPEEDY HYPER SPEED MODE BLO or BLT _ amp 66 100 MHz ES P 27 a et 7 Ps amp BLO BL1 4 BLO BLT SMI NMI Enabled 8 SMI NMI Enabled BLO BL1 Low SPEED MODE SMI NMI Done BLO BLT BLO BL1 amp SMI NMI Enabled SUSPEND MODE BLO BLT 5 28 Power Management Figure 5 7 2 Mode Flow BL2 Disabled amp SMI NMI Enabled BL2 Disabled Hyper Speed Enabled AMD Feature Default gt Feature Option BL2 Disabled BL2 Disabled amp SMI NMI Enabled 812 Enabled amp d HYPER SPEED BL2 Enabled amp SMINMI Enabled SMI NMI Enabled MODE gt CX 66 100 MHz SMINMI Disabled isable BL2 Enabled amp SMUNMI x 1 Disabled SMI NMI BL2 Disabled amp Don i BIZ Disabled Enabled V Enabled Enabled C BL2 Enabled amp SMDNMi Disabled SMINMI E e Done N P 4 BZ Disabled amp SMI NMI Engbled A Disabled A BLZ Enabled amp oe a Vx SMI NMI Enabled 9 TANDBY NT VAN S AA SMI NMI
28. gt px Jp gt lt lt gt lt gt lt gt lt X px lt lt gt gt DX pe gt pe gt gt lt gt gt pe px gt x lt pe gt lt lt pe gt lt lt gt lt pe lt pe pe pe gt lt lt pe gt pe lt lt gt lt gt TX pe gt p gt p gt p gt lt P lt gt lt gt gt lt gt lt P lt lt p lt px gt gt lt lt lt gt lt gt lt pe lt gt pe pe gt lt gt pe 54 gt gt lt gt lt pe x lt px gt x lt px PX gt lt p p p ps pe DX gt lt EA px gt x lt D lt gt lt gt lt gt p pe gt gt lt lt gt pc gt lt gt pe pe pe p p gt px x lt lt px gt lt gt lt bX DX DX ps DX ps DX DX DX DX gt lt gt lt lt p p pe gt px gt lt pe gt px gt lt pe gt lt px gt lt
29. 1 PC Card controller indexed register bit 1 Port 0014h 1 Direct mapped register 001 4h bit 1 RTC index RTC and configuration RAM indexed register bit 1 Pin Naming Two functions available on the pin at the same time Pin function during hardware reset Alternative pin function selected by firmware configuration E T Alternative pin function selected by a hardware configuration pin state at power on reset ROMCS1 An overbar indicates that the signal assumes the logic Low state when asserted RSTDRV The absence of an overbar indicates that the signal assumes the logic High state when asserted ROMCS2 ROMCSO All three ROM chip select signals ROMCSx Any of the three ROM chip select signals Numbers b Binary number d Decimal number Decimal is the default radix h Hexadecimal number x in register address Any of several legal values e g 3x4h as a graphics index address register can be either 3B4h or 3D4h depending on the mode selected Introduction XXV Documentation Conventions Table continued Notation Meaning X Y Z The bit field that consists of bits X through Y and the bit field consisting of the single bit Z Example Use CSC index 52h 5 3 1 General field Bit field in a register one or more consecutive and related bits can It is possible to perform an action if properl
30. 16 bit Disabled Disabled 32 bit Disabled Enabled 8 bit Enabled Disabled Reserved Reserved Reserved 16 bit Enabled Disabled Ol O olo Oj O O O 32 bit Enabled Enabled 1 In the table above CFG3 is defined as the enable disable for the DBUFOE DBUFRDL and DBUFRDH signals They can be enabled independently of whether or not a 32 bit D bus is selected via the firmware to support the VL local bus or 32 bit DRAM interface 2 The 32 bit ROM option must be selected on ROMCSO for the R32BFOE signal to be enabled The selection of the DBUFOE DBUFRDL and DBUFRDH signals is still dependent only on the signal 4 4 1 1 Table 4 6 4 16 CFGO and CFG1 Pins These pins shown in Table 4 6 configure the data bus width 8 16 or 32 bit ofthe ROM interface that is selected by the ROMCSO pin When a 32 bit ROM is selected these pins also enable the R32BFOE ROMCSO is configured as 32 bit all accesses to 32 bit ROM devices on ROMCS2 ROMCSO will result in the assertion of the R32BFOE signal Note The data bus width for the ROMCSO interface can also be changed through programming However this is not recommended The programming feature was implemented mainly for testing CFGO and CFG1 Configuration 8 bit ROMCSO ROM interface Reserved 16 bit ROMCSO ROM interface 32 bit ROMC
31. Low Speed ElanSC400 Microcontroller PLL Internal Bus Timer Clock p Data Bus Channel 0 Buffer 31 CLK IO Programmable Interrupt Controller PIRQx Output Selector Channel 1 Refresh Clock DRAM Controller Port 0061h 0 Y Gate 2 Control Word a Decoder E ed e 2 Port B 0061 SPKR Port B 0061h 1 12 2 Programmable Interval Timer 12 4 12 4 1 Table 12 2 12 4 1 1 12 4 1 2 AMD OPERATION Each of the three 16 bit timer channels can be operated independently Timer ChannelOis the primary system timer It is used for generating interrupt requests Its output is hardwired internally to drive IRQO of the microcontroller s programmable interrupt controller Timer Channel 1 is used for memory refresh It is programmed as a rate generator to produce a refresh pulse to the microcontrollers DRAM controller The refresh source either the PIT or 32 KHz can be read in the System Control Port B NMI Status Register Port 0061h Timer Channel 2 is available for general system use It is also used in conjunction with a bit SPKD in Port B to drive the SPKR output pin Modes of Operati
32. MOELE CWE SEE L TC H L H Byte Access L H XX Even byte Word Access L L L TC H L H Odd byte Even byte 19 5 4 1 Memory Write Protection One exception to the cycle command decode is when a memory write is attempted to a write protected region Write protection to a memory region can be indicated by one of two sources The WR PROT bit from the Memory Window Address Offset High Register is set for the window being accessed during the current cycle During a write protected ROM cycle redirected to Socket If one of these two conditions is true then the WE signal is held in its inactive state for the duration of the cycle so that the PC Card in the socket does not see the memory write command 19 5 4 2 Non DMA Cycle Timing The timing control registers are responsible for directing the PC Card cycle command control block during non DMA cycles issued to a PC Card The timing control registers are divided into four independent timing sets Each set has three registers responsible for Setup timing Command timing Recovery timing Each memory window can be configured for one of the four timing sets This selection is done using the Memory Window 0 4 Stop Address High Registers The contents of the timing control registers are basically counter values They tell the command cycle timer how many clocks to count for each phase setup command and recovery of a PC Card cycle Th
33. For both modes t setup 4 clocks value programmed into setup timing control t command 1 clock value programmed into command timing control t recovery 2 clocks value programmed into recovery timing control Because this PC Card controller is compatible with the 82365SL Rev B and the controller resets to Standard mode PC AT Bus clock timing the four timing sets reset to values consistent with the four possible wait state settings 0 1 2 or 3 PC AT bus wait states of 8236551 Rev B memory windows This means that default PC Card cycles are of the same length as 8236551 Rev B cycles The values of the timing control registers should not be changed when the controller is in Standard mode in order to maintain 82365SL Rev B timing compatibility The timing sets are intended to be changed when the controller is in Enhanced mode to take advantage of the higher access speeds attainable with the VL bus clock Each of the timing control registers has a two bit Prescalar Select field and a five bit Multiplier Value field The Prescalar Select field selects a weighting described in Table 19 12 Prescalar Select Field Weighting Field Value Prescalar Weighting Note The Multiplier Value Nya is combined with the Prescalar Weighting Nores to determine the number of clocks to count for the current state Setup Command active or Recovery The Current State S C or R Npres X 1 PC Card C
34. ISA KBDROW SLCT 39h 2 KBD_ROW7 KBD_ROWS8 PDRQ1 PIRQ2 KBD_ROW10 BALE KBD_ROW11 SBHE KBD_ROW12 MCS16 GPIO LBL2 SLCT 39h 4 GPIO19 2812 GPIO PCPWR SLCTA 39h 5 GPIO CS13 GPIO CS14 PCMA_VPP1 GPIO15 PCMA_VPP2 GPIO PCPWR SLCTA 39h 6 GPIO16 PCMB_VCC GPIO17 PCMB_VPP1 GPIO18 PCMB_VPP2 GPIO PCACD SLCT SAh 0 GPIO20 CD A2 0 PUEN SBh 0 GPIO CSO CS1 PUEN 3Bh 1 GPIO CS1 CS2 PUEN 3Bh 2 GPIO_CS2 DBUFRDI CS3 PUEN 3Bh 3 GPIO CS3 DBUFRDH CS4 PUEN 3Bh 4 GPIO CS4 DBUFOE CS5 PUEN 3Bh 5 _ 5 IOCS16 B 2 Pin Termination Table B 1 Pin Termination Control continued Control Bit CSC Index Pins Affected CS6 PUEN 3Bh 6 GPIO_CS6 IOCHRDY CS7_PUEN 3Bh 7 GPIO CS7 PIRQ1 CS8 PUEN SCh 0 GPIO CS8 PIRQO CS9 PUEN SCh 1 GPIO CS9 TC CS10 PUEN 3Ch 2 GPIO_CS10 AEN CS11_PUEN SCh 3 GPIO CS11 PDACKO CS12 PDEN SCh 4 GPIO CS12 PDRQO CS13 PDEN 3Ch 5 GPIO CS13 PCMA_VCC CS14 PDEN SCh 6 GPIO CS14 PCMA VPP1 GPIO15 PDEN SCh 7 GPIO15 VPP2 GPIO16 PDEN 3Dh 0 GPIO16 GPIO17 PDEN 3Dh 1 GPIO17 PCMB_VPP1 GPIO18 PDEN 3Dh 2 GPIO18 VPP2 GPIO19_ PUEN 3Dh 3 GPIO19 2812 GPIO20 3Dh 4 GPIO20 CD_A2 GPIO21 3Dh 5 GPIO21
35. See also the description for BVD2 A SPKR A DRQ_A and BVD2 B SPKR B DRQ_B the DMA request can also be programmed to appear on these pins These pins are not supported on the ElanSC410 microcontroller LCD Graphics Controller lanSC400 Microcontroller Only FRM LCD Panel Line Frame Start is asserted by the chip the start of every frame to indicate to the LCD panel that the next data clocked out is intended for the start of the first scan line on the panel Some panels refer to this signal as FLM or S scan start up This pin is not supported on the lanSC410 microcontroller System Interfaces 4 11 Table 4 4 Signal Signal Description Table continued Description LC LCD Panel Line Clock is activated at the start of every pixel line Commonly referred to by LCD data sheets as CL1 or CP1 This pin is not supported on the ElanSC410 microcontroller LCDD7 LCDDO LCD Panel Data bits LCDD7 LCDDO are data bits for the LCD panel interface When driving 4 bit single scan panels bits 3 0 form a nibble wide LCD data interface In dual scan panel mode LCDD3 LCDDO are the data bits for the top half of the LCD and LCDD7 LCDDA are the data bits for the bottom half of the LCD When driving 8 bit single scan panels monochrome or color STN these bits are the 8 bit data interface These pins are not supported on the lanSC410 microcontroller LCD Panel VDD Voltage Control is
36. A status register to get information about the state of the controller E Keyboard Configuration Registers A and B for customizing the controller Note that anytime the interface DRAM VL bus or ROM is programmed for 32 bits the matrix keyboard interface is not available Keyboard Interfaces 16 1 16 1 2 16 1 3 16 2 SCP Emulation In a typical PC AT compatible system the keyboard has a processor to map the pressed key into a make and break code that it sends to the SCP in the computer The SCP is the System Control Processor another processor connected to the ISA bus originally the 8042 Each key in the matrix has a unique make and break code The SCP takes the codes from the keyboard and maps them to a scan code The SCP puts this scan code in its output buffer which may cause an IRQ1 The CPU can then read the scan code at Port 0060h This scan code is programmable One of three tables can be used to determine a key s scan code The scan codes reside in ROM memory and are selectable by the BIOS or software It would be very complex to design a hardware keyboard interface that exactly duplicated the SCP function Because the SCP function relies on the key matrix layout and scan code set selected the hardware keyboard interface would differ for every system design and would differ depending on the scan code programmed This would require dictating the keyboard matrix layout which keys at each row column intersect
37. Capture IR State In this controller state the shift register contained in the instruction register loads the fixed value 0001 on the rising edge of BNDSCN TCK The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state When the controller is in this state and a rising edge is applied to BNDSCN TCK the controller enters the Exit1 IR state if BNDSCN TMS is held High or the Shift IR state if BNDSCN_TMS is held Low Shift IR State In this state the shift register contained in the instruction register is connected between BNDSCN TDI and BNDSCN TDO and shifts data one stage towards its serial output on each rising edge of BNDSCN TCK The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state When the controller is in this state and a rising edge is applied to BNDSCN TCK the controller enters the Exit1 IR state if BNDSCN TMS is held High or remains in the Shift IR state if BNDSCN TMS is held Low Test and Debugging 21 7 21 3 1 13 21 3 1 14 21 3 1 15 21 3 1 16 21 3 2 21 3 2 1 21 3 2 2 21 3 2 3 21 8 Exit1 IR State This is a temporary state While in this state if BNDSCN TMS is held High a rising edge applied to BNDSCN TCK causes the controller to enter the Update IR state which terminates the scanning process
38. General Purpose Input Output and Programmable Chip Selects 17 9 17 10 General Purpose Input Output and Programmable Chip Selects LEN 8 INFRARED PORT AMD 18 1 OVERVIEW The lanSC400 and ElanSC410 microcontrollers provide an infrared port designed for systems that need to support an infrared communications port compliant with the Infrared Data Association IrDA standard The infrared port on the lanSC400 and lanSC410 microcontrollers provides a reliable half duplex wireless communications link to other systems that support the IrDA standard using light pulses in the Infrared spectrum to carry the data On the ElanSC400 and ElanSC410 microcontrollers the industry standard 16550A UART is shared between RS 232 and infrared operations Special modifications have been made to the UART to support infrared operation The UART can be used to drive either the standard eight pin RS 232 interface or a two pin infrared interface The infrared port has dedicated transmit and receive data pins called SIROUT and SIRIN respectively These pins are designed to be connected gluelessly to common IrDA transmit and receive LED modules to support Slow Speed up to 115 Kbit s or High Speed 1 152 Mbit s Infrared mode operation The UART and the infrared interface pins are not multiplexed with each other or with any other interfaces and are therefore available on the microcontroller at all times However because the two interfaces shar
39. OVERVIEW The programmable interval timer PIT on the lanSC400 and lanSC410 microcontrollers is software compatible with PC AT 8254 system timers The PIT provides three 16 bit timer channels also called counters that can be operated independently in six different modes The PIT is generally used for timing external events counting and producing repetitive waveforms It can be programmed to count in binary or in BCD All three timer channels are driven from a common clock internally generated from one of the on chip phase locked loops PLL Alternatively lO pin can be configured as an input to provide an external clock source When the internal PLL is used for clock generation the resulting source clock frequency is 1 1892 MHz The standard PC AT timer clock source frequency is 1 19318 MHz Section 12 4 2 1 describes how this affects DOS compatible systems REGISTERS Asummary listing ofthe chip configuration and control CSC index registers used to control the programmable interval timer is shown in Table 12 1 Complete register descriptions be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Direct Mapped Registers The direct mapped registers provide a common set of controls to load read and configure each timer channel The following direct mapped registers are available Programmable Interval Timer 1 Mode Control Register Port 0043h Stores the control word
40. Read ROW W Low Read ROW X Cl Low Figure 16 3 N Key Rollover Example 2 Drive COL Y Low COLZ Read ROW W Low L Read ROW X A CL HOW 7 Ghost Key 16 3 1 2 Key Pressed Interrupt When no keys are pressed it is not necessary for the CPU to spend time scanning the keyboard although it could if the software required it The ElanSC400 and ElanSC410 microcontrollers contain hardware designed to cause an SMI or NMI when any key is Keyboard Interfaces 16 7 16 3 1 3 16 3 1 4 16 3 1 5 16 8 pressed To use it the CPU writes all the columns to Low All the rows ANDed together inside the chip and can be programmed to cause an NMI or SMI on a key press if any row goes Low This can only be used while no keys are pressed because as long as a key is held down the SMI would be active In addition a key press can cause the CPU clock to start back up if it is stopped and the keyboard is programmed to cause a PMU activity As a variation one or several of the columns can be programmed Low so only certain keys will cause the interrupt when pressed This requires careful layout of the key matrix by the system designer to isolate those special keys Keyboard Wake Up The keyboard can be programmed to wake up the system from Suspend mode This is done by programming the necessary columns Low and using th
41. Test data registers selected by the current instruction retain their previous value Order of Scan Cells in Boundary Scan Path This section documents the scan paths and the order of scan cells in the paths There are three scan paths from BNDSCN TDI to BNDSCN in the ElanSC400 and ElanSC410 microcontrollers 1 the instruction path 2 the bypass path and 3 the main data path through the BSR Instruction Path This four cell path is used to scan into the Instruction Register This chain is loaded when the TAP controller is driven to the states Select IR Scan through Update IR See Figure 21 3 Bypass Path This path bypasses the test logic on the microcontroller by reducing the shift length of the device to one bit Main Data Scan Path Table 21 2 shows the main data scan path The order shown is first to last i e the first is closest to BNDSCN TDI and the last is closest to BNDSCN TDO Control cells are used to control the enables of the three state pads They are part of the boundary scan chain Test and Debugging Table 21 2 that is connected between BNDSCN TDI and BNDSCN Their values are shifted serially through BNDSCN TbDl into the boundary scan chain If 1 is loaded into the control cell the associated pins are three stated or selected as inputs Each of the control cells shown in Table 21 2 contains the output enable control for the pads listed below the control cell and before the next con
42. Timing Screen Timing Main Generator and ai Data Gahi Cursor Control momay Data and Attribute FIFOs Attribute Gra LCD Remapping Data Controller Registers Scaling Character Logic FIFO Local Bus CPU Graphics lt lt _ Interface Control Registers 20 4 1 2 Clock Control The master pixel clock is generated from a dedicated PLL with user programmable frequency graphics index 4Ch All other primary clocks and strobes used in the system are derived from the master pixel clock These include the character clock which drives the screen controller the graphics dot or pixel shifter clock and the strobes used for loading data into the shift registers and reading data from the internal FIFO 20 4 1 3 Screen Timing Generation and Cursor Control Screen timing generation is based on a hybrid implementation of the 6845 and VGA CRT control registers Start address generation and text mode cursor control follows the CGA MDA standard An offset register similar to the standard VGA offset register is also included The offset register supports a virtual screen i e a small physical screen that windows into a larger virtual screen Scrolling and character panning are available using the start address registers Graphics Controller 20 7 20 4 1 4 20 4 2 20 4 2 1 20 8 The following additional features are included AC modulation control Selectabl
43. VL RST Local Bus Reset is the VL bus master reset It is controlled with CSC index 14114 Power Management ACIN AC Supply Active can used to indicate to the system that it is powered from an AC source When asserted this signal may disable power management functions if configured to do so BL2 BLO Battery Low Detects are used to indicate to the the current status of the system s primary battery pack 2 can indicate various conditions of the battery as conditions change These inputs may be used to force the system into one of the power saving modes when activated Low Going Edge LBL2 Latched Battery Low Detect 2 may be driven Low and latched on low going edge of the BLZ input to indicate to the system that the chip has been forced into the Suspend mode by a battery dead indication from the BL2 signal It is cleared by one of the all clear indicators that allow the system to resume after a battery dead indication SUS RES Suspend Resume Operation When the chip is in Hyper Speed High Speed Low Speed or Standby mode a software configurable edge on this pin may cause the internal logic to enter Suspend mode When in Suspend a software configurable edge on this pin may cause the chip to enter the High Speed or Low Speed mode The choice of edge is configured using the 505 RES Pin Configuration Register at CSC index 50h 4 8 System Interfaces Table 4 4 Signal Des
44. When the parameter passed in EAX is greater than 1 the register values returned upon instruction execution are EAX 31 0 00000000h EBX 31 0 00000000h ECX 31 0 00000000h EDX 31 0 00000000h Flags Affected None Exceptions None Am486 CPU 3 19 3 6 3 CPUID Example Using the CPUID instruction from 32 bit assembly language is relatively easy using the CPU ID instruction is more difficult from 16 bit C code The following C code fragment shows how to positively identify ElanSC400 microcontroller and derivative CPUs from 16 bit Microsoft C Exception and MyInt6 are used by 4 to install a longjmp handler at the illegal opcode exception vector static jmp buf Exception void MyInt6 void Reenable interrupts and make the setjmp return a 1 showing that the exception occurred enable longjmp xception 1 The goal of IsE4 is to return TRUE if the CPU is an lanSC400 microcontroller or derivative by verifying the following The CPU was made by AMD AuthenticAMD The CPU has no FPU The CPU is capable of write back caching Because of limitations with 16 bit code the upper words of the data are not verified but the verification is still relatively secur BOOL 15 4 void typedef void _far LPFUNC
45. X OK X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Xx X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Note 1 PC Card IRQ mapping is fully compatible with the 82365SL PC Card controller and is controlled by the PC Card index registers The PC Card controller is not supported the ElanSC410 microcontroller 11 4 Programmable Interrupt Controller 11 4 2 Table 11 3 11 5 AMD Interrupt Vectors Table 11 3 lists the vector returned to the CPU for each IRQ during the internal interrupt acknowledge sequence Interrupt Vectors 8h 9h Not available used for cascading Bh Ch Dh Eh Fh INITIALIZATION The PIC is enabled at power on reset However it is not reset by a power on reset None of the direct mapped PIC 8259 registers have power on reset values These registers must go through an initialization sequence before being used Note that all four initialization control words are required on the ElanSC400 and ElanSC410 microcontrollers The Initialization Control Word ICW registers 1 4 are programmed in sequence Writing to Port 20h with bit 4 1 causes the ICW1 Register to be written and resets the PIC s internal state m
46. eee 20 18 Black and White Attributes Example MDA Mode 20 19 8x8 Font Example eene 20 22 10 12 Font Example n 20 22 16 14 Font Example Rn pe os ee A 20 23 Flat Mapped 1 640 240 20 25 Flat Mapped 2 640 240 20 25 Flat Mapped 4 640 240 20 26 Flat Mapped 2 640 480 20 27 Memory Byte Format 1 BPP Flat Mapped Graphics Mode 20 28 16 Grayscale Palette Mapping 1 Pixel 1 BPP Flat Mapped Graphics 20 28 Memory Byte Format 2 BPP Flat Mapped Graphics Mode 20 28 16 Grayscale Palette Mapping 1 Pixel 2 BPP Flat Mapped Graphics Mode sp ER 20 28 Memory Byte Format 4 BPP Flat Mapped Graphics Mode 20 28 16 Grayscale Palette Mapping 1 Pixel 4 BPP Flat Mapped Graphics 20 28 Data Format for 4 Bit Single Scan Monochrome Panel 20 36 Data Format for 8 Bit Single Scan Monochrome Panel 20 36 Data Format for 2x4 Bit Dual Scan Monochrome 20 37 Data Format for 8 Bit Single Scan Color STN 20 38 Format of Device I
47. lanSC400 Microcontroller 1 17 System Diagram with Trade offs lanSC400 Microcontroller 1 18 System Diagram with Trade offs lanSC410 Microcontroller 1 19 Indexed Configuration Register Space 2 5 Using the Index and Data I O Ports to Access CSC Register Space 2 5 SMRAM Organization 3 5 Multiplexed Pins the ElanSC400 Microcontroller 4 14 Multiplexed Pins on the ElanSC410 Microcontroller 4 15 Bus Configuration A 16 Bit DRAM Bus and 16 Bit SD Bus 4 21 Bus Configuration 32 Bit DRAM Bus and 16 Bit SD Bus 4 22 Bus Configuration C 32 Bit DRAM Bus 16 Bit SD Bus and 32 Bit ROM 4 23 Address 4 24 8 Bit Minimal ISA 4 27 16 Bit Maximum ISA Interface 4 27 8 Bit ISA Bus with External Data 4 30 VL Bus Block Diagram 0 2 ee eee 4 36 Power Management Unit Block Diagram 5 8 Interrupts in High Speed Mode Example 5 19 PMU Timer Mode Flow 5 20 Suspend and Wake Up Resume Mode 5 23 Mode Flow
48. y W 4 x 4 Pixel Bit 1 position msb 7 x 4 2 Pixel Bit 0 position msb 6 x 4 2 4 Bits Per Pixel Mode Byte offset y W 2 2 Pixel Bit 3 position msb 7 2 4 Pixel Bit 2 position 6 2 4 Pixel Bit 1 position 5 2 4 Pixel Bit O position Isb 4 2 4 where W is the screen width in pixels is the integer modulus remainder operator represents integer division 20 26 Graphics Controller 20 4 6 2 AMD Memory Configuration Example 640x480 Panel Flat Mapped Mode Figure 20 19 illustrates the memory map for a 2 BPP 640x480 panel in flat mapped mode Another acceptable way to set up the memory map would be to define a virtual screen that is larger than the physical screen and use the start address registers to move the physical screen window through the virtual screen As long as the base address remains the same the virtual screen cannot be larger than 128 Kbytes in 2 BPP mode and 64 Kbytes in 1 BPP mode The shared memory frame buffer base address may be programmed to any 32 Kbyte boundary in the system DRAM address space Figure 20 19 Flat Mapped 2 BPP 640x480 20 4 6 3 Start Addr Reg Mem Address Frame Buffer 0000h Base 00000h Screen 1 Row 1 Base 000A0h Screen 1 Row 2 76800 bytes Base 128601 Screen 1 Row 480 128 Kbyte Base 12C00h 54272 bytes Note Set the start address register to the value
49. 1 usage 2 7 Terminal Count signal See TC signal AMD test and debugging boundary scan architecture signal descriptions 4 12 Boundary Scan Register BSR 21 2 logical structure figure 21 3 boundary scan architecture JTAG 21 1 Bypass Register BPR 21 2 Device Identification Register DID 21 2 format figure 21 2 enabling the boundary scan interface 21 1 IEEE Std 1149 1 1990 xxiv Instruction Register 21 3 order of scan cells in boundary scan path 21 8 overview 21 1 scan paths bypass path 21 8 instruction path 21 8 main data scan path 21 8 main data scan path table 21 9 supported instructions 21 3 TAP controller state diagram figure 21 5 test access port TAP instruction set 21 3 instruction set table 21 3 operation 21 5 states 21 5 test data registers 21 2 Test Clock signal See BNDSCN signal Test Data Input signal See BNDSCN TDI signal Test Data Output signal See BNDSCN TDO signal Test Mode Select signal See BNDSCN TMS signal THRE bit usage 15 6 18 13 U UART FIFO Control Shadow Register CSC index D3h function 15 3 usage 15 7 UART See serial port UART UART ENB bit usage 15 7 UIP bit usage 13 6 Underline Location Register graphics index 3Fh function 20 5 usage 20 15 20 18 V VALUE bit usage 17 7 VCC_ANALOG signal description 4 12 Index 1 23 VCC_BUS signals description 4 12 VCC_CPU signals description 4 12 VCC
50. 11 6 Programmable Timer Register 12 2 Timer EPER RIE EEAS AEE 12 3 Power Management the Programmable Interval 12 6 Real Time Clock Register Summary 13 2 Using RS3 RSO to Specify a Periodic Interrupt Rate 13 5 Power Management the Real Time Clock 13 9 Parallel Port Register Summary 14 2 Parallel Port Signal Definitions by Mode 14 4 Parallel Port Data Register Transactions in Bidirectional and EPP Modes 14 6 Power Management in the Parallel 14 10 Serial Port Register 5 15 2 Baud Rates at 1 8432 MHZ 15 5 Serial Port Interrupt 15 7 Serial Port IRQ 5 15 7 Power Management in the Serial 15 8 Keyboard Interface Register Summary 16 3 Keyboard Signals Shared with the Other Interfaces 16 5 IRQ1 Generation 0 16 12 Power Management in the Keyboard Interfaces 16 14 GPIO Register 5 17
51. 4 11 4 11 4 6 4 6 MEMW 4 6 MWE 4 7 OE 4 11 4 11 PCMA_VPP1 4 11 PCMA VPP2 4 11 4 11 _ 1 4 11 PCMB VPP2 4 11 PDACKT PDACKO 4 6 PDRQ1 PDRQO 4 6 PE 4 9 PIRQ7 PIRQO 4 6 PPDWE 4 9 PPOEN 4 9 R32BFOE 4 7 RAS3 RASO 4 7 RDY A IREQ 4 11 RDY B IREQ 4 11 REG A 4 11 REG 4 11 RESET 4 12 RIN 4 9 ROMCS2 ROMCSO 4 7 ROMRD 4 7 ROMWR 4 7 A 4 11 RST_B 4 11 RSTDRV 4 6 RTS 4 10 SA25 SAQ 4 6 SBHE 4 6 SCK 4 12 SD15 SDO 4 6 SIN 4 10 SIRIN 4 10 SIROUT 4 10 SLCT 4 9 SLCTIN 4 9 SOUT 4 10 SPKR 4 6 STRB 4 9 SUS RES 4 8 TC 4 6 VCC ANALOG 4 12 21 signals continued VCC BUS 4 12 VCC CPU 4 12 VCC LCD 4 12 VCC MEM 4 13 VCC POM 4 13 VCC_PCM2 4 13 VCC PP 4 13 VCC 4 13 VCC SER 4 13 VCC_SYS 4 13 VCC VL 4 12 VL ADS 4 7 VL BLAST 4 8 VL BRDY 4 8 4 8 VL LCLK 4 8 WP A IOIS16 4 11 WP B IOIS16 B 4 11 XT CLK 4 10 XT DATA 4 10 SIN signal control 5 4 5 6 description 4 10 usage 5 22 5 31 5 35 15 4 15 5 15 8 18 3 18 13 SIRIN signal control 18 2 description 4 10 usage 18 5 SIROUT signal description 4 10 usage 18 1 18 4 18 5 SLCT signal control 14 2 description 4 9 SLCTIN signal control 14 1 description 4 9 SMBASE Register usage 3 4 3 6 SMI NMI Select Register CSC index 98h function
52. Alternate A20 Gate Control OOEEh Alternate CPU Reset Control OOEFh Parallel Port LPT2 0278 027Fh Serial Port COM2 02F8 02FFh Parallel Port LPT1 0378 037Fh MDA Graphics Index Data 03B4h 03B5h CGA Graphics Index Data 03041 O3D5h PC Card Index Data O3E1h Serial Port COM1 03F8 03FFh Configuration Basics 2 3 2 Table 2 2 AMD Indirect Mapped Registers Indexed Registers While most of the PC AT legacy registers are direct mapped the vast majority of the configuration and control registers are indirect mapped or indexed When adding registers to a particular architecture one must be careful to maintain compatibility with the existing registers Because of the openness of the ISA architecture and the length of time that the architecture has been evolving this can be difficult to do It is impossible to say exactly what PC AT compatibility is atthis point The use of an indexed addressing scheme makes this compatibility task easier by creating separate address spaces in which the new registers can be placed thus avoiding the possibility for new registers to conflict with legacy registers This technique is far from new it has been used in the PC AT architecture since the original PC used it for the Monochrome Display Adapter MDA register interface The term index appears often in the following text An indexed register is one that is accessed
53. By setting the appropriate bits in the GPIO CS Function Select Registers A C CSC index AO A3h any GPIO CS pin or set of pins can be programmed to be a primary activity and wake up A low going edge on the pin will cause a wake up to occur if the system is in Suspend mode or a primary activity if the system is already running PMU code can detect which pin caused the activity by examining the GPIO as a Wake Up or Activity Source Status Registers CSC index 5A 5Bh GPIO CS Signals and SMI NMI Generation The GPIO XMI to GPIO CS Map Register CSC index BOh can be configured to allow any one GPIO CS signal to generate an SMI or NMI on the falling edge The SMI or NMI handler can notice and reset this condition by checking and resetting bit 5 in the Mode Timer SMI NMI Status Register CSC index 96h GENERAL PURPOSE CHIP SELECTS GP CSA GP CSD The lanSC400 and ElanSC410 microcontrollers contain four internal general purpose chip select signals GP_CSA and GP_CSB are intended for use as chip selects They decode the lower 15 bits of the address bus and can optionally qualify the address with and or To avoid aliasing address bits A15 A10 are compared with 0s GP_CSA and GP_CSB are configured using CSC indexed registers B4 B8h GP CSCand GP CSD are intended for use as memory chip selects They decode the upper 12 bits of the address bus and can optionally qualify the address with MEMH and or MEMW
54. Clock Gating Command WAIT AB Cycle OE gt Control WE gt TOR DRQs DREQ TOW i lt ag Steering ICDIR a gt Both sockets 8 amp Socket IREQs Steering and Card Status Change Interrupt Chip Enables Internal Resets Configuration Bus and 2 Decode 5 _ I ph Register Block amp Socket status 5 Detects ff a x BVDs B RDYs WPs PC Card Controller 19 5 19 4 PIN DEFINITIONS BY MODE Several of the lanSC400 microcontroller pins used for PC Card control have different functions depending on whether or not a socket is configured for the Memory only mode or the Memory and I O mode Table 19 2 compares the functions for these pins each row of the table is one lanSC400 microcontroller pin Only the name in the Memory Only Mode column is used on the lanSC400 microcontroller pin list In many instances in this chapter the names of the dual function signals have been merged into the format Memory only name Memory and I O name For example WP x IOIS16 x represents the signal whose Memory only mode function is Write protect and whose Memory function is Dynamic data bus sizing As a programmable option a DMA request signal can also appear on this pin in Memory and mode The context of the description in which the signal is used determines which function is being used Table 19 2 Dual Mode Signal F
55. DRAM parameter minimum active pulse width Setting this bit adds 1 cycle to the minimum number of memory clock cycles which is 2 for graphics controller cycles and cycles addressed to EDO DRAM and 3 for CPU or DMA cycles addressed to FPM DRAM CAS Precharge Delay CSC index 04h 3 determines the minimum value of the tcp DRAM parameter minimum amount of time CAS is inactive before it goes active If this bit is 0 the minimum tcp value is 1 memory clock for normal reads and writes and 2 memory clocks for write backs and copy backs a four double word burst Note that the additional precharge delay will occur only between consecutive double words not between two 16 bit writes which were broken up into two cycles to accommodate 16 bit DRAM banks If this bit is 1 the minimum tcp value is 2 memory clocks Refresh The DRAM controller performs CAS before RAS refreshes Refresh parameters including enable clock source divisor and self refresh are selectable via CSC index 05h The refresh clock may be sourced from the programmable interval timer PIT for backward PC AT compatibility or from the 32 KHz clock DRAM Controller 9 5 9 5 1 When the 32 KHz clock is used the refresh rate may be programmed to be 8 16 32 or 64 KHz The slowest rate which is within tolerance for the chosen DRAM should be used DRAM refresh requirements are often specified in terms of a refresh interval e g how long a row can go without be
56. Hardware Support Slow Speed Infrared mode does not provide any special hardware support i e CRC generation etc for the IrDA IrLAP Infrared Link Access Protocol layer like High Speed infrared mode does Because of this software must handle all aspects of IrLAP protocol in Slow Speed Infrared mode This also means that the IrLAP need not be implemented if all that is desired is an RS 232 port implemented via infrared Slow Speed Infrared mode does not use DMA Instead it uses all of the traditional UART interrupts and controls for data transfer The standard UART interrupts generated due to Receive Buffer Full Transmit Holding Register Empty and status changes do apply and are generated in this mode As with any conventional 16550 UART Slow Speed Infrared mode can operate with the UART FIFOs either enabled 16550 operation or disabled 16450 operation Slow Speed Infrared mode consists of a transmit section and a receive section as shown in Figure 18 2 The baud clock is 16 times the bit clock in Slow Speed Infrared mode 115 Kbit s or 1 8432 MHz Slow Speed 115 Kbits s Infrared Mode Transmit SIROUT 1 8432 MHz Section p Baud Clock gt Receive Section SIRIN Infrared Port AMD The transmit section accepts the serial data output from the UART and produces an output pulse equivalent to three UART clocks wide on the SIROUT pin Figure 18 3 shows a unit of serial dat
57. It includes the following features i Memory Windows Ten total memory windows Five are fixed for each socket Cycle Speeds Nominal 8 MHz PC AT bus clock speed or nominal 33 MHz Local Bus clock to support higher performance PC Cards DMA Features PC Cards can be configured as DMA initiators in this mode Two different PC Card signals are supported as DMA requests PC Card Controller Memory Windows Memory windows are regions of variable length which are opened by setting aside a block of addresses in the CPU memory map at user defined start stop locations Each of these memory windows can be as small as 4 Kbytes and as large as 64 Mbytes although no window base address can be positioned below 64 Kbytes It is through this 4 Kbyte 64 Mbyte viewing area that a similarly sized block of PC Card memory can be read from or written to Each of the five memory windows per socket can be individually write protected and the data path width can be set to either 8 or 16 bits via the memory window control registers No dynamic memory interface width control is provided such as that provided for the I O windows A typical memory window size is 4 Kbytes so that all ten memory windows may fit into a single 64 Kbyte block segment of CPU address space Because the PC Card may have PC Card Controller AMD up to 64 Mbytes of memory on board the viewed location on the PC Card is software programmable and is commonly referr
58. lanSC400 and lanSC410 microcontrollers It discusses the various configuration and control register spaces available on the chip and briefly describes the pin strapping options available The word configuration is used to indicate chip setup that is typically done once during system initialization whereas operational control abbreviated to control is used to indicate operations that must be performed as an integral part of actually doing work with the chip For example on the lanSC400 microcontroller selecting the number of PC card sockets that will be available to the system is a clear example of configuration whereas using the PC card controller registers to turn on power to a PC card socket is an example of operational control The term register refers to a data storage element The term port refers to an address that is read from or written to in order to access data that is stored in an associated register 2 2 CONFIGURATION METHODS The lanSC400 and ElanSC410 microcontrollers can be configured to operate in several different modes or to have certain operational characteristics that are selected by the system designer Any modes that must be available immediately upon system reset i e boot ROM data path width are configured via pin strapping options The term pin strapping as used in this chapter refers to connecting a weak external terminating resistor to certain pins of the lanSC400 and lanSC410 microcont
59. lanSC410 microcontroller Pin Termination B 5 6 Pin Termination INDEX Numerics 32KXTAL2 32KXTAL1 signals usage 6 5 A AC Supply Active signal See ACIN signal ACIN signal control 5 4 5 6 description 4 8 usage 5 21 5 24 5 25 5 27 5 31 5 35 ACK signal control 14 2 description 4 9 Activity Classification Registers A D CSC index 6A 6Dh function 5 5 Activity Source Enable Registers A D CSC index 62 65h function 5 4 Activity Source Status Registers A D CSC index 66h 69h function 5 5 address buses 4 24 address generation figure 4 24 Address Window Enable Register PC Card index 06h 46h function 7 2 19 4 usage 7 9 19 11 AEN signal control 4 25 10 3 description 4 5 usage 10 4 10 6 AFDT signal control 14 1 description 4 9 AL Register usage 3 11 Alternate CPU Reset Control Port Port OOEFh function 4 40 usage 4 2 Alternate Gate A20 Control Port Port OOEEh function 4 40 486 cache configuration options table 3 3 cache memory management 3 3 CPU control register summary table 3 1 CPU core identification CPUID instruction 3 18 3 20 lanSC400 microcontroller specific features 3 2 instruction set xxiv overview 3 1 registers 3 1 System Management Mode SMM 3 3 auto Halt restart 3 10 base relocation example 3 11 emulating I O instructions 3 11 exceptions and interrupts 3 9 execution environment 3 8 I O trappin
60. void typedef LPFUNC _far LPLPFUNC LPLPFUNC Int6 LPFUNC OldInt6 Save the old int6 vector and install our exception handler Int6 MK FP 0 6 4 OldInt6 Int6 Int6 MyInt6 8088 8086 CPUs don t have exception handling but 8088 80186 CPUs push a different value when pushing SP than the 286 and above asm push 5 sub Sp jnz NotMine Jump if 8088 8086 or 80188 80186 setjmp will only return true if we encountered the illegal exception opcode In this case clean up by restoring the interrupt vector and return FALSE 3 20 Am4869 CPU AMD if setjmp Exception we ever vector to NotMine we ll clean up and return FALSE asm NotMine Int6 OldInt6 return FALSE All set up ready to perform the test The 16 bit compiler doesn t understand 32 bit instructions so we manually code them asm emit 0x66 XOR EAX EAX a 286 should vector to int 6 here emit 0x33 emit OxCO emit OxOF CPUID 386s older 4865 should vector to int 6 here emit OxA2 Test for fragments of the AuthenticAMD string This checks every other word of the string ignores high order words 1 Make sure EAX changed jnz NotMine cmp bx 07541h Check low order string portions jnz NotMine cmp 04163 jnz NotMine cmp dx 06E65h jnz NotMin
61. 16550 Compatible Mode FIFOs In this mode there are two 16 byte FIFOs for transmitting and receiving The CPU can write 16 bytes to the transmit FIFO and use the THRE interrupt or poll the THRE bit to trigger another 16 bytes The receive FIFO has a programmable trigger level that can interrupt the CPU at 1 4 8 or 16 bytes present Writing a byte to a full transmit FIFO results in the last byte being lost If the receive FIFO is full receipt of one more character generates an overrun error The latest character is the one lost the 16 bytes in the FIFO are unchanged Interrupts The serial port on the ElanSC400 and ElanSC410 microcontrollers supports the standard UART interrupts These include the Received Data Available Transmit Holding Register Empty Modem Status and Receiver Line Status interrupts In 16650 compatible mode enabling the Received Data Available interrupt also enables time out interrupts The priority of these interrupts is shown in Table 15 3 If two interrupt sources are pending simultaneously only the highest priority interrupt will be indicated by the 102 100 field of the COMx Interrupt ID Register ports O3FAh O2FAh 3 0 When the interrupt source is cleared a subsequent read from this port will return the next highest priority interrupt source In 16650 compatible mode a FIFO time out occurs when the receive FIFO is not empty and more than four continuous character times have transpired without more data
62. 5 27 BL1 BL0 Mode Flow e 5 28 BE2 Mode FLOW esaia e egere ig dec eqq Codd 5 29 PMU Activity Mode Flow 5 34 Clock Source Block 6 2 Clock 6 3 32 KHz Crystal Circuit a a es 6 5 32 KHz Oscillator Circuit 6 5 Intermediate and Low Speed PLLs Block Diagram 6 6 Graphics Dot Clock PLL Block Diagram 6 7 High Speed PLL Block Diagram 6 7 Memory Mapping System Example 7 5 Address Translation Example 7 6 ROM Flash Interface Block Diagram 8 3 ROM Decode Example 8 5 DRAM Bank 9 4 DMA Controller Block Diagram 10 4 Programmable Interrupt Controller Block Diagram 11 3 Programmable Interval Timer Block Diagram 12 2 Real Time Clock Block Diagram 13 4 RTC Voltage 13 4 Backup Battery Used to Power 1
63. 5 3 GPIO PMUC Mode Change Register 5 7 17 2 Maximum Scan Line Register 20 5 GPIO PMUD Mode Change Register 5 7 17 2 Mode Control Register 20 3 GPIO_XMI to GPIO CS Map Register 5 7 17 2 MDA HGA Status Register 20 3 Graphics Controller Grayscale Mode Register 20 5 Memory Window Address Offset Registers 19 4 Graphics Controller Grayscale Remapping Memory Window Address Registers 19 4 Registers 20 5 Miscellaneous SMI NMI Enable Register 5 6 HGA Configuration Register 20 3 Miscellaneous SMI NMI Status Register 5 6 Horizontal Border End Register 20 4 MMS Window A Destination Register 7 2 Horizontal Display End Register 20 4 MMS Window A Destination Attributes Register 7 2 Horizontal Line Pulse Start Register 20 4 MMS Window B Destination Attributes Register 7 2 Horizontal Total Register 20 4 MMS Window B Destination Register 7 2 Hyper High Speed Mode Timers Register 5 3 MMS Window C F Attributes Register 7 1 Access SMI Enable Register A 5 6 MMS Window C F Device Select Register 7 1 Access SMI Enable Register B 5 6 Mode Timer SMI NMI Enable Register 5 6 Access SMI Status Register A 5 7 Mode Timer SMI NMI Status Register 5 6 Access SMI Status Register B 5 7 Mouse Output Buffer Write Register 16 4 Window Address Registers 19 4 Non Cacheable Window 0 Address Register 7 1 Window Control Register 19 4 Non Cacheable Window 0 Address Attributes SMM Identification and Revi
64. 5 6 SMM See Am486 CPU SOUT signal description 4 10 usage 15 4 15 5 18 3 Speaker Digital Audio Output signal See SPKR signal SPKD bit usage 12 3 SPKR signal description 4 6 usage 4 39 12 3 12 6 19 18 19 19 SRESET signal control 4 39 usage 3 17 Standard Decode to GPIO CS Map Register CSC index B1h function 17 3 usage 8 2 17 7 Standard PC Card mode See PC Card controller Standby mode See power management unit PMU Start Address High Register graphics index OCh function 20 4 usage 20 8 20 16 Start Address Low Register graphics index ODh function 20 4 START DMA bit usage 18 10 STRB signal control 14 1 description 4 9 Strobe signal See STRB signal SUS RES Pin Configuration Register CSC index 50h function 5 3 usage 4 8 SUS RES signal control 5 3 5 5 5 6 16 4 description 4 8 usage 3 5 5 21 5 31 16 1 16 5 16 8 Suspend Mode Pin State Override Register CSC index E5h function 5 7 usage 2 7 17 3 17 6 B 1 Suspend mode See power management unit PMU Suspend Pin State Register A CSC index function 5 7 Suspend Pin State Register B CSC index E4h function 5 7 Suspend Resume Operation signal See SUS RES signal Suspend Temporary Low Speed Mode Timers Register CSC index 44h function 5 3 System Address Bus signals See SA25 SAO signals System Control Port A Register Port 0092h function 4 39 usage 4 2 System Control Port B NMI Status Register Port
65. 6 3 LF VID signal description 4 9 usage 6 3 Light Pen High Register graphics index 10h function 20 4 Light Pen Low Register graphics index 11h function 20 4 Linear 50 Attributes Register CSC index 22h function 8 1 Linear ROMCSO Shadow Register CSC index 21h function 8 1 Local Bus Address Strobe signal See VL ADS signal Local Bus Burst Last signal See VL BLAST signal Local Bus Burst Ready signal See VL BRDY signal Index 11 Local Bus Byte Enable signals See VL BE3 VL BEO signals Local Bus Clock signal See VL LCLK signal Local Bus Data Code Status signal See VL D C signal Local Bus Device Select signal See VL LDEV signal Local Bus Memory I O Status signal See VL M IO signal Local Bus Ready signal See VL LRDY signal Local Bus Reset signal See VL RST signal Local Bus Write Read Status signal See VL W R signal local bus See VL bus controller Loop Filter signals See LF INT LF LS LF VID LF HS signals Low Byte Data Buffer Direction Control signal See DBUFRDL signal Low Speed mode See power management unit Low Speed Standby Mode Timers Register CSC index 43h function 5 3 LVDD signal description 4 12 usage 5 26 6 8 20 38 20 39 LVEE signal description 4 12 usage 5 26 20 39 M signal description 4 12 usage 20 38 20 39 MA12 MAO signals control 9 3 description 4 7 usage 9 1 9 4 9 5 9 8 9 10 9 12 matrix keyboar
66. 80 candisplay the value read back The last port found with any bits set is what will be displayed in ports 680 80 in al 22h Save index 22h for later restoration so SMI mov bl al does not change system state mov 1 0 out 80n al Leave 0 at port 80 to indicate no smi event mov dx 6808 happened Try94 mov al 94h out 22h al in al 23h cmp 1 0 Try95 out 80h al mov al 0 out 23h al Am4869 CPU 3 15 3 16 Try95 endif Try96 mov out mov out in cmp je t V out V t al 94h dx al al 95h 22h al al 23h 1 0 Try96 al 23h al 80h al 0 al 95h dx al You would think this is required but it doesn t seem to be Test this with smi xt pas in the tech kbd directory in in mov out The and then no more in or out al al 1 60h 1 64h dx 3ffh dx al fol al al lowing 1 61h 1 0C0h 16 1 This should clear the interrupt so another can occur Some test code to see what port 64h looked like when smm occurred due to xt kb smi reads OAh Store in a global for display toggle must be done or you only get 1 SMI And this toggling of 61h 7 should clear the xt shift register so you don t get false smis when the next byte is shifted in and the existing data is shifted out to the IRQ signal This delay is required since you are acking the XT KB which is run
67. BIZ Enabled amp UNS Don SMI NMI Disabled AAA jd AAA Bl2 Enabled amp N SMI NMI Disabled N QM l E v VY Jg 2 BIZ Disabled amp XM Y L2 amp ACIN f 2 ACIN BL2 or y d Bee SBE RITICALS A USPEND Power Management 5 29 5 4 12 5 30 SMI NMI Generation The System Management Mode SMM feature of the CPU works closely with power management Using the System Management Interrupt SMI allows the CPU to pause its application code execution and manage the system power usage without affecting the application software The code execution is effectively hidden from the application With an SMI the CPU state is automatically saved and Real mode is entered automatically This is particularly important for Protected mode operating systems that use Real mode BIOS for handling power management functions This interrupt is truly non maskable it is not part of the PC AT architecture so other programs will not interfere with the operation It is also well suited for I O trapping Non Maskable Interrupts NMIs are useful in a closed system one that runs only known software and does not have to hide the power management code from the application software NMIs have the advantage of running faster than SMIs because SMIs need to save the whole state of the CPU to RAM before executing and then restore the state
68. Boot Process Overview In a closed embedded system the designer may be able to simply choose the correct values to output to CSC indexed registers 00 07h and be finished Systems where the DRAM parameters are not known at boot time e g because there is a DRAM DIMM socket available present more issues Many DRAM characteristics such as signalloading cannot be accurately determined by software One way to deal with this issue is to have a staged boot process as follows E First all timing and drive strength registers are programmed to assume a worst case system The values for this are CSC index 04h 5Ch index 05h 40h index 06h 00h and index 07h OO Also if the microcontroller might be operating at 2 7 V CSC index 14h 5 should be set Next the DRAM banks are individually tested for DRAM existence type EDO FPM and size Banks which contain DRAM are enabled with the correct parameters See sections 9 5 2 for a full description of this process A system memory test is then performed to ensure there are no obvious problems The user may be notified and bad banks may be disabled if any problems are encountered B Ifthe user has control over DRAM setup parameters such as timing and drive strength the user s parameters must not be applied to the DRAM array until late in the boot process so that the setup program can always be used to recover the system if it becomes unbootable After finishing or bypassing the setup
69. CSC registers used to control the DRAM controller is shown in Table 9 1 Complete register descriptions can be found in the Flan SC400 Microcontroller Register Set Reference Manual order 21032 Table 9 1 DRAM Controller Register Summary Description Register Address DRAM Controller Function Keyword in Register Set Manual DRAM Bank 0 Configuration 22h 23h DRAM Bank 0 configuration enable data page 3 10 Register Index 00h width and depth address symmetry and FPM EDO selection DRAM Bank 1 Configuration 22h 23h DRAM Bank 1 configuration enable data page 3 11 Register Index O1h width and depth address symmetry and FPM EDO selection Register Index 02h width and depth address symmetry and FPM EDO selection DRAM Bank 3 Configuration 22h 23h DRAM Bank 8 configuration enable data page 3 13 Register Index 03h width and depth address symmetry and FPM EDO selection DRAM Control Register 22h 23h All banks EDO detect interleave options page 3 14 Index 04h RAS to CAS delay CAS precharge delay CAS pulse width and MWE setup time DRAM Refresh Control Register 22h 23h All banks Refresh enable request period self page 3 16 Index 05h refresh input source of the refresh timer RAS time out value Drive Strength Control Register A 22h 23h All banks pad drive strength for 015 00 page 3 17 Index 06h 12 MWE RAS3 RASO Drive Strength Control Register B 22h 23h All
70. Chapter 9 ROM Chapter 8 PC Card Chapter 19 and ISA Chapter 4 are summarized in the chapters devoted to each block Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Heference Manual order 21032 Table 7 1 Memory Management Unit Register Summary Description Register Address MMU Function Keyword in Register Set Manual Non Cacheable Window 0 22h 23h Start address bits SA23 SA16 for Non page 3 19 Address Register Index 10h Cacheable Window 0 Non Cacheable Window 0 22h 23h Start address bits SA25 SA24 and controls page 3 20 Address Attributes SMM Index 11h window size and SMM caching Register Non Cacheable Window 1 22h 23h Start address bits 5 23 5 16 for Non page 3 21 Address Register Index 12h Cacheable Window 1 Non Cacheable Window 1 22h 23h Start address bits SA25 SA24 and controls page 3 22 Address Attributes Register Index 13h window size Cache and VL Miscellaneous 22h 23h Write through caching of the LCD graphics page 3 23 Register Index 14h memory regions and MMU DRAM access delay Linear ROMO Shadow Register 22h 23h Linear access direction using MMS Windows page 3 26 Index 21h C F if applicable Linear ROMCSO Attributes 22h 23h Caching and write protection for regions page 3 28 Register Index 22h 00F0000 00CFFFFh MMS Window C F Attributes 22h 23h Caching and write protection for MMS page 3 38 Register Index 30h Windows C F MMS Window C F D
71. Four individually configurable sets three registers per set of timing registers are used for this and every window can be assigned to use one of the four timing register sets Thus if multiple resources exist on a PC Card and each of the resources have different timings a different window can be set up and used to access each of the resources This provides the maximum performance possible from the PC Card These timing registers are intended to be used only when the PC Card controller is configured for Enhanced mode Any driver that optimizes card performance for a particular card must restore the default timings when the card is removed This ensures proper timings for the next card that is inserted Signal Multiplexing The PC Card address bus A25 A0 is time multiplexed with the ISA and ROM address bus SA25 SAO0 on the lanSC400 microcontroller s pins on a cycle by cycle basis During PC Card accesses the PC Card address appears on these pins during ISA accesses the ISA address appears on these pins The ISA control signals and are time multiplexed with the PC Card IORD and IOWR signals in the same way PC Card Controller 19 7 19 5 2 19 5 2 1 19 5 2 2 19 5 2 3 19 8 Note that because the and signals shared with the ISA bus DMA initiated from an ISA bus device and targeted at a PC Card is limited to common memory i e the PC Card signal REG A or REG B is inactive Th
72. Latched BL2 The LBL2 signal goes Low during Critical Suspend mode and goes High again when the PMU leaves Critical Suspend A bitis available in the Battery AC Pin Configuration Register CSC index 70h 7 to indicate to the system that it has been in Critical Suspend mode This feature can be used by SMI firmware software to indicate the system has resumed from a Critical Suspend so that any problems this has caused can be fixed For example if a PC Card was being written and was powered down by the Suspend the card can then be reconfigured and the write continued Power Management Figure 5 5 ACIN Mode Flow Feature Default ACIN Disabled Hyper Speed Enabled gt Feature Option SMI NMI SMI NMI HYPER SPEED Done Done MODE _ gt 66 100 MHz P I S x SMI NMI N S 7 Done N S o x pog d ACIN Enabled amp ss SMI NMI Enabled PI d ACIN Enabled amp ACIN Disabled ACIN Disabled amp SMI NMI Enabled d Enabled N l 2 NA ACIN Disabled amp SMI NMI ACIN Disabled SMI NMI Enabled Done N y ACIN Enabled 7 TEMPORAR Lo N eneb Low SpEED MEE i 4 hoy NM Disabled rati 2 ACIN Disabled 4 STANDBY SMI NMI Enabled ACIN Enabled ACIN Ende Enabled amp SMI NMI Enabled ACIN 5 SUSPEND MODE CRITICAL MODE P Power Management 5 27
73. Low Speed mode 5 13 Index 15 PMU timer mode flow figure 5 20 Standby mode 5 14 suspend and wake up resume mode flow 5 23 Suspend mode 5 15 Temporary Low Speed mode 5 17 operation 5 9 overview 5 1 registers 5 2 SMI NMI generation 5 30 access 5 5 5 31 trap sources table 5 32 SMI NMI sources table 5 31 state options 5 36 programmable pull ups and pull downs 5 36 Suspend state 5 36 terminology 5 1 wake up sources 5 21 wake up sources table 5 21 PPDWE signal description 4 9 usage 14 5 14 6 PPOEN signal description 4 9 usage 14 5 14 6 Printer Acknowledge signal See ACK signal Printer Busy signal See BUSY signal Printer Select signal See SLCT signal Printer Selected signal See SLCTIN signal Programmable Chip Select signals See GPIO CS14 GPIO CSO signals Programmable DMA Acknowledge signals See PDACK1 PDACKO signals Programmable DMA Request signals See PDRQ1 PDRQO signals programmable interrupt controller PIC block diagram 11 2 initialization 11 5 interrupt vectors 11 5 interrupt vectors table 11 5 IRQ mapping 11 4 IRQ mapping table 11 4 operation 11 3 overview 11 1 PIRQ7 PIRQO signals 11 1 power management 11 6 registers 11 1 Programmable Interrupt Request signals See PIRQ7 PIRQO signals Programmable Interval Timer 1 Mode Control Register Port 0043h function 12 1 programmable interval timer PIT block diagram 12 2 con
74. Memory Byte Format Bit 7 Bit 0 co PEL PEL PEL PEL PEL PEL PEL PEL Leftmost PEL Rightmost PEL Following are the data formats for the HGA graphics mode 16 level or 4 level grayscaling may be selected when using 1 or 2 BPP flat mapped linear packed pixel modes The grayscale palette see Section 20 4 7 2 2 should be used for color mapping in the HGA graphics mode 16 Grayscale Palette Mapping 1 Pixel Red Green Blue Intensity 0 0 0 PEL Bit CO CGA MDA Text Modes Data Structures Thetext modes support emulation of CGA or MDA text attributes and addressing Standard registers O3D8h 03B8h 03D9h 03B9h and O3DAh O3BAh are emulated in CGA MDA modes Cursor positioning and sizing are performed through the 6845 compatible cursor control registers The cursor attributes can be programmed as either blinking at a 1 Hz rate or nonblinking with full or half intensity Character underlining is supported The number of the row scan line used for character underlining is programmable at the Underline Location Register graphics index 3Fh In the text modes display characters are represented in memory as a two byte data structure the character byte followed by the attribute byte The graphics memory space is partitioned into a 16 Kbyte block of display data and an independent off screen font area Graphics Controller 20 15 20 4 5 1 1 Table 20 4 Display Data Memory Space In the display
75. PPDWE GPIO22 PUEN 3Dh 6 GPIO22 PPOEN GPIO23 PUEN 30417 GPIO23 58 B GPIO24 PUEN SEh 0 GPIO24 BUSY BVD2 B GPIO25 PUEN 3Eh 1 GPIO25 ACK BVD1 B GPIO26 3Eh 2 GPIO26 PE RDY GPIO27 PUEN 3Eh 3 GPIO27 ERROR CD B GPIO28 PUEN GP1028 INIT REG B GPIO29 PUEN SEh 5 GPIO29 SLCTIN RST B GPIO30_PUEN 3Eh 6 GPIO30 AFDT MCEH_B GPIO31_PUEN 3Eh 7 GPIO31 STRB MCEL_B CSO_DIR AOh 0 GPIO CSO CS1 DIR AOh 2 GPIO CS1 CS2 DIR AOh 4 GPIO CS2 DBUFRDL CS3 DIR AOh 6 GPIO CS3 DBUFRDH CS4 DIR GPIO CS4 DBUFOE CS5 DIR Aih 2 GPIO CS5 IOCS16 CS6 DIR Aih 4 GPIO CS6 IOCHRDY CS7 DIR A1h 6 GPIO CS7 PIRQ1 Pin Termination B 3 Table B 1 Pin Termination Control continued Control Bit CSC Index Pins Affected CS8 DIR A2h 0 GPIO CS8 PIRQO CS9 DIR A2h 2 GPIO CS9 TC CS10 DIR A2h 4 GPIO_CS10 AEN CS11 DIR A2h 6 GPIO CS11 PDACKO CS12 DIR A3h 0 GPIO CS12 PDRQO CS13 DIR A3h 2 GPIO CS13 PCMA_VCC CS14 DIR A3h 4 GPIO CS14 PCMA VPP1 GPIO15 DIR A3h 6 GPIO15 PCMA_VPP2 GPIO16 DIR A4h 0 GPIO16 GPIO17 DIR A4h 1 GPIO17 PCMB_VPP1 GPIO18 DIR A4h 2 GPIO18 VPP2 GPIO19 DIR A4h 3 GPIO19 2812 GPIO20 DIR A4h 4 GPIO20 CD A2 GPIO21 DIR A4h 5 GPIO21 PPDWE GPIO22 DIR A4h 6 GPIO22 P
76. RST B signals Card Status Change Interrupt Configuration Register PC Card index 05h 45h function 19 4 usage 19 18 Card Status Change Register PC Card index 041 44 function 19 4 usage 19 18 CAS3 CASO signals usage 9 12 Index signals control 9 3 description 4 7 usage 9 1 9 4 9 6 CASL3 CASLO signals control 9 3 description 4 7 usage 9 1 9 4 9 6 CD A signal description 4 10 usage 19 18 19 19 CD A2 signal usage 19 20 CD B signal usage 19 18 19 19 CFG1 CFG0O signals description 4 7 8 7 CFG2 signal description 4 7 usage 8 7 CFG3 signal description 4 7 usage 4 17 8 7 9 1 CFG3 CFGO signals power on reset 4 3 CGA Color Select Register Port O3D9h function 20 3 usage 20 11 CGA Data Port Port 03051 function 20 2 CGA Index Register Port O3D4h function 20 2 CGA Mode Control Register Port 03D8h function 20 3 usage 20 11 CGA mode See graphics controller CGA Status Register Port O3DAh function 20 3 chip selects See programmable chip selects GPIO CS Clear To Send signal See CTS signal CLK IO Pin Output Clock Select Register CSC index 83h function 6 1 usage 10 3 15 3 IO signal control 6 1 description 4 9 usage 6 8 10 3 12 1 12 5 12 6 15 3 clock control block diagram 6 1 bus cycle clock speeds table 6 10 clock generation 6 3 32 KHz crystal circuit figure 6 5 AMD 32 KHz crystal oscillator 6 5 32 KHz oscillator c
77. The count value gets decremented with each successive clock pulse B The gate trigger begins the one shot pulse with the output going Low until the count reaches zero Output then goes High and remain High until the clock pulse after the next trigger The duration of the one shot pulse is the initial count multiplied by the period of the clock input This mode is called hardware retriggerable because once an output pulse has started if a rising edge is experienced at the gate input the counter is reloaded with the initial count and the pulse continues until the new count expires Mode 2 Rate Generator Mode 2 is used to generate a short periodic pulse PC AT compatible BIOS programs including the ones available for the ElanSC400 and ElanSC410 microcontrollers will program Channel 0 to operate in Mode 2 to provide the standard 55 ms timer tick When programmed in this mode the counters operate as divide by N counters where N is the initial count B The output signal starts off High until the initial count is decremented to one The output then goes Low for one clock pulse and goes High again the counter is reloaded with the initial count and the counting sequence is repeated One clock pulse appears at the output for every N clock cycles Mode 3 Square Wave Mode Mode 3 is used to generate a periodic square wave Timer Channels 1 and 2 use this mode by default to drive DRAM refresh and speaker respectively In this
78. Two pixel depths are available for the CGA compatible graphics mode 1 BPP or 2 BPP which correspond to the legacy CGA resolutions of 640x200 or 320x200 that are supported by the lanSC400 microcontroller s LCD controller When the graphics controller is put into CGA compatible mode the frame buffer is fixed at 16 Kbytes in size Flat Mapped Mode The flat mapped mode often referred to as inear packed pixel mode due to the lack of CGA s split addressing takes advantage of modern graphics hardware performance capabilities to get rid of the split memory map The flat mapped mode can be considered the native graphics mode of the lanSC400 microcontroller and should be used for all new graphics driver development It supports 1 2 or 4 BPP operation using a memory map for pixel data that is more intuitive for software writers and also provides higher performance for some graphics operations The flat mapped mode frame buffer size is based upon the pixel color depth 64 Kbyte for 1 BPP mode and 128 Kbytes for 2 and 4 BPP modes As in text mode multiple graphics screens can be stored the graphics frame buffer the number is limited only by the number of screens that can fit in a 64 Kbyte 1 BPP or 128 Kbyte 2 4 BPP frame buffer For example if the LCD resolution is small then each screen will take up less graphics frame buffer space so more screens can be stored at once To determine the number of screens that can be stored for a part
79. Window start address bits 19 12 out DX AL inc DX PC Card controller data register mov AL DOh out DX AL dec DX Back to the index register mov AL 11h Window start address bits 25 20 out DX AL inc DX Data mov 0 out DX AL Set up Socket A s memory window 0 to have end address of 00D0000h This is a 4 Kbyte window dec DX mov AL 12h Window stop address bits 19 12 out DX AL inc DX Data mov AL DOh out DX AL PC Card Controller 19 9 19 5 3 19 5 3 1 19 10 DX Index mov AL 13h Window stop address bits 25 20 out DX AL inc DX Data mov 0 out DX AL Set up Socket A s memory window 0 card offset to be OFFSET WINDOW START gt gt 12 where the desired offset is 0 and the window start address is Db0000h Note that 0 00D0000h FFF30000h so the 14 bit offset value 3F30 The top 2 bits of this register control other features so be sure to mask them off dec DX mov AL 14h Encoded window offset address bits 19 12 to index 14h out DX AL inc DX Data mov AL 30h out DX AL dec DX mov AL 15h Encoded window offset address bits 25 20 to index 15h out DX AL inc DX Data in AL DX 2 bit of this register must be preserved and AL Or AL 3Fh out DX AL Note This example is meant to show basic window setup only For this window from Socket A to function properl
80. addressed memory device When this signal is asserted the memory device may latch data from the data bus PDACK1 PDACKO Programmable DMA Acknowledge signals may each be mapped to one of the seven available DMA channels They are driven active Low back to the DMA initiator to acknowledge the corresponding DMA requests PDRQ1 PDRQO Programmable DMA Requests may each be mapped to one of the seven available DMA channels They are asserted active High by a DMA initiator to request DMA service from the DMA controller PIRQ7 PIRQO Programmable Interrupt Requests may each be mapped to one of the available 8259 interrupt channels They are asserted when a peripheral requires interrupt service Rising Edge Active High Trigger RSTDRV System Reset is the ISA bus reset signal When this signal is asserted all connected devices re initialize to their reset state This signal should not be confused with the internal CPU RESET and SRESET signals SA25 SA0 System Address Bus outputs the physical memory or I O port latched addresses It is used by all external peripheral devices other than main system DRAM In addition this is the local address bus in local bus mode SBHE System Byte High Enable is driven active when the high data byte is to be transferred on the upper 8 bits of the ISA data bus SD15 SDO System Data Bus is shared between ISA 8 or 16 bit ROM Flash and PC Card peripherals and can be dir
81. channel with data and status lines used according to their original Centronics definitions in the IBM PC AT Bidirectional Mode This mode offers byte wide bidirectional parallel data transfers between host and peripheral equivalent to the parallel interface on the IBM PS 2 It is similar to Enhanced Parallel Port EPP mode described below without the external command strobes and without wait state insertion Enhanced Parallel Port EPP Mode The Enhanced Parallel Port mode allows the host faster data transfers through direct register addressing of the peripheral devices This is achieved by automatically generating the address and data strobes The data transfer can be either an 8 bit 16 bit or 32 bit data transfer For a 32 bit data transfer a 32 bit I O write to Port 027Ch causes four back to back 8 bit bus cycles to occur to the four EPP data registers ports 027C 027Fh The timing for EPP mode described in the following sections is illustrated in Figure 14 4 and Figure 14 5 EPP Address Write To begin an address write cycle the host asserts WHITE places the register address on the data signals and asserts ASTRB The peripheral responds by deasserting WAIT to indicate that it is ready to receive the address byte When the host recognizes WAIT as inactive it deasserts ASTRB to latch the address byte into the device The peripheral acknowledges the end of the cycle and indicates that it is ready for the next cycle to beg
82. i When the interruptis received perform a matrix scan The scan is performed one column at a time by writing one column control bit to 0 while the other column bits are written to 1 For each column being checked read back the row inputs through Keyboard Registers A and B at CSC index C8 C9h If for a particular column a row read back bit is 0 then the key corresponding to that row and column is currently pressed Clear the interrupt If the interrupt was an NMI set the NMI DONE bit in the Control Register CSC index 9Dh 1 prior to returning control to the interrupted routine then return Table 16 2 Keyboard Signals Shared with the Other Interfaces Default Signal Alternate Function KBD ROW13 R32BFOE Do not enable the 32 bit ROM interface on ROMCSO KBD ROW12 KBD ROW7 MCS16 SBHE BALE PIRQ2 PDRQ1 CSC index 39h 2 KBD ROW6 KBD ROWO MA12 RAS3 RAS2 CASH3 CASH2 CSC index 00 031 3 CASL3 CASL2 KBD COL6 KBD COL2 PIRQ7 PIRQ3 CSC index 3Ah 1 KBD COL1 KBD COLO XT CLK XT DATA CSC index 39h 3 Keyboard Interfaces 16 5 Figure 16 1 16 6 lanSC400 Microcontroller Data Bus 7 0 Extended Chip Select Matrix Keyboard Controller Block Diagram All pull ups 150K Open KBD COLO Drain KBD COL1 Outputs Indexed KBD COL2 Register KBD COL3 KBD COL4 KBD COL5 KBD COL6
83. is a number These signals are programmable to be inputs or outputs only There are 17 GPIOx pins on the ElanSC400 and ElanSC410 microcontrollers GPIO CSx signals These signals can be programmed to be inputs outputs chip selects or power management functions There are 15 GPIO CSx pins on the ElanSC400 and ElanSC410 microcontrollers Two general purpose I O pins are dedicated GPIO_CSO GPIO_CS1 The rest are shared with other functions including external buffer control the ISA bus interface the parallel port and on the ElanSC400 microcontroller PC Card power control and the PC Card Socket B interface The GPIO_CSx signals can be programmed for the following functions PMU mode change outputs activities wake ups or SMI NMI or memory address decode outputs ROMCS2 ROM Chip Select 2 B External 8042 or similar keyboard controller chip select called SCP_CS in this chapter 17 1 1 External Pins The lanSC400 and ElanSC410 microcontrollers support 32 general purpose I O pins GPIOs Except two pins GPIO_CSO and GPIO_CS1 all the GPIO pins share pins with other functions The designer should carefully consider the system implications of using a pin as a GPIO instead of its alternate function In addition to their general purpose I O functions 15 of the GPIO signals GPIO_CS14 GPIO_CS0 be used as chip selects power management unit PMU I Os or to signal an SMI or NMI 17 1
84. lanSC400 microcontroller must always be disabled in this mode The VL bus may be enabled or disabled As in Configuration A the ROM and PC Card targets reside on the system bus and may be programmed to be 8 or 16 bits wide The matrix keyboard interface is not available in Configuration B Configuration C 32 Bit DRAM Bus 16 Bit SD Bus and 32 Bit ROM Bus Configuration C Figure 4 5 is identical to Configuration B except for the ROM interface which supports 32 bit wide ROM interface Byte lanes V1 and VO are buffered through two external 8 bit transceivers or buffers to generate the lower sixteen bits of the 32 bit ROM data bus Itisimportantto note that 32 bit ROM operation is only supported in Fast ROM mode Once ROMCSO is configured as 32 bit all accesses to 32 bit ROM devices on ROMCS2 ROMCSO will result in the assertion of the R32BFOE signal R32BFOE provides the buffer enable signal for the external transceivers on the low word of the ROM interface ROMRD is used as the direction control signal for both bytes of the high ROM word The use of System Interfaces 4 19 R32BFOE and associated buffers is at discretion of the system designer It is only required if loading on the ROM interface is heavy enough to impact the VL DRAM data bus operation or if a 5 V ROM device needs voltage translation to the 3 3 V VL DRAM bus level The matrix keyboard interface is not available in Configuration C 4 5 1 4 Data Paths Tabl
85. matrix key pressed timer tick interrupt keyboard timer time out and keyboard registers Activity Classification Register 22h 23h Primary and secondary activity classification page 3 81 Index 6Ch CPU access to external VGA controller I O and memory floppy controller registers and IDE hard drive registers DMA request ACIN signal UART RIN pin and UART SIN pin Activity Classification Register D 22h 23h Primary and secondary activity classification page 3 82 Index 6Dh CPU access to parallel port PC Card Socket A PC Card Socket B internal system registers also enables PC Card Ring Indicate and PC Card INTR Battery Level Pin Control and Status Battery AC Pin Configuration 22h 23h BLx pin configuration force CPU clock and page 3 83 Register A Index 70h PMU mode force software ACIN and Suspend indications Battery AC Pin Configuration 22h 23h Assert ACIN to disable PMU BL2 control to page 3 85 Register B Index 71h force PMU mode Battery AC Pin State Register 22h 23h BLO BL2 ACIN and SUS RES states page 3 86 Index 72h Power Management 5 5 Table 5 1 Register Clock Control and Status Address PMU Controller Register Summary continued PMU Controller Function Keyword Description in Register Set Manual CPU Clock Speed Register 22h 23h CPU clock speeds in Hyper High and Low page 3 87 Index 80h Speeds present CPU clock speed CPU Clock
86. page 3 101 Register Index 96h Standby Low Speed High Speed and Hyper Speed mode timers Battery Low and ACIN SMI NMI 22h 23h SMI NMI status BL2 BLO pin edges page 3 102 Status Register Index 97h SMI NMI Select Register 22h 23h Select SMI or NMI RTC alarm RIN pin SIN page 3 104 Index 98h pin PC Card interrupts wake ups internal keyboard interrupts SUS RES pin battery management ACIN and BL2 BL0 and PMU mode timers Access SMI Enable 22h 23h SMI enable for I O access to keyboard internal page 3 105 Register A Index 99h graphics LPT1 LPT2 parallel port UART COM 1 and COM2 Access SMI Enable 22h 23h SMI enable for I O access to GP CSA page 3 106 Register B Index 9Ah GP CSB PC Card Socket A Card Socket B IDE hard drive and floppy controller 5 6 Power Management AMD Table 5 1 PMU Controller Register Summary continued Description in Register Set Manual Register Address PMU Controller Function Keyword Access SMI Status Register 22h 23h Index 9Bh SMI status for access to keyboard internal graphics LPT1 LPT2 parallel port UART COM 1 and COM2 page 3 107 Access SMI Status Register B 22h 23h Index 9Ch SMI status for I O access to GP CSA GP CSB Card Socket A PC Card Socket B IDE hard drive and floppy controller page 3 108 XMI Control Register 22h 23h Index 9Dh Master SMI enable NMI routine done page 3 109 GPIO
87. this is equivalent to the SRESET function on the Am486 microprocessor This reset is a synchronized reset to the CPU only B ISA System Reset The RSTDRV outputis used to reset all external devices connected to the ISA bus VESA Local VL Bus Reset The VL RST output is used to reset all external devices connected to the VL bus System Interfaces 4 1 Table 4 1 Types of Reset Power On Reset Reset System Reset Master Reset Cold Reset Internal Master Reset Hardware Reset Asserting and deasserting the RESET input Resets the entire microcontroller except for the Real Time Clock All configuration registers are reset The CPU core is reset The CPU s RESET input is driven active The microcontroller enters High Speed Power Management mode See Table 4 2 for more detail RTC Only Reset The BBATSEN input being sampled below 2 4 V during a power on reset BBATSEN also provides an internal reset signal to the RTC when an external back up battery is applied for the first time Only the RTC is reset Resets bit 7 VRT of Register D index OCh to 0 An initial read to this register will then set the bit back to 1 CPU Reset Soft Reset Fast Reset Hot Reset CPU Core Reset SRESET Slow Reset Reading the Alternate CPU Reset Control Register Port OOEFh Setting bit 0 of the System Control Port A Register Port 0092h Slow reset command sequences that
88. which terminates the scanning process If BNDSCN TMS is held Low and a rising edge is applied to BNDSCN TCK the controller enters the Shift DR state The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state Update DR State The BSRis provided with a latched parallel output to prevent changes at the parallel output while data is shifted in response to the EXTEST and SAMPLE PRELOAD instructions When the TAP controller is in this state and the BSR is selected data is latched onto the parallel output of this register from the shift register path on the falling edge of BNDSCN_TCK The data held at the latched parallel output does not change other than in this state All shift register stages in a test data register selected by the current instruction retain their previous values during this state The instruction does not change in this state Select IR Scan State This is atemporary controller state The test data register selected by the current instruction retains its previous state If BNDSCN TMS is held Low and a rising edge is applied to BNDSCN_TCK when in this state the controller moves into the Capture IR state and a scan sequence for the instruction register is initiated If BNDSCN TMS is held High and a rising edge is applied to BNDSCN the controller moves to the Test Logic Reset state The instruction does not change in this state
89. 1 20 2 Registers ccu eee we eee 20 2 20 3 Block Diagram 20 6 20 4 OperatiOli esas a a xe bi ex ede dade PLE RES 20 6 20 4 1 Using the Graphics Controller 20 6 20 4 1 1 Interrupts and I O 20 6 20 4 1 2 Clock 20 7 20 4 1 3 Screen Timing Generation and Cursor Control 20 7 20 4 1 4 Internal Unified Memory Architecture 20 8 20 4 2 Graphics 20 8 20 4 2 1 Using the Frame Buffer in Text Mode 20 8 20 4 2 2 Using the Frame Buffer in Graphics Mode 20 9 20 4 2 3 Graphics Mode Memory Maps 20 9 20 4 2 4 Font Buffer 20 10 20 4 2 5 Managing Graphics 20 10 20 4 3 Graphics 20 11 20 4 3 1 CGA Graphics Pixel Formats 20 12 20 4 3 2 CGA Graphics Color Processing 20 13 20 4 4 HGA Graphics 20 13 20 4 4 1 Graphics Mode Memory Model 20 14 20 4 4 2 Graphics Pixel Formats 20 15 20 45 CGA MDA Text Modes 20 15 20 4 5 1 Data 20 15 20 4 5 2 Cursor
90. 10 The RESET CPU command is detected when the CPU issues the standard command write to Port 0064h of FEh The A20GATE and RESET CPU command emulation can be enabled or disabled independently Also the Input Buffer Full SMI NMI s can be disabled from occurring for both sequences independently Keyboard System Scenarios Scenario 1 Simple Matrix Keyboard Support by Interrupting The following is one possible scenario of how the system would use the keyboard controller with interrupting if PC AT compatibility is not required i e the system runs only custom software or guarantees all keyboard accesses go through BIOS and not directly to the keyboard controller 1 No keys are pressed Write the Keyboard Column Register all low 00 and enable the key pressed interrupt to cause an SMI or NMI on a key press any row driven Low The CPU can continue to run the application software without polling the keyboard now 2 As soon as a key is pressed an SMI NMI occurs and the CPU stops running the application software and jumps to the SMI NMI code to service the keyboard 3 The keyboard service code disables the key pressed interrupt from causing an SMI NMI writes the Keyboard Column Register with FE to set only column 0 low reads the Keyboard Row Registers A and B to see if any of the keys on column 0 are pressed continues to walk a 0 through all the columns and reads the rows to identify all the keys that are pressed The
91. 10 dots by setting bits 6 5 of the Font Table Register graphics index 42h to 01b B The total number of lines required for display is 20x11 220 lines This leaves 20 extra lines at the bottom of the panel to be blanked Graphics Controller 20 4 8 2 20 4 8 2 1 AMD The Vertical counter counts in character rows the number of whole character rows the panel display area may be calculated Int 240 11 21 character rows B The Vertical Border End Register graphics index 38h should be programmed to a value of 21 1 20 B There will be 240 21 11 2 9 extra lines at the bottom of the screen therefore the Vertical Adjust Register graphics index 35h should be programmed to a value of 9 To begin blanking the screen after the 20th row the Vertical Display End Register graphics index 37h should be programmed to 19 220 1 E The number of horizontal pixels required is 64x10 640 which equals the number of horizontal pixels on the panel Because no horizontal border is required the Horizontal Total the Horizontal Display End and the Horizontal Border End registers graphics index 30h 31h and 33h should all be set to a value of 63 64 1 If itis desired to slow down the frame refresh rate or if bit of the Extended Feature Control Register graphics index 52h is set see Section 20 4 8 2 3 the value in the Horizontal Total Register may be increased while maintaining the same value in the Ho
92. 10x12 font example figure 20 22 16x14 font example figure 20 23 8x8 font example figure 20 22 black and white attributes figure 20 19 CGA attribute byte figure 20 17 CGA attribute byte background color 20 18 attribute byte foreground color 20 17 CGA MDA character figure 20 17 cursor blinking table 20 20 cursor generation 20 20 data structures 20 15 display data memory mapping table 20 16 font address mapping table 20 21 fonts 20 20 MDA attribute byte figure 20 18 clock control 20 7 configuring graphics modes 20 32 dual scan panel setup 20 33 CPA graphics modes memory map figure 20 12 data formatting 20 35 color STN single scan panels 20 38 monochrome dual scan panels 20 37 monochrome single scan panels 20 36 flat mapped graphics modes 20 23 16 grayscale palette mapping 1 BPP 20 28 16 grayscale palette mapping 2 BPP 20 28 16 grayscale palette mapping 4 BPP 20 28 data formats 20 27 memory byte format 1 BPP flat mapped graphics mode 20 28 2 BPP flat mapped graphics mode 20 28 4 BPP flat mapped graphics mode 20 28 memory configuration example 20 24 20 27 memory configurations table 20 24 panel example 1 BPP 640x240 figure 20 25 2 BPP 640x240 figure 20 25 4 BPP 640x240 figure 20 26 graphics buffers 20 8 font buffer 20 10 frame buffer 20 8 Graphics Frame Buffer MMS Window 7 9 20 8 managing graphics memory 20 10 grayscale generation 20 29
93. 15 3 infrared port 18 1 18 3 initialization 15 7 interrupts 15 6 interrupt priority table 15 7 IRQ assignments table 15 7 operating modes 15 6 operation 15 4 overview 15 1 power management 15 7 registers 15 1 UART frame 15 5 UART frame figure 15 6 SET bit usage 13 6 13 9 Setup Timing Registers function 19 4 usage 19 7 19 13 19 17 signal descriptions 4 5 boundary scan test interface 4 12 clocks 4 9 configuration pins 4 6 general purpose input output GPIO 4 10 keyboard interfaces 4 10 Index LCD graphics controller 4 11 memory interface 4 7 parallel port 4 9 PC Card 4 10 power management 4 8 reset and power 4 12 system interface 4 5 VL bus Interface 4 7 signals ACIN 4 8 ACK 4 9 AEN 4 5 AFDT 4 9 BALE 4 5 BBATSEN 4 12 BL2 BLO 4 8 BNDSON EN 4 6 BNDSON TCK 4 12 BNDSON TDI 4 12 BNDSON TDO 4 12 BNDSON TMS 4 12 D A2 4 10 031 00 4 7 DBUFOE 4 5 DBUFRDH 4 5 DBUFRDL 4 5 DCD 4 9 DSR 4 9 DTR 4 9 ERROR 4 9 FRM 4 11 GPIO CS14 GPIO CSO 4 10 GPIO31 GPIO15 4 10 ICDIR 4 11 INIT 4 9 IOCHRDY 4 6 IOCS16 4 6 TOR 4 6 TOW 4 6 KBD COL7 KBD COLO 4 10 KBD ROW14 KBD ROWO 4 10 LBL2 4 8 5 26 LC 4 12 LCDD7 LCDDO 4 12 HS 4 9 LF INT 4 9 AMD signals continued Index LF LS 4 9 LF VID 4 9 LVDD 4 12 LVEE 4 12 20 38 M 4 12 12 4 7 4 11 4 11
94. 19 6 overview 19 1 PC Card Standard xxiv PCMCIA Standard 2 1 xxiv pin definitions by mode 19 6 power considerations shared PC Card signals table 19 21 system design 19 21 19 11 19 12 19 12 19 12 ee ee wa VCC and VPP control 19 20 VCC control signal definition table 19 21 VPP control signal definition table 19 20 power management 19 24 registers 19 2 signal descriptions 4 10 signal multiplexing 19 7 sound generation 19 18 Standard mode 19 8 19 15 configuring MMS Windows C F 19 16 memory window redirection 19 15 memory window redirection effects table 19 16 memory window socket mapping table 19 15 Socket B memory windows for MMS 19 16 WAIT AB pin usage 19 19 merging WATT signals figure 19 19 Card Extended Features Register CSC index FOh function 19 3 usage 7 10 19 15 19 18 PC Card Mode and DMA Control Register CSC index function 7 2 19 3 usage 6 1 7 9 7 10 10 3 10 4 19 8 19 13 19 16 PC Card Output Enable signal See OE signal PC Card Socket A VCC Enable signal See PCMA signal PC Card Socket A VPP Select signals See PCMA VPP2 PCMA VPP1 signals PC Card Socket A B Input Pull Up Control Register CSC index F2h function 19 3 usage 7 10 PC Card Socket B VCC Enable signal See PCMB VCC signal PC Card Socket B VPP Select signals See PCMB VPP2 PCMB VPP1 signals PC Card Write Enable signal See WE signal PC AT Compatible
95. 1x10x9x32 2 Kbyte 1024 4 MB 1x12x8x32 1 Kbyte 4096 8 MB 1x12x9x32 2 Kbyte 4096 16 MB 1x12x10x32 4 Kbyte 4096 32 MB 1x13x10x32 4 Kbyte 8192 64 MB 1x13x11x32 8 Kbyte 8192 N A Note To use Table 9 4 first find the ASYM WIDTH and DEPTH values for the desired DRAM bank configuration in Table 9 3 Supported DRAM Bank Configurations on page 9 7 DRAM Controller 9 9 Table 9 5 Interleaved System Address A to Memory Address MA Mapping CSC Index 00 03h DRAM MIEEaVER Mapping Bit Values Configuration System Address to MA Mapping for Rows Columns Bytes Banks x Rows x Cols x Bits PageSize Refresh Cycles 1 MB 2x9x9x16 2 Kbyte 512 N A 4 MB 2x10x10x16 4 Kbyte 1024 8 MB 2x11x10x16 4 Kbyte 2048 16 MB 2x11x11x16 8 Kbyte 2048 32 MB 2 12 11 16 8 Kbyte 4096 64 MB 2x12x12x16 16 Kbyte 4096 N A 2 MB 2x9x9x32 4 Kbyte 512 N A 8 MB 2x10x10x32 8 Kbyte 1024 16 MB 2x11x10x32 8 Kbyte 2048 32 MB 2x11x11x32 16 Kbyte 2048 64 MB 2x12x11x32 16 Kbyte 4096 N A N A 9 10 DRAM Controller Table 9 5 Interleaved System Address A to Memory Address MA Mapping cont CSC Index 00 03h DRAM intereaved MA Mapping Bit Values Configuration System Address to MA Mapping
96. 2 GPIO Function Select Registers E F CSC index A4 A5h function 17 2 GPIO functions See general purpose input output GPIO GPIO Read Back Write Registers A D CSC index A6 A9h function 17 2 GPIO Termination Control Registers A D CSC index 38 function 17 2 GPIO_CS Function Select Register CSC index AOh usage 17 7 GPIO CS Function Select Registers A D CSC index 0 function 5 7 17 2 GPIO CS14 GPIO CSO signals control 5 7 8 2 16 3 description 4 10 usage 5 2 5 24 5 35 5 36 17 1 17 9 GPIO PMU to GPIO CS Map Registers A B CSC index AE AFh function 5 7 Index 1 7 GPIO PMUA Mode Change Register CSC index AAh function 5 7 usage 17 7 GPIO PMUA GPIO PMUD signals usage 5 2 5 24 17 7 GPIO PMUB Mode Change Register CSC index ABh function 5 7 usage 17 7 GPIO_PMUC Mode Change Register CSC index ACh function 5 7 usage 17 7 GPIO PMUD Mode Change Register CSC index ADh function 5 7 usage 17 7 GPIO XMI to GPIO CS Map Register CSC index BOh function 5 7 17 2 usage 3 5 17 8 17 9 GPIO31 GPIO15 signals description 4 10 usage 5 36 14 1 17 1 17 9 19 5 graphics controller block diagram 20 6 CGA graphics modes 20 11 color mapping high resolution 20 13 color mapping low resolution 20 13 color processing 20 13 memory byte format high resolution 20 12 memory byte format low resolution 20 13 pixel formats 20 12 CGA MDA text modes 20 15
97. 2 Internal Chip Select Logic The lanSC400 and ElanSC410 microcontrollers contain internal chip select logic that provides two fixed chip selects ROMCS2 and SCP CS and four programmable chip selects GP CSA GP CSD Each of these chip selects can optionally be mapped to any one of the 15 GPIO pins Additionally the programmable chip selects GP CSA GP CSD can be used for power management or to generate SMIs whether or not they are physically mapped to external pins This is fully discussed in Section 17 7 General Purpose Input Output and Programmable Chip Selects 17 1 17 2 REGISTERS A summary listing of the chip setup and control CSC indexed registers used to control the GPIO signals is shown in Table 17 1 Complete register descriptions can be found in the Elan SC400 Microcontroller Register Set Reference Manual order 21032 Table 17 1 GPIO Register Summary Description in Register Set Manual Register Address GPIO Function Keyword Pin Strap Status Register 22h 23h External buffer controls DBUFOE page 3 25 Index 20h DBUFRDH DBUFRDL enable on GPIO CS4 GPIO CS2 ROMO data bus width ROMO or PC Card boot vector decode Pin Mux Register A 22h 23h GPIO CS8 GPIO CS5or ISA signals enable 3 44 Index 38h Pin Mux Register B 22h 23h PC Card power controls or GPIO CSx signals page 3 45 Index 39h keyboard columns or XT keyboard signal
98. 2 system with an optional mode for faster transfers The microcontroller s parallel port interface provides all the status inputs control outputs and the control signals necessary for the external parallel port data buffers Communication between the host microcontroller and the peripheral is asynchronous The parallel port datapath is external to the microcontroller The parallel port can be physically mapped to one of two different I O locations or can be completely disabled Only edge triggered interrupts are supported The parallel port interface is shared with the GPIO31 GP1021 signals and on the ElanSC400 microcontroller with the PC Card Socket B interface Only one of these interfaces can be enabled at one time The parallel port interface can be configured to operate in one of three different modes of operation PC AT Compatible mode This mode provides a byte wide forward host to peripheral channel with data and status lines used according to their original Centronics definitions in the IBM PC AT B Bidirectional mode This mode offers byte wide bidirectional parallel data transfers between host and peripheral equivalent to the parallel interface on the IBM PS 2 B Enhanced Parallel Port EPP mode This mode provides a byte wide bidirectional channel controlled by the microcontroller EPP mode provides separate address and data cycles over the eight data lines of the interface EPP mode offers wider system bandwidth an
99. 4 2 2 10 4 2 3 10 4 2 4 Transfer Modes The DMA controller performs read and write operations in single cycle demand or block transfer modes Areadoperation consists of amemory read cycle from the address in the current address register followed by an I O write cycle write operation consists of an I O read cycle followed by a memory write cycle to the address in the current address register Depending on the DMA channel selected the data may be 8 bits or 16 bits in width ISA bus DMA timing requires that one DMA wait state be inserted during all DMA read cycles and two wait states must be inserted for DMA write cycles Also additional wait states may be added by the actual DMA target Single Transfer Mode In single transfer mode the DMA initiator asserts DRQ and holds it active until acknowledged by the assertion of DACK The DMA controller performs the programmed DMA transfer Demand Transfer Mode In demand transfer mode the DMA initiator asserts DRQ and holds it active as long as it has data to be transferred The DMA controller will continue to perform DMA transfers until Terminal Count TC is reached or the DRQ is deasserted by the DMA initiator Block Transfer Mode In blocktransfer mode the DMA initiator asserts DRQ and holds it active until acknowledged by the assertion of DACK The DMA controller performs DMA transfers until TC is reached indicating the programmed number of transfers has
100. 4 2 8 Sending Back to Back 18 9 18 4 2 9 Receiving Back to Back 18 9 18 4 2 10Transmit Data 5 18 10 18 4 2 11Receive Data Transfers 18 11 18 42 2121 ou esl Pee eR ee 18 12 18 4 2 13Serial Infrared Interaction Pulse SIP Generation 18 12 18 5 Initializatloni c oce ted 18 13 18 6 Power 18 13 CHAPTER 19 PC CARD CONTROLLER lanSC400 MICROCONTROLLER ONLY 19 1 19 1 spp sede As E RR PORE X Rp Unten 19 1 19 2 Registers ae De der tea d ede P nie 19 2 19 3 Block Diagram 4 1 19 5 19 4 Pin Definitions by 19 6 19 5 Operation cde cc du esc RC D Rel De a CR DR 19 6 19 5 1 Signal Multiplexing 19 7 19 5 2 Memory Interface 19 8 19 5 2 1 Standard 19 8 19 5 2 2 Enhanced Mode 19 8 19 5 2 3 PC Card Controller Memory Windows 19 8 19 5 3 l Olnterface ad ea n e 19 10 19 5 3 1 19 10 19 5 4 PC Bus Cycles 19 11 19
101. 5 Port O3D9h 4 Port O3D9h 5 Port O3D9h 4 640x200 Mode In CGA high resolution mode the CO bit maps to RGBI colors as shown in Table 20 3 Color Mapping in CGA High Resolution Mode Green Blue Intensity 0 0 0 0 Port O3D9h 2 Port O3D9h 1 PortO3D9h 0 Port O3D9h 3 HGA Graphics Modes In the HGA graphics modes memory is divided into four interleaved sections a simple extension of the method used in CGA graphics mode Only 1 bit per pixel is supported The graphics mode is enabled by setting bit 4 of the Extended Feature Control Register graphics index 52h to logic 1 Doing this makes the mode register at Port O3B8h and the Configuration register at Port O3BFh visible Graphics Controller 20 13 20 4 4 1 Graphics Mode Memory Model Inthe HGA graphics modes display memory is divided into rows of four memory interleaved scan lines Figure 20 6 illustrates the HGA memory model The standard HGA screen dimensions are 720 by 348 The top quarter of each page is allocated to the first scan line of each four line set lines 0 4 8 the second quarter to the second scan line of each four line set lines 1 5 9 etc B The character height is set to 4 with the lowest two row scan line counter bits used to select the memory planes In addition graphics mode optionally supports two 32 Kbyte pages with Port b
102. 5 4 1 Memory Write Protection 19 13 19 5 4 2 Non DMA Cycle 19 13 19 5 5 Using Standard PC Card Mode 19 15 19 5 5 1 Memory Window Redirection 19 15 19 5 5 2 Configuring MMS Windows 19 16 19 5 6 Using Enhanced PC Card Mode 19 16 19 5 7 DMA Interface soo errereen elle 19 17 19 5 7 1 DMA Cycle Timing 19 17 19 5 8 System Interrupt 19 18 19 5 8 1 Socket Status 19 18 19 5 9 Sound Generation 19 18 19 5 10 Using the WAIT AB CD A and CD BPins 19 19 19 5 10 1WAIT AB Signal Merging 19 19 19 5 10 2CD A and CD B Signal Merging 19 19 19 5 11 Power Considerations 19 20 19 5 11 1Card and 19 20 19 5 11 2Power Considerations for System Design 19 21 19 6 Initialization i ee ea REX UE Re c een aeos soldes 19 22 19 6 1 Identification and Revision Register 19 23 19 7 Power 19 24 Table of Contents xiii xiv CHAPTER 20 GRAPHICS CONTROLLER lanSC400 MICROCONTROLLER ONLY 20 1 CHAPTER 21 20 1 Overview 1 2 ele 20
103. 5 6 Index OAh Cursor End Register 3x4h 3x5h Last line of alphanumeric cursor page 5 7 Index OBh Start Address High Register 3x4h 3x5h High order start address bits first data to be page 5 8 Index OCh displayed at top of screen Start Address Low Register 3x4h 3x5h Low order start address bits first data to be page 5 9 Index ODh displayed at top of screen Cursor Address High Register 3x4h 3x5h High order cursor address bits alphanumeric page 5 10 Index OEh cursor location Cursor Address Low Register 3x4h 3x5h Low order cursor address bits page 5 11 Index OFh cursor location Light Pen High Register 3x4h 3x5h Value of Cursor Address High Register for page 5 12 Read Only Index 10h CGA compatibility Light Pen Low Register 3x4h 3x5h Value of Cursor Address Low Register for CGA page 5 13 Read Only Index 11h compatibility Graphics Index Registers Extended Features Horizontal Total Register 3x4h 3x5h Total number of characters in a horizontal line page 5 14 Index 30h slowing the frame rate Horizontal Display End Register 3x4h 3x5h Number of the last character position in a line page 5 15 Index 31h output from the frame buffer Horizontal Line Pulse Start 3X4 3X5 Horizontal line pulse start horizontal line pulse page 5 16 Register Index 32h width timing requirements Horizontal Border End Register 3x4h 3x5h Last character position to be displayed at the page 5 17 Index 33h end of a line Non display Lines Register 3x4h 3x5h N
104. 50 pins It is the programmer s responsibility to ensure that other options which may use the selected pin are disabled The following C code fragment shows using GPIOO as ROMCS2 SetIO GPOSTAT CTL 1 Force GPIO CS 0 output value to 1 SetIO CSO DIR 1 Make sure GPIO CS 0 is an output SetIO CSO PUEN 0 Disable internal GPIO CS 0 pull up SetIO TERM LATCH 1 Set termination latch do while GetIO TERM LATCH Wait for disable to take place SetIO GPROM CS2 MUX 0 Map ROMCS2 to GPIO CS O0 SetIO GPOSTAT CTL 0 Stop forcing GPIO CS 0 output Memory Mapping and Caching The ElanSC400 and ElanSC410 microcontrollers provide a great deal of control over the cacheability of various memory regions ISA VL bus and PC Card spaces are never cached Memory mapped to the internal graphics controller is never cached in general is cacheable by default but two non cache windows are provided to allow programmer control over areas that should not be cached These two windows are controlled CSC index registers 10 13h Use of a virtual desktop with the LCD screen e g making the logical screen larger than the physical LCD size and scrolling the physical LCD around on the logical screen requires a larger non cacheable window than is provided automatically by the LCD controller One of the non cacheable windows can be used to mark the entire virtual screen area as non cacheable so that the phy
105. Auto Slowdown 22h 23h Fast and slow clock duration auto slowdown page 3 88 Register Index 81h enable Clock Control Register 22h 23h PLL enable restart delay time 32 KHz clock page 3 90 Index 82h state DMA clock frequency SMI NMI Generation and Status Miscellaneous SMI NMI Enable 22h 23h SMI NMI enable wake up SIN pin RIN pin page 3 94 Register Index 90h RTC alarm SUS RES pin force NMI or SMI PC Card and Keyboard SMI NMI 22h 23h SMI NMI enable matrix keyboard key press page 3 95 Enable Register Index 91h keyboard timer and Input Buffer Written and Keyboard Output Buffer Read interrupts PC Card interrupt ring indicate and card detects for PC Card Sockets A and B Mode Timer SMI NMI Enable 22h 23h SMI NMI enable time outs for Suspend page 3 96 Register Index 92h Standby Low Speed High Speed and Hyper Speed mode timers Battery Low and ACIN SMI NMI 22h 23h SMI NMI enable BL2 BLO pin edges page 3 102 Enable Register Index 93h Miscellaneous SMI NMI Status 22h 23h SMI NMI status wake up SIN pin RIN pin page 3 99 Register Index 94h RTC alarm SUS RES pin force NMI or SMI PC Card and Keyboard SMI NMI 22h 23h SMI NMI status matrix keyboard key press page 3 100 Status Register Index 95h keyboard timer and Input Buffer Written and Keyboard Output Buffer Read interrupts PC Card interrupt ring indicate and card detects for PC Card Sockets A and B Mode Timer SMI NMI Status 22h 23h SMI NMI status time outs for Suspend
106. CSC Registers A summary listing of the chip setup and control CSC index registers used to control the DMA controller is shown in Table 10 1 Complete register descriptions can be found in the Elan SC400 Microcontroller Register Set Reference Manual order 21032 CSC indexed registers provide any functionality beyond normal strict PC AT compatibility such as Extended Page registers and the ability to map PDRQx and PDACKx signals to specific channels of the DMA controller Extended Page Registers The Extended Page registers provide the upper address bits during DMA transfers The Extended Page registers permit DMA addresses to extend throughout the 64 Mbyte memory address space The processor writes the Extended Page registers before enabling DMA transfers DMA Controller Table 10 1 DMA Controller Register Summary Description Register Address Controller Function Keyword in Register Set Manual Pin Mux Register A 22h 23h ISA DMA signals enable page 3 44 Index 38h AEN and TC Pin Mux Register B 22h 23h ISA signals enable PDRQ1 page 3 45 Index 39h AEN and TC Wake Up Source Enable 22h 23h Wake up source enable and 1 page 3 61 Register C Index 54h Wake Up Source Status 22h 23h Wake up source status PDRQO and 1 page 3 65 Register C Index 58h Activity Source Enable 22h 23h Activity source enable DMA request page 3 73 Regist
107. CSC index ECh is set to indicate an error The CPU can later read this register bit for status information The error status bit which will be set depends upon how many frames were received after the status bits were last cleared up until the frame which caused the error For example if the status bits were just cleared and then 3 back to back frames are received followed by a frame with a CRC error ECh 2 0 will be clear and ECh S3 will be set Thus it is important to check and clear the CRC error bits after each frame sequence is received To support bit stuffing on the transmit side the transmit state machine must monitor the outgoing data stream to know when the two required STA flags have been transmitted so Infrared Port 18 4 2 7 18 4 2 8 18 4 2 9 that it can start bit stuffing and it must know where the STO flags are so that it can send them without bit stuffing The transmit state machine expects exactly two STA flags at the start of a transmitted frame After transmitting the first two bytes from the transmit buffer i e the STA flags the transmit state machine begins bit stuffing The point at which to stop bit stuffing is determined by starting a down counter with the value found in the IrDA Frame Length Registers A and B after the start flags have been detected Each time the transmit state machine grabs a byte from the transmit FIFO and sends it out the SIROUT pin the down counter is decremented B
108. Channel 10 8 DMA Controller 10 4 4 10 5 10 6 Table 10 7 DMA Controller Event Latency The following requests could delay acknowledgment B higher priority DMA request A cache write back if the DMA target is in a dirty cache line A high priority PMU request The DMA Hold request is prevented from reaching the CPU when the CPU is in the Stop Grant state Latency for this can be 1 ms Once a demand transfer or block transfer has started if the DMA is trying to read from a memory region that is in the cache the transfer will be paused while a cache line write back occurs If the cache holds data that the DMA controller is overwriting a cache line invalidate cycle will also occur On the ElanSC400 microcontroller when the internal graphics controller is enabled and the graphics FIFOs get starved the DMA transfer will be held off while the graphics controller gets more data from DRAM INITIALIZATION The DMA controller is enabled at power on reset but all channels are masked off This is also the state after the Software Reset Register is written POWER MANAGEMENT To conserve power the DMA clock is gated to stop the clock due to DMA controller inactivity Operation of the DMA controller is affected by the power management functions shown in Table 10 7 Power Management in the DMA Controller Power Management Effect Description Activity Ex
109. Controller The graphics controller provides the necessary control registers register and memory decodes bus interface logic data path steering and interrupt generation to support LCD panel operation The entire graphics I O space can be deactivated and become invisible to the CPU 20 4 1 1 Interrupts and I O Trapping An interrupt source and a PMU activity event source are provided The interrupt source is triggered by writes to the 6845 compatible cursor address registers at graphics index OEh and OFh The interrupt source can be used to keep track of the cursor location independent of application software when the physical display screen is smaller than the frame buffer The PMU activity event is triggered by any read or write to the active graphics frame buffer I O trapping via SMI NMI is supported for all of the I O registers and may be selectively disabled for certain frequently used registers that are CGA compatible 20 6 Graphics Controller Figure 20 1 Graphics Controller Block Diagram PMU lanSC400 Microcontroller LCD Clocks and Power LCD Panel gt Control Power Management Control Addresses to Main Address Memory Be m Generator Main Memory Arbitration EE Shared Unit OC D Timebase Memory Generator Y o Interface T
110. ElanSC400 244 Buffer Microcontroller Y A When the parallel port is configured in either Bidirectional or EPP mode the parallel port data write enable pin PPDWE is redefined to function as the Parallel Port Data Register address decode The parallel port output enable PPOEN signal from the microcontroller is controlled through the bidirectional data transfer DIR bit 5 of the Parallel Port Control Port Register PPOEN controls the output enable of the external parallel port data latch Table 14 3 outlines the operation of the parallel port data transfers to and from the internal Parallel Port Data Register when Bidirectional or EPP mode is enabled Table 14 3 Parallel Port Data Register Transactions in Bidirectional and EPP Modes Type Data is driven out on the external parallel port data bus and latched into the external 373 and into the internal data register Data written is latched into the external 373 and into the internal data register Data is read from the internal data register Data is read from the external parallel port data bus Note In EPP mode the read or write cycles refer to EPP address ports 027Bh or 037Bh and data registers of address 027C 027Fh 037C 037Fh 14 6 Parallel Port 14 5 2 14 5 2 1 14 5 2 2 14 5 2 3 14 5 2 3 1 14 5 2 3 2 Operating Modes PC AT Compatible Mode This unidirectional mode provides a byte wide forward host to peripheral
111. GPIO CS PMU Activity and Wake Up 17 8 17 6 2 GPIO CS Signals and SMI NMI Generation 17 8 17 7 General Purpose Chip Selects GP CSA GP CSD 17 8 17 7 1 Using DMA with General Purpose Chip Selects 17 9 17 7 2 Mapping a General Purpose Chip Select to a GPIO CS Pin 17 9 17 7 3 Using General Purpose Chip Selects as PMU Activities 17 9 17 7 4 Using General Purpose Chip Selects to Force an SMI 17 9 17 8 Power 17 9 xii Table of Contents CHAPTER 18 INFRARED PORT 18 1 18 1 OVervI6W cru Soe Siete lee EGG e 18 1 18 2 Registers e eu et eee 18 2 18 3 Block Diagram tae 18 3 18 4 Operation Eid ec xA D 18 3 18 4 4 Slow Speed Infrared Mode 18 4 18 4 1 1 Hardware Support 18 4 18 4 2 High Speed Infrared Mode 18 5 18 4 2 1 High Speed IrDA Frame 18 6 18 4 2 2 Frame 18 7 18 4 2 3 High Speed Infrared Mode 18 7 18 4 2 4 Data Stream 18 7 18 4 2 5 FIFO 18 8 18 4 2 6 Receive and Transmit State Machines 18 8 18 4 2 7 Frame Abort 18 9 18
112. GPIO pins as an external SMI input viathe GPIO XMI to GPIO CS Map Register CSC index BOh No SMI will be propagated to the CPU core unless bit 0 Master SMI Enable in the XMI Control Register CSC index 9Dh 0 has been set The following activities occur when the lanSC400 and lanSC410 microcontrollers process SMI 1 The cache will be automatically flushed unless disabled by setting bit 5 in the Non Cacheable Window 0 Address Attributes SMM Register CSC index 11h 5 2 Caching while in SMM is disabled unless enabled by setting bit 6 in CSC index 11h See Section 7 7 3 1 in this manual for a discussion about caching and SMM 3 The memory management hardware will map an area in DRAM to use for SMRAM when the 32 Kbyte region starting at SMBASE 8000h overlaps the upper memory area or high memory area memory between 00A0000h and 010FFFFh In this case during SMM CPU accesses but not DMA accesses to this 32 Kbyte area are directed to system DRAM instead of ROM or the ISA bus This special feature allows hiding SMRAM under ISA or ROM space In addition to the ISA or ROM space SMRAM can be hidden under any MMS window that has been opened in the upper memory area 00A0000h 00FFFFFh or the high memory area 0100000 010FFFFh For example if MMS Window B which starts at 10000h is opened and not pointing to DRAM starting at 0100000h the SMBASE can be located in this region SMM mode thus time multiplexes this system add
113. Hardware support for software emulation of the System Control Processor SCP emulation logic XT keyboard interface Architectural Overview 1 2 10 1 2 11 1 2 12 Programmable General Purpose Inputs and Outputs Chapter 17 The chip supports several general purpose I O pins GPIOs that can be used on the system board There are two classifications of GPIO available the GPIOx signals which are programmable as inputs or outputs only and the GPIO CSx signals The GPIO CSx signals have many programmable options They can be configured as chip selects As outputs these pins are individually programmable to be High or Low for the following PMU modes Hyper High Speed Low Speed Standby and Suspend As inputs or outputs they can be programmed to cause System Management Interrupts SMIs Non Maskable Interrupts NMIs wake ups or activities for the power management unit They can also be used as I O or memory chip selects Infrared Port Chapter 18 The lanSC400 and ElanSC410 microcontrollers support infrared data transfer This support consists of adding additional transmit and receive serializers as well as a controlling state machine and DMA interface to the internal UART The integrated infrared port includes these features Low speed mode supports all bit rates from UART up to 115 Kbit s E High speed mode transfers 1 152 Mbit s using DMA Dual PC Card Controller Chapter 19 ElanSC400 Microcontroller
114. I O address of the access This information can be used to emulate the I O access An example is to emulate a standard PC AT floppy controller when a non standard one is being used This information can also be used to determine what I O address caused the trap when using the GPIO trap feature which will generate a trap for up to 16 consecutive addresses See the register descriptions for CSC index B4 B7h Emulation is performed by examining the instruction opcode to determine the exact instruction and then using the register information in the State Save Map i e the address of the trapped to determine exactly what to do In the simplest case the value of the AL Register in the State Save Map e g the lowest byte of the EAX Register is used to output or is updated for an input If an instruction is emulated no special action is needed to cause the CPU to continue with the next instruction after the RSM If the SMI did not occur as a result of a trapped I O instruction bit 1 of the word at SMBASE 0FF04h will be zero and the value of bit 0 in this word will be unpredictable as will the value of the word at SMBASE OFFO6h In this case the word at SMBASE O0FFO00h the I O Instruction Restart Slot should not be written to because the results will be unpredictable SMM Base Relocation Example As discussed previously the default value for SMBASE is 30000h This legacy value is not suitable for many operating systems because
115. If BNDSCN TMS is held Low and a rising edge is applied to BNDSCN TCK the controller enters the Pause IR state The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state Pause IR State The pause state allows the test controller to temporarily halt the shifting of data through the instruction register The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state Thecontroller remains in this state as long as BNDSCN TMS isLow When BNDSCN TMS goes High and a rising edge is applied to BNDSCN the controller moves to the Exit2 IR state Exit2 IR State This is a temporary state While in this state if BNDSCN TMS is held High a rising edge applied to BNDSCN TCK causes the controller to enter the Update IR state which terminates the scanning process If BNDSCN TMS is held Low and a rising edge is applied to BNDSCN TCK the controller enters the Shift IR state The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state Update IR State The instruction shifted into the instruction register is latched onto the parallel output from the shift register path on the falling edge of BNDSCN TCK When the new instruction has been latched it becomes the current instruction
116. In this configuration ROMCSx can be either ROMCSO ROMCS 1 or ROMCS2 When used CFG1 pin strap enables 16 bit ROM Flash interface When the CFG1 pin strap pull up is not used an 8 bit ROM Flash interface results See Section 4 4 1 1 for information on using the CFG1 CFGO configuration pins which are always used together 4 22 System Interfaces Figure 4 5 Bus Configuration C 32 Bit DRAM Bus 16 Bit SD Bus and 32 Bit ROM BANK 0 Low Word Low Byte 07 00 lanSC400 Microcontroller DRAM 07 00 T Pina Low Word _____ High Byte 015 08 Low Word XCVR 07 00 Low Byte High Word Low Byte ROM Flash Direction Control DRAM D23 D16 v v Enable Control Low Word High Byte XCVR D15 D8 ROM Flash BANK 0 D31 D24 Direction Control Low High Word High Byte DRAM XCVR 07 00 High Word Low Byte Enable Control ROM Flash SD15 SD8 XCVR High Word High Byte Direction Control High ROM Flash 9 ISA 8 16 SD15 SDO PC Card 8 16 SD15 SDO Notes Anytime the interface DRAM VL bus or ROM is programmed for 32 bits the matrix keyboard interface is not available See Section 1 3 for a complete description of which features can be traded for others See Figure 4 1 and Figure 4 2 for a summary of multiplexed pin options In this configuration all of the ROM chip selects are available 0 must be configured as 32 bit to pro
117. Key Pressed Interrupt KBD COL7 All rows VCC ANDED 150K All rows have pull ups Key Timer Interrupt Data Bus 7 0 Extended Chip Select Keyboard Timer Row Data Bus 7 0 Extended Chip Select gt Keyboard Read CSC CSC Status Indexed Register Registers Data Bus 7 0 Extended Chip Select gt Keyboard CSC Configure Register Data Bus 15 0 Extended Chip Select SUS_RES IB Written Interrupt Data Bus 7 0 CPU Chip Select Input does not Buffer have pull up Write 60h 64h Extended Chip Select gt OB Read Interrupt Data Bus 7 0 CPU Chip Select Extended Chip Select Extended Chip Select Output Buffer Read 60h IRQ12 IRQ1 Data Bus 7 0 CPU Chip Select Extended Chip Select Status Register Read 64h Gate A20 Gate A20 Generation Slow Reset CPU Slow Reset CPU Generation Keyboard Interfaces KBD ROWO D KBD ROW2 52 5525 e KBD_ROW3 es E eb KBD_ROW4 KK KBD ROWS qoc qoc ROW6 EF 5 ROW7 X KBD ROWS KBD ROW9 KBD_ROW10 eb 44 oO KBD ROW11 KBD ROW12 Eum n KBD ROW13 Ada X 55
118. Keyword in Register Set Manual RTC Alarm Hour Register 70h 71h Hours alarm 12 and 24 hour mode page 4 10 Index 05h RTC Current Day of Week 70h 71h Day of the week page 4 11 Register Index 06h RTC Current Day of Month 70h 71h Date of the month page 4 11 Register Index 07h RTC Current Month Register 7Oh 71h Month page 4 12 Index 08h RTC Current Year Register 70h 71h Year page 4 13 Index 09h Register A 70h 71h Update status internal oscillator control rate page 4 16 Index selection Register B 70h 71h Update override SET periodic interrupt page 4 18 Index OBh alarm interrupt and update ended interrupt enables date mode 24 12 hour control and daylight savings enable Register C 70h 71h Interrupt request periodic interrupt alarm page 4 19 Index OCh interrupt and update ended interrupt flags Register D 70h 71h External backup battery condition RTC reset page 4 20 Index ODh BBATSEN Configuration RAM 70h 71h General purpose CMOS RAM bytes page 4 15 Index OE 7Fh 13 3 BLOCK DIAGRAM A block diagram of the real time clock is shown in Figure 13 1 Backup battery considerations along with system diagrams are described in Section 13 4 5 13 3 1 Voltage Monitoring The voltage monitor for the RTC block provides a reset signal to the RTC block when it detects a low backup battery voltage and provides an early warning signal when the system is powering down A diagram of the
119. Matrix SUS RES KBD ROW14 Normally Open Switches AMD 16 3 1 1 N Key Rollover N key rollover is the problem that happens when three keys are pressed at the same time With two keys in the same row and two keys in the same column a fourth key will be detected as pressed Because keyboards no longer incorporate diodes to eliminate current paths through keys the controller and system designer have to resolve this problem B Example Two rows W and X and two columns Y and Z are in the matrix The keys at W Y W Z and X Z are pressed When column Z is driven Low and the rows are read Figure 16 2 rows W and X will be Low as they should be because these keys are pressed When column Y is driven Low and the rows are read Figure 16 3 rows W and X are Low which is wrong Only the key at W Y should be detected but there is a path to row X through the keys at W Z and X Z so the key at X Y appears as the Ghost Key N key rollover is addressed in this design by having many row signals and using several of them for special keys like Shift Alt Ctrl Fn etc By putting only one key on each row there is no path for the Low column signal to drive a row signal it should not This will limit the total size of the keyboard supported but an 80 key keyboard can still be supported with four additional keys handled in this special way Figure 16 2 Rollover Example 1 COL Y Drive COLZ Low Key Pressed
120. No floating point unit Am486 CPU core Robust Microsoft Windows compatible CPU 8 Kbyte write back cache for enhanced performance Fully static design with System Management Mode SMM for power savings Comprehensive power management unit Seven modes of operation allow fine tuning of power requirements for maximum battery life Provides a superset of Advanced Power Management APM 1 2 features B Glueless burst mode ROM Flash interface Reduces system cost by allowing static memory such as mask ROM Flash and SRAM with three ROM Flash chip selects Glueless DRAM controller Extended Data Out EDO and Fast Page Mode FPM DRAMs supported Allows mixed DRAM types on a per bank basis to reduce system cost Architectural Overview 1 1 1 1 1 1 1 2 1 2 Standard PC AT system logic including dual Programmable Interrupt Controllers PIC dual DMA controllers Programmable Interval Timer PIT and Real Time Clock RTC DOS ROM DOS Windows and industry standard BIOS support Leverages the benefits of desktop software at embedded price points Local bus and ISA bus interface Reduces time to market with a wide variety of off the shelf companion chips B Bidirectional parallel port with EPP mode 16550 compatible UART Infrared port for wireless communication Standard and high speed Keyboard interface Matrix keyboard support with up to 15 rows and 8 col
121. Only The PC Card host bus adapter included on the lanSC400 microcontroller conforms to PCMCIA Standard Release 2 1 It provides support for two sockets each implementing the PC Card memory I O interfaces The PC Card controller is not supported on the lanSC410 microcontroller The PC Card controller includes the following features ExCA compliant 82365 register set compatible 8 and 16 bit data bus B DMA transfers between I O PC cards and system DRAM B Ten available memory windows five per socket Of the two PC Card sockets supported only one is available in all modes of operation The second socket is multiplexed with the parallel port and GPIO features Register set compatibility with the 82365SL PC Card Interface Controller is maintained where features are common to both controllers Of the ten memory windows available six are dedicated to the PC Card controller and four are shared with MMS Windows C F Architectural Overview 1 11 1 2 13 Graphics Controller CGA Compatible Text and Graphics Chapter 20 ElanSC400 Microcontroller Only The graphics controller included on the lanSC400 microcontroller offers a low cost integrated graphics solution for the mobile terminal market Integration with the main processor and system logic affords the advantages of an integrated local bus interface and frame and font buffers which are shared with main memory The graphics controller is not supporte
122. Output 43 KBD_ROW11 Input 42 KBD_ROW11 Output 41 KBD ROW12 Input 40 KBD ROW12 Output 39 KBD COLO Input 38 KBD COLO Output Test and Debugging Table 21 2 Main Data Scan Path continued Type KBD COL1 37 Input AMD 36 KBD COL1 Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Output Output PP oO Output Control cell Test and Debugging 21 15 21 16 Test and Debugging Table 1 i MULTIPLEXED PIN CONFIGURATION CONTROL OVERVIEW Many pins on the lanSC400 and ElanSC410 microcontrollers have more than one function Figure 4 1 and Figure 4 2 show the multiplexing of pins by function for each microcontroller Pins with multiplexed functions have their functions selected in one of two ways By configuration pins that are latched during reset By firmware via programmed configuration registers Table A 1 shows how to select the desired pin functions Note Signals noted with an asterisk in Table 1 are not supported on the ElanSC410 microcontroll
123. Pins and Simple Output If the GPIO pin s alternate function has not been selected with the appropriate Pin Mux Register and the GPIO s output bit in CSC index A0 A5h is set the GPIO will now be an output The value of the pin can be set by writing to its bit in CSC index A6 AQh GPIO CS Pins and Automatic Output Automatic outputs are outputs that change state automatically based on hardware events without explicit software attention Fifteen of the GPIOs GPIO CS14 GPIO 50 support automatic output which can be used for two different functions PMU state information output and chip select output To use an automatic output function the pin must be set to output mode using CSC index 5 the output VALUE must be set to 0 CSC index A6 AQh and the desired function must be steered to the correct CSC index AEh AFh and B1 B3h Note that in many cases automatic output must be programmed very carefully to insure that no glitches occur Consider programming GPIO CSO to be ROMCS2 By default it will be pulled up so the ROM will not be driving the data bus The programming must be done in such a way as to keep this true for the entire sequence lfitwasoneofthe GP_CSx selects instead of ROMCS2 its registers would be initialized here to make sure it is not selecting continuously See Section 17 7 Write 0000 to bits 7 4 of the Standard Decode to GPIO CS Map Register CSC index B1h to steer ROMCS2 to
124. RTC voltage monitor is shown in Figure 13 2 The internal RTC reset signal is asserted on power up if the backup battery voltage drops below 2 4 V Internal circuitry prevents multiple resets during power on An internal power down signal is used by the RTC to isolate the RTC core from the rest of the microcontroller The RTC voltage monitor uses the RESET assertion to detect a power down The band gap block generates the bias currents for the four PLLs and provides the 2 4 V reference source for the RTC voltage monitor The current sources constant over Voc temperature and process variations are used by the four PLL charge pumps for adjusting the PLL operating frequency Real Time Clock 13 3 Figure 13 1 Time Base 32 768 KHz Real Time Clock Block Diagram 4 32 32 32 32 A 256 Hz Clock gt Keyboard 16 Hz Clock p LCD Y Y A A A A YYY uuu Divider Periodic Interrupt p Control Selection System 1 of 15 Selector Master Reset 1 Hz Clock Power 5 gt eo Voltage Switch Q m Reference md gt 0 Reset Int R
125. Red Magenta Light Magenta Brown Yellow oio ioio o oj o o Figure 20 11 MDA Attribute Byte 0 Light gray White Bit 7 0 BLINK BAK2 BAK1 BAKO INTEN FOR2 FOR1 FORO Bit Name R W Function 2 0 FOR2 0 R W Foreground definition 3 INTEN R W Intensity of character 0 Normal Intensity 1 High Intensity 6 4 BAK2 0 RAN Background definition 7 BLINK R W Blinking if Port O3B8h 5 is set 101 0 Not Blinking 1 Blinking Character Displayed As 0 Non display Underline Normal display Reverse video Figure 20 12 illustrates the matrix of cursor and character attributes supported in MDA modes For this example the character A is displayed in an 8x14 character block The Maximum Scan Line Register graphics index 40h is programmed to OEh the Underline Location Register graphics index 3Fh is programmed to OEh the Cursor Start Register graphics index is programmed to and the Cursor End Register graphics index OBh is programmed to ODh Note that underlining is only available in MDA mode Alternating rows illustrate the appearance of the character when blink is on and off and when the cursor is on and off 20 18 Graphics Controller Figure 20 12 Black and White Attributes Example for 8x14 Character Cell MDA Mode Only Underline Non displ
126. Reset 4 4 4 2 Signal 5 5 4 5 4 3 Pin Changes for the ElanSC410 Microcontroller 4 13 4 4 Multiplexed Pin Function 4 13 4 4 1 Using the Configuration Pins to Select Pin Functions 4 16 4 4 1 1 CFGO and CFG1 4 16 4 4 1 2 GFG2 duse s 4 17 4 4 1 3 PIN crie Ere em 4 17 4 4 1 4 5 4 17 4 5 Data and Address Buses 4 18 45 1 BataB ses Ree a RE HERES 4 18 4 5 1 1 Configuration A 16 Bit DRAM Bus and 16 Bit SD Bus 4 19 4 5 1 2 Configuration B 32 Bit DRAM Bus and 16 Bit SD Bus 4 19 4 5 1 3 Configuration C 32 Bit DRAM Bus 16 Bit SD Bus and 32 Bit ROM 4 19 4514 Data Paths ie peared et 4 20 Table of Contents CHAPTER 5 4 5 2 Address Buses pr ea 4 24 4 6 System 4 25 4 7 ISA 4 25 444 sx a 4 25 4 7 2 5 i e ug i D RR DRE eR 4 25 4 7 3 Block Diagram ae 4 26 4 7 4 Supported ISA Signals 4 28 4 7 5 Operatio
127. SMBASE a CPU register that defines the start of SMRAM Historically SMRAM is 64 Kbytes in length but in the ElanSC400 and ElanSC410 microcontrollers it is only 32 Kbytes in length occupying the highest addressed 32 Kbytes in the legacy 64 Kbyte SMRAM block Figure 3 1 illustrates the SMRAM address space SMBASE defines the start of the historical 64 Kbyte SMRAM and the 32 Kbyte portion of SMRAM actually implemented by the lanSC400 and lanSC410 microcontrollers starts at SMBASE 8000h This is the location of the SMM handler entry point SMRAM ends at SMBASE 0FFFFh the save area occupies the highest 512 bytes of SMRAM from SMBASE 0FE00h to SMBASE 0FFFFh Am486 CPU Figure 3 1 3 5 4 SMRAM Organization SMBASE 8000h 7FFFh Start of State Save Area SMBASE 8000h SMM Handler Entry Point SMBASE SMBASE default 30000h System Management Interrupt SMI SMM is entered via an SMI which is a type of non maskable interrupt SMI is the highest priority interrupt in the entire system SMI generation is controlled by CSC indexed registers 90 9Dh which are more fully described in Chapter 5 Typically a hardware activity such as a change on the SUS RES pin will be programmed to cause an SMI An SMI may also be forced by setting bit 0 in the Miscellaneous SMI NMI Enable Register CSC index 90h 0 An SMI can be driven into the microcontroller by an external device by configuring one of the
128. Unit Clock gt Generation Real Time Clock Boundary Scan AT Port Logic Timer 8254 Dual Interrupt Clock I O 32 KHz Crystal lanSC400 Microcontroller Block Diagram ElanSC400 Microcontroller Memory Management Decoder Steering LCD Graphics Controller Internal Bus VL Bus Controller System Arbiter Data Bus Graphics or VL Bus Controller GPIOs Controllers DRAM Control 8259 Memory Controller ROM Control Socket A Ctrl PC Card DRAM Control or Controller Keyboard Rows GPIOs or GPIOs or Parallel Port or Keyboard Rows PC Card Socket B EPP Keyboard Parallel Interface Columns or Port Matrix XT SCP XT Keyboard ISA Control or Serial Port Keyboard Rows ISA Bus ISA Control or 4 Infrared un GPIOs ort Architectural Overview 1 3 Figure 1 2 Clock I O lanSC410 Microcontroller Block Diagram ElanSC410 Microcontroller Addr Dual DMA Controllers 8237 Power Management Unit 32 KHz Crystal Clock gt Generation Real Time gt Clock Boundary Scan AT Port Logic Memory Management Unit Address Decoder Data Steering Internal Bus VL Bus Controller System Arbiter SA Bus Data Bus VL Bus Controller GPIOs Timer 8254 Dual Interrupt Controllers 8259 GPIOs or Parallel Port EPP Parallel Port Serial Po
129. VCCA Fr Up E 36 864 MHz p 5 Phase Charge oop Filter Fr Detector Down Pump WES Co Fo Divider 66 3552 MHz VCO Vc 9 Internal External Clock Control 6 7 6 4 2 6 4 2 1 6 4 2 2 6 4 2 3 6 4 2 4 6 4 2 5 6 4 2 6 6 4 2 7 6 8 Clock Control Several of the core clocks on the lanSC400 and lanSC410 microcontrollers are programmable This programmability is either directly controlled by system firmware or is forced due to a power management mode change Table 6 4 shows the speeds for each clock and Table 6 5 shows bus cycle clock speeds for the lanSC400 and ElanSC410 microcontrollers CPU 1x Clock The speed of the CPU s static clock is programmable based on PMU mode Programmable values for High and Low Speed modes stopped for Standby and Suspend modes 33 MHz for Hyper Speed mode CPU Clock Speed Register settings Program the clock value used in High and Low Speed modes Auto Slowdown enabled Changes the CPU clock speed based on the programmed duty cycle when the PMU is in High and Hyper Speed modes The CPU is put in hold before changing this clock Memory Clock This clock is used by the DRAM controller to time the cycles to the DRAM The clock is either 66 MHz when the LCD graphics controller on the lanSC400 microcontroller is enabled and displaying as indicated by the LVDD signal or it is 2x the CPU clock when the LCD c
130. VL bus target connects to the microcontroller s SA25 SA2 address bus The target s address bits 31 through 26 should be appropriately terminated at the target The status outputs VL D C VL M IO and VL W R and the byte enables VL BES3 VL are provided by the microcontroller and should be connected to the corresponding pins on the VL bus target Data Interface The ElanSC400 and lanSC410 microcontrollers support a 32 bit data bus interface to the VL bus target The VESA data sizing signal LBS16 is not supported The VL bus data bus byte ordering for the ElanSC400 and ElanSC410 microcontrollers is shown in Table 4 18 Due to loading requirements on the VL bus data signals an external buffer for the system data bus SD15 SDO might be required when configuring the lanSC400 and lanSC410 microcontrollers to use the local bus controller feature A data transceiver enable DBUFOE and two direction control signals DBUFRDL DBUFHRDH are provided for this function When using the external data buffers the VL bus target should be connected to the microcontrollers SD15 SDO pins The remaining system devices except DRAM should System Interfaces Table 4 18 4 8 4 3 4 8 4 4 AMD be connected to the outputs of the external data transceiver 32 bit DRAM should be connected to 015 00 not to the buffered side VL Bus Data Bus Byte Ordering ane 07 00 015 08 023 016 031 024 Normal Bus Cy
131. after the CPU relinquishes the bus 7 Memory read followed by I O write signals are generated by the DMA controller 8 The DMA controller executes the write cycle by moving the byte from the memory to the transmit FIFO 9 An internal infrared port DMA acknowledge signal is deasserted after the transfer is complete and in turn the DMA controller surrenders the bus back to CPU 10 Steps 6 9 are repeated until the DMA transfer is complete This is indicated by the TC signal from the DMA controller The end of memory transfer indicated when the TC generates an interrupt request IRQ assumes the if the interrupt enable control bit has been enabled Note that the FIFO is still full when the TC signal occurs Before changing to receive mode software must wait until the transmit FIFO is empty This can be done by polling the IrDA Status Register CSC index EBh 0 Alternatively the TC interrupt can be swapped out for a Transmit FIFO Empty interrupt by setting CSC index EAh 7 In this case the interrupt will not occur until the transmit FIFO has completely emptied into the transmit serializer so it is acceptable to change to receive mode immediately to look for the response This is the suggested operating mode for most situations Receive Data Transfers Per the IrLAP specification software should look for the initial connection between IrDA ports to be performed in Slow Speed Infrared mode at 9600 baud During the negotiation phase if bot
132. all standard 82365 compatible status change interrupt and PC Card interrupt enable and routing features The standard interrupt capability is extended by coupling the PC Card controller to the lanSC400 microcontrollers Power Management Unit PMU to support SMI and NMI In addition PC Card controller interrupts memory accesses and I O accesses can be configured to cause PMU wake ups and activities 82365 compatible socket power controls are available for Socket A and VPP1 and VCC controls and the 82365 auto power feature that turns off socket power until a card is inserted is supported The PC Card controller also supports software generated card detect change interrupts For information on redirecting ROMCSO to PC Card Socket A see Section 7 6 4 2 PC Card Controller 19 1 19 2 Table 19 1 Register REGISTERS Two different sets of indexed registers are used to configure the PC Card controller The chip setup and control CSC index registers are accessed via the 22h 23h index data I O scheme The standard 82365SL Rev B registers are accessed via the PC AT I O space at Ports and 03E 1h All PC Card controller registers that pertain to Socket A have indexes from 00 3Fh All PC Card controller registers that pertain to Socket B have indexes ranging from 40 7F h Thus to get the Socket B counterpart index for a given Socket A register add 40h to the Socket A index value If an external 82365 c
133. all subsequent accesses to Port OS3E1h will go to the internal PC Card controller only Immediately following power on reset the PC Card controller defaults to Standard mode which supports only one fully 82365 PC Card socket or two sub 82365 sockets that must share six memory windows instead of the normal ten windows no PC Card controller DMA capability and standard ISA timings only In Standard mode four of the memory windows windows 1 4 that normally belong to Socket B are unavailable because they are redefined to be general purpose MMS See Section 19 5 5 1 for more information on these MMS windows See Section 19 5 5 for more information on Standard mode The PC Card controller can be configured for Enhanced mode by setting CSC index F1h 0 Enhanced mode supports all ten 82365 compliant memory windows and Card controller DMA and is discussed in Section 19 5 6 and Section 19 5 7 Other than the memory window DMA and timing features just described there are no other differences between the Standard and Enhanced modes Identification and Revision Register The Identification and Revision Register for each socket has two different modes for read back In one the 82365SL Rev B compatible value of 82h is read back In the other the lanSC400 microcontroller specific value of OFxh is read back The actual value depends onthe specific version ofthe lanSC400 microcontroller This allows the PC Card controller
134. and begins the countdown from the start When Temporary Low Speed is entered from Suspend mode secondary activities do not reset the Temporary Low Speed timer n Suspend or Critical Suspend modes secondary activities have no effect When events can be programmed to be both activities and SMI NMIs the SMI NMI will be generated and the mode will change during the SMI NMI routine Using the Activity Source Flag Registers The activity source flag registers are read to determine what caused an activity Write to 1 has no effect write to 0 to clear If an activity source is asserted when enabled as an activity it generates an activity The activity sources are listed in Table 5 5 Note When an activity occurs in Suspend mode it sets the flag register Primary activities occurring in Hyper Speed High Speed or Suspend Critical Suspend mode do not incur a mode change but set the status bit for that activity If the primary activity occurs in Hyper Speed or High Speed PMU modes the respective mode timers are reset If the primary activity occurs in Suspend Critical Suspend mode the Hyper Speed High Speed mode time out is increased by 60 uis upon wake up If a secondary activity occurs in any mode except Standby the associated status bit is set However the activity is not latched until Temporary Low Speed or Low Speed mode is entered The secondary activity event but not the status bit is cleared in High Speed or Hype
135. and no 32 bit targets are supported This is because the graphics controller needs a guaranteed short latency for adequate video performance If either 32 bit DRAMs 32 bit ROMs or the VL bus is enabled the internal graphics controller is unavailable Note that as a derivative of the original ElanSC400 microcontroller the ElanSC410 microcontroller shares the primary architectural characteristics of the ElanSC400 microcontroller described above minus the graphics controller The following sections provide an overview of the features of the ElanSC400 and ElanSC410 microcontrollers including on chip peripherals and system interfaces Architectural Overview 1 5 1 2 1 1 2 2 1 2 3 1 6 Low Voltage Am486 CPU Core Chapter 3 The lanSC400 and ElanSC410 microcontrollers are based on the low voltage Am486 CPU core It includes the following features 2 3 3 V operation reduces power consumption Industry standard 8 Kbyte unified code and data write back cache improves both CPU and total system performance by significantly reducing traffic on the DRAM bus System Management Mode SMM facilitates designs requiring power management by providing a mechanism to control power to unneeded peripherals transparently to application software To reduce power consumption the floating point unit has been removed from the Am486 CPU core Floating point instructions are not supported on the ElanSC400 and ElanSC410 micro
136. and page 3 57 Clock Timers Register Index 45h for switching the CPU clockto the programmed speed PMU Wake Up Control and Status SUS RES Pin Configuration 22h 23h SUS RES pin enable pin trigger configuration 3 58 Register Index 50h Power Management 5 3 AMDA Table 5 1 PMU Controller Register Summary continued Description in Register Set Manual Register Address PMU Controller Function Keyword Wake Up Source Enable 22h 23h Wake up source enable RTC alarm UART page 3 59 Register A Index 52h RIN and SIN pins Suspend mode timer time out matrix key press Wake Up Source Enable 22h 23h Wake up source enable BLO BL1 BL2 and page 3 60 Register B Index 53h ACIN Wake Up Source Enable 22h 23h Wake up source enable PIRQ5 PIRQO and page 3 61 Register C Index 54h PDRQ1 PDRQO Wake Up Source Enable 22h 23h Wake up source enable Ring Indicate page 3 62 Register D Index 55h Interrupt Request Card Detect and Status Change for PC Card pins Wake Up Source Status 22h 23h Wake up source status SUS RES RTC page 3 63 Register A Index 56h alarm UART RIN and SIN pins Suspend mode timer time out matrix key press Wake Up Source Status 22h 23h Wake up source status BL2 and page 3 64 Register B Index 57h ACIN Wake Up Source Status 22h 23h Wake up source status PIRQ5 PIRQO and page 3 65 Register C Index 58h PDRQ1 PDRQO Wake Up Source Stat
137. and set to 32 bits Bank 1 is enabled and set to 32 bits or either Bank 2 or 3 is enabled Otherwise they become matrix keyboard signals While avoiding any contention the algorithm must determine the following for each bank E If the bank is populated with DRAM B Ifthe DRAM is EDO or FPM E ifthe DRAM is asymmetrical or symmetrical The depth of the DRAM The width of the DRAM Acode sample that contains the algorithm to determine these values and program the CSC registers appropriately can be found at ftp ftp amd com pub epd e86 To determine total memory size after running the algorithm simply add up the size represented by each enabled bank except do not add in Bank if CSC index 03h is equal to OBOh The amount of DRAM in each bank is determined by using the depth and width fields in the bank s configuration register in the following formula DramBytes 1 lt lt depth field width field 9 In other words the DRAM size is always 2 where is 9 plus the 3 bit quantity in the depth field plus 1 if the bank is 32 bits wide DRAM Controller 9 6 Table 9 6 Event AMD POWER MANAGEMENT Operation of the DRAM controller is affected by the power management functions shown in Table 9 6 Minimizing power consumption was a major goal in the design of the lanSC400 and ElanSC410 microcontrollers Some of the features of the DRAM controller that support this are not applicable to all designs and
138. any VL bus cycle memory or is the source of an activity VL Bus Register Summary Description Address VL Bus Function Keyword in Register Set Manual Cache and VL Miscellaneous 22h 23h VL bus interface enable VL bus reset control page 3 23 Register Index 14h Activity Source Enable Register A 22h 23h Activity source enable VL bus cycle memory page 3 71 Index 62h or I O Activity Source Status Register A 22h 23h Activity source status VL bus cycle memory page 3 75 Index 66h or I O Activity Classification Register A 22h 23h Primary or secondary activity classification page 3 79 Index 6Ah VL bus cycle memory or I O Suspend Pin State Register A 22h 23h Power control in Suspend mode for VL bus page 3 184 Index E3h interface System Interfaces 4 35 AMD 4 8 3 Block Diagram Figure 4 10 is a simplified block diagram showing all the external signals used by the VL bus More complex examples showing how these signals are used in different configurations can be found in Figure 4 4 and Figure 4 5 starting on page 4 22 Figure 4 10 VL Bus Block Diagram 4 8 4 4 8 4 1 4 8 4 2 4 36 Addresses SA25 SA2 Data D31 DO VL_BE3 VL_BEO VL BLAST ElanSC400 Microcontroller VL LCLK VL RST VL W R VL D C VL M IO VL VL_LRDY A A Y VL BRDY Operation Address Interface The
139. are intended for an external SCP are trapped and decoded internally Shutdown cycle issued by the CPU Pulses the internal CPU SRESET signal Only the CPU is reset The Am486 cache state and SMBASE are not affected No effect on configuration registers ISA System Reset Signal Name RSTDRV System Reset ISA Reset Asserting the RESET input Re initializes all devices connected to the ISA bus to their reset state VL Bus Reset Signal Name VL RST VESA Reset Setting bit 4 in the Cache and VL Miscellaneous Register CSC index 14h asserts VL RST Re initializes the VL bus target to its reset state After enabling the VL bus interface VL_RST should be asserted and deasserted before using the VL bus 4 1 1 1 Power On Reset Power on reset is invoked by asserting the RESET input Power on reset can be asserted at any point during operation Power on reset configures the microcontroller as follows E Instruction execution is suspended Instruction fetching is suspended B Any interrupt or trap conditions are ignored B Except as previously noted the contents of all configuration registers are reset to their listed default power on reset states The PLLs are disabled Power on reset mode is exited when the RESET input is deasserted At this point 4 2 System Interfaces Table 4 2 The configuration pins CFG3 CFGO are sampled CPU begins fetching instructions from the r
140. are traded for keyboard row signals the minimum system would have one or two banks of DRAM either Bank 0 or Bank 1 populated with 16 bit DRAMs See Section 1 3 for a complete description of which features can be traded for others See Figure 4 1 and Figure 4 2 for a summary of multiplexed pin options In this configuration ROMCSx can be either 50 51 or 52 When used the CFG1 pin strap enables a 16 bit ROM Flash interface When the CFG1 pin strap pull up is not used 8 bit ROM Flash interface results See Section 4 4 1 1 for information on using the CFG1 CFGO configuration pins which are always used together System Interfaces 4 21 Figure 4 4 Bus Configuration B 32 Bit DRAM Bus and 16 Bit SD Bus Low Word 7 Low Byte ElanSC400 Microcontroller 07 00 DRAM D15 D8 Low Word High Byte DRAM High Word Low Byte DRAM High Word High Byte DRAM Optional D23 D16 CFG3 031 024 DBUFRDL SD7 SDO Low Word XCVR SD7 SDO Low Byte ROM Flash A Low Word E EDS 015 High Byte XCVR ROM Flash A DBUFRDH ISA 8 16 PC Card 8 16 Notes Anytime the interface DRAM VL bus or ROM is programmed for 32 bits the matrix keyboard interface is not available See Section 1 3 for a complete description of which features can be traded for others See Figure 4 1 and Figure 4 2 for a summary of multiplexed pin options
141. at F000 FFFOh 1 On the lanSC400 microcontroller all ROMO accesses may be redirected to PC Card Socket A via a hardware strapping option which is sampled at reset A design could use PC Card Socket A as the sole boot device but this option is most useful for cost sensitive applications using a Flash boot device soldered to the board If the code in the boot device becomes damaged it may be reprogrammed by setting the strapping option to boot from Socket A After it boots the code in the PC Card card may copy itself to memory or open an MMS window to point to itself and redirect ROMO back to the on board Flash device by resetting bit 2 in the Pin Strap Status Register CSC index 20h 7 6 Memory Management 7 5 2 AMD However if the boot device is larger than 1 Mbyte or if additional external address decoding is done in the ROMCSO space note that booting may require a far jump to be stored in the top 16 bytes of the address space and for BIOS code to be stored between 00F0000h and OOFFFFFh in the address space Again this is because the default memory management involves no address translation by the lanSC400 and lanSC410 microcontrollers The MMU simply examines the CPU address and chooses one of several parallel memory spaces to access After the code has booted into the 00F0000 00FFFFFh range it has some programmatic control over which CPU addresses cause an access to ROMO Using the Linear ROMO Shadow Regist
142. been completed Any channel mapped for use with the infrared port must not be programmed for block mode Autoinitialize During autoinitialize the original values of the Current Address and Current Word Count registers are automatically restored to the values in the Base Address and Base Word Count registers of the given channel following the TC Priority After recognition of any one channel for service the other channels are prevented from interfering with that service until it is complete After completion of a service HOLD goes inactive until HLDA is inactive before HOLD is activated for a second cycle The fixed priority scheme is based upon the descending value of channel numbers Channel 0 is the highest priority DRQ must be held active until DACK becomes active in order to be recognized In the rotating priority scheme the last channel serviced becomes the lowest priority with the other channels rotating accordingly DMA Cycles Table 10 5 shows the eight ISA DMA cycle types and the command strobes generated by each The ISA command strobes MEMR and MEMW are asserted only for ISA cycles The TOR and IOW command strobes are asserted for both ISA and PC Card cycles Separate memory strobes are provided for accesses to ROM and PC Card memory The ROM interface uses dedicated ROMRD and ROMWR signals while the PC Card sockets use MCEL_A MCEH_A MCEL_B and DMA Controller 10 7 AMD
143. being placed into or read out of the receive FIFO Reading a character from the receive FIFO clears the time out interrupt Serial Port UART Table 15 3 Table 15 4 15 5 15 6 AMD Receive Line Status First Highest Serial Port Interrupt Priority Received Data Available Second Receiver FIFO trigger 16550 compatible mode FIFO time out Second Transmitter Holding Register Empty Transmit Third FIFO Empty 16550 compatible mode Modem status Fourth Lowest Note In 16450 compatible mode ID2 always reads back Ob The UART interrupts are enabled in ports OSF9h 02F9h and read in ports OBFAh O2FAh The serial port on the lanSC400 and lanSC410 microcontrollers has one internal IRQ that can be mapped to either IRQ3 or IRQ4 The Interrupt Configuration Register E CSC index D8h 6 5 controls which of these two IRQs is input to the programmable interrupt controller Table 15 4 shows the IRQ and I O address assignments for the serial port Serial Port IRQ Assignments Serial Port Interrupt Address COM1 03F8 03FFh COM2 02F8 02FFh INITIALIZATION The serial port is disabled at power on reset and must be configured by software before being enabled When the internal UART is disabled accesses to I O locations the 3F8 3FFh and 2F8 2FFh ranges go off the chip to the ISA bus i Enable the UART by setting the UART_ENB bit in the Parallel Serial Port Configurati
144. concurrency without sacrificing performance B The ROM Flash interface provides the flexibility to optimize the performance of ROM cycles including the support of burst mode ROMs This is beneficial because products based on the ElanSC400 and ElanSC410 microcontrollers may be implemented such that the operating system or application programs are executed from ROM Because the microcontrollers support a large number of external buses and interfaces the address and data buses are shared between the various interfaces to reduce pin count on the chip The result is a versatile architecture that can use various combinations of data bus sizes to achieve cost and performance goals The architecture provides maximum performance and flexibility for high end vertical applications but contains functionality for a wider horizontal market that may demand less performance A typical lower performance lower cost system might implement 16 bit DRAM banks an 8 bit ISA bus an 8 16 bit PC Card bus and use the internal graphic controller A higher performance full featured system might include 32 bit DRAM VL bus to an external graphics controller and a 16 bit ISA PC Card bus The following basic data bus configuration rules apply A complete list of feature trade offs to be considered in system design can be found in Section 1 3 When the internal graphics controller on the ElanSC400 microcontroller is enabled DRAM is always 16 bits wide
145. contain identical FPM devices The lanSC400 and lanSC410 microcontrollers do not alter memory access timing on interleaved banks because data bus contention would increase power consumption but the page size is effectively doubled which can increase page hit frequency and thus performance in some applications The DRAM controller is disabled at power on reset The DRAM drive strength timing andinterleaving parameters and each bank s type EDO or FPM and bank configuration depth width symmetry must be programmed before the DRAM is used This requires system software even in embedded systems unless the DRAM type is guaranteed never to change to detect the DRAM type and configuration and program the controller very early in the boot process Section 9 5 describes the algorithm required to determine the type and configuration If a DRAM device requiring refresh at greater than a 64 KHz rate note that no such devices are available at press time is used the device cannot be refreshed during Suspend mode unless self refresh is chosen Self refresh mode is global if chosen all DRAM devices in the system must support self refresh If the microcontroller is to operate at 2 7 volts one wait state must be added to DRAM hits generated by the MMU This is done by setting bit 5 in the Cache and VL Miscellaneous Register CSC index 14h DRAM Controller AMD 9 2 REGISTERS A summary listing of the chip setup and control
146. data bus widths and timing selectors page 3 138 GP CSC Memory Address Decode Register 22h 23h Index B9h Chip select C address page 3 140 GP CSC Memory Address Decode and Mask Register 22h 23h Index BAh Chip select C address SA3 SA0 mask page 3 141 GP CSD Memory Address Decode Register 22h 23h Index BBh Chip select D address page 3 142 GP CSD Memory Address Decode and Mask Register 22h 23h Index BCh Chip select D address SA3 SA0 mask page 3 143 GP CSC D Memory Command Qualification Register 22h 23h Index BDh GP CSC and GP CSD qualified with IOR IOW GP CSA and GP CSA ISA cycle data bus widths and timing selectors page 3 144 Suspend Mode Pin State Override Register 22h 23h index E5h Pin termination latch General Purpose Input Output and Programmable Chip Selects page 3 186 17 3 17 3 BLOCK DIAGRAM Figure 17 1 shows all the GPIO signals available on the lanSC400 and lanSC410 microcontrollers and their shared functions if any Figure 17 2 shows a block diagram of the GPIO CSx signals Figure 17 1 General Purpose Input Output Block Diagram GPIO31 STRB MCEL B GPIO30 AFDT MCEH GPIO29 SLCTIN RST GP1028 INIT REG B GPIO27 ERROR CD B GPIO26 PE RDY_B GPIO25 ACK BVD1 B GPIO24 BUSY BVD2 B GPIO23 SLCT WP B GPIO22 PPOEN GPIO2
147. displayed frame If the address programmed in the Cursor Address registers is outside of the displayed area of memory the cursor will not be visible on the screen The shape of the cursor is determined by the setting of the Cursor Start and Cursor End registers The Cursor Start Register defines the number of the first row line at which the cursor will be turned on The Cursor End Register defines the last row line used for cursor display The value of the Cursor Start and End registers must be less than or equal to the Maximum Scan Line Register and the Cursor End Register must be greater than or equal to the Cursor Start Register for the cursor to be visible The cursor causes the pixels underneath it to be turned on when it blinks on or normal character data to be displayed when it blinks off i e it is added to the underlying pixel data Cursor blinking may be programmed to one of four modes defined by bits 6 5 in the Cursor Start Register graphics index These modes are defined as in Table 20 7 Cursor Blinking Bits 6 5 Function Effect 0 Blinking Cursor blinks at 1 Hz 2 Hz if graphics index 52h 3 is set to 1 01 No display The cursor is not generated 10 Flashing Cursor blinks at half of frame rate which causes it to appear at half intensity 11 Non blink The pixels of the cursor are always added to the pixels of the character The following illustrates an example of programming the cursor se
148. each PC Card socket allows the system to power the cards up and down at any time However the major drawback is that there are many signals to buffer and total system cost board space and power consumption will all be increased This is acceptable for some but not for all systems If the system design does not fully buffer each PC Card socket then each of the shared signals on the lanSC400 microcontroller requires some amount of special consideration Table 19 18 lists the PC Card signals and the other parts of the system with which they are shared Shared PC Card Signals Address Other PC Card socket ISA bus ROM VL bus Data Other PC Card socket ISA bus ROM VL bus DRAM if 32 bit buffer controls available TOR IOW Other PC Card socket ISA bus WAIT Other PC Card socket OE WE Other PC Card socket Address Signals Shared with the other PC Card socket ISA bus ROM VL bus Because the address is shared with other interfaces the card will have to be powered up when itis connected and the system is operating i e notin Suspend mode Because the address is not bidirectional driven by the ElanSC400 microcontroller only the cards can be 3 3 V or 5 V the designer should ensure that nothing in the system pulls an address line up to 5 V During Suspend mode the address signals all go Low so the cards can be powered off in Suspend Data Signals Shared with the other PC Card socket ISA bus ROM VL bu
149. for ROMCSO ROMCS1 and ROMCS2 As mentioned above software control for the ROMCSO interface width was provided mainly for testing It is not recommended that the ROMCSO data width be set outside of the pin strap method Note that setting the ROMCSO interface width to 32 bit automatically enables the R32BFOE signal Once ROMCSO is configured as 32 bit all accesses to 32 bit ROM devices on ROMCS2 ROMCSO will result in the assertion of the R32BFOE signal Setting ROMCST or ROMCS2 to a 32 bit interface does not automatically enable R32BFOE if buffering is required in this case it must be supplied by the board designer On the lanSC410 microcontroller having a 32 bit ROM interface is mutually exclusive with the matrix keyboard On the ElanSC400 microcontroller having a 32 bit ROM interface is mutually exclusive with the internal LCD graphics controller and with the matrix keyboard Finally if the ROMCSO cycles have been redirected to the PC Card Socket A on the ElanSC400 microcontroller the width of the access is still controlled by the CFGO and CFG1 pin straps The 32 bit ROM option should not be selected concurrently with the option to boot from a PC Card ROM Flash Interface 8 5 2 2 8 5 2 2 1 8 5 2 2 2 Access Speed The ROM devices connected to ROMCS2 ROMCSO can be accessed at either normal speed or at fast speed Normal Speed Mode When Normal Speed mode is selected accesses to the ROM interface occur using
150. for the overlapping ISA window page 3 182 Overlapping ISA Window Size Register 22h 23h Index E2h Window size for the overlapping ISA window page 3 183 PC Card Mode and DMA Control Register 22h 23h Index F1h PC Card controller mode memory window allocation page 3 198 Graphics Index Registers Frame Font Buffer Base Address Register Low 3x4h 3x5h Index 4Fh Graphics Frame Buffer MMS Window enable MMS page select page 5 39 PC Card Index Registers Address Window Enable Register SE0h 3E1h Index 46h Socket memory windows 1 4 enable page 6 15 Memory Window 1 Registers various 3EOh 3E1h Index 58 5Dh MMS Window C configuration page 6 31 page 6 36 Memory Window 2 Registers various 3E0h 3E1h Index 60 65h MMS Window D configuration page 6 37 page 6 42 Memory Window 3 Registers various 3EOh 3E1h Index 68 6Dh MMS Window E configuration page 6 43 page 6 48 Memory Window 4 Registers various 7 2 SE0h 3E1h Index 70 75h MMS Window F configuration Memory Management page 6 49 page 6 54 7 3 7 3 1 7 3 2 7 3 3 AMD ADDRESS DECODING AND ALIASING Most designers are familiar with address aliasing which means that if an address is only partially decoded by a device that device will appear to exist multiple times throughout the address space However there are significant implica
151. gate control sources are forcing the CPU A20 signal to propagate Alternate CPU Reset Control Register Port OOEFh A special 8 bit read only control register provides a fast and reliable way to control the CPU Reset signal A read of this register resets the CPU This SRESET control mechanism together with both bit 0 of Port 0092 and SLOW RC command sequence trapping see Chapter 16 provide three different ways to generate SRESET control Forcing these SRESET events while in SMM mode will cause the SRESET signal to be asserted after the SMM routine is exited System Interfaces 5 gt 5 1 OVERVIEW Power management on the lanSC400 and lanSC410 microcontrollers includes a dedicated power management unit PMU and additional power management features built into each integrated peripheral Power management on the lanSC400 and lanSC410 microcontrollers provides a superset of APM 1 2 features Seven modes of operation allow fine tuning of power requirements for maximum battery life The lanSC400 and ElanSC410 microcontrollers can use the following techniques to conserve power Slow down clocks when the system is not in active use Shut off clocks to parts of the microcontroller that are idle Switch off power to parts of the system that are idle Automatically reduce power use when batteries are low The power management unit controls stopping and changing clocks SMI Syst
152. handler the SMMBASE is moved to the less A000 8000 CodeFragl intrusive location of Set new state base mov dword ptr cs 0FEF8h 0A0000h Am4869 CPU 3 13 3 14 Write sign message to the screen mov mov mov cld ax 0B800h Source and dest segments are the es ax display buffer si 80 2 Scroll everything up 1 line di 0 cx 80 24 movsw di 80 24 2 Init the new bottom line to spaces ax 0720h cx 80 stosw lt Now write the signon message gt 1 80 24 2 Init the destination to start of last line Remember the code fragments including the signon message are being loaded into memory 38000h and a8000h manually by this utility So you can t just use the asm offset directive to find the start of the string like you normally would Since only codefragl is copied into the 38000 area the signon message is re lative to the segment which is hard coded to be CS to codefragl which is the start of the code and to the size of codefragl which is SMI3000Happens CodeFragl mov mov WriteLoopl mov inc jz stosw jmp ExitWritel bx SMI3000Happens CodeFragl 8000h 07 Use light gray attribute al cs bx Attribute is in ah char is in al bx Next char al al Check for sentinel 0 short ExitWritel if sentinel bail else write to screen memory Writ
153. in addition to the modifications to the Vertical Adjust Vertical Display End and Vertical Border End registers described above Horizontal dot doubling is handled the same way as in the single scan case see above Frame Refill Delay Configuration The graphics controller must perform a FIFO flush refill at the beginning of each frame The time required to complete the flush and refill includes an arbitration delay plus a refill time The total time required depends on the display configuration as indicated in the table given under the description of bit 2 in the Extended Feature Control Register There are three options for accommodating the delay f bits 2 and 7 of the Extended Feature Control Register are both set to 0 the delay is automatically added to the end of the last line of each frame as described in the description of bit 2 in the Extended Feature Control Register This may cause contrast problems on some panels f Bit 2 of the Extended Feature Control Register is set and bit 7 is cleared the extra delay is not added automatically at the end of the last line of each line and must be accommodated by increasing the value of the Horizontal Total register so that the difference between the values programmed into the Horizontal Total and Horizontal Border End registers is sufficient to allow for the required delay When this is done all horizontal lines will have the same timing but the dot rate will need to be increased in o
154. intended to perform can be achieved by applying the logical OR function to the CD1 and CD2 pins from Socket A and then sending the resulting signal to the CD A ElanSC400 microcontroller pin as shown in Figure 19 3 PC Card Controller 19 19 Figure 19 3 19 5 11 19 5 11 1 Table 19 16 Vpp Control Card Detect Function for Socket A CDT ElanSC400 Microcontroller lt E 9 o CD2 The same can be done for CD B using CD1 and CD2 from Socket B This ensures that a card is not detected until it is fully inserted because the CD1 and CD2 pins are located at opposite edges of the card To avoid having to use the external gate a second Card Detect input pin can be configured for Socket A The input function A2 is multiplexed on one of the ElanSC400 microcontroller GPIO pins If the CD A2 function is selected via firmware the external gate can be eliminated Power Considerations Card Vcc and Vpp Control An 82365SL compatible Vcc and Vpp control interface is provided for both Socket A and Socket B The following interface signals provide control for the sockets that Vcc and Vpp supply Socket A PCMA VCC PCMA VPP1 PCMA VPP2 Socket B PCMB VCC PCMB VPP1 PCMB VPP2 These signals are multiplexed with other lanSC400 microcontroller interface signals The PC Card functionality for these pins can be enabled on a socket by socket basis Bits in the Power and RESE
155. into PC Card I O address space page 6 17 page 6 24 Memory Window Address Registers 3EOh 3E1h Various Memory Window address bits for mapping into the PC Card memory address space page 6 25 page 6 52 Memory Window Address Offset Registers 3EOh 3E1h Various Memory Window 0 offset address window write protect REG x active common or attribute memory mapping page 6 29 page 6 54 Setup Timing Registers 3EOh 3E1h Various Setup multiplier value and prescalar select before PC Card command goes active page 6 55 page 6 64 Command Timing Registers 3EOh 3E1h Various Command multiplier value and prescalar select page 6 56 page 6 65 Recovery Timing Registers 19 4 3EOh 3E1h Various Recovery multiplier value and prescalar select for address hold time after the PC Card command goes inactive until the address changes state PC Card Controller page 6 57 page 6 66 AMD 19 3 BLOCK DIAGRAM A block diagram of the PC Card controller is shown in Figure 19 1 The PC Card Socket B interface is shared with both the parallel port interface and the GPIO31 GPIO21 signals Only one of these interfaces can be enabled at one time The PC Card power control signals are shared with some of the GPIO signals Figure 19 1 PC Card Controller Block Diagram ElanSC400 Microcontroller
156. it does not allow transparent SMM operation the RAM at 30000h is visible to the host operating system The value of SMBASE can be changed but only from within an SMI handler The solution is to force an SMI to occur and change the SMBASE value from within the handler before the O S gets control This is exactly how the BIOS power management code does it Am486 CPU 3 11 The following simplified program shows how to move handler to A8000 behind the ISA VGA graphics space The program assumes the following SMM features of the currently running BIOS such as power management have been shut off to keep SMM from being relocated by the BIOS SMBASE is at its default 30000h value The program is running from DOS and there few enough TSRs and drivers so that the default SMRAM area 38000 3FFFFh is free for use The display is VGA card in a normal text mode 80x25 screen at B8000h Bi The area at B0000h is free for use by the program e g the internal graphics controller on the ElanSC400 microcontroller is disabled no monochrome card is attached and EMM QEMM etc have not appropriated the area This area is where the MMS A memory mapping window is located Given the above assumptions the code that follows is a fully functional program It contains a code fragment that is moved to the default SMRAM location and another code fragment that is moved to the target SMRAM location via use
157. known as the system data bus 16 bits This is because they are used to support not only ROM data but also PC Card and ISA data as well as DRAM and VL bus data if so configured Further references in this section to the system bus should be taken to mean that portion of the V3 and V2 byte lanes which service the PC Card ROM and ISA interfaces When the DRAM controller is configured to be 32 bits wide it uses V3 VO to carry DRAM data 031 00 Assuming a 16 bit ROM interface DRAM and ROM controller must share byte lanes V3 and V2 in this configuration Because V3 and V2 are used for the system bus as well as the DRAM interface in this configuration the loading on byte lanes V3 and V2 from these other system interfaces must be avoided while they are being used for DRAM data transfers This is where the DBUFOE signal comes into play It is used to electrically connect the devices on the system bus to byte lanes V3 and V2 when PC Card ROM or ISA accesses are being performed When VL bus or DRAM accesses are being performed the system bus is electrically disconnected from V3 and V2 Regardless of the DRAM controller data bus width if the ROM controller is configured to be 32 bits wide the byte lane usage for ROM accesses changes This time however the change is in a fashion that is more intuitive from the perspective of the ROM controller With a 32 bit ROM configuration V3 VO carry ROM data RD31 RDO in a byte lane usage that becomes
158. menu the system can apply user selections to CSC indexed registers 04 07h and finish booting DRAM Controller 9 13 9 5 2 9 14 Dynamic DRAM Detection Algorithm Many systems require the capability to dynamically configure the DRAM controller for the installed DRAM This involves determining the amount and type of DRAM installed and setting the registers appropriately The algorithm that does this must be careful to avoid bus contention between DRAM banks and between DRAM and ROM during the process Avoiding this contention is very difficult because contention can occur in several ways Using DRAM during detection e g using Bank 0 while detecting Bank 1 will result in contention B Executing the detection algorithm from 32 bit ROMs will result in contention If booting from 32 bit ROMs the detection algorithm must be run from the cache Testing for EDO DRAMs must be done carefully or contention will occur The detection algorithm must disable and enable banks but if the algorithm disables a bank while a DRAM refresh is active contention may result A delay must be inserted between disabling refresh and disabling any bank B f disabling or changing device width on a bank causes CAS signals to be transferred tothe keyboard controller a glitch on the upper CAS lines may result causing contention RAS2 RAS3 the upper CAS lines and MA12 automatically become DRAM control signals if Bank 0 is enabled
159. mode the output of the counter has a 50 duty cycle whenever the counter is loaded with an even count B The output is initially High Bi The count decrements by two with each clock cycle when the gate is held High E When the count reaches zero the output toggles state the initial count is reloaded and the sequence is repeated The period of the output signal is equal to the input clock period multiplied by the initial count loaded into the counter If the initial count is an odd number the output is High for N 1 2 cycles and is Low for N 1 2 cycles Mode 4 Software Triggered Strobe Mode 4 generates a strobe under software control In this mode the counter automatically begins to decrement one clock pulse after it is loaded with the initial count through software B The output signal is initially High The count decrements at the rate set by the clock input signal At the moment the terminal count is reached the counter generates a single strobe pulse on the output for one clock pulse duration If the counter is loaded with a count of N then a strobe pulse is produced at the output after 1 clock cycles Programmable Interval Timer 12 4 1 6 12 4 2 12 4 2 1 12 4 2 2 Mode 5 Hardware Triggered Strobe Mode 5 generates a strobe under hardware control The counting in this mode is initiated by a signal at the gate input B The output will be initially High Counting begins at the rising e
160. must be explicitly enabled by the designer The drive strength of the DRAM controller pins can be controlled using CSC indexed registers 06h and 07h Reducing the drive strength to the minimum required for the application will reduce power consumption and EMI emissions i DRAM self refresh during Suspend mode can be selected with CSC index 05h Extended refresh DRAM devices are supported The refresh timer may be programmed to run as slowly as 8 KHz Other DRAM controllerfeatures that minimize power consumption are generally transparent to system design but might be noticed during system bring up and debug These include B RAS signals are staggered during refresh for CPU bus clock frequencies of 16 and 33 MHz RAS signals are not staggered for CPU bus clock frequencies less than 16 MHz B RAS and CAS signals are not generated for disabled banks during refresh MWE is pulsed after reads from EDO devices to force them to three state the data bus Dynamic clock changes initiated by the PMU change the DRAM controller without extra complication Suspend mode operation is accomplished with a single 32 KHz clock Power Management in the DRAM Controller Power Management Effect DRAM Controller DRAM access CPU access to DRAM within graphics Programmable controller memory range DRAM access CPU access to DRAM not in graphics Programmable memory space DRAM Controller 9 15 9 16 DRAM Contro
161. of this field are the receiver s address Bit 0 of the ADDR byte is the C R Command Response bit indicates whether the transmission is from a primary Command or secondary Response station A receiver can use the remaining bits of the address field to determine whether or not the data being received applies to it A value of FEh in this field is used to specify a broadcast message that is applicable to all receivers within range of the transmitter A value of 00h is called the null address and no receiver should try to respond to this address CTL 1 byte The control field follows the address field and specifies the function of a particular frame The control byte command encodings are given in the IrLAP specification B INFO The Information field is optional Whether or not it is present and the meaning of the bytes it contains depends on the value in the CTL field since the CTL field determines the frame type If this field does exist it can be any power of 2 size between 64 bytes and 2048 2K bytes The information field does not have to be of fixed length but must be a multiple of 8 bits FCS Frame Check Sequence field 2 bytes A 16 bit cyclic redundancy check CRC in CCITT format allows the checking of received frames for errors that may have been introduced during frame transmission STO 1 byte Minimum one stop flag at the end of each frame The receiver treats multiple stop flags as single flag The st
162. on WE DMA write initiator TOR TC on OE PC Card Attribute Memory Read Function Three state Even byte Three state not valid Word Access Not valid Even byte Odd Byte Only Access Not valid Three state PC Card Controller 19 11 Table 19 5 PC Card Attribute Memory Write Function Lo Byte Access Even byte Xx Word Access Even byte Odd Byte Only Access Byte Access Three state Three state XX Even byte Odd byte Word Access Odd byte Even byte Odd Byte Only Access Byte Access Odd byte XX Three state Even byte Odd byte Word Access Odd byte Even byte Odd Byte Only Access Table 19 8 PC Card I O Read Function Byte Access Odd byte Three state Three state XX Even byte Odd byte Word Access Odd byte Even byte High Byte Only Byte Access Odd byte XX Three state Even byte Odd byte Word Access Odd byte Even byte Odd Byte Only Access Byte Access Odd byte XX XX MOPEX ee ee Even byte Word Access 19 12 PC Card Controller Odd byte Even byte Table 19 11 PC Write Function DREQ
163. on this bit will automatically reset the CPU The reset pulse lasts for a period predetermined by the CPU reset pulse width timer This bit is not automatically reset to Ob To perform successive resets of the CPU core by software this bit must be written to 0 and then back to 1b Bit 1 is used for A20 signal control Setting this bit allows the CPU Address 20 to be propagated to the system logic clearing this bit default state allows the CPU A20 signal to be driven Low as long as no other A20 gate control sources are forcing the CPU A20 signal to propagate If any A20 gate control source is forcing A20 to propagate then no other A20 gate control source will have any effect on A20 A20 signal propagation control System Interfaces 4 39 4 40 is an artifact of the PC AT legacy architecture The original purpose for the 80286 CPU and later CPUs having greater than 20 address lines was to support software applications that relied on the 8086 8088 address wrap Note This register causes the CPU s SRESET signal to be asserted for 16 CPU clock cycles Alternate Gate A20 Control Register Port OOEEh A special 8 bit read write control register provides a fast and reliable way to control the CPU A20 signal A dummy read of this register returns a value of FFh and forces the CPU A20 to propagate to the core logic while a dummy write to this register will cause the CPU A20 signal to be forced Low as long as no other A20
164. output to the RGB bits of the panel in unison FRC is the method used to obtain gray shading in which individual pixels are turned on and off very rapidly with the average duty cycle of the on time of a pixel determining its shading Configuring Graphics Modes Screen Controller Registers The screen controller registers control the timing of vertical and horizontal display signals Internally the screen controller contains counters for horizontal character elements and vertical rows The Horizontal Total and Vertical Border End registers determine the maximum values for their respective counters Values in the Horizontal and Vertical Display End Line Pulse Start Vertical Adjust and Border End registers are compared to the internal counters to generate internal and or external control signals for their respective functions Note that the actual horizontal line count is two greater than the value programmed into the Horizontal Total Register For the last line of each frame the horizontal end time is increased to allow time for flushing and reloading the internal FIFOs Example Configuration Consider an example where it is desired to display 20 rows of 64 characters with a character cell of 10x11 on a single scan panel of 640x240 pixels The Maximum Scan Line Register graphics index 40h must be programmed with a value equal to the number of lines in a character minus 1 which would be 10 in this example B The character width is set to
165. pe pe px gt lt gt lt gt lt gt lt x lt lt _ lt gt lt DX DX EA jx gt lt gt gt lt px P lt x lt pe gt pe TX x lt gt lt lt D lt 4 gt lt gt px gt lt EA px px gt lt 24 px P lt lt pe pe gt lt p pp gt lt gt lt lt px gt lt px EA lt gt lt px b lt gt lt x lt pe gt pe gt s lt gt 4 gt lt jx bX gt lt lt px jx DX gt lt lt b lt gt x lt x lt gt lt lt px p lt lt DX DX lt lt jx gt lt gt gt lt lt px gt lt pe gt pe lt pe gt lt gt lt EA px gt lt px x gt lt pe gt p gt lt x lt pe gt lt px gt lt lt gt lt px px gt lt pe gt pe lt gt lt ps pe gt jx DX gt lt lt jx gt gt lt lt lt gt lt ES c o 5 5 E ad ad Bo go 2 zc ez az Blink On Cursor On 20 19 Graphics Controller 20 4 5 2 Table 20 7 20 4 5 3 20 20 Cursor Generation The cursor position is set by use of the Cursor Address register pair to point to a character address within the currently
166. peripheral that decodes the full 24 lines of the address bus could be aliased four times in the microcontroller s address space Any 8 bit ISA peripherals and 16 bit ISA peripherals that rely on ISA signals SMEMR and SMEMW will decode only the 20 address lines of the original 8 bit ISA bus and thus could be aliased 64 times into the microcontroller s address space It is up to each designer to determine the requirements for generating SMEMR and SMEMW The most general design generates SMEMXx by qualifying MEMx with A20 A25 all equal to 0 avoiding any aliasing for the lower megabyte However if the only non VL memory mapped peripherals in the system reside below 1 Mbyte itis probably acceptable to simply connect the microcontrollers MEMx signals to the peripheral s lines Even if there are non VL memory mapped peripherals above 1 Mbyte for a closed system it is quite likely that the qualification can be performed with fewer than 6 address lines The designer should also be aware of the potential for making use of the ISA aliasing If a design has 16 Mbyte of RAM it may not be possible to address an ISA peripheral at for example 4 Mbyte but the peripheral could be programmed to respond at 4 Mbyte and the CPU could address it at 20 Mbyte 16 Mbyte 4 Mbyte MULTIPLE MEMORY SPACES One concept which may be foreign to some designers is that of multiple parallel memory spaces as opposed to a single linear space The El
167. programmed to 8 29 MHz the system should be programmed to use the Low Speed CPU clock at less than 8 29 MHz Otherwise this will not have any power saving affect but it will have a performance affect because the CPU will be put in hold occasionally to switch the clock Note that the automatic slowdown feature does not actually change the PMU s mode it simply changes the CPU clock speed The CPU clock speeds can be changed from any mode speed switching is done without violating the clock specifications For example when in High Speed mode the CPU clock can be changed between 33 MHz 16 MHz and 8 MHz without exiting to Low Speed mode to program the new speed The High Speed PLL can be disabled in Standby mode for additional power savings Note that it will take on the order of 200 usec to get it started back up In Standby Mode if the graphics controller on the lanSC400 microcontroller is displaying data the memory controller will operate off of the Low Speed PLL clock 36 MHz regardless of the High Speed PLL enable Clock Control 6 11 Table 6 6 CPU 1 Clock 33 MHz Clock Speed Per PMU Mode Hyper rompe 33 MHz 8 MHz 8 MHz 1 MHz 8 MHz 1 MHz Memory Clock On On On On System Clock 8 29 MHz 8 29 MHz 8 MHz 1 MHz 8 MHz 1 MHz Graphics Dot Clock On On DC PMU Clock 32 KHz 32 KHz Timer Clock On On RTC Clock 32 KHz 32 KHz On DC High Speed PLL On On Low Speed and Inte
168. registers except the selection of the R32BFOE signal which is an indirect result of selecting a 32 bit ROM interface via pin strapping options For a complete list of system level trade offs that are available for the lanSC400 and lanSC410 microcontrollers see Section 1 3 on page 1 16 Pin Multiplexing To support these feature trade offs many pins on the ElanSC400 and ElanSC410 microcontrollers are also traded off i e have multiple and usually mutually exclusive functions Figure 4 1 and Figure 4 2 show the pins and their alternate functions for each microcontroller A table showing how to configure each pin on the lanSC400 and lanSC410 microcontrollers can be found in Appendix Pin Termination When a particular function is configured to be available to the user system the functions of the pins on the ElanSC400 and ElanSC410 microcontrollers change accordingly When the pin function changes the termination of the pin can and often does change Where there may have been an internal pull up the signal may now just be three stated or have a pull down connected Internal design considerations on the ElanSC400 and ElanSC410 microcontrollers require that system firmware latch in or activate the new termination s as a separate operation from the actual pin function selection This is done by setting the TERM LATCH bit in the Suspend Mode Pin State Override Register CSC index E5h 0 after configuring one or more of the pin
169. selects whether or not the system will boot from PC Card Socket A memory card or from the device attached to ROMCSO This pin is sampled at the deassertion of RESET This pin is not supported on the ElanSC410 microcontroller CFG1 CFGO Configuration Pins 1 0 select the data bus width for the physical device s selected by the ROMCSO pin i e 8 16 or 32 bit These pins are sampled at the deassertion of RESET Memory Interface Column Address Strobe High indicates to the devices that a valid column address is asserted on the MA lines These CAS signals are for the odd banks Banks 1 and 3 CASH3 CASH are for the high word and CASH1 CASHO is for the low word CASL3 CASLO Column Address Strobe Low indicates to the DRAM devices that a valid column address is asserted on the MA lines These CAS signals are for the even banks Banks 0 and 2 CASL1 CASLO are for the low word CASL3 CASL2 are for the high word D31 DO Data Bus is used for DRAM and local bus cycles This bus is also used when interfacing to 32 bit ROMs MA12 MAO Memory Address The DRAM row and column addresses are multiplexed onto this bus Row addresses are driven onto this bus and are valid upon the falling edge of RAS Column addresses are driven onto this bus and are valid upon the falling edge of CAS Write Enable indicates an active write cycle to the DRAM devices This signal is also used to three
170. series of refreshes of the LCD screen The duty cyclesthat produce the grayscales are evenly spaced across the range of always off to always on For example when using 4 grayscale mode the pixel on average duty cycles are 0 33 6696 and 100 for the 4 grayscales While graphics index 43h 1 selects the number of grayscales the graphics controller is capable of generating the configuration of the graphics buffer dictates the maximum number of grayscales that can be displayed at any time The graphics buffer can be configured so that either 1 2 or 4 bits of data are required to define each pixel This number of BPP often referred to as the color depth of the graphics buffer in conjunction with the grayscale mode 4 16 defines the maximum number of different grayscales which can be seen on the LCD at any time The maximum grayscales is the lesser of 2BPP and the number of grayscales available Due to its roots in the CGA standard the graphics controller on the lanSC400 microcontroller considers each grayscale as having a Red Green Blue and Intensity component Each componentis either on or off and is each is nominally represented by a bit in the graphics buffer The four RGBI bits taken together can be thought of as Graphics Controller representing a color code with a range of 0 15 Since CGA supported 2 graphics buffer mapping the other two bits had to come from somewhere else In this case th
171. set at rates from once per second to once per day Update ended interrupt Provides update cycle status These three interrupts are enabled in Register B RTC index OBh 6 5 4 Table 13 2 lists the values of RS3 RSO in Register A RTC index OAh 3 0 used to specify different periodic interrupt rates Table 13 2 Using RS3 RSO to Specify a Periodic Interrupt Rate None 3 90625 ms 7 8125 ms 122 070 us 244 141 us 488 281 us 976 562 us 1 953125 ms 3 90625 ms 7 8125 ms 15 625 ms 31 25 ms 62 5 ms 125 ms 250 ms 500 ms 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 of of of of Of a O O O O oO OF O O O O O O O O Real Time Clock 13 5 13 4 2 13 4 3 13 4 4 13 4 5 13 6 Clock The RTC clock is the 32 768 KHz generated by the internal oscillator This clock is used by many cores and is always available as long as there is power Internal Oscillator Control Bits The normal operational setting for the internal oscillator control bits DV2 DVO in Register Ais 010b This turns the oscillator on uses an internal time base of 32768 Hz and enables the countdown chain to run at the internal time base frequency A value of 11xb turns the oscillator on but holds the countdown chain in reset In this mode the time and date updat
172. shown to display the corresponding screen Flat Mapped Graphics Mode Data Formats Following are the data formats for the three flat mapped graphics modes 16 level or 4 level grayscaling may be selected when using 1 or 2 BPP flat mapped modes 16 level grayscaling should be used with the 4 BPP flat mapped mode Note that the grayscale palette see Section 20 4 7 should be used for color mapping in the flat mapped modes Graphics Controller 20 27 Figure 20 20 Memory Byte Format 1 Flat Mapped Graphics Mode Figure 20 21 16 Grayscale Palette Mapping 1 Pixel 1 BPP Flat Mapped Graphics Mode Figure 20 22 Memory Byte Format 2 BPP Flat Mapped Graphics Mode Bit 7 Bit 0 PELO PEL 1 PEL2 PEL3 PEL4 PEL5 PEL6 PEL7 Leftmost Rightmost Red Green Blue Intensity 0 0 0 PEL Bit 0 Bit 7 Bit 0 PEL 0 PEL 0 PEL 1 PEL 1 PEL2 PEL2 PEL3 PEL3 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Leftmost Rightmost Figure 20 23 16 Grayscale Palette Mapping 1 Pixel 2 BPP Flat Mapped Graphics Mode Figure 20 24 Memory Byte Format 4 BPP Flat Mapped Graphics Mode Red Green Blue Intensity 0 0 PEL PEL Bit 1 Bit 0 Bit 7 Bit 0 PELO PELO PELO PELO PEL1 PEL1 PEL1 PEL1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Leftmost PEL Rightmost PEL Figure 20 25 1
173. software can effectively ignore the fact thatthe physical address ofthe first instruction fetched is nowhere near the physical address of the rest of the boot ROM because the high order address lines are not decoded by the ROM Memory Management 7 3 7 3 4 7 4 7 4 If however the boot ROM is larger than 1 Mbyte the designer must be aware that top 16 bytes of the boot ROM must be reserved for afar jump to a location in segment which will reside immediately below 1 Mbyte in the same boot ROM Because of compatibility issues at boot up the only locations in the CPU address space that map to the boot ROM are the 64 Kbytes at the very top of memory and the 64 Kbytes immediately below 1 Mbyte This is discussed in more detail later ISA Bus Addressing The lanSC400 and ElanSC410 microcontrollers provide 26 bits of address on the SA address bus However standard 8 bit ISA devices only decode the lower 20 bits and standard 16 bit PC AT compatible devices decode the lower 24 bits When a cycle is not claimed by internal devices DRAM controller or ROM controller it is driven to the VL bus If the cycle is not claimed on the VL bus an active VL LDEV signal it is then driven to ISA Since the ISA bus receives all unclaimed cycles and the microcontroller s SA bus is 26 bits it is possible to address up to 64 Mbytes on the ISA bus The definition of the ISA bus only contains 24 address lines so a
174. software control bit can command the LCD controller to power up or power down in a normal mode or power down in emergency mode This gives the following three cases Normal Power Up On initial power up LVDD and LVEE are both deasserted High The SCK LC FRM M and all LCDD data signals are held Low Then LVDD switches from High to Low The SCK LC FRM M and all LCDD signals are held Low After waiting for the delay programmed into bits 2 0 of PMU Control Register 1 graphics index 50h the screen controller is enabled so that LC FRM the LCDD bits and M begin cycling After waiting for the delay programmed into bits 5 3 of PMU Control Register 1 LVEE is asserted Normal Power Down First switches from Low to High SCK LC the LCDD bits and M continue to run After waiting for the delay programmed into bits 2 0 of PMU Control Register 2 graphics index 51h the screen controller is disabled and LC FRM the LCDD bits and M are forced Low coincident with the end of the current horizontal line After waiting for the delay programmed into bits 5 3 of PMU Control Register 2 LVDD is asserted to complete the power down Emergency Power Down First LVEE switches from Low to High SCK LC FRM the LCDD bits and M continue to run After waiting for one graphics dot clock period the screen controller is disabled and LC FRM the LCDD bits and M are forced Low After waiting again for one graphics dot clo
175. state EDO DRAMs at the end of EDO read cycles RASS RASO Row Address Strobe indicates to the DRAM devices that a valid row address is asserted on the MA lines ROMCS2 ROM 0 ROM Chip Selects are active Low outputs that provide the chip select for the BIOS ROM and or the ROM Flash array After power on reset the ROMCSO chip select will go active for accesses into the 64K segment that contains the boot vector at address 3FF0000h to 3FFFFFFh ROMCSO can be driven active during a linear direct address decode of certain addresses in the high memory 00A0000 00FFFFFh region By default direct mapped accesses to the 64 Kbyte region from OOFFFFOh to OOFFFFFh are enabled to support legacy PC AT BIOS This area is known as the aliased boot vector It can also be activated by accessing a Memory Management System MMS page that points to the ROMO address space ROMCS is activated only when accessing an MMS page that points to it A third MMS mappable ROMCS2 signal is available by reconfiguring one of the chip s General Purpose Input Output GPIO pins for this function and also requires the use of MMS to access devices connected to it ROM Read indicates that the current cycle is a read of the currently selected ROM device When this signal is asserted the selected ROM device may drive data onto the data bus ROM Write indicates that the current cycle is a write of the currently selected ROM device When this signal is asserted th
176. the 32 bit DRAM interface and the 32 bit ROM interface Data D Bus The D15 DO data bus is used during 16 bit DRAM cycles For 32 bit DRAM VL bus and ROM cycles this bus is combined with the system data bus In other words the data bus pins D31 D16 are shared with the system data bus pins SD15 SDO The lanSC400 and ElanSC410 microcontrollers support the data bus configurations listed below External transceivers or buffers are required in some bus configurations to isolate the buses and to provide proper data steering Configuration A 16 bit DRAM bus 8 16 bit ROM 32 bit VL bus disabled internal graphics controller enabled disabled matrix keyboard interface enabled disabled Configuration B 16 32 bit DRAM bus 8 16 bit ROM 32 bit VL bus enabled disabled internal graphics controller disabled matrix keyboard interface disabled Configuration C 16 32 bit DRAM bus 32 bit ROM 32 bit VL bus enabled disabled internal graphics controller disabled matrix keyboard interface disabled The ElanSC400 and ElanSC410 microcontrollers offer flexibility in configuring the ROM and DRAM data buses for different widths The ROM widths 8 16 32 bits are programmed during power up through two pin straps CFGO and CFG1 When DRAM is configured for 16 bits and the VL bus is disabled the pins SD15 SD0 031 016 are dedicated for the system SD bus This results in Configuration When DRAM is configured for 32 bits or
177. the VL bus is enabled the pins 5015 500 031 016 are shared between the SD bus and DRAM VL bus This corresponds to Configuration B or Configuration C Control signals are available to control an external SD buffer when necessary to isolate the variable system data bus loading ISA PC Card etc from the local data bus or to level shift voltages Devices on the D bus side connected to the microcontroller are the DRAM and the VL bus target on the SD buffer side away from the microcontroller are the ISA ROM and PC Card devices The DRAM widths 16 32 bits as well as the VL bus enabling disabling are programmed through configuration registers When enabled the VL bus is always 32 bits wide The graphics controller on the ElanSC400 microcontroller is enabled disabled through a configuration register Up to four 16 or 32 bit banks of DRAM are supported System Interfaces Table 4 10 4 5 1 1 4 5 1 2 4 5 1 3 The ElanSC400 and lanSC410 microcontrollers contain a total of 4 data byte lanes which are referred to as V3 V2 V1 and VO The functionality of these four data byte lanes depends on the bus configuration chosen as shown in Figure 4 3 Figure 4 4 and Figure 4 5 beginning on page 4 21 The byte lanes map to the microcontroller s pins as shown in Table 4 10 Byte Lanes D7 DO D15 D8 07 00 023 016 SD15 SD8 D31 D24 Configuration A 16 Bit DRAM Bus and 16 Bit SD Bus In this
178. their divisors The divisor for any baud rate can be calculated by dividing 115 200 by the baud rate 15 4 Serial Port UART AMD Table 15 2 Baud Rates at 1 8432 MHz 15 4 2 Error Percentage Desired Decimal Hexadecimal Difference Between Baud Rate Divisor Divisor Desired Baud Rate and Actual 50 75 110 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 UART Frame Each byte of data is transferred using a format called a frame Figure 15 2 shows the format of a typical UART frame The transmitter and receiver must agree on the frame format as well as the baud rate or transmission will not be successful The frame format is determined by the value written into the Line Control Register ports O3FBh O2FBh A frame consists of a start bit 5 8 data bits an optional parity bit and 1 1 5 or 2 stop bits Transmission of a frame is initiated when software writes a byte to the Transmit Holding Register ports O3F8h 02F8h First the SOUT output is driven Low for one baud rate clock period This is the start bit Next 5 6 7 or 8 data bits from the Transmit Holding Register are driven out on SOUT one bit per clock period starting with bit O the LSB If parity has been enabled in the Line Control Register a parity bit is then clocked out Finally 1 1 5 or 2 stop bits are clocked out again according to the frame for
179. time for a period equal to three and a half DMA clock periods This means that PC Card DMA verify cycles can only be run in single transfer DMA mode For PC Card DMA cycles the PC Card controller timing set registers are disabled During these cycles all PC Card cycle timing is dictated by the DMA controller The standard setup command and recovery timing for these PC Card DMA cycles will be 102 ns min 250 ns min and 53 ns min respectively based on a controller clock frequency of 4 MHz If the DMA controller clock frequency is modified the PC Card setup command and recovery timing will be scaled accordingly A PC Card DMA device can add wait states to memory or I O accesses by asserting the WAIT signal if the proper setup from command is observed PC Card Controller 19 17 19 5 8 19 5 8 1 19 5 9 19 18 System Interrupt Control System interrupt generation by the PC Card controller is very flexible APC Card can generate aninterruptrequestonits RDY x IREQ x pin when configured for the Memory and I O mode Also the PC Card controller can generate card status change interrupt when changes in state are detected on any of several PC Card interface signals when the socket is configured for either Memory only or Memory and I O mode B Finally a Ring Indicate signal can be enabled to the PMU block to indicate a change in card status when a card s BVD1 x STSCHG signal is active and the socket
180. timer is then set for some amount of time and enabled to cause an SMI NMI the SMI NMI routine is exited and control is returned to the application software this is for software debounce 4 Onatimertime out key timer interrupt the SMI NMI interrupt occurs and the keyboard service code runs through all the keys to find all that are pressed These are compared to the keys pressed the first time through and any that match are reported back to the software for its use The timer is reset and re enabled the SMI NMI is exited and control is returned to the software 6 The nexttime the timer times out the keyboard service code looks for new keys pressed and does the software debounce before reporting them Any keys that are detected Low for a predetermined amount of time are reported at the programmed typematic rate 7 When all keys are released the keyboard service code starts over at the top programming all columns Low and enabling the key pressed interrupt to cause an SMI NMI Scenario 2 Simple Matrix Keyboard Support by Polling The following is one possible scenario of how the system would use the keyboard controller with polling if PC AT compatibility is not require i e the system runs only custom software or guarantees all keyboard accesses go through BIOS and not directly to the keyboard controller 1 The software running simply goes out and walks a 0 through the columns and reads the rows until a key is detected
181. to BNDSCN TCK the controller moves to the Select DR state Select DR Scan State This is atemporary controller state The test data register selected by the current instruction retains its previous state If BNDSCN TMS is held Low and a rising edge is applied to BNDSCN_TCK when in this state the controller moves into the Capture DR state and a scan sequence for the selected test data register is initiated If BNDSCN TMS is held High and a rising edge is applied to BNDSCN the controller moves to the Select IR Scan state The instruction does not change in this state Capture DR State In this state the BSR captures input pin data if the current instruction is EXTEST or SAMPLE PRELOAD The other test data registers which do not have parallel input are not changed The instruction does not change in this state When the TAP controller is in this state and a rising edge is applied to BNDSCN TCK the controller enters the Exit1 DR state if BNDSCN TMS is High or the Shift DR state if BNDSCN_TMS is Low Shift DR State In this controller state the test data register connected between BNDSCN TDI and BNDSCN TDO as a result of the current instruction shifts data one stage toward its serial output on each rising edge of BNDSCN TCK The instruction does not change in this state When the TAP controller is in this state and a rising edge is applied to BNDSCN TCK the controller enters the Exit1 DR state if BNDSCN TMS is High or rem
182. to ISA Note that there is an exception if the ISA window is put over the graphics region Font memory has write protect priority over the normal system memory write protect window If the programmer does not write protect the font area and then puts a system Graphics Controller memory write protect window in the same place as the font window the font window will not be write protected Graphics hits are write through cacheable by setting CSC index 14h 7 An SMM save state region cannot be put over a graphics area Non cached graphics hits have higher priority than linear ROMO shadowed non shadowed or boot hits which are higher than the non cache window hits When using the non cache window make sure the window is not in the range 00C0000 00FFFFFh SFF0000 3FFFFFFh the SMM save state region or PC Card windows Figure 20 2 16 Kbyte Graphics Frame Buffer MMS Window Implementation 20 4 3 CPU Address Space OOBBFFFh 16 Kbyte Graphics Frame Buffer 00B8000h System Memory DRAM Address Space _ 16 Kbyte 10 16 Kbyt 64 Kbyte __01 16 Kbyte Block 00 p 16 Kbyte Page Select Control Bits CGA Graphics Modes In the CGA graphics modes also called all points addressable or APA graphics memory bits directly represent display pixels No indirect mapping to a font table is used The use of either one or two bits per pixel d
183. to act as activity triggers wake up sources or SMls Serial Infrared Port SIRIN Infrared Serial Input is the digital input for the serial infrared interface SIROUT O Infrared Serial Output is the digital output for the serial infrared interface PC Card Controller ElanSC400 Microcontroller Only Note The names in parentheses in this section are those used in PC Card Memory and I O mode BVD1 A STSCHG_A BVD1 B STSCHG B Battery Voltage Detect is driven Low by a PC Card when its on board battery is dead When the PC Card interface is configured for I O this signal can be driven by the card to indicate a card status change It is typically used to generate a system IRQ in this mode These pins are not supported on the lanSC410 microcontroller BVD2_A SPKR DRQ A BVD2 B SPKR Battery Voltage Detect is driven Low a Card when its on board battery is weak When the PC Card interface is configured for I O this signal can be driven by the card s speaker output When enabled this signal can drive the chip SPKR output When PC Card DMA is enabled the DMA request from the PC Card can be programmed to appear on this signal See also the description for WP A TOIS16 A A and WP B IOIS16 B DRQ_B the DMA request can also be programmed to appear on these pins These pins are not supported on the lanSC410 microcontroller CD A CD B Detect indicates t
184. to control the keyboard interface on the lanSC400 and lanSC410 microcontrollers is shown in Table 16 1 Complete register descriptions can be found in the Elan SC400 Microcontroller Register Set Reference Manual order 21032 Table 16 1 Keyboard Interface Register Summary Description in Register Set Manual Address Register Keyboard Interface Function Keyword Pin Mux Register B 22h 23h Keyboard Row KXBD ROW12 KBD ROWT page 3 45 Index 39h or ISA signals enable Keyboard Column KBD COL1 KBD COLO or XT keyboard XT CLK XT DATA signals enable Pin Mux Register C 22h 23h Matrix keyboard usage state for proper pin page 3 46 Index 3Ah termination during Suspend Wake Up Source Enable 22h 23h Wake up source enable matrix key press page 3 59 Register A Index 52h Wake Up Source Status 22h 23h Wake up source status matrix key press page 3 63 Register A Index 56h Activity Source Enable Register B 22h 23h Activity source enable matrix keyboard key page 3 72 Index 63h press keyboard timer time out and CPU access to keyboard registers Activity Source Status Register B 22h 23h Activity source status matrix keyboard key page 3 76 Index 67h press keyboard timer time out and CPU access to keyboard registers Activity Classification Register B 22h 23h Primary or secondary activity classification page 3 80 Index 6Bh matrix keyboard key press keyboard timer time out and C
185. to disabled A bit must be setto enable the system to transition to Hyper Speed mode Actions Taken During Hyper Speed Mode The following actions are taken on the lanSC400 and lanSC410 microcontrollers during Hyper Speed mode All parts of the system are clocked at full speed A summary of clock speeds PMU mode is shown in Table 6 6 Because this mode uses the CPU core PLL there is a 1 ms delay in changing the CPU frequency a CPU Stop Grant must be done using the CPU s Stop Clock Interrupt Automatic slowdown is available in this mode When enabled via CSC index 81h the automatic slowdown feature slows down the CPU clock at a programmed interval for a programmed amount of time Although power is saved the automatic slowdown feature reduces average system performance because it slows down the CPU clock per a duty cycle that is software controllable via CSC index 81h Power Management 5 4 1 2 5 4 1 3 5 4 2 The CPU clock is programmable to be 66 or 100 MHz The bus clock remains at 33 MHz in Hyper Speed mode Note that the CPU clock on the ElanSC400 and ElanSC410 microcontrollers does not switch dynamically per type of access cycle Entering Hyper Speed Mode The system enters Hyper Speed mode when Hyper Speed Mode is enabled and either of the following occurs The system goes to High Speed mode After a 1 ms delay for the CPU core PLL to start up and stabilize the sys
186. to the most significant bit and BNDSCN TDO connected to the least significant bit of the test data register Data is shifted one stage bit position within the register on each rising edge of the test clock BNDSCN TCK Bypass Register BPR The Bypass Register provides a path from BNDSCN TDI to BNDSCN TDO with one clock cycle latency It helps to bypass a chip completely while testing boards containing many chips Boundary Scan Register BSR The Boundary Scan Register is a single shift register path containing the boundary scan cells that are connected to all input and output pins of the ElanSC400 and ElanSC410 microcontrollers Figure 21 2 shows the logical structure of the BSR While output cells determine the value of the signal driven on the corresponding pin input cells only capture data they do not affect the normal operation of the device Data is transferred without inversion from BNDSCN TDI to BNDSCN TDO through the BSR during scanning The BSR can be operated by the EXTEST and SAMPLE instructions Device Identification Register DID The Device Identification Register is a 32 bit register that contains AMD s ID code for the ElanSC400 and ElanSC410 microcontrollers Figure 21 1 shows the format Format of Device Identification Register 3130 29 28 27 26 25 24 23 222120 191817 16 15 14 1312 1110 9 8 765432 ifo Manufacturer m u 21 2 Test and Debugging AMD 21 2 3 Instruction Register
187. transmit and receive underflow terminal count end of transmission status and High Speed interrupt request status page 3 190 IrDA CRC Status Register 22h 23h Index ECh CRC error detect and receive abort page 3 192 IrDA Own Address Register 22h 23h Index EDh Assigned address page 3 193 IrDA Frame Length Register A 22h 23h Index EEh Transmit mode Length of transmitted infrared data frame first part Receive mode Length of received infrared data frame first part page 3 194 IrDA Frame Length Register B 18 2 22h 23h Index EFh Transmit mode Length of transmitted infrared data frame second part Receive mode Length of received infrared data frame second part Infrared Port page 3 195 18 3 Figure 18 1 1 8432 MHz AMD BLOCK DIAGRAM A block diagram of the infrared port is shown in Figure 18 1 Note that the UART SOUT and SIN pins become disabled when the infrared interface is enabled To complete the serial infrared implementation optical infrared transceivers and their support circuitry e g drivers must be added externally to the chip Infrared Port Block Diagram DRQ DACK Select device and mode Standard UART State Machine 16550 UART Transmit Serializer Bus Interface includes FIFO Receive Serializer SIN High Speed Infrared Receive Serializer E High S
188. upper screen row scan line numbers For example a dual scan 640x240 panel consists of two 640x120 panels joined together If the font size character box size has been set to 8x14 width x height by programming the Maximum Scan Line Register to 13 and setting the character width to 8 the number of lines in a character is not an integer multiple of the number of lines in the half screen i e 120 14 lt gt 0 The Dual Scan Row Adjust Register should be programmed with the number of extra row scan lines at the top of the lowerscreen when a character box overlaps the upper and lower screens This will happen whenever the number of lines in a half screen is not an integer multiple of the character box height Continuing the above example there are 120 lines in a half screen and the character box height is 14 Given that there are 8 whole character rows in the upper screen this leaves Graphics Controller 20 33 20 4 8 2 2 20 34 120 8 14 8 extra lines in the upper screen These 8 lines are the upper portion of a 14 line character box overlapping the upper and lower screens The number of extra lines in the lower screen is therefore 14 8 6 lines In this case a value of 6 should be programmed into the Dual Scan Row Adjust Register In cases where the number of lines in a half screen is an integer multiple of the character box height the Dual Scan Row Adjust Register should be set to zero In general Dual Sc
189. used to control the assertion of the LCD s VDD voltage This is provided to be part of the solution in sequencing the panel s VDD DATA and VEE in the proper order during panel power up and power down to prevent damage to the panel from CMOS driver latch up VDD is used to power the LCD logic and is usually 5 V or 3 V DC This pin is not supported on the lanSC410 microcontroller LCD Panel VEE Voltage Control is used to control the assertion of the LCD s VEE voltage This is provided to be part of the solution in sequencing the panel s VDD DATA and VEE in the proper order during panel power up and power down to prevent damage to the panel from CMOS driver latch up VEE is the LCD contrast voltage and is either positive or negative with an amplitude of 15 30 V DC This pin is not supported on the lanSC410 microcontroller LCD Panel AC Modulation is the AC modulation signal for the LCD AC modulation causes the LCD panel drivers to reverse polarity to prevent an internal DC bias from forming on the panel This pin is not supported on the ElanSC410 microcontroller SCK LCD Panel Shift Clock is the nibble byte strobe used by the LCD panel to latch a nibble or byte of incoming data Commonly referred to by LCD panels as CL2 or CP2 This pin is not supported on the ElanSC410 microcontroller Boundary Scan Test Interface BNDSCN Test Clock is the boundary scan input clock that is used to shift serial data patte
190. used to define the operation of the channels including mode Programmable Interval Timer 1 Channel Count Registers Ports 0040 0042h Store the current count values for each channel Programmable Interval Timer 1 Counter Latch Command Register Port 0043h When the counter latch command is valid the value in the status register plus the output signal of the counter is latched into this status latch register The status in this register is cleared only after the status is read by the CPU Programmable Interval Timer 1 Read Back Command Register Port0043h Allows the status and current mode of each channel to be read Programmable Interval Timer 1 Status Registers Ports 0040 0042h Contain the programmed mode and the null count value for each timer channel System Control Port B NMI Status Register Port 0061h Controls the gate input for Timer Channel 2 and reflects the output signal state for Channel 2 Programmable Interval Timer 12 1 Table 12 1 Programmable Timer Register Summary Description Register Address Programmable Timer Function in Register Set Manual DRAM Refresh Control Register 22h 23h PIT as DRAM refresh clock page 3 14 Index 05h Pin Mux Register A 22h 23h as PIT clock input page 3 44 Index 38h 12 3 BLOCK DIAGRAM Figure 12 1 shows a block diagram of the programmable interval timer Figure 12 1 Programmable Interval Timer Block Diagram
191. used to select between 8 16 or 32 bit data bus widths for the physical device that is connected to the ROMCSO pin Data width selection for the devices that connect to ROMCS1 and ROMCS2 is done through a programmable register The CFG2 pin strap on the ElanSC400 microcontroller selects whether or not the system will boot from the device attached to ROMCSO or from the PC Card Socket A memory card See Section 7 6 4 2 for more information on the redirection of ROMCSO to PC Card Socket A B The CFG3 pin strap is used for selecting between the GPIO I O pins and the SD bus buffer control signals DBUFOE DBUFRDL and DBUFRDH When the buffer control signal configuration is selected using the CFG3 pin DBUFOE DBUFRDL and DBUFRDH signals will be driven from boot time on for all accesses to the peripheral data bus These signals are used for the external transceiver control Each configuration pin has an internal pull down that will take effect to configure the ROM interface if no other external termination is supplied The internal pull downs on the CFG pins are very weak and may be pulled up to the CPU core voltage via a 10 kilohm resistor to select the configuration options described above Table 8 2 provides an overview of the configuration pin functions These pins are described in more detail in Chapter 4 ROM Flash Interface 8 7 Table 8 2 Notes Pin Strap Bus Buffer Options DBUFOE CFG3 CFG1 CFGO DBU
192. via an index or secondary address into an array of registers Because of the use of this secondary address the indexed register may be thought of as residing in a separate indexed register space The secondary address itself is often referred to as an index with many of the same properties as the index of an array Finally the storage element itself which holds the index while data is being read from or written to an indexed register is known as the index register There are four indexed register spaces on the lanSC400 and ElanSC410 microcontrollers The names of these spaces and the direct mapped port addresses through which their index and data registers are accessed are listed in Table 2 2 Refer to the appropriate chapter in this manual for detailed information on the function and usage of registers within the indexed register spaces Refer to the lan SC400 Microcontroller Register Set Reference Manual for bit level reference information concerning registers in these indexed spaces Indexed Register Space Indexed Register Space Access through Direct Mapped Ports Chip Setup and Control CSC 0022h index 0023h data Real Time Clock RTC and CMOS RAM 0070h index 0071h data LCD Graphics Controller ElanSC400 microcontroller only 03B4h index 03B5h data MDA 03D4h index 03D5h data CGA PC Card Controller ElanSC400 microcontroller only O3E0h index data CSC indexed registers a
193. was 03Bbh In order to access an indexed register first write an index to the index register via the index port and then write to or read from the data register via the data port An example of an access to the MDA registers follows mov DX 3B4h Access to IO ports with 16 bit addresses requires the use of DX mov AL 10h Select the MDA Light Pen Register out DX AL Write the index of the Light Pen Register to the hardware inc DX Point to the MDA data port in AL DX Read the MDA Light Pen Register into AL Note that the CSC and RTC register sets listed in Table 2 2 have index and data ports that use only 8 bit addressing Indexed register schemes that utilize 8 bit I O port addressing have two main advantages over those that require 16 bit addresses First 8 bit addresses do not require the use of DX The AL Register is the minimum requirement see earlier examples This can be useful if the initialization code needs to conserve CPU register use in cases where the DRAM is not available yet etc The second advantage of using 8 bit I O addresses is that common 16 bit instructions can be used to store data very easily For example to store the value 81h to CSC index 65h as shown in Figure 2 2 the following 16 bit I O instruction may be executed mov AX 08165h out 22h AX This technique is widely used when a table of indexed registers needs to be written to known values Simply create a table of registers and indexes point t
194. when the limit of the screen controller addressing range is reached e g due to scrolling operations The graphics controller memory addressing range is 128 Kbytes in 4 BPP and 2 BPP modes and 64 Kbytes in 1 BPP mode This is the upper limit on the memory utilization of a screen or contiguous set of screens The start address register and character counter are extended to 15 bits to allow for full scrolling within the addressing limits Graphics Controller 20 23 Table 20 9 20 4 6 1 20 24 Note The start address register described this section refers to 10 bit internal register controlled by the Frame Buffer Base Address Register and the Frame Font Buffer Base Adaress Hegister Low graphics index 4Dh and 4Fh respectively In all flat mapped configurations each character address corresponds to a row of eight pixels Example Memory Configurations Maximum Number of Screens Screen Memory Resolution Bytes Screen 640x200 480x320 Memory Configuration Example 640x240 Panel Flat Mapped Mode Figure 20 16 Figure 20 17 and Figure 20 18 illustrate one way screen memory may be used on a 640x240 panel in mode Another acceptable way to set up the memory map would be to define a virtual screen that is larger than the physical screen and use the start address registers to move the physical screen window through the virtual screen As long as the base addres
195. without action of any kind by software More complex power management schemes can be devised which leverage intelligent power management software and automatic power management hardware in the same system A state sequencer on the ElanSC400 and ElanSC410 microcontrollers monitors the activity in the system and transitions from mode to mode based on built in timers and the level of activity in the system The actions that occur in each mode are programmable All clock switching is done at a safe time when transitions between modes will not harm system operation Because the system implements hidden refresh the PMU requests a CPU Hold before changing the CPU clock so that the CPU is inactive at the time the clock switches Changes in PMU modes affect the CPU clock primarily Other clocks on the microcontroller may be limited by the speed of the CPU clock but they are not otherwise altered by the mode changes More detailed information on clock control and generation is found in Chapter 6 The ACIN feature can be configured to disable most mode transitions and allow the system to run at maximum performance Suspend mode can still be accessed This feature is useful to get maximum non driver managed performance while connected to an AC wall adapter without completely reprogramming all mode timers etc Each mode has a timer that when it times out signals the PMU to step down to the next lower mode see Figure 5 3 Each timer can be disabled t
196. 0 Screen 3 Row 1 Screen 3 Row 2 E100h Note Base 1C200h Screen 3 Row 240 Unused 38400 bytes 38400 bytes 38400 bytes 15872 bytes Set the start address register to the value shown to display the corresponding screen Graphics Controller 20 25 Figure 20 18 Flat Mapped 4 BPP 640 240 Start Addr Reg Mem Address Frame Buffer 0000h Base 00000h Screen 1 Row 1 Base 00140h Screen 1 Row 2 76800 bytes 12 Screen 1 Row 240 128 Base 12C00h Unused 54272 bytes Note Set the start address register to the value shown to display the corresponding screen A section ofthe CPU memory mapis allocated to the graphics frame buffer by programming a base address for the displayed graphics memory The display controller has visibility into shared memory starting from the programmed base address and extending to the limit of the graphics address counter The graphics address counter is 64 Kbytes for 1 BPP mode and 128 Kbyte for 2 and 4 BPP modes The address offset and pixel location offset for a given set of x and y coordinates origin located in the top left corner of the screen y increases positively in the downward direction x increases positively in the rightward direction may be calculated using the following formulae 1 Bit Per Pixel Mode Byte offset y W 8 x 8 Bit position 7 X 8 2 Bits Per Pixel Mode Byte offset
197. 0 5 Table 20 1 Graphics Controller Register Summary continued Description Register Address Graphics Controller Function Keyword in Register Set Manual PMU Control Register 1 3x4h 3x5h Power up power sequencing delays PMU page 5 40 Index 50h power control enable and software power up and power down PMU Control Register 2 3x4h 3x5h Power up power sequencing delays page 5 41 Index 51h Extended Feature Control 3x4h 3x5h Extended feature control RGBI output CGA page 5 42 Register Index 52h legacy I O trap SMI NMI generation enable inter frame FIFO flush refill delay cursor blink rate HGA register extensions read back page memory enable hidden flush 20 3 BLOCK DIAGRAM Figure 20 1 shows a block diagram of the LCD graphics controller Because the VL bus and the graphics controller share control signals use of the internal graphics controller is traded with having an external VL bus If either 32 bit DRAMs 32 bit ROMs or the VL bus is enabled the internal graphics controller is unavailable 20 4 OPERATION The LCD graphics controller on the lanSC400 microcontroller supports the following modes of operation CGA graphics modes graphics modes CGA MDA text modes 80 64 and 40 column B Flat mapped graphics modes Support flat linear maps of 1 2 or 4 bits per pixel BPP up to resolutions of 480x320 or 640x240 and 640x480 at 1 or 2 BPP 20 4 1 Using the Graphics
198. 0061h function 4 39 12 1 22 Index System Data signals See 015 00 signals System interfaces address buses 4 24 address generation figure 4 24 configuration pin usage 4 16 BNDSON EN pin 4 17 boundary scan configuration table 4 18 CFGO0 and CFG1 configuration table 4 16 CFGO0 and CFG1 pins 4 16 CFG2 configuration table 4 17 CFG2 pin 4 17 CFGS configuration table 4 17 CFGS pin 4 17 pin strap bus buffer options table 4 16 data buses 4 18 16 bit DRAM bus and 16 bit SD bus 4 19 32 bit DRAM bus and 16 bit SD bus 4 19 32 bit DRAM bus 16 bit SD bus and 32 bit ROM bus 4 19 bus configuration A figure 4 21 bus configuration B figure 4 22 bus configuration C figure 4 23 byte lanes table 4 19 byte lanes by access target and type table 4 20 data paths 4 20 device and CPU identification Am486 CPU DX Register at CPU reset 4 4 CPU ID codes table 4 4 device initialization 4 1 multiplexed pin configuration control table A 1 multiplexed pin function options 4 13 multiplexed pins figure 4 14 4 15 overview 4 25 reset internal core states table 4 3 power on reset 4 2 types 4 1 types table 4 2 signal descriptions 4 5 System Management Mode SMM See Am486 CPU System Reset signal See RSTDRV signal T TC signal control 4 25 10 3 description 4 6 usage 10 4 18 10 18 11 19 17 Temporary Low Speed mode See power management unit PMU TERM_LATCH bit
199. 0C833h 22h ax Move both the code fragments les mov mov cld rep les mov mov cld rep di CodeDst1 si CodeSrcl cx CodeLenl movs byte ptr es di byte ptr ds di CodeDst2 si CodeSrc2 cx CodeLen2 movs byte ptr es di byte ptr ds Disable the MMS window mov out Enable SMI and mov out Force si si 9D ax 033h 22h ax force it a few times to prove that it works ax 019Dh Enable SMI at index 22h ax SMI This first force will actually generate 2 SMIs This is an expected in this case side the force smi bit in the primary SMM handler at 38000 SMIs will continue to occur until the force smi bit is cleared as is done in the relocated SMM handler at BOOOOh Note that the 2nd time you run this on because the primary handler at 38000 will not be called Also note that in order to start from scratch in terms of SMI handlers you have to power cycle the system resetdrv button CTL ALT DEL will not or hit the hard rese effect of not clearing ly 1 SMI will occur reset the SMMBASE mov ax 0190h out 22h ax mov ax 0090h Disable force smi out 22h ax Exit back to DOS int 20h Return to DOS lt SMI handler for power on reset default 5 gt This code fragment is the initial SMI handler that gets copied to the default SMI location at 3000 8000 to handle the first SMI Inside the default
200. 1 PPDWE GPIO20 CD A2 GPIO19 2812 GPIO18 PCMB VPP2 lanSC400 Microcontroller GPIO17 PCMB VPP1 GPIO16 GPIO15 PCMA_VPP2 GPIO CS14 PCMA VPP1 GPIO CS13 PCMA VCC GPIO CS12 PDRQO GPIO CS11 GPIO CS10 AEN GPIO CS9 TC GPIO CS8 PIRQO GPIO CS7 PIRQ1 GPIO CS6 IOCHRDY GPIO CS5 IOCS16 GPIO CS4 DBUFOE J GPIO CS3 DBUFRDH J GPIO CS DBUFRDL GPIO CS1 GPIO CS0 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAALAA VVVVVVVVVVVVVVVVVVVVVVVVVVVVV VY Y 17 4 General Purpose Input Output and Programmable Chip Selects Figure 17 2 GPIO CSx Signals Block Diagram Register Settings Read Register Interrupt Controller SMI NMI Power Management Unit Activity Wake up High Speed Low Speed Standby Suspend 00 ENA SMI ENA ACT ENA W U HT Polarity Control External 8042 Chip Select Simple Output Yo Address Decode Memory Address Decode ROM Address Decode General Purpose Input Output and Programmable Chip Selects Register Settings Y ES AMD GPIO CSx 17 5 17 4 17 5 17 5 1 17 6 GPIO SYSTEM IMPLICATIONS Because all of the GPIOs except GPIO CS0 and GPIO_CS1 trade off agai
201. 1 0 49h 7 4 5 4 3 0 1 0 7 4 5 4 3 0 1 0 7 4 5 4 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 o of O O O O O O O O O Color to Grayscales Mapping In 16 color grayscales mode color to grayscales mapping is always handled through the 16x4 grayscale palette giving complete flexibility The palette allows any individual RGBI pixel value to be mapped to any 16 grayscale code The 16 color grayscales mode may be used in any memory setup e g CGA text 1 BPP 2 BPP or 4 BPP The invert bits in the Internal Graphics Control Register B CSC index DEh allow for selective inversion of all grayscales or colors in text and graphics modes For example grayscales may be inverted in graphics modes but not text modes or vice versa In four color grayscales mode mapping is handled differently in text and CGA graphics modes In CGA graphics modes four gray shading may be used in high or low resolution Graphics Controller 20 31 20 4 7 2 3 20 4 8 20 4 8 1 20 4 8 1 1 20 32 modes In 1 BPP modes 0 maps to all pixels off and 1 maps to all pixels on inversion also may be applied In 2 BPP modes mapping is performed per Table 20 10 using the color mapping mode Colors may also be inverted using the Internal Graphics Control Register B as is possible in 16 grayscales mo
202. 113 LCDD 1 2 LCDD 1 1 LCDD 1 0 LCDD 213 LCDD 212 LCDD 2 1 LCDD 2 0 20 36 D1 0 D1 4 D1 8 D1 312 D1 316 D1 1 D1 5 D1 9 01 313 D1 317 D1 2 D1 6 D1 10 D1 314 D1 318 D1 3 D1 7 D1 11 D1 315 D1 319 D1 0 D1 8 D1 304 D1 312 D1 1 D1 305 D1 313 D1 2 D1 10 D1 306 D1 314 D1 3 01 11 01 307 01 315 01 4 01 12 01 308 01 316 01 5 01 13 01 309 01 317 01 6 01 14 01 310 01 318 01 7 01 15 01 311 01 319 Graphics Controller 20 4 9 2 Monochrome Dual Scan Panels Table 20 14 Pixel Chart Row Column Monochrome Dual Scan 320x240 COLUMN ROW d COL 319 Upper screen ROW 1 onal D1 318 D1 319 D2 318 D2 319 Upper screen ROW 120 T D120 318 D120 319 Lower screen ROW 121 M 0121 318 0121 319 0122 318 0122 319 Lower screen ROW 240 T P D240 318 D240 319 Figure 20 28 Data Format for 2x4 Bit Dual Scan Monochrome Panel First horizontal line shown SCK LCDD 1 3 D1 0 D1 4 01 316 LCDD 1 2 01 1 01 5 D1 317 LCDD 1 1 01 2 01 6 T D1 318 LCDD 1 0 D1 3 D1 7 D1 319 LCDD 2 3 D121 0 0121 7 D121 316 LCDD_2 2 D121 1 D121 6 zr D121 317 LCDD 2 1 D121 2 D121 5 mE D121 318 LCDD 2 0 D121 3 D1
203. 14 bytes of static user RAM and can be represented in either binary or BCD The RTC includes the following features Counts seconds minutes and hours of the day Counts days of the week date month and year 12 24 hour clock with AM and PM indication in 12 hour mode 14 clock status and control registers 114 bytes of general purpose RAM Three interrupts are separately software maskable and testable Time of day alarm is programmable to occur from once per second to once per day Periodic interrupts can be continued to occur at rates from 122 us to 500 ms Update ended interrupt provides cycle status Dedicated power pin directly supports lithium backup battery when the rest of the chip is completely powered down RTC only mode Voltage monitor circuit checks the voltage level of the lithium backup battery and sets a bit when the battery is below specification B Internal RTC reset signal performs a reset when power is applied to the RTC core PC AT Support Features Chapter 4 The lanSC400 and ElanSC410 microcontrollers provide all of the support functions found in the original IBM PC AT These include the Port B status and control bits speaker control SCP based CPU core reset and A20 gate control as well as extensions for fast CPU core reset and A20 gate control In addition a CPU shutdown cycle e g as a result of a triple fault will generate a CPU core reset Bidirectional Enhanced Par
204. 16 color grayscale duty cycles table 20 30 16 color grayscale options 20 29 4 color grayscale duty cycles table 20 29 4 color grayscale encoding 20 29 HGA graphics modes 20 13 16 grayscale palette mapping figure 20 15 memory byte format figure 20 15 memory map figure 20 14 memory model 20 14 pixel formats 20 15 initialization 13 1 20 38 operation 20 6 overview 20 1 power management 20 39 emergency power down 20 39 registers 20 2 screen controller registers 20 32 Screen timing generation and cursor control 20 7 signal descriptions 4 11 Graphics Controller Grayscale Mode Register graphics index 43h function 20 5 usage 20 29 Graphics Controller Grayscale Remapping Registers graphics index 44 4Bh function 20 5 usage 20 29 H Configuration Register Port OBBFh function 20 3 usage 20 13 mode See graphics controller 8 Index AMD High Byte Data Buffer Direction Control signal See DBUFRDH signal High Speed Infrared mode See infrared port High Speed mode See power management unit PMU Horizontal Border End Register graphics index 33h function 20 4 usage 20 33 20 35 Horizontal Display End Register graphics index 31h function 20 4 usage 20 33 Horizontal Line Pulse Start Register graphics index 32h function 20 4 Horizontal Total Register graphics index 30h function 20 4 usage 20 32 20 33 20 35 Hyper High Speed Mode Timers Register
205. 2 SET 13 6 SPKD 12 3 START DMA 18 10 TERM LATCH 2 7 B 1 THRE 15 6 18 13 UART ENB 15 7 UIP 13 6 VALUE 17 7 VERTDOUB 20 33 VRT 13 7 WAIT 8 9 WAIT NBRST 8 9 WIDTHXx 9 5 BL2 BLO signals control 5 4 5 6 description 4 8 usage 5 21 5 24 5 26 5 31 20 39 BNDSON EN signal description 4 6 usage 4 17 21 1 BNDSCN_TCK signal control 4 17 description 4 12 usage 21 1 21 2 21 4 21 8 2 BNDSON TDI signal control 4 17 description 4 12 usage 21 1 21 2 21 4 21 6 BNDSCN_TDO signal control 4 17 description 4 12 usage 21 1 21 2 21 4 21 6 BNDSCN_TMS signal control 4 17 description 4 12 usage 21 1 21 5 21 8 Boundary Scan Enable signal See BNDSCN_EN signal Bus Address Latch Enable signal See BALE signal BUSY signal control 14 2 14 9 description 4 9 BVD1 A STSCHG signal description 4 10 BVD1 B STSCHG B signal description 4 10 usage 19 18 BVD2 A SPKR signal description 4 10 usage 10 8 19 17 19 18 BVD2 B SPKR B signal description 4 10 usage 10 8 19 17 19 18 Byte High Enable signal See SBHE signal C Cache and VL Miscellaneous Register CSC index 14h function 3 1 7 1 usage 3 3 4 2 4 35 7 11 9 2 Card Data Direction signal See ICDIR signal Card Enables High Byte signals See MCEH A MCEH B signals Card Enables Low Byte signals See MCEL A MCEL B signals Card Reset signals See RST A
206. 2 Power Management in the 17 9 Infrared Port Register Summary 18 2 Power Management in the Infrared Port 18 13 PC Card Controller Register Summary 19 2 Dual Mode Signal Functions 19 6 PC Card Supported Cycle 19 11 PC Card Attribute Memory Read Function 19 11 PC Card Attribute Memory Write 19 12 PC Card Common Memory Read Function 19 12 Card Common Memory Write Function 19 12 PC Card Read 19 12 PC Card Write 19 12 PC Read Function 19 12 PC DMA Write Function 19 13 Prescalar Select Field 19 14 Memory Window Socket Mapping 19 15 Memory Window Redirection Effects 19 16 PC Card Socket B Memory Window Resources Used for MMS 19 16 VPP Control Signal Definition 19 20 VCC Control Signal Definition 1
207. 21 4 IT D121 319 Graphics Controller 20 37 20 4 9 3 Color STN Single Scan Panels Table 20 15 Pixel Chart Row Column Color STN Single Scan 320x240 COLUMN T COL 319 B1 1 B2 1 ROW 240 e R240 319 G240 319 B240 319 Figure 20 29 Data Format for 8 Bit Single Scan Color STN Panel First horizontal line shown SCK LCDD_1 3 R1 0 B12 215 D gt R1 312 B1314 G1 317 LCDD 1 2 G1 0 1 3 815 l G1 312 81 315 1 317 LCDD 1 1 1 0 816 1 312 G1 315 R1 318 LCDD_1 0 B1 3 6 R1 313 B1 315 G1 318 LCDD 2 3 1 1 814 1 6 Gf313 81 316 B1 318 LCDD 212 B1 14 81313 G1 316 R1 319 LCDD 2 1 R1 2 814 617 R1 314 B1 316 G1 319 LCDD 2 0 G1 2 Ri 5 817 61314 R1 317 B1 319 20 5 INITIALIZATION The graphics controller is disabled at power on reset and must be configured by software before being enabled At power on reset LVDD and LVEE are both deasserted The SCK LC FRM M and all LCDD signals are held Low When bringing up the display from reset software should use the following sequence 1 Enable the graphics controller by setting the Internal Graphics Control Register A CSC index DDh 2 and disable the CSC indexed register lockout in the Inte
208. 22 Output 166 SA23 Output 165 SA24 Output 164 SA25 Output 163 20 Input Test and Debugging 21 11 Table 21 2 Main Data Scan Path continued JTAG Cell m memme OO 21 12 162 GPIO20 Output 161 N A Control cell 160 SCK Output 159 LC Output 158 M Output 157 FRM Output 156 LCDD7 Output 155 LCDD6 Input 154 LCDD6 Output 153 LCDD5 Output 152 LCDD4 Input 151 LCDD4 Output 150 LCDD3 Output 149 LCDD2 Output 148 LCDD1 Output 147 LCDDO Output 146 LVEE Input 145 LVEE Output 144 LVDD Output 143 GPIO CS3 Input 142 GPIO CS3 Output 141 GPIO CS2 Input 140 GPIO CS2 Output 139 KBD ROWO Input 138 KBD ROWO Output 137 KBD ROW 1 Input 136 KBD ROW1 Output 135 KBD ROW2 Input 134 KBD ROW2 Output 133 KBD ROWS Input 132 KBD ROW3 Output 131 KBD_ROW4 Input 130 KBD_ROW4 Output 129 KBD ROW5 Input 128 KBD ROW5 Output 127 KBD ROW6 Input 126 KBD ROW6 Output 125 N A Control cell 124 RAST Output 123 RASO Output 122 CASHT Output Test and Debugging Table 21 2 Main Data Scan Path continued JTAG Cell m Peaname OO 121 CASHO Output 120 CASLT Output 119 CASLO Output 118 MA11 Output 117 MA10 Output 116 Out
209. 23h Index BOh GPIO XMI mapping to GPIO CS pins SMI NMI selection page 3 130 Suspend Control Suspend Mode Pin State Register A 22h 23h Index E3h Power control in Suspend mode for PC Card sockets A and B VL bus ISA bus DRAM and ROM interfaces page 3 184 Suspend Mode Pin State Register B 22h 23h Index E4h Power control in Suspend mode for DBUFOE R32BFOE page 3 185 Suspend Mode Pin State Override Register 22h 23h Index E5h Suspend mode override for PC Card sockets A and B DBUFOE R32FOE ISA bus and ROM interface pin termination latch command Power Management page 3 186 5 7 AMD 5 3 BLOCK DIAGRAM Figure 5 1 shows a block diagram of the power management unit Figure 5 1 Power Management Unit Block Diagram Event Generating Signals Primary Activities gt Secondary Activities Wake ups p gt Registers Internal Bus Out T Mis NMIs gt vise state mac Emergency LCD Shutdown Battery Condition Pins Battery Status Advise state mach Suspend Resume Logic Suspend Resume Key Advise state mach p Internal Bus In 5 8 Power Management 5 4 AMD OPERATION The PMU on the lanSC400 and lanSC410 microcontrollers is designed to operate in either fully automatic mode software driven mode or various combinations of the two Fully aut
210. 3 3 3 Matrix Keyboard Support with PC AT Compatibility 16 11 16 3 4 XT 16 12 16 3 4 1 2 16 12 16 3 4 2 Enabling the XT Keyboard Interface 16 13 16 3 4 3 Controlling the XT Keyboard Interface 16 13 16 3 4 4 TINING eee 16 13 16 4 Initialization ee sen omae a a 16 13 16 5 Power 16 13 CHAPTER 17 GENERAL PURPOSE INPUT OUTPUT AND PROGRAMMABLE CHIP SELECTS 17 1 17 1 OVerVIOW sic 17 1 1731 1 External PINS iei diem cem CR non ie eee ORE GRE 17 1 17 1 2 Internal Chip Select Logic 17 1 17 2 Registers esses ER ER 17 2 17 3 Block Diagram eh 17 4 17 4 GPIO System 5 17 6 1 5 Initlalizationz zz uL oct aud ace ee E ERR ERR ERR ERES 17 6 17 5 1 GPIO Pins and Simple 17 6 17 5 2 GPIO Pins and Simple Output 17 7 17 5 8 GPIO CS Pins and Automatic Output 17 7 17 5 3 1 Automatic PMU Information Output 17 7 17 5 3 2 Automatic Chip Select Outputs 17 7 17 6 GPIO CS Signals as PMU Activities and SMI NMI Generation 17 8 17 6 1
211. 3 45 Index 39h control signals for Socket A and B enable Pin Mux Register C 22h 23h Socket A second card detect enable page 3 46 Index 3Ah Wake Up Source Enable 22h 23h Wake up source enable ring indicate Sockets page 3 62 Register D Index 55h A and B interrupt requests card detects and status change Wake Up Source Status 22h 23h Wake up source status ring indicate Sockets page 3 66 Register D Index 59h A and B interrupt requests card detects and status change Activity Source Enable 22h 23h Activity source enable CPU memory and I O page 3 74 Register D Index 65h access to PC Card Sockets A and B ring indicate and PC Card interrupt 19 2 PC Card Controller AMD Table 19 1 Card Controller Register Summary continued Description in Register Set Manual Address PC Card Controller Function Register Activity Source Status Register D 22h 23h Activity source status CPU memory and I O page 3 78 Index 69h access to PC Card Sockets A and B ring indicate and PC Card interrupt Activity Classification Register D 22h 23h Primary or secondary activity classification page 3 82 Index 6Dh CPU Memory and access to PC Sockets A and B ring indicate and PC Card interrupt PC Card and Keyboard SMI NMI 22h 23h SMI NMI enable PC Card interrupt ring page 3 95 Enable Register Index 91h indicate and card detects for Sockets A and B PC Card and Ke
212. 3 7 Implementation with No Backup Battery 5 13 8 Parallel Port Block 14 3 Parallel Port Data Control in PC AT Compatible Mode 14 5 Parallel Port Data Control in Bidirectional and EPP Modes 14 6 EPP Write 14 8 EPP Read ee hee we ee ee ee 14 9 Serial Port Block Diagram 15 4 WART Fraime esce i aaa Rak AR RR ae KORR aca 15 6 Matrix Keyboard Controller Block Diagram 16 6 N Key Rollover Example 1 16 7 N Key Rollover Example 2 16 7 General Purpose Input Output Block 17 4 Table of Contents Figure 17 2 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 19 1 Figure 19 2 Figure 19 3 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure 20 5 Figure 20 6 Figure 20 7 Figure 20 8 Figure 20 9 Figure 20 10 Figure 20 11 Figure 20 12 Figure 20 13 Figure 20 14 Figure 20 15 Figure 20 16 Figure 20 17 Figure 20 18 Figure 20 19 Figure 20 20 Figure 20 21 Figure 20 22 Figure 20 23 Figure 20 24 Figure 20 25 Figure 20 26 Figure 20 27 Figure 20 28 Figure 20 29 Figure 21 1 Figure 21 2 Figure 21 3 GPIO CSx Signals B
213. 30 GPIO18 Output 229 GPIO17 Input 228 GPIO17 Output 227 N A Control cell Bus control 226 GPIO16 Input 225 GPIO16 Output 224 GPIO15 Input 223 GPIO15 Output 222 GPIO_CS14 Input 221 GPIO_CS14 Output 220 GPIO CS13 Input 219 GPIO CS13 Output 218 GPIO CS12 Input 217 GPIO CS12 Output 216 GPIO CS11 Input 215 GPIO CS11 Output 214 GPIO CS10 Input 213 GPIO CS10 Output 212 GPIO CS9 Input 211 GPIO CS9 Output 210 GPIO CS8 Input 209 GPIO CS8 Output 208 GPIO CS7 Input 207 GPIO CS7 Output 206 GPIO CS6 Input 205 GPIO CS6 Output Test and Debugging Table 21 2 Main Data Scan Path continued JTAG Cell m Peaname OO 204 GPIO CS5 Input 203 GPIO CS5 Output 202 GPIO CS1 Input 201 GPIO CS1 Output 200 GPIO CSO Input 199 GPIO CSO Output 198 MEMR Output 197 MEMW Output 196 ROMWR Output 195 ROMRD Output 194 ROMCSO Output 193 ROMCST Output 192 TOR Output 191 TOW Output 190 N A Control cell Control for address bus 189 188 SA1 Output 187 SA2 Output 186 185 SA4 Output 184 SA5 Output 183 SA6 Output 182 SA7 Output 181 SA8 Output 180 SA9 Output 179 SA10 Output 178 SA11 Output 177 SA12 Output 176 SA13 Output 175 SA14 Output 174 SA15 Output 173 SA16 Output 172 SA17 Output 171 SA18 Output 170 SA19 Output 169 SA20 Output 168 SA21 Output 167 SA
214. 3F8h This will effectively send a 1 6 us light pulse with no other pulses because Slow Speed Infrared is not bit stuffed Note that it takes approximately 108 ns to complete the switch from High Speed Infrared mode to Slow Speed Infrared mode after which time the FFh data may be written After writing the SIP pulse data the software will need to wait about 8 us one byte time after the UART s THRE status bit goes active before switching back to High Speed Infrared mode to ensure that the SIP gets sent 18 5 INITIALIZATION The infrared port is disabled at power on reset and must be configured by software before being enabled In Slow Speed Infrared mode the port is essentially operating in standard UART mode For Slow Speed Infrared mode set up all of the registers that are required to set up the UART Slow Speed Infrared operation requires that the UART be set up for 8 data bits no parity and 1 stop bit via the UART Line Control Register at Port O3FBh 02FBh Write SELMODE to 0 CSC index EAh 1 to select Slow Speed Infrared mode and set SELDEVICE to 1 CSC index EAH 0 to enable the infrared interface Enable the UART by setting the UART_ENB bit in the Parallel Serial Port Configuration Register CSC index D1h 0 Select the UART infrared port base address via CSC index D1h 1 and IRQ routing via the Interrupt Configuration Register E CSC index D8h 6 5 For High Speed Infrared mode set the FIFOEN bit to enable the FI
215. 3h Wake up source enable RIN and SIN pins page 3 59 Register A Index 52h Wake Up Source Status 22h 23h Wake up source status RIN and SIN pins page 3 63 Register A Index 56h Activity Source Enable Register A 22h 23h Activity source enable CPU access to UART page 3 71 Index 62h at COM1 or COM2 Activity Source Enable 22h 23h Activity source enable RIN and SIN pins page 3 73 Register C Index 64h 15 2 Serial Port UART Table 15 1 Register Activity Source Status Register A Address 22h 23h Index 66h Serial Port Register Summary continued UART Function Keyword Activity source status CPU access to UART at COM1 or COM2 AMD Description in Register Set Manual page 3 75 Activity Source Status Register C 22h 23h Index 68h Activity source status RIN and SIN pins page 3 77 Activity Classification Register A 22h 23h Index 6Ah Primary or secondary activity classification CPU access to UART at COM1 or COM2 page 3 79 Activity Classification Register C 22h 23h Index 6Ch Primary or secondary activity classification RIN and SIN pins page 3 81 CLK IO Pin Output Clock Select Register 22h 23h Index 83h UART clock output on IO pin page 3 91 Miscellaneous SMI NMI Enable Register 22h 23h Index 90h SMI NMI enable RIN and SIN pins page 3 94 Miscellaneous SMI NMI Status Register 22h 23h Index 94h SMI NMI status RIN and SIN pins page 3 9
216. 4 4Bh For example to remap codes 0 through 7 to code 0 and RGBI codes 8 through 15 to code 15 the first eight nibbles would be programmed to 0 and the second eight nibbles would be programmed to OFh The default mapped duty cycles are given in Table 20 11 Graphics Controller 20 29 Table 20 11 16 Color Grayscale Duty Cycles Active 20 4 7 2 1 20 30 oy BR c i AR Grayscale Remapping The grayscale remapping feature allows system software to tune the look of the displayed graphics without the need to rewrite the application software that is writing bit patterns into the graphics buffer This is done by allowing each bit pattern that represents a pixel in the graphics buffer to be arbitrarily mapped to one of the available grayscales Remapping is available for 1 2 or 4 BPP mode The optimal mapping can vary based on the LCD manufacturer This tuning is done via the eight color mapping registers containing 16 individual bit fields located at graphics index 44h 4Bh and only takes effect when graphics index 43h 0 1b The graphics controller uses a pixel modulation scheme to allow either 4 or 16 grayscales to be present on the display at any one time selected via graphics index 43h 1 Grayscales are achieved by controlling the average time that a pixel is turned on over a
217. 40 480x128 320x200 320x240 Other resolutions may be supported Supports single scan color SuperTwisted Nematic STN panels with 8 bit interface same resolutions as monochrome mode Internal local bus interface provides high performance Logical screen may be larger than physical window Supports panning and scrolling Supports horizontal dot doubling and vertical line doubling The following MDA CGA compatible text mode features are supported 40 64 or 80 columns with characters 16 10 or 8 pixels wide Variable height characters up to 32 lines Variable width characters 8 10 or 16 pixels MDA Monochrome or CGA 4 gray shades 16 gray shades or 16 colors B 16 Kbyte downloadable font area relocatable on 16 Kbyte boundaries within lower 16 Mbytes of system DRAM may be write protected 16 Kbyte graphics frame buffer MMS Window relocatable on either 16 Kbyte boundaries within lower 16 Mbytes of system DRAM CGA compatible mode or 32 Kbyte boundaries when the frame buffer is larger than 16 Kbytes flat mapped mode Graphics Controller 20 1 20 2 Table 20 1 Register The following graphics mode features are supported 640x200 1 bit per pixel CGA compatible graphics buffer memory 320x200 2 bits per pixel CGA compatible graphics buffer memory 640x480 2 bits per pixel flat memory map lower resolutions supported 640x480 1 bit per pixel flat me
218. 6 Register Index 21h shadowing ROM1 space access redirection to PC Card Socket A Linear ROMCSO Attributes 22h 23h Write protection and caching for regions page 3 28 Register Index 22h OOFFFFF 00C0000h ROM Flash Interface 8 1 Table 8 1 ROM Flash Interface Register Summary continued Description in Register Set Manual Register Address ROM Flash Interface Function Keyword ROMCSO Configuration Register A ROMCSO Configuration Register B 22h 23h Index 23h 22h 23h Index 24h Access speed burst mode support and early chip select for ROMO Fast Speed ROM mode wait states for burst and non burst cycles for ROMO page 3 29 page 3 31 ROMCST Configuration Register A 22h 23h Index 25h Access speed burst mode support and early chip select for ROM1 page 3 32 ROMCST Configuration Register B 22h 23h Index 26h Fast Speed ROM mode wait states for burst and non burst cycles for ROM1 page 3 34 ROMCS2 Configuration Register A 22h 23h Index 27h Access speed burst mode support and early chip select for ROM2 page 3 35 ROMCS2 Configuration Register B 22h 23h Index 28h Fast Speed ROM mode wait states for burst and non burst cycles for ROM2 page 3 37 Activity Source Enable Register A 22h 23h Index 62h Activity source enable CPU access to ROMCSO0 and ROMCS2 ROMCS1 page 3 71 Activity Source Status Register A 22h 23h I
219. 6 Grayscale Palette Mapping 1 Pixel 4 BPP Flat Mapped Graphics Mode 20 28 Graphics Controller Red Green Blue Intensity PEL PEL PEL PEL Bit 3 Bit 2 Bit 1 Bit 0 AMD 20 4 7 Grayscale Generation 20 4 7 1 Four Color Grayscale Encoding Selecting grayscaling Option 1 via the Graphics Controller Grayscale Mode Register graphics index 43h 1 enables the four color grayscaling options In four color mode frame rate shading creates four different levels of gray by varying the duty cycle of the on time for individual pixels as seen over successive frames Table 20 10 lists the duty cycles available in the four grayscale modes Table 20 10 Four Color Grayscale Duty Cycles Map Select 1 Duty Cycles Monochrome Mapping Mode 0 33 1 3 0 0 667 2 3 1 0 667 2 3 1 0 667 2 3 1 0 667 2 3 1 0 667 2 3 1 0 667 2 3 1 0 667 2 3 1 Map Map Select 2 Select 2 Duty Cycles Codes Color Mapping Mode Select 1 Codes WO m Qo MP WO MP WI PM W CO WO MP AH AH 20 4 7 2 16 Color Grayscale Encoding The lanSC400 microcontroller s grayscaling logic uses frame rate shading and flicker reduction techniques to generate 16 gray shades All 16 shades may be individually remapped by programming the Graphics Controller Grayscale Remapping registers graphics index 4
220. 8 or 16 bit devices supporting ISA compatible I O memory DMA cycles The following features are supported 8 2944 MHz maximum bus clock speed Programmable DMA clock speed to 16 MHz 8 bit and 16 bit ISA and memory cycles ISA memory is non cacheable Bi Direct connection to 3 or 5 volt peripherals Eight programmable IRQ PIRQ7 PIRQO input pins are available These interrupts may be routed via software to any available PC AT compatible interrupt channel Interrupts on the ElanSC400 and ElanSC410 microcontrollers are described in Chapter 11 Two programmable DMA channels are available for external DMA peripherals These DMA channels may be routed via software to any available ISA DMA channel DMA on the ElanSC400 and ElanSC410 microcontrollers is described in Chapter 10 Note External ISA bus mastering is not supported on the lanSC400 and lanSC410 microcontrollers 4 7 2 Registers A summary listing of the chip setup and control CSC registers used to control the ISA interface is shown in Table 4 12 Complete register descriptions can be found in the Elan SC400 Microcontroller Register Set Reference Manual order 21032 Table 4 12 ISA Interface Register Summary Description Register Address ISA Interface Function in Register Set Manual Linear ROMO Shadow Register 22h 23h 00F0000 00FFFFFh ROMO decode disable page 3 26 Index 21h accesses directed to the ISA bus Pin Mux Register A 22h 23h ISA signal enable P
221. 8000 Memory Management 7 7 7 6 7 6 1 OOAFFFFh which normally is directed to ISA space This allows SMM RAM to be invisible to normal system operation TRANSLATED MEMORY MANAGEMENT When the microcontroller performs translated memory management it translates addresses in addition to selecting the correct address space for each access A window in the CPU address space is mapped to a particular target location in the target address space Note that itis the programmer s responsibility to understand all of the mapping mechanisms and to avoid using translated memory management in a manner which attempts to map more than one target location to the same CPU address space This will result in undefined behavior which could possibly damage hardware e g by enabling multiple drivers onto the same bus The lanSC400 and ElanSC410 microcontrollers have several distinct types of translated memory management MMS Windows A and B MMS Windows C F Graphics Frame Buffer MMS Window lanSC400 microcontroller only 82365 compatible PC Card access ElanSC400 microcontroller only A discussion of each of these translated memory management methods follows MMS Windows A and B The simplest translated memory management is provided by MMS windows A and B MMS Window A when enabled occupies the 32 Kbytes of CPU address space from 00B0000 00B7FFFh taking precedence over ISA accesses in that region It can target any
222. 812 The batteries so low they cannot operate the system Force the system into Critical Suspend mode and do not allow a resume until there is AC power or the batteries are changed ACIN The ACIN signal is used to indicate that the system is connected to a permanent source of power i e an AC wall adapter and that power management is not required Suspend mode is still accessible The ACIN mode flow is diagramed in Figure 5 5 There is a register bit in the Battery AC Pin Configuration Register CSC index 70h 5 to perform a software ACIN which when set has the same affect as asserting the ACIN pin This is useful for software to emulate the effect the hardware ACIN line has on the function of the PMU There is no functional difference between the ACIN pin being active and the ACIN software bit being set Software can determine which is active by reading the Battery AC Pin State Register CSC index 72h 5 ACIN is similar to a primary activity Both can take the PMU back up to Hyper or High Speed mode but the ACIN will keep it there by masking the timer time outs If the PMU Force Mode Register is programmed while ACIN is active and programmed to disable PMU functions the PMU will change mode but will immediately switch back to High Speed or Hyper Speed mode because of ACIN Activities wake ups and SMI NMIS still work when ACIN is active also SMI NMIS are still accessible and the system will still wake up from Suspend whe
223. 9 SMI NMI Select Register 22h 23h Index 98h Select SMI or NMI RIN and SIN pins page 3 104 Access SMI Enable Register A 22h 23h Index 99h SMI enable for access to UART or COM2 page 3 105 Access SMI Status Register 22h 23h Index 9Bh SMI status for I O access to UART COM or COM2 page 3 107 Parallel Serial Port Configuration Register 22h 23h Index D1h 1 or COM base address configuration UART enable page 3 167 UART FIFO Control Shadow Register 22h 23h Index D3h Shadow FIFO control 16550 compatible mode enable FIFO buffer clear trigger for received data available interrupt pending page 3 169 Interrupt Configuration Register E 22h 23h Index D8h IRQ mapping UART IRQ3 or IRQ4 page 3 174 Suspend Pin State Register A 22h 23h Index E3h Suspend state of serial port or infrared interface page 3 184 IrDA Control Register 15 3 22h 23h Index EAh BLOCK DIAGRAM UART or infrared mode select page 3 188 A block diagram of the serial port on the ElanSC400 and lanSC410 microcontrollers is shown in Figure 15 1 Both the serial interface pins and the infrared interface pins are available on the lanSC400 and lanSC410 microcontrollers at all times although only one interface is available at any given time because they both share the same internal UART This means that both a serial device an
224. 9 21 Shared Card 5 19 21 Power Management in the PC Card 19 24 Graphics Controller Register 5 20 2 Color Mapping in CGA Low Resolution 20 13 Color Mapping in CGA High Resolution 20 13 Text Mode Memory Display Data 80 25 20 16 CGA Attribute Byte Foreground 20 17 CGA Attribute Byte Background Color 20 18 Cursor Blinking 2 4 26 ene 20 20 Font Address 0 0 cee eee RII 20 21 Example Memory lt 20 24 Four Color Grayscale Duty 20 29 16 Color Grayscale Duty Cycles 20 30 Grayscale 20 31 Table of Contents xix Table 20 13 Table 20 14 Table 20 15 Table 20 16 Table 21 1 Table 21 2 Table A 1 Table B 1 Pixel Chart Row Column Monochrome Single Scan 320x240 20 36 Pixel Chart Row Column Monochrome Dual Scan 320x240 20 37 Pixel Chart Row Column Color STN Single Scan 320x240 20 38 Power Management in the LCD Graphics 20 40 Test Acces
225. A graphics control video blanking color burst select text or graphics CGA column select page 2 137 CGA Status Register Vertical retrace status simulated vertical sync display memory access status simulated horizontal sync light pen switch light pen status page 2 139 CGA Color Select Register 9 Alternate palette alternate background intense red green or blue border background page 2 138 Chip Setup and Control CSC Index Registers DRAM Control Register 22h 23h Index 04h CAS pulse width for graphics controller reads page 3 14 Cache and VL Miscellaneous Register 22h 23h Index 14h Write through caching of graphics memory page 3 23 PMU Force Mode Register 22h 23h Index 40h Standby mode graphics enable page 3 51 Activity Source Enable Register A 22h 23h Index 62h Activity source enable CPU access to internal graphics and internal graphics memory page 3 71 Activity Source Status Register A 22h 23h Index 66h Activity source status CPU access to internal graphics and internal graphics memory page 3 75 Activity Classification Register A 22h 23h Index Primary or secondary activity classification CPU access to internal graphics I O and internal graphics memory page 3 79 CLK IO Pin Output Clock Select Register 22h 23h Index 83h Route internal graphics dot clock to external IO pin
226. A20 to always be 0 Since the Am486 CPU defaults to 8088 compatible mode the programmer must set the gate to allow A20 propagation for most applications Note Most operating systems such as MS DOS contain code to do this In the case of MS DOS HIMEM SYS contains the code and has an API to allow program control of A20 A20 will be automatically set to propagate if HIMEM SYS is loaded DOSZHIGH UMB is added to CONFIG SYS For information about direct control over the A20 gate see the descriptions for the microcontroller s direct mapped registers at ports 0092h and OOEEh Top of Memory CPU Execution At reset the processor is in Real mode which normally can address only a megabyte but the first instruction is fetched from address FFFFFFFOh at the top of memory The initial value of CS the code segment is 000F000h and the initial value of the instruction pointer IP is OOOFFFOh however the internal CPU base address associated with the code segment is FFFF0000h rather than OOFOOOON The first far jump will cause the CS base address to be setto 16 times the segment of the jump target so all PC AT compatible BIOS implementations have a far jump to a target in segment 000F000h as the first instruction executed This may become an issue if the boot ROM is larger than 1 Mbyte In many implementations a small boot ROM 128 Kbyte or 256 Kbyte will be used and will alias to all addresses decoded as boot ROM addresses In this case the
227. AG Test Features 1 13 1 2 15 System 1 13 1 2 15 1 Data Buses 1 13 1 2 15 2 Address Buses 1 14 1 2 15 3 Memory 1 14 1 2 15 4 ISA Bus Interface For External ISA Peripherals 1 15 1 2 15 5 VESA Local VL Bus 1 15 1 3 System Considerations 1 16 Table of Contents v vi CHAPTER 2 CHAPTER 3 CHAPTER 4 CONFIGURATION BASICS 2 1 2 1 OVerVIeW isum eR CORRER RO eae ae ead as 2 1 2 2 Configuration 2 1 2 3 Configuration Register Spaces And Indexed Addressing 2 2 2 3 1 Direct Mapped Registers 2 2 2 3 2 Indirect Mapped Registers Indexed Registers 2 3 2 3 8 Chip Setup and Control CSC Indexed Registers 2 6 2 4 Feature 2 7 2 4 1 Pin Multiplexing sellee ee 2 7 2 4 2 Pin Termination 2 7 Am486 CPU 3 1 31 Overview eee een has 3 1 32 abe eed aed ee EA a dew d 3 1 3 3 CPU features Specific to the ElanSC400 and ElanSC410 Microcontrollers sss 2 3 2 3 4 Cache Memory
228. ALLEL PORT 14 1 Overview 14 2 Registers bid eek DR er 14 2 1 Direct Mapped Registers 14 2 2 Chip Setup and Control Registers 14 3 Block Diagram RR hs 14 4 Pin Definitions by Mode 14 5 s ouk tek epa he RA eR Rx ea aun HR 14 5 1 Minimal System Design 14 5 1 1 PC AT Compatible Mode 14 5 1 2 Bidirectional and EPP Modes 14 5 2 Operating Modes 14 5 2 1 PC AT Compatible Mode 14 5 2 2 Bidirectional Mode 14 5 2 3 Enhanced Parallel Port EPP Mode 14 6 Initialization oeo aaeeea 14 7 Power SERIAL PORT UART 15 1 OVEINIEW wh Md ee 15 2 Heglsters chee Die teste doe eke ees 15 2 1 Direct Mapped Registers 15 2 2 Chip Setup and Control CSC Index Registers 15 3 Block Diagram sarissa ranama nt E RIKKA ee 15 4 Operation 15 4 1 Baud Rate Generation 15 4 2 UART Frame 15 4 3 Operating Modes 15 4 3 1 16450 Mode No FIFOs 15 4 3 2 16550
229. AS Strobe Assertion Bank Selection 9 5 9 4 1 2 CAS Strobe Assertion Byte Lane Selection 9 5 9 4 2 Timing and Control Signal Generation 9 12 9 4 2 1 Page Mode and RAS 5 9 12 9 4 2 2 MWE 9 12 9 4 2 3 CAS Pulse 9 12 9 4 2 4 CAS Precharge 9 12 9425 Refresh 9 12 9 5 e A 9 13 9 5 1 Boot Process Overview 9 13 9 5 2 Dynamic DRAM Detection Algorithm 9 14 9 6 Power 9 15 Table of Contents ix CHAPTER 10 CONTROLLER 11 12 10 1 Overview hen 10 2 Registers needs ek ke onset Rok koe dU Dor du Dar d 10 2 1 Direct Mapped Registers 10 2 2 Chip Configuration and Control CSC Registers 10 2 2 1 Extended Page Registers 10 3 Block Diagram 0 10 4 Operation 10 4 1 Addressing DMA Channels 10 4 2 Transfers 2 10 4 2 1 Transfer 10 4 2 2
230. BDNSCN the BNDSCN EN pin Low MCEH A BNDSCN TMS the BNDSCN EN pin Low MCEL B GPIO31 STRB Write CSC index 39h 1 0 to 01 MCEH B GPIO30 AFDT Write CSC index 39h 1 0 to 01 PCMA_VCC GPIO_CS13 Set CSC index 39h 5 PCMA VPP1 GPIO_CS14 Set CSC index 39h 5 PCMA_VPP2 GPIO15 Set CSC index 9 5 PCMB_VCC GPIO16 Set CSC index 39h 6 PCMB_VPP1 GPIO17 Set CSC index 39h 6 PCMB VPP2 GPIO18 Set CSC index 39h 6 REG A BNDSCN the BNDSCN EN pin Low A BNDSOCN TDI Pull the BNDSCN EN pin Low REG B 1028 INIT Write CSC index 39h 1 0 to 01 RST B GPIO29 SLCTIN Write CSC index 39h 1 0 to 01 RDY B GPIO26 PE Write CSC index 39h 1 0 to 01 WP B GPIO23 SLCT Write CSC index 39h 1 0 to 01 Multiplexed Pin Configuration Control AMD Table A 1 Multiplexed Pin Configuration Control continued Signal You Signals You How to Configure the Signal You Want on the Pin LCD Graphics Controller ElanSC400 Microcontroller Only FRM VL LCLK Enable the graphics controller by setting CSC index LC VL DDh 2 LCDDO VL RST LCDD1 VL ADS LCDD2 VL W R LCDD3 VL M IO LCDD4 VL LRDY LCDD5 VL D C LCDD6 VL LDEV LCDD7 VL BE3 VL BRDY VL BLAST VL BE2 SCK VL BEO Boundary Scan Interface BDNSCN Pull the BNDSCN EN pin High BNDSCN TDI RST A Pull the BNDSCN EN pin High BNDSCN T
231. C index FFh can be used to identify which silicon revision software is running on A user modifiable bit in the EFLAGS Register indicates support of the CPUID instruction This bit bit 21 is referred to as the EFLAGS ID bit and is reset to 0 at CPU reset RESET or SRESET for compatibility with existing processor designs Using the CPUID instruction the microcontroller can be done with the following steps as shown in the code sample in Section 3 6 3 Ensure that the CPU is capable of executing an invalid opcode exception if it does not recognize the CPUID instruction and install a trap at the exception vector Execute the CPUID instruction twice once to get the manufacturer name and once to get the device description Make sure the manufacturer is AuthenticAMD Make sure the device is described as a 486 SX1 with a write back cache The Am486 CPU core in the lanSC400 and lanSC410 microcontrollers is the first CPU AMD has made with a write back cache and no FPU so these tests should be sufficient to uniquely identify the family For consistency the results reported by CPUID are constant Even though cache accesses can be set to write back or write through and the CPU speed can be clock doubled or clock tripled changing these parameters through software does not alter the CPUID results CPUID Timing CPUID execution timing depends on the selected EAX parameter values as shown Table 3 5 Am486
232. C index EEh and EFh along with some status information and stored to DRAM for later analysis This must be done in a time critical fashion because the received byte count read from EEh and EFh must be reset atthe start of each received frame Failure to handle the task in a time critical fashion will result in data overruns in the receive FIFO The status bits provided are to be used for a status information overrun indication If the software fails to read the byte count out before two byte counts are written the third byte count written will result in losing byte count information This byte count information is necessary for receiving back to back frames because it allows the CPU to ascertain frame boundaries for back to back frames within the DMA buffer Note that the CPU must be running at 33 MHz or faster while receiving back to back frames to avoid getting byte count overruns The process for receiving back to back frames follows Register details can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 and amendments Set up for receive mode Read the byte count latches to clear internal the overrun internal pre bit Write the 11 bit byte count to 111 1111 1111b Start receiving data Receive first byte Byte transferred to FIFO Count decrements Rest of frame data transferred over count decremented once per received byte 2
233. C update E Use the update ended interrupt If enabled this interrupt occurs after every update cycle This means that over 999 ms are available to read the time and date registers Before leaving the interrupt service routine clear the IRQF bit in Register C Use the Update in Progress bit UIP in Register A The UIP bit changes once second The update cycle begins 244 us after the UIP bit goes High This means that if a 15 read on the UIP bit there are at least 244 us before the time or calendar data will be changed If a 1 is read in the UIP bit the time or calendar data may not be valid Note that the time allocated to read time or calendar data should not exceed 244 us Use a periodic interrupt to determine if an update cycle is occurring Note that to ensure correct data the time should not be set on the last day of the month within two seconds of the rollover to the next day Backup Battery Considerations The behavior of the RTC when the primary power supply is turned off depends on whether or not an external backup battery is included in the system design Real Time Clock 13 4 5 1 Using an External Backup Battery Figure 13 3 shows a specific system implementation with the ElanSC400 microcontroller using an external backup battery to keep the 32 KHz oscillator RTC and RAM powered on when the primary system power supply is turned off i e the AVCC source is removed In the circuit shown bo
234. CPU Table 3 5 3 6 2 CPUID Instruction Description OP EAX CPU Core Description Code Input Value Clocks 2 CPUID 0 41 AMD ASCII String 1 14 CPU ID Register gt 1 9 Null Registers CPUID Operation The CPUID instruction requires the user to pass an input parameter to the CPU in the EAX Register The CPU response is returned to the user in registers EAX EBX ECX and EDX E When the parameter passed in EAX is 0 the register values returned upon instruction execution are EAX 31 0 00000001h EBX 31 0 68747541h ECX 31 0 444D4163h EDX 31 0 69746E65h The values in EBX ECX and EDX contain an ASCII string that spells out AuthenticAMD When the parameter passed in EAX is 1 the register values returned EAX 3 0 Stepping ID EAX 7 4 Model AH enhanced Am486 SX1 write back mode 11 8 Family 4H Am486 CPU 00005 1 RESERVED 000000006 000000006 000000006 The 0 in bit 0 of EDX 31 0 indicates that the FPU is not present EAX EAX EBX ECX EDX WWW WE CX qe Kees es Note Please send e mail to the Technical Support Center for stepping ID details Use this e mail address LPD amd com The value returned in EAX after executing the CPUID instruction is identical to the value loaded into EDX upon CPU reset Software must avoid any dependency upon the state of reserved processor bits
235. CSA GP CSB Can cause a trap even when not programmed to come off the microcontroller at a pin PC Card Socket A I O access Can cause a trap the actual address range is programmed in the PC Card controller on the ElanSC400 microcontroller PC Card Socket B I O access Can cause a trap the actual address range is programmed in the PC Card controller on the ElanSC400 microcontroller Graphics I O access accesses to the graphics controller on the lanSC400 microcontroller can cause trap This includes addresses 03B4h 03B5h 03B8h 03BAh 03041 03D5h 03D8 03DCh External VGA video I O access access to addresses 03B4h 03B5h 03D4h 03D5h 03 0 03CCh 03CFh and or 03DAh can cause trap IDE hard drive access I O accesses addressed to 01F0 01F7h OSF6h and or 03F7h can cause a trap Floppy controller access Activity Monitor I O accesses addressed to 03F0 03F2h 03F4h 03F5h and or 03F7h can cause a trap An activity monitor keeps track of activities that indicate the CPU or peripherals are needed or in use so the PMU can determine what mode and clock speed is needed Activities reset timers and or cause mode changes The activity mode flow is diagrammed in Figure 5 8 Two levels of activity are provided primary and secondary activities Primary activities These activities require extensive CPU involvement and force the PMU back to High S
236. CSC index 42h function 5 3 Hyper Speed mode See power management unit PMU Access SMI Enable Register B CSC index 9Ah usage 3 10 17 9 Access SMI Enable Registers CSC index 99 9Ah function 5 6 Access SMI Status Register B CSC index 9Ch usage 3 10 17 9 Access SMI Status Registers CSC index 9B 9Ch function 5 7 Channel Ready signal See IOCHRDY signal I O Chip Select 16 signal See IOCS16 signal I O Instruction Restart Slot Register usage 5 31 Read Command signal See TOR signal Window Address Registers function 19 4 Window Control Register PC Card index 07h 47h function 19 4 Write Command signal See signal ICDIR signal description 4 11 usage 19 8 102 100 field usage 15 6 Identification and Revision Register PC Card index 00h 40h function 19 3 usage 19 23 infrared port block diagram 18 3 High Speed Infrared mode 18 1 18 5 18 7 back to back frames 18 9 bit stuffing 18 8 data modulation figure 18 7 data stream 18 7 10 8 18 9 18 10 18 12 FIFO usage 18 8 frame abort 18 9 frame format figure 18 6 frame sequences 18 7 interrupts 18 12 IrDA frame 18 6 receive and transmit state machines 18 8 serial infrared interaction pulse generation 18 12 transmit data transfers 18 10 18 11 initialization 18 13 IrDA standard xxiv 18 3 18 4 operation 18 3 overview 18 1 power management 18 13 reg
237. Compatible Mode FIFOs 15 44 Interrupts m bm RR m 15 5 InitlallzatiOn u supe xen demere et vae 15 6 Power Table of Contents xi CHAPTER 16 KEYBOARD INTERFACES 16 1 16 1 Overview ehe 16 1 16 1 1 Matrix Keyboard Interface 16 1 16 1 2 SCP 16 2 16 1 3 XT Keyboard Interface 16 2 16 2 REg IES sark ones ets ce pee eee ede dade E nd 16 3 16 3 16 5 16 3 1 Matrix Keyboard Interface 16 5 16 3 1 1 N Key Rollover 16 7 16 3 1 2 Key Pressed 16 7 16 3 1 3 Keyboard 16 8 16 3 1 4 CPU Scanned Keyboard 16 8 16 3 1 5 Keyboard 16 8 16 3 1 6 Typematic Support 16 9 16 3 2 SCP Emulation 16 9 16 3 2 1 SCP GATEA20 and Reset CPU Command Emulation 16 9 16 3 3 Keyboard System Scenarios 16 10 16 3 3 1 Simple Matrix Keyboard Support by Interrupting 16 10 16 3 3 2 Simple Matrix Keyboard Support by Polling 16 10 16
238. DD LCDD7 LC SCK LVEE Z LCDD5 VL LCLK FRM VL LDEV LCDD6 VL LRDY LCDD4 VL LCDD3 VL RST LCDDO VL W R LCDD2 ISA Bus AEN GPIO CS10 Set CSC index 38h 0 IOCHRDY GPIO CS6 Set CSC index 38h 3 GPIO CS5 Set CSC index 38h 4 GPIO CS11 Set CSC index 38h 0 GPIO CS12 Set CSC index 38h 0 GPIO CS9 Set CSC index 38h 0 STRB MCEL Clear CSC index 39h 1 0 MCEH B Clear CSC index 39h 1 0 SLCTIN RST B Clear CSC index 39h 1 0 INIT REG B Clear CSC index 39h 1 0 ERROR CD B Clear CSC index 39h 1 0 PE RDY B Clear CSC index 39h 1 0 ACK BVD1 B Clear CSC index 39h 1 0 BUSY BVD2 B Clear CSC index 39h 1 0 SLCT WP B Clear CSC index 39h 1 0 A 2 Multiplexed Pin Configuration Control Table 1 Multiplexed Pin Configuration Control continued Signals How to Configure the Signal You Want on the Pin Give Up Signal You Want GPIO22 Clear CSC index 39h 1 0 AMD 1 21 PPDWE Clear CSC index 39h 1 0 GPIO20 CD A2 Clear CSC index 3Ah 0 GPIO19 LBL2 Clear CSC index 39h 4 GPIO18 PCMB VPP2 Clear CSC index 39h 6 GPIO17 PCMB VPP1 Clear CSC index 39h 6 GPIO16 PCMB VCC Clear CSC index 39h 6 GPIO15 PCMA VPP2 Clear CSC index 39h 5 GPIO CS14 PCMA VP
239. DMA AEN TC PDRQO PDRQ1 PDACKT PDACKO Optional Interrupts PIRQ7 PIRQO Optional Table 4 14 Signals Shared with the ISA Interface 4 28 Default Signals Enabled Additional ISA Signals CSC Index Bit Bit 0 Bit 1 a 38h 4 GPIO_CS5 IOCST6 38h 3 GPIO CS6 IOCHRDY 38112 GPIO CS7 PIRQ1 38h 1 GPIO CS8 PIRQO 38h 0 GPIO CS12 GPIO CS9 PDRQO AEN TC 39h 2 KBD ROW12 KBD ROW7 MCS16 SBHE BALE PIRQ2 PDRQ1 PDACK1 3Ah 1 KBD COL6 KBD COL2 PIRQ7 PIRQS System Interfaces 4 7 5 4 7 5 1 4 7 5 2 4 7 5 3 Operation The ISA controller on the lanSC400 and lanSC410 microcontrollers generates all the required ISA bus command and control signals and ensures that the ISA timing specifications are met These specifications are based on the IEEE s Personal Computer Bus Standards P996 with certain non critical modifications Bus Speeds The ISA bus runs at a maximum speed of 8 294 MHz while the microcontroller is in High Speed mode In Low Speed or Temporary Low Speed mode the ISA bus speed is dictated by the CPU clock speed and can be programmed to be 8 924 4 147 2 074 or 1 037 MHz In Standby and Suspend modes the ISA bus is not functional The DMA controller clock can be programmed to 16 8 4 or 1 MHz when the microcontroller is in High Speed mode When in Low Speed or Temporary Low Speed mode the DMA clock runs at either the progr
240. DO REG_A Pull the BNDSCN EN pin High BNDSCN TMS MCEH A Pull the BNDSCN EN pin High Miscellaneous BLO IO Write CSC index 38h 7 6 to 01 CLK IO BLO Write CSC index 38h 7 6 to 10 to enable CLK IO as an output or to 11 to enable as a timer clock input SUS RES KBD ROW14 Clear bit 3 of the Keyboard Configuration Register Note This signal is not supported on the lanSC410 microcontroller Multiplexed Pin Configuration Control A 5 6 Multiplexed Pin Configuration Control TERMINATION gt When a particular function on the microcontroller is configured to be available to the user or the system the functions of the pins on the microcontroller change accordingly When the pin function changes the termination of the pin can and often does change System firmware must activate the new termination as a separate operation from the actual pin function selection This is done by setting the TERM LATCH bit in the Suspend Mode Pin State Override Register CSC index E5h 0 after configuring one or more of the microcontroller s pin functions The typical usage is to configure the chip at boot time from system firmware and then set the termination latch bit one time after all the configuration is complete When any of the pin functions shown in Table B 1 are changed the TERM LATCH bit must be set A more complete discussion of pin termination can be found in S
241. Elan SC400 and lanSC410 Microcontrollers User s Manual 1997 Advanced Micro Devices Inc All rights reserved Advanced Micro Devices Inc AMD reserves the right to make changes in its products without notice in order to improve design or performance characteristics The information in this publication is believed to be accurate at the time of publication but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein and reserves the right to make changes at any time without notice AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication This publication neither states nor implies any representations or warranties of any kind including but not limited to any implied warranty of merchantability or fitness for a particular purpose AMD products are not authorized for use as critical components in life support devices or systems without AMD s written approval AMD assumes no liability whatsoever for claims associated with the sale or use including the use of engineering samples of AMD products except as provided in AMD s Terms and Conditions of Sale for such products Trademarks AMD the AMD logo and combinations thereof are trademarks of Advanced Micro Devices Inc Am386 and Am486 are registered trademarks and Am186 Am188 E86 K86 lan Systems in
242. Enable High Speed 66 3552 MHz Graphics Dot p 2 18 432 MHz Clock Select gt 1 8432 MHz UART PLL Block p IO a CLK IO Select Lp 31 1 1892 MHz CLK IO 1 19318 36 864 MHz IN 66 3552 MHZ 33 1776 MHz DRAM and 2 Graphics 16 5888 MHz Controllers gt CPU and 8 2944 MHz VL Bus Be LL Be iB Controller 4 1472 MHz M 16 ISA Bus ROM Lys 32 2 0736 MHZ Controllers 64 1 0368 MHz gt Add Controller DRAM Clock Select CPU Clock Select ISA Bus Clock Select DMA Clock Select Note The graphics controller and the PC Card controller are not supported on the ElanSC410 microcontroller 6 2 Clock Control AMD OPERATION 6 4 6 4 1 Clock Generation The output of the crystal oscillator circuit on the lanSC400 microcontroller generates the various clock frequencies by utilizing four Phase Locked Loop PLL circuits Only three of these PLL circuits are available on the ElanSC410 microcontroller The PLL clock distribution scheme is shown in Figure 6 2 Table 6 2 shows all the PLL output frequencies and their usage Note that these PLL circuits are in addition to the internal CPU core PLL and do not replace it The four PLLs are called Intermediat
243. FO COM2 FIFO Control Port OBFAh O2FAh and then set up all the infrared registers Set SELMODE to 1 to select High Speed Infrared mode and set SELDEVICE to 1 to enable the infrared interface Enable the UART by setting the UART bit in the Parallel Serial Port Configuration Register CSC index D1h 0 Note that configuring the UART registers is not required for this mode 18 6 POWER MANAGEMENT Operation of the infrared port is affected by the power management functions shown in Table 18 2 Table 18 2 Power Management in the Infrared Port Power Management Effect Wake Up Activity Infrared Port Event Description UART Ring Indicate Triggered by the falling edge of RIN RIN signal UART Receive SIN Triggered by the falling edge of SIN signal CPU access to UART Triggered by the falling edge of the address Programmable internal or external decode qualified with commands UART access Accesses to COM1 03F8 03FFh or COM 02F8 02F Fh can cause SMI NMI through an trap Infrared Port 18 13 18 14 Infrared Port gt PC CARD CONTROLLER gt ElanSC400 MICROCONTROLLER ONLY 19 1 OVERVIEW The integrated dual PC Card controller is compliant with Standard Release 2 1 and supports up to two fully 82365 resource compatible PC Card sockets The PC Card Socket interface is shared with both the parallel port interface and the
244. FRDL R32BFOE DBUFRDH Disabled Disabled Disabled Disabled Disabled Disabled Disabled Enabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Enabled oioio o G Oj O 1 In table above CFG3 is defined as the enable disable for the DBUFOE DBUFRDL and DBUFRDH signals They can be enabled independently of whether or not a 32 bit D bus is selected via the firmware to support the VL local bus or 32 bit DRAM interface 2 The 32 bit ROM option must be selected on ROMCSO for the R32BFOE signal to be enabled The selection of the DBUFOE DBUFRDL and DBUFRDH signal are still dependent only on the CFG3 signal 8 5 2 8 5 2 1 8 8 Other ROMCSx Interface Configuration Options As seen above some features of the ROMCSO interface must be configured using hardware pin straps Other ROMCSO features and all features of ROMCS1 and ROMCS2 may be configured by software at any time after the boot code gets control Note that even the ROMCSO interface width may be changed by software after the pin straps have initially configured it This was provided mainly for test purposes All of the ROM chip select interfaces support the following additional features which may be configured by software firmware Data Width Control The ROMCSx data bus widths may each be independently configured for 8 16 or 32 bit wide operation using the CSC registers
245. GPIO CSO Output a 0 to bit 0 of the GPIO Read Back Write Register A CSC index A6h to allow ROMCS2 to propagate Output a 1 to bit of the GPIO CS Function Select Register A CSC index AOh to change the GPIO to being an output from being an input it should now be driven High because ROMCS2 is not being driven Automatic PMU Information Output Up to four GPIO CS pins can be programmed to inform external hardware of internal PMU states The internal signal names associated with this information are PMUA PMUB PMUC and PMUD Each of these signals has a register GPIO PMUx Mode Change Register CSC index AA ADh that defines its value during every distinct PMU state and each of these signals has a 4 bit field in the GPIO to GPIO CS Registers A and CSC index AE AFh that defines which if any GPIO CS pin it drives As noted above the GPIO s output bit in CSC indexed registers AO A5h must be 1 to set the pin to output mode and the GPIO s I O bit in CSC indexed registers A6 A9h must be 0 to allow the PMU signal to propagate Automatic Chip Select Outputs Upto six GPIO CS pins can be programmed as chip selects for external hardware devices The correct sequence for initializing a pin for use as a chip select is shown above in Section 17 5 3 Two of these chip selects ROMCS2 and SCP_CS select hard coded addresses with ROMCS2 selecting any memory operation to the ROMCS2 space SCP_CS selecting any I O
246. GPIO31 GPIO21 signals Only one of these interfaces can be enabled at one time The PC Card controller is not supported on the ElanSC410 microcontroller Each card socket is capable of DMA transfers between I O PC Cards and system DRAM DRQ and DACK pin configurability for DMA is a subset of the PC Card Standard also known as PC 95 or PC Card Standard Release 3 0 Berlin Drafts The PC controller also provides some register level extensions to a standard 82365 to support larger memory window addresses and faster PC Card timings Each socket is provided with five memory windows Each window can be opened anywhere above 64 Kbytes in the 400 microcontroller s 64 Mbyte memory map with 4 Kbyte granularity on 4 Kbyte boundaries Each window may be individually configured to access common or attribute memory Each socket is also provided with two I O windows that can be opened in the range of 0 64 Kbytes In order to save pins on the lanSC400 microcontroller some socket interface pins defined in the PCMCIA Standard Release 2 1 electrical specification are optional or not available B The pin is not supported B The second card detect input signal for Socket is optional shared with another feature and must be enabled by software if required The second card detect input signal for Socket B is not supported There is only one WAIT signal to support both sockets The PC Card controller supports
247. Hz 3x For all PMU modes except Hyper Speed mode the CPU is clocked by the microcontroller specific Phase Locked Loop PLL and clock generation circuitry However when Hyper Speed mode is used the four microcontroller specific PLLs are not used for CPU clock generation In this case the CPU core s own PLL is used When enabled Hyper Speed mode is entered from High Speed mode Any eventthattakes the microcontroller to High Speed mode does so while the CPU core PLL is brought up then switches to Hyper Speed mode The exception to this is when the Hyper Speed mode timer times out and drops to High Speed mode The PMU stays in High Speed mode until a primary activity or ACIN forces a change back to Hyper Speed mode or until the High Speed timer times out and PMU drops to Low Speed mode While the CPU core PLL is brought up the CPU cannot operate in static clock mode The CPU enters the Stop Grant state until the PLL stabilizes Going to High Speed mode while in the Stop Grant state allows any other device time to stabilize e g power on an external device can be turned on by a GPIO The clock selection 66 MHz or 100 MHz can be done at any time If it is done while in Hyper Speed mode it will not take effect until the next time the PMU goes to Hyper Speed mode The system must do a CPU Stop Grant using the CPU s Stop Clock Interrupt before the clock switching can be done for entering and exiting Hyper Speed mode This mode defaults
248. IRQ1 keyboard timer SMI NMI status and clear internal SCP emulation registers or external SCP chip select page 3 149 Keyboard Input Buffer Read Back Register 22h 23h Index C2h Storage of writes to direct mapped ports 0060h and 0064h page 3 151 Keyboard Output Buffer Write Register 22h 23h Index C3h Output buffer back door data shifted in from XT DATA page 3 152 Mouse Output Buffer Write Register 22h 23h Index C4h Mouse output buffer back door page 3 153 Keyboard Status Register Write Register 22h 23h Index C5h Keyboard status back door emulated SCP status register page 3 154 Keyboard Timer Register 22h 23h Index C6h Time delay before the keyboard timer SMI NMI occurs page 3 155 Keyboard Column Register 22h 23h Index C7h Column pin state read or write page 3 156 Keyboard Row Register A 22h 23h Index C8h Row pin state read or write page 3 158 Keyboard Row Register B 22h 23h Index C9h Row pin state read or write page 3 160 Keyboard Column Termination Control Register 16 4 22h 23h Index CAh Pin termination pull up or pull down resistor state read or write Keyboard Interfaces page 3 162 AMD 16 3 OPERATION 16 3 1 Matrix Keyboard Interface Figure 16 1 shows a block diagram of the matrix keyboard controller Note that anytime the interface DRAM VL bus or ROM is programmed for 32 bit
249. IRQO PIRQ1 AEN TC page 3 44 Index 38h IOCHRDY IOCS16 PDRQO PDACKO System Interfaces 4 25 Table 4 12 Register Pin Mux Register B Address 22h 23h Index 39h ISA Interface Register Summary continued ISA Interface Function ISA signal enable MCS16 SBHE BALE PIRQ2 PDRQ1 and PDACK1 Description in Register Set Manual page 3 45 Pin Mux Register C 22h 23h Index 3Ah ISA signal enable PIRQ7 PIRQ3 pin termination when the ISA interface is powered down in Suspend page 3 46 GP CSA B IO Command Qualification Register 22h 23h Index B8h Data bus width and timing for ISA cycles on GP CSA or CSB page 3 138 GP CSC D Memory Command Qualification Register 22h 23h Index BDh Data bus width and timing for ISA memory cycles GP CSC or GP CSD page 3 144 Internal I O Device Disable Echo Z Bus Configuration Register 22h 23h Index DOh CSC register echo and direct mapped register echo to ISA bus for debugging page 3 164 Write Protected System Memory DRAM Window Overlapping ISA Window Enable Register 22h 23h Index EOh Overlapping ISA window enable CPU accesses generate an ISA cycle instead of a DRAM cycle page 3 181 Overlapping ISA Window Start Address Register 22h 23h Index E1h Start address for the overlapping ISA window page 3 182 Overlapping ISA Window Size Register 22h 23h I
250. ISA bus The address is driven out onto the SA bus SA23 SAQO B SBHE is driven out if enabled BALE is driven out if enabled MCS16 and IOCS16 inputs are ignored if enabled or disabled AEN is asserted if enabled DBUFOE is deasserted if enabled E DBUFRDH and DBUFRDL are static if enabled IOW is asserted IOCHRDY input is ignored if enabled or disabled The write data is driven out onto SD7 SDO Note The annotation if enabled above refers to the fact that the pin s may or may not be configured for the ISA bus function There are some direct mapped registers that can be disabled when particular internal features are disabled such as the following Keyboard controller ports 0060h and 0064h PC Card controller ports and OSE1h ports 0070h 0071h UART ports COM1 at O3F8 03FFh and COMe at 02F8 02FFh Parallel port LPT1 at 0378 037Fh and LPT2 at 0278 027Fh System Interfaces 4 31 4 7 6 1 2 4 32 Internal graphics controller ports When these internal features are disabled accesses to these registers reads and writes will be treated as standard ISA bus cycles whether or not direct mapped register echoing is enabled Port 0070h is a special case Writes to Port 0070h always go to Port 0070h as well as to the ISA bus I O ports 0080h 0084 0086h 0088h and 008C 008Eh are also special cases Because these I O ports are bo
251. Last Mode Register CSC index 41h reflects the current mode and also the last mode the PMU was in The following are special cases as far as mode changes are concerned n High Speed mode when a primary activity happens the High Speed mode timer is merely restarted This is not a mode change therefore the PMU Present and Last Mode Change Register remains unchanged n Temporary Low Speed mode when a secondary activity happens the Temporary Low Speed mode timer is merely restarted This is not a mode change therefore the PMU Present and Last Mode Change Register remains unchanged High Speed Low Speed or Temporary Low Speed modes can be entered by programming the PMU Force Mode Register While in the same mode the PMU Present and Last Mode Register does not change because of this register write The Present and Last Mode Register continues to reflect the real last state the PMU was in The write to the PMU Force Mode Register restarts the mode s timer A register Clock Control Register at CSC index 82h 0 to enable keeping the Phase Locked Loops PLLs on during Suspend mode Registers CSC index 42 44h to set the timer value for each of the PMU modes Aregister bit CSC index 40h 4 to speed up all mode timers so that they time out more quickly during debug This is beneficial in reducing the time it takes to go through diagnostic routines to check out the board the microcontroller and power management sof
252. Low Speed modes it is serviced in that mode before changing modes When exiting the SMI routine any flag register that is still set will cause a new SMI and force the system back into the SMI routine When exiting the NMI routine the NMI DONE bit CSC index 9Dh 1 must be set to clear the NMI to the processor When an SMI NMI source is asserted while enabled to cause an SMI NMI it generates an SMI NMI Table 5 3 shows the SMI NMI sources Power Management Table 5 3 5 4 12 1 SMI NMI Sources AMD ACIN signal Rising or falling edge can cause interrupt BL2 BLO signals A falling or rising edge on any of the BL2 BLO signals can cause an interrupt SUS RES signal Rising edge falling edge or both can cause an interrupt Note that if the system is in Suspend mode and SUS RES is not enabled for resume the SMI NMI will not occur Hyper Speed mode High Speed mode Low Speed mode Stand By mode and Suspend mode timers These timer time outs can cause interrupts RTC alarm IRQ8 IRQ8 rising edge can cause an interrupt UART ring indicate Internal UART Ring Indicate RIN signal falling edge can cause an interrupt UART receive Falling edge of internal UART receive SIN signal can cause an interrupt Matrix keyboard key pressed Internal keyboard controller key pressed interrupt falling edge can cause an interrupt Keyboard timer Internal keyboard controller timer tim
253. M1 3F8 3FFh COM2 2F8 2FFh can cause an SMI or NMI through an trap Serial Port UART gt 16 KEYBOARD INTERFACES gt 16 1 The integrated keyboard controller on the lanSC400 ElanSC410 microcontrollers has the following features Matrix keyboard support with to 15 rows and 8 columns Hardware support for software emulation of the System Control Processor SCP emulation logic B XT keyboard interface In addition to the keyboard interfaces provided on the ElanSC400 and lanSC410 microcontrollers any one of the GPIO CSx pins can be enabled to output an external 8042 chip select 16 1 1 Matrix Keyboard Interface The integrated matrix keyboard controller directly interfaces to the rows and columns of a key matrix eliminating the need for external keyboard logic The custom matrix keyboard interface on the lanSC400 and lanSC410 microcontrollers offers the following features 15 row Schmitt trigger input signals with built in pull up resistors 8 column open drain output signals with built in pull up resistors TheSUS RES signal appears as a key in the Keyboard Row Register B CSC index C9h Keyboard Column Register CSC index C7h for setting the column signals Keyboard Row Registers A and for reading the row signals B An interrupt for signaling when a key is pressed A timer for interrupting the CPU to service the keyboard
254. MCSO accesses Note that if the device connected to the boot ROM chip select ROMCSO is less than or equal to 1 Mbyte in size it will alias throughout the 64 Mbyte ROMCSO address space ROM Flash Interface 8 5 1 and the ROM device will not be able to distinguish between two addresses such as 3FFFFFOh and O00FFFFOh This is the typical case in a PC AT compatible system If however the device is greater than1 Mbyte the ROM will decode more address lines and the device will be able to distinguish between the sample addresses of 3FFFFFOh and OOFFFFOh Because of this boot ROM devices used in PC AT compatible environments that are larger than 1 Mbyte must have far jump instructions located in the top 16 bytes of the physical ROM device Failure to do this will cause invalid instructions to be fetched by the CPU during boot up Configuring the ROMCSO Interface Using Pin Straps Several aspects of the ROMCSO interface must be established for devices that contain the boot code prior to the first instruction fetch These include selection of the data bus width 8 16 32 bits selection of the boot device ROMCSO or PC Card Socket A and the selection of GPIO pins or buffer control signals GPIO CS4 GPIO CS2 or DBUFOE DBUFRDH DBUFRDL and R32BFOE Four configuration pin straps which are sampled at power on reset are used to configure those functions that must be selected at reset prior to firmware execution CFG1 CFGOare
255. MD Trigger State ACIN signal 64h Programmable Rising edge of the ACIN signal CPU access to internal System registers 65h Programmable Falling edge of address decodes qualified with command Any VL bus activity memory or I O 62h Programmable Rising edge of the internal signal that decodes a VL bus cycle CPU access to ROMCS2 ROMCSO 62h Programmable Falling edge of chip select qualified with command CPU access to DRAM not in graphics controller range 63h Programmable When the DRAM IS ACT bit CSC index 631 1 is asserted rising edge DMA request 64h Programmable Rising edge of qualified PDRQ1 PDRQO the pin must be programmed as a PDRQ and assigned to a DMA channel that must be unmasked in the DMA controller Interrupt active all except IRQO timer tick Programmable Rising edge of any of the IRQs coming to the PMU Timer tick IRQO Programmable Rising edge of IRQO CPU access to parallel port Programmable Falling edge of address decode qualified with command CPU access to UART internal or external Programmable Falling edge of address decode qualified with commands UART ring indicate Programmable Falling edge of RIN pin UART receive Programmable Falling edge of SIN pin Matrix keyboard key press Programmable Falling edge of internal keyboard key pressed interrupt Keyboard timer time o
256. MM compliant debug handler is available The SMI handler must also ensure DR3 DRO are saved to be restored later The debug registers DRS3 DRO and DR7 must then be initialized with the appropriate values For the software to use the single step feature it must ensure that an SMM compliant single step handler is available and then set the trap flag in the EFLAGS Register If the system design requires the processor to respond to hardware INTR requests while in SMM it must ensure than an SMM compliant interrupt handler is available and then set the interrupt flag in the EFLAGS Register using the STI instruction Software interrupts are not blocked on entry to SMM and the system software designer must provide an SMM compliant interrupt handler before attempting to execute any software interrupt instructions Note that in SMM mode the interrupt vector table has the same properties and location as the Real mode vector table Am486 CPU 3 9 3 5 7 3 5 8 3 5 8 1 3 10 NMI interrupts are blocked entry to the SMI handler If an NMI request occurs during the SMI handler it is latched and serviced after the processor exits SMM Only one NMI requestis latched during the SMI handler If an NMI request is pending when the processor executes the RSM instruction the NMI is serviced before the next instruction of the interrupted code sequence Although NMI requests are blocked when the CPU enters SMM they may be enabled through s
257. OM is installed in the system The first access to the ROM under these conditions will use the wait states defined by the WAIT NBRSTx bit field and then the remainder of the accesses that make up a 16 byte transfer will use the faster timing that is specified by the WAIT BRSTx bit field ROM Flash Interface 8 9 8 5 2 3 8 10 Note that burst mode timings on the ROM interface will only be used when the ROM controller is fulfilling an internal CPU burst request to support a cache line fill At all other times non burst mode wait states will be used Thus burst mode ROM timings will only be used for paragraph aligned accesses because the CPU will not request an internal burst cycle otherwise Note that under certain conditions the ROM controller assembles data as a double word before transfer to the CPU The conditions are that the ROM access is a double word aligned read which is configured to be cacheable with the CPU cache enabled and the ROM interface width is configured to be 8 or 16 bits While the ROM controller is building the double word both the ROM chip select and the ROMRD signal are held in the active state while and A1 change to address ROM data as required This is done regardless of whether a burst mode capable ROM is in the system or not While this feature improves performance for very fast ROM devices it can cause some confusion if the ROMCSx or ROMRD signals are being used as clocks for logic ana
258. P1 Clear CSC index 39h 5 GPIO_CS13 Clear CSC index 39h 5 GPIO_CS12 PDRQO Clear CSC index 38h 0 GPIO CS11 PDACKO Clear CSC index 38h 0 GPIO_CS10 AEN Clear CSC index 38h 0 GPIO_CS9 TC Clear CSC index 38h 0 GPIO_CS8 PIRQO Clear CSC index 38h 1 GPIO_CS7 PIRQ1 Clear CSC index 38h 2 GPIO_CS6 IOCHRDY Clear CSC index 38h 3 GPIO_CS5 16 Clear CSC index 38h 4 GPIO CS4 DBUFOE Hardwire strap the CFG3 pin Low GPIO CS3 DBUFRDH Hardwire strap the CFG3 pin Low GPIO CS2 DBUFRDL Hardwire strap the CFG3 pin Low Parallel Port ACK GPIO25 BVD1 B AFDT GPIO30 MCEH BUSY GPIO24 BVD2 B H GPIO27 CD B GPIO28 REG B GPIO26 RDY B GPIO23 WP B GPIO29 RST GPIO31 MCEL B Write CSC index S9h 1 0 to 10 Keyboard Interfaces XT KBD COL1 Clear CSC index 39h 3 XT DATA KBD COLO Clear CSC index 39h 3 KBD COL6 PIRQ7 Clear CSC index 3Ah 1 KBD COL5 PIRQ6 Clear CSC index 3Ah 1 KBD COL4 PIRQ5 Clear CSC index 3Ah 1 KBD COLS PIRQ4 Clear CSC index 3Ah 1 KBD_COL2 PIRQ3 Clear CSC index 3Ah 1 KBD COL1 XT_CLK Clear CSC index 39h 3 Multiplexed Pin Configuration Control A 3 Table 1 4 Multiplexed Pin Co
259. PIO28 INIT GPIO27 ERROR GPIO26 PE GPIO25 GPIO24 BUSY GPIO23 SLCT GPIO22 PPOEN GPIO21 PPDWE 32KXTAL1 32KXTAL2 LF INT LF LS LF HS RESET VCC RTC SPKR BNDSCN EN AMD DRAM Interface and Feature Configuration Pins DRAM VL ROM and ISA Data VL ROM and ISA Address ROM Flash Control ISA Bus Command and Reset Boundary Scan Interface Parallel Port or GPIOs 32 KHz Crystal Loop Filters Reset RTC Speaker Boundary Scan Enable Note Two functions available on the pin at the same time Function during hardware reset Alternative function selected by firmware configuration 1 Alternate function selected by a hardware configuration pin state at power on reset System Interfaces 4 15 4 4 1 Table 4 5 Notes Using the Configuration Pins to Select Pin Functions The configuration pins are used only for those functions that must be selected at reset prior to firmware execution All other I O functions are selected using configuration registers Table 4 5 provides an overview of the configuration pin functions All of the CFG pins have weak internal pull down resistors that select the default function External pull up resistors are required to select an alternative function Pin Strap Bus Buffer Options 8 bit DBUFOE DBUFRDL DBUFRDH Disabled R32BFOE Disabled Reserved Reserved Reserved
260. PIOs GPIO External Buffer Control GPIO ISA Interface GPIO Power Control Scan Keyboard Columns IRQs XT Keyboard Interface Scan Keyboard Rows ISA Interface Scan Keyboard Rows DRAM Interface GPIO CS8 PIRQO 4 GPIO_CS13 t gt t __ gt GPIO17 505 RES KBD ROW14 lt lt VL_BE3 VL_LCLK VL_BRDY DTR RTS SOUT CTS DCD DSR RIN SIN SIROUT SIRIN ACIN BL2 BLT BLO 10 GPIO CSO GPIO CS1 GPIO CS2 DBUFRDI J GPIO CS3 DBUFRDH GPIO CS4 DBUFOE GPIO CS5 IOCS16 GPIO CS6 IOCHRDY GPIO CS7 PIRQ1 GPIO CS9 TC GPIO_CS10 AEN GPIO CS11 PDACKO GPIO C812 PDRQO GPIO CS14 GPIO15 GPIO16 GPIO18 GPIO19 LBL2 GPIO20 KBD COL7 KBD_COL6 2 PIRQ7 3 KBD COL1 0 XT_CLK DAT KBD_ROW13 R32BFOE KBD_ROW12 MCS16 KBD_ROW11 SBHE KBD_ROW10 BALE PIRQ2 ROWS PDRQ1 KBD_ROW7 PDACK1 KBD_ROWG6 MA12 KBD ROWS RAS3 KBD_ROW4 8452 ROWS CASH3 KBD_ROW2 CASH KBD_ROW1 CASL3 KBD ROWO CASL2 Multiplexed Pins on the lanSC410 Microcontroller MWE 51 50 1 5 MA4 CFG3 MA2 1 CFGO 015 00 015 500 031 018 y SA25 SA0 ROMCS1 ROMCSO RSTDRV BNDSCN TCK BNDSCN TMS BNDSCN TDI BNDSCN TDO lanSC410 Microcontroller 292 BGA GPIO31 STRB GPIO30 AFDT GPIO29 SLCTIN G
261. PIRQO signals control 4 25 PIRQ2 signal control 4 26 PIRQ7 PIRQO signals control 11 2 description 4 6 usage 11 1 14 2 PIRQ7 PIRQS signals control 4 26 PIT See programmable interval timer PIT Pixel Clock Control Register graphics index 4Ch function 20 5 usage 6 1 6 6 PLLRATIO bits usage 6 6 PMU Control Register 1 graphics index 50h function 20 6 usage 20 39 PMU Control Register 2 graphics index 51h function 20 6 usage 20 39 PMU Force Mode Register CSC index 40h function 5 3 usage 5 2 5 3 5 11 5 13 5 15 5 17 5 25 5 26 PMU mode change outputs See GPIO PMUA GPIO PMUD signals PMU Present and Last Mode Register CSC index 41h function 5 3 usage 5 2 PMU See power management unit PMU Power and RESETDRV Control Register PC Card index 02h 42h function 19 3 usage 19 20 power management unit PMU detect 5 24 activities activity monitor 5 32 activity source flag registers 5 33 activity sources table 5 35 primary activities 5 32 secondary activities 5 32 battery low 5 25 CPU clock speed reduction 5 26 Critical Suspend mode access 5 26 block diagram 5 8 general purpose GPIO pins 5 24 GPIO PMUA GPIO PMUD signals 5 24 initialization 5 36 modes ACIN mode flow figure 5 27 activity mode flow figure 5 34 BL1 BLO mode flow figure 5 28 BL2 mode flow figure 5 29 Critical Suspend mode 5 16 flowcharts 5 19 High Speed mode 5 11 Hyper Speed mode 5 10
262. PMU Force Mode Register CSC index 40h allows access to High Speed mode Power Management 5 11 5 4 2 1 5 4 2 2 5 4 2 3 5 12 Actions Taken During High Speed Mode The following actions are taken in the ElanSC400 and ElanSC410 microcontrollers during High Speed mode All parts of the system are clocked at full speed A summary of clock speeds PMU mode is shown in Table 6 6 Automatic slowdown is available in this mode When enabled via CSC index 81h the automatic slowdown feature slows down the CPU clock at a programmed interval for a programmed amount of time Although power is saved the automatic slowdown feature reduces average system performance because it slows down the CPU clock per a duty cycle that is software controllable via CSC index 81h B Ihe CPU clock is programmable to be 33 MHz 16 MHz or 8 MHz Note that the CPU clock on the ElanSC400 and ElanSC410 microcontrollers does not switch dynamically per type of access cycle Entering High Speed Mode The system goes to High Speed mode when High Speed Mode is not disabled via BL2 or and any of the following occurs Hardware reset the CPU clock will default to 8 MHz Hyper Speed mode timer times out A primary is detected and the microcontroller is not currently in Hyper Speed mode Resume or wake up from Suspend Programmed directly with the PMU Force Mode Register is enabled and the s
263. POEN GPIO23 DIR A4h 7 GPIO23 SLCT WP B GPIO24 DIR A5h 0 GPIO24 BUSY BVD2 GPIO25 DIR A5h 1 GPIO25 BVD1 GPIO26 DIR GPIO26 PE GPIO27 DIR GPIO27 ERROR CD B GPIO28 DIR A5h 4 GP1028 INIT REG B GPIO29 DIR A5h 5 GPIO29 SLCTIN RST B GPIO30 DIR A5h 6 GPIO30 AFDT MCEH B GPIO31 DIR A5h 7 GPIO31 STRB MCEL COLOPULLUP KBD COLO XT DAT COL1PULLUP CAh 1 KBD COL1 XT CLK COL2PULLUP CAh 2 KBD_COL2 PIRQ3 COL3PULLUP CAh 3 KBD COL3 PIRQ4 COL4PULLUP CAh 4 KBD_COL4 PIRQ5 COL5PULLUP CAh 5 KBD COLS PIRQ6 COL6PULLUP CAh 6 KBD COL6 PIRQ7 COL7PULLUP CAh 7 KBD COL7 B 4 Pin Termination Table B 1 Control Bit UART ENB D1h 0 AMD Pin Termination Control continued Control Bit CSC Index Pins Affected SIN RIN DSR DCD CTS SOUT RTS DTR PP MODE D2h 1 0 GPIO23 SLCT B GPIO24 BUSY BVD2 GPIO25 ACK BVD1 B GPIO26 PE RDY_B GPIO27 ERROR CD B GP1028 INIT B GP1029 SLCTIN RST B GPIO30 AFDT MCEH B GPIO31 STRB B SIRIN PD DIS EAh 6 SIRIN SKA PU EN F2h 0 GPIO20 CD A2 CD RDY BVD1 A BVD2 A WP A WAIT AB SKB PU EN F2h 1 GPIO23 SLCT WP B GPIO24 BUSY BVD2 GPIO25 ACK BVD1 GPIO26 PE RDY GPIO27 ERROR CD B This signal is not supported on the
264. PU access to keyboard registers PC Card and Keyboard SMI NMI 22h 23h SMI NMI enable matrix keyboard key press page 3 95 Enable Register Index 91h keyboard timer and Input Buffer Written and Keyboard Output Buffer Read interrupts PC Card and Keyboard SMI NMI 22h 23h SMI NMI status matrix keyboard key press page 3 100 Status Register Index 95h keyboard timer and Input Buffer Written and Keyboard Output Buffer Read interrupts SMI NMI Select Register 22h 23h SMI or NMI select page 3 104 Index 98h Access SMI Enable 22h 23h SMI enable for I O access to keyboard page 3 105 Register A Index 99h Access SMI Status Register A 22h 23h SMI state for I O access to keyboard page 3 107 Index 9Bh Standard Decode to GPIO CS 22h 23h External SCP chip select mapping to one of page 3 131 Map Register Index B1h the GPIO CS pins Keyboard Interfaces 16 3 16 1 Register Keyboard Configuration Register A Address 22h 23h Index COh Keyboard Interface Register Summary continued Keyboard Interface Function Keyword Keyboard configuration SMI NMI generation for SCP reset GateA20 command and SUS_RES KBD_ROW14 IRQ12 and IRQ1 generation for SCP emulation and XT interface reset disable GateA20 disable and keyboard transmit time out Description in Register Set Manual page 3 146 Keyboard Configuration Register B 22h 23h Index Cth XT keyboard interface enable XT keyboard select SMI NMI or
265. Pin Control Status Multiplexing GPIO CS Function Select Register A 22h 23h Index AOh GPIO CS3 GPIO 50 as inputs outputs primary activities or wake ups page 3 110 GPIO CS Function Select Register B 22h 23h Index A1h GPIO CS7 GPIO CS4 as inputs outputs primary activities or wake ups page 3 111 GPIO CS Function Select Register C 22h 23h Index A2h GPIO CS11 GPIO CS8 as inputs outputs primary activities or wake ups page 3 112 GPIO CS Function Select Register D 22h 23h Index A3h GPIO CS14 GPIO CS12 as inputs outputs primary activities or wake ups page 3 113 GPIO PMUA Mode Change Register 22h 23h Index AAh Drive GPIO PMUA signal with programmed value in PMU modes page 3 120 GPIO PMUB Mode Change Register 22h 23h Index ABh Drive GPIO PMUB signal with programmed value in PMU modes page 3 122 GPIO PMUC Mode Change Register 22h 23h Index ACh Drive GPIO PMUC signal with programmed value in PMU modes page 3 124 GPIO PMUD Mode Change Register 22h 23h Index ADh Drive GPIO PMUD signal with programmed value in PMU modes page 3 126 GPIO PMU to GPIO CS Map Register A 22h 23h Index AEh GPIO PMUA and GPIO PMUB mapping to GPIO CSx pins page 3 128 GPIO PMU to GPIO CS Map Register B 22h 23h Index AFh GPIO PMUC and GPIO PMUD mapping to GPIO CSx pins page 3 129 GPIO XMI to GPIO CS Map Register 22h
266. Port Configuration Register CSC index D1h 1 controls this selection IRQ levels are mapped separately using the Interrupt Configuration Register E CSC index D8h 6 5 The following direct mapped registers are available for COM1 and 2 B COMx Line Control Register Ports 02FBh OSFBh Used to configure the format of the UART frame for data transfer including character length stop bits and parity Set the DLAB bit in this register to gain access to the baud rate divisor latches Clear the Serial Port UART 15 1 DLAB bit to access to the Transmit Holding and Receive Buffer registers at Port OxF8h and the Interrupt Enable Register at Port OxF9h COMx Baud Clock Divisor Latch LSB Ports 02F8h 03F8h Holds the least significant byte of a 16 bit baud rate clock divisor that is used to generate the 16x baud clock when COMx DLAB is 1 COMx Baud Clock Divisor Latch MSB Ports 02F9h 03F9h Holds the most significant byte of the clock divisor when COMx DLAB is 1 COMx Transmit Holding Register Ports 02F8h 03F8h The byte to be transmitted is written to this write only register when COMx DLAB is 0 COMx Receive Buffer Register Ports 02F8h 03F8h The received byte is read from this read only register When DLAB is 0 This register shares an address with the Transmit Holding Register COMx Interrupt Enable Register Ports 02F9h 03F9h Enables the following serial port interrupts modem
267. QO RSTDRV 4 30 Reset System Interfaces 4 7 6 4 7 6 1 4 7 6 1 1 Using the ISA Bus for Debugging Both direct mapped and CSC indexed register accesses can be made to echo on the ISA bus for debugging purposes This feature provides a data path for all register bits to be propagated to the pins of the chip Setting bits 4 and 5 in the Internal I O Device Disable Echo Z Bus Configuration Register CSC index DOh allows all core register accesses including PC AT cores and CSC indexed registers to be seen from the outside of the chip on the ISA bus Allnon echoed CSC indexed registers PC Card indexed registers and graphics indexed registers operate at CPU speeds All other non VL bus non echoed I O accesses use ISA timing When programmed to echo on the ISA bus direct mapped and CSC indexed registers are accessed at ISA bus speeds The following paragraphs describe this debugging feature for direct mapped and CSC indexed registers Echoing Direct Mapped PC AT Registers Direct mapped register accesses in the ElanSC400 and ElanSC410 microcontrollers can be echoed onto the external ISA bus by setting CSC index DOh 4 This echo feature selection is disabled by default This bit has no affect on the CSC indexed register echo feature Direct Mapped Register Writes During an write to a direct mapped register when the echo feature is enabled the following activity occurs on the external
268. R TSSR EFLAGS 0000 0002h CRO Bits 0 2 3 and 31 PE EM TS and PG cleared rest unmodified DR6 Unpredictable state DR7 0000 0400h CS Selector 3000h Base SMBASE Default value 30000h Attributes 16 bit Expand Up Limit 4 Gbytes EIP 0000 8000h DS ES FS GS SS Selector 0 Base 0 Attributes 16 bit Expand Up Limit 4 Gbytes NMI Non maskable interrupts are disabled on entry To enable execute an IRET from with SMI handler Note 1 The CS Selector value remains at 3000h even if SMBASE is changed SMM Execution Environment Table 3 4 shows the state of the CPU on entry to SMM mode The following is a summary of key features in the SMM environment Real mode style address calculation 4 Gbyte address limit checking TF flag in EFLAGS is cleared and single step traps are disabled IF flag is cleared and NMI is disabled is cleared and debug traps disabled E The RSM instruction no longer generates an invalid opcode exception Opcodes register and stack default to 16 bit usage The processor begins execution of the SMI handler at offset 8000h in SMBASE SMBASE defaults to 30000h but may be moved from within an SMI handler See Section 3 5 9 for details on relocating SMBASE As Table 3 4 shows the CS Selector value is 3000h This is true even if SMBASE has been relocated so care should be taken when reloading CS or if attempti
269. RET will not store the proper value in the CS Base If interrupts are to be enabled or exceptions may occur the SMM handler should perform a far jump to itself at its actual location For example if SMBASE has been relocated to A0000h the following code sequence could be performed push 0A000h new segment selector A000h 16 A0000n push offset ReturnLocation retf far return to self ReturnLocation Any jump call or return that does not have an operand size override prefix and any interrupt or exception will truncate both the new EIP and the return address if any to the 16 low order bits If the SMM handler will be executing any code above 1 Mbyte interrupts should not be enabled and exceptions should not be allowed to occur SMMBASE is not reset as a result of typical reset conditions triple fault Port 0092 0 etc unless an SMI is pending or active in which case a hard reset will occur Exceptions and Interrupts When the CPU enters SMM it disables INTR interrupts debug and single step traps by clearing the EFLAGS DR6 and DR7 registers This prevents a debug application from accidentally breaking into an SMI handler This is necessary because the SMI handler operates from a distinct address space SMRAM and the debug trap does not represent the normal system memory space For an SMI handler to use the debug trap feature of the processor to debug SMI handler code it must first ensure that an S
270. Register CSC index AA ADh that defines its value during every distinct PMU state Each of these signals has a 4 bit field in the GPIO PMU to GPIO CS Map Registers A and B CSC index AE AFh that defines which if any GPIO CS pin it drives The pin s output bit in CSC indexed registers A0 A5h must be 1 to set the to output mode The pin s bit in CSC indexed registers A6 A9h must be 0 to allow the PMU signal to propagate ACIN Detect and Battery Low Four signals are brought into the microcontroller from outside so that the state of the system power can be reported to the microcontroller and used in the power management scheme The Alternating Current INput ACIN signal is meant as an indication that the system is connected to a greater source of power such as an AC wall plug and that power savings are no longer as important as performance The Battery Low and BL2 signals are digital inputs that external voltage comparators or an external processor can drive to inform the microcontroller of the state of the charge on the system batteries Each Battery Low signal can report a different level in the battery discharge For example they may be used as follows B BLO Batteries are getting weak so slow down the clock in High Speed Mode B BLi Batteries are weaker so disable High Speed mode and limit the PMU to to Low Speed mode as the highest mode Power Management 5 4 11 1 5 4 11 2 B
271. Register B RTC index OBh function 13 3 usage 13 5 13 6 Register C RTC index OCh function 13 3 usage 13 6 Register D RTC index ODh function 13 3 usage 4 2 registers Activity Classification Register A 5 5 Activity Classification Register B 5 5 Activity Classification Register C 5 5 Activity Classification Register D 5 5 Activity Source Enable Register A 5 4 Activity Source Enable Register B 5 4 Activity Source Enable Register C 5 4 Activity Source Enable Register D 5 5 Activity Source Status Register A 5 5 Activity Source Status Register B 5 5 Activity Source Status Register C 5 5 Activity Source Status Register D 5 5 Address Window Enable Register 7 2 19 4 Battery Low and ACIN SMI NMI Enable Register 5 6 Battery Low and ACIN SMI NMI Status Register 5 6 Battery AC Pin Configuration Register A 5 5 Battery AC Pin Configuration Register B 5 5 Battery AC Pin State Register 5 5 Cache and VL Miscellaneous Register 3 1 7 1 Card Status Change Interrupt Configuration Register 19 4 Card Status Change Register 19 4 CGA Color Select Register 20 3 CGA Data Port 20 2 CGA Index Address Register 20 2 CGA Mode Control Register 20 3 CGA Status Register 20 3 CGA MDA Data Port 20 2 CGA MDA Index Register 20 2 chip setup and control CSC indexed register map table 2 6 CLK IO Pin Output Clock Select Register 6 1 Clock Control Register 6 1 Index AMD register
272. Row 0 00B8000h l 00B809Fh Display Row 1 00B80A0h I 00B813Fh Display Row 2 00B8140h Pas 00B81DFh Display Row 24 0 8 T 00B8F9Fh 00B8FAO0h Unused 00B8FFFh Notes C is Character byte A is Attribute byte 20 4 5 1 2 20 16 The CGA compatible buffer base address of 00B8000h must be programmed at mode setup through the Shared Memory Address registers This buffer may also be relocated to any other 16 Kbyte boundary in the lower 16 Mbyte of memory if CGA memory address compatibility is not necessary In MDA emulation mode the screen pages begin at 00BOO00h instead of 00B8000h For compatibility the Shared Memory Address registers must be programmed to the appropriate values at mode setup Unlike the original IBM MDA mode four pages of text are available instead of one Character Byte The character byte can be any number from 00h to FFh to designate one of the 256 fonts stored in a font table in memory For example the ASCII code for the letter A is 41h so assuming the frame buffer base address has been set to 00B8000h to display an A in Graphics Controller Figure 20 9 20 4 5 1 3 the upper left corner of the screen one would write 41h into address 00880001 The character byte is used as by the graphics controller as a pointer to the appropriate font location in memory see Section 20 4 5 3 for more information
273. SC index 82h Clock Control Table 6 4 Clock Speeds Clock Programmable Speed Comments CPU 1x clock 33 18 MHz 16 59 MHz 8 29 MHz Default Programmable to one speed at a time for High Speed 8 29 MHz on reset mode 33 18 MHz for Hyper Speed mode clock multiplied by the CPU core PLL to be 66 MHz or 100 MHz to the CPU only 8 29 MHz 4 15 MHz 2 07 MHz 1 04 MHz Programmable to one speed at a time for Low Speed Default 8 29 MHz on reset and Temporary Low Speed modes 0 MHz Clock is stopped in Standby and Suspend modes Memory 66 MHz Clocked at 66 MHz whenever the graphics controller on clock the ElanSC400 microcontroller is enabled and displaying data to the LCD The graphics controller uses the main DRAM as its memory and must access it at 66 MHz whenever data is being displayed to the LCD 2x CPU clock rate Clocked atthe 2x CPU clock rate whenever the graphics controller is not displaying data to the LCD 36 864 MHz Clocked from the Low Speed PLL in Standby mode when this feature is enabled and the LCD is enabled 0 MHz Clock is stopped when no DRAM accesses are occurring such as in Suspend mode or Standby mode when the LCD is shut off DRAM refreshes will continue under the control of the 32 KHz clock Graphics dot 20 736 MHz to 36 864 MHz Speed required is selected by the graphics controller clock depending on the LCD to be driven and graphics mode selected 0 MHz Clock is stopped in modes in w
274. SC400 and ElanSC410 microcontrollers includes the following documents The Elan SC400 and ElanSC410 Microcontrollers Data Sheet order 21028 includes complete pin lists pin state tables timing and thermal characteristics and package dimensions for the ElanSC400 and ElanSC410 microcontrollers The 52400 Microcontroller Register Set Reference Manual order 21032 provides a complete description of all the registers required to program the ElanSC400 and ElanSC410 microcontrollers The 486 Microprocessor Software User s Manual order 18497 includes the Am486 microprocessor instruction set Appendices provide useful information about programming the base architecture and system level registers A glossary of terms is also included Note that this document describes floating point features not supported on the ElanSC400 and lanSC410 microcontrollers Other documents of interest Enhanced Am4869 Microprocessor Family Data Sheet order 19225 Am4869DX DX2 Microprocessor Hardware Reference Manual order 17965 Note that this document describes floating point features not supported on the ElanSC400 and ElanSC410 microcontrollers Additional Information The following non AMD documents provide additional information that may be of interest to users of the ElanSC400 and ElanSC410 microcontrollers IEEE Std 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture order SH16626 NYF Institute
275. SO ROM interface System Interfaces 4 4 1 2 Table 4 7 4 4 1 3 Table 4 8 4 4 1 4 AMD CFG2 Pin On the ElanSC400 microcontroller this configuration pin see Table 4 7 is used for selecting the ROMCSO steering at system boot time CFG2 is not supported on the ElanSC410 microcontroller The boot ROM chip select ROMCSO can either be enabled to drive the ROMCSO pin or can be rerouted to drive the PC Card socket A only interface chip selects The CFGO and CFG1 pins still used to select the data bus width for ROMCSO decode regardless of the CFG2 configuration The PC Card ROMCSO redirection should not be selected when the CFGO and 1 configuration pins are setto select a 32 bit ROM interface See Section 7 6 4 2 for more information on redirecting ROMCSO to PC Card Socket A When the ROM chip select decode has been redirected to PC Card socket A all of the normal PC Card controller features can still be used to drive the PC Card Socket A interface The ROM chip select and decode remapping to the PC Card socket can be enabled and disabled using firmware at any time CFG2 Configuration Enables the ROMCSO decode on the ROMCSO pin 1 Enables the ROMCSO decode to access PC Card socket A CFG3 Pin This configuration pin is used for selecting between the GPIO CS4 GPIO CS2 pins and the SD bus buffer control signals DBUFOE DBUFRDL and DBUFRDH When the buffer control signal configuratio
276. Silicon and AMD Facts On Demand are trade marks of Advanced Micro Devices Inc FusionE86 is a service mark of Advanced Micro Devices Inc Microsoft and Windows are registered trademarks of Microsoft Corp Product names used in this publication are for identification purposes and may be trademarks of their respective companies IF YOU HAVE QUESTIONS WE RE TO HELP YOU Customer Service The AMD customer service network includes U S offices international offices and a customer training center Expert technical assistance is available from the worldwide staff of AMD field application engineers and factory support staff to answer E86 family hardware and software development questions Hotline and World Wide Web Support For answers to technical questions AMD provides a toll free number for direct access to our corporate applications hotline Also available is the AMD World Wide Web home page and FTP site which provides the latest E86 family product information including technical information and data on upcoming product releases For technical support questions on all E86 products send E mail to Ipd support amd com Corporate Applications Hotline Additional contact information is listed on the back of this manual 800 222 9323 toll free for U S and Canada 44 0 1276 803 299 U K and Europe hotline World Wide Web Home Page and FTP Site To access the AMD home page go to http www amd com To download docu
277. Status Register 18 2 Pin Mux Register B 17 2 Keyboard Column Register 16 4 Pin Mux Register C 17 2 Keyboard Column Termination Register 16 4 Pin Strap Status Register 8 1 17 2 Keyboard Configuration Register A 16 4 Pixel Clock Control Register 20 5 Keyboard Configuration Register B 16 4 PMU Control Register 1 20 6 Keyboard Input Buffer Read Back Register 16 4 PMU Control Register 2 20 6 Keyboard Output Buffer Write Register 16 4 PMU Force Mode Register 5 3 18 Index registers continued PMU Present and Last Mode Register 5 3 Power and RESETDRV Control Register 19 3 Programmable Interval Timer 1 Mode Control Register 12 1 Recovery Timing Registers 19 4 Register A 13 3 Register B 13 3 Register C 13 3 Register D 13 3 ROMCSO Configuration Register A 8 2 ROMCSO Configuration Register B 8 2 ROMCST Configuration Register A 8 2 ROMCST Configuration Register B 8 2 ROMCS2 Configuration Register A 8 2 ROMCS2 Configuration Register B 8 2 RTC Alarm Hour Register 13 3 RTC Alarm Minute Register 13 2 RTC Alarm Second Register 13 2 RTC Current Day of Month Register 13 3 RTC Current Day of Week Register 13 3 RTC Current Hour Register 13 2 RTC Current Minute Register 13 2 RTC Current Month Register 13 3 RTC Current Second Register 13 2 RTC Current Year Register 13 3 Setup Timing Registers 19 4 SMI NMI Select Register 5 6 Standard Decode To GPIO_CS Map Register 17 3 Start Addre
278. System Interfaces 4 5 Table 4 4 Signal Type Signal Description Table continued Description IOCHRDY STI PU Channel Ready should be driven by open drain devices When pulled Low during ISA access wait states are inserted in the current cycle This pin has an internal weak pull up that should be supplemented by a stronger external pull up usually 4 7 or 1 Kilohm for faster rise time 16 Chip Select 16 The targeted device drives this signal active early in the cycle to request a 16 bit transfer Read Command indicates that the current cycle is a read from the currently addressed I O device When this signal is asserted the selected I O device may drive data onto the data bus This signal is also shared with the PC Card interface Write Command indicates that the current cycle is a write to the currently addressed I O device When this signal is asserted the selected I O device may latch data from the data bus This signal is also shared with the PC Card interface Memory Chip Select 16 bit is used to signal to the ISA control logic that the targeted memory device is a 16 bit device Memory Read Command indicates that the current cycle is a read of the currently addressed memory device When this signal is asserted the memory device may drive data onto the data bus Memory Write Command indicates that the current cycle is a write of the currently
279. T 1 10 system interfaces 1 13 Local VL bus 1 15 package dimensions xxiv pin designations xxiv register descriptions xxiv signals not supported 4 13 system considerations 1 16 System diagram with trade offs figure 1 19 thermal characteristics xxiv timing xxiv Enhanced PC Card mode See PC Card controller EPP mode See parallel port ERROR signal control 14 2 description 4 9 Extend Bus Cycle signal See WAIT AB signal Extended Feature Control Register graphics index 52h function 20 6 usage 20 13 20 20 20 35 F FAST ROM bit usage 8 11 Fast Speed ROM mode See ROM Flash interface fields See bits FIFOEN bit usage 15 7 Font Buffer Base Address High Byte graphics index 4Eh function 20 5 Index Font Table Register graphics index 42h function 20 5 usage 20 10 20 21 20 32 Frame Buffer Base Address Register graphics index 4Dh function 20 5 usage 20 9 20 23 20 24 Frame Sync Delay Register graphics index 39h function 20 5 Frame Font Buffer Base Address Register Low graphics index 4Fh function 20 5 usage 7 2 20 9 20 24 FRM signal description 4 11 usage 20 38 20 39 G General Purpose signals See GPIO31 GPIO15 signals general purpose input output GPIO general purpose chip selects GP CSA GP CSD 17 8 forcing an SMI 17 9 mapping to a GPIO CS pin 17 9 PMU activities 17 9 GPIO signals block diagram figure 17 4 GPIO CS signals 17 8 block di
280. TC Reset nterna ese BBATSEN Register A B C D Y 4 Bytes gt PIC IRQ8 y Clock Calendar Upate Clock Alarm Internal Bus Calendar RAM 10 Bytes Interface BCD Binary Increment User RAM 114 Bytes Figure 13 2 RTC Voltage Monitor RTC Band Gap BRL _ Voltage Reset Monitor RTC Only Powered Mode BBATSEN 13 4 Real Time Clock AMD 13 4 OPERATION Programs can retrieve time and calendar information from the RTC by reading the appropriate RTC index registers Programs can also change the time calendar and alarm information in the RTC by writing to these registers The 24 12 bit in Register B establishes whether the hour locations represent 1 to 12 or 0 to 23 The 24 12 bit cannot be changed without re initializing the hour registers When the 12 hour format is selected the high order bit of the hours byte represents PM whenitis a 1 The three alarm bytes can be used in two different ways If the alarm enable bit is set the alarm interrupt occurs at the time specified in the appropriate hours minutes and seconds alarm registers B don t care state any hexadecimal byte CO FFh is written to one or more of three alarm registers 13 4 1 Interrupts The RTC provides three different interrupt sources All three are connected internally to IRQ8 The three interrupt sources are Periodic interrupt Can be set at rates from 500 ms to 122 us Alarm interrupt Can be
281. TDRV Control Register PC Card index 02h Socket A and Index 42h Socket B are used to control these features as shown in Table 19 16 and Table 19 17 VPP Control Signal Definition Bit 1 Bit 2 Vpp Control Bit 1 Bit 0 PCMx VPP2 PCMx VPP1 PCMx VCC Comments 0 0 Vpp is N C Voc enabled Vpp enabled Vpp 12 Voc enabled Vpp is N C Voc enabled 19 20 Vpp is N C Vcc disabled PC Card Controller Table 19 17 Socket CD_x Low Control Signal Definition Bit 5 PC Card Power Active Bit 4 V Auto Power CC PCMx VCC Bit 6 of Interface Comments Control ower Status Register X 0 Socket forced off X 0 1 Socket forced on No 1 0 Auto power enabled and no card inserted 19 5 11 2 Table 19 18 Auto power enabled and card inserted powered The lanSC400 microcontroller does not directly support the external data buffer control pin as is found on the 82365SL controller The ElanSC400 microcontroller s PC Card implementation is essentially a non buffered 82365SL design An external buffer may be included in the system design and would require a small amount of external logic to provide the appropriate control Power Considerations for System Design Powering down sections of a system during operation is difficult to handle correctly and the PC Card power planes are no different Fully buffering
282. TE O Strobe In Standard mode this signal is used to indicate to the parallel port device to latch the data on the parallel port data bus In EPP mode this signal is driven active during writes to the EPP data or the EPP address register Serial Port CTS Clear To Send is driven back to the serial to indicate that the external data carrier equipment DCE is ready to accept data DCD Data Carrier Detect is driven back to the serial from a piece of data carrier equipment when it has detected a carrier signal from a communications target DSR Data Set Ready indicates that the external DCE is ready to establish a communication link with the internal serial port controller DTR O Data Terminal Ready indicates to the external DCE that the internal serial port controller is ready to communicate RIN Ring Indicate is used by an external modem to inform the serial port that a ring signal was detected A change in state on this signal by the external modem may be configured to cause a modem status interrupt This signal may be used to cause the chip to resume from a Suspend state System Interfaces 4 9 Table 4 4 Signal Description Table continued Signal Type Description RTS Request To Send indicates to the external that the internal serial port controller is ready to send data SIN Serial Data In is used to receive the serial data from the external serial device
283. The lanSC400 and ElanSC410 microcontrollers offer flexibility in configuring the ROM and DRAM data buses for different widths The widths 8 16 32 bits for ROMCSO are programmed during power up through two pin straps CFGO and CFG1 The DRAM widths 16 32 bits are programmed through configuration registers Up to four 16 or 32 bit banks of DRAM are supported Architectural Overview 1 13 1 2 15 2 1 2 15 3 Address Buses There are two external address buses on the lanSC400 and lanSC410 microcontrollers System Address Bus The SA25 SAO system address bus outputs the physical memory or I O port latched addresses These addresses are used by all external peripheral devices other than main system DRAM In addition the system address bus is the local address bus in VL bus mode DRAM Address Bus DRAM row and column addresses are multiplexed onto the DRAM address bus 12 Row addresses are driven onto this bus and are valid upon the falling edge of RAS Column addresses are driven onto this bus and are valid upon the falling edge of CAS The SA bus is shared between the ISA bus the VL bus the ROM Flash controller and onthe lanSC400 microcontroller the PC Card controller The lanSC400 and lanSC410 microcontrollers provide programmable drive strengths in the I O buffers to accommodate loading for various system configurations Memory Management Chapter 7 The lanSC400 and lanSC410 microcont
284. _LCD signals description 4 12 VCC_MEM signals description 4 13 VCC_PCM signals description 4 13 _ 2 signals description 4 13 VCC_RTC signal description 4 13 usage 13 7 VCC_SER signals description 4 13 VCC_SYS signals description 4 13 VERTDOUB bit usage 20 33 Vertical Adjust Register graphics index 35h function 20 4 usage 20 32 Vertical Border End Register graphics index 38h function 20 5 usage 20 33 Vertical Display End Register graphics index 37h function 20 5 usage 20 32 VESA local bus See VL bus controller VL_ADS signal description 4 7 usage 4 37 VL BES3 VL BEO signals description 4 7 VL BLAST signal description 4 8 usage 4 37 VL BRDY signal description 4 8 VL D C signal description 4 8 usage 4 36 VL LCLK signal description 4 8 usage 4 37 VL LDEV signal description 4 8 usage 4 37 VL LRDY signal description 4 8 usage 4 37 24 VL signal description 4 8 usage 4 36 VL RST signal description 4 8 usage 4 2 4 38 VL W R signal description 4 8 usage 4 36 VL bus controller address interface 4 36 block diagram 4 36 data bus byte ordering table 4 37 data interface 4 36 initialization 4 38 normal bus cycles 4 37 operation 4 36 overview 4 35 power management 4 38 registers 4 35 special bus cycles 4 37 special bus cycles table 4 38 unsupported VL bus signal 4 38 VL Bus Standard 2 0 xxiv VHT bit usage 4 2 13 7 W WAIT AB sig
285. a serial data unit or SDU the corresponding Slow Speed Infrared mode SDU is shown in Figure 18 4 The infrared port accepts the serial data input from the external IrDA device that has been squared and conditioned to the appropriate logic level The incoming pulse on the SIRIN pin is detected and appropriately stretched Figure 18 3 UART Serial Data Unit SDU Prior to Modulation UART SDU gt Start Lata Els Stop 38 Bit Figure 18 4 Slow Speed Infrared Mode SDU After Modulation 18 4 2 Slow Speed Infrared SDU a 4 B Stop Bit Bit Time 1 627 ms High Speed Infrared Mode High Speed Infrared mode supports a fixed transfer rate of 1 152 Mbit s This mode is characterized by a continuous data stream and always uses DMA for data transfers Since many of the High Speed Infrared mode features were implemented to address requirements in the IrDA standard for 1 152 Mbit s operation a short overview of the high speed IrDA frame structure is presented in this section to provide a basis for further discussion The intent of this section is to provide some basic familiarity with a high speed IrDA frame so that the user will understand how to use the High Speed Infrared mode controls provided on the lanSC400 and lanSC410 microcontrollers Infrared Port 18 5 18 4 2 1 High Speed IrDA Frame The basic unit of data transfer defined by th
286. ace are the default speeds Other speeds listed are programmable options B The solid arrows represent the default configurations Dashed arrows show programmable options An arrow leaving a mode at the same point where another arrow enters it represents what happens afterthe entering arrow event happens For example in Figure 5 2 when the High Speed mode timer times out and is programmed to cause an SMI NMI the SMI NMI will happen while in High Speed mode After the interrupt is serviced the system will then drop to Low Speed Mode SMI NMI done An SMI is done when the state restore from the SMI Return instruction is completed An NMI is done when CSC index 9Dh 1 is written Interrupts in High Speed Mode Example Timer Time out amp SMI NMI Enabled Power Management 5 19 Figure 5 3 PMU Timer Mode Flow Reset Feature Default gt Feature Option Hyper Speed enable HvPER SPEED MODE 66 100 MHz Timer Timer Time out Time out Time amp SMI NMI amp SMI NMI Enabled SMI NMI Enabled SMI NMI Done Done OW SPEED MODE 8 4 2 1 MHz Time Time out TEMPORAR Timer _ SMINMI Low SPEED Time Enabled MODE out a Perform SMI NMI I di Low Speed Mode d d 1 Timer Time t amp SMI NMI
287. achine and ICW register pointer Master ICW2 4 are programmed via Port 21h Each time Port 21h is written to following ICW1 the register pointer points to the next internal ICW register Programmable Interrupt Controller 11 5 11 6 The interrupt controller provides interrupt information to the on chip power management unit to allow the monitoring of the system activity A qualified interrupt is sent to the PMU when an interrupt request is active and not masked in the PIC or when an interrupt in service bit is set These signals are implemented as combinatorial paths to allow speeding up or starting of the system clocks depending on which device generates the interrupt request Operation of the programmable interrupt controller is affected by the power management functions shown in Table 11 4 Table 11 4 Power Management in the Programmable Interrupt Controller Power Management Effect PIC Event Description Wake Up Activity SMI NM Yes External interrupt Triggered by a rising edge of any of the request three PIRQ2 PIRQO signals if the PIRQ is enabled mapped to an internal IRQ and the IRQ function is selected via CSC index 38h 1 2 Internal interrupt Triggered by rising edge of any internal IRQ Programmable request coming into the PMU 11 6 Programmable Interrupt Controller gt 1 2 PROGRAMMABLE INTERVAL TIMER 12 1 12 2 12 2 1 i
288. address in DRAM ROMO ROM1 or ROM spaces allowing access to any 32 Kbytes on 32 Kbyte boundaries Complete control over MMS Window A is provided via CSC index registers 32 and 33h MMS Window B when enabled occupies the 64 Kbytes of CPU address space from 0100000h 1 Mbyte to 010FFFFh A20 control must be enabled e g via a read from Port OEEh before MMS Window B will function properly because the PC AT compatible A20 remapping occurs before the MMU receives the address from the CPU From Real mode the last 16 bytes in this window are inaccessible the rest can be accessed using segment 000FFFFh with an offset from 10h to OOOFFFFh however the window still allows access to any address in DRAM ROMO ROM1 or ROM spaces because the address granularity is 32 Kbytes This is the same as MMS Window A even though the size of MMS Window is 64 Kbytes Complete control over MMS Window B is provided via CSC index registers 34h and 35h MMS Windows A and B differ from MMS Windows C F in that they have a fixed decode region and the user supplies a destination start address only 1 To move SMRAM which defaults to 3000 8000 the program must first store an initial handler at 38000h force an SMI to occur e g using CSC index 90h 0 and change SMBASE from within the SMI handler before is suing an RSM instruction Advanced memory mapping can be used to store the runtime SMI handler at the desired address 7 8 Memory Manag
289. aded B gt 1 0 AEN 8237 Compatible Control DMA Controllers TC WE DACK 7 0 or OE DRQ 7 0 Target Memory DRAM ISA ADDR 15 0 1 gt or PC Card Control Memory A Signals 10 4 HLDA HOLD To From CPU Page and Extended Page Registers Note Instead of BVD2 A and BVD2 B the PC Card signals WP A and WP B can be programmed as DMA requests This selection is made in the PC Card Mode and DMA Control Register CSC index F1h 7 4 The PC Card controller is not supported on the ElanSC410 microcontroller DMA Controller 10 4 10 4 1 Table 10 2 AMD OPERATION The ElanSC400 and ElanSC410 microcontrollers support standard PC AT DMA transfers as follows Only fly by DMA transfers are supported A fly by transfer is a transfer in which the data is moved from the I O device to memory DMA write or from memory to the I O device DMA read in a single transaction Single block and demand transfers are supported Memory to memory transfers are not supported The DMA controller operates in standard PC AT mode at 4 MHz or optionally at 8 or 16 MHz The faster speed reduces DMA overhead significantly but is non standard It should only be used when all DMA initiators are capable of the faster timing The internal infrared controller is capable of using the fast DMA timing Note that there is no method to automatically change the DMA controller clock based on init
290. agram figure 17 5 PMU activity and wake up 17 8 SMI NMI generation 17 8 initialization 17 6 GPIO pins and simple input 17 6 GPIO pins and simple output 17 7 GPIO CS pins and automatic output 17 7 automatic chip select outputs 17 7 automatic PMU information output 17 7 overview 17 1 external pins 17 1 internal chip select logic 17 1 power management 17 9 registers 17 2 signal descriptions 4 10 system implications 17 6 GP CS Activity Enable Register CSC index 60h function 5 4 17 2 usage 17 9 GP CS Activity Status Register CSC index 61h function 5 4 17 2 usage 17 2 17 9 GP CS to GPIO CS Map Registers CSC index B2 B3h function 17 3 AMD GP CSA Address Decode and Mask Register CSC index B5h function 17 3 GP CSA Address Decode Register CSC index B4h function 17 3 GP CSA B Command Qualification Register CSC index B8h function 17 3 GP CSB Address Decode and Mask Register CSC index B7h function 17 3 GP CSB Address Decode Register CSC index B6h function 17 3 GP CSC Memory Address Decode and Mask Register CSC index BAh function 17 3 GP CSC Memory Address Decode Register CSC index B9h function 17 3 GP CSC D Memory Command Qualification Register CSC index BDh function 17 3 GP CSD Memory Address Decode Register CSC index BBh function 17 3 GPIO as a Wake Up or Activity Source Status Registers CSC index 5A 5Bh function 5 4 17
291. ains in the Shift DR state if BNDSCN TMS is Low Exit1 DR State This is a temporary state While in this state if BNDSCN is held High a rising edge applied to BNDSCN TCK causes the controller to enter the Update DR state which terminates the scanning process If BNDSCN TMS is held Low and a rising edge is applied to BNDSCN TCK the controller enters the Pause DR state The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state Pause DR State The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between BNDSCN TDI and BNDSCN TDO An example of using this state could be to allow a tester to reload its pin memory from disk during application of a long test sequence The test data register selected by the current instruction retains its previous value during this state The instruction does not change in this state Test and Debugging 21 3 1 8 21 3 1 9 21 3 1 10 21 3 1 11 21 3 1 12 The controller remains in this state as long as BNDSCN TMS is Low When BNDSCN TMS goes High and a rising edge is applied to BNDSCN the controller moves to the Exit2 DR state Exit2 DR State This is a temporary state While in this state if BNDSCN TMS is held High a rising edge applied to BNDSCN TCK causes the controller to enter the Update DR state
292. air as implemented in the PC AT system The master controller drives the CPU s interrupt input signal based on the highest priority interrupt request pending at the master controller s IRQ7 IRQO inputs The master IRQ2 input is configured for Cascade mode and is driven only by the slave controller s interrupt output pin The highest pending interrupt at the slave s IRQ inputs will therefore drive the IRQ2 input of the master Architectural Overview 1 2 6 3 1 2 6 4 1 2 6 5 1 2 7 AMD The interrupt controller has programmable sources for interrupts that are controlled through extended configuration registers and on the ElanSC400 microcontroller through PC Card controller configuration registers Programmable Interval Timer PIT Chapter 12 The programmable interval timer on the lanSC400 and ElanSC410 microcontrollers is software compatible with PC AT 8254 system timers The PIT provides three 16 bit counters that can be operated independently in six different modes The PIT is generally used for timing external events counting and producing repetitive waveforms The PIT can be programmed to count in binary or in BCD Real Time Clock RTC Chapter 13 The RTC designed into the lanSC400 and lanSC410 microcontrollers is compatible with the 146818 device used in PC AT systems The consists of time of day clock with alarm interrupt and a 100 year calendar The clock calendar has a programmable periodic interrupt 1
293. allel Port EPP Chapter 14 The parallel port on the lanSC400 and lanSC410 microcontrollers is functionally compatible with IBM PC AT and PS 2 systems with an added EPP mode for faster transfers The microcontroller s parallel port interface provides all the status inputs control outputs and the control signals necessary for the external parallel port data buffers The parallel port interface on both microcontrollers is shared with some of the GPIO signals and on the ElanSC400 microcontroller with the second PC Card socket interface Only one of these interfaces can be enabled at one time Architectural Overview 1 9 1 2 8 1 2 9 1 10 The parallel port interface be configured to operate in one of three different modes of operation PC AT Compatible mode This mode provides a byte wide forward host to peripheral channel with data and status lines used according to their original Centronics definitions in the IBM PC AT B Bidirectional mode This mode offers byte wide bidirectional parallel data transfers between host and peripheral equivalent to the parallel interface on the IBM PS 2 Enhanced Parallel Port EPP mode This mode provides a byte wide bidirectional channel controlled by the microcontroller It provides separate address and data cycles over the eight data lines of the interface with an automatic address and data strobe for the address and data cycles respectively EPP mode offers wid
294. alling edge of address decode Programmable Card Socket A and qualified with command PC Card INTR signal Triggered by falling edge Programmable PC Card Socket A and Can cause an SMI NMI through an I O trap B I O access the actual address range is programmed in the PC Card controller 19 24 PC Card Controller EN 2 GRAPHICS CONTROLLER lansc400 MICROCONTROLLER ONLY 20 1 OVERVIEW The graphics controller included on the lanSC400 microcontroller offers a low cost integrated graphics solution for the mobile terminal market Integration with the main processor and system logic affords the advantages of an integrated local bus interface and frame and font buffers which are shared with main memory The graphics controller is not supported on the lanSC410 microcontroller The graphics controller includes the following features Supports multiple panel resolutions B Provides internal unified memory architecture UMA with optional write through caching of graphics buffers Stores frame and font buffer data in system DRAM eliminates extra memory chip Provides software compatibility with Color Graphics Adapter CGA Monochrome Display Adapter MDA and Hercules Graphics Adapter HGA text and graphics Supports single scan or dual scan monochrome LCD panels with 4 or 8 bit data interface B Typical panels supported include 640x200 640x240 640x480 480x320 480x2
295. als are the reset for their respective cards When active this signal clears the Interrupt and General Control Register PC Card index O3h and 43h thus placing a card in an unconfigured Memory Only mode state It also indicates the beginning of any additional card initialization These pins are not supported on the ElanSC410 microcontroller WAIT AB Extend Bus Cycle delays the completion of the memory access or I O access that is currently in progress When this signal is asserted Low wait states are inserted into the cycle in progress Only one WAIT input is provided on the chip External logic is required for a two socket implementation to logically AND digitally OR each card s WAIT signal together This pin is not supported on the ElanSC410 microcontroller WE TC Card Write Enable is the PC Card memory write signal Data will be transferred from the chip to the PC Card When PC Card DMA is enabled the DMA Terminal Count to the PC Card will appear on this signal This pin is not supported on the ElanSC410 microcontroller WP A IOIS16 A Write Protect indicates the status of the respective card s Write Protect switch When the DRQ_A WP B respective is configured for an I O interface this signal is used by the card to indicate IOIS16 B back to the chip that the currently accessed port is 16 bits wide When PC Card DMA is B enabled the DMA request from the PC Card can be programmed to appear on this signal
296. always be generated even if CAS no strobes are asserted during one of them The highest order word is always read or written first DRAM Controller 9 5 The DRAM controller will burst CPU cache line fills and flushes using four 32 bit or eight 16 bit back to back CAS cycles if the CPU clock speed is 16 MHz or above The CPU core dictates the order in which the four double words are accessed See the Am486DX DX2 Microprocessor Hardware Reference Manual order 17965 for details For 16 bit banks each of the four 32 bit memory cycles is stretched into two CAS cycles with the highest order word accessed first Table 9 2 System Address to CAS Strobe Mapping 16 Bit Non interleaved inactive inactive inactive inactive 32 bit Non interleaved 1 A1 1 A1 16 bit Interleaved inactive inactive inactive inactive 32 bit Interleaved 9 6 A2 A1 A0 DRAM Controller A2 A1 A0 A2 A1 A0 A2 A1 A0 Table 9 3 DRAM Bank Configurations Physical Bank Configuration CSC Index 00 03h Bit Values Depth Width 512 Kbytes 1 Mbyte ao 2 Mbytes Do 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes Note 1 In this case if all DRAM banks are 16 bits wide at least one of the enable
297. ame GPIO CS pin or to a pin to which PMUx has been mapped Using General Purpose Chip Selects as PMU Activities The GP CS Activity Enable Register CSC index 60h allows any of the general purpose chip selects to be programmed to be primary or secondary activities The GP CS Activity Status Register CSC index 61h allows software to determine which general purpose chip select activity occurred Using General Purpose Chip Selects to Force an SMI accesses decoded by GP CSA and GP CSB can be trapped by setting bits 5 and or 6 in the I O Access SMI Enable Register B CSC index 9Ah The SMI handler can determine and clear the cause of the SMI by examining and resetting bits 5 and or 6 in the I O Access SMI Status Register CSC index 9Ch The SMI handler can emulate the I O or restart the instruction See Chapter 3 for SMI handler details In addition the GPIO_XMI to GPIO_CS Map Register CSC index BOh can be used in conjunction with any one GPIO_CS pin to cause either an SMI or NMI This works with output pins as well as input pins so even GP_CSC and GP_CSD could be programmed to cause an SMI or NMI by programming them to drive the pin that CSC index BOh is sampling POWER MANAGEMENT Operation of the GPIOs is affected by the power management functions shown in Table 17 2 Power Management in the GPIOs Power Management Effect Wake Up Activity Description GPIO CS14 GPIO CSO Triggered by falling edge on the signal
298. ammed value or the CPU clock speed whichever is lower or itcan be disabled Timing compatible with legacy DMA is achieved when the DMA controller is configured to 4 MHz Faster timings however are not anticipated to cause problems for modern DMA devices Addressing All address signals on the lanSC400 and ElanSC410 microcontrollers are internally latched from SA23 through SAO This differs from standard ISA where address bits 23 17 are provided non latched The address to command setup time provided for SA23 SA17 is sufficiently fast that these signals may be connected to devices that decode ISA signals LA23 LA17 early in order to generate MCS16 or IOCS16 If a device has signal pins for standard ISA signals LA19 LA17 and SA19 SA17 the microcontrollers SA19 SA17 pins may be connected to both sets of corresponding device address pins BALE is provided as a programmable option for compatibility purposes SBHE is also available as a programmable option for external devices that require it Note that the microcontroller s address space extends to 64 Mbytes with the addition of address bits SA24 and SA25 ISA memory space is limited to a maximum 16 Mbytes however MEMR and MEMW will not be asserted for any accesses above the programmed limit with the exception of the memory overlay window explained below The ISA memory overlay feature allows the overlapping of a single block of ISA memory space on top of system DRAM space This b
299. an Row Adjust F D int H F D F D where font height in lines D 2 for line doubling 1 otherwise H half the total number of lines in the panel int integer division In CGA graphics modes the character height is 2 one even addressed line and one odd addressed line Therefore the Dual Scan Row Adjust Register would be set to 0 unless there were an odd number of lines in a half screen in which case it would be programmed to 1 In flat mapped modes the character height is 1 Therefore the Dual Scan Row Adjust Register is always set to 0 in these modes Dual Scan Row Offset Address Registers The Dual Scan Offset Address registers graphics index 3C 3Dh must be programmed with a value equal to the number of whole character rows in the upper screen multiplied by the number of bytes in a character row Continuing the example above there are 8 complete character rows in the upper screen see calculation above Each character is represented in memory by 2 bytes and there are 640 8 80 characters in a row This gives 160 bytes in each character row Therefore the Dual Scan Offset Address registers should be programmed with the product of 160 and 8 or 1280 decimal 500h In general Dual Scan Offset Address bytes in a character row or line int H F D where H equals half the total number of scan lines in the panel F is the font height in lines D 2 2 when line doubling is enabled 1 othe
300. anSC400 and ElanSC410 microcontrollers can address up to nine distinct memory spaces System memory address space DRAM ROMO memory address space ROM1 memory address space ROM2 memory address space PC Card A memory address space both data and attribute memory spaces ElanSC400 microcontroller only PC Card B memory address space both data and attribute memory spaces ElanSC400 microcontroller only External ISA VL bus memory address space Memory Management Figure 7 1 64 Mbyte 0110000 0100000 00BCO000 00B8000 00B0000 MMS E MMS D FT __ M MMS 0 Mbyte 0 Mbyte 0 Mbyte 0 Mbyte 0 Mbyte AMD For the purposes of this discussion the VL and ISA buses are treated identically However the designer should realize that they are prioritized by VL bus peripherals if a VL bus peripheral claims a bus cycle the ISA bus never sees it The size of each spaceis 64 Mbyte however as noted in the previous section the 16 Mbyte ISA bus is aliased four times into its 64 Mbytes The lanSC400 and lanSC410 microcontrollers support two classes of memory management schemes non translated and translated memory management Non translated accesses In this case the MMU hardware simply selects one of the 9 distinct memory spaces for the read or write and the memory address is passed unchanged to the hardware controlling that space Translated accesses In this case MMU trans
301. and Implemented Instructions The Instruction Register IR is a 4 bit register that allows instructions to be serially shifted into the device The instruction determines the test to execute the data register to access or both The least significant bit is nearest the BNDSCN TDO output When the TAP controller is reset the Instruction Register is loaded with the default instruction IDCODE Figure 21 2 Logical Structure of Boundary Scan Register Boundary Scan Register System Bidirectional Pin System Logic Input System Three State Output TDO 17852A 090 21 2 3 1 Test Access Port Instruction Set The lanSC400 and ElanSC410 microcontrollers support all three mandatory boundary scan instructions BYPASS SAMPLE PRELOAD and EXTEST along with two additional instructions IDCODE and HIGHZ Table 21 1 shows the TAP instructions that are supported on the lanSC400 and ElanSC410 microcontrollers Table 24 1 Test Access Port Instruction Set Instruction IRS IRO EXTEST SAMPLE PRELOAD IDCODE HIGHZ BYPASS Test and Debugging 21 3 EXTEST The instruction code is 0000 The EXTEST instruction allows testing of circuitry external to the component package typically board interconnects It does so by driving the values loaded into the microcontroller s BSR out on the output pins corresponding to each boundary scan cell It then captures the values on the microcontroller s input pi
302. andler will be entered The hardware will set bit 0 of the I O Access SMI Status Register B CSC index 9Ch 0 to indicate the SMI was caused by trapping a floppy disk controller access Am486 CPU 3 5 8 2 3 5 9 When the SMI handler notices that bit 0 is set the handler should take the following actions Reset this bit by writing OFEh to CSC index 9Ch Power up the floppy disk controller this action is system implementation dependent Restore all floppy disk controller registers to valid states Make the RSM instruction restart the trapped I O instruction by setting the word at the I O Instruction Restart Slot to OOFFh Execute the RSM instruction to allow the floppy access to proceed Note that if one of these I O trap bits in CSC index 9B or 9C is set upon entry to SMI the condition should be dealt with before exiting SMM Restarting an instruction from a subsequent back to back SMI request is not legal I O traps should be prioritized ahead of other SMI causes in the SMI dispatcher Emulating Instructions Trapped instructions can also be emulated and then discarded rather than restarted When a valid I O instruction has been trapped bit 1 of the word at SMBASE 0FFO4H is set When this bit is set bit O of the same word will be 1 if the interrupted instruction was attempting an I O read or 0 for a write and the word at SMBASE OFFO6h will contain the
303. anism to control power to unneeded peripherals transparently to application software To reduce power consumption the floating point unit has been removed from the Am486 CPU core Floating point instructions are not supported on the ElanSC400 and ElanSC410 microcontrollers although normal software emulation can be implemented easily The lanSC400 and ElanSC410 microcontrollers use the industry standard 486 instruction set All software written for the 486 microprocessor and previous members of the x86 architecture family can run on the ElanSC400 and ElanSC410 microcontrollers 3 2 REGISTERS A summary listing of the direct mapped and chip setup and control CSC index registers used to control the CPU on the lanSC400 and ElanSC410 microcontrollers is shown in Table 3 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Table 3 1 CPU Control Register Summary Description Register Address CPU Control Function Keyword in Register Set Manual Direct Mapped Registers RTC CMOS RAM Index Register 0070h Master NMI enable page 2 52 Chip Setup and Control CSC Index Registers Non Cacheable Window 0 22h 23h SMM cache enable and auto flush on SMM page 3 20 Address Attributes SMM Index 11h entry Register Cache and VL Miscellaneous 22h 23h CPU write through or write back cache select page 3 23 Register Index 14h write back bus cycle status
304. annel Address 10 5 Table 10 3 16 Bit DMA Channel Address 10 5 Table 10 4 Supported DMA Initiator Target Combinations 10 6 Table 10 5 ISA DMA Cycle lt 10 8 Table 10 6 DMA Channel Mapping 10 8 Table 10 7 Power Management in the DMA 10 9 Table of Contents Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 12 1 Table 12 2 Table 12 3 Table 13 1 Table 13 2 Table 13 3 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 15 1 Table 15 2 Table 15 3 Table 15 4 Table 15 5 Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 17 1 Table 17 2 Table 18 1 Table 18 2 Table 19 1 Table 19 2 Table 19 3 Table 19 4 Table 19 5 Table 19 6 Table 19 7 Table 19 8 Table 19 9 Table 19 10 Table 19 11 Table 19 12 Table 19 13 Table 19 14 Table 19 15 Table 19 16 Table 19 17 Table 19 18 Table 19 19 Table 20 1 Table 20 2 Table 20 3 Table 20 4 Table 20 5 Table 20 6 Table 20 7 Table 20 8 Table 20 9 Table 20 10 Table 20 11 Table 20 12 Programmable Interrupt Controller Register Summary 11 2 IRQ Mapping eR RII IR RA IH n 11 4 Interrupt VeCtOrs sese Roe RR mec Reb 11 5 Power Management in the Programmable Interrupt Controller
305. ard function on the ElanSC400 microcontroller the boundary scan interface for either microcontroller is enabled by asserting the dedicated BNDSCN_EN configuration pin Using the BNDSCN_EN pin in this way makes this implementation on the ElanSC400 and ElanSC410 microcontrollers non compliant with Std 1149 1 Standard Test Access Port and Boundary Scan Architecture otherwise the JTAG features on the ElanSC400 and ElanSC410 microcontrollers follow this IEEE standard Test and Debugging 21 1 21 2 2 21 2 2 1 21 2 2 2 21 2 2 3 Figure 21 1 The following pins are configured for their boundary scan function when BNDSCN EN is asserted BNDSCN_TCK Test Clock Input Test Clock is JTAG input clock that is used to access the Test Access Port BNDSON TDI Test Data Input Input Test Data Input is the serial input stream for JTAG scan input data BNDSOCN Test Data Output Three State Output Test Data Output is the serial output stream for JTAG scan result data BNDSCN Test Mode Select Input Test Mode Select is an input for controlling the Test Access Port Test Data Registers The lanSC400 and lanSC410 microcontrollers contain the two required test data registers Bypass Register and Boundary Scan Register In addition it includes a Device Identification Register Each test data register is serially connected to BNDSCN TDI and BNDSCN TDO with BNDSON TDI connected
306. are not available on the ElanSC410 microcontroller Configuration pin CFG2 PC Card controller signals MCEL A MCEL B MCEH A MCEH B RST A RST B REG B CD CD B CD A2 RDY B BVD1 A BVD1 B BVD2 A BVD2 B WP A WP B WAIT AB OE WE ICDIR POMA PCMA_VPP1 PCMA VPP2 PCMB VCC PCMB VPP1 PCMB VPP2 Graphics controller signals LCDD7 LCDDO M LC SCK LVEE LVDD B Loop filter signal LF VID The following power pins are renamed on the ElanSC410 microcontroller BI The two LCD pins are called VL on the ElanSC410 microcontroller PCM and 2 are both called PP on the ElanSC410 microcontroller 4 4 MULTIPLEXED PIN FUNCTION OPTIONS Many pins on the lanSC400 and ElanSC410 microcontrollers have more than one function Figure 4 1 and Figure 4 2 show the multiplexing of pins by function for each microcontroller Pins with multiplexed functions have their functions selected in one of two ways By configuration pins that are latched during reset By firmware via programmed configuration registers Reference tables showing which configuration registers are used to select pin functions are included in Appendix A of this manual System Interfaces 4 13 Figure 4 1 LCD Graphics Controller or VESA Local Bus 8 Pin Serial Port Infrared Interface Power Management Interface GPIOs GPIO External Buffer Contro
307. as pressed 2 When the key is detected pressed for several milliseconds it is accepted as a valid hit and used by the software Keyboard Interfaces 16 3 3 3 Scenario 3 Matrix Keyboard Support with PC AT Compatibility The following is one possible scenario of how the system would use the keyboard controller if PC AT compatibility is required i e the system runs standard PC AT software and has to guarantee that accesses directly to the keyboard controller will work 1 No keys are pressed Write the Keyboard Column Register all low 00 and enable the key pressed interrupt to cause an SMI on a key press any row goes Low The CPU can continue to run the application software without polling the keyboard now 2 Enable the Input Buffer Full flag IBF being set to cause an SMI 3 Enable the Output Buffer Full flag OBF being cleared to cause an SMI 4 When key is pressed an SMI occurs and the CPU stops running the application software and jumps to the SMI code to service the keyboard 5 The SMI keyboard service code disables the key pressed interrupt from causing an SMI writes the Keyboard Column Register with FEh to set only column 0 low reads the Keyboard Row Registers A and B to see if any of the keys on column 0 are pressed continues to walk a 0 through all the columns and reads the rows to identify all the keys that are pressed 6 The timer is then set for some amount of time and enabl
308. ating system independent method of adding support for specialized hardware features Two uses that may be quite common with systems based on the lanSC400 and ElanSC410 microcontrollers are power management and PC AT keyboard emulation because complete hardware support for both of these features is integrated directly into the lanSC400 and lanSC410 microcontrollers Am486 CPU 3 3 3 5 2 3 5 3 3 4 Power management is a good example of something that has both hardware specific and operating system specific components Basic power management can be performed completely transparently to the operating system with hardware support This is possible because the operating system knows nothing about SMM The power management unit PMU can cause a System Management Interrupt SMI to occur based on various PMU activities see Chapter 5 for details The operating system knows nothing about the SMI which causes the transition to SMM Code in the SMM handler usually provided by the BIOS will respond to the activity and cause a power management state transition and then return from the SMI with a resume RSM instruction The matrix keyboard controller can also generate SMIs With the hardware support provided by the lanSC400 and lanSC410 microcontrollers an SMI handler can let the matrix keyboard controller emulate a PC AT keyboard also completely transparently to the operating system See Chapter 16 for details SMM Requi
309. ay Reverse Reverse and Normal Underline IXIXIXIXIX X X IX XIX IX IX X X X IX XIX IX IX X X XC IXIXIXIXIX X X IX XIXIX IX X X X X XIX IX IX X X EX IXIXIXIXIX X X X IX XIXIXIX X X IX X XIX IX IX X X XC IXIXIXIXIX X X X IX XIXIX IX X X IX IX XIX IX IX X X IX IX XIXIX IX XIX IX IX XIXIX X X X IX X XIXIX X X X XC IX XIXIX IX XIX IX IX XIXIX IX X X XIXIX IX X X XC IX XIXIXIX X X IX IX XIXIX IX X X IX X XIXIX IX X X XC IX XIXIXIX X X IX IX XIXIXIX X X IX IX XIXIX IX X X IX X X IX XIXIXIX X X
310. banks I O pad drive strength for SA23 page 3 18 Index 07h SD15 SDO Cache and VL Miscellaneous 22h 23h MMU DRAM access delay 2 7 V operation page 3 23 Register Index 14h Activity Source Enable Register B 22h 23h Activity source enable CPU access to DRAM page 3 72 Index 63h non graphics access Activity Source Status Register B 22h 23h Activity source status CPU access to DRAM page 3 76 Index 67h non graphics access Activity Classification Register B 22h 23h Primary or secondary activity classification page 3 80 Index 6Bh CPU access to DRAM non graphics access Suspend Pin State Register A 22h 23h DRAM interface state in Suspend mode page 3 184 Index E3h Note 1 CASL3 CASL2 CASH3 CASH2 RAS3 RAS2 and MA12 can be enabled by setting the correct bits in any of the four configuration registers 32 bit data width and either Bank 0 or Bank 1 enabled or just Bank 2 or Bank 3 enabled DRAM Controller 9 3 9 3 BLOCK DIAGRAM Figure 9 1 shows an example DRAM subsystem with all four banks populated The memory address MA data D and memory write enable MWE signals are shared by all banks The DRAM output enables OE are not driven by the lanSC400 and ElanSC410 microcontrollers and should be grounded Each bank 0 3 has a corresponding RAS signal Each microcontroller byte lane 0 3 has a corresponding CAS signal The CAS signals are further subdivided in
311. bles disassembles double word to and from the CPU for fast ROM cycles Supports programmable wait states based on the CPU bus clock for faster ROMs Slower ROMs are also supported by starting the ISA controller and using the ISA bus speed MEMR and MEMW signals B High performance support for burst mode ROMs B Drives appropriate data steering signals during 8 and 16 bit cycles The ROM Flash interface operates at the CPU bus speed maximum 33 MHz and provides three separate ROM chip selects Note that DMA to ROM devices is not supported on the lanSC400 and lanSC410 microcontrollers Note also that if the 32 bit ROM interface is enabled the matrix keyboard interface is not available and on the lanSC400 microcontroller the internal graphics controller is unavailable 8 2 REGISTERS A summary listing of the chip setup and control CSC index registers used to control the ROM Flash interface is shown in Table 8 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Table 8 1 ROM Flash Interface Register Summary Description Register Address ROM Flash Interface Function Keyword in Register Set Manual Pin Strap Status Register 22h 23h Data bus width default boot interface ROMO page 3 25 Index 20h or PC availability of the external buffer control signals Linear ROMCSO Shadow 22 22h Linear ROMO decode boot ROM caching and page 3 2
312. buffered for each card In Suspend mode and IOW are left High this would back power the card if it is not buffered off WAIT Signals Shared with the other PC Card socket Because the WAIT signals for the two sockets need to be ORed together logical OR since they are active Low this is actually an AND gate their pull ups must be handled carefully On the system board each card s WAIT pull up would normally be tied to that card s Voc but this can cause problems in a non buffered system With each socket WATT pulled up to that card s Voc and the two WAIT signals ORed together neither socket can be powered down at any time even if it does not have a card installed If one socket is powered down when the other socket is in use the powered down socket s Vcc goes away the pull up no longer pulls up the AND gate gets a low input the WAIT signal is seen as Low at the ElanSC400 microcontroller and the system locks up when it attempts to access the socket with a card The lanSC400 microcontroller cannot distinguish which card is actually pulling the WAIT The best approach for this is to tie the socket WAIT pull ups to a Vcc that is always on when the system is operating This pull up should be gated so the cards can be powered off in Suspend mode and will not be back powered by the WAIT pull up B OE WE Signals Shared with the other PC Card socket If the card is to be powered off in Suspend mode then these signals should be bu
313. but not ATA and booting the BIOS or XIP eXecute In Place O S image Thus multiple builds can be kept on different PC Cards and swapped out quickly as required There are several caveats to keep in mind when redirecting ROMCSO to PC Card Socket A via the CFG2 pin strap First of all the PC Card that is used must not decode more of the PC Card space than it actually has physical memory for Many linear Flash SRAM cards perform only a partial decode of the address space The amount of decode is equal to the physical memory on the card Such a PC Card will be aliased throughout the PC Card memory space For example a 4 Mbyte card with this type of address decoding will appear atO O3FFFFFh 0400000 07FFFFFh and soon allthe way through 64 Mbytes Card memory space This is important because the boot vector address driven to the PC Card will always be 3FFFFFOh so card that does not alias and that is less than 64 Mbyte will have no way to hook the boot vector Because the CPU will begin fetching from 3FFFFFOh PC Cards must supply a boot vector hook in the top 16 bytes of the card space Note that the first access beyond the current segment will cause A25 A20 to be asserted As long as no inter segment code control transfer call jmp etc occurs code can be fetched from any location in the top 64 Kbytes of the PC Card indefinitely In order to Memory Management 7 7 7 7 1 7 7 2 7 7 3 continue operation fr
314. can be used to drive either a standard eight pin serial interface or a two pin infrared interface using the chip setup and control CSC index registers The infrared port is fully documented in Chapter 18 The UART powers up as a 16450 compatible device It can be switched to and from the 16550 compatible mode under software control In 16650 compatible mode the receive and transmit sections are each aided by 16 byte FIFOs to off load the CPU from repetitive service routines The serial port includes the following features B Fight pin interface serial in serial out six modem control lines Separately enabled receiver line status receiver data character timeout transmitter holding register and modem status interrupts Programmable UART transfer rates up to 115 Kbit s Baud rate generator provides input clock divisor from 1 to 65535 to create 16x clock B The programmable serial interface includes 5 6 7 or 8 bit data Even odd no or stick parity generation and checking 1 1 1 2 or 2 stop bit generation Break generation detection Internal diagnostics Serial loopback transmit to receive Error simulation Receive line noise filter 15 2 REGISTERS 15 2 1 Direct Mapped Registers Note that because the lanSC400 and lanSC410 microcontrollers include only one serial port the on board UART can only be mapped to either COM1 or COMe at any time The SP CONFIG bit in the Parallel Serial
315. ch the data byte into the device The peripheral acknowledges the end of the cycle and indicates that it is ready for the next cycle to begin by asserting WAIT The host can then modify the address data on the data signals and change the state of the WRITE signal EPP Data Read To begin a data read cycle the host deasserts WRITE places the data signals in a high impedance state and then asserts DSTRB The peripheral responds by driving the data signals and deasserting WAIT to indicate that the data is valid When the host recognizes WAIT as inactive it reads the data from the data signals and deasserts DSTRB The peripheral places the data signals in the high impedance state acknowledges the end of the cycle and indicates that it is ready for the next cycle to begin by asserting WAIT The host can then drive the data signals and change the state of the WRITE signal Parallel Port Figure 14 5 EPP Read Cycle Ion SLCTIN Address Regi gister Access ASTRB n Data Register Access A SD7 SDO DBUFRDL 14 5 2 3 5 Time Out The EPP time out feature ensures that an external peripheral does not hangup the host A 10 us time out counter is implemented in case the peripheral asserts BUSY WAIT to insert wait states but then fails to deassert the signal back to High during an EPP data address read or write c
316. change the VCO input voltage level Since the VCO output frequency tracks the VCO input voltage the VCO output frequency is adjusted whenever Fr and Ff differ in phase or frequency The feedback divide ratio determines the frequency multiplication factor Frequency multiplication is 1 Feedback Divider Clock Control 6 5 For the Intermediate PLL the feedback divider is 1 45 therefore the frequency multiplication is 45 With an inputfrequency of 32 768 KHz the output frequency is 1 47456 MHz The input clock for the Low Speed PLL Fr originates at the Intermediate PLL output It is multiplied by 25 to generate the 36 864 MHz clock output Figure 6 5 Intermediate and Low Speed PLLs Block Diagram VCCA Up Reference Loop Filter Regeng mU Phase Charge Fr Detector Down Pump nu Feedback md 6 4 1 3 Table 6 3 6 6 Frequency es Ff Divider VCO Internal External Frequency Output Fo Graphics Dot Clock PLL The input clock to the Graphics Dot Clock PLL is the output clock 36 864 MHz of the Low Speed PLL divided by 16 The output frequency is programmable using three CSC indexed register bits PLLRATIO 2 0 in the range of 20 736 MHz to 36 864 MHz spaced 2 304 MHz apart Thesethree bits in the Pixel Clock Control Register graphics index 4Ch control the output frequency by selecti
317. cheable Window 0 Address Register CSC index 10h function 7 1 Non Cacheable Window 0 Address Attributes SMM Register CSC index 11h function 3 1 7 1 AMD Non Cacheable Window 1 Address Register CSC index 12h function 7 1 Non Cacheable Window 1 Address Attributes Register CSC index 13h function 7 1 Non Display Lines Register graphics index 34h function 20 4 usage 20 35 Normal Speed ROM mode See ROM Flash interface OE signal description 4 11 usage 9 4 19 17 Offset Register graphics index SEh function 20 5 usage 20 34 Overflow Register graphics index 36h function 20 5 Overlapping ISA Window Size Register CSC index E2h function 4 26 usage 4 29 7 7 Overlapping ISA Window Start Address Register CSC index E1h function 4 26 usage 4 29 7 7 P Paper End signal See PE signal parallel port Bidirectional mode 14 7 block diagram 14 3 data transfer Bidirectional and EPP modes figure 14 6 Data Register transactions table 14 6 PC AT Compatible mode figure 14 5 enhanced parallel port EPP mode 14 7 EPP read cycle figure 14 9 EPP write cycle figure 14 8 initialization 14 10 minimal system design 14 5 operating modes 14 7 operation 14 5 overview 14 1 PC AT Compatible mode 14 5 pin definitions by mode 14 4 power management 14 10 registers 14 1 signal definitions by mode table 14 4 signal descriptions 4 9 Index 13 Parallel P
318. ck period LVDD is asserted to complete the power down Graphics Controller 20 39 Table 20 16 Power Management the LCD Graphics Controller Graphics Controller Event CPU access to graphics controller Description Triggered by the falling edge of I O chip selects qualified with command Power Management Effect wakeup sey Programmable CPU access to DRAM within graphics controller memory range When the VID_DRAM bit in graphics index 4Fh is asserted rising edge and the CPU accesses DRAM within graphics memory space Programmable Graphics I O access 20 40 accesses to the graphics controller can cause an SMI through a trap This includes the following addresses 03B4h 03B5h 03B8h 03BAh or 03D4h 03D5h 03D8 03DCh Graphics Controller EN 21 TEST AND DEBUGGING 21 1 The lanSC400 and lanSC410 microcontrollers provide test and debug features compat ible with the standard Test Access Port TAP and Boundary Scan Architecture JTAG The test logic provided allows for testing to ensure that components function correctly that interconnections between various components are correct and that various components interact correctly on the printed circuit board The boundary scan test logic consists of a boundary scan register and support logic that are accessed through a test access port TAP The TAP provides a si
319. ck transfer mode 10 7 demand transfer mode 10 7 DMA cycle types 10 7 DMA initiator target combinations table 10 6 priority 10 7 single transfer mode 10 7 DMA Resource Channel Map Register A CSC index DBh function 10 3 usage 10 8 18 2 18 11 DMA Resource Channel Map Register B CSC index DCh function 10 3 usage 10 8 19 3 documentation ElanSC400 microcontroller documentation set xxiii ElanSC410 microcontroller documentation set xxiii FTP site iii literature ordering iii world wide web site iii DRAM Bank 0 Configuration Register CSC index 00h function 9 3 DRAM Bank 1 Configuration Register CSC index 01h function 9 3 DRAM Bank 2 Configuration Register CSC index 02h function 9 3 DRAM Bank 3 Configuration Register CSC index 03h function 9 3 DRAM Control Register CSC index 04h function 9 3 usage 9 5 9 12 DRAM controller bank configuration figure 9 4 bank configurations supported table 9 7 block diagram 9 4 initialization 9 13 boot process overview 9 13 detection algorithm 9 14 memory sizing 9 14 memory management 7 7 operation 9 5 power management 9 15 registers 9 3 system address decoding 9 5 CAS strobe assertion byte lane selection 9 5 byte lane mapping table 9 6 interleaved system address A to memory address MA mapping table 9 10 non interleaved system address A to memory address MA mapping table 9 8 RAS strobe assertion bank selection 9 5 system desi
320. cle Types Table 4 15 4 7 5 4 Device Sits on this Bus DMA Initiator Memory Device Sits on this Bus DMA Target ISA Command Strobes Generated Data Transfer Direction DMA Cycle Type ISA ISA to Memory DMA Write ISA PC Card to Memory DMA Write ISA DRAM to Memory DMA Write PC Card ISA I O to Memory DMA Write ISA ISA Memory to I O DMA Read PC Card ISA Memory to I O DMA Read ISA PC Card Memory to I O DMA Read ISA DRAM Memory to I O DMA Read 2 External Buffer Control Signals When the lanSC400 and lanSC410 microcontrollers are configured for a 32 bit DRAM interface or are in local bus mode it is necessary to use an external data bus buffer for the ISA bus External buffers are also useful when the bus is heavily loaded To provide buffering three optional signals DBUFOE DBUFRDL and DBUFRDH may be enabled Figure 4 9 illustrates how external 245 transceivers could be connected to the microcontroller using these signals 8 Bit ISA Bus with External Data Buffer Figure 4 9 Addresses SA23 SA0 SD15 SD8 245 BSD15 BSD8 Data DBUFRDH gt DIR DBUFOE OE BSD7 BSDO SD7 SDO Data control 245 ElanSC400 Microcontroller DBUFRDL gt DIR MEMR MEMW TOW DMA AEN TC PDACK1 PDACKO PDRQ1 PDRQO Interrupts PIRQ7 PIR
321. cles The VL bus on the lanSC400 and lanSC410 microcontrollers supports single and burst mode transfers to and from the VL bus target There are five types of normal VL bus cycles Memory read non burst Memory read burst i Memory write non burst read non burst write non burst The VL bus controller is tightly coupled with the internal memory controller and address decode logic The microcontroller drives the current CPU address onto the VL bus and asserts VL ADS when the cycle is not internally decoded as a DRAM ROM MMU hit or access to an internal core or register VL LDEV is then sampled at the next rising edge of the CPU clock VL BLAST is valid at the rising edge of VL LCLK that samples VL ADS asserted Bus transfers are terminated by VL_LRDY and VL LBRDY If no VL bus device asserts VL LDEV the cycle is then driven to the ISA bus VL bus accesses are not cached DRAM ROM and cycles that result in an MMS windows access are of higher priority than VL bus accesses Special Bus Cycles The special bus cycles listed in Table 4 19 may also be visible on VL bus accesses Note Technically these special cycles are not considered VL bus accesses on the lanSC400 and ElanSC410 microcontrollers VL ADS will not be asserted for these special cycles It might be difficult for a system to determine that a special cycle has occurred particularly when the CPU is in a Hold state and its output states for th
322. configuration shown in Figure 4 3 byte lanes V1 and VO form the DRAM data bus byte lanes 015 08 and D7 DO respectively Bytes lanes V3 and V2 form the SD data bus byte lanes SD15 SD8 and SD7 SDO respectively No external buffers or transceivers are requiredto provide isolation between local and system data buses in this mode The internal graphics controller on the ElanSC400 microcontroller may be enabled or disabled The VL bus is always disabled in this mode The ROM and PC targets reside on the SD bus and may be programmed to be 8 or 16 bits wide The matrix keyboard may be enabled or disabled in this mode Note that the RAS and CAS signals for DRAM banks 2 and 3 are traded for keyboard row signals Configuration B 32 Bit DRAM Bus and 16 Bit SD Bus This configuration Figure 4 4 differs from Configuration A in that either the DRAM interface is programmed to be 32 bits wide and or the VL bus is enabled This configuration uses byte lanes V3 and V2 for the upper word of the DRAM bus and or the VL bus The SD system bus is formed by buffering byte lanes V3 and V2 through external transceivers to create SD15 SD8 and SD7 SDO These external transceivers might be required to reduce SD bus loading on the high word of the VL bus 32 bit DRAM bus DBUFOE is the enable signal for these two transceivers while DBUFRDL and DBUFHRDH are the direction control signals for the low and high bytes of the SD bus The internal graphics controller on the
323. controllers The legacy function of these bits was to enable and disable ISA bus I O channel check or parity error Non Maskable Interrupt NMI sources Bits 5 and 4 of this register are read only status bits that return the status of the SPKR output pin state and the DRAM refresh activity respectively The DRAM refresh indicator bit toggles once each time the DRAM refresh cycle occurs Although this rate was nominally 15 087 us on a PC AT the refresh rate can be varied on the lanSC400 and lanSC410 microcontrollers if PIT Channel 1 is used as the DRAM refresh signal By default the system 32 768 KHz clock is used for DRAM refresh The normal PC AT functions performed by bits 7 6 i e IOCHCK and Error indication are not supported on the lanSC400 and lanSC41 0 microcontrollers These bits always read back a value of 0 NMI Control The power management unit keyboard scan timer 8042 emulation logic and the PC Card controller are the only possible sources for the generation of an NMI to the internal CPU A master enable function inhibits any NMIs from reaching the CPU regardless of the state of the individual source enables NMIs can be enabled by writing a 0 to the most significant bit at I O address 0070h Port 0070h is a write only register and bits 0 6 function as the RTC index address port System Control Port A Register Port 0092h Bit 0 of this register is used for fast CPU reset A low to high transition
324. controllers although normal software emulation can be implemented easily The lanSC400 and ElanSC410 microcontrollers use the industry standard 486 instruction set Software written for the 486 microprocessor and previous members of the x86 architecture family can run on the ElanSC400 and ElanSC410 microcontrollers Power Management Chapter 5 Power management the lanSC400 and ElanSC410 microcontrollers includes dedicated power management unit and additional power management features built into each integrated peripheral The lanSC400 and lanSC410 microcontrollers can use the following techniques to conserve power Slow down clocks when the system is not in active use B Shut off clocks to parts of the chip that are idle Switch off power to parts of the system that are idle Automatically reduce power use when batteries are low The power management unit PMU controls stopping and changing clocks SMI generation timers activities and battery level monitoring It provides Hyper Speed High Speed Low Speed Temporary Low Speed Standby Suspend and Critical Suspend modes Dynamically adjusted clock speeds for power reduction Programmable activity and wake up monitoring General purpose I O pins to control external devices and external power management Battery low and AC power monitoring SMI NMI synchronization and generation Clock Generation Chapter 6 The lanSC400 and ElanSC410 micr
325. cribes the PC AT compatible programmable interrupt controller PIC Chapter 12 describes the PC AT compatible programmable interval timer PIT Chapter 13 describes the PC AT compatible real time clock RTC Chapter 14 covers the parallel port including PC AT Compatible mode Bidirectional mode and Enhanced Parallel Port EPP mode Chapter 15 describes the serial port UART Chapter 16 describes the keyboard interfaces available on the microcontroller including the matrix scan keyboard interface System Control Processor SCP emulation and the XT interface Chapter 17 covers the general purpose input output signals and the programmable chip selects available on the microcontroller Chapter 18 describes the infrared port and using DMA for high speed infrared transfers Chapter 19 describes the integrated PC Card controller available on the lanSC400 microcontroller Chapter 20 describes the integrated LCD graphics controller available on the lanSC400 microcontroller Chapter 21 covers the test and debugging features of the microcontroller including the boundary scan interface test access port operation and scan paths Appendix A describes multiplexed pin configuration control It includes a table listing which signals are traded for others and how each multiplexed signal is enabled Appendix B covers pin termination and includes a table with control bits and affected pins Introduction xxiii
326. cription Table continued Signal Type Description Clocks CLK IO y o Clock Input Output can be used as an input to drive the integrated 8254 timer with a 1 19318 mHz clock signal from an external source or it can be used as an output to bring out certain internal clock sources to drive external devices INT LF LS A Loop Filters are used to connect external RC loop filters required by the internal PLLs LF VID LF HS LF VID is not supported on the ElanSC410 microcontroller 32KXTAL1 32 768 KHz Crystal Interface Signals are used for the 32 768 KHz crystal This is the main 32KXTAL2 clock source for the chip and is used to drive the internal Phase Locked Loops PLLs that generate all other clock frequencies needed in the system Parallel Port Note The names in parentheses in this section are those used in EPP mode ACK INTR Printer Acknowledge In standard mode this signal is driven by the parallel port device with the state of the printer acknowledge signal In EPP Mode this signal is used to indicate to the chip that the parallel port device has generated an interrupt request AFDT DSTRB Auto Line Feed Detect In standard mode this signal is driven by the chip indicating to the parallel port device to insert a line feed at the end of every line In EPP mode this signal is driven active by the chip during reads or writes to the EPP data registers BUSY WAIT P
327. d See keyboard interfaces Matrix Scanned Keyboard Column Output signals See KBD COL7 KBD COLO signals Matrix Scanned Keyboard Row Input signals See KBD ROW14 KBD ROWO signals Maximum Scan Line Register graphics index 40h function 20 5 usage 20 10 20 18 20 20 20 32 20 33 MCEH signal description 4 11 usage 19 19 MCEH B signal description 4 11 MCEL signal description 4 11 usage 19 19 12 B signal description 4 11 MCS16 signal control 4 26 description 4 6 MDA mode See graphics controller MDA HGA Data Port Port O3B5h function 20 2 MDA HGA Index Register Port 03B4h function 20 2 MDA HGA Mode Control Register Port 03B8h function 20 3 MDA HGA Status Register Port O3BAh function 20 3 Memory Address signals See MA12 MAO signals Memory Chip Select signal See MCS16 signal memory management address decoding and aliasing 7 3 internal address bus size 7 3 ISA bus addressing 7 4 special handling for A20 7 3 top of memory CPU execution 7 3 address translation example figure 7 6 caching 7 11 memory mapping 7 11 memory mapping system example figure 7 5 multiple memory spaces 7 4 non translated memory management 7 6 DRAM memory management 7 7 ROMO memory management 7 6 overview 7 1 registers 7 1 ROMCS2 operation 7 11 system considerations 7 11 2 7 Volt operation 7 11 System Management Mode SMM caching 7 12 translated memory management 7 8 MMS window
328. d B page 3 198 Register Index 1 10 3 BLOCK DIAGRAM A block diagram of the DMA controller block on the ElanSC400 and lanSC410 microcontrollers is shown in Figure 10 1 The DMA system supports seven DMA channels Two DMA controllers are used the slave controller supports four 8 bit channels and the master controller supports three 16 bit channels Channels 0 3 must be programmed as 8 bit channels and Channels 5 7 must DMA Controller 10 3 be programmed as 16 bit channels Channel 4 must be programmed to Cascade mode and must be unmasked if any of the 8 bit channels 0 3 are to be used The external DMA ISA signals are shared with other functions PDRQO and PDACKO are shared with GPIO CS12 and GPIO CS11 respectively AEN and TC and shared with GPIO CS10 and GPIO CSS respectively PDRQ1 and are shared with KBD ROW8 ROWT respectively On the ElanSC400 microcontroller PC Card DMA requests can be programmed to appear on either the WP x pins or the BVD2 x pins Figure 10 1 DMA Controller Block Diagram lanSC400 Microcontroller PDR p gt PDACKO gt PDACK1 P B B REG B PC Card DMA PC Card DMA Requests gt Acknowledge Infrared DMA Request Infrared DMA Acknowledge Signals Infrared Read Write Channel m IOW Mapping Initiator gt TC Casc
329. d DMA has completed The PC Card controller can operate at up to 33 MHz During power saving modes the clock to the controller can be dropped down as low as DC Because PC Card cycles are measured in terms of the number of clock cycles slowing down the clock to the controller slows down PC Card cycles because the number of clocks counted per cycle remains constant Operation of the PC Card controller is affected by the power management functions shown in Table 19 19 Table 19 19 Power Management in the PC Card Controller Power Management Effect PC Card Controller Event Description Wake Up Activity PC Card Ring Indicate Triggered by a falling edge on the signal Programmable signal when the PC Card controller is programmed PC Card index or 43h for a ring indicate signal The PC Card controller uses the BVD1 x pins for ring indicate signals PC Card Detect Triggered by either PC Card Detect signal signals rising or falling edge PC Card IRQ signals Triggered by either PC Card Interrupt Request signal rising edge only active if the IRQ is enabled in the interrupt controller PC Card Status Triggered by either PC Card Status Change Change IRQs Interrupt Request signal rising edge only active if the IRQ is enabled in the interrupt controller CPU access to PC Triggered by falling edge of address decode Programmable Card Socket A and qualified with command memory CPU access to PC Triggered by f
330. d Write OFFEOh ESP Register Read Write OFFDCh EBX Register Read Write OFFD8h EDX Register Read Write OFFD4h ECX Register Read Write OFFDOh EAX Register Read Write OFFCCh DR6 Register Read only OFFC8h DR7 Register Read only TR lower two bytes Read only OFFCOh LDTR lower two bytes Read only OFFBCh GS Selector lower two bytes Read only OFFB8h FS Selector lower two bytes Read only OFFB4h DS Selector lower two bytes Read only OFFBOh SS Selector lower two bytes Read only OFFACh CS Selector lower two bytes Read only OFFA8h ES Selector lower two bytes Read only OFFO8h Internal Registers No access OFFO6h Trap Address Read only OFFO4h Trapped bit 1 and Read Write bit 0 Read only OFFO2h Halt Auto Restart Bit 0 1 Read Write OFFOOh I O Trap Restart in lower byte if FFh Read Write OFEFCh SMM Revision Identifier Read Write OFEF8h SMBASE Read Write OFEOOh Internal Registers Am486 CPU No access 3 7 Table 3 4 3 5 5 3 8 SMM Initial Register Values Register or Feature SMM Initial State EAX EBX ECX EDX Unmodified contain values from interrupted program ESI EDI EBP ESP GDTR LDTR IDT
331. d an IrDA device can be designed into the same system the ElanSC400 and ElanSC410 microcontrollers support real time switching between the two ports Serial Port UART 15 3 Figure 15 1 Serial Port Block Diagram Modem Control SIROUT SIRIN Infrared Baud Clock Port 1 8432 MHz Select Device and Mode ElanSC400 Microcontroller 15 4 OPERATION The UART converts serial data received on the serial input line SIN into parallel data that can be processed by the microcontroller The UART also converts parallel data into serial data for transmission off the chip on the serial output line SOUT Data can be transmitted and received at the same time 15 4 1 Baud Rate Generation The serial data can be transferred from or to the UART on the microcontroller at baud rates up to 115 200 for a transfer rate of 115 Kbit s The transmit and receive sections can be operated at different baud rates The UART clock on the ElanSC400 and ElanSC410 microcontrollers runs at 1 8432 MHz To generate the baud rate of the transfer the UART clock is divided by a divisor value chosen by the programmer The UART s baud rate generator automatically calculates the baud rate from the divisor value programmed into the two COMx Baud Rate Divisor Registers MSB and LSB These registers are read at initialization to set the baud rate for the transfer Table 15 2 lists some typical baud rates and
332. d banks must be Bank 2 or Bank 3 to force proper output of the MA12 signal DRAM Controller 9 7 Table 9 4 Non Interleaved System Address to Memory Address MA Mapping CSC Index 00 03h DRAM Non Interleaved MA Mapping Bit Values Configuration System Address to MA Mapping for Rows Columns Bytes Banks x Rows x Cols x Bits PageSize Refresh Cycles 0 5 MB 1x9x9x16 1 Kbyte 512 N A 2 MB 1x10x10x16 2 Kbyte 1024 4 MB 1x11x10x16 2 Kbyte 2048 8 MB 1x11x11x16 4 Kbyte 2048 16 MB 1x12x11x16 4 Kbyte 4096 32 MB 1x12x12x16 8 Kbyte 4096 N A 1 MB 1x9x9x32 2 Kbyte 512 N A 4 MB 1x10x10x32 4 Kbyte 1024 8 MB 1x11x10x32 4 Kbyte 2048 16 MB 1x11x11x32 8 Kbyte 2048 32 MB 1x12x11x32 8 Kbyte 4096 64 MB 1x12x12x32 16 Kbyte 4096 N A 9 8 DRAM Controller Table 9 4 Non Interleaved System Address A to Memory Address MA Mapping cont CSC Index 00 03h DRAM Non Interleaved MA Mapping Bit Values Configuration System Address to MA Mapping for Rows Columns Bytes Banks x Rows x Cols x Bits PageSize Refresh N A 1 MB 1x10x9x16 1 Kbyte 1024 2 MB 1x12x8x16 0 5 Kbyte 4096 4 MB 1x12x9x16 1 Kbyte 4096 8 MB 1x12x10x16 2 Kbyte 4096 16 MB 1x13x10x16 2 Kbyte 8192 32 MB 1x13x11x16 4 Kbyte 8192 N A N A 2 MB
333. d in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Programmable Interrupt Controller Register Summary Register Description in Register Set Manual Programmable Interrupt Controller VO Address Function Keyword Chip Setup and Control CSC Index Registers Keyboard Configuration Register A 22h 23h Index COh XT keyboard IRQ1 control SCP mouse emulation IRQ12 control page 3 146 Interrupt Configuration Register A 22h 23h Index D4h PIRQ1 PIRQO mapping to IRQ15 IRQ1 page 3 170 Interrupt Configuration Register B 22h 23h Index D5h PIRQ3 PIRQ2 mapping to IRQ15 IRQ1 page 3 171 Interrupt Configuration Register C 22h 23h Index D6h PIRQ5 PIRQA4 mapping to IRQ15 IRQ1 page 3 172 Interrupt Configuration Register D 22h 23h Index D7h PIRQ7 PIRQ6 mapping to IRQ15 IRQ1 page 3 173 Interrupt Configuration Register E 22h 23h Index D8h Mapping of UART infrared port parallel port and cursor high low address register IRQs IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 page 3 174 PC Card Index Registers Interrupt and General Control Register S3EOh 3E1h Index Socket and 43h Socket 8 IRQ mapping for RDY X page 6 11 Card Status Change Interrupt Configuration Register 11 3 3E0h 3E1h Index 05h A and 45h B BLOCK DIAGRAM A block diagram of the PIC on the lanSC400 ElanSC410 microcontroll
334. d increased performance over both the PC AT Compatible and Bidirectional modes 14 2 REGISTERS The parallel port interface is controlled primarily by software A summary listing of the chip setup and control CSC registers used to control the parallel port interface is shown in Table 14 1 Complete register descriptions can be found in the Elan SC400 Microcontroller Register Set Reference Manual order 21032 14 2 1 Direct Mapped Registers The parallel port interface can be mapped to one of the two I O locations LPT1 from ports 0378 037Fh or LPT2 from ports 0278 027Fh The following direct mapped registers are available for either LPT1 or LPT2 B Parallel Port Control Register Port 037Ah or 027Ah This register sets the various signals that control the data transfer to or from the parallel port peripheral device These control signals are SLCTIN INIT STRB and AFDT The parallel port s internal interrupt request is enabled or cleared in this register Bidirectional data direction is controlled through bit 5 of this register Parallel Port 14 1 Parallel Port Status Register Port 0379h 02791 115 register keeps track the parallel port peripheral device status via the status input signals BUSY ACK SLCT ERROR and PE The fields of this register vary according to mode of operation B Parallel Port Data Registers Ports 0378h 037C 037Fh or 0278h 027C 027Fh These internal registers i
335. d of CPU clock CPU Clock Auto Slowdown 22h 23h Fast clock duration in High Speed mode slow page 3 88 Register Index 81h clock duration in Low Speed mode auto slowdown Clock Control Register 22h 23h PLL enable restart delay time 32 KHz clock page 3 90 Index 82h state DMA clock frequency CLK IO Pin Output Clock Select 22h 23h pin clock source page 3 91 Register Index 83h PC Card Mode and DMA Control 22h 23h Clock speed for PC Card controller page 3 198 Register Index Fih Graphics Index Registers Pixel Clock Control Register 3x4h 3x5h Graphics dot clock base frequency and divide page 5 36 Index 4Ch select 6 3 BLOCK DIAGRAM Figure 6 1 shows a high level block diagram of the clock sources on the lanSC400 and ElanSC410 microcontrollers and how the clocks are generated is the definitive information source for what clock speeds are supported in each peripheral core Clock Control 6 1 Figure 6 1 Clock Source Block Diagram 32 768 KHz 32 768 KHz il 32 768 KHz Oscillator RTC DRAM 1 4746 MHz _Enable Intermediate PLL Controller and PMU Enable Low Speed PLL 36 864 MHz EMS Enable 20 736 MH Graphics Dot z Graphics 36 864 MH Clock PLL 2 Controller Dot Clock
336. d on the lanSC410 microcontroller The graphics controller includes the following features Supports multiple panel resolutions Provides internal unified memory architecture UMA with optional write through caching of graphics buffers Stores frame and font buffer data in system DRAM eliminates extra memory chip Provides software compatibility with Color Graphics Adapter CGA Monochrome Display Adapter MDA and Hercules Graphics Adapter HGA text and graphics Supports single scan or dual scan monochrome LCD panels with 4 or 8 bit data interface B Typical panels supported include 640x200 640x240 640x480 480x320 480x240 480x128 320x200 320x240 Other resolutions may be supported Supports single scan color STN panels with 8 bit interface same resolutions as monochrome mode Internal local bus interface provides high performance Logical screen may be larger than physical window Supports panning and scrolling Supports horizontal dot doubling and vertical line doubling The following MDA CGA compatible text mode features are supported 40 64 or 80 columns with characters 16 10 or 8 pixels wide Variable height characters up to 32 lines Variable width characters 8 10 or 16 pixels MDA Monochrome or CGA 4 gray shades 16 gray shades or 16 colors 16 Kbyte downloadable font area relocatable on 16 Kbyte boundaries within lower 16 Mbytes of system DRAM may be write pro
337. d some IBF Mouse Command Data are set and cleared automatically when accesses occur Input Buffer is written or read Output Buffer is written or read etc IRQ1 As part of the SCP support IRQ1 will be generated if itis enabled when the flag is set because of a write to CSC index C3h IRQ12 As part of the SCP support IRQ12 will be generated if it is enabled when the OBF flag is set because of a write to the Mouse Output Buffer Write Register CSC index C4h SCP GATEA20 and Reset CPU Command Emulation The lanSC400 and ElanSC410 microcontrollers do not support an 200 or RESCPU input pin These inputs are typically driven by the external SCP in response to a command request that is issued by the main CPU In the implementation on the lanSC400 and ElanSC410 microcontrollers the 200 and RESET CPU command sequences detected by internal logic and the appropriate action is taken The A20GATE command is detected when the CPU issues the standard command write to Port 0064h of D1h followed by a data write to Port 0060h Bit 1 of the write to Port 0060h drives the A20 control logic A value of 1 allows the CPU A20 signal to propagate to the core logic while a value of 0 allows the CPU A20 signal to be driven Low as long as no other 2 control sources are forcing the CPU A20 signal to propagate Keyboard Interfaces 16 9 16 3 3 16 3 3 1 16 3 3 2 16
338. d stop toggling Entering Suspend Mode The system goes to Suspend mode when any of the following occurs The Standby mode timer times out Programmed directly with the PMU Force Mode Register Critical Suspend mode is unlocked by BLZ and or BLT and BL2 B The SUS RES signal is enabled and changes Leaving Suspend Mode The system leaves Suspend mode when any of the following occurs The Suspend mode timer times out SMI NMI is enabled it goes to Temporary Low Speed mode All the PLLs except the CPU core PLL must be started back up to service the XMI in Temporary Low Speed mode The timing sequence is shown in the lan SC400 and ElanSC410 Microcontrollers Data Sheet order 21028 If enabled as a wake up it goes to High or Low Speed mode based on either BLZ or BL1 f both the SMI NMI and wake up are enabled it goes to High or Low Speed mode before servicing the SMI NMI as opposed to servicing the SMI in Temporary Low Speed mode B 812 is enabled and asserted Goes to Critical Suspend mode Power Management 5 15 5 4 6 5 4 6 1 5 4 6 2 5 4 6 3 5 16 A wake up source is detected active or the SUS RES signal toggles f enabled forces the system to High Speed or Low Speed mode The PLLs have to be started back up Critical Suspend Mode Critical Suspend mode is used when a battery dead indication comes in on BL2 and the microcontroller must quick
339. d up some DRAM accesses particularly graphics controller FIFO fills and CPU burst cycles After a row address is driven out on MA12 MAO with a RAS strobe the DRAM controller may keep issuing new column addresses on MA12 MAO with CAS strobes until either a new page is required a refresh cycle is required or the DRAM s parameter RAS time out value would be violated The tras value may be set to either 10 or 100 us via bit 5 of the DRAM Refresh Control Register CSC index 05h MWE Generation The controller asserts MWE one cycle before asserting any CAS strobes so that the DRAMs can distinguish write from read cycles this assertion of MWE before CAS is referred to as an early write cycle The DRAMs will latch the written data on the falling edge of CAS assuming that their twos parameter is not violated For systems with heavily loaded MWE lines the DRAM Control Register CSC index 04h 6 can be set to delay CAS after MWE by an extra clock period to ensure that the tcs parameter is met This delay is also applied to reads to guarantee that MWE is inactive before CAS strobes active to meet the DRAMs ihcs parameter For EDO DRAMSs after the completion of a read or multiple reads in the case of a graphics controller FIFO fill or a CPU burst MWE will be pulsed low with all CAS strobes deasserted for one memory clock to disable the DRAM outputs CAS Pulse Width CSC index 04114 determines the minimum value of the
340. data portion of memory Even addresses contain character bytes the ASCII code for the character to be displayed at that screen location that are used by the graphics controller to point to the correct font in memory to display that character refer to Section 20 4 5 3 for more information on fonts Odd addresses contain attribute bytes that allow attributes such as blinking background foreground colors intensity and underlining to be manipulated on individual characters Each even odd combination of bytes represents one character on the screen For example in CGA text modes memory address 00B8000h is the character byte for the upper left character on the display 00B8001h is the attribute for that character address 00B8002h is the character byte for the next character to the right 00B8003h is its attribute etc Table 20 4 illustrates the memory mapping for page 0 of the CGA 80x25 text mode Note that one page or one screen of information takes up 4 Kbytes of memory and there are 16 Kbytes of memory available for display data Therefore memory will hold four pages or screens of data at one time Selection between pages can be performed using graphics index OCh and ODh the 6845 compatible Start Address High and Low registers The 40x25 text mode only functions in the same manner except that eight pages are provided because each page uses only 2 Kbytes of memory Text Mode Memory Display Data CGA 80x25 Display
341. de In color text modes without contrast enhancement enabled the R and G bits of the color value are used to select the shading value with R the most significant and G the least significant When contrast enhancement is enabled the 16x4 grayscale palette becomes a 16x2 palette allowing for full remapping of the grayscales In monochrome text modes the logical OR of the RGB bits turns on a pixel If the intensity bit is off the on and off pixels of a character are mapped to shades 3 and 0 respectively If the intensity bit is on the on and off pixels are mapped to shades 2 and 1 When contrast enhancement is enabled the 16x4 grayscale palette becomes a 16x2 palette allowing for full remapping of the grayscales In linear packed pixel modes 4 or 16 color gray shading may be used in 1 or 2 BPP modes The 16x2 grayscales palette should be enabled in this case allowing for full remapping of the grayscales 16 color gray shading should be selected in 4 BPP flat mapped mode Color STN Mode In color STN mode eight normal and eight intensified colors are supported under the CGA RGBI format The colors are normal if the I intensity bit is set to 0 For a normal color each of the R G and B signals is driven with a 2 3 duty cycle waveform when on For an intensified color each of the R G and B bits is driven with a constant one duty cycle when on If monochrome mapping is selected the 4 or 16 grayscale Frame Rate Control FRC is
342. de paradigm On the lanSC400 and ElanSC410 microcontrollers this support includes providing two timing sets for the device one slower set for the first access of the burst or non burst device and another faster set of timings for the remainder of the burst The first type of wait state specified in the WAIT NBRSTx bit field is always used in the first access for either burst or non burst supported device It starts at the assertion of the chip select or at the transition of 5 whichever occurs later The second type of wait state specified in the WAIT BRSTx bit field is used only for any subsequent burst read accesses to a burst mode ROM device It starts at the transition of SAS3 SAO The burst address valid duration depends on which wait state is used If the wait state is set to 0 then the minimum address duration is 30 ns one bus clock cycle If wait states are added via the deassertion of IOCHRDY the data setup time to IOCHRDY assertion is 0 ns minimum System firmware must set up the wait state usage via the ROMCSx WS SLCT bits These bits are located in the ROMCSx Configuration Register A CSC index 23h 25h and 27h for ROMCSO ROMCS 1 and ROMCS2 respectively If ROMCSx WS SLCT 0 then it will be assumed that a burst mode capable ROM is not installed in the system and the WAIT NBRSTx timings will always be used for all ROM accesses If ROMCSx WS SLCT 1 then it will be assumed that a burst mode capable R
343. default is disabled This signal is also used as a keyboard row input Programmable to cause Suspend Resume both or neither Programmable to Suspend on rising or falling edge Resume on rising or falling edge or toggle mode Suspend if operating Resume if Suspended on rising or falling edge The SUS RES pin has a 15 ms debounce time The waveforms below describe the different possible actions of the SUS RES signal depending on how it is programmed Resume 9Per Suspend SES OR X Suspend _ Sus Resume oper OR X oper Resume oper X OR sus Suspend SUS X GR Resume Oper __ N X X OR x Suspend SUS L oper or sus OR sus or oper toggle sus or oper OR oper or sus toggle _SUS or oper oper or sus Notes Oper The PMU is operating in Hyper High Low Standby Temporary Low Speed mode Sus The PMU is in Suspend mode X The PMU is in any mode Suspend The SUS RES signal forces the PMU to Suspend mode Resume The SUS RES signal resumes the system from Suspend mode Toggle The SUS RES signal forces the PMU to Suspend mode if the PMU is operating or resume the system from Suspend mode Power Management 5 21 Table 5 2 Wake Up Sources PMU Wake Up Sources continued Description Suspend mode timer time out External DMA request Suspend mode timer time out can cause a wake up DMA request pin either PDRQO or PDRQ1 rising edge triggered Only acti
344. dentification Register 21 2 Logical Structure of Boundary Scan Register 21 3 TAP Controller State 21 5 Table of Contents xvii xviii LIST OF TABLES Table 2 1 Internal Port Address 2 2 Table 2 2 Indexed Register 2 3 Table 2 3 Chip Setup and Control CSC Indexed Register 2 6 Table 3 1 CPU Control Register Summary 3 1 Table 3 2 Cache Configuration lt 3 3 Table 3 3 SRAM State Save 3 7 Table 3 4 SMM Initial Register 3 8 Table 3 5 CPUID Instruction lt 3 19 Table 4 1 Typos ol RR RC ERE ETE PUE ERROR RE ER 4 2 Table 4 2 Internal Core States Immediately Following Power On 4 3 Table 4 3 CPU ID rn 4 4 Table 4 4 Signal Description Table 4 5 Table 4 5 Pin Strap Bus Buffer 5 4 16 Table 4 6 CFGO and CFG1 4 16 Table 4 7 CFG2
345. der of ROMCSO and any portion of ROMCS1 or ROMCS2 spaces an MMS window is required See Chapter 7 for more detail on using MMS windows ROMCSO must be connected to the boot ROM device which is why the direct mapped accesses to the BFF0000 3FFFFFFh region are included ROM Flash Interface 8 3 8 4 2 8 4 The 00C0000 00FFFFFh region is broken down into four segments each having independent controls Each segment is 64 Kbytes wide 00C0000 00CFFFFh i 00D0000 00DFFFFh 00E0000 00EFFFFh iM 00F0000 00FFFFFh Each of these four segments has individual controls for enable and also for cacheability and write protection of linear accesses The direct mapped accessibility is provided for these segments in order to support the standard PC AT ROM memory map compatibility with minimum effort on the part of the system designer software engineer Accesses to any segment that is not enabled for ROMCSO linear decode will go to the external ISA or VL bus Accesses to any segments that have been enabled for linear ROMCSO decode may be redirected to DRAM for use in shadowing ROM BIOS This is commonly referred to as shadowing support or simply shadowing On the lanSC400 and ElanSC410 microcontrollers the shadowing control operates on an all or nothing basis If shadowing is enabled then accesses to all of the above segments that have been enabled for linear ROMCSO decode will be redirected to DRAM Note that neither PC Card win
346. dge of the gate input The output remains High until the count has expired The output goes Low for one clock cycle and goes High again E After writing the control word and the initial count the counter is loaded at the next clock pulse after the trigger The strobe pulse occurs N 1 clock pulses after the Low to High transition trigger on the gate input This count sequence is retriggerable Timer Configuration Configuring Timer Channel 0 Timer Channel 0 is used for generating interrupt requests Its output is hardwired internally to drive IRQO of the interrupt controller For DOS compatible systems system BIOS usually programs the PIT 1 Channel 0 Count Register Port 0040h to a value of FFFFh DOS relies on this periodic interrupt in order to keep accurate time of day Because the timer clock source is 1 1892 MHz in the ElanSC400 and ElanSC410 microcontrollers the IRQO is generated every 55 11 ms Historically the timer clock source has been 1 19318 MHz This translates into an IRQO generation rate of 54 93 ms This IRQO generation rate difference causes the time keeping function of DOS to be inaccurate There are two possible ways to address this issue One method involves modifying Port 0040h via the system BIOS The second method involves driving the timer from an external clock source Modifying PIT 1 Channel 0 Count Register Port 0040h If the system BIOS programs Port 0040h to a value of FF23h the desired IRQO gen
347. dows nor MMS windows C F may be located in any segment that has been enabled for ROMCSO linear decode regardless of whether or not shadowing has been enabled Doing so will result in unexpected system operation and must be avoided Any segment that is not enabled for ROMCSO linear decode may be overlaid with a PC Card or MMS C F window The ROMCSO linear decode may be redirected to PC Card Socket A to support field upgrades of firmware or special development environments This redirection can be done using either pin strapping as explained below or software manipulation of CSC registers In addition ROMCS 1 can also be redirected to PC Card Socket A under software control only The ROM controller supports enhanced access times for burst mode ROM devices These devices support faster access speeds for certain transfers to improve ROM interface performance as described below Data Bus Usage This section provides a brief overview of the data bus usage by the ROM controller because it is not intuitively obvious This section is included for the benefit of those who are trying to connect a logic analyzer to the microcontrollers ROM interface The lanSC400 and ElanSC410 microcontrollers are highly configurable but system level resources must be shared for several configurations The 32 bit data bus on the lanSC400 and lanSC410 microcontrollers is broken down into four byte lanes V3 VO These byte lanes carry data to and from the CPU from diff
348. driven with the programmed frequency for all cycles The CPU clock does not speed up to 8 MHz for ISA PC Card or ROM cycles They happen at the programmed CPU clock speed For example if the CPU clock is programmed to 2 MHz the ISA cycles will be approximately 4 times as long as normal because the ISA clock is also 2 MHz Entering Low Speed Mode The system goes to Low Speed mode when any one of the following occurs The High Speed mode timer times out Programmed directly with the PMU Force Mode Register B BLO goes Low programmable option primary activity happens and the High Speed mode is disabled via BL2 or Resume or wake up from Suspend mode when the High Speed mode is disabled When a secondary activity occurs in Low Speed mode the Timer may be reset programming option modes are not changed Leaving Low Speed mode The system leaves Low Speed mode when any one of the following happens B The Low Speed mode timer times out Drops to Standby mode Programmed directly out with the PMU Force Mode Register go to any other mode A primary activity is detected and High Speed mode is enabled Goes back up to High Speed mode 812 goes Low programmable option using CSC index 70 711 Cause a mode change to Critical Suspend mode if enabled and ACIN is not active The SUS RES signal toggles If enabled forces the system to Suspend mode Power Management 5 13
349. e Check the stepping that it has write back cache and that it has no FPU EAX should already contain a 1 from previous CPUID instruction emit OxOF CPUID emit 2 QI bx bx dx jnz NotMine Jump if FPU or other feature present mov bx ax and bx OFh xor ax cmp bx 4 Check for stepping 4 or greater of core jb NotMine cmp ax 04A0h Check features jnz NotMine Passed all the tests Must be an ElanSC400 microcontroller or derivative Clean up and return TRUE Int6 OldInt6 return TRUE Am4869 CPU 3 21 3 22 Am486 CPU ESTA 4 4 1 4 1 1 SYSTEM INTERFACES INITIALIZATION The microcontroller is in an indeterminate state when power is first applied Power on reset places the microcontroller into a defined state as described in this section Other types of reset defined below are used to control the state of specific parts of the microcontroller Types of Reset The ElanSC400 and lanSC410 microcontrollers employ five different types of reset which are summarized in Table 4 1 Power On Reset This master hardware is generated by the RESET input RESET is an asynchronous input equivalent to POWERGOOD in the PC AT system architecture B RTC Only Reset This internal reset uses the BBATSEN signal to sense the Real Time Clock s back up battery voltage during a power on reset CPU Reset Also called soft reset
350. e These user RAM bytes provide low power CMOS battery backed storage and extend the RAM available to the program Real Time Clock Register Summary Description in Register Set Manual Address Real Time Clock Function Keyword Chip Setup and Control CSC Index Registers Wake Up Source Enable 22h 23h Wake up source enable RTC alarm IRQ8 page 3 59 Register A Index 52h Wake Up Source Status 22h 23h Wake up source status RTC alarm page 3 63 Register A Index 56h Miscellaneous SMI NMI Enable 22h 23h SMI NMI enable RTC alarm IRQ8 page 3 94 Index 90h Miscellaneous SMI NMI Status 22h 23h SMI NMI status RTC alarm page 3 99 Register A Index 94h SMI NMI Select Register 22h 23h SMI or NMI selection RTC alarm page 3 104 Index 98h Internal I O Device Disable Echo 22h 23h RTC enable page 3 164 Z Bus Configuration Register Index DOh RTC and Configuration RAM Index Registers RTC Current Second Register 70h 71h Seconds page 4 5 Index 00h RTC Alarm Second Register 70h 71h Seconds alarm page 4 6 Index 01h RTC Current Minute Register 70h 71h Minutes page 4 7 Index 02h RTC Alarm Minute Register 70h 71h Minutes alarm page 4 8 Index RTC Current Hour Register 70h 71h Hours 12 and 24 hour mode page 4 9 Index 04h 13 2 Real Time Clock AMD Table 13 1 Real Time Clock Register Summary continued Description Register Address Real Time Clock Function
351. e 4 11 shows the external signals used for all permitted CPU initiated data transfers Table 4 11 Byte Lanes by Access Target and Type Tarai Access Byte 3 Byte 2 Byte 1 Byte 0 9 2 V1 32 Bit DRAM or VL Bus double word Read Write 031 024 SD15 SD8 D23 D16 507 500 015 08 07 00 16 Bit DRAM Read Write D15 D8 D7 DO D15 D8 07 00 32 Bit ROM Flash Read Write 031 024 5015 9508 023 016 SD7 SDO D15 D8 D7 DO 16 Bit ROM Flash PC Read Write 015 08 07 00 SD15 SD8 SD7 SDO Card or ISA Slave 8 Bit ROM Flash PC Card or ISA Slave Parallel Port Read Write SD7 SDO SD7 SDO SD7 SDO SD7 SDO Read Write 07 00 SD7 SDO SD7 SDO SD7 SDO 4 20 System Interfaces Figure 4 3 Bus Configuration A 16 Bit DRAM Bus and 16 Bit SD Bus BANK 3 3 BANK 2 m p al BANK 0 L Low Word Low Byte ElanSC400 Microcontroller 3 m m I Bank 2 Low Word High Byte DRAM Low Word SD7 SDO 07 00 023 016 Low Byte ROM Flash Optional Low Word High Byte SD15 SD8 SD15 SD8 D31 D24 ROM Flash ISA 8 16 SD15 SDO Card 8 16 5015 500 Notes The lanSC400 and ElanSC410 microcontrollers support a maximum of 4 banks of 32 bit DRAM but because the RAS and CAS signals for the high word and for banks 2 and 3
352. e ElanSC400 microcontroller s ISA data bus SD15 SD0 is used to directly access data on the PC Card data bus If buffering of the PC Card address and data buses is desired the ICDIR signal can be used along with some combinational logic external to the ElanSC400 microcontroller to control the direction and enabling of these buffers during PC Card accesses Memory Interface The lanSC400 microcontroller s PC Card Controller can be configured to operate in either of two modes Standard mode or Enhanced mode The mode applies to both sockets simultaneously i e the sockets cannot be configured independently for different modes Standard and Enhanced modes differ in three areas number of memory windows supported PC Card cycle speeds supported and PC Card DMA configuration support Standard Mode Standard mode is the default power up mode Standard mode is further described in Section 19 5 5 It includes the following features i Memory Windows Six total memory windows Two are fixed one for each socket and the remaining four can float i e can be configured for Socket A or B on a window by window basis Cycle Speeds Nominal 8 MHz PC AT bus clock speed only Features PC Cards cannot be configured as initiators in this mode Enhanced Mode Enhanced mode is entered by programming the MODE bit in the PC Card Mode and DMA Control Register CSC index F1h Enhanced mode is further described in Section 19 5 6
353. e Infrared Data Association Serial Infrared Link Access Protocol IrLAP specification is called a frame As a basic point of reference the 1 152 Mbit s IrDA frame is similar to an HDLC frame Each 1 152 Mbit s IrDA frame consists of two pieces the payload data and the wrapping layer The payload data contains some overhead data used to operate the link along with the user information to be transmitted The wrapping layer surrounds the payload data with start and end flags which delimit the frame The wrapping layer also provides CRC data for error detection and recovery The payload data consists of three fields Address ADDR Control CTL and an optional Information INFO field The following is an in sequence breakdown of a high speed 1 152 Mbit s IrDA frame shown in Figure 18 5 STA 2 bytes The STA bytes are part of the wrapping layer For 1 15 Mbit s IrDA a minimum of two STA flags are required at the beginning of each frame The start flag is set to a constant value of 7Eh 01111110b that is defined by the IrLAP standard More than the required minimum of two start flags can be sent since an infrared receiver treats multiple start flags as a single flag Multiple start flags are depicted in the diagram below STA flags are alternatively referred to as BOF Beginning Of Frame flags ADDR 1 byte An 8 bit field atthe beginning of the payload data specifies the address of the intended receiver Actually only bits 7 1
354. e PLL Low Speed PLL High Speed PLL and Graphics Dot Clock PLL The Graphics Dot Clock PLL is not available on the ElanSC410 microcontroller Each of the integrated phase locked loops has a dedicated pin to support the required external loop filter These pins are LF INT Intermediate PLL LF LS Low Speed PLL LF HS High Speed PLL and LF VID Graphics Dot Clock PLL Two capacitors and one resistor are required to implement each loop filter The LF VID pin is not supported on the ElanSC410 microcontroller The crystal oscillator needs two pins but it does not require any external components except the crystal the load capacitors and the feedback resistor are integrated on chip Figure 6 2 Clock Generation 32 768 KHz 32 768 KHz Real Time Crystal Clock Oscillator PMU Intermediate _1 47456 MHz DRAM PLL Controller Low Speed 36 864 MHz 5 UART PLL Y Dot Clock Graphics PLL Controller High Speed 66 3552 MHz ae DRAM B Controller ISA Bus 2 a yy DMA Controller CPU and VL Bus Controller ROM Flash p Interface PC Card Notes L Controller On ElanSC400 microcontroller graphics controller s DRAM interface is clocked by 66 MHz DRAM clock Both the ROM Flash interface and the PC Card controller are clocked from the CPU clock They also have the option of being run from the slow system clock Neither the graphics controller nor t
355. e R and G components are controlled by bits 1 0 of the bitmap for a particular pixel in the graphics buffer and the B and components come from Port O3D9h 5 4 respectively A similar situation exists for 1 BPP high resolution CGA mode In this case when the bit associated with a pixel 0b the components are each Ob color code 0 When the bit 1b the RGBI components come from O3D9h 2 O3D9h 1 OSD9h 0 and O3D9h 3 respectively Since flat mapped graphics mode is custom its 2 BPP mode uses a different scheme for specifying the components B and are represented by bits 1 0 of the bitmap for a particular pixel in the graphics buffer and the R and G components are always assumed to be 0 For 4 BPP flat mapped graphics mode the RGBI color code is specified by bits 3 0 of the bitmap for each pixel RGBI color codes are mapped to one of the available grayscales per Table 20 12 On the left is each possible RGBI combination which also presents each of the 16 RGBI color codes in binary On the right is the register and bit field for specifying which grayscale will be present on screen for a pixel with that RGBI color code associated with it Table 20 12 Grayscale Remapping 20 4 7 2 2 Bit Field Bit Field CSC Index 16 Color Grayscale 4 Color Grayscale Mode Mode 44h 3 0 1 0 44h 7 4 5 4 45h 3 0 1 0 45h 7 4 5 4 46h 3 0 1 0 46h 7 4 5 4 47h 3 0 1 0 47h 7 4 5 4 48h 3 0 1 0 48h 7 4 5 4 49h 3 0
356. e clocks the other cores receive Table 6 6 shows the clock speeds for each PMU mode The CPU clock is programmable to run at 33 18 MHz to 1 04 MHz in High Speed and Low Speed modes and at 33 18 MHz for Hyper Speed mode the 33 MHz is multiplied up by the CPU core PLL to 66 MHz or 100 MHz When the CPU clock is at 33 16 or 8 MHz the system clock used for ISA access will occur using the 8 29 MHz clock When the CPU clock is below 8 MHz 4 2 or 1 MHz the clock for ISA access will occur using the same clock speed 4 2 or 1 MHz The automatic slowdown feature is another way to fine tune the system by giving up some performance for lower power When enabled via CSC index 81h the automatic slowdown feature will cause the CPU clock to switch between two clock speeds at a programmed duty cycle Although this will impact system performance it is a way to fine tune the power requirements of the system Caution should be taken when using this feature while DMA transfers are active Auto slowdown also provides thermal protection should this become necessary Occasionally slowing down the CPU clock reduces the CPU s heat This feature is effective when the PMU is in Hyper or High Speed modes When Hyper Speed mode is enabled and entered the PMU will switch to using the High Speed mode CPU clock speed When Hyper Speed mode is disabled the PMU will switch between High and Low Speed CPU clock speeds If the High Speed CPU clock is
357. e correct bank which RAS strobe will be asserted If two banks are interleaved using the DRAM Control Register CSC index 04h both banks RAS strobes are asserted simultaneously B The DRAM controller generates an address offset by subtracting the start of the selected bank from the physical address B The highest order bits of the address offset will be asserted on MA12 MAO as the row address with the RAS strobe the middle bits of the offset will be asserted on 12 MAO as the column address with the CAS strobe s and the lowest order bits will be used in conjunction with the size of the read or write request to determine which byte lanes will be read or written which CAS strobes will be asserted The number of row column and byte lane address bits depends on the particular DRAM bank s device configuration Table 9 2 shows the byte lane mapping Table 9 4 shows the row and column mapping for non interleaved banks and Table 9 5 shows the row and column mapping for interleaved banks RAS Strobe Assertion Bank Selection Bank 0 is considered to be the first bank and Bank 3 is the last bank Any combination of banks can be enabled e g it is not necessary to enable Bank 0 in order to enable Bank 2 The first enabled DRAM bank is located in the CPU address space at physical address 0000000h The size of each enabled bank is automatically calculated by the lanSC400 and ElanSC410 microcontrollers using the WIDTH and DEPTH field
358. e cycles do not occur This mode is useful for precision setting of the clock If entering this mode from the oscillator off mode a 200 ms delay must be observed to allow for oscillator stabilization prior to attempting to set the time Time and date update cycles begin 500 ms after the countdown chain reset is removed Programming DV2 DVO to any value except 010b 11xb disables the input clock from the oscillator circuit In this mode time and date update cycles do not occur but the RTC draws slightly less power Upon exiting this mode a 200 ms delay should be observed before reconfiguring or using the time and date information to allow for oscillator stabilization DV2 DVO are not affected by a reset of the RTC subsystem Update Cycle The RTC executes an update cycle once per second assuming the DV2 DVO divider is not clear and the SET bit in Register B is clear When the SET bit is 1 the program can initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring With a 32 768 KHz time base the update cycle takes 1984 us During the update cycle the time calendar and alarm bytes are not available because they are taken off the bus for the entire update cycle If a program reads these RAM locations before the update is complete the output is undefined The update in progress UIP status bit is set during this time There are three ways to handle nonavailability during an RT
359. e key pressed interrupt as the wake up As an alternative to using the columns the 505 RES signal can be used to do the wake up The enables to make these wake ups are described in Section 5 4 9 CPU Scanned Keyboard The CPU handles all scanning of the keyboard There is no state machine to automatically walk a 0 through the columns and save the pressed key information for the CPU to retrieve later The CPU obtains its key pressed information by writing the column signals Low through the Keyboard Column Register at CSC index C7h one at a time and reading the rows through Keyboard Registers A and B at CSC index C8 C9h to check if any of the rows are Low If any row is detected Low then the key atthat row column intersection is pressed To account for key bounce a software debounce should occur by waiting an appropriate amount of time several milliseconds actual time depends on key switch characteristics and system design and scanning the keys again to confirm the same keys are pressed The software firmware that is controlling this can then map that row column intersection into a code indicating which key is pressed Keyboard Timer The keyboard controller incorporates its own timer that can be set for 3 91 ms to 1 second in 3 91 ms increments On a time out the timer generates a key timer interrupt that can be programmed to cause an SMI or NMI and start the CPU clock back up if it has been stopped Note The internal RTC must be i
360. e mapping of the parallel port s internal interrupt request to either the PIRQ5 or PIRQ7 output Table 14 1 Parallel Port Register Summary Description Register Address Parallel Port Function Keyword in Register Set Manual Pin Mux Register B 22h 23h Parallel port signals enable page 3 45 Index 39h Activity Source Enable 22h 23h Activity source enable CPU access to the page 3 74 Register D Index 65h parallel port Activity Source Status Register D 22h 23h Activity source status CPU access to the page 3 78 Index 69h parallel port Activity Classification Register D 22h 23h Primary or secondary activity classification page 3 82 Index 6Dh CPU access to the parallel port Access SMI Enable 22h 23h SMI enable for I O access to LPT1 or LPT2 page 3 105 Register A Index 99h Access SMI Status Register A 22h 23h SMI state for access to LPT1 or LPT2 page 3 107 Index 9Bh Parallel Serial Port Configuration 22h 23h Internal parallel port enable base address page 3 167 Register Index D1h configuration LPT1 or LPT2 14 2 Parallel Port AMD Table 14 1 Parallel Port Register Summary continued Description Register Address Parallel Port Function Keyword in Register Set Manual Parallel Port Configuration 22h 23h PC AT Compatible Bidirectional or EPP page 3 168 Register Index D2h mode select EPP timeouts Interrupt Configuration 22h 23h IRQ mapping to the programmable interrupt page 3 174 Registe
361. e out can cause an interrupt Keyboard input buffer written Internal keyboard controller input buffer written can cause an interrupt Keyboardoutputbuffer read Internal keyboard controller output buffer read can cause an interrupt GPIO CS14 GPIO_CS0 signals Falling edge can cause SMI NMI PC Card Detect signals Either edge of a Card Detect change can cause an SMI NMI PC Card INTR signal Falling edge can cause an SMI NMI PC Card Ring Indicate signal Falling edge can cause an SMI NMI Force SMI NMI bits Bits for software to force an SMI NMI to occur Peripheral I O trapping Causes an interrupt Wake up Access SMIs Any wake up can cause SMI NMI Causing an SMI from the following instruction cycles allows the SMI code to program the I O Instruction Restart Slot Register in the CPU This register causes the CPU to re execute the I O cycle that caused the SMI This can be used to power up external devices for use start up clocks etc before the device is actually accessed by the I O cycle Table 5 4 shows the I O trap sources Power Management 5 31 Table 5 4 5 4 13 5 32 Trap Sources Parallel port access LPT1 0378 037Fh LPT2 0278 027Fh can cause trap UART access COM1 03F8 03FFh or COM2 0 2F8 02FFh can cause a trap Keyboard access Reads and writes to ports 0060h and 0064h can cause a trap GP
362. e scope of this document However as the previous section discusses the controller s memory mapping is quite sophisticated This section focuses on differences between the lanSC400 microcontroller and the 82365 with particular emphasis on memory management The standard 82365 registers are mapped at I O locations O3EO and OSE1h Additionally CSC index registers FO F2h are used for PC Card control The lanSC400 microcontroller has two distinct PC Card modes Standard and Enhanced When bit 0 in the PC Card Mode and Control Register CSC index F1h is clear Standard mode the PC Card Socket B memory windows 1 4 are reassigned to be MMS windows Window 0 in each socket is still available for PC Card and Socket A s windows 1 4 can be individually remapped to point either to Socket A or Socket B using bits 4 7 of the PC Card Extended Features Register CSC index FOh When CSC index F1h 0 is set Enhanced mode each PC Card socket has its full complement of five memory windows and MMS Windows C F are disabled Simplified PC Card Control In addition to the standard access of the PC Card space PC Card A data space may be accessed by remapping ROMCSO0 and or ROMCS to the PC Card ROMCSO remapping is provided to support reprogramming of soldered down Flash boot parts from a PC Card when a jumper is set The ROMCSO redirection feature also allows testing of code by placing it on a PC Card memory card linear Flash or SRAM
363. e selected ROM device may latch data from the data bus ROM 32 Bit Buffer Output Enable provides the buffer enable signal for the external transceivers on the low word of the ROM interface This signal is automatically provided when the ROMCSO interface is configured as 32 bit the configuration can be done using either CFG1 CFGO or CSC index 201 1 0 Once ROMCSO is configured as 32 bit all accesses to 32 bit ROM devices on ROMCS2 ROMCSO will result in the assertion of the R32BFOE signal VL Bus Interface VL ADS Local Bus Address Strobe is asserted to indicate the start of a VL bus cycle It is always strobed Low for one clock period The address and status lines will be valid on the rising edge of VL LCLK which samples this signal Low VL BES VL BEO Local Bus Byte Enables indicate which byte lanes of the 32 bit data bus are involved with the current VL bus transfer System Interfaces Table 4 4 Signal Description Table continued Signal Type Description VL BLAST Local Bus Burst Last is asserted to indicate that the next VL BRDY assertion will terminate the current VL bus transfer VL BRDY Local Burst Ready is asserted by the VL bus target to indicate that it is terminating the current burst transfer The chip samples this signal on the rising edge of VL LCLK VL BRDY should be asserted for one VL LCLK p
364. e signal PPDWE and the output enable signal PPOEN B n PC AT Compatible mode PPDWE is used to drive data to the external parallel port data bus In the Bidirectional or EPP mode of operation the PPDWE signal is reconfigured via firmware to function as an address decode for the Parallel Port Data Register Minimal System Design PC AT Compatible Mode The PC AT Compatible parallel port requires an external 374 Octal D Flip Flop to latch the data from the SD data bus and drive the data onto the external parallel port data bus as shown in Figure 14 2 Parallel Port Data Control in PC AT Compatible Mode 374 Octal D Flip Flop SD7 SDO lanSC400 2 Microcontroller Parallel Port Data Bus The PPDWE signal is the parallel port data write enable signal In PC AT Compatible mode a write operation to the Parallel Port Data Register causes SD7 SDO data to be latched and driven onto the parallel port data bus A read operation causes the internal Parallel Port Data Register to return the last value that was written to it Bidirectional and EPP Modes The Bidirectional and EPP mode configuration requires two external devices one 373 Octal D Transparent Latch and one 244 Octal Buffer as shown in Figure 14 3 Parallel Port 14 5 Figure 14 3 Parallel Port Data Control Bidirectional and EPP Modes 373 Octal D Transparent Latch SD7 SDO Parallel Port Data Bus D Q EN OE
365. e state of the RTC power supply prior to the application of the primary power supply and not the state of the RTC power supply in real time Real Time Clock AMD 13 5 INITIALIZATION The real time clock is enabled at power on reset however it is not reset by a power on reset 1 Before initializing the internal registers set the SET bit in Register B to prevent time or calendar updates from occurring 2 Initialize the ten time calendar and alarm registers in either binary or BCD data format 3 Specify the format in the data mode DM bit of Register B All ten time calendar and alarm registers must use the same data mode either binary or BCD 4 Clear the SET bit to enable updates Wheninitialized the RTC makes all updates in whatever data mode has been programmed To change the data mode the ten data bytes must be re initialized 13 6 POWER MANAGEMENT Operation of the programmable interrupt controller is affected by the power management functions shown in Table 13 3 Table 13 3 Power Management in the Real Time Clock Power Management Effect RTC Event Description Wake Up Activity RTC alarm Triggered by the rising edge of internal IRQ8 Programmable I d Real Time Clock 13 9 13 10 Real Time Clock xs 1 4 PARALLEL PORT 14 1 The parallel port on the lanSC400 and lanSC410 microcontrollers is functionally compatible with an IBM PC AT and PS
366. e taken that this supply voltage is isolated properly to provide a clean noise free voltage to the PLLs Voc BUS 3 3 V DC Supply Pins provide power to the SD bus signals Voc CPU 3 3 V DC Supply Pins provide power to the internal CPU LCD or 3 3 V DC Supply Pins provide power to the LCD panel VL bus control signals on the Vcc VL ElanSC400 microcontroller These pins are called Voc VL on the ElanSC410 microcontroller 4 12 System Interfaces Table 4 4 Signal Description Table continued Signal Description MEM 3 3 V DC Supply Pins provide power to the system memory signals Voc POM or 3 3 V DC Supply Pin provides power to the PC Card Socket A control signals on the Voc PP ElanSC400 microcontroller This pin is called Voc PP on the ElanSC410 microcontroller Voc PCM or 3 3 V DC Supply Pin provides power to the parallel port PC Card slot B control signals on Voc PP the ElanSC400 microcontroller This pin is called PP on the lanSC410 microcontroller 3 3 V Supply Pin provides power to the internal real time clock and on board static configuration RAM This pin may be driven independently of all other power pins 3 3 V DC Supply Pins provide power to the serial port I O signals 3 3 V DC Supply Pins provide power to the ISA bus control signals 4 3 PIN CHANGES FOR THE LANSC410 MICROCONTROLLER The following signals supported on the lanSC400 microcontroller
367. e the internal UART only one interface can be enabled at any given time This means that both a serial device and an IrDA device can be designed into the same system and the microcontroller will support real time switching between the two ports The infrared port on the ElanSC400 and ElanSC410 microcontrollers is capable of half duplex operation only The port operates in either Slow Speed or High Speed Infrared modes Slow Speed Infrared mode Supports a variable programmable baud rate in exactly the same way as a standard 16550 UART using the same registers and controls Either interrupt driven or polled I O operation is possible in Slow Speed Infrared mode but DMA is not supported in this mode The serialized data format that is emitted from the SIROUT pin in this mode is identical to what is found on a standard RS 232 SOUT signal i e programmable length start data and stop bit fields but the pulses are inverted and shortened High Speed Infrared mode Supports a fixed transfer rate of 1 152 Mbit s This mode is characterized by a continuous data stream the data bytes are not separated from each other with individual start and stop bits DMA is always used for transferring High Speed Infrared mode data between system DRAM and the UART s transmit and receive ports Infrared Port 18 1 18 2 REGISTERS A summary listing of the chip setup and control CSC registers used to control the infrared port in
368. e to either one toggle phase change per frame or up to 128 horizontal lines per toggle Frame and line pulse timing control Allows the graphics controller to have compatible timing with a large number of different LCD panels Vertical and horizontal border registers Allow unused areas of the display panel to be blanked if necessary Dual scan screen setup registers Allows for setup of dual scan screens in text or graphics modes Optional SMI NMI trapping Allows for mode set register compatibility Internal Unified Memory Architecture Unlike older graphics controller architectures where a separate memory device was used to support the graphics controller frame and font buffers the ElanSC400 microcontroller s graphics controller uses a portion of main system DRAM for these buffers to lower system cost This technique is known as Unified Memory Architecture UMA With UMA the system cost is lowered power consumption is reduced board space is saved and external design is simplified On the other hand the graphics controller must constantly access the main system DRAM to refresh the LCD Because delays in providing data to the LCD refresh would result in visual artifacts present on the LCD screen the graphics controller is given very high priority over other types of DRAM accesses Because the amount of data that needs to be transferred from system DRAM to the graphics controller to support screen refresh is proporti
369. eLoopl Exit the handler Another SMI will happen immediately because we haven t and cleared th forcesmi bit This time the SMBASE has changed so we will start executing from the A000 8000 location db OFh OAAh return from SMI Resume instruction SMI3000Happens db SMI handler installed amp working SMM base relocated to system DRAM a CodeLenl t 0 0 EQU 5 CodeFragl lt SMI handler for relocated 5 gt This code fragment is the SMI handler for the 2nd SMI and beyond It gets copied to the somewhat arbitrary location of A000 8000 Am4869 CPU AMD CodeFrag2 7 lt Click the speaker for an audible indication of SMI activity gt 7 mov bx 4300 frequency of click mov ax 34DDh mov dx 0012h cmp bx jnb ExitClick div bx mov bx ax in al 61h test al 03 jne SpkrEnabled Or al 03 out 61n al mov al 0B6h out 43h al SpkrEnabled mov al bl out 42h al mov al bh out 42h al short delay while the speaker is putting out the click mov cx 08000h loop Don t bother to put back timer count or speaker gate value this is just a test utility in 1 618 al off the speaker gat out 61n al ExitClick Clear all SMI status bits or another SMI can result Any SMM status port that has an SMI status bit set will be written to port 680H and port
370. ected as an access to any other memory space An ISA bus memory cycle may also be generated if the CPU generates a memory address that resides in the ISA overlapping memory region window This window can be defined to overlay any system memory region below 16 Mbytes Architectural Overview 1 2 15 4 1 2 15 5 ISA Bus Interface For External ISA Peripherals Chapter 4 The ISA interface consists of a subset of ISA compatible bus signals allowing for the connection of 8 or 16 bit devices supporting ISA compatible I O memory DMA cycles The following features are supported 8 2944 MHz maximum bus clock speed Programmable DMA clock speed up to 16 MHz 8 bit and 16 bit ISA I O and memory cycles ISA memory is non cacheable Direct connection to 3 or 5 volt peripherals Eight programmable IRQ input pins are available These interrupts may be routed via software to any available PC AT compatible interrupt channel Two programmable DMA channels are available for external DMA peripherals These DMA channels may be routed to software to any available ISA DMA channel VESA Local VL Bus Interface Supports 32 Bit Memory and I O Targets Chapter 4 The VESA local VL bus controller provides the signals and associated timing necessary to supporta single VESA compliant VL bus target Multiple VL bus targets can be supported using external circuitry to allow multiple VL devices to share the VL LDEV signal This al
371. ection 2 4 2 Note Signals noted with an asterisk in Table B 1 are not supported on the ElanSC410 microcontroller Table B 1 Pin Termination Control Control Bit CSC Index Pins Affected WIDTHO ENBLO 00h 3 7 MA12 WIDTH1 BNK ENBL1 01h 3 7 ROWS5 RAS3 BNK ENBL2 02h 7 KBD ROWA4 BNK ENBL3 03117 KBD ROWS 5 KBD ROW KBD ROW CASLT KBD ROWO CASLO VL ENB 141 3 LCDD7 BE3 VID ENB DDh 2 LCDD6 VL LDEV LCDD5 VL D C LCDD4 VL_LRDY LCDD3 TO LCDD2 VL W LCDD1 VL ADS LCDDO VE RST M VL_BE2 LC VL SCK VL FRM VL_LCLK LVEE BRDY LVDD VL BLAST Pin Termination B 1 Table B 1 Pin Termination Control continued Control Bit CSC Index Pins Affected GP EQU DMA 38h 0 GPIO CS9 TC GPIO CS10 AEN GPIO CS11 PDACKO GPIO CS12 GP EQU PIRQO 38h 1 GPIO_CS8 GP_EQU_PIRQ1 38h 2 GPIO CS7 PIRQ1 GP EQU IOCHRDY 38h 3 GPIO_CS6 IOCHRDY GP_EQU_IOCS16 38h 4 GPIO CS5 IOCST6 BLO CLKIO SLCT 38h 7 6 BLO CLK 10 PP PCMB SLCT 39h 1 0 GPIO21 PPDWE GPIO22 PPOEN GPIO23 SLCT WP B GPIO24 BUSY BVD2 GPIO25 ACK BVD1 GPIO26 PE GPIO27 ERROR CD B GP1028 INIT REG B GPIO29 SLCTIN RST B GPIO30 AFDT MCEH B GPIO31 STRB B
372. ectly connected to all of these devices In addition these signals are the upper word of the local data bus the 32 bit DRAM interface and the 32 bit ROM interface In these modes the system data bus can be generated via an external buffer connected to the SD bus and controlled by the buffer control signals provided SPKR Speaker Digital Audio Output controls an external speaker driver It is generated from the internal 8254 compatible timer Channel 2 output ANDed with I O Port 0061h 1 Speaker Data Enable the PC Card speaker signals are exclusively ORed with each other and the speaker control function of the timer to generate the SPKR signal TC Terminal Count is driven from the DMA controller pair to indicate that the transfer count for the currently active DMA channel has reached zero and that the current DMA cycle is the last transfer Configuration Pins BNDSCN EN Boundary Scan Enable enables the boundary scan pin functions When this pin is High the boundary scan interface is enabled When this pin is Low the boundary scan pin functions are disabled and the pins are configured to their default functions 4 6 System Interfaces Table 4 4 Signal Description Table continued Signal Description CFG3 Configuration Pin 3 enables the SD buffer control signals DBUFOE DBUFRDH and DBUFRDL This pin is sampled at the deassertion of RESET CFG2 Configuration Pin 2
373. ed Using these two registers it is possible to quickly select which portion of the text frame buffer is displayed at any time The format of the text mode frame buffer is discussed in Section 20 4 5 1 1 Graphics Controller 20 4 2 2 20 4 2 3 20 4 2 3 1 20 4 2 3 2 AMD Using the Frame Buffer in Graphics Mode In graphics mode software writes data into the frame buffer in order to display individual pixels The ElanSC400 microcontroller s graphics controller can be configured to use either 1 2 or 4 bits of the frame buffer data to form each pixel displayed With 1 bit per pixel a pixel can have only 2 states on or off In this mode an off pixel can not be seen on the display and an on pixel is displayed at full contrast giving a dark appearance on a monochrome LCD Adding to the pixel depth configuring the graphics controller for 2 or 4 BPP allows gray shades to be displayed Graphics Mode Memory Maps There are three types of memory maps available in graphics mode on the lanSC400 microcontroller CGA compatible linear or flat mapped and paged CGA Compatible Mode The CGA compatible memory map is provided for software compatibility with applications that use the CGA memory map For performance reasons on early PCs the 16 Kbyte CGA graphics frame buffer is split into two address ranges The first 8 Kbytes control even numbered scan lines on the LCD display and the second 8 Kbytes control odd numbered scan lines
374. ed immediately upon entry to SMM and no caching is performed during SMM This dramatically reduces the performance of systems that depend on SMI interrupts but is safe to use with overlaid SMM RAM Auto flush enabled SMM caching enabled This could be even lower performance than the previous case for overlaid SMM RAM because a manual flush should be performed upon exiting SMM The only possible reason to use this configuration is if SMM routines are very lengthy Auto flush disabled SMM caching disabled This should work for systems where the SMM RAM is not overlaying anything which is cacheable but is not itself always present For example if SMM RAM has been relocated to 00A0000 it potentially overlays an ISA bus VGA card memory Because the ISA bus is not cacheable VGA memory will not be in the cache when SMM is entered and the cache will not need to be flushed Because caching during SMM is disabled no flush needs to be performed upon exit from SMM Auto flush disabled SMM caching enabled This could be useful a closed environment where SMM RAM is always visible to make SMls faster Memory Management E 8 ROM FLASH INTERFACE gt 8 1 OVERVIEW The integrated ROM Flash interface includes the following features 8 16 and 32 bit ROM Flash interfaces Three ROM Flash chip selects Dedicated ROM Read and Flash Write signals for better performance Generates ROMWR for writes to Flash devices Assem
375. ed to as the card offset Thus using only a small window the entire PC Card memory mapped resource is accessible Because the PC Card controller is 82365 compatible the card offset is related to the window s base address One simple way to determine the value to program into the offset register which is 14 bits distributed over two PC Card controller indexed registers 14h and 15h for Window 0 5 offset for example is to use the formula REGISTER OFFSET WINDOW START 12 where REGISTER is the 14 bit offset register OFFSET is the desired base address of the PC Card memory region to access note 4 Kbyte granularity for this WINDOW START is the window s start address which would be programmed for Socket A Window 0 via PC Card controller index 10h and 11h gt gt refers to a shift right operation shift right 12 bits Note PC Card controller memory windows should never be opened in any region that is enabled for linear ROMCSO decode whether or not shadowing is enabled Failure to adhere to this may cause improper system operation because no internal address decoding priority is defined in this regard As a window setup example the following code opens PC Card Socket A s memory window 0 as a 4 Kbyte window at 00D0000h in CPU memory space and points it to card offset 0 Set up Socket A s memory window 0 to have a start address of 00000008 mov DX 3E0h PC Card controller index register mov AL 10h
376. ed to cause an SMI the SMI routine is exited and control is returned to the application software this is for software debounce 7 Ona timer time out key timer interrupt the SMI interrupt occurs and the keyboard service code runs through all the columns to identify all keys that are pressed Those keys found are compared to the keys pressed the first time through and any that match are translated into the correct PC AT scan code The first key scan code is written through the Keyboard Output Buffer Write Register CSC index C3h into the Output Buffer 8 The SMI routine is then exited and control is returned to the application software 9 When the software reads the Output Buffer to get the keystroke the OBF being cleared causes an SMI the code puts the next key scan code into the Output Buffer and exits and so on until all pressed keys are reported 10 While a key is in the pressed state the timer can be used to perform software debounce of the key press and provide information on the duration of the key press for Typematic support 11 When all keys are released the routine returns to the top programming all columns Low and a key pressed interrupt to cause an SMI 12 If the software writes to the Input Buffer with a command to the keyboard controller it causes an SMI and the SMI code can read the byte from the Keyboard Input Buffer Read Back Register CSC index C2h and act accordingly Keyboard Interfaces 16 11
377. efines the color depth of the image The CGA graphics modes are enabled by setting bit 1 of the CGA Mode Control Register Port 03081 Bit 4 of the CGA graphics mode register selects between 320x200 four color mode or 640x200 two color mode The CGA Color Select Register Port O3D9h can be used to map colors in the CGA graphics modes Graphics Controller 20 11 20 4 3 1 20 4 3 1 1 Figure 20 3 Figure 20 4 20 4 3 1 2 20 12 CGA Graphics Pixel Formats High Resolution Mode As discussed earlier in the CGA high resolution mode each byte in memory contains information relating to eight pixels The bytes are organized sequentially using the odd even format described in Figure 20 3 resulting in a screen resolution of 640x200 with two colors mapped to each pixel CGA Graphics Mode Memory Map CGA Graphics Frame Buffer 100 Even numbered 8000 bytes Scan Lines Unused 192 bytes 16 Kbytes 100 Odd numbered 8000 bytes Scan Lines Unused 192 bytes The byte offset and bit offset of a given pixel in the display coordinates origin located in the top left corner of the screen y increases positively in the downward direction x increases positively in the rightward direction may be calculated from x and y coordinates as follows Byte offset y 2 8192 y 2 80 x 8 CO Bit offset 7 x968 where is integer division with truncation is the integer modulus rema
378. egister CSC index F1h for a list of PC Card restrictions Graphics Frame Buffer MMS Window ElanSC400 Microcontroller Only On the ElanSC400 microcontroller when the internal LCD controller is enabled and configured for graphics not text mode graphics index 4Fh can be used to set up a specialized memory mapping window This window occupies the 16 Kbytes of CPU address space from 00B8000 00BBFFFh and can be mapped to the lowest 16 Mbytes of DRAM only that is to any of the four 16 Kbyte pages within the 64 Kbyte frame buffer defined by graphics index 4Dh Typically the frame buffer will be programmed to 00B0000h and this mode simply allows backward compatibility for CGA display programming Memory Management 7 9 7 6 4 7 6 4 1 7 6 4 2 7 10 When the Graphics Frame Buffer window is set the frame buffer is not visible to the CPU atthe location it actually occupies in DRAM unless that region of system CPU address space defaults to DRAM anyway It is visible only one 16 Kbyte page at a time through the MMS window This window should not be used for anything except the internal LCD controller enabling the LCD controller causes several side effects such as disabling caching on the mapped region PC Card Memory Management ElanSC400 Microcontroller Only Standard 82365 PC Card Control The PC Card controller on the lanSC400 microcontroller is modeled on the 82365 device a complete discussion of it is beyond th
379. em Management Interrupt generation timers activities and battery level monitoring The PMU provides Hyper Speed High Speed Low Speed Temporary Low Speed Standby Suspend and Critical Suspend modes Dynamically adjusted clock speeds for power reduction Programmable activity and wake up monitoring General purpose I O pins to control external devices and external power management Battery low and AC power monitoring SMI NMI synchronization and generation 5 1 1 PMU Terms This document refers to activities wake ups SMI NMls battery controls timer time outs and events The following are the definitions Activities Indicate the system is doing something and needs to be operating Activities can reset timers and cause mode changes to higher modes Activities are only effective from Hyper Speed High Speed Low Speed Standby and Temporary Low Speed modes they have no affect when the PMU is in Suspend mode A primary activity is one that requires extensive CPU involvement and forces the PMU back to High Speed mode from Low Speed or Standby modes A secondary activity does not require extensive CPU time to service it Wake ups Actions that wake up the PMU from Suspend mode and take it back to an operating mode Hyper High or Low Speed Wake ups are only effective when the PMU is in Suspend mode SMI NMIs Many things can be programmed to cause SMI or Non Maskable Interrupt NMI in the sys
380. ement 7 6 2 7 6 3 AMD MMS Windows C D E and F These four MMS windows are more powerful than MMS windows A and B but they are more complex to program To enable the setup of MMS Windows C F on either lanSC400 or ElanSC410 microcontroller the PC Card controller indexed register space mustbe enabled CSC index DOh 1 1 and the PC Card controller must be set up to operate in Standard mode CSC index F1h 0 0 On either microcontroller once any of MMS Windows C F is opened via PC Card index space disabling the internal PC Card controller does not disable the MMS windows but disallows their reconfiguration until the internal PC Card controller is re enabled When the internal PC Card controller is disabled on either microcontroller I O accesses to the PC Card indexed register space go off the microcontroller to the ISA bus Note The register settings described above are required even though the internal PC Card controller is not available on the ElanSC410 microcontroller MMS Windows C F are very flexible In addition to allowing mapping to any address in the target DRAM or ROM address spaces they allow selection of window location within the CPU address space as well as selection of window size The granularity of all addresses and sizes is 4 Kbytes which may have some advantages over the 32 Kbyte granularity of MMS windows A and B MMS Windows C F differ from MMS Windows A B in that the user supplies the destinatio
381. er Multiplexed Pin Configuration Control Signal You System Interface Signals You Give Up How to Configure the Signal You Want on the Pin BALE KBD ROW10 Set CSC index 39h 2 DBUFOE GPIO CS4 Hardwire strap the CFG3 pin High DBUFRDH GPIO CS3 Hardwire strap the CFG3 pin High DBUFRDL GPIO CS2 Hardwire strap the CFG3 pin High MCS16 KBD ROW12 Set CSC index 39h 2 PDACKi KBD ROW7 Set CSC index 39112 PDRQ1 KBD_ROW8 Set CSC index 39h 2 PIRQ7 KBD_COL6 Set CSC index 3Ah 2 PIRQ6 KBD_COL5 Set CSC index 3Ah 2 PIRQ5 KBD_COL4 Set CSC index 3Ah 2 PIRQ4 KBD_COL3 Set CSC index 3Ah 1 PIRQ3 KBD_COL2 Set CSC index 3Ah 1 PIRQ2 KBD_ROW9 Set CSC index 39112 PIRQ1 GPIO_CS7 Set CSC index 38h 2 PIRQO GPIO_CS8 Set CSC index 38h 1 R32BFOE KBD_ROW13 Hardwire strapping both the CFG1 and CFGO pins High enables the 32 bit ROM interface on ROMSCO This automatically enables R32BFOE SBHE KBD_ROW11 Set CSC index 39h 2 Multiplexed Pin Configuration Control A 1 Table 1 Multiplexed Pin Configuration Control continued Signal You Signals You How to Configure the Signal You Want on the Pin Memory Interface KBD_ROW3 Set bit 3 of the DRAM Bank x Configuration Register CASH2 KBD_ROW2 KBD ROW1 KBD ROWO KBD ROW6 KBD ROW5 KBD ROWA LCDD1 Enable the VL bus interface by setting CSC index 14h 3 LV
382. er C Index 64h Activity Source Status Register C 22h 23h Activity source status DMA request page 3 77 Index 68h Activity Classification Register 22h 23h Primary or secondary activity classification page 3 81 Index 6Ch DMA request Clock Control Register 22h 23h DMA controller clock frequency select high page 3 90 Index 82h speed infrared operation CLK IO Pin Output Clock Select 22h 23h Internal DMA and 2x DMA clock select for page 3 91 Register Index 83h CLK IO Internal I O Device Disable Echo 22h 23h DMAO and 1 slave controller disable page 3 164 Z Bus Configuration Register Index DOh DMA Channel 0 3 Extended 22h 23h Highest two bits of memory address for page 3 175 Page Register Index D9h channels 3 0 Channel 5 7 Extended 22h 23h Highest two bits of memory address for page 3 176 Page Register Index DAh channels 7 5 DMA Resource Channel Map 22h 23h PDRQx PDACKx and infrared controller page 3 177 Register A Index DBh mapping to internal DMA controller channels DMA Resource Channel Map 22h 23h PC Card Sockets A and B mapping to internal page 3 178 Register B Index DCh DMA controller channels IrDA Control Register 22h 23h Infrared DMA start up control data rate select page 3 188 Index EAh IrDA Status Register 22h 23h Infrared DMA IRQ state and generation page 3 190 Index EBh PC Card Mode and DMA Control 22h 23h DMA enable for PC Card Sockets A an
383. er and the Linear ROMO Attributes Register CSC index 21 and 22h the CPU can discretely control address space selection in five different 64 Kbyte regions 00C0000 00CFFFFh 00D0000 00DFFFFh 00E0000 00EFFFFh 00F0000 00FFFFFh and 3FF0000 S3FFFFFFh These are the only regions that may be mapped to ROMO space without using translated memory management DRAM and Non Translated Memory Management Before any DRAM can be used the boot code must program the DRAM controller using CSC index registers 00 07h The DRAM controller logically concatenates all the system DRAM into a single unified address space which starts at address 0 By default CPU addresses from 0 to the top of DRAM are mapped to the DRAM space in preference to ISA VL bus space The two exceptions to this are the window from 640 Kbytes to 1 Mbyte 00A0000 0100000h which defaults to ISA VL bus space or ROMO as described in the previous section and the 64 Kbyte window at the top of CPU address space 3FF0000 3FFFFFFh which defaults to ROMO The ElanSC400 and ElanSC410 microcontrollers offer a limited amount of programmatic control over DRAM using non translated memory management In the region 00C0000 00FFFFFh any accesses that would have gone to ROMO can be redirected to DRAM by setting bit 5 in the Linear ROMO Shadow Register at CSC index 21h Any of these 64 Kbyte regions that are mapped to the ISA bus instead of ROMO are not redirected by setting this bit This bit was desig
384. er controller drives the CPU s interrupt input signal based on the highest priority interrupt request pending at the master controller s IRQ7 IRQO inputs The master IRQ2 input is configured for Cascade mode and is driven only by the slave controller s interrupt output pin The highest pending interrupt at the slave s IRQ inputs will therefore drive the IRQ2 input of the master The interrupt controller has programmable sources for interrupts that are controlled using CSC indexed registers and on the ElanSC400 microcontroller using PC Card indexed registers 11 2 REGISTERS The following types of registers are used to configure the PIC on the lanSC400 and ElanSC410 microcontrollers Direct mapped initialization registers set the PIC to a known state Direct mapped operation control words These registers set up any special operating modes for the PIC Direct mapped status registers Interrupt Request Register indicates which internal IRQs are requesting service The In Service Register indicates which internal IRQs are being serviced The Interrupt Mask Register sets the mask bits for the internal IRQs Programmable Interrupt Controller 11 1 indexed configuration registers Table 11 1 A summary listing of the CSC and PC Card indexed registers used to control the PIC is shown in Table 11 1 Complete register descriptions for all the registers used to configure the PIC can be foun
385. er screens Offset Register 3x4h 3x5h Frame buffer width page 5 27 Index 3Eh Underline Location Register 3x4h 3x5h Scan line number of the underline attribute page 5 28 Index 3Fh used in MDA modes Maximum Scan Line Register 3x4h 3x5h Number of lines a character row of identically page 5 29 Index 40h addressed horizontal lines minus one LCD Panel AC Modulation Clock 3x4h 3x5h Horizontal line divide ratio modulation mode page 5 30 Control Register Index 41h Font Table Register 3x4h 3x5h Offset font plane character width and font page 5 31 Index 42h table write protection Graphics Controller Grayscale 3x4h 3x5h Grayscale functions remapping mapping page 5 32 Mode Register Index 43h mode shade mode contrast enhancement color STN and color border Graphics Controller Grayscale 3x4h 3x5h Grayscale remapping registers for page 5 34 Remapping Registers Index 44 4Bh corresponding input grayscale code Pixel Clock Control Register 3x4h 3x5h Graphics dot clock base frequency and divide page 5 36 Index 4Ch select Frame Buffer Base Address 3x4h 3x5h Frame buffer window base address high byte page 5 37 Register Index 4Dh Font Buffer Base Address High 3x4h 8x5h Font buffer window base address high byte page 5 38 Byte Index 4Eh Frame Font Buffer Base Address 3x4h 3x5h Frame and font buffers window base address page 5 39 Register Low Index 4Fh low bytes Graphics Frame Buffer MMS window enable MMS page select allocate DRAM Graphics Controller 2
386. er system bandwidth and increased performance over both the PC AT Compatible and Bidirectional modes Serial Port Chapter 15 The lanSC400 and ElanSC410 microcontrollers include an industry standard 16550A UART The UART can be used to drive a standard 8 pin serial interface or a 2 pin infrared interface The 8 pin serial interface and infrared interface pins are available on the lanSC400 and lanSC410 microcontrollers at all times though only one is available at any given time The UART powers up as a 16450 compatible device It can be switched to and from the FIFO 16550 mode under software control In the FIFO mode the receive and the transmit circuitry are each enhanced by separate 16 byte FIFOs to off load the CPU from repetitive service routines The serial port includes the following features Fight pin interface serial in serial out two modem control lines and four modem status lines Separately enabled receiver line status receiver data character time out transmitter holding register and modem status interrupts Baud rate generator provides input clock divisor from 1 to 65535 to create 16x clock 5 6 7 or 8 bit data Even odd stick or no parity generation and checking 1 1 1 2 or 2 stop bit generation Break generation detection Keyboard Interfaces Chapter 16 The integrated keyboard controller has the following features Matrix keyboard support with up to 15 rows and 8 columns
387. eral Purpose I O GPIO Pins The lanSC400 and ElanSC410 microcontrollers support several general purpose I O pins GPIOs that can be used for power management The GPIO pins are fully described in Chapter 17 The GPIO CSx signals have many programmable options for power management As outputs these pins are individually programmable to be High or Low for each PMU mode Hyper Speed High Speed Low Speed Standby Suspend As inputs or outputs they can be programmed to cause SMI NMIs wake ups or to be activities for the PMU They can also be used as I O or memory chip selects As an output a GPIO CSx can be A PMU mode change output set for High or Low for each PMU mode A maximum of four of the GPIO CSx signals can be PMU mode change outputs at any one time See Section 5 4 10 1 and Chapter 17 Enabled to cause an SMI NMI Only one GPIO CSx can cause an SMI NMI at any one time Enabled to cause an activity and wake up Memory or I O decode As an input a GPIO CSx can be Enabled to cause an SMI NMI Only one GPIO CSx can cause an SMI NMI at any one time Enabled to cause an activity wake up the system from Suspend mode Mappable GPIO PMUA GPIO PMUD Signals Up to four GPIO_CS pins can be programmed to inform external hardware of internal PMU states The internal signal names associated with this information are PMUA PMUB PMUC and PMUD Each of these signals has a register GPIO PMUx Mode Change
388. eration rate of 54 93 ms can be achieved E Driving an external 1 19318 MHz clock on the pin A system designer may choose to supply an external clock source frequency of 1 19318 MHz on the microcontroller s CLK IO pin This pin must be specifically configured for this functionality by the system BIOS during the system boot process prior to configuring Port 0040h Configuring Timer Channel 1 Timer Channel 1 can be programmed as the system memory DRAM refresh clock source It is programmed as a rate generator to produce a refresh pulse to the DRAM controller In the ElanSC400 and lanSC410 microcontrollers the 32 KHz oscillator clock source is the default memory refresh clock source If Timer Channel 1 is configured as the refresh clock source the 32 KHz clock source is always enabled as the refresh clock source when the system enters the Suspend mode of operation and CAS before RAS refresh is enabled in Suspend In this case the refresh clock source will switch back to the timer Channel 1 upon resuming from Suspend This is required because the timer clock source is disabled during Suspend Programmable Interval Timer 12 5 12 4 2 3 12 4 3 12 5 12 6 Table 12 3 Configuring Timer Channel 2 The gate line for Timer Channel 2 is controlled by Port 0061h 0 The output of Timer Channel 2 is read at Port 0061h 5 The output goes to the speaker SPKR when Port 0061h 1 is set Programming the Timer Cha
389. erent devices depending on the current microcontroller configuration see Table 4 11 It may help to think of the use of the microcontroller s data bus as being DRAM centric because the byte lane assignments always seem to make the most sense from the standpoint of the DRAM controller When the DRAM controller is configured to be 16 bits wide it uses byte lanes V1 and VO to carry DRAM data D15 D8 and D7 DO respectively When a ROM interface is configured to be 16 bits wide it uses the other 2 byte lanes V3 and V2 to carry ROM data RD15 RD8 and RD7 RDO respectively ROM Flash Interface Figure 8 2 64 Mbyte 1 Mbyte 00F0000 00E0000 00D0000 00C0000 00B8000 00B0000 00A0000 0000000 ROM Decode Example CPU Address Space ROMO Space ROMO Default 2 Mbyte Boot Upper 16 bytes 2 Mbyte 16 Bytes 32 Kbyte MMS window 1 Mbyte ROMO Default 64 Kbyte Boot Vector Enabled 64 Kbyte BIOS Disabled Disabled Notes Enabled enabled ROMO linear decode Disabled Disabled disabled for ROMO linear decode MMS decode ROMO linear decode and shadowable 0 Mbyte ROMO composite decode In this way a system using a 16 bit DRAM interface and a 16 bit ROM interface is simplified because the data buses for these two functions are completely isolated It is important to note that V3 and V2 are collectively
390. eriod per burst transfer If VL LRDY is asserted at the same time as VL BRDY VL BRDY will be ignored and the VL bus transfer will be terminated VL D C O Local Bus Data Code Status is driven Low to indicate that code is being transferred A High VL MIO on this signal indicates that data is being transferred VL W R Local Bus Memory l O Status is driven Low to indicate an I O transfer A High on this signal i indicates a memory transfer Local Bus Write Read Status is driven Low to indicate a read transfer A High on this signal indicates a write Bus Cycle Initiated VL M IO VL D C VL W R Interrupt Acknowledge 0 Halt Special Cycle 0 0 1 Read 0 1 0 Write 0 1 1 Code Read 1 0 0 Reserved 1 0 1 Memory Read 1 1 0 Memory Write 1 1 1 VL LCLK O Local Bus Clock is the VL bus clock It is used by the VL bus target for all timing references This signal is in phase with the internal CPU s clock input Rising Edge Active VL LDEV Local Bus Device Select is asserted by the VL bus target to indicate that it is accepting the current transfer as indicated by the address and status lines The VL bus target will assert this signal as a function of the address and status presented on the bus VL may be qualified with VL ADS by the local bus device VL LRDY Local Bus Ready is asserted by the VL bus target to indicate that it is terminating the current bus cycle This signal is sampled by the chip on the rising edge of VL
391. ernal RTC or an external device will be used for the RTC function in a system design 13 2 REGISTERS Two different sets of index registers are used to configure the RTC The setup and control CSC index registers are accessed via the 22h 23h data I O scheme The standard RTC index registers are accessed via the PC AT I O space at Ports 0070h and 0071 Real Time Clock 13 1 13 2 1 Table 13 1 Register A summary listing of the chip setup and control CSC and index registers used to control the real time clock is shown in Table 13 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 RTC and Configuration RAM Index Registers These indexed registers function as the configuration setup and status for the Real Time Clock RTC as well as user configurable RAM locations index registers 00 09h contain RTC seconds minutes hours day of week date of months months of year and year status as well as second minute and hour alarm configuration control Both binary and BCD formats are supported for these registers RTC registers 0A ODh are used to configure the RTC All index values from OE 7Fh can be used as read write RAM locations The 114 general purpose RAM bytes are not dedicated to the RTC They can be used by system or application level software and are fully available during the update cycl
392. ers is shown in Figure 11 1 IRQ mapping for card status change interrupt page 6 13 The interrupt controller block on the ElanSC400 and ElanSC410 microcontrollers is functionally compatible with the standard cascaded 8259A controller pair as implemented in the PC AT system Interrupt Requests 0 7 are configured for master operation in Cascade mode with IRQ2 dedicated to cascading the slave interrupt controller Interrupt Requests 8 15 are configured for slave operation Programmable Interrupt Controller Figure 11 1 Programmable Interrupt Controller Block Diagram PIRQ7 PIRQO External interrupt sources Internal interrupt sources Interrupt Configuration Registers A E Interrupt Mapping and IRQ Qualification Qualified IRQ15 IRQ8 IRGs to PMU IRQ7 IRQ3 IRQ1 IRQO INT2 Slave C de li in INT to CPU INT IRQ2 INT2 Slave INT1 Master ElanSC400 Microcontroller 11 4 OPERATION The PIC as implemented on the ElanSC400 and lanSC410 microcontrollers is different from the standard 8259 part in the following ways Cascade mode is hardwired internally using INT2 for the cascade 8080 8085 mode is not supported Automatic End of Interrupt is not supported in the slave However AEOI is supported in the master After initialization the PIC always comes in fully nested mode EOls s
393. es Low programmable option using CSC index 70 711 Cause a mode change to Critical Suspend mode if ACIN is not active The 505 RES signal toggles If enabled forces the system to Suspend mode Power Management 5 4 5 5 4 5 1 5 4 5 2 5 4 5 3 Suspend Mode Suspend mode is used when the system wants to enter a very low power mode keeping the DRAM refreshed and saving the status of the microcontroller s internal wake up or resume registers so it can return to the point it left off If the system PLLs the High Speed Low Speed Intermediate and Graphics Dot Clock PLLs are shut off it will take longer to return but Suspend power requirements will be reduced Actions Taken During Suspend Mode The following actions are taken in the lanSC400 and ElanSC410 microcontrollers during Suspend mode All clocks are stopped except the RTC and memory refresh which are derived off the 32 KHz oscillator without the system PLL s involvement B ThePLLs shut down programmable option via CSC index 82h 0 Note that clocks can be stopped gated off without shutting down the PLLs B The is left running B The DRAM refresh either CAS before RAS or self refresh is programmable to be left active or turned off f CAS before RAS refresh is left active the refresh clock is switched from the timer counter to the 32 KHz oscillator E The pins on the microcontroller go to their predetermined state an
394. es drivers further discussion of which is beyond the scope of this document In addition to the window configuration registers the PC Card controller supports other control registers used for interrupt routing and enabling selection of common attribute memory and socket power control The status of the PC Card interface as well as the status of pending PC Card and PC Card controller interrupt events can be read Interrupts can be routed to the power management unit to cause NMIs Non Maskable Interrupts and SMIs System Management Interrupts or to serve as wake up or activity events The PC Card Controller can run at various speeds There are two main speed categories running atthe current ISA bus clock rate which is variable on the ElanSC400 microcontroller from 8 MHz down to 1 MHz or running at the current CPU clock speed which is variable on the lanSC400 microcontroller from 33 MHz down to 1 MHz As described in Section 19 5 2 the PC Card controller operates in one of two modes Standard or Enhanced Standard mode This mode is standard for the ElanSC400 microcontroller and does not include compatibility with the standard 82365 B Enhanced mode This mode provides full 82365 compatibility with additional enhancements including DMA and timing controls When the PC Card controller is configured for Enhanced mode the bus timings of memory cycles can be fine tuned in terms of setup command and recovery hold times
395. ese signals are undefined System Interfaces 4 37 Table 4 19 Special Bus Cycles VL Write back Completion of all write backs in response to a WBINVD instruction Flush Completion of a WBINVD or INVD instruction Flush Acknowledge 1 Completion of all write backs in response to the assertion ofthe internal CPU s FLUSH signal Flush Acknowledge 2 Completion of a cache flush in response to the assertion ofthe internal CPU s FLUSH signal Stop Grant Assertion of internal CPU s STPCLK signal Halt Shutdown 4 8 4 5 Unsupported VL Bus Signal Note that the microcontroller s VL bus does not drive the VESA RDYRTN signal The system designer is responsible for tying the VL bus target s LRDY and RDYRTN signals together 4 8 5 Initialization The VL bus controller is disabled at power on reset After enabling the VL bus interface VL RST should be asserted and deasserted before using the VL bus The VL bus reset control is located at CSC index 14h 4 4 8 6 Power Management The speed of the VL bus changes with the CPU speed VL bus logic switching is disabled when the VL bus interface is disabled Operation of the VL bus is affected by the power management functions shown in Table 4 20 Table 4 20 Power Management in the VL Bus Controller Power Management Effect VL Bus Event Description su wu VL bus cycle Any VL bus cycle mem
396. eserve certain system resources Any indexed register is an example of this but the CSC index register at 22h must absolutely be preserved to maintain a transparent SMM handler 9 System registers including processor mode and interrupt enable information are restored from the State Save Map If the SMM handler has stored invalid information here such as setting SMBASE to a value that is not 32 Kbyte aligned or setting illegal bits in the saved CRO register image a shutdown mode is entered 10 The override of A20 is removed 11 The SMRAM memory mapping override is removed 12 Caching is restored to its original state 13 If a soft CPU reset has been requested it will be issued and the CPU SRESET signal will be pulsed State Save Map When an SMI occurs the entire state of the CPU including internal registers not normally visible to the programmer is automatically saved to SMRAM so that when the SMI processing is finished the CPU core state can be transparently restored by the RSM instruction The area of SMRAM where the state is stored is called the State Save Map Table 3 3 shows the format of the State Save Map Many SMI handlers will have no interest in the format of the State Save Map except for the location of SMBASE because the goal of the handler is complete transparency to other code running on the machine Some SMI handlers are required to communicate with other code running on the machine A typical example of this m
397. eset vector of 3FFFFFOh in ROMCSO space when RESET is deasserted The state of CFG1 CFGO pin straps determines the width of the ROMO data bus as described in Section 4 4 These pin straps are used to select between 8 16 or 32 bit data bus widths for the physical device that is connected to the ROMCSO pin for the linear address decode At power on reset the 64 Kbyte segment between and OOFFFFFh is enabled by default for ROMCSO decode 3FF0000 3FFFFFFRh is enabled for decode CSC index 21h and in many systems this will alias to OOFOOOO OOFFFFFh Setting the characteristics of the ROM address spaces is described in Chapter 8 The CFG2 pin strap selects whether or not the system will boot from the device attached to ROMCSO or from the PC Card Socket A memory card The CFG3 pin strap is used for selecting between the GPIO CSx I O pins and the SD bus buffer control signals DBUFOE DBUFRDL and DBUFRDH When the buffer control signal configuration is selected using the CFG3 pin the DBUFOE DBUFRDL and DBUFRDH signals will be driven from boot time on for all accesses to the peripheral data bus These signals are used to control external transceivers on the system data bus A power on reset configures the internal cores and peripherals of the lanSC400 and ElanSC410 microcontrollers as shown in Table 4 2 After the deassertion of RESET the configuration registers should be initialized with the information required for the
398. ess mapping must not change during the DMA transfer An 8 bit DMA initiator may not transfer to a target that is less than its bus width For example a 16 bit initiator cannot transfer to an 8 bit target An 8 bit target can transfer to a 16 bit target Supported DMA Initiator Target Combinations DMA Target DRAM _ ISABus PC Card Yes Yes Infrared Port 8 bits PC Card 8 16 bits ISA bus 8 16 bits Note The PC Card controller is not supported on the lanSC410 microcontroller All DMA transfers are fly by type the data is moved from the I O device to memory DMA write or from memory to the I O device DMA read in a single transaction A non fly by transfer implies two cycles one for the initiator and one for the target PC AT DMA transactions are always fly by type Memory to memory transfers are not supported Bi There are three modes of DMA transfers supported single transfer demand transfer and block transfer described more completely below Fly by DMA transfers require the ability to simultaneously assert an I O command and a memory command i e MEMW writes IOW MEMR for reads The ISA bus provides an additional signal AEN to prevent I O devices residing on the same bus as the DMA initiator from decoding the memory target address driven by the DMA controller DMA Controller 10 4 2 1 10 4 2 1 1 10 4 2 1 2 10 4 2 1 3 10
399. evice Select 22h 23h Physical device selection for MMS Windows page 3 39 Register Index 31h C F Memory Management 7 1 Table 7 1 Register MMS Window A Destination Register Address 22h 23h Index 32h Memory Management Unit Register Summary continued MMU Function Keyword Destination start address bits SA22 SA15 for MMS Window A Description in Register Set Manual page 3 40 MMS Window A Destination Attributes Register 22h 23h Index 33h Destination start address bits SA25 SA23 enabling caching write protection and physical device selection for MMS Window A page 3 41 MMS Window B Destination Register 22h 23h Index 34h Destination start address bits SA22 SA15 for MMS Window B page 3 42 MMS Window B Destination Attributes Register 22h 23h Index 35h Destination start address bits SA25 SA23 enabling caching write protection and physical device selection for MMS Window B page 3 43 Internal I O Device Disable Echo Z Bus Configuration Register 22h 23h Index DOh PC Card controller enable required to setup MMS Windows C F for either microcontroller page 3 164 Write Protected System Memory DRAM Window Overlapping ISA Window Enable Register 22h 23h Index EOh Stop address bits SA25 SA20 for the write protected window page 3 181 Overlapping ISA Window Start Address Register 22h 23h Index E1h Start address
400. exed Register Writes During an I O write to a CSC indexed register the following activity occurs on the external ISA bus when the CSC indexed register echo feature is enabled The I O address is driven out onto SA23 SAQ For writes to the index register this address is 22h For writes to the actual CSC indexed register the address is 23h SBHE is driven out if enabled BALE is driven out if enabled MCS16 and IOCS16 inputs are ignored if enabled or disabled AEN is asserted if enabled DBUFOE is deasserted if enabled DBUFRDH and DBUFRDL are static if enabled TOW is asserted IOCHRDY input is ignored if enabled or disabled The write data is driven out onto SD7 SDO All accesses are performed at ISA bus speeds when the CSC indexed register echo feature is enabled If a particular core feature is disabled the individual CSC indexed registers associated with that core can still be accessed and if the echo feature is enabled will be echoed onto the ISA bus The actual register bits may or may not be functional in this state CSC Indexed Register Reads During an read to a CSC indexed register the following activity will occur on the external ISA bus when the CSC indexed register echo feature is enabled The I O address is driven out onto SA23 SAO B SBHE is driven out if enabled BALE is driven out if enabled MCS16 and lOCS16 inputs are ignored if enabled or disabled AEN is asser
401. f these signals need to be latched to generate the interrupt and be read by system software to determine the cause of the interrupt The Card Status Change Register description explains how each of these register bits is to be controlled by hardware The PC Card controller is compliant with revision B of the 82365 Unlike revision C compatibility the status bits will latch when a status change is detected even when the event is not first unmasked To avoid spurious interrupts when enabling status change event sources the latch should be cleared prior to unmasking the status change interrupt source The CD CHNG bit in the Card Status Change Register can also be set but not cleared by writing to the FORCE CD xbitinthe PC Card Extended Features Register This feature allows software to generate a card detect change event that can be read back from the Card Status Change Register Sound Generation When a socket is configured for the Memory and I O mode its BVD2 x SPKR x pin can be used to generate sounds on the system speaker via the ElanSC400 microcontroller s SPKR pin PC Card Controller 19 5 10 19 5 10 1 The first step of this feature is the masking of the BVD2 x SPKR signals with the CARD 15 IObitinthe Interrupt and General Control Register no sounds can be generated on BVD2 x when the socket is configured for the Memory only mode and the masked signal is held in the inactive high state The resulting masked SPKR
402. ffered for each card In Suspend mode OE and WE are left High this would back power the card if it is not buffered off The PC Card power control signals allow the system to turn each power plane of the card on and off PCMx VCC x being A or B controls the 5 V 3 V power plane and PCMx VPP1 and PCMx VPP2 work together to choose 12 V Vcc or GND for the PC Card VPP power pins To design a system that provides either 5 V or 3 3 V to the PC Card power planes use an ElanSC400 microcontroller GPIO signal for the 3 3 V enable or use a GPIO to steer the PCMx VCC signal to either the 5 V or 3 V enable The PC Card sockets are usable individually but they are not able to be powered individually if they are not buffered INITIALIZATION The PC Card controller is disabled at power on reset and must be configured and enabled by software There are really two levels at which the PC Card controller can be disabled Individual features can be turned off i e Card windows can be disabled IRQs unrouted etc Access to the PC Card controller index and data registers can be disabled ports 3EOh and 3E1h respectively PC Card Controller 19 6 1 The controller starts off with both the individual features and the access to the index and data registers being disabled To gain access to the registers used to turn on individual features the PC Card controller index and data ports must be made access
403. figuring timer channel 0 12 5 timer channel 1 12 5 timer channel 2 12 6 initialization 12 6 modes Mode 0 interrupt on terminal count 12 3 Mode 1 hardware retriggerable one shot 12 3 Mode 2 rate generator 12 4 Mode 3 square wave mode 12 4 Mode 4 software triggered strobe 12 4 Mode 5 hardware triggered strobe 12 5 timer modes table 12 3 operation 12 3 overview 12 1 power management 12 6 programming the timer channels 12 6 registers 12 1 R R32BFOE signal control 5 7 description 4 7 usage 4 16 8 6 RASS3 RASO signals control 9 3 description 4 7 usage 9 1 9 12 RDY IREQ signal description 4 11 usage 19 18 RDY B IREQ B signal description 4 11 usage 19 18 real time clock RTC backup battery considerations 13 6 backup battery not used figure 13 8 backup battery used figure 13 7 block diagram 13 3 initialization 13 9 interrupts 13 5 specifying a periodic interrupt rate table 13 5 operation 13 5 oscillator control 13 6 overview 13 1 power management 13 9 registers 13 1 RTC clock 13 6 RTC voltage monitor 13 4 system implications 13 8 update cycle 13 6 voltage monitoring 13 3 1 16 Recovery Timing Registers function 19 4 usage 19 7 19 13 19 17 REG signal description 4 11 usage 19 8 19 16 REG B signal description 4 11 usage 19 8 19 16 Register index function 13 3 usage 13 5 13 6
404. flush cycle status CPU shutdown cycle status graphics memory write through cache Various SMI NMI Enable and 22h 23h See Chapter 5 Table 5 1 for complete listing various Status Registers Index 90 9Ch Am486 CPU 3 1 Table 3 1 CPU Control Register Summary continued Description Register Address CPU Control Function Keyword in Register Set Manual XMI Control Register 22h 23h Master SMI enable page 3 109 Index 9Dh lanSC400 Microcontroller 22h 23h Major and minor stepping level of ElanSC400 page 3 201 Revision ID Register Index FFh and ElanSC410 microcontrollers 3 3 CPU FEATURES SPECIFIC TO THE lanSC400 AND lanSC410 MICROCONTROLLERS The lanSC400 and ElanSC410 microcontrollers are fully integrated systems in silicon and the CPU is central to this integration Most of the details of the communication between the CPU core and the peripherals are transparent to the user and are not documented here While we have tried to provide most of the information designers will require to incorporate the lanSC400 and lanSC410 microcontrollers into products a full description of the operation of a 486 microprocessor is well beyond the scope this chapter which discusses programming issues related to this specific implementation rather than general x86 or 486 programming Any bookstore with a good computer section will have many good books on x86 programming and the following AMD publications a
405. follows 1 Software sets up the transmit buffer in system DRAM with data as required 2 Software routes the infrared DMA to an 8 bit DMA channel via the DMA Resource Channel Register A CSC index DBh 7 6 Note that any channel mapped for use with the infrared port must not be programmed for block mode See Section 10 4 2 1 3 3 Software ensures the DMA clock is running sufficiently fast to avoid transmit underflow This is based on system latency issues and will be worst case if the internal graphics controller on the ElanSC400 microcontroller is in use with a high resolution LCD panel with high color depth This is because the LCD controller will be accessing system DRAM constantly in order to keep the LCD panel fed with display data Operation at 8 or 16 Mhz is suggested See the Clock Control Register CSC index 82h 6 5 4 Software selects infrared mode via EAh 0 selects High Speed Infrared mode via the IrDA Control Register CSC index EAh 1 optionally enables High Speed Infrared mode IRQs via EAh 3 sets up infrared controller for transmit operation by clearing EAh 4 and then sets the START bit to begin the DMA operation Note that all EAh register accesses can be done via if desired 5 a result of the START_DMA bit being set an internal infrared port DMA request is generated by the infrared interface 6 DMA issues an internal infrared port DMA acknowledge signal to the requesting IrDA device
406. for Rows Columns Bytes Banks x Rows x Cols x Bits PageSize Refresh Cycles N A 2 MB 2x10x9x16 2 Kbyte 1024 4 MB 2x12x8x16 1 Kbyte 4096 8 MB 2x12x9x16 2 Kbyte 4096 16 MB 2x12x10x16 4 Kbyte 4096 32 MB 2x13x10x16 4 Kbyte 8192 64 MB 2x13x11x16 8 Kbyte 8192 N A N A 4 MB 2x10x9x32 4 Kbyte 1024 8 MB 2x12x8x32 2 Kbyte 4096 16 MB 2x12x9x32 4 Kbyte 4096 32 MB 2x12x10x32 8 Kbyte 4096 64 MB 2x13x10x32 8 Kbyte 8192 N A N A Note To use Table 9 5 first find the ASYM WIDTH and DEPTH values for the desired DRAM bank configuration in Table 9 3 Supported DRAM Bank Configurations on page 9 7 DRAM Controller 9 11 9 4 2 9 4 2 1 9 4 2 2 9 4 2 3 9 4 2 4 9 4 2 5 9 12 Timing and Control Signal Generation All memory controller timing is derived from a single clock which operates at 66 MHz if the CPU speed is 33 MHz or if the graphics controller on the ElanSC400 microcontroller is enabled When the graphics controller is disabled the memory clock operates at two times the CPU bus clock The lan SC400 and ElanSC410 Microcontrollers Data Sheet order 21028 shows all the relevant timing diagrams Page Mode and RAS Time Outs The DRAM controller uses the page mode capabilities of the DRAM whenever the CPU speed is greater than 8 MHz This can greatly spee
407. for either 16 or 32 bit ROM interface running in Fast mode DRAM Controller Chapter 9 The integrated DRAM controller provides the signals and associated timing necessary to support an external DRAM array with minimal software programming and overhead Internal programmable registers are provided to select the DRAM type and operating mode as well as refresh options A wide variety of commodity DRAMs are supported and substantial flexibility is built into the DRAM controller to optimize performance of the CPU and on the lanSC400 microcontroller the internal graphics controller which uses system DRAM for its buffers The DRAM controller supports the following features 3 3 V 70 ns DRAMs Up to four banks 16 bit or 32 bit banks Up to 64 Mbytes of total memory Self refresh DRAMs Fast page and Extended Data Out EDO DRAMs Two way interleaved operation among identically populated banks using fast page mode devices Mixed depth and width of DRAM banks in non interleaved mode Symmetrical and asymmetrical DRAM support Architectural Overview 1 7 1 2 6 1 2 6 1 1 2 6 2 1 8 Integrated Standard PC AT Peripherals The lanSC400 and ElanSC410 microcontrollers include all the standard peripheral controllers that make up a PC AT system Dual DMA Controllers Chapter 10 Dual cascaded 8237A compatible DMA controllers provide seven user DMA channels Of the seven internal channels fo
408. functions The typical usage is to configure the chip at boot time from system firmware and then set the termination latch bit one time after all the configuration is complete There may be times however when the chip is reconfigured after the system firmware has performed the initial chip configuration When all reconfiguration is completed the TERM LATCH bit must once again be set Note that it does not hurt to set the TERM LATCH bit over and over but it will probably negatively affect system operation to fail to set it after changing pin functions Appendix B includes a listing of pins and their respective termination control bits When any ofthe pin functions shown in Table B 1 are changed the TERM LATCH bit must be set CSC indexed registers that affect pad pull up pull down termination include 00 03h 14h 38 AO A5h D1h D2h DDh EAh and F2h Configuration Basics 2 7 2 8 Configuration Basics ESES o O AMDA 3 486 CPU 3 1 OVERVIEW The lanSC400 and ElanSC410 microcontrollers are based on the low voltage Am486 CPU core It includes the following features 2 3 3 V operation reduces power consumption Industry standard 8 Kbyte unified code and data write back cache improves both CPU and total system performance by significantly reducing traffic on the DRAM bus System Management Mode SMM facilitates designs requiring power management by providing a mech
409. g 2 2 indexed configuration register space figure 2 5 indexed register space table 2 3 Index 1 3 AMD LCD graphics controller indexed registers 2 3 PC Card indexed registers 2 4 RTC indexed registers 2 3 indirect mapped registers indexed registers 2 3 internal I O port address map table 2 2 methods 2 1 multiplexed pin configuration control table A 1 overview 2 1 pin multiplexing 2 7 pin termination 2 7 register spaces 2 2 system trade offs 1 16 Configuration Pin 0 signal See CFGO signal Configuration Pin 1 signal See 1 signal Configuration Pin 2 signal See CFG2 signal Configuration Pin signal See CFG3 signal Configuration RAM function 13 3 CPU Clock Auto Slowdown Register CSC index 81h function 6 1 CPU Clock Speed Register CSC index 80h function 6 1 6 11 usage 6 8 6 11 CPU See Am486 CPU CPUID instruction description 3 19 example 3 20 operation 3 19 timing 3 18 Critical Suspend mode See power management unit PMU CRO Register usage 3 3 Crystal Interface signals 32KXTAL1 32KXTAL2 signals CTS signal control 15 2 description 4 9 Cursor Address High Register graphics index OEh function 20 4 Cursor Address Low Register graphics index OFh function 20 4 Cursor End Register graphics index OBh function 20 4 usage 20 18 20 20 Cursor Start Register graphics index OAh function 20 4 usage 20 18 20 20 customer service FTP site iii hotlines ii
410. g 3 10 memory mapping and caching 7 12 requirements 3 4 restarting I O instructions 3 10 SMM initial register values table 3 8 SRAM state save map table 3 7 SRESET 4 40 SRESET interaction 3 17 state save map 3 6 System Management Interrupt SMI 3 5 generation 5 30 System Management Random Access Memory SMRAM 3 4 uses 3 3 Attribute Memory Select signals See REG_A REG_B signals Auto Line Feed Detect signal See AFDT signal Backup Battery Sense signal See BBATSEN signal BALE signal control 4 26 description 4 5 Battery Low and ACIN SMI NMI Enable Register CSC index 93h function 5 6 Battery Low and ACIN SMI NMI Status Register CSC index 97h function 5 6 Index 1 Battery Low Detect signals See BL2 BLO signals Battery Voltage Detect signals See BVD1_A STSCHG A BVD1 B STSCHG B signals Battery Voltage Detect signals See BVD2 A SPKR A BVD2 B SPKR B signals Battery AC Pin Configuration Registers A B CSC index 70 71 function 5 5 usage 5 12 5 25 5 26 Battery AC Pin State Register CSC index 72h function 5 5 usage 5 25 5 26 BBATSEN signal control 13 3 description 4 12 usage 4 2 13 7 Bidirectional mode See parallel port bits DEPTHx 9 5 DIR 14 6 DM 13 9 DSIZE 8 11 DV2 DVO 13 6 FAST ROM 8 11 FIFOEN 15 7 ID2 IDO 15 6 IRQ ENABLE 18 12 IRQF 13 6 PLLRATIO 6 6 RS3 RSO 13 5 SELDEVICE 15 7 SELMODE 18 11 18 1
411. g an external VL bus on that microcontroller W f either 32 bit DRAMs 32 bit ROMs or the VL bus is enabled the internal graphics controller on the ElanSC400 microcontroller is unavailable because of internal design constraints The lanSC400 and ElanSC410 microcontrollers provide an absolute minimum of dedicated ISA control signals Any additional ISA controls are traded with GPIOs or keyboard rows and columns B The SD buffer shares control signals with some of the GPIOs This buffer controls the high word of the D data bus 031 016 Note that using the SD buffer is optional The high word of the D data bus can be hooked up directly to devices that want the SD data bus SD15 SD0O Buffering aids in voltage translation or isolation for heavy loading B The R32BFOE signal buffers the high word of the D data bus 031 016 for 32 bit ROMs The control signal associated with the ROM32 buffer is shared with a keyboard row On the ElanSC400 microcontroller the parallel port is traded for PC Card Socket B It requires an external buffer and latch E The serial and infrared ports share the same internal UART Real time switching between the two is supported however only one is available at any given time B ROMCS2 is not connected to a dedicated pin Software may enable and map it to any of the 15 GPIO CS pins Architectural Overview Typical Mobile Terminal Design ElanSC400 Microcontroller Figure 1 3 INOH Y
412. gn issues 9 1 timing and control signal generation 9 12 CAS precharge delay 9 12 CAS pulse width 9 12 MWE generation 9 12 page mode and RAS time outs 9 12 refresh 9 12 DRAM Refresh Control Register CSC index 05h function 9 3 usage 9 12 Drive Strength Control Register A CSC index 06h function 9 3 Drive Strength Control Register B CSC index 07h function 9 3 DSIZE bit usage 8 11 DSR signal control 15 2 description 4 9 DTR signal control 15 2 description 4 9 Dual Scan Offset Address High Register graphics index 3Ch function 20 5 usage 20 33 20 35 Dual Scan Offset Address Low Register graphics index 3Dh function 20 5 Dual Scan Row Adjust Register graphics index 3Bh function 20 5 usage 20 33 DV2 DVO bits usage 13 6 DX Register usage 4 4 EAX Register usage 3 11 3 19 EBX Register usage 3 19 ECX Register usage 3 19 EDX Register usage 3 19 EFLAGS Register usage 3 9 Index 5 lanSC400 microcontroller block diagram 1 3 configuration basics 2 1 CPU cache 3 3 differences from lanSC410 microcontroller 1 2 distinctive characteristics 1 1 documentation set xxiii logic symbol figure 4 14 multiplexed pins figure 4 14 overview 1 5 address buses 1 14 Am486 CPU core 1 6 clock generation 1 6 data buses 1 13 DMA controller 1 8 DRAM controller 1 7 EPP parallel port 1 9 general purpose inputs outputs 1 11 graphics controller 1 12 interrupt control
413. h row 11 XX XX 1E78h row 12 0000h row 13 0000h Flat Mapped Graphics Modes In the flat mapped graphics modes the CPU views graphics memory as flat packed pixel linear map Pixel data is organized in memory as a linear array starting from the upper leftmost pixel and ending with the bottom rightmost pixel The packed pixel size may be set to 1 2 or 4 bits In all cases the leftmost displayed pixel uses the most significant bit s of a given byte in memory Table 20 9 shows some example memory configurations that are available for some screen pixel resolutions and memory window sizes Because graphics memory is shared with system memory the entire lower 16 Mbytes of system DRAM space is available for use as the graphics frame buffer Any memory that is not used to refresh the display may be used for other purposes there are no inherent boundaries between what may be considered graphics memory and system memory The base address of the frame buffer may be set to any 32 Kbyte boundary within the lower 16 Mbytes of memory by programming the Frame Buffer Base Address Register graphics index 4Dh With all memory and pixel configurations there will be some number of pages of screen memory different screens of data stored simultaneously in memory The screen controller address counter will wrap around to the beginning of the first page of the display buffer
414. h stations agree to connect at 1 15 Mbit s the SELMODE bit is set to 1 In this transfer mode whenever the receive FIFO is not empty an internal infrared port DMA request is generated If the DMA controller has been set up this will result in DMA transfers of data from receive FIFO to system DRAM Sequence of events 1 Software allocates space in system DRAM for a receive buffer 2 Same as Transmit Step 2 Infrared Port 18 11 18 4 2 12 18 4 2 13 18 12 3 51 3 4 Software selects infrared mode EAh 0 selects High Speed Infrared mode the IrDA Control Register CSC index EAh 1 optionally enables High Speed Infrared mode IRQs via CSC index EAh 3 and sets up infrared controller for receive operation by setting CSC index EAh 4 Note that all EAh register accesses can be done via one I O if desired 5 As soon as the receive FIFO has any data in it an internal infrared port DMA request is generated by the infrared controller to request that the data be transferred to system DRAM 6 Theinternal DMA controller issues an internal infrared port DMA acknowledge signal to the requesting IrDA device after the CPU relinquishes the bus 7 Memory write followed by read signals are generated by the DMA controller 8 The DMA controller executes the read cycle by moving the byte from the receive FIFO to the memory 9 The internal infrared port DMA acknowledge signal i
415. hange Interrupt Request signal rising edge can cause a wake up Only active if the IRQ is enabled in the interrupt controller Power Management AMD Figure 5 4 Suspend and Wake Up Resume Mode Flow Feature Default Feature Option SMI NMI Hyper Speed Enabled poe HYPER SPEED SUS RES amp SMI NMI N33 16 8 MH SUS RE 66 100 MHz SMINM Enabled amp SMI NMI Done Enabled 505 RES RES 305 nES SUS RES Ss _ MINMI 5 Done BET SMI NMI Wake up amp Last_mode SUSPEND Done lt SUS_RES T m SUS RES amp 5 SMI NMI IO Enabled Done amp BLO sus or BEI Low SPEED SUS_RES MODE 4 MI NMI Done qus nes SMI NMI SUS RES Ls Enabled SMI NMI lt 505 RES f done amp SMI NMI SMI NMI Enabled Done 7 505 RES SUS RES x y L LN S N y Z p N 2 vt X ES Ld je a Y 7 d g 23 u ACIN or BL2 or Wake up Pause to allow SUS RES Wake up SUS RES Power Supplies to come up BL2 8 SPEND MODE lt ACIN or BL2 or BL2 amp BL1 Wake up amp Wake up SUS RES Enabled Power Management 5 23 5 4 10 5 4 10 1 5 4 11 5 24 Gen
416. hat card is properly inserted Socket A is capable of being CD A2 configured to use two card detect inputs and socket B is only provided with one If only one card detect is to be used for a socket the input signals should be driven from a logical AND digital OR of the CD1 and CD2 signals from their respective card interfaces These pins are not supported on the lanSC410 microcontroller 4 10 System Interfaces Table 4 4 Signal Description Table continued Signal Type Description ICDIR O Card Data Direction controls the direction of the card data buffers or voltage translators It works in conjunction with the and MCEH card enable signals to control data buffers on the card interface When this signal is High the data flow is from the chip to the card socket indicating a data write cycle When this signal is Low the data flow is from the card socket into the chip indicating a read cycle This pin is not supported on the ElanSC410 microcontroller OE O PC Card Output Enable This is the PC Card memory read signal This pin is not supported on the ElanSC410 microcontroller MCEH MCEH B O Card Enables High Byte enables a PC Card s high data bus byte transceivers for the respective card interfaces These pins are not supported on the ElanSC410 microcontroller MCEL A MCEL B O Card Enables Low Byte enables a PC Card s low data bus byte transceivers for the respec
417. he DRAM device should be checked against the table to make sure the device is supported D Each bank s device type FPM or EDO can be set independently The device type must be set correctly and FPM and EDO devices may not be mixed in the same bank E If DRAMs requiring the MA12 signal e g asymmetric 8 Mbit or 16 Mbit depths are to be used the matrix keyboard interface may not be used see item F below Also in this case if all DRAM banks are 16 bits wide at least one of the enabled banks must be Bank 2 or Bank 3 to force proper output of the MA12 signal Any given set of banks can be enabled e g Bank 2 can be enabled without enabling Bank 0 or Bank 1 F Setting the width of Bank 0 or Bank 1 to 32 bits or enabling Bank 2 or Bank 3 causes the DRAM controller to pre empt ROW6 KBD ROWO If the internal matrix keyboard interface is to be used the following limitations apply All banks must be 16 bits wide because CASL2 CASL3 CASH2 CASHS are multiplexed with ROWO ROW1 KBD_ROW2 ROW Only two banks 0 and 1 may be used because RAS2 and RAS3 are multiplexed with KBD_ROW4 and KBD_ROWS5 Asymmetric 8 Mbit and 16 Mbit depth DRAMs are not supported because MA12 is multiplexed with KBD ROWS DRAM Controller 9 1 Bank 0 may be interleaved with Bank 1 and or Bank 2 may be interleaved with Bank 3 9 2 as long as the banks to be interleaved with each other
418. he PC Card controller are supported on ElanSC410 microcontroller Clock Control 6 3 AMD Table 6 2 Integrated Peripheral Clock Sources Source PLL Resultant Frequency Where Used Intermediate PLL 1 4746 MHz Low Speed PLL input 1 4746 MHz Low Speed PLL 36 864 MHz High Speed PLL input 36 864 MHz Graphics Dot PLL input 20 1 8432 MHz UART 2 18 4328 MHz UART 31 1 1892 MHz PIT Graphics Dot Clock PLL Programmable 20 736 36 864 MHz Graphics controller dot clock 36 864 1 36 864 MHz DRAM controller Graphics controller High Speed PLL 66 3532 MHz DRAM controller 66 3532 MHz Graphics controller 33 1776 MHz CPU VL bus controller 16 5888 MHz CPU VL bus controller DMA controller 8 2944 MHz CPU VL bus controller ISA bus controller ROM Flash interface DMA controller PC Card controller 4 1472 MHz CPU VL bus controller ISA bus controller ROM Flash interface DMA controller PC Card controller 2 0736 MHz CPU VL bus controller ISA bus controller ROM Flash interface DMA controller PC Card controller 1 0368 MHz CPU VL bus controller ISA bus controller ROM Flash interface DMA controller PC Card controller 6 4 Clock Control 6 4 1 1 Figure 6 3 Figure 6 4 6 4 1 2 AMD 32 KHz Crystal Oscillator The 32 KHz oscillator circuit is shown in Figure 6 3 and Figure 6 4 the only external component required for operation is a 32 768 KHz cry
419. he parallel port device has generated an interrupt request In PC AT Compatible and Bidirectional modes this signal is driven by the microcontroller to select the parallel port device In EPP mode this signal is driven active by the microcontroller when selecting the parallel port device and writes to the EPP address register In PC AT Compatible and Bidirectional modes this signal is driven by the microcontroller indicating to the parallel port device to insert a line feed at the end of every line i e carriage return In EPP mode this signal is driven active by the microcontroller during reads or writes to the EPP data registers In PC AT Compatible and Bidirectional modes this signal is used to indicate to the parallel port device to latch the data on the parallel port data bus In EPP mode this signal is driven active during writes to the selected parallel port device and writes to the internal EPP data or the EPP address register Note The initialization INIT error ERROR and the paper signals have the same function in PC AT Compatible Bidirectional and EPP modes 14 4 Parallel Port 14 5 14 5 1 14 5 1 1 Figure 14 2 14 5 1 2 OPERATION The parallel port can be configured in hardware as either a PC AT Compatible port or a Bidirectional EPP port In any mode a read or write to or from the data registers will generate the parallel port data write enabl
420. hich LCD is not displaying data Timer clock 1 1892 MHz PC AT standard is 1 19318 MHz speed on the ElanSC400 and ElanSC410 microcontrollers is 1 1892 MHz Clocked from CLK_IO pin For designs that need exact timer counts the CLK IO pin can be driven with the PC AT standard clock from an external oscillator 0 MHz Clock is stopped in Suspend mode because it does not need the timer active UART clock 1 8432 MHz or 18 432 MHz Programmable to use either speed can be changed at any time 1 8432 MHz is standard PC AT 18 432 MHz is support for 1 Mbit s serial infrared 0 MHz Clock is stopped in Suspend mode or when the UART is disabled via CSC index D1h 0 System clock 8 29 MHz 4 15 MHz 2 07 MHz 1 04 MHz 8 MHz in High Speed mode equals the CPU clock in Low Speed and Temporary Low Speed modes 0 MHz Clock stopped in Standby and Suspend modes Clock Control 6 9 Table 6 4 Clock Clock Speeds continued Programmable Speed Comments clock 32 KHz Always runs as long as there is power PMU clock 32 KHz Always runs as long as there is power DMA clock 16 59 MHz 8 29 MHz 4 15 MHz 2 07 MHz 1 04 MHz Follows CPU clock when it is operating 0 MHz Clock stopped when DMA is disabled or not in use High Speed PLL Low Speed and Intermediate PLL Graphics Dot Clock PLL Table 6 5 66 MHz 36 864 MHz 1 4746 MHz 20 736 MHz 36 864 MHz Bus Cycle Clock S
421. hould already be defined Programmable Interrupt Controller 11 3 AMD 11 4 1 IRQ Mapping Table 11 2 shows the resources of the lanSC400 and lanSC410 microcontrollers and the IRQs that these peripherals can be mapped to IRQ mapping in the ElanSC400 and ElanSC410 microcontrollers is programmable using CSC index registers and PC Card index registers Note that sharing interrupts i e steering two IRQ sources into the same IRQ line is not recommended and may lead to unpredictable system behavior Table 11 2 IRQ Mapping IRQ Number Microcontroller Resource Programmable Interval Timer Matrix Keyboard Controller Keyboard Output Buffer Full XT Keyboard Controller Shift Buffer Full UART 8 Pin Serial and Infrared Ports Parallel Port Real Time Clock Graphics Controller Cursor Control Address Register Accesses Matrix Keyboard Controller Mouse Output Buffer Full PC Card Sockets A and O and Memory mode IREQx pin Memory only mode status change RI gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt PIRQO Programmable IRQ I O Pin PIRQ1 Programmable IRQ I O Pin PIRQ2 Programmable IRQ I O Pin PIRQ3 Programmable IRQ I O Pin PIRQ4 Programmable IRQ I O Pin PIRQ5 Programmable IRQ I O Pin PIRQ6 Programmable IRQ I O Pin PIRQ7 Programmable IRQ I O Pin
422. i D15 DO signals control 9 3 usage 8 4 031 00 signals description 4 7 usage 1 13 4 18 8 5 9 1 9 4 Data Buffer Output Enable signal See DBUFOE signal Data Bus signals See 031 00 signals data buses 4 18 16 bit DRAM and 16 bit SD bus 4 19 32 bit DRAM and 16 bit SD bus 4 19 32 bit DRAM 16 bit SD and 32 bit ROM bus 4 19 byte lanes table 4 19 byte lanes by access target and type table 4 20 data paths 4 20 Data Carrier Detect signal See DCD signal Data Set Ready signal See DSR signal Data Terminal Ready signal See signal signal control 4 17 5 7 description 4 5 usage 8 5 8 7 9 1 DBUFRDH signal description 4 5 usage 8 6 8 7 9 1 DBUFRDL signal control 4 17 8 6 8 7 description 4 5 usage 8 7 9 1 DCD signal control 15 2 description 4 9 DEPTHx field usage 9 5 DIR bit usage 14 6 DM bit usage 13 9 DMA Address Enable signal See AEN signal DMA Channel 0 3 Extended Page Register CSC index D9h function 10 3 DMA Channel 5 7 Extended Page Register CSC index DAh function 10 3 DMA controller addressing DMA channels 10 5 16 bit channel address generation table 10 5 8 bit channel address generation table 10 5 autoinitialize 10 7 block diagram 10 3 channel mapping 10 8 DMA channel mapping table 10 8 Index initialization 10 9 latency 10 9 operation 10 5 overview 10 1 power management 10 9 registers 10 1 transfers 10 6 blo
423. iagram 4 26 bus speeds 4 29 command strobes 4 29 debugging 4 31 DMA cycle types table 4 30 10 8 echoing direct mapped PC AT registers 4 31 echoing extended registers 4 33 external buffer control signals 4 30 initialization 4 34 ISA Bus PC AT Bus Draft Standard 996 xxiv ISA signals table 4 28 operation 4 29 overview 4 25 power management 4 34 registers 4 25 shared signals table 4 28 8 3 16 5 supported ISA signals 4 28 J JTAG See test and debugging K KBD COL7 KBD COLO signals description 4 10 KBD ROW14 KBD ROWO signals control 16 4 description 4 10 Keyboard Column Register CSC index C7h function 16 4 usage 16 5 16 10 Index Keyboard Column Termination Control Register CSC index CAh function 16 4 Keyboard Configuration Register A CSC index COh function 16 4 Keyboard Configuration Register B CSC index C1h function 16 4 usage 16 9 Keyboard Input Buffer Read Back Register CSC index C2h function 16 4 keyboard interfaces initialization 13 1 16 13 matrix keyboard interface 16 1 16 5 block diagram figure 16 6 CPU scanned keyboard 16 8 key pressed interrupt 16 7 n key rollover example 1 figure 16 7 example 2 figure 16 7 shared signals table 8 3 16 5 timer 16 8 typematic support 16 9 wake up 16 8 operation 16 5 overview 16 1 power management 16 13 registers 16 3 SCP emulation 16 2 16 9 SCP GateA20 and reset CPU emulation 16 9 signal descrip
424. iator If the DMA clock is programmed for 16 MHz the ISA and PC Card DMA cycle timing will be non standard and may result in failures The DMA clock is controlled by CSC index 82h Addressing DMA Channels Channels 0 3 support 8 bit data transfers between 8 bit I O devices and system memory 8 bit DMA may access any location within the 64 Mbyte system address space however the address counter is only 16 bits wide so 8 bit DMA requests cannot cross 64 Kbyte physical page boundaries As shown in Table 10 2 during 8 bit DMA transfers the DMA slave controller provides the lower 16 bits DMA Page registers provide the next 8 bits and Extended Page registers provide the top 2 bits of the system memory address DMA Channel 4 is used to cascade channels 0 3 from the slave controller through the master controller to the CPU and is not available for data transfer Channels 5 7 support 16 bit data transfers between 16 bit devices and system memory 16 bit DMA may access any even word aligned location within the 64 Mbyte system address space however the address counter is only 16 bits wide so 16 bit DMA requests cannot cross 128 Kbyte physical page boundaries As shown in Table 10 3 during 16 bit transfers AO is 0 the master controller provides the next 16 bits Page registers provide the next 7 bits and Extended Page registers provide the top 2 bits of the system memory address 8 Bit DMA Channel Address Generat
425. ible Interrupts can be generated by either an installed PC Card or by the PC Card controller itself based on several events Either of these interrupt types can be routed to several target destinations on the ElanSC400 microcontroller by the PC Card controller Each socket can be configured to operate in one of two modes as defined by the PCMCIA Standard Release 2 1 Memory only mode or Memory and I O mode 19 6 PC Card Controller 19 5 1 AMD Memory only mode is the only mode originally defined in the PCMCIA Standard Release 1 0 This specification had no support for I O cards but defined the basic connector and card electrical and physical formats Memory and I O mode was added when support for I O cards was included in the PCMCIA Standard Release 2 1 Memory and mode redefines a few signals on the PC Card interface that were not often used or are memory card specific Although a memory card can be read when the PC Card controller is configured to be in Memory and I O mode the intent is that the interface be set up in Memory only mode if a memory card Flash SRAM ROM etc is inserted and in Memory and I O mode if an card is inserted ATA serial port modem network adapter etc The type of inserted and the system resources it requires can be read from the card CIS Card Information Structure which is defined by the PCMCIA Standard Release 2 1 This is typically the job of the PC Card and socket servic
426. ible by enabling their corresponding internal address decode by setting CSC index DOh 1 Note Subsequently turning off the index data port address decode by clearing CSC index DOh 1 does not disable any PC Card controller features windows etc that have already been turned on To completely disable the PC Card controller all features must be turned off individually and then CSC index DOh 1 must be cleared When the PC Card controller is disabled all of the CPU I O accesses to the Card controller indexed registers i e ports and 03E1h are driven to the ElanSC400 microcontroller s ISA or VL bus When the PC Card controller is enabled all writes to Port go to both the internal PC Card controller s index register and to the ISA or VL bus This is done to support the possibility of having a second 82365 compatible PC Card controller external to the ElanSC400 microcontroller to support two additional PC Card sockets C and D Reads from Port come from the internal PC Card index register only and are not seen on external buses The destination for I O reads or writes to the PC Card controller data port OBE1h depends upon the data that was last written to Port If the last data written to Port was 80 FFh then subsequent Port O3E1h accesses will go to the external ISA or VL bus only This will remain the case until new data that is between 00 7Fh is written to Port O3EOh at which time
427. icular resolution and pixel color depth multiply the LCD pixels in the X dimension by those in the Y dimension and multiply by the color depth number of BPP Divide the result by eight to get the number of bytes required to store a single screen s worth of data then divide 64 Kbytes or 128 Kbytes based on selection of 1 BPP or 2 4 BPP as explained earlier to get the number of screens that will fit into the graphics frame buffer Regardless of whether graphics or text mode is being used the frame buffer base address must be configured at system boot time The memory maps described above are then relative to the frame buffer base address This programming is done via the Frame Buffer Base Address Register and the Frame Font Buffer Base Address Register Low graphics index 4Dh and 4Fh The frame buffer base address for any of the above modes can be set to any 16 Kbyte boundary within the lowest 16 Mbytes of system DRAM when the frame Graphics Controller 20 9 20 4 2 3 3 20 4 2 4 20 4 2 5 20 10 buffer is 16 Kbytes and to any 32 Kbyte boundary within the lowest 16 Mbytes of system DRAM when the frame buffer is larger than 16 Kbytes Paged Mode The paged mapping mode is provided for use when CPU address space is limited such as in a Real mode only system When paged mode is enabled a 64 Kbyte frame buffer is available and can be located above 1 Mbyte using the frame buffer base address registers mentioned earl
428. ier This mode differs from other modes in that the software that is updating the 64 Kbyte graphics only text mode not supported frame buffer will not access it directly i e atthe address programmed into the frame buffer base address but rather via a special 16 Kbyte LDC graphics window that becomes available at 00B8000h in the CPU address space when paged mode is enabled Although the CPU can only access 16 Kbytes of the 64 Kbyte buffer at a time the graphics controller can access the entire 64 Kbytes at all times so that the frame buffer data can be used to constantly refresh the LCD screen Font Buffer The font buffer is used only in text mode and does not exist in any graphics mode The font buffer can be made to reside anywhere below 16 Mbytes in system DRAM on a 16 Kbyte boundary The font buffer is usedto hold pixel data that is used to form the ASCII characters available in text mode A piece of graphics hardware known as the character generator uses the ASCII codes stored in even addresses of the text frame buffer to look up the associated ASCII character bitmap data in the font buffer and then display it to the screen The font buffer is fixed at 16 Kbytes in size and can hold character bitmap data for characters up to 32 pixels in height and of 8 10 or 16 pixel in width There are 256 ASCII characters that must be supported by each set of text character fonts character bitmap is referred to as a font It is possible to sto
429. ight be an implementation of Advanced Power Management APM Operating systems may make BIOS calls to communicate APM information The BIOS will typically force an SMI to occur to exchange information with the SMI handler In this case the SMI handler requires knowledge of the format of the State Save Map so that it can examine or store register values Although the entire state of the CPU is written out to the State Save Map the format of some of the internal registers is subject to change and is not documented These areas in the map are marked No access in the table Some registers such as EAX may be altered by the SMI handler before returning These areas in the map are marked Read Write Other areas in the map can be read by the SMI handler but should not be altered because alteration would leave the CPU in an undefined state For example the segment selector registers such as DS CS etc can be read but should not be written because the internal hidden descriptor would no longer match the selector value These map areas are marked Read Only in the table Am486 CPU Table 3 3 SRAM State Save Map Offset from Length Permitted OFFFCh CRO Register Read only OFFF8h Register Read only OFFF4h EFLAGS Register Read Write OFFFOh EIP Register Read Write OFFECh EDI Register Read Write OFFE8h ESI Register Read Write OFFE4h EBP Register Rea
430. ignal goes active or a bit in the Battery AC Pin Configuration Register CSC index 70h 5 is set Leaving High Speed Mode The system leaves High Speed mode when any one of the following occurs A primary activity occurs and Hyper Speed mode is enabled Goes to Hyper Speed mode after the CPU core PLL is stable f Hyper Speed is enabled the system stays in High Speed mode for 1 ms only The High Speed mode timer times out Drops to Low Speed mode Programmed directly out with the PMU Force Mode Register go to any other mode The SUS RES signal toggles f enabled forces the system directly to Suspend mode B BLO or BL2 are asserted programmable option using CSC index 70 711 BL2 causes a mode change to Critical Suspend mode if enabled and ACIN is not active BLO causes a mode change to Low Speed mode if enabled and ACIN is not active Power Management 5 4 3 5 4 3 1 5 4 3 2 5 4 3 3 Low Speed Mode This mode is used when there is not a lot of CPU intensive activity in the microcontroller and the CPU clock can be slowed down for all CPU cycles Actions Taken During Low Speed Mode The following actions are taken in the ElanSC400 and ElanSC410 microcontrollers during Low Speed mode The CPU clock can be programmed to 8 MHz 4 MHz 2 MHz or 1 MHz in this mode A summary of clock speeds per PMU mode is shown in Table 6 6 The CPU clock is
431. in by asserting WAIT The host can then modify the address data on the data signals and change the state of the WHITE signal EPP Address Read To begin an address read cycle the host deasserts WHITE places the data signals in a high impedance state and then asserts ASTRB The peripheral responds by driving the data signals with the address byte and then deasserting WAIT to indicate that the address is valid When the host recognizes WAIT as inactive it reads the address from the data signals and deasserts ASTRB The peripheral places the data signals in a high impedance state acknowledges the end of the cycle then indicates that it is ready for the next cycle to begin by asserting WAIT The host can then drive the data signals and change the state of the WHITE signal Parallel Port 14 7 Figure 14 4 Write Cycle PPDWE PPOEN ASTRB AFDT DSTRB SD7 SDO BUSY WAIT DBUFOE DBUFRDL 14 5 2 3 3 14 5 2 3 4 14 8 Address Register Access Data Register Access X 5 Data Write To begin a data write cycle the host asserts WRITE drives the data signals and asserts DSTRB The peripheral responds by deasserting WAIT to indicate that it is ready to receive the data byte When the host recognizes WAIT as inactive it deasserts DSTRB to lat
432. inder operator Memory Byte Format CGA High Resolution Graphics Bit 7 Bit 0 PEL PEL PEL PEL PEL PEL PEL PEL Leftmost PEL Rightmost PEL Low Resolution Mode In the CGA low resolution mode each byte in memory contains information relating to four pixels The bytes are organized sequentially using the odd even format described in Figure 20 3 resulting in a screen resolution of 320x200 with four colors mapped to each pixel The byte offset and bit offset of a given pixel in the display coordinates origin located in the top left corner of the screen y increases positively in the downward direction x increases positively in the rightward direction may be calculated from x and y coordinates as follows Graphics Controller Figure 20 5 20 4 3 2 20 4 3 2 1 Table 20 2 20 4 3 2 2 Table 20 3 20 4 4 AMDA Byte offset 2 8192 2 80 4 C1 Bit offset msb 7 x964 2 CO Bit offset Isb 6 x 4 2 where is integer division with truncation is the integer modulus remainder operator Memory Byte Format CGA Low Resolution Graphics Bit 7 Bit 0 PEL PEL PEL PEL Leftmost PEL Rightmost PEL CGA Graphics Color Processing 320x200 Mode In CGAlow resolution mode the C1 and CO bits mapto RGBI colors as shown in Table 20 2 Color Mapping in CGA Low Resolution Mode Green Blue Intensity Port 03D9h 2 Port O3D9h 1 Port 03091 0 Port O3D9h 3 Port O3D9h 5 Port O3D9h 4 Port O3D9h
433. ing a WBINVD or INVD instruction Cache line fills are disabled Cache write throughs and cache invalidations are enabled This configuration allows software to disable the cache for a short time then re enable it without flushing the original contents Invalid setting A general protection exception with an error code of 0 is generated Cache line fills cache write throughs and cache invalidations are enabled This is the normal operating configuration Caching is controlled by the memory management subsystem on a per access basis For example ISA bus accesses are not cached The programmer has some control over which regions of memory are cacheable and which are not This is discussed in Chapter 7 SYSTEM MANAGEMENT MODE SMM System Management Mode SMM is a separate operating mode of the CPU apart from Real Virtual and Protected modes with distinct hardware and software features SMM is intended for use only by system firmware e g BIOS and not by application software or general purpose system software SMM lets the system designer add to computer products software controlled features that operate transparently to the operating system and software applications This section presents basic information on using SMM on the lanSC400 and lanSC410 microcontrollers more complete information is available in the Enhanced Am486 Microprocessor Family Data Sheet order 19225 Uses of SMM SMM provides an oper
434. ing refreshed The required refresh rate can be calculated by dividing the number of rows that must be refreshed by the required refresh interval For example if a DRAM part is organized as 2 Mbit x 8 with 11 row addresses meaning there are 2048 rows and 10 column addresses and must be refreshed in 32 ms the formula is 2048 rows 32 ms 64 Kbyte Rows s Some DRAM devices will internally refresh multiple rows per refresh request so the DRAM data sheet must be read carefully to understand the requirements of the particular device If the chosen DRAM devices require a refresh rate faster than 64 KHz note that no such devices are available at press time they must be refreshed using the programmable interval timer PIT and if the system is to support Suspend mode the DRAM must support self refresh because the PIT is disabled during Suspend mode When the self refresh bit in CSC index 051 is set whenever the CPU enters Suspend mode all system DRAMs are placed into self refresh mode by asserting CAS before RAS and then holding both signals active If the memory clock is 33 MHz or greater the RAS signal assertions and deassertions will be staggered turned on and off one strobe at a time to minimize switching currents and noise INITIALIZATION Complete source code of a sample application that initializes the DRAM controller and determines the type and size of the attached DRAM devices can be found at ftp ftp amd com pub epd e86
435. ion Slave Controller Extended Page Registers DMA Page Registers Channel x Memory Address Register 25 24 23 16 A15 A0 Table 10 3 16 Bit DMA Channel Address Generation Master Controller Extended Page Registers DMA Page Registers Channel x Memory Address Register 25 24 23 17 16 1 Controller 10 5 10 4 2 Table 10 4 10 6 DMA Transfers Because the ElanSC400 and ElanSC410 microcontrollers support the standard PC AT system architecture the method for DMA transfer complies with the Industry Standard Architecture ISA specifications The following general rules apply to DMA transfers on the ElanSC400 and ElanSC410 microcontrollers The DMA initiatoris the I O device that asserts DRQ This is always an I O device residing on either the ISA bus or PC Card bus or the infrared port and may be either 8 bits Channels 0 3 or 16 bits Channels 5 7 Note that the infrared port must be programmed as an 8 bit channel B The DMA target is the memory device being accessed by the I O device the DMA Initiator It is always a memory resource and may be either DRAM 16 32 bits ISA bus 8 16 bits or PC Card bus 8 16 bits as listed in Table 10 4 Note that ROMCSx and VL bus targets are not supported neither is a PC Card initiator to a PC Card target E Thetarget memory must be currently mapped into the CPU address space either linearly or using an MMS window This addr
436. ion or requiring hardware ROM fetches to get the scan code maps for each key press Due to these size and complexity constraints the matrix keyboard interface described in this chapter is custom to the ElanSC400 and ElanSC410 microcontrollers and hardware compatible with the PC AT However PC AT compatibility can still be achieved by using SMIs to capture the keystrokes and map them to the correct scan code for the CPU The lanSC400 and lanSC410 microcontrollers provide software and hardware support for SCP emulation and PC AT compatibility with the following features B The SCP Input Buffer Output Buffer Status Register for SCP software emulation B An interrupt for signaling that the Input Buffer has been written An interrupt for signaling that the Output Buffer has been read Hardware for generating the IRQ1 signal Hardware for emulating the SCP A20GATE command Hardware for emulating the SCP RESET CPU command XT Keyboard Interface The XT keyboard interface in the lanSC400 and ElanSC410 microcontrollers is compatible with IBM s PC XT keyboard consisting of clock and data inputs XT CLK and XT DATA to the ElanSC400 and ElanSC410 microcontrollers The XT keyboard interface includes the following features Compatible with IBM s PC XT keyboard Operates at speeds up to 250 KHz Keyboard Interfaces 16 2 REGISTERS A summary listing of the chip setup and control CSC indexed registers used
437. ion on pin termination INITIALIZATION The power management unit is enabled at power on reset The default mode is High Speed mode at an 8 MHz CPU clock Power Management 6 CLOCK CONTROL 6 1 OVERVIEW To support power management features the internal cores of the lanSC400 and ElanSC410 microcontrollers operate over a range of frequencies The PMU determines the optimal clock speed based on current system activities and programmable register values The lanSC400 and lanSC410 microcontrollers require only one 32 768 KHz crystal to generate all the other clock frequencies required by the system The output of the on chip crystal oscillator circuit is used to generate the various frequencies by utilizing four Phase Locked Loop PLL circuits An additional PLL in the CPU is used for Hyper Speed mode 6 2 REGISTERS A summary listing of the chip setup and control CSC and graphics index registers used to control the clocks on the ElanSC400 and ElanSC410 microcontrollers is shown in Table 6 1 Complete descriptions for all registers can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Table 6 1 Clocking Register Summary Description Register Address Clock Function Keyword in Register Set Manual Chip Setup and Control CSC Index Registers CPU Clock Speed Register 22h 23h CPU clock speeds in Hyper High and Low page 3 87 Index 80h Speed modes present spee
438. ircuit figure 6 5 clock generation figure 6 3 frequency selection control for graphics dot clock PLL table 6 6 Graphics Dot Clock PLL 6 6 Graphics Dot Clock PLL block diagram 6 7 High Speed PLL 6 7 High Speed PLL block diagram figure 6 7 integrated peripheral clock sources table 6 4 Intermediate and Low Speed PLLs 6 5 Intermediate And Low Speed PLLs block dia gram figure 6 6 clock source block diagram figure 6 2 clock speeds table 6 9 clocks CPU 1x clock 6 8 DMA clock 6 8 memory clock 6 8 RTC clock 6 8 System clock 6 8 timer clock 6 8 UART clock 6 8 initialization 6 11 operation 6 3 overview 6 1 power management 6 11 clock speed per PMU mode table 6 12 registers 6 1 Clock Control Register CSC index 82h function 6 1 usage 5 2 6 11 10 3 18 2 18 11 Clock Input Output signal See CLK 10 signal Column Address Strobe High signals See signals Column Address Strobe Low signals See CASL3 CASLO signals COM Line Control Register Port O3FBh usage 18 13 COM FIFO Control Register Port 2 usage 18 13 COM Line Control Register Port O2FBh usage 18 13 Command Timing Registers function 19 4 usage 19 7 19 13 19 17 configuration direct mapped registers 2 2 feature trade offs 1 16 2 7 indexed registers chip setup and control CSC registers 2 6 CSC indexed register map table 2 6 index and data I O port usage figure 2 5 indexed addressin
439. is configured for the Memory and I O mode The standard PC AT edge triggered interrupts are supported status change interrupt can be generated from changes in the following signals CD A CD B BVD1 A BVD1 B BVD2 A BVD2 B RDY A and RDY B for memory cards only The status change interrupts can be steered to any of the following system interrupts SMI NMI IRQ3 5 IRQ7 IRQ9 12 and IRQ14 15 The Card I O interface signals RDY A IREQ A and RDY B IREQ_B the PC Card function is indicated in parenthesis can be steered to any of the following system interrupts IRQ3 5 IRQ7 IRQ9 12 and IRQ14 15 The PC Card I O interface signals BVD1 A STSCHG BVD1 B STSCHG B the PC Card function is indicated in parenthesis can be steered to any of the following system interrupts NMI SMI IRQ3 IRQ5 IRQ7 IRQ9 IRQ12 and IRQ14 IRQ15 Socket Status Inputs A card status change interrupt for each socket can be generated by any of four different sources depending on the configuration of the Card Status Change and the Card Status Change Interrupt Configuration registers Refer to these register descriptions for details on how these four sources control the generation of the card status change interrupt for a socket The socket status inputs BVD1 x BVD2 x CD x and RDY x are used to generate the card status change interrupt indicating a socket status change Changes in the state o
440. isters 18 2 Slow Speed Infrared mode 18 1 18 3 18 4 hardware support 18 4 interrupts 18 4 serial data unit SDU figure 18 5 transmit and receive sections 18 4 UART serial data unit SDU figure 18 5 INIT signal control 14 1 description 4 9 initialization clocks 6 1 1 device 4 1 DMA controller 10 9 DRAM controller 9 13 general purpose input output GPIO pins 17 6 graphics controller 20 38 infrared port 18 13 ISA bus interface 4 34 keyboard interfaces 16 13 multiplexed pin configuration table A 1 parallel port 14 10 PC Card controller 19 22 PMU 5 36 programmable interrupt controller PIC 11 5 programmable interval timer PIT 12 6 real time clock RTC 13 9 ROM Flash interface 8 6 serial port UART 15 7 VL bus controller 4 38 Index Initialize Printer signal See INIT signal instruction set xxiv Interface Status Register PC Card index 01h 41h function 19 3 usage 19 21 Internal Graphics Control Register A CSC index DDh function 20 4 usage 4 35 20 33 20 35 20 38 Internal Graphics Control Register B CSC index DEh function 20 4 usage 20 31 20 38 Internal I O Device Disable Echo Z Bus Configuration Register CSC index DOh usage 4 26 4 31 7 2 10 3 13 2 19 3 Interrupt and General Control Register PC Card index 03h 43h function 19 4 usage 4 11 19 11 19 17 19 19 Interrupt Configuration Register A CSC index D4h functi
441. isters that can be disabled when particular internal features are disabled such as the following Keyboard controller ports 0060h and 0064h PC Card controller ports and OSE1h RTC ports 0070h 0071h UART ports COM1 at O3F8 03FFh and 2 at 02F8 02FFh B Parallel port LPT1 at 0378 037Fh and LPT2 at 0278 027 Internal graphics controller ports When these features are disabled accesses to these registers reads and writes will be treated as standard ISA bus cycles whether or not direct mapped register echoing is enabled System Interfaces 4 7 6 2 4 7 6 2 1 4 7 6 2 2 When the is enabled reads come from the internal register only When the is disabled reads come from the ISA bus only All read accesses that are not decoded as direct mapped register accesses or CSC indexed register accesses will occur on the external ISA bus with all enabled ISA control signals available Echoing CSC Indexed Registers CSC indexed register accesses can also be programmed to echo on the external ISA bus by setting CSC index DOh 5 In order to eliminate any bus contention and or cycle to cycle address conflicts on the external ISA bus the microcontroller will always force the CSC indexed register accesses to run at the ISA bus speed when echoing is enabled The CSC indexed register echoing feature is totally independent of the direct mapped register echoing feature CSC Ind
442. it 7 being the page select bit Figure 20 6 Graphics Mode Memory HGA Graphics Frame Buffer 87 Bank 0 7830 bytes Scan Lines Unused 362 bytes 87 Bank 1 7830 bytes Scan Lines Unused 362 bytes 32 Kbytes Page 0 87 Bank 2 7830 bytes Scan Lines Unused 362 bytes 87 Bank 3 7830 bytes Scan Lines Unused 362 bytes 87 Bank 0 7830 bytes Scan Lines Unused 362 bytes 87 Bank 1 7830 bytes Scan Lines Unused 362 bytes 32 Kbytes Page 1 87 Bank 2 7830 bytes Scan Lines Unused 362 bytes 87 Bank 3 7830 bytes Scan Lines Unused 362 bytes 20 14 Graphics Controller 20 4 4 2 Figure 20 7 Figure 20 8 20 4 5 20 4 5 1 AMD HGA Graphics Pixel Formats In the graphics mode each byte in memory contains information relating to eight pixels The bytes are organized sequentially using the interleaved format described above resulting in a screen resolution of 720x348 with two colors mapped to each pixel The byte offset and bit offset of a given pixel in the display coordinates origin located in thetop left corner of the screen y increases positively in the downward direction x increases positively in the rightward direction may be calculated from x and y coordinates as follows Byte offset 4 8192 y 4 90 x 8 Bit offset 7 x968 where is integer division with truncation 96 is the integer modulus remainder operator
443. it stuffing is done on all data from the start of the counter to a counter value of zero This count must include all of the bytes in the payload field plus the two CRC bytes The infrared transmit state machine does not automatically insert STA or STO flags It is up to the infrared driver software to load the transmit buffer with all of the flags CRC bytes and data and to load the proper transfer count into the DMA controller prior to initiating the DMA transfer For transmit operations the software should construct the transmit buffer to contain frame data as follows two STAs payload data 16 bit software generated CRC of the payload data one STO The DMA transfer count must be the sum of all bytes in the transmit buffer Failure to properly program the Frame Length Registers will result in the transmit state machine becoming locked up In order to recover from this type of software error a reset for the high speed transmit state machine has been implemented To activate it write any data to CSC index ECh This also clears the frame error status so be sure to read the error status before resetting the transmit state machine Frame Abort A frame abort can occur due to the following Blocking the infrared transmission path in the middle of the frame i Random introduction of infrared noise Intentional termination by the transmitter Regardless of what caused the aborted frame the receiver treats a frame as an aborted frame whe
444. ket B Inactive Inactive Active win 3 REG ACT 4 Socket A Active win 4 REG ACT Inactive Inactive 19 5 5 2 Table 19 15 19 5 6 19 16 4 Socket B Inactive Inactive Active win 4 REG ACT Configuring MMS Windows C F MMS windows C F are configured using a combination of PC Card index registers and CSC index registers PC Card Socket B Memory Window 1 4 configuration registers the PC Card index registers that are used to define the start address and the stop address ofthe window in the CPU address space the offset address and the window enable disable configuration Table 19 15 below shows the PC Card Socket B memory window resources that are used to configure MMS windows C F in Standard PC Card mode Note that if the integrated PC Card controller is disabled the CPU will not be able to access the PC Card index registers If the MMS C F windows are setup when the integrated PC Card controller is enabled and then the integrated PC Card controller is disabled the MMS C F windows would still be functional PC Card Socket B Memory Window Resources Used for MMS FE Memory PC Card Index Registers Used Window Control Window 0 None Window 1 46h 1 58 5Dh Window 2 46h 2 60 65 Window 3 46h 3 68 6Dh Window 4 46h 4 70 75h Using Enhanced PC Card Mode Enhanced mode is enabled by programming the MODE bit in the PC Card Mode and DMA Control Registe
445. l ROM x32 Buffer Output Enable signal See R32BFOE signal ROM Flash interface architectural overview 8 3 block diagram 8 2 configuration access speed 8 9 data width control 8 8 early chip select 8 10 other options 8 8 pin strap bus buffer options table 8 8 50 interface using pin straps 8 7 ROMCSx configuration dependencies 8 11 data bus usage 8 4 Fast Speed mode 8 9 initialization 8 6 memory management 7 6 Normal Speed mode 8 9 operation 8 3 overview 8 1 power management 8 11 registers 8 1 ROM decode example figure 8 5 ROMCSO Configuration Register A CSC index 23h function 8 2 usage 8 9 ROMCSO Configuration Register B CSC index 24h function 8 2 usage 8 9 50 signal usage 4 16 4 17 7 6 7 10 8 3 8 4 8 6 8 8 19 9 ROMCS 1 Configuration Register A CSC index 25h function 8 2 ROMCS Configuration Register CSC index 26h function 8 2 usage 8 9 Index 1 19 ROMCST signal usage 7 10 8 3 8 4 8 8 ROMCS2 Configuration Register A CSC index 27h function 8 2 ROMCS2 Configuration Register B CSC index 28h function 8 2 usage 8 9 ROMCS2 signal control 7 11 8 2 usage 8 3 8 8 17 7 ROMCS2 ROMCSO signals control 5 4 description 4 7 usage 5 35 8 11 ROMRD signal description 4 7 usage 8 3 8 6 8 10 ROMWR signal description 4 7 usage 8 3 Row Address Strobe signals See RAS3 RASO signals RS3 RSO bits usage 13 5 RST A signal de
446. l GPIO ISA Interface GPIO PC Card Power Control Scan Keyboard Columns IRQs XT Keyboard Interface Scan Keyboard Rows ISA Interface Scan Keyboard Rows DRAM Interface GPIO CS8 PIRQO lt lt 2 0 CS14 PCMA VPP1 KOKAT 505 RES KBD ROW14 AAA LCDD7 VL BE3 LCDD6 VL LDEV LCDD5 VL D C LCDD4 VL LRDY LCDD3 VL M TO LCDD2 W LCDD1 VL ADS LCDDO VERST M VL LC VL BET SCK VL BEO LCLK LVEE VL_BRDY LVDD BLAST DTR RTS SOUT CTS DCD DSR RIN SIN SIROUT SIRIN ACIN BL2 BLT BLO 10 GPIO CSO GPIO_CS1 GPIO CS2 DBUFRDIU _ 3 GPIO CS4 DBUFOE GPIO CS5 100516 GPIO CS6 IOCHRDY GPIO CS7 PIRQ1 GPIO CS9 TC GPIO_CS10 AEN _ 11 PDACKO GPIO C812 PDRQO GPIO CS13 PCMA VCC K GPIO15 PCMA_VPP2 GPIO16 PCMB_VCC GPIO17 PCMB_VPP1 GPIO18 PCMB_VPP2 GPIO19 LBL2 GPIO20 CD A2 KBD COL7 KBD_COL6 2 PIRQ7 3 BD COL1 0 XT_CLK DAT KBD_ROW13 R32BFOE KBD_ROW12 MCS16 KBD_ROW11 SBHE KBD_ROW10 BALE PIRQ2 ROWS PDRQ1 KBD ROW7 PDACK1 KBD_ROWG6 MA12 KBD ROWS RAS3 ROWA RAS2 ROWS CASH3 KBD_ROW2 CASH KBD_ROW1 CASL3 KBD ROWO CASL2 ElanSC400 Microcontroller 292 BGA Multiplexed Pins on the ElanSC400 Microcontroller MWE
447. lates the address in addition to choosing the space The DRAM ROMO ISA VL bus and on the ElanSC400 microcontroller PC Card Socket A spaces are each accessible to a degree using non translated memory management All spaces except the ISA VL bus are fully accessible using translated memory management Memory Mapping System Example CPU M S ROMO ROM1 ROM2 emay space DRAM 64 Mbyte 64 Mbyte 64 Mbyte 16 Mbyte 16 Kbyte A E 16 Kbyte m g 5 16 Kbyte x i 16 Kbyte 32 Kbyte MMS F 16 Kbyte Graphics Frame Buffer MMS 32 MMS Note MMS Windows C F are variable in size minimum 4 Kbytes and be located anywhere in the CPU memory address space except the lowest 64 Kbyte region of the CPU memory space on 4 Kbyte boundaries The Graphics Frame Buffer MMS Window is not supported on the ElanSC410 microcontroller Memory Management 7 5 Figure 7 2 Source Address Stop Source Address Start Note Address Translation Example CPU and DMA Source Destination Boot vector Boot vector Non translated linear Destination Stop Address Destination Start Address MMS Window have a fixed decode region the user supplies a destination start address only MMS Windows require the user to program the start and
448. ler 1 8 ISA bus interface 1 15 JTAG test features 1 13 keyboard interfaces 1 10 memory management 1 14 PC Card controller 1 11 PC AT peripherals 1 8 PC AT support features 1 9 power management 1 6 programmable interval timer PIT 1 9 real time clock RTC 1 9 ROM Flash interface 1 7 serial port UART 1 10 System interfaces 1 13 VESA Local VL bus 1 15 package dimensions xxiv pin designations xxiv register descriptions xxiv System considerations 1 16 System diagram with trade offs figure 1 18 typical mobile terminal design figure 1 17 thermal characteristics xxiv timing xxiv lanSC400 Microcontroller Revision ID Register CSC index FFh function 3 2 lanSC410 microcontroller block diagram 1 4 configuration basics 2 1 CPU cache 3 3 differences from lanSC400 microcontroller 1 2 distinctive characteristics 1 1 documentation set xxiii logic symbol figure 4 15 multiplexed pins figure 4 15 overview 1 5 address buses 1 14 Am486 CPU core 1 6 clock generation 1 6 data buses 1 13 DMA controller 1 8 DRAM controller 1 7 EPP parallel port 1 9 general purpose inputs outputs 1 11 interrupt controller 1 8 ISA bus interface 1 15 JTAG test features 1 13 keyboard interfaces 1 10 memory management 1 14 PC AT peripherals 1 8 PC AT support features 1 9 power management 1 6 programmable interval timer PIT 1 9 real time clock RTC 1 9 ROM Flash interface 1 7 serial port UAR
449. ll 32 GPIO signals can be programmed as inputs or outputs or to support their alternate function They are enabled as GPIO inputs at power on reset with pin dependent pull ups or pull downs enabled To change GPIO to be an output set the appropriate bit in GPIO Function Select Registers A F CSC index A0 A5h To select the alternate non GPIO pin function set the appropriate bit in Pin Mux Registers A C CSC index 38 3Ah To disable the pull up or pull down reset the appropriate bits in GPIO Termination Control Registers A D CSC index 3B 3Eh Note After changing to or from an alternate function or enabling or disabling pull up pull down be sure to set the Pin Termination Latch Command Bit in the Suspend Mode Pin State Override Register CSC index E5h 0 GPIO Pins and Simple Input GPIO pins are selected for simple input at power up with the exception of GPIO CS4 GPIO CS2 which can be selected as buffer control signals via a strapping option The input value of the pins can be read using the GPIO Read Back Write Registers A D CSC index A6 A9h Any of the following actions will disable simple input on the GPIO pin B Selecting the pin s alternate function via the Pin Mux Registers A C CSC index 38 3Ah Setting the GPIO s output bit CSC index A0 A5h to turn the GPIO into an output General Purpose Input Output and Programmable Chip Selects 17 5 2 17 5 3 17 5 3 1 17 5 3 2 AMD GPIO
450. ller xs 10 CONTROLLER AMD 10 1 OVERVIEW Direct memory access DMA permits data transfer between memory and peripherals without CPU involvement On the lanSC400 and lanSC410 microcontrollers dual cascaded 8237A compatible DMA controllers provide seven user DMA channels Of the seven internal channels four are 8 bit channels and three are 16 bit channels Since the lanSC400 and ElanSC410 microcontrollers support the standard PC AT system architecture the method for DMA transfer complies with the Industry Standard Architecture ISA specifications and will not be described in detail in this chapter Any two of the seven channels can be simultaneously mapped to the external DMA request acknowledge lines PRDQ1 PDRQO and PDACK1 PDACKO DMA transfers can be initiated by external ISA peripherals or by the serial infrared port and on the lanSC400 microcontroller the PC Card interface Sockets A and B Each of these internal peripherals has a field in its control register for specifying which DMA channel is to be used for the transfer Specific information about DMA transfers in the infrared port and the PC Card controller can be found in Section 18 4 2 9 and Section 19 5 7 respectively The DMA controller on the lanSC400 and ElanSC410 microcontrollers is software compatible with the PC AT cascaded 8237 controller pair Its features include Single block and demand transfer modes Enable disable channel controlle
451. lock Diagram 17 5 Infrared Port Block 18 3 Slow Speed 115 Kbits s Infrared 18 4 UART Serial Data Unit SDU 18 5 Slow Speed Infrared Mode SDU 18 5 High Speed Infrared Frame Format 18 6 High Speed Infrared Data Modulation 18 7 PC Card Controller Block Diagram 19 5 Merging WAIT signals from Sockets B 19 19 Card Detect Function for Socket 19 20 Graphics Controller Block Diagram 20 7 16 Kbyte Graphics Frame Buffer MMS Window Implementation 20 11 CGA Graphics Mode Memory 20 12 Memory Byte Format CGA High Resolution Graphics 20 12 Memory Byte Format CGA Low Resolution 5 20 13 Graphics Mode Memory 20 14 Memory Byte Format 0 0 000 cee 20 15 16 Grayscale Palette Mapping 1 20 15 CGA MDA 20 17 CGA Attribute 20 17 MDA Attribute
452. lock is in addition to the ISA memory region found in standard PC architecture between 640 Kbytes and 1 Mbyte An ISA window of 64 Kbyte granularity and programmable start location may be defined using registers at CSC index EO E2h This window is fully locatable throughout the first 16 Mbytes of system memory space and can have a maximum size of 16 Mbytes When this window is enabled and a memory access is detected in this region the ElanSC400 and ElanSC410 microcontrollers will execute the cycle on the ISA bus and the DRAM interface will not be activated This ISA window is not affected by the system DRAM write protect controls Any system DRAM that is located at the same address as this ISA window becomes invisible to the system unless it is accessed through the MMS or video buffer relocation The block is active for ISA memory even if the upper limit for other ISA accesses has been set to 1 Mbyte All ISA memory space is non cacheable Command Strobes The ISA command strobes MEMR and MEMW are asserted only for ISA cycles The IOR IOW command strobes are asserted for both ISA and PC Card cycles Separate memory strobes are provided for accesses to ROM and PC Card memory The ROM System Interfaces 4 29 interface uses dedicated ROMRD and ROMWR signals while the PC Card sockets use MCEL A MCEH A MCEL B and MCEH B Table 4 15 shows the eight ISA DMA cycle types and the command strobes generated by each ISA DMA Cy
453. look like that shown in Figure 20 13 only shaded area is used for display Figure 20 13 8x8 Font Example Figure 20 14 10x12 Font Example 20 22 Bit 14 13 12 11 10 9 8 Hex Data row 0 0030h row 1 0078h row 2 00CCh row 3 00CCh row 4 00FCh row 5 00CCh row 6 00CCh row 7 0000h The bit map for the letter A in a 10x12 font may look like that shown in Figure 20 14 only shaded area is used for display Bit 12 11 10 9 8 Hex Data row 0 000Ch row 1 001Eh row 2 X X 0033h row 3 X X 8061h row 4 X X 8061h row 5 X X 8061h row 6 X X 807Fh row 7 X X 8061h row 8 X X 8061h row 9 X X 8061h row 10 0000h row 11 0000h Graphics Controller AMD The bit map for the letter A in a 16x14 font may look like that shown in Figure 20 15 shaded area is used for display Figure 20 15 16x14 Font Example 20 4 6 Bit 71615 14131211 0 15 14 13 12 11 1019 8 Hex Data row 0 C003h row 1 X X FOOFh row 2 3C3Ch row 3 X X X X X X XX 1E78h row 4 XX XX 1E78h row 5 XX XX 1E78h row 6 X X X X X X XX FE7Fh row 7 XX XX FE7Fh row 8 XX XX 1E78h row 9 X X X X X X XX 1E78h row 10 XX XX 1E78
454. lows the ElanSC400 and ElanSC410 microcontrollers to operate as a normal VL bus motherboard controller in accordance with the VL Bus Standard 2 0 On the ElanSC400 microcontroller the VL bus is available only when the internal graphics controller is disabled The microcontroller s VL bus controller includes the following features 33 MHz operation at 3 3 V 32 bit data bus B Burst mode transfers B Register control of local bus reset VESA bus mastering and DMA transfers to and from the VL bus target are not supported VL memory is non cacheable Architectural Overview 1 15 1 3 SYSTEM CONSIDERATIONS Figure 1 3 shows the lanSC400 microcontroller as it might be used in a typical mobile terminal design Figure 1 4 and Figure 1 5 show more complex system designs for each microcontroller and the features that are traded for others because of pin multiplexing The ElanSC400 and ElanSC410 microcontrollers support a maximum of 4 banks of 32 bit DRAM but because the RAS and CAS signals for the high word and for banks 2 and 3aretraded for keyboard row signals the minimum system would have one or two banks of DRAM either Bank 0 or Bank 1 populated with 16 bit DRAMs The 12 signal for asymmetrical support is also traded with a keyboard row signal Because the VL bus and the graphics controller share control signals on the lanSC400 microcontroller use of the internal graphics controller is traded with havin
455. ly important for those systems that use an external RTC POWER MANAGEMENT Operation of the keyboard interfaces on the lanSC400 and lanSC410 microcontrollers is affected by the power management functions shown in Table 16 4 Keyboard Interfaces 16 13 Table 16 4 Power Management the Keyboard Interfaces Keyboard Interface Event Matrix keyboard key press Description Triggered by the falling edge of the internal keyboard controller s key pressed interrupt Power Management Effect eee eem Programmable PU access to internal keyboard ports 60h and 64h Triggered by the falling edge of the internal keyboard controller s chip select Programmable Keyboard timer time out Triggered by keyboard controller s timer time out interrupt Keyboard input buffer write Triggered by keyboard controller s input buffer write interrupt Keyboard output buffer read Triggered by keyboard controller s output buffer read interrupt Keyboard access 16 14 Reads and writes to ports 0060h and 0064h can cause an SMI through a trap Keyboard Interfaces EE 1 GENERAL PURPOSE INPUT OUTPUT AND PROGRAMMABLE CHIP SELECTS 17 1 OVERVIEW The lanSC400 and ElanSC410 microcontrollers support 32 general purpose I O pins GPIOs that be used on the system board There two classifications of GPIO available GPIOx signals where x
456. ly go to a Suspend mode and stay there until an unlock event occurs When an unlock event occurs in Critical Suspend mode the system will do one of the following Go to Suspend mode and wait for a wake up B Wake up if the unlock event is also programmed as a wake up Wake up if a wake up was sensed while the system was in Critical Suspend The unlock events that can be enabled are is toggled B 812 goes inactive 812 and go inactive Actions Taken During Critical Suspend Mode The following actions are taken in the lanSC400 and ElanSC410 microcontrollers during Critical Suspend mode Same as Suspend mode B Thesystemis locked in Critical Suspend mode as long as an unlock event does not occur The LCD panel shutdown sequence is accelerated The voltage and control signals to the panel will disable without regard to normal power down sequencing which is specified in graphics index 50 51h B PLLs shut down Entering Critical Suspend Mode The system goes to Critical Suspend mode when 812 goes Low programmable option and ACIN is not enabled or asserted Leaving Critical Suspend Mode The system leaves Critical Suspend mode when either of the following occurs B An unlock occurs Goes to Suspend mode An unlock that is enabled as a wake up occurs Forces the system to High Speed or Low Speed mode Power Management 5 4 7 5 4 7 1 5 4 7 2 AMD Temporary Low Speed Mode Te
457. lyzer that is capturing state mode data Simply making the ROM accesses noncacheable will cause the chip select and ROMRD signal to toggle for each ROM access Early Chip Select Controls exist for each of the ROM chip selects to specify chip select qualification Reducing the qualifiers brings the chip select out earlier which may be required under certain circumstances For Normal Speed mode read operations disabling the early chip select feature causes the chip select to come out when the address decode is true and the ROMRD or ROMWR command is asserted and an edge is seen on the internal ROM controller clock Normal Speed mode write operations to a Flash device for example require that the early chip select feature be enabled When the early chip select feature is enabled the chip select comes out as a result of address decode being true with no other qualification regardless of whether Normal or Fast Speed mode is configured For Fast Speed mode operations with the early chip select feature disabled the chip select comes out when the address decode is true and an edge is seen on the internal ROM controller clock In this case no qualification with the ROMRD or ROMWR command is performed Table 8 3 shows how various fields in the CSC indexed registers control configuration of the ROM Flash interface ROM Flash Interface AMD Table 8 3 ROMCSx Configuration Dependencies ROMCSx Data HOC ROMCSx Configuration Summary Bus Wid
458. mat chosen in the Line Control Register Reception of a frame is initiated when a start bit is received the SIN input is driven Low for one baud rate clock period This start bit allows the receiver to synchronize its clock with the sender s clock The receiver then clocks the next 5 8 bits into the Receive Buffer Register ports OBF8h 02F8h and then validates that the received parity is correct if enabled and that at least one stop bit is received Any errors are reported in the Line Status Register ports OBFDh O2FDh Serial Port UART 15 5 AMDA Figure 15 2 UART Frame 15 4 3 15 4 3 1 15 4 3 2 15 4 4 15 6 UART Frame gt Start lt Data Bits Stop Bit Bit Operating Modes The UART on the ElanSC400 and lanSC410 microcontrollers supports two different modes of operation 16450 Compatible Mode No FIFOs In this mode there is storage for only one byte to be transmitted and for only one byte of received data If a second transmit byte is written by the CPU before the first is moved from the Transmit Holding Register to the Transmit Serializer the second byte will be lost This situation can be avoided by waiting for a Transmit Holding Register Empty THRE interrupt or by polling the THRE bit If a received character is not read by the CPU before a second character is completely received the first character is lost and an overrun error occurs generating an interrupt
459. ments and software ftp to ftp amd com and log on as anonymous using your E mail address as a password Or via your web browser go to ftp ftp amd com Questions requests and input concerning AMD s WWW pages can be sent via E mail to webmaster amd com Documentation and Literature Free E86 family information such as data books user s manuals data sheets application notes the FusionE86 Partner Solutions Catalog and other literature is available with a simple phone call Internationally contact your local AMD sales office for complete E86 family literature Literature Ordering 800 222 9323 toll free for U S and Canada 512 602 5651 direct dial worldwide 512 602 7639 fax 800 222 9323 AMD Facts On Demand faxback service toll free for U S and Canada AMD TABLE OF CONTENTS PREFACE CHAPTER 1 INTRODUCTION XXI ElanSC400 and lanSC410 Microcontrollers xxi Purpose of This Intended Audience xxi Overview of This Manual Related Documents xxiv AMD Documentation xxiv Additional Information xxiv Documentation Conventions XXV ARCHITECTURAL OVERVIEW 1 1 1 1 lanSC400 and lanSC410
460. mmand CPU access to IDE hard drive Programmable Power Management Falling edge of address decode qualified with command 5 35 5 4 14 5 4 14 1 5 4 14 2 5 5 5 36 State Options PMU Modes Suspend State Options The lanSC400 and lanSC410 microcontrollers allow external board components to be left either powered in Suspend mode or powered off When an external component is left powered its inputs should not toggle or else power will be wasted The interface signals are held in an inactive state When the external component is to be powered off in Suspend mode the interface signals are held Low Any signal that is left High tries to power the device through an I O pin resulting in possible damage Three registers CSC index E3 E5h allow each interface group of pins to be individually programmed to a specific state in Suspend mode and allow for the overriding of pull ups and pull downs Power down groups for each pin are listed in the Elan SC400 and lanSC410 Microcontrollers Data Sheet order 21028 Programmable Pull Up and Pull Down Options The GPIO and GPIO CS pins all have default termination Four registers CSC index 3B 3Eh are used to enable or disable the default pull up or pull down resistors Any time the termination configuration is changed the TERM LATCH bit CSC index E5h 0 must be set to enable the current configuration See Section 2 4 2 and Appendix B for more informat
461. mode See parallel port PC AT port 4 39 overview 4 39 registers 4 39 PCMA VCC signal description 4 11 usage 19 20 PCMA VPP1 signal description 4 11 usage 19 20 PCMA VPP2 signal description 4 11 usage 19 20 PCMB VCC signal description 4 11 usage 19 20 1 14 AMD PCMB VPP 1 signal description 4 11 usage 19 20 PCMB VPP2 signal description 4 11 usage 19 20 PCMCIA See PC Card controller PDACK1 PDACKO signals control 4 25 10 3 description 4 6 usage 10 1 10 4 10 8 PDRQ1 PDRQO signals control 4 25 5 4 10 3 description 4 6 usage 5 22 10 4 10 8 10 9 PE signal control 14 2 description 4 9 Phase Locked Loops PLLs clock generation figure 6 3 clock sources table 6 4 control during Suspend mode 5 15 CPU PLL in Hyper Speed PMU mode 5 10 5 12 function 6 3 Graphics Dot Clock PLL 6 6 High Speed PLL 6 7 Intermediate and Low Speed PLLs 6 5 PIC See programmable interrupt controller PIC Pin Mux Register A CSC index 38h function 17 2 usage 5 22 17 6 Pin Mux Register B CSC index 39h function 17 2 usage 14 2 16 3 17 6 Pin Register C CSC index function 17 2 usage 16 3 17 6 Pin Strap Status Register CSC index 20h function 8 1 17 2 usage 7 6 7 11 pin termination 17 6 configuration 2 7 control table B 1 default pull ups and pull downs 5 36 TERM LATCH bit 2 7 pins multiplexed pins figure 4 14 4 15 pins See signals PIRQ1
462. mode change Note When EN HYPER CSC index 40h 6 is set any PMU Force Mode Register write that forces High Speed goes to Hyper Speed instead With EN HYPER set High Speed mode is not accessible through the PMU Force Mode Register Also after a wake up from Suspend the TIMEO NOW bit CSC index 41h 6 cannot be written to for at least 30 us Table 5 1 PMU Controller Register Summary Description Register Address PMU Controller Function Keyword in Register Set Manual PMU Mode Control and Status PMU Force Mode Register 22h 23h PMU mode force high speed clock delay timer page 3 51 Index 40h status speed up Suspend and Standby mode timer debug LCD operation in Standby Hyper Speed mode enable Low Speed timer reset PMU Present and Last Mode 22h 23h Read present and last PMU mode time out page 3 53 Register Index 41h current mode timer in Hyper Speed mode Hyper High Speed Mode Timers 22h 23h Timer values for dropping down to High Speed page 3 54 Register Index 42h and Low Speed modes from Hyper and High Speed Low Speed Standby Mode 22h 23h Timer values for dropping to Standby and page 3 55 Timers Register Index 43h Suspend modes from Low Speed and Standby Suspend Temporary Low Speed 22h 23h Timer values to count down in Temporary Low page 3 56 Mode Timers Register Index 44h Speed and Suspend modes NMI SMI service Wake Up Pause High Speed 22h 23h Timer values for stabilizing power supplies
463. mory 1 2 0r4bits per pixel packed pixel flat mapped graphics up to 640x240 480x320 with two mapping modes 16 Kbyte window with bank swapping to address up to 64 Kbytes of graphics frame buffer while consuming only 16 Kbytes of DOS Real mode CPU address space Direct mapped no bank swapping with locatable base address up to 128 Kbyte direct addressability Hercules Graphics mode emulation REGISTERS Graphics controller registers are indexed using I O ports 03D4h index and 03051 data for Color Graphics Adapter CGA mode and ports 03B4h index and 03B5h data for Monochrome Display Adapter MDA mode Different ports are used depending on the graphics mode selected The mode is selected using bit O of the Internal Graphics Control Register A CSC index DDh When MDA mode is selected the MDA index and data registers are located at ports O3B4h and O3B5h respectively in the address space When CGA mode is selected the CGA index and data registers are located at ports 03D4h and 03D5h respectively in the I O address space The graphics controller indexed registers are accessed using a two step process B write to the I O address port for the chosen mode is performed The data written is the index of the requested graphics controller register This I O write is followed by an I O read or write to the data port for the chosen mode This access causes the graphics contr
464. mple serial interface that makes it possible to test all signal traces with only a few probes The TAP can be controlled via a bus master The bus master can be either automatic test equipment or a component PLD that interfaces to the four pin test bus The test and debugging features on the ElanSC400 and ElanSC410 microcontrollers include the following elements Five pins BNDSCN TDI BNDSCN TMS BNDSCN BNDSCN_TDO and EN On the ElanSC400 microcontroller only BNDSCN EN pin is dedicated the other four are multiplexed with the PC Card controller signals All five boundary scan interface pins are dedicated on the lanSC410 microcontroller Test Access Port TAP controller Decodes the inputs on the Test Mode Select BNDSCN TMS line to control test operations B instruction Register IR The instruction codes select the specific test or debug operation to be performed and the test data register to be accessed Test Data Registers Boundary Scan Register BSR Device Identification Register DID and Bypass Register BPR The instruction and test data registers are separate shift register paths connected in par allel that have a common serial data input and a common serial data output connected to the TAP signals BNDSCN TDI and BNDSCN TDO respectively 21 2 BOUNDARY SCAN ARCHITECTURE 21 2 1 Enabling the Boundary Scan Interface Because the boundary scan interface is shared with the PC C
465. mporary Low Speed mode is a PMU mode that the programmer can use to handle events that occur when the PMU is currently in a clock off mode This mode is used to service a secondary activity or an SMI NMI from Standby mode and then return to Standby mode or to service the Suspend timer time out SMI NMI and then return to Suspend mode Temporary Low Speed mode may be entered when a secondary activity occurs Secondary activities are invoked as a result of events that do not need extensive CPU time to service so the PMU does not return to High Speed mode for them Instead Temporary Low Speed mode acts as a temporary low speed mode that has its own timer and returns to Standby mode if it was entered by a secondary activity A secondary activity that is received while in Temporary Low Speed mode causes the system to restart the Temporary Low Speed timer The Temporary Low Speed mode timer works differently that other mode timers When other mode timers time out the PMU transitions to the next lower power performance state When the Temporary Low Speed mode timer expires the PMU returns to the clock off state from which it was awakened to process the secondary activity in the first place When Temporary Low Speed mode is entered from Standby mode the Standby timer will be paused while in Temporary Low Speed mode The Standby timer then resumes its count down when it returns to Standby mode When Temporary Low Speed mode is entered from Suspend it ac
466. n 4 29 4 7 5 1 5 4 29 4 7 5 2 Addressing 2 2 4 29 4 7 5 3 Command Strobes 4 29 4 7 5 4 External Buffer Control Signals 4 30 4 7 6 Using the ISA Bus for Debugging 4 31 4 7 6 1 Echoing Direct Mapped PC AT Registers 4 31 4 7 6 2 Echoing CSC Indexed 4 33 4 7 7 initialization sss llle 4 34 4 7 8 Power Management 4 34 4 8 Local VL Bus 4 35 4 8401 4 35 48 2 Registers eee 4 35 4 8 8 Block Diagram ee 4 36 4 8 4 Operation 4 36 4 8 4 1 Address Interface 4 36 4 8 4 2 Data Interface 4 36 4 8 4 3 Normal Bus Cycles 4 37 4 8 4 4 Special Bus 4 37 4 8 4 5 Unsupported VL Bus Signal 4 38 4 8 5 Initialization RR RARI RR ERR 4 38 4 8 6 Power Management 4 38 4 9 PC AT 4 39 4 9 1 DE RA WERRIER ER 4 39 4 9 2
467. n ACIN is active ACIN can also be used as part of the Critical Suspend unlock scheme When the ACIN signal is enabled and active it causes the following to happen Forces the system into High Speed or Hyper Speed mode if Hyper Speed mode is enabled if it is in Low Speed Temporary Low Speed or Standby modes If it is in Suspend mode ACIN active does not cause a mode change unless programmed to be a wake up Forces most PMU mode timers time outs to be ignored by the PMU so the microcontroller does not time out and change modes The microcontroller can still go into Suspend mode through a SUS RES pin toggle or register force The Suspend mode timer remains operational when ACIN is active Disables BLO or BL2 from causing a mode or clock speed change unless it is also programmed as an SMI or a wake up The state of the ACIN signal can be read from CSC index 72h 3 Battery Low The three Battery Low pins BLO BL1 and BL2 are active Low signals that allow the system to monitor the state of the system batteries with up to three different levels The mode flows for these three signals are diagrammed in Figure 5 6 and Figure 5 7 As a result of the battery low monitoring the PMU can be programmed to reduce the CPU clock speed in High Speed mode disable High Speed mode and use Low Speed mode as the fastest mode or go to Critical Suspend Mode All three Battery Low inputs are negative edge triggered There is a 60 m
468. n is selected using the CFG3 pin the DBUFOE DBUFRDL DBUFRDH are driven from boot time on for all accesses to the peripheral data bus These three signals are to be used for the external system bus transceiver control See Table 4 8 for the CFG3 configuration definitions Configuration Enables the GPIO CS4 GPIO CS2 signals on the pins Enables the SD bus buffer control signals DBUFOE DBUFRDL and DBUFRDH on the I O pins BNDSCN EN Pin The BNDSON EN configuration pin see Table 4 9 is used to enable the boundary scan function I O pins The following pins are configured for their boundary scan function when BNDSON EN is asserted BNDSCN E BNDSCN TMS BNDSCN TDI BNDSCN System Interfaces 4 17 Table 4 9 4 5 4 5 1 4 18 Boundary Scan Function Configuration BNDSCN EN Configuration 0 Enables the PC Card function 1 Enables the boundary scan function DATA AND ADDRESS BUSES Data Buses The lanSC400 and ElanSC410 microcontrollers provide 32 bits of data that are divided into two separate 16 bit buses System Data SD Bus The system or peripheral data bus 015 00 is always 16 bits wide and is shared between ISA 8 or 16 bit ROM Flash and on the lanSC400 microcontroller the PC Card peripherals The system data bus can be directly connected to all of these devices In addition these signals are the upper word of the VESA local VL data bus
469. n seven or more consecutive 1s are received The abort terminates the frame immediately without waiting to receive the FCS field or a STO flag An abort will cause CSC index ECh 7 to be set Sending Back to Back Frames Transmission of back to back frames is allowed by butting the data i e payload data and wrappers for up to seven frames up against each other in the transmit buffer If two consecutive frames are not back to back the time delay between the last ending flag of the first frame and the start of next frame should be separated by at least seven bit times refer to frame abort sequence described in Section 18 4 2 7 Receiving Back to Back Frames When receiving frames there is no way to tell how big the frame will be before it is received To handle this software must allocate a receive buffer that is larger than all of the data that is expected to be received for all frames in the current frame sequence and set the DMA transfer count to that large number During receipt the DMA transfer count should never expire Software must rely solely on the Received Frame Complete RFC interrupt and the Receive Buffer Empty status bit to know when a frame or frame sequence is complete Infrared Port 18 9 18 4 2 10 18 10 In order to support back to back frames the infrared circuitry counts the bytes as they received Atthe end of receipt of a frame the byte count can be read from the Frame Length Registers CS
470. n start and stop addresses as well as an offset address After the use of these windows is enabled via resetting CSC index F1h 0 the windows are controlled using two registers in the CSC index space and the PC Card index registers normally used for Socket B Memory Windows 1 4 B The MMS Window C F Attributes and MMS Window C F Device Select registers CSC index 30h and 31h contain bits that control the device selection ROMO ROM1 ROM2 or and write protect and cacheability options for each of the windows The Address Window Enable Register for PC Card Socket B PC Card index 46h contains individual enables for these windows at bits 1 4 PC Card index registers 58 75h contain location information This is programmed as a start address which defines the start of the window in CPU address space a stop address which defines the end of the window in CPU address space thus implicitly defining the length and an offset address which should be programmed to the desired target address minus the Start Address Because MMS windows C F on the lanSC400 microcontroller share the memory mapping logic in the PC Card controller use of these windows places restrictions on PC Card socket use This may be unworkable in many designs especially those expecting to use standard card and socket services for two PC Card cards and those requiring translated PC Card timing or DMA See the description of the PC Card Mode and DMA Control R
471. nal description 4 11 usage 19 19 WAIT BRST bit usage 8 9 WAIT NBRST bit usage 8 9 Wake Up Pause High Speed Clock Timers Register CSC index 45h function 5 3 usage 5 2 Wake Up Source Enable Registers A D CSC index 52 55h function 5 4 Wake Up Source Status Registers A D CSC index 56 59h function 5 4 WE signal description 4 11 usage 19 13 19 17 WIDTHXx field usage 9 5 WP A IOIS16 signal description 4 11 usage 10 8 19 17 Index WP 01516 B signal description 4 11 usage 10 8 19 17 Write Enable signal See MWE signal Write Protect signals See WP A IOIS16 A WP B IOIS16 B signals Write Protected System Memory DRAM Window Overlapping ISA Window Enable Register CSC index EOh function 4 26 usage 4 29 XMI Control Register CSC index 9Dh function 5 7 usage 3 5 16 5 XT Keyboard Clock signal See XT CLK signal XT Keyboard Data signal See XT DATA signal XT keyboard See keyboard interfaces signal control 16 3 description 4 10 usage 16 2 16 12 16 13 XT DATA signal control 16 3 16 4 description 4 10 usage 16 2 16 12 16 13 Index AMD 25 1 26
472. nal may go High again after Suspend mode is reached Because system current consumption is reduced the voltage from the battery may rise When the BL2 signal is used as the Critical Suspend mode change signal all wake up sources can be detected and latched but they will not cause a wake up until the system is unlocked Unlocking the system from Critical Suspend is a programmable function The system is locked into Critical Suspend after a BL2 signal is seen active until one of the following unlock sources happens is seen active BL2 alone is seen inactive Both BL2 and are inactive These unlock sources do not automatically cause a wake up unless programmed as wake up sources They only disable the lock circuit so a wake up source can resume the system If the BL2 signal is enabled to cause an SMI NMI the system will still enter Critical Suspend in 55 us and then service the SMI NMI after the system wakes up When the system 15 active and the LCD is displaying data the BL2 force to Critical Suspend mode occurs without regard to normal LCD power sequencing The LVEE LVDD and LCD signals do not sequence off as they normally do when going to Suspend They all go inactive atapproximately the same time This is done so Critical Suspend mode is entered as quickly as possible A signal is available on the microcontroller to indicate when the microcontroller is locked into Critical Suspend mode by a BL2 the LBL2 signal
473. nals are used to select the appropriate I O device for the DMA transfer AEN is also asserted when DMA cycle is occurring internal to the chip AEN is also asserted for all accesses to the PC Card I O space to prevent ISA devices from responding to the signal assertions since these signals are shared between the PC Card and ISA interfaces BALE O Bus Address Latch Enable is driven at the beginning of an ISA bus cycle with valid address This signal can be used by external devices to latch the address for the current cycle BALE is also asserted for all accesses to the Card interfaces memory I O DMA cycles This prevents an ISA device from responding to a cycle based on a previously latched address DBUFOE O Data Buffer Output Enable is used to control the output enable on the external transceiver required to drive the peripheral data bus in local bus and 32 bit DRAM modes DBUFRDH O High Byte Data Buffer Direction Control controls direction of data flow through the external transceiver required to drive the peripheral data bus in local bus and 32 bit DRAM mode This is the control signal for the upper 8 bits of the data bus DBUFRDL Low Byte Data Buffer Direction Control controls direction of data flow through the external transceiver required to drive the peripheral data bus in local bus and 32 bit DRAM mode This is the control signal for the lower 8 bits of the data bus
474. ncluding the EPP 32 bit data registers hold the data read from or written to the parallel port 14 2 2 Chip Setup and Control Registers The following chip setup and control CSC registers are available Pin Mux Register B Setting bit 1 in this register enables the parallel port signals B Parallel Serial Port Configuration Register By default the internal parallel port is disabled the port is enabled by setting bit 2 of this register Bit 3 controls mapping the parallel port interface to one of the two locations LPT1 from ports 0378 037Fh or LPT2 from ports 0278 027Fh Parallel Port Configuration Register This register is used to configure the operation mode of the parallel port and to enable EPP mode time outs The default mode is PC AT Compatible mode Bidirectional or EPP mode must be enabled by setting the following bits To enable bidirectional data transfers set bit 1 to 1 To enable EPP mode set bit O to 1 Activity Monitor Registers For power management these registers report that the parallel port is the source of an activity Access SMI Enable and Status Registers These registers allow the user to determine that the parallel port is the source of a system management interrupt SMI This information can be used to power up an external peripheral for use before the peripheral is actually accessed by the I O cycle B interrupt Configuration Register E This register controls th
475. nd Qualification Register 17 3 GP CSB Address Decode and Mask Register 17 3 GP Address Decode Register 17 3 GP CSC Memory Address Decode and Mask Register 17 3 GP CSC Memory Address Decode Register 17 3 GP CSC D Memory Command Qualification Register 17 3 GP CSD Memory Address Decode and Mask Register 17 3 GPIO as a Wake Up or Activity Source Status Register A 5 4 GPIO as a Wake Up or Activity Source Status Register B 5 4 GPIO as a Wake Up or Activity Source Status Registers 17 2 GPIO Function Select Registers 17 2 1 17 registers continued registers continued GPIO Read Back Write Registers A D 17 2 Keyboard Row Register A 16 4 GPIO Termination Control Registers A D 17 2 Keyboard Row Register B 16 4 GPIO CS Function Select Register A 5 7 Keyboard Status Register Write Register 16 4 GPIO CS Function Select Register B 5 7 Keyboard Timer Register 16 4 GPIO CS Function Select Register C 5 7 LCD Panel AC Modulation Clock Control Register GPIO CS Function Select Register D 5 7 20 5 GPIO CS Function Select Registers A D 17 2 Light Pen High Register 20 4 GPIO to GPIO CS Map Register A 5 7 Light Pen Low Register 20 4 GPIO PMU to GPIO CS Map Register B 5 7 Linear ROMCSO Attributes Register 8 1 GPIO PMUA Mode Change Register 5 7 17 2 Linear ROMCSO Shadow Register 8 1 GPIO_PMUB Mode Change Register 5 7 17 2 Low Speed Standby Mode Timers Register
476. ndex 66h Activity source enable CPU access to ROMCSO0 and ROMCS2 ROMCS1 page 3 75 Activity Classification Register A 22h 23h Index Primary or secondary activity classification CPU access to 5 and ROMCS2 ROMCS1 page 3 79 Standard Decode to GPIO_CS Map Register 22h 23h Index B1h ROM Chip Select 2 ROMCS2 mapping to one of the GPIO_CS pins page 3 131 Suspend Pin State Register A 22h 23h Index E3h Status of ROM interface in Suspend mode powered not powered page 3 184 Suspend Pin State Register B 22h 23h Index E4h Status of R32FOE in Suspend mode page 3 185 Suspend Mode Pin State Override Register 8 3 22h 23h Index E5h BLOCK DIAGRAM Power Down Group B output signals three state when ROM interface remains powered in Suspend mode page 3 186 Figure 8 1 is a simplified block diagram showing all the external signals used by the ROM Flash interface More complex examples showing how these signals are used in different configurations can be found in Figure 4 3 Figure 4 4 and Figure 4 5 If the 32 bit ROM interface is enabled the matrix keyboard interface is not available and on the ElanSC400 microcontroller the internal graphics controller is unavailable The R32BFOE signal is shared with the KBD_ROW13 signal Note that unlike ROMCSO and ROMCS 1 ROMCS2 is not mapped to an external pin by default It can be mapped to any of
477. ndex E2h Window size for the overlapping ISA window page 3 183 Suspend Pin State Register A 22h 23h Index E3h Power control in Suspend mode for ISA bus interface page 3 184 Suspend Mode Pin State Override Register 4 7 3 22h 23h Index E5h Block Diagram Suspend mode override for ISA bus interface page 3 186 Block diagrams of the ISA interface are shown in Figure 4 7 and Figure 4 8 The ISA bus can be set up for either an 8 bit only configuration or an 8 16 bit configuration depending on the pin multiplexing options that are selected The two programmable DMA channels can use any available 8 or 16 bit DMA channel Inthe 8 bit only configuration shown in Figure 4 7 all bus cycles including DMA are performed as 8 bit transfers on the lower half of the SD data bus The single available DMA handshake pair can be routed to any available 8 bit channels In the 8 16 bit configuration shown in Figure 4 8 8 and 16 bit bus cycles can access 8 or 16 bit target devices 4 26 System Interfaces Figure 4 7 8 Bit Minimal ISA Interface lanSC400 Microcontroller Addresses SA23 SA0 Data SD7 SDO Command strobes AEN TC PDACKO 4 DMA Interrupts 4 PIRQO Reset RSTDRV Figure 4 8 16 Bit Maximum ISA Interface lanSC400 Microcontroller BALE Addresses SBHE SA23 SA0 015 00
478. ned to support shadowing slow ROM into faster DRAM the Linear ROMO Attributes Register CSC index 22h allows this shadowed memory to be write protected and or made cacheable On the ElanSC400 microcontroller in any region in the lower 16 Mbyte but typically in the range 00B0000 00BFFFFh for compatibility the internal LCD controller can be programmed to direct accesses to the frame buffer 32 128 Kbytes depending on graphics mode and the 16 Kbyte font buffer text modes only to DRAM in preference to ROM or ISA The Overlapping ISA Window Start Address and Overlapping ISA Window Size registers CSC index E1 and E2h can be programmed to force accesses that would normally default to DRAM to go to the ISA bus instead The primary use for this is to allow systems that have 16 Mbytes or more of DRAM to support ISA peripherals that require a large memory window without relying on ISA bus aliasing The 64 Kbytes at the top of CPU address space 3 FFOOO0 3FFFFFFh which defaults to ROMO can be redirected to DRAM by setting bit 3 in CSC index register 21h Boot code should normally do this because in most systems there is no reason to access ROMO at that address range after the first instruction fetch When System Management Mode SMM is entered an SMI the 32 Kbyte area where the system state is stored and where SMM execution starts is automatically mapped to DRAM This allows SMM RAM to be mapped in a location such as 00A
479. nfiguration Control continued Signals You Give Up Signal You Want How to Configure the Signal You Want on the Pin KBD COLO XT DATA Clear CSC index 39h 3 ROW13 R32BFOE Do not enable the 32 bit ROM interface on ROMCSO e g do not hardwire strap both the CFG1 and CFGO pins High ROW12 MCS16 Clear CSC index 39h 2 KBD ROW11 5 Clear CSC index 39112 KBD ROW10 BALE Clear CSC index 39h 2 KBD_ROW9 PIRQ2 Clear CSC index 39h 2 KBD_ROW8 1 Clear CSC index 39112 KBD ROW7 PDACK1 Clear CSC index 39h 2 KBD_ROW6 MA12 Clear bit 3 of the DRAM Bank x Configuration Register KBD_ROW5 RAS3 Clear bit 3 of the DRAM Bank x Configuration Register KBD_ROW4 RAS2 Clear bit 3 of the DRAM Bank x Configuration Register KBD ROWS CASH3 Clear bit 3 of the DRAM Bank x Configuration Register KBD_ROW2 CASH2 Clear bit 3 of the DRAM Bank x Configuration Register KBD_ROW1 CASL3 Clear bit 3 of the DRAM Bank x Configuration Register KBD_ROWO CASL2 Clear bit 3 of the DRAM Bank x Configuration Register PC Card Controller ElanSC400 Microcontroller Only BVD1 B GPIO25 ACK Write CSC index S9h 1 0 to 01 BVD2 B GPIO24 BUSY Write CSC index 39h 1 0 to 01 CD A2 GPIO20 Set CSC index 0 CD B GPIO27 ERROR Write CSC index 39h 1 0 to 01 LBL2 GPIO19 Set CSC index 39h 4 MCEL A
480. nfiguration and control registers Some of these registers are accessed directly without using an indexed addressing scheme Many of the PC AT legacy registers fall into this category An example of a direct mapped register is the System Control Port A Register which can be accessed using x86 assembly language shown below Note that accesses to direct mapped registers with 8 bit addresses can omit the use of the DX Register in AL 92h Read the register mov AL 1 out 92h AL Write a value of 1 to System Control Port A Accesses to direct mapped registers with 16 bit addresses must use the DX Register as is the case for any x86 compatible CPU as follows mov DX 3FFh mov AL OAAh out DX AL Write a value of AAh to the serial port scratch register Table 2 1 shows a summary of the direct mapped registers that are implemented in the ElanSC400 and ElanSC410 microcontrollers Internal I O Port Address Map 2 2 Internal I O Device Address Range Slave DMA DMA1 0000 000Fh Master Programmable Interrupt Controller PIC 0020 0021h CSC Index Data 0022h 0023h Programmable Interval Timer PIT 0040 0043h Keyboard 0060h 0064h System Control Port B NMI Status 0061h RTC Index Data 0070h 0071h General 8x Registers 0080h 0084 0086h 0088h 008C 008Fh DMA Page Registers 0081 0083h 0087h 0089 008Bh System Control Port A 0092h Slave PIC 00A0 00A1h Master DMA DMAO 00 0 00 even addresses only
481. ng the divide value in the feedback divider as shown in Table 6 3 The Graphics Dot Clock PLL requires a stabilization period after changing frequency Figure 6 6 shows the block diagram for the Graphics Dot Clock PLL The Graphics Dot Clock PLL is not available on the lanSC410 microcontroller Frequency Selection Control for Graphics Dot Clock PLL PLLRATIO 2 0 Divider Output Frequency 000 9 20 736 MHz 001 23 04 MHz 25 344 MHz 27 648 MHz 29 952 MHz 32 256 MHz 34 56 MHz 36 864 MHz Clock Control AMD Figure 6 6 Graphics Dot Clock PLL Block Diagram VCCA Fr Up Loop Filter 36 864 MHz 16 m Charg p Detector Dow Pump Cy Ff R C2 PLLRATIO 2 0 Programmable Fo m Co 20 736 36 864 MHz vco Internal External 6 4 1 4 High Speed PLL The High Speed PLL generates a 66 3552 MHz clock for the DRAM controller Figure 6 7 shows the block diagram for the High Speed PLL The input to the High Speed PLL is the output of the Low Speed PLL divided by 5 The feedback divider is 9 which results in a output frequency Fo of 66 3552 MHz This frequency is divided by two in the PMU to provide the 33 MHz input for the PLL in the CPU core Figure 6 7 High Speed PLL Block Diagram
482. ng to load CS to another segment register because the base value will not match the selector When the SMI handler is invoked the CPU s PE and PG bits in CRO are reset to 0 to disable paging The processor is in an environment similar to Real mode but without the 64 Kbyte limit checking However the default operand size and the default address size are set to 16 bits The EM bit is cleared so that no exceptions are generated Am486 CPU AMD Because the segment bases other than CS are cleared to 0 and the segment limits are 3 5 6 set to 4 Gbytes the address space may be treated as a single flat 4 Gbyte linear space that is unsegmented The CPU is still in Real mode and when a segment selector is loaded with a 16 bit value that value is then shifted left by 4 bits and loaded into the Segment Base Register Loading a selector does not alter the limit or attributes in the hidden part of the descriptor In SMM the CPU can access or jump anywhere within the 4 Gbyte physical address space However because the CPU is in a mode similar to Real mode the following restrictions apply Address prefix overrides are required to reach any address greater than 1 Mbyte Because segment addresses are simply the selector value shifted left 4 bits only the first 1 Mbyte may be addressed without an override both for data accesses and for control transfers B If SMBASE has been relocated reloading CS with 30001 e g via a far return or I
483. ning relatively slow microcode Failure to do this can cause the XT KB to generate a continuous stream of SMIs mov loop and out cx 0ffffh Short delay al 7fh 611 1 ai 1 96h 22h al ai 1 23h 1 0 Try97 23h al 80h al L 0 ai 1 96h dx al Enable the XT kb interface again Am4869 CPU 3 5 10 Try97 Try9B Try9C ExitSmm mov out db CodeLen2 code ends end go al 9Ch 226 1 1 238 0 ExitSmm 23h al al 9CR dx al al bl 22h al OFh OAAh EQU C odeFrag2 SMM Interaction With SRESET The Am486 CPU NMI and SMI input signals are edge triggered The Am486 CPU core clears all internal NMI and SMI events upon receipt of the SRESET signal Internal to the lanSC400 and ElanSC410 microcontrollers the NMI and SMI signals are asserted once andare then held in the asserted state until the source for the interrupt is cleared Therefore an SRESET event that is subsequent to or concurrent with the assertion of one of these interrupts clears the interrupt internal to the CPU even though the external PMU logic is asserting the SMI or NMI signal As a result the interrupt handler is never called to clear Am4869 CPU restore index 22h AMD return from SMI Resume instruction 3 17 3 6 3 6 1 3 18 the PMU logic and no new edge is ever generated to the CPU on these signals C
484. nitialization 6 11 6 6 Power 6 11 Table of Contents 7 MEMORY MANAGEMENT 7 1 TA OVerVIOW xL Ug wu bue F r UR 7 1 4 2 7 1 7 3 Address Decoding and 7 3 7 3 1 Internal Address Bus Size 7 3 7 3 2 Special Handling for A20 7 3 7 3 8 of Memory CPU Execution 7 3 7 3 4 ISA Bus Addressing 7 4 7 4 Multiple Memory Spaces 7 4 7 5 Non Translated Memory 7 6 7 5 4 ROMO and Non Translated Memory Management 7 6 7 5 2 DRAM and Non Translated Memory Management 7 7 7 6 Translated Memory Management 7 8 7 6 1 MMS Windows A and B 7 8 7 6 2 MMS Windows D E and F 7 9 7 6 8 Graphics Frame Buffer MMS Window 7 9 7 6 4 Card Memory Management 7 10 7 6 4 1 Standard 82365 PC Card 7 10 7 6 4 2 Simplified PC Card 7 10 7 7 System Considerations 7 11 7 7 1 2 7 Volt Operation
485. nitialized before the keyboard timer function can be used This is particularly important for those systems that use an external RTC The timer can be used to support key debounce typematic keys and to keep the CPU scanning the keyboard These three different rates are as follows Debounce Typically 5 40 ms depending on the key switch characteristics Typematic support The PC AT standard calls for a delay the time a key is held down until the typematic support begins of 250 ms to 1 second 250 ms intervals The typematic period interval from one key output to the next is 2 to 30 characters per second 33 500 ms per key output at a variable rate defined by the following equation Period 8 A x 28 0 00417 where A and B are programmable by the system Keyboard Interfaces 16 3 1 6 16 3 2 16 3 2 1 The keyboard timer will not support this exact equation the resolution of the timer is small enough and the range broad enough to work without a noticeable difference CPU scanning A good touch typist can type 50 words per minute this equals 250 keystrokes per minute or about 5 keystrokes per second This indicates the keyboard should be scanned every 200 ms to look for a new key press Typematic Support The typematic the feature is the keyboard automatically repeating a key at a programmable rate as long as a key is held down after it has been pressed a predetermined amount
486. nnels The timer channels are programmed by first writing a control word into the PIT 1 Mode Control Register and then writing an initial count into the count register of the timer channel being programmed The control word determines the format of the initial count A new initial count can be written at any time without affecting the programmed mode The mode definitions describe how counting is handled in each mode The new count must follow the programmed count format The channel must be read without disturbing the count in progress There are three possible methods to accomplish this a simple read operation counter latch command and read back command Simple read operation The count value in the count latch of the counter is read It should be noted that simple reads will not always return a correct value The two methods that follow are the preferred way of reading the current count Counter latch command This command is written to the PIT 1 Mode Control Register and acts like a control word The SC1 SCO bits select one of the three channels two other bits RW1 and RWO distinguish this command from a control word Read back command Also written to the PIT 1 Mode Control Register It allows the user to check the count value programmed mode and current state of the output of the chosen channel INITIALIZATION The programmable interval timer is enabled at power on reset After power up the state of the timer it
487. ns to be loaded into their corresponding BSR locations I O pins are selected as input RUNBIST or output depending on the value loaded into their control setting locations in the BSR Values shifted into input latches in the BSR are never used by the internal logic of the ElanSC400 and ElanSC410 microcontrollers Note After using the EXTEST instruction the ElanSC400 and ElanSC410 microcontrollers must be reset before normal non boundary scan use SAMPLE PRELOAD The instruction code is 0001 The SAMPLE PRELOAD instruction has two functions that it performs When the TAP controller is in the Capture DR state the SAMPLE PRELOAD instruction allows a snapshot of the normal operation of the component without interfering with that normal operation The instruction causes BSR cells associated with outputs to sample the value being driven by the microcontroller It causes the cells associated with inputs to sample the value being driven into the microcontroller On both outputs and inputs the sampling occurs on the rising edge of BNDSCN_TCK When the TAP controller is in the Update DR state the SAMPLE PRELOAD instruction preloads data to the device pins to be driven to the board by executing the EXTEST instruction Data is preloaded to the pins from the BSR on the falling edge of BNDSCN_TCK IDCODE The instruction code is 0010 The IDCODE instruction selects the DID to be connected to BNDSCN_TDI and BNDSCN_TDO allowing the device iden
488. nst other functionality the designer will usually be constrained in choosing which GPIO pins to use for which functions Figure 17 1 shows the mapping of GPIO pins to alternate functions Choosing between GPIOs and alternate functions is done by functional groups within the Pin Mux Registers A C CSC indexed registers 38 3Ah except for the buffer control group GPIO CS2 GPIO 54 which is selected via pin strapping at reset In addition to the alternate function trade offs the following should also be considered when selecting which GPIO pins to use All GPIOs are by default terminated by either pull ups or pull downs depending on alternate function The termination can be disabled but should be considered when deciding which GPIO to use For example if a GPIO that is pulled down by default is to be used for a chip select the internal pull down will have to be overridden by a stronger external pull up resistor or else the external device will see its chip select active at reset This also has power implications when the chip select is active current will be flowing through the pull up resistor See Section 2 4 2 and Appendix B for more information on pin termination GPIO31 GPIO15 are only capable of simple I O They can be set to be High Low or not driven and can be read back GPIO CS14 GPIO CSO have the I O capabilities of GPIO31 GPIO15 and additional chip select PMU and SMI NMI capabilities INITIALIZATION A
489. ntroller is shown in Figure 21 3 Figure 21 3 Controller State Diagram 1 CC Test Logic Reset i 1 1 0 Run Test ldle Select DR Scan Select IR Scan 21 3 1 21 3 1 1 0 Capture DR Capture IR SA 0 1 1 0 1 0 Pause DR 2 Pause IR 22 0 1 Update DR Update IR A Controller States Test Logic Reset State In this state the test logic is disabled so that normal operation of the device can continue unhindered This is achieved by initializing the instruction register such that the IDCODE instruction is loaded No matter what the original state of the controller the controller enters Test Logic Reset state when the BNDSCN TMS inputis held High 1 for atleast five rising edges of BNDSCN_TCK The controller remains in this state while BNDSCN TMS is High The TAP controller is also forced to enter this state at power up Test and Debugging 21 5 21 3 1 2 21 3 1 3 21 3 1 4 21 3 1 5 21 3 1 6 21 3 1 7 21 6 Run Test Idle State This is a controller state between scan operations When in this state the controller remains in this state as long as BNDSCN TMS is held Low For instructions not causing functions to execute during this state no activity occurs in the test logic The instruction register and all test data registers retain their previous state When BNDSCN TMS is High and a rising edge is applied
490. nutes and hours of the day Counts days of the week date month and year 12 24 hour clock with AM and PM in 12 hour mode 14 bytes of clock and control registers 114 bytes of general purpose RAM Three interrupts are separately software maskable and testable Time of day alarm is programmable to occur from once per second to once per day Periodic interrupts can be continued to occur at rates from 122 us to 500 ms Update ended interrupt provides cycle status The RTC has its own reset and power pin separate from the rest of the core supplies When the chip is powered off the RTC can remain powered up and in full functional mode maintaining time calendar and user RAM data The RTC includes ten registers for time calendar and alarm data and four general purpose registers named A B C and D Register D has a status bit that indicates the validity of the contents of the RAM time registers and the calendar This status bit is set based on the power supply level on the RTC Vcc supply pin VCC_RTC The RTC alarm function is Supported The RTC interrupt request is connected internally to IRQ8 This along with other IRQs may be configured as the system power management unit s wake up activity Note The RTC must be initialized correctly to provide proper function of the matrix keyboard timer and on the ElanSC400 microcontroller the internal graphics controller This initialization must occur regardless of whether the int
491. o allow the PMU to remain in any mode except for the Temporary Low Speed timer The PMU mode timers when used in conjunction with activities and wake ups can provide power management control that is transparent to the operating system Temporary Low Speed is a temporary mode Its timer has a default minimum so that the PMU returns to the appropriate mode soon after the event that sent it to Temporary Low Power Management 5 9 5 4 1 5 4 1 1 5 10 Speed mode is done The appropriate mode is dependent on entry conditions and other configurations this can be determined by examining the flowcharts shown in Figure 5 3 Figure 5 8 This timer is different than the other mode timers in that respect The timer has no disable It does not cause the PMU to stay in Temporary Low Speed mode it always continues on to another mode This timer allows a system design that only goes as low as Standby mode but will still service secondary activities and then return to the low power Standby mode rather than getting stuck in Temporary Low Speed mode Again this feature provides for hardware only power management that automatically trades off processing performance with power consumption based on the real time needs of the System Hyper Speed Mode Hyper Speed mode is used when performance is much more valuable than battery life Hyper Speed mode utilizes the CPU s clock multiplying capability to run the CPU at 66 MHz 2x or 100 M
492. o this table using the x86 SI register and then use the x86 OUTSW out string word to write the desired data to the specified indexed register This 16 bit I O write with the OUTSW instruction is broken down internally into the two required 8 bit writes to the respective index and data registers Figure 2 1 and Figure 2 2 show the configuration and control registers spaces graphically Configuration Basics AMD Figure 2 1 Indexed Configuration Register Space Direct Mapped I O Ports Indexed Register Spaces PC Card Controller Card Data Indexed Register Space FP ElanSC400 Microcontroller CGA Data CGA Index Graphics Controller Indexed Register Space MIDA Deika ElanSC400 Microcontroller MDA Index 3D5h 3D4h 3B5h 3B4h RTC and CMOS 7ih Register Space 23h CSC Indexed 22h pooier paca I e e 00h Figure 2 2 Using the Index and Data I O Ports to Access CSC Register Space Index gt CSC Index Port 22h CSC Data CSC Data Port 23h 00h In this example the value of 81h is written to CSC index 65h lanSC400 Chip Setup and Control CSC Register Space Configuration Basics 2 5 2 3 3 Table 2 3 2 6 Chip Setup and Control CSC Indexed Registers The registers specific to the lanSC400 and lanSC410 microcontrollers that are indirectly accessed using ports 22h 23h are used for most of the im
493. oard signals because their function is shared Allows Port 0060h to be read as an internal por Allows IRQ1 to be used by the XT interface Controlling the XT Keyboard Interface Two control bits Port 0061h 7 6 are provided for control of the XT keyboard interface Bit 7 is used to clear the keyboard interrupt clear the keyboard data shift buffer and force the data line XT DATA Low which can be used as a busy signal to the keyboard Two writes are required for the proper operation of this bit the first to set it and the second to clear it If it is not cleared then the shift buffer will be held in a clear configuration Bit 6 when 0 forces the keyboard clock line XT Low which can also be used as a busy signal to the keyboard Once a serial keyboard byte has been assembled it can be read at Port 0060h Timing The XT keyboard clock typically runs at roughly 100 KHz or 10 us per bit The falling edge ofthe XT CLK input after being delayed by two CPUCLKS 6 is what clocks the shift buffer Therefore XT DATA should be changed on the rising edge of the XT CLK signal The XT keyboard interface will run at speeds up to 250 KHz INITIALIZATION Both the matrix keyboard interface and the XT keyboard interface are disabled at power on reset and must be configured by software before being enabled Note that the internal RTC must be initialized before the keyboard timer function can be used This is particular
494. ocontrollers require only one 32 768 KHz crystal to generate all the other clock frequencies required by the system The output of the on chip crystal oscillator circuit is used to generate the various frequencies by utilizing four Phase Locked Loop PLL circuits An additional PLL in the CPU is used for Hyper Speed mode Architectural Overview 1 2 4 1 2 5 ROM Flash Interface Chapter 8 The integrated ROM Flash interface supports the following features 3 16 and 32 bit ROM Flash interfaces Three ROM Flash chip selects Burst mode ROMs ROM accesses at both ISA and CPU speeds normal and fast speed modes Dedicated ROM Read and ROM Write signals for better performance Each ROM space can accommodate up to 64 Mbytes of ROM The three ROM spaces may be individually write protected This is useful for protecting code residing in Flash devices Three ROM access modes are supported Normal mode Fast mode and Burst mode A different set of timings is used in each mode In Normal ROM access mode the bus cycles follow ISA like timings In Fast ROM access mode the bus cycle timing occurs at the CPU clock rate with controls for wait state insertion Burst ROM access timing is used when the ROM Flash interface is fulfilling an internal CPU burst request to support a cache line refill Wait states are supported for all ROM and Flash accesses including burst mode Burst mode page mode ROM reads are supported
495. of time Because the key matrix is scanned by the CPU there is no specific hardware for typematic but the timer can be used to aid in typematic support SCP Emulation To facilitate software emulation of a PC AT keyboard the keyboard controller provides the SCP Input Buffer Output Buffer and Status registers as well as IRQ generation Keyboard Configuration Register B at CSC index C1h 3 2 enables the internal SCP emulation registers B input Buffer This CPU write register ports 0060h and 0064h can be enabled to cause an SMI NMI when the CPU writes it The firmware can then read out the byte at the Keyboard Input Buffer Read Back Register CSC index C2h and use the information for its keyboard code By writing to the Input Buffer at Port 00601 or 0064h the IBF flag in the Status Register is set By reading CSC index C2h the IBF flag in the Status Register is cleared Output Buffer This CPU read register Port 0060h is writable at the Keyboard Output Buffer Write Register CSC index C3h This is where the firmware would communicate information back to the CPU such as key press scan codes By reading the Output Buffer at Port 0060h the OBF flag in the Status Register is cleared By writing CSC index C3h the OBF flag in the Status Register is set Status Register This CPU read register Port 0064h is writable at the Keyboard Status Register Write Register CSC index C5h Several of the bits are writable by firmware an
496. of Electrical and Electronic Engineers Inc 800 678 4333 www ieee org Infrared Data Association Serial Infrared Physical Layer Link Specification Version 1 1 Infrared Data Association IrDA 510 943 6546 www irda org October 1995 Infrared Data Association Serial Infrared Link Access Protocol IrLAP Version 1 1 IrDA 510 943 6546 www irda org June 1996 ISA Bus PC Bus Draft Standard 996 D2 02 order DS0224 Institute of Electrical and Electronic Engineers Inc 800 678 4333 www ieee org July 1990 ISA System Architecture Mindshare Inc Third Edition Reading MA Addison Wesley 1995 PC Card Standard Personal Computer Memory Card International Association PCMCIA 408 433 2273 www pc card com February 1995 PCMCIA Standard Release 2 1 PCMCIA 408 433 2273 www pc card com July 1993 The Indispensable PC Hardware Book Hans Peter Messmer Second Edition Wokingham England Addison Wesley 1995 Introduction AMD VL Bus Standard 2 0 Video Electronics Standards Association VESA 408 435 0333 www vesa org November 1993 DOCUMENTATION CONVENTIONS The following table lists the documentation conventions used throughout this manual Documentation Conventions Table Notation Meaning Reference Notation CSC index O0h 1 ElanSC400 Chip Setup and Control CSC indexed register 00h bit 1 Graphics index 00h 1 Graphics controller indexed register 00h bit 1 PC Card index
497. of MMS because the DRAM at the target SRAM location of A8000h is not visible during normal system operation The code fragment moved to the default SMRAM location changes SMBASE and performs an RSM instruction Since the cause of the SMI has not been removed another SMI occurs immediately but using the relocated SMBASE The other code fragment removes the cause of the SMM the force SMM bit and performs an RSM instruction Both code fragments update the VGA display to show that the SMI occurred This program was assembled with TASM and linked with TLINK into a tiny model COM file It assumes that there are not so many TSRs and drivers loaded that it loads too high CS should be well below 3000h when the program runs code segment para public usel6 CODE 386 assume cs code ds code es nothing fs nothing gs nothing org 100h Go jmp short PastTheData Data for moves We are moving one code fragment into 3000 8000 assuming that that does not interfere with the location of this program and another fragment into A000 8000 via the MMS window at B000 0000 CodeDst1 LABEL DWORD dw 8000h 3000h CodeSrcl DW CodeFragl CodeDst2 LABEL DWORD dw 0000h OBO00h CodeSrc2 DW CodeFrag2 PastTheData in al 22h push ax 3 12 Am4869 CPU Use MMS Window 5 to map CPU address B000 0 to RAM address 000 8000 OA800h SHR 15 4 100 32h mov out mov out 22h ax ax
498. oftware Triggered Strobe 12 4 1 6 Mode 5 Hardware Triggered Strobe 12 4 2 Timer Configuration 12 4 2 1 Configuring Timer Channel 0 12 4 2 2 Configuring 1 12 4 2 3 Configuring Timer Channel 2 12 4 8 Programming the Timer Channels 12 5 Initialization eee 12 6 Power Table of Contents 13 14 15 REAL TIME CLOCK 13 1 Overview 13 2 RegISIeTS cose es ee ad awed eed kd ex IE ae 13 2 1 RTC and Configuration RAM Index Registers 13 3 Block Diagram soar em 13 3 1 Voltage Monitoring 13 4 Operation onec ieee RS RS RE EUR 13471 Interrupts esa see etie oem b 13 4 2 Clock 13 4 3 Internal Oscillator Control Bits 13 4 4 Update Cycle 13 4 5 Backup Battery Considerations 13 4 5 1 Using an External Backup Battery 13 4 5 2 Not Using an External RTC Backup Battery 13 4 5 3 Overall System Implications 13 5 Initialization 2 13 6 Power PAR
499. oftware by executing an IRET instruction If the SMI handler requires the use of NMI interrupts it should invoke a dummy interrupt service routine to execute an IRET instruction When an IRET instruction is executed NMI interrupt requests are serviced in the same Real mode manner in which they are handled outside of SMM Auto Halt Restart In some power managed systems the Halt HLT instruction can be used to halt execution when there is no work to be done Typically HLT is executed with interrupts enabled and an interrupt request brings the CPU out of halt state After the interrupt is serviced main line execution resumes with the instruction after the Halt instruction When an SMI occurs while the CPU is halted by default the Halt instruction is restarted upon exitfrom SMM This will cause the CPU to re enter the halt state after having executed the SMI This feature is called Auto Halt Restart The SMI handler may choose to disable this feature on a per SMI basis This causes the CPU to resume with the instruction after the HLT upon exit from SMM just as it does when a regular interrupt handler exits In this case the SMI causes the CPU to leave the halt state to continue executing main line code after the SMI handler finishes Bit 0 of the word at SMBASE 0FFO2h is the Auto Halt Restart bit It will be set to 1 upon SMM entry if and only if the interrupted instruction was a HLT When the SMI handler resets this bit to 0 execution af
500. oller to allow access to the addressed configuration register A summary listing of the direct mapped chip setup and control CSC index and graphics index registers used to control the LCD graphics controller is shown in Table 20 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Graphics Controller Register Summary Description Address Graphics Controller Function Keyword in Register Set Manual Direct Mapped Registers CGA MDA Index Registers 03B4h 03D4h Graphics controller indexed register to read or page 2 130 write for MDA HGA or CGA modes page 2 135 CGA MDA Data Ports 03B5h 03051 Data to be written to register selected in 3x4h page 2 131 for MDA HGA CGA modes page 2 136 20 2 Graphics Controller AMD Table 20 1 Graphics Controller Register Summary continued Description in Register Set Manual Register Address Graphics Controller Function Keyword MDA HGA Mode Control Register 03B8h Text blink control video blanking HGA graphics enable MDA HGA select HGA page select page 2 132 MDA HGA Status Register Vertical retrace status simulated vertical sync display memory access status simulated horizontal sync page 2 133 HGA Configuration Register Allow HGA page select HGA text or graphics enable page 2 134 CGA Mode Control Register Text attribute CG
501. om the PC Card above 1 Mbyte but outside of the top 64 Kbytes Protect mode must be entered and an MMS window must be set up and pointed to the ROMO device Finally it is important to note that default termination on the PC Card Socket A Vcc control pin at reset is such that PC Card socket power is enabled This was done to support redirection of ROMCSO to Socket A However software running in the configuration must be careful to manually turn the socket power on via the PC Card control registers prior to configuring the PC Card socket power controls as such via CSC index 39h 1 0 Failure to do this will shut off card power while instructions are being fetched from it After boot the ROMCSO redirection can be cancelled by resetting bit 2 in the Pin Strap Status Register CSC index 20h ROMCS remapping is provided as a simple method e g using MMS windows A or B of accessing a memory card in PC Card Socket A without having to learn all the intricacies of programming the 82365 This is controlled with bit 6 in the Linear ROMO Shadow Register CSC index 21h SYSTEM CONSIDERATIONS 2 7 Volt Operation If the microcontroller is operated at 2 7 volts the boot code should set bit 5 in the Cache and VL Miscellaneous Register CSC index 14h or MMU DRAM accesses will not work properly ROMCS 2 Operation Unlike ROMCSO and ROMCS1 ROMCS2 is not mapped to an external pin by default It be mapped to any of the GPIO CS14 GPIO
502. omatic mode allows extensive power management operations to be performed completely transparently to software In this mode wake ups and activities move the PMU to higher power performance states and time outs without the presence of activities move the PMU to lower power performance states n software driven modes the PMU provides all of the resources required by a power management driver to implement almost any power management scheme including a superset of APM 1 2 In addition the PMU may be used in a role where it operates completely independently of any O S drive or application software to provide intelligent power utilization at the system level For fully automatic mode operation the BIOS HAL initialization code must set up the PMU to define time outs between the PMU states modes and also to define what events should be taken by the PMU as activities wake ups etc Once the operating system has loaded the PMU requires no software intervention In a software driven power management scheme the PMU Force Mode Register is used by a software state machine to force the hardware into the desired power consumption state When no power management software is available the hardware can be configured once at boot time by BIOS or system firmware to implement power management based on mode timers and power management events After this has been done the PMU hardware controls the system performance power consumption state automatically and
503. ompatible PC Card controller were added Socket C would be controlled by indexes 80 BFh and Socket D would be controlled by indexes FFh See Section 19 6 for details on how an external 82365 compatible PC Card controller works with ports Note that the PC Card controller index register O3EOh like the lanSC400 microcontroller CSC index register at Port 0022h and the other lanSC400 microcontroller index registers is a system level resource that can be accessed by more than one driver or software thread in a system Any interrupt driven routine must restore the index register to its original value prior to returning from the interrupt This ensures proper system operation A summary listing of the chip setup and control CSC and PC Card index registers used to control the PC Card controller is shown in Table 19 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 PC Card Controller Register Summary Description Address PC Card Controller Function in Register Set Manual Chip Setup and Control CSC Index Registers MMS Window C F Attributes 22h 23h Caching and write protection for MMS page 3 38 Register Index 30h Windows C F MMS Window C F Device Select 22h 23h Physical device selection for MMS Windows page 3 39 Register Index 31h C F Pin Mux Register B 22h 23h PC Card Socket B signals Vcc and Vpp page
504. on The six timer modes are shown in Table 12 2 Channel 0 and Channel 1 operate in four modes only Channel 2 supports all six modes of operation of the timer Mode selection is performed in the PIT 1 Mode Control Register Port 0043h Timer Modes Supported Channels Channel 0 Channel 1 Channel 2 Yes Yes Yes Interrupt on Terminal Count Hardware Retriggerable One Shot Rate Generator Square Wave Generator Software Triggered Strobe Hardware Triggered Strobe Mode O Interrupt on Terminal Count Mode 0 is used to cause an event after a predetermined interval B Theinitial countis loaded into the count register and the output of the counter goes Low B If the gate input is held High the count value gets decremented by one for each input clock pulse If the gate input is held Low the count will maintain its state until after a rising edge of the clock after the gate goes High again The output of the counter is initially Low and will remain Low until the counter reaches zero The output then goes High until a new count or a new Mode 0 control word is loaded into the Counter Mode 1 Hardware Retriggerable One Shot Mode 1 is used to create a fixed duration output After an initial count is loaded into the count register a rising edge on the gate input causes the output of the counter to go Low Programmable Interval Timer 12 3 12 4 1 3 12 4 1 4 12 4 1 5 12 4
505. on 11 2 Interrupt Configuration Register B CSC index D5h function 11 2 Interrupt Configuration Register C CSC index D6h function 11 2 Interrupt Configuration Register D CSC index D7h function 11 2 Interrupt Configuration Register E CSC index D8h function 11 2 usage 14 2 15 1 15 7 18 13 interrupts See programmable interrupt controller PIC IOCHRDY signal control 4 25 description 4 6 usage 8 9 IOCS16 signal control 4 25 description 4 6 signal description 4 6 usage 4 29 10 6 10 7 17 8 19 7 19 17 TOW signal description 4 6 usage 4 29 10 6 10 7 17 8 19 7 19 17 IrDA Control Register CSC index function 18 2 usage 15 7 18 11 18 13 IrDA CRC Status Register CSC index ECh function 18 2 usage 18 8 18 9 18 12 IrDA Frame Length Register A CSC index EEh function 18 2 usage 18 9 10 Frame Length Register CSC index EFh function 18 2 usage 18 9 IrDA Own Address Register CSC index EDh function 18 2 usage 18 8 IrDA Serial Input signal See SIRIN signal IrDA Serial Output signal See SIROUT signal IrDA Status Register CSC index EBh function 18 2 usage 18 11 18 12 IrDA See infrared port IRQ ENABLE bit usage 18 12 IRQF bit usage 13 6 ISA bus interface 4 25 16 bit maximum ISA interface figure 4 27 8 bit ISA bus with external data buffer figure 4 30 8 bit minimal ISA interface figure 4 27 addressing 4 29 7 4 block d
506. on Register CSC index D1h 0 Select either COM1 or COM2 The SP CONFIG bit in the Parallel Serial Port Configuration Register CSC index D1h 1 controls this selection Select UART mode instead of infrared mode by writing the SELDEVICE bit to 0 in the IrDA Control Register CSC index EAh 0 Configure the UART by programming the required registers After the UART is enabled it powers up as a 16450 compatible device It can be switched to and from 16650 compatible mode under software control Enable 16650 compatible mode by setting the FIFOEN bit in the COMx FIFO Control Register ports OSFAh O2FAh 0 Note that the contents of either of these write only registers can be read back in the UART FIFO Control Shadow Register CSC index D8h POWER MANAGEMENT The internal UART clock is turned off if the UART_ENB bit CSC index D1h 0 is 0 Operation of the serial port is affected by the power management functions shown in Table 15 5 Serial Port UART 15 7 Table 15 5 Power Management in the Serial Port Serial Port Event UART Ring Indicate RIN signal Description Triggered by the falling edge of RIN Power Management Effect Activity UART Receive SIN signal Triggered by the falling edge of SIN CPU access to UART internal or external Triggered by the falling edge of the address decode qualified with commands Programmable UART access 15 8 Accesses to CO
507. on display lines to be added to the bottom of page 5 18 Index 34h the vertical display sequence after vertical adjust rolls over Vertical Adjust Register 3x4h 3x5h Vertical adjust excess lines page 5 19 Index 35h 20 4 Graphics Controller Table 20 1 Register Address Graphics Controller Register Summary continued Graphics Controller Function Keyword AMD Description in Register Set Manual Overflow Register 3x4h 3x5h Vertical synch mode eighth bits of the Vertical page 5 20 Index 36h Display Enable End Register and Vertical Border End Register Vertical Display End Register 3x4h 3x5h Number of the last character line to be output page 5 21 Index 37h from the frame buffer at the bottom of the screen Vertical Border End Register 3x4h 3x5h Last character line to be output to the panel at page 5 22 Index 38h the bottom of the display Frame Sync Delay Register 3x4h 3x5h Number of character clocks to delay frame page 5 23 Index 39h sync from beginning of horizontal line pulse Dual Scan Row Adjust Register 3x4h 3x5h Dual scan mode character row overlap page 5 24 Index 3Bh Dual Scan Offset Address High 3x4h 3x5h Dual scan mode high byte of offset address page 5 25 Register Index 3Ch between lower and upper screens Dual Scan Offset Address Low 3x4h 3x5h Dual scan mode low byte of offset address page 5 26 Register Index 3Dh between lower and upp
508. onal to the display resolution as well as the color depth of each pixel number of bits of data required to form each pixel system performance can decrease as LCD panel resolution and color depth increase Graphics Buffers The lanSC400 microcontroller s graphics controller can maintain two buffers in UMA DRAM the frame buffer also known as the Graphics Frame Buffer MMS Window and the font buffer The frame buffer has meaning in either text or graphics modes whereas the font buffer is only supported in text mode The frame buffer is illustrated in Figure 20 2 Using the Frame Buffer in Text Mode In text mode software writes two types of data to the frame buffer These are the ASCII code of the character to be displayed and an attribute byte that modifies display characteristics of the ASCII character color intensity or blinking Thus two bytes are written into the frame buffer for each text mode character displayed For example a standard CGA 80x25 text display uses 80 x 25 x 2 4000 bytes for each screen that is displayed Because the lanSC400 microcontroller s text mode frame buffer is fixed at 16 Kbytes data for up to four different text mode screens with a few unused bytes left over per screen can be stored in the font buffer at any time The Start Address High and Low registers graphics index OCh and ODh are used to specify where in the frame buffer the text data for the upper left corner of the display should be fetch
509. onsequently no further interrupt ever occurs from these sources To avoid this situation the boot code which is invoked as a result of the SRESET should force the NMI and SMI signals to be deasserted via their enable bits and then re enable them This will cause a new edge to be asserted to the CPU for the NMI and SMI events if any events were pending SMIs can be disabled via CSC index 9Dh 0 NMIs can be disabled via Port 0070h 7 Note that SRESET is normally the result of either setting Port 0092h 0 reading Port OOEFh sending a CPU reset command to the keyboard controller or experiencing a CPU triple fault All of these means have been used by older software to switch the CPU from Protected mode back to Real mode CPU CORE IDENTIFICATION USING THE CPUID INSTRUCTION Information about the integrated Am486 CPU core is available by reading the DX Register after a system reset see reset information in Chapter 4 and also by using the CPUID instruction at any time The CPUID instruction is available on later model 32 bit processors from all leading x86 vendors and allows programs to determine information about the CPU including the manufacturer cache type and availability of an FPU The lanSC400 and ElanSC410 microcontrollers the first members of a new family of embedded devices The CPUID instruction can be used to identify a processor as belonging to this family and then the ElanSC400 Microcontroller Revision ID Register CS
510. ontroller 19 5 5 19 5 5 1 Table 19 13 AMD Using Standard PC Card Mode Standard mode is the default mode In Standard PC Card mode a total of six PC Card memory windows is available Each socket has one memory window dedicated to it The remaining four windows are mapped to PC Card Socket A by default but are individually mappable to either Socket A or Socket B In this Standard PC Card mode four of the memory windows that are normally used for Socket B in Enhanced PC Card mode are used for MMS windows C F instead When only one socket is implemented in the system design i e Socket A the lanSC400 microcontroller provides one fully 82365 compatible PC Card socket If two PC Card sockets are implemented in a system design and the Standard PC Card mode is selected the six available PC Card memory windows can be mapped in various combinations between Socket A and Socket B In any situation in which a socket has less than five memory windows available to it compatible PC Card drivers are not guaranteed to work with the sockets Although a memory window from Socket A may be mapped to Socket B the controls still remain in their original Socket A index locations Memory Window Redirection In Standard mode four of the memory windows nominally assigned to Socket A can be reassigned to Socket B This feature is controlled by the PC Card Extended Features Register CSC index FOh The bits MEM WIN SEL 3 0 in this register control
511. ontroller is not displaying data The speed is selected by LVDD the PMU mode and the CPU clock speed selected Timer Clock This clock is used by the Programmable Interval Timer PIT The clock is either the Low Speed output divided by 31 or it is an external oscillator brought on the CLK 10 pin This option defaults to using the internal PLL for the timer clock if the pin multiplexing registers select CLK IO to be active as an input then the PIT gets its clock from this input UART Clock This clock is used by the UART It operates at either 1 8432 MHz for standard UART interfaces or 18 432 MHz to support the serial infrared 1 Mbit s transfer frequency The UART clock is stopped in Suspend mode or when the UART is disabled CSC index D1h 0 The clock is changed based on the indication that the infrared interface needs High Speed Infrared mode and that the UART is in use System Clock This clock is used by the ISA bus controller the PC Card controller internal ISA cycles and PC Card cycles at ISA speeds The system clock is a maximum of 8 29 MHz and will be 4 2 or 1 MHz depending on the CPU clock frequency This clock is controlled by the PMU mode and the CPU clock frequency RTC Clock Used by many cores this clock is the 32 768 KHz generated by the internal oscillator it is always available DMA Clock This clock is used by the ISA bus controller and the DMA controller The DMA clock is controlled by C
512. op flag is set to a constant value of 7Eh or 01111110b STO flags are alternatively referred to as EOF End Of Frame flags Figure 18 5 High Speed Infrared Frame Format 18 6 5 n FIFI 5 T 7 CIC T A A DL NES 515 Start Stop Infrared Port 18 4 2 2 18 4 2 3 Figure 18 6 18 4 2 4 AMD Frame Sequences Frames are grouped into frame sequences which may consist of from one to seven frames The maximum number of frames in a sequence is a parameter that two stations negotiate when they form a connection and is known as the window size for the connection After the connection has been established only frame sequences that have less than or equal to the negotiated window size are allowed The window size may never be greater than seven When only one frame is sent the window size is considered to be 1 Each time a frame sequence is sent an acknowledgment must be sent back to the transmitting station by the receiving station to confirm that the data was received Since the interface is only capable of half duplex operation the act of listening for a response after having sent out some data costs some turnaround time overhead Thus a larger window size and the sending of multiple frames per sequence also known as back to back frames may increase performance The entire frame structure shown above is repeated for each frame in the sequence Window size can be limited by resources on eithe
513. operation to ports 60h and 64h These two selects can be independently mapped to any one of the GPIO CS pins using the Standard Decode to GPIO CS Map Register CSC index B1h General Purpose Input Output and Programmable Chip Selects 17 7 17 6 17 6 1 17 6 2 17 7 17 8 The other four chip selects GP CSA GP CSB GP_CSC GP_CSD can be independently mapped to any one of the GPIO_CS pins using the GP_CS to GPIO_CS Map Registers A and CSC index B2 B3h GP CSAandGP decode I O addresses and GP_CSC and GP_CSD decode memory addresses These signals can be used for internal functions in addition to or instead of being used for external chip selects See Section 17 7 for details on selecting I O and memory regions for decode GPIO_CS SIGNALS AS PMU ACTIVITIES AND SMI NMI GENERATION As noted in Section 17 5 3 1 PMU state information can be output on GPIO_CS pins GPIO_CS pins can also be used to input information to the PMU or to generate an SMI or NMI Chapter 5 contains a discussion of the PMU and SMI generation Note thata GPIO CS can be configured to provide information to the PMU orto generate an SMI or NMI independent of whether the pin has been configured as an input or as an output For example an SMI could be generated by external hardware input or by writing to a GPIO CS register output or by accessing a particular device or memory region automatic output GPIO CS PMU Activity and Wake Up
514. or CPU address valid They are configured via CSC indexed registers B9 BDh CSC indexed registers BA BDh also allow any combination of the lowest four bits of the address to be ignored during decode SA3 SAO0 for GP CSA and GP CSB SA17 SA14 for GP CSC and GPC_CSD and also allow automatic forcing of 16 bit ISA cycles on a per chip select basis General Purpose Input Output and Programmable Chip Selects 17 7 1 17 7 2 17 7 3 17 7 4 17 8 Table 17 2 Using with General Purpose Chip Selects The memory chip selects GP CSC and GP CSD can be used for DMA cycles chip selects GP CSA and GP CSB are asserted for CPU initiated cycles only The GP CSC and GP CSD memory chip selects behave as follows Raw address decode CPU or DMA Qualified with MEMR assertion CPU B Qualified with MEMW assertion CPU or DMA B Qualified with MEMW or MEMR assertion CPU or DMA Qualified with CPU address valid The chip select would not be asserted for DMA cycles Mapping a General Purpose Chip Select to a GPIO CS Pin As discussed in Section 17 5 3 each chip select can be independently mapped to any one of the GPIO CS pins for use as an external device chip select and or to generate an SMI or NMI via CSC index BOh Many external devices require no additional logic to use this scheme CSC indexed registers B1h and B2h perform this mapping Do not map two different GP CS signals to the s
515. ort Configuration Register CSC index D2h function 14 3 usage 14 2 14 9 Parallel Port Output Buffer Enable signal See PPOEN signal Parallel Port Write Enable signal See PPDWE signal Parallel Serial Port Configuration Register CSC index D1h function 14 2 15 3 18 2 usage 14 2 15 1 15 7 18 13 PC Card and Keyboard SMI NMI Enable Register CSC index 91h function 5 6 usage 16 3 PC Card and Keyboard SMI NMI Status Register CSC index 95h function 5 6 usage 16 3 PC Card controller block diagram 19 5 bus cycles 19 11 19 17 attribute memory read function table attribute memory write function table common memory read function table common memory write function table DMA cycle timing 19 17 DMA read function table 19 12 DMA write function table 19 13 read function table 19 12 write function table 19 12 memory write protection 19 13 non DMA cycle timing 19 13 prescaler select field weighting table 19 14 supported cycle types table 19 11 CD and CD B signal merging 19 19 card detect function for Socket A figure 19 20 DMA channel mapping 10 8 dual mode signal functions table 19 6 Enhanced mode 19 8 19 16 external PC card controller usage 19 23 I O interface 19 10 windows 19 10 Identification and Revision Register 19 23 initialization 19 22 interrupts 19 18 Socket status inputs 19 18 memory interface 19 8 memory windows 19 8 memory management 7 10 operation
516. ory or Programmable 4 38 System Interfaces 4 9 4 9 1 4 9 2 4 9 2 1 AMD PC AT PORT LOGIC Overview The lanSC400 and lanSC410 microcontrollers provide all of the support functions found in the original IBM PC AT These include the Port B status and control bits speaker control SCP based CPU core reset and A20 gate control as well as extensions for fast CPU core reset and A20 gate control In addition a CPU shutdown cycle e g as a result of a triple fault will generate a CPU core reset None of these resets will affect either on board PC AT legacy registers or CSC indexed registers specific to the lanSC400 and lanSC410 microcontrollers Registers Direct Mapped Registers The following PC AT features are supported using direct mapped registers System Control Port B NMI Status Register Port 0061h Port B is a PC AT standard miscellaneous feature 8 bit control register The lower two bits of this register are read write control bits that enable or disable sound generation features The standard sound source on the PC AT is the output of PIT Channel 2 which is fed to the system speaker via a driver The PIT has several modes of operation that require software to have access to the PIT gate control This gate control is provided by bit 0 In addition software can enable or disable the PIT output data from reaching the system via bit 1 Bits 3 and 2 are reserved on the lanSC400 and ElanSC410 micro
517. page 3 91 Access SMI Enable Register A 22h 23h Index 99h SMI on I O access to internal graphics controller page 3 105 I O Access SMI Enable Register B 22h 23h Index 9Ah SMI on I O access to external VGA graphics controller page 3 106 Access SMI Status Register 22h 23h Index 9Bh SMI status of I O access to internal graphics controller page 3 107 Access SMI Status Register B 22h 23h Index 9Ch SMI status of I O access to external VGA graphics controller page 3 108 Graphics Controller 20 3 Graphics Controller Register Summary continued Table 20 1 Register Address Graphics Controller Function Keyword Description in Register Set Manual Internal Graphics Control 22h 23h Graphics controller enable CGA MDA mode page 3 179 Register A Index DDh compatibility mode linear flat mapped graphics mode panel type drive width horizontal dot doubling and vertical line doubling Internal Graphics Control 22h 23h Non display data value blanked data value page 3 180 Register B Index DEh text mode data polarity graphic modes data polarity pixel depth for linear flat mapped modes lockout for CSC registers at 3x4h 3x5h underline attribute Graphics Index Registers Legacy CGA MDA Registers Cursor Start Register 3x4h 3x5h Alphanumeric cursor start line blinking control page
518. peed Infrared Transmit Serializer lt q SIRIN DMA Interface p SIROUT Infrared State 18 432 MHz Machine Note Blocks inside the dashed box are part of the standard UART 18 4 OPERATION The Infrared Data Association IrDA consists of member companies that have an interest in generating hardware and software standards for infrared communications Supporting the IrDA standard the infrared port on the ElanSC400 and ElanSC410 microcontrollers provides a reliable half duplex wireless communications link to other IrDA compatible systems The hardware designed into the lanSC400 and ElanSC410 microcontrollers is not a generic infrared port implementation What is provided is an infrared port designed to support an IrDA compatible system implementation Most of the features of the infrared port on the ElanSC400 and ElanSC410 microcontrollers were derived directly from either from the requirements of the IrDA specifications or at the system level from the goals of the IrDA specifications Acomplete understanding of the IrDA specifications will help the user to better comprehend the features in the ElanSC400 and ElanSC410 microcontrollers that support those specifications See the Infrared Data Association Serial Infrared Physical Layer Link Specification and the Infrared Data Association Serial Infrared Link Access Protocol IrLAP for more detail Two different modes of operation are
519. peed mode from Low Speed or Standby modes When a primary activity is received while in High Speed mode it resets the High Speed time out timer Primary activities have no affect in Suspend mode Suspend mode is exited using wake ups instead of activities When a primary activity is received in Temporary Low Speed mode it forces a switch to High Speed mode unless Temporary Low Speed was entered from Suspend When Temporary Low Speed is entered from Suspend it is an extension of Suspend mode so only a wake up can cause a mode change activities have no effect Secondary activities These activities require CPU involvement but they do not need the highest performance in the system Secondary activities are handled differently depending on the state the PMU is in when the secondary activity is received n High Speed or Hyper Speed mode secondary activities have no effect since the CPU is already in the highest performing mode n Low Speed mode if the timer is enabled a secondary activity causes the timer to be reset and to begin counting down n Standby mode a secondary activity causes the PMU to switch to Temporary Low Speed mode Once the activity is complete the Temporary Low Speed timer begins counting down On a timer time out the PMU returns to Standby mode When another secondary activity comes before the timer times out the PMU remains in Temporary Power Management 5 4 13 1 Low Speed mode
520. peeds 33 66 Runs in all modes except Critical Suspend Programmable to be shut off in Standby and Suspend modes Runs in all modes except Critical Suspend Programmable to be shut off in Suspend mode Runs in all modes except Critical Suspend Programmable to be shut off in Suspend mode Only runs when internal graphics controller on the ElanSC400 microcontroller is enabled 33 LCD 66 LCD Standby 66 No LCD Programmable Option ROM and Internal Registers Programmable Option PC Card 6 10 Programmable Co CO A A Option A A A A A AJ m N N N N N A oj oj O o oj o ojojo Clock Control 6 5 6 6 INITIALIZATION The CPU Clock Speed Register CSC index 80h controls CPU clock speed in Hyper Speed High Speed and Low Speed PMU modes The Clock Control Register CSC index 82h controls the DMA clock frequency the internal CPU PLL restart delay time and the microcontroller specific PLLs Note Ifthe graphics controller on ElanSC400 microcontroller is enabled the memory DRAM clock is always 66 MHz If the graphics controller is not enabled the memory clock is always 2x the CPU clock On the lanSC410 microcontroller the memory clock is always 2x the CPU clock POWER MANAGEMENT The PMU controls the clock generation circuitry to change th
521. portant chip configuration It is important to remember that all of the index registers must be treated as system resources Interrupt handlers in particular must always save any index register used by the handler and then restore the index register before returning control to the interrupted routine The indexes for these CSC registers were chosen such that related functions are as much as possible grouped together in the register map The groups start on either 8 or 16 byte boundaries in the map For example all of the DRAM control functions are accessed starting at CSC index 00h Even though there are only eight DRAM control registers indexes 00 07h the next block cache control starts at 10h Table 2 3 shows the organization of the CSC registers by functional grouping and the index at which the group begins Chip Setup and Control CSC Indexed Register Map Start Index Register Group Name DRAM Setup and Configuration Cache Control ROM Configuration Setup and Control MMS Configuration Setup and Control GPIO Pin Multiplexing and Termination PMU Mode Control and Status PMU Wake Up Control and Status PMU Activity Control and Status Battery Level BL Pin Control and Status Clock Control and Status Factory Level Debug Registers SMI NMI Generation and Status GPIO Pin Control Status and Multiplexing Matrix and XT Keyboard Control and Status Extended PC AT Feature
522. provided Slow Speed mode and High Speed mode Infrared Port 18 3 18 4 1 18 4 1 1 Figure 18 2 18 4 Slow Speed Infrared Mode Slow Speed Infrared mode supports a programmable baud rate in exactly the same way as a standard 16550 UART When operating in Slow Speed Infrared mode the infrared port on the ElanSC400 and lanSC410 microcontrollers is like a two wire virtual RS 232 cable that has transmit and receive signals only and that can operate only in half duplex mode Slow Speed Infrared mode is similar to High Speed Infrared mode in terms of the pulse stream from the SIROUT pin All fields are transmitted with the least significant bit of each byte first and the data stream is RZI Return to Zero Inverted Besides this one other observable difference between the output of the infrared interface s SIROUT pin and the UART interface s SOUT pin is that the actual pulses sent out on the SIROUT pin to the external infrared LED module are pulse shaped to only 3 16 of a standard RS 232 bit cell time in order to reduce transmit operation power consumption The pulse width is not adjustable it is fixed to be the minimum width allowed by the rDA Serial Infrared Physical Layer Link Specification and is centered in the standard RS 232 bit cell time slot In this mode incoming pulses are detected and stretched to the full RS 232 bit cell length by the microcontroller prior to being fed to the on board UART for deserialization
523. put 115 MA8 Output 114 MA7 Output 113 MA6 Output 112 MA5 Output 111 MA4 Output 110 MA3 Input 109 MA3 Output 108 MA2 Input 107 MA2 Output 106 MA1 Input 105 MA1 Output 104 MAO Input 103 MAO Output 102 MWE Output 101 N A Control cell Control for data bus 100 DO Input 99 DO Output 98 D1 Input 97 D1 Output 96 D2 Input 95 D2 Output 94 D3 Input 93 D3 Output 92 D4 Input 91 D4 Output 90 D5 Input 89 D5 Output 88 D6 Input 87 D6 Output 86 D7 Input 85 D7 Output 84 D8 Input 83 D8 Output 82 D9 Input 81 D9 Output 80 D10 Input Test and Debugging 21 13 Table 21 2 Main Data Scan Path continued JTAG Cell m meme Comment O 21 14 79 D10 Output 78 D11 Input 77 011 Output 76 D12 Input 75 D12 Output 74 D13 Input 73 013 Output 72 D14 Input 71 D14 Output 70 D15 Input 69 D15 Output 68 KBD COL7 Input 67 KBD COL7 Output 66 GPIO CS4 Input 65 GPIO CS4 Output 64 KBD ROW13 Input 63 KBD ROW13 Output 62 KBD COL2 Input 61 KBD COL2 Output 60 KBD COLS3 Input 59 KBD COLS3 Output 58 KBD COL4 Input 57 KBD COL4 Output 56 KBD COL5 Input 55 KBD COL5 Output 54 KBD COL6 Input 53 KBD COL6 Output 52 N A Control cell Control for data bus 51 KBD ROW7 Input 50 KBD ROW7 Output 49 KBD ROWS8 Input 48 KBD_ROW8 Output 47 KBD_ROW9 Input 46 KBD_ROW9 Output 45 KBD_ROW10 Input 44 KBD_ROW10
524. r In the Enhanced PC Card mode the PC Card control registers are used to control PC Card Socket B memory windows 1 4 MMS windows C F are not available In this mode any CSC index register bits that pertain to MMS window C F control have no effect PC Card Controller Interface 19 5 7 19 5 7 1 The lanSC400 microcontroller supports between PC Cards and system ISA memory as defined in the PC Card Standard also known as PC Card 95 or PC Card Standard Release 3 0 Berlin Drafts DMA is supported between an I O PC Card and system memory DMA between two PC Cards is not supported PC Card DMA is only supported in Enhanced mode See Table 4 15 for a complete listing of ISA DMA cycle types and command strobes generated One of two PC Card interface signals from each socket can be configured as the DREQ Request signal to be routed to the lanSC400 microcontrolle s DMA controller BVD2 x SPKR x orWP x IOIS16 x Regardless of which signal is configured to serve as DREQ onthe PC Card interface the x signal always acts as DMA Acknowledge x signal The socket must be configured for Memory and I O mode via the CARD 15 IO bitin the Interrupt and General Control Register before a card can issue DMA requests Note that the PC Card Standard requires that a third PC Card signal INPACK be available to be used as the DREQ input The lanSC400 microcontroller does not suppo
525. r Address increment or decrement Software priority 64 Mbyte system address space for increased performance Dynamic clock enable design for reducing clocked elements during DMA inactivity Programmable clock frequency for performance 10 2 REGISTERS 10 2 1 Direct Mapped Registers The DMA controller block on the ElanSC400 and ElanSC410 microcontrollers supports the following direct mapped registers These registers are one per channel Memory Address Register Read Write This register provides the lower bits of the channel memory address It is read written via two successive I O accesses It is used in conjunction with the Page Register to form a 24 bit memory address The microcontroller can perform 26 bit DMA accesses using the Extended Page registers available in CSC indexed register space DMA Controller 10 1 10 2 2 10 2 2 1 10 2 Transfer Count Register Read Write This register is written and read in two successive bytes The actual number of transfers will be one more than specified by this register B Page Register Read Write Provides the middle address bits during DMA transfers The processor writes the Page Register before enabling DMA transfers The following registers are one per controller slave master Status Register Read This register is read to determine the status of DMA requests and terminal counts detected per channel Control Registe
526. r Write This register controls various functions of the master slave controller such as priority type fixed or rotating and timing It is also used to disable the master slave controller while writing to the DMA registers Software Request Register Write Software can initiate DMA request as long as the controller is programmed for block mode This register is used to select which DMA channel will assert or deassert a DMA request initiated by software Mask Register Write This register is used to mask or unmask channels Setting a mask bit to 1 disables the channel Mode Register Write This register is used to specify the transfer mode demand single block or cascade address decrement and type of DMA operation verify write or read per channel B Clear Byte Pointer Register Write This register is used across the slave or master controller to determine which byte will be accessed in the 16 bit registers of the DMA controller Controller Reset Register Write A write of any data to this register resets the DMA controller to the same state as a hardware reset Reset Mask Register Write Writing data to this register resets the Mask Register thereby activating the associated DMA channels General Mask Register Write This register provides another alternative for enabling the DMA channels It is used to disable or enable incoming requests Chip Configuration and Control
527. r E Index D8h controller 14 3 BLOCK DIAGRAM The parallel port interface is shared with the GPIOS31 GPIO21 signals and on the ElanSC400 microcontroller with the PC Card Socket B interface Only one of these interfaces can be enabled at one time Figure 14 1 shows a block diagram of the parallel port interface Figure 14 1 Parallel Port Block Diagram p ACK p gt AFDT BUSY ElanSC400 Microcontroller ERROR INIT gt PPDWE ye PPOEN lt SLCT pe SLCTIN p STRB 06 85 35730 Parallel Port 14 3 14 4 PIN DEFINITIONS BY MODE The pin definitions for the parallel port vary according to mode of operation Table 14 2 shows the parallel port signals that appear on the pins of the ElanSC400 and ElanSC410 microcontrollers in PC AT Compatible Bidirectional and EPP modes Table 14 2 Parallel Port Signal Definitions by Mode ElanSC400 and PC AT Compatible lanSC410 and Microcontrollers Bidirectional Mode Pin Name Signal Name In PC AT Compatible and Bidirectional modes this signal is driven by the parallel port device with the state of the printer busy signal In EPP mode this signal is used to add wait states to the current cycle In PC AT Compatible and Bidirectional modes this signal is driven by the parallel port device with the state of the printer acknowledge signal In EPP mode this signal is used to indicate to the microcontroller that t
528. r Speed mode Itis possible to configure the microcontroller to allow a secondary activity that occurs while in Low Speed mode to reset the Low Speed mode timer CSC index 40h 7 Also note that if an event is active when it is enabled as an activity that activity will be detected by the PMU and the status bit for this activity will be set For this reason it is recommended that the associated status bit be cleared immediately following an activity being enabled PMU activity status bits are undefined when the associated event is not enabled as an activity Power Management 5 33 Figure 5 8 5 34 PMU Activity Mode Flow Feature Default Hyper Speed Enabled Feature Option Sain H IGH SPEEDN Activity DEUS RE Timor 66 100 MHz 33 Primary Activity Secondary 20 x Activity Activity Timer not reset e Timer not reset Hyper Speed Enabled Primary p Nn Activity Primary N Activity Secondary Activity Primary Activity Secondary Activity Secondary Activity N Primary f STANDBY Activity Activity SUSPEND MODE 2 Activity Activity Primary Secondary Activity Activity Power Management Table 5 5 Activity Activity Sources Enable CSC index Primary or Secondary A
529. r adding transparent BIOS support for device emulation and power management Because SMM is unfamiliar to many experienced x86 programmers its implementation in the lanSC400 and ElanSC410 microcontrollers is covered in Section 3 5 3 2 Am486 CPU 3 4 Table 3 2 3 5 3 5 1 AMD Because there are now many x86 CPU variants available from several different vendors programs sometimes require the ability to determine the hardware they are running on The lanSC400 and ElanSC410 microcontrollers can themselves itself via the CPUID instruction This is discussed in Section 3 6 CACHE MEMORY MANAGEMENT The lanSC400 and lanSC410 microcontrollers contain an 8 Kbyte unified code and data cache Cache operation defaults to write through although write back mode can be enabled at any time by setting bit O in the Cache and VL Miscellaneous Register CSC index 14h 0 Only the L1 cache is supported on the lanSC400 and ElanSC410 microcontrollers there is no support for an L2 cache The L1 cache can be configured through the standard cache configuration bits in the CPU s machine status register CRO register The CD cache disable bit bit 30 and NW not write through bit 29 are decoded as shown in Table 3 2 Cache Configuration Options CD Operating Mode Cache line fills cache write throughs and cache invalidations are disabled To completely disable the cache set both CD and NW to 1 and flush the cache by execut
530. r the transmitting or receiving station such as transmit receive buffer space storage space to temporarily hold received data CRC calculations etc High Speed Infrared Mode High Speed Infrared mode is similar in some ways to Slow Speed Infrared mode in terms of the pulse stream from the SIROUT pin As mentioned earlier all fields are transmitted with the least significant bit of each byte first Of course the bit cell times will be shorter to reflect the higher speed but the data stream is still Return to Zero Inverted like Slow Speed Infrared mode Another minor difference is that the bit cell time for the High Speed Infrared mode data is 1 4 the actual bit cell as opposed to 3 16 of the actual bit cell in Slow Speed Infrared mode Figure 18 6 for more detail on High Speed Infrared mode modulation In terms of the actual data observed in the data stream High Speed Infrared mode has some notable differences as compared to Slow Speed Infrared mode High Speed Infrared Data Modulation 1 4 Bit Time gt lt 0 4179 0 12515 7 Bit gt Time 6 Data Stream In Slow Speed Infrared mode the parallel data is converted into individual 5005 with start and stop bits delimiting the serialized data word With High Speed Infrared mode however all of the data bytes in an IrDA frame are merged into a contiguous bit stream that is delimited by flag bytes at the
531. r without interposing hardware between the microcontroller and the system System Interfaces Chapter 4 Data Buses The lanSC400 and ElanSC410 microcontrollers provide 32 bits of data that are divided into two separate 16 bit buses System Data Bus The system or peripheral data bus 5015 500 is always 16 bits wide and is shared between ISA 8 or 16 bit ROM Flash and PC Card peripherals It can be directly connected to all of these devices In addition these signals are the upper word of the VESA local VL data bus the 32 bit DRAM interface and the 32 bit ROM interface Data Bus The 015 00 data bus is used during 16 bit DRAM cycles For 32 bit DRAM VL bus and ROM cycles this bus is combined with the system data bus In other words the data bus pins D31 D16 are shared with the system data bus pins SD15 SDO The lanSC400 and ElanSC410 microcontrollers support the data bus configurations listed below External transceivers or buffers are required in some bus configurations to isolate the buses and to provide proper data steering 16 bit DRAM bus 8 16 bit ROM 32 bit VL bus disabled internal graphics controller enabled disabled 16 32 bit DRAM bus 8 16 bit ROM 32 bit VL bus enabled disabled internal graphics controller disabled 16 32 bit DRAM bus 32 bit ROM 32 bit VL bus enabled disabled internal graphics controller disabled See Figure 1 3 and Figure 1 4 for block diagrams of example systems
532. rder to maintain the same frame rate obtained when Bit 2 of the Extended Feature Control Register is cleared This option would be the one most frequently used A third option most useful when using text mode on a dual screen panel is enabled by setting both Bit 2 and Bit 7 of the Extended Feature Control Register When this is done the Non display Lines Register must be set to a non zero value The graphics controller will then perform the FIFO flush refill during one of the non displayed lines In this case no extra time is added to any horizontal lines however at least one extra line must be output at the end of the frame Typically this extra line has minimal or no impact on the contrast ratio of an LCD panel LCD Data Formatting The examples given in the tables and figures in this section are for 320x240 resolution panels Graphics Controller 20 35 20 4 9 1 Monochrome Single Scan Panels Table 20 13 Pixel Chart Row Column Monochrome Single Scan 320x240 ROW ROW 1 COLUMN COL 319 ROW 2 ROW 240 Figure 20 26 Data Format for 4 Bit Single Scan Monochrome Panel First horizontal line shown SCK LCDD 1 3 LCDD 1 2 LCDD 1 1 LCDD 1 0 Figure 20 27 Data Format for 8 Bit Single Scan Monochrome Panel D240 318 D240 319 First horizontal line shown SCK LCDD
533. re a good starting point for learning about the Am486 microprocessor as it has evolved over time The oldest publication is listed first The subsequent publications enhance the original functional descriptions Am4869DX DX2 Microprocessor Hardware Reference Manual 1994 order 17965 Am4869 Microprocessor Software User s Manual 1994 order 18497 WI Enhanced Am486 Microprocessor Family Data Sheet 1995 order 19225 Am5x86 Microprocessor Family Data Sheet 1996 order 19751 The CPU core in the lanSC400 and lanSC410 microcontrollers is derived from the Enhanced Am486 microprocessor Family as described in order 19225 The following differences may be relevant to the programmer E There is no floating point unit FPU Bi There is no provision for an L2 cache From a CPU core perspective only the cache is always in write back mode will report this state in response to the CPUID instruction However other logic within the lanSC400 and lanSC410 microcontrollers actually controls whether cache operation is write through or write back on an access by access basis The true default on the lanSC400 and ElanSC410 microcontrollers is write through although all accesses can be write back if desired This is discussed in Section 3 4 One feature of the enhanced Am486 CPU that is fully supported by the lanSC400 and lanSC410 microcontrollers is System Management Mode SMM which is a powerful mechanism fo
534. re more than one set of fonts at a time in the font buffer The number of font sets that can be stored is based on the fixed 16 Kbyte font buffer size and the number of bytes required per font set The number of bytes per font set is based on the size of the font character cell When the cell height see the Maximum Scan Line Register at graphics index 40h and width see the Font Table Register at graphics index 42h have been determined one or more different font sets of identical size again based on the size of the character cell can be stored in the font buffer Then any of the loaded font sets can be quickly selected for display by selecting a font offset between 0 and 31 via graphics index 42h The font buffer format is detailed in Section 20 4 5 3 Managing Graphics Memory The following general guidelines apply Graphics memory must be in system memory DRAM space This means that the address must be lower than the top of DRAM value that is calculated by the DRAM controller when it is programmed iM Graphics memory must not overlap with an MMS window a PC Card window or a region that has been enabled for linear ROMO decode when shadowing has been enabled The possible shadow ROM areas are 00C0000 00FFFFFh Accesses in the range of 00B0000 00FFFFFh that coincide with a graphics frame or font buffer will be directed to DRAM If the access is not in a graphics area and not in ROM shadow ROM MMS or PC Card areas it will go
535. re the main method for configuring the ElanSC400 and ElanSC410 microcontrollers and are discussed in more detail in Section 2 3 3 RTC indexed registers allow access to the real time clock configuration time and date status and the 114 bytes of CMOS RAM thatis typically used by system firmware BIOS in a PC AT compatible system LCD graphics controller indexed registers lanSC400 microcontroller only allow LCD panel configuration and control To conform to different standards in the PC AT architecture the LCD controller can use one of the two different index and data register port addresses listed above If configured to support MDA Monochrome Display Adapter compatibility O3BAh O3B5h are the port addresses that allow access to the Configuration Basics 2 3 2 4 graphics controller s index and data registers If CGA compatibility Color Graphics Adapter is configured O3D4h and 03D5h are used instead PC Card indexed registers ElanSC400 microcontroller only provide PC Card controller configuration status and control The indexed register spaces on the lanSC400 and lanSC410 microcontrollers are accessed via index and data registers which are in turn accessed via sets of direct mapped I O ports This is the double addressing mentioned earlier For each indexed space there is an index port and a data port For example in the case of the original MDA the index port was and the data port
536. read it always reads back a value of 1 for all subsequent reads prior to a RTC reset Real Time Clock 13 7 13 4 5 2 Figure 13 4 13 4 5 3 13 8 6 When the main system power supply is off and the backup battery is initially installed the external RC circuit consisting of R1 and C1 causes a slow rising edge on the BBATSEN input causing the RTC to be reset via an internal power on reset circuit The is then reset or not as described in items 4 and 5 Not Using an External RTC Backup Battery Figure 13 4 shows a specific system implementation with the lanSC400 Microcontroller that does not use an external backup battery to keep the RTC and RAM powered on when the primary system power supply is turned off i e the AVCC source is removed Implementation with No Backup Battery Used AVCC VCC BBATSEN ElanSC400 Microcontroller Referring to the description of the operation of the RTC reset and VRT bit as outlined above this implementation will always reset the RTC and therefore clear the VRT bit whenever the primary system power supply is turned on and a master reset is performed Overall System Implications Using the scheme described above allows the BIOS to detect the state of the backup battery independently of the actual Vcc level that is applied to the RTC i e when the system has booted and firmware reads the VRT bit The state of the VRT bit will reflect th
537. red by the falling edge of the signal Programmable Yes 4 34 qualified with the correct command System Interfaces 4 8 4 8 1 4 8 2 Table 4 17 Register AMD VESA LOCAL VL BUS CONTROLLER Overview The VESA local VL bus controller provides the signals and associated timing necessary to support a single VL bus target compliant with the Video Electronics Standards Association s VESA VL Bus Standard 2 0 The VL bus controller includes the following features B 33 MHz operation at 3 3 V 32 bit data bus Burst mode transfers Control of local bus reset through a CSC indexed register VESA bus mastering and DMA transfers to and from the VL bus target are not supported Note that on the lanSC400 microcontroller the VL bus is only available when the internal graphics controller is disabled in the Internal Graphics Control Register A CSC index DDh 2 Registers A summary listing of the chip setup and control CSC registers used to control the VL bus is shown in Table 4 17 Complete register descriptions can be found the lan SC400 Microcontroller Register Set Reference Manual order 21032 The following CSC indexed registers are used to program the VL bus interface Cache and VL Miscellaneous Register Setting bit in this register enables the VL bus The VL bus reset is also controlled in this register Activity Monitor Registers For power management these registers report that
538. rements The ability of SMM to operate completely transparently to any operating system places several requirements on SMM implementation Anarea of memory the O S is not aware of must be available to store the complete state of the CPU on SMM entry This area is called the State Save Map and is a part of the SMRAM System Management Random Access Memory Code that O S is not aware of must be available to execute the SMM task This code is also stored in SMRAM The effect on the cache of using this data and code space that the O S is not aware of must be carefully considered The ElanSC400 and ElanSC410 microcontrollers offer several options for managing the cache during SMM execution The SMM code itself must not execute for too long or the O S will notice the increased interrupt latency e g by losing characters coming in from a UART System Management Random Access Memory SMRAM As noted above SMM requires an area of memory independent of the O S to store system state when SMM is entered and to store the code that runs during SMM This memory is called SMRAM Because there is no way to inform most legacy operating systems to leave a particular area of RAM alone the lanSC400 and lanSC410 microcontrollers have the ability to hide SMRAM underneath other resources such as ROM or ISA memory space This effectively makes SMRAM invisible to the operating system This hiding is accomplished by changing the value of
539. ress space resource between MMS and SMM functions If there is no overlap between the SMRAM region and upper or high memory no redirection occurs 4 A20M is deasserted so that SMM code can access any address in the system 5 The entire CPU core state is saved at the top of SMRAM in the State Save Map as shown in Table 3 3 State is stored one double word DWORD at a time starting at SMRAM FFFCh and proceeding downward in a stack like fashion Am486 CPU 3 5 3 5 4 1 3 6 6 Interrupts including are disabled and registers are initialized as shown in Table 3 4 Recognition of CPU soft resets is disabled 7 SMM Execution starts at SMBASE 8000h See Section 3 5 5 for more information 8 The SMM routine supplied by the customer or BIOS vendor executes and performs whatever tasks are necessary to deal with the SMI At the end of execution this routine must make sure that the SMI source has been cleared usually by writing a 0 to the appropriate bit in CSC indexed registers 94 97h or 9B 9Ch Then the routine must execute a RSM resume opcode OFh to return from System Management Mode If the source of the SMI is not cleared another SMI is issued immediately upon return from the current SMI Note that the state save is for CPU core registers only For example none of the CSC indexed registers PC AT legacy registers etc are included Since SMI is the highest priority interrupt care must be taken to pr
540. rinter Busy In standard mode this signal is driven by the parallel port device with the state of the printer busy signal In EPP mode this signal is used to add wait states to the current cycle ERROR Error The printer asserts the Error signal to inform the parallel port of a deselect condition paper end PE or other error condition INIT Initialize Printer This signals the printer to begin an initialization routine PE Paper End The printer asserts this signal when it is out of paper PPDWE O Parallel Port Write Enable controls an external 374 type latch in a unidirectional parallel port design This device is used to latch the SD7 SDO bus onto the parallel port data bus To implement a bidirectional parallel port this pin is reconfigured to act as an address decode for the parallel port data port It may then be externally gated with IOR and IOW to provide the Parallel Port Data Read and Write Strobes respectively PPOEN O Parallel Port Output Buffer Enable supports a bidirectional parallel port design PPOEN is used to control the output enable of the external Parallel Port Output Buffer 373 octal D type transparent latch SLCT Printer Select is returned by a printer upon receipt of SLCTIN SLCTIN ASTRB O Printer Selected In Standard mode this signal is driven by the chip to select the parallel port device In EPP mode this signal is driven active by the chip during reads or writes to the EPP address register STRB WRI
541. rizontal Display End and the Horizontal Border End registers thus increasing the dead time between active display of each horizontal line B doubling is enabled by setting the VERTDOUB bit in the Internal Graphics Control Register A the Vertical Adjust Vertical Display End and Vertical Border End registers must be recalculated using twice the number of lines in a character row The Maximum Scan Line Register keeps its same value regardless of the setting of VERTDOUB Forthe example above the number of lines in a character row would become 22 making the programmed values of the Vertical Border End Vertical Adjust and Vertical Display End registers change to 9 20 and 9 respectively B f horizontal dot doubling is enabled each pixel is sent to the display twice making the effective character width double This must be accounted for when setting up the Horizontal Total the Horizontal Display End and Horizontal Border End registers Dual Scan Panel Setup When a dual scan panel is being used an additional set of registers must be programmed in order to facilitate the internal calculation of row line numbers and refresh addresses These are the Dual Scan Row Adjust and Dual Scan Offset Address High Low registers Dual Scan Row Adjust Registers The Dual Scan Row Adjust Register graphics index 3Bh is used in text modes and CGA graphics modes to determine row scan line numbers in the lower screen which correspond to equivalent
542. rmediate PLL Graphics Dot Clock PLL UART CLock On DC Notes 1 The Memory clock is stopped in Standby mode if the graphics controller on the lanSC400 microcontroller is disabled or the LCD is not refreshed 2 Graphics on the lanSC400 microcontroller is programmable to shut down in standby mode If Temporary Low Speed mode is entered from Standby mode the graphics dot and memory clocks may or may not be enabled 3 The UART clock is stopped in Suspend mode or when the UART is disabled via CSC index D1h 0 4 The graphics dot clock and the Graphics Dot Clock PLL are not supported on the lanSC410 microcontroller 6 12 Clock Control EN 7 7 1 The lanSC400 and ElanSC410 microcontrollers contain a sophisticated memory management unit MMU This MMU makes achieving memory mapped PC AT compatibility and 82365 compatibility quite easy for the designer However if the designer wants to do something different there is a lot of information to be learned about the MMU The purpose of this chapter is to explain what the MMU is capable of and how it can be programmed to achieve the designer s goals 7 2 REGISTERS A summary listing of the chip setup and control CSC registers used to control the MMU windows on the lanSC400 and lanSC410 microcontrollers is shown in Table 7 1 Registers used to configure the address spaces for DRAM
543. rnal Graphics Control Register B CSC index DEh 6 2 Program all graphics controller registers load initial memory image and keep the display blanked Port O3x8h 3 3 Set the CSC indexed register lockout bit CSC index DEh 6 and unblank the display Port O3x8h 3 The PMU or software control bit can command the LCD controller to power up or power down in a normal mode or power down in emergency mode These three possible cases are described in Section 20 6 Note The internal RTC must be initialized before the graphics controller can be used This is particularly important for system designs that do not use the internal RTC 20 38 Graphics Controller 20 6 20 6 1 20 6 2 20 6 3 AMD POWER MANAGEMENT Operation of the LCD graphics controller is affected by the power management functions shown in Table 20 16 The graphics controller generates correct sequencing for the external LCD panel power control signals LVDD and LVEE and the LCD timing signals so that power sequencing requirements for various LCD panels can be satisfied The power up and power down sequencing can be activated either by a control signal from the system PMU or by writing to a bit A special battery failure power down mode generates accelerated power down timing so that LCD power can be brought down gracefully under emergency battery fail conditions When enabled this special sequencing is activated by an edge on the BL2 pin The PMU or
544. rns in from BNDSON TDI BNDSON TDI Test Data Input is the serial input stream for boundary scan input data This has weak internal pull up resistor It is sampled on the rising edge of BNDSCN_TCK If not driven this input is sampled High internally BNDSCN TDO O Test Data Output is the serial output stream for boundary scan result data It is in the high TS impedance state except when scanning is in progress BNDSCN TMS Test Mode Select is an for controlling the test access port This has a weak internal pull up resistor If it is not driven it is sampled High internally Reset and Power BBATSEN Backup Battery Sense Real Time Clock backup battery voltage is sampled on this pin each time the AVCC pin has power applied to it followed by a chip master reset If this samples below 2 4 V the VRT bit RTC index ODh will be cleared until read one time At this time the VRT bit will be set until BBATSEN is sampled again BBATSEN also provides a power on reset signal for the RTC when an RTC backup battery is applied for the first time GND Ground Pins RESET Reset Input is an asynchronous hardware reset input equivalent to POWERGOOD in the System architecture Voc 3 3 V DC Supply Pins provide power to the core Vcc ANALOG 3 3 V Supply Pins provide power to the analog section of the chip including the internal PLLs and integrated oscillator circuit Extreme care should b
545. rollers These pins are sampled at reset time and their states at that time are used to configure specific aspects of the chip The pins used for this on the ElanSC400 and ElanSC410 microcontrollers are not dedicated to this function As soon as the reset is deasserted and normal system operation begins the pins are used to implement part of the DRAM interface See Section 4 1 1 1 for more detail Each of the pin strap pins has a very weak internal pull down resistor Thus if no external termination is connected the configuration will act as if external pull downs were applied To select the alternate pin strap function for a particular pin a stronger pull up must be applied externally The external pull ups if used should be 10 kilohms Most configuration options do not need to be configured before the boot code begins to execute In these cases system firmware must configure the chip using Chip Setup and Control CSC registers that are unique to the ElanSC400 and ElanSC410 microcontrollers and are accessed using direct mapped I O ports 22h 23h as described in the following section Although some configuration options are controlled by non CSC registers the vast majority of system configuration is done using the CSC registers Configuration Basics 2 1 CONFIGURATION REGISTER SPACES AND INDEXED ADDRESSING 2 3 2 3 1 Table 2 1 Direct Mapped Registers The lanSC400 and ElanSC410 microcontrollers contain hundreds of co
546. rollers manage up to nine separate physical device memory address spaces All but the ISA memory address space can have a depth of up to 64 Mbytes each The ISA bus memory area is limited to 16 Mbytes The nine memory spaces are listed below System memory address space DRAM il ROMO memory address space ROMCSO ROM1 memory address space ROMCST pin ROM2 memory address space ROMCS2 pin PC Card Socket A memory address spaces common and attribute ElanSC400 microcontroller only PC Card Socket B memory address spaces common and attribute ElanSC400 microcontroller only External ISA VL bus memory address space The system memory address space DRAM is accessible using direct mapped CPU addresses and can also be accessed by the CPU in an indirect method using the Memory Mapping System MMS DRAM is also accessible by the integrated graphics controller on the ElanSC400 microcontroller if enabled The ROMO address space is partially accessible via a direct mapping of the CPU address bus and partially accessible via the MMS The ROM1 and ROM address spaces are only accessible indirectly using the MMS On the ElanSC400 microcontroller the PC Card address spaces are accessed through a separate 82365SL compatible address mapping system The ISA VL bus address space is accessible as a direct mapping of the CPU address bus ISA memory cycles are generated when the CPU generates a memory cycle that is not det
547. rt Infrared Infrared Port DRAM Control Memory Controller ROM Control DRAM Control or Keyboard Interface Matrix XT SCP ISA Bus Controller Keyboard Rows GPIOs or Keyboard Rows Columns or XT Keyboard ISA Control or Keyboard Rows ISA Control ISA Control or Architectural Overview GPIOs 1 2 AMD ARCHITECTURAL OVERVIEW The architectural goals of the ElanSC400 microcontroller included a focus on CPU performance CPU to memory performance and internal graphics controller performance The resulting architecture includes several distinguishing features of interest to the system designer The main system DRAM is shared between the CPU and graphics controller so that the graphics controller can be serviced quickly to maintain video display performance at higher panel resolutions The internal unified memory architecture UMA implemented on the lanSC400 microcontroller means lower cost and less complication for the system designer with only one DRAM interface fewer pins and a much smaller board for many designs CPU to memory performance is critical for both DRAM and ROM accesses The CPU on the ElanSC400 microcontroller has a concurrent path to the ROM Flash interface and can execute code out of ROM Flash at the same time as the graphics controller is accessing DRAM for a screen refresh Many system designs will be able to take advantage of this
548. rt the INPACK interface signal DMA write verify cycles to the PC Card are also supported specifically to support PC Card floppy disk drive controllers DMA Cycle Timing The lanSC400 microcontroller has several enhancements to support DMA to and from PC Cards A PC Card can be either a DMA target or a DMA initiator When a PC Card is a DMA target the PC Card cycles have the same format as normal memory cycles i e the decode for the window hits is handled by the MMU in the same way as cycles originating from the CPU When a PC Card is a DMA initiator the PC Card I O cycles have the same timing as the DIOR and DIOW signals from the DMA controllers These signals are simply gated onto the PC Card and IOW signals respectively DMA Terminal Count cycles and DMA verify cycles are exceptions these cycles have their own state machines that track when to pulse the PC Card I O command signals For DMA Terminal Count cycles a state machine clocked by the DMA clock tracks the type of cycle being requested It waits for the cycle state machine to enter the Command state and if it determines that a PC Card initiated DMA is being serviced and the Command cycle is more than two clocks long it will enter a state that allows the TC input to be enabled onto the WE or OE signal as appropriate When there is one clock left in the Command state it will inactivate the TC signal on WE or OE For DMA verify cycles the IOR command is pulsed one
549. rwise int integer division There is always a direct correspondence between the value programmed into the Offset Register graphics index 3Eh and the number of bytes in a line or row If virtual screen is being used the number of bytes in a line row is based on the size of the virtual screen not the physical screen Note that in 1 BPP flat mapped mode a virtual screen must be an even number of bytes wide If the logical screen and physical screen are the same width the Offset Register may in this case be programmed to an odd value In graphics modes the same principles apply as in text modes except that the height of a character row will be 2 for CGA graphics modes 4 for HGA modes and 1 for flat mapped modes The character width is limited to 8 pixels 16 with horizontal doubling The number of bytes in a horizontal line will depend on the pixel depth For example for 2 bits per pixel with a horizontal width of 640 pixels each byte holds data for four pixels Therefore the number of bytes in a line would equal 640 4 or 160 bytes Graphics Controller 20 4 8 2 3 20 4 9 If the number of horizontal lines is being doubled by setting the VERTDOUB bit in Internal Graphics Control Register A to a logic 1 the effective character box height is doubled so the values programmed into the Dual Scan Row Adjust and Dual Scan Offset Address High Low registers must be calculated using the doubled character height as noted above
550. s LBL2 parallel port PC Card Socket B or GPIOx signals Pin Mux Register C 22h 23h PC Card Socket A second card detect or GPIO page 3 46 Index signal GPIO Termination Control 22h 23h GPIOx and GPIO CSx pull ups and pull 3 47 Registers A D Index 3B 3Eh downs page 3 50 GPIO as Wake Up or Activity 22h 23h Wake up or activity source status GPIO CSx page 3 67 Source Status Registers A B Index 5A 5Bh signals page 3 68 GP CS Activity Enable Register 22h 23h Activity enable forGP_CSA GP_CSDsignals page 3 69 Index 60h primary and secondary activity classification GP CS Activity Status Register 22h 23h Activity status GP CSA GP CSC signals page 3 70 Index 61h Mode Timer SMI NMI Status 22h 23h SMI NMI status GPIOx signals page 3 96 Register Index 96h Access SMI Enable 22h 23h SMI enable I O access to GP CSA or page 3 106 Register B Index 9Ah GP CSB address range Access SMI Status Register B 22h 23h SMI status I O access to GP CSA or page 3 108 Index 9Ch GP CSB address range GPIO CS Function Select 22h 23h GPIO CSx signals activity wake up input or page 3 110 Registers A D Index output page 3 113 GPIO Function Select Registers 22h 23h GPIOx signals inputs or outputs page 3 114 E F Index A4 A5h page 3 115 GPIO Read Back Write 22h 23h GPIO CSx status and control page 3 116 Registers A D Index A6 A9h page 3 119 GPIO PMUx Mode Change 22h 23h Drive GPIO PMUA GPIO PMUD signal
551. s DRAM There are many considerations here depending on which of the above interfaces are used in the system and the voltage at which they are run Because the data is shared PC Card Controller 19 21 19 6 19 22 with other interfaces the card will have to be powered up when it is connected and the system is operating i e not in Suspend mode Because the data bus is bidirectional the voltages become more of an issue DRAM and VL bus in this system are 3 3 V only If the PC Card power plane is to be at 5 V or the ISA bus parallel port or ROM are 5 V then the SD level translating buffer must be added to the system controlled by the lanSC400 microcontrollers DBUFOE DBUFRDL and DBUFRDH signals This will isolate the 5 V devices ISA ROM parallel port PC Card from the 3 3 V devices DRAM and VL bus If the card is to be powered at 3 3 V and the ISA ROM are 5 V then additional buffering is needed to isolate the PC Cards sockets from the ISA ROM devices The lanSC400 microcontroller signal ICDIR is provided for steering this buffer the socket card enables MCEL x and MCEH can be used to enable the buffers IOR IOW Signals Shared with other PC Card socket ISA bus Because the data is shared with other interfaces the card will have to be powered up when it is connected and the system is operating i e not in Suspend mode If the card is to be powered off in Suspend mode then these signals should be
552. s continued Command Timing Registers 19 4 CPU Clock Auto Slowdown Register 6 1 CPU Clock Speed Register 6 1 Cursor Address High Register 20 4 Cursor Address Low Register 20 4 Cursor End Register 20 4 Cursor Start Register 20 4 descriptions xxiv DMA Channel 0 3 Extended Page Register 10 3 DMA Channel 5 7 Extended Page Register 10 3 DMA Resource Channel Map Register A 10 3 DMA Resource Channel Map Register B 10 3 DRAM Bank 0 Configuration Register 9 3 DRAM Bank 1 Configuration Register 9 3 DRAM Bank 2 Configuration Register 9 3 DRAM Bank 3 Configuration Register 9 3 DRAM Control Register 9 3 DRAM Refresh Control Register 9 3 Drive Strength Control Register A 9 3 Drive Strength Control Register B 9 3 Dual Scan Offset Address High Register 20 5 Dual Scan Offset Address Low Register 20 5 Dual Scan Row Adjust Register 20 5 lanSC400 Microcontroller Revision ID Register 3 2 Extended Feature Control Register 20 6 Font Buffer Base Address High Byte 20 5 Font Table Register 20 5 Frame Buffer Base Address Register 20 5 Frame Sync Delay Register 20 5 Frame Font Buffer Base Address Register Low 20 5 general purpose configuration CMOS RAM 13 3 GP CS Activity Enable Register 5 4 17 2 GP CS Activity Status Register 5 4 GP CS to GPIO CS Map Registers 17 3 GP CSA Address Decode and Mask Register 17 3 GP CSA I O Address Decode Register 17 3 GP CSA B Comma
553. s programmed into each DRAM configuration register and all enabled banks are automatically placed contiguously in the memory space There is no direct programmer control over bank location or ordering and there are no bank alignment restrictions for the programmer to worry about For the purposes of length and start address calculation interleaving two banks effectively combines them into a single larger bank CAS Strobe Assertion Byte Lane Selection Table 9 2 shows a mapping of physical addresses to CAS strobes The microcontroller simultaneously issues up to two CAS strobes during a memory cycle addressed to a 16 bit bank or up to four strobes during a cycle addressed to a 32 bit bank The number of CAS cycles required depends on the bank width and the originator of the memory request DMA controller requests are always satisfied in one CAS cycle 8 bit DMA requests assert only one CAS strobe and 16 bit DMA requests assert two CAS strobes and access an aligned word On the ElanSC400 microcontroller graphics controller requests fill up the graphics controller FIFO by burst reading as much data as required via optimized back to back CAS cycles starting with the lowest order address Because the graphics controller only supports 16 bit DRAM reads two CAS strobes are asserted on each cycle CPU requests are always treated by the DRAM controller as 32 bits wide so if the request is addressed to a 16 bit bank two CAS cycles will
554. s the matrix keyboard interface is not available The matrix keyboard signals shown in Table 16 2 are shared with other functions on the ElanSC400 and lanSC410 microcontrollers Support for up to 112 keys is provided with 14 row and 8 column pins dedicated The row signals have built in pull up resistors 7150 Kilohm eliminating the need for external discrete components The column pull ups are programmable to be individually disabled in Suspend mode This eliminates the current draw when a column has been programmed to remain Low in Suspend mode in order to enable a key press as a wake up source The SUS RES signal is also brought into the Keyboard Row registers and the key pressed interrupt logic This signal can be individually disabled With this design the suspend resume functions can be more closely incorporated into the keyboard i e using the SUS RES key with other key presses to initiate system actions like reset If the hardware suspend is not needed in the system design this signal gives another row input for a total of 15 rows and support for up to 120 keys The basic operation of the matrix keyboard interface includes the following steps Write all keyboard columns to 0 via the Keyboard Column Register at CSC index C7h This is required so that a key press on any column will generate an interrupt Note that an SMI or NMI is the only type of interrupt the matrix keyboard interface recognizes as a key pressed interrupt
555. s A B 7 8 MMS windows C F 7 9 PC Card memory management 7 10 Memory Read Command signal See MEMH signal Memory Window Address Offset Registers function 19 4 usage 19 9 19 13 19 15 19 16 Memory Window Address Registers function 19 4 usage 19 13 19 16 Memory Write Command signal See MEMW signal MEMR signal description 4 6 usage 4 29 10 6 17 8 MEMW signal description 4 6 usage 4 29 10 6 17 8 Index Miscellaneous SMI NMI Enable Register CSC index 90h function 5 6 usage 3 5 Miscellaneous SMI NMI Status Register CSC index 94h function 5 6 MMS Window A Destination Register CSC index 32h function 7 2 usage 7 8 MMS Window A Destination Attributes Register CSC index 33h function 7 2 usage 7 8 MMS Window B Destination Register CSC index 34h function 7 2 usage 7 8 MMS Window B Destination Attributes Register CSC index 35h function 7 2 usage 7 8 MMS Window C F Attributes Register CSC index 30h function 7 1 usage 7 9 MMS Window C F Device Select Register CSC index 31h function 7 1 usage 7 9 MMS windows See memory management MMU See memory management Mode Timer SMI NMI Enable Register CSC index 92h function 5 6 Mode Timer SMI NMI Status Register CSC index 96h function 5 6 usage 17 8 Mouse Output Buffer Write Register CSC index C4h function 16 4 usage 16 9 MWE signal control 9 3 description 4 7 usage 9 4 9 12 9 15 N NMI master enable bit 5 30 Non Ca
556. s Port Instruction 21 3 Main Data Scan 21 9 Multiplexed Pin Configuration A 1 Pin Termination B 1 Table of Contents INTRODUCTION SC400 AND lanSC410 MICROCONTROLLERS The SC400 and ElanSC410 microcontrollers are the latest in a series of E86 family microcontrollers which integrate proven x86 CPU cores with a comprehensive set of on chip peripherals The lanSC400 and ElanSC410 microcontrollers combine a 32 bit low voltage Am4869 CPU with a complete set of PC AT compatible peripherals along with sophisticated power management features PURPOSE OF THIS MANUAL This manual describes the technical features and programming interface of the ElanSC400 and ElanSC410 microcontrollers Intended Audience The Elan SC400 and ElanSC410 Microcontrollers User s Manual is intended for computer software and hardware architects and system engineers who are designing or are considering designing systems based on the ElanSC400 and ElanSC410 microcontrollers Overview of This Manual This manual is organized into the following chapters Chapter 1 provides an architectural overview of the ElanSC400 and ElanSC410 microcontrollers including system trade offs and block and system diagrams Chapter 2 is an overview of
557. s a result of data being received from the XT keyboard interface Internal Allows IRQ1 to be generated as aresult of the Keyboard Output Buffer Write Register CSC index C3h being written to Internal Allows IRQ1 to be generated as a result of CSC index C3h being written to Internal Allows IRQ1 to be generated as a result of data being received from the XT keyboard interface or as a result of CSC index C3h being written to When configured like this if either IRQ1 source is being asserted the other source will not be able to generate an IRQ1 Care must be taken in the IRQ1 handler for this specialized case because if both sources of IRQ1 are asserted simultaneously i e a write to C3h is quickly followed by arrival of data from the XT keyboard interface The handler must not exit until one of the following has occurred Both IRQ1 sources are cleared CSC index CO 4 has been toggled after one of the IRQ1 sources hasbeen cleared to generate an edge forthe remaining IRQ source Failure to perform one of the above can result in the loss of further IRQ1 requests being detected by the PIC as an edge is required for this 16 12 Keyboard Interfaces 16 3 4 2 16 3 4 3 16 3 4 4 16 4 16 5 AMD Enabling the XT Keyboard Interface The XT keyboard interface is enabled by setting CSC index C1h 4 Setting this bit does the following Allows the pins XT DATA and XT CLK to become available as keyb
558. s and Peripheral Control ISA Bus Configuration Infrared Port Control and Status PC Card Controller Configuration Chip Revision Note While all possible effort was made to group the controls for related functions together some control bits affect severalfunctional areas of the chip and so may be located in a group other than expected For a complete listing of registers that belong to each of the above groups refer to the Elan SC400 Microcontroller Register Set Reference Manual Configuration Basics 2 4 2 4 1 2 4 2 Do not mistake the Card controller configuration group as listed in Table 2 3 for the 82365 compatible indexed registers that are accessed via I O ports OSEOh and O3E1h This is a good example of configuration versus operational control Configure the PC Card controller will there be one socket or two capable or not etc with the CSC indexed registers When itis configured operate the PC Card controller control PC Card Vpp windows etc with the PC Card controller indexed registers FEATURE TRADE OFFS The ElanSC400 and ElanSC410 microcontrollers are extremely versatile devices that can be configured to support several different feature sets For example on the ElanSC400 microcontroller you can have either an LCD controller ora VESA Local bus a second PC Card socket or a parallel port etc All of these feature trade offs are configured using CSC indexed
559. s deasserted after the transfer is complete and in turn the DMA controller surrenders the bus back to the CPU 10 Steps 5 9 are repeated until the I O transfer is complete The transfer can complete in two possible ways a valid STO flag can be detected or the transfer can be aborted due to the infrared path becoming obstructed etc In either case it is possible to get an interrupt to notify the software of the event When in receive mode CSC index EBh 6 changes meaning from TC EOT status to RFC ABORT RFC stands for Received Frame Complete and this bit will be set when the receive state machine detects the STO flag Note that this does not indicate that the data has been transferred to DRAM yet just that the STO flag has been detected In order to know when the transfer to DRAM is complete poll CSC index EBh 2 after receipt of the RFC ABORT interrupt If the interrupt was due to an abort rather than RFC that status will be available in the CRC Status Register CSC index ECh 7 Interrupts The normal UART interrupts generated due to Receive Buffer Full Transmit Holding Register Empty and status changes do not apply and are not generated in High Speed Infrared mode Special interrupts are supported for this mode including DMA Terminal Count End of Transmission Receive FIFO Overflow and Transmit FIFO Underflow The interrupt request signal from the infrared interface is multiplexed with the IRQ signal of the internal UART Thus
560. s debounce time during which all further edges will be ignored After the debounce time another edge can be detected If a Battery Low input changes polarity during the debounce time and remains changed after 60 ms this other edge will be detected after the first 60 ms debounce time Power Management 5 25 5 4 11 2 1 5 4 11 2 2 5 26 These power saving features occurs on the falling edge the respective Battery Low signal unless ACIN is enabled and active When ACIN goes inactive any active and enabled battery low feature will take affect at that time The state of all Battery Low signals can be read from the Battery AC Pin State Register CSC index 72h 2 0 CPU Clock Speed Reduction BLO and can be programmed to force the microcontroller to disable Hyper Speed mode and use 8 29 MHz as the High Speed CPU frequency or to disable High Speed mode and force the microcontroller to go to Low Speed mode as the highest mode The PMU Force Mode Register does not override the Battery Low feature If the PMU Force Mode Register is used to force Hyper or High Speed the system returns to Low Speed or High Speed due to BLO and Critical Suspend Mode Access Battery Low 2is programmable to force the microcontroller to Critical Suspend mode within 55 us from the falling edge of BL2 and lock the system into this mode to stop it from resuming until it is unlocked The unlock requires special handling because the BL2 sig
561. s in page 3 120 Registers Index AA ADh PMU modes page 3 126 GPIO PMU to GPIO CS Map 22h 23h GPIO PMUA GPIO PMUD mapping to page 3 128 Registers A B Index AE AFh CSx pins page 3 129 GPIO XMI to GPIO CS Map 22h 23h GPIO CSx pin to the internal GPIO page 3 130 Register Index BOh signal SMI or NMI selection 17 2 General Purpose Input Output and Programmable Chip Selects Table 17 1 Register Standard Decode to GPIO CS Map Register Address 22h 23h Index B1h GPIO Register Summary continued GPIO Function Keyword Keyboard controller chip select SCP CS and ROMCS2 mapping to GPIO CSx pins AMD Description in Register Set Manual page 3 131 GP CS to GPIO CS Registers A B 22h 23h Index B2 B3h GP CSA GP CSD mapping to GPIO CSx pins 3 132 page 3 133 GP CSA I O Address Decode Register 22h 23h Index B4h Chip select A address page 3 134 GP CSA I O Address Decode and Mask Register 22h 23h Index B5h Chip select A address mask page 3 135 I O Address Decode Register 22h 23h Index B6h Chip select B address page 3 136 GP_CSB I O Address Decode and Mask Register 22h 23h Index B7h Chip select B address and SA3 SAO0 mask page 3 137 GP CSA B Command Qualification Register 22h 23h Index B8h GP CSA and GP qualified with IOR IOW GP CSA and GP CSA ISA cycle
562. s remains the same the virtual screen cannot be larger than 128 Kbytes in 2 BPP mode and 64 Kbytes in 1 BPP mode These are not the only possible maps other screens up to a maximum of 640x240 or 480x320 are also supported The shared memory frame buffer base address may be programmed to any 32 Kbyte boundary in the system DRAM address space Graphics Controller Figure 20 16 Flat Mapped 1 BPP 640 240 Start Addr Reg Mem Address 0000h Base 00000h Base 00050h Base 04ABOh Frame Buffer Screen 1 Row 1 Screen 1 Row 2 4B00h Base 04B00h Base 04B50h Base 095B0h Screen 1 Row 240 Screen 2 Row 1 19200 bytes Screen 2 Row 2 9600h Base 09600h Base 09650h Base Screen 2 Row 240 Screen 3 Row 1 19200 bytes Screen 3 Row 2 E100h Note Base 3 240 Unused 19200 bytes 7936 bytes AMD Set the start address register to the value shown to display the corresponding screen Figure 20 17 Flat Mapped 2 BPP 640x240 Start Addr Reg Mem Address 0000h Base 00000h Base 000A0h Base 09560h Frame Buffer Screen 1 Row 1 Screen 1 Row 2 4B00h Base 09600h Base 096A0h Base 12B60h Screen 1 Row 240 Screen 2 Row 1 Screen 2 Row 2 9600h Base 12C00h Base 12CA0h Base 1C160h Screen 2 Row 24
563. s system configurations On the ElanSC400 microcontroller the DRAM controller multiplexes between using the system address 25 5 or the address generated by the internal LCD graphics controller depending on which system is accessing DRAM The DRAM controller then generates a separate DRAM address on the MA12 MAO bus The separate DRAM address is a multiplexed row column address required by DRAM devices This use of dual address buses feeding the DRAM controller frees up the system address bus to allow CPU accesses to other peripherals during graphics controller DRAM fetches Address Generation Address SA25 SA12 Am486 A25 A2 M CPU A25 A0 t DMA Controller SA11 SA4 LCD Graphics SA3 SA0 Controller Display Address Controller MA12 MAO DRAM ElanSC400 Microcontroller Controller System Interfaces AMD SYSTEM INTERFACES 4 6 The following system interfaces are described in separate chapters of this book ROM interface Chapter 8 DRAM interface Chapter 9 Parallel port interface Chapter 14 Serial port interface Chapter 15 Keyboard interfaces Chapter 16 Infrared port interface Chapter 18 PC Card interface ElanSC400 microcontroller only Chapter 19 Graphics interface lanSC400 microcontroller only Chapter 20 4 7 ISA BUS INTERFACE 4 7 1 Overview The ISA interface consists of a subset of ISA compatible bus signals allowing for the connection of
564. scription 4 11 RST B signal description 4 11 RSTDRv signal description 4 6 usage 4 1 RTC Alarm Hour Register RTC index 05h function 13 3 RTC Alarm Minute Register RTC index 03h function 13 2 RTC Alarm Second Register RTC index 01h function 13 2 RTC Current Day of Month Register RTC index 07h function 13 3 RTC Current Day of Week Register RTC index 06h function 13 3 RTC Current Hour Register RTC index 04h function 13 2 RTC Current Minute Register RTC index 02h function 13 2 RTC Current Month Register RTC index 08h function 13 3 RTC Current Second Register RTC index 00h function 13 2 RTC Current Year Register RTC index 09h function 13 3 RTC See real time clock RTC RTS signal control 15 2 description 4 10 1 20 5 SA25 SAQ signals control 7 1 7 2 description 4 6 usage 4 24 19 7 SBHE signal control 4 26 description 4 6 usage 4 29 scan keyboard See keyboard interfaces SCK signal description 4 12 usage 20 38 20 39 SCP emulation See keyboard interfaces SD15 SDO signals description 4 6 usage 1 13 4 18 19 8 Segment Base Register usage 3 9 SELDEVICE bit usage 15 7 SELMODE bit usage 18 11 18 12 Serial Data In signal See SIN signal Serial Data Out signal See SOUT signal serial port UART 16450 compatible mode no FIFOs 15 6 16550 compatible mode FIFOs 15 6 baud rate generation 15 4 baud rates at 1 8432 MHz table 15 5 block diagram
565. se 4 50 5019 V 8 19205 104009 Od Od LVS ScVS HI uuo enas Joyejsues euas BEJ Od PIED Od 0dS Slds q91 0850 0199 21590 0189 uuo uuo MOH XEN OYS SZYS aol suwnjop SMOH Jeyeeds CO rs Hune JOMOd dnyoe M 57914 9007 15 49 2 ze 00t 2SUeI3 VIN MO z z OVIN LIVIN i co 5 __ MOJ oa siq 1 a Ho LxXueg O ueg 1 17 Architectural Overview Figure 1 4 troller icrocon th Trade offs lanSC400 lagram System D J0j2euuo2 jos L 199208 PIED Od paesu Joye sues euas yae dang 4 L d vs as dS 5 HES as Od HO Od MO MO sng 5 VSI as WO 1 4009 4901 r YS sng MO QMO ______________________ ________ dnyoeg A ddns
566. self is undefined The mode count value and output of all channels are undefined Each timer channel must be programmed before it can be used The timer clock is either the Low Speed PLL divided by 31 or it is an external oscillator brought in on the CLK IO pin The default is to use the PLL to generate the timer clock If the pin multiplexing registers select CLK IO to be active as an input then the PIT gets its clock from this input For DOS applications the pin should have a stable 1 19218 MHz frequency on it because it will be switched in immediately as the timer clock POWER MANAGEMENT Operation of the programmable interval timer is affected by the power management functions shown in Table 12 3 Power Management in the Programmable Interval Timer Power Power Management Effect Effect PIT Event Description a Activity SM Timer tick IRQO Triggered by the rising edge of internal EE Programmable BE IRQO 12 6 Programmable Interval Timer CHAPTER 1 3 REAL TIME CLOCK 13 1 The designed into the lanSC400 and lanSC410 microcontrollers is compatible with the MC146818A device used in PC AT systems The RTC consists of time of day clock with alarm and a 100 year calendar The clock calendar has a programmable periodic interrupt and 114 bytes of static user RAM and can be represented in either binary or BCD The RTC includes the following features Counts seconds mi
567. sical memory always reflects the actual desired display Memory Management 7 11 7 7 3 1 7 12 The programmer has control over cacheability of BIOS code segments by using the Linear ROMO Attributes Register CSC index 22h For compatibility the BIOS should usually be left non cacheable but in an embedded design it may be desirable to allow it to be cached The programmer also controls the caching of each MMS window MMS and or PC Card caching should only be enabled under very special circumstances such as completely static window mapping as the CPU is not aware of MMU mapping the CPU caching operates using linear memory addresses The programmer should also be careful not to access the same 16 byte cache line through two different linear CPU addresses especially if one of the accesses is non translated and thus cached by default Caching in System Management Mode Caching during SMM operation is controllable using bits 5 and 6 in the Non Cacheable Window 0 Address Attributes SMM Register CSC index 11h By default the cache will be flushed upon entry to SMM and caching will not be enabled during SMM execution The programmer could speed up SMM entry and execution by changing these bits but careful consideration must be given to system issues The following list gives information about each of the possible bit combinations Auto flush enabled SMM caching disabled This is the default state The cache is flush
568. similar to the DRAM controller Relative to the 16 bit ROM interface byte lane usage this is a byte lane switch for RD15 RDO which use V1 VO in a 32 bit ROM configuration but use V3 V2 in a 16 bit ROM configuration Note that any data transfer between either PC Card or ISA controllers always uses byte lanes V3 and V2 In a 32 bit configuration the ROM controller is using byte lanes that were previously used only by the VL and DRAM interfaces so further external buffering may be required Whereas the DBUFOE signal is used to control the electrical connection of the ROM devices with ROM Flash Interface 8 5 8 5 8 6 byte lanes V3 and V2 when 16 bit ROM interface is used with 32 bit DRAM interface the R32BFOE signal is used to control the electrical connection of the ROM devices with byte lanes V1 and VO when a 32 bit ROM interface is used with any DRAM interface width The DBUFRDH and DBUFRDL signals are the data direction controls for the buffers which are connected to bytes lanes V3 and V2 respectively The ROMRD signal is used as the direction control for the V1 and VO byte lane buffers should they be required in the system The use of R32BFOE and associated buffer is at the discretion of the system designer It should be used if the ROM device that is connected to the low word of a 32 bit ROMCSO interface will load the bus too heavily for proper DRAM VL bus operation The use of DBUFOE is also at the discretion of the sys
569. sion Register 19 3 Register 3 1 7 1 index and data I O port usage figure 2 5 Non Cacheable Window 1 Address Register 7 1 indexed configuration register space figure 2 5 Non Cacheable Window 1 Address Attributes indexed register space table 2 3 Register 7 1 Interface Status Register 19 3 Non display Lines Register 20 4 Internal Graphics Control Register A 20 4 Offset Register 20 5 Internal Graphics Control Register B 20 4 Overflow Register 20 5 Internal I O Device Disable Echo Z Bus Overlapping ISA Window Size Register 4 26 Configuration Register 4 26 Overlapping ISA Window Start Address Register internal I O port address map table 2 2 4 26 Interrupt and General Control Register 19 4 Parallel Port Configuration Register 14 3 Interrupt Configuration Register A 11 2 Parallel Serial Port Configuration Register 14 2 Interrupt Configuration Register B 11 2 PC Card and Keyboard SMI NMI Enable Register Interrupt Configuration Register C 11 2 5 6 Interrupt Configuration Register D 11 2 PC Card and Keyboard SMI NMI Status Register Interrupt Configuration Register E 11 2 5 6 IrDA Control Register 18 2 PC Card Extended Features Register 19 3 IrDA CRC Status Register 18 2 Card Mode and Control Register 7 2 19 3 IrDA Frame Length Register A 18 2 PC Card Socket A B Input Pull Up Control Register IrDA Frame Length Register B 18 2 19 3 IrDA Own Address Register 18 2 Pin Mux Register A 17 2 IrDA
570. sly to most commodity FPM Fast Page Mode and EDO Extended Data Out sometimes referred to as hyper page mode 3 3 70 ns DRAM devices The following features and constraints should be considered carefully as they may affect overall system design A Up to four DRAM banks are supported unless the matrix keyboard is to be used see item F below B Each bank has an independently selectable width of 16 or 32 bits However if any DRAM bank is configured to be 32 bits the system must meet these constraints On the lanSC400 microcontroller the internal graphics controller must not be used The internal matrix keyboard interface must not be used see item F below An external buffer might be required for the 16 bit SD bus which is multiplexed with 031 016 and a pull up might be required on CFG3 to reconfigure GPIO CS4 GPIO CS2 as buffer control signals DBUFOE DBUFRDL and DBUFRDH C Each bank has an independently selectable depth and symmetry Symmetry is the term used to describe the DRAM s internal row column configuration e g how close the number of rows is to the number of columns All devices in a given bank must have the same depth and symmetry but the physical width of the devices making up the bank is irrelevantto the lanSC400 and lanSC410 microcontrollers as long as electrical signal loading constraints are not violated Supported device depths and symmetries are listed in Table 9 3 The data sheet for t
571. socket on which an I O window is to be opened Each I O window is defined in terms of a 16 bit start and finish address thus providing I O windows as small as 1 byte and as large as 65536 bytes with 1 byte granularity If the start address is made equal to the finish address the window will be 1 byte wide The PC Card controller makes no attempt to limit where the I O windows are opened in the 0 64 Kbyte range so care should be taken not to conflict with other I O mapped resources especially the PC Card controller index and data registers I O windows have individual enable bits that are located together with the memory window enable bits in the Address Window Enable Register on a per socket basis windows may be forced to 8 or 16 bits in width via a register bit or dynamically sized based on the IOIS16 signal which may be driven by a PC Card The selection of whether this is forced or dynamic is done via a register control bit and would typically be configured by a PC Card device driver when the card is inserted PC Card Bus Cycles The possible PC Card bus cycle types and the associated PC Card command signal are summarized in Table 19 3 Decode tables for each function follow PC Card Supported Cycle Types Cycle Type PC Card Command Signal Memory read attribute or common Memory write attribute or common read write DMA read target DMA write target WE DMA read initiator IOW TC
572. ss High Register 20 4 Start Address Low Register 20 4 SUS_RES Pin Configuration Register 5 3 Suspend Mode Pin State Override Register 5 7 Suspend Mode Pin State Register A 5 7 Suspend Mode Pin State Register B 5 7 Suspend Temporary Low Speed Mode Timers Register 5 3 System Control Port B NMI Status Register 12 1 UART FIFO Control Shadow Register 15 3 Underline Location Register 20 5 Vertical Adjust Register 20 4 Vertical Border End Register 20 5 Vertical Display End Register 20 5 Wake Up Pause High Speed Clock Timers Register 5 3 Wake Up Source Enable Register A 5 4 Wake Up Source Enable Register B 5 4 Wake Up Source Enable Register C 5 4 Wake Up Source Enable Register D 5 4 Wake Up Source Status Register A 5 4 Wake Up Source Status Register B 5 4 Wake Up Source Status Register C 5 4 Wake Up Source Status Register D 5 4 Write Protected System Memory DRAM Window Overlapping ISA Window Enable Register 4 26 XMI Control Register 5 7 Request To Send signal See RTS signal reset CPU reset 4 39 4 40 internal core states table 4 3 SRESET and SMM 3 17 types 4 1 types table 4 2 RESET signal description 4 12 usage 4 1 4 2 13 3 RIN signal control 5 4 5 6 15 2 description 4 9 usage 5 22 5 31 15 8 18 13 Ring Indicate signal See RIN signal ROM Chip Select signals See ROMCS2 ROMCSO signals ROM Read signal See ROMRD signal ROM Write signal See ROMWR signa
573. stal The inverting amplifier AMP is integrated on chip with the feedback resistor and the load capacitors The on chip oscillator circuit can be bypassed by removing the external crystal grounding the 32KXTAL1 pin and driving the 32KXTAL2 pin with an external 32 KHz clock When 32KXTAL1 is grounded the amplifier no longer affects the circuit 32 KHz Crystal Circuit AMP d d Internal External eor rn cm 32KXTAL1 32KXTAL2 32 768 KHz Crystal 32 KHz Oscillator Circuit 2KXTAL1 32 KHz 3 2V Oscillator VAVAV x 32KXTAL2 5 Intermediate and Low Speed PLLs Figure 6 5 shows the block diagram for both the Intermediate and Low Speed PLLs Each consists of a phase detector a charge pump a voltage controlled oscillator VCO an external loop filter and a feedback divider This is a generic implementation of the charge pump PLL architecture all four PLLs use the same architecture The Intermediate and Low Speed PLLs differ only in component values and frequency of operation The phase detector compares the phase and frequency of the two clock signals reference frequency Fr and feedback frequency Ff The Up signal is a logic one if Fr leads Ff while the Down signal is a logic one if Ff leads Fr The Up and Down signals control the charge pump The charge pump either charges or discharges the loop filter capacitors to
574. standard ISA bus compatible timings The wait state control registers in CSC indexes 24h 26h and 28h have no effect in this mode The standard ISA bus IOCHRDY signal may be driven Low during Normal Speed ROM data transfers to add wait states to a ROM cycle Fast Speed Mode Fast Speed mode can be enabled directly by a configuration bit on a per chip select basis Additionally if a ROMCSx interface width is configured for 32 bit operation that interface will automatically be forced to use fast speed timings If Fast Speed mode is selected for a ROMCSx access that access will operate at the same rate as the CPU 1x clock up to a limit of 33 MHz In Fast Speed mode the access time can be slowed down to accommodate slower ROM devices by inserting wait states Wait states tor ROMCSx cycles are controlled using the ROMCSx Configuration Register CSC index 24h 26h and 28h for ROMCSO ROMCS 1 and ROMCS2 respectively The lanSC400 and ElanSC410 microcontrollers provide wait state control for both burst and non burst accesses Note that burst type accesses are not limited to burst mode ROMs The term burstas used here refers to a technology designed into some ROM devices that allows operation with fewer wait states on the second and subsequent accesses that make up a 16 byte transfer than is required on the first access of the transfer The burst mode ROM terminology comes from supporting ROM devices whose internal architecture uses a burst mo
575. start and at the end of the stream STA STO flags Infrared Port 18 7 18 4 2 5 18 4 2 6 18 8 When observing this data stream SIROUT pin the user will see that extra 0 bits have been inserted into the data stream by the infrared transmit hardware for all frame fields except the STA and STO flags This action called zero bit stuffing has two purposes B Synchronization This disallows too much time to pass without a light pulse being emitted remember that a 0 bitis transmitted as a light pulse since the signal is inverted B Allowing a value of 7Eh to be part of the normal non flag data This is required since the STA and STO flags as defined by the IrDA specification are merely bytes of 7Eh FIFO Usage For performance reasons the 16550 FIFOs must be enabled via Port O3FAh or O2FAh when operating in High Speed Infrared mode Even though DMA to the UART is notallowed when operating the UART in normal RS 232 mode or in Slow Speed Infrared mode in High Speed infrared mode DMA is used for all data transfers between main system DRAM and the UART s transmit and receive FIFOs When transmitting data is placed in a buffer located in system DRAM and is then transferred via DMA to the transmit FIFO The transmit state machine takes data from thetransmit FIFO serializes bit stuffs pulse shapes and inverts the data before sending it out the SIROUT pin When receiving the receive state machine takes
576. status receiver line status transmitter holding empty received data available and time out interrupts when COMx DLAB is 0 COMx Interrupt ID Register Ports O2FAh 03FAh A read only register used to identify UART interrupts COMx FIFO Control Register Ports 02F3h 03F3h A write only register used to enable and control the FIFO in 16650 compatible mode COM x Line Status Register Ports 02FDh OSFDh Shows the status of the data transfer including parity and framing errors as well as break and empty indicators COMx Modem Control Register Ports Used to enable COMx interrupts and loopback diagnostic mode and to assert RTS and DTR COMx Modem Status Register Ports 02FEh O3FEh Contains both real time and latched status bits for DCD RIN DSR and CTS Scratch Pad Register Ports 02FFh OSFFh This general purpose I O location can be used to hold temporary data and is not required for serial data transfer 15 2 2 Chip Setup and Control CSC Index Registers A summary listing of the chip setup and control CSC index registers used to control the serial port interface is shown in Table 15 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 Table 15 1 Serial Port Register Summary Description Register Address UART Function Keyword in Register Set Manual Wake Up Source Enable 22h 2
577. stop address and an offset 7 5 7 5 1 NON TRANSLATED MEMORY MANAGEMENT As noted above when performing non translated memory management the MMU simply decides which device space will receive a given memory cycle by examining the memory address provided by the CPU However after examination the address is passed unchanged to the hardware managing that space ROMO and Non Translated Memory Management For most of the CPU address space the default memory space on power up is the ISA VL bus The exceptions are CPU address ranges 00F0000 00FFFFFh and 3FF0000 3FFFFFFh which are mapped to ROMO or PC Card Socket A The CPU boots by jumping to location FFFFFFFOh which is aliased to SFFFFFFh which must execute a far jump to the initialization code Because the CPU boots in Real mode the target of the initial far jump must be in the lower megabyte and for any PC AT compatible BIOS the segment of the jump target will be FOOOh This means that jump target will be in the range 00F0000 OOFFFFFh In atypical boot ROM scenario 5 is connected to a single EPROM or Flash device with a capacity of 128 or 256 Kbytes The upper address lines are not connected to this device so the device is aliased throughout the entire 64 Mbyte address space In this scenario a single contiguous BIOS segment can be programmed into the ROM and the ROM can be treated as if the upper 64 Kbytes are mapped at 70000 and as if the CPU starts execution
578. system and interrupts should be re enabled See Section 4 4 1 for more detail on configuration pin usage Internal Core States Immediately Following Power On Reset Internal Core Ste Comments Internal Am486 CPU Enabled Power Management Unit Enabled High Speed mode 8 MHz ISA Bus Controller Enabled Not all pins available until programmed VL Bus Controller Disabled ROM Flash Controller Enabled Pin straps are used to set the ROM width for ROMCSO and device from which to fetch ROM PC Card DRAM Controller Disabled DMA Controllers Enabled Programmable Interrupt Enabled Although the PIC address decode enable Controllers control is affected by power on reset the internal state of the PICs is not reset until the PICs receive ICW1 Programmable Interval Timer Enabled Real Time Clock Enabled Not reset by a power on reset Parallel Port Disabled Serial Port Disabled Matrix Keyboard Controller Disabled XT Keyboard Controller Disabled GPIOs Enabled System Interfaces 4 3 Table 4 2 Internal Core States Immediately Following Power On Reset continued Internal Core Ste Comments Infrared Port Disabled PC Card Controller Disabled cards is enabled to support using CFG2 to cause reset vector to point to PC Card Socket A The PC Card controller is not supported on the ElanSC410 microcontroller Graphics Controller Disabled The graphics con
579. t card detect state page 6 8 Index 01h memory write protect power status ready and 41h 8 Power and RESETDRV Control 3E0h 3E1h Auto power enable socket Vcc enable Vpp page 6 9 Register Index 02h control and 42h 4B PC Card Controller 19 3 19 1 Register Interrupt and General Control Register Address 3E0h 3E1h Index 03h and 43h B PC Card Controller Register Summary continued PC Card Controller Function IRQ mapping for RDY_x card status change interrupt destination and memory configuration PC Card Reset RST_x ring indicate enable Description in Register Set Manual page 6 11 Card Status Change Register 3EOh 3E1h Index 04h A and 44h CD x x BVD1 x BVD2 x states battery warning battery dead page 6 12 Card Status Change Interrupt Configuration Register 3E0h 3E1h Index 05h A and 45h IRQ mapping for card status change interrupt card status change interrupt on x RDY x BVD1 x or BVD2 x state page 6 13 Address Window Enable Register 3E0h 3E1h Index 06h A and 46h windows 1 and 0 enable memory windows 1 4 enable page 6 15 Window Control Register S3EOh 3E1h Index 07h A and 47h window size and timing set page 6 16 Window Address Registers 3EOh 3E1h Various Window address bits for mapping
580. t the base physical address for the lanSC400 and lanSC410 microcontrollers is 3FF0000h The default instruction pointer value of FFFOh is added to this base address and the result is that the absolute physical address for the first instruction fetch for the lanSC400 and ElanSC410 microcontrollers is 3FFFFFOh as stated above Even though the CPU is in real mode 25 20 will remain asserted until inter segment far jump or call is made When this is done address bits A25 A20 are deasserted by the CPU and the code fetches come from addresses that are below 1 Mbyte Because of this Am486 CPU behavior the lanSC400 and lanSC410 microcontrollers by default support an enabled linear address decode of 64 Kbytes in this high segment of the ROMCSO space to support extended boot code that may want to reside at the top of the ROMCSO space On a typical PC AT compatible system the boot vector behavior is as described above but in the top 15 bytes the code performs a far jump to some entry point in the PC AT compatible BIOS ROM with a code segment of FOOOh As described above the far jump causes subsequent accesses to be performed with A25 A20 deasserted This means that immediately following the far jump code fetches will be from the PC AT compatible BIOS that resides in the 64 Kbyte segment from 00F0000 00FFFFFh To support this PC AT quirk the lanSC400 and lanSC410 microcontrollers enable this region also by default for linear RO
581. tected 16 Kbyte frame buffer relocatable on either 16 Kbyte boundaries within lower 16 Mbytes of system DRAM CGA compatible mode or 32 Kbyte boundaries when the frame buffer is larger than 16 Kbytes flat mapped mode The following graphics mode features are supported 640x200 1 bit per pixel CGA compatible graphics buffer memory map 320x200 2 bits per pixel CGA compatible graphics buffer memory 640x480 2 bits per pixel flat memory map lower resolutions supported Architectural Overview 1 2 14 1 2 15 1 2 15 1 640 480 1 bit per pixel flat memory 1 2 or 4 bits per pixel packed pixel flat x mapped graphics up to 640x240 480x320 with two mapping modes 16 Kbyte window with bank swapping to address up to 64 Kbytes of graphics frame buffer while consuming only 16 Kbytes of DOS Real mode CPU address space Direct mapped no bank swapping with locatable base address up to 128 Kbyte direct addressability Hercules Graphics mode emulation JTAG Test Features Chapter 21 The lanSC400 and lanSC410 microcontrollers provide a boundary scan interface based on the EEE Std 1149 1 Standard Test Access Port and Boundary Scan Architecture The test access port provides a scan interface for testing the microcontroller and system hardware in a production environment It contains extensions that allow a hardware development system to control and observe the microcontrolle
582. ted if enabled DBUFOE is deasserted if enabled DBUFRDH and DBUFRDL are static if enabled IOR is asserted System Interfaces 4 33 4 7 7 4 7 8 Table 4 16 ISA Bus Event Description GPIO CS14 GPIO CS0 IOCHRDY input is ignored if enabled or disabled SD7 SDO is driven with the data that is present on the internal data bus All accesses are performed at ISA bus speeds when the CSC indexed register echoing feature is enabled If a particular core feature is disabled the individual CSC indexed registers associated with that core can still be accessed and if the echo feature is enabled will be echoed onto the ISA bus The actual register bits may or may not be functional in this state Note that since DBUFOE is always deasserted in the above listed scenarios echoed data will never be seen past the system data bus buffers if any are used in the system Initialization The ISA bus controller is enabled at power on reset Power Management The power management unit monitors the MEMR and MEMW signals for activity The internal clock for the ISA bus controller is shut off when no ISA accesses are being performed Operation of the ISA bus controller is affected by the power management functions shown in Table 4 16 Power Management in the ISA Bus Controller Power Management Effect wakeup su wur Triggered by the falling edge of the signal Primary GP CSA GP CSD Trigge
583. tem The only mode changes that occur for an SMI NMI are changes to restart the clocks for interrupt servicing Power Management 5 1 5 2 5 2 1 5 2 Battery control The ACIN BL2 BLO battery monitoring signals B Timer time out Each mode has a timer that allows the PMU to drop to the next mode e g High Speed drops to Low Speed when the timer times out Events A generic label to indicate any or all of the above terms PMUA PMUB PMUC and PMUD Up to four GPIO CS pins can be programmed to inform external hardware of internal PMU states The internal signal names associated with this information are PMUA PMUB PMUC and PMUD REGISTERS A summary listing of the chip setup and control CSC registers used to control the PMU is shown in Table 5 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 PMU Mode Control and Status Registers CSC index registers 40 45h are used for mode control and status reporting Important features of these registers include B A register for software to immediately program the PMU to any of the modes The PMU Force Mode Register CSC index 40h immediately takes the system to the programmed PMU mode If the programmed mode is the mode the system is already in the associated mode timer is reset register to read the present mode and the last mode the PMU was The PMU Present and
584. tem designer but will probably be required if the system allows use of PC Card or ISA expansion buses INITIALIZATION A portion of the ROM Flash interface is enabled at power on reset to support boot up of system firmware By default only two regions are enabled by the ROM controller They are enabled for ROMCSO and for linear accesses only These regions are the 64 Kbyte block from S3FF0000 3FFFFFFh that encompasses the normal CPU boot vector segment and the 64 Kbyte block from 00F0000 00FFFFFh that encompasses the aliased boot vector segment On an x86 CPU the normal boot vector the place where the CPU fetches the first instruction after reset will be at the top of the address space minus 15 bytes Because the ElanSC400 and ElanSC410 microcontrollers do not in any way utilize the CPU address bits A32 A26 these address bits are ignored and only the 26 address bits from A25 A0 are used to specify the boot vector This means that on the lanSC400 and lanSC410 microcontrollers the normal boot vector will be 3FFFFFOh instead of FFFFFFFOh for a standard Am486 microprocessor and the first instruction following reset will be fetched from this location After reset on an Am486 CPU the code segment register is set to FOOOh and A31 A20 effectively A25 A20 on the lanSC400 and lanSC410 microcontrollers are held in the asserted state Because segment registers must be multiplied by 16 to obtain the base physical address at rese
585. tem goes to Hyper Speed mode unless High Speed mode was entered by the Hyper Speed timer time out Note that if Hyper Speed mode is enabled and a write to the PMU Force Mode Register CSC index 40h forced High Speed mode the system goes to Hyper Speed mode The system is in High Speed mode and a primary activity happens The same PLL start up time restrictions apply Leaving Hyper Speed Mode The system leaves Hyper Speed mode when any of the following occurs i The Hyper Speed mode timer times out The system drops to High Speed mode B The system is programmed directly out with the PMU Force Mode Register The system can go to any other mode The SUS RES signal toggles f enabled forces the system directly to Suspend mode B BLO or BL2 go Low programmable option using CSC index 70 711 BL2 causes a mode change to Critical Suspend mode if enabled and ACIN is not active BLO or BL1 causes a mode change to Low Speed mode or High Speed mode 8 MHz if enabled and ACIN is not active High Speed Mode This mode is used when performance is more valuable than battery life High Speed mode does not use the CPU core PLL for operation it drives the enhanced Am486 CPU core in static clock mode High Speed mode can be disabled by enabling and asserting the BL2 BLO inputs CSC index 70 and 71h When this occurs activities that normally caused a mode change to High Speed go to Low Speed instead Only the
586. ter the RSM continues with the instruction after the HLT otherwise the HLT is re executed The SMI handler should never set this bit doing so causes unexpected behavior when the interrupted instruction is not a halt Trapping Restarting Instructions An I O instruction is said to be trapped if address decode logic external to the CPU core asserts the SMI input to the CPU during an I O cycle The ElanSC400 and ElanSC410 microcontrollers have several programmable sources for enabling SMI generation based on certain I O address cycles being decoded When any of these is enabled and the specified I O access occurs SMM will be entered as a result of an I O trap The Trap Restart feature allows a trapped I O instruction to be restarted This feature is very useful for power managed systems For example consider a system with a floppy disk controller that may be shut off to conserve power The operating system knows nothing of this power management so the power management must be completely transparent to the O S If the power management firmware decides that the floppy should be turned off perhaps because of a PMU timer time out it can turn off the floppy controller and then can turn on trapping for floppy disk accesses by setting bit 0 in the Access SMI Enable Register B CSC index 9Ah 0 When the O S next attempts to read from or write to a floppy controller address the instruction will be trapped and the SMI h
587. terface is shown in Table 18 1 Complete register descriptions can be found in the lan SC400 Microcontroller Register Set Reference Manual order 21032 CSC index registers for power management and SMI NMI control in the UART are listed in Chapter 15 in Table 15 1 Table 18 1 Register Clock Control Register Address 22h 23h Index 82h Infrared Port Register Summary Infrared Port Function Keyword DMA clock frequency select for High Speed Infrared mode Description in Register Set Manual page 3 90 Parallel Serial Port Configuration Register 22h 23h Index Dih COM1 or COM base address configuration UART enable page 3 167 UART FIFO Control Shadow Register 22h 23h Index D3h Shadow FIFO control 16550 compatible mode enable FIFO buffer clear trigger for received data available interrupt pending page 3 169 Interrupt Configuration Register E 22h 23h Index D8h IRQ mapping for infrared port page 3 174 DMA Resource Channel Map Register A 22h 23h Index DBh DMA controller channel mapping for infrared port page 3 177 IrDA Control Register 22h 23h Index EAh Infrared mode enable infrared data rate Slow Speed and High Speed mode DMA start up interrupt requests data direction receive blocking SIRIN pull down disable and end of transmission status page 3 188 IrDA Status Register 22h 23h Index EBh Transmit and receive FIFO status
588. ternal DMA request Triggered by rising edge of PDRQO or Programmable PDRQ1 if PDRQ is enabled and mapped to a DMA channel and Pin Mux Register A CSC index 38h 0 selects the DMA function of the pin DMA Controller 10 9 10 10 Controller REN 1 1 PROGRAMMABLE INTERRUPT gt CONTROLLER 11 1 OVERVIEW Dual cascaded 8259 compatible programmable interrupt controllers support 15 user interrupt levels The two internal devices are internally connected on the ElanSC400 and ElanSC410 microcontrollers and must be programmed to operate in Cascade mode Eight external interrupt requests PIRQ7 PIRQO can be mapped to any of the 15 internal IRQ inputs The programmable sources for interrupts going into the programmable interrupt controller PIC block are controlled through the CSC and PC Card index registers The interrupt controller block includes these features Software compatibility with PC AT interrupt controllers 15 level priority controller Programmable interrupt modes Individual interrupt request mask capability Accepts requests from peripherals Resolves priority on pending interrupts and interrupts in service Issues interrupt request to processor Provides interrupt vectors for interrupt service routines Tied into the PMU for power management The interrupt controller block is functionally compatible with the standard cascaded 8259A controller pair as implemented in the PC AT system The mast
589. th D1 and D2 are required to have a maximum forward voltage drop of 0 25 V at a forward current of 100 uA Figure 13 3 Backup Battery Used to Power RTC D1 D2 Y m p NU VCC RTC BBATSEN Gil 7 ElanSC400 Microcontroller RTC index ODh contains the VRT Valid RAM and Time bit This bit can be sampled at system boot time by the BIOS to determine whether or not the RTC time date and user RAM are valid since the last boot The operation of the RTC reset and bit is outlined below for the circuit in Figure 13 3 1 The VCC_RTC pinis a dedicated power supply pin for the 32 KHz crystal oscillator and the RTC 2 When the primary system power supply is turned on the analog pin AVCC drives the VCC_RTC pin through an external diode 3 When the primary power supply is turned off or non functional VCC_RTC is driven by the backup battery through a second external diode 4 An on chip voltage monitor circuit monitors the voltage level of the backup battery through the BBATSEN pin every time the system primary power supply is initially applied the AVCC pin has power applied to it and the ElanSC400 microcontroller s master reset RESET pin is deasserted 5 If the backup battery is sampled below 2 4 V the RTC logic is completely reset The read only bit RTC index ODh 7 is cleared and latched in this state until the bit is read After this bit is initially
590. th Wee 8 51 Normal Speed Non Burst 8 bit don t care 8 bit Fast Speed Non Burst 0x 8 bit don t care 1 16 bit Normal Speed Non Burst 10 16 bit don t care 0 16 bit Fast Speed Non Burst 10 16 bit 0 1 16 bit Fast Speed Burst Capable 10 16 bit 1 1 32 bit Fast Speed Non Burst 11 32 bit 0 don t care 32 bit Fast Speed Burst Capable 11 32 bit 1 don t care Notes Non burst Not capable of burst mode ROM interface timings Burst capable Capable of burst mode ROM interface timings under conditions specified in bit 3 of CSC index registers 23h 25h and 27h 8 6 POWER MANAGEMENT To improve power dissipation the ROM Flash interface s internal clock is turned off if there is no access to the interface or if the access is to the ISA bus Operation of the ROM Flash interface is affected by the power management functions shown in Table 8 4 Table 8 4 Power Management in the ROM Flash Interface Power Management Effect ROM Flash Interface Ben su wr ROM access Triggered by the falling edge of the Programmable ROMCS2 ROMCSO chip selects qualified with the command ROM Read Write ROM Flash Interface 8 11 8 12 ROM Flash Interface EN 9 1 9 DRAM CONTROLLER SYSTEM DESIGN The lanSC400 and ElanSC410 microcontrollers can directly control up to 64 Mbytes of DRAM The integrated DRAM controller interfaces glueles
591. th internal read write registers and typically used as external writable ports for diagnostics they must be handled differently All I O writes to these registers are run as ISA and internal cycles In addition AEN will not be asserted and DBUFOE DBUFRDH and DBUFRDL will be asserted This allows the ISA bus cycle to modify any external ISA bus register that may be present during a write cycle i e Port 0080h debug card All write accesses that are not decoded as direct mapped register accesses or CSC indexed register accesses will be driven onto the external ISA bus with all enabled ISA control signals available assuming the cycle is not claimed by a device on the VL bus External cycles are first given to the VL bus if not claimed they default to the ISA bus Direct Mapped Register Reads During an I O read to a direct mapped register when the echo feature is enabled the following activity occurs on the external ISA bus The I O address is driven out onto the SA bus SA23 SAO SBHE is driven out if enabled BALE is driven out if enabled 516 and IOCS16 inputs are ignored if enabled or disabled B AEN is asserted if enabled B DBUFOE is deasserted if enabled B DBUFRDH and DBUFRDL are static if enabled IOR is asserted IOCHRDY input is ignored if enabled or disabled SD7 SDO is driven with the data that is present on the internal data bus There are some internal PC AT Core reg
592. the destination socket for PC Card memory cycles as shown in Table 19 13 Note that in Enhanced Mode the bits MEM WIN SEL 3 0 have no effect on PC Card cycles all five memory windows for each socket are available to that socket only Memory Window Socket Mapping CSC Index FOh MEM_WIN_SEL Socket A Memory Windows 1 4 Socket Mapping CSC Index MEM WIN SEL Socket A Memory Windows 1 4 Socket Mapping 0000 0h 1 2 3 4 None 1000 8h 2 3 4 1 1 3 4 2 3 4 1 2 1 2 4 3 24 1 3 14 23 4 When hit to one of the Socket A memory windows 1 through 4 is decoded the bits MEM WIN SEL 3 0 determine which socket s MCEL x MCEH x and REG x pins are actually activated Table 19 14 outlines the effects the redirection has on the socket specific PC Card cycle control signals In the table the status of the REG x pin is described in terms of how the REG ACT bit in the Memory Window Address Offset High Register for the hit window is used PC Card Controller 19 15 19 14 MEM WIN SEL Memory Window Memory Window Redirection Effects Socket B 1 Socket A Active win 1 REG ACT Inactive Inactive 1 Socket B Inactive Inactive Active win 1 REG ACT 2 Socket A Active win 2 REG ACT Inactive Inactive 2 Socket B Inactive Inactive Active win 2 REG ACT 3 Socket A Active win 3 REG ACT Inactive Inactive 3 Soc
593. the GPIO_CS14 GPIO_CS0 pins This process is described in Section 7 7 2 8 2 ROM Flash Interface Figure 8 1 8 4 8 4 1 AMD ROM Flash Interface Block Diagram SA25 SA4 Addresses SA3 SA0 015 00 Data D15 DO 32 bit ROMs ROMSCO ROMCS1 ROMCS2 ROMRD ROMWR R32BFOE CFG3 CFG2 CFG1 CFGO ElanSC400 Microcontroller OPERATION Architectural Overview The ROM controller provides for control over three ROM interfaces and each of the interfaces may be individually configured for interface width 8 16 32 bit with 26 bit 64 Mbyte addressability Although there is a chip select ROMCSO ROMCS 1 and ROMCS2 that is dedicated to each of these ROM interfaces the remainder of the standard bus signals are shared The ROM interfaces also share two signals that are specific to the ROM interface ROMRD and ROMWR These signals are similar in function to the ISA MEMR and MEMW commands but provide further isolation of the ROM interface from the ISA bus and also support the non ISA standard timings that are present when Fast Speed ROM mode is enabled Each of the three interfaces has separate configuration and timing controls Of the three interfaces only ROMCSO may be accessed via direct mapped non MMS translated memory cycles and only the regions between 00C0000 00FFFFFh and SFF0000h 3FFFFFFh are included in this direct mapped access capability To access the remain
594. the IRQ routing to the interrupt controller level for High Speed Infrared mode IRQs is controlled by the same bits as for the UART in the Interrupt Configuration Register E CSC index D8h 6 5 The IRQ_ENABLE bit along with the SELMODE bit in the IrDA Control Register acts as the select signal Upon interrupt request the interrupt handler can read the infrared port status registers to find the cause and then process the interrupts accordingly RECV BLOCKING bit CSC index 5 is provided to disable the receive section while in transmit mode This prevents any leakage or erroneous data being captured while transmitting This feature can be disabled by clearing the BLOCKING bit Serial Infrared Interaction Pulse SIP Generation In High Speed Infrared mode the IrLAP specification requiresthe infrared portto be capable of generating a Serial Infrared Interaction Pulse SIP A SIP is used to quiet Slow Speed Infrared mode traffic in the local vicinity of the High Speed Infrared mode traffic The SIP Infrared Port AMD is required to be generated once each 500 ms when the primary station generating the pulses is not actually transmitting To do this on the lanSC400 and ElanSC410 microcontrollers software must put the infrared controller into Slow Speed Infrared mode at 9600 baud with the UART set up for 1 start bit and no parity Then a value of FFh must be written to the COMx Transmit Holding Register Port O2F8h 0
595. the basic concepts required to configure the microcontroller It discusses the direct mapped and indirect mapped indexed register spaces Chapter 3 discusses the integrated Am486 CPU and how it differs from other Am486 CPUs Also included is information on cache memory management System Management Mode SMM and core CPU identification methods Chapter 4 describes the system interfaces on the microcontroller including initialization pin descriptions and configuration data and address buses and example bus configurations The ISA and VESA local VL bus interfaces as well as the PC AT port logic are also described Chapter 5 describes the power management features of the microcontroller including power management modes of operation flowcharts and control functions Chapter 6 describes how to control the clocks on the microcontroller Also included is a description of clock generation Chapter 7 discusses memory management on the microcontroller Subjects include address decoding and aliasing memory spaces and translated and non translated memory management Chapter 8 describes the ROM Flash interface including configuration and initialization Chapter 9 covers the DRAM controller including system design issues system address decoding timing and control signal generation and initialization Introduction xxi xxii Chapter 10 describes the PC AT compatible DMA controller Chapter 11 des
596. the incoming bit stream from the SIRIN pin inverts pulse stretches un bit stuffs and then places it into the receive FIFO on the UART from which point it is transferred via DMA to DRAM Receive and Transmit State Machines In High Speed Infrared mode the UART receive and transmit serializers and controlling state machines have some properties that are specific to High Speed Infrared mode operation First the receiver state machine filters all incoming data before starting to put anything in the receive FIFO This filtering consists of waiting for a valid STA flag to be detected Upon seeing this it enables bit unstuffing to occur and then starts looking for the address byte which should come right after the STA flag s If the received address does not match the broadcast address FEh or the address that has been programmed into the IrDA Own Address Register CSC index EDh the receive state machine will not place the data into the receive FIFO but will instead begin looking for STA flags again This avoids software from handling frames that were destined for another station If a match does occur the data is deserialized and placed into the receive FIFO From the data in the payload field the infrared receive state machine calculates a 16 bit CRC and compares it against the one which was received at the end of the frame If the calculated CRC and the received CRC do not match then a register bit in the CRC Status Register
597. tification code to be shifted out of the device on BNDSCN_TDO Note that the DID is not altered by data being shifted on BNDSCN TDI HIGHZ The instruction code is 0011 The HIGHZ instruction connects the Bypass Register between BNDSCN_TDI and BNDSCN This instruction makes all outputs both two and three state on the ElanSC400 and ElanSC410 microcontrollers disabled or puts them in a high impedance state BYPASS The instruction code is 1111 The BYPASS instruction selects the bypass register to be connected to BNDSCN TDI or BNDSCN_TDO effectively bypassing the test logic on the ElanSC400 and ElanSC410 microcontrollers by reducing the shift length of the device to one bit Note that an open circuit fault in the board level test data path causes the Bypass Register to be selected following an instruction scan cycle due to the pull up resistor on the BDNSCN TDI input This has been done to prevent any unwanted interference with the proper operation of the system logic Test and Debugging 21 3 AMD TEST ACCESS PORT CONTROLLER OPERATION The TAP controller is a synchronous finite state machine that controls the sequence of operations of the test logic The TAP controller changes state in response to the rising edge of BNDSCN TCK and defaults to the Test Logic Reset state at power up Re initialization to the Test Logic Reset state is accomplished by holding the BNDSCN TMS pin High for five BNDSCN TCK periods The TAP co
598. tions 4 10 system scenarios 16 10 matrix keyboard with PC AT compatibility 16 11 simple matrix keyboard with interrupts 16 10 simple matrix keyboard with polling 16 10 XT keyboard interface 16 2 16 12 controlling 16 13 enabling 16 13 interrupts 16 12 IRQ1 generation table 16 12 timing 16 13 Keyboard Output Buffer Write Register CSC index C3h function 16 4 usage 16 9 16 11 Keyboard Row Register A CSC index C8h function 16 4 usage 16 5 Keyboard Row Register B CSC index C9h function 16 4 usage 16 5 Keyboard Status Register Write Register CSC index C5h function 16 4 usage 16 9 AMD Keyboard Timer Register CSC index C6h function 16 4 L Latched Battery Low Detect 2 signal See LBL2 signal LBL2 signal description 4 8 LC signal description 4 12 usage 20 38 20 39 LCD Panel AC Modulation Clock Register graphics index 41h function 20 5 LCD Panel AC Modulation signal See M signal LCD Panel Data signals See LCDD7 LCDDO signals LCD Panel Line Clock signal See LC signal LCD Panel Line Frame Start signal See FRM signal LCD Panel Shift Clock signal See SCK signal LCD Panel VDD Voltage Control signal See LVDD signal LCD Panel VEE Voltage Control signal See LVEE signal LCD See graphics controller LCDD7 LCDDO signals description 4 12 usage 20 38 20 39 LF HS signal description 4 9 usage 6 3 LF INT signal description 4 9 usage 6 3 LF LS signal description 4 9 usage
599. tions associated with aliasing on the ElanSC400 and ElanSC410 microcontrollers which must be thoroughly understood by the designer before attempting to use the memory management features The rest of this chapter assumes a full understanding of the implications of the architectural features discussed in this section Internal Address Bus Size The internal address bus on the lanSC400 and lanSC410 microcontrollers is 26 bits wide Even though the Am486 CPU has a 32 bit address bus the top six address lines are not connected even internal to the ElanSC400 and ElanSC410 microcontrollers This means that from a programming perspective the ElanSC400 and ElanSC410 microcontrollers can see 64 Mbytes of memory at a time memory that is aliased 64 times into the 4 Gbyte physical address space of the Am486 CPU Special Handling for A20 The Am486 CPU contains logic to perform special handling for A20 Because the ElanSC400 and ElanSC410 microcontrollers are designed to be PC AT compatible they contain logic to allow backward compatibility all the way to the 8088 One of these 8088 features is the address wrap that occurs from the top of its 1 Mbyte memory back down to the bottom of memory The Am486 CPU core is required to have direct support for this because aliasing must occur even before the internal cache sees the address to support backward compatibility The Am486 CPU performs this function with the A20 control gate which can force
600. tive card interfaces These pins are not supported on the ElanSC410 microcontroller PCMA VCC PC Card Socket A Enable can be used to control the to socket A This pin is not supported on the ElanSC410 microcontroller PCMB VCC PC Card Socket Enable be used to control the Vcc to socket This pin is supported on the ElanSC410 microcontroller PCMA VPP2 O PC Card Socket A VPP Selects can be used to control the VPP to socket A These pins are PCMA VPP1 not supported on the ElanSC410 microcontroller PCMB VPP2 O PC Card Socket B VPP Selects can be used to control the VPP to socket B These pins are PCMB VPP1 not supported on the ElanSC410 microcontroller RDY A Card Ready indicates that the respective card is ready to accept a new data transfer RDY B B command When the card interface is configured as an I O interface this signal is used as the card Interrupt Request input into the chip These pins are not supported on the ElanSC410 microcontroller REG A DACK O Attribute Memory Select signals are driven inactive High for accesses to a PC Card s REG B DACK B Common Memory and asserted Low for accesses to a PC Card s Attribute Memory and space for their respective card interfaces When PC Card DMA is enabled the DMA acknowledge to the PC Card will appear on this signal These pins are not supported on the ElanSC410 microcontroller RST A RST B Card Reset sign
601. to Low and High CASLx and signals to support interleaving Banks 0 and 2 share CASL3 CASLO and banks 1 and share Banks configured for 16 bit operation do not use CASL3 CASL2 2 or D31 D16 and if the matrix keyboard controller is to be used CASL3 CASL2 CASH3 CASH2 RAS3 RAS2 and MA12 may not be used by the DRAM array Figure 9 1 DRAM Bank Configuration D31 DO MA12 MAO 6 1 24 D23 1 D15 D D7 D 03 3 16 215 08 0 RAS3 lt NIS CASH2 CASH CASHO d MWE N 5 031 024 023 016 015 08 07 00 ASD CASL2 CASLT 023 016 015 08 07 00 RAST amp CASHS CASH CASHO CASH3 CASHO 031 024 023 016 015 08 07 00 RASO CASL2 CASLT CASLO CASL3 CASLO Note The shaded area of each bank and its associated signals are used for 32 bit DRAM only The OE signals for all banks should be grounded since the ElanSC400 and lanSC410 microcontrollers implement early write 9 4 DRAM Controller 9 4 9 4 1 9 4 1 1 9 4 1 2 AMD OPERATION System Address Decoding The DRAM controller receives physical addresses from the CPU the DMA controller and the graphics controller and decomposes them as follows B The DRAM controller uses information about each bank s address and size to select th
602. to both identify itself as 82365SL Rev B compatible and identify the ElanSC400 microcontroller specific features that are available The default read value is 82h In orderto read the lanSC400 microcontroller specific value these steps must be followed 1 The Identification and Revision Register index value 00h for Socket A 40h for Socket B must be written to the PC Card controller index register at 2 The PC Card controller data register at 1 must be written This write goes to the Identification and Revision Register which is read only in the 82365SL Rev B For this reason the lanSC400 microcontroller s PC Card controller ignores the data written and records only the fact that the write occurred PC Card Controller 19 23 3 The controller data register at 1 must be read immediately after step 2 4 f any other reads or writes occur between steps 2 and 3 the mechanism is broken and the 82365SL Rev B compatible value of 82h is read back Thus these steps must be surrounded with STI CLI CPU instructions to avoid an interrupt handling routine from disarming the PC Card controller stepping level read back circuit 19 7 POWER MANAGEMENT The PC Card controller core manages its own power by gating its clock The clock is enabled only when the following conditions are true cycle has been started Any CPU cache line write back due to PC Card initiate
603. trol cell The control cell for the first group is the last element in the scan chain Main Data Scan Path Cell Comment Type 281 CD A Input 280 Input 279 WAIT AB Input 278 WP A Input 277 BVD2 A Input 276 BVD1 A Input 275 GPIO25 Input 274 GPIO25 Output 273 GPIO22 Input 272 GPIO22 Output 271 GPIO30 Input 270 GPIO30 Output 269 GPIO31 Input 268 GPIO31 Output 267 GPIO24 Input 266 GPIO24 Output 265 GPIO26 Input 264 GPIO26 Output 263 21 Input 262 21 Output 261 GPIO23 Input 260 GPIO23 Output 259 GPIO29 Input 258 GPIO29 Output 257 GPIO28 Input 256 GPIO28 Output 255 GPIO27 Input 254 GPIO27 Output 253 N A Control cell Controller for miscellaneous cells 252 SPKR Output 251 RESET Input 250 RTS Output 249 SIROUT Output 248 DTR Output 247 DCD Input Test and Debugging 21 9 Table 21 2 Main Data Scan Path continued JTAG Cell m Paname Comment O 21 10 246 SIRIN Input 245 Input 244 CTS Input 243 SOUT Output 242 SIN Input 241 RIN Input 240 ACIN Input 239 RSTDRV Output 238 SUS RES Input 237 BL2 Input 236 BLT Input 235 BLO Input 234 BLO Output 233 GPIO19 Input 232 GPIO19 Output 231 GPIO18 Input 2
604. troller is not supported on the ElanSC410 microcontroller 4 1 1 2 Am486 CPU DX Register at CPU Reset The DX register always contains a component identifier at the conclusion of the CPU reset process The upper byte of DX DH contains 04h and the lower byte of DX DL contains a CPU type stepping identifier Table 4 3 shows the value in the DX register after CPU reset Table 4 3 CPU ID Codes CPU Type and Cache Mode Component Revision During CPU Reset ID DH ID DL SX1 in write back mode 4 4 System Interfaces 4 2 SIGNAL DESCRIPTIONS The descriptions in Table 4 4 are organized in alphabetical order within the functional group listed here System Interface Configuration Pins Memory Interface VL Bus Interface Power Management Clocks Parallel Port Serial Port Keyboard Interfaces General Purpose Input Output Serial Infrared Port PC Card ElanSC400 Microcontroller Only LCD Graphics Controller ElanSC400 Microcontroller Only Boundary Scan Test Interface Reset and Power Table 4 4 Signal Description Table Signal Type Description System Interface AEN O DMA Address Enable is used to indicate that the current address active on the SA25 SAO0 address bus is a memory address and that the current cycle is DMA cycle All I O devices should use this signal in decoding their I O addresses and should not respond when this signal is asserted When AEN is asserted the PDACK1 PDACKO sig
605. ts like Suspend in that only a wake up can change the mode to High or Low Speed activities and ACIN do not change the mode A force mode register write however can change to any other mode Actions Taken During Temporary Low Speed Mode The following actions are taken in the ElanSC400 and ElanSC410 microcontrollers during Temporary Low Speed mode CPU clock goes to the programmed Low Speed mode rate A summary of clock speeds per PMU mode is shown in Table 6 6 All other clocks go to the appropriate Low Speed mode rate Except LCD graphics if it was disabled in the mode the PMU is coming from Temporary Low Speed mode timer is started Entering Temporary Low Speed Mode The system goes to Temporary Low Speed mode when one of the following occurs secondary activity is received in Standby mode fasecondary activity happens in Temporary Low Speed mode the timer is restarted An SMI NMI is triggered while in the Standby mode or by a Suspend timer time out SMI NMI in Suspend does not cause the PMU to go to Temporary Low Speed unless itis caused by the Suspend timer time out The system goes to Temporary Low Speed mode to service the SMI NMI During the interrupt service routine the PMU Force Mode Register can be used to change the PMU mode to any other mode rather than letting the system go back to Suspend or Standby mode Programmed directly with the PMU Force Mode Register Power Management 5 17
606. tup registers for an 8x8 character cell Character Cell Cursor Start 5 Cursor End 6 Maximum Scan Line 7 gt lt gt 24 gt 24 gt lt gt 24 gt 24 Fonts The character fonts are stored in memory as a bit map representing the shape of the character 256 different font characters are stored in each font area representing character codes from to OFFh A relocatable 16 Kbyte block of memory is allocated for font storage The font memory is organized so as to maximize system DRAM page hits during text display refresh The font memory may be independently write protected The 16 Kbyte font memory area is divided into 32 pages of 256 words Each page corresponds to the pixel information of a particular scan line Up to 32 scan lines may be used in the vertical dimension of a font The Maximum Scan Line Register graphics index O9h is used by the graphics controller to determine the displayed vertical height of the font The horizontal dimension is selectable Graphics Controller Table 20 8 AMD as 8 10 or 16 bits The displayed pixel information is left justified and the odd and even bytes are swapped see the examples below If the vertical height selected is 16 or less the Font Table Register graphics index 42h may be used to select alternate fonts only one font set is available if the number of row lines e
607. tware The Temporary Low Speed timer is not affected by this bit field in the Wake Up Pause High Speed Clock Timers Register at CSC index 45h 5 3 to set the timer value for delaying starting up the High Speed CPU clock when going to High Speed mode from Suspend Power Management AMD Upon wake up the microcontroller goes into High Speed mode at a reduced fre quency 8 29 MHz and delays running the clock up to the maximum programmed speed based on CSC index 451 5 3 If an SMI NMI is serviced for the wake up the CPU speed stepping delay timer contin ues to count down during the interrupt service If the timer times out during the inter rupt service routine the CPU clock speeds up during the routine This feature is useful for lowering the sudden current draw on the power supply when returning from Sus pend Software can determine if full operating speed has been reached by reading CSC index 40h 3 This feature should not be disabled if the HS COUNTING bit CSC index 401 3 is set It should not be disabled when in use A register field CSC index 45h 2 0 to set the timer value for delaying bringing the system out of Suspend allowing time for the power planes to stabilize if any have been turned off A register bit CSC index 40h 5 to disable the LCD in Standby mode A register bit CSC index 41h 6 to immediately time out the active timer allowing software to cause an immediate
608. umns lanSC400 Microcontroller The lanSC400 microcontroller includes the following additional features designed specifically for mobile computing applications A block diagram of the lanSC400 microcontroller is shown in Figure 1 1 Figure 4 1 shows how signals are multiplexed on the ElanSC400 microcontroller Dual PC Card PCMCIA Version 2 1 controller supports 8 16 bit data bus Provides end user after market system expansion Compliant with Exchangeable Card Architecture ExCA also called QuickSwap 82365 register set compatible Leverages off the shelf card and socket services Supports DMA transfers between PC cards and system DRAM LCD graphics controller Supports both color and monochrome SuperTwisted Nematic STN LCDs Internal unified memory architecture UMA eliminates separate video memory ElanSC410 Microcontroller Targeted specifically at embedded systems the ElanSC410 microcontroller includes all the features of the ElanSC400 microcontroller without the PC Card controller and the internal graphics controller A complete list of pin changes for the ElanSC410 microcontroller is included in Section 4 3 A block diagram of the ElanSC410 microcontroller is shown in Figure 1 2 Figure 4 2 shows how signals are multiplexed on the ElanSC410 microcontroller Architectural Overview Figure 1 1 Addr Unit Am486 CPU Address Addr Dual DMA Controllers E 8237 Power Management
609. unctions Memory Only Mode Memory and I O Mode Alternate Name Function Name Function Name Function Ready indication Interrupt request Write protect Dynamic data bus sizing DMA request Battery voltage detect 1 Status change indication Battery voltage detect 2 Speaker driver DMA request 19 5 OPERATION The lanSC400 microcontroller s PC Card controller provides signals and timings to support memory I O and DMA cycles to the two supported socket interfaces A and B The PC Card controller design is optimized for a low cost non buffered PC Card socket implementation The PCMCIA Standard Release 2 1 has specifically designed the PC Card socket interface s pin lengths to support hot PC Card insertion and removal in a non buffered implementation As a card is inserted first ground is applied to the card then power then bus signals The PC Card is thus able to three state its bus interface signals by the time they come in contact with the system bus Each socket shares the same address and data bus but each socket has dedicated chip selects for the low and high byte of the data bus as required by the PCMCIA Standard Release 2 1 Both sockets share a single WAIT signal Each socket supports a reset signal that is software controllable via a PC Card controller indexed register bit Memory and I O accesses to PC Cards are done via memory or I O windows that software must enable before any access is poss
610. ur are 8 bit channels and three are 16 bit channels Channel 4 is used for the cascade function Any two of the seven channels can be mapped simultaneously to external DMA request acknowledge lines The controller on the ElanSC400 and ElanSC410 microcontrollers is software compatible with the PC AT cascaded 8237 controller pair Its features include Single block and demand transfer modes Enable disable channel controller Address increment or decrement Software priority 64 Mbyte system address space for increased performance Dynamic clock enable design reduces clocked elements during DMA inactivity Programmable clock frequency for performance Dual Interrupt Controllers Chapter 11 Dual cascaded 8259 compatible programmable interrupt controllers support 15 user interrupt levels Eight external interrupt requests can be mapped to any of the 15 internal IRQ inputs The interrupt controller block includes these features Software compatibility with PC AT interrupt controllers 15 level priority controller Programmable interrupt modes Individual interrupt request mask capability Accepts requests from peripherals Resolves priority on pending interrupts and interrupts in service Issues interrupt request to processor Provides interrupt vectors for interrupt service routines Tied into the PMU for power management The interrupt controller block is functionally compatible with the standard cascaded 8259A controller p
611. us their meaning in terms of how much time is spent in each phase is dependent on the clock speed used for the command cycle timer The clock speed is determined by three factors The value of both the MODE and CLK SEL bits in the PC Card mode and DMA Control Register and the PMU state The MODE bit in the PC Card Mode and DMA Control Register selects between Standard and Enhanced mode for the PC Card controller block In Standard mode only the PC AT bus 8 MHz clock can be used for cycle control Thus the granularity for cycle phase timing is 125 ns In Enhanced mode the CLK SEL bit in the PC Card Mode and DMA Control Register selects between the PC AT bus nominal 8 MHz clock and the VL bus nominal 33 MHz clock Thus when the VL bus clock is selected the granularity for cycle phase timing is 30 ns The last factor in clock speed used for the command cycle timer is the PMU state The PMU has control of the PC AT bus and VL bus clocks for power savings reasons and can enter states that stretch out clock cycles This has the effect of also stretching out PC Card accesses PC Card Controller 19 13 Table 19 12 19 14 The actual timings of each phase of all non DMA memory I O cycles are based on the following Clock speed as described above Value programmed into the command setup and recovery timing control set selected by a particular memory or I O window Operating mode Standard or Enhanced
612. us 22h 23h Wake up source status Ring Indicate page 3 66 Register D Index 59h Interrupt Request Card Detect and Status Change for PC Card pins GPIO as a Wake Up or Activity 22h 23h Wake up or activity source status page 3 67 Source Status Register A Index 5Ah GPIO CS0O GPIO CS7 GPIO as a Wake Up or Activity 22h 23h Wake up or activity source status page 3 68 Source Status Register B Index 5Bh GPIO CS8 GPIO CS14 PMU Activity Control and Status GP CS Activity Enable Register 22h 23h Activity enable GP CSA GP CSD page 3 69 Index 60h GP CS Activity Status Register 22h 23h Activity status GP CSA GP CSD page 3 70 Index 60h Activity Source Enable Register A 22h 23h Activity source enable CPU access to UART page 3 71 Index 62h internal graphics I O and memory ROMCS2 ROMCSO and any VL bus cycle Activity Source Enable Register B 22h 23h Activity source enable CPU access to DRAM page 3 72 Index 63h matrix key pressed timer tick interrupt keyboard timer time out and keyboard registers Activity Source Enable 22h 23h Activity source enable CPU access to external page 3 73 Register C Index 64h VGA controller and memory floppy controller registers and IDE hard drive registers DMA request ACIN signal UART RIN pin and UART SIN pin 5 4 Power Management AMD Table 5 1 PMU Controller Register Summary continued Description in Register Set Manual Register Address PMU Controller Function Keyword
613. ut Programmable The keyboard timer interrupt CPU access to internal keyboard ports 60h and 64h Programmable Falling edge of internal keyboard chip select GPIO CS14 GPIO CS0 Primary Falling edge of the signal GP CSA GP CSD and memory signals Programmable Falling edge of the signal qualified with the correct command CPU access to PC Card Socket A and B memory Programmable Falling edge of address decode qualified with command CPU access to PC Card Socket A and B I O Programmable Falling edge of address decode qualified with command PC Card Ring Indicate signal Programmable Falling edge of the PC Card Ring Indicate signal PC Card INTR signal Programmable Falling edge of the PC Card INTR signal CPU access to graphics controller I O Programmable Falling edge of I O chip selects qualified with command CPU access to DRAM within graphics controller memory range Programmable When the VID DRAM bit in graphics index 4Fh is asserted rising edge and the CPU accesses DRAM within graphics memory space CPU access to external VGA video controller I O Programmable Falling edge of address decode qualified with command CPU access to external VGA video controller memory Programmable Falling edge of address decode qualified with command CPU access to floppy controller Programmable Falling edge of address decode qualified with co
614. ve if the PDRQ is enabled and mapped to a DMA channel in the DMA Controller and the Pin Mux Register A CSC index 38h 0 selects the DMA function of the pin External IRQ Any of the three external IRQ lines PIRQ2 PIRQO rising edge causes wake up Only active if the PIRQ is enabled and mapped to an IRQ in the interrupt controller and the Pin Mux Register A CSC index 38h 1 2 selects the IRQ function of the pin RTC alarm IRQ8 rising edge triggered UART ring indicate signal The internal UART Ring Indicate RIN falling edge triggered UART receive signal Falling edge of the internal UART receive SIN signal triggered Matrix keyboard key press Internal keyboard controller key pressed interrupt falling edge causes trigger GPIO CS14 GPIO_CS0 signals Triggered by the falling edge on the signal PC Card detect signals Either PC Card Detect signal rising or falling edge can cause a wake up PC Card ring indicate signals When the PC Card controller on the lanSC400 microcontroller is programmed PC Card index 03h or 43h for a ring indicate signal a falling edge can cause a wake up The PC Card controller uses the BVD1 x pins for ring indicate signals PC Card IRQ signals Either PC Card Interrupt Request signal rising edge can cause a wake up Only active if the IRQ is enabled in the interrupt controller PC Card status change IRQ signals 5 22 Either PC Card Status C
615. vide access to the R32BFOE signal Once ROMCSO is configured as 32 bit all accesses to 32 bit ROM devices on ROMCS2 ROMCSO will result in the assertion of the R32BFOE signal Mixed ROM sizes can be supported Once any ROM is buffered High or Low all ROMs connected to that word must be buffered System Interfaces 4 23 4 5 2 Figure 4 6 4 24 Address Buses Address generation on the lanSC400 and lanSC410 microcontrollers is shown in Figure 4 6 There are two address buses on the ElanSC400 and ElanSC410 microcontrollers System Address Bus The SA25 SAO system address bus outputs the physical memory or I O port latched addresses These addresses are used by all external peripheral devices other than main system DRAM including ISA services the ROM Flash interface and on the lanSC400 microcontroller the PC Card controller In addition this is the local address bus in VL bus mode Memory Address Bus DRAM row and column addresses are multiplexed onto the memory address bus MA12 MAO Valid row addresses are driven onto this bus by the falling edge of RAS Valid column addresses are driven onto this bus by the falling edge of CAS The SA bus is shared between the ISA bus the VL bus ROM Flash interface and on the ElanSC400 microcontroller the PC Card controller The lanSC400 and ElanSC410 microcontrollers provide programmable drive strengths in the I O buffers to accommodate loading for variou
616. when done NMls only save a limited state and there is less setup involved in using it so it is simpler to implement The power management unit keyboard scan timer 8042 emulation logic and on the ElanSC400 microcontroller the PC Card controller are the only possible sources for the generation of an NMI to the internal CPU There is also a master enable function provided which can inhibit any NMIs from reaching the CPU regardless of the state of the individual source enables NMI can be enabled by writing a 0 to the most significant bit at I O address 0070h Port 0070h is a write only register and bits 0 6 function as the RTC index address port All the interrupts discussed here can be programmed to cause SMls or except the trapping which uses SMls to service Interrupt flag registers are provided in the CSC indexed registers to determine the source of the SMI NMI If an SMI NMI occurs while the system is in Suspend mode the interrupt will not wake up the system Only wake ups can do that An exception to this is the Suspend Mode timer time out When this is enabled as an SMI NMI the system will go to Temporary Low Speed mode to service the SMI NMI Note This is the only SMI NMI source that can be serviced while in Suspend When an SMI NMI is triggered in a Standby mode the PMU will go to Temporary Low Speed mode to service it When an SMI NMI is triggered by a timer time out in High Speed Low Speed or Temporary
617. x signals are exclusive ORed together and sent to the PC AT port to be merged with the other sources of the lanSC400 microcontroller s SPKR signal Using the WAIT AB CD A and CD B Pins To achieve the maximum benefit from the pins available on the lanSC400 microcontroller some of the PC Card signals specified in the PCMCIA Standard Release 2 1 must be gated together before driving the ElanSC400 microcontroller pin This merging function is described in the following sections WAIT AB Signal Merging The ElanSC400 microcontroller has only one pin WAIT AB to support the PC Card WAIT signal from Socket A and Socket B To support WAIT from both sockets the WAIT signal from each socket should be logical ORed together after being masked off by their respective Card Enable pins as shown in Figure 19 2 In other words WAIT from Socket A should be logical ANDed with MCEL A and MCEH before being ORed with the same masking function on Socket B s WAIT Figure 19 2 Merging WAIT signals from Sockets A and B 19 5 10 2 WAIT Socket WAIT AB WATT Socket B MCEL B MCEH B CD A and CD B Signal Merging The lanSC400 microcontroller has only one dedicated card detect pin to support the PC Card Card Detect 1 and CD2 Card Detect 2 pins from Socket A The CD pin is the dedicated card detect input for Socket A The Card Detect function that this signal is
618. xceeds 16 The total number of fonts available for a given number of row lines may be calculated by the formula fonts INT 32 row lines where fonts is the number of available fonts row lines is the number of row lines used in the font and INT truncates the fractional part of the division result The address of the word corresponding to a given character and row line is given by the equation fontpixel address font table base address 512 row line fontoffset 2 character Table 20 8 shows the bit mapping used for font addresses Font Address Mapping oen 0 2 4 7 RA FontOFF bit 0 RA 4 FontOFF bit 1 RA 4 FontOFF bit 2 bit 3 RA 4 FontOFF bit 3 RA FontOFF bit 4 Font table base 00 Notes The Character Address 7 0 is the character byte stored in the frame buffer It is used by the graphics controller as an address to point to the position in memory where that character font resides The Row Address is generated by the graphics controller and used to point to the row scan line of the font to be displayed These bits from the Font Table Register graphics index 42h are used to select the offset within the font memory area to be used during display Graphics Controller 20 21 20 4 5 3 1 8x8 Font Example The bit map for the letter A in an 8x8 font may
619. y it must be enabled via PC Card index 06h and socket power must be applied via PC Card index 02h as a minimum Interface Both sockets have two windows available I O PC Cards of both 8 and 16 bit widths are supported on both sockets Each window has the following features Full 16 bit decode is performed for single byte addressability of the entire 64 Kbyte system address space 64 Kbyte range is accessible 16 bit wide start and stop registers The following PC Card optional signals are supported SPKR A and SPKR B for digital audio STSCHG A and STSCHG B can be mapped to system interrupts STSCHG A and STSCHG B RI can be configured as PMU activity or wake up source Windows PC Card controller windows differ slightly from memory windows in that no address translation is performed This is because PC Card controller I O window is capable of being made to be 64 Kbytes wide which is the same as the maximum range of an x86 CPU like the ElanSC400 microcontroller PC Card Controller 19 5 4 Table 19 3 Table 19 4 Byte Access AMD There two I O windows per socket and they are available regardless of whether the PC Card controller is in Standard or Enhanced mode In order for I O windows to be used however the PC Card controller must be configured to be in Memory and I O mode by setting bit 5 of the Interrupt and General Control Register for the
620. y configured will A certain action is going to occur XMI SMI or NMI Set 29h 1 Write bit 1 of index 29h to 1 Note The applicable indexed register space will either be obvious from the surrounding text or will be stated explicitly For example RTC index Oh 1 would be a reference to bit 1 in real time clock indexed register space Clear 29h 1 Write bit 1 of index 29h to O xxvi Introduction 1 ARCHITECTURAL OVERVIEW 1 1 lanSC400 AND lanSC410 MICROCONTROLLERS The lanSC400 and ElanSC410 microcontrollers combine 32 bit low voltage Am486 CPU with a complete set of PC AT compatible peripherals along with the power management features required for battery operation The lanSC400 and lanSC410 microcontrollers use the industry standard 486 microprocessor instruction set All software written for the x86 architecture family is compatible with the lanSC400 and lanSC410 microcontrollers The lanSC400 and ElanSC410 microcontrollers include the following distinctive characteristics E86 family of x86 embedded processors Offers improved time to market software migration and field proven development tools Highly integrated single chip CPU with a complete set of common peripherals Accelerates time to market with simplified hardware Low power 0 35 micron process technology Single chip delivers smallest system form factor 33 MHz 66 MHz and 100 MHz operating frequencies
621. yboard SMI NMI 22h 23h SMI NMI status PC Card interrupt ring page 3 100 Status Register Index 95h indicate and card detects for Sockets A and B SMI NMI Select Register 22h 23h SMI or NMI select PC Card interrupts page 3 104 Index 98h Access SMI Enable 22h 23h SMI enable access to Sockets A and B page 3 106 Register B Index 9Ah Access SMI Status Register B 22h 23h SMI status I O access to Sockets A and B page 3 108 Index 9Ch Internal I O Device Disable Echo 22h 23h PC Card controller enable MMS Windows page 3 164 Z Bus Configuration Register Index DOh C F setup DMA Resource Channel Map 22h 23h Sockets A and B mapping to an internal DMA page 3 178 Register B Index DCh controller channel Suspend Pin State Register A 22h 23h Suspend state of Socket A and Socket page 3 184 Index E3h interfaces PC Card Extended Features 22h 23h PC Card Memory Window selection and page 3 196 Register Index FOh Socket mapping force card detect event PC Card Mode and DMA Control 22h 23h Operating mode Standard mode Enhanced page 3 198 Register Index 1 mode clock speed and DMA enables for both sockets PC Card Socket Input Pull Up 22h 23h Sockets A and B input pull up resistor enable page 3 200 Control Register Index F2h PC Card Index Registers Identification and Revision 3EOh 3E1h Interface ID revision level page 6 7 Register Index 00h Socket A and 40h Socket 8 Interface Status Register 3EOh SE1h Battery voltage detec
622. ycle A clock of frequency 1 47456 MHz from the clock divider block is used to provide the source for the 15 clock counts Setting bit 2 to 1 in the Parallel Port Configuration Register enables this time out function Reading bit 0 in the Parallel Port Status Register shows whether an EPP time out has occurred when bit 0 is a 1 a time out has occurred Consecutive reads of the Parallel Port Status Register always return a 0 bit O of this register is reset after each read Parallel Port 14 9 14 6 INITIALIZATION The parallel port is disabled at power on reset The parallel port must be configured by software before the parallel port is enabled After it is enabled the parallel port defaults to PC AT Compatible mode 14 7 POWER MANAGEMENT Operation of the parallel port is affected by the power management functions shown in Table 14 4 Table 14 4 Power Management in the Parallel Port Parallel Port Event Parallel port access Description Triggered by the falling edge of an address decode qualified with the command VO read write Power Management Effect sm wur Programmable Parallel port access 14 10 Accesses to LPT1 378 37Fh or LPT2 278 27Fh can cause an SMI through an trap Parallel Port 5 5 5 Lun 1 5 SERIAL PORT UART AMD 15 1 OVERVIEW The lanSC400 and ElanSC410 microcontrollers include a single industry standard 16550A UART The UART

ElanSC400 and ElanSC410 Microcontrollers User`s Manual

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