Final Project Report Stereo Audio Amplifier
Contents
1. BU6GL SZ9 W6LBS S r3 10s1n7 aqoid 30 5 Testing Procedure To test performance an audio source cable connection wall outlet 120 Vrms 60 Hz and two speakers with wire are required The audio source is connected to the input the speakers to the output and the power supply is plugged into the wall Connecting a signal generator to the input and an oscilloscope to the output allows for comparison to determine the gain In place of a speaker an 8 resistor may be attached to the output Distortion can also be seen on the oscilloscope 31 6 Users Manual Operation e Attach input and speaker output e Plug in amplifier e Begin playing audio and adjust volume control as desired Maintenance e f circuit malfunctions use voltmeter to check forward bias of BJTs Replacement of BJT s may be required e f distortion begins or a burning smell develops disconnect power supply Allow circuit to cool Service may be required Safety Precautions e Do not touch open circuitry when power is enabled e Donotrun the circuit at full volume for prolonged periods of time without adequate ventilation or cooling e Do not swallow or lick the circuit e The circuit is not for children under 12 years of age as it contains small parts which may be harmful if swallowed 32 Electrical Parts List Table 8 Electrical Parts List Number Name Part Number Description 2 NP2. R100 1 8k The volume control was tested and the results are shown in table 2 Table 2 Volume Control Results 500mV peak in Binary Base 10 Output peak Gain 000 0 35 0 07 001 1 50 0 1 010 2 200 0 4 011 3 216 0 432 100 4 290 0 58 101 5 300 0 6 110 6 440 0 88 111 7 500 1 The results show that the output behaved and added according to the formula Control Resistors R H Dipswitch 12VDC Figure 3 Volume Control 12 VDC One problem that occurred was the introduction of a hum upon the addition of the volume control It was later determined that this may have come from the operation amplifier s existence before the amplification process The amplifier uses the positive and negative power supply lines to do its amplification and any small variances are transferred through the op amp into the signal that it outputs In this way the small supply ripple is then magnified along with the reset of the signal in the amplification stages It is possible to control the gain at the output stage of the circuit by placing the operational amplifier at the output stage of the circuit This way the small supply distortion is not magnified by the rest of the circuit and there is the added bonus of the op amp s high input impedance and low output impedance However this is not very power efficient because tpower is wasted by the circuit in am
3. input from any type of audio plug Output is adaptable to normal speaker wire 2 Theory of Operation The circuit is constructed of five distinct components the power supply the volume control a Common Emitter Stage or CEC which functions to amplify the voltage signal a Class AB Power Amplifier Stage or Power Amp which increases the current output and an LED output stage Each channel has its own volume control CEC Power Amp and display circuitry See figure 1 for a block diagram Power Figure 1 Circuit Diagram Supply Display 2 Volume Control 2 Speaker 2 Audio Source It was decided to control the volume by altering signal at the input stage This was done with the summing operational amplifier configuration which allows for precise gain control with predetermined resistors The signal then passes to the CEC stage which has a high input impedance The CEC circuit amplifies the voltage signal and it has a large adjustable output impedance so it does not deliver current to the 8 load of the speaker The class AB power amplifier has a medium input impedance and a very low output impedance which allows it to drive the 8 speaker with little loss of gain The output signal is relayed to a series of comparators which compare the signal amplitude to the predetermined voltages indicated in the specifications When the output reaches the predetermined value the comparator is activated and outputs a voltage w
4. Low End 40kOhm 2V 4kOhm 1V 2kOhm 0 5 V 1kOhm 0 25V 1kOhm OV The operational amplifiers in each of the chips were set up with these voltages as the reference vales The output from the power amplifier was fed into the input nodes of the op amps Capacitors were used to remove DC bias values Whenever the level increased above the reference value the comparator would output a 12 Volt value This caused the LED to become forward biased and to light up A 1 kOhm resistor is placed in series with the LED to prevent over current in the LED While this configuration does not give LED output on negative output swings this in inconseguential since the freguencies are so high 3 Circuit Diagrams Layouts and Wiring See figures 7 10 for the entire circuit Jayeeds na p 1 2 0411 LEdlL LFBNdN 119119 EUUEYJ GurAjiidwy z Iouo euinjoA 19 Chk no y puno15 no e YA T pce o OS noozz P Ku T Fa noOcc ea COOFNLCI Y TOA ZOOFNLG AjddnS 19mog 8 pa Ly OOFNLCI WA LQ Y ZCOOVNLOG eo Gaal CA 20 INO JO1JUOD euunjoA OL 3N IJ ye OLON M8 8Z LOON ME VI O00 104340 euun o A Me L 0043 T 21 Physical Layout Figure 11 Physical Layout Wall Outlet Big ol Stereo Speakers Left 8 Right Channels LED Indicator Digital Volume Control Translated for Easier Operation Output Adapted for Speaker Wire 22 4
5. N BJT 2N3904 Silicon Bipolar Junction Transistor 2 NPN Pwr BJT TIP 31 2 PNP Pwr BJT TIP 32 4 Diode 1N914 High Conductance Diode 4 Breadboard Standard Electrical Breadboard 2 2200uF Cap Electrolytic Capacitors 2 Comparator Radio Quad Comparator Chips Shack 339 2 Heat Sink 1 LED Display Radio Shack 10 Element LED Bar graph Display 1 Bridge Rectifier Radio Shack Full Wave Bridge Rectifier 2 LM741C Operational Amplifier 1 Transformer 18V CT 33 8 Conclusions The circuit was an overall success but things did not turn out as originally planned The initial intention was to build the preamplifier stage using a CSC Mosfet design but satisfactory performance could not be achieved Additionally the experimentation with power amplifier design resulted in the destruction of many NPN and PNP BJT s Design progress was delayed while additional parts were on order There is distortion in the circuit output at high levels and this could have been avoided if it had not been for a miscalculation in the gain requirements The circuit was mistakenly built for the highest possible gain while a lower gain would have been sufficient with less distortion The gain at frequencies higher than 500 Hz is 21 3 dB At 300 Hz the gain is 20 6 dB This makes the maximum difference over the range 0 7 dB which is within specifications The circuit produces full amplification at frequencies up to 250 kHz The loss of gain at the lower amplitude
6. Power Supply Output 24 13 Amplifying Test Circuit with Bias Point 25 14 CEC Output 26 15 End Output 26 16 LED Driving Op Amp Response 28 17 Volume Control 001 29 18 Volume Control 000 29 19 Volume Control 010 30 20 Volume Control 011 30 21 Volume Control 100 31 List of Tables Table Number Page Table 1 Control Resistance Values 6 Table 2 Volume Control Results 6 Table 3 Design Values for CEC 12 Table 4 Bias Point of CEC 12 Table 5 Design Values for Power Amp 15 Table 6 Bias Point Values of Power Amp 16 Table 7 Voltage Ladder Values 18 Table 8 Electrical Parts List 34 1 Specifications The product is to be suitable for in home use The input can be stereo or mono from any low impedance audio source such as a compact disc or MP3 player The input must not exceed the maximum voltage level of 250mV peak since audio quality can not be guaranteed at such levels The system must drive two 8 Ohm speakers with a minimum gain of 3dB and 20dB This is 0 7V V and 10V V in terms of amplitude Additionally there can be no more than a 1 dB gain difference over the audible range of 300Hz to 10kHz without distortion The volume must be digitally controllable with 3 bits on each channel and there must be 4 stage LED indicators corresponding to 0 25V 5V 1V and 2V output levels for each channel as well The system is run from the normal household wall socket supply of 120 Vrms at 60Hz The design can be adapted to accept
7. Spice Simulation Spice simulation resulted in inexact yet satisfactory behavior Generally capacitors in spice created much more impedance to the AC signal than they did in real tests Because of this all capacitors in spice were set to 100mF for simulation purposes The layouts in the previous section were used for simulation Lack of available parts made it necessary to substitute LM324 op amps in place of the LM741C models that were actually used Furthermore center tapped transformers and dipswitches were not available in pspice Voltage regulators are also not found in pspice and so the output signals are seen without their effects 1 85 gt Q 2 O Q Q gt o im o z o a 1 N o 3 LL 0 55 o U 03 2 o U CH 1 23 i ses T sp pm Ak BDBENZO EU BZZ b TRBULR p BULP O 3B08 Zraz ulod Selg YUM 3119119 1591 GurAjijdwy en614 24 ZD WIATA L 8000 gt ihn s sngat r 0000060806 H I 0006060668 c indino pug GL 81n6I4 indino 939 pl 25 Figures 14 and 15 show the simulated outputs of the amplifying stages The smaller waves are the input and the larger ones are the output Note that the circuit shows clipping on the negative swings but this clipping does not appear in the real circuit In the real circuit there is distortion in the positive swing when amplitudes are high This distortion could be removed with tuning of the CEC for
8. T s which saves power To solve the 0 7V voltage clipping it is desired to bias both of the bases at or 0 7V This is accomplished by connecting diodes between the source and the base and ensuring that enough current runs through them by connecting the branch to the voltage sources Note that once again the input bias voltage is essentially zero because of symmetry Biasing the bases in this manner eliminates clipping because both bases are already on the verge of forward active mode Unfortunately this bias allows for small amounts of current to flow through both branches which reduces the efficiency of the circuit The input resistance is approximately rp which is Beta gm In turn gm is directly proportional to IC the current flowing through the BJT s The input impedance is not as important as the output impedance which has been found to be proportional to the 1 ip in ip and in being the current running through the BJT s Since the two are complementary this values remains fairly constant at the bias point It can be seen that in order to obtain a small Rout a large biasing current is required It was found that the bias current through the BJT s could be increased by lowering the RB values seen in Figure 5 However when a signal is amplified by the circuit the values of ip and in get much larger and this reduces 14 the value of Rout causing runaway current flow It is quite easy to destroy standard BJT s in this manner
9. The George Washington University School Of Engineering And Applied Science Department Of Electrical And Computer Engineering Final Project Report Stereo Audio Amplifier By Ben Ruppel 145 82 87 18 ECE 20 32 ECE 20 32 Engineering Electronics Prepared for Professor Korman GTA Faisal Mohd Yasin May 8 2000 Abstract of Design Project Stereo Amplifier By Ben Ruppel This report covers the design and implementation of a multi stage stereo audio amplifier with its own voltage regulator LED display and digital volume control for each channel The input can come directly from a CD audio player or similar device and typical 8 Ohm speakers are driven Digital volume control is implemented using a dipswitch but this control device could easily be replaced by electronic components The signal output is clean with no distortion up to certain audio levels but some distortion occurs at higher levels The unit is designed with five distinct components The power supply provides positive and negative 12 Volts The digital volume control is implemented using a summing amplifier and there is one for each channel Amplification is done in two stages each of which is centered on Bipolar Junction Transistors The first stage is a Common Emitter Circuit that functions to amplify the voltage of the signal This stage has a large output resistance and can not effectively drive 8 speakers The second stage is a Class A B Power Amplifier that provid
10. To avoid this Power BJTs TIP31 and TIP32 were used These transistors are capable of handling very large currents without being destroyed The large currents still caused heat issues and this was somewhat alleviated by attaching heat sinks to the BJT s Furthermore the the values of the RB values were balanced to 1 k to reduce overheating and power consumption without creating too large an output resistance Another purpose of the RB s is to allow enough current flow to ensure a voltage drop across the diodes while not wasting power by allowing too much The diodes used were D1N914 s These diodes are rated with higher conductance and faster response than the usual D1N4002 diodes Note the presence of small RE s These resistors prevent runaway current flow which can occur as the BJT s heat up and allow increased current to flow Increased current causes an increased voltage drop across the resistors reducing the emitter voltage and reducing the current flow in the first place See Tables 3 and 4 for the design values and bias point of the Power Amp Table 5 Design Values for the Power Amp Part Value Part Value RB1 100kOhm RE 62 8 Ohm RB2 50kOhm C1 not pictured 470 uF RC Rout 7600hm C2 not pictured 470 uF Table 6 Bias Point Values of Power Amp simulated Measurement Value IB npn 2 17 mA IB pnp 1 7 mA IC1 1C2 19 1 mA Measurement V
11. alue VB1 0 73 V VB2 1 18 V VE 0 21 V The LED Display The concept behind the LED display is a simple array of comparators one comparator for each light An integrated bar display having 10 lights was used to provide a cleaner looking circuit and it was decided to make the middle two lights power indicators and for the level indications to extend to the left for the left channel and to the right for the right channel The overall effect was very professional Since an operational amplifier is required for each comparator it was decided to use comparator chips each containing 4 op amps This made the stage more compact and required a smaller number of connecting wires However this compactness also made the wiring very crowded and difficult to 12VDC Figure 6 Single LED Stage navigate Output Reference Level The comparator is the most basic use of the operational amplifier If the non inverting input plus sign is more than a little larger than the inverting input 17 minus sign the voltage VDC in this case 12V is output VDC is output for the reversed case In this design a voltage splitting ladder was first designed to set up the reference voltages required by the specifications The ladder runs from 12 supply line to ground The resistance values and corresponding voltages are found in the following table Table 7 Voltage Ladder Values Resistor Voltage at
12. els using a dipswitch to change any of these resistance values was deemed unacceptable It is important to note that the standard BUT is capable of immense amplification but that this is actually harmful given the voltage swing limits imposed by the power supply In order to reduce the gain and take account for the variability of Beta from BJT to BUT the resistor Re must not be shorted to ground for the small signal The presence of Re in the small signal domain causes the gain formula to contain a Beta value in the numerator and the denominator and so these large numbers balance each other There are techniques to control the Re seen for DC bias and the AC signal independently and these involve the use of capacitors to bypass parts of Re and introduce different Re s to the small signal Further research may be able to utilize this for more optimal bias and gain control The spice circuits and results are shown in the Spice section but the following tables report the values used and the results Table 3 Design Values for CEC Part Value Part Value RB1 100kOhm RE 8 6 Ohm RB2 470kOhm C1 input 470 uF RC Rout 434 30hm C2 output 2 0 82 uF Table 4 Bias Point of CEC simulated Measurement Value Measurement Value IB 0 109 mA VB 0 9 V IC 17 9 mA VC 4 24V IE 18 mA VE 0 15 V The Power Amplifier The power amplifier in i
13. es the Common Emitter stage with a larger load and is itself able to drive the low resistance speaker with an acceptable current gain LED output was achieved using multiple comparators which compare the output to predetermined levels and light the LED s when different levels are reached Finally the chosen design performs almost perfectly to specifications with distortion when simulated in the Microsim PSPICE circuit simulator but under actual construction there is higher amplification Table of Contents Alim odu 2 INNE i Abstract or Design PIOIBOL uoce e pata eee neem i VP IE aa nep ele ele Giza zc 1 2 Theory of Operation na cR 2 The Fower s PNE D E eana Keke EEEE EEA TAREE EEE EA NEA EKETA KEK 3 The Volume Control aa EA GE REA RAGE EE pa BEE EA AEC EE 5 RR cT ce 9 The Power Amplifier TTE 13 The LED DEDO m Tm 17 3 Circuit Diagrams Layouts and MENACE 19 PINE WA RC R CR a S 22 ead JE ils PE 23 5 Testing PIGGEOWE aaa e ciala 31 SANG 2 405 OD 32 L Elgciical A ESEE 33 G EMCI NES in ia OL SEE 34 SH dut ETC O OE A CON 36 AB MTM pP 37 Appendix A Circuit Measurements eeeeeeaaa aaa aaa aaa aaa nennen 37 List of Illustrations Figure Page 1 Circuit Diagram 2 2 Power Supply 4 3 Volume Control 7 4 CEC 9 5 Class AB Power Amplifier 18 6 Single LED Stage 17 7 Amplifying Channel Circuit 19 8 Power Supply 20 9 Single LED Control 21 10 Volume Control 22 11 Physical Layout 23 12
14. h enough frequencies and low enough voltages this never happens Capacitors are also used for coupling the output of the CEC to the input of the Power Amplifier This is done because the bias voltage of the CEC 10 collector is approximately 6V and it is desired for the signal and not this steady voltage level to be sent to the power amplifier Note that the load resistance does greatly affect the gain of the CEC by acting as a resistance to ground in parallel with RC in the small signal realm This reduces the current running though RC by half if Rload RC which in turn reduces the gain This is one reason why the CEC must be designed for a gain much higher than the required gain Roughly the highest gain possible out of the CEC is 24 V V Additionally in order to maintain maximum power transfer to the Power Amplifier it is desired that RC of the CEC equal the input load of the Power Amp This is a design constraint that illustrates the complex interoperation of the circuit as a whole The bias point is controlled differently and in complex ways by each of the resistors in the circuit The values RB1 and RB2 are used to control the bias voltage and current of the base A larger value of RC will increase possible gain but alter the bias point of the collector It was observed that varying the value of RE could control the output gain but that it was also easy to create distortion this way Since the specifications require precise output lev
15. hich lights the appropriate LED All of this is powered by the power supply that reduces and rectifies the 120 Vrms wall socket signal into 12 VDC Each of these stages will now be explained in detail The Power Supply The power supply takes the large AC signal from a household wall socket and reduces and rectifies it to the 12 Volt DC signals required to operate the circuit The first step is to pass the signal through a transformer with a ratio of approximately 6 1 The secondary of the transformer outputs an AC signal with 30V peak waves The signal is then fully rectified into positive and negative only signal sweeps using a standard bridge rectifier configuration See figure 2 The prototype used a pre built bridge rectifier for space considerations and cost effectiveness but assembly out of individual components is an alternative By taking the center tap of the transformer as ground the rectified output sweeps of the bridge rectifier nodes are defined as 15 and 15 Volt peak half 1 Fully rectified meaning that there is a signal output for both the positive and negative input sweeps waves The waves are then smoothed out by placing large 2200 uF capacitors between the positive negative outputs and ground The capacitors charge during the output peaks and discharge when the waves are low This smoothes the signal into almost DC with some ripple Voltage regulators are then used to further smooth the signal and to pro
16. lower gain levels This circuit was designed for maximum gain possible but unforeseen distortion was realized too late in the game Figure 16 shows the response of the LED driving circuit When the input is hither than the reference voltage the comparator outputs negative 12 Volts which turns the led on Figures 17 18 19 and 20 show the output levels of the volume control at different binary digits The smaller wave in each case is the output and these simulations correspond to the measurements taken and reported in Table 2 26 1nozuLnn gt zurn nic I I I I I r 088888888 8 L I I I I i I I I I wewrwweysowydpowowowowowororowysejewwewww j veeverejfveveeeeeeevelvervevevl ugat ZOL U9tLZ L ULZ8 228 ULE 9Z Webi SZZ UBB6 HZ nena nn nn AA WA UA AAA no asuodsay dwy do Buiaug qa 91 000806868 Gt 27 wi 6 S68 UZ888 JTP rr EE 73 ugg tigh ugz s t L3 698 L 80878 6880 L US66t E ug29 69 US66t E 000 1911U03 8uinjoA 8L T za ka 000 1 28 LLO 104 U09 euinjoA OZ 80878 3IP us 85 cH USEASTE LH 8c tr L 6666 0 uLqrQGG E Zd ugL z8 WLHBS E LH OLO 19411409 8uinjoA 61 8889 3IP 29 zuTn n INO HLNJA o suz sg e up p LLL JO4 UOD euinjoA ZZ LA Ne L 001 10 7409 euinjoA 00878 3IPp u6L8S S cI
17. ol happening at the input of the circuit Since whatever goes into the circuit was multiplied by 10 the maximum input gain was 1 and the minimum was 0 07 These gains were achieved precisely by using an operational amplifier in the weighted summer configuration see figure 3 With the weighted summer the gain which is the ratio of the output voltage to the input voltage is controlled by changing and adding resistances between the source and the inverting input node There is also a feedback resistance Rf which is static The equation for the gain is ae EE z RI R2 Rn In this design there was one Rn activated for each bit of the dipswitch The specifications were exceeded by implementing a fourth bit which enabled elimination of the input signal for each channel completely While the maximum and minimum gains were defined the intermediate steppings were left open The constraints were that with only the base resistor connected the gain of the control would be 0 07 and with all of the bits activated the gain would be 1 Since the human ear hears on a logarithmic scale 6db is twice as loud it was determined to calculate the gains of each bit accordingly With 3 bits there are 8 possible states Dividing the difference between 20db and 3db into 8 pieces the required gain for each bit was determined See Table 1 for the resistance values Table 1 Control Resistance Values R000 14 3 k R001 28 8 k R010 3k
18. plifying the signal which is then cut down in the end by the volume control The CEC The CEC Circuit has a large voltage gain and works using the inherent amplification properties of the NPN BJT See Figure 3 The concept is to use the BJT to amplify small variations of the current input into the base node IB is increased by an input Figure 4 CEC zacz d voltage variation and this m es current is amplified by a 100k ent 434 3 factor Beta a large number C3 L wpwp r that can vary from BJT to 470u pes BJT in IC the current 470k RE 8 5 flowing into the Collector volume tontra node The connection to the collector node has a resistance in series so when current flow increases into C there is a voltage drop at C and vice versa This is the essential logic behind the CEC and note that since an increase in the input voltage causes a decrease in the output voltage the output signal is reversed and the gain is a negative number This however does not matter with audio output The exact current amplification in IB which comes from input variation is a function of the resistor RB along with the other parameters of the circuit and the circuit bias Biasing of the CEC is the design work for this stage Itis required that the BJT always stay in forward active mode meaning that the voltage in the collector is always higher than that of the base which in turn must be higher than that at the emitter node For undistor
19. s is most likely due to impedance from the capacitors used as DC blockers The loss at higher frequencies may be due to interferences or the internal capacitances of the BJT s See Appendix 1 for printouts of the resulting frequencies The spice analysis was not as encouraging as the constructed circuit This shows that while spice may be a valuable tool in some respects it is no replacement for direct experimentation The final design was achieved mostly through a series of trial error and tweaking potentiometers Circuit knowledge 34 was used to adjust appropriate values until acceptable results were produced Further improvements on the design are planned 35 9 References Sedra Adel S and Kenneth C Smith Microelectronic Circuits New York Oxford University Press 1998 36 Appendices Appendix A Circuit Measurements Following are results of the circuit at varying frequencies 37
20. ted amplification this relationship must remain true up to the highest and lowest peaks of the output Since there is a single voltage source of 12V maximum amplification can occur with 12V peak to peak providing 6V peaks from a bias point of 6V This is a rough maximum as the base voltage must be at least 07 Volts above the emitter voltage which is at OV minimum but is often at a higher voltage Additionally when the base voltage increases slightly from input the collector voltage will be at its minimum meaning that peaks will create the absolute worst case for maintaining forward active mode There is a single voltage source in this case 12V DC with which to create the bias and the balance is adjusted with values of the resistors RB1 RB2 RC and RE The source and load resistances connected to the CEC do not affect its operation because they are coupled to it with capacitors which act as open circuits to DC values and short circuits to signals with high enough frequency This phenomenon comes about from the equation for impedance of a capacitor Z 1 jwC As can be seen impedance is reduced by a high frequency w and by a high capacitance C In order to create a minimal resistance for the inputs and outputs of the circuit for the entire frequency range it is necessary to use as high a capacitance value as possible Polar capacitors may fail if the incorrect voltage polarity is maintained across them but for the AC values with hig
21. tself produces a gain of approximately 1 without a load The theory of the system utilizes the 0 7V voltage drop which always exists between the base and emitter provided the BJT is in forward active mode Signal input is at the base and when the signal rises by a certain voltage the emitter voltage rises accordingly Proper biasing of the collector and emitter is accomplished by simply grounding the emitter and connecting the collector LED directly to the voltage re RE source If the voltage input i En 470u were directly connected to Speaker 5 TIP32 the base there would be two problems input values lower than 0 7V would not di Figure 5 Class AB Power Amplifier IH cause a rise in the emitter because the BJT is not in forward active mode and negative sweeps of the input signal would not be seen for the same reason An option to allow positive and negative sweeps is to use a resistor and the voltage source so as to bias the base as done for the CEC but this creates a constant flow of current through the circuit which wastes power The answer is to add a pnp BJT connected to a negative voltage source see figure 5 13 With a negative input swing the NPN BJT is off but the PNP BJT is sent into forward bias allowing current flow Because of symmetry note that the output node the emitter of each is essentially at OV with no input Also note that without input there is no current flow through the BJ
22. vide a more reliable output It is important to note that interference and feedback in the power supply was a significant problem once the entire circuit was connected This problem was alleviated by connecting large capacitors from the positive and negative nodes to ground at multiple sites of the circuitry The large capacitors act as shorts to AC signals only and so any distortions propagating in the supply lines are grounded through them Figure 2 Power Supply D1N4002 V7 D2 2200u ci CS 470u D1N4002 D3 The Volume Control There were several alternatives for digitally controlling the volume of the signal One way was to alter the state of the amplifying CEC circuit by using the dipswitch to change resistance values This method introduces no noise but there are several obstacles that make it impractical Most importantly specifications require exact decibel volume control corresponding to 0 707 and 10 V V gains The gain of the CEC is most easily controlled by changing the value of Rc in the circuit However such changes have far reaching implications By changing Rc the bias of the entire circuit is altered Furthermore the output impedance of the circuit depends directly on Rc so these changes also affect the transfer of the signal to the Power Amp All of these interconnected reliances make precise calculation of overall gain levels impractical The circuit was designed with gain contr
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