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USER`S MANUAL

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1. Shift RIP Figure 14 8 Timing Diagram for UART Mode 2 Operation ELECTRONICS 14 9 UART S3F84Q5_UM_REV1 00 UART Mode 3 Function Description In mode 3 11 bits are transmitted through the TxD or received through the RxD Mode 3 is identical to mode 2 but can be configured to variable baud rate Each data frame has four components e Start bit 0 e 8 data bits LSB first e Programmable 9th data bit e Stop bit 1 Mode 3 Transmit Procedure 1 Select the baud rate generated by setting BRDATA 2 Select mode 9 bit UART by setting UARTCON bits 6 and 7 to 11B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 3 Write transmission data to the shift register UDATA FFH to start the transmit operation Mode 3 Receive Procedure 1 Select the baud rate to be generated by setting BRDATA 2 Select mode 3 and set the receive enable bit RE in the UARTCON register to 1 3 The receive operation starts when the signal at the RxD pin goes to low level N Write to Shift Register UARTDATA Shift Start Bit DO D1 D2 D3 D4 D5 D6 D7 Stop Bit Transmit TB8 or Parity bit RB8 or Parity bit Bit Detect Sample Time ERE RIP Figure 14 9 Timing Diagram
2. 6 47 JR JUMp Relative rM 6 48 LD 6 49 LD OAC EE 6 50 LDB Eoad Bit n ndr eit ted a a 6 51 S3F84Q5_UM_REV 1 00 MICROCONTROLLER xxi List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load Memory 6 52 LDC LDE LEoad Memoty etii 6 53 LDCD LDED Load Memory and 6 54 LDCI LDEI Load Memory and 6 55 LDCPD LDEPD Load Memory with 6 55 LDCPD LDEPD Load Memory with 6 56 LDCPI LDEPI Load Memory with 6 57 LDW Load a oT o 6 58 MULT Multiply Unsigned ee aig Ailes Aa dee a 6 59 NEXT DH 6 60 MEE 6 61 OR Eogical 6 62 Pop from Stack n cmi nl or daga 6 63 POPUD Pop User Stack Decrementing sse 6 64 POPUI Pop User Stack Incrementing sse 6 65 PUSH Puslito Stack uie e Te et ue
3. Input high ETT All input pins except ViN Vpp leakage current ILIH2 Xour Input low E All input pins except Viu 20V leakage current liio vin OV leakage current leakage current Pull up resistor Vin 0 V Port 0 3 Vpp 9V 25 50 100 kQ clock clock Sub operating Vpp 2 0 to 5 5 V stop 32 768 kHz crystal oscillator Ipp4 Sub idle main osc stop Vpp 2 0 to 5 5 V 32 768 kHz crystal oscillator Ibps Main stop mode sub Vpp 2 010 5 5 V osc stop TA 25 C NOTE D C electrical values for Supply current Ipp do not include current drawn through internal pull up resisters output port drive current LVR and ADC ELECTRONICS 21 3 ELECTRICAL DATA S3F84Q5_UM_REV1 00 Table 21 3 A C Electrical Characteristics Ta 40 C to 85 2 0 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Interrupt input Port 1 INTO INT1 500 ns high low width tnt Port 3 INT2 INT8 Vpp 5V ate 10 nRESET input Input 10 us low width Vpp 5V 1096 NOTE Theunit tcpu means one CPU clock period Figure 21 1 Input Timing Measurement Points 21 4 ELECTRONICS S3F84Q5_UM_REV1 00 ELECTRICAL DATA CPU Clock 10 MHz 8 MHz Supply Voltage V Figure 21 2 Operating Voltage Range S3F84Q5 Figure 21 3 Schmitt
4. 19 4 19 5 Program Memory Address 4 0 0 19 5 19 6 Sector Configurations in User Program Mode sse 19 7 20 1 Low Voltage Reset Circuit writin neia aa ea entente nnne nennen 20 2 Input Timing Measurement 21 4 21 2 Operating Voltage Range 53 8405 21 5 21 3 Schmitt Trigger Input Characteristic 21 5 21 4 Stop Mode Release Timing When Initiated by a 21 7 21 5 Definition of DEE andllEE iiem IAE red tet dete ede e 21 9 22 1 32 SOP 450A Package Dimensions 22 1 22 2 32 SDIP 400 Package 22 2 22 3 28 SOP 375 Package Dimensions sse 22 3 22 4 30 Pin SDIP Package Dimensions sees 22 4 22 5 32 ELP Package 5 5 22 5 23 1 SMDS or SK 1000 Product Configuration 23 2 23 2 SSF84Q5 Target Board 23 3 23 3 40 Pin Connector Pin Assignment for 8405 2 40 8 23 6 23 4 TB84Q5 Adapter tat e Eie ERE 23 7 xiv S3F84Q5 UM REV 1 00 MICROCONTROLLE
5. TE E 2 6 Register Set pA 2 8 3218 121 2 8 Prime Register Space aiia i ie de c ego 2 9 Working H8glsters z uie iterare ite epiac Ate Peer MA b T Meets 2 10 Using the Register 440000 2 11 PR E 2 13 Common Working Register Area 2 nenas 2 15 4 Bit Working Register 0 0 2 16 8 Bit Working Register Addressing 2 18 System and User Stack ante ree ir retis etate c Lt 2 20 Chapter 3 Addressing Modes OVER VIC We AL 3 1 Register Addressing 29 I rident penne tere c esu 3 2 Indirect Register Addressing Mode 2 40 224 0 1 10 nennen enne nennen nns 3 3 Indexed Addressing MOde X tte tcc te en UR ERR RR LE DEREN 3 7 Direct Address Mode DA i imet ite Elite ad EAR ERR RE EE GERADE 3 10 Indirect Address Mode tet t e ld ente tide se etg c AE 3 12 Relative Address Mode RA 3 13 Immediate Mode M Et 3 14 53 8405 UM REV 1 00 MICROCONTROLL
6. OAT Ed EE Tr cr Power Down Modes Stop Mode Idle MOCO C rr DIM Hardware Reset Values Chapter 9 Ports c quts Port Data Registers Port 0 Chapter 10 Basic Timer tet eti a Dive edite eds Aa cela Basic Time BT s iiec eee bere s Basic Timer Control Register BTCON Basic Timer Function Description 53 8405 UM REV 1 00 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 Bit Timer A B TIITIGI t do C dulce cire edt CMM NET du 1 1 1 OVGIVIOW ede e dedi e a Dae dg uou Re ect tado de Aa sade an Sa 11 1 Function DescriptiOn ne rrr Aas rne areas 11 2 Timer A Control Register TACON en rese 11 3 IEEE 11 5 Timer 5 11 6 CIE fict IRI EEG EOM ente A its 11 6 12 16 Bit Timer 1 Made hae ed Gate ee ee 12 1 FUNCHOM EE 12 2 Timer 1 Control Register 12 3 Bock Diagrams 12 5
7. 23 5 STOP zustand 23 5 OTP MTPProgrammier Writer coe ce rte per nds 23 9 53 8405 UM REV 1 00 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 SSF84Q5 Block Diagram esses ener nnns 1 3 1 2 SSF84Q5 Pin Assignment 32 DIP 32 5 1 4 1 3 SSF84Q5 Pin Assignment 28 1 4 1 4 SSF84Q5 Pin Assignment 30 2 2 420 00 1 5 1 5 SSF84Q5 Pin Assignment 32 1 6 1 6 Pili Gircult TYPO T xe ri Deren e ePi abor nob ele 1 10 1 7 Pin Circuit Type 2 yi La perdat du dte dic pate a dp eR Pee 1 10 1 8 Pin Circuit Type 2 1 P2 2 P2 4 P2 6 1 10 1 9 Pin Circuit Type 1 1 0 0 0 1 P1 4 1 7 P2 0 2 1 P2 3 P2 5 P2 7 P3 1 3 2 1 10 1 10 Pin Circuit Type 1 2 P1 0 1 1 31 1 11 1 11 Pin Circuit Type 2 2 P3 3 3 6 0 1 11 1 12 Pin Circuit Type 2 3 PO 2 nnn nnns nennen neas 1 12 1 13 Pin Circuit Type 2 4 1 2 4 3 1 12 2 1 Program Memory Address Space sse 2 2 2 2 Smart OPUOM T PE 2 3 2 3 Internal Register File Organization 53 8405 2 5 2 4 Register Page Pointer PP 2 6 2 5 Set 1 Set 2
8. Reset value 00H Not Used 7 6 bit xx Not used for 53 8405 5 4 bit P3 6 Input mode INTS falling edge interrupt Input mode with pull up INT8 falling edge interrupt Push pull output Open drain output Input mode INT7 falling edge interrupt Input mode with pull up INT7 falling edge interrupt Push pull output Open drain output Input mode INT6 falling edge interrupt Input mode with pull up INT6 falling edge interrupt Push pull output Open drain output Figure 9 7 Port 3 High Byte Control Register ELECTRONICS 9 13 PORTS S3F84Q5_UM_REV1 00 Port 3 Control Register Low Byte P3CONL EDH Set1 Bank0 R W Reset value 00H P3 2 SCK 1 50 P3 0 SI 7 6 bit P3 3 Input mode INT5 falling edge interrupt Input mode with pull up INT5 falling edge interrupt Push pull output Open drain output Input mode SCK input INT4 falling edge interrupt Input mode with pull up SCK input INT4 falling edge interrupt Push pull output Alternative output mode SCK output Input mode INTS falling edge interrupt Input mode with pull up INT3 falling edge interrupt Push pull output Alternative output mode SO Input mode SI INT2 falling edge interrupt Input mode with pull up SI INT2 falling edge interrupt Push pull output Open drain output mode Figure 9 8 Port 3 Low Byte Control Register P3CONL 9 14 ELECTRONICS S3F84Q5_UM_REV1 00 PORTS Port 3 Interrupt En
9. 4 18 P1CONL Port 1 Control Register Low 0 44 00 4 19 Port 1 Interrupt Control 4 20 2 Port 2 Control Register High 4 nnns 4 21 P2CONL Port 2 Control Register Low Byte 04 22 1 1 1100 4 22 P3CONH Port Control Register High 4 04408 4 23 P3CONL Port Control Register Low 4000000000 0 4 24 Port Interrupt Enable 4 25 P3PND Port 3 Interrupt Pending 4 26 P3PND Port Interrupt Pending Register 4 27 PP Register Page PoiDtet iei ee e 4 28 PWMCON PWM Control Register one eot eed eor doeet eee eon 4 29 RPO Register Polnter 0 s c ien et eei ted te e ER ERE n 4 30 RP1 Register Pointer 1 svi esac oua at 4 30 SIOCON Serial I O Module Control Registers sse 4 31 SIOPS SIO Prescaler Register 4 32 SPH Stack Pointer High entente 4 32 STPCON Stop Control Register reri a a E entente nnne 4 33 SYM System Register ee ee ERR ce ue
10. mocou re aw olololololololo Location FCH is not mapped Basic timer counter erent jo o ojojojo o o Location FEH is not mapped Interrupt priority register RW 4 2 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers ee el on _ Hex Lo o v o lofo moon em mw Cimer regse moon tm mw o o o o o e Emeismungss meon tm mw Tw n x a x x mero come Tw e l e e h e EmeBemw Tw n e e imer courier ghey nom em n courier ow bye amp Timer terup ponang regse aw lole loloto Location F2H is not mapped Watch Timer Control Register wrcoN rw Flash memory control register Flash memory user programming enable FMUSR FSH register Flash memory sector address register high FMSECH F6H byte Flash memory sector address register FMSECL F7H low byte Locations F8H FFH are not mapped ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is are appended to the register name for bit addressing S3F84Q5_UM_REV1 00 Name of
11. Set watch timer interrupt to 15 fo 1 Set watch timer interrupt to 0 55 Set watch timer interrupt to 0 255 Set watch timer interrupt to 3 91ms Watch Timer Enable Bit EN Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit No interrupt pending when read EN Clear pending bit when write Interrupt is pending when read ELECTRONICS 4 43 S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 S3F8 series interrupt structure has three basic components levels vectors and sources The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F84Q5 interrupt structure recognizes eight interrupt levels The interrupt lev
12. 7 4 bit address Register pointer provides three provides five low order bits high order bits Together they create an 8 bit register address Figure 2 12 4 Bit Working Register Addressing Selects RPO R6 OPCODE Register instructi 01110 address 0140 14190 76H Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES S3F84Q5_UM_REV1 00 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100 This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 14 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 15 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101 become the five high order bits of the register address The three low order bits of the reg
13. 14 8 Uart Mode 2 Function 14 9 Serial Communication for Multiprocessor Configurations 2 14 11 viii S3F84Q5_UM_REV 1 00 MICROCONTROLLER Table of Contents Continued Chapter 15 Serial I O Interface ER ARE Ree PRIOR RF DAR Programming Procedure ocsi oii ioiii tis iik Serial Control Registers SIOCON SIO Prescaler Register SIOPS Chapter 16 14 Bit PWM Pulse Width Modulation EUH EE Function Description me tone othe ce elt Ott cote E Te PWM Control Register PWMCON Chapter 17 10 Bit Analog To Digital Converter OVOIVIOW ooo E EON RR aden FUNCUOM DOSCIDUOM eem Em Te TS estoy ETE IGI A D Converter Control Register ADCON Internal Reference Voltage Levels Block Diagram p Internal A D Conversion Procedure Chapter 18 Watch Timer M ME Nae etl aye Watch Timer Control Register WTCON Watch Timer Circuit Diagram S3F84Q5_UM_REV 1 00 MICROCONTROLLER Table of Contents Continued Chapter 19 Embedded Flash Memory Interface I ME P ada ida dak aaa casa 19 1
14. Figure 14 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS 14 7 UART S3F84Q5_UM_REV1 00 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD 1 pin or received through the RxD P0 0 pin Each data frame has three components e Start bit 0 e 8 data bits LSB first e Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 8bit BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01 3 Write transmission data to the shift register UDATA FFH The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 8bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P0 0 will cause the UART module to start the serial data receive operation Write to Shift Register UDATA shit LLL 5o 9 y pe X os D4 A 5 X pe X 07 f Rx RxD Start Bit Do D1 D2 D3 D4 D5 D6 D7 Stop Bit JL JL RIP Figure 14 7 Timing Diagram for UART Mode 1 Operation 14 8 ELECTRONICS S3F84Q5_UM_REV1 00 UART UART MODE 2 FUNCTION DES
15. LD BTCON 101000116 LD T1DATAH 00 LD T1DATAL 0FOH LD T1CON 401000110b EI MAIN ROUTINE JR T MAIN INT Timer1 match e e e Interrupt service routine e IRET END Set stack area Disable Watch dog 53 8405 UM REV1 00 fxx 256 interval clear counter Enable interrupt Duration 7 68ms 8 MHz x tal ELECTRONICS S3F84Q5_UM_REV1 00 TIMER 0 TIMER 0 ONE 16 BIT TIMER MODE TIMER 0 The 16 bit timer 0 is used in one 16 bit timer or two 8 bit timers mode If TCCON 7 is set to 1 Timer 0 is used as a 16 bit timer If TCCON 7 is set to 0 timer 0 is used as two 8 bit timers e One 16 bit timer mode Timer 0 e Two 8 bit timers mode Timer C and D OVERVIEW The 16 bit timer 0 is an 16 bit general purpose timer Timer 0 has the interval timer mode by using the appropriate TCCON setting Timer 0 has the following functional components e Clock frequency divider fxx divided by 1024 512 8 or 1 with multiplexer e 16 bit comparator and 16 bit reference data register TCDATA TDDATA e Timer 0 match interrupt generation e Timer 0 control register TCCON Bank1 read write FUNCTION DESCRIPTION Interval Timer Function The timer 0 module can generate an interrupt the timer 0 match interrupt TCINT The TCINT pending condition should be cleared by software when it has been serviced When the global interrupt is enabled even though TCINT is disabled the application s
16. 9 14 9 9 Port Interrupt Control Register 9 15 9 10 Port Interrupt Pending Register 2 2 2 40000 0 9 15 10 1 Basic Timer Control Register BTCON sse nennen 10 2 10 2 Oscillation Stabilization Time ON RESET 10 4 10 3 Oscillation Stabilization Time on STOP Mode 10 5 xii S3F84Q5 UM REV 1 00 MICROCONTROLLER List of Figures Concluded Figure Title Page Number Number 11 1 Timer A Control Register 2 0 100 000000 0 11 3 11 2 Timer Interrupts Pending Register 11 4 11 3 Timer DATA Register 11 4 11 4 Simplified Timer A Functional Block Diagram seen 11 5 11 5 Simplified Timer B Functional Block 11 6 11 6 Timer B Control Register 11 7 11 7 Timer B DATA Registers 11 7 12 1 Timer 1 Control Register T1CON sssssssssssssses eene nnne nnne 12 3 12 2 Timer A B D and 1 Pending Register 12 4 12 3 Timer 1 Functional Block Diagram 02 0000 12 5 13 1 Timer 0 Control Register TCCON sssssssssssssese ener 13 2 13 2 Timer 0 Fun
17. 4 34 Timer 1 Control 4 35 Timer Control 2 4 37 Timer Control Register 4 38 Timer D Control Register ssssssssssseseseeeeee eene einen enne nnns nnne 4 39 TINTPND Interrupt Pending 4 40 UARTCON UART Control Register 4 41 UARTPND UART Pending and Parity 4 42 WTCON Watch Timer Control Register eene 4 43 S3F84Q5 UM REV 1 00 MICROCONTROLLER xix List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add wih rc 6 14 ADD eor MET 6 15 AND Logical AND x tie ees ER Econ Hte deuda de A Aa ee 6 16 BAND BIEAND teneo ea di ete iet Ra eet etas ta tete 6 17 BCP ER 6 18 Bit Gomplement ba te 6 19 BITR Her 6 20 BITR BICROSOL 6 20 BITS Bit SOL AT i I eed 6 21 BOR BIt OP Given 6 22 BTJRF Bit Test Jump Relative on 6 23 BTJRT Bit T
18. 6 66 PUSHUD Push User Stack 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Catry Flagis n ca dec rd dee HL pad Lid aet ar dc Ede dadas 6 69 RET acu eer rence reer cre errr R 6 70 RL Rotate Lefts en Avi ie Ge 6 71 RLC Rotate Left through 6 72 RR Rotate RIOM Em 6 73 RRC Rotate Right through 6 74 SBO Select Bank e ae od deg doo e EU eai 6 75 SB1 Select Em 6 76 SBC Subtract with Carry 2 ad ara eave ca oh eee 6 77 SCF Set Garry Flag erri dices 6 78 SRA Shift Right Arithimetic 6 79 SRP SRPO SRP1 Set Register 6 80 STOP Stop cte e d e ardet Hebe duet Landed s 6 81 SUB v REPRE 6 82 SWAP Swap Nibbles ic itd de e ei e ae od ai 6 83 Test Complement under 440 00 6 84 Test nder 2222240 teet ete ae decente cece delega ea 6 85 WFI Wate Tor IniterFUlpt u oo roce reitera ftrt 6 86 XOR Logical Exclusive eu iet id Aviad eiie eode 6 87 xxii 53 8405 UM REV 1 00 MICROCONTROLLER SF84Q5 UM REV1 00 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsun
19. 3 30 0 30 NOTE Dimensions are in millimeters Figure 22 2 32 SDIP 400 Package Dimensions 22 2 ELECTRONICS S3F84Q5_UM_REV1 00 MECHANICAL DATA 10 45 0 3 7 70 0 2 18 02 17 62 02 t 2 15 01 2 50 0 05 NOTE Dimensions millimeters Figure 22 3 28 SOP 375 Package Dimensions ELECTRONICS 22 3 MECHANICAL DATA S3F84Q5_UM_REV1 00 30 SDIP 400 8 94 0 2 27 88MAX 27 48 0 2 0 56 01 1 30 1 12 1 778 4 gt 4 gt 5 08 MAX 3 30 0 3 0 51 NOTE Dimensions in millimeters Figure 22 4 30 Pin SDIP Package Dimensions 22 4 ELECTRONICS INDEX AREA MECHANICAL DATA 5 00 0 10 5 DETAIL A 0 20 REF NOTE 1 ALL DIMENSION ARE IN mm ANGLES IN DEGREES COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS COPLANARITY SHALL NOT EXCEED 0 08 mm WARPAGE SHALL NOT EXCEED 0 10 PACKAGE LENGTH PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC S S3F84Q5_UM_REV1 00 a 0 75 0 05 0 203 0 008 3 50 REF 69 SIZE 3 7 3 7 3 10 0 10 3 50 REF 7 3 10 0 10 0 25 0 05 32X 10 0 203 0 058 0 008 Terminal Thickness DETAIL A Figure 22 5 32 pin ELP Package Dimensions 22 5 ELECTRONICS S3F84Q5_UM_RE
20. 01H This leaves the value 03H in general register 00H and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3F84Q5_UM_REV1 00 MULT multiply Unsigned MULT Operation Flags Format Examples dst src dst lt dst x src The 8 bit destination operand even register of the register pair is multiplied by the source INSTRUCTION SET operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Set if result is 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles src dst 3 22 22 22 Given Register 20H register 01H register 02H MULT OOH 02H gt Register OOH 01H register 01H MULT gt Register OOH OOH register 01H Opcode Addr Mode Hex dst 84 RR 85 RR 86 RR src 09H register O3H 06H 20H register 02H 09H 0 MULT gt Register 00H 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register 00H of the register pair 00H 01H by the source register 02H operand 09H The 16 bit product 0120H
21. POWER DOWN S3F84Q5_UM_REV1 00 Table 8 2 S3F84Q5 Set1 Registers Values after RESET 5 Hex Port 0 Data Register Po RW Port 1 Data Register P RW Port 2 Data Register RW Port 3 Data Register Pa RW RW PWM extension data register E5H W Port 0 control register POCON RW P1 interrupt control register Punt RW Port 1 control High register PICONH RW 0 0 0 0 0 0 0 0 Port tcontrolLowregister PICONL RW Port 2 control High register P2CONH EAH RW Port2controlLowregister P2CONL RW Port 3 control High register PSCONH RW Port 3 control Low register PSCONL eon RW interrupt control register Pant RW 0 0 0 0 0 0 0 0 P3 interrupt pending register PWM control register PWMCON FOH Location F1H is not mapped Serial I O control register SIO pre scalar register FH FOH F3H SIO data regi
22. 02 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt level enable bit 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR 5 10 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR Set1 is used to set the relative priorities of the interrupt levels the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 21 22 21 C22 IRQO IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5
23. Flags Format Example 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 2 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 71 INSTRUCTION SET S3F84Q5_UM_REV1 00 RET Return RET Operation Flags Format Example PC SP SP e SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and 1234 RET gt 101AH SP 00 The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET RL Rotate Left RL Operation dst lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n
24. If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 DA cc 2 0to F dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W LABEL W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H ELECTRONICS S
25. ae FE m MDATA Counter 8 bit Data Extension Buffer Control Logic Extension Data Buffer PWM le 8 bit PWM Data Register PWM Extension ES Data Register PWMCON 3 clear 8 bit up counter overflow DATA BUS 7 0 Figure 16 4 PWM Module Functional Block Diagram ELECTRONICS 16 6 S3F84Q5_UM_REV1 00 14 BIT PWM PROGRAMMING TIP Programming the PWM Module to Sample Specifications d lt lt Interrupt Vector Address gt gt ORG 0000H VECTOR INT PWM SSF84Q5 PWM interrupt vector i lt lt Initialize System and Peripherals gt gt ORG 0100H RESET DI Disable interrupt LD BTCON 10100011B Watchdog disable SB1 OR P2CONH 411000000B Configure P2 7 PWM output SBO LD PWMCON 01001110B 64 counter interrupt enable LD PWMDATA 80H Set PWM value LD PWMEX 00H Set PWMEX value EI Enable interrupt lt lt Main loop gt gt C o R t MAIN INT PWM PWM interrupt service routine AND PWMCON 11111110B clear pending bit IRET END ELECTRONICS 16 7 S3F84Q5_UM_REV1 00 A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the 8 input channels to equivalent 10 bit digital values The analog input level must lie between the AV REF and values The A D converter has the following
26. RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE and JR Program Memory Next OPCODE Program Memory Address Used PC Value Current Instruction OPCODE Signed fF Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3F84Q5_UM_REV1 00 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTE
27. The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fosc 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits 7 4 The 8 bit basic timer counter BTCNT can be cleared during normal operation by writing a 1 to BTCON 1 clear the frequency dividers for the basic timer input clock you write a 1 to BTCON O Basic Timer Control Register BTCON D3H Set1 R W Divider clear bit for basic timer 0 No effect 1 Clear both dividers Watchdog timer enable bits 1010B Disable watchdog function Other value Enable watchdog function Basic timer counter clear bits 0 No effect 1 Clear basic timer counter Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 fxx 128 11 Invalid selection NOTE When you write a 1 to 0 or BTCON 1 the basic timer divider or basic timer counter is cleared The bit is then cleared automatically to 0 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3F84Q5_UM_REV1 00 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow s
28. ADDRESS SPACES S3F84Q5_UM_REV1 00 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces e One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 H15 e One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 Slice 31 11111XXX RP1 Registers
29. Co 1 input mode with purupi a fo Purmo 1 0 P1 0 ADCO INTO EJES Input mode INTO input oja Input mode with pull up INTO input ENDE Push pull output Alternative function ADCO input ELECTRONICS 4 19 CONTROL REGISTERS S3F84Q5_UM_REV1 00 P1INT Port 1 Interrupt Control Register E7H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W 7 6 Not used for S3F84Q5 5 4 P1 1 INT1 Interrupt Enable Disable Selection Bits ojx Interrupt Disable Interrupt Enable falling edge Interrupt Enable rising edge 3 2 P1 0 INTO Interrupt Enable Disable Selection Bits Interrupt Disable Interrupt Enable falling edge Interrupt Enable rising edge 1 INT1 Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 0 INTO Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 4 20 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER P2CONH Port 2 Control Register High Byte EAH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P2 7 PWM ofo mame Co input mode wit pup SSS Push pull output Alternative function PWM signal output 5 4 P2 6 T1CAP o TO ma Lo wih 3 2 P2 5 T1OUT 9 0 Fo r mumwewhpd
30. Disable counting operating 10 fxx 2 1 Enable counting operating 11 Timer D counter clear bit 0 No effect 1 Clear the timer D counter when write Figure 13 4 Timer D Control Register TDCON 13 6 ELECTRONICS S3F84Q5_UM_REV1 00 TIMER 0 FUNCTION DESCRIPTION Interval Timer Function Timer C and Timer D The Timer C and D module can generate an interrupt the Timer C match interrupt TCINT and the Timer D match interrupt TDINT The Timer match interrupt pending condition 0 and the Timer D match interrupt pending condition TINTPND 4 must be cleared by software in the application s interrupt service by means of writing a 0 to the 0 and TINTPND 4 interrupt pending bit When the global interrupt is enabled even though TCINT and TDINT are disabled the application s service routine can detect a pending condition of TCINT and TDINT by the software and execute the corresponding sub routine When this case is used the TCINT and TDINT pending bit must be cleared by the application sub routine by writing 0 to the corresponding pending bit TCCON 0 and TINTPND 4 In interval timer mode a match signal is generated when the counter value is identical to the values written to the Timer C or Timer D reference data registers TCDATA or TDDATA The match signal generates corresponding match interrupt TCINT TDINT and clears the counter If for example you write the value 20H to TCDATA a
31. FM USR Flash Memory User Programming Enable Register F5H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits 10100101 Enable user programming mode Other values Disable user programming mode ELECTRONICS 4 11 CONTROL REGISTERS S3F84Q5_UM_REV1 00 IMR Interrupt Mask Register DDH Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value X X X X X x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 Register addressing mode only Interrupt Level 7 IRQ7 Enable Bit SIO UART Transmit UART Receive 0 Disable mask 1 Enable unmask Interrupt Level 6 IRQ6 Enable Bit P3 0 P3 6 0 Disable mask 1 Enable unmask Interrupt Level 5 IRQ5 Enable Bit P1 0 P1 1 0 Disable mask 1 Enable unmask Interrupt Level 4 IRQ4 Enable Bit Timer 1 match capture or overflow 0 Disable mask 1 Enable unmask Interrupt Level 3 IRQ3 Enable Bit Watch Timer or PWM overflow 0 Disable mask 1 Enable unmask Interrupt Level 2 IRQ2 Enable Bit Timer C match Timer D match or overflow 0 Disable mask 1 Enable unmask Interrupt Level 1 IRQ1 Enable Bit Timer B match or overflow 0 Disable mask Enable unmask Interrupt Level
32. Figure 10 2 Oscillation Stabilization Time on RESET 10 4 ELECTRONICS S3F84Q5_UM_REV1 00 BASIC TIMER Normal STOP Mode Oscillation Stabilization Time Normal Operating lt 4 Operating Mode Mode STOP Instruction STOP Mode Execution External Interrupt RESET STOP Release Signal Oscillator XOUT 10000B 00000B tWAIT Basic Timer Increment NOTE Duration of the oscillator stabilzation wait time tWAIT it is released by an interrupt is determined by the setting in basic timer control register o e o po Figure 10 3 Oscillation Stabilization Time STOP Mode Release ELECTRONICS 10 5 BASIC S3F84Q5_UM_REV1 00 PROGRAMMING TIP Configuring the Basic Timer This example shows how to configure the basic timer to sample specification RESET ORG 0000H lt lt Smart Option gt gt ORG 003CH DB OFFH DB OFFH DB OFFH DB OFFH lt lt Initialize System and Peripherals gt gt ORG 0100H DI LD CLKCON 00011000B LD SP amp 0FFFFH LD BTCON 02 EI LD BTCON 02H JR T MAIN 003CH must be initialized to OFF 003DH must be initialized to OFF normal reset disable ISP protection 003FH No sub clock nRESET pin enable Disable interrupt Select non divided CPU clock Stack pointer must be set Enable watchdog function Basic timer clock fog 4096 Basic counter BTCNT
33. Flags No flags are affected Format Example Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken 8 no jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0 DJNZ R1 LOOP DJNZ is typically used to control loop of instructions In many cases label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DUNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET EI Enable Interrupts Operation SYM 0 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 9F Example Given SYM 00H EI If the SYM register contains the value that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM O is th
34. INSTRUCTION SET S3F84Q5_UM_REV1 00 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 OR src b dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H andregister 01H BOR R1 01H 1 gt R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 00000111B The s
35. one 16 bit Timer O Figure 13 2 Timer 0 Functional Block Diagram ELECTRONICS 0 S3F84Q5_UM_REV1 00 TWO 8 BIT TIMERS MODE TIMER C and D OVERVIEW The 8 bit Timer C and D are the 8 bit general purpose timers Timer C have the interval timer mode and the Timer D have the interval timer mode and PWM mode by using the appropriate TCCON and TDCON setting respectively Timer C and D have the following functional components e Clock frequency divider with multiplexer fxx divided by 1024 512 8 and 1 for Timer C fxx divided by 8 4 2 or 1 for Timer D e 8 bit counter TDCNT 8 bit comparator and 8 bit reference data register TCDATA TDDATA e Timer C match interrupt generation e Timer control register TCCON DOH read write Timer D have I O pin for match and PWM output P1 6 TDOUT e Timer D overflow interrupt generation e Timer D match interrupt generation e Timer D control register D1H read write Timer C and D Control Register TCCON TDCON You can use the Timer C and D control register TCCON and TDCON to e Enable the Timer C interval timer mode and D operating interval timer mode and PWM mode e Select the Timer C and D input clock frequency e Clear the Timer C and D counter TCCNT and TDCNT e Enable the Timer C and D interrupt e Clear Timer C and D interrupt pending conditions 13 4 ELECTRONICS S3F84Q5_UM_REV1 00 TIMER 0 TCCON
36. 300H ISP area size 512 byte ISP protection enable disable bit 10 500H ISP area size 1024 byte 0 Enable not erasable by LDC 11 900H ISP area size 2048 byte 1 Disable erasable by LDC ROM Address 003FH TTD II P1 2 XTin 1 3 L pom P0 2 nRESET selection bit 0 Nomal I O P0 2 pin enable 1 nRESET Pin enable VR level selection bits LVR enable 10 2 2V or disable bit 11 3 0V Not used 0 Enable 01 4 0V 1 Disable pin function selection bit 0 XTin Xtout pin enable 1 Normal pin enable NOTES 1 The unused bits of 3CH 3DH 3EH 3FH must be logic 1 2 WhenLVR is enabled LVR level must be set to appropriate value 3 You must determine P1 2 P1 3 function on smart option In other words after reset operation you can t change P1 2 P1 3 function For example if you select XTIN P1 2 XTOUT P1 3 function by smart option you can t change on Normal after reset operation 4 After selecting ISP reset vector address in selecting ISP protection size don t select upper than ISP area size Figure 2 2 Smart Option Smart option is the ROM option for start condition of the chip The ROM address used by smart option is from to 003CH and 003DH are not used in S8F84Q5 ELECTRONICS 2 3 ADDRESS SPACES S3F84Q5_UM_REV1 00 REGISTER ARCHITECTURE In the S8F84Q5 implementation the upper 64 byte area of register files is expanded two 64 byte areas
37. Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit EX No interrupt pending Clear pending bit when write Interrupt pending 0 Timer Match Capture Interrupt Pending Em No interrupt pending Clear pending bit when write Interrupt pending 4 40 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER UARTCON UART Control Register F5H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Operating mode and baud rate selection bits 0 Mode 0 SIO mode fxx 16 x BRDATA1 1 o t 8 bit UART fxx 16 x BRDATA1 1 1 Mode 2 9 bit UART fxx 16 Mode 3 9 bit UART fxx 16 BRDATA1 1 5 Multiprocessor communication enable bit for modes 2 and 3 only Disable 1 Enable 4 Serial data receive enable bit Disable Enable 1 3 Location of the 9th data bit to be transmitted UART mode 2 or 3 or 1 2 Location of the 9t data bit that was received in UART mode 2 or 3 0 or 1 Receive interrupt enable bit Disable Receive interrupt 1 Enable Receive interrupt 0 Transmit interrupt enable bit Disable Transmit interrupt 1 Enable Transmit Interrupt NOTES 1 In mode 2 or 3 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received gth data bit is 0 In mode 1 if MCE 1
38. Digital Output Analog Input AVss VEOB V2 VEOT nes Figure 21 5 Definition of DLE and ILE Table 21 9 AC Electrical Characteristics for Internal Flash ROM S3F84Q5 only 5 C to 85 C Parameter Tw wax NEN RR Fo s DuawesTme Ve 20v 5 Fwe me les NOTES 1 The programming time is the time during which one byte 8 bit is programmed 2 The Sector erasing time is the time during which all 128 bytes of one sector block is erased 3 In case of S3F84Q5 the chip erasing is only available Tool Program Mode ELECTRONICS 21 9 S3F84Q5_UM_REV1 00 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F84Q5 is available 32 pin SDIP package Samsung 32 SDIP 400 32 pin SOP package 32 SOP 450A 30 pin package 30 SDIP 400 28 pin SOP package 28 SOP 375 and a 32 pin ELP package 32 ELP 0505 Package dimensions are shown in Figures21 1 21 2 21 3 21 4 and 21 5 12 00 0 30 8 34 0 20 19 90 0 20 2 00 0 20 2 40 MAX 0 10 MAX aoo MAX 0 4 3 0 40 20 10 0 05 MIN NOTE Dimensions are in millimeters Figure 22 1 32 SOP 450A Package Dimensions ELECTRONICS 22 1 MECHANICAL DATA S3F84Q5_UM_REV1 00 32 SDIP 400 9 10 0 20 27 88 MAX 27 48 0 20 5 08 MAX e o H o 0 51
39. IRQ7 FAH UART Receive interrupt S W FCH SIO interrupt S W EAH P3 0 external interrupt IN T2 S W P3 1 external interrupt IN T3 S W P3 2 external interrupt IN T4 S W FOH P3 3 external interrupt IN T5 S W F2H lt P3 4 external interrupt INT6 S W P3 5 external interrupt INT7 S W F6H P3 6 external interrupt IN T8 S W NOTES 1 Within a given interrupt level the low vector address has high priority For example DOH has higher priority than D2H within the level IRQO The priorities within each level are set at the factory External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3F84Q5 Interrupt Structure 5 4 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE Interrupt Vector Addresses All interrupt vector addresses for the SSF84Q5 interrupt structure is stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses The default program reset address in the ROM is 0100H Decimal 16 383 16K byte Program Memory Area 100H lt Default FFH Reset Interrupt Vector Address Address Area Figure 5 3 ROM Vector
40. Timer B Counter Clear Bit 3 No effect 1 Clear the timer B counter After clearing return to zero Ti 3 er B Overflow Interrupt Enable Bit Disable interrupt 1 Enable interrupt Timer B Match Interrupt Enable Bit Disable interrupt Enable interrupt Timer Start Stop Bit Stop Timer B 1 Start Timer T CONTROL REGISTERS S3F84Q5_UM_REV1 00 TCCON Timer Control Register EOH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 Timer 0 operation mode selection bit Two 8 bit timers mode Timer C D One 16 bit timer mode Timer 0 6 Not used for S8F84Q5 Must kept 0 5 4 Timer Input Clock Selection Bits 9 i o ms x 3 Timer Counter Clear Bit 3 No affect 1 Clear the timer C counter when write 2 Timer C Counter Run Enable Bit 3 Disable counter running 1 Enable counter running 1 Timer C Interrupt Enable Bit Disable Interrupt 1 Enable Interrupt 0 Timer Interrupt pending No interrupt pending Clear pending bit when write 1 Interrupt pending 4 38 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER TDCON Timer D Control Register E3H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer D operating Mode Selection Bits fo fo Interval mode
41. User Program Mode 22 tee ce Ed at ee erede Ge ie OAE EAA a 19 2 Flash Memory Control Registers User Program Mode 19 2 ISP TM On Board Programming Sector te was titi pads Sese cg ueste ib lea aurata 19 5 ET 19 7 mires fluo C ES 19 9 ROACING PE 19 10 Hard Lock Protection ciae ce cle ct 19 11 Chapter 20 Low Voltage Reset MQ 20 1 21 Electrical Data ifs etl th slc 21 1 Chapter 22 Mechanical Data e P 22 1 Chapter 23 Development Tools OVeLVIOW 23 1 SHINE E A 23 1 tap ET C D EE ORIS Ta ta Pe a 23 1 SAMA AsSemblet tia me e eter teet toe eiecti E d tie td eue 23 1 2 ebat ied pe oett eb cane oth eddie Mx 23 1 23 2 23 3 IDEE EED
42. When BTCNT 4 is set a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when Stop mode is released 1 During Stop mode an external power on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 Ifan external power on reset occurred the basic timer counter will increase at the rate of fosc 4096 If an external interrupt is used to release Stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set When a BTONT 4 is set normal CPU operation resumes Figure 10 2 and 10 3 shows the oscillation stabilization time on RESET and STOP mode release ELECTRONICS 10 3 BASIC S3F84Q5_UM_REV1 00 Oscillation Stabilization Time Normal Operating mode Reset Release Voltage nRESET Internal Reset Release 4 trst RC gt 1 0 8 VDD 1 Oscillator XOUT Oscillator Stabilization Time 10000B tWAIT 4096x16 fOSC 1r Basic timer increment and CPU operations are IDLE mode NOTE Duration of the oscillator stabilization wait time tWAIT when it is released by a Power on reset is 4096 x 16 fOSC tRST RC R and C are value of external power on reset
43. and register 02H PUSHUD 00H 01H Register OOH 02H register 01H 05H register 02H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 69 INSTRUCTION SET S3F84Q5_UM_REV1 00 PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 83 IR R Given Register register 01H 05H and register 04H 2AH PUSHUI 900H 04H Register OOH 04H register 01H 05H register 04H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET RCF Reset Carry Flag RCF Operation
44. are located in address EOH and E1H Bank1 and are read write addressable using register addressing mode A reset clears TCCON to OOH This sets Timer C to disable interval timer mode selects an input clock frequency of fxx 1024 and disables Timer C interrupt You can clear the Timer C counter at any time during normal operation by writing a 1 to TCCON 3 A reset clears TDCON to OOH This sets Timer D to enable interval timer mode and disable PWM mode selects an input clock frequency of fxx 8 and disables Timer C interrupt You can clear the Timer D counter at any time during normal operation by writing a 1 to TDCON 3 To enable the Timer C interrupt TCINT and Timer D interrupt TDINT you must write TCCON 7 to TCCON 2 TDCON 2 and TCCON 1 TDCON 1 to 1 To generate the exact time interval you should write TCCON 3 TDCON 3 and 0 TINTPND 4 which cleared counter and interrupt pending bit When the global interrupt is enabled to detect an interrupt pending condition when TCINT and TDINT are disabled the application program can poll for the pending bit TCCON O and TINTPND 4 When a 1 is detected a Timer C interrupt TCINT and Timer D interrupt TDINT is pending When the TCINT and TDINT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the Timer C and D interrupt pending bit TCCON 0 and TINTPND 4 Also to enable Timer D overflow interrupt TDOVF
45. called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3C84Q5 the total number of addressable 8 bit registers is 592 Of these 592 registers 15 bytes are for CPU and system control registers 49 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 512 registers are for general purpose use page 0 page 1 You can always address set 1 register locations regardless of which of the two register pages is currently selected Set 1 location however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3F84Q5 Register Type Summary Register Type Number of Bytes System and peripheral registers General purpose registers including the 16 bit common working register area Total Addressable Bytes 82 2 4 ELECTRONICS S3F84Q5_UM_REV1 00 Bank 0 System and Peripheral Control Registers Register Addressing Mode System Registers Register Addressing Mode General Purpose Register Register
46. indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir src dst 3 6 34 R R 35 R IR dst src 3 6 36 R IM Examples Given R1 10H R2 C 1 register 01H 20H register 02H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 register OAH SBC 01H 02H gt Register 01H 1CH register 02H SBC 01H 02H gt Register 01H 15H register 02H register OAH SBC 01H 428AH gt Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 79 INSTRUCTION SET S3F84Q5_UM_REV1 00 SCF set Carry Flag SCF Operation Flags C Format Example lt 1 The carry flag is set to logic one regardless of its previous value Set to 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 lt dst 0 dst lt dst n 1 0 6 An arithmetic shift right of one bit position is performed on the destin
47. lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir src dst 3 6 44 R R 45 R IR dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H register 08H 8AH OR RO R1 gt RO R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01H O00H gt Register 00H 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and H1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst lt
48. supply current NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads Internal RESET Operation Oscillation Stop Mode e Stabilization Time Operating lt Data Retention Mode Mode Execution Of Stop Instrction NOTE twarr is the same as 4096 x 16 x 1 fosc Figure 21 4 Stop Mode Release Timing When Initiated by a RESET Table 21 7 LVR Low Voltage Reset Circuit Characteristics 25 C Low voltage reset ELECTRONICS 21 7 ELECTRICAL DATA S3F84Q5_UM_REV1 00 Table 21 8 A D Converter Electrical Characteristics TA 40 C to 85 2 0 to 5 5 V Vss OV Parameter _ Symbol _Test Conditions Typ Mac Total accuracy Vpp 9 12 V CPU clock 8 MHz 5 12 V AVsg OV Wewswemyew 4E 7 E gt vw e ve Ass __ Yes aureae Thom a oct 1 ma NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc is operating current during A D conversion 21 8 ELECTRONICS S3F84Q5_UM_REV1 00 ELECTRICAL DATA
49. then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET BXOR Bit XOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Se
50. to their default hardware Reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The on chip Low Voltage Reset features static Reset when supply voltage is below a reference value Typ 2 3 3 0 4 0V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference value When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 8 1 RESET and POWER DOWN S3F84Q5_UM_REV1 00 Watchdog nRESET nRESET Internal System RESETB When the Von level is lower than Vivr Smart Option 3FH 6 l NOTES 1 The target of voltage detection level is the one you selected at smart option3FH 2 BGR is Band Gap voltage Reference Figure 8 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you must make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use th
51. 0 IRQO Enable Bit Timer A match or overflow 0 Disable mask 1 Enable unmask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER IPH instruction Pointer High Byte DAH Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value X X X X X X x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address 15 8 The lower byte of the IP address is located the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 4 0 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 0 ELECTRONICS Register addressing mode only Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 13 CONTROL REGISTERS S3F84Q5_UM_REV1 00 IPR Interrupt Priority Register FFH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value X X X X X X x X Re
52. 1 1 3 1 2 1 1 1 2 1 2 2 1 1 2 1 8 ELECTRONICS SF84Q5_UM_REV1 00 PRODUCT OVERVIEW Table 1 3 Descriptions of Pins Used to Read Write the Flash ROM Main Chip namng Programming P3 1 SO Serial data pin Output port when reading and input port when writing Can be assigned as an Input or push pull output port P3 2 SCK SCLK Serial clock pin Input only pin TEST Vpp Power supply pin for flash ROM cell writing indicates that MTP enters writing mode When 12 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode nRESET PO2 nRESET 7 1 Chipinitialization Vpp Vss Vss 1 32 32 pin Power supply pin for logic circuit 1 30 30 pin 1 28 28 pin ELECTRONICS 1 9 PRODUCT OVERVIEW PIN CIRCUITS P Channel Out Output N Channel Disable Figure 1 6 Pin Circuit Type 1 Pull up register 2D 50 kohm typical Pull up Enable e Open drain enable Data Pin Circuit Output Types Disable Schmitt Trigger Figure 1 8 Pin Circuit Type 2 1 P2 2 P2 4 P2 6 P3 0 SF84Q5 UM REV1 00 Open drain enable P Channel Data Out Output N Channel Disable Figure 1 7 Pin Circuit Type 2 VDD Pull up register 50 kohm typical Pull up Enable Data Pin Circuit Output Type 1 Disable Figure 1 9 Pin Circuit Type 1 1 0 0 0 1 1 4 1 7 P2 0 2 1 P2 3 P2 5 P2 7 P3 1 3 2 ELECTRONICS SF84Q5_
53. 1 P2 0 TBOUT TACAP TACK BUZ TAOUT 6 bit P 2 3 7BOUT Input mode Input mode with pull up Push pull output Alternative function TBOUT signal output Input mode TACAP input Input mode with pull up TACAP input Push pull output Open drain output Input mode TACK input Input mode with pull up TACK input Push pull output Alternative function BUZ output Input mode Input mode with pull up Push pull output Alternative function TAOUT signal output Figure 9 6 Port 2 Low Byte Control Register P2CONL ELECTRONICS 9 11 PORTS S3F84Q5_UM_REV1 00 PORT 3 Port 3 is a 7 bit I O Port that you can use two ways e General purpose I O e Alternative function Port is accessed directly by writing or reading the port data register at location E3H Set1 Banko Port 3 Control Interrupt Control Register Port 3 pins are configured individually by bit pair settings in two control registers located PSCONL EDH Set1 and Set1 When you select output mode a push pull or an open drain circuit is configured In input mode many different selections are available e Input mode e Output mode Push pull or Open drain e Alternative function External Interrupt INT2 INTS falling edge e Alternative function SIO module SI SO SCK 9 12 ELECTRONICS S3F84Q5_UM_REV1 00 PORTS Port 3 Control Register High Byte PSCONH Set1
54. 42H 6FH If general register OOH contains the value 42H and register 42H the value 6FH the statement POPUD 02H 200H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register OOH 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 67 INSTRUCTION SET S3F84Q5_UM_REV1 00 PUSH Push To Stack PUSH Operation Flags Format Examples SIC SP e SP 1 QSP src A PUSH instruction decrements the stack pointer value and loads the contents of the source src in
55. 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump 2 200 3 11 3 12 Indirect 3 12 3 13 Relative 3 13 3 14 Immediate 3 14 S3F84Q5_UM_REV 1 00 MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 4 1 Register Description nennen nnns 4 4 5 1 S3C8 S3F8 Series Interrupt 5 2 5 2 SSF84Q5 Interrupt Structure 2 trenes 5 4 5 3 ROM Vector Address Area 22 22 0 0 ns 5 5 5 4 interrupt Function erer kae ee eee tee iere tits 5 7 5 5 System Mode Register SYM 5 9 5 6 Interrupt Mask Register 1 5 10 5 7 Interrupt Request Priority Groups sse 5 11 5 8 Interrupt Priority Register IPR 5 12 5 9 Interrupt Request Register 5 13 6 1 System
56. Addressing Mode ADDRESS SPACES Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes Figure 2 3 Internal Register File Organization S3F84Q5 ELECTRONICS 2 5 ADDRESS SPACES S3F84Q5_UM_REV1 00 REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W Source register page selection bits 0000 Source Page 0 Source Page 1 others Not used for the S8F84Q5 Destination register page selection bits 0000 Destination Page 0 Destination Page 1 others Not used for the S3F84Q5 NOTE Ahardware reset operation writes the A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to address other pages Figure 2 4 Register Page Pointer PP 2 6 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES PROGRAMMING TIP Using the Page Pointer
57. BTJR r2 b RA DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 R2 R1 IR2 R1 R1 IM rO Rb POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM PUSH PUSH BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA 1 1 1 Ir1 r2 RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3F84Q5_UM_REV1 00 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equa
58. Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Ir Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into program memory location 2200H 21FFH 1H 7FH R6 22H R7 00H LDEPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into external data memory location 2200H 21FFH 1H 7FH R6 22H R7 00H ELECTRONICS 6 59 INSTRUCTION SET S3F84Q5_UM_REV1 00 LDW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register 00H 1AH register 01H 02H register 02H and register 03H OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register OOH 03H register 01H OFH register 02H 03H register OFH R2 03H R3 OFH Register 04H 03H register 05H R6 12H R7 34H Register 02H OFH register 03H OEDH LDW RR2 R7 LDW 04H 01H LDW RR6 1234H LDW 02H 0FEDH 0FH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word
59. INTERFACE SERIAL I O INTERFACE OVERVIEW Serial module SIO can interface with various types of external devices that require serial data transfer The components of each SIO function block are 8 bit control register SIOCON Clock selection logic 8 bit data buffer SIODATA 8 bit presale SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input pin SCK SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps 1 2 Configure the I O pins at port 3 SO SCK SI by loading the appropriate value to the Register Load an 8 bit value to the SIOCON control register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 When you write the transmit data to the serial buffer by writing data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 is set to 1 and an SIO interrupt request is generated ELECTRONICS 15 1 SERIAL I O INTERFACE S3F84Q5_UM_REV1 00 SERIAL I O CONTROL REGISTERS SIOCON
60. Module to Sample Chapter 19 Embedded Flash Memory Interface SOCIO EIdS6 ie uer A e deceased eer De Program Reading S3F84Q5 UM REV 1 00 MICROCONTROLLER Standard Stack Operations Using PUSH and Hard Eock Protecuorn eiae etie deerit eds Page Number xvii List of Register Descriptions Register Full Register Name Page Identifier Number FLAGS System Flags Register aaa 4 8 Flash Memory Control Register 4 9 FMSECH Flash Memory Sector Address Register High Byte 4 10 FMSECL Flash Memory Sector Address Register Low 4 10 FMUSR Flash Memory User Programming Enable Register 4 11 IPH Instruction Pointer High Byte sse 4 13 IPL Instruction Pointer Low Byte 4 13 IRQ Interrupt Request Register 40 4 15 OSCCON Oscillator Control Register sssssssssseseseeeeeneenen nennen nnne 4 16 POCON Port 0 Control Register ssssssssssssssssseeeeneenne nennen nennen nnns 4 17 P1CONH Port 1 Control Register High
61. Probe Adapter gt Trace Timer Unit TB84Q5 8 Base Unit Target Board EVA Power Supply Unit Chip Figure 23 1 SMDS or SK 1000 Product Configuration 23 2 ELECTRONICS S3F84Q5_UM_REV1 00 DEVELOPMENT TOOLS TB84Q5 TARGET BOARD The TB84Q5 target board is used for the S8F84Q5 microcontroller It is supported by the SMDS2 or SK 1000 development system In Circuit Emulator Figure 23 2 TB84Q5 Target Board Configuration To User Vcc OOO On TB84Q5 1 RESET 74HC11 a 2 144 S3E84Q0 EVA Chip 2 40 5 6 External Triggers sw2 SW3 SW 1 lela SMDS SMDS2 RUN Mode Figure 23 2 S3F84Q5 Target Board Configuration NOTE The symbol marks the default status of all the jumpers in the board ELECTRONICS 23 3 DEVELOPMENT TOOLS S3F84Q5_UM_REV1 00 Table 23 1 Power Selection Settings for TB84Q5 To User_Vcc Settings Operating Mode Comments SMDS2 SK 1000 supplies TB84Q5 Vpp to the target board Target 2 evaluation chip and the target system To User VDD SMDS2 or SK 1000 supplies External Vpp only to the target board ed evaluation chip The target Vss gt system must have a power supply of its own To User_VDD SMDS2 SK 1000 Table 23 2 DIP Switch for Smart Option Configur
62. R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Slice 2 Slice 1 Figure 2 6 8 Byte Working Register Areas Slices 2 10 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES USING THE REGISTER POINTS Register pointers RPO and mapped to addresses D6H D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 8 and 2 9 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 8 In some cases it may be necessary to define working register areas in different non contiguous areas of the register
63. RO lt RO RO lt RO RO lt RO R1 R24C 4 5 The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H ADC 80H 82H ADC 80H 83H ADC 80H 84H ADC 80H 85H 80H 80H 80H 80H 80H 80H 80H lt 80H 80H 81H 82H 83H 84H 80H 85H 81H 85H Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are address
64. Register 01H register 02H 03H SUB 01H 02H SUB 01 90 SUB 01 65 Register 01H 17H register 02H 03H Register 01H 91H C S and V 1 Register 01H OBCH C and S 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET SWAP SWAP Operation Flags Format Examples Swap Nibbles dst dst 0 3 dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 1 IR Given Register register 02H and register OA4H SWAP 00H gt Register SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if general register contains the value 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the 00 register leaving the value 11100011B ELECTRONICS 6 85 INSTRUCTION SET S3F84Q5_UM_REV1 00 TCM Test Com
65. The control registers for serial interface SIOCON is located at F2H It has the control settings for SIO module e Clock source selection internal or external for shift clock e Interrupt enable e Edge selection for shift operation e Clear 3 bit counter and start shift operation e Shift operation transmit enable e Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first SIO Control Registers SIOCON F2H Set1 R W Reset 00H SIO shift clock select bit SIO Interrupt pending bit 0 Internal clock P S clock 0 No interrupt pending 1 External clock SCK 0 Clear pending condition when write 1 Interrupt is pending Data direction control bit 0 MSB first mode SlIOinterrupt enable bit 1 LSB first mode 0 Disable 510 interrupt 1 Enable SIO interrupt 510 mode selction bit 0 Rececive only mode 1 Transmit receive mode SIO shift operation enable bit 0 Disable shifter and clock counter Shift clock edge selction bit 1 Enable shfter and clock counter 0 Tx falling edges Rx at rising edges 1 rising edges Rx at falling edges 510 counter c
66. Trigger Input Characteristic Diagram ELECTRONICS 21 5 ELECTRICAL DATA Table 21 4 Oscillator Characteristics TA 40 C to 85 S3F84Q5_UM_REV1 00 Oscillator Test Condition Clock Circuit Main crystal or ceramic Vpp 2 0 to 5 5 V External clock Main system Table 21 5 Oscillation Stabilization Time TA 40 C to 85 2 0 V to 5 5 V Unit 20 ms 10 ns l Oscillator Test Condition Min Typ Max Main crystal fosc gt 1 0 MHz Main ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xin input high and low width 50 main system Oscillator twarr When released by a reset 1 216 fosc stabilization wait time twajr When released by an interrupt 2 NOTES 1 foscis the oscillator frequency 2 The duration of the oscillator stabilization wait time tyyA r when it is released by an interrupt is determined by the setting in the basic timer control register BTCON ELECTRONICS S3F84Q5_UM_REV1 00 ELECTRICAL DATA Table 21 6 Data Retention Supply Voltage in Stop Mode TA 40 C to 85 C Vpp 2 0 V to 5 5V Parameter Symbol Conditions Min Typ Max Unit Data retention Stop mode 2 0 5 5 supply voltage Data retention Ipppn Stop mode 2 0V 0 1 5
67. bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OH XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H R W Bank address status flag BA Carry flag C _ Fast interrupt Zero flag 2 status flag FIS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z fl
68. e Schmitt trigger input characteristics e Oscillator characteristics e Oscillation stabilization time e Data retention supply voltage in Stop mode e Stop mode release timing when initiated by a RESET e Power on RESET circuit characteristics e A D converter electrical characteristics ELECTRONICS 21 1 ELECTRICAL DATA Table 21 1 Absolute Maximum Ratings S3F84Q5_UM_REV1 00 25 C Parameter Symbol Conditions Rating Unit Supply voltage Vpp 0 3 to 6 5 V Input voltage Vi All input ports 0 3 to Vpp 0 3 V Output voltage Vo All output ports 0 3 to 0 3 V Output current high lou One I O pin active 25 mA All I O pins active 80 Output current low lot One I O pin active 30 mA Total pin current for ports 1 2 3 100 Total pin current for ports 0 200 Operating temperature 40 to 85 C Storage temperature E 65 to 150 C ELECTRONICS S3F84Q5_UM_REV1 00 ELECTRICAL DATA Table 21 2 D C Electrical Characteristics TA 40 C to 85 Vpp 2 0 to 5 5 V Parameter Operation VDp Fx 1 4 2 LVR off 2 0 5 5 V Voltage 1 4MHz LVR 5 5 1 10 2 Input high 0 1 2 3 Vpp 2 0 to 5 5 V voltage nRESET and Input low Ports 0 1 2 3and Vpp 20 to 5 5 V 02Vpp v voltage nRESET voltage ports 0 3 voltage port 0 3 Symbol Conditions Min Typ Max Unit
69. file In Figure 2 9 RPO points to the upper slice and to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements F PROGRAMMING Setting the Register Pointers SRP 70H RPO 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001 XXX 16 Byte 1 8 Byte Slice y Contiguous Working 00000X XxX 8 Byte Slice Register block RPO Figure 2 7 Contiguous 16 Byte Working Register Block ELECTRONICS 2 11 ADDRESS SPACES 11110 00000 8 Byte Slice S3F84Q5_UM_REV1 00 Register File Contains 32 8 Byte Slices 8 Byte Slice 16 Byte Contiguous working Register block Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 12H 13H 14H and 15 respectively SRPO 80H ADD RO R1 ADC RO R2 ADC RO R3 ADC RO R4 ADC RO R5 RPO lt 80H RO lt RO RO lt RO
70. if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to instead of OOH 2 20 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES i PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SPL 4OFFH SPL FFH Normally the SPL is set to OFFH by the initialization routine PUSH PP Stack address OFEH PUSH RPO Stack address OFDH lt RPO PUSH RP1 Stack address OFCH RP1 PUSH R3 Stack address OFBH lt R3 POP R3 R3 lt Stack address OFBH POP RP1 lt Stack address OFCH POP RPO POP PP RPO lt Stack address OFDH PP lt Stack address OFEH ELECTRONICS 2 21 S3F84Q5_UM_REV1 00 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM8RC ins
71. individual bit or related bits Register ID FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Mode 7 R Read only W Write only R W Read write Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit 4 4 Register location Register address in the internal Register name hexadecimal register file D5H Set 1 7 5 4 3 2 9 X X x x x x 0 0 R W R W R W R W R W R R W Register addressing modg only R W Carry Flag C Operation does not generate a carry or borrow conditidn EN Operation generates carry out or borrow into high ord drbit7 Zero Flag Z EN Operation result is a non zero value a Operation result is zero Sign Flag 5 Operation generates positive number MSB 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings RESETvalue notation Not used x Undetermined value 0 Logic zero 1 Logic one Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER ADCON A D Converter Control Register FBH Set 1 Bank 0 Bit Identifier RESET Value Read Write 7 4 _ 5 4 3 2 4 o 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W A D Input Pin Selection Bits Other value Connected with GND i
72. is below a reference voltage value Typical 3 0 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 20 1 LOW VOLTAGE RESET S3F84Q5_UM_REV1 00 Watchdog nRESET nRESET Internal System nRESET When the Vpb level is lower than Vivr NOTES BGR is Band Gap voltage Reference Figure 20 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 20 2 ELECTRONICS S3F84Q5_UM_REV1 00 ELECTRICAL DATA 2 1 ELECTRICAL DATA OVERVIEW In this section the following S3F84Q5 electrical characteristics are presented in tables and graphs e Absolute maximum ratings e D C electrical characteristics e A C electrical characteristics e Operating Voltage Range
73. mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET Test Under Mask Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir src dst 3 6 74 R R 75 R IR dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02 23H RO R1 gt RO OC7H 02H 2 TM R1 02H register 02H 23H Z 0 00H 01H gt Register 00H 2BH register 01H 02H 7 0 TM 00H 01H Register 2BH register 01H 02H register 02H 23H Z 0 TM 00 54 gt Register 00 2BH 2 1 In the first example if working register RO contains the value 0C7
74. mode To release Idle mode however any type of interrupt that is internal or external can be used 2 Before enter the STOP or IDLE mode the ADC must be disabled Otherwise the STOP or IDLE current will be increased significantly 8 4 ELECTRONICS S3F84Q5_UM_REV1 00 RESET and POWER DOWN HARDWARE RESET VALUES The reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values e 1 shows the reset bit value as logic one or logic zero respectively e An x means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3F84Q5 Set1 Registers Values after RESET poo mmm Delete eae Hex 7 6 58 4 3 2 1 0 Location DOH is not mapped STOP Register swoon om mw o o o o Oscilator om RW Basic Timer Control Register RW System Clock Register RW 9 x RedsrPomero Reo os RW Register Poner Re om aw Location D8H is not mapped merrupt Bequest Register ma R folo x System Mode Register sw oem RW 01 Register PagePointer PP om aw 0 0 0 0 ELECTRONICS 8 5 RESET
75. n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2EH C In the first example if general register OOH contains the value 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 73 INSTRUCTION SET S3F84Q5_UM_REV1 00 RLC Rotate Left Through Carry RLC Operation dst dst 0 lt C lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples C Set if the bit rotated from the most significant bit
76. occurred IRET clears the FIS bit that was set at the beginning of the service routine Flags All flags are restored to their original settings that is the settings before the interrupt occurred Format IRET Bytes Cycles Opcode Hex Normal 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast 1 6 In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H 0H FFH 100H Interrupt Service Routine JP to FFH FFFFH NOTE In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS 6 47 INSTRUCTION SET S3F84Q5_UM_REV1 00 JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional
77. points to Instruction OPERAND start of working register block Program Memory usas Base Address wo Operan dsi src X gt INDEX Instruction Point to One of the 71 Woking Register 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3F84Q5_UM_REV1 00 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to RPO or RP1 gt RPO or RP1 Selected RP points to start of Program Memory ee block OFFSET NEXT 2 Bits 4 bit Workin Register Point to Working i ad OPCODE Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits L wem Value used in 16 Bits Instruction Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File p 5c mE RPO or RPO or Selected block RP points Program Memory to start of working OFFSET register OFFSET NEXT 2 Bits an gt Register Register Address OPCODE
78. position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register OAAH register 01H 02H and register 02H 17H 0 RLC OOH gt Register 00H 54H C 1 gt Register 01H 02H register 02H 2 C 0 In the first example if general register 00H has the value 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register 00H resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET RR Rotate Right RR Operation dst lt dst 0 dst 7 lt dst 0 dst dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if
79. protection mode Hard lock protection The read protection mode is available only in Tool Program mode So in order to make a chip into read protection you need to select a read protection option when you program an initial your code to a chip by using Tool Program mode by using a programming tool The S3F84Q5 has the pumping circuit internally Therefore 12 5V into VPP test pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions programming reading sector erase hard lock protection FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE Flash Memory Control Register FMCON register is available only in user program mode to select the Flash Memory operation mode sector erase byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON F4H Set 1 Bank 1 R W Flash operation start bit 0 Operation stop 1 Operation start Flash memory mode selection bits This bit will be automatically cleared 0101 Programming mode just after the erase and hard lock 1010 Sector erase mode operation has been done 0110 Hard lock mode others Not available Not used for S3F84Q5 Figure 19 1 Flash Memory Control Register FMCON The bit 0 of FMCON register 0 is a start bit for Erase and Hard Lock operation mode Therefore operation of Erase and Hard Lock mode is activated when you set FM
80. read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the SSF84Q5 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3F84Q5 microcontroller Also included in Part II are electrical mechanical OTP and development tools data It has 17 chapters Chapter 7 Clock Circuit Chapter 16 14 bit PWM pulse width modulation C
81. register IMR R W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO0 IRQ7 Interrupt priority register R W _ Controls the relative processing priorities of the interrupt levels The eight levels of S3F84Q5 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W _ This register enables disables fast interrupt processing and dynamic global interrupt processing NOTE All interrupts must be disabled before IMR register is changed to any value Using DI instruction is recommended 5 6 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are e Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM 0 e Interrupt level enable disable settings IMR register e Interrupt level priority settings IPR register e Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary reg
82. registers in its internal register file 64 bytes in the register file are mapped for system and peripheral control functions ELECTRONICS 2 1 ADDRESS SPACES S3F84Q5_UM_REV1 00 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S83F84Q5 have 16Kbytes of internal multi time programmable MTP program memory see Figure 2 1 The first 256 bytes of the ROM 0H OFFH are reserved for interrupt vector addresses Unused locations except 3CH 3DH 3EH 3FH in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations 3CH 3DH 3EH 3FH is used as smart option ROM cell The default program Reset address in the ROM is 0100H Decimal 16383 16 Kbyte Program Memory Area Available ISP Sector Area Interrupt Vector Area Smart option ROM cell Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES Smart Option ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH note ISP reset vector change enable disable bit Not used ISP protection size selection 0 OBP reset vector address 00 256 bytes 1 Normal vector address 0100H 01 2 512 bytes 10 1024 bytes ISP reset vector address selection bit 11 2048 bytes 00 200H ISP area size 256 byte 01
83. result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 A2 r r src 6 r Ir src dst 3 6 A4 R R A5 R IR dst src 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS 6 31 INSTRUCTION SET S3F84Q5_UM_REV1 00 CPIJE Compare Increment and Jump on Equal Operation Flags Format Example dst src RA If dst src 0 PC lt PC RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is the relative address is add
84. set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3F84Q5_UM_REV1 00 Table 6 2 Flag Notation Conventions 7 5 V D H 0 1 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3F84Q5_UM_REV1 00 Notation INSTRUCTION SET Table 6 4 Instruction Notation Conventions Description Actual Operand Range IRR Condition code Working register only Bit b of working register Bit LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only I
85. system Watch Timer Oscillator Oscillator Circuit Circuit Basic Timer 1 8 1 4 OSC inst F Timer Counter requency STOPCON Dividing Watch Timer fxx 128 Circuit LCD Controller 14 42 1 8 1 16 SIO Figure 7 5 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK CIRCUIT S3F84Q5_UM_REV1 00 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register is located at address D4H Set1 It is read write addressable and has the following functions e Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Setl R W 5 I2 T2 T2 Not used Not used Divide by selection bits for CPU clock frequency 00 fxx 16 01 fxx 8 10 fxx 2 11 fxx 1 non divided Figure 7 6 System Clock Control Register CLKCON 7 4 ELECTRONICS S3F84Q5_UM_REV1 00 CLOCK CIRCUIT MAIN SUBSYSTEM OSCILLATOR SELECTION OSCCON When a main oscillator is selected users cannot stop operating of a main oscillator by handling the OSCCON register while the sub oscillator can be stopped If users intend to stop operating of a main oscillator users must use STOP instruction When a sub oscillator is selected users must do the contrary of the above case Oscillator Control
86. the chip erase execution in the tool program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The Program Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 SetFlash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR 00000000B 8 PROGRAMMING Hard Lock Protection SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01100001B Hard Lock mode set amp start NOP Dummy instruction this instruction must be needed LD FMUSR 0 User program mode disable ELECTRONICS 19 11 S3F84Q5_UM_REV1 00 LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW By smart option 3FH 6 in ROM user can select internal RESET LVR or external RESET The S3F84Q5 can be reset in four ways e external power on reset e bythe external reset input pin pulled low e by the digital watchdog timing out by the Low Voltage reset circuit LVR During an external power on reset the voltage Vpp is High level and the RESETB pin is forced Low level The RESETB signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3F84Q5 int
87. the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost Overrun error In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P0 0 and 1 to alternative function RXD P0 0 TXD P0 1 for UART module by setting the POCON register to appropriatly value Load an 8 bit value to the UARTCON control register to properly configure the UART I O module For interrupt generation set the UART interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write transmit data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit UARTPND 1 or UARTPND O is set to 1 and an UART interrupt request is generated cU pon ELECTRONICS 14 1 UART S3F84Q5_UM_REV1 00 UART CONTROL REGISTER UARTCON The control register for
88. the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Reference Voltage Input Analog ADCO ADC7 Input Pin S3F84Q5 NOTE symbol signifies an offset resistor with a value of from 50 to 100Q Figure 17 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 17 5 S3F84Q5_UM_REV1 00 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 1 of the watch timer control register WTCON 1 to 1 And if you want to service watch timer overflow interrupt IRQ3 vector DEH then set the WTCON 6 to 1 The watch timer overflow interrupt pending condition 0 must be cleared by software in the application s interrupt service routine by means of writing a 0 to the WTCON O interrupt pending bit After the watch timer starts and elapses a time the watch timer interrupt pending bit WTCON 0 is automatically set to 1 and interrupt requests commence in 3 91 ms 0 25 0 5 and 1 second intervals by setting Watch timer speed selection bits WTCON 3 2 The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will functi
89. the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given Register register 01H 02H and register 02H 17H RR OOH Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register contains the value 31H 001 10001 the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000 in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 75 INSTRUCTION SET S3F84Q5_UM_REV1 00 RRC Rotate Right Through Carry RRC Operation dst dst 7 lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand and the carry flag rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherw
90. the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes even number for program memory and odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given RO 77H R6 30H and R7 00H LDCPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 LDEPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src Ir rr 4 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes even number for program memory and an odd number for data memory No flags are affected Bytes
91. timer 0 interrupt you must write TCCON 7 TCCON 2 and TCCON 1 to 1 To generate the exact time interval you should write TCCON 3 and 0 which cleared counter and interrupt pending bit In case of the global interrupt is enabled to detect an interrupt pending condition when TCINT is disabled the application program can poll for the pending bit 0 When a 1 is detected a timer 0 interrupt is pending When the TCINT sub routine has been serviced the pending condition must be cleared by software by writing 0 to the timer 0 interrupt pending bit TCCON O Timer C Control Register TCCON Set1 Bank1 Reset 2 00H R W Timer C interrupt pending bit Timer 0 operation mode selection bit 0 No interrupt pending 0 Two 8 bit timers mode Timer C D 0 Clear pending bit when write 1 One 16 bit timer mode Timer 0 1 Interrupt is pending Not used Timer C interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer C clock selection bits 00 fxx 1024 Timer C counter enable bit 01 fxx 512 0 Disable counting operation 10 fxx 8 1 Enable counting operation 11 fxx Timer C counter clear bit 0 No affect 1 Clear the timer C counter when write Figure 13 1 Timer 0 Control Register TCCON 13 2 ELECTRONICS S3F84Q5_UM_REV1 00 TIMER 0 BLOCK DIAGRAM MSB LSB fxx 102 TCCNT TDCNT 512 TCCON 3 fxx TCDATA TDDATA TCCON 1 NOTE When TCCON 7 is 1
92. using the appropriate T1CON setting is e Interval timer mode Toggle output at T1 OUTpin e Capture input mode with a rising or falling edge trigger at the T1CAP pin e PWM mode T1PWM PWM output shares their output port with T1OUT pin Timer 1 has the following functional components e Clock frequency divider fxx divided by 1024 256 64 8 1 or T1CK External clock with multiplexer External clock input pin T1CK e A 16 bit counter 16 bit comparator and two 16 bit reference data register T1DATAH L e O pins for capture input T1CAP or match output T1OUT e Timer 1 overflow interrupt and match capture interrupt generation e Timer 1 control register TT CON ELECTRONICS 12 1 16 1 S3F84Q5_UM_REV1 00 FUNCTION DESCRIPTION Timer 1 Interrupts The timer 1 module can generate two interrupts the timer 1 overflow interrupt T1OVF and the timer 1 match capture interrupt T1INT A timer 1 overflow interrupt pending condition can be cleared by both software and hardware when it has been serviced A timer 1 match capture interrupt pending condition should be cleared by software when it has been serviced Interval Mode match Timer 1 module can generate an interrupt Timer 1 match interrupt T1INT In interval timer mode a match signal is generated and T1OUT is toggled when the counter value is identical to the value written to the T1 reference data register TTDATAH L The match signal generates a
93. write one or both of the register pointers RPO and Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one Flags No flags are affected Format SIC Examples The statement SRP 40H Bytes Cycles Opcode Addr Mode Hex src 4 31 IM sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the nRESET pin must be held to Low level until the required oscillation stabilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction leakage current could be flown because of the fl
94. you must write TCCON 7 to 0 TDCON 2 and TDCON 0 to 1 To generate the exact time interval you should write TDCON 3 and TINTPND 5 witch cleared counter and interrupt pending bit Timer C Control Register TCCON Set1 Bank1 Reset 00H R W Timer C interrupt pending bit Timer 0 operation mode selection bit 0 No interrupt pending 0 Two 8 bit timers mode Timer C D 0 Clear pending bit when write 1 One 16 bit timer mode Timer 0 1 Interrupt is pending Not used Timer C interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer C clock selection bits 00 fxx 1024 Timer counter enable bit 01 fxx 512 0 Disable counting operation 10 fxx 8 1 Enable counting operation 11 fxx Timer counter clear bit 0 No affect 1 Clear the timer C counter when write Figure 13 3 Timer C Control Register TCCON ELECTRONICS 13 5 0 S3F84Q5_UM_REV1 00 Timer B Control Register TDCON E1H Setl Bank1 Reset 2 00H R W Timer D operating mode selection bits Timer D overflow interrupt enable bit 00 Interval mode 0 Disable overflow interrupt 01 6 bit PWM mode OVF interrupt can occur 1 Enable overflow interrupt 10 7 bit PWM mode OVF interrupt can occur 11 8 bit PWM mode OVF interrupt can occur Timer D match interrupt enable bit 0 Disable match interrupt 1 Enable match interrupt Timer D clock selection bits 00 fxx 8 Timer D count enable bit 01 fxx 4 0
95. 0 C3 r Irr 2 opc sro dst 2 10 D3 Irr r coe MI 8 35 ee ES 4 src dst 3 12 F7 XS rr r 5 dst src XL XL 4 14 A7 r XL rr 6 src dst XL XL 4 14 B7 XL rr r 7 DA 4 14 DA 8 opc DA DA 4 14 B7 DA 9 DA 4 14 DA 10 opc DA DA 4 14 B7 DA NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats 3 and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 DA source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS 6 53 INSTRUCTION SET S3F84Q5_UM_REV1 00 6 54 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC RO OGRR2 lt contents of program memory location 0104H RO R2 01H R3 04H LDE RO OGRR2 lt contents of external data memory location 0104H RO 2AH R2 01H 04H LDC nete ogRR2 RO 11H cont
96. 1 AMHz LVR Enable 3 0 V to 5 5 V 1 10MHz Package Type e 28 SOP 30 pin SDIP 32 pin SDIP SOP 32 pin ELP ELECTRONICS SF84Q5_UM_REV1 00 BLOCK DIAGRAM XIN gt XOUT XT OUT nRESET gt OSC nRESET TAOUT 4 8 Bit TACK gt Timer TACAP CounterA T1OUT lt 16 bit T1CK Timer T1CAP Counter 1 8 Bit Timer Counter B 8 Bit timer C D ELECTRONICS 8 Bit Basic Timer PRODUCT OVERVIEW ADCO 7 1144444 I O Port and Interrupt Control SAM8RC CPU 8 16 Kbyte 272 528 Byte ROM RAM Watch Timer BUZ Figure 1 1 S3F84Q5 Block Diagram PRODUCT OVERVIEW PIN ASSIGNMENT Vss XOUT XIN Vpp TEST RxD P0 0 TxD PO 1 nRESET P0 2 INT5 P3 3 INT6 P3 4 AVREF INTO ADCO P1 0 INT1 ADC1 P 1 1 XTIN ADC2 P1 2 XTour ADC3 P 1 3 ADCA P1 4 ADC5 P1 5 Vss XOUT XIN Vpp TEST RxD P0 0 TxD PO 1 nRESET P0 2 AVREF INTO ADCO P1 0 INT1 ADC1 P1 1 XTIN ADC2 P1 2 XTout ADC3 P1 3 ADC4 P1 4 ADC5 P1 5 53 8405 View 32 SOP 32 SDIP O O S3F84Q5 Top View 28 SOP O SF84Q5_UM_REV1 00 VDD P3 2 SCK INTA SCLK P3 1 SO INT3 SDAT P3 0 SI INT2 P2 7 PWM P2 6 T1CAP 2 5 100 P3 6 INT8 P3 5 INT7 2 1 P2 3 TBOUT 2 2 P2 1 TACK BUZ P2 0 TAOUT P1 7 ADC7 P1 6 ADC6 TDOUT 32 SOP VDD 2 5 4 SCLK P3 1 SO INT
97. 1 Interrupt pending 1 Interrupt pending Timer A overflow Timer 1 match interrupt pending flag interrupt pending flag 0 Not pending clear pending bit 0 Not pending clear pending bit 1 Interrupt pending 1 Interrupt pending Timer B match capture Timer D overflow interrupt pending flag 0 Not pending clear pending bit 0 Not pending clear pending bit 1 Interrupt pending 1 Interrupt pending Timer B overflow interrupt pending flag 0 Not pending clear pending bit 1 Interrupt pending Timer D macth capture interrupt pending flag 0 Not pending clear pending bit 1 Interrupt pending Figure 12 2 Timer A B D and TIMER 1 Pending Register TINTPND 12 4 ELECTRONICS S3F84Q5_UM_REV1 00 16 BIT TIMER 1 BLOCK DIAGRAM T1CON 7 5 1 0 fxx 1024 gt fxx 256 gt fxx 64 gt 16 bit Up Counter Read Only 16 bit Comparator TINTPND 6 16 bit Timer Buffer Overflow In PWM mode T1CON 4 3 N High level when data gt counter Low level when data lt counter 16 bit Timer Data Register T1DATAH L TICON 4 3 Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 12 3 TIMER 1 Functional Block Diagram ELECTRONICS 12 5 16 1 PROGRAMMING TIP Using the Timer 1 INITIAL MAIN ORG 0000h VECTOR 0E4h INT_Timer1_match ORG 0100h DI LD SP
98. 1 1100 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H R0 lt lt 0 Bits 4 7 3 bits 0 3 1 DA R1 lt 31 0 leave the value 31 BCD in address 27H QR1 ELECTRONICS 6 35 INSTRUCTION SET DEC Decrement DEC Operation Flags Format Examples dst dst lt 051 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex dst 2 4 00 01 Given R1 and register 03H 10H DEC Ri gt R1 02H DEG gt Register 03H OFH S3F84Q5_UM_REV1 00 Addr Mode dst R IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register one leaving the value OFH ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET DECW DECW Operation Flags Format Examples NOTE Decrement Word dst dst dst 1 The contents of the destina
99. 19 1 ISP Sector Size S3F84Q5_UM_REV1 00 Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 2 Bit 1 Bit 0 1 X X 0 0 0 0 100H 1FFH 256 byte 256 Bytes 0 0 1 100H 2FFH 512 byte 512 Bytes 0 1 0 100H 4FFH 1024 byte 1024 Bytes 0 1 1 100H 8FFH 2048 byte 2048 Bytes NOTE The area of the ISP sector selected by Smart Option bit 2 003EH 0 not be erased and programmed by LDC instruction in user program mode ISP Reset Vector and ISP Sector Size If you use ISP sectors by setting the ISP enable disable bit to 0 and the Reset Vector Selection bit to 0 at the Smart Option you can choose the reset vector address of CPU as shown in Table 19 3 by setting the ISP Reset Vector Address Selection bits Table 19 2 Reset Vector Address Smart Option 003EH ISP Reset Reset Vector Usable Area for ISP ISP Sector Size Vector Address Selection Bit Address After POR Sector Bit 7 Bit 6 Bit 5 1 X X 0100H 0 0 0 0200H 100H 1FFH 256 Bytes 0 0 1 0300H 100H 2FFH 512 Bytes 0 1 0 0500H 100H 4FFH 1024 Bytes 0 1 1 0900H 100H 8FFH 2048 Bytes NOTE The selection of the ISP reset vector address by smart option 7 003EH 5 is not dependent of the selection of ISP sector size by smart option 00 2 003EH 0 ELECTRONICS S3F84Q5_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE SECTO
100. 3 40 Pin Connector Pin Assignment for TB84Q5 23 6 ELECTRONICS S3F84Q5_UM_REV1 00 A 9 5 e U O 5 5 o Q DEVELOPMENT TOOLS Target Board Target System J2 JO Ji 40 Part Name AP64SD C Order Code SM 6532 Figure 23 4 TB84Q5 Adapter Cable ELECTRONICS 23 7 DEVELOPMENT TOOLS S3F84Q5_UM_REV1 00 SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer Series In Circuit Emulator e OPENice i500 e SMART Kit OTP MTP Programmer e SPW 2 e BlueChips Combi e GW PRO2 Development Tools Suppliers Please contact our local sales offices on how to get MDS tools Or contact the 3rd party tool suppliers directly as shown below 8 bit In Circuit Emulator OPENice i500 AlJI System TEL 82 31 223 6611 FAX 82 331 223 6613 E mail openice aijisystem com URL http Awww aijisystem com SMART Kit amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http www cnatech com 23 8 ELECTRONICS S3F84Q5_UM_REV1 00 OTP MTP PROGRAMMER WRITER DEVELOPMENT TOOLS SPW2 Single PROM OTP FLASH MTO Programmer e Download Upload
101. 3 SDAT P3 0 SI INT2 P2 7 PWM P2 6 T1CAP P2 5 T1OUT P2 4 T1CK P2 3 TBOUT P2 2 TACAP P2 1 TACK BUZ P2 0 TAOUT P1 7 ADC7 P1 6 ADC6 TDOUT Figure 1 3 53 8405 Pin Assignment 28 SOP 1 4 ELECTRONICS SF84Q5 UM REV1 00 PIN ASSIGNMENT Vss XOUT XIN Vpp TEST RxD P0 0 TxD PO 1 nRESET P0 2 INT5 P3 3 AVREF INTO ADCO P 1 0 INT1 ADC1 P1 1 XTIN ADC2 P1 2 XTOUT ADC3 P1 3 ADCA P1 4 ADC5 P1 5 S3F84Q5 Top View 30 SDIP O PRODUCT OVERVIEW VDD P3 2 SCK INT4 SCLK P3 1 SO INT3 SDAT P3 0 SI INT2 P2 7 PWM P2 6 T1CAP 2 5 100 P3 5 INT7 P2 4 T1CK P2 3 TBOUT P2 2 TACAP P2 1 TACK BUZ P2 0 TAOUT P1 7 ADC7 P1 6 ADC6 TDOUT Figure 1 4 S3F84Q5 Pin Assignment 30 SDIP ELECTRONICS 1 5 PRODUCT OVERVIEW SF84Q5_UM_REV1 00 P2 7 PWM P2 6 T1CAP P2 5 T1OUT P3 6 INT8 P3 5 INT7 P2 4 T1CK P2 3 TBOUT P2 2 TACAP 19 18 INT2 SI P3 0 SDAT INT3 SO P3 1 SCLK INT4 SCK P3 2 P2 1 TACK BUZ P2 0 TAOUT P1 7 ADC7 53 8405 P1 6 ADC6 TDOUT Top View P1 5 ADC5 32 ELP P1 4 ADC4 P1 3 ADC3 XTour 9 24 N VDD VSS N ce Xout Xin Vpp TEST 99 S O P1 2 ADC2 XTN 1 2 RxD PO 0 T
102. 3F84Q5_UM_REV1 00 INSTRUCTION SET JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL_X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS 6 49 INSTRUCTION SET S3F84Q5_UM_REV1 00 LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src
103. 6 IRQ6 Request Pending Bit P1 0 P1 1 0 Not pending 1 Pending Level 5 IRQ5 Request Pending Bit Timer 1 match capture or overflow 0 Not pending 1 Pending Level 4 IRQ4 Request Pending Bit Watch Timer 0 Not pending 1 Pending Level 3 IRQ3 Request Pending Bit PWM overflow 0 Not pending 1 Pending Level 2 IRQ2 Request Pending Bit Timer C match Timer D match or overflow 0 Not pending 1 Pending Level 1 IRQ1 Request Pending Bit Timer B match or overflow 0 Not pending Level 0 IRQO Request Pending Bit Timer A match or overflow 0 Not pending 1 Pending CONTROL REGISTERS S3F84Q5_UM_REV1 00 OSCCON oscillator Control Register D2H Set 1 Bit Identifier RESET Value Read Write 7 4 7 5 5 4 2 0 0 E 0 R W R W R W Not used for S8F84Q5 Main Oscillator Control Bit Main oscillator RUN 1 Main oscillator STOP Sub Oscillator Control Bit Sub oscillator RUN 1 Sub oscillator STOP Not used for 53 8405 System Clock Selection Bit Select main oscillator for system clock 1 Select sub oscillator for system clock ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER POCON Port 0 Control Register E6H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W 5 4 2 lo Input mode In
104. 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows e PR 5controls the relative priorities of group C interrupts e Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C e PR O controls the relative priority setting of IRQO and IRQ1 interrupts ELECTRONICS 5 11 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 Interrupt Priority Register IPR FFH Setl R W Group priority D7 D4 D1 0 IRQO gt IRQ1 1 IRQ1 gt IRQO Undefined Group B B gt C gt A 0 IRQ2 gt IRQ3 IRQ4 A gt B gt C 1 IRQ3 IRQ4 gt IRQ2 B gt A gt C Subgroup B C gt A gt B 0 IRQ3 gt IRQ4 gt gt 1 IRQ4 IRQ3 Group C 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 1 1 0 0 1 1 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ DCH Set1 to monitor interrupt request status for all levels in the microcontroller s in
105. 9 INSTRUCTION SET S3F84Q5_UM_REV1 00 BITR Bit Reset BITR dst b Operation dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst b 0 2 4 77 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITR R11 o R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B 6 20 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET BITS Bit Set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R13 gt R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21
106. Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 Enable Disable Interrupt Instructions El Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing e interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels e interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source e system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 1 Interrupt Control Register Overview Control Register i RW Function Description Interrupt mask
107. As it produces the re locatable object codes only the user should link object files Object files can be linked with other object files and loaded into memory SASM requires a source file and an auxiliary register file device_name reg with device specific information SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generating an object code in the standard hexadecimal format Assembled program codes include the object code used for ROM data and required In circuit emulators program control data To assemble programs SAMA requires a source file and an auxiliary definition device name def file with device specific information HEX2ROM HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler A ROM code is needed to fabricate a microcontroller which has a mask ROM When generating a ROM code file by 2 the value FF is automatically filled into the unused ROM area up to the maximum ROM size of the target device ELECTRONICS 23 1 DEVELOPMENT TOOLS S3F84Q5_UM_REV1 00 TARGET BOARDS Target boards are available for all the S3C8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB84Q5 is a specific target board for the S3F84Q5 development IBM PC AT or Compatible RS 232C Emulator SMDS2 or SK 1000 Target gt RAM Break Display Unit System
108. CON 0 to 1 Also you should wait a time of Erase Sector erase or Hard lock to complete it s operation before a byte programming or a byte read of same sector area by using LDC instruction When you read or program a byte data from or into flash memory this bit is not needed to manipulate NOTE When the ID code A5H is written to the FMUSR register A mode of sector erase user program and hard lock may be executed unfortunately So it should be careful of the above situation 19 2 ELECTRONICS S3F84Q5_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE Flash Memory User Programming Enable Register FMUSR The FMUSR register is used for a safety operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000 by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101b user program mode is disabled Flash Memory User Programming Enable Register FMUSR F5H Set 1 Bank 1 R W Flash memory user programming enable bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 19 2 Flash Memory User Programming Enable Register FMUSR ELECTRONICS 19 3 EMBEDDED FLASH MEMORY INTERFACE S3F84Q5_UM_REV1 00
109. CONL Port 2 pins are configured individually by bit pair settings in two control registers located P2CONL low byte Set1 and P2CONH high byte EAH Set1 When you select output mode a push pull an open drain circuit is configured In input mode many different selections are available e Input mode e Output mode Push pull or Open drain e Alternative function Timer A signal in out mode TAOUT TACAP TACK e Alternative function Timer B signal out mode TBOUT e Alternative function Timer 1 signal in out mode T1OUT T1CAP T1CK e Alternative function PWM out mode PWM e Alternative function Buzzer output BUZ ELECTRONICS 9 9 PORTS S3F84Q5_UM_REV1 00 Port 2 Control Register High Byte P2CONH EAH Setl Banko R W Reset value 00H 1 T1OUT T1CK Input mode Input mode with pull up Push pull output Alternative function PWM signal output Input mode T1CAP input Input mode with pull up input Push pull output Open drain output Input mode Input mode with pull up Push pull output Alternative function T1OUT signal output Input mode T1CK input Input mode with pull up T 1CK input Push pull output Open drain output Figure 9 5 Port 2 High Byte Control Register 2 9 10 ELECTRONICS S3F84Q5_UM_REV1 00 PORTS Port 2 Control Register Low Byte P2CONL Bank0 R W Reset value 00H P2 3 P2 2 P2
110. CRIPTION In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin In mode 2 the baud rate is fixed at fxx 16 Each data frame has three components e Start bit 0 e 8 data bits LSB first e Programmable 9th data bit e Stop bit 1 The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCONO 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCONO 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 clock frequency Mode 2 Transmit Procedure 1 Select mode 2 9 bit UARTO by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to or 1 2 Write transmission data to the shift register UDATA FFH to start the transmit operation Mode 2 Receive Procedure 1 Select mode 2 and set the receive enable bit RE in the UARTCON register to 1 2 The receive operation starts when the signal at the RxD pin goes to low level clock Write to Shift Register U shift Jb db X os X n4 X Ds X X X J J Stop Bit TIP TB8 or Parity bit Transmit RB8 or Parity bit MI stangi 00 X D X X X Ds X De X D7 Aag Bit Detect Sample Time
111. Chapter 13 Timer 0 One 16 Bit Timer Mode Timer 0 13 1 M 13 1 FUNCHOM 13 1 BlockDiagtam rus 13 3 Two 8 Bit Timers Mode Timer C and D enne nennen nnne nnn sns ente en 13 4 rod e ok rM SS Sn ree CA EE 13 4 F nctiori Descriptign s c t e tet ta e tet 13 7 Chapter 14 UART noA 14 1 Programming Procedure sided ettet Ae ree he 14 1 UART Control Register 14 2 UART Interrupt Pending Register UARTPND 14 3 Uart Data Register 14 4 Uart Baud Rate Data Register 14 4 Baud Rate Calculations sssssssssssssssseseseseene eee nnne nennen rns nr tren tene en res 14 5 Block TEC 14 6 Uart Mode 0 Function Description esras 14 7 Uar Mode 1 Function Description eioi arati
112. ER Table of Contents Continued Chapter 4 Control Registers UII cT 4 1 Chapter 5 Interrupt Structure rad eut oasis ni ni sinum iles Dea A C IE Ioni 5 1 Interrupt TYPOS 5 2 SSF84Q5 Interrupt Ao aani eai taa aan iaa 5 3 System Level Interrupt Control 4 0 5 6 Interrupt Processing Control 5 7 Peripheral Interrupt Control Registers nnns nennen 5 8 System Mode Register SYM 5 9 Interrupt Mask Register IMR 5 10 Interrupt Priority Register 5 11 Interrupt Request Register 5 13 Interrupt Pending Function Types 5 14 Interrupt Source Polling 5 15 Interrupt Service Routines sssssssssssssssseeeeeee eene enne 5 15 Generating interrupt Vector Addresses sse enne tenente nnns 5 16 Nesting of Vectored Interrupts 5 16 Instruction Pointer ae ein a 5 16 Fast lnterr pt PTOCOSSIDg iita perve CABE CERE andi octe
113. ES The three components of the S3C8 S3F8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source 54 Type 2 One level IRQn one vector V4 multiple sources S S Type 3 One level IRQn multiple vectors V4 V multiple sources S4 51 Sham In the S8F84Q5 microcontroller two interrupt types are implemented Levels Vectors Sources 1 IRQn vi Type 2 IRQn NOTES 1 The number of Sn and Vn value is expandable 2 Inthe S3F84Q5 implementation interrupt types 1 and 2 are used Figure 5 1 S3C8 S3F8 Series Interrupt Types 5 2 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE S3F84Q5 INTERRUPT STRUCTURE The S3F84Q5 microcontroller supports 23 interrupt sources Every interrupt source has a corresponding interrupt address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contend
114. FMSECL F7H Set 1 Bank 1 R W Don t care Flash Memory Sector Address Low Byte NOTE Thelow byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 19 4 Flash Memory Sector Address Register Low Byte FMSECL 19 4 ELECTRONICS S3F84Q5_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store on board program software boot program code for upgrading application code by interfacing with I O pin The ISP sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the Tool Program mode by Serial programming tools The size of ISP sector can be varied by settings of Smart Option You can choose appropriate ISP sector size according to the size of On Board Program software Decimal 16 383 16K bytes Internal Program Memory Area Available ISP Sector Area S3F84Q5 Figure 19 5 Program Memory Address Space ELECTRONICS 19 5 EMBEDDED FLASH MEMORY INTERFACE Table
115. Flags Register 6 6 7 1 Crystal Ceramic Oscillator fx 7 2 7 2 External Oscillator fX esna entente nennen 7 2 7 3 Crystal Ceramic Oscillator fxt sss 7 2 7 4 External Oscillator i tee ee e ae te elec 7 2 7 5 System Clock Circuit nns 7 3 7 6 System Clock Control Register 2 7 4 7 7 Oscillator Control Register 5 0 4040000 0 7 5 7 8 STOP Control Register 7 7 8 1 Low Voltage Reset Circuit 0 c cccccceeececeeececeeeeeaeeseeeeeeceaeeeeaaeseeeeeseaeeesaeeseaaeeeeeeeeeas 8 2 8 2 Reset Block Diagrar 2 nigi deditus eue cete cede de eie 8 3 8 3 Timing for S8F84Q5 after 8 3 9 1 Port 0 Control Register 9 4 9 2 Port 1 High Byte Control Register 9 6 9 3 Port 1 Low Byte Control Register 9 7 9 4 Port 1 Interrupt Control Register 9 8 9 5 Port 2 High Byte Control Register 2 9 10 9 6 Port 2 Low Byte Control Register P2CONL 9 11 9 7 Port High Byte Control Register PBCONH sse 9 13 9 8 Port Low Byte Control Register
116. Flash Memory Sector Address Registers There are two sector address registers for addressing a sector to be erased The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Sector Address Register High Byte indicates the high byte of sector address The FMSECH is needed for S3F84Q5 because it has 128 sectors respectively One sector consist of 128 bytes Each sector s address starts or XX80H that is a base address of sector is XX00H or XX80H So FMSECL register 6 0 don t mean whether the value is 1 or 0 We recommend that the simplest way is to load sector base address into FMSECH and FMSECL register When programming the flash memory you should write data after loading sector base address located in the target address to write data into FMSECH and FMSECL register If the next operation is also to write data you should check whether next address is located in the same sector or not It case of other sectors you must load sector address to FMSECH FMSECL register according to the sector Flash Memory Sector Address Register High Byte FMSECH F6H Set 1 Bank 1 RW Flash Memory Setor Address High Byte NOTE high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 19 3 Flash Memory Sector Address Register High Byte FMSECH Flash Memory Sector Address Register Low Byte
117. H LD FMSECL 80H Set sector address 1780 17 LD R2 4H 7H Set a ROM address in the same sector 1780H 17FFH LD R3 84H LD R4 78H Temporary data LD FMUSR 0A5H User program mode enable LD FMCON 01010000B Start program LDC RR2 R4 Write the data to a address of same sector 1784H NOP Dummy instruction this instruction must be needed LD FMUSR 0 User program mode disable ELECTRONICS 19 9 EMBEDDED FLASH MEMORY INTERFACE S3F84Q5_UM_REV1 00 READING The read operation of programming starts by LDC instruction The Program Procedure in User Program Mode 1 Load a flash memory upper address into upper register of pair working register 2 Load flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 3H Load flash memory upper address To upper of pair working register LD R3 0 Load flash memory lower address To lower pair working register LOOP LDC RO RR2 Read data from flash memory location Between 300H and 3FFH INC R3 CP R3 0FFH JP NZ LOOP 19 10 ELECTRONICS S3F84Q5_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by write 0110 in FMCON 7 4 If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by
118. H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 87 INSTRUCTION SET S3F84Q5_UM_REV1 00 WEI wait for Interrupt WFI Operation Flags Format Example The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 1 2 3 The following sample program structure shows the sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET XOR Logical Exclusive OR XOR dst src Operation dst lt dst src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored Flags C Unaffect
119. ICS S3F84Q5_UM_REV1 00 14 BIT PWM PWM CONTROL REGISTER PWMCON The control register for the PWM module PWMCON is located at register address FOH Set 1 Bank 0 PWMCON is used the 14 bit PWM modules Bit settings in the PWMCON register control the following functions e PWM counter clock selection e PWM data reload interval selection e PWM counter clear e PWM counter stop start or resume operation e PWM counter overflow upper 6 bit counter overflow interrupt control A reset clears all PWMCON bits to logic zero disabling the entire PWM module PWM Control Registers PWMCON FOH Set 1 Bank 0 Reset 00H R W PWM input clock PWM 14 bit OVF Interrupt pending bit selection bits 0 No interrupt pending 00 fosc 256 0 Clear pending condition when write 01 fosc 64 1 Interrupt is pending 10 fosc 8 11 fosc 1 PWM counter interrupt enable bit 0 Disable PWM OVF interrupt Not used for 1 Enable PWM OVF interrupt SSF84Q5 PWM counter enable bit 0 Stop counter 1 Start resume countering PWM counter clear bit 0 No effect 1 Clear the 14 bit up counter Figure 16 3 PWM Capture Module Control Register PWMCON ELECTRONICS 16 5 14 BIT PWM S3F84Q5_UM_REV1 00 fxx 64 fxx fxx 256 fxx 8 PWMCON 6 7 MUX From 6 bit up counter 13 8 From 8 bit up counter 7 0 6 bit 8 bit PWMCON 0 PWMCON 2 PWMCON 1 1 When PWMDATA gt Counter 0 When PWMDATA lt Counter 8 bit lt
120. LVR Low Voltage Reset Circuit 21 7 21 8 A D Converter Electrical 21 8 21 9 AC Electrical Characteristics for Internal Flash ROM S3F84Q5 only 21 9 23 1 Power Selection Settings for 8405 23 4 23 2 DIP Switch for Smart Option Configuration 0 23 4 23 3 DIP Switch for Sub Oscillator Alternative 23 4 23 4 Using Single Header Pins as the Input Path for External Trigger Sources 23 5 xvi S3F84Q5 UM REV 1 00 MICROCONTROLLER List of Programming Tips Description Chapter 2 Address Spaces Using the Page Pointer for RAM Clear Page 0 1 Setting the Register Pointers ra Da cadera eT Edad Using the RPs to Calculate the Sum of a Series of Addressing the Common Working Register Area Chapter 7 Clock Circuit Switching the GRU clock inet e et eed tht donee t n io tst eet Chapter 10 Basic Timer Configuring the Basic 9 9 Chapter 12 16 bit Timer 1 Using the Timer 1 22 te ee Cte a eee Chapter 15 Serial I O Interface Chapter 16 14 Bit PWM Pulse Width Modulation Programming the PWM
121. M 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set1 R W Global interrupt enable bit Always logic 0 0 Disable interrupts processing Fast interrupt level 1 Enable all interrupts processing selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing Not used for the S3F84Q5 4 00 00 Figure 5 5 System Mode Register SYM ELECTRONICS 5 9 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 INTERRUPT MASK REGISTER IMR The interrupt mask register IMR DDH Set1 is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH Set1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set1 R W 01
122. M8 Internal Data Bus RxD P0 0 Write to UDATA Start TxD 0 1 Tx Control Tx Clock TIP TxD 0 1 RIP Receive Rx Control Shift 1 to 0 Transition Detector Shift Bit Detector Value Shift Register J UDATA SAMB8 Internal Data Bus Figure 14 5 UART Functional Block Diagram 14 6 ELECTRONICS S3F84Q5_UM_REV1 00 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0 UART is input and output through the RxD P0 0 pin and TxD P0 1 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 00B 2 Write transmission data to the shift register UDATA FFH to start the transmission operation Mode 0 Receive Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD 0 1 pin and will read the data at the RxD P0 0 pin A UART receive interrupt vector FCH occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA Shift RxD Data Out DO D1 D2 D3 D4 D5 D6 D7 Transmit TxD Shift Clock 1 Write to UARTPND Clear RIP and set RE shi 1 JU JU di RxD Data In TL
123. Mode Tx at falling SIOCON 4 0 15 4 15 5 Serial Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 15 4 15 6 Serial I O Timing Receive Only 15 5 16 1 14 Bit PWM Basic 16 3 16 2 14 Bit Extended PWM 16 4 16 3 PWM Capture Module Control Register 16 5 16 4 PWM Module Functional Block 16 6 53 8405 UM REV 1 00 MICROCONTROLLER xiii List of Figures Concluded Figure Title Page Number Number 17 1 A D Converter Control Register 17 2 17 2 A D Converter Data Register 17 3 17 3 A D Converter Functional Block 17 4 17 4 Recommended A D Converter Circuit for Highest Absolute 17 5 18 1 Watch Timer Control Register 18 2 18 2 Watch Timer Circuit Diagram sse eene nnne nens 18 3 19 1 Flash Memory Control Register 19 2 19 2 Flash Memory User Programming Enable Register 22 2 2 19 3 19 3 Flash Memory Sector Address Register High Byte FMSECH 19 4 19 4 Flash Memory Sector Address Register Low Byte
124. NS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F84Q5_UM_REV1 00 ADC Add with carry ADC Operation Flags Format Examples dst src dst dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if ari
125. Point to Working Pair Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 52 er Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3F84Q5_UM_REV1 00 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte O or 1 lt _ LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed F
126. Prime Area Register 2 9 2 6 8 Byte Working Register Areas 2 10 2 7 Contiguous 16 Byte Working Register Block 2 11 2 8 Non Contiguous 16 Byte Working Register Block 2 12 2 9 16 Bit Register Pair edet ete saves 2 13 2 10 Register File 2 14 2 11 Common Working Register Area enne 2 15 2 12 4 Bit Working Register Addressing seen 2 17 2 13 4 Bit Working Register Addressing Example 2 2 17 2 14 8 Bit Working Register 00 2 18 2 15 8 Bit Working Register Addressing 2 19 2 16 Stack Operations ne Le DB Pe A Pee Das 2 20 3 1 Register 00 3 2 3 2 Working Register 00 2 3 2 3 3 Indirect Register Addressing to Register 00 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register 3
127. R CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual The locations and read write characteristics of all mapped registers in the S3F84Q5 register file are listed in Table 4 1 4 2 and 4 3 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers poo mmm I7 ee Hex 7 6 5 4 3 2 1 0 Location DOH is not mapped STOP Control Regstr AW o o o o OscistrOonrRegser osccon om RW BascTmerConmolRegster BrcON RW o o o o System Clock Control Register RW 9 Register Poitero Reo De mw Re mw 1109 Location D8H is not mapped e me mw xxr instruction Pointer Low Byte PL oeh ma nw m o ImemptMaskRegser RW SysemModeRedser omm RW o Register Page Pomer PP RW ELECTRONICS 4 1 CONTROL REGISTERS S3F84Q5_UM_REV1 00 Table 4 2 Set 1 Bank 0 Registers _ ee oc _ 17 6 8 4 3 2 1 0 Port 0 Data Register Po EM RW Port 1 Data Register P em RW Port 2 Data Regi
128. R List of Tables Table Title Page Number Number 1 1 Pin Descriptions of 28 SOP 32 SOP 32 SDIP 30 5 1 7 1 2 Pin Descriptions of 28 SOP 32 SOP 32 SDIP 30 0 1 8 1 3 Descriptions of Pins Used to Read Write the Flash 1 9 2 1 SSF84Q5 Register Type Summary 2 4 4 1 Set 1 Beglslers oce peru e eie em tutis 4 1 4 2 Set 1 Bank 0 RBeglslers ca ee re deca ete dee e aaa 4 2 4 3 Set 1 Bank 1 4 3 5 1 Interrupt Control Register Overview 5 6 5 2 Interrupt Source Control and Data Registers 5 8 6 1 Instruction Group sse eee enne 6 2 6 2 Flag Notation nnne nens 6 8 6 3 Instruction Set Symbols ssssssssssssssseeee eene 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Quick Reference n Re A ET adig ee 6 10 6 6 GONITIOM I COG OG ERE 6 12 8 1 S3F84Q5 Set1 Registers Values after RESET 8 5 8 2 SSF84Q5 Seti BankO Registers Values after 8 6 8 3 SSF84Q5 Seti Bank1 Registers Values afte
129. R ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode The only unit of flash memory to be erased and programmed in User Program Mode is called sector The program memory of S3F84Q5 is divided into 128 sectors for unit of erase and programming Every sector has all 128 byte sizes of program memory areas So each sector should be erased first to program a new data byte into a sector Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit Sector Erase is not supported in Tool Program Modes MDS mode tool or Programming tool Sector 127 128 Byte Sector 10 128 Byte Sector 0 9 128 byte x 10 S3F84Q5 Figure 19 6 Sector Configurations in User Program Mode ELECTRONICS 19 7 EMBEDDED FLASH MEMORY INTERFACE S3F84Q5_UM_REV1 00 The Sector Erase Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Sector Address Register FMSECH FMSECL 3 Set Flash Memory Control Register FMCON to 10100001B 4 Check the sector erase status bit whether sector erase is success or not 5 Set Flash Memory User Programming Enable Register FMUSR to 00000000B PROGRAMMING TIP Sector Erase SB1 reErase LD FMUSR 0A5H User program mode enable LD FMSECH 10H LD FMSECL 00H Set sector address 1000H 107FH LD FMCON 10100001B Start se
130. Register OSCCON D2H Set1 R W we e 314 3 2 2 Not used System clock selection bit 0 Mainsystem oscillator select 1 Subsystem oscillator select Not used Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP When the CPU is operated with fxt sub oscillation clock itis possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter input clock Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100ms maximum warm up time Here the warm up time is from the stop release signal activates until the basic timer counter counting start Figure 7 7 Oscillator Control Register OSCCON ELECTRONICS 7 5 CLOCK CIRCUIT S3F84Q5_UM_REV1 00 SWITCHING THE CPU CLOCK Data loading in the oscillator control register OSCCON determine whether a main or a sub clock is selected as the CPU clock and also how this frequency is to be divided by setting CLKCON This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies OSCCON O select the main clock fx or the sub clock fxt for the CPU clock OSCCON 3 start or stop main clock oscillation and OSCCON 2 start or stop sub clock oscillation CLKCON 4 3 control the frequency divider circuit and divide t
131. Resume counting 4 Overflow Interrupt Enable bit 14 bit Counter Overflow Disable interrupt 1 Enable interrupt 0 PWM 14 Bit Counter Overflow Interrupt Pending Bit No interrupt pending EN Clear pending condition when write Interrupt pending Clear pending bit when write ELECTRONICS 4 29 CONTROL REGISTERS S3F84Q5_UM_REV1 00 RPO Register Pointer 0 D6H Set 1 Bank 0 RESET Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the 53 8405 1 Register Pointer 1 D7H Set 1 Bank 0 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte worki
132. S COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH Figure 2 11 Common Working Register Area ELECTRONICS 2 15 ADDRESS SPACES S3F84Q5_UM_REV1 00 I PROGRAMMING Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations using working register addressing mode only Examples 1 10 OC2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H the value in location 40H 2 ADD 0C3H 45 Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register point
133. SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SPH OD8H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 55H SP OOFCH POP 00 Register OOH 01H register 01H 55H SP OOFCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 65 INSTRUCTION SET S3F84Q5_UM_REV1 00 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register
134. T1 input Push pull output Alternative function ADC1 input 11 0 bit P 1 0 ADCO INTO Input mode INTO input Input mode with pull up INTO input Push pull output Alternative function ADCO input Figure 9 3 Port 1 Low Byte Control Register P1CONL 9 7 PORTS S3F84Q5_UM_REV1 00 Port 1 External Interrupt Register P1INT E7H Set1 R W Reset value 00H 7 Not used INT1 INTO 1 7 6 bits Not used for 53 8405 5 4 bits INT1 Interrupt Enable Disable Selection Ox Interrupt disable 10 Interrupt enable falling edge 11 Interrupt enable rising edge 3 2 bits INTO Interrupt Enable Disable Selection Ox Interrupt disable 10 Interrupt enable falling edge 11 Interrupt enable rising edge 1 bits INT1 Pending bit No interrupt pending when read Pending bit clear when write Interrupt is pending when read No effect when write 0 bits INTO Pending bit No interrupt pending when read Pending bit clear when write Interrupt is pending when read No effect when write Figure 9 4 Port 1 Interrupt Control Register 9 8 ELECTRONICS S3F84Q5_UM_REV1 00 PORTS PORT 2 Port 2 is an 8 bit port that you can use two ways e General purpose I O e Alternative function Port 2 is accessed directly by writing or reading the port 2 data register P2 at location E2H Set1 Port 2 Control Register P2CONH P2
135. UCTION SET COM Complement COM Operation Flags Format Examples dst dst lt NOT dst S3F84Q5_UM_REV1 00 The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to D Unaffected H Unaffected Bytes Cycles dst 2 Given R1 07H and register 07H OF1H COM Ri gt R1 OF8H COM gt R1 07H register 07H OEH Opcode Addr Mode Hex dst 60 R 61 IR In the first example destination working register R1 contains the value 07H 000001 11B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros vice versa leaving the value OF8H 11111000 In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET CP Compare Operation Flags Format Examples dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Set if a borrow occurred src dst cleared otherwise Z Set if the
136. UM_REV1 00 LDCD LDED Load Memory and Decrement LDCD LDED dst src Operation Flags Format Examples dst lt src rr r 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H OCDH external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by RR6 lt HRR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst lt src rr rr 4 1 These instructions are used for user stacks or block tra
137. UM_REV1 00 PRODUCT OVERVIEW Pull up register 50 kohm typical Pin Circuit Type 1 Pin config bits Ext INT Figure 1 10 Pin Circuit Type 1 2 P1 0 1 1 P3 1 3 2 Pull up register 50 kohm typical Pull up Enable Open drain Enable Data Output Disable Pin Circuit Type 2 Pin config bits Input Ext INT Figure 1 11 Pin Circuit Type 2 2 P3 3 3 6 P3 0 ELECTRONICS 1 11 PRODUCT OVERVIEW VDD Pull up register 50 kohm typical Pull up enable gt 9 Open drain enable Data T 2 Output DIsable i Smart input mode Pin Circuit option Input Data nRESET Figure 1 12 Pin Circuit Type 2 3 P0 2 Pull up register 50 kohm typical Pull up enable gt Data Pin Circuit Type 1 Output Disable input mode XTout XTin Input Figure 1 13 Pin Circuit Type 2 4 P1 2 1 3 SF84Q5_UM_REV1 00 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3F84Q5 microcontroller has two kinds of address space e Internal program memory ROM e Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the internal register file The S3F84Q5 have 16 Kbytes of on chip program memory which is configured as the Internal ROM mode all of the 16 Kbyte internal program memory is used The S3F84Q5 microcontroller has 528 general purpose
138. USER S MANUAL S3F84Q5 8 BIT CMOS MICROCONTROLLERS Dec 2007 REV 1 00 Confiden 5 ung Elec Copyright 2007 Samsun g Electronics Inc All Rights s Reserved Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3F84Q5 8 Bit CMOS Microcontrollers User s Manual Revision 1 00 Publication Number 02 1 00 S3 F84Q5 122007 Copyright 2007 Samsung Electronics Co Ltd Typical parameters can and do vary in different applications All operating p
139. V1 00 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator SMDS2 or SK 1000 for the S3C7 S3C9 and 53 8 microcontroller families SMDS2 is a newly improved version of SMDS2 and SK 1000 is supported by a third party tool vendor Samsung also offers supporting software that includes debugger an assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be easily sized moved scrolled highlighted added or removed SASM The SASM is a re locatable assembler for Samsung s S3C8 series microcontrollers The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and conditional assembly It runs on the MS DOS operating system
140. able Register P 3INT Set1 R W Reset value 00H P3 5 iNT Not used P 3 6 INT7 TS INT8 P3 n bit configuration settings 0 Disable interrupt 1 Enable interrupt NOTE 15 0 1 2 3 4 5 and 6 Figure 9 9 Port 3 Interrupt Control Register P3INT Port3 Interrupt Pending Register P 3P ND Setl R W Reset value 00H P3 4 P3 5 INT6 5 Notused P3 6 INT8 P3 n bit configuration settings No interrupt pending when read Pending bit clear when write Interrupt is pending when read No effect when write NOTE 5 0 1 2 3 4 5 and 6 Figure 9 10 Port Interrupt Pending Register P3PND ELECTRONICS 9 15 S3F84Q5_UM_REV1 00 BASIC TIMER BASIC TIMER OVERVIEW Basic Timer BT You can use the basic timer BT in two different ways Asa watchdog timer to provide an automatic reset mechanism in the event of a system malfunction e To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are e Clock frequency divider fogc divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter FDH Seti read only e Basic timer control register read write ELECTRONICS 10 1 BASIC S3F84Q5_UM_REV1 00 BASIC TIMER BT BASIC TIMER CONTROL REGISTER BTCON
141. ad Write R W R W R W R W R W R W R W R W Addressing Mode 7 and 1 Register addressing mode only Priority Control Bits for Interrupt Groups A B and C note 0 0 0 Group priority undefined 0 0 1 gt gt 0 1 0 gt gt 0 1 1 gt gt 1 0 0 gt gt 1 0 1 gt gt 1 1 0 gt gt 1 1 1 Group priority undefined Interrupt Subgroup C Priority Control Bit 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Interrupt Group C Priority Control Bit 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQS Interrupt Subgroup B Priority Control Bit 0 IRQ3 gt IRQ4 1 IRQ4 gt IRQ3 Interrupt Group B Priority Control Bit 0 IRQ2 IRQ3 IRQ4 1 IRQ3 IRQ4 IRQ2 Interrupt Group A Priority Control Bit 0 IRQO gt 1 IRQ1 IRQO NOTE Interrupt Group A IRQO IRQ1 Interrupt Group B IRQ2 IRQ3 IRQ4 Interrupt Group C IRQ5 IRQ6 IRQ7 4 14 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER IRQ Interrupt Request Register DCH Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Addressing Mode ELECTRONICS Register addressing mode only Level 7 IRQ7 Request Pending Bit SIO UART Transmit UART Receive 0 Not pending 1 Pending Level
142. ag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows Out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the
143. ait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3F84Q5_UM_REV1 00 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRPO src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3F84Q5_UM_REV1 00 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether
144. alues to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS S3F84Q5_UM_REV1 00 FLAGS System Flags Register D5H Set 1 Reset Value X X X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value BG Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 1 Operation generates negative number MSB 1 verflow Flag V Operation result is lt 127 or lt 128 Operation result is gt 127 lt 128 3 Decimal Adjust Flag D Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 1 Fast Interrupt Status Flag FIS 0 Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected Bank 1 is selected 4 8 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER FMCON Flash Memory Control Register F4H Set 1 Bank 1 Bit Identifier qp xc ue Reset Value 0 0 0 0 0 Read Writ
145. and data edit function e PC based operation with RS232C port e Full function regarding OTP programmer Read Program Verify Blank Protection Fast programming speed 1Kbyte sec Support all of SAMSUNG OTP devices Low cost Download the files from the 3rd party link shown below C amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http www cnatech com International Sale SEMINIX e TEL 82 2 539 7891 FAX 82 2 539 7819 E mail cindy seminix com e URL http Awww seminix com Jui 2002 USER s Manual a ij i ALII Syston Lid BlueChips Combi BlueChips combi is a programmer for all Samsung MCU It can program not only all Samsung OTP MTP Flash MCU but also the popular E E PROMs New devices will be supported just by adding device files or upgrading the software It is connected to host PC s serial port and controlled by the software System e TEL 82 31 223 661 1 FAX 82 31 223 6613 E mail openice aijisystem com e URL http www aijisystem com sae GW PRO2 Gang Programmer for One time PROM device 8 devices programming at one time Fast programming speed 1 2Kbyte sec PC based control operation mode Full Function regarding OTP program Read Program Vertify Protection blank e Data back up even at power break After setup in Desgin Lab it can be moved to the factory site Key Lock protectin
146. ansmit Receive Mode Tx at rising SIOCON 4 1 15 4 ELECTRONICS S3F84Q5_UM_REV1 00 Shift Clock Data Input Data Output SERIAL I O INTERFACE IRQS Start Complets Figure 15 6 Serial I O Timing in Receive Only Mode PROGRAMMING TIP SIO ORG 0000H VECTOR OFCH INT_SIO ORG 0100H INITIAL LD SYM 00H LD BTCON 10100010B LD CLKCON 0001 1000B LD SP 0FFH LD 10111100B LD SIOCON 00100110B LD SIOPS 20 EI ELECTRONICS SIO interrupt vector address Global Fast interrupt disable SYM Watch dog disable non divided CPU clock SIO setting Enable SIO Interrupt setting baud rate SERIAL I O INTERFACE PROGRAMMING TIP SIO Continued MAIN SUB_SIO INT_SIO LD OR RET AND IRET SUB_SIO MAIN SIODATA TRANSBUF SIOCON 00001000B SIOCON 11111110 Data transmit routine 1 byte transmission Shift start 8 bit transmit Pending bit clear S3F84Q5_UM_REV1 00 ELECTRONICS S3F84Q5_UM_REV1 00 14 BIT PWM 14 BIT PWM PULSE WIDTH MODULATION OVERVIEW This microcontroller has the 14 bit PWM circuit The operation of all PWM circuit is controlled by a single control register PWMCON The PWM counter is a 14 bit incrementing counter It is used by the 14 bit PWM circuits To start the counter and enable the PWM circuits you set PWMCON 2 to 1 If the counter is stopped it retains its current count value when re started it resume
147. arameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufact
148. atch interrupt TAINT When timer A interrupt occurs and is serviced by the CPU the pending condition is cleared by software In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the Timer A reference data register TADATA The match signal generates a timer A match interrupt and clears the counter If for example you write the value 10H to TADATA and OBH to TACON the counter will increment until it reaches 10H At this point the TA interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is e
149. ation On means switch to low level results in logic 0 On Off means switch to high level results in logic 1 Off NOTE For debugging with the target board smart option is totally determined by the DIP switches in the target board other than the data configured by software Table 23 3 DIP Switch for Sub Oscillator Alternative Pins On means P1 2 and P1 3 are used to be Sub Oscillator pins On Off means P1 2 and P1 3 are used to be general I Os Off NOTE use the sub oscillator make sure that SW3 8 SW1 1 SW1 2 are all in ON status 23 4 ELECTRONICS S3F84Q5_UM_REV1 00 DEVELOPMENT TOOLS Table 23 4 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Connector from Triggers External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation chip 53 8400 is in idle mode STOP LED This LED is ON when the evaluation chip 53 8400 is in stop mode ELECTRONICS 23 5 DEVELOPMENT TOOLS S3F84Q5_UM_REV1 00 VSS NC XOUT NC XIN TEST P0 0 PO 1 P0 2 AVref P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P3 3 OL 97 2 o2 2 95 NOTE N C means Connection Figure 23
150. ation operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 7 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R D1 IR Given Register 9AH register 02H register 03H OBCH and C 1 SRA 00H gt Register 00H 0CD C 0 SRA 02H gt Register 02H register In the first example if general register contains the value 10011010B the statement SRA 00H shifts the bit values in register right one bit position Bit zero 0 clears the flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101 in destination register OOH ELECTRONICS 6 81 INSTRUCTION SET SRP SRPO SRP1 set Register Pointer SRP SIC SRPO SIC SRP1 SIC Operation If src 1 1 and src 0 Othen If src 1 0 and src 0 1 then If src 1 src 0 Othen RP1 3 111171 lt 53 8405 UM REV1 00 src 3 7 src 3 7 src 4 7 0 src 4 7 1 The source data bits one and zero LSB determine whether to
151. can be used to return to the original program flow RET pops the top of the stack back into the program counter Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR dst 2 14 D4 IA Examples Given RO 35H R1 21H 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000 0000 0001H 49H CALL 40H SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first 6 26 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET example
152. ck Interrupts e 23 interrupt sources 9 external and 14 internal with 23 vectors 8 levels Ports e Total 22 24 26 bit programmable pins Basic Timer e One programmable 8 bit basic timer BT for Oscillation stabilization control Timers e 8 bit timer counter Timer with three operating modes Interval mode capture mode and PWM mode SF84Q5 UM REV1 00 e 8 bit timer counter Timer B with 2 operating modes interval mode and PWM mode e 16 bit capture timer counter Timer 1 with three operating modes Interval mode Capture mode for pulse period or duty and PWM mode Timer 0 Timer Counters programmable 8 bit timer counters e Configurable as one 16 bit timer counter Watch Timer e Real time and interval time measurement e Four frequency output 0 5 1 2 4kHz to BUZ pin PWM module e 14 bit PWM e 8 bit base 6 bit extension frame A D Converter e Eight analog input channels e 10 bit conversion resolution Serial I O e synchronous serial I O module e Selectable transmit and receive rates Asynchronous UART e Programmable baud rate generator e Support serial data transmit receive operations with 8 bit 9 bit UART Low Voltage Reset LVR e Low Voltage Check to make system reset Vive 2 2 3 0V 4 0V by smart option Operating Temperature Range e 40 to 85 C Operating Voltage Range e 2 0V to 5 5V 1 AMHz LVR Disable LVR to 5 5 V
153. clear Enable interrupt Enable watchdog function Basic counter BTCNT clear ELECTRONICS S3F84Q5 UM REV1 00 8 BIT TIMER A B 8 TIMER 8 BIT TIMER A OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting e Interval timer mode Toggle output at TAOUT pin e Capture input mode with a rising or falling edge trigger at the TACAP pin e PWM mode TAOUT Timer A has the following functional components e Clock frequency divider divided by 1024 256 or 64 with multiplexer e External clock input TACK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register e O pins for capture input TACAP PWM or match output TAOUT e Timer A overflow interrupt and match capture interrupt generation e Timer A control register TACON Set1 Bank1 read write ELECTRONICS 11 1 8 BIT TIMER S3F84Q5_UM_REV1 00 FUNCTION DESCRIPTION Timer A Interrupts The timer A module can generate two interrupts the timer A overflow interrupt and the timer A match capture interrupt TAINT Timer A overflow interrupt can be cleared by both software and hardware and match capture interrupt pending conditions are cleared by software when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A m
154. components e Analog comparator with successive approximation logic e D A converter logic resistor string type e ADC control register ADCON e Eight multiplexed analog data input pins ADO AD7 alternately digital data I O port e 10 bit A D conversion data output register ADDATAH L AVner AVgg AV gz is internally connected to Vgs FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at the first you must set port control register P1 CONH L for AD analog input And you write the channel selection data in the A D converter control register ADCON 4 7 to select one of the eight analog input pins ADO 7 and set the conversion start bit ADCON 0 The read write ADCON register is located at address Set1 The unused pin can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of a 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 4 7 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH L r
155. ctional Block Diagram 13 3 13 3 Timer C Control Register 13 5 13 4 Timer D Control Register ener nnns 13 6 13 5 Timer C and D Function Block 13 8 13 6 Timer D PWM Function Block Diagram sse 13 9 14 1 UART Control Register 0 4 40000 14 2 14 2 UART Interrupt Pending Register 2 14 3 14 3 UART Data Register 22222 101 000 14 4 14 4 UART Baud Rate Data Register 0000 2 14 4 14 5 UART Functional Block Diagram ssssssssesesese eene 14 6 14 6 Timing Diagram for UART Mode 0 14 7 14 7 Timing Diagram for UART Mode 1 14 8 14 8 Timing Diagram for UART Mode 2 Operation 14 9 14 9 Timing Diagram for UART Mode Operation 14 10 14 10 Connection Example for Multiprocessor Serial Data Communications 14 12 15 1 Serial I O Interface Control Register 15 2 15 2 SIO Pre Scaler Register 20 2 0 00 enne 15 3 15 3 SIO Functional Block Diagram 15 3 15 4 Serial Timing Transmit Receive
156. ctor erase NOP Dummy instruction this instruction must be needed NOP Dummy instruction this instruction must be needed FMCON 00000001B Check sector erase status bit JR NZ reErase Jump to reErase if fail LD FMUSR 0 User program mode disable 19 8 ELECTRONICS S3F84Q5_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one byte unit after sector erase And for programming safety s sake must set FMSECH and FMSECL to flash memory sector value The write operation of programming starts by LDC instruction You can write until 128byte because this flash sector s limit is 128byte So if you written 128byte must reset FMSECH and FMSECL The Program Procedure in User Program Mode Must erase sector before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 01010000B Set Flash Memory Sector Register FMSECH FMSECL to sector value of write address Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B o aon oar PROGRAMMING TIP Program SB1 LD FMSECH 17
157. d Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer D9H Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W 7 0 Stack Pointer Address The SP value is undefined following a reset 4 32 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER STPCON Stop Control Register D1H Set 10 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before executing the STOP instruction you must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed ELECTRONICS 4 33 CONTROL REGISTERS S3F84Q5_UM_REV1 00 SYM System Mode Register DEH Set 1 Reset Value 0 X X X 0 0 Read Write R W R W R W R W R W R W 7 Tri state External Interface Control Bit 1 Normal operation disable tri state operation Set external interface lines to high impedance enable tri state operation 6 5 Not used for the 53 8405 4 2 Fast Interrupt Level Selection Bits 2 1 Fast Interrupt Enable Bit 3 EN Disable fast interrupt p
158. destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles dst opc 1 4 Given RO 1BH register and register 1BH OFH INC RO gt RO 1CH INC OOH gt Register OOH ODH INC RO RO 1BH register 01H 10H INSTRUCTION SET Opcode Addr Mode Hex dst rE r r 0 to F 20 R 21 IR In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS 6 45 INSTRUCTION SET S3F84Q5_UM_REV1 00 INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffect
159. divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 03H R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value and R1 contains 40H 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONICS 6 39 INSTRUCTION SET S3F84Q5_UM_REV1 00 DJNZ Decrement and Jump if Non Zero DJNZ Operation r dst r r 41 If r z0 lt PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or instruction
160. drain output 1 0 P3 4 INT6 Input mode INT6 falling edge interrupt 1 Input mode with pull up INT6 falling edge interrupt 3 0 JPuspulotpt ELECTRONICS 4 23 CONTROL REGISTERS S3F84Q5_UM_REV1 00 P3CONL Port Control Register Low Byte EDH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 5 4 3 2 Input mode INT3 falling edge interrupt Input mode with pull up INT3 falling edge interrupt Push pu output 1 0 4 24 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER PSINT Port Interrupt Enable Register EEH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used for 53 8405 6 P3 6 INT8 External Interrupt Enable Bit INT8 falling edge interrupt disable 1 INT8 falling edge interrupt enable 5 P3 5 INT7 External Interrupt Enable Bit NT7 falling edge interrupt disable 1 NT7 falling edge interrupt enable 4 P3 4 INT6 External Interrupt Enable Bit NT6 falling edge interrupt disable 6 falling edge interrupt enable 3 P3 3 INT5 External Interrupt Enable Bit NT5 falling edge interrupt disable 1 NT5 falling edge interrupt enable 2 P3 2 INT4 External Interrupt Enable Bit INT4 falling edge interrupt disable 1 INT4 falling edge interrupt enable 1 P3 1 INT3 External Interrupt Enable Bit falling edge i
161. dst opc src 2 4 r IM r8 r R r 0toF 4 D7 Ir r src dst 3 E4 R R E5 R IR opc dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R 8006006 6 50 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET LD Load LD Continued Examples Given RO 01H R1 OAH register OOH 01H register 01H 20H register 02H 02H LOOP and register OFFH LD RO 10H LD R0 01H gt RO 10H gt RO 20H register 01H 20H LD 01H RO gt Register 01H 01H RO O1H LD R1 RO gt R1 20H RO 01H LD RO R1 gt RO 01H R1 OAH register 01H OAH gt gt gt gt LD 00H 01H Register OOH 20H register 01H 20H LD 02H 00H Register 02H 20H register 01H LD 00H 0AH Register 00H OAH LD 00H 10H Register OOH 01H register 01H 10H LD 00H 02H gt Register 01H register 01H 02 register 02H 02H LD RO LOOP R1 gt RO OFFH R1 OAH LD LOOP RO R1 gt Register 31H OAH RO 01H R1 OAH ELECTRONICS 6 51 INSTRUCTION SET S3F84Q5_UM_REV1 00 LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags a
162. e 1 Enable interrrupt 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture falling edge counter running OVF can occur 11 mode OVF interrupt and match interrupt can occur Timer A overflow interrupt enable bit 0 Disable overflow interrupt 1 Enable overflow interrrupt Timer A counter clear bit 0 No effect 1 the timer A counter when write When the counter clear bit 3 is set the 8 bit counter is cleared and italso is cleared automatically Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 BIT S3F84Q5_UM_REV1 00 Timer Interrupt P ending Register TINTPND F1H 1 Bank1 Reset 00H TT gt Timer A macth capture interrupt pending flag 0 Not pending clear pending bit Interrupt pending Timer 1 overflow interrupt pending flag 0 Not pending clear pending bit 1 1 Interrupt pending Timer A overflow Timer 1 match interrupt pending flag interrupt pending flag 0 Not pending clear pending bit 0 Not pending clear pending bit 1 Interrupt pending 1 Interrupt pending Timer B match capture Timer D overflow interrupt pending flag 2 flag 0 Not pending clear pending bit 0 Not pending clear pending bit 1 Interrupt pending 1 Interrupt pending Timer B overflow interrupt pending flag 0 Not pending clear pending bit 1 Inter
163. e basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 8 2 ELECTRONICS S3F84Q5_UM_REV1 00 MCU Initialization Sequence RESET and POWER DOWN The following sequence of events occurs during a Reset operation All interrupts are disabled The watchdog function basic timer is enabled Ports 0 3 are set to input mode Peripheral control and data registers reset to their initial values see Table 8 1 The program counter is loaded with the ROM reset address 0100H or other values set by smart option When the programmed oscillation stabilization time interval has elapsed the address stored in the first and second bytes of RESET address in ROM is fetched and executed Smart Option Internal nRESET LVR nRESET Watchdog nRESET nRESET Input Normal Mode or Power Down Mode ELECTRONICS Figure 8 2 Reset Block Diagram Oscillation Stabilization Wait Time 8 19 ms at 8 MHz RESET Operation Figure 8 3 Timing for S3F84Q5 after RESET 8 3 RESET POWER DOWN S3F84Q5_UM_REV1 00 POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 200 uA except that the LVR Low Voltage Reset is enabled All syst
164. e R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits Programmingmode Sectorerasemode Fo 1 1 tock mode Other values Not available 43 11 Not used for the S3F84Q5 0 Flash Operation Start Bit EZ Operation stop 1 Operation start This bit will be cleared automatically just after the erase or hardlock operation completed ELECTRONICS 4 9 CONTROL REGISTERS S3F84Q5_UM_REV1 00 FMSECH Flash Memory Sector Address Register High Byte F6H Set 1 Bank 1 Bit Identifier _ 5 4 3 2 a o 0 0 0 0 0 0 0 Reset Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Bits High Byte The 15th 8th bits to select a sector of flash ROM NOTE The high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address FMS ECL Flash Memory Sector Address Register Low Byte F7H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Flash Memory Sector Address Bit Low Byte The 7 bit to select a sector of flash ROM 6 0 Bits 6 0 Don t care NOTE The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address 4 10 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER
165. e decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F84Q5_UM_REV1 00 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI W
166. e enable bit for global interrupt processing ELECTRONICS 6 41 INSTRUCTION SET S3F84Q5_UM_REV1 00 ENTER Enter ENTER Operation SP lt SP 2 QSP lt IP IP lt lt 2 This instruction is useful when implementing threaded code languages contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement After Address IP Address Address Data PC 40 Enter 40 Enter 1F Address H 41 Address 01 Address L 42 Address L 10 0022 Address 43 Address 20 00 110 Routine 21 IPL 50 22 Data 22 Data Stack Stack ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET EXIT exit EXIT Operation Flags Format Example Address IP PC SP 20 21 22 IP lt 5 SP lt 2 lt IP IP lt 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded i
167. e pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 16 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the S3F84Q5 the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However
168. ecuted the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In S3F84Q5 interrupt structure TimerA TimerB TimerD and PWM counter overflow interrupts belong to this category of interrupts in which pending bits can be cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register 5 14 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows Sog PF OND A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifie
169. ed H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 AO RR Al IR Given RO R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW gt Register 02H 10H register 00H In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode to increment the contents of general register from OFFH to OOH and register 02H from OFH to 10H system malfunction may occur if you use a Zero 2 flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET IRET Interrupt Return IRET IRET Normal IRET Fast Operation FLAGS SP PC o IP SP lt SP 1 FLAGS lt FLAGS PC SP FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt
170. ed Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 r Ir opc src dst 3 6 B4 R R B5 R IR opc dst src 3 6 B6 R IM Examples Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H XOR RO R1 gt RO OC5H R1 02H XOR RO R1 gt RO OE4H R1 02H register 02H 23H XOR 00H 01H gt Register 00H 29H register 01H 02H gt gt XOR 00H 01H Register 08H register 01H 02H register 02H 23H 00H 454H Register 00H 7FH In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 89 S3F84Q5_UM_REV1 00 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3F84Q5 microcontroller has two oscillator circuits a main clock and a sub clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits The maximum CPU clock frequency of 53 84 5 is determined by register settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal ceramic resonator or an external clock source e Oscilla
171. ed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 9 16 Bit Register Pair ELECTRONICS 2 13 ADDRESS SPACES S3F84Q5_UM_REV1 00 Special Purpose Registers General Purpose Register Po t T Hi Bank 1 Bank 0 Control Registers System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE Inthe S3F84Q5 microcontroller page 0 1 are implemented Page 0 Page 0 Register Addressing Only All Indirect Register Addressing Indexed Modes Addressing Modes Can be Pointed by Register Pointer Figure 2 10 Register File Addressing ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACE
172. ed to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 C2 dr NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 03H 02H R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 lt RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relat
173. egister where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH L before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD7input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 17 1 S3F84Q5_UM_REV1 00 CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete a 10 bit conversion When Fxx 8 is selected for conversion clock with a 8 MHz fxx clock frequency one clock cycle is 1 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit 10 bits set up time 50 clocks 50 clock x 1us 50 us at 8 MHz A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located at address Seti Banko It has three functions e Analog input pin selection bits 4 5 6 and 7 e A D convers
174. el numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings let you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 S3F8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3F84Q5 uses 23 vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In 53 8405 interrupt structure there 23 possible interrupt sources that means every source has its own vector When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 INTERRUPT TYP
175. em functions are halted when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by an nRESET signal or by an external interrupt Using RESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to High level All system and peripheral control registers are then reset to their default values and the contents of all data registers are retained A Reset operation automatically selects a slow clock f 16 because CLKCON 3 CLKCON 4 are cleared to After the oscillation stabilization interval has elapsed the CPU executes the system initialization routine by fetching the 16 bit address stored in the first and second bytes of RESET address configured by smart option in ROM Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Clock related external interrupts cannot be used External interrupts INTO INT8 in the S3F84Q5 interrupt structure meet this criterion Note that when Stop mode is released by an external interrupt the current values in system and peripheral control registers are not changed When you use an interrupt to release Stop mode the CLKCON 3 and CLKCON 4 register values remain unchanged and the currently selected clock value is used thus you can also program the duration of the oscillation stabilization interval by puttin
176. en write 1 Interrupt pending UART receive interrupt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Figure 14 2 UART Interrupt Pending Register UARTPND ELECTRONICS 14 3 UART S3F84Q5_UM_REV1 00 UART DATA REGISTER UDATA UART Data Register UDATA F8H Set1 Bank1 R W Reset Value Transmit or Receive data Figure 14 3 UART Data Register UDATA UART BAUD RATE DATA REGISTER BRDATA The value stored in the UART baud rate register BRDATA lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATA F8H Set1 R W Reset Value FFH Brud rate data Figure 14 4 UART Baud Rate Data Register BRDATA 14 4 ELECTRONICS S3F84Q5_UM_REV1 00 UART BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register 8bit BRDATA Mode 0 baud rate fxx 16 x 8Bit BRDATA 1 Mode 1 baud rate 16 x 8Bit BRDATA 1 Mode 2 baud rate fxx 16 Mode 3 baud rate fxx 16 x 8Bit BRDATA 1 Table 14 1 Commonly Used Baud Rates Generated by 8 bit BRDATA uM BRDATA sese uws oe ELECTRONICS 14 5 UART S3F84Q5_UM_REV1 00 BLOCK DIAGRAM SA
177. ents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R8 no change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers R2 R8 no change LDC R0 201H RR2 RO lt contents of program memory location 0105H 01H RR2 6DH R2 01H 04H LDE R0 01H RR2 contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H LDC nete 01H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H 04H LDE R0 1000H RR2 contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H LDC 0 1104 lt contents of program memory location 1104H 88H LDE 0 1104 lt contents of external data memory location 1104H 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H 11H LDE 1105 0 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 55 INSTRUCTION SET S3F84Q5_
178. er FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 78 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET SBC subtract with Carry SBC dst src Operation dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Set if a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise
179. er serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address e The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 e The five high order bits in the register pointer select an 8 byte slice of the register space e The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 12 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 14 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 16 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES Selects RPO or Address OPCODE fe
180. errupt levels IRQO0 IRQ7 can be selected for fast interrupt processing PROCEDURE FOR INITIATING FAST INTERRUPTS To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register FAST INTERRUPT SERVICE ROUTINE When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced arwon Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically RELATIONSHIP TO INTERRUPT PENDING BIT TYPES As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt
181. errupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state 6 38 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET DIV Divide Unsigned DIV Operation Flags Format dst src dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the
182. ess value is one bit in length Given R1 07H andregister 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 000001 11B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R11 o R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 1
183. essed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 14 11 UART S3F84Q5_UM_REV1 00 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications Set all S8F84Q5 devices masters and slaves to UART mode 2 or 2 Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is e First byte the address identifying the target slave device 9th bit 2 1 e Next bytes data 9th bit 0 4 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3F84Q5 Interconnect RxD RxD TxD RxD TxD RxD Master Slave 1 Slave 2 Slave 5328405 S3F84Q5 S3F84Q5 SSF84Q5 Figure 14 10 Connection Example for Multiprocessor Serial Data Communications 14 12 ELECTRONICS S3F84Q5_UM_REV1 00 SERIAL I O
184. est Jump Relative on 2 0222 0 1 0 ener nnne 6 24 BXOR Bit XOR cm RR 6 25 CALL Gall Procedute sitire e TRE eoe Ha eiie bier 6 26 CCF Complement Carry ennemis nnn enne 6 27 CLR GI fep 6 28 COM rene E 6 29 CP COMPAS aie 6 30 Compare Increment and Jump on Equal 6 31 CPIJNE Compare Increment and Jump on 6 32 DA Decimal AGUS s e dee Hoe ee A Rel Or Dee d eae ut 6 33 DA Decimal AdJUSL E Et Pe eei 6 34 DEC Decrement 2 oec ee He da pea ee ve 6 35 DECW Decrement forro EE 6 36 DI Disable Interrupts ss tea re dereud e ee diu v pe 6 37 DIV Divide Unsigned rr RR BR GR Perte RA 6 38 DJNZ Decrement and Jump if 6 39 El Enable Interr pts iii cri eame eti ee rehab Fert 6 40 ENTER ETE axe et e e t a ag d aate hatin evn A 6 41 EXIT cum H eet 6 42 IDLE 116 uite ee Hatte dida He eal Pede te t Lg eO ie 6 43 INC et 6 44 INCW Incremernt WOFd x deve rie pe d ect Ug ler 6 45 IRET Interrupt Return icc erre ERE He GER ei rein ideis 6 46 JP
185. f a valid stop bit was not received In mode 0 the UARTCON 5 bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Figure 14 1 UART Control Register UARTCON 14 2 ELECTRONICS S3F84Q5_UM_REV1 00 UART UART INTERRUPT PENDING REGISTER UARTPND The UART interrupt pending register UARTPND is located at address F6H Banko It contains the UART data transmit interrupt pending bit UARTPND 0 and the receive interrupt pending bit UARTPND 1 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 is set to 1 when the 8th receive data bit has been shifted In mode 1 or 2 the UARTPND 1 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 flag must be cleared by software in the interrupt service routine In mode 0 of the UART module the transmit interrupt pending flag UARTPND O is set to 1 when the 8th transmit data bit has been shifted In mode 1 or 2 the UARTPND O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UARTPND 0 flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND F6H Set1 R W Reset Value UART transmit interrupt pending flag 0 Not pending 0 Clear pending bit wh
186. for RAM Clear Page 0 Page 1 LD PP 00H Destination lt 0 Source lt 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO 00H LD PP 10H Destination lt 1 Source 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR RO 00H NOTE You should refer page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program ELECTRONICS 2 7 ADDRESS SPACES S3F84Q5_UM_REV1 00 REGISTER SET 1 The term set 7 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contains 46 mapped system and peripheral control registers The lower 32 byte area contains 14 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at any time using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about wo
187. for UART Mode 3 Operation 14 10 ELECTRONICS S3F84Q5_UM_REV1 00 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C8 series multiprocessor communication features let a master S3F84Q5 send a multiple frame serial message to a slave device in a multi SSF84Q5 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART mode 2 or 3 with the parity disable mode In mode 2 and 3 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addr
188. g operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation mode displayed in LCD pannel Stand alone mode C amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http www cnatech com International Sale SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 e E mail cindy seminix com e URL http Awww seminix com ELECTRONICS 23 9
189. g s SAM8RC family of 8 bit single chip CMOS microcontrollers offer a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes address data bus architecture and a large number of bit configurable ports provide a flexible programming environment for applications with varied memory and requirements Timer counters with selectable operating modes are included to support real time operations S3F84Q5 MICROCONTROLLER S3F84Q5 single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based Samsung s latest CPU architecture The S3F84Q5 is a microcontroller with a 16K byte full flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3F84Q5 by integrating the following peripheral modules with the powerful SAM8 RC core e Four configurable I O ports 22 pins 24pins 26pin e Twenty three interrupt sources with twenty three vectors and eight interrupt level e One watchdog timer function Basic Timer e One 8 bit basic timer for oscillation stabilization e Four 8 bit timer counters with time interval PWM and Capture mode Timer C and Timer D can be used for 16 bit Timer 0 e One 16 bit timer counter with three operating modes Interval timer Capture and PWM mode If Timer and Timer are used for Timer 0 S3F84Q5 has two 16 bit Timer Timer 0 and Timer 1 e Analog to digita
190. g the appropriate value to BTCON register before entering Stop mode The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In Idle mode CPU operations are halted while select peripherals remain active During Idle mode the internal clock signal is gated off to the CPU but not to interrupt logic and timer counters Port pins retain the mode input or output they had at the time Idle mode was entered There are two ways to release idle mode 1 Execute a Reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The Reset automatically selects a slow clock f 16 because CLKCON 3 and CLKCON 4 are cleared to 00B If interrupts are masked a Reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 3 and CLKCON 4 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced Following the IRET from the service routine the instruction immediately following the one that initiated idle mode is executed NOTES 1 Only external interrupts that are not clock related can be used to release stop
191. hapter 8 RESET and Power Down Chapter 17 10 Bit Analog To Digital Converter Chapter 9 Ports Chapter 18 Watch Timer Chapter 10 Basic Timer Chapter 19 Embedded Flash Memory Interface Chapter 11 8 bit Timer A B Chapter 20 Low Voltage Reset Chapter 12 16 bit Timer 1 Chapter 21 Electrical Data Chapter 13 Timer 0 Chapter 22 Mechanical Data Chapter 14 UART Chapter 23 Development Tools Chapter 15 Serial I O Interface S3F84Q5_UM_REV 1 00 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S3C8 Series Microcontrollers cccceesceceeeeeceneeeeeneeceeeeeeeaeeeeaae sence eene nennen tnnnenne nennt 1 1 SSF84Qb MicroconttrollGr accio ott i re ete it tee itt er c e e ee 1 1 za rcp A E 1 2 Block Diagram eite e e cet d et eee ted e d itl n e en 1 3 Pin Assignment tse RR ERAN 1 4 PII sector Page ese EEEN 1 5 1 7 ELE 1 10 2 Address Spaces OVGIVIOW m tb ere De da Lt ied eed 2 1 Program Memory ROM 5 1 deceret eet dre e HR 2 2 Register Architecture eae eret e ecu de eue 2 4 Register Page Pointer PP
192. he selected fxx clock by 1 2 8 16 For example you are using the default CPU clock normal operating mode and a main clock of fx 16 and you want to switch from the main clock fx to a sub clock fxt and to stop the main clock To do this you need to set CLKCON 4 3 to 11 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxt and stops main clock oscillation The following steps must be taken to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscillation Then after a certain number of machine cycles have elapsed select the main clock by setting OSCCON O to 0 I PROGRAMMING Switching the CPU clock 1 This example shows how to change from the main clock to the sub clock MA2SUB LD OSCCON 09 Switches to the sub clock Stop the main clock oscillation RET 2 This example shows how to change from sub clock to main clock SUB2MA AND OSCCON 07 Start the main clock oscillation CALL DLY16 Delay 16 ms AND OSCCON 06 Switch to the main clock RET DLY16 SRP 0C0H LD RO 20H DEL NOP DJNZ RO DEL RET 7 6 ELECTRONICS S3F84Q5_UM_REV1 00 CLOCK CIRCUIT STOP Control Register STPCON D1H Set1 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before execute the STOP instruction set this STPCON register as 101001018 Otherwise the STOP instruction
193. if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS 6 27 INSTRUCTION SET S3F84Q5_UM_REV1 00 CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if C O the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET CLR CLR Operation Clear dst dst 0 The destination location is cleared to O Flags No flags are affected Format Examples Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 BO R 4 1 Given Register 4FH register 01H 02H register 02H CLR OOH gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH ELECTRONICS 6 29 INSTR
194. ignal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010 The 1010 value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the oscillator clock divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of 5 4096 for reset or at the rate of the preset clock source for an external interrupt
195. igure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3F84Q5_UM_REV1 00 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory 4 Next Instruction LSB Must be Zero uen urren Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESSING MODES
196. ing interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 Levels Vectors Sources Reset C lear RESET 100H Basic timer overflow H W DOH Timer A overflow H W S W D2H _ S W Timer A match capture D4H Timer B overflow H W S W dis D6H Timer B match S W D8H Timer D overflow H W S W IRQ2 DAH TimerD match S W DCH Timer match S W DEH _ Watch timer interrupt S W PWM Counter Overflow H W S W E2H mW Timer 1 overflow H W S W E4H S W Timer 1 match capture E6H P1 0 external interrupt INTO S W IRQ5 P1 1 external interrupt INT1 S W UART Transmit interrupt S W
197. int to the OPERAND LA Working Register Two Operand 1 048 Instruction Example Sample Instruction ADD R1 R2 Where 1 R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Register addressing mode Program Memory Register File amp btRegstr ADDRESS OPCODE Point to One gt Register in Register Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3F84Q5_UM_REV1 00 INDIRECT REGISTER ADDRESSING MODE Continued Register File P
198. ion End of conversion ECO status bit 3 A D conversion speed selection bits 1 2 e operation start bit 0 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADCO ADC7 can be selected dynamically by manipulating the ADCON 4 7 bits And the pins not used for analog input can be used for normal function A D Converter Control Register ADCON Set1 Reset 00H R W AJD input pin selection bits 4 A D conversion Start bit 0000 ADCO i ES 0 Disable operation 0001 ADC1 B COMME 1 Start operation Auto clear 0010 ADC2 is in progress 0011 ADC3 1 A D conversion 0100 ADC4 0101 ADC5 Clock source selection bits 0110 ADC6 00 fxx 16 fosc 8MHz 0111 ADC7 01 fxx 8 fosc 8MHz other values Connected with GND internally 10 fxx 4 fosc 8MHz 11 fxx fosc 2 2 5MHz NOTE Maximum clock input AMHz Figure 17 1 A D Converter Control Register ADCON 17 2 ELECTRONICS S3F84Q5_UM_REV1 00 A D CONVERTER Conversion Data Register High Byte ADDATAH F9H Banko Read only Conversion Data Register Low Byte ADDATAL Set1 Bank0 Read only Figure 17 2 A D Converter Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain
199. is stored in the register pair OOH 01H ELECTRONICS INSTRUCTION SET S3F84Q5_UM_REV1 00 NEXT next NEXT Operation PC lt lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 10 OF Example The following diagram shows one example of how to use the NEXT instruction Before After Address Data Address Data PC 0120 Address 01 PC 0130 44 AddressL 10 Address Data 43 Address Data 43 Address 44 Address L 45 Address 45 Address H 120 130 Routine Memory Memory ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET NOP Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex opc 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 63 INSTRUCTION SET S3F84Q5_UM_REV1 00 OR Logical OR OR Operation Flags Format Examples dst src dst
200. isable watch timer 1 Enable watch timer Buzzer signal selection bits 00 0 5 kHz Watch timer speed selection bits 01 1 kHz 00 Set watch timer interrupt to 1 s 10 2 kHz 01 Set watch timer interrupt to 0 5 s 11 4 kHz 10 Set watch timer interrupt to 0 25 s 11 Set watch timer interrupt to 3 91 ms Figure 18 1 Watch Timer Control Register WTCON 18 2 ELECTRONICS S3F84Q5_UM_REV1 00 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON O Pending Bit WT INT Enable BUZ P2 1 ES WTINT E kHz Enable Disable Frequency Dividing 32 768 kHz Circuit Clock Selector fx Main clock where fx 24 19 MHz 2 Sub clock 32 768 kHz fxt fx 128 fw Watch timer frequency Figure 18 2 Watch Timer Circuit Diagram ELECTRONICS 18 3 S3F84Q5_UM_REV1 00 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F84Q5 has an on chip full flash memory internally instead of masked ROM The flash memory is accessed by LDC instruction and the type of sector erase and a byte programmable flash a user can program the data in the flash memory area any time you want The S8F84Q5 s embedded 16K byte memory has two operating features e User program mode e Tool program mode Refer to the chapter 1 S3F84Q5 Overview ELECTRONICS 19 1 EMBEDDED FLASH MEMORY INTERFACE S3F84Q5_UM_REV1 00 USER PROGRAM MODE This mode supports sector erase byte programming byte read and one
201. ise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register 00H 2AH C 1 RRC gt Register 01H 02H register 02H OBH C 1 In the first example if general register 00 contains the value 55H 01010101B the statement RRC OOH rotates this value bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2 00101010B in destination register OOH The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 77 INSTRUCTION SET S3F84Q5_UM_REV1 00 SB1 Select Bank 1 SB1 Operation BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS regist
202. ister address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO Address 7 These address bits indicate 8 bit 8 bit logical working register address T addressing Register pointer hree low order bits provides five high order bits TTT TTT 4 8 bit physical address Figure 2 14 8 Bit Working Register Addressing 2 18 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES RPO Selects RP1 8 bit address R11 Register 1100 011 form instruction 10101 011 address LD R11 R2 OABH Specifies working register addressing Figure 2 15 8 Bit Working Register Addressing Example ELECTRONICS 2 19 ADDRESS SPACES S3F84Q5_UM_REV1 00 SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3F84Q5 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register ar
203. ister file address register pointer information 5 Interrupt Request Register Polling Read only Cycle nRESET R IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram ELECTRONICS 5 7 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS S3F84Q5_UM_REV1 00 For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 2 Table 5 2 Interrupt Source Control and Data Registers InterruptSource Source Interrupt Level Register s Location s Timer A match capture TACON Timer A overflow TADATA TACNT TINTPND TBCON TBDATA TINTPND TCCON TCDATA TDDATA TDCNT TINTPND PWMCON P2CONH WTCON Timer B match Timer B overflow Timer C match Timer D match Timer D overflow PWM overflow interrupt Watch timer interrupt P1 0 external interrupt P1 1 external interrupt P3 0 external interrupt P3 1 external interrupt P3 2 external interrupt P3 3 external interrupt P3 4 external interrupt P3 5 external interrupt P3 6 external interrupt SIO interrupt P3CONH P3CONL P3INT P3PND SIOCON SIOPS SIODATA UARTCON UARTPND BRDATA UDATA UART Transmit interrupt UART Receive interrup
204. ive address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 register 03H 04H CPIJNER1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 33 INSTR DA Decimal Adjust UCTION SET S3F84Q5_UM_REV1 00 DA dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation
205. l after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes 0000 1000 0111 1111 note note 0110 note 1110 note 1101 0101 0100 1100 0110 note 1110 note 1001 0001 1010 0010 1111 note 0111 note 1011 0011 NOTES Always false Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal 1 0 2 1 2 0 5 0 S 1 V 1 V 0 2 1 2 0 OR V 0 OR V 1 V 0 V 1 O29 ONN ll O C 0 AND Z 0 1 OR 2 1 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 For operations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET INSTRUCTION DESCRIPTIO
206. l converter with 8 input channels and 10 bit resolution One asynchronous UART and one synchronous SIO e One Watch timer for real time operation e High current LED drive I O ports High current output typical 12 mA The S3F84Q5 microcontroller is ideal for use in a wide range of home applications requiring simple timer counter ADC etc They are currently available in 32 pin SOP SDIP 28 pin SOP 30 pin SDIP and 32 ELP 0505 package NOTE The S3F84Q5 is perfectly pin to pin compatible with the SAM88RCRI product 53 9498 9498 ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM8RC CPU core Memory e 528 byte general purpose register RAM e 16K byte internal multi time program memory Full Flash Y Sector size 128 Bytes 10 Years data retention Fast programming time Chip erase 10ms Sector erase 10ms Byte program 30us Y User programmable by LDC instruction Y Endurance 10 000 erase program cycles Y Sector 128 bytes erase available Y Byte programmable External serial programming support Y Expandable OBP On board program sector Oscillation Sources e Crystal or ceramic for main clock 10MHz max e Crystal for sub clock 32 768kHz e clock divider 1 1 1 2 1 8 1 16 Instruction Set e 78 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time e 400 ns at 10 MHz minimum main clock e 122 us at 32 768kHz minimum sub clo
207. lear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 15 1 Serial I O Interface Control Register SIOCON 15 2 ELECTRONICS S3F84Q5_UM_REV1 00 SERIAL I O INTERFACE SIO PRESCALER REGISTER SIOPS The control register for serial I O interface module SIOPS is located at F3H Set1 Banko The value stored in the SIO prescaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock Xin 4 SIOP 1 or external SCK input clock SIO Pre Scaler Registers SIOPS F3H Set1 R W Baud rate XiN A SIOPS 1 Figure 15 2 SIO Pre Scaler Register SIOPS 3 Bit Counter Clear SIOCON 3 SIOCON 0 Pending SIOCON 1 SIOCON 7 Interrupt Enable Shift Clock Source Select SIOCON 4 Edge Select SIOCON 2 Shift Enable SIOCON 5 Mode Select SCK SIOPS F4H CLK SIO Shift Buffer SIODATA 8 Bit z Prescaler Value 1 SIOPS 1 SIOCON 6 LSB MSB First Mode Select Figure 15 3 SIO Functional Block Diagram ELECTRONICS SERIAL I O INTERFACE S3F84Q5_UM_REV1 00 Transmit IRQS N Complete Set SIOCON 3 Figure 15 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 A JC Cs JC Transmit IRQS 5 Complete Set SIOCON 3 Figure 15 5 Serial I O Timing in Tr
208. leared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir opc src dst 3 6 54 R R 55 R IR dst src 3 6 56 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H gt gt AND 01H 02H Register 01H 00H register 02H 03H 01H 25H Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffec
209. llows the CPU to process the next interrupt request ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location fron Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends execute DI restore the IMR to its original value b
210. ncreasing from 0000H Whenever an overflow is occurred an overflow OVF1 interrupt can be generated Although you can use the match or the overflow interrupt in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the T1OUT pin is held to low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to high level for as long as the data value is greater than the counter value One pulse width is equal to 12 2 ELECTRONICS S3F84Q5_UM_REV1 00 16 BIT TIMER 1 TIMER 1 CONTROL REGISTER T1CON You use the TIMER 1 control register T1CON to e Select the TIMER 1 operating mode interval timer capture mode or PWM mode e Select the TIMER 1 input clock frequency e Clear the TIMER 1 counter e Enable the TIMER 1 overflow interrupt e Enable the TIMER 1 match capture interrupt T1CON is located at address Seti Bank1 and is read write addressable using Register addressing mode A reset clears T1CON to OOH This sets TIMER 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all TIMER 1 interrupts You can clear the TIMER 1 counter at any time during normal operation by writing a 1 to T1CON 2 To generate the exact time interval you should write 1 to T1CON 2 and clear appropriate pending bits of the TINTPND 6 register To detect a match capture or overflow interrupt pe
211. nd OEH to TCCON the counter will increment until it reaches 20H At this point the Timer C interrupt request is generated the counter value is cleared and counting resumes and you write the value 10H to TDDATA 0 to TCCON 6 and OEH to TDCON the counter will increment until it reaches 10H At this point TD interrupt request is generated the counter value is cleared and counting resumes ELECTRONICS 13 7 0 S3F84Q5_UM_REV1 00 TCCON 5 4 1 024 512 IXX 8 Comparator TCDATA IXXA y X TDDATA TDONT R TDCON 5 4 TDCON 3 TDCON 7 6 NOTE When TCCON 7 is 0 two 8 bit timer C D Interval mode Clear Figure 13 5 Timer C and D Function Block Diagram 13 8 ELECTRONICS S3F84Q5_UM_REV1 00 TIMER 0 Pulse Width Modulation Mode Timer D Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TDOUT P1 6 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the Timer data register PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH in case of 8 bit PWM mode and then continues incrementing from Although you can use the match signal to generate a Timer D overflow interrupt interrupts are not typically used PWM type applications Instead the pulse at the TDOUT is held to L
212. nding condition when T1INT or T1OVF is disabled the application program should poll the pending bit T1 CON and INTPND register When a 1 is detected a TIMER 1 match capture or overflow interrupt is pending Timer 1 Control Register E8H Bank1 RW Reset Value 00H TE TSTS TS T2 T3 Ts Timer 1 clock source selection bit Timer 1 overflow interrupt 000 fxx 1024 enable bit 001 fxx 0 Disable overflow interrupt 010 fxx 256 1 Enable overflow interrrupt 011 External clock T1CK falling edge 100 fxx 64 Timer 1 match capture interrupt enable bit 101 External clock T1CK rising edge 0 Disable interrupt 110 fxx 8 1 Enable interrrupt 111 Counter stop Timer 1 counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 mode and T1INT can occur NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 TIMER 1 Control Register T1CON ELECTRONICS 12 3 16 1 S3F84Q5_UM_REV1 00 Timer Interrupt Pending Register TINTP ND F1H Setl Bank1 Reset 00H R W Timer A macth capture Timer 1 overflow interrupt pending flag interrupt pending flag 0 Not pending clear pending bit 0 Not pending clear pending bit
213. ndirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode See list of condition codes in Table 6 6 Rn n 2 0 15 Rn b n 2 0 15 b 2 0 7 Rn n 2 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg reg 0 255 n 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where 0 2 14 addr RRp addr range 0 65535 where 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 ELECTRONICS 6 9 INSTRUCTION SET S3F84Q5_UM_REV1 00 Table 6 5 Opcode Quick Reference OPCODE MAP DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb
214. ned by software Pins can also be assigned individually as alternative function pins 2 I O port with bit programmable pins Configurable to input mode push pull output mode Pins can also be assigned individually as alternative function pins 3 I O port with bit programmable pins Configurable to input mode push pull output mode Pins can also be assigned individually as alternative function pins ELECTRONICS 9 1 PORTS 53 8405 UM REV1 00 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all four S8F84Q5 I O port data registers Data registers for ports 0 1 2 and 3 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location R W Port 0 data register PO 224 EOH Seti R W Port 1 data register 1 225 Seti R W Port 2 data register P2 226 E2H Set1 R W Port 3 data register P3 227 E3H Seti R W 9 2 ELECTRONICS S3F84Q5_UM_REV1 00 PORTS PORT 0 Port 0 is 3 bit I O Port that you can use two ways e General purpose I O e Alternative function Port 0 is accessed directly by writing or reading the port 0 data register PO at location EOH Set1 Port 0 Control Register POCON Port 0 pins are configured individually by bit pair settings in three control registers located POCON When you select output mode a p
215. ng register slice 2 0 Not used for the S3F84Q5 4 30 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER SIOCON serial 1 0 Module Control Registers F2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 SIO Shift Clock Selection Bit Interval clock P S Clock 1 External clock SCK 6 Data Direction Control Bit MSB first mode LSB first mode 1 5 Sl Mode Selection Bit Receive only mode 1 Transmit Receive mode 4 Shift Clock Edge Selection Bit Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges 3 Sl Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting 2 Sl Shift Operation Enable Bit Disable shift and clock counter 1 Enable shift and clock counter Interrupt Enable Disable SIO interrupt 1 Enable SIO interrupt 0 SIO Interrupt Pending Bit No interrupt pending Clear pending bit when write 1 Interrupt pending ELECTRONICS 4 3 CONTROL REGISTERS S3F84Q5_UM_REV1 00 SIOPS sio Prescaler Register F3H Set 1 Bank1 0 0 0 0 RESET Value 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Baud rate Input clock fxx SIOPS 1 x 4 or SCK input clock SPH stack Pointer High Byte D8H Set 10 Banko Bit Identifier 7 6 5 4 3 2 0 RESET Value X X X X X X X X Rea
216. nsfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H and 1034H external data memory locations 1033H ODDH 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 RR6 1 R8 R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 57 INSTRUCTION SET S3F84Q5_UM_REV1 00 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src r rr 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of
217. nternally End Of Conversion EOC Status Bit EX A D conversion is in progress A D conversion complete Clock Source Selection Bits e r mmee me O A D Conversion Start Bit lo Disable operation Start operation NOTE Maximum ADC clock input 4MHz ELECTRONICS 4 5 CONTROL REGISTERS S3F84Q5_UM_REV1 00 BTCON Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 4 Watchdog Timer Function Enable Bit fifo 1 Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Code 1 Invalid setting 4 Basic Timer 8 Bit Counter Clear Bit ES No effect Clear the basic timer counter value 0 Basic Timer Divider Clear Bit EN No effect Clear both dividers NOTE When you write a 1 to 0 or BTCON 1 the basic timer counter or basic timer divider is cleared The bit is then cleared automatically to 4 6 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER System Clock Control Register D4H Set 1 RESET Value 0 0 Read Write R W R W 7 5 Not used for the 53 8405 4 3 CPU Clock System Clock Selection Bits note 71 fxx 1 non divided 2 0 Not used for the S3F84Q5 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate v
218. nterrupt disable 1 INT3 falling edge interrupt enable 0 P3 0 INT2 External Interrupt Enable Bit INT2 falling edge interrupt disable 1 INT2 falling edge interrupt enable ELECTRONICS 4 2 CONTROL REGISTERS S3F84Q5_UM_REV1 00 P3PND Port Interrupt Pending Register EFH Set 1 Bank 0 Bit Identifier Reset Value Read Write Addressing Mode 4 26 7 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Register addressing mode only Not used for 53 8405 Port 3 6 INT8 External Interrupt Pending Bit No interrupt pending when read Pending bit clear when write i EX No effect when write Port 3 5 INT7 External Interrupt Pending Bit pending whenread Port 3 4 INT6 External Interrupt Pending Bit No interrupt pending when read Pending bit clear when write i i Interrupt is pending when read No effect when write ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER P3PND Port Interrupt Pending Register EFH Set 1 Bank 0 Bit Identifier Reset Value Read Write Addressing Mode ELECTRONICS 7 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Register addressing mode only Port 3 3 INT5 External Interrupt Pending Bit No interrupt pending when read Pending bit clear when write i i Interrupt is pending when read No effect when write Port 3 2 INT4 External Interrupt Pending Bit No interru
219. nto the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before After Data Address Data IP 0052 Address Data Address Data PC 0060 50 PCL old 60 60 Main 51 00 0022 140 Exit 2 00 Data Memory 22 Data Memory Stack Stack ELECTRONICS 6 43 INSTRUCTION SET S3F84Q5_UM_REV1 00 IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation In application programs a IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 6 Example The instruction IDLE stops the CPU clock but not the system clock NOP NOP NOP 6 44 ELECTRONICS S3F84Q5_UM_REV1 00 INC Increment INC Operation Flags Format Examples dst dst lt dst 1 The contents of the
220. o a known operating status To ensure correct start up the user should take that reset signal is not released before the level is sufficient to allow MCU operation at the chosen frequency The RESETB pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms 2 fxx fxx 10 MHz When a reset occurs during normal operation with both Vpp and RESETB at High level the signal at the RESETB pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3F84Q5 has built in low voltage reset circuit that allows detection of power voltage drop of external Vpp input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset includes an analog comparator and Vref circuit The value of a detection voltage is set internally by hardware The on chip Low Voltage Reset features static reset when supply voltage
221. oating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations NOP NOP NOP ELECTRONICS 6 83 INSTRUCTION SET S3F84Q5_UM_REV1 00 SU B subtract SUB Operation Flags Format Examples 6 84 dst src dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 22 r r SIC 6 23 r Ir src dst 3 6 24 R R 25 R IR dst src 3 6 26 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH SUB R1 R2 R1 OFH R2 03H SUB R1 R2 R1 08H R2 SUB 01H 02H
222. oji 6 bit PWM mode OVF interrupt can occur 7 bit PWM mode OVF interrupt can occur 8 bit PWM mode OVF interrupt can occur 5 4 Timer Clock Selection Bits S opipa SSS x NN 3 Timer Counter Clear Bit 3 No effect 1 Clear the timer D counter when write 2 Timer D Count Enable Bit Disable count operation 3 1 Enable count operation Timer match Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer overflow interrupt enable bit Disable interrupt 1 Enable interrupt ELECTRONICS 4 3 CONTROL REGISTERS S3F84Q5_UM_REV1 00 TINTPND Interrupt Pending Register F1H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 Timer 1 Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 6 Timer 1 Match Capiure Interrupt Pending Bit ES No interrupt pending Clear pending bit when write Interrupt pending 5 Timer D Overflow Interrupt Pending Bit EN No interrupt pending Clear pending bit when write Interrupt pending 4 Timer Match Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 3 Timer B Overflow Interrupt Pending Bit E No interrupt pending Clear pending bit when write Interrupt pending 2 Timer B Match Capture Interrupt Pending Bit No interrupt pending
223. on in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences Watch timer has the following functional components Real Time and Watch Time Measurement e Using a Main Clock Source or Sub clock e O pin for Buzzer Output Frequency Generator P2 1 BUZ e Timing Tests in High Speed Mode e Watch timer overflow interrupt IRQ3 vector DEH generation e Watch timer control register WTCON set 1 bank 1 F3H read write ELECTRONICS 18 1 WATCH S3F84Q5_UM_REV1 00 WATCH TIMER CONTROL REGISTER WTCON The watch timer control register WTCON is used to select the watch timer interrupt time and Buzzer signal to enable or disable the watch timer function It is located in set 1 bank 1 at address F3H and is read write addressable using register addressing mode A reset clears WTCON to OOH This disables the watch timer So if you want to use the watch timer you must write appropriate value to WTCON Watch Timer Control Register WTCON F3H Set 1 Bank 1 Reset 00H R W Watch timer clock selection bit Watch timer interrupt pending bit 0 Select main clock divided by 2 fx 128 0 Interrupt request is not pending 1 Select Sub clock fxt Clear pending bit when write 0 1 Interrupt request is pending Watch timer INT Enable Disable bit 0 Disable watch timer INT 1 Enable watch timer INT Watch timer Enable Disable bit 0 D
224. ow level as long as the reference data value is less than or equal to x the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to to x 256 in case of 8 bit PWM mode is selected see Figure 13 6 5 4 8 Bit OVF TDCON 6 7 TINTPND 5 Cl Up Counter R ear TDCON 3 Read Only TDCON O TDCON 6 7 TDOUT PWM Interval TINTPND 4 Pending Bit TDCON 1 Selected TDOVF TDCON 3 NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 13 6 Timer D PWM Function Block Diagram ELECTRONICS 13 9 S3F84Q5_UM_REV1 00 UART UART OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes e Shift Register with baud rate of fxx 16 x 8bit BRDATA 1 e 8 bit UART mode variable baud rate fxx 16 x 8bit BRDATA 1 e 9 bit UART mode fxx 16 e 9 bit UART mode variable baud rate fxx 16 x 8bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register UDATA is at address FFH Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of
225. performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 06 0 0 0 9 1 0 3 06 0 ADD 0 0 0 9 60 1 ADC 0 9 0 66 1 0 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 0 0 9 AO 60 1 1 6 1 6 9A 66 1 Flags Set if there was carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 40 R 41 6 34 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET DA Decimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD Ri1 RO C lt lt 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 R1 lt 3CH 06 If addition is performed using the BCD values 15 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 001
226. plement Under Mask TCM Operation Flags Format Examples 6 86 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir src dst 3 6 64 R R 65 R IR dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H registerOOH 2BH register 01H 02H and register 02 23H TCM 0C7H R1 02H Z 1 TCM RO0 R1 gt RO 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H gt Register 00H 2BH register 01H 02H Z 1 TCM 00H 01H Register OOH 2BH register 01H O2H register 02H 23H Z 1 TCM 00H 34 gt Register 00 2BH Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO0 R1 tests bit one in the destination register for a 1 value Because the
227. processing for interrupts with either type of pending condition clear function by hardware or by software PROGRAMMING GUIDELINES Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends Please refer to IRET instruction in chapter 6 ELECTRONICS 5 17 S3F84Q5_UM_REV1 00 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8RC instruction set is specifically designed to support the large register files that are typical of most 5 8 microcontrollers There 78 instructions The powerful data manipulation capabilities and features of the instruction set include e A full complement of 8 bit arithmetic and logic operations including multiply and divide e special instructions I O control data registers are mapped directly into the register file e Decimal adjustment included in binary coded decimal BCD operations e 16 bit word data can be incremented and decremented e Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bit
228. pt pending when read lo Pending bit clear when write Interrupt is pending when read No effect when write Port 3 1 INT3 External Interrupt Pending Bit o NomemppedngWhenea Pending bitear menw Port 3 0 INT2 External Interrupt Pending Bit No interrupt pending when read Pending bit clear when write i i Interrupt is pending when read No effect when write 4 27 CONTROL REGISTERS S3F84Q5_UM_REV1 00 PP Register Page Pointer DFH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits Fo 0 bestnaion pageo Fo o Lo bestnaion paget Other values Don t care 3 0 Source Register Page Selection Bits 71 9191911 7 NOTE Inthe S3F84Q5 microcontroller the internal register file is configured as two pages Page 0 Page 1 4 28 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER PWMCON Contro Register FOH Seti BankO RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 PWM Input Clock Selection Bit 6 o O o t fises o O afo jfooB 0 0 5 4 Not used for 53 8405 3 PWM Counter Clear Bit No effect 1 Clear 14 bit up counter when write 2 P M Counter Enable Bit Stop counter 1 Start
229. pt pending register TINTPND RW jojo ojojo ojojo Location F2H is not mapped Watch Timer Control Register RW Flash memory control register FMCON RW Flash memory user programming enable FMUSR FSH R W register Flash memory sector address register FMSECH F6H high byte Flash memory sector address register FMSECL F7H low byte Locations F8H FFH are not mapped NOTE Not mapped or not used x Undefined ELECTRONICS 8 7 S3F84Q5_UM_REV1 00 PORTS I O PORTS OVERVIEW The S3F84Q5 microcontroller has four bit programmable ports PO P3 The port 0 and 3 are 3 bit 7 bits ports and the others are 8 bit ports This gives a total of 22 24 26 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special instructions are required Table 9 1 gives you a general overview of the S3F84Q5 I O port functions Table 9 1 S3F84Q5 Port Configuration Overview Port Configuration Options 0 port with bit programmable pins Configurable to input or push pull output mode Pull up resistors can be assigned by software Pins can also be assigned individually as alternative function pins 1 I O port with bit programmable pins Configurable to input or push pull output mode Pull up resistors can be assig
230. put mode with pull up Ea Push pull output Open drain Output 3 2 P0 1 TxD ofo mam 2 Co 1 input ode wit pulp a fo Push puloutpat 1 0 P0 0 RxD Input mode RxD input ojja Input mode with pull up RxD input 42 Push pull output Alternative function RxD output NOTE When users use Port 0 users must be care of the pull up resistance status ELECTRONICS 4 17 CONTROL REGISTERS S3F84Q5_UM_REV1 00 P1CONH Port 1 Control Register High Byte E8H Set 1 Bank 0 Bit Identifier RESET Value Read Write 7 6 3 2 1 0 4 18 _ 5 4 2 4 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W P1 7 ADC7 ESTIS Push pull output Alternative function ADC7 input P1 6 ADC6 TDOUT o r MemaweundonTDOUTmwa CS EKIGO T P1 5 ADC5 0 mpamode Fo r mumwewhpdu Pio P1 4 ADCA o o mumde CAKET Push pull output Alternative function ADC4 input ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER P1CONL Port 1 Control Register Low Byte E9H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 P1 3 ADC3 ofo mam Co input mode wit pup Push pull output Alternative function ADC3 input 5 4 P1 2 ADC2 a ofero 3 2 P1 1 ADC1 INT1
231. qual to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the timer A capture input selection bit in the Port 2 low byte control register P2CONL When P2CONL 5 4 is 00 and 01 the TACAP input or normal input is selected When P2CONL 5 4 is set to 10 and 11 output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS S3F84Q5 UM REV1 00 8 BIT TIMER A B TIMER A CONTROL REGISTER TACON You use the timer A control register TACON e Select the timer A operating mode interval timer capture mode and PWM mode e Select the timer A input clock frequency e Clear the timer A counter TACNT e Enable the timer A overflow interrupt or timer A match capture inte
232. r 8 7 9 1 SSF84Q5 Port Configuration 200 1 4 00 404 2 9 1 9 2 Port Data Register 9 2 13 1 PWM Control and Data 13 2 13 2 PWM output stretch Values for Extension Data Register PWMDATAL 1 0 13 3 14 1 Commonly Used Baud Rates Generated by 8 bit BRDATA 14 5 16 1 PWM Control and Data 16 2 16 2 PWM output stretch Values for Extension 16 3 19 1 ISP Secor SIZG iiiter diei tte E diem a d etd dave e de bee eed de pe dta 19 6 19 2 Reset Vector Address uc rt etr une RA 19 6 53 8405 UM REV 1 00 MICROCONTROLLER xv List of Tables Table Title Page Number Number 21 1 Absolute Maximum 21 2 21 2 D C Electrical Characteristics 21 3 21 3 Electrical Characteristics 21 4 21 4 Oscillator Characteristics 5 21 6 21 5 Oscillation Stabilization 0 21 6 21 6 Data Retention Supply Voltage in Stop Mode 21 7 21 7
233. r B Data Register Read Write Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bits are located at TINTPND register Figure 11 5 Simplified Timer B Functional Block Diagram 11 6 ELECTRONICS S3F84Q5_UM_REV1 00 Timer B Control Register TBCON E5H Setl 1 R W Reset 00H T2 gt Timer B input clock selection bit Timer B start stop bit 00 fxx 8 0 Stop timer B 01 fxx 4 1 Starttimer B 10 fxx 2 Timer match interrupt Not used enable bit 0 Disable interrupt 1 Enable interrrupt Timer B overflow interrupt enable bit Timer B operating mode selection bit 0 Disable overflow interrupt 0 Interval mode TBOUT mode 1 Enable overflow interrrupt 1 PWM mode OVF interrupt and match interrupt can occur Timer B counter clear bit 0 No effect 1 Clear the timer B counter when write NOTE When th counter clear bit 3 is set the 8 bit counter is cleared and italso is cleared automatically Figure 11 6 Timer B Control Register TBCON Timer B Data Register TBDATA E7H Set1 Bank1 R W Reset Value FFh 8 BIT TIMER A B Figure 11 7 Timer B DATA Registers TBDATA ELECTRONICS S3F84Q5_UM_REV1 00 16 BIT TIMER 1 16 BIT TIMER 1 OVERVIEW The S3F84Q5 has two 16 bit timer counters The 16 bit timer 1 is a 16 bit general purpose timer counter Timer 1 has three operating modes one of which you select
234. re Pins can also be assigned individually as alternative function pins Test signal input pin for factory use only must be connected to in normal mode Pull down register is connected internally Power supply input pin ELECTRONICS 1 7 PRODUCT OVERVIEW SF84Q5_UM_REV1 00 Table 1 2 Pin Descriptions of 28 SOP 32 SOP 32 SDIP 30 SDIP Pin Pin Pin Description Circuit Pin Shared Names Type Type No Functions areas 2428720 A D converter analog input channels 1 2 P1 0 P1 7 2 4 1 1 A D converter reference voltage 8 10 9 Serial data RXD for receive input and 5 transmit output mode 0 Serial data TXD pin for transmit output and shift clock output mode 0 P1 0 P1 1 P3 0 P3 2 P3 3 P3 6 TAOUT LESS 120718 1921720 Timer counter 1 external capture input 23 27 25 Timer counter B match output or 20 22 21 P2 3 Timer counter B PWM output Timer counter D match output or 15 17 16 P1 6 Timer counter D PWM output ADC6 Timer counter 1 PWM output Timer counter TACK TACAP T1OUT T1CK T1CAP TBOUT TDOUT RESETB external clock input Timer counter A match output or 17 19 18 P2 0 Timer counter A PWM output AA AA gt gt ea BE INTO INT1 External interrupts INT4 INT2 INT5 8 Le 1 1 1 1 2 2 1 1 1 1 1 1 1
235. re affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb ro NOTE Inthe second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register 00H 05H LDB R0 00H 2 gt RO LDB 00H 0 R0 gt RO 07H register 05H 06H register 04H In the first example destination working register RO contains the value 06H and the source general register 00H the value 05H The statement LD R0 00H 2 loads the bit two value of the register into bit zero of the RO register leaving the value 07H in register RO In the second example is the destination register The statement LD 00H 0 R0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register 00H ELECTRONICS S3F84Q5 0 M_REV1 00 INSTRUCTION SET LDC LDE Load Memory LDC LDE Operation Flags Format dst src dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory and odd an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 1 opo dst sro 2 1
236. rking register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the 53 84 5 the set 2 address range COH FFH is accessible on page 0 only 53 8405 has implemented only page 0 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 location In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations 2 8 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes of the S3F84Q5 s 256 byte register page 0 is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the register page pointer PP to the appropriate source and destination values Set 1 Bank 0 Bank 1 CPU and system control General purpose ia Peripheral and LCD data register Figure 2 5 Set 1 Set 2 Prime Area Register Map ELECTRONICS 2 9
237. rocessing Enable fast interrupt processing 0 Global Interrupt Enable Bit 4 EN Disable all interrupt processing Enable all interrupt processing NOTES 1 Because an external interface is not implemented SYM 7 must always be 0 2 Youcan select only one interrupt level at a time for fast interrupt processing 3 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 4 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O 4 34 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER T1CON Timer 1 Control Register E8H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 Input Clock Selection Bits tex Non dvdey of ofws o 1 0 1 exteralclockrisingedge 0000 SOS 4 3 Timer 1 Operating Mode Selection Bits IES Interval mode oja Capture mode Capture on rising edge OVF can occur 1 Capture mode Capture on falling edge OVF can occur 0 1 PWM mode 2 Timer 1 Counter Clear Bit 3 No effect 1 Clear the timer 1 counter Auto clear bit 1 Timer 1 Match Capiure Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1 Overflow Interrupt Enable Disable o
238. rogram Memory Example REGISTER Instruction dst eo References OPCODE Points to Program Register Pair 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File 1 5 RPO or RPO Selected RP points Program Memory to start fo working register block ds Working Register Point to the ADDRESS Address Working Register tof MENFE Value used in OPERAND panes LAE Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3F84Q5_UM_REV1 00 INDIRECT REGISTER ADDRESSING MODE Concluded Register File MSB Points to RPO or RPO or Selected RP points to start of working register oe ee Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair E NN CERE References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 Ex
239. rrupt e Timer A start stop e Clear Timer A match capture interrupt pending conditions TACON is located at address E4H Set1 Bank1 and is read write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all Timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 You can start Timer A counter by writing a 1 to 0 The timer A overflow interrupt TAOVF has the vector address EOH When a timer A overflow interrupt occurs and is serviced by the CPU and the pending condition can be cleared by both software and hardware To enable the timer A match capture interrupt you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and TINTPND 0 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit Timer A Control Register TACON E4H Set1 1 R W Reset Timer A input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer A 01 fxx 256 1 Start timer A 10 fxx 64 11 External clock TACK Timer A match capture interrupt enable bit Timer A operating mode selection bit 0 Disable interrupt 00 Interval mode TAOUT mod
240. rupt pending Timer D macth capture interrupt pending flag 0 Not pending clear pending bit 1 Interrupt pending Figure 11 2 Timer interrupts Pending Register TINTPND Timer A Data Register TADATA E6H 1 R W Reset Value FFh Figure 11 3 Timer A DATA Register TADATA 11 4 ELECTRONICS S3F84Q5 UM REV1 00 8 BIT TIMER A B BLOCK DIAGRAM TACON 2 TAOVF A Overflow 1 7 6 Data Bus gt Pending TINTPND 1 fxx 1024 fxx 256 8 bit Up Counter TACON 3 X fxx 64 gt Read Only TINTPND O Timer A Buffer Reg Overflow In PWM mode TAOVE High level when data gt counter TACON 5 4 Low level when data lt counter Timer A Data Register Read Write 5 4 Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bits are located at TINTPND register Figure 11 4 Simplified timer A Functional Block Diagram ELECTRONICS 8 BIT TIMER S3F84Q5_UM_REV1 00 8 BIT TIMER B OVERVIEW The S3F84Q5 micro controller has an 8 bit counter called timer B 2 Overflow 7 6 Data Bus Pending TINTPND 3 8 bit Up Counter C TBCON 3 Read Only TBCON 1 8 bit Comparator TINTPND 2 Timer B Buffer Reg Overii verflow In PWM mode High level when data counter Low level when data counter TBCON 4 Time
241. rwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H 03H ADD 01H 425H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3F84Q5_UM_REV1 00 AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 c
242. s a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence ae sce Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the and status flags setting SYM O to 1 It a
243. s counting from the retained count value When there is a need to clear the counter you set PWMCON 3 to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are Fxx 256 Fxx 64 Fxx 8 Fxx 1 FUNCTION DESCRIPTION PWM The 14 bit PWM circuits have the following components 8 bit comparator and extension cycle circuit 8 bit reference data registers PWMDATA e 6 bit extension data registers PWMEX e PWM output pins P2 7 PWM PWM counter The PWM counter is a 14 bit incrementing counter comprised of a lower 8 bit counter and an upper 6 bit counter To determine the PWM module s base operating frequency the lower byte counter is compared to the PWM data register value In order to achieve higher resolutions the six bits of the upper counter can be used to modulate the stretch cycle To control the stretching of the PWM output duty cycle at specific intervals the 6 bit extended counter value is compared with the 6 bit value bits 7 2 that you write to the module s extension register ELECTRONICS 16 1 14 S3F84Q5_UM_REV1 00 PWM data and extension registers PWM duty data registers located in the address E4H Set 1 Bank 0 determine the output value generated by the 14 bit PWM circuit 68 bit data register PWMDATA e 6 bit extension registers PWMEX which only bits 7 2 are used To program the required PWM output you load the appropriate initialization value
244. s into the 8 bit data registers PWMDATA and the 6 bit extension registers PWMEX To start the PWM counter or to resume counting you set PWMCON 2 1 A reset operation disables all PWM output The current counter value is retained when the counter stops When the counter starts counting resumes at the retained value PWM clock rate The timing characteristic of PWM output is based on the f clock frequency The PWM counter clock value is determined by the setting of PWMCON 6 7 Table 16 1 PWM Control and Data Registers PWM data registers PWMDATA Set1 8 bit PWM basic cycle frame value PWMEX Seti 6 bit extension stretch value PWM control registers PWMCON FOH BankO PWM counter stop start resume and fxx clock settings PWM function Description The PWM output signal toggles to Low level whenever the lower 8 bit counter matches the reference value stored in the module s data register PWMDATA If the value in the PWMDATA register is not zero an overflow of the lower counter causes the PWM output to toggle to High level In this way the reference value written to the data register determines the module s base duty cycle The value in the 6 bit extension counter is compared with the extension settings in the 6 bit extension data register PWMEX This 6 bit extension counter value together with extension logic and the PWM module s extension register is then used to stretch the d
245. s within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src S3F84Q5_UM_REV1 00 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pr
246. service routine can detect a pending condition of TCINT by the software and execute it s sub routine When this case is used the TCINT pending bit must be cleared by the application sub routine by writing a 0 to the TCCON 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the timer 0 reference data registers TCDATA and TDDATA The match signal generates a timer 0 match interrupt and clears the counter If for example you write the value 32H and 10H to TCDATA and TDDATA respectively and 8EH to TCCON the counter will increment until it reaches 3210H At this point the timer 0 interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 13 1 0 S3F84Q5_UM_REV1 00 Timer 0 Control Register TCCON You use the timer 0 control register TCCON to e Enable the timer 0 operating interval timer e Select the timer 0 input clock frequency e Clear the timer 0 counter e Enable the timer 0 interrupt e Clear timer 0 interrupt pending conditions TCCON is located at address EOH Set1 Bank1 and is read write addressable using register addressing mode A reset clears TCCON to This sets timer 0 to disable interval timer mode selects an input clock frequency of fxx 1024 and disables timer 0 interrupt You can clear the timer 0 counter at any time during normal operation by writing a 1 to TCCON 3 To enable the
247. ster P mw Port 3 Data Register Ps e rw data register PWMDATA em rw extension data register Pwmex rw 0 0 0 0 0 0 Port 0 control register rw Pr interrupt control register Pur ew o o ojojo o Port 1 control High register rw Port 1 control Low register Picon RW Port 2 control High register ean mw Port 2 control Low register Pecon rw Port 3 control High register ecn rw Port control Low register PSCON RW P3 interrupt control register rw P3 interrupt pending register rw PWM control register PWMCON rw Jo o ojojojojo o Location F1H is not mapped Serial control register SIO pre scalar register SIO data register UART control register UART pending register aneno rw convener aata oye R convener aata registertowbyte x x
248. ster F4H 5H F6H F7H F8H UART pending register UART Baud rate data register UART data register UDATA F8H ND converter data regisihigh bye ADDATAH R x x x x x x x x AID converter dataregstortow byte ADDaTAL FAM R x x ND convertrcontrolregster AW olololololololo Location FCH is not mapped Basic timer counter Bront FDH jo o ojojojojo o Location FEH is not mapped Imempiymgse PR rm NOTE Not mapped or not used x Undefined FSH FAH UART control register 8 6 ELECTRONICS S3F84Q5_UM_REV1 00 RESET and POWER DOWN Table 8 3 S3F84Q5 Bank1 Registers Values after RESET 5 Hex Timer control register RW Timer Dcontrolregister RW Timer control register ESH Timer 1 control register TiCON RW Timer counter Timer D counter R Timer A counter TACNT ew R j x x x x x x x x Timer B counter Tont en R x x x x x x x x Timer t counter high nonm x x x x x x x x Timer Interru
249. t Timer 1 match capture Timer 1 overflow T1DATAH T1DATAL T1CNTH T1CNTL E4H BANK1 E6H BANK1 EAH BANK1 F1H BANK1 E5H BANK1 E7H BANK1 EBH BANK1 F1H BANK1 EOH BANK1 E2H BANK1 E8H BANK1 E1H BANK1 BANK1 E9H BANK1 F1H BANK1 EDH BANKO EAH BANKO EFH BANK1 BANK1 EEH BANK1 EFH BANK1 ECH BANK1 EDH BANK1 P1INT E7H BANKO P1CONL E9H BANKO ECH BANKO EDH BANKO EEH BANKO EFH BANKO F2H BANKO F3H BANKO BANKO F5H BANKO F6H BANKO F7H BANKO F8H BANKO NOTE If an interrupt is un masked Enable interrupt level in the IMR register DI instruction should be executed before clearing the pending bit or changing the enable bit of the corresponding interrupt 5 8 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE SYSTEM MODE REGISTER SYM The system mode register SYM DEH Set1 is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SY
250. t ete tale hia 5 16 Procedure for Initiating Fast 5 17 East Imerr pt Service ROUNE uices cicer a de ege De Rag 5 17 Relationship to Interrupt Pending Bit 5 17 Programming Guidelines 5 17 Chapter 6 Instruction Set OVOIVIOW bti tei tentat et te t co eate ettet pt oss 6 1 setenta edu eiui i d id 6 1 Register Addressing en ein Dead e ec tee b ae tr i Ded un 6 1 Addressing MOGESS areis te UMS 6 1 Flags Register FELAGS irti see chee aide Al ati tie baie tite bat fs 6 6 Flag Descriptions oen ue queue n 6 7 Instr ction Set Notation ioter e teet ea S cabe ie Pie trt eda carter eas 6 8 CONCITION E 6 12 Instruction Descriptions oid eet eene t pee d cn da 6 13 vi S3F84Q5 UM REV 1 00 MICROCONTROLLER Table of Contents Continued Part Hardware Descriptions Chapter 7 Clock Circuit Overview System Clock Circuit Main Oscillator Circuits Sub Oscillator Circuits Clock Status During Power Down Modes System Clock Control Register CLKCON sssssssssssssssseeee eene entere enne en nennen nin Main Subsystem Oscillator Selection OSCCON Switching the CPU Clock Chapter 8 RESET and Power Down System Reset oie t Hoe td Hoi
251. t if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb 0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 00000011B BXOR R1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3F84Q5_UM_REV1 00 CALL Call Procedure CALL dst Operation SP lt SP 1 QSP lt PCL SP lt SP 1 QSP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET
252. t mode many different selections are available e Input mode e Push pull output mode e Alternative function External Interrupt INTO INT1 e Alternative function Timer D output TDOUT e Alternative function ADC input mode ADCO ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 e Alternative function XTn by smart option ELECTRONICS 9 5 PORTS S3F84Q5_UM_REV1 00 Port 1 Control Register High Byte P1CONH E8H Set1 R W Reset value 00H P1 7 ADC7 ADC6 ADC5 ADC4 TDOUT 7 6 bit P 1 7 ADC7 Input mode Input mode with pull up Push pull output Alternative function ADC7 input Input mode Alternative function TDOUT mode Push pull output Alternative function ADC6 input Input mode Input mode with pull up Push pull output Alternative function ADC5 input Input mode Input mode with pull up Push pull output Alternative function ADC4 input Figure 9 2 Port 1 High Byte Control Register P1CONH 9 6 ELECTRONICS S3F84Q5_UM_REV1 00 ELECTRONICS PORTS Port 1 Control Register Low Byte P1CONL E9H Set1 R W Reset value 00H ADC3 ADC2 ADC1 ADCO INT1 INTO 7 6 bit P 1 3 ADC3 Input mode Input mode with pull up Push pull output Alternative function ADC3 input Input mode Input mode with pull up Push pull output Alternative function ADC2 input 13 2 bit P 1 1 ADC 1 INT1 Input mode INT1 input Input mode with pull up IN
253. table 23 3 to meet the current version of 53 84 5 target board Preface The S3F84Q5 Microcontroller User s Manual is designed for application designers and programmers who are using the S3F84Q5 microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to 53 8405 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to
254. tatement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 Source This leaves the value 07H in register 01H ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF Operation dst src b If src b is 0 then PC lt dst The specified bit within the source operand is tested If it is a the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed Flags No flags are affected Format Example Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F84Q5_UM_REV1 00 BTJRT sit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1
255. ted Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb 0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register with the bit O value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F84Q5_UM_REV1 00 BCP Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison C Unaffected Z Set if the two bits are the same cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB addr
256. ternal data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F84Q5_UM_REV1 00 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or Value used in
257. terrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled InterruptRequestRegister IRQ DCH Setl Read only Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F84Q5_UM_REV1 00 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and ex
258. the UART is called UARTCON at address F5H Seti Banko It has the following control functions e Operating mode and baud rate selection e Multiprocessor communication and interrupt control e Serial receive enable disable control 9th data bit location for transmit and receive operations mode 2 e UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON UART Control Register UARTCON F5H Set1 R W Reset Value OOH er er ve Tr ne Te Operating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication Received interrupt enable bit enable bit for modes 2 and 3 only 0 Disable 0 Disable 1 Enable 1 Enable Serial data receive enable bit Location of the 9th data bit that was 0 Disable received UART mode 2 or 3 0 or 1 1 Enable Location of the 9th data bit to be transmitted in UART mode 2 or 3 0 or 1 MS1 MSO Mode Description Baud Rate Shift register fxx 16 x BRDATA 1 8 bit UART fxx 16 x BRDATA 1 9 bit UART fxx 16 9 bit UART fxx 16 x BRDATA 1 NOTES 1 In mode 2 or 3 if the UARTCON 5 bitis set to 1 then the receive interrupt will not be activated if the received 9th data bitis 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated i
259. then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 0 2 descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit ELECTRONICS 4 4 CONTROL REGISTERS S3F84Q5_UM_REV1 00 UARTPND uaRT Pending and Parity Control F6H Set 1 Bank 0 RESET Value 0 0 Read Write R W R W 7 3 Not used for the SSF84Q5 E UART receive interrupt pending flag Not pending ES Clear pending bit when write Interrupt pending 0 UART transmit interrupt pending flag Clear pending bit when write Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for LDB when manipulating UARTPND values 4 42 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER WTCON watch Timer Control Register F3H Set 1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 Watch Timer Clock Selection Bit Select main clock divided by 27 fx 128 1 Select sub clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt 1 Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 0 0 5 kHz 3 2 Watch Timer Speed Selection Bits
260. thmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir src dst 3 6 14 R R 6 15 R IR dst src 3 6 16 R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H and register OAH R1 R2 gt R1 14H R2 03H R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H 01H 02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET ADD ADD dst src Operation dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared othe
261. timer 1 match interrupt and clears the counter Capture Mode In capture mode for Timer 1 a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the T1 data register T1 DATAH L for rising edge or falling edge You can select rising or falling edges to trigger this operation Timer 1 also gives you capture input source the signal edge at the T1CAP pin You select the capture input by setting the capture input selection bit in the port 2 control register 2 Both kinds of timer 1 interrupts T1OVF can be used in capture mode the timer 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 capture interrupt is generated whenever the counter value is loaded into the T1 data register T1 DATAH L By reading the captured data value in T1DATAH L and assuming a specific value for the timer 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP pin PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 data register In PWM mode however the match signal does not clear the counter but can generate a match interrupt The counter runs continuously overflowing at FFFFH and then continuous i
262. tion location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 81 IR Given RO 12H R1 R2 register OFH and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS 6 37 INSTRUCTION SET S3F84Q5_UM_REV1 00 DI Disable Interrupts DI Operation SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while int
263. to the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H register 4 SPH and SPL OOH PUSH 40H gt Register 40H stack register OFFH 4FH SPH OFFH SPL PUSH 40H Register 40H register 4FH stack register SPH SPL In the first example if the stack pointer contains the value 0000 and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F84Q5_UM_REV1 00 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given Register 00H 03H register 01H 05H
264. tor stop and wake up functions e Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 e System clock control register CLKCON e Oscillator control register OSCCON and STOP control register STOPCON CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx main clock fxt sub clock fxx selected system clock ELECTRONICS 7 1 CLOCK CIRCUIT MAIN OSCILLATOR CIRCUITS XIN CI XOUT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx S3F84Q5_UM_REV1 00 SUB OSCILLATOR CIRCUITS 32 768 kHz Figure 7 3 Crystal Ceramic Oscillator fxt XTIN XTOUT Figure 7 4 External Oscillator fxt ELECTRONICS S3F84Q5_UM_REV1 00 CLOCK CIRCUIT CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and idle mode affect the system clock as follows e n Stop mode the main oscillator is halted Stop mode is released and the oscillator started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock e Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Main System Sub
265. tructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are e Register R e Indirect Register IR e Indexed X e Direct Address DA e Indirect Address 1 e Relative Address RA e Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3F84Q5_UM_REV1 00 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 3 2 Program Memory Register File 8 bit Register File Address dst gt OPERAND Point to One DEGODE Register in Register One Operand File Instruction Value used Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RPO or RP1 6 Selected RP points to start of working Program Memory PEED register orking Register dst block OPCODE Po
266. u Pio 1 0 P2 4 T1CK Fo Input mode T1CK input Input mode with pull up 1 input 3 Push pulloutput 00 2 ELECTRONICS 4 21 CONTROL REGISTERS S3F84Q5_UM_REV1 00 P2CONL Port 2 Control Register Low Byte EBH Set 1 Bank 0 Bit Identifier RESET Value Read Write 7 6 1 0 4 22 _ 5 4 3 2 4 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W P2 3 TBOUT ofo mame Fo t mumodewnpuip EXE Push pull output Alternative function TBOUT signal output P2 2 TACAP Co o mamme AGREE f i wih E P2 1 TACK BUZ 0 f i wit a oferon P2 0 TAOUT of ofm oo o inputmodewinpubup Push pull output Alternative function TAOUT signal output ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER P3CONH Port 3 Control Register High Byte ECH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W 7 6 Not used for S3F84Q5 5 4 P3 6 INT8 Input mode INT8 falling edge interrupt 1 Input mode with pull up INT8 falling edge interrupt i Push pull output Open drain output 3 2 P3 5 INT7 Input mode INT7 falling edge interrupt Input mode with pull up INT7 falling edge interrupt 1 Push pull output Open
267. ured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea Box 37 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page http www samsung com Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR Samsung Electronics LSI Development Group Gi Heung South Korea PRODUCT NAME S3F84Q5 8 bit CMOS Microcontroller DOCUMENT NAME S3F84Q5 User s Manual Revision 1 00 DOCUMENT NUMBER 21 S3 F84Q5 122007 EFFECTIVE DATE December 2007 DIRECTIONS Revision 1 00 REVISION HISTORY Preliminary Spec for internal release only NP l Aug 2006 REVISION DESCRIPTIONS FOR REVISION 1 00 Chapter Subjects Major changes comparing with last version Chapter Name jects Maj g paring 1 Overview 1 2 1 Changed operation voltage 1 10MHz from 4 0 5 5V to 3 0 5 5V also made the corresponding change in chapter 20 electrical Data 2 Changed one of the LVR levels from 2 3V to 2 2V also made the corresponding change in chapter 20 electrical Data 3 Added one more package 32 pin ELP also made the corresponding change in chapter 22 mechanical data 5 Interrupt 5 17 Added one sentence Please refer to IRET instruction in chapter 6 Memory Interface 20 LVR All Pages The whole chapter was added in V1 0 23 Tools 23 3 Redrew figure 23 2 and table 23 2 and
268. ush pull or an open drain circuit is configured Many different selections are available e Input mode e Output mode Push pull or Open drain e Alternative function UART module TXD RXD e Alternative function RESETB configured by smart option ELECTRONICS 9 3 PORTS 9 4 S3F84Q5_UM_REV1 00 Port 0 Control Register POCON E6H Set1 BankO R W Reset value 00H Not used XX Not used for 53 8405 5 4 bit P0 2 Input mode Input mode with pull up Push pull output Open drain Output 3 2 bit PO 1 TxD Input mode Input mode with pull up Push pull output Alternative function TxD 1 0 bit PO 0 RxD Input mode RxD input Input mode with pull up RxD input Push pull output Alternative function RxD output When users use Port 0 users must be care of the pull up resistance status register value Figure 9 1 Port 0 Control Register POCON ELECTRONICS S3F84Q5_UM_REV1 00 PORTS PORT 1 Port 1 is an 8 bit I O port that you can use two ways e General purpose I O e Alternative function Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H Seti Banko Port 1 Control Register P CONH P1CONL Port 1 pins are configured individually by bit pair settings in three control registers located P1CONL low byte E9H Set1 and P1CONH high byte Set1 When you select output mode a push pull circuit is configured In inpu
269. uty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles see Table 16 2 If for example the value in the extension register is the 32nd cycle will be one pulse longer than the other 255 cycles If the base duty cycle is 50 96 it will therefore be stretched to 50 496 For example if you write 80H to the extension register all odd numbered pulses will be one cycle longer If you write FCH to the extension register all pulses will be stretched by one cycle except the 256th pulse PWM output goes to an output buffer and then to the corresponding PWM output pin In this way you can obtain high output resolution at high frequencies 16 2 ELECTRONICS S3F84Q5_UM_REV1 00 Table 16 2 PWM output stretch Values for Extension Registers 14 BIT PWM PWMEX Bit Stretched Cycle Number 1 3 5 7 9 55 57 59 61 63 2 6 10 14 50 54 58 62 4 12 20 44 52 60 8 24 40 56 16 48 32 Not used Not used 100 200 PWM Clock 4MHz OH PWMDATA Register Values 20H 3FH Figure 16 1 14 Bit PWM Basic Waveform ELECTRONICS 14 PWM S3F84Q5_UM_REV1 00 OH 100H PWM Clock 4 2 PWMDATA Register 2H Values 02H PWMEX 151 64th 1st 32th 64th Register 4H Values 1 Extended D EP Value is 04H OH 100H 4MHz Figure 16 2 14 Bit Extended PWM Waveform ELECTRON
270. verflow interrupt 1 Enable overflow interrupt ELECTRONICS 4 3 CONTROL REGISTERS S3F84Q5_UM_REV1 00 TACON Timer A Control Register E4H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Timer Input Clock Selection Bits 0 fxx 1024 1 fxx 256 5 4 Timer Operating Mode Selection Bits Internal mode TAOUT mode Capture mode capture rising edge counter running OVF occur 1 Capture mode capture on falling edge counter running OVF can occur 1 PWM mode OVF interrupt can occur 3 Timer Counter Clear Bit 3 No effect 1 Clear the timer A counter After clearing return to zero 2 Ti 3 er A Overflow Interrupt Enable Bit Disable interrupt 1 Enable interrupt 1 Timer A Match Capture Interrupt Enable Bit Disable interrupt Enable interrupt 0 Timer Start Stop Bit Stop Timer A 1 Start Timer 4 36 ELECTRONICS S3F84Q5_UM_REV1 00 CONTROL REGISTER TBCON Timer B Control Register E5H Set 1 Bank 1 Bit Identifier RESET Value Read Write 7 6 ELECTRONICS _ 5 4 3 2 0 0 0 0 0 0 0 0 RW RW RM RW RW RW RW Timer B Input Clock Selection Bits olope rots ma i o mg 1 fxx 1 Not used for S8F84Q5 Interval mode TBOUT mode 1 PWM mode OVF interrupt can occur
271. will not execute as well as reset will be generated Figure 7 8 STOP Control Register STPCON ELECTRONICS 7 7 S3F84Q5_UM_REV1 00 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW By smart option 8FH 7 in ROM user can select internal RESET LVR or external RESET The S3F84Q5 can be RESET in four ways e external power on reset e bythe external nRESET input pin pulled low e bythe digital watchdog peripheral timing out by Low Voltage Reset LVR During an external power on reset the voltage at Vpp is High level and the nRESET pin is forced to Low level The nRESET signal is an input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S8F84Q5 into a known operating status To ensure correct start up the user should take care that nRESET signal is not released before the Vpp level is sufficient to allow MCU operation at the chosen frequency The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 8 19 ms 216 fxx fxx 8 MHz When a reset occurs during normal operation with both Vpp and nRESET at High level the signal at the nRESET pin is forced Low and the Reset operation starts All system and peripheral control registers are then set
272. within the range Vss to usually Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 ELECTRONICS 17 3 S3F84Q5_UM_REV1 00 BLOCK DIAGRAM A D Converter Control Register ADCON FBH ADCON 0 ADC Start ADCON 7 4 Control Clock ADCON 3 Circuit Selector EOC Flag ADCO P 1 0 ADC1 P1 1 ADC2 P 1 2 Successive Approximation Circuit Comparator ADC6 P 0 6 ADC7 P 0 7 AVref Conversion Result D A Converter To data bus Figure 17 3 A D Converter Functional Block Diagram 17 4 ELECTRONICS S3F84Q5_UM_REV1 00 A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 1 2 Analog input must remain between the voltage range of Vss and AVper Configure 1 0 1 7 for analog input before A D conversions To do this you load the appropriate value to the P1CONH and P1CONL for ADCO ADC7 registers Before the conversion operation starts you must first select one of the eight input pins ADCO ADC7 by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful The converted digital value is loaded to
273. xD PO 1 INT5 P3 3 INT6 P3 4 nRESET PO 2 INTO ADCO P1 0 INT1 ADC1 P1 1 Figure 1 5 S3F84Q5 Pin Assignment 32 ELP 1 6 ELECTRONICS SF84Q5_UM_REV1 00 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 Pin Descriptions of 28 SOP 32 SOP 32 SDIP 30 SDIP Shared Functions I O port with bit programmable pins RxD TxD Configurable to input or push pull output RESETB mode 0 2 be configured to open drain output mode Pull up resistors can be assigned by software Pins can also be assigned individually as alternative function pins I O port with bit programmable pins INTO INT1 Configurable to input or push pull output ADCO ADC7 mode Pull up resistors can be assigned TDOUT by software Pins can also be assigned individually as alternative function pins XTIN XTOUT P2 0 P2 1 P2 3 I O port with bit programmable pins TAOUT TACK P2 5 P2 7 Configurable to input mode push pull 23 TACAP output mode pin2 6 2 4 2 2 can be TBOUT configured to n channel open drain 23 T1CAP T1CK BUZ P2 2 P2 4 P2 6 output mode Input mode with pull up T1OUT resistors can be assigned by software PWM Pins can also be assigned individually as alternative function pins P3 0 I O port with bit programmable pins SI SO SCK INT2 P3 1 P3 2 Configurable to input or push pull output 31 4 5 8 mode P3 0 P3 3 3 6 be configured P3 3 P3 6 to open drain output mode Pull up resistors can be assigned by softwa
274. y returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 SSF8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 1P8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 5 16 ELECTRONICS S3F84Q5_UM_REV1 00 INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and e When a fast interrupt occurs the contents of the FLAGS register are stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3F84Q5 microcontroller the service routine for any one of the eight int

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