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NI 5792R User Manual and Specifications

1. Save As Select Copy Open Additional Copy and check Add Copy to lt your project name gt vproj Select the destination folder for the new file specify a file name and click OK Use this FPGA VI with the NI 579x Configuration Design Library 14 NI 5792R User Manual and Specifications ni com 14 15 16 17 18 19 In the Project Explorer window expand IO Module Tree View Use any element under IO Module NI 5792 NI 5792 in the block diagram of the FPGA VI e Note Ifyou are using the NI 5792 CLIP use Rx I and Rx Q from the CLIP IO Node in a single cycle Timed Loop running on IO Module Sample Clock the 250 MHz clock This CLIP provides one sample per cycle at the 250 MHz rate Note Ifyou are using the NI 5792 Multiple Sample CLIP use Rx I N Rx I N 1 Rx QN Rx Q N 1 from the CLIP IO Node in a single cycle Timed Loop running on IO Module Half Sample Clock the 125 MHz clock This CLIP provides two samples per cycle at the 125 MHz rate 4 Note For either CLIP if you are using the DSP Instrument Design Library you must use the 2 samples per cycle 2x overclocking instances of the DSP VIs Place these VIs in a single cycle Timed Loop running on IO Module Half Sample Clock and wire IO Module Sample Clock to the clock x 2 terminals Add any FPGA code controls and indicators that you need Refer to Streaming lvproj for example FPGA code controls and indicators Click the Run button LabVI
2. e Use an external Sample Clock Set the CPTR period manually Host driven synchronization requires an additional FPGA I O line and host involvement for CPTR alignment Note Host driven synchronization is repeatable only if the phase relationships between devices remain constant Host driven synchronization guarantees that the maximum phase offset between the master and slave device is one half of a Sample Clock period The phase offset approaches zero as the phase relationships between the devices approach zero Note The phase relationship between the device and the Reference Clock does not affect host driven synchronization Synchronization Example You can find examples of both FPGA code and host code for synchronization at lt labview gt examples instr ni579x Streaming 18 NI 5792R User Manual and Specifications ni com How Synchronization Works When you share triggers between multiple devices propagation delays on the signal path cause the trigger to arrive at different times on each device The synchronization library uses the CPTR to slow down the trigger evaluation rate All devices must produce a CPTR signal that is equal in frequency and phase aligned The synchronization FPGA VIs produce and align a CPTR that occurs simultaneously across all the FPGAs The CPTR is periodic and the Sample Clock rate controls the CPTR period When you power on the FPGAs the CPTRs are not aligned The alignment FPGA VI and the h
3. Port 1 Wr Data 1 DIO Port 1 Rd Data 2 H T 1 1 T 1 1 T 1 1 T 1 1 T 1 1 T 1 1 1 1 1 DIO Port 1 0 A A al y DIO Port 1 1 A a y DIO Port 4 2 AUX I O A pi DIO Port 1 Wr Data 2 DIO Port 1 Rd Data 3 DIO Port 1 Wr Data 3 DIO Port 1 WE Vv y DIO Port 4 3 A 1 PFI 0 Rd Data PFI O Wr Data PFI 1 Rd Data PFI 1 Wr Data PFI 2 Rd Data PFI 2 Wr Data PFI 3 Rd Data PFI 3 Wr Data PFIO y Y A y Jp PFI 1 L A L y y PFI2 A y JE PFI 3 A ie PFI lt 0 3 gt WE ay 4 y y 1 The following figure shows the NI 5792 low pass filter bank NI 5792R User Manual and Specifications National Instruments 9 Figure 5 Low pass Filter LPF Bank 3800 MHz LPF om X ATORES 2400 MHz LPF ae a RX 1800 MHz LPF ARL RX 1068 MHz LPF E x LON _ AS Z _ X J 711 MHz LPF AAN RX 474 MHz LPF E ET RX w 16 MHz LPF TU RX 4400 MHz LPF ie g A RX NI 5792 Component Level Intellectual Property CLIP The LabVIEW FPGA Module includes component level intellectual property CLIP for HDL IP integration NI FlexRIO devices support two types of CLIP user d
4. device to any slave device across the selected FPGA I O line NI 5792R User Manual and Specifications National Instruments 17 e The CPTR period must be the same across all devices Devices can have different Sample Clock frequencies if the device Sample Clocks have a fixed phase relationship e Route the FPGA I O lines to all the devices that you are synchronizing Synchronization Versions The synchronization library provides two alignment methods depending on user needs FPGA self synchronization and host driven synchronization Both synchronization methods produce the same quality of synchronization but differ in their requirements and versatility of operation FPGA Self Synchronization FPGA self synchronization does not require host involvement Using the host VIs is optional The FPGAs can all independently align their CPTRs To perform a self synchronization your devices must meet the following requirements e Sample Clocks are locked to the same Reference Clock e Sample Clocks are an integer multiple of the Reference Clock e All the devices are fewer than 60 degrees out of phase with each other Note FPGA self synchronization is repeatable only if the devices meet all the requirements If the devices do not meet the requirements use host driven synchronization Host Driven Synchronization Host driven synchronization allows you to perform the following actions e Decouple the Sample Clock and the Reference Clock
5. e AS NZS CISPR 11 Group 1 Class A emissions e FCC 47 CFR Part 15B Class A emissions e ICES 001 Class A emissions Note In the United States per FCC 47 CFR Class A equipment is intended for use in commercial light industrial and heavy industrial locations In Europe 32 NI 5792R User Manual and Specifications ni com Canada Australia and New Zealand per CISPR 11 Class A equipment is intended for use only in heavy industrial locations Note Group equipment per CISPR 11 is any industrial scientific or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection analysis purposes ei Note For EMC declarations certifications and additional information refer to the Online Product Certification section CE Compliance C This product meets the essential requirements of applicable European Directives as follows e 2006 95 EC Low Voltage Directive safety e 2004 108 EC Electromagnetic Compatibility Directive EMC Online Product Certification To obtain product certifications and the DoC for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column Environmental Management NI is committed to designing and manufacturing products in an environmentally responsible manner NI recognizes that eliminating certain hazardous substances from our products is beneficia
6. if LabVIEW is already running select File Create Project In the Create Project dialog box select LabVIEW FPGA Project and click Finish Select FlexRIO on My Computer and click Next Either discover a LabVIEW FPGA target in your system or create a new system and specify an FPGA target for which to construct a project Click Finish in the Project Preview dialog box Click File Save and specify a name for the project Creating an FPGA Target VI De R a 10 11 12 13 In the Project Explorer window expand FPGA Target Right click FPGA Target and select New FPGA Base Clock In the Resource pull down menu select 200 MHz Clock and click OK Right click IO Module in the Project Explorer window and select Properties Select Enable IO Module Select the NI 5792 from the IO Module list The available CLIP for the NI 5792 is displayed in the Component Level IP pane Select NI 5792 or NI 5792 Multi Sample CLIP in the Name list of the Component Level IP pane In the Clock Selections category select 200 MHz Clock from the pull down menu for Clock 200 MHz Leave Clock 40 MHz configured as the Top Level Clock Click OK Note Configuring these clocks is required for proper CLIP operation Refer to the NI 5792 CLIP topics in the MI FlexRIO Help for more information about configuring your clocks Select File Open and select lt labview gt instr lib ni579x config v1 FPGA Public ni579x Config FPGA Template vi Select File
7. 1 5 kHz resolution bandwidth RBW RX LO Residual Power Note All values are nominal Table 7 Residual Power Center Frequency Temperature 23 C 5 C dBFS gt 200 MHz to 300 MHz 30 gt 300 MHz to 1 GHz 42 gt 1 GHz to 2 GHz 52 gt 2 GHz to 3 GHz 52 gt 3 GHz to 3 9 GHz 52 gt 3 9 GHz to 4 4 GHz 52 Note Receiver LO suppression is measured at the same RX attenuation after an VQ correction RX Sideband Image Suppression ei Note All values are nominal Table 8 Sideband Image Suppression Center Frequency Temperature 23 C 5 C dBc gt 200 MHz to 300 MHz 27 gt 300 MHz to 1 GHz 39 24 NI 5792R User Manual and Specifications ni com Table 8 Sideband Image Suppression Continued Center Frequency Temperature 23 C 5 C dBc gt 1 GHz to 2 GHz 58 gt 2 GHz to 3 GHz 54 gt 3 GHz to 3 9 GHz 45 gt 3 9 GHz to 4 4 GHz 35 Note The image suppression specifications hold at the center frequency of the acquired instantaneous bandwidth after the device performs a single recent point T Q impairment self correction RX Third Order Intermodulation Distortion IP 3 Note All values are nominal Table 9 RX IP3 Frequency Temperature 23 C 5 C dBm gt 200 MHz to 1 GHz 9 gt 1 GHz to 2 GHz 7 gt 2 GHz to 3 GHz 6 gt 3 to 3 9 GHz 4 gt 3 9 GHz to 4 4 GHz 1 No
8. 4 R z a ZS 904 2 2 2 S 110 ra 130 4 ie 150 T T T T T 10 100 1k 10k 100k 1M 10M Offset Frequency Hz LO OUT Front Panel Connector Brequency Tanges lssecicseriariesereeiseiteevy sevens 200 MHz to 4 4 GHz PONET rE EEA TAA 3 dBm 3 dB nominal Output power resOlUtion cceceseeseeteeteeeeeeeee 0 15 dB Output Impedance cceecceeceeceteeteteeeeseeeeeee 50 Q nominal Output VSWR aiseria TARA 1 78 1 Amplitude settling time eee eeeeeteeeeeeeees lt 0 25 dB in less than 10 ms typical Maximum DC voltage ccceceeeseeseeteeseteeeeee 0 5 Voc 28 NI 5792R User Manual and Specifications ni com Figure 11 LO Output Power vs LO Frequency 7 0 6 5 7 6 0 5 5 7 5 0 5 45 7 4 0 5 LO Output Power dBm 3 5 5 3 0 4 2 5 7 2 0 T T T T T T T T 2G 7G 1 2E 09 1 7E 09 2 2E 09 2 7E 09 3 2E 09 3 7E 09 4 2E 09 LO Frequency Hz LO IN Front Panel Connector Frequency tange nencai ninina 200 MHz to 4 4 GHz Trnput POWED cceccecesceseeseesececsecesesseeeeseeseeseees 3 dBm 3 dB nominal Input impedance eee eniin 50 Q Input VSWR eiria i a A i 1 78 1 Absolute maximum pOWer c ceseseeseeseereeseeee 15 dBm Maximum DC powel ceeesetteteereereree 0 5 VDC Baseband Characteristics Analog to Digital Converters ADC Resolution 14 bits Data tate sicsccssissiesiasiassassasinsieessusdiecdsveeveanss 250 MS s VQ data rate cccccecsecescesses
9. AL INSTRUMENTS Figure 1 NI FlexRIO Device NI FlexRIO NI FlexRIO Adapter Module FPGA Module z exRIO Device Related Information NI 5792 Specifications on page 21 Contents Electromagnetic Compatibility Guidelines cccccseeeeeeceseeececeseeeecesceeeceecaeceeceeeeeeeeeeetaees 3 Connecting Cables cornrne aea E A E E C 3 How to Use Your NI FlexRIO Documentation Set cccccsceesseseesceeseeeeceseceeeeeeeeeaeseeeeeeeees 4 Key POaturesis ciccseseds iusscsveds scoscesvesesesseeteesbesesectassee sass Front Panel and Connector Pinouts AUX I O Connector Bl ck Dia grains sionin e Eaa TEES E seal arene ear dian ap da ares bee Ae NI 5792 Component Level Intellectual Property CLIP ceeesssseessesececeseeecneeeeeenseeees 10 5792 CLAP sacsccvisueeuis ctensussssesien chs KEES aE E aA EASES wll Programmable Chipsi enisinia oai 12 Using Your NI 5792R with a LabVIEW FPGA Example VI 12 Using the Included Streaming Example ccceccesssesseeeeseseeseesesessceesesseserseseeeesaenees 13 Creating a LabVIEW Projectisccsaecsaiscisesisceiessasaes inris Ativesees cis odes causal caresses 14 NI 579x Configuration Design Library ccceescceseesceeeeceseeeceesecsevsccaseecsevscsaesaeeeceaseetaesaes 16 FPGA VI Requirement cceceeseescessesecssescesseeseesececeaecaecaseesecseeseeseseaeeaecaesaeeeaesaeeeees 16 Host VI Requirements sei Synchronization Overview cis css css caasscs
10. DC coupled 0 V to 2 V LO IN Local oscillator input 20 dBm maximum AUXTO Refer to the table below for signal list and descriptions Related Information NI 5792 Specifications on page 21 6 NI 5792R User Manual and Specifications ni com AUX I O Connector Table 3 NI 5792 AUX 1 0 Connector Pin Assignments AUX I O Connector Pin Signal Signal Description 1 DIO Port 0 0 Bidirectional single ended SE digital I O DIO data channel al i 2 GND Ground reference for signals a 17 3 DIO Port 0 1 Bidirectional SE DIO data channel k 13 4 DIO Port 0 2 Bidirectional SE DIO data channel 12 5 GND Ground reference for signals 9 6 DIO Port 0 3 Bidirectional SE DIO data channel 6C_J 7 DIO Port 1 0 Bidirectional SE DIO data channel i 3 8 GND Ground reference for signals RF 9 DIO Port 1 1 Bidirectional SE DIO data channel 10 DIO Port 1 2 Bidirectional SE DIO data channel 11 GND Ground reference for signals 12 DIO Port 1 3 Bidirectional SE DIO data channel 13 PFIO Bidirectional SE DIO data channel 14 NC No connect 15 PFI1 Bidirectional SE DIO data channel 16 PFI2 Bidirectional SE DIO data channel 17 GND Ground reference for signals 18 5 V 5 V power 10 mA maximum 19 PFI3 Bidirectional SE DIO
11. EW creates a default build specification and begins compiling the VI The Generating Intermediate Files window displays the code generation process The Compilation Status window displays the progress of the compilation The compilation takes several minutes Click Close in the Compilation Status window Save and close the VI Save the project Creating a Host VI 1 10 11 12 In the Project Explorer window right click My Computer and select New VI to open a blank VI Select Window Show Block Diagram to open the VI block diagram Add the Open FPGA VI Reference function from the FPGA Interface palette to the block diagram Right click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference In the Configure Open FPGA VI Reference dialog box select VI in the Open section In the Select VI dialog box select your project under your device and click OK Click OK in the Configure Open FPGA VI Reference dialog box The target name appears under the Open FPGA VI Reference function in the block diagram Open the FPGA Interface palette Add any Read Write Control or Invoke Method nodes necessary to configure and communicate with your FPGA VI Add the Close FPGA VI Reference function to your block diagram Wire the FPGA VI Reference function to the Close FPGA VI Reference function Save and close the VI NI 5792R User Manual and Specifications National Instruments 15 13 Save the proje
12. Remove the captive screw covers 2 Install the PXI EMC filler panels by securing the captive mounting screws to the chassis as shown in the figure below Make sure that the EMC gasket is on the right side of the PXI EMC filler panel Figure 12 PXI EMC Filler Panels and Chassis 1 Captive Screw Covers 2 Captive Mounting Screws 3 EMC Gasket Note You must populate all slots with a module or a PXI EMC filler panel to ensure proper module cooling Do not over tighten screws 2 5 lb in maximum For additional information about the use of PXI EMC filler panels in your PXI system visit ni com info and enter emcpanels Related Information Electromagnetic Compatibility Guidelines on page 3 34 NI 5792R User Manual and Specifications ni com Where to Go for Support The National Instruments Web site is your complete resource for technical support At ni com support you have access to everything from troubleshooting and application development self help resources to email and phone assistance from NI Application Engineers A Declaration of Conformity DoC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electromagnetic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification If your product supports calibration you can obtain the calibr
13. Sample Clock 1 5x Half Sample Clock 1 i i gt PLL Locked Mq Sync Clock gt Register Bus Idle y j Register Bus Address PLL Loop SPI Register Register Bus Read Data Filter em Engine Bus Register Bus Read _ Register Write Data Clock 7 e Register Bus Write DAC SPI 4 DAC RF LO and Attenuators SPI Enable VCXO 1 Initialization Done gt User Error gt User Return _ gt User Command Idle le User Command 4 User Command Commit r User Command Status 4 User Data 0 4 User Data 1 1 Calibration EEPROM Microcontroller Enable PLL External Sample CLK External Ref CLK Al Gain Control RF Filter Control t RF Filters From RF LO pt LO Locked eset DIO Port 0 Rd Data 0 DIO Port 0 Wr Data 0 DIO Port 0 Rd Data 1 DIO Port 0 Wr Data 1 DIO Port 0 Rd Data 2 DIO Port 0 Wr Data 2 DIO Port 0 Rd Data 3 DIO Port 0 Wr Data 3 DIO Port 0 WE DIO Port 0 0 A DIO Port 0 1 An A y y T DIO Port 0 2 A y y t DIO Port 0 3 1 1 1 T 1 T 1 T 1 1 T 1 n 1 DIO Port 1 Rd Data 0 t DIO Port 1 Wr Data 0 1 DIO Port 1 Rd Data 1 DIO
14. USER MANUAL AND SPECIFICATIONS NI 5792R RF Receiver Adapter Module The NI 5792 is an RF receiver adapter module designed to work in conjunction with your NI FlexRIO FPGA module The NI 5792 features the following connectors and chips 2 channel 250 MS s analog to digital converter ADC with 14 bit accuracy LO input and LO output connectors to support LO sharing for multiple channel applications Timing chip with clocking options from the backplane and the front panel Programmable attenuators Selectable receive filters The following front panel connectors RX IN LO OUT CLK IN CLK OUT LO IN This document contains signal information and lists the specifications of the NI 5792R which is composed of the NI FlexRIO FPGA module and the NI 5792 This document also contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA Example VI and how to create and run your own LabVIEW project with the NI 5792R AnH wm Note MNI 5792R refers to the combination of your NI 5792 adapter module and your NI FlexRIO FPGA module MI 5792 refers to your NI 5792 adapter module only Note The NI 5792 is only compatible with the NI PXTe 796xR FPGA modules Note Before configuring your NI 5792R you must install the appropriate software and hardware Note For EMC compliance operate this device according to the documentation The following figure shows an example of a properly connected NI FlexRIO device NATION
15. al and Specifications National Instruments 19 Synchronization Checklist Verify that the project settings in the system the project the host VI and the FPGA VI are configured as follows e System settings Route the FPGA I O lines to all the devices Depending on your chassis size you may have to route PXI trigger lines using Measurement amp Automation Explorer MAX Refer to the Measurement amp Automation Explorer MAX Help at ni com manuals for more information about routing PXI trigger lines with MAX e Project settings Configure the adapter module IoModSyncClock either PXI CLK10 or DStarA if you are not driving the adapter module CLK IN connector Add the FPGA Reference Clock Configure the Reference Clock to have zero synchronization registers In the FPGA IO Property dialog box set Number of Synchronization Registers for Read to 0 Add the FPGA I O lines that you are synchronizing Do not remove synchronization registers e Host VI Configure the adapter module clock source based on the project settings Lock the adapter module clock to the clock source Run the Synchronization VI Refer to the example FPGA code at lt labviewdir gt examples instr ni579x Streaming e FPGA VI Configure the CPTR period The synchronization library ensures that the CPTR period is the same on the host and the FPGA Refer to the example FPGA code at lt labviewdir gt examp
16. ation certificate for your product at ni com calibration National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also has offices located around the world to help address your support needs For telephone support in the United States create your service request at ni com support and follow the calling instructions or dial 512 795 8248 For telephone support outside the United States visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events NI 5792R User Manual and Specifications National Instruments 35 Refer to the NI Trademarks and Logo Guidelines at ni com trademarks for information on National Instruments trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents You can find information about end user license agreements EULAs and third party legal notices in the readme file for your NI product Refer to the Export Compliance Information at ni com legal export compliance for the National Instruments global trade compliance policy and
17. cceececceseeeeeeeeseeneens 200 MHz to 4 4 GHz ADO arai i a AA E ER E EE 14 bit dual channel at 250 MS s Phase Noise ieia orei a ER lt 95 dBc Hz 10 kHz offset 2 4 GHz carrier Dynamic r n genine eeni gt 106 dB Receive RX IP3 ccsesseseceeceeceseeseeeeeseceeeneees 6 dBm at 2 GHz Instantaneous bandwidth ee eeeeeeeeeeeeee 200 MHz Front Panel and Connector Pinouts Table 2 shows the front panel connector and signal descriptions for the NI 5792 A Caution To avoid permanent damage to the NI 5792 disconnect all signals connected to the NI 5792 before powering down the module and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module Caution Connections that exceed any of the maximum ratings of any connector on the NI 5792R can damage the device and the chassis NI is not liable for any damage resulting from such connections A NI 5792R User Manual and Specifications National Instruments 5 Table 2 NI 5792 Front Panel Connectors ALL COAXIAL PORTS 5VDCMAX 50 W AUX 1 0 0 33 V DC 200 MHZ 4 4 GHz RF Receiver Qe Device Front Panel Connector Signal Description RX IN Receive channel input 20 dBm maximum gt PO NTRUMENTs LO OUT Local oscillator output 12 dBm maximum 0 dBm ee nominal CLK IN Reference Clock input 50 Q single ended 20 dBm maximum CLK OUT Exported clock output
18. ct Run the Host VI 1 Open the front panel of your host VI 2 Click the Run button to run the VI NI 579x Configuration Design Library The NI 579x Configuration Design Library consists of host and FPGA VIs that provide an interface to configure the hardware on the NI 5792 The library allows you to perform the following actions e Configure the mixers e Configure the RF signal path including attenuators amplifiers and filters e Read from and write to the EEPROM e Configure the reference level for the Rx channel e Configure the clocks e Reinitialize the CLIP e Query for CLIP errors The NI 579x Configuration Design Library relies on the Register Bus Design Library The Register Bus provides a packet based configuration interface which exposes all of the address spaces of the configurable chips and subsystems of the adapter module without requiring hundreds of controls and indicators on your FPGA VI front panel The NI 579x Configuration Design Library host VIs all require a register bus object for the device you want to configure Create the register bus object using Open Session vi or use ni579x Open vi For more information about how to use the NI 579x Configuration Design Library refer to the example located at lt labview gt examples instr ni579x Streaming Streaming lvproj FPGA VI Requirements Copy all the controls indicators and FPGA logic required to use the NI 579x Configuration Design Library
19. data channel Caution The AUX I O connector accepts a standard third party HDMI cable but the AUX I O port is not an HDMI interface Do not connect the AUX I O port on the NI 5792 to the HDMI port of another device NI is not liable for any damage resulting from such signal connections NI 5792R User Manual and Specifications National Instruments 7 Block Diagram The following figure shows the NI 5792 block diagram Figure 3 NI 5792 Block Diagram 31 75 dB Maximum 31 75 dB Maximum RX IN 0 25 dB Step 0 25 dB Step TI ADS4249 SD ADC fi tfAH gt eH Ae 44 onz RX Filter 104 MHz Noise Reject P 0 LO OUT Bank A bo LPF LPF a a TI ADS4249 RX LO e i i w 3 Filter Bank G ES 12 dB ne ADC Ly 14 Bits 104 MHz Noise Reject LPF LPF ADF 4351 Synthesizer LO The following figure shows the connections between the NI 5792 and the LabVIEW FPGA CLIP 8 NI 5792R User Manual and Specifications ni com Figure 4 NI 5792 Connector Signals and CLIP Signal Block Diagram NI 5792 Adapter Module LabVIEW FPGA CLIP From RF 1 ADC Data Mixer i ADC 14 i ADS4249 ADC Clock 4 i ADC SPI OUT2 CLK IN oa gt CLK1 AD9511 REF IN OUTI CLK2 OUT3 cp SPI i r RI apc c Rg Interface q S z Sample Clock Sample Clock PLL gt
20. e Floor 26 NI 5792R User Manual and Specifications ni com RX IN Frequency Characteristics Brequency tangele sieas 200 MHz to 4 4 GHz Instantaneous bandwidth 6 dB ceeeereeee 200 MHz Tuning resolution cecccsesessssessesesseseesesees lt 250 kHz LO step size Integer MOde ceececeeceseesenseeseeeeeeeeeeeeees 4 MHz 6 MHz 12 MHz and 24 MHz step sizes Fractional mode cceceeseeseeseeteeteeseeeeeeees 100 kHz step size Frequency Settling Time Settling times genae a a ae lt 50 ms per 100 MHz step Phase Noise Note All values are nominal Table 13 Phase Noise at 2 4 GHz Offset Frequency Loop Phase Noise dBc Hz 1 kHz 85 10 kHz 95 100 kHz 97 1 MHz 100 10 MHz 110 Tuning resolution combines LO step size capability and frequency shift DSP implemented on the FPGA All LO step size specifications are assumed to be with fractional mode enabled and 100 kHz LO step size The settling time specification only includes frequency settling and it excludes any residual amplitude settling that may occur as a result of large frequency changes Driver and operating system timing can affect transition times This specification reflects only hardware settling 2 NI 5792R User Manual and Specifications National Instruments 27 Figure 10 Phase Noise 50 900 MHz 2 4 GHz 44 GHz 70
21. eceeiscisstasipctessetesdestendessassussapsatasassessessshsesstuseatedaestestnetesess Synchronization VersiOns cccccesccscescesscesseeecesecseeseeseceseceecsaecaeeseeeeeeseceecaecseeseeeeeeaeeaees 18 Synchronization Example cccceccesssesceseesecsceseceseesecaecsecseeeseesesenseaecaeeseeeseeeseeceaeenaeats 18 How Synchronization Works cccecesssscsesessesececseeseneescceeeeceaesesaeeeceeseesacsevaeeeseeenanaes 19 Synchronization Checklist ae CLOCKING cesetetsetysepeteeess isch E E T E TE E E TE stsaaeites SIX Sample PLO SOUS anina aE rE EEA ONN NI S5792 Specifications isinir sacsteieadessewed douse cro Veatseesst sua to raeedbed go0eed Sak E ccondestye ey st shadbedees BOX IN A A E E EE sto sdbsunssvavstosansiesaauscnionsussvbasveunenvesiiesGectecdenue LO OUT Front Panel Connector A LO IN Front Panel Conmectot ececcesessessessceseeeeceecesecseceaeesecseeseesececeaecaesaaesaecaeeaeeeees Baseband Characteristics c cssscciccasl ss suetueseednssedecue ian sueteedt coveveledee tonsveledos Gonduensh desu canelosased AUX I O Port 0 DIO lt 0 3 gt Port 1 DIO lt 0 3 gt and PFI lt 0 3 gt ccesccseseeeeeeeeeees 30 2 NI 5792R User Manual and Specifications ni com AVA ONIN C113 costa casa gn cu sxe vena ene Shas E E A E REEE enestene tenes Operating Environment Environmental Managementt c ceccessescesesseesceseeeeceeceaecaecseeceecseseceeceaecnecnaeeaeeaeeaeees 33 Installing PXDEMC F
22. efined and socketed e User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI e Socketed CLIP provides the same IP integration of the user defined CLIP but also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface The following figure shows the relationship between an FPGA VI and the CLIP 10 NI 5792R User Manual and Specifications ni com Figure 6 CLIP and FPGA VI Relationship NI FlexRIO FPGA Module FPGA User Defined CLIP CLIP Socket User Defined 4 7 Labview 4 Saad Adan CLIP FPGAVI p ockete apter i cup K Eed A Module gt rt yi DRAM 0 DRAM 1 CLIP Socket CLIP Socket i Adapter Module i External V O Connector Socketed Socketed CLIP CLIP The NI 5792 ships with socketed CLIP items that add module I O to the LabVIEW project 5792 CLIP 1 NI5792 CLIP This CLIP generates one sample per clock cycle at a default sample rate of 250 MHz You can set a lower sample rate by using an external Sample Clock This CLIP provides access to I and Q data for one RF receive channel The CLIP also provides a User Command interface for common configurat
23. entation Locations and Descriptions Document Location Description NI FlexRIO FPGA Module Installation Guide and Specifications Available from the Start menu and at ni com manuals Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module NI 5792R User Manual and Specifications this document Available from the Start menu and at ni com manuals Contains signal information examples CLIP details and specifications for your adapter module 4 NI 5792R User Manual and Specifications ni com Table 1 NI FlexRIO Documentation Locations and Descriptions Continued Document Location Description LabVIEW FPGA Module Embedded in LabVIEW Contains information about the basic Help Help and at ni com functionality of the LabVIEW FPGA manuals Module NI FlexRIO Help Available from the Start Contains FPGA Module adapter menu and at ni com module and CLIP configuration manuals information LabVIEW Examples Available in NI Example Contains examples of how to run Finder FPGA VIs and Host VIs on your device IPNet ni com ipnet Contains LabVIEW FPGA functions and intellectual property to share NI FlexRIO product ni com flexrio Contains product information and page data sheets for NI FlexRIO devices Key Features The NI 5792 includes the following key features RF frequency range cce
24. er modules Synchronization aligns the devices so that the devices are synchronized to the nearest Sample Clock cycle The devices may be offset by up to one half of one Sample Clock cycle if the devices are 180 degrees out of phase If the devices are zero degrees out of phase device alignment offset is also zero degrees devices Caution Before attempting to synchronize your NI FlexRIO devices notice the ei Note For the best synchronization results minimize the phase offset between A following caveats e Synchronization does not account for differences in analog signal paths Synchronization does not account for data pipeline delays that occur before and after the synchronization VIs For example synchronization does not account for ADC DAC pipeline delays e The synchronized edge is always delayed relative to the unsynchronized edge The application is responsible for accounting for this delay if necessary The synchronization VIs provide the actual synchronization delay value e Lock all devices to a common time reference Use the Reference Clock as the time reference e Set the synchronization registers for the Reference Clock to zero e Synchronization does not account for propagation delays of the Reference Clock e All Sample Clocks must have a fixed phase relationship with each other e The Common Periodic Time Reference CPTR period must be greater than the maximum propagation delay of a signal from the master
25. from the following VI lt labview gt instr lib ni579x Config v1 FPGA Public ni579x Config FPGA Template vi The FAM Support installer installs this VI on your system Configure your FPGA target to contain a FIFO with the following configuration Name reg host instruction fifo 0 e Type Host to Target DMA e Requested number of elements 1 023 Data type U64 e Arbitration for read Arbitrate if multiple requestors only Number of elements per read 1 16 NI 5792R User Manual and Specifications ni com Host VI Requirements Configure your host VI to use the NI 579x Configuration Design Library using the following configuration 1 Create a Register Bus object for your device and initialize the session using ni579x Open vi 2 Use any of the NI 579x Configuration Design Library Host VIs using the Register Bus object returned by the ni579x Open VI 3 To access the Host VIs select Functions Instrument I O Instrument Drivers NI 579x Configuration 4 Close the session using the ni579x Close VI Synchronization Overview Synchronization coordinates Sample Clock cycles across multiple NI FlexRIO devices Sources of error such as common clock propagation delay cabling and cable lengths analog delays in the FPGA module and or adapter module and skew jitter in the common clock can affect frequency and phase relationships between devices Use the programming example to synchronize across multiple NI FlexRIO adapt
26. how to obtain relevant HTS codes ECCNs and other import export data 2013 National Instruments All rights reserved 373947B 01 May13
27. ick the Open FPGA VI Reference PXI 7966R function and select Configure Open FPGA VI Reference c Inthe Configure Open FPGA VI Reference dialog box click the Browse button next to the Bitfile button d In the Select Bitfile dialog box that opens select the bitfile for your desired target The bitfile name is based on the adapter module example type and FPGA module e Click the Select button f Click OK in the Configure Open FPGA VI Reference dialog box g Save the VI 7 On the front panel in the RIO Device pull down menu select an NI 5792 resource that corresponds with the target configured in step 6 8 Configure your measurement a Specify the center frequency in the LO Frequency Hz control b Specify the reference level in the Reference Level dBm control c Specify the sample rate in the Sample Rate S s control 9 Click the Run button to run the VI NI 5792R User Manual and Specifications National Instruments 13 10 11 12 The VI acquires data and displays the captured waveform on the Power Level Power Spectrum and I amp Q Data graphs Click the STOP button to stop the VI Close the VI Creating a LabVIEW Project This section explains how to set up your target and create an FPGA VI and host VI for data communication This section focuses on proper project configuration proper CLIP configuration and how to access NI 5792 I O nodes Creating a Project 1 2 3 4 Launch LabVIEW or
28. ifications National Instruments 31 Storage Environment Ambient temperature range e eee eeeeeeeeeee 40 C to 70 C Tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 Relative humidity range eee eeeeeeeeereeeeee 5 to 95 noncondensing Tested in accordance with IEC 60068 2 56 Operational SHOCK cee seeeeteeeesereeeeeeeeeeeeee 30 g peak half sine 11 ms pulse Tested in accordance with IEC 60068 2 27 Test profile developed in accordance with MIL PRF 28800F Random vibration Operating ececceecsecssesseeceeseeseeeeeeeeeeeeees 5 Hz to 500 Hz 0 3 gims Nomoperating cccccecceeeeeeeeceeceeceseeseeseenes 5 Hz to 500 Hz 2 4 gims Tested in accordance with IEC 60068 2 64 Nonoperating test profile exceeds the requirements of MIL PRF 28800F Class 3 Compliance and Certifications Safety This product is designed to meet the requirements of the following electrical equipment safety standards for measurement control and laboratory use e TEC 61010 1 EN 61010 1 e UL61010 1 CSA 61010 1 Note For UL and other safety certifications refer to the product label or the Online Product Certification section Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement control and laboratory use e EN 61326 1 IEC 61326 1 Class A emissions Basic immunity e EN 55011 CISPR 11 Group 1 Class A emissions
29. illet Panels ccc ys sctscostesescesscseesn sxsdeesd consveta ce covenatot ce soleheton de suednele sontveann 34 Where to Go for Support aissas isi E S a hia 35 Electromagnetic Compatibility Guidelines This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility EMC stated in the product specifications These requirements and limits are designed to provide reasonable protection against harmful interference when the product is operated in the intended operational electromagnetic environment This product is intended for use in industrial locations However harmful interference may occur in some installations when the product is connected to a peripheral device or test object or if the product is used in residential or commercial areas To minimize interference with radio and television reception and prevent unacceptable performance degradation install and use this product in strict accordance with the instructions in the product documentation Furthermore any modifications to the product not expressly approved by National Instruments could void your authority to operate it under your local regulatory rules AN Caution To ensure the specified EMC performance operate this product only with shielded cables and accessories Caution To ensure the specified EMC performance the length of all I O cables must be no longer than 3 m 10 ft A N Caution To ensure the specified EMC perf
30. ions of the base band clocking programmable attenuators receive amplifier receive filters LO filters and RF path which includes the ability to import and export the LO The baseband clocking can be configured using one of the following settings e Internal Sample Clock e Internal Sample Clock locked to an external Reference Clock through the CLK IN connector e External Sample Clock through the CLK IN connector e Internal Sample Clock locked to an external Reference Clock through the Sync Clock 2 NI5792 Multiple Sample CLIP This CLIP generates two samples per clock cycle at a clock rate that is half the sample rate This CLIP provides access to I and Q data for one RF receive channel The CLIP also provides a User Command interface for common configurations of the base band clocking programmable attenuators receive amplifier NI 5792R User Manual and Specifications National Instruments 11 receive filters LO filters and RF path which includes the ability to import and export the LO The baseband clocking can be configured using one of the following settings e Internal Sample Clock e Internal Sample Clock locked to an external Reference Clock through the CLK IN connector e External Sample Clock through the CLK IN connector e Internal Sample Clock locked to an external Reference Clock through the Sync Clock This CLIP also contains a FAM Registers Bus interface which is a low level bus interface that directly program
31. l not only to the environment but also to NI customers For additional environmental information refer to the Minimize Our Environmental Impact web page at ni com environment This page contains the environmental regulations and directives with which NI complies as well as other environmental information not included in this document Waste Electrical and Electronic Equipment WEEE a6 EU Customers At the end of the product life cycle all products must be sent to a WEEE recycling center For more information about WEEE recycling centers National Instruments WEEE initiatives and compliance with WEEE Directive 2002 96 EC on Waste Electrical and Electronic Equipment visit ni com environment weee htm ETIESE RIGS EI hE RoHS QO RAA National Instruments 6 P E ETIA Er m P REE HREA E M446 ROHS XF National Instruments F E RoHS AHH A HER ni com environment rohs_ chinao For information about China RoHS compliance go to ni com environment rohs_china NI 5792R User Manual and Specifications National Instruments 33 Installing PXI EMC Filler Panels To ensure specified EMC performance PXI EMC filler panels must be properly installed in your NI FlexRIO system The PXI EMC filler panels National Instruments part number 778700 01 must be purchased separately For more installation information refer to the NJ FlexRIO FPGA Module Installation Guide and Specifications 1
32. les instr ni579x Streaming Clocking The NI 5792 clock source controls the sample rate and other timing functions on the device The following table contains information about the possible NI 5792 clock sources 20 NI 5792R User Manual and Specifications ni com Table 4 NI 5792R Clock Sources Clock Frequency Source Options Sample Clock 250 MHz Free running and internally sourced e External through the CLK IN front panel connector Reference Clock 10 MHz Free running and internally sourced e External through the CLK IN front panel connector e Sourced through PXI CLK 579x Sample Projects The NI 5792 software contains sample projects that are a starting point for application development The projects are available in LabVIEW under Create Project Sample Projects NI 579X NI 5792 Specifications Specifications are warranted by design and under the following conditions unless otherwise noted e Chassis fan speed is set to High In addition NI recommends using slot blockers and EMC filler panels in empty module slots to minimize temperature drift The NI 5792 uses NI LabVIEW and LabVIEW FPGA software Specifications describe the warranted product performance over ambient temperature ranges of 0 C to 55 C unless otherwise noted Typical values describe useful product performance beyond specifications that are not covered by warranty and do not include guardbands for measuremen
33. n EEPROM to El amplifier is in the signal path RX IN Average Noise Floor Note All values are typical Table 6 Average Noise Floor Center Frequency Average Noise Level dBm Hz Temperature 23 C 5 C gt 200 MHz to 1 GHz 165 gt 1 GHz to 2 GHz 165 gt 2 GHz to 3 GHz 164 22 NI 5792R User Manual and Specifications ni com Table 6 Average Noise Floor Continued Center Frequency Average Noise Level dBm Hz Temperature 23 C 5 C gt 3 GHz to 3 9 GHz 160 gt 4 GHz to 4 4 GHz 151 Note Performance is measured with 0 dB of RX attenuation Figure 9 Average Noise Floor 159 161 163 Noise Floor dBm Hz 165 7 167 5 169 T 200M 700M T T T T T T 12G 17G 22G 27G 32G 37G 4 4 G Frequency Hz Voltage Standing Wave Ratio VSWR Note All values are nominal Input impedance eee Input VSWR with 10 dB of RX attenuation DIQNGHIZ sirane E 2 0 GHz lt f lt 3 GHz PO GHZ nenni INE sivas sean 1 5 1 OEA 1 1 1 TE ITEE 1 9 1 NI 5792R User Manual and Specifications National Instruments 23 Spurious Responses Note All responses are typical Non input related residual spurs 3 0 GHZ otiera EEEE 101 dBm 3 05039 GHZsu hinini aaa 100 dBm AA GH Zoar a a eaten nsss 91 dBm Note Performance is measured with 0 dB of RX attenuation and a
34. nstr ni579x Streaming Note The examples available for your device are dependent on the version of the software and driver you are using For more information about which software versions are compatible with your device visit ni com info enter rdsoftwareversion in the text field and click the NI FlexRIO link in the results The NI 5792R example project includes the following components e A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware e Atleast one VI that runs on Windows and interacts with the LabVIEW FPGA VI Note Inthe LabVIEW FPGA Module software NI FlexRIO adapter modules are referred to as JO Modules Using the Included Streaming Example Complete the following steps to run an example that acquires a waveform using the NI 5792 Connect an antenna to the RX IN connector on the front panel of the NI 5792 Launch LabVIEW Select File Open Project Navigate to lt labview gt examples instr ni579x Streaming Select Streaming lvproj PNY oP Ie Ne In the Project Explorer window select Rx Streaming Host vi under My Computer to open the host VI The Open FPGA VI Reference function in this VI uses the NI 7966R as the FPGA target by default If you are using an NI FlexRIO FPGA module other than the NI 7966R complete the following steps to change to the FPGA VI to support your target a Specify the center frequency in the LO Frequency Hz control b On the block diagram right cl
35. ormance you must install PXI EMC Filler Panels National Instruments part number 778700 1 in adjacent chassis slots Related Information Installing PXI EMC Filler Panels on page 34 Connecting Cables 1 Use any shielded 50 Q SMA cable to connect signals to the connectors on the front panel of your device 2 Use the SHH19 H19 AUX cable NI part number 152629 01 or 152629 02 to connect to the digital I O DIO and programmable function interface PFI signals on the NI 5792R User Manual and Specifications National Instruments 3 AUX I O connector NI recommends using the SCB 19 connector block to access the DIO and PFI signals Related Information NI 5792 Specifications on page 21 How to Use Your NI FlexRIO Documentation Set Refer to Figure 2 and Table 1 to learn how to use your FlexRIO documentation set Figure 2 How to Use Your NI FlexRIO Documentation Set INSTALL Hardware and Software CONNECT Signals and Learn About Your Adapter Module NI FlexRIO FPGA Module Installation Guide and Specifications a a NI FlexRIO Adapter Module User Guide and Specifications LEARN About LabVIEW FPGA Module Are You New to LabVIEW FPGA Module Module Yes No No LabVIEW FPGA lt gt NI FlexRIO lt gt LabVIEW Module Help Help Examples PROGRAM Your NI FlexRIO System in LabVIEW FPGA Table 1 NI FlexRIO Docum
36. ost VI align the CPTRs The following figure shows the relationship between the CPTRs the Reference Clock and the Sample Clock Figure 7 CPTR Alignment Reference Clock Sample Clock CPTR Device A CPTR Device B ei Note Lock Device A and Device B to a common clock Once the CPTRs are aligned synchronize an edge across multiple FPGAs The master device distributes the signal across an FPGA I O line All devices monitor the same FPGA I O line The edge is synchronized at the next CPTR edge After all the device CPTRs are aligned an edge sent out on the FPGA I O lines is read at the same clock cycle across all the devices Note The quality of synchronization is only as good as the quality of Sample Clock locking Some static skew may exist You can calibrate to eliminate this skew if necessary The following figure shows the relationship between the time that the master device reads a Reference Trigger Ref Trig and the time that all the devices read the synchronized version of the Reference Trigger Synchronized Ref Trig This synchronization requires CPTR alignment on all the devices Figure 8 Reading the Reference Triggers Sample Clock CPTR Device A CPTR Device B Ref Trig Synchronized Ref Trig NI 5792R User Manu
37. s registers on all programmable devices such as the analog to digital converter ADC Programming registers on these devices allows for more advanced configuration Note You can configure the LO using the User Command interface Use the FAM Registers Bus interface to program the LO synthesizer then use the User Command interface to configure the LO filters Refer to the MI FlexRIO Help for more information about NI FlexRIO CLIP items how to configure the NI 5792 with a socketed CLIP and for a list of available socketed CLIP signals Programmable Chips You can program the following chips from the CLIP Chip Part Number ADC TI ADS4249 Clock Distribution ADI AD9511 EEPROM SST25VF080B Programmable RF Attenuator Peregrine PE43703 Using Your NI 5792R with a LabVIEW FPGA Example VI Note You must install the software before running this example Refer to the NI FlexRIO FPGA Installation Guide and Specifications for more information about installing your software The NI FlexRIO Adapter Module Support software includes an example project to help you get started creating your LabVIEW FPGA application This section explains how to use an existing LabVIEW FPGA example project to acquire samples with the NI 5792R 12 NI 5792R User Manual and Specifications ni com For more detailed information about acquiring data on your NI 5792R refer to the streaming example available at lt labview gt examples i
38. seceeesseceseesseeeee 1 84 kS s to 250 MS s gt 4 ADCs are dual channel components with each channel assigned to I and Q respectively 5 The NI 5792 decimates the data rate using Fractional Decimation DSP blocks implemented in the LabVIEW FPGA target NI 5792R User Manual and Specifications National Instruments 29 CLK IN Front Panel Connector Frequency Reference Clock ccececeeceeseeseeseeseeeeeeeeees 10 MHz Sample ClOck cceeccececeseeteeteeneeneeneeee 250 MHz Amplitude SQUAL Crist ssicisls ates ESE 0 7 Vpk pk to 5 0 Vpk pk into 50 Q typical Sinepes 1 4 Vok pk to 5 0 Vok pk el VRMS to 3 5 Vrms into 50 Q typical Input impedance ce eeeseesecseceeceseesenseeseeneene 50 Q nominal COUPLING sactan asa AC CLK OUT Front Panel Connector Interface standard ecccecceceeceteeeeeeeeeeneeee 3 3 V LVCMOS Interface logic Maximum Vo scecccssessscessesseceseesseseseesseeeee 0 55 V Minimum V4 essessceecseeesessenseeseeseeseeeeeeees 2 7V Maximum Vy seeeecescseceseeseeceeseeseeseeseeseeeees 3 6V Output impedance see eeeeeeeeereeeeee 50 Q 20 Coupling DC LCC eva ells esti cecntianeadtant a E32 MA Dimensions and Weight DIMENSIONS 3553 ssi sass Masten deees i aed hei A eee 12 9 x 2 0 x 12 1 cm 5 1 x 0 8 x 4 7 in WSIS as a A ek oP St AAA Sra 413 g 14 6 oz ess fa Sak eee cess a n debrat e anans RX IN LO OUT LO IN CLK IN CLK OUT POWT nihe hisel aea EEES case 6 W AUX I O Port 0 DIO l
39. t 0 3 gt Port 1 DIO lt 0 3 gt and PFI lt 0 3 gt Number of channels ccceceeecseseeeereeeeeeeees 12 bidirectional 8 DIO and 4 PFI Connector typen er rne aia EnA ecient HDMI Interface standard ccceececcssceseeeeteeeeeeseeee 3 3 V LVCMOS 30 NI 5792R User Manual and Specifications ni com Interface logic Maximum Vyp ceecceccsccssesseeceeseeseeseeseeseeeees 0 8 V Minimum V1p eeeeeceeeeseeceeceeceeseeseeeeeeeeeeeeees 2 0 V Maximum VoL Minimum V oppesstsssssessiecsethsapentenseeesaagtieas 2 7V Maximum Vp eeecesceccesesseeceeseeseeseeseeeeeeees 3 6 V 50 Q 20 2 mA Pull down resistor ceesesesseeeeesereeeceseneeeeee 150 kQ Recommended operating voltage ceeeeee 0 3 V to 3 6 V Overvoltage protection sssees eseese E10 V Maximum toggle frequency ceeeseseeseeseereeee 6 6 MHz 5 V MAXIMUM POWE ee ceeeeeeeesereeeeeeeeeeeee 10 mA 5 V voltage tolerance cscs eeteeeeeeeereeeeee 42Vto5V Environment Maximum altitude ee ceeeeeeeeeereeseeeeeeeeee 2 000 m at 25 C ambient temperature Pollution Degree cee ssseeeeeesenereeeeeeeeeee 2 Indoor use only Operating Environment Ambient temperature range cceceseseeseereeee 0 C to 55 C Tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 Relative humidity range eeeeeeeeeereeeee 10 to 90 noncondensing Tested in accordance with IEC 60068 2 56 NI 5792R User Manual and Spec
40. t uncertainty or drift Typical values may not be verified on all units shipped from the factory Unless otherwise noted typical values cover the expected performance of units over ambient temperature ranges of 23 C 5 C with a 90 confidence level based on measurements taken during development or production Nominal values or supplemental information describe additional information about the product that may be useful including expected performance that is not covered under Specifications or Typical values Nominal values are not covered by warranty Related Information Front Panel and Connector Pinouts on page 5 Connecting Cables on page 3 NI 5792 User Manual and Specifications on page 1 NI 5792R User Manual and Specifications National Instruments 21 RX IN RX IN Amplitude Range RX input attenuation eee eeeeeeeeeeeeeeee 0 dB to 63 5 dB in 0 25 dB steps Absolute Amplitude Accuracy Note All values are typical Table 5 Absolute Amplitude Accuracy Center Frequency Absolute Amplitude Accuracy Temperature 23 C 5 C dB gt 200 MHz to 1 GHz 0 55 gt 1 GHz to 2 GHz 0 55 gt 2 GHz to 3 GHz 0 65 gt 3 GHz to 3 9 GHz 1 3 gt 3 9 GHz to 4 4 GHz 1 6 improve performance Performance is verified over the first 45 dB of RX attenuation Note Correction coefficients in EEPROM are valid only when the baseband Note Absolute amplitude accuracy uses a correction coefficient i
41. te Values are based on two input tones spaced 1 MHz apart such that the tones are 6 db less than full scale with 0 dB of RX attenuation Gain Compression Note All values are nominal Table 10 Gain Compression Frequency Temperature 23 C 5 C dBm gt 200 MHz to 1 GHz 20 gt GHz to 2 GHz 18 NI 5792R User Manual and Specifications National Instruments 25 Table 10 Gain Compression Continued Frequency Temperature 23 C 5 C dBm gt 2 GHz to 3 9 GHz 15 gt 3 9 GHz to 4 4 GHz 12 Note Values are based on two input tones spaced 250 MHz apart with 0 dB of RX attenuation and with one tone placed out of band Dynamic Range ei Note All values are nominal Table 11 Dynamic Range at 900 MHz Reference Level IP dBm Noise Floor Dynamic Range dB dBm dBm Hz 5 25 138 109 15 15 148 109 25 5 158 109 35 4 167 109 Note The signal level of each tone is set to 6 dB less than the reference level to prevent overload Dynamic range 2 3 x IP3 Noise Floor Table 12 Dynamic Range at 2 400 MHz Reference Level IP dBm Noise Floor Dynamic Range dB dBm dBm Hz 5 21 142 109 15 12 151 109 25 2 161 109 35 3 166 109 Note The signal level of each tone is set to 6 dB less than the reference level to prevent overload Dynamic range 2 3 x IP Nois

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