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UPD78F4225GC-8BT-A

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1. Ii V jj etw zs ID NZ Ld E m W Y E t r ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 18 0 0 709 a 0 5x19 9 5 0 10 0 020x0 748 0 374 0 004 B 11 77 0 463 b 0 25 0 010 C 0 5x19 9 5 0 020x0 748 0 374 5 3 0 209 0 5 0 020 5 3 0 209 0 5x19 9 5 0 020x0 748 0 374 e 91 3 0 051 11 77 0 463 f 3 55 00 140 G 18 0 0 709 g 90 3 0 012 H 0 5 0 020 h 1 85 0 2 0 073 0 008 1 58 0 062 3 5 0 138 J 1 2 0 047 j 2 0 0 079 K 7 64 0 301 k 3 0 0 118 L 1 2 0 047 1 0 25 0 010 M 1 58 0 062 m 14 0 0 551 N 1 58 0 062 n 1 4 0 2 0 055 0 008 1 2 0 047 1 4 0 2 0 055 0 008 7 64 0 301 h 1 8 1 3 h 0 071 0 051 Q 1 2 0 047 q 0 59 0 000 0 197 R 1 58 0 062 r 5 9 0 232 S 3 55 600 140 S 0 8 0 031 T C 2 0 C 0 079 t 2 4 0 094 U 12 31 0 485 u 2 7 0 106 V 10 17 0 400 v 3 9 0 154 w 6 8 0 268 TGK 080SDW G1E x 8 24 0 324 14 8 0 583 2 1 4 0 2 0 055 0 008 User s Manual U12697EJ4V1UD APPENDIX C EMBEDDED SOFTWARE The following embedded software is available for more efficient program development or maintenance of the uPD784225 Subseries Real Time Operating System RX78K4 real time OS This is a real time OS complying with the uITRON specification The RX78K4 nucleus and tools to create multiple information tables configurator have been added Use the RX78K4 in combinatio
2. 90 5 1 Port 106 5 2 Configuration 107 5 3 Port Mode Registers and Output Latch Settings When Using Alternate Functions 130 6 1 Configuration of Real Time Output ua was h upaqa niae 135 6 2 Operation for Manipulating Real Time Output Buffer Registers 2 137 6 3 Operation Modes and Output Triggers of Real Time Output 139 7 1 REI ESI rere reer 142 8 1 Configuration of 16 Bit Timer Event Counter a neni 146 8 2 Valid Edge of TIOO Pin and Capture Trigger of 00 148 8 3 Valid Edge of TIO1 Pin and Capture Trigger of 00 148 8 4 Valid Edge of TIOO Pin and Capture Trigger 01 149 9 1 Configuration of 8 Bit Timer Event Counters 1 2 181 10 1 Configuration of 8 Bit Timers 5 arid 6 2 2 Susana asas sassa tsk aaa 201 11 1 Interval Time of Interval uuu numasqa eren R rina 215 11 2 Configuration of Watch iiia 216 11 3 Interval Time f Interval uu g n n a as ri er Eee dd deeded 219 13 1 Configuratio
3. 8 4 1 Operation as interval timer 16 bits u 842 PPGOoutput operatiOm 8 4 3 User s Manual U12697EJ4V1UD 13 8 4 4 Operation as external event counter ti area NNi aN 166 8 4 5 Operation to output SQUatGNWaV8 u 168 8 4 6 Operation to output one shot pulse u 170 8 5 Sa s 176 CHAPTER 9 8 TIMER EVENT COUNTERS 1 2 180 91 idi rcc 180 meii 181 9 2 Control Hegislels niente nini edu LL eM IM DILE 184 E EO e EET IN 189 9 4 1 Operation as interval timer 8 bit operation u 189 9 4 2 Operation as external event counter u u 193 943 Operation to output square wave 8 bit 194 9 4 4 Operation to output 8 bDit PWM ierit
4. 309 18 5 3 Transfer direction specification 309 18 5 4 Acknowledge signal nn ana tetn nnne tenetis 310 18 55 StOD CODOITIOD Ir aie a 311 User s Manual U12697EJAV1UD 15 185 6 AWalt sig al WAIT u ua u awama 312 18 5 7 JPG interrupt request INTINGO u Lun tot cuir anasan e erais niiet 314 18 5 8 Interrupt request INTIICO generation timing and wait control 332 18 5 9 Address match detection iiie ni tici ease tdt ne L 333 E mail 333 18 5 11 Extended CodeS zu y ICE RUE n Ere Ete Ed Eoi e Ent 334 J8 5 12 ADAIG N gonnen raia ea re a ap aiaa a E Aai 334 18 5 13 Wake up TUNCHON eea E ade eats 336 18 5 14 GomrmunicationireserVvatigm 12 eren tede 337 18 5 15 Additional Cautloris e rente rape te udo printed enge asss 340 16 5 16 COMMUNICATION Operation econtra emet elec ea retia Edo a creer 341 18 6 Timing Charts eH t 343 CHAPTER 19 CLOCK OUTPUT FUNCTION J J J J J J nnne 350 19 t Uil f
5. 2 1 P01 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P15 ANI5 P16 ANI6 P17 ANI7 AVss P130 ANO0 P131 ANO1 AVREF1 P70 SI2 RXD2 P71 SO2 TxD2 P72 SCK2 ASCK2 P20 SI1 RxD1 P21 SO1 TxD1 P22 SCK1 ASCK1 P23 PCL P24 BUZ O P25 SIO SDAQNete O 26 500 O P27 SCKO SCLOQNete O P40 ADO O P41 AD1 O O AN O Q GQ OOOOOOOOOOOOOO 22 eo lt isp St n Vssi P56 A14 O P51 A9 O P57 A15 P42 AD2 P44 AD4 P45 AD5 O P46 AD6 O P47 AD7 P50 A8 O P52 A10 0 OOO qun lt lt lt st LO wo LO aaa P60 A16 P61 A17 P62 A18 O P63 A19 P64 RD 9 30 31 32 33 34 35 36 37 38 39 40 60 O RESET O P127 RTP7 O P126 RTP6 O P125 RTP5 O P124 RTP4 O P123 RTP3 O P122 RPT2 I O P121 RTP1 H O P120 RTPO H O P37 EXA O P36 TIO1 O P35 TI00 O P34 Tl2 O P33 TH O P32 TO2 O P31 TO1 O P30 TOO H O P67 ASTB O P66 WAIT O P65 WR Notes 1 The SDAO and SCLO pins are provided only for the u PD784225Y Subseries 2 The VPP pin is provided only in the wPD78F4225 and 78F4225Y User s Manual U12697EJ4V1UD 35 CHAPTER 1 OVERVIEW 36 Cautions 1 Connectthe TEST pin directly to a Vsso or pull down For the pull down connection use of a resistor with a resistance between 470 Q and 10 kQ is reco
6. u 495 24 7 Low Power Consumption 497 24 7 1 Setting low power consumption mode T L L U u aw Ona qaqaqa 497 24 7 2 Returning to main system clock operation 498 24 7 3 Standby function in low power consumption 499 CHAPTER 25 RESET FUNCTION 504 CHAPTER 26 ROM CORRECTION csseeccsseeceseeceeeseseesneeeesseeseseeeeeesneeessaeeeesneesseaeesesneeesssaesaseaeees 506 26 1 ROM Correction FUNCIONS LLULLU A Den eate ua lead asado exu Rcx Rene ER dS 506 26 2 ROM Correction Configuration U seen u uuu u u u J 508 26 3 Control Register for ROM Correction 510 26 4 Usage of ROM Correction U U u u u u u 511 26 5 Conditions for Executing ROM Correction U u u u u 512 CHAPTER 27 uPD78F4225 AND uPD78F4225Y 513 27 1 Internal Memory Size Switching Register IMS u 514 27 2 Flash Memory Overwriting J sienne nennen nnnm nnn tnn u u u u J 515 27 3 On B
7. 1 5 Function List uuu a ua 1 6 Differences Between uPD784225 Subseries Products and uPD784225Y Subseries Products eR DEBER E CHAPTER 2 PIN FUNCTIONS 5 itti ient L l 21 dente 2 2 Pin Function Description 2 3 Pin I O Circuits and Recommended Connection of Unused Pins CHAPTER 3 CPU ARCHITECTURE enirn noc 3 1 Memory Sp te iem 3 2 intemal ROM Area J lll ll Ai Yan De uev n SEU Oe aa Der YE 33 u Etc 3 3 1 Vector table area 2 E ee iisas aa sss 3 3 2 instruction table area r 3 3 3 CALLF instruction entry area u ee eee 3 4 Internal Data Area eere SIII cenavenccenmansuucecdenesvecectastnndeasnndecnesreetdendceanedasecedes 3 4 1 Interrial PAN er ct occisis teneur eia oe totes rrrrereneer reece LORI E sS Or 3 4 Special function register SFR area sse nennen nennen nennt 34 3 External SFR area eerte nter 3 5 External Memory Sp
8. 428 MEE Uaec 429 22 42 Counting Number of Edges orienter egre tib cR epe laqaq ash 429 22 43 Interrupt Request Generation and Acknowledgment Unit Clock 1 fcuk 431 User s Manual U12697EJ4V1UD 25 LIST OF FIGURES 7 8 Figure No Title Page 23 1 Format of Memory Expansion Mode Register MM a 438 23 2 Format of Programmable Wait Control Register 1 PWC1 a 439 23 3 HPD784224 a nai a aa a a 441 23 4 uPD784225 Memory ee 443 23 5 Instruction Fetch from External Memory in External Memory Expansion Mode 446 23 6 Read Timing for External Memory in External Memory Expansion 447 23 7 External Write Timing for External Memory in External Memory Expansion Mode 448 23 8 Read Modify Write Timing for External Memory in External Memory Expansion Mode 449 23 9 Read Write Timing by Address Wait 450 23 10 Read Timing by Access Walt FUNCION opsionni aaa 454 23 11 Write Timing by Access Wait 456 23 12 Timing by External Wait Signals ssie
9. rs rya y y x 198 Operation enabled Interrupt Operation Count starts request stopped generated Level inverted Counter cleared User s Manual U12697EJ4V1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 5 Cautions 1 Error when the timer starts An error of up to 1 clock occurs before the match signal is generated after the timer is started This is because 8 bit timer counters 1 and 2 TM1 TM2 are started asynchronously to the count pulse Figure 9 11 Start Timing of 8 Bit Timer Counter TM1 TM2 count value Timer starts 2 Operation after the compare register is changed while the timer is counting If the value after 8 bit compare registers 10 and 20 CR10 CR20 changes is less than the value of 8 bit timer counter 1 and 2 TM1 TM2 counting continues overflows and counting starts again from 0 Consequently when the value M after CR10 and CR20 change is less than the value N before the change the timer must be restarted after CR10 and CR20 change Figure 9 12 Timing After Compare Register Changes During Timer Counting CR10 CR20 N X TM1 TM2 count value XA X x X fX FFFFH 0000H 0001H 0002H Caution Except when the TI1 TI2 input is selected always set TCE1 0 TCE2 0 before setting the STOP mode Remark gt gt 3 TM1 TM2 read out during timer operation Since the count clock stops temporarily when TM1 and TM2 are read during operation select a wavefor
10. 335 18 5 Walt TIMES DEBER 337 19 1 Configuration of Clock Output Function 0 351 20 1 Configuration of Buzzer Output Function nennen nennen 354 22 1 Interrupt Request Service Modes L enne 359 22 2 Interrupt Request Sources 360 22 3 364 22 4 Flag List of Interrupt Control Registers for Interrupt Requests 365 22 5 Multiple Interrupt Servicing c un a u eee ade de ee 387 22 6 Interrupts for Which Macro Servicing Can Be Used 394 22 7 Interrupt Acknowledge Processing Time seen 432 22 8 Macro Service Processing Time L nnne tenen nennen 433 23 1 Pin Functions in External Memory Expansion 437 23 2 Pin States in Ports 4 to 6 in External Memory Expansion 437 23 3 Settings of Program Wait Control Register 2 PWC2 439 23 4 P37 EXA Pin Status im Each ModE cse ciere eret eterna ener ape caer a 461 24 1 Standby FunctiomModes iie EGER C CLE HD LL Lt 463 24 2 Operating States HALT Mode nenne nennen neret inneren neni 471 24 3 Releasing HALT Mode and Operation
11. 458 23 13 Configuration of External Access Status Output 459 23 14 Format of External Access Status Enable Register EXAE 460 23 15 Example of Local Bus Interface Multiplexed Bus u 462 24 1 Standby Function State Transito sssini iana oiea taniri ea 464 24 2 Format of Standby Control Register 5 466 24 3 Format of Clock Status Register PCS a 467 24 4 Format of Oscillation Stabilization Time Specification Register OSTS 469 24 5 Operations After Releasing HALT Mode cecccesceseeeeeseeeeaeeeeeeseaeesseeseaeessaeeeaeessaeseaeeseeeeseeseaeeeaeees 474 24 6 Operations After Releasing STOP Mode U u 483 24 7 Releasing STOP Mode by NMI ln putes u n aa a aqa Ce a arin 486 24 8 Example of Releasing STOP Mode by INTPO to INTP5 Input 487 24 9 Operations After Releasing IDLE 0 2 00 2 2 0 0000 000000 nennen 491 24 10 Example of Handling Address Data BUS u 496 24 11 Flow for Setting Subsystem Clock Operation UL us u uuu as aqata asas qaqusqa kasus 497 24 12 Setting Timing for Subsystem Clock Operation
12. 498 24 13 Flow to Restore Main System Clock Operation 499 24 14 Timing for Restoring Main System Clock Operation 499 25 1 Oscillation of Main System Clock in Reset Period a 504 25 2 Receiving Reset Signal 1 u to rdi incertus iex Set pest Teneo eire Rack eame ates Sd Lene a Reus 505 26 1 ROM Correction Block uku u S u uns S esa Su sns SS eS Eo LAS E a 508 26 2 Memory Mapping Example 784225 509 26 3 Format of ROM Correction Address Register 509 26 4 Format of ROM Correction Control Register CORO 510 27 1 Format of Internal Memory Size Switching Register 5 514 27 2 Format of Communication Mode Selection 0 4 0 0 0 0 nennen 517 27 3 Connection of Flashpro IIl in 3 Wire Serial I O Mode When Using 3 Wire Serial I O 0 518 27 4 Connection of Flashpro IIl 3 Wire Serial Mode When Using Handshake 518 27 5 Connection of Flashpro Ill in UART Mode When Using 519 26 User s Manual U12697EJ4V1UD LIST OF FIGURES 8 8 Figure No Title Page 29 1 Power Supply Voltage and Clock Cycle Time CPU Clock Frequency fCPU 553 29 2 Power Supply Voltage and Cloc
13. 199 9 12 Timing After Compare Register Changes During Timer Counting 199 10 1 Block Diagram of 8 Bit Timers Sang O srona reet inae edet nda seed ue aaraa as 201 10 2 Format of 8 Bit Timer Mode Control Register 5 TMCS sse 204 10 3 Format of 8 Bit Timer Mode Control Register 6 205 10 4 Format of Prescaler Mode Register 5 PRM5 u u 206 10 5 Format of Prescaler Mode Register 6 6 207 10 6 Timing of Interval Timer Operation U 209 10 7 Timing of Operation Based on CRn0O Transitions 212 10 8 Cascade Connection Mode with 16 Bit 213 10 9 Start Timing of 8 Bit Timer COURtel iiie eee Ee LEID IRE SEES 214 10 10 Timing After Compare Register Changes During Timer 214 11 1 Block Diagrami of Watch TIMET u n 216 11 2 Format of Watch Timer Mode Control Register 218 11 3 Operation Timing of Watch Timer Interval 220 12 1 Block Diagram of Watchdog Tim8et ga sse ayau neret enne 221 12 2 Format of Watchdog Timer Mode Register WDM 1 223 13 1 Block Diagram of A D Conve
14. Output latch P20 P22 Internal bus PM20 PM22 PU Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal 110 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS Figure 5 5 Block Diagram of P21 P23 to P24 and P26 PU21 PU23 PU24 PU26 Vpp P ch Internal bus PU PM RD WR A Output Latch P21 P23 P24 P26 P21 SO1 TxD1 P23 PCL PM21 PM23 PM24 5 26 Alternate function Pull up resistor option register Port mode register Port 2 read signal Port 2 write signal User s Manual U12697EJ4V1UD P24 BUZ P26 SO0 111 CHAPTER 5 PORT FUNCTIONS 3 a o g Figure 5 6 Block Diagram of P25 P ch A D 72 eee P25 SIO SDAONete Note SDAO pin applies only to the uPD784225Y Subseries 112 PU PF PM RD WR Pull up resistor option register Port function control register Port mode register Port 2 read signal Port 2 write signal User s Manual U12697EJ4V1UD 777 CHAPTER 5 PORT FUNCTIONS Figure 5 7 Block Diagram of P27 P ch Alternate function 7 3 a s c o 2 uc Ot P27 SCKO SCLONete Alternate function Note SCLO pin applies o
15. Watchdog timer interrupt is held pending because WDT4 0 Pending watchdog timer interrupt is serviced d When an NMI request is generated twice during NMI service program execution Main routine NMI request ra NMI request NMI request Held pending since NMI service program is being executed Held pending since NMI service program is being executed NMI request was generated twice or more but is only acknowledged once User s Manual U12697EJAV1UD 381 CHAPTER 22 INTERRUPT FUNCTIONS Cautions 1 382 Macro service requests are acknowledged and serviced even during execution of a non maskable interrupt service program To avoid macro service processing being performed during a non maskable interrupt service program manipulate the interrupt mask register in the non maskable interrupt service program to prevent macro service generation The RETI instruction must be used to return from a non maskable interrupt Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used Refer to Section 22 12 Restoring Interrupt Function to Initial State when a program is to be restarted from the initial status after a non maskable interrupt acknowledgement Non maskable interrupts are always acknowledged except during non maskable interrupt service program execution except when a high non maskable interrupt request is generated during execution of a low priority non mas
16. ertet cas Een teneri D a 363 PLE Mare Ie aero e ds 363 22 3 Interrupt Servicing Control Registers u u u uu u 364 22 9 1 Jriterrupt control registers locirani UL L Au treten ete LES Enea 366 22 3 2 Interrupt mask registers MK1 u nnne nene 370 22 3 3 In service priority register 372 22 3 4 Interrupt mode control register IMC a 373 22 3 5 Watchdog timer mode register WDM 374 22 3 6 Interrupt selection control register SNMI 375 22 3 Program status word PSW u u niaaa 376 22 4 Software Interrupt Acknowledgment Operations l l u 377 22 41 BRK instruction software interrupt acknowledgment operation 377 22 4 BRKCS instruction software interrupt software context switching acknowledgment EE 377 16 User s Manual U12697EJ4V1UD 22 5 Operand Error Interrupt Acknowledgement Operation 378 22 6 Non Maskable Interrupt Acknowledgment Operation
17. Cascade connection mode connection with TM5 Caution When selecting the TM6 operation mode using TMC66 or selecting discrete cascade connection mode using TMC64 stop the timer operation in advance To stop the timer operation during cascade connection clear both bit 7 TCE5 of 8 bit timer mode control register 5 TMC5 and bit 7 TCE6 of TMC6 User s Manual U12697EJAV1UD 205 CHAPTER 10 8 BIT TIMERS 5 6 2 Prescaler mode registers 5 and 6 PRM5 PRM6 This register sets the count clock of 8 bit timer counters 5 and 6 TM5 TM6 PRM5 and PRM6 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PRM5 and PRM6 to 00H Figure 10 4 Format of Prescaler Mode Register 5 PRM5 Address OFF6CH After reset OOH R W Symbol 7 6 5 4 2 1 0 Count clock selection fxx 4 3 13 MHz fxx 8 1 56 MHz fxx 16 781 kHz fxx 32 391 kHz fxx 128 97 6 kHz fxx 512 24 4 kHz Other than above Setting prohibited Cautions 1 If data different from that of PRM5 is written stop the timer beforehand 2 Be sure to set bits to 7 of PRM5 to 0 Remark Values in parentheses apply to operation at fxx 12 5 MHz 206 User s Manual U12697EJAV1UD CHAPTER 10 8 BIT TIMERS 5 6 Address OFF6DH After reset OOH R W Symbol PRM6 Figure 10 5 Format of Prescaler Mode Register 6 PRM6 4 3 2 1 0 rae Tes Count clock selection
18. IIC0 Data IIC0 Data MSTSO L STTO L WREL0 L INTIICO TRCO Send Note Release the slave wait by either IICO FFH or setting WRELO 348 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 21 Slave Master Communication Example When Master and Slave Select 9 Clock Wait 3 3 3 Stop condition Master device process IOO s ICO FHM IC0 lt Address ACKD0 STD0 SPD0 WTIMO H ACKEO d MSTSO STTO A SPTO WREL0 Note INTIICO ni Pt SPIEO 1 TRCO Transfer lines SCLO 1 2 SDAO S 6 AA Slave device process 25 CR lt Data ACKDO STDO SPDO WTIMO H ACKEO H MSTSO L STTO L SPTO L WRELO INTIICO When SPIEO 1 TRC0 Note Release the slave wait by either IICO FFH or setting WRELO User s Manual U12697EJAV1UD 349 CHAPTER 19 CLOCK OUTPUT FUNCTION 19 1 Functions The clock output function is used to output the clock supplied to a peripheral LSI or carrier output during remote transmission The clock selected by the clock output control register CKS is output from the PCL P23 pin To output the clock pulse follow the procedure described below 1 Select the output frequency of the clock pulse while clock pulse output is disabled with bits 0 to 3 CCSO to CCS3 2 Set the P23
19. OFFB2H Serial clock prescaler mode register 0Note 2 OFFB4H Slave address register 0Note 2 2218 OFFB6H 12C bus status register ONote 2 a S S OFFB8H Serial shift register 0Note 2 Notes 1 These are the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed F0000H is added to this value 2 Only in the uPD784225Y Subseries User s Manual U12697EJAV1UD 87 CHAPTER 3 CPU ARCHITECTURE AddressNote 1 OFFCOH Table 3 6 Special Function Register SFR List 4 4 Special Function Register SFR Name Standby control register OFFC2H Watchdog timer mode register OFFC4H Memory expansion mode register OFFC7H Programmable wait control register 1 Bit Manipulation Unit After Reset 1 Bit 16 Bits OFFC8H OFFC9H Programmable wait control register 2 OFFCEH Clock status register OFFCFH Oscillation stabilization time specification register OFFDOH to OFFDFH External SFR area OFFEOH Interrupt control register INTWDTM WDTIC OFFE1H Interrupt control register INTPO PICO OFFE2H Interrupt control register INTP1 PIC1 OFFESH Interrupt control register INTP2 PIC2 OFFE4H Interrupt control register INTP3 PIC3 5 Interrupt control
20. 0 289 17 4 Format of Serial Operation Mode Register 0 290 User s Manual U12697EJAV1UD 23 LIST OF FIGURES 5 8 Figure No Title Page 17 5 Wire Serial W O Mode TIMING vcs uyu Sun cers it ponte T eem etes cue endi irme dh 291 18 1 Serial Bus Configuration Example in IC Bus 293 18 2 Block Diagram of Clocked Serial Interface Bus 2 404424 11 0020 02000 294 18 3 Format of 2 Bus Control Register 0 IICCO sss nnns 296 18 4 Format of 2 Bus Status Register 0 50 301 18 5 Format of Prescaler Mode Register 0 for Serial Clock 304 18 6 Pir Cobfiguratioli scienti E LI MEI E 307 18 7 Serial Data Transfer Timing Of PC Bus aa 308 18 8 ER 308 18 9 0 655 309 18 10 Transfer Direction Specification 309 18 111 Acknowledge SIGH all rd aus sm m ac lu 310 ISP MEE ren EE 311 18 19 Wait SIigiial csi nu ue us Susa aaa NEM LL MAS dri EIER 312 18 14 Example of Arbitration Timing iere tete e t rette ie deer wed ie ender 335 18 15 Timing of Communication Reservation ssssssssee
21. AX mem Operand A byte AX mem Operation A CY A byte Flag Z AC P V CY lt r byte r CY r byte saddr byte saddr CY lt saddr byte sfr byte sfr CY lt sfr byte Pis rCYerer A saddr2 A CY lt A saddr2 r saddr r CY lt r saddr r saddr CY saddr r r sfr r CY r sfr sfr r sfr CY sfr r saddr saddr saddr lt saddr saddr A saddrp A CY A saddrp A saddrg A CY A saddrg saddrp A saddrp CY lt saddrp A saddrg A saddrg CY saddrg A A laddr16 A CY lt A addr16 A lladdr24 A A addr24 laddr16 A addr16 CY addr16 A lladdr24 A addr24 CY addr24 A A mem A CY A mem mem A mem CY mem A User s Manual U12697EJ4V1UD lt lt lt cxx cy lt lt lt lt lt lt lt lt lt lt lt lt 527 CHAPTER 28 INSTRUCTION OPERATION Mnemonic 528 Operand A byte Operation A CY A byte CY r byte r CY r byte CY saddr byte saddr CY saddr byte CY sfr byte sfr CY lt sfr byte CY nr r CYcre r CyY A saddr2 A CY
22. fxx 4 fxx 8 fxt recommended fxr Main system clock oscillation control Use oscillator internal feedback resistor is used Stop oscillator internal feedback resistor is not used Normal operation mode HALT mode automatically cleared upon release of HALT mode STOP mode automatically cleared upon release of STOP mode IDLE mode automatically cleared upon release of IDLE mode impaired When setting the EXTC bit of OSTS to 1 a clock with the opposite phase of the clock input to the X1 pin must be input to the X2 pin 2 Execute a NOP instruction three times after a standby instruction after standby release Otherwise if conflict occurs between standby instruction execution and an interrupt request the standby instruction is not performed and the interrupt request is acknowledged after the execution of several instructions The instructions executed before the interrupt request is acknowledged are instructions whose execution is started within 6 clocks following execution of the standby instruction User s Manual U12697EJ4V1UD CHAPTER 4 CLOCK GENERATOR Example MOV STBC byte NOP NOP NOP 3 When 2 0 the oscillation of the main system clock does not stop even if is set to 1 refer to 4 5 1 Main system clock operations Remarks 1 fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency fxr Subsystem clock
23. s OFF37H Pull up resistor option register 7 Notes 1 These values are when the LOCATION OH instruction is executed When the LOCATION 0FH instruction is executed F0000H is added to these values 2 Since each port is initialized in the input mode by a reset OOH is not actually read out The output latch is initialized to 0 User s Manual U12697EJ4V1UD 85 CHAPTER 3 CPU ARCHITECTURE Table 3 6 Special Function Register SFR List 2 4 Bit Manipulation Unit AddressNote 1 Special Function Register SFR Name After Reset 1 Bit 8 Bits 16 Bits zs OFF3CH Pull up resistor option register 12 OFF40H Clock output control register OFF42H Port function control register 2Note 2 OFF4EH Pull up resistor option register 0 OFF50H 8 bit timer counter 1 OFF51H 8 bit timer counter 2 OFF52H Compare register 10 8 bit timer event counter 1 OFF53H Compare register 20 8 bit timer event counter 2 OFF54H 8 bit timer mode control register 1 OFF55H 8 bit timer mode control register 2 OFF56H Prescaler mode register 1 OFF57H Prescaler mode register 2 OFF60H 8 bit timer counter 5 OFF61H 8 bit timer counter 6 OFF64H Compare register 50 8 bit timer 5 OFF65H Compare register 60 8 bit timer 6 OFF68H 8 bit timer mode control register 5 OFF69H 8 bit timer mode control register 6 OFF6CH Pr
24. 20 3 Control Registers The buzzer output function is controlled by the following two registers Clock output control register CKS Port 2 mode register PM2 1 Clock output control register CKS This register sets the frequency of the buzzer output CKS is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CKS to 00H Remark CKS provides a function for setting the clock for PCL output in addition to setting the buzzer output frequency Figure 20 2 Format of Clock Output Control Register CKS Address OFF40H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Buzzer output buzzer Stop buzzer output Start buzzer output Buzzer output frequency selection fxx 210 12 2 kHz fxx 211 6 1 kHz fxx 212 3 1 kHz fxx 213 1 5 kHz CLOE Clock output control Refer to Figure 19 3 CCS3 CCS2 CCS1 CCSO Clock output frequency selection Refer to Figure 19 3 Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 Figures in parentheses apply to operation with fxx 12 5 MHz User s Manual U12697EJAV1UD 355 CHAPTER 20 BUZZER OUTPUT FUNCTIONS 2 356 Port 2 mode register PM2 This register sets port 2 input output in 1 bit units When the P24 BUZ pin is used as the buzzer output function set the output latches of PM24 and P24 to 0 2 is set by a 1 bit or 8 bit memory manipulation instruction RESE
25. 412 22 29 Parallel Data Input TIMING u u asas 413 22 30 Macro Service Data Transfer Processing Flow 415 22 31 Type C Macro Service Channel n intact del caet e side ede eee beer 418 22 32 Stepper Motor Open Loop Control by Real Time Output 420 22 39 Data Transfer Control TIMING i i cts eL PEE ERE Re PEE 421 22 34 Single Phase Excitation of 4 Phase Stepper Motor 423 22 35 1 2 Phase Excitation of 4 Phase Stepper Motor 423 22 36 Automatic Addition Control Ring Control Block Diagram 1 When Output Timing Varies Willi t 2 Phiase EXCITATIOTI Aussa aeai 424 22 37 Automatic Addition Control Ring Control Timing Diagram 1 When Output Timing Varies withil 2 Phase seii eenaa iaa 425 22 38 Automatic Addition Control Ring Control Block Diagram 2 1 2 Phase Excitation Constant Velocity Operation a aaa a E aA a E T R ENESA 426 22 39 Automatic Addition Control Ring Control Timing Diagram 2 1 2 Phase Excitation Constant Velocity Operation 5e n Adel a ke 427 22 40 Macro Service Data Transfer Processing Flow Counter
26. Deletion of timer output from Table 10 1 Configuration of 8 Bit Timers 5 and 6 Modification of Figure 10 1 Block Diagram of 8 Bit Timers 5 and 6 Modification of caution in 1 8 bit timer counters 5 and 6 TM5 TM6 Modification of caution in 2 8 bit compare registers 50 and 60 CR50 CR60 Modification of description in 1 8 bit timer mode control registers 5 and 6 TMC5 TMC6 Modification of Figure 10 2 Format of 8 Bit Timer Mode Control Register 5 TMC5 Modification of Figure 10 3 Format of 8 Bit Timer Mode Control Register 6 TMC6 Modification of Figure 10 4 Format of Prescaler Mode Register 5 PRM5 Modification of Figure 10 5 Format of Prescaler Mode Register 6 PRM6 Modification of Figure 10 6 Timing of Interval Timer Operation Modification of caution in 10 4 2 Operation as interval timer 16 bit operation Modification of Figure 10 8 Cascade Connection Mode with 16 Bit Resolution CHAPTER 10 8 BIT TIMERS 5 6 Modification of Table 11 1 Interval Time of Interval Timer Modification of Figure 11 1 Watch Timer Block Diagram Modification of Figure 11 2 Format of Watch Timer Mode Control Register WTM Modification and addition of caution to Figure 11 3 Operation Timing of Watch Timer Interval Timer CHAPTER 11 WATCH TIMER Modification of Figure 12 1 Watchdog Timer Block Diagram Modification of description in 12 3 2 Interrupt priority order CHAPTER 12 WATCHDOG TIMER Modification of Figure 13 2 Format of
27. INTIICO Prescaler mode register 0 for the serial clock SPRMO amped brea ona Internal bus 294 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 1 2 3 4 5 6 7 8 9 Serial shift register 0 IICO The IICO register converts 8 bit serial data into 8 bit parallel data and 8 bit parallel data into 8 bit serial data IICO is used in both transmission and reception The actual transmission and reception are controlled by writing and reading IICO IIC0 is set by an 8 bit memory manipulation instruction RESET input sets IICO to OOH Slave address register 0 SVAO When used as a Slave this register sets a slave address SVAO is set by an 8 bit memory manipulation instruction RESET input sets SVAO to OOH SO latch The SO latch holds the output level of the SDAO pin Wake up controller This circuit generates an interrupt request when the address setin slave address register 0 SVAO and the receive address match or when an extended code is received Clock selector This selects the sampling clock that is used Serial clock counter The serial clock that is output or input during transmission or reception is counted to check 8 bit data communication Interrupt request signal generator This circuit controls the generation of the interrupt request signal INTIICO The 12 interrupt request is generated by the following two t
28. INTTMn l CRn0 transition TMn overflows since M lt N e Operated by CRn0 transition M gt N Countcock_ LE U U LILI LILI LU LU uu 1 N OiH NJ oth 1 CRn0 H INTTMn CRn0 transition Remark n 1 2 192 User s Manual U12697EJAV1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 4 2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to the TI1 P33 and TI1 P34 pins with 8 bit timer counters 1 and 2 TM1 TM2 Each time the valid edge specified by prescaler mode registers 1 and 2 PRM1 PRM2 is input TM1and TM2 are incremented The edge setting is selected to be either the rising edge or falling edge If the count of TM1and TM2 matches the values of 8 bit compare registers 10 and 20 CR10 CR20 TM1and TM2 are cleared to 0 and an interrupt request signal INTTM1 2 is generated and INTTM2 are generated each time the values of the TM1 and TM2 match the values of CR10 and CR20 Figure 9 7 Timing of External Event Counter Operation with Rising Edge Is Specified TIn pin input V V V V V V V V V V V V V V CRn0 N INTTMn Remark N to FFH n 1 2 User s Manual U12697EJAV1UD 193 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 4 3 Operation to output
29. In the master When the start condition is generated In the slave When 1 is input to the LSB of the first byte transfer direction specification bit If a wait is cancelled by setting bit 5 WRELO of I C bus control register 0 IICCO at the ninth clock while bit 3 TRCO of 12C bus status register 0 IICSO is 1 TRCO is cleared and the SDAO line becomes high impedance User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 4 Format of 2 Bus Status Register 0 IICSO 3 3 Acknowledge detection The acknowledge is not detected The acknowledge is detected Clear condition ACKDO 0 Set condition ACKDO 1 When the stop condition is detected At the rising edge of the first clock in the next byte Cleared by LRELO 1 When IICEO 1 gt 0 When RESET is input The start condition is not detected When the SDAO line is low at the rising edge of the ninth clock of SCLO The start condition is detected This indicates the address transfer period Clear condition STDO 0 Set condition STDO 1 When the stop condition is detected At the rising edge of the first clock of the next byte after transferring the address Cleared by LRELO 1 When IICEO 1 gt 0 When RESET is input The stop condition is not detected When the start condition is detected The stop condition is detected Communication is ended by
30. DACS0 gt write l AVreF1 D A conversion setting register 1 DACS1 D A conversion setting register 0 DACS0 2R ANO1 P131 AVss ANOO P130 DAM1 DACE1 DAM0 DACE0 Internal bus 1 D A conversion setting registers 0 and 1 DACS0 DACS1 DACS0 and DACS1 set the analog voltages that are output to the ANO0 and ANO1 pins respectively DACS0 DACS1 are set by 8 bit memory manipulation instruction RESET input sets DACS0 and DACS1 to 00H The analog voltages output by the ANO0 and ANO pins are determined by the following equation D A converter mode register 0 DAM0 D A converter mode register 1 DAM1 DACSn ANOn output voltage AVREF1i 256 n 0 1 Cautions 1 Inthe real time output mode when the data set in DACSO and DACS 1 is read before the output trigger is generated the set data is not read and the previous data is read 2 In the real time output mode set the data of DACSO and DACS 1 until the next output trigger is generated after the output trigger is generated User s Manual U12697EJ4V1UD 249 CHAPTER 14 D A CONVERTER 14 3 Control Registers D A converter mode registers 0 and 1 DAMO DAM1 The D A converter is controlled by D A converter mode registers 0 and 1 DAM0 DAM1 These registers enable or stop the operation of the D A
31. Prescaler Prescaler 22 Clock to peripheral hardware Selector iid System IDLE fx pe controller oscillator STOP or bit 2 of STBC m m MCK 1 when selecting subsystem 8 clock clock as CPU clock 8 Internal system clock Note This controller secures the oscillation stabilization time after releasing STOP mode User s Manual U12697EJ4V1UD 91 CHAPTER 4 CLOCK GENERATOR 4 3 Control Registers 1 Standby control register STBC 92 This register is used to set the standby mode and select the internal system clock For details of the standby mode refer to CHAPTER 24 STANDBY FUNCTION A write operation can be performed only using dedicated instructions to avoid entering the standby mode due to an inadvertent program loop These dedicated instructions MOV STBC and byte have a special code structure 4 bytes The write operation is performed only when the opcode of the 3rd byte and 4th byte are complements of each other When the 3rd byte and 4th byte are not complements of each other the write operation is not performed and an operand error interrupt is generated In this case the return address saved in the stack area indicates the address of the instruction that caused the error Therefore the address that caused the error can be determined from the return address that is saved in the stack area If a return from an operand erro
32. Project Manager Ver 3 12 or Later Windows Based U14610E Documents related to development tools hardware user s manuals Document Name Document No IE 78K4 NS In Circuit Emulator U13356E IE 784225 NS EM1 Emulation Board U13742E IE 784000 R In Circuit Emulator U12903E Documents related to flash memory writing Document Name Document No PG FP3 Flash Memory Programmer User s Manual U13502E Other documenis Document Name Document No SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769E Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution Therelated documenis listed above are subject to change without notice Be sure to use the latest version of each document for designing User s Manual U12697EJAV1UD 11 CONTENTS CHAPTER 1 OVERVIEW Jf NE Dole 12 Ordering NfO MATON uu 1 3 Pin Configuration Top View I UU nennen nennen nnn asss usss usss sasa ta nass manna 14 Block Diagram
33. User s Manual U12697EJ4V1UD 423 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 36 Automatic Addition Control Ring Control Block Diagram 1 When Output Timing Varies with 1 2 Phase Excitation Macro service control word macro service channel 1M memory space Internal RAM 1237FEH 1237FCH 1256 123402H Output timing 123400H tle 123007H Output data 8 items 123000H 00 00H MR 08H l RC 08H l l p Channel pointer SAH Mode Addition register 7FH Type C MPT MPD incremented 2 byte timer data automatic addition control interrupt request generation at MSC 0 16 bit capture compare register 00 L Buffer register RTBL P120 To stepper External P122 motor connection 16 bit timer counter 0 TM0 P123 Remark Internal RAM addresses in the figure the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed OF0000H should be added to the values in the figure 424 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 37 Automatic Addition Control Ring Control Timing Diagram 1 When Output Timing Varies with 1 2 Phase Excitation FFFFH TM1W Count value At9 At8 re OH x 4 Count starts INTP2 TOO Compare regist
34. lt 5 5 0 2 50 2 7 V lt Voo lt 4 5 V 1 9 V lt Voo lt 2 7 V ASCK high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 1 9 V lt Voo lt 2 7 V User s Manual U12697EJ4V1UD 581 CHAPTER 29 ELECTRICAL SPECIFICATIONS 3 Serial Operation Ta 40 to 85 C AVpp 1 9 to 5 5 V Vss AVss 0 V 2 2 d I C bus mode uPD78F4225Y only Parameter Standard Mode High Speed Mode MAX SCLO clock frequency Bus free time between stop and start conditions Hold timeNote1 HD STA Low level width of SCLO clock High level width of SCL0 clock Setup time of start restart conditions Data hold When using tHD DAT time CBUS compatible master When using 12 QNote 2 bus Data setup time 100Note 4 Rise time of SDAO and 20 0 1CbNote 5 SCLO signals Fall time of SDAO and 20 0 1CbNote 5 SCLO signals Setup time of stop condition Pulse width of spike restricted by input filter Load capacitance of each bus line Notes 1 For the start condition the first clock pulse is generated after the hold time 2 To fill the undefined area of the SCLO falling edge it is necessary for the device to provide an internal SDAO signal on with at least 300 ns of hold time 3 If the device does not extend the SCLO
35. 7 8 50 P50 to P57 Port 5 These pins constitute an 8 bit I O port In addition to I O port pins they also function as an address bus LEDs can be directly driven The following operation modes can be specified in 1 bit units a Port mode These pins function as an 8 bit I O port Input or output can be specified in 1 bit units by means of the port 5 mode register When used as an input port pull up resistors can be connected in 8 bit units with bit 5 PUO5 of the pull up resistor option register b Control mode These pins function as the middle address bus pins A8 to A15 in the external memory expansion mode If PUOS 1 pull up resistors can be connected P60 to P67 Port 6 These pins constitute an 8 bit I O port In addition to I O port pins they also function as an address bus and control signal outputs in the external memory expansion mode The following operation modes can be specified in 1 bit units a Port mode These pins function as an 8 bit I O port Input or output can be specified in 1 bit units by means of the port 6 mode register When used as an input port pull up resistors can be connected in 8 bit units with bit 6 PUO6 of the pull up resistor option register b Control mode These pins function as the higher address bus pins A16 to A19 in the external memory expansion mode P64 to P67 function as the control signal output pins RD WR WAIT ASTB in the external memory expansion mode If
36. A CY A laddr16 A CY A addr16 C A lladdr24 A CY A addr24 CY laddr16 A addr16 lt addr16 A CY lladdr24 A addr24 CY lt addr24 A CY A mem A CY A mem CY mem A mem CY mem A CY User s Manual U12697EJAV1UD lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt CHAPTER 28 INSTRUCTION OPERATION Mnemonic CMP Operand A byte Operation A byte Flag AC P V CY lt r byte r byte saddr byte saddr byte sfr byte sfr byte nr r r A saddr2 A saddr2 r saddr r saddr saddr r saddr r r sfr r sfr sfr r sfr r saddr saddr saddr saddr A saddrp A saddrp A saddrg A saddrg saddrp A saddrp A saddrg A saddrg A A laddr16 A addr16 A lladdr24 A addr24 laddr16 A addr16 A lladdr24 A addr24 A A mem A mem mem A mem A User s Manual U12697EJ4V1UD lt lt lt E lt lt lt lt lt E lt lt lt m lt 531 CHAPTER 28 INSTRUCTION OPERATION Mnemonic Operand Bytes 532 A byte Operation A AAbyte F
37. EP 78230GC R Emulation probe Probe to connect the in circuit emulator and the target system For 80 pin plastic QFP GC 8BT type EV 9200GC 80 Conversion socket refer to Figures B 2 and B 3 Conversion socket to connect the EP 78230GC R and a target system board on which an 80 pin plastic QFP GC 8BT type can be mounted Remarks 1 The TGK 080SDW is a product made by Tokyo Eletech Corporation For further information contact Daimaru Kogyo Ltd Tokyo Electronics Department TEL 81 3 3820 7112 Osaka Electronics Department TEL 81 6 6244 6672 2 The EV 9200GC 80 is sold in sets of 5 3 The TGK 080SDW is sold individually 606 User s Manual U12697EJAV1UD APPENDIX B DEVELOPMENT TOOLS B 3 2 Software SM78K4 System simulator This enables debugging at the C source level or assembler level while simulating operation of the target system on the host machine The SM78K4 operates on Windows By using the SM78K4 logic verification and performance verification can be performed separately to hardware development without using an in circuit emulator thus improving development efficiency and software quality Use the SM78K4 in combination with the device file DF784225 sold separately Part number 5 78 4 Remark The xxxx part number differs depending on the host machine and operating system used LUSxxxxSM78K4 ID78K4 NS Integrated debugger supporting in circuit emulator
38. Integrated debugger Device file Embedded software Real time OS mk Host machine PC or EWS Interface board Flash memory In circuit emulator writing environment um Interface adapter Flash programmer Flash memory write adapter On chip flash memory product Emulation probe Conversion socket or conversion adapter Target system Remark Parts enclosed by broken lines vary depending on the product Refer to B 3 1 Hardware 602 User s Manual U12697EJAV1UD APPENDIX B DEVELOPMENT TOOLS B 1 Language Processing Software SP78K4 78K IV Series Development tools software common to the 78K IV Series are combined in this software package package Part number uSxxxxSP78K4 RA78K4 Assembler package Program that converts a program written in mnemonic to an executable microcontroller object code In addition this assembler package has functions to create symbol tables and optimize branch instructions etc automatically Use this in combination with the device file DF784225 sold separately Caution on using in PC environment Although the assembler package is a DOS based application it can be used in the Windows environment by using the Project Manager included in the assembler pack age on Windows Part number uSooxxRA78K4 CC78K4 C compiler package Program that converts a program written in C language to an executable microcontroller object code Use this in co
39. WHL 1 C C 4 End if C 20 or CY 1 User s Manual U12697EJAV1UD 547 CHAPTER 28 INSTRUCTION OPERATION 28 3 Lists of Addressing Instructions 1 8 bitinstructions The values enclosed by parentheses are combined to express the A description as r MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC SHR SHL ROR4 ROL4 DBNZ PUSH POP MOVM XCHM CMPME CMPMNE CMPMNC CMPMC MOVBK XCHBK CMPBKE CMPBKNE CMPBKNC CMPBKC Table 28 1 8 Bit Addressing Instructions Second laddri6 mem NoneNote 2 operand lladdr24 saddrp WHL First operand saddrg A MOV MOV MOV Nete 6 MOV MOV MOV MOV ADDNee XCH XCH XCH Nete6 XCH XCH XCH ADD Nete 1 ADD Nete 1 ADD Notes 1 6 ADD Note 1 ADDNote 1 ADDNote 1 ADD Note 1 MOV MOV MOV MOV MOV MOV RORNote 3 ADDNote1 XCH XCH XCH XCH ADD Note 1 ADDNote 1 ADDNote 1 ADDNote 1 MOV Mov Note6 MOV MOV ADDNote 1 ADD Note 1 AppNote 1 XCH ADDNote 1 MOV MOV MOV Note 1 Note 1 Note 1 ADD ADD ADD laddr16 MOV MOV MOV lladdr24 ADDNote 1 mem MOV saddrp ADDNote 1 saddrg mem3 STBC WDM TDE MOV MOVBKNote 5 TDE ADD Note 1 MOVMNote 4 Notes 1 ADDC SUB SUBC AND OR XOR and CMP are identical to ADD 2 There is no second operand or the second operand is not an operand addres
40. 0 091 00 062 0 201 Tim O m Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL http www necel com pkg en mount index html User s Manual U12697EJ4V1UD 611 APPENDIX B DEVELOPMENT TOOLS 2 Package drawing of the conversion adapter TGK 080SDW Combined with the emulation probe and mounted on the board Figure B 7 TGK 080SDW Package Drawing Reference Unit mm ja A D Inm p R 1 ht t z _ Q Pipe 4 p o ME iQ b toe TQ M2 screw GRE UIS p E 57 ete qo sd a ie E T HS gt iN 1JJJ LLLM H n 3 ANNI Protrusion 4 places m Note Made by TOKYO ELETECH Corp 612 lt
41. 592 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Clock Timing twxH je twxL X1 XT1 Data Retention Characteristics STOP mode setting Voo RESET NMI Cleared by falling edge NMI Cleared by rising edge User s Manual U12697EJ4V1UD 593 CHAPTER 30 PACKAGE DRAWINGS 80 PIN PLASTIC QFP 14x14 detail of lead end rS NOTE ITEM MILLIMETERS Each lead centerline is located within 0 13 mm of A 17 20 0 20 its true position T P at maximum material condition 14 00 0 20 14 00 0 20 17 20 0 20 0 825 0 825 0 32 0 06 0 13 0 65 1 60 0 20 0 80 0 20 0 17 8 89 0 10 1 40 0 10 0 125 0 075 o 7 3 30 1 70 MAX P80GC 65 8BT 1 D O o z r x I o T o o 594 User s Manual U12697EJ4V1UD CHAPTER 30 PACKAGE DRAWINGS 80 PIN PLASTIC TQFP FINE PITCH 12x12 detail of lead end NOTE Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition User s Manual U12697EJ4V1UD rs pP Y Y R L U Q ITEM MILLIMETERS 14 0 0 2
42. 7 When a productis first written after shipment erase write and write only are both taken as one rewrite Example P Write E Erase Shipped product P gt E gt P gt E gt P rewrites Shipped product gt ES P gt E gt P gt E gt P rewrites Remarks 1 The range of the operating clock during flash memory programming is the same as the range during normal operation 2 When using the PG FP3 the time parameters that need to be downloaded from the parameter files for write erase are automatically set Unless otherwise directed do not change the set values User s Manual U12697EJ4V1UD 587 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29 3 Timing Charts AC Timing Measurement Points 1 uPD784224 784225 784224Y 784225Y Vop 1V 0 8Vpp or 1 8 V 0 8Vpp or 1 8 V Points of measurement 0 8V 0 8 V 0 45 V 2 uPD78F4225 78F4225Y Vop 1V 0 8Vpp or 1 9 V 0 8Vpp or 1 9 V Points of measurement 0 8 V 0 8 V 0 45 V 588 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Timing Waveforms 1 Read operation CLK tcvk A8 to A19 output Higher address TDAID ADOtoAD7 ___HiZ_ __ Lower address Joe Lower address 1 0 output output 5 5 gt tOHsTLA ASTB output RD output WAIT
43. A saddr2 CY r saddr r CY r saddr CY saddr r saddr lt saddr r CY r Sfr CY r sfr CY sfr r sfr CY lt sfr r CY saddr saddr saddr CY saddr saddr CY A saddrp A CY A saddrp CY A saddrg A CY A saddrg CY saddrp A saddrp CY lt saddrp A CY saddrg A saddrg CY lt saddrp A CY A laddr16 A CY A addr16 CY A lladdr24 A lt A addr24 CY laddr16 A addr16 lt addr16 A CY lladdr24 A addr24 lt addr24 A CY A mem A CY A mem CY mem A mem CY lt mem A CY User s Manual U12697EJ4V1UD lt lt S lt xx lt lt S lt lt lt lt lt lt S lt lt CHAPTER 28 INSTRUCTION OPERATION Mnemonic SUB Operand A byte Operation A CY A byte Flag AC P V CY lt r byte r CY r byte saddr byte saddr lt saddr byte sfr byte sfr CY sfr byte nr r CYer r A saddr2 A CY A saddr2 r saddr CY lt r saddr saddr r saddr CY lt saddr r r sfr r CY r sfr sfr r sfr CY sfr r saddr saddr saddr CY lt saddr
44. Address float time from RD Voo 5 0 V 10 0 Voo 3 0 V 10 0 Voo 2 0 V 10 0 Data input time from address Voo 5 0 V 10 2 5 a n T 37 Voo 3 0 V 10 2 5 a n T 52 Voo 2 0 V 10 2 5 a n T 120 Data input time from ASTBL tpsrip Voo 5 0 V 10 2 n T 35 Voo 3 0 V 10 2 50 Voo 2 0 V 10 2 n T 80 Data input time from RD Remark 1 fxx bo Main system clock frequency Voo 5 0 V 10 1 5 n T 40 Voo 3 0 V 10 1 5 n T 50 Voo 2 0 V 10 a 1 during address wait otherwise 0 n Number of wait states n gt 0 User s Manual U12697EJ4V1UD 1 5 n T 90 559 CHAPTER 29 ELECTRICAL SPECIFICATIONS 1 Read write operation 2 3 Parameter Delay time from ASTBL to RD Conditions Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 10 Data hold time from RDT Voo 5 0 V 10 0 Voo 3 0 V 10 0 Voo 2 0 V 10 0 Address active time from RDT Voo 5 0 V 10 0 5T 2 Voo 3 0 V 10 0 5T 12 Voo 2 0 V 10 0 5T 35 Delay time from to ASTBT Voo 5 0 V 10 0 5T 9 Voo 3 0 V 10 0 5T 9 Voo 2 0 V 10 0 5T 40 RD low level width Voo 5 0 V 10 1 5 T 25 Voo 3 0 V 10 1 5 T
45. CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 11 Configuration for Pulse Width Measurement with Free Running Counter fxx 4 8 fxx 16 3 16 bit timer counter 0 INTTM3 00 35 16 bit capture compare register 01 CR01 INTTM01 Internal bus Figure 8 12 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with Both Edges Specified it 00 pin input l EE NM TEM 1 Value loaded V V V INTTMO1 OVFO Caution For simplification purposes delay due to noise elimination is not taken into consideration in the capture operation by TIOO pin input and in the interrupt request generation timing in the above figure For a more accurate picture refer to Figure 8 14 CRO1 Capture Operation with Rising Edge Specified 160 User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TI00 P35 and TI01 P36 pins can be measured when 16 bit timer counter 0 TM0 is used as a free running counter refer to Figure 8 13 When the edge specified by bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 is input to the TIOO P35 pin the value of the TMO is loaded to 16 bit capture compare register 01 CRO1 and external interrupt request signal 01 is set When the edge specified
46. CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 17 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with Rising Edge Specified t mmo coun vane Xon ooo Koo Koe X 1 X9 X o d o4 LE Value loaded to CRO1 ij Value loaded Y 3 1 8 94 J Y INTTM01 Bs D N n Y S cu lt _ TIOO pin input Caution For simplification purposes delay due to noise elimination is not taken into consideration in the capture operation by TIOO pin input and in the interrupt request generation timing in the above figure For a more accurate picture refer to Figure 8 14 CR01 Capture Operation with Rising Edge Specified 164 User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 4 Pulse width measurement by restarting When the valid edge of the TIOO P35 pin is detected the pulse width of the signal input to the TIOO P35 pin can be measured by clearing 16 bit timer counter 0 TMO once and then resuming counting after loading the count value of TMO to 16 bit capture compare register 01 CRO1 Refer to Figure 8 18 The edge of the TIOO P35 pin is specified by bits 4 and 5 500 and 501 of prescaler mode register 0 PRMO The rising or falling edge can be specified The valid edge is detected through sampling at the count clock cycle selected by prescaler mode register 0 PRMO and the capture operation is not performed u
47. CY lt rpis rpo lt 0 rpma rpm x n lt mem3 s o mem3 7 4 mem3 s o lt mem3 z 4 14 Bit manipulation instructions MOV1 AND1 OR1 XOR1 NOT1 SET1 CLR1 Mnemonic Operand CY saddr bit lt mem3 7 4 mem3 s o lt Aa o mem3 7 4 mem3 s o Operation CY lt saddr bit Flag S Z AC P V CY CY sfr bit CY c sfr bit CY X bit CY lt X bit CY A bit CY lt Abit CY PSWL bit CY PSW bit CY PSWH bit CY PSWh bit CY laddr16 bit CY lt laddr16 bit CY laddr24 bit CY lt lladdr24 bit CY mem2 bit N NN N CY lt mem2 bit saddr bit CY saddr bit CY sfr bit CY sfr bit CY X bit CY X bit CY A bit CY A bit CY PSWL bit CY PSWL bit lt CY PSWH bit CY PSWh bit CY laddr16 bit CY laddr16 bit CY lladdr24 bit CY lladdr24 bit lt CY mem2 bit CY 538 N O ay NO N N mem2 bit CY User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION Mnemonic AND1 Operand CY saddr bit Operation CY CYA saddr bit Flag s Z AC P V CY CY saddr bit CY CYA saddr bit CY sfr bit CY lt CYA str bit CY sfr bit CY CYA sfr bit CY X bit CY
48. Clear condition WRELO 0 Note Set condition WRELO 1 Automatically cleared after execution Setbyan instruction When RESET is input Disable Enable Clear condition SPIEO 0 Note Set condition SPIEO 1 Cleared by an instruction Setbyan instruction When RESET is input Note This flag signal becomes invalid by setting IICEO to 0 User s Manual U12697EJAV1UD 297 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 3 Format of I2C Bus Control Register 0 IICCO 2 4 wrMO Control of wait and interrupt request generation Interrupt request generated at the falling edge of the eighth clock For the master After the eighth clock is output wait with the clock output low For the slave After the eighth clock is input the master waits with the clock low Interrupt request generated at the falling edge of the ninth clock For the master After the ninth clock is output wait with the clock output low For the slave After the ninth clock is input the master waits with the clock low This bit setting becomes invalid during an address transfer and becomes valid after the transfer ends In the master a wait is inserted at the falling edge of the ninth clock in an address transfer The slave that received the base address inserts a wait at the falling edge of the ninth clock after the acknowledge is generated The slave that received the extended code inserts the waits at
49. sfrp rp wl CO NINI O1 sfrp rp saddrp word saddrp word sfrp word sfrp word saddrp saddrp saddrp saddrp User s Manual U12697EJ4V1UD lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 535 CHAPTER 28 INSTRUCTION OPERATION 8 24 bit arithmetic instructions ADDG SUBG Flag Z AC P V CY Mnemonic Operand Operation rg rg rg CY lt rg rg rg imm24 rg CY rg imm24 WHL saddrg WHL CY WHL saddrg rg rg rg CY lt rg rg rg imm24 rg CY rg imm24 WHL saddrg WHL CY WHL saddrg 9 Multiplication division instructions MULU MULUW MULW DIVUW DIVUX Flag Mnemonic Operand Bytes Operation S Z AC PN CY AX AXr AX high order rp low order AXXrp AX high order rp low order AXXrp AX quotient r remainder AX rNote 1 AXDE quotient rp remainder AXDE rpNete 2 Notes 1 When r 0 r X AX FFFFH 2 When rp 0 rp DE AXDE FFFFFFFFH 10 Special arithmetic instructions MACW MACSW SACW Flag S Z AC PN CY Operation AXDE lt B X C AXDE B B 2 C C 2 byte lt byte 1 End if byte 0 or P V 1 AXDE lt B X C AXDE B B 2 C lt C 2
50. 0 5 x ES Remark INT Function returning the integer portion of the value in parentheses Analog input voltage AVop pin voltage ADCR A D conversion result register ADCR value Figure 13 5 shows the relationship between the analog input voltage and the A D conversion result Figure 13 5 Relationship Between Analog Input Voltage and A D Conversion Result 255 5 gt 2 254 c e t y A D conversion 253 Ur result ADCR 2d 0 222 1 J ue ee 0 Tessa 1 1 3 2 5 3 507 254 509 255 511 1 512 256 512 256 512 256 512 256 512 256 512 Input voltage AVop 234 User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER 13 4 3 Operation modes of A D converter Select one channel for analog input from between ANIO to ANI7 with the A D converter input selection register ADIS and commence A D conversion A D conversion can be started in the following two ways Hardware start Conversion start by trigger input P03 Software start Conversion start by setting A D converter mode register ADM In addition to this the result of A D conversion will be stored in the A D conversion result register ADCR and at the same time an interrupt request signal INTAD will be issued 1 A D conversion operation by hardware start The A D conversion operation can be made to e
51. 00040n 64 bytes 0003FH Vector table area 64 bytes 00000H FFEFFH Internal RAM 4 352 bytes External 91 912 896 bytes Internal ROM 128 KB external memory expansion mode The 4 608 bytes in this area can be used as the internal ROM only when the LOCATION 0FH instruction is executed LOCATION 0H instruction execution 126 464 bytes LOCATION 0FH instruction execution 131 072 bytes This is the base area and the entry area based on resets or interrupts However the internal RAM is excluded in a reset AYNLOALIHOYV HdldVHO CHAPTER 3 CPU ARCHITECTURE 3 2 Internal ROM Area The following products in the uPD784225 Subseries have on chip ROM that can store the programs and table data If the internal ROM area and internal data area overlap when the LOCATION OH instruction is executed the internal data area becomes the access target The overlapped internal ROM area cannot be accessed Access Space Part Number Internal ROM LOCATION OH Instruction LOCATION OFH Instruction uUPD784224 96 KB x 8 bits 00000H to OFOFFH 00000H to 17FFFH 10000H to 17FFFH uPD784225 128 KB x 8 bits 00000H to OEDFFH 00000H to 1FFFFH uPD78F4225 10000H to 1FFFFH The internal ROM can be accessed at high speed Usually a fetch is at the same speed as an external ROM fetch By setting the IFCH bit of the memory expansion mode register MM to 1 the high speed fetch fun
52. 16 Call return instructions CALL CALLF CALLT BRK BRKCS RET RETI RETB RETCS RETCSB Mnemonic Operand Bytes laddr16 Operation SP 3 lt PC 3 SP lt SP 3 PCuw lt 0 lt addr16 Flag S Z AC P V CY lladdr20 SP 3 lt 4 SP lt SP 3 lt addr20 SP 3 lt PC 2 SP lt SP 3 PCuw lt 0 lt rp SP 3 lt 2 SP lt SP 3 PC erg SP 3 PC 2 SP SP 3 PCuw lt 0 lt rg SP 3 PC 2 SP SP 3 PC lt rg laddr20 SP 3 3 SP SP 3 PC lt PC 3 jdisp16 laddr1 1 SP 3 lt PC 2 SP lt SP 2 0 PC11 lt 1 lt addr11 addr5 SP 3 lt PC 1 SP lt SP 3 PCuw lt 0 lt 5 SP 2 lt PSW SP 1 lt PC 1 uw SP 4 lt PC 1 SP SP 4 PCuw lt 0 PCiw lt 003EH lt RP2 lt PSW 92 0 n RSS lt 0 IE lt 0 RP3s 11 PCuw lt 0 lt SP SP SP 3 lt SP lt SP 3 o s PSW lt SP 2 SP lt 4 flag with the highest priority that is set to 1 in the ISPR is cleared to 0 lt SP lt SP 3 o s PSW lt SP 2 SP lt SP 4 laddr16 PSW l
53. 379 22 7 Maskable Interrupt Acknowledgment Operation 383 22 7 1 WM ctored Interr pt ccce ertet rre etd 385 221 2 Context switchibg ioi e or ek SERE HR RR ce 385 22 7 3 Maskable interrupt priority levels 4 8 4 4 387 22 8 Macro Service Function n nano nano 393 22 81 Qutline of macro service function eee decocti eire tee ta era e Reed ed pua as 393 22 8 2 Types of macro serviCing u u m nennen a nnne tnter 393 22 8 3 Basic macro 396 22 8 4 Operation at end of macro service u 397 22 8 5 Macro service control registers L u u a u u u uu Sua aiian aidaa id 400 22 8 6 Macro service Type A suu uu Aree hese Sau eee 404 22 8 Macro service type B tio mua amis HER 409 22 8 8 Macro seiviCce type ey sicut usas npe decade eol appa qua sects 414 22 8 9 Go riter mode nee SSS A Susu Ma ee 428 22 9 When Interrupt Requests and Macro Service Are Temporarily Held Pending 430 22 10 Instructions Whose Execution Is Temporarily Suspended by Interrupt or Macro SeIVIGB u enano a ade erate Sata ada deut d
54. 5 306 Serial shift register 0 0 This register performs serial communication shift operation synchronized with the serial clock Although this register can be read and written in 1 bit and 8 bit units do not write data to during a data transfer Address OFFB8H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Slave address register 0 SVAO This register stores the slave address of the 2 bus It can be read and written in 8 bit units but bit 0 is fixed to 0 Address OFFB4H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Suo 21 1 User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 4 Bus Mode Function 18 4 1 Pin configuration The serial clock pin SCLO and the serial data bus pin SDAO have the following configurations 1 5 0 I O pin for the serial clock The outputs to both the master and slave are N ch open drains The input is a Schmitt input 2 SDAO Shared I O pin for serial data The outputs to both the master and slave are N ch open drains The input is a Schmitt input Since the outputs of the serial clock line and serial data bus line are N ch open drains external pull up resistors are required Figure 18 6 Pin Configuration Vppo Slave device Master device SCL0 SCL0 Clock output k Vppo gt H Clock output Clock input gt Clock input
55. 6 Arbitration failed operation no participation after arbitration failed a When arbitration failed while transmitting slave address data AD6 to ADO D7 to DO D7 to DO A1 A2 1 50 01000110B Example Read ALDO during interrupt servicing A2 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 b When arbitration failed while transmitting an extended code AD6 to ADO D7 to DO D7 to DO 1 2 1 50 0110 010 Example Read ALDO during interrupt servicing Set LRELO 1 from the software A2 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJ4V1UD 327 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 328 c When arbitration failed during a data transfer lt 1 gt When WTIM0 0 lt 2 gt Al A2 A3 A1 IICSO 10001110B A2 50 01000000B Example Read ALDO during interrupt servicing IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 When WTIMO 1 Al A2 A A1 IICSO 10001110B A2 50 01000100B Example Read ALDO during interrupt servicing IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY d When failed in the restart condition during a data transfer lt 1 gt lt 2 gt Not an ext
56. Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY h When arbitration failed in the low data level and the stop condition was about to be generated WTIMO 1 1 Al A2 A3 A4 A1 50 1000x110B A2 50 1000xx00B 50 01000000B Example Read ALDO during interrupt servicing A4 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJAV1UD 331 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 8 Interrupt request INTIICO generation timing and wait control By setting the WTIMO bit in 12 bus control register 0 IICCO INTIICO is generated at the timing shown in Table 18 2 and wait control is performed Table 18 2 INTIICO Generation Timing and Wait Control During Slave Operation During Master Operation Address Data Reception Data Transmission Address Data Reception Data Transmission gNotes 1 2 gNote 2 gNote 2 9 8 8 gNotes 1 2 gNote 2 gNote 2 9 9 9 Notes 1 The INTIICO signal and wait of the slave are generated on the falling edge of the ninth clock only when the address set in slave address register 0 SVAO matches In this case ACK is output regardless of the ACKEO setting The slave that received the extended code generates INTIICO at the falling edge of th
57. WDM lt byte LOCATION locaddr Specification of the high order word of the location address of the SFR and internal data area SEL RBn RSS lt 0 RBS2 0 n RBn ALT RSS lt 1 RBS2 0 lt n RSS RSS No operation IE 1 Enable interrupt 546 IE 0 Disable interrupt User s Manual U12697EJAV1UD CHAPTER 28 INSTRUCTION OPERATION 20 String instructions MOVTBLW MOVM XCHM MOVBK XCHBK CMPME CMPMNE CMPMC CMPMNC CMPBKE CMPBKNE CMPBKC CMPBKNC Flag S Z AC P V CY Mnemonic Operand Operation MOVTBLW addr8 byte addr8 2 lt addr8 byte byte 1 addr8 addr8 2 End if byte 0 MOVM TDE A TDE lt lt 1 C C 1 End if C 0 TDE A TDE lt A TDE lt TDE 1 C C 1 End if C 0 TDE A TDE A TDE lt TDE 1 C C 1 End if C 0 TDE A TDE gt A TDE TDE 1 C C 1 End if C 0 TDE WHL TDE WHL TDE TDE 1 WHL lt WHL 1 C C 1 End if C 0 TDE WHL TDE WHL TDE TDE 1 WHL WHL 1 C C 1 End if C 0 TDE WHL TDE o WHL TDE lt TDE 1 WHL lt WHL 1 C C 1 End if C 0 TDE WHL TDE lt gt WHL TDE lt TDE 1 WHL WHL 1 C C 1 End if C 0 A TDE lt 1 C lt C 1 Endif C 0or Z 0 T
58. X bit 0 A bit A bit 0 PSWL bit PSWL bit lt 0 PSWH bit PSWi bit lt 0 laddr16 bit laddr16 bit 0 lladdr24 bit lladdr24 bit 0 N N NINJ mem2 bit mem2 bit 0 CY _ 540 CY 0 User s Manual U12697EJAV1UD CHAPTER 28 INSTRUCTION OPERATION 15 Stack manipulation instructions PUSH PUSHU POP POPU MOVG ADDWG SUBWG INCG DECG Flag Mnemonic Operand Operation S Z AC P V CY PSW SP 2 lt PSW SP lt 5 2 sfrp SP 2 lt SP lt SP 2 sfr SP 1 lt sfr SP lt SP 1 post SP 2 post SP SP 2 x mNote rg SP 3 lt rg SP lt SP 3 post UUP 2 lt post UUP lt UUP 2 x mNete PSW PSW lt SP SP SP 2 a sfrp sfrp SP SP lt SP 2 sfr sfr lt SP SP lt SP 1 post post SP SP SP 2 x mNote rg rg lt SP SP lt SP post SP imm24 SP WHL WHL SP post UUP UUP lt UUP 2 x mNote SP imm24 SP WHL WHL lt SP SP word SP lt SP word SP lt SP word SP lt SP 1 SP lt SP 1 SP word SP SP wm hw Note m is the number of registers specified by post User s Manual U12697EJ4V1UD 541 CHAPTER 28 INSTRUCTION OPERATION
59. input ipsrwTH mi tusrwr EXA N N User s Manual U12697EJ4V1UD 589 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 Write operation CLK A8 to A19 output ADO to AD7 output ASTB output WR output WAIT input TDAID tsasT Lower address output HHsTLA e ipsrop Data output tHwop tsopwa e Higher address Lower address output X tpaw tpwsr TADEXD toysriwr tosTWTH gt m tHsTWT d m lExADR EXA N 590 TEXTAH lExwps User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Serial Operation 1 3 wire serial I O mode tkcv1 2 SCK 2 UART mode ASCK 3 2 bus mode uPD784224Y 784225Y and 78F4255Y only Stop Start Restart Stop condition condition condition condition User s Manual U12697EJAV1UD 591 CHAPTER 29 ELECTRICAL SPECIFICATIONS Clock Output Timing en CLKOUT Interrupt Input Timing NMI twitH twit INTPO to INTP5 Reset Input Timing twRsH twnsL RESET
60. m VITATE IIS T ISTIS T IST TA Lie RTBL D12 D13 D14 Output latch 4 P127 to P124 002 D03 D04 Output latch P123 to P120 D11 D12 D13 D14 A Software processing by INTTM2 RTBH write B Software processing by INTTM1 RTBL write 140 User s Manual U12697EJ4V1UD CHAPTER 6 REAL TIME OUTPUT FUNCTION 6 5 Usage of Real Time Output Function 1 5 Disabling the real time output operation Set bit 7 RTPOE 0 in the real time output port control register RTPC Initial settings Set 0 in the output latch since the output latch and real time output are configured as a logical AND Set the port to output mode Set the initial value in the real time output buffer registers RTBH RTBL Enable real time output operation RTPOE 1 After generating the selected transfer trigger the RTBH and RTBL values are output from the pin Set the next real time output value in RTBH and RTBL by using trigger interrupt servicing or by some other means Subsequently the next real time output values are sequentially set in RTBH and RTBL by the interrupt servicing for the selected trigger 6 6 Cautions For the initial setting set bit 7 RTPOE in the real time output port control register RTPC to 0 to disable the real time output operation User s Manual U12697EJAV1UD 141 CHAPTER 7 TIMER OVERVIEW The uPD784225 784225Y Subseries includes one on chip 16 bit timer event counter two on
61. twxL X1 input rising falling 4 5 V lt Voo lt 5 5 V time txn txr 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V Cautions 1 When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as Vss e Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator 2 When the main system clock is stopped and the device is operating on the subsystem clock wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock User s Manual U12697EJAV1UD 571 CHAPTER 29 ELECTRICAL SPECIFICATIONS Subsystem Clock Oscillator Characteristics Ta 40 to 85 C Resonator Recommended Circuit Parameter Conditions Crystal Oscillation frequency fxr Vss XT2 XT1 resonator Oscillation stabilization 4 5 V Voo lt 5 5 V N timeNote 1 9 V lt Voo lt 4 5 V External XT1 input frequency fxr clock XT1 input high low level widt
62. 1 an interrupt mask flag in the interrupt mask register MK0 Macro service processing can be executed in the interrupt disabled state and during execution of an interrupt service program Figure 22 18 Macro Service Processing Sequence Generation of interrupt request for which macro service processing can be specified Macro service processing execution Data transfer real time output port control MSC MSC 1 Decrement macro service counter MSC i a Yes Interrupt service mode bit 0 Interrupt request flag 0 v Interrupt request generation Execute next instruction The macro service type and transfer direction are determined by the value set in the macro service control word mode register Transfer processing is then performed using the macro service channel specified by the channel pointer according to the macro service type The macro service channel is memory which contains the macro service counter which records the number of transfers the transfer destination and transfer source pointers and data buffers and can be located at any address in the range FE00H to FEFFH when the LOCATION OH instruction is executed or FFE00H to FFEFFH when the LOCATION OFH instruction is executed 396 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 8 4 Operation at end of macro service In macro servicing processing is performed the number of times specified during execution of another program
63. 1 in the stop condition detection state SPDO when bit 0 1 in I C bus status register 0 IICSO In addition when the start condition is detected bit 1 STDO in 50 is set to 1 308 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 2 Address The 7 bit data following the start condition defines the address The address is 7 bit data that is output so that the master selects a specific slave from the multiple slaves connected to the bus line Therefore the slaves on the bus line must have different addresses The slave detects this condition by hardware and determines whether the 7 bit data matches slave address register 0 SVAO After the slave was selected when the 7 bit data matched the SVAO value communication with the master continues until the master sends a start or stop condition Figure 18 9 Address SCLO 1 2 3 4 5 6 7 8 9 oo N ECEE Address Note INTIICO ___ 007 Note When the base address or extended code is received during slave operation INTIICO is not generated The address is output by writing the slave address and the transfer direction described in 18 5 3 Transfer direction specification to serial shift register 0 IICO as 8 bit data In addition the received address is written to IICO The slave address is allocated to the higher seven bits of IICO 18 5 3 Transfer direction specification Since the master specifies the transfer direction after the 7 bit addre
64. 12 0 0 2 12 0 0 2 14 0 0 2 1 25 1 25 0 22 0 05 0 08 0 5 T P 1 0 0 2 0 5 0 145 0 05 0 08 1 0 0 1 0 05 gu 1 150 1 0 25 0 6 0 15 P80GK 50 9EU 1 0 D Ol uz 5 r x rz G To O mD gt 595 CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS The uPD784225 784225Y Subseries should be soldered and mounted under the following recommended conditions For soldering methods and conditions other than those recommended below contact an NEC sales representative For technical information see the following website Semiconductor Device Mount Manual http www necel com pkg en mount index html Table 31 1 Soldering Conditions for Surface Mount Type 1 3 1 uPD784224GK 9EU 80 plastic TQFP fine pitch 12 x 12 uPD784224YGK xxx 9EU 80 pin plastic TQFP fine pitch 12 x 12 uPD784225GK xxx 9EU 80 plastic TQFP fine pitch 12 x 12 uPD784225YGK xxx 9EU 80 pin plastic TQFP fine pitch 12 x 12 uPD78F4225GK 9EU 80 pin plastic TQFP fine pitch 12 x 12 uPD78F4225YGK 9EU 80 plastic TQFP fine pitch 12 x 12 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or IR35 103 2 higher Count Two times or less Exposure limit 3 daysNete after that prebake at 125 C for 10 hours Package peak temperature 215 C Time 40 seconds max
65. 146 CHAPTER 8 16 BIT TIMER EVENT COUNTER 1 16 bit timer counter 0 TM0 TMO is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to OOOOH in the following cases 1 RESET is input 2 TMC03 and 02 are cleared lt 3 gt Valid edge of TIOO is input in the clear amp start mode entered by inputting valid edge of TIOO lt 4 gt Match between TMO and CR00 in the clear amp start mode entered on match between TMO and CROO lt 5 gt f bit 6 of TOCO OSPT is set or the valid edge of TIOO is input in the one shot pulse output mode User s Manual U12697EJ4V1UD 147 CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 Capture compare register 00 CR00 CR00 is a 16 bit register that functions as a capture register and as a compare register Whether this register functions as a capture or compare register is specified by using bit 0 CRC00 of capture compare control register 0 When using CR00 as compare register The value set to CR00 is always compared with the count value of 16 bit timer counter 0 TM0 When the values of the two match an interrupt request INTTM00 is generated When TM00 is used as an interval timer CR00 can also be used as a register that holds the in
66. 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 6 Timing Charts In the IC bus mode the master outputs an address on the serial bus and selects one of the slave devices from multiple slave devices as the communication target The master transmits the TRCO bit bit 3 of IC bus status register 0 IICSO that indicates the transfer direction of the data after the slave address and starts serial communication with the slave Figures 18 20 and 18 21 are the timing charts for data communication Shifting of serial shift register 0 IICO is synchronized with the falling edge of the serial clock SCLO The transmission data is transferred to the SOO latch and output from the SDAO pin with the MSB first The data input at the SDAO pin is received by IICO at the rising edge of SCLO User s Manual U12697EJAV1UD 343 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 20 Master Slave Communication Example When Master and Slave Select 9 Clock Wait 1 3 1 Start condition Address Master device process Address lt Data STD0 SPD0 WTIMO H ACKEO H MSTS0 STTO J SPTO N WRELO L INTIICO Y TRCO H Transfer lines 4 SCLO SDAO 6 X A3 X A2 AAT X AO NW N DEE Start condition Slave device process IIC0 lt FFHNete ACKD0 STD0 SPD0 Li WTIMO H ACKEO H MSTSO L STTO L SPTO
67. 21 2 Block Diagramiof POO to POS Pils innin eun u ss aqa cutee nud 358 22 1 Interrupt Control Register XXICN J LLL U a naam nnne ennt nes 367 22 2 Format of Interrupt Mask Registers mme 371 22 3 Format of In Service Priority Register ISPR imisi tiia anaedai 372 22 4 Format of Interrupt Mode Control Register 373 22 5 Format of Watchdog Timer Mode Register 374 22 6 Format of Interrupt Selection Control Register 5 375 24 User s Manual U12697EJ4V1UD LIST OF FIGURES 6 8 Figure No Title Page 22 7 Format of Program Status Word PSWL 2 1 enne nennen nennen nnns 379 22 8 Context Switching Operation by Execution of BRKCS 2 377 22 9 Return from BRKCS Instruction Software Interrupt RETCSB Instruction Operation 378 22 10 Non Maskable Interrupt Request Acknowledgment Operations 380 22 11 Interrupt Acknowledgment Processing Algorithm 2 384 22 12 Context Switching Operation by Generation of an Interrupt 385 22 13 Return from Interrupt That Uses Context Switching by Means of RETCS Instruction 386 22 14 Examples of Servicing When Another Interrupt Request Is Generate
68. 27 x 1 fw 28 x 1 fw 29 x 1 fw Other than above Setting prohibited Cautions 1 Stop the timer operation before overwriting WTM 2 Do not overwrite WTM when both the watch timer and interval timer are being used If the timer is stopped to overwrite WTM both the prescaler and timer are cleared causing an error to occur for the watch timer interrupt INTWT Remark fw Watch timer clock oscillation frequency fxx 27 or fxr bo Main system clock frequency fxr Subsystem clock oscillation frequency User s Manual U12697EJAV1UD 219 CHAPTER 11 WATCH TIMER Figure 11 3 Operation Timing of Watch Timer Interval Timer Watch timer Overflow Overflow Start SLL LLL JUUL Watch timer interrupt INTWT vs ys IL l 1 1 Interrupt time of watch timer E Interrupt time of watch timer Interval timer interrupt INTTM3 1 l l Interval time Interval time 220 nT nT Caution When enabling operation of the watch timer mode control register WTM watch timer and 5 bit counter the time until the first watch timer interrupt request INTWT is generated is not exactly the same time as set by bits 4 to 6 of WTM WTM4 to WTM6 This is because the 5 bit counter starts counting 1 cycle after 9 bit prescaler output Following the first INTWT generation the INTWT signal is generated at the set
69. 3 1 2 A 4 AS A1 50 0010x010B A2 11 50 0010x110B 50 0010x100B A4 50 0010xx00B A5 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJ4V1UD 321 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 322 b Start Code Data Start Address Data Stop lt 1 gt When WTIMO 0 SVA0 match after restart lt 2 gt Al A2 A3 4 5 1 50 0010 010 2 50 0010 000 50 0001 110 44 50 0001x000B IICSO 00000001B Remarks Always generated A Generated only when SPIE0 1 x Don t care When WTIMO 1 SVA0 match after restart 3 A4 Al A2 A A5 A6 A1 50 0010x010B A2 50 0010x110B 50 0010xx00B A4 50 0001x110B A5 50 0001 00 A6 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY c Start Code Data Start Code Data Stop lt gt When WTIMO 0 extended code received after restart lt 2 gt A4 AS A1 50 0010x010B A2 50 0010x000B 50 0010x010B A4 50 0010x000B IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care Whe
70. 30 Voo 2 0 V 10 1 5 n T 25 Address active time from wrt Voo 5 0 V 10 0 5T 2 Voo 3 0 V 10 0 5T 12 Voo 2 0 V 10 0 5T 35 Delay time from address to WR Voo 5 0 V 10 1 a T 24 Voo 3 0 V 10 1 a T 34 Voo 2 0 V 10 1 a T 70 Address hold time from WRT Voo 5 0 V 10 0 5T 14 Voo 3 0 V 10 0 5T 14 Voo 2 0 V 10 0 5T 14 Delay time from ASTBJ to data output tpsrop Voo 5 0 V 10 0 5T 15 Voo 3 0 V 10 0 5T 30 Voo 2 0 V 10 0 5T 240 Delay time from WR to data output Voo 5 0 V 10 0 5T 30 Voo 3 0 V 10 0 5T 30 Voo 2 0 V 10 0 5T 30 Delay time from ASTBJ to WR Voo 5 0 V 10 0 5T 9 Voo 3 0 V 10 0 5T 9 Voo 2 0 V 10 0 5T 20 Data setup time to WRT Remark T tcvk 1 fxx fxx Main system clock frequency Voo 5 0 V 10 1 5 n T 20 Voo 3 0 V 10 1 5 n T 25 Voo 2 0 V 10 a 1 during address wait otherwise 0 n Number of wait states n gt 0 560 1 5 n T 70 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 1 Read write operation 3 3 Parameter Conditions Data hold time from WRT Voo 5 0 V 10 0 5T 14 Voo 8 0 V 10 0 5T 14 Voo
71. 5 1 a T 70 Address hold time from WRT Voo 5 0 V 10 0 5T 14 Voo 3 0 V 10 0 5T 14 Voo 2 0 V 5 0 5T 14 Delay time from ASTBI to data output Voo 5 0 V 10 0 5T 15 Voo 3 0 V 10 0 5 30 Voo 2 0 V 5 0 5T 240 Delay time from WR to data output Voo 5 0 V 10 0 5T 30 Voo 3 0 V 10 0 5T 30 Voo 2 0 V 5 0 5T 30 Delay time from ASTBI to WR Voo 5 0 V 10 0 5T 9 Voo 3 0 V 10 0 57 9 Voo 2 0 V 5 0 5T 20 Data setup time to WRT Remark 1 fxx boc Main system clock frequency Voo 5 0 V 10 1 5 n T 20 Voo 3 0 V 10 1 5 n T 25 Voo 2 0 V 5 a 1 during address wait otherwise 0 n Number of wait states n 2 0 1 5 n T 70 User s Manual U12697EJ4V1UD 577 CHAPTER 29 ELECTRICAL SPECIFICATIONS 1 Read write operation 3 3 Parameter Data hold time from WRT Conditions Voo 5 0 V 10 0 5T 14 Voo 3 0 V 10 0 5T 14 Voo 2 0 V 5 0 5T 50 Delay time from WRT to ASTBT Voo 5 0 V 10 0 5T 9 Voo 3 0 V 10 0 5T 9 Voo 2 0 V 5 0 5T 30 WR low level width Voo 5 0 V 10 1 5 n T 25 Voo 3 0 V 10 1 5 n T 30 Voo 2 0 V 5 1 5 n T 30 Delay time f
72. 50 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care When WTIMO 1 STTO 1 SPTO 1 A1 A2 A3 44 AS A1 IICSO 10xxx110B A2 50 10xxxx00B IICSO 10xxx110B A4 50 10xxxx00B IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJ4V1UD 315 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY c Start Code Data Data Stop Extended code transmission lt 1 gt When WTIMO 0 SPTO 1 Al A2 4 A5 A1 IICSO 1010x110B A2 50 1010x000B 50 1010x000B WTIMO 1 A4 50 1010xx00B IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care lt 2 gt When WTIMO 1 1 Al A2 A4 A1 50 1010x110B A2 50 1010x100B 50 1010xx00B 4 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care 316 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 2 Slave operation when receiving slave address data SVAO match a Start Address Data Data Stop 1 When WTIMO 0 2 A1 A2 A3 A4 A1 A2 A3 A4 IICS0 0001x110B IICS0 0001x000B IICS0 0001x000B IICS0 00000001B Remarks A Always generated A Generated only when SPIE0 1 x Don
73. 784225 Subseries watchdog timer 1 The watchdog timer mode register WDM can only be written by a special instruction MOV WDM byte 2 If the RUN bit is set to 1 by writing to the watchdog timer mode register WDM write the same value every time Even when different values are written the contents written the first time cannot be changed 3 Once the RUN bit is set to 1 it cannot be reset to 0 by the software User s Manual U12697EJ4V1UD 225 CHAPTER 13 A D CONVERTER 13 1 Functions The A D converter converts analog inputs into digital values and is configured by eight 8 bit resolution channels ANI0 to ANI7 Successive approximation is used as the conversion method and conversion results are saved in the 8 bit A D conversion result register ADCR A D conversion can be started by the following two methods 1 Hardware start Conversion is started by trigger input P03 rising edge falling edge or both rising and falling edges can be specified 2 Software start Conversion is started by setting the A D converter mode register ADM Select one channel for analog input from ANI0 to ANI7 and perform A D conversion If hardware start is used A D conversion stops at the end of the A D conversion operation If software start is used the A D conversion operation is repeated Each time one A D conversion is completed an interrupt request INTAD is issued 13 2 Configuration The A D converter includes the foll
74. CYA X bit CY X bit CY CYA X bit CY A bit CY CYA A bit CY A bit CY CYA Abit CY PSWL bit CY lt CY PSWL bit CY PSWL bit CY lt CY PSWL bit CY PSWH bit CY lt CY PSWh bit CY PSWH bit lt CY PSWh bit CY laddr16 bit CY lt CY addr16 bit CY laddr16 bit CY lt CYA laddr16 bit CY laddr24 bit CY CYA laddr24 bit CY addr24 bit CY CY laddr24 bit CY mem2 bit CY lt CY meme bit CY mem2 bit N N N O O N N N N W CY CYA mem2 bit CY saddr bit CY CYV saddr bit CY saddr bit CY CYV saddr bit CY sfr bit lt sfr bit CY sfr bit CY lt CYV sfr bit CY X bit CY CYV X bit CY X bit CY CYV X bit CY A bit CY CYV A bit CY A bit CY CYV A bit CY PSWL bit lt CYV PSWL bit CY PSWL bit CY CYV PSWL bit CY PSWH bit CY CYV PSWh bit CY PSWH bit CYV PSWh bit CY laddr16 bit addr16 bit CY laddr16 bit CY addr16 bit CY laddr24 bit CY CYV Iladdr24 bit CY lladdr24 bit CY laddr24 bit CY mem2 bit CY lt mem2 bit CY mem2 bit N N ol N Mm NINI DM W CY lt CYV
75. In the PWM mode the PWM output is set to the inactive level by TCE1 O 2 If LVS1 LVR1 are read after setting data 0 is read User s Manual U12697EJAV1UD 185 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 3 Format of 8 Bit Timer Mode Control Register 2 TMC2 Address OFF55H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 2 2 count control Counting is disabled prescaler disabled after the counter is cleared to 0 Start counting TMC26 TM2 operation mode selection Clear and start mode when TM2 and CR20 match PWM free running mode Discrete mode Cascade connection mode connection with TM1 Timer output control by software No change Reset to 0 Set to 1 Setting prohibited Other than PWM mode TMC26 0 PWM mode TMC26 1 Timer output control Active level selection Disable inversion operation Active high Enable inversion operation Active low Timer output control Output disabled port mode Output enabled Caution Whenselecting the TM2 operation mode using TMC26 or selecting discrete cascade connection mode using TMC24 stop timer operation in advance To stop the timer operation during cascade connection clear both bit 7 TCE1 of 8 bit timer mode control register 1 TMC1 and bit 7 TCE2 of TMC2 Remarks 1 In the PWM mode the PWM output is set to the inactive level by TCE2 0 2 If LVS2 and LVR2 are read after
76. In the real time output mode the analog voltage is output synchronized with the output trigger In the normal mode the output analog voltages are maintained until new data is set in DACSO and DACS1 In the real time output mode after new data is set DACSO and DACS1 it is held until the next output trigger is generated Caution Set DACEO and DACE1 after data has been set DACSO and DACS1 14 5 Cautions 1 Output impedance of the D A converter Since the output impedance of the D A converter is high current cannot be taken from the ANOn pin n 0 1 If the input impedance of the load is low insert a buffer amplifier between the load and the ANOn pin In addition use the shortest possible wire from the buffer amplifier or load to increase the output impedance If the wire is long surround it with a ground pattern User s Manual U12697EJAV1UD 251 CHAPTER 14 D A CONVERTER Figure 14 3 Buffer Amplifier Insertion Example a Inverting Amplifier L1 PD784225 784225Y T R2 Ri ANOn The input impedance of the buffer amplifier is R1 b Voltage follower u PD784225 784225Y l The input impedance of the buffer amplifier is R4 If there is no and RESET is low the output is undefined 2 Output voltage of the D A converter Since the output voltage of the D A converter changes in stages use the signals output from the D A converter after passing them through a low pas
77. OFFC2H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 wom mw o o wm o wow worn Watchdog timer operation setting Stops the watchdog timer Clears the watchdog timer and starts counting WDT4 Watchdog timer interrupt request priority Watchdog timer interrupt request lt NMI pin input interrupt request Watchdog timer interrupt request gt NMI pin input interrupt request Overflow time ms 12 5 MHz Count clock fcu 217 fcu 219 fcu 220 fci 2 1 Cautions 1 The watchdog timer mode register WDM can only by written by a special instruction MOV WDM byte 2 When writing to WDM to set the RUN bit to 1 write the same value every time Even if different values are written the contents written the first time cannot be updated 3 Once the RUN bit is set to 1 it cannot be reset to 0 by the software Remark Internal system clock fxx to fxx 8 bo Main system clock oscillation frequency User s Manual U12697EJ4V1UD 223 CHAPTER 12 WATCHDOG TIMER 12 3 Operations 12 3 1 Count operation The watchdog timer is cleared by setting the RUN bit of the watchdog timer mode register WDM to 1 to start counting After the RUN bit is set to 1 when the overflow time set by bits WDT2 and WDT1 in WDM has elapsed a non maskable interrupt INTWDT is generated If the RUN bit is reset to 1 before the overflow time elapses the watchdog timer is cleared and counti
78. SAR Compares the voltage of the analog input with the voltage tap comparison voltage from the series resistor string and saves the result from the most significant bit MSB The contents of SAR will be transmitted across to the A D conversion result register after the least significant bit LSB is saved A D conversion finished A D conversion result register ADCR Holds A D conversion results At the end of each A D conversion operation the conversion result from the successive approximation register is loaded ADCR is read with an 8 bit memory manipulation operation RESET input makes ADCR undefined Sample amp hold circuit Samples analog inputs one by one as they are sent from the input circuit and sends them to the voltage comparator The sampled analog input voltages are saved during A D conversion Voltage comparator Compares the analog input voltage with the output voltage of the series resistor string Series resistor string Placed between AVpp and AVss generates the voltage that is compared with that of the analog input signal ANIO to ANI7 pins Eight analog input channels used for inputting analog data to the A D converter for A D conversion Pins not selected for analog input with the A D converter input selection register ADIS can be used as input ports Cautions 1 Use the ANIO to ANI7 input voltages within the rated voltage range Inputting a voltage equal to or greater than AVpp or equal to or smaller than
79. SDAO Data output E SDA0 p o Data output Data input Data input User s Manual U12697EJ4V1UD 307 CHAPTER 18 12 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 2 Bus Definitions and Control Method Next the serial data communication formats of the IC bus and the meanings of the signals used are described Figure 18 7 shows the transfer timing of the start condition data and stop condition that are output on the serial data bus of the 12 bus Figure 18 7 Serial Data Transfer Timing of I2C Bus n O Poi i 2 i Start Address R W ACK Data ACK Data ACK Stop condition condition The master outputs the start condition slave address and stop condition The acknowledge signal ACK can be output by either the master or slave Normally this is output on the side receiving 8 bit data The serial clock SCLO continues to be output by the master However the slave can extend the SCLO low level period and insert waits 18 5 1 Start condition When the SCLO pin is high the start condition is the SDAO pin changing from high to low The start conditions for the SCLO and SDAO pins are the signals output when the master starts the serial transfer to the slave The slave has hardware that detects the start condition Figure 18 8 Start Condition The start condition is output when bit 1 STTO of I2C bus control register 0 IICCO is set
80. TM2 have the following two modes Mode using 8 bit timer event counters 1 and 2 TM1 TM2 alone discrete mode Mode using 8 bit timer event counters 1 and 2 connected in cascade 16 bit resolution cascade connection mode These two modes are described next Mode using 8 bit timer event counters 1 and 2 alone discrete mode The timer operates as an 8 bit timer event counter with the following functions Interval timer External event counter Square wave output PWM output Mode using 8 bit timer event counters 1 and 2 connected in cascade 16 bit resolution cascade connection mode The timer operates as a 16 bit timer event counter connected in cascade with the following functions Interval timer with 16 bit resolution External event counter with 16 bit resolution Square wave output with 16 bit resolution 180 User s Manual U12697EJAV1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 2 Configuration 8 bit timer event counters 1 and 2 include the following hardware Table 9 1 Configuration of 8 Bit Timer Event Counters 1 and 2 Item Configuration Timer counter 8 bit x 2 TM1 TM2 Register 8 bit x 2 CR10 CR20 Timer output 2 TO1 TO2 Control registers 8 bit timer mode control register 1 TMC1 8 bit timer mode control register 2 TMC2 Prescaler mode register 1 PRM1 Prescaler mode register 2 PRM2 Figure 9 1 Block Diagram of 8 Bit Timer Event Counters 1 and 2 1 2 1
81. These pins can be used for port functions Refer to 16 3 2 Asynchronous serial interface UART mode 2 Communication operation c Transmission Setting prohibited When only transmission is used these pins can be used as P20 and P70 CMOS I O Refer to serial operation mode registers 1 and 2 CSIM1 CSIM2 x Don t care n 1 2 User s Manual U12697EJ4V1UD 257 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 16 2 Asynchronous Serial Interface Mode The asynchronous serial interface UART Universal Asynchronous Receiver Transmitter offers the following two modes 1 Operation stopped mode This mode is used when serial transfer is not performed to reduce the power consumption 2 Asynchronous serial interface UART mode This mode is used to send and receive the 1 byte data that follows the start bit and supports full duplex transmission A UART dedicated baud rate generator is provided on chip enabling transmission at any baud rate within a broad range The baud rate can also be defined by dividing the input clock to the ASCK pin The MIDI standard baud rate 31 25 Kbps can be used by utilizing the UART dedicated baud rate generator 16 2 1 Configuration The asynchronous serial interface includes the following hardware Figure 16 2 shows the block diagram of the asynchronous serial interface Table 16 3 Configuration of Asynchronous Serial Interface Item Configuration Registers Transmit shift
82. ii Slave CPU 1 Seis Serial clock SCLO Address 1 SDAO Slave CPU 3 SCLO Address 2 SDAO Slave IC SCLO Address 3 SDAO Slave IC SCLO Address N 18 2 Configuration The clocked serial interface in the 2 bus mode includes the following hardware Figure 18 2 is a block diagram of clocked serial interface IICO in the 2 bus mode Table 18 1 12C Bus Mode Configuration Item Configuration Registers Serial shift register O IICO Slave address register 0 SVAO Control registers 12C bus control register 0 IICCO 12C bus status register 0 IICSO Prescaler mode register 0 for serial clock SPRMO User s Manual U12697EJAV1UD 293 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 2 Block Diagram of Clocked Serial Interface I2C Bus Mode Internal bus bus status register 0 IICSO El COIO TRCO ACKDOSTDO SPDO 4 bus control register 0 IICCO WRELO Slave address spo gt register 0 SVA0 m Match Noise signal eliminator gt Serial shift register 0 IIC0 Data hold time correction circuit Acknowledge detector lt N ch open drain output Wake up controller Acknowledge 4 detector 4o Start condition detector Stop condition detector Serial clock counter Interrupt request signal generator
83. saddr A saddrp A CY A saddrp A saddrg A CY A saddrg saddrp A saddrp CY lt saddrp saddrg A saddrg CY saddrg A A laddr16 A CY lt A addr16 A lladdr24 A lt A addr24 laddr16 A addr16 CY addr16 A lladdr24 A addr24 CY addr24 A A mem A CY A mem mem A mem CY mem A User s Manual U12697EJ4V1UD lt lt lt E lt lt lt lt lt E lt lt lt m lt 529 CHAPTER 28 INSTRUCTION OPERATION Mnemonic Operand Bytes 530 A byte Operation A CY A byte CY Flag Z AC P V CY lt r byte r CY r byte CY saddr byte saddr CY saddr byte CY sfr byte sfr CY lt sfr byte CY r r LcYer r cv A saddr2 A CY A saddr2 CY r saddr r CY r saddr CY saddr r saddr CY saddr r CY r sfr r CY r sfr CY sfr r sfr CY sfr r CY saddr saddr lt saddr saddr CY A saddrp A CY saddrp A saddrg A CY saddrg CY saddrp A saddrp CY lt saddrp A CY saddrg A saddrg CY lt saddrg
84. stops for the RESET active period After the oscillation stabilization time elapses normal operation starts The difference from the normal reset operation is that the data memory saves the contents before setting the STOP mode User s Manual U12697EJAV1UD 487 CHAPTER 24 STANDBY FUNCTION 24 5 IDLE Mode 24 5 1 Settings and operating states of IDLE mode The IDLE mode is set by setting both the STP and HLT bits in the standby control register STBC to 1 STBC can only be written with 8 bit data by using a special instruction Therefore the IDLE mode is set by the MOV STBC byte instruction When interrupts are enabled the IE flag in PSW is set to 1 specify three NOP instructions after the IDLE mode setting instruction after the IDLE mode is released If this is not done after the IDLE mode is released multiple instructions can be executed before interrupts are acknowledged Inserting NOP instructions may change the order relationship between the interrupt servicing and the instruction execution so to prevent problems caused by changes in the execution order be sure to take the measures described earlier The system clock when setting the IDLE mode can be set to either the main system clock or the subsystem clock The operating states in the IDLE mode are described next 488 User s Manual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION Table 24 7 Operating States in IDLE Mode IDLE Mode Setting With Subsystem Clo
85. to SCK 2 7 V lt Voo lt 5 5 V 1 8 V lt Voo lt 2 7 V SI hold time from SCK SO output delay time from SCKL SO output hold time from SCKT c UART mode Parameter ASCK cycle time Conditions 4 5 V lt Voo lt 5 5 V 0 5tkcy2 50 2 7 V lt Voo lt 4 5 V 1 8 V lt Voo lt 2 7 V ASCK high low level width 564 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 1 8 V lt Voo lt 2 7 V User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 3 Serial Operation Ta 40 to 85 C AVpp 1 8 to 5 5 V Vss AVss 0 V 2 2 d bus mode uPD784224Y 784225Y only Parameter Standard Mode High Speed Mode MAX MIN MAX SCLO clock frequency Bus free time between stop and start conditions Hold timeNote1 HD STA Low level width of SCLO tLow clock High level width of SCLO clock Setup time of start restart conditions Data hold When using tHD DAT time CBUS compatible master When using 12 QNote 2 bus Data setup time 100Note 4 Rising time of SDAO and 20 0 1CbNote 5 SCLO signals Falling time of SDAO and 20 0 1CbNote 5 SCLO signals Setup time of stop condition Pulse width of spike restricted by input filter Load capacitance of each bus line Notes 1 For the start conditio
86. when used from FEDFH Figure 3 7 Format of Stack Pointer SP 23 0 SP User s Manual U12697EJAV1UD 75 CHAPTER 3 CPU ARCHITECTURE 76 Figure 3 8 Data Saved to Stack PUSH sfr instruction PUSH sfrp instruction Stack Stack SP SP m 2 SP 1 a Higher byte SP lt SP 1 SP 2 Lower byte SP SP 2 PUSH PSW instruction PUSH rg instruction Stack Stack ar ail 4 PSWHrto I sr 1 PSWH Undefined SP 1 Higher byte SP 2 PSWL aig Middle byte SP SP 2 SP 3 Lower byte SP SP 3 CALL CALLF CALLT instructions Vectored interrupt PUSH post PUSHU post instructions Stack Stack for PUSH AX RP2 RP3 Stack ST SP m SP 1 Undefined 190 16 PSWH tof scion pete SP 1 R7 1 PSWH4 l RP3 pe PC15 to PC8 ids PSWL SP 2 R6 SP 3 PC7 to PCO SP 3 PC15 to PC8 SP 3 R5 L RP2 SP SP 3 SP 4 PC7 to PCO SP 4 R4 SP SP 4 SP 5 A AX SP 6 SP lt SP 6 User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE Figure 3 9 Data Restored from Stack POP sfr instruction POP sfrp instruction Stack Stack SP lt SP 1 SP SP 2 SP 1 UE Higher byte T SP m SP m Lower byte POP PSW instruction POP rg instruction Stack Stack SP lt E de SP SP 3 PSWHzto PSWH ras Higher byte SP m PSWL ae
87. 0 V lt Voo 5 5 V R 10 MQ 2 0 V lt AVner AVpp AVpo 1 8 V lt Voo lt 2 0 V R 10 MQ 1 8 V lt AVner lt AVpp AVpo Settling time Load conditions 4 5 V lt lt 5 5 V C 30 pF 2 7 V lt AVrer lt 4 5 V 1 8 V lt lt 2 7 V Output resistance Ro DACS0 1 55H Reference voltage AVREF1 AVner current Alpert For only 1 channel Notes 1 Excludes quantization error 0 2 FSR 2 This value is indicated as a ratio to the full scale value FSR User s Manual U12697EJAV1UD 567 CHAPTER 29 ELECTRICAL SPECIFICATIONS Data Retention Characteristics Ta 40 to 85 C Voo AVpp 1 8 to 5 5 V Vss AVss 0 V Parameter Conditions Data retention voltage STOP mode Data retention current Vpppn 5 0 V 10 Vpppn 2 0 V 10 Vpp rise time Vpo fall time Voo hold time from STOP mode setting STOP release signal input time Oscillation stabilization Crystal resonator 30 wait time Ceramic resonator 5 Low level input voltage RESET POO INTPO to POS INTP5 0 0 1 High level input voltage 0 9VpppR Vpppn 568 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 29 2 Electrical Specifications of uPD78F4225 and 78F4225Y For the timing charts refer to 29 3 Timing Charts Absolute Maximum Ratings Ta 25 C Par
88. 0H or LOCATION 0FH POP PSW POPU post MOV PSWL A MOV PSWL byte MOVG SP imm24 Write instruction and bit manipulation instruction to interrupt control registers MK1 IMC ISPR or SNM1 register excluding BT BF instructions PSW bit manipulation instructions excluding BT PSWL bit addr20 instruction BF PSWL bit addr20 instruction BT PSWH bit addr20 instruction BF PSWH bit addr20 instruction SET1 CY instruction NOT1 CY instruction CLR1 CY instruction Note Interrupt control registers WDTIC PICO PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIICO SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMICOO TMICO1 TMIC1 TMIC2 ADIC TMIC5 TMIC6 TMIC7 TMIC8 WTIC KRIC Caution If problems are caused by a long pending period for interrupts and macro servicing when the corresponding instructions are used in succession a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an NOP instruction etc in the series of instructions 436 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 1 External Memory Expansion Function The external memory expansion function connects external memory to areas other than the internal ROM RAM and SFR A time divided address data bus is used to connect external memory A 256 byte expansion mode and a 1 MB expansion mode are supported for the external memory expansion function When external memory is connect
89. 10000H 32 768 bytes Macro service control word area 52 bytes Data area 512 bytes Note 1 Internal RAM External memory Program data area 3 584 bytes 8 072 bytes 980 736 bytes OF100H OFOFFH Program data area Internal ROM CALLF entry 61 696 bytes area 2 KB CALLT table area Internal ROM Note4 64 bytes Vector table area 00000H 64 bytes Access in the external memory expansion mode The 3 840 bytes in this area can be used as the internal ROM only when the LOCATION OFH instruction is executed LOCATION 0H instruction execution 94 464 bytes LOCATION OFH instruction execution 98 304 bytes This is the base area and the entry area based on resets or interrupts However the internal RAM is excluded in a reset 3HnlO31IHOHV HdldVHO 09 antAvr3Z269ern IenueNW 5 1951 Notes 1 FFFFFH 20000H 1FFFFH 10000H OFFFFH 00000H Access in the Figure 3 2 uPD784225 Memory On execution of LOCATION OH instruction On execution of LOCATION OFH instruction FFFFFH Special function registers SFR FFFDFH FFFDOH FFFOOH 256 bytes External memoryN 1 896 KB General purpose registers 128 bytes Internal ROM 65 536 bytes Macro service control word oFEo6H area 52 bytes Data area 512 bytes Internal RAM 4 352 bytes Program data area 3 840 bytes Internal ROM CALLF entry 60 928 bytes area 2 KB CALLT table area
90. 111 full scale 3 2LSB Integral linearity error This expresses the extent to which the conversion characteristics differ from the theoretical linear relationship The integral linearity error indicates the maximum error between the actual and theoretical measurement values when the zero scale and full scale errors are both 0 Differential linearity error This expresses the difference between the actual and theoretical measurement values of the width output by a certain code when the width output by a theoretical code is 1LSB Figure 13 10 Zero Scale Error Figure 13 11 Full Scale Error Full scale error Ideal linearity Digital output lower 3 bits Zero scale error 0 3 AVpp 2 AVpp 1 AVpp 0 1 2 3 AVDD Analog input LSB Analog input LSB User s Manual U12697EJ4V1UD 239 CHAPTER 13 A D CONVERTER Figure 13 12 Integral Linearity Error Figure 13 13 Differential Linearity Error Ideal linearity Digital output Digital output Differential linearity error Integral linearity error Analog input Analog input 8 Conversion time This expresses the time from when the analog input voltage is applied to when the digital output is obtained The sampling time is included in the conversion time value shown in the characteristic table 9 Sampling time This is the time during which the analog switch is on to allow the analog voltage to be fetched in the sample amp hol
91. 16 bit units Also four of the 16 bit registers can be combined with the 8 bit register for address expansion and manipulated in 24 bit units Each register can generally be used as the temporary storage for the operation result or the operand of the operation instruction between registers The area from OFE80H to OFEFFH during LOCATION OH instruction execution or the OFFE80H to OFFEFFH during LOCATION OFH instruction execution can be accessed by specifying an address as normal data memory whether or not it is used as the general purpose register area Since there are eight register banks in the 78K IV Series efficient programs can be written by suitably using the register banks in normal processing or interrupt servicing Each register has the unique functions shown below A R1 This register is primarily for 8 bit data transfers and operation processing It can be combined with all of the addressing modes for 8 bit data This register can be used to store bit data This register can be used as a register that stores the offset value during indexed addressing or based indexed addressing X R0 This register can store bit data AX RPO This register is primarily for 16 bit data transfers and operation results It can be combined with all of the addressing modes for 16 bit data AXDE When a DIVUX MACW or MACSW instruction is executed this register can be used to store 32 bit data B R3 This register fun
92. 2 Flash Memory Overwriting The uPD78F4225 is equipped with an on chip 128 KB flash memory The following method is available for overwriting the on chip flash memory On board overwrite mode Overwriting performed using a flash programmer Flash memory overwriting can be performed 20 times A voltage of 10 V is required for deleting and writing the flash memory 27 3 On Board Overwrite Mode The on board overwrite mode is used with the target system mounted on board Overwriting is performed by connecting a special flash programmer Flashpro III part No FL PR3 PG FP3 to the host machine or target system Overwriting is controlled via the serial interface Writing to the flash memory can be performed using the flash memory write adapter connected to Flashpro III Remark Flashpro Ill is a product of Naito Densei Machida Mfg Co Ltd On board overwrite mode settings are performed by controlling the TEST VrP and RESET The serial interface is selected according to the number of pulses applied to the pin User s Manual U12697EJAV1UD 515 CHAPTER 27 uPD78F4225 AND uPD78F4225Y PROGRAMMING 27 3 1 Selecting communication mode Flashpro Ill writes to the flash memory by serial communication The communication mode is selected from the modes shown in Table 27 3 then writing is performed The selection of the communication mode has the format shown in Figure 27 2 Each communication mode is selected acco
93. 218 User s Manual U12697EJAV1UD CHAPTER 11 WATCH TIMER 11 4 Operation 11 4 1 Operation as watch timer The watch timer operates with time intervals of 2 4 fw or 2 fw with the main system clock 4 19 MHz or subsystem clock 32 768 kHz The watch timer generates an interrupt request INTWT at fixed time intervals The count operation of the watch timer is started when bits 0 WTMO and 1 WTM1 of the watch timer mode control register WTM are set to 1 When these bits are cleared to 0 the 5 bit counter is cleared and the watch timer stops the count operation When the interval timer function is started at the same time the watch timer can be started from 0 seconds by resetting WTM1 to 0 However an error of up to 2 4 fw or 2 fw may occur when the watch timer overflows INTWT Caution A time interval of 0 5 second cannot be generated by the 12 5 MHz main system clock Use the 32 768 kHz subsystem clock to generate the 0 5 second time interval 11 4 2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request INTTM3 at intervals specified by a count value set in advance The interval time can be selected by bits 4 through 6 WTM4 through WTM6B of the watch timer mode control register WTM Table 11 3 Interval Time of Interval Timer WTMS5 WTM4 Interval Time fxx 12 5 MHz fxx 4 19 MHz fxr 32 768 kHz 2 x 1 fw 25 x 1 fw 26 x 1 fw
94. 238 13 6 CAUtlONS eec M 241 CHAPTER 14 D A CONVERTER J I aaa saa a aS 248 14 1 248 14 2 me S assqa 248 14 3 Control RegisSI rgu u LU A aus qasasqa usss ERE De 250 14 4 yu a 251 14 5 CAUtlONS ee 251 CHAPTER 15 SERIAL INTERFACE OVERVIEW 253 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL I O 255 16 1 Switching Asynchronous Serial Interface Mode and 3 Wire Serial I O Mode 256 16 2 Asynchronous Serial Interface Mode 2 u u u u 258 16 2 1 Configuration ee ate lle 258 16 2 2 Control registers a unaq sisaqa qasasqa Sa aq pa SEX Roca eua SCR viens 261 10 3 OPO neath iscsi l 266 16 3 1 Operation Stopped mode sat inrcr aaa a 266 16 3 2 Asynchronous serial interfac
95. 37 4n interrupts Context 22 switching Remarks 1 IROM Internal ROM with high speed fetch specified PRAM Peripheral RAM of internal RAM only when LOCATION OH instruction is executed in the case of branch destination IRAM Internal high speed RAM EMEM Internal ROM when external memory and high speed fetch are not specified 2 nis the number of wait states per byte necessary for writing data to the stack the number of wait states is the sum of the number of address wait states and the number of access wait states 3 Ifthe vector table is EMEM and if wait states are inserted in reading the vector table add 2 m to the value of the vectored interrupt in the above table and add m to the value of context switching where m is the number of wait states per byte necessary for reading the vector table 4 If the branch destination is EMEM and if wait states are inserted in reading the instruction at the branch destination add that number of wait states 5 Ifthe stack is occupied by PRAM and if the value of the stack pointer SP is odd add 4 to the value in the above table 6 Thenumber of wait states is the sum of the number of address wait states and the number of access wait states 432 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 11 2 Processing time of macro service The macro service processing time differs depending on the type of the macro service as shown in
96. 4 5 V 2 0 V lt Voo lt 2 7 V BR RL RR RR MT Ml wl 1 9 V lt Voo lt 2 0 V Supply voltage When detecting VPP low level When detecting VPP high level When detecting VPP high voltage Write time Operating temperature Storage temperature Programming temperature Notes 1 When rewriting without using handshake mode 2 Operation cannot be guaranteed when the number of rewrites exceeds 20 Inthe case of K standard products operation cannot be guaranteed when the number of rewrites exceeds 5 Cautions 1 If writing is not successful in the initial write operation execute the program command again and then execute the verify command to confirm that the write operation has been completed normally K standard 2 Handshake mode is supported by products other than those with the K standard Remarks 1 The fifth letter from the left in the lot number indicates the standard of the product 2 After executing the program command execute the verify command to confirm that the write operation has been completed normally 3 Handshake mode is the CSI write mode that uses P24 Handshake mode can be used with the PG FR3 and FL PR3 4 The standard only applies to ES engineering sample products Because these products are engineering samples their operation cannot be guaranteed 586 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS F
97. 5 5 V Vbo 1 0 lon 100 pANote 2 1 8 V lt Voo 5 5 V Vo 0 5 Input leakage current Vi 0 V Except X1 X2 low XT1 XT2 X1 X2 XT1 XT2 Input leakage current Except X1 X2 high XT1 XT2 X1 X2 XT1 XT2 Output leakage current low Output leakage current high Notes 1 P21 P23 P24 P26 P30 to P32 P35 to P37 P40 to P47 P50 to P57 P60 to P67 P71 P120 to P127 2 Per pin User s Manual U12697EJAV1UD 557 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics Ta 40 to 85 C Vpp AVpp 1 8 to 5 5 V Vss AVss 0 V 2 2 Parameter Conditions Supply voltage Operation 12 5 MHz Voo 5 0 V 10 mode fxx 6 MHz 3 0 V 10 2 MHz Voo 2 0 V 10 HALT mode 12 5 MHz Voo 5 0 V 10 6 MHz Voo 3 0 V 10 2 MHz Voo 2 0 V 10 IDLE mode 12 5 MHz Voo 5 0 V 10 6 MHz Voo 3 0 V 10 2 MHz Voo 2 0 V 10 Operation 32 kHz 5 0 V 10 modeNote fxx 32 kHz Von 3 0 V 10 fxx 32 kHz 2 0 V 10 HALT fxx 32 kHz Voo 5 0 V 10 modeNote 32 kHz Von 3 0 V 10 fxx 32 kHz 2 0 V 10 IDLE fxx 32 kHz 5 0 V 10 modeNote fxx 32 kHz Von 3 0 V 10 fxx 32 kHz 2 0 V 10 Data retention voltage HALT
98. 7 07 0 15 0 Note These are the addresses when the LOCATION OH instruction is executed The addresses when the LOCATION OFH instruction is executed are the sum of the above values and OF0000H Caution R4 R5 R6 R7 RP2 and RP3 be used as the X A C B AX and BC registers when the RSS bit in the PSW is set to 1 However use this function only when using a 78K lll Series program Remark When changing the register bank and when returning to the original register bank is necessary execute the SEL RBn instruction after using the PUSH PSW instruction to save the PSW to the stack If the stack position is not changed when returning to the original state the POP PSW instruction is used to return When the register banks in the vectored interrupt servicing program are updated the PSW is automatically saved on the stack when an interrupt is acknowledged and returned by the RETI and RETB instructions Therefore when one register bank is used in an interrupt servicing routine only the SEL RBn instruction is executed and the PUSH PSW or POP PSW instruction does not have to be executed Example When register bank 2 is specified PUSH PSW SEL RB2 Operation in register bank 2 POP PSW Operation in original register bank 80 User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE 3 8 2 Functions In addition to being manipulatable in 8 bit units general purpose registers can be a pair of two 8 bit registers and be manipulated in
99. 8 bit I O port Input or output can be specified in 1 bit units by means of the port 12 mode register Regardless of whether the input mode or output mode is specified pull up resistors can be connected in 1 bit units using pull up resistor option register 12 b Control mode These pins function as a real time output port RTPO to RTP7 that outputs data synchronized with a trigger When the pins specified as the real time output port are read 0 is read 10 P130 P131 Port 13 These pins constitute a 2 bit I O port In addition to I O port pins they also function as the analog outputs of the D A converter The following operation modes can be specified in 2 bit units a Port mode These pins function as a 2 bit I O port Input or output can be specified in 1 bit units by means of the port 13 mode register On chip pull up resistors are not available b Control mode These pins function as the analog outputs ANOO ANO1 of the D A converter The values are undefined when the pins specified as analog outputs are read Caution Ifthe D A converter uses only one channel when AVner lt Von use either of the following processes at pins that are not used for analog output Set the port mode register PM13X to 1 input mode and connect to Vsso Setthe port mode register PM13X to 0 output mode Set the output latch to 0 and output a low level User s Manual U12697EJAV1UD 51 CHAPTER 2 PIN FUNCTIONS 11 1 This
100. A This description corresponds to MOV R7 R5 2 Generation of instruction code in the RA78K4 In the RA78K4 when an instruction with the same function as an instruction that directly specifies A or AX in the operand column in the operation list of the instruction is used the instruction code that directly describes A or AX in the operand column is given priority and generated Example The MOV A r instruction where r is B has the same function as the MOV r instruction where r is A and r is B In addition they have the same MOV A B description in the assembler source program In this case the RA78K4 generates code that corresponds to the MOV A r instruction If A X B C AX or BC is described in an instruction that specifies r r rp or rp in the operand column the A X C AX or BC instruction code generates the instruction code that specifies the following registers based on the operand of the RSS quasi directive in the RA78K4 Register If RO to R7 and RPO to RP4 are specified for r r rp and rp in the operand column an instruction code that conforms to the specification is output Instruction code that directly describes A or AX in the operand column is not output The A B and C registers that are used in indexed addressing and based indexed addressing cannot be described as R1 R3 R2 or R5 R7 R6 3 Cautions on use Switching the RSS bit obtains the same effect as ho
101. AVss even if within the absolute maximum rated range will cause the channel s conversion values to become undefined or may affect the conversion values of other channels 2 Analog input pins AN10 to AN17 function alternately as input port pins P10 to P17 When performing an A D conversion with any one of the AN10 to AN17 inputs selected do not execute input instructions to port 1 during conversion otherwise the conversion resolution may decrease When a digital pulse is applied to a pin that adjoins the pin undergoing A D conversion the expected A D conversion value may not be acquired due to coupling noise Therefore do not apply a pulse to a pin that adjoins the pin undergoing A D conversion AVss pin Ground pin of the A D converter Always use this pin at the same potential as the Vss pin even when not using the A D converter pin Analog power supply pin and reference voltage input pin of the A D converter Always use this pin at the same potential as the pin even when not using the A D converter User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER 13 3 Control Registers The A D converter is controlled by the following two registers A D converter mode register ADM A D converter input selection register ADIS 1 A D converter mode register ADM Used to set the A D conversion time of the analog input to be converted start stop of the conversion operation and external triggers ADM is
102. Asynchronous serial interface CSI Clocked serial interface 3 The watchdog timer has two interrupt sources a non maskable interrupt INTWDT and a maskable interrupt INTWDTM either but not both of which can be selected 22 1 1 Software interrupts Interrupts by software consist of the BRK instruction which generates a vectored interrupt and the BRKCS instruction which performs context switching Software interrupts are acknowledged even in the interrupt disabled state and are not subject to priority control 22 1 2 Operand error interrupts These interrupts are generated if there is an illegal operand in an MOV STBC byte instruction or MOV WDMC byte instruction and LOCATION instruction Operand error interrupts are acknowledged even in the interrupt disabled state and are not subject to priority control 22 1 3 Non maskable interrupts A non maskable interrupt is generated by NMI pin input or the watchdog timer Non maskable interrupts are acknowledged unconditionallyNete even in the interrupt disabled state They are not subject to interrupt priority control and have a higher priority than any other interrupt Note Except during execution of the service program for the same non maskable interrupt or during execution of the service program for a higher priority non maskable interrupt 22 1 4 Maskable interrupts A maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag In a
103. CR50 202 8 bit compare register 60 CR60 202 8 bit timer mode control register 1 TMC1 183 8 bit timer mode control register 2 TMC2 183 8 bit timer mode control register 5 TMC5 203 8 bit timer mode control register 6 TMC6 203 204 8 bit timer counter 1 TM1 182 8 bit timer counter 2 TM2 182 8 bit timer counter 5 TM5 202 8 bit timer counter 6 TM6 202 16 16 bit capture compare register 00 CROO 147 16 bit capture compare register 01 CRO1 148 16 bit timer mode control register 0 TMCO 149 150 155 157 16 bit timer output control register 0 TOCO 152 153 16 bit timer counter 0 TMO 146 616 User s Manual U12697EJAV1UD APPENDIX D REGISTER INDEX D 2 Register Index Alphabetical Order A ADCR ADIC ADIS ADM ASIM1 ASIM2 ASIS1 ASIS2 B BRGC1 BRGC2 C CC CKS CORAH CORAL CORC CROO CR01 CR10 CR20 CR50 CR60 CRCO CSIICO CSIMO CSIM1 CSIM2 D DACSO DACS1 DAMO DAM1 E EGNO EGPO EXAE I IIC0 IICC0 A D conversion result register 227 Interrupt control register 368 A D converter input selection register 230 A D converter mode register 228 Asynchronous serial interface mode register 1 260 261 267 Asynchronous serial interface mode register 2 260 261 267 Asynchronous serial interface status register 1 262 268 Asynchronous serial int
104. Delay time from WR to Voo 5 0 V 10 1 n T 40 WAITT Voo 3 0 V 10 1 n T 60 Voo 2 0 V 10 1 n T 90 Remark T tcvk 1 fxx fxx Main system clock frequency a 1 during address wait otherwise 0 n Number of wait states n gt 0 User s Manual U12697EJ4V1UD 563 CHAPTER 29 ELECTRICAL SPECIFICATIONS 3 Serial Operation Ta 40 to 85 C Voo AVpp 1 8 to 5 5 V Vss AVss 0 V 1 2 a 3 wire serial mode SCK Internal clock output Parameter SCK cycle time Conditions 4 5 V lt lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V SCK high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V SI setup time to SCKT 2 7 V lt Voo lt 5 5 V 1 8 V lt Voo lt 2 7 V SI hold time from SCKT SO output delay time from SCKL SO output hold time from SCKT b 3 wire serial I O Parameter SCK cycle time mode SCK External clock input Conditions 4 5 V lt lt 5 5 V 0 5tkcy1 50 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V SCK high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V SI setup time
105. Figure 8 3 Format of Capture Compare Control Register 0 CRCO Address FF16H After reset 04H R W Symbol 6 5 7 4 3 2 1 0 CRCO2 Selection of operation mode of CRO1 Operates as compare register Operates as capture register CRCO1 Selection of capture trigger of CROO Captured at valid edge of TIO1 Captured in reverse phase of valid edge of TIOO CRCOO Selection of operation mode of CROO Operates as compare register Operates as capture register Cautions 1 Before setting CRCO be sure to stop the timer operation 2 When the mode in which the timer is cleared and started on a match between 16 bit timer counter 0 TMO and CROO is selected by 16 bit timer mode control register 0 TMCO do not specify CROO as a capture register 3 16 bit timer output control register 0 TOCO This register controls the operation of the 16 bit timer event counter output controller by setting or resetting via timer output level software enabling or disabling reverse output enabling or disabling output of the 16 bit timer event counter enabling or disabling the one shot pulse output operation and selecting an output trigger for a one shot pulse by software TOCO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets TOCO to 00H Figure 8 4 shows the format of TOCO User s Manual U12697EJAV1UD 153 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 4 Format of 16 Bit Timer Output Control Register 0 T
106. Format of Interrupt Mode Control Register IMC Address OFFAAH After reset 80H R W Symbol 7 6 5 4 3 2 1 0 Nesting control of maskable interrupts lowest level Interrupts with level 3 lowest level can be nested Nesting of interrupts with level 3 lowest level is disabled User s Manual U12697EJAV1UD 373 CHAPTER 22 INTERRUPT FUNCTIONS 22 3 5 Watchdog timer mode register WDM The WDT4 bit of WDM specifies the priority of NMI pin input non maskable interrupts and watchdog timer overflow non maskable interrupts WDM be written to only by a dedicated instruction This dedicated instruction MOV WDM byte has a special code configuration 4 bytes and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements If the 3rd and 4th bytes of the operation code are not mutual 1 s complements a write is not performed and an operand error interrupt is generated In this case the return address saved in the stack area is the address of the instruction that was the source of the error and thus the address that was the source of the error can be identified from the return address saved in the stack area If recovery from an operand error is simply performed by means of the RETB instruction an endless loop will result Asanoperanderror interruptis only generated in the event of an inadvertent program loop with the NEC assembler RA78KA only the correct dedicated instruction is
107. Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if y
108. IE 78K4 NS ID78K4 Integrated debugger supporting in circuit emulator IE 784000 R Host Machine Supply Medium IBM PC AT compatible 3 5 inch 2HD FD Japanese Windows English Windows Japanese Windows English Windows Windows OSF Motif are employed as the GUI for PC and EWS respectively providing users with their unique look and operability In addition the enhanced C language supported debug function enables the result of a trace to be displayed at the C language level using the window integration function in which the source program disassemble display and memory display are linked to the result of trace Moreover the efficiency of debugging programs that use a real time OS can be raised by installing function expansion modules such as task debuggers and system perform ance analyzers Control program to debug the 78K IV Series Use these integrated debuggers in combination with the device file DF784225 sold separately Part number uSxxxxID78K4 NS uSxxxxID78K4 Remark The xxxx part number differs depending on the host machine and operating system used USxxxxSM78K4 NS uSxxxxID78K4 Host Machine Supply Medium IBM PC AT compatible 3 5 inch 2HD FD Japanese Windows English Windows Japanese Windows English Windows User s Manual U12697EJ4V1UD 607 APPENDIX B DEVELOPMENT TOOLS B 4 Cautions on Designing Target System The connection c
109. MPD for data b Updating of data macro service pointer It is possible to choose whether the data macro service pointer MPD is to be incremented or decremented c Automatic addition The current compare register value is added to the data addressed by the timer macro service pointer MPT and the result is transferred to the compare register If automatic addition is not specified the data addressed by MPT is simply transferred to the compare register d Ring control An output data pattern of the length specified beforehand is automatically output repeatedly User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 30 Macro Service Data Transfer Processing Flow Type C 1 2 Macro service request acknowledgment Read contents of macro service mode register Determine channel type To other macro service processing TYPE G Read channel pointer contents m Read memory addressed by MPT Yes Automatic addition specified Transfer data to compare register Retain MPT No Increment MPT Add data to compare register No Decrement MPT Yes Increment MPTNete Note 1 byte transfer 1 No 2 byte transfer 2 Read memory addressed by MPD Transfer data to buffer register Decrement MPD 1 Increment MPD Yes Increment MPD 1 User s Manual U12697EJAV1UD 415 CHAPTER 22 INTERRUPT FUNCTIONS 416 Figur
110. Middle byte SP m Lower byte RET instruction RETI RETB instructions POP post POPU post instructions Stack Stack for POP AX RP2 RP3 Stack SP SP 3 SP SP 4 SP SP 6 PSWH to Note SP 3 de PC19 to PC16 3 PC19 to PC16 SP 5 R7 BPa SP 1 PC15 to PC8 PSWL SP 4 R6 T SP m PC7 to PC0 SP 1 PC15 to PC8 SP 3 R5 T T RP2 SP m PC7 to PC0 SP 2 R4 SP 1 A t AX SP m x Note This 4 bit data is ignored User s Manual U12697EJ4V1UD 77 CHAPTER 3 CPU ARCHITECTURE 78 Cautions 1 In stack addressing the entire 1 MB space can be accessed but the stack cannot be guaranteed in the SFR area and internal ROM area 2 The stack pointer SP becomes undefined when RESET is input In addition even when the SP is in an undefined state non maskable interrupts can be acknowledged Therefore when the SP is in an undefined state immediately after the reset is cleared and a request for a non maskable interrupt is generated unexpected operations sometimes occur To avoid this danger always specify the following in the program after clearing a reset RSTVCT CSEG DW RSTSTRT to INITSEG CSEG BASE RSTSTRT LOCATION 0H or LOCATION OFH MOVG SP STKBGN User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE 3 8 General Purpose Registers 3 8 1 Structure There are sixteen 8 bit general purpose registers In addition two 8 bit general purpose registers can be combined and used as a 16 bit general purpo
111. NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redunda
112. NEC Electronics Corporation Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation SPARCstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company Ethernet is a trademark of Xerox Corporation OSF Motif is a trademark of the Open Software Foundation Inc TRON is the abbreviation for the Realtime Operating system Nucleus ITRON is the abbreviation for Industrial TRON 4 User s Manual U12697EJ4V1UD These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of August 2005 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of
113. P17Note 1 ANIO to ANI7 Input P50 to P57 A8 to A15 Output P20 RxD1 SI1 Input P60 to P63 A16 to A19 Output P21 TxD1 SO1 Output P64 RD Output P22 ASK1 Input P65 WR Output SCK1 Input P66 WAIT Input Output P67 ASTB Output PCL Output P70 RxD2 SI2 Input BUZ Output P71 TxD2 SO2 Output SIO Input P72 ASCK2 Input SDA0Note 3 O SCK2 Input SO0 Output Output SCK0 Input P120 to P127 RTP0 to RTP7 Output Output P130 P131Note1 ANOO ANO1 Output SCLONote 3 O P30 to P32 TOO to TO2 Output P33 P34 TH TI2 Input Notes 1 Ifthe read command is executed for these ports when they are being used as alternate function pins the data read will be undefined 2 The function is set by the memory expansion mode register MM when the P40 to P47 P50 to P57 and P60 to P67 pins are used as alternate function pins 3 The SDAO and SCLO pins are only available in the uwPD784225Y Subseries Cautions 1 When not using external wait in the external memory expansion mode the P66 pin can be used as an I O port 2 Specify the SCL0 P27 and SDAO P25 pins as N ch open drain by setting the port function control register PF2 when the I2C bus mode is to be used Remark x Don t care setting is not required Port mode register and output latch do not exist PMxx Port mode register Pxx Port output latch 130 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS Address 0FF20H 0FF22
114. P63 A19 P64 RD P65 WR P66 WAIT P67 ASTB P70 RxD2 SI2 P71 TxD2 SO2 P72 ASCK2 SCK2 Note The SDAO and SCLO pins are provided only in the uPD784225Y Subseries User s Manual U12697EJ4V1UD 53 CHAPTER 2 PIN FUNCTIONS Table 2 1 Types of Pin I O Circuits and Recommended Connection of Unused Pins 2 2 Pin Name I O Circuit Type Recommended Connection of Unused Pins P120 RTPO to P127 RTP7 Input Independently connect to Vsso via a resistor P130 ANOO P131 ANO1 Output Leave open RESET XT1 Connect to Vsso XT2 Leave open AVREF1 Connect to AVpp AVss Connect to Vsso TEST VppNote Connect directly to Vsso or pull down For the pull down connection use of a resistor with a resistance between 470 Q and 10 kQ is recommended Note VPP pin is provided only in the uPD78F4225 78F4225Y Remark Since the type numbers are unified in the 78K Series they are not always sequential in each product not all the circuits are incorporated 54 User s Manual U12697EJAV1UD CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin I O Circuits 1 2 Schmitt triggered input with hysteresis characteristics Pull up enable Output disable Vppo rs Vppo N ch Vsso 77 lt Vppo Pull up enable P Vppo is Data gt P ch Nch Output disable Input ena
115. PUO6 1 in the external memory expansion mode pull up resistors can be connected Caution When external waits are not used in the external memory expansion mode P66 can be used as an I O port pin P70 to P72 Port 7 These pins constitute a 3 bit I O port In addition to I O port pins they also function as the data I O and clock I O of the serial interface The following operation modes can be specified in 1 bit units a Port mode These pins function as a 3 bit I O port Input or output can be specified in 1 bit units by means of the port 7 mode register Regardless of whether the input mode or output mode is specified pull up resistors can be connected in 1 bit units using pull up resistor option register 7 b Control mode These pins function as data I O and clock I O for the serial interface User s Manual U12697EJ4V1UD CHAPTER 2 PIN FUNCTIONS i SI2 502 These are the I O pins for serial data in the serial interface i SCK2 This is the I O pin of the serial clock in the serial interface iii RxD2 TxD2 These are the serial data I O pins in the asynchronous serial interface iv ASCK2 This is the baud rate clock input pin in the asynchronous serial interface 9 P120 to P127 Port 12 These pins constitute an 8 bit I O port In addition to I O port pins they also function as a real time output port The following operation modes can be specified in 1 bit units a Port mode These pins function as an
116. Pots K PsotoP57 ANO0 Pone K gt Peo to P67 ANO1 D A AVREF1 converter Pot K gt P70 to P72 AVss Poti2 gt P120 to P127 ANIO to ANI7 Port 13 P130 P131 A D AVss converter RESET X1 PCL Clock output System control X2 control XT1 BUZ Buzzer output XT2 Vomp Vss 551 TEST VepNete2 Notes 1 The SDAO and SCLO pins are provided only in the uPD784225Y Subseries 2 The VPP pin is provided only for the uPD78F4225 and 78F4225Y Remark The internal ROM and RAM capacity varies depending on the product 38 User s Manual U12697EJ4V1UD CHAPTER 1 OVERVIEW 1 5 Function List 1 2 Product Name uPD784224 uPD784225 uPD78F4225 uPD784224Y uPD784225Y uPD78F4225Y Number of basic instructions mnemonics 113 General purpose registers 8 bits x 16 registers x 8 banks or 16 bits x 8 registers x 8 banks memory mapping Minimum instruction execution time 160 ns 12 5 MHz operation with main system clock 61 us 32 768 kHz operation with subsystem clock Internal memory ROM 96 KB 128 KB 128 KB mask ROM mask ROM flash memory RAM 3 584 bytes 4 352 bytes Memory space 1 MB of combined program and data space ports Total 67 CMOS input 8 CMOS I O 59 Pins with added Pins with pull up 57 functionsNote resistors LED direct drive outputs 16 Real time output ports 4 bits x 2 or 8 bits x 1 Time
117. RXBn is read or when the next data is received To find out the contents of the error be sure to read ASIS before reading RXBn 2 Be sure to read receive buffer register n RXBn even when a receive error occurs If RXBn is not read an overrun error will occur at reception of the next data and the receive error status will continue indefinitely Remark 1 2 User s Manual U12697EJAV1UD 277 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O 16 3 3 Standby mode operation 1 HALT mode operation The serial transfer operation is normally performed 2 STOP mode or IDLE mode operation a When internal clock is selected as serial clock Asynchronous serial interface mode register n ASIMn transmit shift register n TXSn receive shift register n RXn and receive buffer register n RXBn stop operation holding the value immediately before the clock stops If the clock stops STOP mode during transmission the TxDn pin output data immediately before the clock stopped is held If the clock stops during reception receive data up to immediately before the clock stopped is stored and subsequent operation is stopped When the clock is restarted reception is resumed Remark n 1 2 b When external clock is selected as serial clock Serial transmission is performed normally However interrupt requests are held pending without being acknowledged Interrupt requests are acknowledged after the STOP mode or IDLE mode has bee
118. Request Is Generated During Main routine Interrupt requesti _ _ Level 1 Interrupt request k Level 2 Interrupt request n Level 2 Macro service request j Level 2 24 m Interrupt request Level 3 Interrupt request m Level 1 Z Interrupt request o Level 3 Interrupt request p Level 1 Interrupt Servicing 2 3 i servicing k servicing servicing n servicing p servicing o servicing 4 j macro service m servicing User s Manual U12697EJ4V1UD The macro service request is serviced irrespective of interrupt enabling disabling and priority The interrupt request is held pending since it has a lower priority than interrupt request k Interrupt request m generated after interrupt request has a higher priority and is therefore acknowledged first Since servicing of interrupt request n performed in the interrupt disabled state interrupt requests o and p are held pending After interrupt request n servicing the pending interrupt requests are acknowledged Although interrupt request o was generated first interrupt request p has a higher priority and is therefore acknowledged first 389 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 14 Examples of Servicing When Another Interrupt Request Is Generated During Interrupt Servicing 3 3 Main routine El r servicing El Interrupt request q _ 12 oo E L nter
119. SERIC1 SRIC1 STIC1 Service processing enable or disable the context SERIC2 SRIC2 STIC2 switching function and specify priority TMIC3 TMICOO TMICO1 TMIC1 TMIC2 ADIC TMIC5 TMIC6 WTIC Interrupt mask registers MKO MKOL MKOH Control masking of maskable interrupt requests MK1 MK1L MK1H Associated with the mask control flag in the interrupt control register Can be accessed in word or byte units In service priority register ISPR Records priority of interrupt request currently acknowledged Interrupt mode control register IMC Controls nesting of maskable interrupt with priority specified as lowest level level 3 Interrupt selection control SNMI Selects whether to use input signal from the P02 pin and register the interrupt signal from the watchdog timer as a maskable interrupt or NMI Watchdog timer mode register Specifies the priority of interrupts from the NMI pin input and overflow of the watchdog timer Program status word Enables or disables acknowledging maskable interrupts An interrupt control register is allocated to each interrupt source The flags of each register perform control of the contents corresponding to the relevant bit position in the register The interrupt control register flag names corresponding to each interrupt request signal are shown in Table 22 4 364 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Default Priority Table 22 4 Flag List o
120. STBC byte STOP mode not executed Execute instruction up to 6th clock Interrupt request Interrupt servicing User s Manual U12697EJ4V1UD 485 CHAPTER 24 STANDBY FUNCTION 1 Releasing STOP mode by NMI input When the valid edge specified by external interrupt edge enable register 0 EGP0 EGN0 is input by NMI input the oscillator starts oscillating again The STOP mode is then released after the oscillation stabilization time set by the oscillation stabilization time specification register OSTS has elapsed When the STOP mode is released and non maskable interrupts from the NMI pin input can be acknowledged execution branches to the NMI interrupt service program If acknowledgement is not possible such as when the STOP mode has been set in the NMI interrupt service program execution starts again from the instruction following the instruction that set the STOP mode When acknowledgement is enabled execution branches to the NMI interrupt service program by executing the RETI instruction For details of NMI interrupt acknowledgment refer to 22 6 Non Maskable Interrupt Acknowledgment Opera tion Figure 24 7 Releasing STOP Mode by NMI Input STOP Oscillator SUU JUUUUUU 2 U STP F F1 STP F F2 i NMI input when the rising P I edge is specified Oscillator stops Timer count time for stabilization Time until clock starts oscilla
121. See Table 3 6 Special Function Register SFR List when resetting User s Manual U12697EJ4V1UD 505 CHAPTER 26 ROM CORRECTION 26 1 ROM Correction Functions In the uPD784224 784225 784224Y and 784225Y part of the program in the mask ROM can be replaced by the program in the internal expansion RAM The use of ROM correction enables command bugs discovered in the mask ROM to be repaired and the flow of the program to be changed ROM correction can be used in a maximum of four located within the internal ROM program Caution Note that ROM correction cannot be emulated by the in circuit emulator IE 784000 R IE 784000 R EM Specifically the command addresses that require repair from the inactive memory externally connected to a microcontroller by a user program and the repair command codes are loaded into the peripheral RAM The above addresses and the internal ROM access addresses are compared by the comparator built into the microcontroller during execution of internal ROM programs during command fetch and the internal ROM s output data is then converted to call command CALLT codes and output when a match is determined When the CALLT command codes are changed to valid commands by the CPU and executed the CALLT table is referenced and the process routine and other peripheral RAM are branched Atthis point a CALLT table is prepared for each repair address for referencing purposes Four repair address can be set for the uPD
122. Table 22 8 Table 22 8 Macro Service Processing Time Units Clock 1 Data Area Processing Type of Macro Service IRAM Other SFR memory Memory gt SFR Type B SFR memory Memory SFR Type C Counter mode MSC 0 USC 0 Remarks 1 IRAM Internal high speed RAM 2 Inthe following cases in the other data areas add the number of clocks specified below Ifthe data size is 2 bytes with IROM or PRAM and the data is located at an odd address 4 clocks If the data size is 1 byte with EMEM The number of wait states for data access If the data size is 2 bytes with EMEM 4 2n where n is the number of wait states per byte 3 If MSC 0 with type A B or C add 1 clock 4 With type C add the following value depending on the function to be used and the status at that time Ring control 4 clocks Add 7 more clocks if the ring counter is 0 during ring control User s Manual U12697EJAV1UD 433 CHAPTER 22 INTERRUPT FUNCTIONS 22 12 Restoring Interrupt Function to Initial State If an inadvertent program loop or system error is detected by means of an operand error interrupt the watchdog timer NMI pin input etc the entire system must be restored to its initial state In the wPD784225 interrupt acknowledgment related priority control is performed by hardware This interrupt acknowledgment related hardware must also be restored to its initial
123. The external access status enable register EXAE controls the EXA signal output indicated during external access EXAE is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets EXAE to 00H Figure 23 14 Format of External Access Status Enable Register EXAE Address OFF8DH After reset 00H Symbol 7 6 5 4 3 2 1 0 0 Port function 1 External access status function 23 6 4 External access status signal timing A timing chart for the P37 EXA and external bus interface pin is shown below The EXA signal is active low and indicates the external access status when 0 a Data fetch timing P4 P5 P60 to P63 P67 ASTB J P64 RD N P65 WR H P37 EXA N 460 User s Manual U12697EJ4V1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS b Data read timing P4 P5 P60 to P63 P67 ASTB P64 RD N P65 WR H P37 EXA N c Data write timing P67 ASTB N P64 RD N P65 WR H P37 EXA 23 6 5 EXA pin status in each mode P37 EXA pin status in each mode is shown in Table 23 4 Table 23 4 P37 EXA Pin Status in Each Mode After reset Hi Z Normal operation Hi Z immediately after the reset is canceled input mode PM37 1 Port operations when EXAE 00H with PM37 and P37 0 EXA signal output enabled when EXAE 01H with PM37 and P37 0 HALT modeStandby IDLE modeHi Z STOP modeHi Z User s Manual U12697EJAV1UD 461 CHAPTER 23 LOCAL BUS INTERFACE FU
124. U12697EJ4V1UD 21 LIST OF FIGURES 3 8 Figure No Title Page 8 28 Timing of One Shot Pulse Output Operation by External Trigger with Rising Edge Specified 175 8 29 Start Timing of 16 Bit Timer Counter uae L u G Su 176 8 30 Timing After Changing Compare Register During Timer Count Operation 176 8 31 Data Hold Timing of Capture Register u uuu au uiaiia su ssuiqussas 177 8 32 Operation Timing Of OV FO Flag y a rete etae sta rea repro D eeu cin 178 9 1 Block Diagram of 8 Bit Timer Event Counters 1 02 181 9 2 Format of 8 Bit Timer Mode Control Register 1 185 9 3 Format of 8 Bit Timer Mode Control Register 2 2 186 9 4 Format of Prescaler Mode Register 1 PRM1 187 9 5 Format of Prescaler Mode Register 2 PRM2 188 9 6 Timing of Interval 190 9 7 Timing of External Event Counter Operation with Rising Edge Is Specified 193 9 8 Timing ot aul Ree in dic nee Wa eens 196 9 9 Timing of Operation Based on CRn0 Transitions a 197 9 10 Cascade Connection Mode with 16 Bit Resolution a 198 9 11 Start Timing of 8 Bit
125. V 5 1 5 T 90 Input time from RD to WAITL tDRWTL Voo 5 0 V 10 T 40 Voo 3 0 V 10 T 60 Voo 2 0 V 5 T 70 Hold time from RD to WAIT Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 Delay time from RD to WAITT DRWTH Voo 5 0 V 10 1 n T 40 Voo 3 0 V 10 1 n T 60 Voo 2 0 V 5 1 n T 90 Data input time from WAITT towTip Voo 5 0 V 10 0 5T 5 Voo 3 0 V 10 0 5T 10 Voo 2 0 V 5 0 5T 30 Delay time from WAITT to RDT Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 Delay time from WAITT to wrt Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 Input time from WR to WAITL Remark T tcvk 1 fxx fxx Main system clock frequency Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 a 1 during address wait otherwise 0 n Number of wait states n 2 0 User s Manual U12697EJ4V1UD 579 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 External wait timing 2 2 Parameter Conditions Hold time from WR to Voo 5 0 V 10 WAIT Voo 3 0 V 10 Voo 2 0 V 5 Delay time from WR to Voo 5 0 V 10 1 n T 40 WAITT Voo 3 0 V 10 1 n T 60 Voo 2 0 V 5 1 T 90 Remark 1 fxx fxx Main system clock frequency n Number
126. WIRE SERIAL I O MODE b Communication operation The 3 wire serial I O mode transmits and receives data in 8 bit units Data is transmitted and received with each bit synchronized with the serial clock The shifting of serial I O shift register 0 SIOO is synchronized with the falling edge of the serial clock SCKO The transmitted data is held in the latch and output from the SOO pin Atthe rising edge of SCKO the received data that was input to the SIO pin is latched to SIOO Atthe end of the 8 bittransfer the SIOO operation automatically stops and the interrupt request flag CSIIFO is set Figure 17 5 3 Wire Serial I O Mode Timing SCKO SIO 500 CSIIFO Transfer ends Transfer start synchronized with the falling edge of SCKO c Start transfer If the following two conditions are satisfied the serial transfer starts when the transfer data is set in the serial shift register S100 Control bit CSIEO 1 during SIOO operation After an 8 bit serial transfer the internal serial clock enters the stopped state or SCKO is high Transmit receive communication mode When CSIEO 1 and MODEO 0 the transfer starts with an SIOO write Receive only mode When CSIEO 1 and MODEO 1 the transfer starts with an SIOO read Caution Even if CSIEO becomes 1 after the data is written to 5100 transfer does not start Serial transfer is automatically stopped by the end of the 8 bit transfer and the interrupt re
127. a certain time the sample amp hold circuit enters the hold status and the input analog voltage is held until A D conversion ends Bit 7 of the successive approximation register SAR is set The tap selector sets the voltage tap for the series resistance string at 1 2 AVpp The difference in voltage between the series resistance string s voltage tap and analog input is compared with the voltage comparator If the analog input is greater than 1 2 AVpp the setting for the MSB in SAR will remain the same If it is smaller than 1 2 AVpp the MSB will be reset Next bit 6 of SAR is automatically set and the next comparison is started The series resistor string voltage tap is selected as shown below according to bit 7 to which a result has already been set Bit 7 1 3 4 AVpp Bit 7 0 1 4 AVpp The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated according to the result as follows Analog input voltage gt Voltage tap Bit 6 1 Analog input voltage lt Voltage tap Bit 6 0 Comparisons of this kind are repeated until bit 0 of SAR When comparison of all eight bits is completed the valid digital result remains in SAR and this value is transferred to the A D conversion result and latched At the same time it is possible to issue an A D conversion end interrupt request INTAD Caution The value of the first A D conversion is undefined if ADCS is set when bit 0 ADCE of the A D 232
128. a non participation state on the bus the start condition can be transmitted when the bus is released by reserving communication The following two states are included when the bus does not participate When there was no arbitration in the master and the slave When the extended code is received and operation is not as a slave bus released when ACK is not returned and bit 6 LRELO 1 in the I C bus control register IICCO When bit 1 STTO of IICCO is setinthe not participating state in the bus after the bus is released after stop condition detection the start condition is automatically generated and the wait state is entered When the bus release is detected stop condition detection the address transfer starts as the master by the write operation of serial shift register 0 IICO In this case set bit 4 SPIEO in IICCO When STTO is set whether it operates as a start condition or for communication reservation is determined by the bus state When the bus is released eesesessoscsssosososesesescescossecoseocsosesoe Start condition generation When the bus is not released standby state 77 Communication reservation The method that detects the operation of STTO sets STTO and verifies the STTO bit again after the waittime elapses Use the software to save the wait time which is listed in Table 18 5 The wait time can be set by bits 3 1 and 0 SMC CL1 CLO of prescaler mode register 0 for serial clock SPRMO Table 18 5
129. ae aS Sg Kaa KOEN CEN E M A B ES E A 22 1 27 TEE mec a Ia a a CRn0 aad MEE 1 tenp rn INTTMn TOn I 51 gt E 4 i 4 CRn0 transition Reload Reload N gt M b When the CRnO value changes from N to M after TMn overflows sd el dis odo Lleida inda Mo ACSI TR TETRA RT RT CRnO LL read valo MALAE Reload CRn0 transition Reload N M c When the CRnO value changes from N to M within two clocks 00H 01H immediately after TMn overflows Count do i iib na Vn TTR CRn0 ne lt INTTMn 9 l 1 l 9 ae amp CRn0 transition Bed 2 Remarks 1 1 2 2 CRnO M Master side CRn0 S Slave side User s Manual U12697EJAV1UD 197 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 4 5 Operation as interval timer 16 bit operation Cascade connection 16 bit timer mode By setting bit 4 TMC24 of 8 bit timer mode control register 2 TMC2 to 1 the timer enters the timer counter mode with 16 bit resolution With the count preset in 8 bit compare registers 10 and 20 CR10 CR20 as the interval the timer operates as an interval timer by repeatedly generating interrupt requests lt Seiting method gt 1 2 3 lt 4 gt Set each regi
130. at 200 C or VP15 103 2 higher Count Two times or less Exposure limit 3 daysNete after that prebake at 125 C for 10 hours Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating 2 uPD784225GC xxx 8BT 80 pin plastic QFP 14 x 14 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or IR35 00 2 higher Count Two times or less VPS Package peak temperature 215 C Time 40 seconds max at 200 C or VP15 00 2 higher Count Two times or less Wave soldering Solder bath temperature 260 C max Time 10 seconds max WS60 00 1 Count Once Preheating temperature 120 C max package surface temperature Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 596 User s Manual U12697EJAV1UD CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS Table 31 1 Soldering Conditions for Surface Mount Type 2 3 3 uPD784224GC xxx 8BT 80 plastic 14 x 14 uPD784224YGC xxx 8BT 80 pin plastic 14 x 14 uPD784225YGC xxx 8BT 80 pin plastic QFP 14 x 14 uPD78F422
131. be connected in 1 bit units via pull up resistor option register 0 regardless of whether the input mode or output mode is specified Port 0 also supports external interrupt request input as an alternate function RESET input sets port 0 to the input mode Figure 5 2 shows the block diagram of port 0 Caution Even though port 0 is also used as an external interrupt input when port 0 is not used as interrupt input pin be sure to set interrupt disabled by using external interrupt rising edge enable register 0 EGPO and external interrupt falling edge enable register 0 EGNO or setting the interrupt enable flag PMKn n 0 to 5 to 1 Otherwise the interrupt request flag is set and unintentional interrupt servicing may be executed when setting ports to output mode and thus changing the output level User s Manual U12697EJAV1UD 107 CHAPTER 5 PORT FUNCTIONS Figure 5 2 Block Diagram of P00 to P05 Voo PU00 to PU05 D gt P ch RD Alternate function e A WRPonr POO INTPO PO1 INTP1 9 PO2 INTP2 NMI to POS INTP5 Output latch P00 to P05 Internal bus PM00 to PM05 PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal 108 User s Manual U12697EJ4V1UD CHAPTER 5 PORT FUNCTIONS 5 2 2 Port 1 This is an 8 bit input only port with no on chip pull up resistor Port 1 supports A D converter analog
132. bit timer output control register 0 TOCO 1 and the external trigger TIOO input are always valid in one shot pulse output mode If the software trigger is used in one shot pulse output mode the TIOO pin cannot be used as a general purpose port pin Therefore fix the TIOO pin to either high level or low level OSPT 5 5 172 User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 One shot pulse output with external trigger A one shot pulse can be output from the TO0 P30 pin by setting 16 bit timer mode control register 0 TMC0 capture compare control register 0 CRC0 and 16 bit timer output control register 0 TOC0 as shown in Figure 8 27 and by using the valid edge of the TI00 P35 pin as an external trigger The valid edge of the TIOO P35 pin is specified by bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 The rising falling or both the rising and falling edges can be specified When the valid edge of the TI00 P35 pin is detected the 16 bit timer event counter is cleared and started and the output is asserted at the count value set in advance to 16 bit capture compare register 01 CR01 After that the output is deasserted at the count value set in advance to 16 bit capture compare register 00 CR00 Cautions 1 If the external trigger is generated while the one shot pulse is being output the counter is cleared and restarted and the one shot pulse is output again 2 The software trig
133. by setting 16 bit timer mode control register 0 TMCO capture compare control register 0 CRCO and 16 bit timer output control register 0 TOCO as shown in Figure 8 25 and by setting bit 6 OSPT of TOCO by software By setting OSPT to 1 the 16 bit timer event counter is cleared and started and its output is asserted at the count value set in advance to 16 bit capture compare register 01 CRO1 After that the output is deasserted at the count value set in advance to 16 bit capture compare register 00 CROO Even after the one shot pulse has been output TMO continues its operation To stop TMO TMCO must be reset to 00H Cautions 1 Do not set OSPT to 1 while the one shot pulse is being output To output the one shot pulse 170 again wait until INTTMOO which occurs a match between TMO and 00 occurs 2 The software trigger bit 6 OSPT of 16 bit timer output control register 0 TOCO 1 and the external trigger TIOO input are always valid in one shot pulse output mode If the software trigger is used in one shot pulse output mode the TIOO pin cannot be used as a general purpose port pin Therefore fix the TIOO pin to either high level or low level User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 25 Control Register Settings for One Shot Pulse Output by Software Trigger a 16 bit timer mode control register 0 TMC0 TMC03 TMC02 TMC01 OVFO TWoo o o Jo 0 ot on on o C
134. channel correction pointers CORC is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CORC to 00H Figure 26 4 Format of ROM Correction Control Register CORC Address OFF88H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CORENn Controls the match detection for the ROM correction address register and the fetch address Disabled Enabled CORCHO Channel selection Address pointer channel 0 Address pointer channel 1 Address pointer channel 2 Address pointer channel 3 Remark 0 510 User s Manual U12697EJ4V1UD CHAPTER 26 ROM CORRECTION 26 4 Usage of ROM Correction lt 1 gt The correct address and post correction instruction correction program are stored in the microcontroller external inactive memory EEPROM lt 2 gt A substitute instruction is read from the inactive memory using a serial interface etc when the initialization program is running after being reset and this is stored in the peripheral RAM and external memory The correction channel is then selected the address for the command that requires correction is read and set in ROM correction address registers H L CORAH CORAL and the correction enable flag CORENO to 3 is set to 1 A maximum of four locations can be set lt 3 gt The CALLT instruction is then executed during execution of the corrected address Program execution internal ROM Correct address execute
135. chip 8 bit timer event counters and two 8 bit timers Since a total of six interrupt requests are supported these timer event counters can function as six timer event counter units Table 7 1 Timer Operation 16 Bit Timer 8 Bit Timer 8 Bit Timer Event Counter Event Counter 1 Event Counter 2 RUMEN Ss 6 Bit Timer G Count width 8 bits 16 bits Operation mode Interval timer External event counter Function Timer output PPG output PWM output Square wave output One shot pulse output Pulse width measurement 2 inputs No of interrupt requests 2 142 User s Manual U12697EJ4V1UD CHAPTER 7 TIMER OVERVIEW Figure 7 1 Block Diagram of Timer 1 2 16 bit timer event counter Clear fxx 4 fxx 16 16 bit timer counter 0 TMO INTTM3 01 O 7 Edge detector INTTMOO 16 bit capture compare register 00 CROO INTTMO1 16 bit capture compare register 01 CRO1 o 25 2 2 2 2 TIOO Edge detector 8 bit timer event counter 1 fxx 2 fxx 28 fxx 24 fxx 25 fxx 27 fxx 2 Output controller O TO1 8 bit timer counter 1 TM1 8 bit compare register 10 CR10 INTTM2 TH Edge detector INTTM1 Selector 8 bit timer event counter 2 fxx 22 fxx 28 cipar 4 S Bie 9 8 bit timer counter 2 T5
136. conversion accuracy it is necessary to sufficiently reduce the impedance of the sensor and other signal sources Figure 13 21 shows the internal equivalence circuit of the ANIO to ANI7 pins in the microcontroller If the impedance of the signal source is high it can be made to seem smaller by connecting a large capacitance to the ANIO to ANI7 pins A circuit example is shown in Figure 13 22 In this case because a low pass filter is configured in the circuit impedance will no longer be able to follow analog signals with large differential coefficients When converting high speed analog signals or performing conversion in scan mode be sure to insert a low impedance buffer 246 User s Manual U12697EJAV1UD CHAPTER 13 A D CONVERTER Figure 13 21 Internal Equivalence Circuit of ANI0 to ANI7 Pins R1 R2 ANIn C1 C2 C3 Remark nz0to7 Table 13 2 Resistance and Capacitance Values for Equivalence Circuits Reference Values Caution The resistance and capacitance values in Table 13 2 cannot be guaranteed Figure 13 22 Example of Circuit When Signal Source Impedance Is High lt Sensor internal gt R1 R2 impedance I I I I 1 Sensor output 27 I I I I C1 C2 C3 0 lt 0 1 uF Low pass filter configured 2 Remark nz0to7 User s Manual U12697EJAV1UD 247 CHAPTER 14 D A CONVERTER 14 1 Function The D A converter converts the digital input
137. converter mode register ADM is 0 User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER Figure 13 4 Basic Operations of A D Converter Conversion gt time Sampling time lt A D converter Sampling A D conversion operation Conversion result SAR Undefined Conversion result INTAD A D conversion is performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset ADCR 0 by software If a write operation to ADM or the A D converter input selection register ADIS is performed during A D conversion the conversion operation is initialized and conversion starts from the beginning if the ADCS bit is set 1 RESET input makes the A D conversion result register ADCR undefined If bit O ADCE of the A D converter mode register is not set to 1 the value of the first A D conversion is undefined immediately after A D conversion starts Poll the A D conversion end interrupt request INTAD and discard the first A D conversion result User s Manual U12697EJAV1UD 233 CHAPTER 13 A D CONVERTER 13 4 2 Input voltage and conversion result The relationship between the analog input voltage input to the analog input pins ANI0 to ANI7 and the A D conversion result value saved in the A D conversion result register ADCR is expressed by the following equation ADCR INT VIN_ x 256 0 5 AVpp or ADCR 0 5 x ae lt Vin lt ADCR
138. count becomes OOH lt 1 gt RESET is input 2 TCEn is cleared 3 TMn 0 match in the clear and start mode Caution In cascade connection mode the count becomes 00H by clearing bit 7 TCE5 of 8 bit timer mode control register 5 TMC5 and bit 7 TCE6 of 8 bit timer mode control register 6 TMC6 Remark 5 6 8 bit compare registers 50 and 60 CR50 CR60 The value set in CR50 and CR60 are compared to the count value in 8 bit timer counter 5 TM5 and 8 bit timer counter 6 TM6 respectively If the two values match an interrupt request INTTM5 INTTM6 is generated except in the PWM mode The values of CR50 and CR60 can be set in the range of 00H to FFH and can be written during counting Caution sure to stop the timer operation before setting data in cascade connection mode To stop the timer operation clear both TCE5 of TMC5 and TCE6 of TMC6 User s Manual U12697EJAV1UD 203 CHAPTER 10 8 BIT TIMERS 5 6 10 3 Control Registers The following four registers control 8 bit timers 5 and 6 8 bit timer mode control registers 5 and 6 TMC5 TMC6 Prescaler mode registers 5 and 6 PRM5 PRM6 1 8 bit timer mode control registers 5 and 6 TMC5 TMC6 TMC5 and TMC6 make the following three settings 1 Control of the counting for 8 bit timer counters 5 and 6 TM5 TM6 2 Selection of the operation mode of 8 bit timer counters 5 and 6 TM5 TM6 3 Selection of the discrete mode or
139. cycles PW01 PWOO 0 0 Write data Higher address b Setting 1 wait cycle PW01 PW00 0 1 c Setting an external wait PW01 PW00 1 1 T7 y E east zima lt we data X User s Manual U12697EJ4V1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 8 Read Modify Write Timing for External Memory in External Memory Expansion Mode ASTB RD WR ADO to AD7 A8 to A19 ASTB RD WR ADO to AD7 A8 to A19 Internal wait signal 1 clock wait ADO to AD7 A8 to A19 WAIT a Setting 0 wait cycles PW01 PWOO 0 0 1 M nn igher address Read data HE Write dataX data Higher address Higher address iN b Setting 1 wait cycle PWO1 PW00 0 1 Read data 122 lt Lower address gt Write data Higher address Higher address c Setting an external wait PW01 PW00 1 1 5 y o o Ce 77 7 Read dela datay 4 Toner adress A Wt data C data X Higher address X Higher address X User s Manual U12697EJAV1UD 449 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 5 Wait Functions If slow memory and I O are connected externally to the uPD784225 waits be inserted in the external memory access cycle The wait cycle includes an address wait to guarantee the address decoding time and an access wait to guarantee the access time 23 5 1 Address wait The address wait guarantees the address decodin
140. error is not included in the overall error 3 Quantization error When analog values are converted to digital values an error of 1 2 LSB inevitably occurs In an A D converter because analog input voltages within a range of 1 2 LSB are converted into the same digital code this quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error integral linearity error and differential linearity error values shown in the characteristics table Figure 13 8 Overall Error Figure 13 9 Quantization Error Overall error Digital output Digital output 1 2LSB Quantization error 1 1 215 Analog input Analog input 238 User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER 4 5 6 7 Digital output lower 3 bits Zero scale error This expresses the difference between the actual and theoretical analog input voltage measurement values when the digital output changes from 0 000 to 0 001 1 2LSB If the actual value is higher than the theoretical value the zero scale error indicates the difference between the actual and theoretical analog input voltage measurement values when the digital output changes from 0 001 to 0 010 3 2LSB Full scale error This expresses the difference between the actual and theoretical analog input voltage measurement values when the digital output changes from 1 110 to 1
141. error occurs it is possible to determine the contents of the reception error by reading the status of asynchronous serial interface status register n ASISn Remark 1 2 User s Manual U12697EJAV1UD 273 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O b Parity types and operations Parity bits serve to detect bit errors in transmit data Normally the parity bit used on the transmit side and the receive side are of the same type In the case of even parity and odd parity it is possible to detect 1 bit odd number errors In the case of 0 parity and no parity errors cannot be detected i Even parity During transmission Makes the number of 1 s in transmit data that includes the parity bit even The value of the parity bit changes as follows If the number of 1 bits in transmit data is odd 1 if the number of 1 bits in transmit data is even 0 During reception The number of 1 bits in receive data that includes the parity bit is counted and if it is odd a parity error occurs ii Odd parity During transmission Odd parity is the reverse of even parity It makes the number of 1 s in transmit data that includes the parity bit odd The value of the parity bit changes as follows If the number of 1 bits in transmit data is odd 0 if the number of 1 bits in transmit data is even 1 During reception The number of 1 bits in receive data is counted and if
142. event counter x 1 unit 8 bit timer event counter x 4 units 8 bit timer x 2 units 16 bit timer event counter x 1 unit 8 bit timer event counter x 6 units 16 bit timer event counter x 1 unit 8 bit timer event counter x 2 units Serial interfaces UART IOE 3 wire serial I O x 2 channels CSI 3 wire serial I O x 1 channel UART time division transmission function IOE 3 wire serial I O x 2 channels CSI 3 wire serial 1 O 2 wire serial I O SBI x 1 channel CSI 3 wire serial with automatic communication function x 1 channel Interrupts NMI pin Yes No Macro service Yes No Context switching Yes No Programmable priority 4 levels 2 levels Standby function HALT STOP IDLE mode In low power consumption mode HALT or IDLE mode HALT STOP mode ROM correction Yes No Yes Package 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 100 pin plastic fine pitch 14 x 14 100 pin plastic QFP 14 x 20 Note The pins with added functions are included in the I O pins User s Manual U12697EJ4V1UD 80 pin plastic QFP 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 599 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for system development using the uPD784225 Subseries Figure B 1 shows the development tools For PC98 NX ser
143. flags can be manipulated bit wise by software RESET input sets all bits to 1 Context switching enable flag xxCSE The context switching enable flag specifies that a maskable interrupt request is to be serviced by context switching In context switching the register bank specified beforehand is selected by hardware a branch is made to a vector address stored beforehand in the register bank and at the same time the current contents of the program counter PC and program status word PSW are saved in the register bank Context switching is suitable for real time processing since execution of interrupt servicing can be started faster than with normal vectored interrupt servicing This flag can be manipulated bit wise by software RESET input sets all bits to 0 Macro service enable flag xxISM The macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled as a vectored interrupt or by context switching or by macro servicing When macro service processing is selected at the end of the macro service when the macro service counter reaches 0 the macro service enable flag is automatically cleared 0 by hardware vectored interrupt servicing context switching servicing This flag can be manipulated bit wise by software RESET input sets all bits to 0 Interrupt mask flag xxMK An interrupt mask flag specifies enabling disabling of vectored interrupt servicing and macro service
144. from the instruction following the instruction that set the IDLE mode For details of interrupt acknowledgement refer to 22 7 Maskable Interrupt Acknowledgment Opera tion Releasing IDLE mode by RESET input When the RESET input rises from low to high and the reset condition is released the oscillator starts oscillating Oscillation stops for the RESET active period After the oscillation stabilization time elapses normal operation starts The difference from the normal reset operation is the data memory saves the contents before setting the IDLE mode User s Manual U12697EJ4V1UD 503 CHAPTER 25 RESET FUNCTION When a low level is input to the RESET input pin a system reset is performed The hardware enters the states listed in Table 25 1 Since the oscillation of the main system clock unconditionally stops during the reset period the current consumption of the entire system can be reduced When the RESET input goes from low to high the reset state is released After the count time of the timer for oscillation stabilization 41 9 ms at 12 5 MHz operation the contents of the reset vector table are set in the program counter PC Execution branches to the address set in the PC and program execution starts from the branch destination address Therefore a reset can be started from any address Figure 25 1 Oscillation of Main System Clock in Reset Period Oscillation is rtd U UL Main system clock oscillator uncondi
145. generated when MOV WDM byte is written initialize the system by program Other write instructions MOV WDM A AND WDM byte SET1 WDM 7 etc are ignored and do not perform any operation That is a write is not performed to WDM and an interrupt such as an operand error interrupt is not generated WDM can be read at any time by a data transfer instruction RESET input clears the WDM register to OOH Figure 22 5 Format of Watchdog Timer Mode Register WDM Address OFFC2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 RUN Specifies operation of watchdog timer refer to Figure 12 2 WDT4 Priority of watchdog timer interrupt request Watchdog timer interrupt request lt NMI pin input interrupt request Watchdog timer interrupt request gt NMI pin input interrupt request WDT2 WDT1 Specifies count clock of watchdog timer refer to Figure 12 2 Caution The watchdog timer mode register WDM can be written only by using a dedicated instruction MOV WDM byte 374 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 3 6 Interrupt selection control register SNMI SNMI selects whether to use interrupt request signals from the watchdog timer and inputs from the P02 pin as maskable interrupts or non maskable interrupts Since the bits of this register can be set 1 only once after reset the bits should be cleared 0 by reset SNMI is set with a 1 bit or 8 bit memory manipulation instruction RESET inpu
146. input as an alternate function Figure 5 3 shows a block diagram of port 1 Figure 5 3 Block Diagram of P10 to P17 Alternate function lt PIO ANIO to P17 ANI7 Internal bus RD Port 1 read signal Caution Do not execute a read instruction including bit manipulation instructions for port 1 when it is used as an analog input port since port 1 can also be used as A D converter analog input If middle voltage is input to an analog input pin while the port is being read the middle voltage will be read possibly impairing the reliability of the device User s Manual U12697EJAV1UD 109 CHAPTER 5 PORT FUNCTIONS 5 2 3 Port 2 Port 2 is an 8 bit I O port with an output latch The input mode output mode can be specified for the P20 to P27 pins in 1 bit units using the port 2 mode register A pull up resistor can also be connected in 1 bit units via pull up resistor option register 2 regardless of whether the input mode or output mode is specified The P25 and P27 pins can be specified as N ch open drain using a port function control register only the UPD784225Y Subseries Port 2 supports serial interface data I O clock I O clock output and buzzer output as alternate functions RESET input sets port 2 to the input mode Figures 5 4 to 5 7 show a block diagram of port 2 Figure 5 4 Block Diagram of P20 and P22 PU20 PU22 Alternate function A 4 P20 SH RxD1 P22 SCK1 ASCK1
147. into analog values and consists of two voltage output D A converter channels with 8 bit resolution The conversion method is an R 2R resistor ladder Set DACEO of D A converter mode register 0 DAM0 and DACE1 of D A converter mode register 1 DAM1 to start D A conversion The D A converter has the following two modes 1 Normal mode After D A conversion the analog voltage is immediately output 2 Real time output mode After D A conversion the analog voltage is output synchronized with the output trigger Since a sine wave is created when this mode is used MSK modems can be easily incorporated into cordless phones Caution If only one channel of the D A converter is used when lt make either of the following settings at pins that are not used for analog output Set the port mode register PM13X to 1 input mode and connect to Vss Setthe port mode register PM13X to 0 output mode and the output latch to 0 and output a low level 14 2 Configuration The D A converter includes the following hardware Table 14 1 Configuration of D A Converter Registers D A conversion setting register 0 DACSO D A conversion setting register 1 DACS1 Control registers D A converter mode register 0 DAMO D A converter mode register 1 DAM1 248 User s Manual U12697EJAV1UD CHAPTER 14 D A CONVERTER Figure 14 1 Block Diagram of D A Converter Internal bus DACS1 write L INTTM2
148. is used External clock is used Oscillation stabilization time 219 fxx 41 9 ms 218 fxx 21 0 ms 217 fxx 10 5 ms 216 fxx 5 2 ms 215 fxx 2 6 ms 2 4 fxx 1 3 ms 2 3 fxx 655 us 212 fxx 328 us 512 fxx 41 0 us Cautions 1 When a crystal ceramic resonator is used make sure to clear the EXTC bit to O If the EXTC bit is set to 1 oscillation stops 2 When using the STOP mode during external clock input make sure to set the EXTC bit to 1 before setting the STOP mode If the STOP mode is used during external clock input when the EXTC bit of OSTS has been cleared the 0784225 be damaged or its reliability may be impaired 3 If the EXTC bit is set to 1 during external clock input the opposite phase of the clock input to the X1 pin must be input to the X2 pin If the EXTC bit is set to 1 the u PD784225 operates only with the clock input to the X2 pin Remark 1 Figures in parentheses apply to operation at fxx 12 5 MHz 2 x Don t care 96 User s Manual U12697EJAV1UD CHAPTER 4 CLOCK GENERATOR 4 4 System Clock Oscillator 4 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator standard 12 5 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and the reverse phase clock signal
149. it is even a parity error occurs iii O Parity During transmission makes the parity bit 0 regardless of the transmit data A parity bit check is not performed during reception Therefore no parity error occurs regardless of whether the parity bit value is 0 or 1 iv No parity No parity is appended to transmit data Transmit data is received assuming that it has no parity bit No parity error can occur because there is no parity bit 274 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL c Transmission Transmission is begun by writing transmit data to transmission shift register n TXSn The start bit parity bit and stop bit s are automatically added The contents of transmit shift register n TXSn are shifted out upon transmission start and when transmit shift register n TXSn becomes empty a transmit interrupt INTSTn is generated Caution In the case of UART transmission follow the procedure below when performing transmission for the first time lt gt Set the port to the input mode PM21 1 or PM71 1 and write 0 to the port latch 2 Set bit 7 TXEn of asynchronous serial interface mode register n ASIMn to 1 to enable UART transmission output a high level from the TXDn pin 3 Set the port to the output mode PM21 0 or PM71 0 4 Write transmit data to TXSn and start transmission If the port is set to the output mode first 0 will b
150. it is not necessary to save or restore CPU statuses such as the program counter PC and program status word PSW contents This is therefore very effective in improving the CPU service time refer to 22 8 Macro Service Function 22 2 3 Context switching When an interrupt is acknowledged the prescribed register bank is selected by hardware a branch is made to a preset vector address in the register bank and at the same time the current program counter PC and program status word PSW are saved in the register bank refer to 22 4 2 BRKCS instruction software interrupt software context switching acknowledgment operation and 22 7 2 Context switching Remark Context refers to the CPU registers that can be accessed by a program while that program is being executed These registers include general purpose registers the program counter PC program status word PSW and stack pointer SP User s Manual U12697EJAV1UD 363 CHAPTER 22 INTERRUPT FUNCTIONS 22 3 Interrupt Servicing Control Registers uPD784225 interrupt servicing is controlled for each interrupt request by various control registers that specify interrupt servicing The interrupt control registers are listed in Table 22 3 Table 22 3 Control Registers Register Name Symbol Function Interrupt control registers WDTIC PICO PIC1 PIC2 Record the generation of interrupt requests control PIC3 PIC4 PIC5 CSIICO masking specify vectored interrupt servicing or macro
151. latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 5 4 3 Operations I O port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is off the pin status does not change Caution In the case of 1 bit memory manipulation instructions although a single bit is manipulated the port is accessed in 8 bit units Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 134 User s Manual U12697EJAV1UD CHAPTER 6 REAL TIME OUTPUT FUNCTION 6 1 Function The real time output function transfers preset data in the real time output buffer register to the output latch by hardware synchronized with the generation of a timer interrupt or an externalinterrupt and outputs it off the chip The pins for output off the chip are called the real time output port Since jitter free signals can be output by using the real time output port this operation is ideal for the control of stepper motors etc The port mode or real time output mode can be specified in 1 bit
152. level Remark 1 2 User s Manual U12697EJAV1UD 195 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 8 Timing of PWM Output a Basic operation active level H Count clock JU U LH UU U U LH UU TMn OOH JOH TEFA oe 27 TN Na 07 IFEH 00 01H 02H IM TOME TCEn 4 22 22 INTTMn n 3 5 Eie eee j Reload Active level Inactive level Reload Active level b When CRn0 0 Count clock U U LJ UUUULC GCJUULo oJ LILI LI l 1 1 1 TMn OOH JOTH 1 02 TN IN iIN 2 TFFH ooH o1HIO2H V l l l l co X H Q J X l l ee read value 31 7 On bi Inactive level Reload Reload Inactive level c When CRn0 FFH Couteock TLE LT LA LILI LIL Loy LLL LL LLL j TMn OOH o H 2 FFr ooH o1H o2H 7 T N IN N 22 IFFHIooH o1H o2H M _ M X FF X FH 00 EE ERE LEER Ton r Reload l Inactive level Reload Active level Active level Inactive level Inactive level Remark 1 2 196 User s Manual U12697EJAV1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 9 Timing of Operation Based on 0 Transitions a When the CRnO value changes from N to M before TMn overflows pore els oe
153. lt 4 gt lt 5 gt lt 6 gt When the watchdog timer is cleared in a timer interrupt servicing program When there are successive temporary stores of interrupt requests and macro services see 22 9 When Interrupt Requests and Macro Service Are Temporarily Held Pending When an inadvertent program loop is caused by logical errors in the program when each module in the program operates normally but the entire system does not operate properly and when the watchdog timer is periodically cleared When the watchdog timer is periodically cleared by an instruction group that is executed during an inadvertent program loop When the STOP mode and HALT mode or IDLE mode is the result of an inadvertent program loop When the watchdog timer also inadvertently loops when the CPU hangs up because of introduced noise In cases lt 1 gt lt 2 gt and lt 3 gt detection becomes possible by correcting the program In case lt 4 gt the watchdog timer can be cleared only by the 4 byte special instruction Similarly in lt 5 gt if there is no 4 byte special instruction the STOP mode and HALT mode or IDLE mode cannot be set Since the result of the inadvertent program loop is to enter state lt 2 gt three or more bytes of consecutive data must be a specific pattern example BT PSWL bit Therefore the results of lt 4 gt lt 5 gt and the inadvertent program loop are believed to very rarely enter state lt 2 gt 12 4 2 Cautions about the
154. mode in which the internal pull up resistors are not used User s Manual U12697EJ4V1UD 495 CHAPTER 24 STANDBY FUNCTION 4 5 6 496 Are the address bus the address data bus etc handled appropriately The address bus address data bus and RD and WR pins have a high impedance in the STOP and IDLE modes Normally these pins are pulled up by pull up resistors If the pull up resistors are connected to the power supply that is backed up the current flows through the pull up resistors when the low input impedance of the circuit connected to the power supply that is not backed up and the current consumption increases Therefore connect the pull up resistors on the power supply side that is not backed up as shown in Figure 24 10 The ASTB pin has a high impedance in both the STOP and IDLE modes Handle in the manner described in 1 above Figure 24 10 Example of Handling Address Data Bus Power supply that is backed up Power supply that is not backed up Vppo Vppo uPD784225 CMOS IC etc ADn IN OUT n 0 to 7 Vss1 Set the input voltage level applied to the WAIT pin in a range from the Vss voltage to the Vppo voltage Ifa voltage outside of this range is applied not only does the current consumption increase but the reliability of the UPD784225 is negatively affected A D converter The current flowing through the AVpp pin be reduced by clearing the ADCS bit that is bit 7 in th
155. not an operand address 3 When saddrp is saddrp2 in this combination this is a short code length instruction 4 MULUW and DIVUX are identical to MULW User s Manual U12697EJ4V1UD 549 CHAPTER 28 INSTRUCTION OPERATION 3 24 bit instructions The values enclosed by parentheses are combined to express WHL description as rg MOVG ADDG SUBG INCG DECG PUSH Table 28 3 24 Bit Addressing Instructions Second imm24 lladdr24 saddrg operand First operand saddrg lladdr24 mem1 saddrg SP Note There is no second operand or the second operand is not an operand address 4 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR BFSET Table 28 4 Bit Manipulation Instruction Addressing Instructions Second operand saddr bit sfr bit saddr bit sfr bit A bit X bit A bit X bit PSWL bit PSWH bit PSWL bit PSWH bit memo2 bit mem2 bit laddr16 bit addr16 bit First operand lladdr24 bit Naddr24 bit saddr bit sfr bit A bit X bit PSWL bit PSWH bit mem2 bit laddr16 bit lladdr24 bit Note There is no second operand or the second operand is not an operand address 550 User s Manual U12697EJAV1UD CHAPTER 28 INSTRUCTION OPERATION 5 Call return instructions and branch instructions CALL CALLF CALLT BRK RET RETI RETB RETCS RETCSB BRKCS BR BNZ BNE BZ BE BNC BNL BC BL BNV BPO BV BP
156. of Oscillation Stabilization Time Specification Register OSTS 96 4 6 External Circuit of Main System Clock Oscillator 97 4 7 External Circuit of Subsystem Clock Oscillat r u u uu m Sua ua ua usis 98 4 8 Examples of Incorrect Resonator Connection a 99 4 9 Main System Clock Stop Function eccceeeeeeeeneeeeeeeeeeeeeeeeeaeeeeeeeaeeeeeeeeaeeseaeseaeeseaeeseeeseaeeseeeseaeenes 102 4 10 System Clock and CPU 104 5 1 Port GOnmiQuration em 105 5 2 Block DiagramiOtiP00 10 B5 inicia iioii esde oti trece Redit edunt 108 5 8 Block Biagrarmi or 10 o up E eee 109 5 4 Block Diagramiot P20 ard P22 cei N a ui San Raetia ura dadas settle cutest 110 5 5 Block Diagram of P21 P23 to P24 and P26 eee enne 111 5 6 Block Diagram Of P25 RE T dn Les nc EL u eee 112 5 7 Block Diagrami Of ro cm 113 5 8 Block Diagramiof P30 to P32 and PST uuu unn aani ar 114 5 9 Block Diagram oft t0 PSG ER 115 5 10 Block Diagram Of P40 to B4 eer 117 5 11 Block Diagram of P50 toP57 acne ced REE ea Pa deel Re curses nies 119 5 12 Block Dia
157. of the counting for 8 bit timer counters 1 and 2 TM1 2 Selection of the operation mode of 8 bit timer counters 1 and 2 TM1 TM2 Selection of the discrete mode or cascade mode Setting of the state of the timer output only for TMC2 Control of the timer or selection of the active level in PWM free running mode Control of timer output TMC1 and TMC2 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC1 and TMC2 to OOH Figures 9 2 and 9 3 show the TMC1 format and TMC2 format respectively User s Manual U12697EJAV1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 2 Format of 8 Bit Timer Mode Control Register 1 TMC1 Address OFF54H After reset OOH R W Symbol 6 5 4 2 1 0 Counting is disabled prescaler disabled after the counter is cleared to 0 Start counting TMC16 TM1 operation mode selection Clear and start mode when TM1 and CR10 match PWM free running mode Timer output control by software No change Reset to 0 Set to 1 Setting prohibited Other than PWM mode TMC16 0 PWM mode TMC16 1 Timer output control Active level selection Disable inversion operation Active high Enable inversion operation Active low TOE1 Timer output control Output disabled port mode Output enabled Caution When selecting the TM1 operation mode using TMC16 stop the timer operation in advance Remarks 1
158. output latch to 0 39 Set bit PM23 of the port mode register PM2 to 0 to set the output mode 4 Set bit 4 CLOE of CKS to 1 Caution If the output latch of P23 is set to 1 clock output cannot be used Remark Theclock output function is designed so that pulses with a narrow width are not output when clock output enable disabled is switched See in Figure 19 1 Figure 19 1 Remote Control Output Application Example PCL P23 pin output TEE 350 User s Manual U12697EJAV1UD CHAPTER 19 CLOCK OUTPUT FUNCTION 19 2 Configuration The clock output function includes the following hardware Table 19 1 Configuration of Clock Output Function Control registers Clock output control register CKS Port 2 mode register PM2 Figure 19 2 Block Diagram of Clock Output Function fxx fxx 2 fxx 2 fxx 2 2 25 25 fxx 27 fxr Synchronization J gt hz orcus Selector Clock output control register Port 2 mode register PM2 Internal Bus 19 3 Control Registers The following two registers are used to control the clock output function Clock output control register CKS Port 2 mode register PM2 1 Clock output control register CKS This register sets the PCL output clock CKS is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CKS to 00H Remark CKS provides a function for setting the buzzer o
159. patrone pini pev eve pate rese EUER Eden 195 9 4 5 Operation as interval timer 16 bit operation u 198 9 5 CAUTIONS esses ce Seca LUI LL eei 199 CHAPTER 10 8 BIT TIMERS 5 200 bI 200 Joann 201 10 3 Control Registers eror is Ra Z as sss 204 10 4 grec E 208 10 4 1 Operation as interval timer 8 bit operation en 208 10 4 2 Operation as interval timer 16 bit operation u 213 10 5 CAUtlOMS u 214 CHAPTER 11 WATCH TIMER u u uu cones ce enne awasqa cran 215 TET FUNCIO mE CE 215 216 11 3 Watch Timer Control Register u u u u u J 217 11 4 Op rati i u u u SS oR oo 219 11 41 Operation as Watch timer cierre tti eor ahus 219 Tt 4 2 Operation as interval sasan squa 219 CHAPTER
160. pending non maskable interrupt is acknowledged after completion of the non maskable interrupt service program currently being executed after execution of the RETI instruction However even if the same non maskable interrupt request is generated more than once during execution of the non maskable interrupt service program only one non maskable interrupt is acknowledged after completion of the non maskable interrupt service program User s Manual U12697EJAV1UD 379 CHAPTER 22 INTERRUPT FUNCTIONS 380 Figure 22 10 Non Maskable Interrupt Request Acknowledgment Operations 1 2 a When a new NMI request is generated during NMI service program execution Main routine NMIS 1 d NMI request NMI request NMI request held pending since NMIS 1 Pending NMI request is serviced A b When a watchdog timer interrupt request is generated during NMI service program execution when the watchdog timer interrupt priority is higher when WDT4 in the WDM 1 Main routine Watchdog timer interrupt request NMI request User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 10 Non Maskable Interrupt Request Acknowledgment Operations 2 2 c When a watchdog timer interrupt request is generated during NMI service program execution when the NMI interrupt priority is higher when WDT4 in the WDM 0 Main routine NMI request Watchdog timer interrupt request
161. products are shown below On chip flash memory version Mask ROM version LPD78F4225Y uPD784225Y uPD78F4225 uPD784225 ROM 128 KB RAM 4352 bytes uPD784224Y uPD784224 ROM 96 KB RAM 3584 bytes Flash memory 128 KB RAM 4352 bytes These products have applications in the following fields Car audio portable audio telephones etc User s Manual U12697EJAV1UD 31 CHAPTER 1 OVERVIEW 78K IV SERIES LINEUP C Products in mass production Supports bus uPD784038Y uPD784038 Enhanced internal memory capacity Pin compatible with the uPD784026 Supports multimaster bus uPD784225Y uPD784225 80 pin ROM correction added Standard models uPD784026 Supports multimaster 2 bus Enhanced Supports multimaster bus A D converter 784216 784218 16 bit timer and power management uPD784216A uPD784218A 100 pin enhanced I O and Enhanced internal memory internal memory capacity capacity ROM correction added u PD784054 uPD784046 ASSP models On chip 10 bit A D converter LPD784956A 2 L PD784938A For DC inverter control Enhanced functions of the uPD784908 UPD784908 enhanced internal memory capacity On chip IEBus controller ROM correction added Supports multimaster IC bus uPD784928Y Lu PD784928 PD784915 Enhanced functions Software servo control of the uPD784915 On chip analog circ
162. program at priority level 3 Executing a maskable interrupt The instruction following MOV STBC service program with the same byte is executed priority The interrupt request that released This excludes executing an interrupt the HALT mode is held pendingNete 3 service program in priority level 3 when the PRSL bitNete 4 is cleared to 0 Executing a high priority interrupt service program Holds the HALT mode Macro service Macro service processing execution request End condition is not satisfied End HALT mode condition is satisfied again When VCIENote 5 1 HALT mode again When VCIENete 5 o Same as release by maskable interrupt request Holds the HALT mode Notes 1 Interrupt mask bit in each interrupt request source 2 Interrupt enable flag in the program status word PSW The pending interrupt request is acknowledged when acknowledgement is enabled Bit in the interrupt mode control register IMC m gt Bit in the macro service mode register of the macro service control word that is in each macro service request source User s Manual U12697EJ4V1UD 473 CHAPTER 24 STANDBY FUNCTION Figure 24 5 Operations After Releasing HALT Mode 1 4 1 Interrupt after HALT mode Main routine MOV STBC byte HALT mode 2 Reset after HALT mode Interrupt request HALT mode release Interrupt servicing Main routine MOV STBC byte HALT mode RES
163. register INTP4 PIC4 OFFE6H Interrupt control register INTP5 PIC5 OFFE8H Interrupt control register INTIICONete 2 INTCSIO CSIICO OFFE9H Interrupt control register INTSER1 SERIC1 OFFEAH Interrupt control register INTSR1 INTCSI1 SRIC1 OFFEBH Interrupt control register INTST1 STIC1 OFFECH Interrupt control register INTSER2 SERIC2 OFFEDH Interrupt control register INTSR2 INTCSI2 SRIC2 OFFEEH Interrupt control register INTST2 STIC2 OFFEFH Interrupt control register INTTM3 TMIC3 OFFFOH Interrupt control register INTTM00 TMICOO OFFF1H Interrupt control register INTTMO 1 TMICO1 OFFF2H Interrupt control register INTTM1 OFFF3H Interrupt control register INTTM2 TMIC2 OFFF4H Interrupt control register INTAD ADIC OFFF5H Interrupt control register 5 TMIC5 OFFF6H Interrupt control register INTTM6 TMIC6 OFFF9H Interrupt control register INTWT WTIC Es a S oa ee az m RS ee RU ARS ee et m OFFFCH Notes 88 Internal memory size switching registerNote 3 IMS Doe es mns es DLE lt S l Sos ES o su eism These values are when the LOCATION OH instruction is executed When the LOCATION 0FH instruction is executed FOOOOH is ad
164. register STBC can be read PCS is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PCS to 32H Figure 24 3 Format of Clock Status Register PCS Address OFFCEH After reset 32H R Symbol 7 6 5 4 3 2 1 0 Feedback resistor state for subsystem clock Internal feedback resistors used Internal feedback resistors not used CPU clock operating frequency fxx 2 fxx 4 fxx 8 fxt recommended fxr 0 Oscillator operating 1 Oscillator stopped 0 Main system clock operation 1 Subsystem clock operation Remark x Don t care User s Manual U12697EJAV1UD 467 CHAPTER 24 STANDBY FUNCTION 3 468 Oscillation stabilization time specification register OSTS The OSTS register sets the oscillator operation and the oscillation stabilization time when the STOP mode is released Whether a crystal ceramic oscillator or an external clock will be used is set by the EXTC bit of OSTS If only the EXTC bit is set to 1 the STOP mode can also be set when the external clock is input Bits OSTS0 to OSTS2 in OSTS select the oscillation stabilization time when the STOP mode is released Generally select an oscillation stabilization time of at least 40 ms when using a crystal oscillator and at least 4 ms when using a ceramic oscillator The time until the oscillation stabilizes is affected by the crystal ceramic oscillator that is used and the capacitance of the connected capacit
165. resistor option register 7 PU 131 Pull up resistor option register 12 PU12 131 R Real time output buffer register H RTBH 136 Real time output buffer register L RTBL 136 User s Manual U12697EJ4V1UD 615 APPENDIX D REGISTER INDEX Real time output port control register RTPC 138 Real time output port mode register RTPM 137 Receive shift register RX1 258 Receive shift register RX2 258 Receive buffer register 1 RXB1 258 Receive buffer register 2 RXB2 258 ROM correction address register H CORAH 509 ROM correction address register L CORAL 509 ROM correction control register CORC 509 S Serial I O shift register 0 5100 Serial I O shift register 1 SIO1 Serial I O shift register 2 SIO2 279 Serial operation mode register 0 CSIMO 286 287 288 Serial operation mode register 1 CSIM1 280 281 282 Serial operation mode register 2 5 2 280 281 282 Serial shift register 0 IICO 294 305 Slave address register 0 SVAO 294 305 Standby control register STBC 91 92 464 465 284 279 T Transmission shift register 1 TXS1 258 Transmission shift register 2 TXS2 258 W Watch timer mode control register WTM 216 Watchdog timer mode register WDM 221 373 8 8 bit compare register 10 CR10 182 8 bit compare register 20 CR20 182 8 bit compare register 50
166. s Manual U12697EJ4V1UD 4 4 1 Main system clock oscillator tret nea RS eee 4 442 Subsystem clock oscillator rris 4 4 8 Examples of incorrect resonator connection 4 4 4 Frequency divider secesii niinc detecte ier cL c deo a Sasa IE ee 4 4 5 When subsystem clock is not used eene rennen nennen nnn nnn 4 5 Clock Generator Operations U 4 5 1 Main system clock operations ooo exe Pues 42522 S bsystem clock operationis ce ee vein Pe re L eva 4 6 Changing System Clock and CPU Clock Settings CHAPTER 5 PORT FUNCTIQNS L err n Yn amma ce nando 5 1 Digit l WO POTIS tec 5 2 Port cenewcedecressececeseasencxesceetcudie reves ecueccvastescaueeeveecierseaeedsen 5 2 1 PON m 5 22 EE 5 2013 2 E D24 ROMS aksa 529 POM RE 326 POM S ron a aT aA Or Aaoi 52 7 EE E
167. s Manual U12697EJAV1UD CHAPTER 27 wPD78F4225 AND 4PD78F4225Y PROGRAMMING The flash memory versions in the uPD784225 and 784225Y Subseries are the uPD78F4225 and 78F4225Y The LPD78F4225 and uPD78F4225Y are described in this chapter using the PD78F4225 as the representative product The uPD78F4225 and 78F4225Y are versions with on chip flash memories that enable programs to be written deleted and overwritten while mounted on the substrate The differences between the flash memory versions uPD78F4225 and 78F4225Y and mask ROM versions uPD784224 784225 784224Y and 784225Y are shown in Table 27 1 Table 27 1 Differences Between uPD78F4225 78F4225Y and Mask ROM Versions uPD78F4225 78F4225Y Mask ROM Versions Internal ROM structure Flash memory Mask ROM Internal ROM capacity 128 KB uPD784224 784224Y 96 KB LPD784225 784225Y 128 KB Internal RAM capacity 4 352 bytes LPD784224 784224Y 3 584 bytes LPD784225 784225Y 4 352 bytes Changing internal ROM capacity using PossibleNete Not possible the internal memory size switching register IMS TEST pin None Provided VPP pin Provided None Note The capacity of the flash memory will become 128 KB and the internal RAM capacity will become 4 352 bytes by RESET input Caution There differences in noise immunity and noise radiation between the flash memory and mask ROM versions When pre producing an application set with the flash memory version and t
168. service priority register 371 M MK0H Interrupt mask flag register 0H 369 370 MKOL Interrupt mask flag register OL 369 370 MK1H Interrupt mask flag register 1H 369 370 MK1L Interrupt mask flag register 1L 369 370 MM Memory expansion mode register 437 O OSTS Oscillation stabilization time specification register 95 467 P P0 Port 0 106 P1 Port 1 108 P2 Port 2 109 P3 Port 3 113 Port 4 115 P5 Port 5 117 P6 Port 6 119 P7 Port 7 123 P12 Port 12 126 P13 Port 13 127 PCS Clock status register 94 466 PF2 Port function control register 2 132 PICO Interrupt control register 366 Interrupt control register 366 PIC2 Interrupt control register 366 PIC3 Interrupt control register 366 PIC4 Interrupt control register 366 PIC5 Interrupt control register 366 PMO Port 0 mode register 128 PM Port 2 mode register 128 352 355 PM3 Port 3 mode register 128 PMA Port 4 mode register 128 5 Port 5 mode register 128 PM6 Port 6 mode register 128 7 Port 7 mode register 128 PM12 Port 12 mode register 128 PM13 Port 13 mode register 128 PRMO Prescaler mode register 0 154 PRM1 Prescaler mode register 1 186 PRM2 Prescaler mode register 2 186 187 PRM5 Prescaler mode register 5 205 PRM6 Prescaler mode register 6 205 206 6
169. setting data 0 is read 186 User s Manual U12697EJAV1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 2 Prescaler mode registers 1 and 2 PRM1 PRM2 This register sets the count clock of 8 bit timer counters 1 and 2 TM1 2 and the valid edge of the 1 and TI2 inputs PRM1 and PRM2 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PRM1 and PRM2 to OOH Figure 9 4 Format of Prescaler Mode Register 1 PRM1 Address OFF56H After reset OOH R W Symbol 7 6 5 4 2 1 0 Count clock selection Falling edge of TI1 Rising edge of T11 fxx 4 3 13 MHz fxx 8 1 56 MHz bo 16 781 kHz fxx 32 391 kHz fxx 128 97 6 kHz fxx 512 24 4 kHz Cautions 1 If data different from that of PRM1 is written stop the timer beforehand 2 sure to set bits to 7 of to 0 3 When specifying the valid edge of TI1 for the count clock set the count clock to fxx 4 or below Remark Values in parentheses apply to operation at fxx 12 5 MHz User s Manual U12697EJAV1UD 187 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 5 Format of Prescaler Mode Register 2 PRM2 Address OFF57H After reset OOH R W Symbol 7 6 5 4 2 1 0 Count clock selection Falling edge of Tl2 Rising edge of TI2 fxx 4 3 13 MHz fxx 8 1 56 MHz fxx 16 781 kHz fxx 32 391 kHz fxx 128 97 6 kHz fxx 512 2
170. signal low level hold time tow only the maximum data hold time tup pat needs to be satisfied 4 The high speed mode I C bus can be used in a standard mode bus system In this case the conditions described below must be satisfied e f the device does not extend the SCLO signal low level hold time tsu paT gt 250 ns e f the device extends the SCLO signal low level hold time sure to transmit the data bit to the SDAO line before the SCLO line is released tsu DAT 1 000 250 1 250 ns by standard mode lC bus specification 5 Cb Total capacitance per bus line unit pF 582 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 4 Clock Output Operation Ta 40 to 85 AVpp 1 9 to 5 5 V Vss AVss 0 V Parameter Conditions PCL cycle time 4 5 V lt lt 5 5 V nT 31 250 PCL high low level 4 5 V lt 5 5 V 0 5T 10 15 615 width PCL rise fall time 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 1 9 V lt Voo lt 2 7 V Remark T tcvk 1 fxx fxx Main system clock frequency n Division ratio set by software in the CPU e When using the main system clock n 1 2 4 8 16 32 64 128 When using the subsystem clock 1 5 Other Operations Ta 40 to 85 AVpp 1 9 to 5 5 V Vss AVss 0 V Parameter Conditions NMI high low level width Interrupt input high IN
171. square wave 8 bit resolution A square wave with any frequency is output at the interval preset in 8 bit compare registers 10 and 20 CR10 CR20 By setting bit 0 of 8 bit timer mode control registers 1 and 2 TMC1 TMC2 to 1 the output state of TO1 and TO2 is inverted with the count preset in CR510 and CR20 as the interval Therefore square wave output of any frequency duty cycle 50 is possible Setting method 1 lt 2 gt lt 3 gt lt 4 gt Set the registers Set the port latch which also functions as a timer output pin and the port mode register to 0 PRMn Selects the count clock e 0 Compare value TMCn Clear and start mode when TMn and CRnO match Timer Output Control by Software High level output Low level output Inversion of timer output enabled Timer output enabled TOEn 1 When TCEn 1 is set the counter starts operating If the values of TMn and CRnO match the timer output is inverted Also INTTMn is generated and TMn is cleared to OOH Then the timer output is inverted at the same interval to output a square wave from TOn Remark 1 2 194 User s Manual U12697EJ4V1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 4 4 Operation to output 8 bit PWM By setting bit 6 TMC16 TMC26 of 8 bit timer mode control registers 1 and 2 TMC1 TMC 2 to 1 the timer operates as a PWM output Pulses with the duty cycle determined by the value set in 8 bit com
172. state in which the subsystem clock is used as the system clock and the main system clock is stopped Figure 24 11 shows the flow for setting subsystem clock operation Figure 24 12 shows the setting timing diagram Figure 24 11 Flow for Setting Subsystem Clock Operation Normal operation using the main system clock Write STBC 70H Execute the instruction to switch to the subsystem clock N Verify the switch to the subsystem clock dl Yes Stop the oscillation of Write STBC 74H the main system clock Switch to the backup power supply End User s Manual U12697EJAV1UD 497 CHAPTER 24 STANDBY FUNCTION Figure 24 12 Setting Timing for Subsystem Clock Operation Main system clock step main system cock oscitaton 1 Subsystem clock um 1 System clock STBC 00H 70H 74H Subsystem clock CST bit I Power supply Main power supply rBackup power supply ss Power supply switching 24 7 2 Returning to main system clock operation When returning to main system clock operation from subsystem clock operation the system power supply first switches to the main power supply and enables the oscillation of the main system clock set STBC 70H Then the software waits for the oscillation stabilization time of the main system clock and the system clock switches to the main system clock set STBC to OOH Cautions 1
173. t care When WTIM0 1 Al A2 A1 A2 A3 4 50 0001x110B 50 0001x100B 50 0001 00 50 00000001B Remarks Always generated A Generated only when SPIE0 1 x Don t care User s Manual U12697EJ4V1UD 317 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 318 b Start Address Data Start Address Data Stop lt 1 gt When WTIMO 0 SVA0 match after restart lt 2 gt A1 A2 A3 A4 A 5 A1 50 0001x110B A2 50 0001x000B 50 0001x110B A4 50 0001x000B ICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care When WTIMO 1 SVAO match after restart Al A2 A3 4 AS A1 50 0001x110B A2 50 0001xx00B 50 0001x110B A4 11 50 0001 00 50 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY c Start Address Data Start Code Data Stop lt 1 gt When WTIMO 0 extended code received after restart lt 2 gt A1 A3 A2 A4 A5 A1 11 50 0001x110B A2 50 0001x000B 50 0010x010B A4 50 0010x000B IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care When WTIMO 1 extended code
174. the falling edge of the eighth clock Clear condition WTIMO 0 Nete Set condition WTIMO 1 Cleared by an instruction Setbyan instruction When RESET is input Acknowledge control Acknowledge is disabled Acknowledge is enabled The SDAO line during the ninth clock period goes low However the control is invalid during an address transfer When EXCO 1 the control is valid Clear condition ACKEO 0 Nete Set condition ACKEO 1 Cleared by an instruction Set by an instruction When RESET is input Note This flag signal becomes invalid by setting IICEO to 0 298 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 3 Format of I2C Bus Control Register 0 IICCO 3 4 STTO Start condition trigger The start condition is not generated When the bus is released stop condition The start condition is generated started as the master The SDAO line is changed from high to low and the start condition is generated Then the standard time is guaranteed and SCLO goes low When not participating with the bus The trigger functions as the start condition reserved flag When set the start condition is auto matically generated after the bus is released Wait status when master The wait status is canceled and the restart condition is generated Cautions on set timing Master reception Setting is prohibited during transfer STTO can b
175. the master and the bus is released Clear condition SPDO 0 Set condition SPDO 1 Remark After the bit is set at the rising edge of the first clock in the address transfer byte after detecting the start condition When IICEO 1 gt 0 When RESET is input IICE0 When the stop condition is detected LRELO Bit 6 of 12C bus control register 0 IICCO Bit 7 of 12C bus control register 0 IICCO User s Manual U12697EJ4V1UD 303 CHAPTER 18 12 BUS MODE uPD784225Y SUBSERIES ONLY 3 Prescaler mode register 0 for serial clock SPRM0 The SPRMO register sets the transfer clock of the 2 bus SPRMO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets SPRMO to 00H Figure 18 5 Format of Prescaler Mode Register 0 for Serial Clock SPRMO 1 2 Address OFFB2H After reset 00H R wNete Symbol 7 6 3 2 1 0 SCLO line level detection valid only when IICEO 1 Detects a low SCLO line Detects a high SCLO0 line Clear condition CLD 0 Set condition CLD 1 When the SCLO line is low When the SCLO line is high When IICEO 0 When RESET is input SDAO line level detection valid only when IICEO 1 Detects a low SDAO line Detects a high SDAO line Clear condition DAD 0 Set condition DAD 1 When the SDAO line is low When the SDAO line is high When 0 When RESET is input Note Bit
176. trigger 286 When MODEO 0 reading is disabled and when MODEO 1 writing is disabled User s Manual U12697EJAV1UD CHAPTER 17 3 WIRE SERIAL I O MODE 17 3 Control Registers Serial operation mode register 0 CSIMO The CSIMO register sets the serial clock and operation mode to the 3 wire serial mode and enables or stops operation CSIMO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Figure 17 2 Format of Serial Operation Mode Register 0 CSIMO Address OFF90H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIMO CSIEO 0 o o o MODEO 5 101 SCLOO SIOO operation enable disable setting Shift register operation Operation disabled Serial counter Clear Port Port functionNote Operation enabled Count enabled Transfer operation mode flag Serial function Port function Operation mode Transmit receive Transfer start trigger SIOO write 500 output Normal output communication mode SIOO read Fixed low Receive only mode Clock selection External clock to SCKO 8 bit timer counter 2 TM2 output TO2 fxx 8 1 56 MHz bo 16 781 kHz Note If CSIEO 0 5100 operation stopped state the pins connected to 510 500 and SCKO can function as ports Cautions 1 Set8 bit timer mode control register 2 TMC2 as follows when selecting 8 bit timer counter 2 TM2 output as the c
177. using the 78K IV Series Supports the integrated debugger ID78K4 NS Use in combination with an interface adapter to connect to the power supply unit emulation probe and host machine IE 70000 MC PS B Power supply unit Adapter to supply power from a socket of AC 100 V to 240 V IE 70000 98 IF C Interface adapter Interface adapter required when a PC 9800 series PC except notebook type is used as the host machine for the IE 78K4 NS C bus supported IE 70000 CD IF A PC card Interface PC card and interface cable required when a notebook PC is used as the host machine for the IE 78K4 NS PCMCIA socket supported IE 70000 PC IF C Interface adapter Interface adapter required when using an IBM PC AT compatible as the host machine for the IE 78K4 NS ISA bus supported IE 70000 PCI IF A Interface adapter Interface adapter required when using a PC that incorporates PCI bus as the host machine for the IE 78K4 NS IE 784225 NS EM1 Emulation board Board to emulate the peripheral hardware specific to device Used in combination with an in circuit emulator NP 80GK Emulation probe Probe used to connect the in circuit emulator and the target system This is for an 80 pin plastic TQFP fine pitch GK 9EU type TGK 080SDW Conversion adapter refer to Figure B 4 Conversion adapter to connect the NP 80GK and a target system board on which an 80 pin plastic TQFP fine pitch GK 9EU type can be
178. write signal User s Manual U12697EJ4V1UD CHAPTER 5 PORT FUNCTIONS Figure 5 14 Block Diagram of P66 WRPuo Pull up resistor option register 5 RDpuo WRPus Port 6 mode register gt PM66 RDpme rio External wait mode B8 WRpes 5 Output latch AIL e P66 e P66 WAIT Wait input 1 7 Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal User s Manual U12697EJ4V1UD 123 CHAPTER 5 PORT FUNCTIONS 5 2 8 Port 7 This is 3 bit I O port with an output latch Input mode output mode can be specified for the P70 to P72 pins in 1 bit units using the port 7 mode register A pull up resistor can be connected via pull up resistor option register 7 regardless of whether the input mode or output mode is specified Port 7 supports serial interface data I O and clock I O as alternate functions RESET input sets port 7 to the input mode Figures 5 15 to 5 17 show block diagrams of port 7 Figure 5 15 Block Diagram of P70 D gt P ch Alternate function e A Internal bus uc n 4 P7O SI2 RXD2 PU Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal 124 User s Manual U12697EJ4V1UD CHAPTER 5 PORT FUNCTIONS Figure 5 16 Block Diagr
179. 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Figure 17 4 Format of Serial Operation Mode Register 0 CSIMO Address OFF90H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 SIOO operation enable disable setting Shift register operation Serial counter Port Operation disabled Clear Port functionNote Operation enabled Operation count enabled Serial function port function Transfer operation mode flag Operation mode Transfer start trigger 500 output Transmit receive SIOO write Normal output communication mode Receive only mode SIOO read Low level fixed Clock selection External clock to SCKO 8 bit timer counter 2 TM2 output TO2 fxx 8 1 56 MHz fxx 16 781 kHz Note If CSIEO 0 SIOO operation stopped state the pins connected to 510 500 and 5 can function as ports Cautions 1 Set8 bit timer mode control register 2 TMC2 as follows when selecting 8 bit timer counter 2 TM2 output as the clock TMC26 0 24 0 LVS2 0 LVR2 0 TMC21 1 Moreover set TOE2 to 0 when TO2 is not output externally and TOE2 to 1 when TO2 is output externally 2 Set the external clock and TO2 to fxx 8 or below when selecting the external clock SCKO and TM2 output TO2 for the clock Remark Figures in parentheses apply to operation at fxx 12 5 MHz 290 User s Manual U12697EJ4V1UD CHAPTER 17 3
180. 0 TMPR001 TMCSE00 INTTM01 TMIC01 TMIF01 TMMK01 5 01 010 011 TMCSE01 INTTM1 TMIC1 TMIF1 TMMK1 TMISM1 TMPR10 TMPR11 TMCSE1 INTTM2 TMIC2 TMIF2 TMMK2 TMISM2 TMPR20 TMPR21 TMCSE2 INTAD ADIC ADIF ADMK ADISM ADPROO ADPRO01 ADCSE INTTM5 5 TMIF5 TMMK5 TMISM5 TMPR50 TMPR51 TMCSE5 INTTM6 TMIC6 TMIF6 TMMK6 TMISM6 TMPR60 TMPR61 TMCSE6 INTWT WTIC WTIF WTMK WTISM User s Manual U12697EJ4V1UD WTPRO WTPR1 WTCSE 365 CHAPTER 22 INTERRUPT FUNCTIONS 22 3 1 Interrupt control registers An interrupt control register is allocated to each interrupt source and performs priority control mask control etc for the corresponding interrupt request The interrupt control register format is shown in Figure 22 1 1 2 3 4 5 366 Priority specification flags CcxPR1 xxPRO The priority specification flags specify the priority of individual interrupt sources for the 23 maskable interrupts Up to 4 priority levels can be specified and a number of interrupt sources can be specified at the same level Among maskable interrupt sources level 0 is the highest priority If multiple interrupt requests are generated simultaneously among interrupt source of the same priority level they are acknowledged in default priority order These
181. 0000H A one pulse count operation is consequently not possible when using these registers as event counters 3 Operation after changing compare register during timer count operation If the value to which the current value of 16 bit capture compare register 00 CR00 has been changed is less than the value of 16 bit timer counter 0 TM0 TM0 continues counting overflows and starts counting again from 0 If the new value of CROO M is less than the old value N the timer must be restarted after the value of CR00 has been changed Figure 8 30 Timing After Changing Compare Register During Timer Count Operation Count pulse PN SF Na a x x CROO N X TM0 count value X 1 x X FFFFH 0000H 0001H 0002H Remark gt X gt M 176 User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 4 Data hold timing of capture register If the valid edge is input to the TI00 P35 pin while 16 bit capture compare register 01 CR01 is being read CR01 performs the capture operation but this capture value is not guaranteed However the interrupt request flag INTTM01 is set as a result of detection of the valid edge Figure 8 31 Data Hold Timing of Capture Register TMO count value N N41 N 2 XX M 1 M 2 Edge input N Interrupt request flag Capture read signal Capture operation ignored 5 Setting valid edge To set the valid edge of the TIOO P35 pin set bits 2 and 3 of 16 bit timer mode c
182. 01 PM33 to PM36 Pull up resistor option register Port mode register Port 3 read signal Port 3 write signal User s Manual U12697EJ4V1UD 115 CHAPTER 5 PORT FUNCTIONS 5 2 5 Port 4 Port 4 is an 8 bit I O port with an output latch The input mode output mode can be specified for the P40 to P47 pins in 1 bit units using the port 4 mode register When the P40 to P47 pins are used as input ports a pull up resistor can be connected in 8 bit units via bit 4 PUO4 of the pull up resistor option register Port 4 can drive LEDs directly Port 4 supports the address data bus function in the external memory expansion mode as an alternate function RESET input sets port 4 to the input mode Figure 5 10 shows a block diagram of port 4 116 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS Internal data bus Figure 5 10 Block Diagram of P40 to P47 PM40 to P47 Output latch RDP4 P40 to P47 MMO to MM3 controller External access data PUO PM RD WR o a o o o 79 2 Pull up resistor option register Port mode register Port 4 read signal Port 4 write signal User s Manual U12697EJ4V1UD P40 ADO to PA7 AD7 117 CHAPTER 5 PORT FUNCTIONS 5 2 6 Port 5 Port 5 is an 8 bit I O port with an output latch The input mode output mode can
183. 1 SERIF1 STIF1 User s Manual U12697EJAV1UD SRIC2 SERIC2 STIC2 SRIF2 SERIF2 STIF2 255 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL I O 16 1 Switching Asynchronous Serial Interface Mode and 3 Wire Serial I O Mode The asynchronous serial interface mode and the 3 wire serial I O mode cannot be used at the same time These modes can be switched by setting asynchronous serial interface mode registers 1 and 2 ASIM1 ASIM2 and serial operation mode registers 1 and 2 CSIM1 CSIM2 as shown in Figure 16 1 below Figure 16 1 Switching Asynchronous Serial Interface Mode and 3 Wire Serial I O Mode OQ 5 4 2 1 0 Address After R W reset ASIM1 TXE1 RXE1 PS11 PS10 511 ISRM1 0 OFF70H 00H R W 2 TXE2 2 PS21 PS20 ci2 512 ISRM2 OFF71H 00H R W Specification of operation in asynchronous serial interface mode see Figure 16 3 CSIE1 Operation stopped mode 3 wire serial mode Asynchronous serial interface mode 1 Other than above Setting prohibited dS 5 4 3 2 1 O Address After R W reset CSIM1 CSIE1 o wo SCL11 SCL10 OFFO91H R W ERE Specification of operation in 3 wire serial I O mode see Figure 16 13 256 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL
184. 1 Note 2 clock continues oscillating clock stops oscillating Clock generator Both the main system clock and subsystem clock can oscillate The clock supply to the CPU stops CPU Operation disabled Port output latch Holds the state before the HALT mode was set Operation enabled Operational when the watch timer output is selected as the count clock Select fxt as the count clock of the watch timer 16 bit timer counter Operation enabled Operational when 1 and TI2 are selected as the count clocks 8 bit timer counters 1 2 Operation enabled Operational when TI5 and TI6 are selected as the count clocks 8 bit timer counters 5 6 Watch timer Operational when fxx 27 is selected as the count clock Operation enabled Operational when fxr is selected as the count clock Watchdog timer Operation disabled initializing counter A D converter Operation enabled Operation disabled D A converter Operation enabled Real time output port Operation enabled Serial interface Operation enabled Operational during external SCK External interrupt INTPO to INTP5 Operation enabled Bus lines during ADO to AD7 High impedance external expansion Ag to A19 Holds the state before the HALT mode was set Low level High level Holds input status Notes 1 Including when an external clock is not supplied 2 Inclu
185. 12 WATCHDOG iC uev nan Tun AEEA NEARER AARAA 221 12 eniicuigmee a AR 221 12 2 COMUrOl ROGISCON em M 222 12 3 Op ratioiilguuu u i OS SPR 224 12 94 COUN Operation t Ee Ripe Q aie Lee a a asha aB Ru 224 12 3 2 Interrupt priority order ni Leti ec eee ck a aset ee quete lasqa 224 12 4 R u qaglss 225 12 4 1 General cautions when using the watchdog timer u 225 12 4 2 Cautions about the uPD784225 Subseries watchdog 225 CHAPTER 13 A D CONVERTER retenir mna enn uni aua 226 TST Entona ccc coach eee sted eee uere teo entire cde nape uiu dtr ren uL ted rre die LI e Le LIEU 226 13 2 Configuration usut u usu 226 13 3 enilulidcemec 229 14 User s Manual U12697EJ4V1UD 13 4 edJcupIm 232 13 4 1 Basic operations of A D 4 232 13 4 2 Input voltage and conversion result 234 18 4 3 Operation modes of A D converter u 235 13 5 Reading A D Converter Characteristics Table u u u
186. 130 131 2 2 V lt Voo lt 5 5 V 0 3Vpp 1 9 V lt Voo lt 2 2 V 0 2Vpp X1 X2 XT1 XT2 2 2 V lt Voo lt 5 5 V 0 2Vpp 1 9 V lt lt 2 2 V 0 1Vpp P25 P27 2 2 V lt Voo lt 5 5 V 0 3Vpp OcO ojo o o o o o o oI o 1 9 V lt Voo lt 2 2 V 0 2Vpp Input voltage high 2 2 V lt Voo lt 5 5 V 1 9 V lt Voo lt 2 2 V P00 to P05 P20 P22 P33 2 2 V lt Voo lt 5 5 V P34 P70 P72 RESET 1 9 V lt Voo lt 2 2 V P10 to P17 P130 P131 2 2 V lt Voo lt 5 5 V 1 9 V lt Voo lt 2 2 V X1 X2 XT1 XT2 2 2 V x Voo lt 5 5 V 1 9 V lt Voo lt 2 2 V P25 P27 2 2 V lt Voo lt 5 5 V 1 9 V lt Voo lt 2 2 V Output voltage low For pins other than 4 5 V lt lt 5 5 V P40 to P47 P50 to P57 lo 1 6 mANote 2 P40 to P47 P50 to P57 4 5 V Voo lt 5 5 V lo 8 mANote 2 lo 400 pANote 2 1 9 V lt Voo lt 5 5 V Output voltage high lon 1 mANote 2 4 5 V Voo 5 5 V lon 100 pANote 2 1 9V lt Vo lt 5 5V Input leakage current Vi 0 V Except X1 X2 low XT1 XT2 X1 X2 XT1 XT2 Input leakage current Except X1 X2 high XT1 XT2 X1 X2 XT1 XT2 Notes 1 P21 P23 P24 P26 P30 to P32 P35 to P37 P40 to P47 P50 to P57 P60 to P67 P71 P120 to P127 2 Per pin 574 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Cha
187. 18 User s Manual U12697EJ4V1UD APPENDIX D REGISTER INDEX PSW PU0 PU2 PU3 PUT PU12 PUO PWC1 PWC2 R RTBH RTBL RTPC RTPM RX1 RX2 RXB1 RXB2 S SERIC1 SERIC2 SIOO SIO1 SIO2 SNMI SPRMO SRIC1 SRIC2 STBC STIC1 STIC2 SVAO T TMO TM1 2 TM5 TM6 TMCO TMC1 TMC2 TMC5 TMC6 TMICOO TMICO1 Program status word 375 Pull up resistor option register 0 131 Pull up resistor option register 2 131 Pull up resistor option register 3 131 Pull up resistor option register 7 131 Pull up resistor option register 12 131 Pull up resistor option register 131 Programmable wait control register 1 438 Programmable wait control register 2 438 Real time output buffer register H 136 Real time output buffer register L 136 Real time output port control register 138 Real time output port mode register 137 Receive shift register 1 258 Receive shift register 2 258 Receive buffer register 1 258 Receive buffer register 2 258 Interrupt control register 367 Interrupt control register 367 Serial I O shift register 0 284 Serial I O shift register 1 279 Serial I O shift register 2 279 Interrupt selection control register 374 Prescaler mode register O for serial clock 303 Interrupt control register 367 Interrupt control register 367 Standby control register 91 92
188. 1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 31 Type C Macro Service Channel 2 2 b With ring control Higher addresses t Hig Bits 8 to 15 TSFR Macro service counter MSC Bits 0 to 7 Timer SFR pointer TSFRP DSFR Bits 16 to 23 Note Timer macro service Timer buffer area pointer MPT Bits 8 to 15 Macro service Bits 0 to 7 Data SFR pointer DSFRP Bits 16 to 23 Note Data macro service pointer MPD Pies 818 Bits 0 to 7 Data buffer area Modulo register MR Ring counter RC Channel pointer Macro service control word Mode register Lower addresses Macro service buffer address macro service pointer Note Bits 20 to 23 must be set to 0 3 Examples of use of type C a Basic operation An example is shown below in which the output pattern to the real time output port and the output interval are directly controlled Update data is transferred from the two data storage areas set in the 1 MB space beforehand to the real time output function buffer register RTBL and the compare register CR10 User s Manual U12697EJ4V1UD 419 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 32 Stepper Motor Open Loop Control by Real Time Output Port Macro service control word macro service channel 1 MB memory space Internal RAM 123411H 09H TSFRP 52H Lower 8 bits Outpu
189. 2 0 V 10 0 5T 50 Delay time from WRT to Voo 5 0 V 10 0 5T 9 ASTBT Voo 3 0 V 310 0 5T 9 Voo 2 0 V 10 0 5T 30 WR low level width Voo 5 0 V 10 1 5 T 25 Vop 3 0 V 10 1 5 T 30 Vop 2 0 V 10 1 5 n T 30 Delay time from address tADEXD Voo 5 0 V 10 to EXAL Voo 3 0 V 10 Voo 2 0 V 10 Delay time from EXAL to Voo 5 0 V 10 ASTBI Voo 3 0 V 10 Voo 2 0 V 10 Delay time from RDT to texros 5 0 V 10 EXAT Von 3 0 V 10 Voo 2 0 V 10 Delay time from WRT to texwos Voo 5 0 V 10 EXAT Voo 3 0 V 10 Voo 2 0 V 10 Delay time from EXA to tEXADR Voo 5 0 V 10 ASTBT Von 3 0 V 10 Voo 2 0 V 10 Remark T tcvk 1 fxx fxx Main system clock frequency n Number of wait states n gt 0 User s Manual U12697EJ4V1UD 561 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 External wait timing 1 2 Parameter Input time from address to WAIT Conditions Voo 5 0 V 10 2 a T 40 Voo 3 0 V 10 2 60 Voo 2 0 V 10 2 a T 300 Input time from ASTBJ to WAIT Voo 5 0 V 10 1 5T 40 Voo 3 0 V 10 1 5T 60 Voo 2 0 V 10 1 5T 260 Hold time from ASTB to AIT Voo 5 0 V 10 0 5 n T4 5 Voo 3 0 V 10 0 5 n
190. 2 VP RP4 UP RP5 DE RP6 HL RP7 rg rg VVP RG4 UUP RG5 TDE RG6 WHL RG7 sfr Special function register symbol see the special function register table sfrp Special function register symbol 16 bit manipulation register see the special function register table postNote 2 AX RP0 BC RP1 RP2 RP3 VP RP4 UP RP5 PSW DE RP6 HL RP7 Multiple descriptions are possible However UP is restricted to the PUSH POP instruction and PSW is restricted to the PUSHU POPU instruction TDE WHL TDE WHL TDE WHL VVP UUP register indirect addressing TDE byte WHL byte SP byte UUP byte VVP byte based addressing imm24 A imm24 B imm24 DE imm24 HL indexed addressing TDE A TDE B TDE C WHL A WHL B WHL C VVP DE VVP HL based indexed addressing Everything under mem except WHL WHL TDE WHL AX BC RP2 RP3 VVP UUP TDE WHL Notes 1 By setting the RSS bit to 1 R4 to R7 can be used as X A C and B Use this function only when 78K III Series programs are also used 2 By setting the RSS bit to 1 RP2 and RP3 can be used as AX and BC Use this function only when 78K III Series programs are also used 520 User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION 1 Operand format and descriptions 2 2 Note saddr saddr FD20H to FF1FH Immediate data or label saddr1 FE00H to FEFFH Immediate data or la
191. 225Y SUBSERIES ONLY Modification of Figure 23 8 Read Modify Write Timing for External Memory in External Memory Expansion Mode CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 27 2 Flash Memory Overwriting Deletion of self overwrite mode 27 3 On Board Overwrite Mode Deletion of dedicated flash programmer Flashpro 11 Modification of Table 27 3 Communication Modes Modification of Figure 27 2 Format of Communication Mode Selection Modification of Table 27 4 Major Functions of On Board Overwrite Mode Deletion of batch erase batch blank check and batch verify Change of block to area Change of 78K IV SERIES LINEUP Modification of minimum instruction execution time 1 5 Function List CHAPTER 27 uPD78F4225 AND uPD78F4225Y PROGRAMMING CHAPTER 1 OVERVIEW Modification of Cautions in Figure 13 2 Format of A D Converter Mode Register ADM CHAPTER 13 A D CONVERTER Addition of Table 16 2 Serial Interface Operation Mode Settings CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 Addition of Table 17 2 Serial Interface Operation Mode Settings CHAPTER 17 3 WIRE SERIAL I O MODE Addition of reserved words in Figure 22 21 Format of Macro Service Control Word CHAPTER 22 INTERRUPT FUNCTIONS Modification of Table 23 3 Settings of Program Wait Control Register 2 PWC2 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Modification of Figure 24 1 Standby Function State Tran
192. 2697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 28 Timing of One Shot Pulse Output Operation by External Trigger with Rising Edge Specified Sets 08H to TMC0 TMO count starts Count clock Two count vase 0000 TIOO pin input INTTMO1 INTTM00 I TOO pin output y Cautions 1 16 bit timer counter 0 starts operating as soon as TMC02 and TMC03 are set to a value other than 0 0 operation stop mode 2 The software trigger bit 6 OSPT of 16 bit timer output control register 0 TOC0 1 and the external trigger TIOO input are always valid in one shot pulse output mode If the software trigger is used in one shot pulse output mode the TIOO pin cannot be used as a general purpose port pin Therefore fix the TIOO pin to either high level or low level User s Manual U12697EJAV1UD 175 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 Cautions 1 Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer is started This is because 16 bit timer counter 0 TM0 is started asynchronously to the count pulse Figure 8 29 Start Timing of 16 Bit Timer Counter 0 Count pulse wc oe count value 0000H Timer starts 2 16 bit compare register settings Set 16 bit capture compare registers 00 and 01 CR00 01 to a value other than
193. 3 to Table 22 2 Interrupt Request Sources Modification of Figure 22 33 Data Transfer Control Timing Modification of Figure 22 36 Automatic Addition Control Ring Control Block Diagram 1 When Output Timing Varies with 1 2 Phase Excitation Modification of Figure 22 37 Automatic Addition Control Ring Control Timing Diagram 1 When Output Timing Varies with 1 2 Phase Excitation Modification of Figure 22 38 Automatic Addition Control Ring Control Block Diagram 2 1 2 Phase Excitation Constant Velocity Operation Modification of Figure 22 39 Automatic Addition Control Ring Control Timing Diagram 2 1 2 Phase Excitation Constant Velocity Operation CHAPTER 22 INTERRUPT FUNCTIONS 23 2 Control Registers Modification of Figure 23 1 Format of Memory Expansion Mode Register MM Addition of 3 Programmable wait control register 2 PWC2 CHAPTER 23 LOCAL BUS INTERFACE FUNCTONS Modification of Figure 24 1 Standby Function State Transition Modification of Figure 24 4 Format of Oscillation Stabilization Time Specification Register OSTS Modification of Table 24 2 Operating States in HALT Mode Modification of Figure 24 5 Operations After Releasing HALT Mode Modification of caution in 24 4 1 Settings and operating states of STOP mode Modification of Table 24 5 Operating States in STOP Mode Modification of Figure 24 6 Operations After Releasing STOP Mode Modification of Table 24 7 Operating States in IDLE Mode Modification of
194. 4 0 6 5 3 2 1 oe o w o Tome oe Internal ROM fetch 0 Fetch at the same speed as from external memory All of the wait control settings are valid High speed fetch The wait control settings are invalid AW Address wait setting 0 An address wait is not inserted A one clock address wait is inserted at the address output timing Port 4 Port 5 P60 to P63 P40 to P47 P50 to P57 Single chip mode Port 256 KB ADO to AD7 A8 to 15 A16 Port expansion mode A17 1 MB A16 to A19 expansion mode Other than above Setting prohibited Note When the external wait function is not used the WAIT pin can be used as a port 438 User s Manual U12697EJ4V1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 2 Programmable wait control register 1 PWC1 PWC1 is an 8 bit register that sets the number of waits The insertion of wait cycles is controlled by PWC1 over the entire space PWC1 can be read and written by a 1 bit or 8 bit memory manipulation instruction RESET input sets PWC1 to AAH Figure 23 2 Format of Programmable Wait Control Register 1 PWC1 Address OFFC7H After reset AAH R W Symbol 7 6 5 4 3 2 1 0 Pwo Data access cycles Insertion wait cycles y fetch cycles Low level period that is input at the WAIT pin Remarks 1 The insertion of wait cycles is controlled by the entire address space exce
195. 4 4 kHz Cautions 1 If data different from that of PRM2 is written stop the timer beforehand 2 Be sure to set 0 to bits 3 to 7 of PRM2 3 When specifying the valid edge of TI2 for the count clock set the count clock to fxx 4 or below Remark Figures in parentheses apply to operation at fxx 12 5 MHz 188 User s Manual U12697EJ4V1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 4 Operation 9 4 1 Operation as interval timer 8 bit operation The timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the count preset in 8 bit compare registers 10 and 20 CR10 CR20 If the count in 8 bit timer counters 1 2 TM1 TM2 matches the value set in CR10 and CR20 the values of 1 and 2 are cleared to 0 and the count continues At the same time an interrupt request signal 1 INTTM2 is generated The TM1 and TM2 count clock can be selected with bits 0 to 2 TCLnO to TCLn2 of prescaler mode registers 1 and 2 PRM1 PRM2 Setting method 1 Set each register PRMn Selects the count clock e 0 Compare value TMCn Selects the clear and start mode when TMn and CRn0 match TMCn 0000xxx0B x Don t care 2 When TCEn 1 is set counting starts 3 When the values of TMn and CRnO match INTTMn is generated TMn is cleared to 00H 4 Then INTTMn is repeatedly generated at the same interval When counting stops set TCEn 0 Re
196. 464 465 Interrupt control register 367 Interrupt control register 367 Slave address register O 294 305 16 bit timer counter O 146 8 bit timer counter 1 182 8 bit timer counter 2 182 8 bit timer counter 5 202 8 bit timer counter 6 202 16 bit timer mode control register 0 149 150 155 157 8 bit timer mode control register 1 183 8 bit timer mode control register 2 183 8 bit timer mode control register 5 203 8 bit timer mode control register 6 203 204 Interrupt control register 367 Interrupt control register 367 User s Manual U12697EJ4V1UD 619 APPENDIX D REGISTER INDEX TMIC1 Interrupt control register 368 TMIC2 Interrupt control register 368 TMIC3 Interrupt control register 367 TMIC5 Interrupt control register 368 TMIC6 Interrupt control register 368 TOCO 16 bit timer output control register 0 152 153 TXS1 Transmission shift register 1 258 TXS2 Transmission shift register 2 258 W WDM Watchdog timer mode register 221 373 WDTIC Interrupt control register 366 WTIC Interrupt control register 368 WTM Watch timer mode control register 216 620 User s Manual U12697EJAV1UD Edition 2nd edition APPENDIX E REVISION HISTORY Contents Modification of power supply voltage range only for uwPD78F4225 78F4225Y Before change 1 8 to 5 5 V After change Voo 1 9 to 5 5 V Modifica
197. 48 28 2 16 Bit Addressing Instr ctloris oerte it tree te cerit E es 549 28 3 24 Bit Addressing R weenie 550 28 4 Bit Manipulation Instruction Addressing Instructions 2 550 28 5 Call Return Instructions and Branch Instruction Addressing Instructions 551 31 1 Soldering Conditions for Surface Mount eeeeecceeneeeeeeeeeeeeeeeeeeeeseaeeseeeeeaeeseeeeeeesneeesieeteeeeeees 596 30 User s Manual U12697EJAV1UD CHAPTER 1 OVERVIEW The uPD784225 Subseries is a member of the 78K IV Series and is an 80 pin general purpose microcontroller in which the functions of the uPD784216 Subseries have been limited and to which a ROM correction function has been added The 78K IV Series includes 8 16 bit single chip microcontrollers and provides a high performance CPU with functions such as 1 MB memory space access The uPD784225 has a 128 KB ROM and 4 352 byte RAM on chip In addition it has a high performance timer counter an 8 bit A D converter an 8 bit D A converter and an independent 2 channel serial interface The uPD784224 is the uPD784225 with 96 KB mask ROM and a 3 584 byte RAM The uPD78F4225 is the uPD784225 with the mask ROM replaced by a flash memory The uPD784225Y Subseries is the wPD784225 Subseries with an added I C bus control function The relationships among the
198. 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V External X1 input 4 5 V lt Voo lt 5 5 V clock frequency fx 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V uPD74HCUO4 1 8 V lt Voo lt 2 0 V 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Vpp lt 2 7 V MYNINI NINI AJAJ AJTIAI NI INI NINJ AJAJAJA 1 8 V lt Voo lt 2 0 V 1 input high low level width twxHr twxL X1 input rising falling 4 5 V lt Voo lt 5 5 V time txr txF 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V Cautions 1 When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as Vss e Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator 2 When the main system clock is stopped and the device is operating on the subsystem clock wait until the oscillation stabilization time ha
199. 5GC 8BT 80 pin plastic QFP 14 x 14 uPD78F4225YGC 8BT 80 plastic QFP 14 x 14 Soldering Method Soldering Conditions Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Two times or less Exposure limit 7 daysNete after that prebake at 125 C for 10 hours Recommended Condition Symbol IR35 107 2 Package peak temperature 215 C Time 40 seconds max at 200 C or higher Count Two times or less Exposure limit 7 daysNete after that prebake at 125 C for 10 hours VP15 107 2 Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once Preheating temperature 120 C max package surface temperature Exposure limit 7 daysNete after that prepake at 125 C for 10 hours WS60 107 1 Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating User s Manual U12697EJ4V1UD 597 CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS Table 31 1 Soldering Conditions for Surface Mount Type 3 3 4 uPD784224GC xxx 8BT A 80 pin plastic 14 x 14 uPD784225GK xxx 9EU A 80 pin plastic TQFP fine pitch 12 x 12 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or IR60 203 3 higher Count Three times or less Ex
200. 784225 Match with address pointer 0 table 0078H Conversion command code FCH Match with address pointer 1 X CALLT table 007AH Conversion command code FDH Match with address pointer 2 CALLT table 007CH Conversion command code FEH Match with address pointer 3 CALLT table 007EH Conversion command code FFH Caution As it is necessary to reserve four locations for the CALLT tables when the ROM correction function is used 0078H 007AH 007CH 007EH ensure that these are not used for other applications However the CALLT tables can be used if the ROM correction function is not being used The differences between 78K IV ROM correction and 78K 0 ROM correction are shown in Table 26 1 506 User s Manual U12697EJAV1UD CHAPTER 26 ROM CORRECTION Table 26 1 Differences Between 78K IV ROM Correction and 78K 0 ROM Correction Difference Generated command codes 78K IV CALLT instruction 1 byte instruction FCH FDH FEH FFH Branch instruction for peripheral RAM 3 byte instruction Change of stack pointer Yes 3 byte save None Address comparison conditions Instruction fetch only Instruction fetch only Correction status flag None As there is a possibility that the addresses match owing to an invalid fetch the status is not necessary Yes Jump destination address during correction CALLT table 0078H 007AH 007CH 007EH User s Manual U12697EJ4V1UD
201. 8 bit timer event counter 1 Internal bus TM2 compare match TH O Edge detector 8 bit compare Selector INTTM1 hola register 10 CR10 5 1 fxx 28 5 Dx 5 y Match x o G fo 25 3 it fxx 27 8 bit timer fxx 29 counter 1 TM1 to TM2 Clear NTTM2 O TO1 controller Teer more o Toss Ten roe Prescaler mode 8 bit timer mode register 1 PRM1 control register 1 TMC1 Internal bus User s Manual U12697EJAV1UD 181 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 182 Figure 9 1 Block Diagram of 8 Bit Timer Event Counters 1 and 2 2 2 2 8 bit timer event counter 2 Internal bus TI20 Edge detector 8 bit compare INTTM1 register 20 CR20 i o fxx 23 o di 2 8 fxx 28 2 fxx 27 8 bit timer fxx 29 counter 2 TM2 to TM2 TM1 overflow Output controller o TO2 8 bit timer mode control register 2 TMC2 E TCL22 TCL21 TCL20 Prescaler mode register 2 PRM2 Internal bus User s Manual U12697EJ4V1UD CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 1 8 bit timer counters 1 and 2 TM1 TM2 2 1 and 2 are 8 bit read only registers that count the count pulses The counter is incremented in synchronization with the rising edge of the count clock When the count is read out during operation the co
202. 8H Internal bus Edge INTP4 detection Macro service request Port 3 Remark Macro service channel addresses in the figure are the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed OF0000H should be added to the values in the figure 412 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 29 Parallel Data Input Timing Port 3 INTP4 A Data fetch macro service User s Manual U12697EJ4V1UD 413 CHAPTER 22 INTERRUPT FUNCTIONS 22 8 8 Macro service type C 1 414 Operation For the type C macro service data in the memory specified by the macro service channel is transferred to two SFRs fortimer use and data use specified by the macro service channelin response to a single interrupt request the SFRs can be freely selected An 8 bit or 16 bit timer SFR can be selected In addition to the basic data transfers described above the following functions can be added to the type C macro service to reduce the size of the buffer area and alleviate the burden on software These specifications are made by using the mode register of the macro service control word a Updating of timer macro service pointer It is possible to choose whether the timer macro service pointer MPT is to be kept as it is or incremented decremented MPT is incremented or decremented in the same direction as the macro service pointer
203. 97EJAV1UD 357 CHAPTER 21 EDGE DETECTION FUNCTION 21 2 Edge Detection of P00 to P05 Pins The P00 to P05 pins do not incorporate an analog delay based noise eliminator Therefore a valid edge is input to the pins and edge detection is performed acknowledged immediately after passing through the hysteresis type input buffer Figure 21 2 Block Diagram of P00 to P05 Pins P00 to P05 input mode in input mode INTP0 INTP1 INTP2 NMI P00 to P05 Edge detector INTP3 to INTP5 to interrupt controller P00 to P05 output mode in output mode 358 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS The uPD784225 is provided with three interrupt request service modes refer to Table 22 1 These three service modes can be set as required in the program However interrupt servicing by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in Table 22 2 Context switching cannot be selected for non maskable interrupts or operand error interrupts Multiple interrupt control using 4 priority levels can easily be performed for maskable vectored interrupts Interrupt Request Service Mode Vectored interrupts Context switching Table 22 1 Interrupt Request Service Modes Servicing Performed Software PC amp PSW Contents Saving to amp restoring from stack Service Executed by branching to service program at addressN te specified by vecto
204. 9H OFE38H OFE33H OFE32H OFE31H OFE30H OFE2FH OFE2EH OFE2DH OFE2CH OFE2BH OFE2AH OFE29H OFE28H OFE27H OFE26H OFE25H OFE24H OFE23H OFE22H OFE21H OFE20H OFE1FH OFE1EH OFE1DH OFE1CH OFE1BH OFE1AH OFE19H OFE18H OFE17H OFE16H OFE13H OFE12H OFE11H OFE10H OFEOFH OFEOEH OFEODH OFEOCH OFEOBH OFEOAH 9 OFE08H 0 OFEO6H Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Channel pointer Mode register Note uPD784225Y Subseries only User s Manual U12697EJ4V1UD Source INTWT INTTM6 5 INTAD INTTM2 INTTM1 INTTMO1 INTTMOO INTTM3 INTST2 INTSR2 INTCSI2 INTSER2 INTST1 INTSR1 I
205. A D Converter Mode Register ADM Addition of 13 5 Reading the A D Converter Characteristics Table Modification of description in 13 6 Cautions CHAPTER 13 A D CONVERTER Modification of Figure 16 2 Block Diagram in Asynchronous Serial Interface Mode Modification of Table 16 3 Relationship Between 5 Bit Counter Source Clock and m Value Modification of Table 16 4 Relationship Between Main System Clock and Baud Rate Modification of Figure 16 11 Block Diagram 3 Wire Serial I O Mode User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL y o APPENDIX E REVISION HISTORY Edition 2nd edition Contents Modification of Figure 17 1 Block Diagram of Clocked Serial Interface in 3 Wire Serial I O Mode 3 4 Applied to CHAPTER 17 3 WIRE SERIAL MODE Modification of Figure 18 3 Format of 2 Bus Control Register IICCO Addition of note about bit TRCO to Figure 18 4 Format of I C Bus Status Register IICSO Modification of Figure 18 5 Format of Prescaler Mode Register SPRMO for Serial Clock Modification of description about interrupt request timing of master operation and slave operation in 18 5 7 I C interrupt request INTIICO Modification of value in Table 18 5 Wait Times CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Modification of Figure 21 2 Block Diagram of P00 to P05 CHAPTER 21 EDGE DETECTION FUNCTION Addition of remark
206. A LAE IE N er er eee ee Pere 5 28 POM Z aaa 5 2 92 le nee ne UD LE UIS 5 210 Pot Bisco teeta ss tu LS 5 3 Gontrol Redisters u u u i Pe Su usa sa sasa E cu Witing OVOP EE 5 4 2 Reading from VO Dert y eine Ae eR ERA UR 543 u a ak enden deeds aqa nere seran Ra estates CHAPTER 6 REAL TIM OUTPUT FUNCOM k uu l PME DnuMIIcubnpE 6 3 Corntrol Hegislers oodd uiu S 6 4 Operation asua im Pasce crassi aet iudex aaa aeaa auai 6 5 Usage of Real Time Output Function u U u u u u nnn nnn 6 6 er DIDI tape a ua SS Gaius assis Qusa ee asua CHAPTER 7 TIMER u u a CHAPTER 8 16 BIT TIMER EVENT COUNTFER u nennen nnn nnne nnn nn nnn NE 8 2 esnipcubpme 8 3 Control Registers rece iiio e ciu m
207. ALT Mode by Maskable Interrupt Request MKNote 1 ENote 2 State During Release Not executing an interrupt service program Executing a low priority maskable interrupt service program The PRSL bitNote 4 js cleared to 0 while executing an interrupt service program at priority level 3 Operation After Release Acknowledges interrupt requests Executing a maskable interrupt service program with the same priority This excludes executing an interrupt service program in priority level 3 when the PRSL bitNete 4 is cleared to 0 Executing a high priority interrupt service program The instruction following the MOV STBC byte instruction is executed The interrupt request that released the HALT mode is held pendingNete 3 Holds the HALT mode Macro service request Notes 1 Macro service processing execution End condition is not satisfied End HALT mode condition is satisfied again When VCIENote 5 1 HALT mode again When VCIENete 5 o Same as a release by a maskable interrupt request Interrupt mask bit in each interrupt request source 2 Interrupt enable flag in the program status word PSW m gt request source 3 Releasing HALT mode by RESET input After branching to the reset vector address as in anormal reset the program is executed However the contents Holds the HALT mode The pending interrupt request is acknowledged when acknowledgement is possible Bit
208. AV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 16 Communication operation 1 Master operation The following example shows the master operation procedure Figure 18 18 Master Operation Procedure START IICCLO lt xxH Select the transfer clock IICC0 xxH IICE0 SPIEO WTIMO 1 STTO 1 No Start write transfer No Yes No Yes No reception Stop condition generation No slave with address match Yes transmission Start write transfer Data processing Yes ol Generate restart condition or stop condition WTIMO 0 ACKE0 1 Stop condition detection Address transfer ends WRELO 1 Start reception Data processing Transfer ends User s Manual U12697EJ4V1UD 341 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 2 Slave operation The following example is the slave operating procedure Figure 18 19 Slave Operating Procedure lt xxH IICEO 1 Participate communication LRELO 1 WTIMO 0 ACKEO 1 WTIMO 1 Start write transfer Data processing WRELO 1 Start reception Yes Data processing Yes Transfer ends Detect restart condition or stop condition 342 User s Manual U12697EJAV1UD CHAPTER 18
209. After 473 24 4 Releasing HALT Mode by Maskable Interrupt 479 24 5 Operating States in STOP Mode 0101 481 24 6 Releasing STOP Mode and Operation After Release seen 482 24 7 Operating States IDLE Mode U 489 24 8 Releasing IDLE Mode and Operation After Release u 490 24 9 Operating States in HALT 500 24 10 Operating States in IDEE Mode u rette retis aei kanaa uk a 502 25 1 State of Hardware During and After Reset 244 4 4 10 00 505 26 1 Differences Between 78K IV ROM Correction and 78K 0 ROM Correction 507 User s Manual U12697EJAV1UD 29 LIST OF TABLES 3 3 Table No Title Page 26 2 ROM Gorrection GomfiQuration a uote her Eadem eee a teen PESE ERR ER Ru 508 27 1 Differences Between uPD78F4225 78F4225Y and Mask ROM Versions 513 27 2 Internal Memory Size Switching Register IMS 514 27 3 Comm nication MODES 516 27 4 Major Functions of On Board Overwrite 517 28 1 8 Brt Addressing Instr ctloris u 5
210. B output N RD output NE b Setting 1 wait cycle PW01 PW00 0 1 uma ADO to AD7 HEE Hz Baa Hi Z ASTB output 2656 RD output mS GM mm Note fxx Main system clock frequency This signal is only in the uPD784225 454 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 10 Read Timing by Access Wait Function 2 2 c Setting 2 wait cycles PW01 PW00 1 0 ADO to em dg Data input a ASTB output JA eee RD output Note fo Main system clock frequency This signal is only in the wPD784225 User s Manual U12697EJ4V1UD 455 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 11 Write Timing by Access Wait Function 1 2 a Setting 0 wait cycles PW01 PW00 0 0 ADO AD7 _Hi Z HR PAO output address ASTB output N WR output N b Setting 1 wait cycle PW01 PW00 0 1 ASTB output A WR output Nf Note fxx Main system clock frequency This signal is only in the uPD784225 456 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 11 Write Timing by Access Wait Function 2 2 c Setting 2 wait cycles PW01 PW00 1 0 fy Note Gb Vs X XR ADO to AD7 Hi Z Lower Hi Z Hi Z output 7 Ec MM ipd C ASTB output 7 WR output N Note f Main system clock frequency This signal is only in the uPD784225 User s Manu
211. C bus status register 0 IICSO STTO Bit 1 in I C bus control register 0 IICCO 334 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 14 Example of Arbitration Timing Master 1 Hi Z SDAO 3 d ypP dp o ASsbo N PR N S Aa Master 1 arbitration Master 2 failed SCL0 SDA0 Transfer lines SDA0 Table 18 4 Arbitration Generation States and Interrupt Request Generation Timing Arbitration Generation State Interrupt Request Generation Timing During address transmission Falling edge of clock 8 or 9 after byte transferNote 1 Read write information after address transmission During extended code transmission Read write information after extended code transmission During data transmission During ACK transfer period after data transmission Restart condition detection during data transfer Stop condition detection during data transfer When stop condition is output SPIEO 1 Nete 2 Data is low when the restart condition is about to be Falling edge of clock 8 or 9 after byte transferNote 1 output The restart condition should be output but the stop Stop condition is output SPIEO 1 Note 2 condition is detected Data is low when the stop condition is about to be output Falling edge of clock 8 or 9 after byte transferNote 1 SCLO is low when the restart condition is about to be output N
212. CMPBKC CMPBKNC SACW 22 11 Interrupt and Macro Service Operation Timing Interrupt requests are generated by hardware The generated interrupt request sets 1 an interrupt request flag When the interrupt request flag is set 1 it takes of 8 clocks 0 64 us fxx 12 5 MHz to determine the priority etc Following this if acknowledgment of that interrupt or macro service is enabled interrupt request acknowledgment processing is performed when the instruction being executed ends If the instruction being executed is one which temporarily holds interrupts and macro servicing pending the interrupt request is acknowledged after the following instruction refer to 22 9 When Interrupt Requests and Macro Service Are Temporarily Held Pending for these instructions Figure 22 43 Interrupt Request Generation and Acknowledgment Unit Clock 1 fcLk Interrupt request flag 8 clocks pV Instruction Interrupt request acknowledgment processing macro service processing User s Manual U12697EJ4V1UD 431 CHAPTER 22 INTERRUPT FUNCTIONS 22 11 1 Interrupt acknowledge processing time The time shown in Table 22 7 is required to acknowledge an interrupt request After the time shown in this table has elapsed execution of the interrupt processing program is started Table 22 7 Interrupt Acknowledge Processing Time Unit Clock 1 Vector Table Branch IROM PRAM destination Stack IRAM PRAM EMEM Vectored 26 29
213. CO CRC02 CRC01 CRC00 o o o o or CR00 used as compare register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the external event counter function For details refer to Figures 8 2 and 8 3 Figure 8 21 Configuration of External Event Counter 16 bit capture compare register CROO gt INTTM00 Valid edge of TIOO 16 bit timer counter 0 TMO 16 bit capture compare register 01 CRO1 Internal bus User s Manual U12697EJAV1UD 167 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 22 Timing of External Event Counter Operation with Rising Edge Specified f LI LI LJ LI LILI LILI LILILI LI Tmo countvate focos once ones XN X N CR00 N INTTMOO D A OPT Caution Read TM0 when reading the count value of the external event counter 8 4 5 Operation to output square wave The 16 bit timer event counter outputs a square wave of any frequency at the interval specified by the count value preset to 16 bit capture compare register 00 CROO By setting bits 0 TOEO and 1 TOCO1 of 16 bit timer output control register 0 to 1 the output status of the TOO P30 pin is inverted at the interval specified by the count value preset to CROO In this way a square wave of any frequency can be output 168 User s Manual U12697EJAV1UD CHAP
214. Caution When INTP2is specified as an output trigger specify the valid edge using external interrupt rising edge enable register 0 EGPO and external interrupt falling edge enable register 0 EGNO Table 6 3 Operation Modes and Output Triggers of Real Time Output Port BYTE EXTR Operation Mode RTBH Port Output RTBL Port Output 4 bits x 2 channels INTTM2 INTTM1 INTTM1 INTP2 8 bits x 1 channel INTTM1 INTP2 User s Manual U12697EJAV1UD 139 CHAPTER 6 REAL TIME OUTPUT FUNCTION 6 4 Operation When real time output is enabled by bit 7 RTPOE 1 in the real time output port control register data in the real time output buffer register RTBH RTBL is transferred to the output latch synchronized with the generation of the selected transfer trigger set by EXTR and BYTENote Based on the setting of the real time output port mode register RTPM only the transferred data for the bits specified in the real time output port are output from bits to RTP7 A port pin set in the port mode by RTPM can be used as general purpose port pin When the real time output operation is disabled by RTPOE 0 RTPO to RTP7 output 0 regardless of the RTPM setting Note EXTR Bit 4 of the real time output port control register RTPC BYTE Bit 5 of the real time output port control register RTPC Figure 6 5 Example of Operation Timing of Real Time Output Port EXTR 0 BYTE 0 INTTM2 INTTM1 n
215. Control Register Settings When Timer 0 Operates as Interval Timer a 16 bit timer mode control register 0 TMC0 TMC03 TMC02 TMC01 OVF0 fe o o one Clears and starts on match between TMO and CROO b Capture compare control register 0 CRCO CRC02 CRC01 00 o o o o om o CR00 as compare register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the interval timer function For details refer to Figures 8 2 and 8 3 User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 7 Configuration of Interval Timer 16 bit capture compare register 00 CR00 fxx 4 INTTM00 fxx 16 Selector INTTM3 00 35 Clear circuit Figure 8 8 Timing of Interval Timer Operation count value 0000 0005 X N 0001 EBD 0001X CU XX A iC Count starts Cer Ciear INTTM00 l 1 snos acknowledgement enn acknowledgement Interval time Interval time Interval time Remark Interval time N 1 x t N 0001H to FFFFH User s Manual U12697EJ4V1UD 157 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 4 2 PPG output operation The 16 bittimer event counter can be used for PPG Programmable Pulse Generator output by setting 16 bit timer mode control register 0 TMCO and capture compare control register 0 CRCO as shown in Figure 8 9 The PPG ou
216. Count clock TM N oH m N FFH ooH 1 CRn0 M I TCEn I H I I 1 1 l l 1 INTTMn 4 CRn0 transition TMn overflows since M lt N e Operated by CRn0 transition M gt N Countcock_ LE U U LI LIL LIL LU LU l TMn N 1 N oH n 1 l CRn0 I TCEn H l l INTTMn i CRn0 transition Remark n 5 6 User s Manual U12697EJAV1UD 211 CHAPTER 10 8 BIT TIMERS 5 6 Figure 10 7 Timing of Operation Based on CRn0 Transitions a When the CRn0 value changes from N to M before TMn overflows B ina ats E O TESIISSTERTERT 7 C O TCEn eu m mM INTTMn 2 21 MD CRn0 transition N b When the CRn0 value changes from N to M after TMn overflows e JUL ULL LULL LL alak A OE mT 77 1M RE CRn0 _ ie INTTMn 5 l 21 E SEE NE QN 0 transition N M c When the CRn0 value changes from N to M within two clocks 00H 01H immediately after TMn overflows ee Bes EET SRO TCT 27 TW WR CRnO a E EE 3 3 37 INTTMn 22 l 22 S CEN CRn0 transition N M Remark n 5 6 212 User s Manual U12697EJAV1UD CHAPTER 10 8 BIT TIMERS 5 6 10 4 2 O
217. D conversion operation is immediately stopped Figure 13 7 A D Conversion Operation by Software Start ADM setting ADCS 1 TRG 0 ADIS write ADCS 0 A D conversion ANIn ANIn ANIm ANIm M Conversion operation V interrupted and Stop r conversion result not left ove INTAD Note f bit 0 ADCE of the A D converter mode register is not set to 1 the value of the first A D conversion is undefined immediately after A D conversion starts Poll the A D conversion end interrupt request INTAD and discard the first A D conversion result User s Manual U12697EJAV1UD 237 CHAPTER 13 A D CONVERTER 13 5 Reading A D Converter Characteristics Table Words used specifically for the A D converter are defined below 1 Resolution The lowest identifiable analog input voltage or the ratio of the analog input voltage to one bit of a digital output is known as 1LSB least significant bit The ratio to the full scale of 1LSB is expressed as FSR full scale range In the case of 8 bit resolution 1LSB 1 28 1 256 0 4 FSR5 The accuracy is unrelated to the resolution and is determined by the overall error 2 Overall error This indicates the maximum difference between the actual and theoretical measurement values Zero scale error full scale error integral linearity error differential linearity error and combinations of these errors are expressed as the overall error Note that the quantization
218. DE A TDE A CMPMNE TDE TDE TDE lt TDE 1 C C 1 End if C 0o0rZ 0 A TDE 1 C lt C 1 Endif C 20o0rZ 1 TDE A TDE TDE lt TDE 1 C lt C 1 Endif C 200rZ 1 A TDEE 1 C C 1 End if C 0 or CY 0 A TDE TDE 1 C C 1 End if C 200r CY 0 TDE TDE 1 C lt C 1 End if C 200r CY 1 A TDE TDE 1 C C 1 End if C 20 or CY 1 TDE WHL TDE TDE 1 WHL WHL 1 C C 1 End if C 0 or Z 0 TDE A TDE A CMPMNC TDE A TDE A CMPBKE TDE WHL N N N N S N N N N lt lt lt lt lt ib lt TDE WHL TDE WHL TDE TDE 1 WHL WHL 1 C C 1 End if C 0 or Z 0 CMPBKNE TDE WHL TDE WHL lt 1 WHL WHL 1 C 1 End if C 200r Z 1 TDE WHL TDE WHL TDE TDE 1 WHL WHL 1 C e C 4 End if C 20 orZ 1 CMPBKC TDE WHL TDE WHL lt 1 WHL WHL 1 C C 1 End if C 0 or CY 0 TDE WHL TDE WHL TDE TDE 1 WHL WHL 1 C C 4 End if C 0 or CY 0 CMPBKNC TDE WHL TDE WHL lt 1 WHL WHL 1 C C 1 End if C 0 or CY 1 TDE WHL TDE WHL TDE TDE 1 WHL
219. E BP BN BLT BGE BLE BGT BNH BH BF BT BTCLR BFSET DBNZ Table 28 5 Call Return Instructions and Branch Instruction Addressing Instructions Instruction Address Operand addr20 addr20 addr16 addr20 Basic instructions CALL BR RETCS RETCSB laddr11 addr5 Composite instructions Note BNZ BNE BZ BE BNC BNL BL BNV BPO BV BPE BP BN BLT BGE BLE BGT BNH and BH are identical to BC 6 Other instructions ADJBA ADJBS CVTBW LOCATION SEL NOT El DI SWRS User s Manual U12697EJ4V1UD 551 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29 1 Electrical Specifications of u PD784224 784225 784224 and 784225Y For the timing charts refer to 29 3 Timing Charts Absolute Maximum Ratings Ta 25 C Parameter Conditions Ratings Supply voltage Vop Voo 0 3 to 6 5 AVpp 0 3 to 0 3 AVss 0 3 to Vsso 0 3 1 D A converter reference voltage input 0 3 to 0 3 Input voltage Vi 0 3 to 0 3 Analog input voltage Analog input pin AVss 0 3 to AVner 0 3 Output voltage 0 3 to Voo 0 3 Output current low Per pin 15 Total of all pins 100 Output current high Per pin 10 Total of all pins 40 Operating ambient 40 to 85 temperature Storage temperature 65 to 150 Caution Product quality may suffer if th
220. ES uPD784216A SUBSERIES AND 4PD780058A SUBSERIES 599 APPENDIX B DEVELOPMENT TOOLS netten cete ne esce unen 600 B 1 Language Processing Software eese u u u u T 603 B 2 Flash Memory Writing 15 ener nennen nennen uu u u nnne innen nnn 604 B 3 Debugging Tools cocer ctedceecessseseceeeseusieadecceetetdcs sr aae DEus a Dome ui dieiis ea 605 18 User s Manual U12697EJAV1UD B 3 1 HardWalfe u E I EEM 605 B 3 2 SONWALE 607 B 4 Cautions on Designing Target System l l u uu u 608 B 5 Conversion Socket EV 9200GC 80 and Conversion Adapter TGK 080SDW 610 APPENDIX EMBEDDED SOFTWARE U 613 APPENDIX D REGISTER 2 22 2 21 2 ur eL en creato ccu asiaani adan 614 D 1 Register Index J U U u u U u uu u J Q J J 614 D 2 Register Index Alphabetical Order J l l u 617 APPENDIX E REVISION HISTORY cscccccceiccssceccctecccsccecessetessecteeennedc
221. ET input gt Normal reset operations 474 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Figure 24 5 Operations After Releasing HALT Mode 2 4 3 HALT mode during interrupt servicing routine whose priority is higher than or equal to release source interrupt Main routine MOV STBO byte HALT mode INT e HALT mode release HALT mode release source interrupt pending Y Execution of the pending interrupt 4 HALT mode during interrupt servicing routine whose priority is lower than release source interrupt Main routine MOV STBC byte HALT mode INT HALT mode release Execution of the HALT mode release source s interruption User s Manual U12697EJAV1UD 475 CHAPTER 24 STANDBY FUNCTION Figure 24 5 Operations After Releasing HALT Mode 3 4 5 Macro service request in HALT mode a Interrupt request is issued VCIE 0 immediately after macro service end condition is satisfied Main routine MOV STBC byte HALT mode Last macro service request gt Macro service processing HALT mode release Servicing of interrupt request due to end of macro service b Macro service end condition is not satisfied or interrupt request is not issued VCIE z 1 after macro service end condition is satisfied Main routine MOV STBC byte HALT mode Last macro service request gt Macro service proces
222. ET input sets CSIM1 and CSIM2 to OOH Figure 16 13 Format of Serial Operation Mode Registers 1 and 2 CSIM1 CSIM2 Address OFF91H OFF92H After reset 00H R W Symbol 6 5 4 3 2 1 0 SIOn operation enable disable setting Shift register operation Serial counter Operation disabled Clear Port functionNote Operation enabled Counter operation Serial function port enabled function Note When CSIEn 0 SlOn operation stop status pins connected to SOn and SCKn can be used as ports Remark 1 2 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 2 3 wire serial I O mode The 3 wire serial I O mode is effective when connecting peripheral I O or a display controller with an on chip clocked serial interface This mode is used to perform communication with the serial clock SCK1 SCK2 serial output SO1 SO2 and serial input SI1 SI2 lines a Register setting The 3 wire serial I O mode is set by serial operation mode registers 1 and 2 CSIM1 CSIM2 CSIM1 and CSIM2 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 and CSIM2 to 00H Figure 16 14 Format of Serial Operation Mode Registers 1 and 2 CSIM1 CSIM2 Address OFF91H OFF92H After reset 00H R W Symbol Gg 6 5 4 3 2 1 0 csmn csn o o o o woven scum 5 SIOn operation enable disable setting Shift register operation Serial counter O
223. FH FFFEOH FFFCFH SFR Internal RAM Internal RAM Internal RAM FF100H External memoryNete 1 External memory 17FFFH Internal ROM Internal ROM Internal ROM 00000H Single chip mode 256 KB expansion mode 1 MB expansion mode Notes 1 Area having any expanded size in the unshaded parts 2 External SFR area 442 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 4 0784225 Memory 1 2 a When executing the LOCATION OH instruction FFFFFH External memoryNote 1 External memory 1FFFFH 10000H OFFEOH Note 2 External memory OFFCFH SFR Internal RAM Internal RAM Internal RAM Internal ROM Internal ROM Internal ROM 00000H Single chip mode 256 KB expansion mode 1 MB expansion mode Notes 1 Area having any expanded size in the unshaded parts 2 External SFR area User s Manual U12697EJ4V1UD 443 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 4 0784225 Memory 2 2 b When executing the LOCATION OFH instruction FFFFFH FFFEOH FFFCFH SFR Internal RAM Internal RAM OEEO0H External memoryNot 1 External memory 1FFFFH Internal ROM Internal ROM Internal ROM 00000H Single chip mode 256 KB expansion mode 1 MB expansion mode Notes 1 Area having any expanded size in the unshaded parts 2 External SFR area 444 User s Manual U12697EJAV1UD CHAPTER 23 L
224. Figure 24 9 Operations After Releasing IDLE Mode Modification of description in iii Releasing the HALT mode by RESET input Modification of description in iii Releasing the IDLE mode by RESET input CHAPTER 24 STANDBY FUNCTION Modification of Figure 25 2 Receiving Reset Signal CHAPTER 25 RESET FUNCTION Modification of Table 26 1 Differences Between 78K IV ROM Correction and 78K 0 ROM Correction Modification of example of four pointer settings in 26 5 Conditions for Executing ROM Correction CHAPTER 26 ROM CORREC TION Modification of Figure 27 1 Format of Internal Memory Size Switching Register IMS Addition of dedicated flash programmer Flashpro 111 User s Manual U12697EJ4V1UD CHAPTER 27 uPD78F4225 AND uPD78F4225Y PROGRAMMING 623 APPENDIX E REVISION HISTORY Edition 2nd edition 3rd edition Contents Modified throughout 4 4 Applied to APPENDIX B DEVELOPMENT TOOLS Modified throughout The following products have been developed e uPD78F4225GC 8BT 78F4225GK 9EU 78F4225YGC 8BT 78F4225YGK 9EU APPENDIX C EMBEDDED SOFTWARE Throughout Addition of Caution related to operation in one shot pulse output mode CHAPTER 8 16 BIT TIMER EVENT COUNTER Change of watch timer interrupt interval from 0 5 second to 214 fw or 25 fw CHAPTER 11 WATCH TIMER Modification of Figure 18 17 Communication Reservation Procedure CHAPTER 18 BUS MODE uPD784
225. Fixed address on peripheral RAM 507 CHAPTER 26 ROM CORRECTION 26 2 ROM Correction Configuration ROM correction includes the following hardware Table 26 2 ROM Correction Configuration Register ROM correction address register H L CORAH CORAL Control register ROM correction control register CORC A ROM correction block diagram is shown in Figure 26 1 and Figure 26 2 shows an example of memory mapping Figure 26 1 ROM Correction Block Diagram Instruction fetch address Match ld Correction branch Comparator process request signal CALLT command Correction address pointer n ROM correction address register CORAH CORAL ROM correction control register CORC Remark n 0to3 m 0O 1 508 User s Manual U12697EJ4V1UD CHAPTER 26 ROM CORRECTION Figure 26 2 Memory Mapping Example uPD784225 01FFFFH Internal ROM OOFEFFH OOFFFFH a Internal high speed RAM 00FD00H oe OOFCFFH OOFEFFH Internal RAM Peripheral RAM 00 0 correction program OOEDFFH OOEEOOH 00007FH Reference table 3 Reference table 2 Reference table 1 Reference table 0 Internal ROM CALLT Table area 000040H 00003FH Vector table area 000000H 000000H 1 ROM correction address register CORAH CORAL This register sets the header address correction address of the command in the mask ROM that needs to be repaired A m
226. H instruction is executed Internal memory The internal data area and internal ROM area are as follows Part Number Internal Data Area Internal ROM Area uPD784224 OF100H to OFFFFH 00000H to OFOFFH 10000H to 17FFFH uPD784225 OEEOOH to OFFFFH 00000H to OEDFFH 10000H to 1FFFFH Caution The following area which is overlapped with the internal data area in the on chip ROM cannot be used when the LOCATION OH instruction is executed Part Number Use Prohibited Area uPD784224 OF100H to OFFFFH 3 840 bytes uPD784225 OEEOOH to OFFFFH 4 608 bytes External memory External memory is accessed in the external memory expansion mode 2 When the LOCATION OFH instruction is executed nternal memory The internal data area and internal ROM area are as follows Part Number Internal Data Area Internal ROM Area LPD784224 FF100H to FFFFFH 00000H to 17FFFH uPD784225 to FFFFFH 00000H to 1FFFFH External memory External memory is accessed in the external memory expansion mode 58 User s Manual U12697EJAV1UD GNLAPPaZ692LN IenueN sasn 6S Notes 1 Figure 3 1 uPD784224 Memory On execution of On execution of LOCATION OH instruction LOCATION OFH instruction FFFFFH Special function registers SFR FFFDFH FFFDOH FFFFFH neral pur Internal RAM External memory 1 General purpose 928 KB registers 128 bytes 3 584 bytes 18000H 17FFFH Internal ROM
227. H instruction is executed or OFFEOOH to OFFEFFH when the LOCATION OFH instruction is executed The macro service channel is indicated by the channel pointer as shown in Figure 22 27 In the channel pointer the lower 8 bits of the address are written to the macro service counter in the macro service channel i Higher addresses Macro service channel Macro service control word Lower addresses Figure 22 27 Type B Macro Service Channel Bits 8 to 15 Macro service counter MSC Bits 0 to 7 SFR pointer SFRP Bits 16 to 23 Note Macro service pointer MP Bits 0 to 7 Channel pointer Mode register Macro service buffer address macro service pointer Note Bits 20 to 23 must be set to 0 User s Manual U12697EJ4V1UD SFR Buffer area 411 CHAPTER 22 INTERRUPT FUNCTIONS 3 Example of use of type B An example is shown below in which parallel data is input from port 3 in synchronization with an external signal The INTP4 external interrupt pin is used for synchronization with the external signal Figure 22 28 Parallel Data Input Synchronized with External Interrupts Macro service control word macro service channel Internal RAM 64K memory space 0A01FH Buffer area 0 Channel pointer 6EH Type B SFR memory 8 bit transfer interrupt request generation when MSC 0 Mode register 1
228. H to 0FF27H 0FF2CH 0FF2DH After reset FFH Symbol PM0 PM2 PM3 PM4 PM5 PM6 PM7 PM12 PM13 27 PM37 PM47 PM57 PM67 PM127 R W 5 4 3 2 1 0 PM25 PM24 PM23 PM22 PM21 PM20 PM35 PM34 PM33 PM32 PM31 PM30 PM55 PM54 PM53 PM52 PM51 PM50 1 1 1 PM72 PM71 PM70 PM125 PM124 PM123 PM122 PM121 PM120 1 1 1 1 PM131 PM130 Figure 5 20 Format of Port Mode Register 6 PM26 PM36 PM46 PM56 PM66 PM126 Pxn pin I O mode specification x 0 n 0to5 x 2 6 12 0 to 7 X 7 0 2 13 0 1 Output mode output buffer Input mode output buffer off User s Manual U12697EJ4V1UD 131 CHAPTER 5 PORT FUNCTIONS 2 Pull up resistor option registers PU0 PU2 PU3 PU7 PU12 PUO These registers are used to set whether to use an on chip pull up resistor at each port or not in 1 bit or 8 bit units PUn n 0 2 3 7 12 can specify pull up resistor connection at each port pin PUO can specify pull up resistor connection at ports 4 5 and 6 Pull up resistors are connected irrespective of whether an alternate function is used These registers are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to 00H Cautions 1 Ports 1 and 13 do not incorporate pull up resistors 2 For ports 4 5 and 6 a pull up resistor can be connected in external memory expansion mode Figure 5 21 Form
229. IDLE modes Data retention current STOP mode Voo 2 0 V 10 Voo 5 0 V 10 Pull up resistor Note When the main system clock is stopped and the subsystem clock is operating Remark Unless otherwise specified the characteristics of alternate function pins are the same as those of port pins 558 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS AC Characteristics Ta 40 to 85 C Voo AVpp 1 8 to 5 5 V Vss AVss 0 V 1 Read write operation 1 3 Parameter Cycle time Conditions 4 5 V lt Voo lt 5 5 V 80 2 7 V lt Vo lt 4 5 V 160 2 0 V lt Voo lt 2 7 V 320 1 8 V lt Voo lt 2 0 V 500 Address setup time to ASTBL Voo 5 0 V 10 0 5 a T 20 Voo 3 0 V 10 0 5 a T 40 Voo 2 0 V 10 0 5 a T 80 Address hold time from ASTBL THSTLA Voo 5 0 V 10 0 5T 19 Voo 3 0 V 10 0 5T 24 Voo 2 0 V 10 0 5T 34 ASTB high level width Voo 5 0 V 10 0 5 a T 17 Voo 3 0 V 10 0 5 a T 40 Voo 2 0 V 10 0 5 a T 110 Address hold time from RDT Voo 5 0 V 10 0 5T 14 Voo 3 0 V 10 0 5T 14 Voo 2 0 V 10 0 5T 14 Delay time from address to RD Voo 5 0 V 10 1 a T 24 Voo 3 0 V 10 1 a T 35 Voo 2 0 V 10 1 a T 80
230. ION OFH MOVG SP STKBGN User s Manual U12697EJAV1UD 89 CHAPTER 4 CLOCK GENERATOR 4 1 Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware The following two types of system clock oscillators are available 1 Main system clock oscillator This circuit oscillates at frequencies of 2 to 12 5 MHz Oscillation can be stopped by setting the standby control register STBC to STOP mode bit 1 STP 1 bit 0 HLT 0 or by stopping the main system clock bit 2 of STBC MCk 1 after switching to the subsystem clock 2 Subsystem clock oscillator This circuit oscillates at the frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the internal feedback resistor can be set by STBC This enables the power consumption to be decreased in the STOP mode 4 2 Configuration The clock generator includes the following hardware Table 4 1 Clock Generator Configuration Item Configuration Control registers Standby control register STBC Oscillation mode selection register CC Clock status register PCS Oscillation stabilization time specification register OSTS Oscillators Main system clock oscillator Subsystem clock oscillator 90 User s Manual U12697EJ4V1UD CHAPTER 4 CLOCK GENERATOR Figure 4 1 Block Diagram of Clock Generator Subsystem fxr _ Watch timer clock clock output function oscillator
231. L WRELO E ar Note INTIICO When EXCO 1 TRCO L Receive Note Release the slave wait by either IICO FFH or setting WRELO 344 User s Manual U12697EJ4V1UD CHAPTER 18 I2C BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 20 Master Slave Communication Example When Master and Slave Select 9 Clock Wait 2 3 2 Data Master device process IIC0 IIC0 Data IIC0 Data STDO SPDO L WTIMO H ACKEO H 5 50 H STTO L SPTO L WRELO INTIICO A TRCO H Transfer lines SCLO 8 d SDAO DO D7 X D6 X D5 Slave device process IIC0 lt FFHNete ACKD0 STDO L SPDO L WTIMO H ACKEO H MSTSO L STTO L SPTO L Note WRELO INTIICO TRCO L Receive Note Release the slave wait by either IICO FFH or setting WRELO User s Manual U12697EJAV1UD 345 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 20 Master Slave Communication Example When Master and Slave Select 9 Clock Wait 3 3 3 Stop condition Master device process IIC0 IIC0 Data IIC0 Address ACKD0 STD0 SPD0 WTIMO H ACKE0 H MSTS0 STTO SPTO WREL0 L N 4 INTIICO ILIA TRCO H Send Transfer lines 1 2 3 4 5 6 7 8 9K 1 2 SCLO SDAO N 27 X D6 X DS X D4 X DS X D2 X D X DON 6 XA5 Stop condition Start condition Sla
232. M Figure 22 25 Asynchronous Serial Reception Internal RAM 0FE7FH MSC 0EH SFRP 74HNote Note Lower 8 bits of RXB1 address OFE70H Channel pointer 7FH Type A SFR Memory 8 bit transfer Mode register 11H interrupt request generation when MSC 0 Internal bus Receive buffer RXB1 RxD1 P20 INTSR1 macro service request Shift register Remark Addresses in the figure are the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed 0 0000 should be added to the values in the figure 408 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 8 7 Macro service type B 1 Operation Datatransfers are performed between a data area in memory and an SFR specified by the macro service channel With type B the data transfer direction can be selected as memory to SFR or SFR to memory Data transfers are performed the number of times set beforehand in the macro service counter One macro service processing transfers 8 bit or 16 bit data This type of macro service is macro service type A for general purposes and is ideal for processing a large amount of data because up to 64 KB of data buffer area when 8 bit data is transferred or 128 KB of data buffer area when 16 bit data is transferred can be set in any address space of 1 MB User s Manual U12697EJAV1UD 409 CHAPTER 22 IN
233. M26 PM25 PM24 PM23 PM22 21 20 2 1 mode selection n 0 to 7 Output mode output buffer Input mode output buffer off User s Manual U12697EJ4V1UD 353 CHAPTER 20 BUZZER OUTPUT FUNCTIONS 20 1 Function This function outputs a square wave at frequencies of 1 5 kHz 3 1 kHz 6 1 kHz and 12 2 kHz The buzzer frequency selected by the clock output control register CKS is output from the BUZ P24 pin The following procedure outputs the buzzer frequency lt 1 gt Select the buzzer output frequency by using bits 5 to 7 BCS0 BCS1 BZOE of CKS In a state where the buzzer is prohibited from sounding lt 2 gt Set the P24 output latch to 0 lt 3 gt Set bit 4 PM24 of the port 2 mode register PM2 to 0 to set the output mode Caution When the output latch of P24 is set to 1 the buzzer output cannot be used 20 2 Configuration The buzzer output function includes the following hardware Table 20 1 Configuration of Buzzer Output Function Control register Clock output control register CKS Port 2 mode register PM2 Figure 20 1 Block Diagram of Buzzer Output Function fxx 210 fxx 211 fxx 212 bo 213 Selector gt BUZ P24 L BZOE BCS1 50 P24 output latch PM24 Clock output control register CKS Port 2 mode register PM2 Internal bus 354 User s Manual U12697EJ4V1UD CHAPTER 20 BUZZER OUTPUT FUNCTIONS
234. Mask Registers MK0 MK1 lt Byte access gt Address 0FFACH to 0FFAFH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L 1 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDTMK MKOH TMMK3 STMK2 SRMK2 SERMK2 STMK1 SRMK1 SERMK1 CSIMKO MK1L 1 TMMK6 TMMK5 ADMK TMMK2 TMMK1 TMMK01 TMMK00 MK1H Interrupt servicing enabled Interrupt servicing disabled lt Word access gt Address 0FFACH 0FFAEH After reset FFFFH R W Symbol 15 14 13 12 11 10 9 8 MKO TMMK3 STMK2 SRMK2 SERMK2 STMK1 SRMK1 SERMK1 CSIMKO 7 6 5 4 3 2 1 0 1 5 PMK4 PMK3 PMK2 PMK1 PMKO WDTMK 15 14 13 12 11 10 9 8 MK1 1 1 1 1 1 1 WTMK 1 Interrupt request enable disable Interrupt servicing enabled Interrupt servicing disabled User s Manual U12697EJ4V1UD 371 CHAPTER 22 INTERRUPT FUNCTIONS 22 3 3 In service priority register ISPR The ISPR shows the priority level of the maskable interrupt currently being serviced and the non maskable interrupt being processed When a maskable interrupt request is acknowledged the bit corresponding to the priority of that interrupt request is set 1 and remains set until the service program ends When a non maskable interrupt is acknowledged the bit corresponding to the priority of that non maskable interrupt is set 1 and remains set until the service program ends When the RETI or RETCS instruction is executed the bit among those set 1 in t
235. NCTIONS 23 7 External Memory Connection Example u PD784225 A8to A19 ASTB AD0 to AD7 462 Vppi Figure 23 15 Example of Local Bus Interface Multiplexed Bus SRAM cs OE Data bus WE 1 01 to 1 08 Address bus 0 to A19 Address latch User s Manual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION 24 1 Configuration and Function The uPD784225 has a standby function that can decrease the system s power consumption The standby function has the following six modes Table 24 1 Standby Function Modes HALT mode Stops the CPU operating clock The average power consumption can be reduced by intermittent operation during normal operation chips internal STOP mode Stops the main system clock All of the chip s internal operations are stopped and an extremely low power consumption state of only leakage current is entered IDLE mode In this mode the oscillator continues operating while the rest of the system stops Power consumption in the IDLE mode is close to that in the STOP mode but normal program operation can be restored in about the same time as it takes from the HALT mode Low power consumption mode The subsystem clock is used as the system clock and the main system clock is stopped The CPU can operate with the subsystem clock to reduce power consumption Low power consumption HALT mode This is a standby function in the low po
236. NTCSII INTSER1 INTIICONete INTCSIO INTP5 INTP4 INTP3 INTP2 INTP1 INTPO INTWDTM 401 CHAPTER 22 INTERRUPT FUNCTIONS 2 402 Macro service mode register The macro service mode register is an 8 bit register that specifies the macro service operation This register is written in internal RAM as part of the macro service control word refer to Figure 22 21 The format of the macro service mode register is shown in Figure 22 22 Figure 22 22 Format of Macro Service Mode Register 1 2 7 6 1 0 5 4 3 2 vae wooo ors ons Counter Mode Counter Data transfer Data size Datatransfer Data size decrement direction 1 byte direction 1 byte Memory gt SFR Memory gt SFR Data transfer Data transfer direction direction SFR gt memory SFR gt memory Data transfer Data size Datatransfer Data size direction 2 bytes direction 2 bytes Memory gt SFR Memory gt SFR Data transfer Data transfer direction direction SFR gt memory SFR gt memory User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 22 Format of Macro Service Mode Register 2 2 1 0 7 6 5 4 3 2 VCIE MOD2 CHT3 CHT2 CHT1 CHTO Type C Decrements MPD Increments MPD Data size for timer specif
237. NTERRUPT FUNCTIONS Figure 22 9 Return from BRKCS Instruction Software Interrupt RETCSB Instruction Operation Register bank n n 0 to 7 D Restoration Restoration RETCSB instruction operand Transfer Restoration To original register bank 22 5 Operand Error Interrupt Acknowledgement Operation An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of the MOV STBC byte instruction or LOCATION instruction or the MOV WDM byte instruction does not match the 4th byte of the operand Operand error interrupts cannot be disabled When an operand error interrupt is generated the program status word PSW and the start address of the instruction that caused the error are saved to the stack the IE flag is cleared 0 the vector table value is loaded into the program counter PC and a branch is performed within the base area only As the address saved to the stack is the start address of the instruction in which the error occurred simply writing an RETB instruction at the end of the operand error interrupt service program will result in generation of another operand error interrupt You should therefore either process the address in the stack or initialize the program by referring to 22 12 Restoring Interrupt Function to Initial State 378 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 6 Non Maskabl
238. OC0 Address OFF1AH After reset Symbol TOCO 7 Cautions 1 154 00H R W 4 1 o OSPE TOCO4 LVSO LVRO TOCO1 TOEO OSPT Output trigger control of one shot pulse by software One shot pulse output disabled One shot pulse output enabled OSPE Controls of one shot pulse output operation Successive pulse output One shot pulse output Inversion disabled Inversion enabled Timer output control by software Not affected Reset 0 Set 1 Setting prohibited Inversion disabled Inversion enabled TOEO Output control of 16 bit timer event counter Output disabled output is fixed to O level Output enabled Before setting TOCO be sure to stop the timer operation 2 LVS0 and LVRO are 0 when read after data has been set to them 3 OSPT is 0 when read because it is automatically cleared after data has been set User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 4 Prescaler mode register 0 PRM0 This register selects the count clock of the 16 bit timer event counter and the valid edge of the TIOO and TIO1 input PRMO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PRMO to 00H Figure 8 5 Format of Prescaler Mode Register 0 PRMO Address OFF1CH After reset 00H R W Symbol 7 6 5 4 1 0 3 2 Selection of valid edge of TIO1 Falling edge Rising edge Setting prohibited Bo
239. OCAL BUS INTERFACE FUNCTIONS 23 4 Timing of External Memory Expansion Functions The timing control signal output pins in the external memory expansion mode are described below 1 RD pin shared by P64 This pin outputs the read strobe during an instruction fetch or a data access from external memory During an internal memory access the read strobe is not output held at the high level 2 WR pin shared by P65 This pin outputs the write strobe during a data access to external memory During an internal memory access the write strobe is not output held at the high level 3 WAIT pin shared by P66 This pin inputs the external wait signal When the external wait is not used the WAIT pin can be used as an I O port During an internal memory access the external wait signal is ignored 4 ASTB pin shared by P67 This pin always outputs the address strobe in any instruction fetch or data access from external memory During an internal memory access the address strobe is not output held at the low level 5 AD0 to AD7 A8 to A15 A16 to A19 pins shared by P40 to P47 P50 to P57 P60 to P63 These pins output the address and data signals When an instruction is fetched or data is accessed from external memory valid signals are output or input During an internal memory access the signals do not change Figures 23 5 to 23 8 are the timing charts User s Manual U12697EJ4V1UD 445 CHAPTER 23 LOCAL BUS INTERFACE FUNC
240. Releasing IDLE Mode 2 2 3 IDLE mode during interrupt servicing routine whose priority is higher than or equal to release source interrupt Main routine INT Y MOV STBC byte IDLE mode IDLE mode release IDLE mode release source interrupt pending Execution of the pending interrupt lt 4 IDLE mode during interrupt servicing routine whose priority is lower than release source interrupt Main routine IDLE mode MOV STBC byte IDLE mode release INT Execution of the IDLE mode release source s interruption 492 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Figure 24 9 Operations After Releasing IDLE Mode 3 3 5 Conflict between IDLE mode seiting instruction and interrupt Main routine MOV STBC byte IDLE mode not executed Execute instruction up to 6th clock Interrupt servicing User s Manual U12697EJ4V1UD 493 CHAPTER 24 STANDBY FUNCTION 1 2 3 494 Releasing IDLE mode by NMI input When the valid edge specified by external interrupt edge enable register 0 EGP0 EGN0 is input by NMI input the IDLE mode is released When the IDLE mode is released and non maskable interrupts from the NMI pin input can be acknowledged execution branches to the NMI interrupt service program If acknowledgement is not possible such as when the IDLE mode has been set in the NMI interrupt service program execution
241. S Target Mask ROM Versions IMS Settings uPD784224 EEH uPD784225 FFH User s Manual U12697EJ4V1UD 69 CHAPTER 3 CPU ARCHITECTURE 3 7 Control Registers The control registers are the program counter PC program status word PSW and stack pointer SP 3 7 1 Program counter PC This is a 20 bit binary counter that saves address information about the program to be executed next see Figure 3 5 Usually this counter is automatically incremented based on the number of bytes in the instruction to be fetched When the instruction that is branched is executed the immediate data or register contents are set RESET input sets the lower 16 bits of the PC to the 16 bit data at addresses 0 and 1 and the higher four bits of the PC to 0000 Figure 3 5 Format of Program Counter PC 19 0 PG 3 7 2 Program status word PSW The program status word PSW is a 16 bit register that consists of various flags that are set and reset based on the result of the instruction execution A read or write access is performed in higher 8 bit PSWH and lower 8 bit PSWL units In addition bit manipulation instructions can be used to manipulate each flag The contents of the PSW are automatically saved on the stack when a vectored interrupt request is acknowledged and when a BRK instruction is executed and are automatically restored when a RETI or RETB instruction is executed When context switching is used the contents are aut
242. STBL tosTip Voo 5 0 V 10 2 T 35 Voo 3 0 V 10 2 T 50 Voo 2 0 V 5 2 n T 80 Data input time from RD Remark 1 fxx fxx Main system clock frequency Voo 5 0 V 10 1 5 n T 40 Voo 3 0 V 10 1 5 n T 50 Voo 2 0 V 5 a 1 during address wait otherwise 0 n Number of wait states n 2 0 576 User s Manual U12697EJAV1UD 1 5 T 90 CHAPTER 29 ELECTRICAL SPECIFICATIONS 1 Read write operation 2 3 Parameter Delay time from ASTBL to RD Conditions Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 Data hold time from RD Voo 5 0 V 10 0 Voo 3 0 V 10 0 Voo 2 0 V 5 0 Address active time from RDT Voo 5 0 V 10 0 5T 2 Voo 3 0 V 10 0 5T 12 Voo 2 0 V 5 0 5T 35 Delay time from RDT to ASTBT Voo 5 0 V 10 0 57 9 Voo 3 0 V 10 0 5T 9 Voo 2 0 V 5 0 5T 40 RD low level width Voo 5 0 V 10 1 5 n T 25 Voo 3 0 V 10 1 5 n T 30 Voo 2 0 V 5 1 5 n T 25 Address active time from WRT Voo 5 0 V 10 0 5T 2 Voo 3 0 V 10 0 5T 12 Voo 2 0 V 5 0 5T 35 Delay time from address to WR Voo 5 0 V 10 1 a T 24 Voo 3 0 V 10 1 34 Voo 2 0 V
243. Space The external memory space is the memory space that can be accessed based on the setting of the memory expansion mode register MM The program and table data can be stored and peripheral I O devices can be assigned 68 User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE 3 6 uPD78F4225 Memory Mapping The uPD78F4225 has a 128 KB flash memory and 4 352 byte internal RAM The uPD78F4225 has a function memory size switching function so that a part of the internal memory is not used by the software The memory size is switched by the internal memory size switching register IMS Based on the IMS setting the memory mapping can be the same memory mapping as the mask ROM versions with different internal memories ROM RAM IMS can only be written by an 8 bit memory manipulation instruction RESET input sets IMS to FFH Figure 3 4 Format of Internal Memory Size Switching Register IMS Address OFFFCH After rese FFH W Symbol 7 6 5 4 3 2 1 0 Internal ROM capacity selection Internal RAM capacity selection 1 536 bytes 2 304 bytes 3 072 bytes 3 840 bytes Caution Mask ROM versions uPD784224 784225 do not have an IMS register Even if a write instruction is executed to IMS in mask ROM versions the instruction will be invalid Table 3 3 shows the IMS settings that produce the same memory map as the mask ROM versions Table 3 3 Settings of Internal Memory Size Switching Register IM
244. T 10 Voo 2 0 V 10 0 5 n T 30 Delay time from ASTBJ to WAITT tDSTWTH Voo 5 0 V 10 1 5 n T 40 Voo 3 0 V 10 1 5 n T 60 Voo 2 0 V 10 1 5 T 90 Input time from RD to WAIT DRWTL Voo 5 0 V 10 T 40 Voo 3 0 V 10 60 Voo 2 0 V 10 T 70 Hold time from RDJ to WAIT Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 10 Delay time from RD to WAITT DRWTH Voo 5 0 V 10 1 n T 40 Voo 3 0 V 10 1 n T 60 Voo 2 0 V 10 1 n T 90 Input time from WAIT to data towTip Voo 5 0 V 10 0 5T 5 Voo 3 0 V 10 0 5T 10 Voo 2 0 V 10 0 5T 30 Delay time from WAITT to RDT Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 10 Delay time from WAITT to WRT Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 10 Delay time from WR to WAIT Remark T tcyk 1 fxx fxx Main system clock frequency tpwwrL Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 10 a 1 during address wait otherwise 0 n Number of wait states n gt 0 562 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 External wait timing 2 2 Parameter Conditions Hold time from WR to Voo 5 0 V 10 WAIT Voo 3 0 V 10 Voo 2 0 V 10
245. T input sets PM2 to FFH Figure 20 3 Format of Port 2 Mode Register PM2 Address OFF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 PM27 PM26 PM25 PM24 PM23 PM22 21 20 P2n pin mode selection n 0 to 7 Output mode output buffer Input mode output buffer off User s Manual U12697EJ4V1UD CHAPTER 21 EDGE DETECTION FUNCTION The POO to P05 pins have an edge detection function that be programmed to detect the rising edge or falling edge and send the detected edge to on chip hardware components The edge detection function is always functioning even in the STOP mode and IDLE mode 21 1 Control Registers External interrupt rising edge enable register 0 EGPO external interrupt falling edge enable register 0 EGNO The EGPO and EGNO registers specify the valid edge to be detected by the 00 to P05 pins They can be read written by an 8 bit or 1 bit manipulation instruction RESET input sets EGPO and EGNO to 00H Figure 21 1 Format of External Interrupt Rising Edge Enable Register 0 EGPO and External Interrupt Falling Edge Enable Register 0 EGNO Address OFFAOH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Address OFFA2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 eeno o o INTPn pin valid edge n 0 to 5 Interrupt disabled Falling edge Rising edge Both rising and falling edges User s Manual U126
246. TER 8 16 BIT TIMER EVENT COUNTER Figure 8 23 Control Register Settings in Square Wave Output Mode a 16 bit timer mode control register 0 TMC0 TMC03 TMC02 TMC01 OVFO o olo i o o Clears and starts on match between TM0 and CR00 b Capture compare control register 0 CRC0 CRC02 CRC01 CRC00 e e e e m w CR00 used as compare register c 16 bit timer output control register 0 TOCO OSPT OSPE TOC04 LVSO LVRO 01 TOEO Enables TOO output Reverses output on match between TMO and CROO Specifies initial value of TOO output Does not reverse output on match between TMO and CRO1 Disables one shot pulse output Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the square wave output function For details refer to Figures 8 2 to 8 4 Figure 8 24 Timing of Square Wave Output Operation mopomu LE LI LJ LT LI LE LT U LIL LU uu ro coun vaue ooo N INTTM00 TOO pin output User s Manual U12697EJAV1UD 169 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 4 6 Operation to output one shot pulse The 16 bit timer event counter can output a one shot pulse in synchronization with a software trigger and an exte 1 rnal trigger T100 P35 pin input One shot pulse output with software trigger A one shot pulse can be output from the TO0 P30 pin
247. TERRUPT FUNCTIONS Figure 22 26 Macro Service Data Transfer Processing Flow Type B Macro service request acknowledgment Read contents of macro service mode register Determine channel type Other To other macro service processing TYPE B Read channel pointer contents m Determine transfer direction Memory SFR SFR Memory Select transfer source SFR with Select transfer source memory with SFR pointer macro service pointer MP Read data from SFR and write to Read data from memory and write to memory addressed by MP SFR specified by SFR pointer Increment MPNete Note 1 byte transfer 1 2 byte transfer 2 MSC lt MSC 1 No Yes Clear 0 interrupt service mode bit ISM Yes Clear 0 interrupt request flag IF e interrupt request generation 410 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS 2 Macro service channel configuration The macro service pointer MP indicates the data buffer area in the 1 MB memory space that is the transfer destination or transfer source The lower 8 bits of the SFR that is the transfer destination or transfer source is written to the SFR pointer SFRP The macro service counter MSC is a 16 bit counter that specifies the number of data transfers The macro service channel that stores the MP SFRP and MSC is located in internal RAM space addresses to OFEFFH when the LOCATION O
248. TION OPERATION 7 16 bit arithmetic instructions ADDW SUBW CMPW Mnemonic ADDW Operand AX word Operation AX CY AX word rp word rp CY lt rp word rp rp rp CY lt rp rp AX saddrp2 AX CY AX saddrp2 rp saddrp rp CY lt rp saddrp saddrp rp saddrp CY saddrp rp rp sfrp rp CY c rp sfrp sfrp rp OD GOD GOO N IO sfrp CY lt sfrp rp saddrp word saddrp CY saddrp word sfrp word sfrp CY lt sfrp word saddrp saddrp saddrp CY saddrp saddrp AX word lt AX word word CY lt rp word CY lt rp rp saddrp2 AX lt AX saddrp2 rp saddrp rp CY lt rp saddrp saddrp rp saddrp CY saddrp rp rp sfrp rp CY lt rp sfrp sfrp rp GC GO wl GOO NINI GO sfrp CY lt sfrp rp saddrp word saddrp saddrp word sfrp word sfrp CY lt sfrp word saddrp saddrp saddrp CY saddrp saddrp AX word AX word rp word rp word rp rp rp rp AX saddrp2 AX saddrp2 rp saddrp rp saddrp saddrp rp saddrp rp rp sfrp rp sfrp
249. TIONS 446 Figure 23 5 Instruction Fetch from External Memory in External Memory Expansion Mode ASTB RD AD0 to AD7 A8 to A19 ASTB RD ADO to AD7 A8 to A19 Internal wait signal 1 clock wait ASTB RD ADO to AD7 A8 to A19 WAIT a Setting 0 wait cycles PW01 PWOO 0 0 Instruction code Higher address b Setting 1 wait cycle PWO1 PW00 0 1 c Setting an external wait PWO1 PWOO 1 1 EMG MMC X Lower address X Instruction code X X Higher address X User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 6 Read Timing for External Memory in External Memory Expansion Mode AD0 to AD7 A8to A19 ASTB RD AD0 to AD7 A8 to A19 Internal wait signal 1 clock wait ASTB RD ADO to AD7 A8 to A19 WAIT a Setting 0 wait cycles PW01 PWOO 0 0 X Higher address b Setting 1 wait cycle PWO1 PWOO 0 1 LM N LLL X Higher address c Setting an external wait PW01 PWOO 1 1 MEE AGE ooo o r rw Higher address 222 22 honera OO User s Manual U12697EJ4V1UD 447 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 7 ASTB WR AD0 to AD7 A8 to A19 ASTB WR ADO to AD7 A8 to A19 Internal wait signal 1 clock wait ASTB WR ADO to AD7 A8 to A19 WAIT 448 External Write Timing for External Memory in External Memory Expansion Mode a Setting 0 wait
250. TM2 utput fou B fxx 29 TI2 O Edge detector Run 20 INTTM2 Remark OVF Overflow flag User s Manual U12697EJAV1UD 143 CHAPTER 7 TIMER OVERVIEW Figure 7 1 Block Diagram of Timer 2 2 8 bit timer 5 fxx 22 fo 23 Clear 4 8 bit timer counter 5 t 8 TMS 8 2 2 pode 8 bit compare register 50 5 INTTM5 CR50 D 6 8 bit timer 6 fxx 23 8 bit timer counter 6 pet 3 TM6 fxx 25 fxx 27 2 8 bit compare register 60 INTTM6 CR60 144 User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 1 Function The 16 bit timer event counter has the following functions Interval timer PPG output Pulse width measurement External event counter Square wave output One shot pulse output 1 Interval timer When the 16 bittimer event counter is used as an interval timer it generates an interrupt request at predetermined time intervals 2 PPG output The 16 bit timer event counter can output a square wave whose frequency and output pulse width can be freely set 3 Pulse width measurement The 16 bit timer event counter can be used to measure the pulse width of a signal input from an external source 4 External event counter The 16 bit timer event counter can be used to measure the number of pulses of a signal input from an external source 5 Square wave output Th
251. TO Set the STTO flag communication reservation Define communication Define that communication is being reserved Defines and sets the user flag to any RAM Wait Save the wait time by the software see Table 18 5 Communication reservation e e Yes Check the communication reservation No Start condition generated Communication cies Clear the user flag reservation is released 9 MOV IICO xxH write H Note When the communication is being reserved serial shift register 0 IICO is written by the stop condition interrupt Remark 5 0 1 in 12 bus control register 0 IICC0 MSTSO Bit 7 in I2C bus status register 0 IICSO IIC0 Serial shift register 0 User s Manual U12697EJ4V1UD 339 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 15 Additional cautions After a reset when the master is communicating from the state where the stop condition is not detected bus is not released perform master communication after the stop condition is first generated and the bus is released Multiple masters cannot communicate in the state where the bus is not released the stop condition is not detected The following procedure generates the stop condition 1 Set prescaler mode register 0 SPRMO for the serial clock 2 Set bit 7 IICEO in IC bus control register 0 IICCO lt 3 gt Set bit 0 of IICCO 340 User s Manual U12697EJ
252. TP0 to INTP5 low level width RESET high low level width User s Manual U12697EJ4V1UD 583 CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Converter Characteristics Ta 40 to 85 C AVpp 1 9 to 5 5 V Vss AVss 0 V Parameter Conditions Resolution Overall errorNotes 1 2 6 25 MHz lt fxx lt 12 5 MHz 4 5 V lt Voo lt 5 5 V AVpp 3 125 MHz lt fxx lt 6 25 MHz 2 7 V lt 5 5 V AVpp 2 MHz lt fxx lt 3 125 MHz 2 0 V lt Von lt 5 5 V AVpp 2 MHz 1 9 V lt lt 5 5 V AVpp Conversion time tconv 14 Sampling time tsamp 24 fxx Analog input voltage Vian AVss Reference voltage Resistance between Ravrero A D conversion is not performed AVppo AVss Notes 1 Excludes quantization error 0 2 FSR 2 This value is indicated as a ratio to the full scale value FSR Remark fxx Main system clock frequency D A Converter Characteristics Ta 40 to 85 C AVpp 1 9 to 5 5 V Vss AVss 0 V Parameter Conditions Resolution Overall errorNotes 1 2 2 0 V Voo 5 5 V R 10 MQ 2 0 V lt lt AVop 1 9 V lt Voo lt 2 0 V AVpp R 10 MQ 1 9 V lt AVner lt AVop Settling time Load conditions 4 5 V lt lt 5 5 V C 30 pF 2 7 V lt AVRnz
253. TRUCTION OPERATION Mnemonic Operand Bytes saddr bit addr20 Operation PC lt PC 4Note 2 jdisp8 saddr bit 1 if saddr bit 0 Flag s Z AC P V CY sfr bit addr20 PC PC 4 jdisp8 sfr bit 1 if sfr bit 0 X bit addr20 PC PC 3 jdisp8 X bit lt 1 if X bit 0 A bit addr20 PC PC 3 jdisp8 A bit 1 if A bit 0 PSWL bit addr20 PC PC 3 jdisp8 PSWL bit 1 if PSW bit 0 PSWH bit addr20 PC PC jdisp8 PSWi bit lt 1 if PSWu bit 0 laddr16 bit addr20 PC PC 3 jdisp8 addr16 bit 1 if laddr16 bit 0 lladdr24 bit addr20 PC PC 3 jdisp8 lladdr24 bit 1 if lladdr24 bit 0 mem2 bit addr20 PC PC 3 jdisp8 mem2 bit 1 if mem2 bit 0 B addr20 B B 1 PC PC 2 jdisp8 if B 0 C addr20 C C 1 PC PC 2 jdisp8 if C 0 saddr addr20 saddr saddr 1 PC lt 3Note 1 jdisp8 if saddr z 0 Notes 1 This is used when the number of bytes is three When four it becomes PC lt PC 4 jdisp8 2 This is used when the number of bytes is four When five it becomes PC lt PC 5 jdisp8 19 CPU control instructions MOV LOCATION SEL SWRS NOP El DI Mnemonic Operand STBC byte Operation STBC lt byte Flag S Z AC P V CY WDM byte
254. Table 16 2 Serial Interface Operation Mode Settings 1 Operation stopped mode CSIMn PM20 CSIEn SCLn1 SCLn0 P20 21 P21 22 22 70 P70 71 P71 72 P72 P20 RxD1 SI1 P70 RxD2 SI2 Pin Function P21 TxD1 SO1 P71 TxD2 SO2 Pin Function P22 ASCK1 SCK1 P72 ASCK2 SCK2 Pin Function 2 Asynchronous serial interface mode Other than above CSIMn CSIEn SCLn1 SCLnO y Note 1 Note 1 QNote 2 External clock yNote 1 Note 1 Internal clock Setting prohibited P20 RxD1 SI1 P70 RxD2 SI2 Pin Function P21 TxD1 SO1 P71 TxD2 SO2 Pin Function TxDn CMOS output P22 ASCK1 SCK1 P72 ASCK2 SCK2 Pin Function ASCKn input P22 P72 yNote 1 Note 1 External clock Internal clock External clock yNote 1 Note 1 Internal clock ASCKn input P22 P72 TxDn CMOS output ASCKn input Other than above 3 3 wire serial I O mode CSIMn CSIEn SCLn1 SCLn0 Note 4 Note 3 Note 3 External clock Internal clock Setting prohibited P20 RxD1 SI1 P70 RxD2 SI2 Pin Function S nNote 3 P21 TxD1 SO1 P71 TxD2 SO2 Pin Function SOn CMOS output P22 ASCK1 SCK1 P72 ASCK2 SCK2 Pin Function SCKn input SCKn output Remark Other than above
255. The SDAO and SCLO pins are provided only in the uPD784225Y Subseries User s Manual U12697EJ4V1UD 45 CHAPTER 2 PIN FUNCTIONS 2 Non port pins 2 2 Pin Name RTPO to RTP7 Output Alternate Function P23 Function Clock output for main system clock subsystem clock trimming P24 Buzzer output P120 to P127 Real time output port that outputs data synchronized with the trigger ADO to AD7 P40 47 Lower address data bus when the memory is externally expanded A8 to A15 A16 to A19 Output P50 to P57 Middle address bus when the memory is externally expanded P60 to P63 Higher address bus when the memory is externally expanded P64 Strobe signal output for external memory read P65 Strobe signal output for external memory write Input P66 Wait insertion during external memory access Output P67 Strobe output that externally latches the address information that is output to ports 4 to 6 in order to access external memory P37 External access status output X1 System reset input X2 Crystal connection for main system clock oscillation XT1 Input XT2 Crystal connection for subsystem clock oscillation ANIO to ANI7 Input P10 to P17 Analog voltage input for A D converter ANOO ANO1 Output P130 P131 Analog voltage output for D A converter AVREF1 Reference voltage applied f
256. The macro service ends when the processing has been performed the specified number of times when the macro service counter MSC reaches 0 Either of two operations may be performed at this point as specified by the VCIE bit bit 7 of the macro service mode register for each macro service 1 When VCIE bit is 0 In this mode an interrupt is generated as soon as the macro service ends Figure 22 18 shows an example of macro service and interrupt acknowledgment operations when the VCIE bit is 0 This mode is used when a series of operations end with the last macro service processing performed etc It is mainly used in the following cases Asynchronous serial interface receive data buffering INTSR1 INTSR2 A D conversion result fetch INTAD Compare register update as the result of a match between a timer register and the compare register INTTMOO INTTMO1 INTTM1 INTTM2 INTTM5 INTTM6 User s Manual U12697EJAV1UD 397 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 19 Operation at End of Macro Service When VCIE 0 Main routine Macro service request 1 Macro service processing Last macro service request Macro service processing a Other interrupt request Last macro Servicing of interrupt request d Bu due to end of macro service Servicing of other interrupt gt service request Servicing of interrupt request due to end of macro
257. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is g
258. V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL I O The uPD784225 provides two on chip serial interface channels for which the asynchronous serial interface UART mode and the 3 wire serial I O IOE mode can be selected These two serial interface channels have exactly the same functions Table 16 1 Differences in Names Between UART1 IOE1 and UART2 IOE2 Pin name UART1 IOE1 P22 ASCK1 SCK1 P20 RxD1 SI1 P21 TxD1 SO1 UART1 IOE2 P72 ASCK2 SCK2 P70 RxD2 SI2 P71 TxD2 SO2 Asynchronous serial interface mode register ASIM1 ASIM2 Name of bits inside asynchronous serial interface mode register TXE1 RXE1 PS11 PS10 CL1 SL1 ISRM1 TXE2 RXE2 PS21 PS20 CL2 SL2 ISRM2 Asynchronous serial interface status register ASIS1 ASIS2 Name of bits inside asynchronous serial interface status register PE1 FE1 OVE1 PE2 FE2 OVE2 Serial operation mode register CSIM1 CSIM2 Name of bits inside serial operation mode register CSIE1 MODE1 SCL11 SCL10 CSIE2 MODE2 SCL21 SCL20 Baud rate generator control register BRGC1 BRGC2 Name of bits inside baud rate generator control register TPS10 to TPS12 MDL10 to MDL13 TPS20 to TPS22 MDL20 to MDL23 Interrupt request name INTSR1 INTCSH INTSER1 INTST1 INTSR2 INTCSI2 INTSER2 INTST2 Interrupt control register and name of bits used in this chapter SRIC1 SERIC1 STIC1 SRIF
259. Wa lt A A PSWL A PSW A PSWH lt PSWH r3 byte lt byte A r3 A r3 NI NI GI NN N Ww r3 A 524 lt User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION 2 16 bit data transfer instruction MOVW Mnemonic MOVW Operand rp word Operation rp word Flag s Z AC P V CY saddrp word saddrp word sfrp word sfrp word laddr16 word addr16 word l addr24 word addr24 word rp rp rp rp AX saddrp2 AX lt saddrp2 rp saddrp rp saddrp saddrp2 AX saddrp2 AX saddrp rp saddrp lt rp AX sfrp AX lt sfrp rp sfrp rp sfrp sfrp AX sfrp AX sfrp rp sfrp rp saddrp saddrp saddrp saddrp rp addr16 rp addr16 laddr16 rp addr16 rp rp 24 rp addr24 lladdr24 rp QU O ol ysl wl nl wos nl nl nit oy Z addr24 rp AX saddrp AX lt saddrp AX saddrg AX lt saddrg AX mem AX mem saddrp AX saddrp AX saddrg AX saddrg AX mem AX mem AX User s Manual U12697EJ4V1UD 525 CHAPTER 28 INSTRUCTION OPERATION 3 24 bit data transfer in
260. Wait Times Wait Time 26 clocks x 1 fxx 46 clocks x 1 fxx 92 clocks x 1 fxx 37 clocks x 1 TM2 output 16 clocks x 1 fxx 32 clocks x 1 fxx 13 clocks x 1 TM2 output User s Manual U12697EJAV1UD 337 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 15 shows the timing of communication reservation Figure 18 15 Timing of Communication Reservation Program processing E write Communi SPDO and i STDO Hardware processing 2191 INTIICO M settings setting SCLO 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 p A t Output from the master that possessed the bus IC0 Serial shift register STTO Bit 1 in 12 bus control register 0 IICC0 STDO Bit 1 in 12 bus status register 0 IICSO SPDO Bit 0 in 2 bus status register 0 IICSO The communication reservation is accepted at the following timing After bit 1 STDO 1 in 2 bus status register 0 IICSO the communication is reserved by bit 1 STTO 1 in IC bus control register 0 IICCO until the stop condition is detected Figure 18 16 Communication Reservation Acceptance Timing SCLO SDAO STDO A SPDO Rh Wait state 338 User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 17 shows the communication reservation procedure Figure 18 17 Communication Reservation Procedure SET1 ST
261. When returning from subsystem clock operation stopped oscillation of the main system clock to main system clock operation do not simultaneously specify MCK 0 and CK2 0 by write instructions to STBC 2 The oscillation stabilization time specification register OSTS specifies the oscillation stabilization time after the STOP mode is released except when released by RESET when the system clock is the main system clock This cannot be used when the system clock is restored from the subsystem clock to the main system clock Figure 24 13 is the flow for restoring main system clock operation and Figure 24 14 is the restore timing diagram 498 User s Manual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION Figure 24 13 Flow to Restore Main System Clock Operation Normal operation using the subsystem clock Operating with the backup power supply Switch to the main power supply Write STBC 70H Execute the instruction that starts the main system clock x Has the oscillation NO stabilization time elapsed Software wait Execute the instruction that switches to the main system clock Write STBC 00H Figure 24 14 Timing for Restoring Main System Clock Operation Main system clock PFLELU LU LI LI LI LI LIL LU 1 I Subsystem clock LLLA I l System clock Oscillation stabilization time STBC 74H CST bit 1 Switch to main system clock Backup pow
262. X D REGISTER INDEX M Macro service mode register 401 Memory expansion mode register MM 437 O Oscillation mode selection register CC 93 Oscillation stabilization time specification register OSTS 95 467 P Port 0 P0 106 Port 0 mode register PM0 128 Port 1 P1 108 Port 2 P2 109 Port 2 mode register PM2 128 352 355 Port 3 P3 113 Port 3 mode register PM3 128 Port 4 P4 115 Port 4 mode register PM4 128 Port 5 P5 117 Port 5 mode register PM5 128 Port 6 P6 119 Port 6 mode register PM6 128 Port 7 P7 123 Port 7 mode register PM7 128 Port 12 P12 126 Port 12 mode register PM12 128 Port 13 P13 127 Port 13 mode register PM13 128 Port function control register 2 PF2 132 Prescaler mode register 0 PRMO 154 Prescaler mode register 1 PRM1 186 Prescaler mode register 2 PRM2 186 187 Prescaler mode register 5 PRM5 205 Prescaler mode register 6 PRM6 205 206 Prescaler mode register O for the serial clock SPRMO 303 Program status word PSW 375 Programmable wait control register 1 PWC1 438 Programmable wait control register 2 PWC2 438 Pull up resistor option register PUO 131 Pull up resistor option register 0 PUO 131 Pull up resistor option register 2 PU2 131 Pull up resistor option register 3 PU3 131 Pull up
263. X1 and TX2 can be written with an 8 bit memory manipulation instruction but cannot be read RESET input sets TXS1 and TXS2 to FFH Caution Do not write to TXS1 and TXS2 during transmission TXS1 TXS2 and receive buffer registers 1 2 RXB1 RXB2 are allocated to the same address Therefore attempting to read TXS1 and TXS2 will result in reading the values of RXB1 and RXB2 Receive shift registers 1 2 RX1 RX2 These registers are used to convert serial data input to the RxD1 and RxD2 pins to parallel data Receive data is transferred to receive buffer registers 1 and 2 RXB1 RSB2 one byte at a time as it is received RX1 and RX2 cannot be directly manipulated by program Receive buffer registers 1 2 RXB1 RXB2 These registers are used to hold receive data Each time one byte of data is received new receive data is transferred from receive shift registers 1 and 2 RX1 RX2 If a data length of 7 bits is specified receive data is transferred to bits 0 to 6 of RXB1 and RXB2 and the MSB of RXB1 and RXB2 always becomes 0 RXB1 and RXB2 can be read by an 8 bit memory manipulation instruction but cannot be written RESET input sets RXB1 and RXB2 to FFH Caution RXB1 RXB2 and transmit shift registers 1 2 TXB1 TXB2 are allocated to the same address Therefore attempting to read RXB1 and RXB2 will result in reading the values of TXB1 and TXB2 Transmission controller This circuit controls transmit operations such as the
264. a is as follows based on the wait timing When 8 clock waits are selected The acknowledge signal is synchronized with the falling edge of the eighth clock of SCL output by setting ACKEO 1 before the wait is released When 9 clock waits are selected By setting ACKEO 1 beforehand the acknowledge signal is synchronized with the falling edge of the eighth clock of SCLO and is automatically output 310 User s Manual U12697EJAV1UD CHAPTER 18 I2C BUS MODE uPD784225Y SUBSERIES ONLY 18 5 5 Stop condition When the SCLO pin is high and the SDAO pin changes from low to high a stop condition occurs The stop condition is the signal output by the master to the slave when serial transfer ends The slave has hardware that detects the stop condition Figure 18 12 Stop Condition SDAO The stop condition is generated when bit 0 SPTO of 2 bus control register 0 IICC0 is set to 1 And when the stop condition is detected if bit 0 SPDO in 12C bus status register 0 IICSO is set to 1 and bit 4 SPIEO of IICCO is also set to 1 INTIICO is generated User s Manual U12697EJAV1UD 311 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 6 Wait signal WAIT The wait signal notifies the other side that the master or slave is being prepared wait state for data communication The wait state is reported to the other side by setting the SCLO pin low When both the master and the slave are released from the wait state the nex
265. aaa aqsu do ix eU E ete CN VENE ROO in vt IO E Su Du UR 431 22 11 Interrupt and Macro Service Operation Timing seen 431 22 11 1 Interrupt acknowledge processing uu 432 22 11 2 Processing time of macro service esses nnne nennen nnne nene 433 22 12 Restoring Interrupt Function to Initial State eere 434 22213 er io eec EDDIE 435 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 437 23 1 External Memory Expansion Function 437 23 2 Control Hegislels u uU Aaa aa ii eras Ie 438 23 3 Memory Map for External Memory Expansion 440 23 4 Timing of External Memory Expansion Functions eese 445 23 5 Elaine 450 23 9 4 Address eo esee eem erit spes ee 450 DOO AGCOSSOWBlL 0 451 23 6 External Access Status Output Function U u u u u nnne 459 23 6 1 SUMMARY uu Q a 459 23 6 2 Configuration of external access status output function a a 459 23 6 3 External access st
266. able disable Interrupt servicing enabled Interrupt servicing disabled xxISMn Interrupt servicing mode specification Vectored interrupt servicing context switching processing Macro service processing Context switching processing specification Processing as vectored interrupt Processing by context switching xxPRnO Interrupt request priority specification Priority 0 Highest priority Priority 1 Priority 2 Priority 3 368 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS TMIC1 TMIC2 TMIF1 TMIF2 Figure 22 1 Interrupt Control Register xxICn 3 3 Address 0FFF2H to 0FFF6H 0FFF9H After reset 43H R W 2 Q TMMK1 TMISM1 TMCSE1 0 0 TMPR11 TMMK2 TMISM2 TMCSE2 0 0 TMPR21 ADMK ADISM ADCSE 0 0 ADPRO1 ADIC TMIC5 TMIF5 TMMKS TMISM5 TMCSE5 EMEN TMPR51 TMPRSO TMMK6 TMISM6 TMCSE6 TMPR61 TMPR60 WTMK WTISM WTCSE WTPR1 WTPR0 TMIC6 WTIC ADIF TMIF6 WTIF Interrupt request generation No interrupt request interrupt signal is not generated TMPR10 TMPR20 ADPR00 Interrupt request interrupt signal is generated Interrupt servicing enable disable Interrupt servicing enabled Interrupt servicing disabled Interrupt servicing mode specification Vectored interrupt servicing context switching processing Macro service processing Context switching p
267. able flag IE is set to 1 if interrupts can be acknowledged execution branches to interrupt service program When interrupts cannot be acknowledged and when the IE flag is cleared to 0 execution restarts from the instruction following the instruction that set the HALT mode For details of interrupt acknowledgement refer to 22 7 Maskable Interrupt Acknowledgment Opera tion iii Releasing HALT mode by RESET input When the RESET input rises from low to high and the reset condition is released the oscillator starts oscillating Oscillation stops for the RESET active period After the oscillation stabilization time elapses normal operation starts The difference from the normal reset operation is the data memory saves the contents before setting the HALT mode User s Manual U12697EJ4V1UD 501 CHAPTER 24 STANDBY FUNCTION 2 IDLE mode a Settings and operating states of IDLE mode When the low power consumption mode is set in the IDLE mode set 77H in STBC Table 24 10 shows the operating states in the IDLE mode Table 24 10 Operating States in IDLE Mode Clock generator The main system clock stops oscillating The oscillator of the subsystem clock continues operating The clock supplied to the CPU and the peripherals stops CPU Operation disabled Port output latch Holds the state before the IDLE mode was set 16 bit timer event counter Operational when the watch timer output is selected as the count clock
268. ace iiec i eraut sae cn need uenia nonae 3 6 uPD78F4225 Memory Mapping u u uu u 3 7 Registers RT 3 7 1 Program counter P enisi n ayaqku etes ahua w aus 23 72 Program status word POW 3 7 3 Using the RSS Dituuu P A qas 274 Stack pointer SP iiec operan diesel tines 3 8 General Purpose Registers 3 8 1 led c p X c 25 FUNCIONS ua duse tute etc Ir nad PET IE LLLA UN reer cee LI E err CE UI E 3 9 Special Function Registers SFRS U u u u u u u mue ge CHAPTER 4 CLOCK GENERATOR rentre IIIa eene era naa ME IIDMDI I 4 2 CONPIQUIALION m 4 3 2 Po 4 4 Systemi Clock Oscillator e trot reiecit iere cen benc 12 User
269. addition of a start bit parity bit and stop bit s to data written to transmit shift registers 1 and 2 TXS1 TXS2 according to contents set to asynchronous serial interface mode registers 1 and 2 ASIM1 ASIM2 Reception controller This circuit controls reception according to the contents set to asynchronous serial interface mode registers 1 and 2 ASIM1 ASIM 2 It also performs error check for parity errors etc during reception and transmission If it detects an error it sets a value corresponding to the nature of the error in asynchronous serial interface status registers 1 and 2 ASIS1 ASIS2 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 16 2 2 Control registers The asynchronous serial interface is controlled by the following six registers Asynchronous serial interface mode registers 1 2 ASIM1 ASIM2 Asynchronous serial interface status registers 1 2 ASIS1 ASIS2 Baud rate generator control registers 1 2 BRGC1 BRGC2 1 Asynchronous serial interface mode registers 1 2 ASIM1 ASIM2 ASIM1 and ASIM are 8 bit registers that control serial transfer using the asynchronous serial interface ASIM1 and ASIM2 are set by a 1 bit or 8 bit memory manipulation operation RESET input sets ASIM1 and ASIM2 to OOH User s Manual U12697EJAV1UD 261 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 Figure 16 3 Format of Asynchronous Serial Interface Mode Regis
270. addressing TDE RG6 This register functions as a pointer and sets the base address in register indirect addressing and based addressing This register functions as a pointer in string and SACW instructions WHL RG7 This register primarily performs 24 bit data transfers and operation processing This register functions as a pointer and specifies the base address during register indirect addressing or based addressing This functions as a pointer in string and SACW instructions User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE In addition to a function name X A C B E D L H AX BC VP UP DE HL VVP UUP TDE WHL that emphasizes its unique function each register can be described by an absolute name R0 to R15 RP0 to RP7 RG4 to RG7 For the correspondence refer to Table 3 5 Table 3 5 Correspondence Between Function Names and Absolute Names a 8 bit registers b 16 bit registers Function Name RSS 0 RSS 1Note Function Name RSS 0 RSS 1Note Absolute Name Absolute Name c 24 bit registers Absolute Name Function Name Note Use RSS 1 only when a 78K lll Series program is used Remark R8 to R11 do not have function names User s Manual U12697EJ4V1UD 83 CHAPTER 3 CPU ARCHITECTURE 3 9 Special Function Registers SFRs 84 These are registers that are
271. ain system clock oscillation does not stop When bit 6 CK2 of STBC is set to 1 and the operation is switched to subsystem clock operation CST 1 after that the main system clock oscillation stops refer to Figure 4 9 Figure 4 9 Main System Clock Stop Function 1 2 a Operation when MCK is sei after setting CK2 during main system clock operation MCK CK2 CST Oscillation does not stop Main system clock oscillation Subsystem clock oscillation CPU clock b Operation when MCK is set during main system clock operation MCK CK2 CST Oscillation does not stop Main system clock oscillation Subsystem clock oscillation CPU clock 102 User s Manual U12697EJAV1UD CHAPTER 4 CLOCK GENERATOR Figure 4 9 Main System Clock Stop Function 2 2 c Operation when CK2 is set after setting MCK during main system clock operation MCK CK2 CST A Main system clock oscillation Subsystem clock Y N oscillation CPU clock 4 5 2 Subsystem clock operations During operation with the subsystem clock with bit 6 CK2 of the standby control register STBC set to 1 the following operations are carried out a The instruction execution time remains constant minimum instruction execution time 61 us when operated at 32 768 kHz irrespective of the setting of bits 4 and 5 CKO and CK1 of STBC b The watchdog timer continues operating Caution Do not set the STOP mode while the subsystem clo
272. al I O or a display controller with an internal clocked serial interface 17 2 Configuration The 3 wire serial I O mode includes the following hardware Figure 17 1 is a block diagram of the clocked serial interface CSI in the 3 wire serial I O mode Table 17 1 3 Wire Serial Configuration Register Serial I O shift register 0 5100 Control register Serial operation mode register 0 CSIMO User s Manual U12697EJAV1UD 285 CHAPTER 17 3 WIRE SERIAL I O MODE SIO 500 SCK0 Figure 17 1 Block Diagram of Clocked Serial Interface in 3 Wire Serial I O Mode Internal bus Serial I O shift register 0 SIOO Serial clock Interrupt INTCSIO counter generator TO2 E controlle 4 71 fxx 16 Serial I O shift register 0 SIOO This 8 bit shift register performs parallel to serial conversion and serial communication shift operations synchro nized with the serial clock SIOO is set by an 8 bit memory manipulation instruction When bit 7 CSIEO in serial operation mode register 0 CSIMO is 1 serial operation starts by writing data to or reading it from SIOO When transmitting the data written to SIOO is output to the serial output SOO When receiving data is read from the serial input SIO to SIOO RESET input sets SIOO to 00H Caution Do not access SIOO during a transfer except for an access that becomes a transfer start
273. al U12697EJ4V1UD 457 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 12 Timing by External Wait Signal a Read Timing PW01 PW00 1 1 ADO to 07 Data input 2 ASTB output N RD output N WAIT input s b Write timing PW01 PW00 1 1 Soa MERC output address ASTB output N WR output N WAIT input Nf Note fxx Main system clock frequency This signal is only in the uPD784225 458 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 6 External Access Status Output Function 23 6 1 Summary The external access status signal is output from the P37 EXA pin This signal is output at the moment of external access when use of the external bus interface function has been enabled This signal detects the external access status of other devices connected to the external bus prohibits other devices from outputting data to the external bus and enables reception 23 6 2 Configuration of external access status output function Figure 23 13 Configuration of External Access Status Output Function External access EXA signal generator I P37 EXA STOP and IDLE status signals External input P37 EXAE register EXAE V External access status output circuit EXA P37 port User s Manual U12697EJAV1UD 459 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 6 3 External access status enable register
274. al en Espa a NEC Electronics Hong Kong Ltd Madrid Spain Seoul Branch Tel 091 504 27 87 Seoul Korea Tel 02 558 3737 Succursale Francaise V lizy Villacoublay France NEC Electronics Shanghai Ltd Tel 01 30 67 5800 Shanghai P R China Tel 021 5888 5400 e Filiale ltaliana Milano Italy Tel 02 66 75 41 NEC Electronics Taiwan Ltd Taipei Taiwan Branch The Netherlands Tel 0227192977 Eindhoven The Netherlands Tel 040 2654010 NEC Electronics Singapore Pte Ltd Novena Square Singapore e Tyskland Filial Tel 6253 8311 Taeby Sweden Tel 08 63 87 200 e United Kingdom Branch Milton Keynes UK Tel 01908 691 133 J05 6 6 User s Manual U12697EJ4V1UD Major Revisions in This Edition Page Description U12967JJ3V0UD00 U12967JJ4V0UD00 CHAPTER 1 OVERVIEW Change of 78K IV SERIES LINEUP Modification of minimum instruction execution time in 1 5 Function List CHAPTER 13 A D CONVERTER Modification of Cautions in Figure 13 2 Format of A D Converter Mode Register ADM CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL I O Addition of Table 16 2 Serial Interface Operation Mode Settings CHAPTER 17 3 WIRE SERIAL I O MODE Addition of Table 17 2 Serial Interface Operation Mode Settings CHAPTER 22 INTERRUPT FUNCTIONS Addition of reserved words in Figure 22 21 Format of Macro Service Control Word CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Modification of Table 23 3 Settings of Program Wait Con
275. alue setting register 1 OFF86H D A converter mode register 0 OFF87H D A converter mode register 1 OFF88H ROM correction control register OFF89H ROM correction address register H OFF8AH ROM correction address register L OFF8BH OFF8DH External access status enable register OFF90H Serial operation mode register 0 OFF91H Serial operation mode register 1 OFF92H Serial operation mode register 2 OFF94H Serial I O shift register 0 OFF95H Serial I O shift register 1 OFF96H Serial I O shift register 2 OFF98H Real time output buffer register L OFF99H Real time output buffer register H 9 Real time output port mode register OFF9BH Real time output port control register OFF9CH Watch timer mode control register OFFAOH External interrupt rising edge enable register 0 OFFA2H External interrupt falling edge enable register 0 OFFAS8H In service priority register OFFA9H Interrupt selection control register OFFAAH Interrupt mode control register OFFACH Interrupt mask flag register OL OFFADH Interrupt mask flag register OH OFFAEH Interrupt mask flag register 1L OFFAFH Interrupt mask flag register 1H OFFBOH 12C bus control register Note 2 xr S SR es Ses ss as
276. am of P71 D gt P ch A Output latch gt Internal bus P71 71 602 2 PM71 Alternate function PU Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal User s Manual U12697EJAV1UD 125 CHAPTER 5 PORT FUNCTIONS 126 3 a c g Figure 5 17 Block Diagram of 72 Voo P ch PU PM RD WR Output latch P72 SCK2 P72 AsCK2 Pull up resistor option register Port mode register Port 7 read signal Port 7 write signal User s Manual U12697EJ4V1UD CHAPTER 5 PORT FUNCTIONS 5 2 9 Port 12 This is an 8 bit I O port with an output latch Input mode output mode can be specified for the P120 to P127 pins in 1 bit units using the port 12 mode register A pull up resistor can be connected via pull up resistor option register 12 regardless of whether the input mode or output mode is specified Port 12 supports the real time output function as an alternate function RESET input sets port 12 to the input mode Figure 5 18 shows a block diagram of port 12 WReu Figure 5 18 Block Diagram of P120 to P127 Voo PU120 to PU127 D gt P ch a s 2 PU PM RD WR A Output latch 5 120 to 127 J 4 PM120 to 127 Alternate f
277. ameter Supply voltage Conditions Voo Ratings 0 3 to 6 5 lt 0 3 to 10 5 0 3 to 0 3 AVss 0 3 to Vsso 0 3 AVREF1 D A converter reference voltage input 0 3 to Vono 0 3 Input voltage Vn 0 3 to Vppo 0 3 Vie VPP pin during programming 0 3 to 10 5 Analog input voltage Van Analog input pin AVss 0 3 to AVner 0 3 Output voltage Vo 0 3 to Voo 0 3 lt lt lt lt lt Output current low Per pin 15 Total for all pins 100 Output current high Per pin 10 Total for all pins 40 Operating ambient temperature During normal operation 40 to 85 During flash memory programming 10 to 40 Storage temperature 65 to 125 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded User s Manual U12697EJAV1UD 569 CHAPTER 29 ELECTRICAL SPECIFICATIONS Operating Conditions e Operating ambient temperature Ta 40 to 85 C e Power supply voltage and clock cycle time See Figure 29 2 e Operating vol
278. anual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION Figure 24 6 Operations After Releasing STOP Mode 1 3 1 Interrupt after STOP mode Main routine MOV STBC byte STOP mode INT Oscillation stabilization time wait STOP mode release gt rp Interrupt servicing Main routine 2 Reset after STOP mode MOV STBC byte STOP mode RESET input gt Normal reset operations including oscillation stabilization time wait User s Manual U12697EJ4V1UD 483 CHAPTER 24 STANDBY FUNCTION Figure 24 6 Operations After Releasing STOP Mode 2 3 3 STOP mode during servicing routine of interrupt whose priority is higher than or equal to release source interrupt Main routine MOV STBC byte STOP mode INT Oscillation stabilization time wait STOP mode release STOP mode release source interrupt pending Execution of the pending interrupt 4 STOP mode during servicing routine of interrupt whose priority is lower than release source interrupt Main routine MOV STBO byte STOP mode INT Oscillation stabilization time wait STOP mode release Execution of the STOP mode BW release source s interruption 484 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Figure 24 6 Operations After Releasing STOP Mode 3 3 5 Conflict between STOP mode setting instruction and interrupt Main routine MOV
279. as those of port pins User s Manual U12697EJ4V1UD 575 CHAPTER 29 ELECTRICAL SPECIFICATIONS AC Characteristics TA 40 to 85 C AVpp 1 9 to 5 5 V Vss AVss 0 V 1 Read write operation 1 3 Parameter Cycle time Conditions 4 5 V lt Voo lt 5 5 V 80 2 7 V lt Voo lt 4 5 V 160 2 0 V lt Voo lt 2 7 V 320 1 9 V lt Voo lt 2 0 V 500 Address setup time to ASTBL Voo 5 0 V 10 0 5 a T 20 Voo 3 0 V 10 0 5 a T 40 Voo 2 0 V 5 0 5 a T 80 Address hold time from ASTBJ THSTLA Voo 5 0 V 10 0 5T 19 Voo 3 0 V 10 0 5T 24 Voo 2 0 V 5 0 5T 34 high level width Voo 5 0 V 10 0 5 a T 17 Voo 3 0 V 10 0 5 a T 40 Voo 2 0 V 5 0 5 a T 110 Address hold time from RDT Voo 5 0 V 10 0 5T 14 Voo 3 0 V 10 0 5T 14 Voo 2 0 V 5 0 5T 14 Delay time from address to RD Voo 5 0 V 10 1 a T 24 Voo 3 0 V 10 1 a T 35 Voo 2 0 V 5 1 a T 80 Address float time from RDJ Voo 5 0 V 10 0 Voo 3 0 V 10 0 Voo 2 0 V 5 0 Data input time from address Voo 5 0 V 10 2 5 a n T 37 Voo 3 0 V 10 2 5 a n T 52 Voo 2 0 V 5 2 5 120 Data input time from A
280. assigned special functions such as the mode and control registers of the on chip peripheral hardware and are mapped to the 256 byte area from 0FF00H to OFFFFHNete Note These are the addresses when the LOCATION OH instruction is executed They are FFFOOH to FFFFFH when the LOCATION OFH instruction is executed Caution In this area do not access an address that is not allocated by an SFR If erroneously accessed the PD784225 enters the deadlock state The deadlock state is released only by reset input Table 3 6 shows the list of special function registers SFRs The meanings of the items are described below After Reset This symbol indicates the on chip SFR In the NEC assembler RA78K4 this is a reserved word In the C compiler CC78K4 it can be used as an sfr variable by a pragma sfr directive Indicates whether the corresponding SFR can be read or written R W Can read write R Read only W Write only When the corresponding SFR is manipulated the appropriate bit manipulation unit is indicated An SFR that can be manipulated in 16 bits can be described in the sfrp operand If specified by an address an even address is described An SFR that can be manipulated in one bit can be described in bit manipulation instructions Indicates the state of each register when RESET is input User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE Table 3 6 Special Function Register SFR List 1 4 Bit Manipulation Unit A
281. at of Pull Up Resistor Option Register Address OFF30H OFF32H OFF33H OFF37H OFF3CH After reset OOH R W Symbol 9 PUO 0 0 PU05 PU04 PU03 PU02 PU01 PU00 PU2 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU3 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 PU7 0 0 0 0 0 PU72 PU71 PU70 PU12 PU127 PU126 PU125 PU124 PU123 PU122 PU121 PU120 Pxn pin pull up resistor specification x 0 n 0to5 x 2 3 12 n 0to7 x 7 n O0to2 No pull up resistor connection Pull up resistor connection Address OFF4EH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Port n pull up resistor specification n 4 to 6 No pull up resistor connection Pull up resistor connection Caution Connecting pull up resistors unnecessarily may increase the current consumption or latch up other devices so specify a mode whereby pull up resistors are only connected to the required parts If required and not required parts exist together externally connect pull up resistors to the required parts and set the mode that specifies not to connect on chip pull up resistors 132 User s Manual U12697EJ4V1UD CHAPTER 5 PORT FUNCTIONS 3 Port function control register 2 PF2 This register specifies N ch open drain for pins P25 and P27 PF2 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PF2 to 00H Caution Only the uPD784225Y Subseries incorporates PF2 When using the 2 bus mode serial interfac
282. atch timer Watch timer TMIC3 INTTM00 match signal generation of 16 bit timer counter 0 and capture compare register 00 CROO INTTMO1 match signal generation of 16 bit timer counter 0 and capture compare register 01 CRO1 Timer counter TMICOO TMICO1 INTTM1 match signal generation of 8 bit timer counter 1 Timer counter 1 INTTM2 match signal generation of 8 bit timer counter 2 Timer counter 2 INTAD A D converter conversion end A D converter INTTM5 match signal generation of 8 bit timer counter 5 Timer counter 5 INTTM6 match signal generation of 8 bit timer counter 6 Timer counter 6 INTWT watch timer overflow Note 4PD784225Y Subseries only Watch timer User s Manual U12697EJ4V1UD Context Switching Possible Macro Service Possible Macro Service Control Word Address OFEO6H Vector Table Address OFE08H OFEOAH OFEOCH OFEOEH OFE10H OFE12H OFE16H OFE18H OFE1AH OFE1CH OFE1EH OFE20H OFE22H OFE24H OFE26H OFE28H OFE2AH OFE2CH OFE2EH OFE30H OFE32H OFE38H 361 CHAPTER 22 INTERRUPT FUNCTIONS Remarks 1 The default priority is a fixed number and indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously 2 ASI
283. ate Generator Control Registers 1 and 2 BRGC1 BRGC2 264 16 6 Baud Rate Allowable Error Considering Sampling Errors When 0 272 16 7 Format of Asynchronous Serial Interface Transmit Receive Data 273 16 8 Asynchronous Serial Interface Transmit Completion Interrupt Request Timing 275 16 9 Asynchronous Serial Interface Receive Completion Interrupt Request Timing 276 16 10 Receive Error TIMIN as e e erede ep Lese ia Bl Bote verba 277 16 11 Block Diagram in 3 Wire Serial l O Mode a 280 16 12 Format of Serial Operation Mode Registers 1 and 2 CSIM1 51 2 281 16 13 Format of Serial Operation Mode Registers 1 and 2 CSIM1 CSIM2 282 16 14 Format of Serial Operation Mode Registers 1 and 2 CSIM1 CSIM2 283 16 15 3 Wire Serial V O Mode TIMING us tiere eite Lene tae cec 284 17 1 Block Diagram of Clocked Serial Interface in 3 Wire Serial I O 286 17 2 Format of Serial Operation Mode Register 0 CSIM0 a 287 17 3 Format of Serial Operation Mode Register 0
284. ation is possible with functions such as CO coverage Connect to a host machine via Ethernet or a dedicated bus An interface adapter sold separately is required for connection IE 70000 98 IF C Interface adapter Interface adapter required when a PC 9800 series except notebook type PC is used as the host machine for the IE 784000 R C bus supported IE 70000 PC IF C Interface adapter Interface adapter required when using an IBM PC AT compatible as the host machine ISA bus supported IE 78000 R SV3 Interface adapter Interface adapter and cable required when an EWS is used as the host machine for the IE 784000 R Connect to a board inside the IE 784000 R Note that 10Base 5 is supported as the Ethernet A commercial conversion adapter is required for other systems IE 784000 R EM Emulation board common to 78K IV Series IE 784225 NS EM1 Emulation board Board to emulate peripheral hardware specific to device IE 78K4 R EX2 Emulation probe conversion board Conversion board for 80 pin packages required when using the IE 784225 NS EM1 on IE 784000 R EP 78054GK R Emulation probe Probe to connect the in circuit emulator and the target system For 80 pin plastic TQFP fine pitch GK 9EU type TGK 080SDW Conversion adapter refer to Figure B 4 Conversion adapter to connect the EP 78054GK R and a target system board on which an 80 pin plastic TQFP fine pitch GK 9EU type can be mounted
285. ative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1 User s Manual U12697EJ4V1UD 5 Regional Information Some information contained in this document may vary from country to country Before using any NEC Electronics product in your application please contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country GLOBAL SUPPORT http www necel com en support support html NEC Electronics America Inc U S NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd Santa Clara California Duesseldorf Germany Hong Kong Tel 408 588 6000 Tel 0211 65030 Tel 2886 9318 800 366 9782 e Sucurs
286. atus enable register 460 23 6 4 External access status 1 460 29 65 EXA pinistatus Iri eachimode eiie et dec cus ol re dh ug eue nd 461 23 7 External Memory Connection Example u u u u uu 462 CHAPTER 24 STANDBY FUNCTION u 463 24 1 Configuration and Function U U u uu 463 24 2 Control RegiSt r III aa asas saneveseucedeateeveceeuvecterseasedvce 465 24 3 HALT I u EEE 470 24 3 1 Settings and operating states of HALT mode seen 470 243 2 Releasing HALT mode sedendo e dn Dre EE REP RES MERI 472 244 STOP ecc cC RD SY 480 User s Manual U12697EJAV1UD 17 24 4 1 Settings and operating states of STOP 480 24 4 2 Releasing STOP mode cir ates rh bd ee n ETE 482 24 5 IDLE U 488 24 5 1 Settings and operating states of IDLE 488 24 5 2 Releasing IDLE mode cmt rerit icr EAA RAE a 490 24 6 Check Items When Using STOP or IDLE
287. aximum of four program locations can be repaired with ROM correction First of all the channel is selected with bit 0 CORCHO and bit 1 CORCH 1 of the ROM correction control register CORC and the address is then set in the specified channel s address pointer when the address is written in CORAH and CORAL Figure 26 3 Format of ROM Correction Address Register CORAH CORAL 7 0 Address After reset R W CORAH FF89H 00 R W 15 0 Address After reset R W CORAL FF8AH 0000 R W 2 Comparator ROM correction address registers H and L CORAH CORAL normally compare the corrected address value with the fetch register value If any of the ROM correction control register CORC bits between bit 4 and bit 7 CORENO to 3 are 1 and the correct address matches the fetch address value a table reference instruction CALLT is issued from the ROM correction circuit User s Manual U12697EJAV1UD 509 CHAPTER 26 ROM CORRECTION 26 3 Control Register for ROM Correction ROM correction is controlled by the ROM correction control register CORC 1 ROM correction control register CORC The register that controls the issuance of the table reference instruction CALLT when the correct address set in ROM correction address registers H and L CORAH CORAL match the value of the fetch address This register is composed of a correction enable flag CORENO to 3 that enables or disables match detection with the comparator and four
288. back to the compare register Use of this automatic addition control eliminates the needto calculate the compare register setting value in the program each time Ring control With ring control predetermined output patterns are prepared for one cycle only and the one cycle data patterns are output repeatedly in order in ring form When ring control is used only the output patterns for one cycle need to be prepared allowing the size of the data ROM area to be reduced The macro service counter MSC is decremented each time a data transfer is performed With ring control too an interrupt request is generated when MSC 0 When controlling a stepper motor for example the output patterns will vary depending on the configuration of the stepper motor concerned and the phase excitation method single phase excitation two phase excitation etc but repeat patterns are used in all cases Examples of single phase excitation and 1 2 phase excitation of a 4 phase stepper motor are shown in Figures 22 34 and 22 35 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS Phase A Phase B Phase C Phase D Figure 22 34 Single Phase Excitation of 4 Phase Stepper Motor G Phase A Phase B Phase C Phase D 1 cycle 4 patterns Figure 22 35 1 2 Phase Excitation of 4 Phase Stepper Motor 1 cycle 8 patterns
289. be specified for the P50 to P57 pins in 1 bit units using the port 5 mode register When the P50 to P57 pins are used as input ports a pull up resistor can be connected in 8 bit units via bit 5 PUOS of the pull up resistor option register Port 5 can drive LEDs directly Port 5 supports the address bus function in the external memory expansion mode as an alternate function RESET input sets port 5 to the input mode Figure 5 11 shows a block diagram of port 5 118 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS Internal data bus Figure 5 11 Block Diagram of P50 to P57 WRPuo MIS D RDpuo Vppo X to 50 75 P50 A8 to 57 15 Output latch P50 to P57 RDps I O controller o 2 o o o s c c PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal to Bits 0 to of the memory expansion mode register MM User s Manual U12697EJ4V1UD 119 CHAPTER 5 PORT FUNCTIONS 5 2 7 Port 6 Port 6 is an 8 bit I O port with an output latch The input mode output mode can be specified for the P60 to P67 pins in 1 bit units using the port 6 mode register When pins P60 to P67 are used as input ports a pull up resistor can be connected in 8 bit units via bit 6 PUO6 of the pull up resistor
290. bel saddr2 FD20H to FDFFH FF00H to FF1FH Immediate data or label saddrp FD20H to FF1EH Immediate data or label when manipulating 16 bits saddrp1 FE00H to FEFFH Immediate data or label when manipulating 16 bits saddrp2 FD20H to FDFFH FF00H to FF1EH Immediate data or label when manipulating 16 bits saddrg FD20H to FEFDH Immediate data or label when manipulating 24 bits saddrg1 FE00H to FEFDH Immediate data or label when manipulating 24 bits saddrg2 FD20H to FDFFH Immediate data or label when manipulating 24 bits addr24 OH to FFFFFFH Immediate data or label addr20 OH to FFFFFH Immediate data or label addr16 OH to FFFFH Immediate data or label addr11 800H to FFFH Immediate data or label addr8 OFEOOH to OFEFFHN te Immediate data or label addr5 40H to 7EH Immediate data or label imm24 24 bit immediate data or label word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label n 3 bit immediate data locaddr OH or 0FH Note When 0H is set by the LOCATION instruction these addresses become the addresses shown here When OFH is set by the LOCATION instruction the values of the addresses shown here with F0000H added become the addresses User s Manual U12697EJAV1UD 521 CHAPTER 28 INSTRUCTION OPERATION 2 Operand column symbols Auto increment Auto decrement Immediate data 16 bit absolute address 24 bit 20 bit absolute address 8 bit relative address 16 bit r
291. ble IN OUT Pull up enable Output disable Input Deb Vppo IN OUT Vsso 77 enable Type 8 K Vppo Pull up enable De Vppo Data gt P ch N ch Output disable lt User s Manual U12697EJ4V1UD IN OUT Type 9 Comparator ci VREF threshold voltage Input enable 55 CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin I O Circuits 2 2 Type 10 Type 12 D Pull up enable IN OUT Output disable IN OUT Open drain Output Analog output disable voltage N ch Feedback cut off D gt IN OUT Open drain Output disable Pull up enable 56 User s Manual U12697EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 3 1 Memory Space The uPD784225 can access a 1 MB space The mapping of the internal data area differs depending on the LOCATION instruction special function registers and internal RAM The LOCATION instruction must always be executed alter releasing reset and cannot be used more than once The program after releasing reset must be as follows RSTVCT CSEG ATO DW RSTSTRT to INITSEG CSEG BASE RSTSTRT LOCATION 0H or LOCATION 0FH MOVG SP STKBGN User s Manual U12697EJ4V1UD 57 CHAPTER 3 CPU ARCHITECTURE 1 When the LOCATION 0
292. ble INTWDT watchdog timer Watchdog Not Not overflow timer possible possible 360 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS Type of Interrupt Request Maskable Default Priority Table 22 2 Interrupt Request Sources 2 2 Interrupt Request Generating Source INTWDTM watchdog timer overflow Generating Unit Watchdog timer Interrupt Control Register Name WDTIC INTPO pin input edge detection INTP1 pin input edge detection INTP3 pin input edge detection INTP2 pin input edge detection INTP4 pin input edge detection INTP5 pin input edge detection Edge detection PICO PIC1 PIC2 PIC3 PIC4 PIC5 INTIICO CSI0 12C bus transfer end Note INTCSIO CSIO 3 wire transfer end Clocked serial interface CSIICO INTSER1 ASI1 UART reception error INTSR1 ASI1 UART reception end INTCSI1 CSI1 3 wire transfer end INTST1 ASI1 UART transmission end Asynchronous serial interface clocked serial interface 1 SERIC1 SRIC1 STIC1 INTSER2 ASI2 UART reception error INTSR2 ASI2 UART reception end INTCSI2 CSI2 3 wire transfer end INTST2 ASI2 UART transmission end Asynchronous serial interface clocked serial interface 2 SERIC2 SRIC2 STIC2 INTTM3 reference time interval signal from w
293. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment commu
294. by bits 6 and 7 ES10 and ES11 is input to the TIO1 P36 pin the value of TMO is loaded to 16 bit capture compare register 00 CROO and an external interrupt request signal INTTM00 is set The rising falling or both rising and falling edges can be specified for the TI00 P35 TIO1 P36 pins The valid edge of TIOO P35 pin and TIO1 P36 pin is detected through sampling at the count clock cycle selected by prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected twice Therefore noise with a short pulse width can be eliminated Figure 8 13 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter a 16 bit timer mode control register 0 TMCO TMC03 02 01 OVFO Top o jo oj 1 0 o b Capture compare control register 0 CRCO Free running mode CRC02 CRC01 00 CR00 used as capture register Captures valid edge of TIO1 P36 pin to CROO CR01 used as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the pulse width measurement function For details refer to Figures 8 2 and 8 3 User s Manual U12697EJAV1UD 161 CHAPTER 8 16 BIT TIMER EVENT COUNTER Capture operation free running mode The following figure illustrates the operation of the capture register when the capture trigger is input Figure 8 14 CR01 Capture Operation with Rising Edge S
295. byte lt byte 1 if byte 0 then End if P V 1 then if overflow AXDE 7FFFFFFFH End if underflow AXDE 80000000H End TDE WHL lt TDE WHL AX TDE TDE 2 WHL WHL 2 C C 1 End if C 0 or CY 1 536 User s Manual U12697EJAV1UD CHAPTER 28 INSTRUCTION OPERATION 11 Increment and decrement instructions INC DEC INCW DECW INCG DECG Flag AC P V CY Mnemonic Operand Operation rer i saddr lt saddr 1 rer 1 saddr saddr 1 rp lt rp 1 saddrp saddrp 1 rp lt 1 lt saddrp 1 rg lt rg 1 rg rg 1 Flag Z AC P V CY Mnemonic Operand Operation Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract X lt A lt OOH if Az 0 X A lt FFH if Az 1 User s Manual U12697EJAV1UD 537 CHAPTER 28 INSTRUCTION OPERATION 13 Shift and rotate instructions ROR ROL RORC ROLC SHR SHL SHRW SHLW ROR4 ROL4 Mnemonic Operand Operation CY rz ro rmi rm x n CY rz tma rm x n CY lt ro rz lt CY rm1 lt rm x n CY lt ro lt CY rm lt rm x n CY ro rz lt 0 rm1 lt rm x n CY lt r7 0 rma rm x n CY lt rpis 0 rpm rpm x n
296. cascade connection mode TMC6 only TMC5 and TMC6 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC5 and TMC6 to 00H Figures 10 2 and 10 3 show the TMC5 format and TMC6 format respectively Figure 10 2 Format of 8 Bit Timer Mode Control Register 5 TMC5 Address OFF68H After reset OOH R W Symbol 6 5 4 3 2 1 toes mose o o o o o o TM5 count control Counting is disabled prescaler disabled after the counter is cleared to 0 Start counting TM5 operation mode selection Clear and start mode when TM5 and CR50 match PWM free running mode Caution When selecting the TM5 operation mode using TMC56 stop the timer operation in advance Remarks 1 In the PWM mode the PWM output is set to the inactive level by 5 0 2 If LVS5 and LVR5 are read after setting data 0 is read 204 User s Manual U12697EJAV1UD CHAPTER 10 8 BIT TIMERS 5 6 Figure 10 3 Format of 8 Bit Timer Mode Conirol Register 6 TMC6 Address OFF69H After reset OOH R W Symbol TMC6 6 5 4 3 3 tees we o 0 0 TCE6 TM6 count control Counting is disabled prescaler disabled after the counter is cleared to 0 Start counting TMC66 TM6 operation mode selection Clear and start mode when TM6 and CR60 match PWM free running mode TMC64 Discrete mode or cascade connection mode selection Discrete mode
297. causes are considered lt 1 gt The reception is not correct lt 2 gt The last data has been received When the receiving side sets the SDAO line low at the ninth clock the acknowledge signal becomes active normal reception response If bit 2 ACKEO 1 in 2 bus control register 0 IICCO the acknowledge signal automatic generation enable state is entered Bit 3 TRCO in 12 bus status register 0 IICSO is set by the data in the eighth bit following the 7 bit address information However set ACKEO 1 in the reception state when TRCO bit is 0 When the slave is receiving TRCO 0 the slave side receives multiple bytes and the next data is not required when ACKEO 0 the master side cannot start the next transfer Similarly if the next data is not needed when the master is receiving TRCO 0 set ACKEO 0 so that the ACK signal is not generated when you want to output a restart or stop condition This prevents the output of MSB data in the data on the SDAO line when the slave is transmitting transmission stopped Figure 18 11 Acknowledge Signal SCLO 1 2 3 4 5 6 7 8 9 oo A ime When receiving the base address the automatic output of the acknowledge is synchronized with the falling edge ofthe eighth clock of SCLO regardless of the ACKEO value When receiving at an address other than the base address the acknowledge signal is not output The output method of the acknowledge signal when receiving dat
298. ceived as the start bit the 5 bit counter is initialized and begins counting and data sampling is performed When following the start bit character data the parity bit and one stop bit are detected reception of one frame of data is completed When reception of one frame of data is completed the receive data in the shift register is transferred to receive shift register n RXBn and a receive completion interrupt INTSRn is generated Also even if an error occurs the receiving data for which the error occurred is transferred to RXBn If an error occurs when bit 1 ISRMn of ASIMn is cleared 0 INTSRn is generated refer to Figure 16 10 When bit ISRMn is set 1 INTSRn is not generated When bit RXEn is reset to 0 during a receive operation the receive operation is immediately stopped At this time the contents of RXBn and ASISn remain unchanged and INTSRn and INTSERn are not generated Remark n 1 2 Figure 16 9 Asynchronous Serial Interface Receive Completion Interrupt Request Timing 4 fS XX START INTSRn Caution Even when a receive error occurs be sure to read receive buffer register n RXBn If RXBn is not read an overrun error will occur during reception of the next data and the reception error status will continue indefinitely Remark n 1 2 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL e Receive error Errors that occur during reception are of three typ
299. ces must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to Vpp or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O se
300. citation Constant Velocity Operation FFFFH TM0 Count value OH A Count starts INTTP2 TOO Compare register CR10 TO At T1 At T2 At T3 At T4 At T5 At T6 At T7 At T8 At T9 At Buffer register D D6 RTBL or os Cos X X oo P120 P121 P122 P123 Note For the INTP2 high low level width refer to the data sheet User s Manual U12697EJAV1UD 427 CHAPTER 22 INTERRUPT FUNCTIONS 22 8 9 Counter mode 1 Operation MSC is decremented the number of times set in advance to the macro service counter MSC Because the number of times an interrupt occurs can be counted this function can be used as an event counter where the interrupt generation cycle is long Figure 22 40 Macro Service Data Transfer Processing Flow Counter Mode Macro service request acknowledgement Read contents of macro service mode register Identify channel type Others To other macro service processing Counter mode MSC is 16 bit width MSC 1 No Clear interrupt processing type bit ISM to 0 Clear interrupt request flag IF to 0 Vectored interrupt request is generated 428 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS 2 Configuration of macro service chann
301. ck Without Subsystem Clock Clock generator The oscillators for both the main system clock and subsystem clock continue operating The clock supply to both the CPU and peripherals is stopped CPU Operation disabled Port output latch Holds the state before the IDLE mode was set 16 bit timer event counter Operational when the watch timer output Operation disabled is selected as the count clock select fxr as the count clock of the watch timer 8 bit timer event counters 1 2 Operational only when TI1 and TI2 are selected as the count clocks 8 bit timers 5 and 6 Operational only when TI5 and TI6 are selected as the count clocks Watch timer Operational only when fxr is selected as Operation disabled the count clock Watchdog timer Operation disabled A D converter Operation disabled D A converter Operation enabled Real time output port Operational when an external trigger is used or TI1 and 2 are selected as the count clocks of 8 bit timer event counters 1 and 2 Serial interface Except 2 bus Operational only when an external input clock is selected as the serial clock mode bus mode Operation disabled External interrupt INTPO to INTP5 Operation enabled Bus lines during ADO to AD7 High impedance external expansion Ag to A19 High impedance ASTB High impedance WR RD High impedance WAIT Holds input status Caution Inthe IDLE mod
302. ck is operating 4 6 Changing System Clock and CPU Clock Settings The system clock and CPU clock can be switched by means of bits 4 to 6 CKO to CK2 of the standby control register STBC Whether the system is operating on the main system clock or the subsystem clock can be determined by the value of bit 0 CST of the clock status register PCS User s Manual U12697EJAV1UD 103 CHAPTER 4 CLOCK GENERATOR This section describes the procedure for switching between the system clock and the CPU clock Figure 4 10 System Clock and CPU Clock Switching Vpp RESET Interrupt request signal System clock fxx fxx fxr CPU clock Tue ee Mm Minimum Maximum speed Subsystem clock Highest speed Speed operation operation operation operation Wait 41 9 ms 12 5 MHz Internal reset operation The CPU is reset by setting the RESET signal to low level after power application After that when reset is released by setting the RESET signal to high level the main system clock starts oscillating At this time the oscillation stabilization time 2 9 fx is secured automatically After that the CPU starts operation at the minimum speed of the main system clock 1 280 ns 9 12 5 MHz operation After the lapse of a sufficient time for the Vpp voltage to increase to enable operation at maximum speed STBC and CC are rewritten and maximum speed operation is carried out Upon detection of a decrease in the Vpp voltage due to an in
303. converter DAMO and DAM1 are set by a 1 bit and 8 bit memory manipulation instruction RESET input sets DAM0 and DAM1 to 00H Figure 14 2 Format of D A Converter Mode Registers 0 and 1 DAMO DAM1 Address OFF86H OFF87H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 DAMn D A converter channel n operation mode 0 Normal mode 1 Real time output mode 0 Stop conversion Cautions 1 Whenthe D A converter is used set the alternate function port pins to the input mode and disconnect the pull up resistors 2 Always set bits 2 to 7 to 0 3 The output when the D A converter operation has stopped enters a high impedance state 4 The output triggers in the real time output mode are INTTM1 for channel 0 and INTTM2 for channel 1 Remark 0 1 250 User s Manual U12697EJ4V1UD CHAPTER 14 D A CONVERTER 14 4 Operation 1 lt 2 gt lt 3 gt lt 4 gt lt 5 gt Select the operation mode of channel 0 using DAMO of D A converter mode register 0 DAMO and the operation mode of channel 1 using DAM1 of D A converter mode register 1 DAM1 Set the data that corresponds to the analog voltages that are output to pins ANOO P130 and ANO1 P131 of D A conversion setting registers 0 and 1 DACSO DACS1 Set DACEO of DAMO and DACE1 of DAM1 to start D A conversion for channels 0 and 1 respectively After D A conversion in the normal mode the analog voltages at pins ANOO P130 and ANO1 P131 are immediately output
304. ct the subsystem clock to operate the system with low current consumption 30 5 us 32 768 kHz operation With the subsystem clock selected main system clock oscillation can be stopped using STBC The HALT mode can be used However the STOP mode cannot be used Subsystem clock oscillation cannot be stopped The main system clock is divided and supplied to the peripheral hardware The subsystem clock is supplied to the 16 bit timer event counter the watch timer and clock output functions only Thus the 16 bit timer event counter when watch timer output is selected for the count clock during operation with the subsystem clock the watch function and the clock output function can also be continued in the standby state However since all other peripheral hardware operates with the main system clock the peripheral hardware except external input clock operation also stops if the main system clock is stopped User s Manual U12697EJAV1UD 101 CHAPTER 4 CLOCK GENERATOR 4 5 1 Main system clock operations During operation with the main system clock with bit 6 CK2 of the standby control register STBC set to 0 the following operations are carried out a Because the operation guaranteed instruction execution speed depends on the power supply voltage the instruction execution time can be changed by setting bits 4 to 6 CKO to CK2 of STBC b If bit 2 of STBC is set to 1 during operation with the main system clock the m
305. ction Port function 3 2 1 0 m ve TxD1 P21 TxD2 P71 pin function Port function UART mode Receive only Serial function Port function UART mode Transmit only Port function Serial function UART mode Transmit Receive No parity Serial function Serial function Always add 0 parity during transmission Do not perform parity check during reception parity error not generated Odd parity Even parity Character length specification 7 bits 8 bits Transmit data stop bit length specification Receive completion interrupt control at error occurrence Generate receive completion interrupt when error occurs Note sure to write 0 to bit 0 Do not generate receive completion interrupt when error occurs Caution Switch the operation mode after stopping serial transmission and reception Remark 1 2 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL b Asynchronous serial interface status registers 1 and 2 ASIS1 ASIS2 ASIS1 and ASIS2 can be read by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIS1 and ASIS 2 to OOH Address OFF72H OFF73H After reset 00H R Symbol 7 6 5 4 3 2 e 0 Parity error flag Parity error not generated Parity error generated when parity of transmit data does not match Framing error flag Framing error not ge
306. ction this table is referenced and the base area address written in the table is branched to as the subroutine Since a CALLT instruction is one byte many subroutine call descriptions in the program can be CALLT instructions so the object size of the program can be reduced Since a maximum of 32 subroutine entry addresses can be described in the table they should be registered in order from the most frequently described When not used as the CALLT instruction table the area can be used as normal program memory or data memory 3 3 3 CALLF instruction entry area The area from 00800H to 00FFFH can be for direct subroutine calls in the 2 byte call instruction CALLF Since a CALLF instruction is a 2 byte call instruction compared to when using the CALL instruction 3 bytes or 4 bytes of a direct subroutine call the object size can be reduced When you want to achieve high speed describing direct subroutines in this area is effective If you want to decrease the object size an unconditional branch BR is described in this area and the actual subroutine is placed outside of this area When a subroutine is called from five or more locations reducing the object size is attempted In this case since only a 4 byte location for the BR instruction is used in the CALLF entry area the object size of many subroutines can be reduced 64 User s Manual U12697EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 3 4 Internal Data Area The internal data area consi
307. ction is used An internal ROM fetch is a high speed fetch fetch in two system clocks in 2 byte units If an instruction execution cycle similar to the external ROM fetch is selected waits are inserted by the wait function However when a high speed fetch is used waits cannot be inserted for the internal ROM Note that external waits must not be set for the internal ROM area If an external wait is set for the internal ROM area the CPU enters a deadlock state The deadlock state is only released by a reset input RESET input causes an instruction execution cycle similar to the external ROM fetch cycle User s Manual U12697EJAV1UD 61 CHAPTER 3 CPU ARCHITECTURE 3 3 Base Area The area from 0 to FFFFH becomes the base area The base area is used for the following Reset entry address Interrupt entry address Entry address for CALLT instruction 16 bit immediate addressing mode instruction address addressing 16 bit direct addressing mode 16 bit register addressing mode instruction address addressing 16 bit register indirect addressing mode Short direct 16 bit memory indirect addressing mode This base area is allocated in the vector table area CALLT instruction table area and CALLF instruction entry area When the LOCATION OH instruction is executed the internal data area is placed in the base area Be aware that the program is not fetched from the internal high speed RAM area and special function regist
308. ctions as a loop counter and can be used by the DBNZ instruction This register can store the offset in indexed addressing and based indexed addressing This register is used as the data pointer in a MACW or MACSW instruction C R2 This register functions as a loop counter and can be used by the DBNZ instruction This register can store the offset in based indexed addressing This register is used as the counter in string and SACW instructions This register is used as the data pointer in a MACW or MACSW instruction RP2 When context switching is used this register saves the lower 16 bits of the program counter PC RP3 Whencontext switching is used this register saves the higher 4 bits of the program counter PC and the program status word PSW except bits O to 3 in PSWH User s Manual U12697EJAV1UD 81 CHAPTER 3 CPU ARCHITECTURE 82 VVP RG4 This register functions as a pointer and specifies the base address in register indirect addressing based addressing and based indirect addressing UUP RG5 This register functions as a user stack pointer and implements another stack separate from the system stack by the PUSHU and POPU instructions Thisregisterfunctions as a pointer and acts as the register that specifies the base address during register indirect addressing and based addressing DE RP6 HL RP7 This register stores the offset during indexed addressing and based indexed
309. curs on match between TMO and CR00 occurs b One shot pulse output with external trigger If the external trigger is generated while the one shot pulse is being output the counter is cleared and restarted and the one shot pulse is output again 9 Operation of OVFO flag The OVFO flag is set to 1 in the following case Select mode in which 16 bit timer event counter is cleared and started on a match between TMO and CROO Count pulse CR00 TM0 OVF0 INTTM00 178 Set CR00 to FFFFH When TMO counts up from FFFFH to 0000H Figure 8 32 Operation Timing of OVF0 Flag FFFFH FFFEH FFFFH 0000H 0001H User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 10 Conflicting operations lt 1 gt Conflict between the read period of the 16 bit capture compare registers CROO and CR01 and the capture trigger input CROO and 01 used as capture registers The capture trigger input has priority The read data of CROO and CRO1 is undefined 2 Match timing conflict between the write the period of the 16 bit capture compare registers CROO and CRO1 and 16 bit timer counter 0 TMO CROO and CR01 are used as compare registers A match discrimination is not normally performed Do not perform write to CR00 and CR01 around the match timing User s Manual U12697EJAV1UD 179 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 1 Functions 1 2 8 bit timer event counters 1 and 2 TM1
310. d 4 CALLT routine branch When matched with address pointer 0 CALLT table 0078H When matched with address pointer 1 CALLT table 007AH When matched with address pointer 2 CALLT table 007CH When matched with address pointer 3 CALLT table 007EH 5 Substitute instruction execution 6 Addition of 3 to the stack pointer SP 7 Restoration to any addresses with the branch instruction BR User s Manual U12697EJAV1UD 511 CHAPTER 26 ROM CORRECTION 26 5 Conditions for Executing ROM Correction In order to use the ROM correction function it is necessary for the external environment and program to satisfy the following conditions 1 External environment Must be connected externally to an inactive memory and be configured to read that data 2 Target program The data setting instruction for CORC CORAH and CORAL must be previously annotated in the target program program stored in the ROM The setting data the items written in lower case in the setting example below must be read from the external inactive memory and the correct number of required correction pointers must be set Example of four pointer settings MOV CORC 00H Specified channel 0 MOVW CORAL datal Sets the channel 0 match address MOV CORAH ch0_datah Sets the channel 0 match address MOV CORC 01H Specified channel 1 MOVW CORAL ch1_datal Sets the channel 1 match address MOV CORAH Zch1 datah Sets the channe
311. d During Interrupt eadem Avnet ei 388 22 15 Examples of Servicing of Simultaneously Generated Interrupt Requests 391 22 16 Differences in Level Interrupt Acknowledgment According to IMC Register Setting 392 22 17 Differences Between Vectored Interrupt and Macro Service Processing 393 22 18 Macro Service Processing Sequence esceeeceeeneeseeeceeeeseeeceaeeeseeseaeeeseeteaeeseeseaeeseaeseaeetsaeeneeteaees 396 22 19 Operation at End of Macro Service When VCIE 0 nuqa nennen nennen 398 22 20 Operation at End of Macro Service When VCIE 1 02 0 4 1 1 0 0 0 399 22 21 Format of Macro Service Control Word 401 22 22 Format of Macro Service Mode Register u 402 22 23 Macro Service Data Transfer Processing Flow Type 405 22 24 A Macro Service Channel essere nennen teretes etse reset 407 22 25 Asynchronous Serial RECeption u u uuu unan nennen nennen neret 408 22 26 Macro Service Data Transfer Processing Flow 410 22 27 B Macro Service Channel esses ener ii E nne 411 22 28 Parallel Data Input Synchronized with External Interrupts
312. d circuit Sampling device mi Conversion time 240 User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER 13 6 Cautions 1 2 3 Current consumption in standby mode The A D converter operation is stopped in the standby mode Atthis time the current consumption can be reduced by setting bit 7 ADCS of the A D converter mode register ADM to 0 or by stopping the reference voltage circuit bit 0 of ADM ADCE 0 The method to reduce the current consumption in the standby mode is shown in Figure 13 14 Figure 13 14 Method to Reduce Current Consumption in Standby Mode AVop ADCS P ch T Series resistor string ADCE AVss Q Reference voltage circuit ANIO to ANI7 input range Use the ANIO to ANI7 input voltages within the rated voltage range Inputting a voltage equal to or greater than AVpp or equal to or smaller than AVss even if within the absolute maximum rated range will cause the channel s conversion values to become undefined or may affect the conversion values of other channels Conflicting operations 1 Conflict between A D conversion result register ADCR write and read of ADCR by instruction at conversion end The read operation to ADCR is prioritized After the read operation a new conversion result is written to ADCR 2 Conflict between ADCR write and external trigger signal input at conversion end External trigger signals cannot be received
313. d in 1 bit units For input mode pins use of on chip pull up resistors can be specified for all pins by a software setting LEDs can be driven directly Port 6 P6 8 bit I O port Input output can be specified in 1 bit units For input mode pins use of on chip pull up resistors can be specified for all pins by a software setting ASTB RxD2 SI2 Port 7 P7 3 bit I O port 2 502 Input output specified 1 bit units Regardless of whether the input or output mode is specified use of P72 ASCK2 SCK2 an on chip pull up resistor can be specified by a software setting in 1 bit units P120 to P127 RTP0 to RTP7 Port 12 P12 8 bit I O port Input output can be specified in 1 bit units Regardless of whether the input or output mode is specified use of an on chip pull up resistor can be specified by a software setting in 1 bit units P130 P131 ANOO ANO1 Port 13 P13 2 bit I O port Input output can be specified in 1 bit units 44 User s Manual U12697EJ4V1UD CHAPTER 2 PIN FUNCTIONS 2 Non port pins 1 2 Alternate Function Function TIOO TIO1 P35 External count clock input to 16 bit timer counter P36 Capture trigger signal input to capture compare register 00 P33 External count clock input to 8 bit timer counter 1 P34 External count clock input to 8 bit timer counter 2 T T TO TO TO Output P30 16 bit
314. d with using this product Be sure to read the cautions in the text of each chapter and summarized at the end of each chapter How to Read This Manual It is assumed that the readers of this manual have general knowledge about electrical engineering logic circuits and microcontrollers If there are no particular differences in the function The uPD784225 in the uPD784225 Subseries is described as the representative mask ROM version and the uPD78F4225 is described as the representative flash memory version If there are differences in the function Each product name is presented and described separately Since uPD784225 Subseries products are described as representative even this case for information on the operation of uPD784225Y Subseries products read the sections on the uPD784224Y 784225Y and 78F4225Y instead of the uPD784224 784225 and 78F4225 Tounderstand the overall functions Read in the order of the contents To debug when the operation is unusual Since the cautions are summarized at the end of each chapter see the cautions associated with the function For detailed explanations of registers whose names are known See APPENDIX D REGISTER INDEX User s Manual U12697EJAV1UD For detailed explanations of the instruction functions Refer to the other manual 78K IV Series User s Manual Instruction U10905E For explanations of the application examples of the functions Refer to t
315. ddition acknowledgment enabling disabling can be specified for all maskable interrupts by means of the IE flag in the program status word PSW In addition to normal vectored interrupts maskable interrupts can be acknowledged by context switching and macro servicing though some interrupts cannot use macro servicing refer to Table 22 2 The priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined default priority as shown in Table 22 2 Also multiservicing control can be performed with interrupt priorities divided into 4 levels However macro service requests are acknowledged without regard to priority control or the IE flag 362 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 2 Interrupt Servicing Modes There are three uPD784225 interrupt servicing modes as follows Vectored interrupt servicing Macro servicing Context switching 22 2 1 Vectored interrupt servicing When an interrupt is acknowledged the program counter PC and program status word PSW are automatically saved to the stack a branch is made to the address indicated by the data stored in the vector table and the interrupt service routine is executed 22 2 2 Macro servicing When an interrupt is acknowledged CPU execution is temporarily suspended and data transfer is performed by hardware Since macro servicing is performed without the intermediation of the CPU
316. ddressNete 1 Special Function Register SFR Name After Reset 1 Bit 8 Bits 16 Bits a 22 OFFOOH Port 0 OFFO1H Port1 OFFO2H Port 2 OFFO3H Port 3 OFFO4H Port 4 OFFO5H Port 5 OFFO6H Port 6 OFFO7H Port 7 OFFOCH Port 12 Z ee ER oA sS S 2 2 ay 2 2 2 2 2 OFFODH Port 13 OFF10H 16 bit timer counter 0 OFF11H OFF12H Capture compare register 00 OFF13H_ 16 bit timer event counter OFF14H Capture compare register 01 OFF15H_ 16 bit timer event counter OFF16H Capture compare control register 0 OFF18H 16 bit timer mode control register 0 OFF1AH 16 bit timer output control register 0 OFF1CH Prescaler mode register 0 OFF20H Port 0 mode register OFF22H Port 2 mode register OFF23H Port 3 mode register OFF24H Port 4 mode register OFF25H Port 5 mode register OFF26H Port 6 mode register OFF27H Port 7 mode register OFF2CH Port 12 mode register OFF2DH Port 13 mode register OFF30H Pull up resistor option register 0 OFF32H Pull up resistor option register 2 OFF33H Pull up resistor option register 3 eem esp Ss omms lasu e Se s s eee ios Be ee D pe Se Sp AL
317. ddrp A saddrp lt saddrp saddrg A saddrg saddrg VA A laddr16 A lt AV saddr16 A lladdr24 lt AV saddr24 laddr16 A addr16 addr16 VA Waddr24 A addr24 addr24 VA A mem lt AV mem mem A mem mem VA User s Manual U12697EJ4V1UD UU Ul Uj UJ U U U U UU U U U U uU u U 533 CHAPTER 28 INSTRUCTION OPERATION Mnemonic 534 Operand A byte Operation A byte 79 r byte r amp r byte saddr byte saddr v byte sfr byte sfr lt sfr V byte nr rerver A saddr2 lt AN saddr2 r saddr rer saddr saddr r lt saddr Vr r sfr rer X sfr sfr r sfr lt sfr r saddr saddr saddr lt saddr v saddr A saddrp A saddrp A saddrg A saddrg saddrp A saddrp saddrp A saddrg A saddrg saddrg A A laddr16 A lt Ax addr16 A lladdr24 A lt addr24 laddr16 A addr16 lt addr16 VA lladdr24 A addr24 lt addr24 A A mem AN mem A mem YA User s Manual U12697EJ4V1UD vI Tvi VI Vivi V V p V Ul V Vivi V CHAPTER 28 INSTRUC
318. ded to these values Only in the uPD784225Y Subseries Only in the uPD78F4225 and 78F4225Y User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE 3 10 Cautions 1 2 Program fetches are not possible from the internal high speed RAM space when executing the LOCATION 0H instruction 0FD00H to 0FEFFH when executing the LOCATION 0FH instruction FFD00H to FFEFFH Special function registers SFRs Do not access an address that is allocated to SFR in the area from 0FF00H to OFFFFHNete f mistakenly accessed the uPD784225 enters the deadlock state The deadlock state is released only by reset input Note These addresses are when the LOCATION OH instruction is executed They are FFFOOH to FFFFFH when the LOCATION OFH instruction is executed Stack pointer SP operation Although the entire 1 MB space can be accessed by stack addressing the stack cannot be guaranteed in the SFR area and the internal ROM area Stack pointer SP initialization The SP becomes undefined when RESET is input Even after a reset is cleared non maskable interrupts can be acknowledged Therefore the SP enters an undefined state immediately after clearing the reset When a non maskable interrupt request is generated unexpected operations sometimes occur To minimize these dangers always describe the following in the program immediately after clearing a reset RSTVCT CSEG DW RSTSTRT to INITSEG CSEG BASE RSTSTRT LOCATION 0H or LOCAT
319. des Operation stopped mode 3 wire serial I O mode 1 Operation stopped mode Since serial transfers are not performed in the operation stopped mode the power consumption can be decreased In the operation stopped mode the pins can be used as ordinary I O port pins a Register settings The operation stopped mode is set by serial operation mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Figure 17 3 Format of Serial Operation Mode Register 0 CSIMO Address OFF90H After reset OOH R W Symbol 6 5 4 3 2 1 0 s T s wes sas sor CSIMO CSIEO 0 oo SIOO operation enable disable setting Shift register operation Operation disabled Clear Serial counter Port Port functionNote Operation enabled Operation count enabled Serial function port function Note If CSIEO 0 5100 operation stopped state the pins connected 510 SOO and SCKO can function as ports User s Manual U12697EJ4V1UD 289 CHAPTER 17 3 WIRE SERIAL I O MODE 2 3 wire serial I O mode The 3 wire serial I O mode is effective when connecting peripheral I O or a display controller with an internal clocked serial interface Communication is over three lines the serial clock SCKO serial output 500 and serial input 610 a Register setting The 3 wire serial I O mode is set by in serial operation mode register
320. ding when an external clock is supplied User s Manual U12697EJ4V1UD 471 CHAPTER 24 STANDBY FUNCTION 24 3 2 Releasing HALT mode The HALT mode can be released by the following three sources Non maskable interrupt request only possible for NMI pin input Maskable interrupt request vectored interrupt context switching macro service RESET input Table 24 3 lists the release sources and describes the operation after release Operations following the release of the HALT mode are also shown in Figure 24 5 472 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Table 24 3 Releasing HALT Mode and Operation After Release ENote 2 State During Release Operation After Release RESET input _ Normal reset operation NMI pin input Not executing a non maskable Acknowledges interrupt requests interrupt service program Executing a low priority non maskable interrupt service program Executing the service program for The instruction following the MOV the same request STBC byte instruction is executed Executing a high priority non maskable The interrupt request that released interrupt service program the HALT mode is held pendingNete 3 Maskable Not executing an interrupt Acknowledges interrupt requests interrupt service program request except Executing a low priority maskable macro service interrupt service program request The PRSL bitNote 4 is cleared to 0 while executing an interrupt service
321. during A D conversion Therefore external trigger signals are not received during an ADCR write operation 3 Conflict between ADCR write and A D converter mode register ADM write or between A D converter input selection register ADIS write at conversion end The write operation to ADM or ADIS is prioritized A write to ADCR is not performed Moreover no interrupt signal INTAD is issued at conversion end User s Manual U12697EJAV1UD 241 CHAPTER 13 A D CONVERTER 4 S 6 242 Anti noise measures Attention must be paid to noise fed to AVpp and ANIO to ANI7 to preserve the 8 bit resolution The influence of noise grows proportionally to the output impedance of the analog input source Therefore it is recommended to connect C externally as shown in Figure 13 15 Figure 13 15 Handling of Analog Input Pin Vppo If there is the possibility that noise equal to or greater than AVpp 4 equal smaller than AVss enter clamp with a diode having a small Vr 0 3 or less AVpp ANI0 to ANI7 C 100 to 1000 pF i ANI0 P10 to ANI7 P17 The analog input pins ANIO to ANI7 can also be used as input port pins P10 to P17 Do not execute an input command that corresponds with port 1 during conversion if any of the ANIO to ANI7 pins have been selected for A D conversion as this would result in a lowered resolution Moreover if a digital pulse is applied to other analog input pins duri
322. e Note EXCO Bit 5 of 1 C bus status register 0 IICSO COIO Bit 4 of 2C bus status register 0 50 3 Since the processing after an interrupt request is generated differs depending on the data that follows the extended code this processing is performed by software For example when operation as a slave is not desired after an extended code is received enter the next communication wait state by setting bit 6 1 of 12 bus control register 0 IICCO Table 18 3 Definitions of Extended Code Bits Slave Address R W Bit Description General call address Start byte CBUS address Address reserved in the different bus format 10 bit slave address setting 18 5 12 Arbitration When multiple masters simultaneously output start conditions when STTO 1 occurs before STDO 1Note the master communicates while the clock is adjusted until the data differ This operation is called arbitration A master that failed arbitration sets the arbitration failed flag ALDO of 12C bus status register 0 IICSO at the timing of the failed arbitration The SCLO and SDAO lines enter the high impedance state and the bus is released Failed arbitration is detected when ALDO 1 by software atthe timing ofthe interrupt request generated next eighth or ninth clock stop condition detection etc At the timing for generating the interrupt request refer to 18 5 7 I C interrupt request INTIICO Note STDO Bit 1 in I
323. e make sure to specify N ch open drain for the P25 and P27 pins Figure 5 22 Format of Port Function Control Register 2 PF2 Address OFF42H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 ero o j ee o j o o j o o P2n pin N ch open drain specification n 5 7 Don t set N ch open drain Set N ch open drain User s Manual U12697EJAV1UD 133 CHAPTER 5 PORT FUNCTIONS 5 4 Operations Port operations differ depending on whether the input or output mode is set as shown below 5 4 1 Writing to I O port 1 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode A value is written to the output latch by a transfer instruction but since the output buffer is off the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instructions although a single bit is manipulated the port is accessed in 8 bit units Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 5 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer instruction The output
324. e UART 267 16 39 Standby mode operator uya hoi denials a weenie ees vend 278 16 4 3 Wire Serial Mode UU UU uu a Ta ainaani asenaan 279 16 4 1 vere fateris este addas eens aes 279 16 42 Control registers rrr sus ceni eio patti retro peas ginge Edo a vie sas RR cR YT eR EE Reg 281 164 sacs m chs uu u Susan EET 282 CHAPTER 17 3 WIRE SERIAL W O MODE u uuu u 285 WZ aininm 285 17 2 Configuration m 285 17 3 Control Beglsters rite eter ar E aa aaa 287 Qr eripe E 289 CHAPTER 18 BUS MODE uPD784225Y SUBSERIES 292 18 1 Function OVervie W mc 292 18 2 Configuratio meet 293 18 3 Control Beglsters L a a u Sima Sasu asss 296 18 4 FC Bus Mode F u etioh LUIS ua 307 Lr ME eese Er UE 307 18 5 PC Bus Definitions and Control Method l u u u 308 1 Start Condition k uu usupa He en uum R ski 308 1852 ccc
325. e only external interrupts INTPO to INTP5 and the watch timer interrupt INTWT can release the IDLE mode and be acknowledged as interrupt requests All other interrupt requests are held pending and acknowledged after the IDLE mode has been released through NMI input INTPO to INTP5 input or INTWT User s Manual U12697EJAV1UD 489 CHAPTER 24 STANDBY FUNCTION 24 5 2 Releasing IDLE mode The IDLE mode is released by NMI input INTP0 to INTP5 input the watch timer interrupt INTWT or RESET input An outlines of the release sources and operations following release are shown in Table 24 8 Operations following release of the IDLE mode are also shown in Figure 24 9 Release Source RESET input Table 24 8 Releasing IDLE Mode and Operation After Release MKNote 1 SMNote 2 ENote 3 State During Release Operation After Release Normal reset operation NMI pin input Not executing a non maskable interrupt service program Executing a low priority non maskable interrupt service program Acknowledges interrupt requests Executing the service program for the NMI pin input Executing a high priority non maskable interrupt service program Executes the instruction following the MOV STBC byte instruction The interrupt request that released the IDLE mode is held pendingNete 4 INTPO to INTP5 pin input watch timer interrupt Notes 1 Not executing an interrupt service program Executing a low
326. e 16 bit timer event counter can output a square wave with any frequency 6 One shot pulse output The 16 bit timer event counter can output a one shot pulse with any output pulse width User s Manual U12697EJ4V1UD 145 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 2 Configuration The 16 bit timer event counter includes the following hardware Table 8 1 Configuration of 16 Bit Timer Event Counter Configuration Timer counter 16 bits x 1 TM0 Register 16 bit capture compare register 16 bits x 2 CR00 CR01 Timer output 1 TO0 Control registers 16 bit timer mode control register 0 TMC0 Capture compare control register 0 CRC0 16 bit timer output control register 0 TOC0 Prescaler mode register 0 PRM0 Figure 8 1 Block Diagram of 16 Bit Timer Event Counter Internal bus Capture compare control register 0 CRC0 CRC02 CRC01 CRC00 00 Selector 16 bit capture compare 01 register 00 CROO Match 16 bit timer counter Output controller Noise die 16 bit capture compare register 01 01 gt INTTMO1 Selector 16 bit timer output control register 0 TOC0 sns O 16 bit timer mode control register 0 TMC0 Prescaler mode register 0 PRM0 Internal bus User s Manual U12697EJ4V1UD
327. e 22 30 Macro Service Data Transfer Processing Flow Type C 2 2 Ring control No Yes Ring counter 0 No Yes No Increment MPD Yes Subtract modulo register contents from data macro service pointer MPD and Add modulo register contents to data macro service pointer MPD and return pointer to return pointer to start address start address Load modulo register contents into ring counter MSC lt MSC 1 Yes Clear 0 interrupt service mode bit ISM Yes No End Clear 0 interrupt request flag IF Vectored interrupt request generation User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS 2 Macro service channel configuration There are two kinds of type C macro service channels as shown in Figure 22 31 The timer macro service pointer MPT mainly indicates the data buffer area in the 1 MB memory space to be transferred or added to the timer counter compare register The data macro service pointer MPD indicates the data buffer area in the 1 MB memory space to be transferred to the real time output port The modulo register MR specifies the number of repeat patterns when ring control is used The ring counter RC holds the step in the pattern when ring control is used When initialization is performed the same value as in the MR is normally set in this counter The macro service counter MSC is a 16 bit counter that specifies the nu
328. e 350 19 2 COnfIQUEGllOT uu ut S y 351 19 3 2 2 EI 351 CHAPTER 20 BUZZER OUTPUT FUNCTIONS 354 20 1 FUNCION pe 354 varese d 354 20 3 Control Hegisltets ua niece a kasukus eld ed esee da denne eda 355 CHAPTER 21 EDGE DETECTION FUNCTION 357 21 1 Control Registers ETIN 357 21 2 Edge Detection of POO to P05 Pins uu u u u u 358 CHAPTER 22 INTERRUPT FUNCTIONS 4 20 359 22 1 Interrupt Hequest SOURCES oec retinere u ren nien aane 360 22 1 14 SoftWare interr pte stet ae 362 22122 Operand error intert pie ticus entree 362 22 1 3 Non maskable Iriterr pts i cete Eri aa a ieri pes ee 362 22 1 4 Maskable Interr pls tats kuu ssspkusmashassqsqansshaqasapinsssahassaassasmassspasisqaqhasiqasapapditaqasaspas 362 22 2 Interrupt Servicing Modes netten tenu dune iain 363 22 2 1 Vectored interr pt servicing corriere irte treten ect dte ce e npa e Reb deir pne dan 363 22 2 2 Macro Servicing
329. e A D converter mode register ADM to O AVpp pin must always have the same voltage as the Voo If current is not supplied to the AVpp pin in the STOP mode not only does the current consumption increase but the reliability of the uPD784225 is negatively affected D A converter The D A converter consumes a constant current in the STOP and IDLE modes By clearing the DACEn n 0 1 bits in the D A converter mode registers DAMO DAM1 to 0 the output of ANOn n 0 1 has a high impedance and the current consumption can be decreased Do not apply an external voltage to the ANOn pins If an external voltage is applied not only is the current consumption increased but the uPD784225 may be destroyed or the reliability decreased User s Manual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION 24 7 Low Power Consumption Mode 24 7 1 Setting low power consumption modeNete When the low power consumption mode is entered set 70H in the standby control register STBC This setting switches the system clock from the main system clock to the subsystem clock Whether the system clock switched to the subsystem clock can be verified from the data read from the CST bit in the clock status register PCS refer to Figure 24 3 To check whether switching has ended set 74H in STBC to stop the oscillation of the main system clock Then switch to the backup power supply from the main power supply Note The low power consumption mode is a
330. e Interrupt Acknowledgment Operation Non maskable interrupts are acknowledged even in the interrupt disabled state Non maskable interrupts can be acknowledged alt all times except during execution of the service program for an identical non maskable interrupt or a non maskable interrupt of higher priority The relative priorities of non maskable interrupts are set by the WDT4 bit of the watchdog timer mode register WDM see 22 3 5 Watchdog timer mode register WDM Except in the cases described in 22 9 When Interrupt Requests and Macro Service Are Temporarily Held Pending a non maskable interrupt request is acknowledged immediately When a non maskable interrupt request is acknowledged the program status word PSW and program counter PC are saved in that order to the stack the IE flag is cleared 0 the in service priority register ISPR bit corresponding to the acknowledged non maskable interrupt is set 1 the vector table contents are loaded into the PC and a branch is performed The ISPR bit that is set 1 is the NMIS bit in the case of a non maskable interrupt due to edge input to the NMI pin and the WDTS bit in the case of watchdog timer overflow When the non maskable interrupt service program is executed non maskable interrupt requests of the same priority as the non maskable interrupt currently being executed and non maskable interrupts of lower priority than the non maskable interrupt currently being executed are held pending A
331. e Stabilization Time fox MHz C1 pf C2 pf MIN V MAX V MAX Tost ms CSTLS2M00G56 B0 CSTCC2 00MG0H6 CSTCRAMOO0G55 RO CSTS0400MG06 CSTCC4 00MGOH6 CSTCR6M00G53 RO CSTS0600MG03 CSTCC6 00MG CSTS0800MG03 CSTCC8 00MG CSTS1000MG03 CSTCC10 0MG CSA12 5MTZ CST12 5MTW CSTCV12 5MTJOCA Kyocera Corporation PBRC4 00HR PBRC4 00GR KBR 4 0MKC KBR 4 0MSB PBRC8 00HR PBRC8 00GR KBR 8 0MKC KBR 8 0MSB PBRC10 00BR A PBRC12 50BR A Caution FCR4 0MC5 FCR6 0MC5 FCR8 0MC5 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation Oscillation frequency precision is not guaranteed For applications requiring oscillation frequency precision the oscillation frequency must be adjusted on the implementation circuit For details please contact directly the manufacturer of the resonator you will use User s Manual U12697EJAV1UD 573 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics Ta 40 to 85 C Vpp AVpp 1 9 to 5 5 V Vss AVss 0 V 1 2 Parameter Conditions VPP supply voltage In normal operation 0 2Vpp Input voltage low Note 1 2 2 V lt Voo lt 5 5 V 0 3Vpp 1 9 V lt Voo lt 2 2 V 0 2Vpp P00 to P05 P20 P22 P33 2 2 V lt Voo lt 5 5 V P34 P70 P72 RESET 1 9 V lt Von lt 2 2 V 0 2Vpp 0 15 P10 to P17
332. e absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded 552 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Operating Conditions e Operating ambient temperature Ta 40 to 85 C e Power supply voltage and clock cycle time see Figure 29 1 e Operating voltage during subsystem clock operation Vpp 1 8 to 5 5 V Figure 29 1 Power Supply Voltage and Clock Cycle Time CPU Clock Frequency fcpu 10 000 8 000 500 400 Guaranteed 320 operation range 300 Clock cycle time tcvx ns 200 160 100 80 Supply voltage V Capacitance Ta 25 C Vpp Vss 0 V Parameter Conditions Input capacitance f 1 MHz Output capacitance Unmeasured pins returned to 0 V I O capacitance User s Manual U12697EJ4V1UD 553 CHAPTER 29 ELECTRICAL SPECIFICATIONS Main System Clock Oscillator Characteristics Ta 40 to 85 C Resonator Recommended Circuit Parameter Conditions Ceramic Oscillation 4 5 V lt Voo lt 5 5 V resonator frequency fx or crystal 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V resonator 1 8 V lt Voo lt 2 0 V 4
333. e eighth clock 2 When the address that received SVAO does not match INTIICO and wait are not generated Remark The numbers in the table indicate the number of clocks of the serial clock In addition the interrupt request and wait control are both synchronized with the falling edge of the serial clock 1 When transmitting and receiving an address When the slave is operating The interrupt and wait timing are determined regardless of the WTIMO bit When the master is operating The interrupt and wait timing are generated by the falling edge of the ninth clock regardless of the WTIMO bit 2 When receiving data When the master and slave are operating The interrupt and wait timing are set by the WTIMO bit 3 When transmitting data When the master and slave are operating The interrupt and wait timing are set by the WTIMO bit 4 Releasing a wait The following four methods release a wait WRELO 1 in 2 bus control register 0 IICCO Writing to serial shift register O IICO Setting the start condition STTO 1 in IICCO Setting the stop condition SPTO 1 in IICCO When an eight clock wait is selected WTIMO 0 the output level of ACK must be determined before releasing the wait 5 Stop condition detection INTIICO is generated when the stop condition is detected 332 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 9 Address match detection In the I2C b
334. e in 1 bit units Port 3 P30 to P37 Input or output can be specified in 1 bit units Specifiable in 1 bit units Port 4 P40 to P47 Input or output can be specified in 1 bit units Can drive LEDs directly Specifiable individually for each port Port 5 P50 to P57 Input or output can be specified in 1 bit units Can drive LEDs directly Specifiable individually for each port Port 6 P60 to P67 Input or output can be specified in 1 bit units Specifiable individually for each port Port 7 P70 to P72 Input or output can be specified in 1 bit units Specifiable in 1 bit units Port 12 P120 to P127 Input or output can be specified in 1 bit units Specifiable in 1 bit units Port 13 106 P130 P131 Input or output can be specified in 1 bit units User s Manual U12697EJ4V1UD CHAPTER 5 PORT FUNCTIONS 5 2 Port Configuration The ports include the following hardware Table 5 2 Port Configuration Item Configuration Control registers Port mode register PMm m 0 2 to 7 12 13 Pull up resistor option register PUO PUm m 0 2 3 7 12 Ports Total 67 input 8 I O 59 Pull up resistors Total 57 software control 5 2 1 Port 0 Port 0 is a 6 bit I O port with an output latch The input mode output mode can be specified for the POO to P05 pins in 1 bit units using the port 0 mode register A pull up resistor can also
335. e instruction and bit manipulation instruction excluding BT and BF to interrupt control registersNote MK1 IMC ISPR and SNMI PSW bit manipulation instruction Excluding the BT PSWL bit addr20 instruction BF PSWL bit addr20 instruction BT PSWH bit addr20 instruction BF PSWH bit addr20 instruction SET1 CY instruction NOT1 CY instruction and CLR1 CY instruction Note Interrupt control registers WDTIC PICO PIC1 PIC2 PICS PIC4 PIC5 CSIICO SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMICOO TMICO1 TMIC1 TMIC2 ADIC TMIC5 TMIC6 WTIC Caution If problems are caused by a long pending period for interrupts and macro servicing when the corresponding instructions are used in succession a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an NOP instruction etc in the series of instructions 430 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 10 Instructions Whose Execution Is Temporarily Suspended by Interrupt or Macro Service Execution ofthe following instructions istemporarily suspended by an acknowledgeable interrupt request or macro service request and the interrupt or macro service request is acknowledged The suspended instruction is resumed after completion of the interrupt service program or macro service processing Temporarily suspended instructions MOVM XCHM MOVBK XCHBK CMPME CMPMNE CMPMC CMPMNC CMPBKE CMPBKNE
336. e output from the pins which may cause malfunction Remark 1 2 Figure 16 8 Asynchronous Serial Interface Transmit Completion Interrupt Request Timing We X TA START INTSTn a Stop bit length 1 START INTSTn b Stop bit length 2 Caution Do not write to asynchronous serial interface mode register n ASIMn during transmis sion If you write to the ASIMn register during transmission further transmission operations may become impossible in this case input RESET to return to normal Whether transmission is in progress or not can be judged by software using the transmit completion interrupt INTSTn or the interrupt request flag STIFn set by INTSTn Remark n 1 2 User s Manual U12697EJAV1UD 275 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 d Reception 276 When the RXEn bit of asynchronous serial interface mode register n ASIMn is set to 1 reception is enabled and sampling of the RxDn pin input is performed Sampling of the RxDn pin input is performed by the serial clock set by baud rate generator control register n BRGCn The 5 bit counter for the baud rate generator will begin counting when the RxDn pin input reaches low level and the start timing signal for data sampling will be output when half of the time set for the baud rate has passed If the result of re sampling the RxDn pin input with this start timing signal is low level the RxDn pin input is per
337. e set only during the wait period after ACKEO 0 is set and the fact that reception is completed is passed to the slave Master transmission During the ACKO acknowledge period the start condition may not be normally gener ated Set STTO during the wait period Setting synchronized to SPTO is prohibited Resetting between setting STTO and the generation of the clear condition is prohibited Clear condition STTO 0 Set condition STTO 1 Cleared by an instruction Setbyan instruction IICEO 0 LRELO 1 When arbitration failed Clear after generating the start condition in the master When RESET is input User s Manual U12697EJAV1UD 299 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 3 Format of I2C Bus Control Register 0 IICC0 4 4 SPTO Stop condition trigger The stop condition is not generated The stop condition is generated ends the transfer as the master After the SDAO line goes low the SCLO line goes high or wait until SCLO goes high Then the standard time is guaranteed the SDAO line is changed from low to high and the stop condition is generated Cautions on set timing Master reception Setting is prohibited during transfer SPTO can be set only during the wait period after ACK0 0 is set and the fact that reception is completed is passed to the slave Master transmission During the ACKO acknowledge period the start condition may not be normally generat
338. ecuting a low priority non maskable interrupt service program Acknowledges interrupt requests Executing the service program for the NMI pin input Executing a high priority non maskable interrupt service program The instruction following the MOV STBC byte instruction is executed The interrupt request that released the STOP mode is held pendingNote 4 INTPO to INTP5 pin input watch timer interrupt Not executing an interrupt Service program Executing a low priority maskable interrupt service program The PRSL bitNete 5 is cleared to 0 while an interrupt service program at priority level 3 is being executed Acknowledges interrupt requests Executing a maskable interrupt service program with the same priority This excludes executing an interrupt service program in priority level 3 when the PRSL bitNote 5 is cleared to 0 Executing a high priority interrupt service program The instruction following MOV STBC byte instruction is executed The interrupt request that released the STOP mode is held pendingNete 4 Notes 1 Interrupt mask bit in each interrupt request source 2 Macro service enable flag that is in each interrupt request source Interrupt enable flag in the program status word PSW Holds the STOP mode 3 4 The pending interrupt request is acknowledged when acknowledgement is possible 5 Bit in the interrupt mode control register IMC 482 User s M
339. ed Set SPTO during the wait period Setting synchronized to STTO is prohibited Resetting between setting SPTO and the generation of the clear condition is prohibited Set SPTO only by the master ete When WTIMO 0 is set be aware that if SPTO is set during the wait period after the eighth clock is output the stop condition is generated during the high level of the ninth clock after the wait is released When the ninth clock must be output set WTIMO 0 1 during the wait period after the eighth clock is output and set SPTO during the wait period after the ninth clock is output Clear condition SPTO 0 Set condition SPTO 1 Cleared by an instruction Setbyan instruction IICEO 0 LRELO 0 When arbitration failed Automatically clear after the stop condition is detected When RESET is input Note Set SPTO only by the master However SPTO must be set once and the stop condition generated to operate the master by the time the first stop condition is detected after operation is enabled For details refer to 18 5 15 Additional warnings Cautions 1 When bit 3 TRCO 1 in I C bus status register 0 IICSO after WRELO is set at the ninth clock and the wait is released TRCO is cleared and the SDAO line becomes high impedance 2 SPTO and STTO are 0 when read after data has been set Remark STDO Bit 1 in 12 bus status register 0 IICSO ACKDO Bit 2 in 12 bus status register 0 IICSO TRCO Bit 3 in I C bus stat
340. ed ports 4 to 6 are used Ports 4to 6 control address data and read write strobes and wait and address strobes etc Table 23 1 Pin Functions in External Memory Expansion Mode Pin Functions When External Device Connected Alternate Functions Name Function ADO to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Middle address bus P50 to P57 A16 to A19 High address bus P60 to P63 RD Read strobe P64 WR Write strobe P65 Wait signal P66 Address strobe P67 Table 23 2 Pin States in Ports 4 to 6 in External Memory Expansion Mode External Expansion Mode Single chip mode Port Port Port 256 KB expansion mode Address data Address Address RD WR WAIT ASTB 1 MB expansion mode Address data Address Address RD WR WAIT ASTB Caution When the external wait function is not used the WAIT pin can be used as the port in all of the modes User s Manual U12697EJAV1UD 437 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 2 Control Registers 1 Memory expansion mode register MM MMis 8 bit register that controls the external expanded memory sets the number of address waits and controls the internal fetch cycle MM can be read or written by a 1 bit or 8 bit memory manipulation instruction Figure 23 1 shows the MM format RESET input sets MM to 20H Figure 23 1 Format of Memory Expansion Mode Register MM Address OFFC4H After reset 20H R W Symbol 7
341. eeeeeeeeneneneen nennen 338 18 16 Communication Reservation Acceptance Timing 338 18 17 Communication Reservation Procedure u 339 18 18 Master Operation PFPOCed uten 341 18 19 Slave Operating ProGedUre u u u nqa E EE abususta qia 342 18 20 Master Slave Communication Example When Master and Slave Select 9 Clock Wait 344 18 21 Slave Master Communication Example When Master and Slave Select 9 Clock Wait 347 19 1 Remote Control Output Application 350 19 2 Block Diagram of Clock Output FUNCHION quya veo e vua 351 19 3 Format of Clock Output Control Register 352 19 4 Format of Port 2 Mode Register PMD uu eene eorr aei et 353 20 1 Block Diagram of Buzzer Output Function u 354 20 2 Format of Clock Output Control Register 355 20 3 Format of Port 2 Mode Register 2 48 356 21 1 Format of External Interrupt Rising Edge Enable Register 0 EGPO and External Interrupt Falling Edge Enable Register O EGNO Lu eerie dri teet SE sc kn FR ERE aan 357
342. el The macro service channel consists of only a 16 bit macro service counter MSC The lower 8 bits ofthe address of the MSC are written to the channel pointer Figure 22 41 Counter Mode 7 0 Macro service Higher 8 bytes Higher addresses Macro service channel counter MSC ower8 bytes Ba Channel pointer Mode register Lower addresses 3 Example of using counter mode Here is an example of counting the number of edges input to external interrupt pin INTP5 Figure 22 42 Counting Number of Edges Internal RAM OFE7EH Channel pointer 7EH Counter mode Mode register 00H Interrupt request is generated when MSC 0 Internal bus INTP5 P05 INTP5 macro service request Remark The internal RAM address in the figure above is the value when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed add OFOOOOH to this value User s Manual U12697EJAV1UD 429 CHAPTER 22 INTERRUPT FUNCTIONS 22 9 When Interrupt Requests and Macro Service Are Temporarily Held Pending When the following instructions are executed interrupt acknowledgment and macro service processing are held pending for 8 system clock cycles However software interrupts are not held pending El DI BRK BRKCS RETCS RETCSB addr16 RETI RETB LOCATION 0H or LOCATION 0FH POP PSW POPU post MOV PSWL A MOV PSWL byte MOVG SP imm 24 Writ
343. elative address Bit reversal Indirect addressing 24 bit indirect addressing Not changed Clear to 0 Set to 1 Set or clear based on the result Operate with the P V flag as the parity flag Operate with the P V flag as the overflow flag 4 Operation column symbols jdisp8 Two s complement data 8 bits of the relative address distance between the head address of the next instruction and the branch address jdisp16 Two s complement data 16 bits of the relative address distance between the head address of the next instruction and the branch address PCuw PC bits 16 to 19 bits 0 to 15 522 User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION 5 Number of bytes in instruction that has mem in operand Register Indirect Addressing Based Addressing Indexed Addressing Based Indexed Addressing Note This becomes a 1 byte instruction only when TDE WHL TDE TDE WHL or WHL is described in mem in the MOV instruction 6 Number of bytes in instruction that has saddr saddrp r or rp in operand The number of bytes in an instruction that has saddr saddrp r or rp in the operand is described in two parts divided by a slash The following table shows the number of bytes in each part Description No of Bytes on Left Side No of Bytes on Right Side saddr2 saddr1 saddrp2 saddrp1 r2 rp2 7 Descriptions of instructions with mem in operand a
344. em clock oscillator when the main system clock stops To minimize leakage current set bit 7 SBK of the standby control register STBC to 1 In this case also connect the XT1 and XT2 pins as described above 100 User s Manual U12697EJAV1UD CHAPTER 4 CLOCK GENERATOR 4 5 Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operation mode including the standby mode Main system clock fxx Subsystem clock fxr CPU clock Clock to peripheral hardware The following clock generator functions and operations are determined using the standby control register STBC and the oscillation mode selection register CC a Upon generation of the RESET signal the lowest speed mode of the main system clock 1 280 ns 9 12 5 MHz operation is selected STBC 30H CC 00H Main system clock oscillation stops while a low level is being applied to the RESET pin With the main system clock selected one of six CPU clock types 80 ns 160 ns 320 ns 640 ns 1 280 ns 12 5 MHz operation can be selected by setting STBC and CC With the main system clock selected two standby modes the STOP mode and the HALT mode are available To decrease current consumption in the STOP mode the subsystem clock feedback resistor can be disconnected to stop the subsystem clock by using bit 7 SBK of STBC when the system does not use the subsystem clock STBC can be used to sele
345. emarks 1 Figures in parentheses apply to operation at fxx 12 5 MHz 2 x Don t care User s Manual U12697EJAV1UD 469 CHAPTER 24 STANDBY FUNCTION 24 3 HALT Mode 24 3 1 Settings and operating states of HALT mode The HALT mode is set by setting the HLT bit in the standby control register STBC to 1 STBC can be written in with 8 bit data by a special instruction Therefore the HALT mode is specified by the MOV STBC byte instruction When interrupts are enabled IE flag in PSW is set to 1 specify three NOP instructions after the HALT mode setting instruction after the HALT mode is released If this is not done after the HALT mode is released multiple instructions may execute before interrupts are acknowledged Inserting NOP instructions may change the order relationship between the interrupt servicing and instruction execution so to prevent problems caused by changes in the execution order be sure to take the measures described earlier The system clock when setting the HALT mode can be set to either the main system clock or the subsystem clock The operating states in the HALT mode are described next 470 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Table 24 2 Operating States in HALT Mode HALT Mode Setting HALT Mode Setting During Main System Clock Operation HALT Mode Setting During Subsystem Clock Operation No subsystem clock Subsystem clock When the main system When the main system Note
346. ended code Example SVAO does not match Al A2 AS A1 IICSO 1000x110B A2 50 01000110B Example Read ALDO during interrupt servicing IICSO 00000001B Remarks Always generated A Generated only when SPIEO 1 x Don t care Dn D6 to DO Extended code Al A2 AS A1 50 1000x110B A2 50 0110x010B Example Read ALDO during interrupt servicing IICCO L 1 set by software A3 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care Dn D6 to DO User s Manual U12697EJ4V1UD 329 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 330 e When failed in the stop condition during a data transfer Al A2 1 50 1000x110B A2 IICSO 01000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care Dn D6 to DO f When arbitration failed at a low data level and the restart condition was about to be generated WTIMO 1 STTO 1 1 2 A4 A1 IICS0 1000x110B A2 50 1000xx00B 50 01000100B Example Read ALDO during interrupt servicing A4 IICSO 00000001B Remarks A Always generated A Generated only when SPIE0 1 x Don t care g When arbitration failed in a stop condition and the restart condition was about to be generated WTIMO 1 STTO 1 Al A2 A3 1 50 1000x110B A2 11 50 1000 00 IICSO 01000001B
347. ept 2 bus mode Operational only when an external input clock is selected as the serial clock bus mode Operation disabled External interrupt INTPO to INTP5 Operation enabled Bus lines during ADO to AD7 High impedance external expansion A8 to A19 Holds the state before the HALT mode was set Low level High level 500 Input state is retained User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION b Releasing the HALT mode i ii Releasing HALT mode by NMI input When the valid edge specified by external interrupt edge enable register 0 EGP0 EGN0 is input to the NMI input the HALT mode is released When the HALT mode is released if non maskable interrupts by NMI pin input can be acknowledged execution branches to the NMI interrupt service program If interrupts cannot be acknowledged when the HALT mode has been set in the NMI interrupt service program execution starts again from the instruction following the instruction that setthe HALT mode When interrupts can be acknowledged by executing the RETI instruction execution branches to the NMI interrupt service program For details of NMI interrupt acknowledgement refer to 22 6 Non Maskable Interrupt Acknowledgment Operation Releasing HALT mode by a maskable interrupt request An unmasked maskable interrupt request is generated to release the HALT mode When the HALT mode is released and the interrupt en
348. equest flag SRIFn is set Remark n 1 2 Figure 16 15 3 Wire Serial I O Mode Timing SCKn SIn SOn SRIFn Transfer completion L Transfer start in synchronization with falling edge of SCKn Remark n 1 2 c Transfer start Serial transfer is started by setting transmit data to or reading serial I O shift register n SIOn when the following two conditions are satisfied SIOn operation control bit CSIEn 1 Following 8 bit serial transfer the internal serial clock is stopped or SCKn is high level Transmit receive mode When CSIEn 1 and MODEn 0 and transfer is started when SIOn is written Receive only mode When CSIEn 1 and MODEn 1 and transfer is started when SIOn is read Caution After data is written to SlOn transfer will not start even if CSIEn is set to 1 Serial transfer automatically stops at the end of 8 bit transfer and the interrupt request flag SRIFn is set Remark 1 2 284 User s Manual U12697EJ4V1UD CHAPTER 17 3 WIRE SERIAL I O MODE 17 1 Function This mode transfers 8 bit data by using the three lines of the serial clock SCK0 the serial output SO0 and the serial input 510 Since the 3 wire serial I O mode can perform simultaneous transmission and reception the data transfer processing time becomes shorter The start bit of the 8 bit data to be serially transferred is fixed to the MSB The 3 wire serial I O mode is effective when connecting peripher
349. er CR1W TO At Ti At T2 At T9 A TA ALT5 At T6 At T7 At T8 At T9 At Buffer register P120 P121 P122 P123 Note For the INTP2 high low level width refer to the data sheet User s Manual U12697EJAV1UD 425 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 38 Automatic Addition Control Ring Control Block Diagram 2 1 2 Phase Excitation Constant Velocity Operation Macro service control word Macro service channel 1M memory space Internal RAM Output timing 1233FFH te 123007H D6 pointer TAH Mode C MPT retained MPD Addition i register decremented 1 byte timer data jJ automatic addition ring control at MSC 0 interrupt request generation 16 bit capture compare register 00 amp L CR00 Output P121 latch To stepper connection P123 Output data 8 Items P120 16 bit timer counter 0 TMO Remark Internal RAM addresses in the figure are the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed OF0000H should be added to the values in the figure 426 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 39 Automatic Addition Control Ring Control Timing Diagram 2 1 2 Phase Ex
350. er SFR area in the internal data area Also use the data in the internal RAM area after initialization 62 User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE 3 3 1 Vector table area The 64 byte area from 00000H to 0003FH is reserved as the vector table area The program start addresses for branching by interrupt requests and RESET input are stored in the vector table area If context switching is used by each interrupt the register bank number of the switch destination is also stored in this area The portion that is not used as the vector table can be used as program memory or data memory The values written in the vector table are 16 bit values Therefore branching can only be to the base area Table 3 1 Vector Table Address Interrupt Source Vector Table Address Interrupt Source Vector Table Address BRK instruction INTST1 Operand error INTSER2 NMI INSR2 INTWDT non maskable INTCSI2 INTWDT maskable INTST2 INTP0 INTTM3 INTP1 INTTM00 INTP2 INTTM01 INTP3 INTTM1 INTP4 INTTM2 INTP5 INTAD INTIICONote INTTM5 INTCSIO INTTM6 INTSER1 INTWT INTSR1 INTCSI1 Note Only in the u PD784225Y Subseries User s Manual U12697EJAV1UD 63 CHAPTER 3 CPU ARCHITECTURE 3 3 2 CALLT instruction table area The 64 KB area from 00040H to 0007FH can store the subroutine entry addresses for the 1 byte call instruction CALLT For a CALLT instru
351. eration Serial counter Operation disabled Clear Port functionNete Operation enabled Counter operation Serial function port enabled function Transfer operation mode flag Operation mode Transfer start trigger SOn output Transmit receive mode SIOn write Normal output Receive only mode SIOn read Fix to low level Clock selection External clock to SCKn 8 bit timer counter 2 TM2 output TO2 fxx 8 1 56 MHz bo 16 781 kHz Notes 1 When CSIEn 0 SIOn operation stop status pins connected to SIn SOn and SCKn can be used as ports 2 Set the external clock and TO2 to fxx 8 or below when selecting the external clock SCKn and TM2 output TO2 for the clock Remarks 1 1 2 2 Figures in parentheses apply to operation at fxx 12 5 MHz User s Manual U12697EJ4V1UD 281 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O 16 4 3 Operation 1 282 The following two types of 3 wire serial I O operation modes are available Operation stopped mode 3 wire serial I O mode Operation stopped mode Serial transfer is not possible in the operation stopped mode which reduces power consumption Moreover in operation stopped mode pins can be used as normal I O ports a Register setting The operation stop mode is set by serial operation registers 1 and 2 CSIM1 CSIM2 CSIM1 and CSIM2 can be set by a 1 bit or 8 bit memory manipulation instruction RES
352. erface status register 2 262 268 Baud rate generator control register 1 262 263 269 Baud rate generator control register 2 262 263 269 Oscillation mode selection register 93 Clock output control register 350 351 ROM correction address register H 509 ROM correction address register L 509 ROM correction control register 509 16 bit capture compare register 00 147 16 bit capture compare register 01 148 8 bit compare register 10 182 8 bit compare register 20 182 8 bit compare register 50 202 8 bit compare register 60 202 Capture compare control register 0 152 155 157 Interrupt control register 0 366 Serial operation mode register 0 286 287 288 Serial operation mode register 1 280 281 282 Serial operation mode register 2 280 281 282 D A conversion setting register 0 248 D A conversion setting register 1 248 D A converter mode register 0 249 D A converter mode register 1 249 External interrupt falling edge enable register 0 356 External interrupt rising edge enable register 0 356 External access status enable register 459 Serial shift register 0 294 305 12 bus control register 0 295 296 User s Manual U12697EJAV1UD 617 APPENDIX D REGISTER INDEX IICS0 12C bus status register 0 300 IMC Interrupt mode control register 372 IMS Internal memory size switching register 68 513 ISPR In
353. eri supply Main power supply Power supply 24 7 3 Standby function in low power consumption mode The standby function in the low power consumption mode has a HALT mode and an IDLE mode User s Manual U12697EJ4V1UD 499 CHAPTER 24 STANDBY FUNCTION 1 HALT mode a Settings and operating states of HALT mode When the HALT mode is set in the low power consumption mode set 75H in STBC Table 24 9 shows the operating states in the HALT mode Table 24 9 Operating States in HALT Mode Clock generator The clock supplied to the CPU stops and only the main system clock stops oscillating CPU Operation disabled Port output latch Holds the state before the HALT mode was set 16 bit timer event counter Operational when the watch timer output is selected as the count clock select fxr as the count clock of the watch timer 8 bit timer event counters 1 2 Operational when TI1 and TI2 are selected as the count clocks 8 bit timers 5 and 6 Operational when TI5 and TI6 are selected as the count clocks Watch timer Operational only when fxr is selected as the count clock Watchdog timer Operation disabled counter is initialized A D converter Operation disabled D A converter Operation enabled Real time output port Operational when an external trigger is used or TI1 and TI2 are selected as the count clocks of 8 bit timer counters 1 and 2 Serial interface Exc
354. ernal 18 external 7 Software sources BRK instruction BRKCS instruction operand error Non maskable Internal 1 external 1 Maskable Internal 17 external 6 4 level programmable priority Three processing formats Vectored interrupt macro service context switching Power supply voltage Vpp 1 8 to 5 5 V Vpp 1 9 to 5 5 V Package 80 pin plastic TQFP fine pitch 12 x 12 80 pin plastic QFP 14 x 14 Note Only in the wPD784225Y Subseries 40 User s Manual U12697EJ4V1UD CHAPTER 1 OVERVIEW An overview of the timers is shown below For details referto CHAPTER 8 16 BIT TIMER EVENT COUNTER CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 and CHAPTER 10 8 BIT TIMERS 5 6 16 Bit Timer 8 Bit Timer 8 Bit Timer 8 Bit Timer 5 8 Bit Timer 6 Event Counter Event Counter 1 Event Counter 2 Count width 8 bits 16 bits Operation mode Interval timer External event counter Functions Timer output PPG output PWM output Square wave output One shot pulse output Y Pulse width measurement 2 inputs Number of interrupt requests 2 Note Can also be used as a 16 bit timer event counter or 16 bit timer when connected in cascade When using as a 16 bit timer event counter the following functions are available Interval timer External event counter Square wave output An overview of the serial
355. ernal high speed RAM IRAM Table 3 2 Internal RAM Area List Internal RAM Internal RAM Area Product Name uPD784224 3 584 bytes 0F100H to OFEFFH Peripheral RAM PRAM 3 072 bytes 0 100 to OFCFFH uPD784225 4 352 bytes uPD78F4225 to OFEFFH 3 840 bytes to OFCFFH Internal High Speed RAM IRAM 512 bytes OFDOOH to OFEFFH Remark The addresses in the table are the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed 0 0000 is added to the above values 66 User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE Figure 3 3 is the internal RAM memory map Figure 3 3 Internal RAM Memory Map OOFEFFH General purpose register area OOFE80H Available range for short direct addressing 1 OOFE39H Macro service control word area OOFEO6H OOFEOOH Internal high speed RAM OOFDFFH Available range for short direct addressing 2 00FD20H OOFD1FH 00FD00H OOFCFFH Peripheral RAM Differs according to the producto Note uPD784224 00 100 uPD784225 78 4225 00 0 addresses in the figure the values when the LOCATION instruction executed When the LOCATION 0FH instruction is executed 0F0000H is added to the above values User s Manual U12697EJ4V1UD 67 CHAPTER 3 CPU ARCHITECTURE 1 Internal high speed RAM IRAM The internal
356. erval time of the prescaler controls the operation of the 5 bit counter and sets the set time of the watch flag WTM is set by a 1 bit 8 bit memory manipulation instruction RESET input sets WTM to 00H User s Manual U12697EJ4V1UD 217 CHAPTER 11 WATCH TIMER Figure 11 2 Format of Watch Timer Mode Control Register WTM Address OFF9CH After reset OOH R W Symbol 7 6 5 4 3 2 0 0 WTM WTM7 WTM6 WTM5 WTM4 WTM3 oo WTM1 WTM0 Selects count clock of watch timer Main system clock 27 Subsystem clock fxr Selects interval time of prescaler 24 fw 488 us 25 tw 977 us 26 fw 1 95 ms 27 fw 3 91 ms 28 tw 7 81 ms 29 tw 15 6 ms above Setting prohibited 214 tw 0 5 s 25 fw 977 us Clear after operation stop Start WTMO Controls operation of 5 bit counter Operation stop clear both prescaler and timer Operation enable Cautions 1 Stop the timer operation before overwriting WTM 2 Do not overwrite WTM when both the watch timer and interval timer are being used If the timer is stopped to overwrite WTM both the prescaler and timer are cleared causing an error to occur for the watch timer interrupt INTWT Remarks 1 fw Watch timer clock oscillation frequency 27 or fxr bo Main system clock oscillation frequency Subsystem clock oscillation frequency 2 Figures in parentheses apply to operation at fw 32 768 kHz
357. es parity errors framing errors and overrun errors As the data reception result error flag is set inside asynchronous serial interface status register n ASISn the receive error interrupt request INTSERn is generated The receive error interrupt is generated before a receive completion interrupt request INTSRn Receive error causes are shown in Table 16 4 What type of error has occurred during reception can be detected by reading the contents of asynchronous serial interface status register n ASISn during processing of the receive error interrupt INTSERn refer to Table 16 5 and Figure 16 10 The contents of ASISn are reset to 0 either when receive buffer register n RXBn is read or when the next data is received if the next data has an error this error flag is set Remark 1 2 Table 16 5 Receive Error Causes Receive Error Parity error Parity specified for transmission and parity of receive data don t match Framing error Stop bit was not detected Overrun error Next data reception was completed before data was read from the receive buffer register Figure 16 10 Receive Error Timing STOP RxDn input START INTSRnNete INTSERn when framing overrun error occurs INTSERn when parity error occurs Note INTSRn will not be triggered if an error occurs when the ISRMn bit has been set 1 Cautions 1 The contents of ASISn are reset to 0 either when receive buffer register n
358. escaler mode register 5 OFF6DH Prescaler mode register 6 OFF70H Asynchronous serial interface mode register 1 OFF71H Asynchronous serial interface mode register 2 OFF72H Asynchronous serial interface status register 1 ay ae eH Ha eH He Se OFF73H Asynchronous serial interface status register 2 OFF74H Transmission shift register 1 Reception buffer register 1 OFF75H Transmission shift register 2 Reception buffer register 2 OFF76H Baud rate generator control register 1 OFF77H Baud rate generator control register 2 OFF7AH Oscillation mode selection register OFF80H A D converter mode register OFF81H A D converter input selection register eae s RD rS pee SS eee fl S S s mS e ee m Roo E Wf ms ee os OFF83H A D conversion result register Undefined Notes 1 These are the values when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed FOOOOH is added to this value 2 Only in the uPD784225Y Subseries 86 User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE Table 3 6 Special Function Register SFR List 3 4 Bit Manipulation Unit AddressNote 1 Special Function Register SFR Name After Reset 1 Bit 8 Bits 16 Bits OFF84H D A conversion value setting register 0 OFF85H D A conversion v
359. etails about non maskable interrupt acknowledgement refer to 22 6 Non Maskable Interrupt Acknowledgment Operation Caution The HALT mode cannot be released by the watchdog timer 2 Releasing HALT mode by a maskable interrupt request The HALT mode can only be released by a maskable interrupt request when that interrupt s mask flag is 0 If an interrupt can be acknowledged when the HALT mode is released and the interrupt request enable flag IE is set to 1 execution branches to the interrupt service program If the IE flag is cleared to 0 when acknowledge ment is not possible execution restarts from the next instruction that sets the HALT mode For details about interrupt acknowledgement refer to 22 7 Maskable Interrupt Acknowledgment Operation A macro service temporarily releases the HALT mode performs one time processing and returns again to the HALT mode If the macro service is only specified a few times the HALT mode is released when the VCIE bit in the macro service mode register in the macro service control word is cleared to 0 The operation after this release is identical to the release by the maskable interrupt described earlier Also when the VCIE bit is set to 1 the HALT mode is entered again and the HALT mode is released by the next interrupt request 478 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Release Source Maskable interrupt request except for a macro service request Table 24 4 Releasing H
360. etecececceecsenevenuncevecaesesedececussedsuneers 621 User s Manual U12697EJAV1UD 19 LIST OF FIGURES 1 8 Figure No Title Page 2 1 MEI rere reer IEEE 55 3 1 nPD784224 Memory Mau Sos u uu uuu uuu sssunaiusapastqasqapasaaapaskaqassqupqqaqsthsasasqanaqqaqayahaassqupahasqa a 59 3 2 uPD784225 Memory Map rhet dre denn 60 3 3 Internal RAM Memory Map 67 3 4 Format of Internal Memory Size Switching Register 5 69 3 5 Format of Program Counter PC u nnne u tnter enne trennen 70 3 6 Format of Program Status Word PSW nennen enne 70 3 7 Format of Stack Pointer SP iusticie tes heen een 75 3 8 Data Saved ai reinen heim NE 76 3 9 Data Restored from Stack ertet er 77 3 10 Format of General Purpose Register 79 3 11 General Purpose Register Addresses a 80 4 1 Block Diagram of Clock 91 4 2 Format of Standby Control Register 5 93 4 3 Format of Oscillation Mode Selection Register 94 4 4 Format of Clock Status Register PCS nnne nennen 95 4 5 Format
361. ets RTPM to 00H Figure 6 3 Format of Real Time Output Port Mode Register RTPM Address OFF9AH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPMO Real time output port selection m 0 to 7 Port mode Real time output mode Caution When used as a real time output port set the port pins for real time output to the output mode 138 User s Manual U12697EJ4V1UD CHAPTER 6 REAL TIME OUTPUT FUNCTION 2 Real time output port control register RTPC This register sets the operation mode and output trigger of the real time output port Table 6 3 shows the relationship between the operation mode and output trigger of the real time output port RTPC is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets RTPC to 00H Figure 6 4 Format of Real Time Output Port Control Register RTPC Address OFF9BH After reset OOH R W Symbol 6 3 2 1 0 RTPOE Real time output port operation control 0 Operation disabled 1 Operation enabledNote BYTE Real time output port operation mode 0 4 bits x 2 channels 1 8 bits x 1 channel EXTR Real time output control by INTP2 0 INTP2 not set as real time output trigger 1 INTP2 set as real time output trigger Note Whenreal time output operation is enabled RTPOE 1 the values ofthe real time output buffer registers RTBH and RTBL are transferred to the real time output port output latch
362. f TIOO Generated on match between TMO and CROO and match between TMO and CRO1 No overflow User s Manual U12697EJ4V1UD 151 CHAPTER 8 16 BIT TIMER EVENT COUNTER Cautions 1 Before changing the clear mode and TOO output timing be sure to stop the timer operation reset 02 and TMCOS to 0 0 The valid edge of the TIOO pin is selected by using prescaler mode register 0 PRMO 2 When a mode in which the timer is cleared and started on a match between TMO and CROO the OVFO flag is set to 1 when the count value of TMO changes from FFFFH to 0000H with CROO set to FFFFH 3 The software trigger bit 6 OSPT of 16 bit timer output control register 0 TOCO 1 and the external trigger TIOO input are always valid in one shot pulse output mode If the software trigger is used in one shot pulse output mode the TIOO pin cannot be used as a general purpose port pin Therefore fix the TIOO pin to either high level or low level Remark TOO Output pin of the 16 bit timer event counter TIOO Input pin of the 16 bit timer event counter TMO 16 bit timer counter 0 CROO Compare register 00 CR01 Compare register 01 152 User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 Capture compare control register 0 CRC0 This register controls the operation of the capture compare registers CR00 and CR01 CRCO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CRCO to 00H
363. f Interrupt Control Registers for Interrupt Requests Interrupt Request Signal INTWDTM WDTIC Interrupt Control Register Interrupt Request Flag WDTIF Interrupt Mask Flag WDTMK Macro Service Enable Flag WDTISM Priority Speci fication Flag WDTPR0 WDTPR1 Context Switching Enable Flag WDTCSE INTP0 PICO PIFO PMKO PISMO PPROO PPRO1 PCSEO INTP1 PIC1 PIF1 PMK1 PISM1 PPR10 PPR11 PCSE1 INTP2 PIC2 PIF2 PMK2 PISM2 PPR20 PPR21 PCSE2 INTP3 PIC3 PIF3 PMK3 PISM3 PPR30 PPR31 PCSE3 INTP4 PIC4 PIF4 PMK4 PISM4 PPR40 PPR41 PCSE4 INTP5 PIC5 PIF5 PMK5 PISM5 PPR50 PPR51 PCSE5 INTIICO INTCSIO CSIICO CSIIFO CSIMKO CSIISMO CSIPROO CSIPRO1 CSICSEO INTSER1 SERIC1 SERIF1 SERMK1 SERISM1 SERPR10 SERPR11 SERCSE1 INTSR1 INTCSI1 SRIC1 SRIF1 SRMK1 SRISM1 SRPR10 SRPR11 SRCSE1 INTST1 STIC1 STIF1 STMK1 STISM1 STPR10 STPR11 STCSE1 INTSER2 SERIC2 SERIF2 SERMK2 SERISM2 SERPR20 SERPR21 SERCSE2 INTSR2 INTCSI2 SRIC2 SRIF2 SRMK2 SRISM2 SRPR20 SRPR21 SRCSE2 INTST2 STIC2 STIF2 STMK2 STISM2 STPR20 STPR21 STCSE2 INTTM3 TMIC3 TMIF3 TMMK3 TMISM3 TMPR30 TMPR31 TMCSE3 INTTM00 TMIC00 TMIF00 TMMK00 TMISM00 TMPR00
364. f the order which the interrupt requests y servicing were generated Notes 1 Low default priority 2 High default priority Remarks 1 to 2 inthe figure above are arbitrary names used to differentiate between the interrupt requests and macro service requests 2 High low default priorities in the figure indicate the relative priority levels of the two interrupt requests 390 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 15 Examples of Servicing of Simultaneously Generated Interrupt Requests Main routine 1 Interrupt request a Level 2 Macro service request b Level 3 7 Macro service request b servicing When requests are generated ESSE simultaneously they are Macro service request c Level 1 _________ Macro service request servicing acknowledged in order starting Interrupt request d Level 1 2 with macro service requests Interrupt request e Level 1 Macro service request f servicing Macro service requests are acknowledged in default Macro service request f Level 1 Interrupt request d servicing priority order b c f not dependent upon the programmable priority order As interrupt requests are Interrupt request e servicing acknowledged in high to low priority level order d and e are acknowledged first As d and e have the same Interrupt request a servicing priority level the interrupt Default priority order request with the higher defau
365. fxx 4 3 13 MHz fxx 8 1 56 MHz fxx 16 781 kHz fxx 32 391 kHz fxx 128 97 6 kHz 1 fxx 512 24 4 kHz Other than above Setting prohibited Cautions 1 If data different from that of PRM6 is written stop the timer beforehand 2 Be sure to set bits to 7 of PRM6 to 0 Remark Values in parentheses apply to operation at fxx 12 5 MHz User s Manual U12697EJ4V1UD 207 CHAPTER 10 8 BIT TIMERS 5 6 10 4 Operation 10 4 1 Operation as interval timer 8 bit operation The timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the count preset in 8 bit compare registers 50 and 60 CR50 CR60 If the count in 8 bit timer counters 5 and 6 TM5 TM6 matches the value set in CR50 and CR60 the values of 5 and TM6 are cleared to 0 and the count continues At the same time an interrupt request signal 5 INTTM6 is generated The TM5 and TM6 count clock can be selected with bits 0 to 2 TCLnO to TCLn2 of prescaler mode registers 5 and 6 PRM5 PRM6 Setting method 1 Set each register PRMn Selects the count clock e 0 Compare value TMCn Selects the clear and start mode when TMn and CRnO match TMCn 0000xxx0B x Don t care 2 When TCEn 1 is set counting starts 3 When the values of TMn and CRnO match INTTMn is generated TMn is cleared to 00H 4 Then INTTMn is repeatedl
366. g time By setting the AW bit in the memory expansion mode register MM to 1 an address wait is inserted into the entire memory access timeN te When the address wait is inserted the high level period of the ASTB signal is lengthened by one system clock when 80 ns fxx 12 5 MHz Note This excludes the internal RAM internal SFR and internal ROM during a high speed fetch When the internal ROM access is set to have the same cycle as an external ROM access an address wait is inserted during an internal ROM access Figure 23 9 Read Write Timing by Address Wait Function 1 3 a Read timing when an address wait is not inserted ASTB BAN DEED Rb Note fxx Main system clock frequency This signal is only the uPD784225 450 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 9 Read Write Timing by Address Wait Function 2 3 b Read timing when an address wait is inserted D X 43 3 ELNE A8 to A19 Higher address Hi Z Hi Z Hi Z ASTB RD Note f Main system clock frequency This signal is only in the uPD784225 User s Manual U12697EJAV1UD 451 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 9 Read Write Timing by Address Wait Function 3 3 c Write timing when an address wait is not inserted dd fs FT Ss A8 to A19 Higher address ASTB WR d Write timing when an address wait is inserted ASTB Note fxx Main system cloc
367. ger bit 6 OSPT of 16 bit timer output control register 0 1 and the external trigger TIOO input are always valid in one shot pulse output mode If the software trigger is used in one shot pulse output mode the TIOO pin cannot be used as a general purpose port pin Therefore fix the TIOO pin to either high level or low level User s Manual U12697EJAV1UD 173 CHAPTER 8 16 BIT TIMER EVENT COUNTER 174 Figure 8 27 Control Register Settings for One Shot Pulse Output by External Trigger a 16 bit timer mode control register 0 TMC0 TMC03 TMC02 TMC01 OVFO Too o o o on on on o b Capture compare conirol register 0 CRCO Clears and starts or free running at valid edge of TI00 P35 pin CRC02 CRC01 CRC00 o o o o CR00 used as compare register CR01 used as compare register c 16 bit timer output control register 0 TOCO OSPT OSPE 04 LVSO LVRO 0 01 TOEO Enables TOO output Reverses output on match between TMO and CROO Specifies initial value of TOO output Reverses output on match between TMO and CR01 Sets one shot pulse output mode Caution Set 00 and CR01 to a value in the following range 0000H lt CRO1 lt CROO lt FFFFH Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the one shot pulse output function For details refer to Figures 8 2 to 8 4 User s Manual U1
368. gram of P60 10 6 ier etri Si eR usa sua dp ceca UR De UAE seid 121 5 13 Block Diagram of P64 P65 and P67 5 iie usu ae 122 5 14 6 cise t DLE 123 5 15 Block Diagram ot u un n ttt eei rg cte et per 124 5 16 Bleck Diagrammof P71 TEES 125 5 17 Block Diagramiof P723 ice eoi erred eeu 126 5 18 Block Diagramiof P120 t0 127 20 User s Manual U12697EJ4V1UD LIST OF FIGURES 2 8 Figure No Title Page 5 19 Block Diagram Ot P130 arid P 191 n unas etre retira ee eiii itt 128 5 20 Format of Port Mode Registe aori y tr tte RE e br 131 5 21 Format of Pull Up Resistor Option Register 1 u 132 5 22 Format of Port Function Control Register 2 2 44420444 0 00000 133 6 1 Block Diagram of Real Time Output Port nennen nennen 136 6 2 Configuration of Real Time Output Buffer Register a 137 6 3 Format of Real Time Output Port Mode Register a 138 6 4 Format of Real Time Output Port Control Register RTPC 139 6 5 Example of Operation Timing of Real Time Output Port EXTR 0 BYTE 0 140 7 1 Block Diagram 143 8 1 Block Diagram of 16 Bit T
369. h txt u PD74HCUO4 Note Time required to stabilize oscillation after applying supply voltage Vpp Cautions 1 When using the subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as Vss e Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator 2 When the main system clock is stopped and the device is operating on the subsystem clock wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock Remark For the resonator selection and oscillator constant customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation 572 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constants Main system clock Ceramic resonator connection Ta 40 to 85 C Manufacturer Murata Mfg Co Ltd Part Number Oscillation Recommended Oscillation Oscillation Frequency Circuit Constant Voltage Rang
370. he Application Note To know the electrical specifications Refer to CHAPTER 29 ELECTRICAL SPECIFICATIONS Differences Between the uPD784225 Subseries and the u PD784225Y Subseries Conventions The only functional difference between the uPD784225 Subseries and uPD784225Y Subseries is the clocked serial interface The two subseries share all other functions Caution The clock serial interface is described in the following two chapters CHAPTER 17 3 WIRE SERIAL I O MODE CHAPTER 18 C BUS MODE uPD784225Y SUBSERIES only For an overview of the serial interface also read CHAPTER 15 Data significance Higher digits on the left and lower digits on the right Active low representation overscore over pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary or Decimal xxxx Hexadecimal User s Manual U12697EJ4V1UD 9 Register Representation 7 6 5 4 2 1 0 Bits whose numbers are circled are reserved words in NEC s assembler or are defined as sfr EDC dc og ere e xm owe variables by the pragma sfr directive in the C compiler When writing When reading Write O or 1 The operation Read O or 1 is not affected by either value Must write O Must write 1 Write the value for the Read the value tha
371. he ISPR that corresponds to the highest priority interrupt request is automatically cleared 0 by hardware The contents of the ISPR are not changed by execution of the RETB or RETCSB instruction RESET input clears the ISPR to OOH Figure 22 3 Format of In Service Priority Register ISPR Address OFFA8H After reset 00H R Symbol 7 6 5 4 3 2 1 0 ISPR NMIS WDTS 0 UE ISPR3 ISPR2 ISPR1 ISPR0 NMIS NMI processing status NMI interrupt is not acknowledged NMI interrupt is acknowledged WDTS Watchdog timer interrupt servicing status Watchdog timer interrupt is not acknowledged Watchdog timer interrupt is acknowledged Priority level n 0 to 3 Interrupt of priority level n is not acknowledged Interrupt of priority level n is acknowledged Caution The in service priority register ISPR is a read only register The microcontroller may malfunction if this register is written 372 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 3 4 Interrupt mode control register IMC IMC contains the PRSL flag The PRSL flag specifies enabling disabling of nesting of maskable interrupts for which the lowest priority level level 3 is specified When IMC is manipulated the interrupt disabled state DI state should be set first to prevent malfunction IMC can be read or written by an 8 bit manipulation instruction or bit manipulation instruction RESET input sets the IMC register to 80H Figure 22 4
372. he source clock of the 5 bit counter TMC16 0 LVS1 0 LVR1 0 TMC11 1 Moreover set TOE1 to 0 when TO1 is not output externally and TOE1 to 1 when TO1 is output externally n 1 2 Figures in parentheses apply to operation at fxx 12 5 MHz fsck Source clock of 5 bit counter m Value set in 5 0 to TPSn2 0 lt m lt 5 k Value set in MDLnO to MDLn3 0 k x 14 User s Manual U12697EJAV1UD 265 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O 16 3 Operation The asynchronous serial interface has the following two operation modes Operation stop mode Asynchronous serial interface UART mode 16 3 1 Operation stopped mode Serial transfer cannot be performed in the operation stopped mode resulting in reduced power consumption Moreover in the operation stopped mode pins can be used as regular ports 1 Register setting The operation stopped mode is set by asynchronous serial interface mode registers 1 and 2 ASIM1 ASIM2 ASIM1 and ASIM2 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM1 and ASIM2 to OOH Address OFF70H OFF71H After reset OOH R W Symbol 5 4 3 2 1 0 ASIMn RxEn Psm PSro Sin iSRMn ow RxD1 P20 RxD2 P70 TxD1 P21 TxD2 P71 Operation mode pin function pin function Operation stop Port function Port function UART mode Serial function Port function Receive only UART mode Port function Serial f
373. hen mass producing it with the mask ROM version be sure to conduct sufficient evaluations for the commercial samples not engineering samples of the mask ROM version User s Manual U12697EJAV1UD 513 CHAPTER 27 uPD78F4225 AND uPD78F4225Y PROGRAMMING 27 1 Internal Memory Size Switching Register IMS IMS is a register used to prevent a certain part of the internal memory from being used by software By setting IMS it is possible to establish a memory map that is the same as the mask ROM product s memory map for an internal memory ROM RAM of a different capacity IMS is set by an 8 bit memory manipulation instruction RESET input sets IMS to FFH Figure 27 1 Format of Internal Memory Size Switching Register IMS Address OFFFCH After reset FFH w Symbol 7 6 5 4 3 2 1 0 Internal ROM capacity selection 96 KB 128 KB Setting prohibited RAM1 RAM0 Internal high speed RAM capacity selection 3 072 bytes 3 840 bytes Other than above Setting prohibited Caution IMS is not available in the mask ROM versions uPD784224 784225 784224Y and 784225Y The IMS settings to create the same memory map as mask ROM versions are shown in Table 27 2 Table 27 2 Internal Memory Size Switching Register IMS Settings Relevant Mask ROM Version IMS Setting uPD784224 784224Y EEH uPD784225 784225Y FFH 514 User s Manual U12697EJAV1UD CHAPTER 27 J4PD78F4225 AND uPD78F4225Y PROGRAMMING 27
374. high speed RAM can be accessed at high speed FD20H to FEFFH can use the short direct addressing mode for high speed access The two short direct addressing modes are short direct addressing 1 and short direct addressing 2 based on the address of the target Both addressing modes have the same function In a portion of the instructions short direct addressing 2 has a shorter word length than short direct addressing 1 For details see 78K IV Series Instruction User s Manual U10905E A program cannot be fetched from IRAM If a program is fetched from an address that is mapped by IRAM the CPU inadvertently loops The following areas are reserved in IRAM e General purpose register area FE80H to FEFFH e Macro service control word area FEQ6H to FE39H Macro service channel area FE00H to FEFFH the address is set by a macro service control word When reserved functions are not used in these areas they can be used as normal data memory Remark The addresses here are the addresses when the LOCATION OH instruction is executed When the LOCATION OFH instruction is executed OF0000H is added to the values here 2 Peripheral RAM PRAM The peripheral RAM PRAM is used as normal program memory or data memory When used as the program memory the program must be written beforehand in the peripheral RAM by a program A program fetch from the peripheral RAM is high speed and can occur in two clocks in 2 byte units 3 4 2 Special function registe
375. ied by MPT 1 byte Retains MPT No automatic addition Retains MPT Increments MPT No ring control Ring control Automatic addition No ring control Ring control Data size for timer specified by MPT 2 bytes No automatic addition No ring control Ring control Automatic addition No ring control Ring control 3 Macro service channel pointer The macro service channel pointer specifies the macro service channel address The macro service channel can be located in the 256 byte space from FE00H to FEFFH when the LOCATION OH instruction is executed or FFEOOH to FFEFFH when the LOCATION OFH instruction is executed and the higher 16 bits of the address are fixed Therefore the lower 8 bits of the data stored to the highest address of the macro service channel are set in the macro service channel pointer User s Manual U12697EJ4V1UD 403 CHAPTER 22 INTERRUPT FUNCTIONS 22 8 6 Macro service type A 1 404 Operation Data transfers are performed between buffer memory in the macro service channel and an SFR specified in the macro service channel With type A the data transfer direction can be selected as memory to SFR or SFR to memory Data transfers are performed the number of times set beforehand in the macro service counter One macro service processing transfers 8 bit or 16 bit data Type A macro
376. ied use of P03 INTP3 an on chip pull up resistor can be specified by a software setting in P04 P05 Pa INTP4 1 bit units INTP5 P10 to P17 ANI0 to ANI7 Port 1 P1 8 bit input only port RxD1 SI Port 2 P2 TxD1 SO1 8 bit I O port Input output can be specified in 1 bit units ASCK1 SCK1 PCL Regardless of whether the input or output mode is specified use of an on chip pull up resistor can be specified by a software setting in BUZ 1 bit units S10 SDAONote 500 TO1 8 bit I O port TO2 Input output can be specified in 1 bit units TH Regardless of whether the input or output mode is specified use of an on chip pull up resistor can be specified by a software setting in TI2 1 bit units TIOO TIO1 EXA P40 to P47 ADO to AD7 Port 4 P4 8 bit I O port Input output can be specified in 1 bit units For input mode pins use of on chip pull up resistors can be specified for all pins by a software setting LEDs can be driven directly Note The SDAO and SCLO pins are provided only in the uPD784225Y Subseries SCKO SCLONote TOO Port 3 P3 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 User s Manual U12697EJ4V1UD 43 CHAPTER 2 PIN FUNCTIONS 1 Port pins 2 2 Pin Name Alternate Function Function P50 to P57 A8 to A15 Port 5 P5 8 bit I O port Input output can be specifie
377. ies 600 Unless otherwise specified products supported by PC AT and compatible machines can be used for the PC98 NX series When using the PC98 NX series refer to the explanation of IBM PC AT and compatible machines For Windows Unless otherwise specified Windows indicates the following OSs Windows 3 1 Windows 95 98 2000 Windows NT Ver 4 0 User s Manual U12697EJAV1UD APPENDIX B DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 1 2 1 When using in circuit emulator IE 78K4 NS Language processing software Dj Assembler package C compiler package a C library source file Device file Debugging tools System simulator Integrated debugger Device file Embedded software Real time OS mE Host machine PC Interface adapter PC card interface etc Flash memory writing environment Flash programmer Emulation board Flash memory write adapter On chip flash Emulation probe memory product In circuit emulator Power supply unit Conversion socket or conversion adapter Target system User s Manual U12697EJAV1UD 601 APPENDIX B DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 2 2 2 When using in circuit emulator IE 784000 R Language processing software Assembler package C compiler package library source file Device file Debugging tools System simulator
378. ified 162 8 16 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Begiste s uS SU ie Pis Ud uay 163 8 17 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with Rising Edge Specified dopnas asrine etre aan 164 8 18 Control Register Settings for Pulse Width Measurement by Restarting 165 8 19 Timing of Pulse Width Measurement by Restarting with Rising Edge Specified 166 8 20 Control Register Settings in External Event Counter Mode 2 460 167 8 21 Configuration of External Event Counter SER E ERRAT 167 8 22 Timing of External Event Counter Operation with Rising Edge Specified 168 8 23 Control Register Settings in Square Wave Output 169 8 24 Timing of Square Wave Output Operation L nennen neni 169 8 25 Control Register Settings for One Shot Pulse Output by Software Trigger 171 8 26 Timing of One Shot Pulse Output Operation by Software Trigger 172 8 27 Control Register Settings for One Shot Pulse Output by External Trigger 174 User s Manual
379. illation stabilization time specification register OSTS to 1 Using the STOP mode in the state where bit EXTC of OSTS is cleared 0 while the external clock is input may destroy the PD784225 or reduce reliability When the EXTC bit of OSTS is set to 1 always input to pin X2 the clock that has the inverse phase of the clock input at pin X1 Execute three NOP instructions after the standby instruction after releasing standby If this is not done when the execution of a standby instruction conflicts with an interrupt request the standby instruction is not executed and interrupts are acknowledged after executing multiple instructions that follow a standby instruction The instruction that is executed before acknowledging the interrupt starts being executed within a maximum of six clocks after the standby instruction is executed User s Manual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION Example MOV STBC byte NOP NOP NOP Cautions 3 When 2 0 even if MCK 1 the oscillation of the main system clock does not stop refer to 4 5 1 Main system clock operations Remarks 1 fxx Main system clock oscillation frequency fx or fx 2 fx Main system clock oscillation frequency fxt Subsystem clock oscillation frequency 2 x Don t care 2 Clock status register PCS PCS is an 8 bit read only register that shows the operating state of the CPU clock When bits 2 and 4 to 7 in PCS are read the corresponding bits in the standby control
380. ily halt the A D conversion operations before continuing 3 If ADCS is set after ADCE is set and the following time has elapsed the first A D conversion value can be used When 2 7 V to 5 5 V 14 us or more When 2 0 V to 2 7 V 28 us more When 1 9 V to 2 0 V 48 us or more uPD78F4225 78F4225Y When Voo 1 8 V to 2 0 V 48 us or more uPD784224 784225 784224Y 784225Y 4 If ADCS is set when ADCE 0 the first A D conversion value is undefined Remark fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency 2 A D converter input selection register ADIS Used to specify the input ports for analog signals to be A D converted ADIS can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ADIS to 00H Figure 13 3 Format of A D Converter Input Selection Register ADIS Address OFF81H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 Analog input channel setting User s Manual U12697EJAV1UD 231 CHAPTER 13 A D CONVERTER 13 4 Operations 13 4 1 Basic operations of A D converter lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt Select one channel for A D conversion with the A D converter input selection register ADIS The voltage input to the selected analog input channel is sampled by the sample amp hold circuit After sampling has been performed for
381. imer Event Counter Un aan 146 8 2 Format of 16 Bit Timer Mode Control Register 0 151 8 3 Format of Capture Compare Control Register 0 153 8 4 Format of 16 Bit Timer Output Control Register 0 154 8 5 Format of Prescaler Mode Register 0 155 8 6 Control Register Settings When Timer 0 Operates as Interval Timer 156 8 7 Contigurationvotlntervall TMe u 225022 Te HE Ret E RERUM ERR EE S REIR E aE 157 8 8 Timing of Interval Timer Operation sicco ect uu 157 8 9 Control Register Settings PPG Output 158 8 10 Control Register Settings for Pulse Width Measurement with Free Running Counter and One jer Teal E 159 8 11 Configuration for Pulse Width Measurement with Free Running Counter 160 8 12 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with Both Edges Specified c ori ttu bti nb Leia 160 8 13 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter 161 8 14 CRO01 Capture Operation with Rising Edge 162 8 15 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Spec
382. in the interrupt mode control register IMC Bit in the macro service mode register of the macro service control word that is in each macro service of the internal RAM are held at the value before the HALT mode was set User s Manual U12697EJ4V1UD 479 CHAPTER 24 STANDBY FUNCTION 24 4 STOP Mode 24 4 1 Settings and operating states of STOP mode The STOP mode is set by setting the STP bit in the standby control register STBC to 1 STBC can be written with 8 bit data by a special instruction Therefore the STOP mode is set by the MOV STBC byte instruction When interrupts are enabled IE flag in PSW is set to 1 specify three NOP instructions after the STOP mode setting instruction after the STOP mode is released If this is not done after the STOP mode is released multiple instructions can be executed before interrupts are acknowledged Inserting NOP instructions may change the order relationship between the interrupt servicing and instruction execution so to prevent problems caused by changes in the execution order be sure to take the measures described earlier The system clock when setting the STOP mode can only be set to the main system clock Caution Since an interrupt request signal is used when releasing the standby mode when an interrupt source that sets the interrupt request flag or resets the interrupt mask flag is generated even though the standby mode is entered it is immediately released When the STOP mode sett
383. indicates ROM code suffix 2 Products that have the part numbers suffixed by A are lead free products 2 uPD784225Y Subseries Part Number Package Internal ROM UPD784224Y GC xxx 8BT 80 pin plastic QFP 14 x 14 Mask ROM UPD784224Y GK xxx 9EU 80 pin plastic TQFP fine pitch 12 x 12 Mask ROM UPD784225Y GC xxx 8BT 80 pin plastic QFP 14 x 14 Mask ROM UPD784225Y GK xxx 9EU 80 pin plastic TQFP fine pitch 12 x 12 Mask ROM UPD78F4225YGC 8BT 80 pin plastic QFP 14 x 14 Flash memory UPD78F4225YGK 9EU 80 pin plastic TQFP fine pitch 12 x 12 Flash memory UPD784224YGC xxx 8BT A 80 plastic QFP 14 x 14 Mask ROM UPD784224YGK xxx 9EU A 80 plastic TQFP fine pitch 12 x 12 Mask ROM UPD784225YGC xxx 8BT A 80 plastic QFP 14 x 14 Mask ROM UPD784225YGK xxx 9EU A 80 plastic TQFP fine pitch 12 x 12 Mask ROM UPD78F4225YGC 8BT A 80 pin plastic QFP 14 x 14 Flash memory UPD78F4225YGK 9EU A 80 pin plastic TQFP fine pitch 12 x 12 Flash memory Remarks 1 indicates ROM code suffix 2 Products that have the part numbers suffixed by A are lead free products 34 User s Manual U12697EJ4V1UD CHAPTER 1 OVERVIEW 1 3 Pin Configuration Top View e 80 pin plastic 14 x 14 80 pin plastic TQFP fine pitch 12 x 12 N g 2 lo 2 2 2 gt E lt lt lt m gern 5 8 m gt S E E u a 2 2 S lt gt x x x X gt gt ALA OOO
384. ing instruction conflicts with the setting of an unmasked interrupt request flag or a non maskable interrupt request either of following two statuses are entered 1 Status in which STOP mode is set once and then released 2 Status in which STOP mode is not set The oscillation stabilization time after releasing STOP mode is inserted only for the status in which STOP mode is set once and then released The operating states in the STOP mode are described next 480 User s Manual U12697EJ4V1UD CHAPTER 24 STANDBY FUNCTION Table 24 5 Operating States in STOP Mode STOP Mode Setting With Subsystem Clock Without Subsystem Clock Clock generator Only main system clock stops oscillating CPU Operation disabled Port output latch Holds the state before the STOP mode was set 16 bit timer counter Operational when the watch timer output is Operation disabled selected as the count clock select fxr as the count clock of the watch timer 8 bit timer counters 1 2 Operational only when 1 and TI2 are selected as the count clocks 8 bit timer counters 5 6 Operational only when TI5 and TI6 are selected as the count clocks Watch timer Operational only when fxr is selected as Operation disabled the count clock Watchdog timer Operation disabled initializing counter A D converter Operation disabled D A converter Operation enabled Real time output port Operational when an external trigger
385. ing non maskable interrupt service program execution except when a high priority non maskable interrupt request is generated during execution of a low priority non maskable interrupt service program and for a certain period after execution of the special instructions shown in 22 9 Therefore a non maskable interrupt will be acknowledged even when the stack pointer SP value is undefined in particular after reset release etc In this case depending on the value of the SP it may happen that the program counter PC and program status word PSW are written to the address of a write inhibited special function register SFR refer to Table 3 6 in 3 9 Special Function Registers SFRs and the CPU becomes deadlocked or an unexpected signal output from a pin or PC and PSW are written to an address is which RAM is not incorporated with the result that the return from the non maskable interrupt service program is not performed normally and a software malfunction occurs Therefore the program following RESET release must be as follows CSEG ATO DW STRT CSEG BASE STRT LOCATION OFH or LOCATION 0 MOVG SP imm24 User s Manual U12697EJAV1UD 435 CHAPTER 22 INTERRUPT FUNCTIONS 10 When the following instructions are executed interrupt acknowledgement and macro service processing are held pending for 8 system clocks However software interrupts are not held pending El DI BRK BRKCS RETCS RETCSB addr16 RETI RETB LOCATION
386. ing takes place only when the third and fourth opcodes are mutual 1 s complements If the third and fourth opcodes are not mutual 1 s complements and not written the operand error interrupt is generated In this case the return address saved in the stack is the address of the instruction that caused the error Therefore the address that caused the error can be identified from the return address saved in the stack If returning by simply using the RETB instruction from the operand error an infinite loop results Since an operand error interrupt is generated only when the program inadvertently loops the correct special instruction is only generated when MOV WDM byte is described in the NEC assembler RA78K4 make the program initialize the system Other write instructions MOV WDM WDM byte instruction SET1 WDM etc are ignored and nothing happens In other words WDM is not written and interrupts such as operand error interrupts are not generated After a system reset RESET input when the watchdog timer starts when the RUN bit is set to 1 the WDM contents cannot change Only reset stop the watchdog timer The watchdog timer can be cleared by a special instruction WDM can be read by an 8 bit data transfer instruction RESET input sets WDM to 00H Figure 12 2 shows the WDM format 222 User s Manual U12697EJAV1UD CHAPTER 12 WATCHDOG TIMER Figure 12 2 Format of Watchdog Timer Mode Register WDM Address
387. ing the program so that the RSS bit is not set to 1 1 Using the RSS bit Registers used by instructions where the A X B C and AX registers are directly described in the operand column of the operation list see 28 2 Registers that are implicitly specified by instructions that use the A AX B and C registers with implied addressing Registers that are used in addressing by instructions that use the A B and C registers with indexed addressing and based indexed addressing The registers used in these cases are switched in the following ways by the RSS bit When RSS 0 A R1 X5R0 B gt R3 C R2 AXSRPO0 BC5RP1 When RSS 1 AoR5 gt 4 B gt R7 C R6 AXSRP2 BC RP3 The registers used in other cases always become the same registers regardless of the contents of the RSS bit For registers A X B C AX and BC in the NEC assembler RA78KA instruction code is generated for any register described by name or for registers set by an RSS quasi directive in the assembler When the RSS bitis set or reset always specify an RSS quasi directive immediately before or immediately after that instruction see the following examples Program examples When RSS 0 RSS 0 RSS quasi directive CLR1 PSWL 5 MOV B A This description corresponds to MOV R3 R1 User s Manual U12697EJ4V1UD 73 CHAPTER 3 CPU ARCHITECTURE When RSS 1 RSS 1 RSS quasi directive SET1 PSWL 5 MOV B
388. instruction MOV WDM byte The RETI instruction must not be used to return from a software interrupt caused by the BRK instruction Use the RETB instruction The RETCS instruction must not be used to return from a software interrupt caused by the BRKCS instruction Use the RETCSB instruction When a maskable interrupt is acknowledged by vectored interruption the RETI instruction must be used to return from the interrupt Subsequentinterrupt related operations will not be performed normally if a different instruction is used The RETCS instruction must be used to return from a context switching interrupt Subsequent interrupt related operations will not be performed normally if a different instruction is used Macro service requests are acknowledged and serviced even during execution of a non maskable interrupt service program To avoid macro service processing being performed during a non maskable interrupt service program manipulate the interrupt mask register in the non maskable interrupt service program to prevent macro service generation The RETI instruction must be used to return from a non maskable interrupt Subsequent interrupt acknowledgement will not be performed normally if a different instruction is used Refer to 22 12 Restoring Interrupt Function to Initial State when a program is to be restarted from the initial status after a non maskable interrupt acknowledgement Non maskable interrupts are always acknowledged except dur
389. interfaces is shown below For details refer to CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL I O CHAPTER 17 3 WIRE SERIAL I O MODE and CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Function UART1 IOE1 UART2I IOE2 Operation stop mode Asynchronous serial interface mode 3 wire serial I O mode Y Fixed to MSB 2 bus modeNote Note Only in the u PD784225Y Subseries User s Manual U12697EJAV1UD 41 CHAPTER 1 OVERVIEW 1 6 Differences Between uPD784225 Subseries Products and uPD784225Y Subseries Products Product Internal ROM uPD784224 uPD784224Y 96 KB mask ROM uPD784225 uPD784225Y 128 KB mask ROM uPD78F4225 uPD78F4225Y 128 KB flash memory Internal RAM 3 584 bytes 4 352 bytes Power supply voltage Vpp 1 8 to 5 5 V Vpp 1 9 to 5 5 V Internal memory size switching register IMS Note None Provided TEST pin Provided None VPP pin None Provided Note The internal flash memory capacity and internal RAM capacity can be changed with the internal memory size switching register IMS 42 User s Manual U12697EJ4V1UD CHAPTER 2 PIN FUNCTIONS 2 1 Pin Function List 1 Port pins 1 2 Alternate Function Function INTPO Port 0 PO P01 PO INTP2 NMI Input output can be specified in 1 bit units Regardless of whether the input or output mode is specif
390. interval time Remarks n Number of interval timer operations 220 User s Manual U12697EJ4V1UD CHAPTER 12 WATCHDOG TIMER The watchdog timer detects inadvertent program loops Program or system errors are detected by the generation of watchdog timer interrupts Therefore at each location in the program the instruction that clears the watchdog timer starts the count within a constant time is input Ifthe watchdog timer overflows without executing the instruction that clears the watchdog timer within the set period a watchdog timer interrupt INTWDT is generated to signal a program error 12 1 Configuration Figure 12 1 is a block diagram of the watchdog timer Figure 12 1 Block Diagram of Watchdog Timer Watchdog timer fcik 1 2 1 020 foux 219 INTWDT Selector Clear signal 217 Note Write 1 to bit 7 RUN of the watchdog timer mode register WDM Remark Internal system clock fxx to fxx 8 User s Manual U12697EJ4V1UD 221 CHAPTER 12 WATCHDOG TIMER 12 2 Control Register Watchdog timer mode register WDM The WDM is the 8 bit register that controls watchdog timer operation To prevent the watchdog timer from erroneously clearing this register due to an inadvertent program loop this register is only written by a special instruction This special instruction has a special code format 4 bytes in the MOV WDM byte instruction Writ
391. ion x 2 channels Real time output port by combining with the timer counters two stepper motors can be independently controlled Clock frequency division function Clock output function Select from fxx 2 22 fxx 23 fxx 24 fxx 25 26 fxx 27 fxr Buzzer output function Select from fxx 210 211 212 fxx 213 Power supply voltage Vpp 1 8 to 5 5 V uPD784224 784225 784224Y 784225Y Vpp 1 9 to 5 5 V uPD78F4225 78F4225Y Note Only in the u PD784225Y Subseries User s Manual U12697EJAV1UD 33 CHAPTER 1 OVERVIEW 1 2 Ordering Information 1 uPD784225 Subseries Part Number Package Internal ROM UPD784224GC xxx 8BT 80 pin plastic QFP 14 x 14 Mask ROM UPD784224GK xxx 9EU 80 pin plastic TQFP fine pitch 12 x 12 Mask ROM UPD784225GC xxx 8BT 80 pin plastic QFP 14 x 14 Mask ROM UPD784225GK xxx 9EU 80 pin plastic TQFP fine pitch 12 x 12 Mask ROM UPD78F4225GC 8BT 80 pin plastic QFP 14 x 14 Flash memory UPD78F4225GK 9EU 80 pin plastic TQFP fine pitch 12 x 12 Flash memory UPD784224GC xxx 8BT A 80 pin plastic QFP 14 x 14 Mask ROM UPD784224GK xxx 9EU A 80 pin plastic TQFP fine pitch 12 x 12 Mask ROM UPD784225GC xxx 8BT A 80 pin plastic QFP 14 x 14 Mask ROM UPD784225GK xxx 9EU A 80 pin plastic TQFP fine pitch 12 x 12 Mask ROM UPD78F4225GC 8BT A 80 pin plastic QFP 14 x 14 Flash memory UPD78F4225GK 9EU A 80 pin plastic TQFP fine pitch 12 x 12 Flash memory Remarks 1
392. is entered Enabling the acknowledgment of interrupt requests is controlled by the interrupt mask flags that correspond to each interrupt request and the priority of each interrupt This flag is set to 1 by executing the EI instruction and is reset to 0 by executing the DI instruction or by interrupt acknowledgement 4 Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow to bit 3 this flag is set to 1 Otherwise the flag is reset to 0 This flag is used when the ADJBA and ADJBS instructions are executed 5 Register set selection flag RSS This flag sets the general purpose registers that function as X A C and B and the general purpose register pairs 16 bits that function as AX and BC This flag is used to maintain compatibility with the 78K Ill Series Always set this flag to 0 except when using a 78K lll Series program 6 Zero flag Z This flag indicates that the operation result is O If the operation result is 0 this flag is set to 1 Otherwise it is reset to 0 The state of the Z flag can be tested by a conditional branch instruction 7 Sign flag S This flag indicates that the MSB in the operation result is 1 The flag is set to 1 when the MSB of the operation result is 1 If 0 the flag is reset to 0 The S flag state can be tested by a conditional branch instruction 8 Register bank selection flags RBSO to RBS2 This is a 3 bit flag that selects one of the eight register banks regis
393. is the reference power input pin of the D A converter If the D A converter is not used connect to the Vppo pin 12 This is the analog power supply pin of the A D converter Even if the A D converter is not used always use this pin at the same potential as the Vppo pin AVpp functions alternately as the reference voltage input pin of the A D converter 13 AVss This is the ground potential pin of the A D converter Even if the A D converter is not used always use this pin at the same potential as the Vsso pin 14 RESET This is the active low system reset input pin 15 X1 X2 These are the crystal resonator connection pins for main system clock oscillation When an external clock is supplied input this clock signal at X1 and its inverted signal at X2 16 XT1 XT2 These are the crystal resonator connection pins for subsystem clock oscillation When an external clock is supplied input this clock signal at XT1 and its inverted signal at XT2 17 Vppo Vppo is the positive power supply pin for the ports Vop1 is the positive power supply pin for other than the ports and analog pins Always use this pin at the same potential as pin Vppo and 1 18 Vsso Vssi Vsso is the ground potential pin for the ports Vssi is the ground potential pin for other than the ports and analog pins Always use this pin at the same potential as pin Vsso and Vss 19 uPD78F4225 78F4225Y only This is the high
394. is used or TI1 and TI2 are selected as the count clocks of 8 bit timer counters 1 and 2 Serial interface Except 2 bus Operational only when an external input clock is selected as the serial clock mode bus mode Operation disabled External interrupt INTPO to INTP5 Operation enabled Bus lines during ADO to AD7 High impedance external expansion Ag to A19 High impedance ASTB High impedance WR RD High impedance WAIT Holds input status Caution Inthe STOP mode only external interrupts INTPO to INTP5 and the watch timer interrupt INTWT can release the STOP mode and be acknowledged All other interrupt requests are held pending and acknowledged after the STOP mode has been released through NMI input INTPO to INTP5 input or INTWT User s Manual U12697EJAV1UD 481 CHAPTER 24 STANDBY FUNCTION 24 4 2 Releasing STOP mode The STOP mode is released by NMI input INTP0 to INTP5 input the watch timer interrupt INTWT or RESET input An outline of the release sources and operations following release are shown in Table 24 6 Operations following release of the STOP mode are also shown in Figure 24 6 Table 24 6 Releasing STOP Mode and Operation Afier Release Release Source MKNote1 SMNote 2 RESET input IENote 3 State During Release Operation After Release Normal reset operation NMI pin input Not executing a non maskable interrupt service program Ex
395. ived When the stop condition is detected address data are 0000 or 1111 set by the rising Cleared by LRELO 1 edge of the eighth clock When IICEO 1 0 When RESET is input Note This is cleared when a bit manipulation instruction is executed for other bits in IICSO User s Manual U12697EJAV1UD 301 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 4 Format of 2 Bus Status Register 0 IICS0 2 3 COIO Address match detection The address does not match The address matches Clear condition COIO 0 Set condition COIO 1 During start condition detection During stop condition detection Cleared by LRELO 1 When IICEO 1 0 When RESET is input When the received address matches the base address SVAO set at the rising edge of the eighth clock Reception state not the transmission state The SDAO line has high impedance Transmission state The value in the SO latch can be output to the SDAO line valid after the falling edge of the ninth clock of the first byte Clear condition TRCO 0 Set condition TRCO 1 When the stop condition is detected Cleared by LRELO 1 When IICEO 1 0 Cleared by WRELO 1Note When ALDO 0 gt 1 When RESET is input In the master When 1 is output to the first byte LSB transfer direction specification bit In the slave When the start condition is detected When not participating in the communication
396. k Cycle Time CPU Clock Frequency fCPU 570 B 1 Development Tool Configuration chert 601 B 2 Distance Between In Circuit Emulator and Conversion 608 B 3 Target System Connection Conditions 1 u 608 B 4 Target System Connection Conditions 2 u 609 B 5 Package Drawing of EV 9200GC 80 Reference Unit mm 610 B 6 Recommended Board Installation Pattern of EV 9200GC 80 Reference Unit mm 611 B 7 TGK 080SDW Package Drawing Reference Unit 612 User s Manual U12697EJ4V1UD 27 LIST OF TABLES 1 3 Table No Title Page 2 1 Types of Pin I O Circuits and Recommended Connection of Unused Pins 53 3 1 Vector Table Address e E deadeebsteutuntascesenqeccnscacevs secsenadneetsieceigatcaeeuescies seed 63 3 2 Internal RAM Area TiiSI 66 3 3 Settings of Internal Memory Size Switching Register 5 69 3 4 Register BanKkeSel e tfenm a Q u u u ase L A QS paces 72 3 5 Correspondence Between Function Names and Absolute 83 3 6 Special Function Register SFR 8 nennen neret nnns 85 4 1 Glock Generator
397. k and the IE flag is cleared 0 PSWL is also saved to the stack by the PUSH PSW instruction and is restored from the stack by the RETI RETB and POP PSW instructions When context switching or the BRKCS instruction is executed PSWL is saved to a fixed area in the register bank and the IE flag is cleared 0 PSWL is restored from the fixed area in the register bank by the RETCSI or RETCSB instruction RESET input clears PSWL to 00H Figure 22 7 Format of Program Status Word PSWL After reset 00H Symbol 7 6 5 4 3 2 1 0 Used for normal instruction execution Enable or disable interrupt acknowledgment Disabled Enabled Used for normal instruction execution 376 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 4 Software Interrupt Acknowledgment Operations A software interrupt is acknowledged in response to execution of the BRK or BRKCS instruction Software interrupts cannot be disabled 22 4 4 BRK instruction software interrupt acknowledgment operation When the BRK instruction is executed the program status word PSW and program counter PC are saved in that order to the stack the IE flag is cleared 0 the vector table OO3EH 003FH contents are loaded into the lower 16 bits of the PC and 0000B into the higher 4 bits and a branch is performed the start of the service program must be in the base area The RETB instruction must be used to return from a BRK instruction software inter
398. k frequency This signal is only in the uPD784225 452 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 5 2 Access wait An access wait is inserted during low RD and WR signals The low level is lengthened by 1 fxx 80 ns fxx 12 5 MHz per cycle The wait insertion methods are the programmable wait function that automatically inserts a preset number of cycles and the external wait function that is controlled from the outside by the wait signal Wait cycle insertion control is set by the programmable wait control register PWC1 for the 1 MB memory space If an internal ROM or internal RAM is accessed during a high speed fetch a wait is not inserted If accessing an internal SFR a wait is inserted based on the required timing unrelated to this setting If set so that an access has the same number of cycles as for an external ROM a wait is also inserted in an internal ROM access in accordance with the PWC1 setting If there is space that was externally selected to be controlled by the wait signal by PWC1 pin P66 acts as the WAIT signal input pin RESET input makes pin P66 act as an ordinary I O port Figures 23 10 to 23 12 show the bus timing when an access wait is inserted User s Manual U12697EJAV1UD 453 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 10 Read Timing by Access Wait Function 1 2 a Setting 0 wait cycles PW01 PW00 0 0 ADO to AD7 H Z He Data input AST
399. kable interrupt service program and for a certain period after execution of the special instructions shown in 22 9 Therefore a non maskable interrupt will be acknowledged even when the stack pointer SP value is undefined in particular after reset release etc In this case depending on the value of the SP it may happen that the program counter PC and program status word PSW are written to the address of a write inhibited special function register SFR see Table 3 6 in 3 9 Special Function Registers SFRs and the CPU becomes deadlocked or an unexpected signal is output from a pin or the PC and PSW are written to an address at which RAM is not incorporated with the result that the return from the non maskable interrupt service program is not performed normally and a software malfunction occurs Therefore the program following RESET release must be as shown below CSEG AT 0 DW STRT CSEG BASE STRT LOCATION or LOCATION MOVG SP imm24 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 7 Maskable Interrupt Acknowledgment Operation A maskable interrupt can be acknowledged when the interrupt request flag is set 1 and the mask flag for that interrupt is cleared 0 When servicing is performed by a macro service the interrupt is acknowledged and serviced by the macro service immediately In the case of vectored interruption and context switching an interrupt is acknowledged in the interrupt enab
400. l 1 match address MOV CORC 02H Specified channel 2 MOVW CORAL ch2 datal Sets the channel 2 match address MOV CORAH Zch2 datah Sets the channel 2 match address MOV CORC 03H Specified channel 3 MOVW CORAL ch3_datah Sets the channel match address MOV CORAH Zch3 datal Sets the channel match address MOV CORC romcor en Sets 00H when correction is disabled Sets FOH when correction is operated BR NORMAL BR COR ADDRO Specifies the address of the correction program channel 0 BR ADDR1 Specifies the address of the correction program channel 1 BR COR ADDR2 Specifies the address of the correction program channel 2 BR ADDR3 Specifies the address of the correction program channel 3 j two level branch NOMAL instruction Next instruction 3 Setting branch instructions in the CALLT table For the CALLT table that corresponds to each channel in the case of the above program the header addresses for the BR COR_ADDRO BR COR_ADDR1 BR COR_ADDR2 and BR COR_ADDR3 instructions are speci fied ADDRO to ADDRG indicate the address where the correction program is located These instructions are branched by the CALLT instruction and BR instruction into two levels because only the base area can be branched to with CALLT There is no need to branch these instructions into two levels when they are to be attached to the RAM base area with the LOCATION instruction 512 User
401. l function registers SFR each time an interrupt request is generated and a vectored interrupt request is generated when the specified number of transfers have been performed With type C macro servicing notonly are datatransfers performed to two locations in response to a single interrupt request but it is also possible to add output data ring control and a function that automatically adds data to a compare register The entire 1 MB memory space can be used Type C is mainly used with the INTTM1 and INTTM2 interrupts and is used for stepper motor control etc by macro service with RTBL or RTBH CR10 and CR20 used as the SFRs to which data is transferred Counter mode This mode is used to decrement the macro service counter MSC when an interrupt occurs and is used to count the division operation of an interrupt and interrupt generator When MSC is 0 a vectored interrupt can be generated To restart the macro service MSC must be set again MSC is fixed to 16 bits and cannot be used as an 8 bit counter User s Manual U12697EJAV1UD 395 CHAPTER 22 INTERRUPT FUNCTIONS 22 8 3 Basic macro service operation Interrupt requests for which the macro service processing generated by the algorithm shown in Figure 22 11 can be specified are basically serviced in the sequence shown in Figure 22 18 Interrupt requests for which macro service processing can be specified are not affected by the status of the IE flag but are disabled by setting
402. lag Z AC P V CY 79 r byte r lt rAbyte saddr byte saddr saddr Abyte sfr byte sfr sfrAbyte nr rerAr A saddr2 lt A saddr2 r saddr r lt rA saddr saddr r saddr saddr Ar r sfr r lt rAsfr sfr r sfr lt sfrAr saddr saddr saddr saddr saddr A saddrp lt A saddrp A saddrg lt saddrg saddrp A saddrp lt saddrp AA saddrg A saddrg lt saddrg AA A laddr16 A lt A addr16 A lladdr24 A A addr24 laddr16 A addr16 addr16 AA lladdr24 A addr24 addr24 AA A mem A mem mem A mem mem AA User s Manual U12697EJ4V1UD UU Ul Uj UJ U U U U CHAPTER 28 INSTRUCTION OPERATION Mnemonic Operand A byte Operation AVbyte Flag Z AC P V CY 79 r byte r rVbyte saddr byte saddr saddr Vbyte sfr byte sfr sfrVbyte nr rervr A saddr2 lt AV saddr2 r saddr r lt rV saddr saddr r saddr saddr Vr r sfr r rV sfr sfr r sfr sfrVr saddr saddr saddr lt saddr V saddr A saddrp A AV saddrp A saddrg A AV saddrg sa
403. lash Memory Programming Characteristics TA 10 to 40 C Vpp AVpp 1 9 to 5 5 V Vss AVss 0 V VPP 9 7 to 10 3 V 2 2 2 Write erase characteristics Parameter VPP supply voltage Conditions During flash memory programming Vpp supply current When VPP Vera fxx 12 5 MHz VPP supply current When VPP 2 Step erase time Note 1 Overall erase time per area When step erase time 0 2 sNote 2 Write back time Note 3 ms Number of write backs per write back command When write back time 50 msNote 4 times write back command Number of erase write backs times Step write time Note 5 us Overall write time per word When step write time 50 us 1 word 1 byte Note 6 Number of rewrites per area 1 erase 1 write after erase 1 rewriteNote 7 Notes 1 The recommended setting value for the step erase time is 0 2 s 2 The prewrite time before erasure and the erase verify time write back time is not included 3 The recommended setting value for the write back time is 50 ms 4 Write back is executed once by the issuance of the write back command Therefore the retry times must be the maximum value minus the number of commands issued 5 The recommended step write time setting value is 50 us 6 The actual write time per word is 100 us longer The internal verify time during or after a write is not included
404. lding two register sets However be careful and write the program so that implicit descriptions in the program and dynamically changing the RSS bit during program 74 execution always agree Also since a program with RSS 1 cannot be used in a program that uses context switching the portability of the program becomes poor Furthermore since different registers having the same name are used the readability of the program worsens and debugging becomes difficult Therefore when RSS 1 must be used write the program while taking these problems into consideration A register that does not have the RSS bit set can be accessed by specifying the absolute name User s Manual U12697EJAV1UD CHAPTER 3 CPU ARCHITECTURE 3 7 4 Stack pointer SP This is a 24 bit register that saves the starting address of the stack LIFO 00000H to FFFFFFH refer to Figure 3 7 The stack is used for addressing during subroutine processing or interrupt servicing Always set the higher four bits to 0 The contents of the SP are decremented before writing to the stack area and incremented after reading from the stack refer to Figures 3 8 and 3 9 The SP is accessed by special instructions Since the SP contents become undefined when RESET is input always initialize the SP from the initialization program immediately after clearing the reset before acknowledging a subroutine call or interrupt Example Initializing SP MOVG SP Z0FEEOH SP lt OFEEOH
405. lears and starts or free running at valid edge of T100 P35 b Capture compare conirol register 0 CRCO CRC02 CRC01 CRC00 o 0 0 0 CR00 used as compare register CR01 used as compare register c 16 bit timer output control register 0 TOCO OSPT OSPE 04 LVSO LVRO TOC01 TOEO Enables TOO output Reverses output on match between TMO and CROO Specifies initial value of TOO output Reverses output on match between TMO and CRO1 Sets one shot pulse output mode Set to 1 for output Caution Set CR00 and CR01 to a value in the following range 0000H lt CR01 lt 00 lt FFFFH Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the one shot pulse output function For details refer to Figures 8 2 to 8 4 User s Manual U12697EJ4V1UD 171 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 26 Timing of One Shot Pulse Output Operation by Software Trigger Sets 0CH to TMC0 TMO count starts w LL iur da count value 0000 Y 0001 ERN 2 m Y 1XM 2XM 3 set value _ INTTMO1 INTTMOO ci TOO pin output 21 Cautions 1 16 bit timer counter 0 starts operating as soon as TMC02 TMC03 set a value other than 0 0 operation stop mode 2 The software trigger bit 6 OSPT of 16
406. led state when the IE flag is set 1 if the priority of that interrupt is one for which acknowledgment is permitted If maskable interrupt requests are generated simultaneously the interrupt for which the highest priority is specified by the priority specification flag is acknowledged If the interrupts have the same priority specified they are acknowledged in accordance with their default priorities A pending interrupt is acknowledged when a state in which it can be acknowledged is established The interrupt acknowledgment algorithm is shown in Figure 22 11 User s Manual U12697EJAV1UD 383 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 11 Interrupt Acknowledgment Processing Algorithm Interrupt request No Interrupt mask released Yes Macro service Highest default priority among macro service requests No Interrupt enabled state Yes Higher priority No than interrupt currently zi processing execution being serviced Higher priority No than other existing interrupt g requests Highest default No priority among interrupt requests of same priority Interrupt request held pending Yes Context switching Context switching generation Vectored interrupt generation 384 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 7 1 Vectored interrupt When a vectored interrupt maskable in
407. lock TMC26 0 TMC24 0 LVS2 0 LVR2 0 TMC21 1 Moreover set TOE2 to 0 when TO2 is not output externally and TOE2 to 1 when TO2 is output externally 2 Set the external clock and TO2 to fxx 8 or below when selecting the external clock SCKn and TM2 output TO2 for the clock Remark Figures in parentheses apply to operation at fxx 12 5 MHz User s Manual U12697EJAV1UD 287 CHAPTER 17 3 WIRE SERIAL I O MODE Table 17 2 Serial Interface Operation Mode Settings 1 Operation stopped mode Note 1 Note 1 Note 1 CSIMO PM25 P25 26 P26 27 P27 First Shift P25 SIO SDAO P26 SO0 P27 SCKO SCLO CSIEO SCLO1 SCLOO Bit Pin Function Pin Function Pin Function Other than above 2 3 wire serial I O mode 1Note 2 xNote 2 External Setting prohibited P25 SIO SDAO Pin Function S ONote 2 P26 SO0 Pin Function SO0 P27 SCK0 SCL0 Pin Function SCKO input clock CMOS output Note 3 SCKO output Internal clock Other than above Setting prohibited Notes 1 2 When only transmission is used this pin can be used as P25 CMOS I O These pins can be used for port functions 3 Refer to serial operation mode register 0 CSIMO Remark x Don t care 288 User s Manual U12697EJAV1UD CHAPTER 17 3 WIRE SERIAL I O MODE 17 4 Operation 3 wire serial I O has the following two operation mo
408. lock period T Start 33 55 67 1T 301 95T 335 5T Sampling error 0 5T Remark T 5 bit counter source clock period 15 5 320 Baud rate allowable error k 0 x 100 4 8438 272 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 2 Communication operation a Data format The format for transmitting and receiving data is shown in Figure 16 7 Figure 16 7 Format of Asynchronous Serial Interface Transmit Receive Data 1 data frame gt lt Character bits EE Each data frame is composed of the bits outlined below Start bit uses 1 bit e Character bits 7 bits 8 bits Parity Even parity odd parity O parity no parity Stop bit s 1 bit 2 bits Specification of the character bit length inside data frames selection of the parity and selection of the stop bit length are performed with asynchronous serial interface mode register n ASIMn If 7 bits has been selected as the number of character bits only the lower 7 bits bits O to 6 are valid In the case of transmission the most significant bit bit 7 is ignored In the case of reception the most significant bit bit 7 always becomes 0 The setting of the serial transfer rate is performed with the ASIMn and baud rate generator control register n BRGCn If a serial data reception
409. lt a gt b gt c gt d gt e gt f priority d is acknowledged first Remark f in the figure above are arbitrary names used to differentiate between the interrupt requests and macro service requests User s Manual U12697EJ4V1UD 391 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 16 Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting The PRSL bit of IMC is set to 1 and nesting IMC 80H between level 3 interrupts is disabled El a servicing El Interrupt request a Even though interrupts are enabled interrupt Level 3 Interrupt request b is held pending since it has the request b same priority as interrupt request a NS b servicing The PRSL bit of IMC is set to 0 so that a IMC lt 00H level 3 interrupt is acknowledged even during El level 3 interrupt servicing nesting is c servicing possible A d servicing Interrupt request Interrupt Since level 3 interrupt request c is being Level 3 request UN serviced in the interrupt enabled state and Level 3 PRSL 0 interrupt request d which is also level 3 is acknowledged Main routine IMC 00H Interrupt request eNote 1 As interrupt request 3 and f are both of the same level the one with the higher default Level 3 priority f is acknowledged first Interrupt request fNote 2 2 When the interrupt enabled state is set evi 3 f servicing during servicing of interrupt
410. m with a high and low level that exceed 2 cycles of the CPU clock for the count clock When reading TM1 and TM2 in cascade connection mode to avoid reading while the count is changing take measures such as obtaining a count match by reading twice using software User s Manual U12697EJAV1UD 199 CHAPTER 10 8 BIT TIMERS 5 6 10 1 Functions 8 bit timers 5 and 6 TM5 TM6 have the following two modes Mode using 8 bit timers 5 and 6 TM5 TM6 alone discrete mode Mode using 8 bit timers 5 and 6 connected in cascade 16 bit resolution cascade connection mode These two modes are described next 1 Mode using 8 bit timers 5 and 6 alone discrete mode The timer operates as an 8 bit timer with the following function Interval timer 2 Mode using 8 bit timers 5 and 6 connected in cascade 16 bit resolution cascade connection mode The timer operates as a 16 bit timer connected in cascade with the following functions Interval timer with 16 bit resolution 200 User s Manual U12697EJAV1UD CHAPTER 10 8 BIT TIMERS 5 6 10 2 Configuration 8 bit timers 5 and 6 include the following hardware Table 10 1 Configuration of 8 Bit Timers 5 and 6 Item Configuration Timer counter 8 bit x 2 TM5 TM6 Register 8 bit x 2 CR50 CR60 Control register 8 bit timer mode control register 5 TMC5 8 bit timer mode control register 6 TMC6 Prescaler mode register 5 PRM5 Prescaler mode register 6 PRM6 Fig
411. mal operation starts The difference from the normal reset operation is the data memory saves the contents before setting the IDLE mode User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION 24 6 Check Items When Using STOP or IDLE Mode mode The following points must be checked to decrease the current consumption when using the STOP mode or IDLE 1 Is the output level of each output pin appropriate The appropriate output level of each pin differs depending on the circuit in the next stage Select the output level so that the current consumption is minimized e If a high level is output when the input impedance of the circuit in the next stage is low current flows from the power source to the port and the current consumption increases This occurs when the circuit in the next stage is for example a CMOS IC When the power supply is turned off the input impedance of a CMOS IC becomes low To suppress the current consumption and not negatively affect the reliability of the CMOS IC output a low level If a high level is output latch up results when the power supply is applied again Depending on the circuit in the next stage the current consumption sometimes increases when a low level is input In this case output a high level or high impedance to reduce the current consumption When the circuit in the next stage is a CMOS IC if the output is high impedance when power is supplied to the CMOS IC the current consu
412. mark 1 2 User s Manual U12697EJ4V1UD 189 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 6 Timing of Interval Timer Operation 1 3 a Basic operation TMn count value X N X 00H X o1HX Count starts CRn0 N INTTMn TER E TOn Clear _ Interrupt request acknowledgement Interval time Interval time Remarks 1 Interval time N 1 xt N 00H to FFH 2 1 2 190 User s Manual U12697EJAV1UD Interval time CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 6 Timing of Interval Timer Operation 2 3 b When CRn0 00H Count clock UUU tT IYI T P R M m TMn 00H OOH OOH 1 l 1 CRn0 QOH OOH l teen 5 1 34 nrm LE LELILI LS Interval time c When CRn0 FFH t i LI TII l l Jo EH rrujood LEH FFH 00H l l INTTMn 1 A A Interrupt request acknowledgement Interrupt request RENE uu 1 l Interval time Remark n 1 2 User s Manual U12697EJAV1UD 191 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 Figure 9 6 Timing of Interval Timer Operation 3 3 d Operated by CRn0 transition M lt N Count clock 1 1 1 1 TM N oH m N FrijorH l 1 CRn0 M I I I
413. masked 8 for Standby interrupt c Wai 9 interrup 2 22 A Wait for RESET input stable RESET input oscillation Notes 1 Only unmasked interrupt requests 2 When INTPO to INTP5 and the watch timer interrupt INTWT are not masked Remark NMlis only valid with external input The watchdog timer cannot be used for the release of standby HALT mode STOP mode IDLE mode User s Manual U12697EJ4V1UD 464 CHAPTER 24 STANDBY FUNCTION 24 2 Control Registers 1 Standby control register STBC The STBC register sets the STOP mode and selects the internal system clock To prevent the standby mode from accidentally being entered due to an inadvertent program loop this register can only be written by a special instruction This special instruction is MOV STBC byte which has a special code structure 4 bytes This register can only be written when the third and fourth byte opcodes are mutual 1 s complements If the third and fourth byte opcodes are not mutual 1 s complements the register is not written and an operand error interrupt is generated In this case the return address that is saved on the stack is the address of the instruction that caused the error Therefore the address that caused the error can be determined from the return address saved on the stack If the RETB instruction is used to simply return from an operand error an infinite loop occurs Since an operand error interrupt is generated only when the p
414. mber of data transfers The lower 8 bits of the SFR that is the transfer destination is written to the timer SFR pointer TSFRP and data SFR pointer DSFRP The macro service channel that stores these pointers and counters is located in internal RAM space addresses to OFEFFH when the LOCATION OH instruction is executed or 0FFE00H to OFFEFFH when the LOCATION OFH instruction is executed The macro service channel is indicated by the channel pointer as shown in Figure 22 31 In the channel pointer the lower 8 bits of the address are written to the macro service counter in the macro service channel User s Manual U12697EJAV1UD 417 CHAPTER 22 INTERRUPT FUNCTIONS Higher addresses Macro service channel Macro service control word Lower addresses Figure 22 31 Macro Service Channel 1 2 No ring control Bi 1 Macro service Bits 81013 counter MSC Bits 0 to 7 Timer SFR pointer TSFRP TSFR Bits 16 to 23 Note Timer macro service pointer MPT BiS 8 10 13 Bits 0 to 7 Data SFR pointer DSFRP DSFR _ Timer buffer area Bits 16 to 23 Note Data macro service pointer MPD Bits 8 to 15 Bits 0 to 7 Channel pointer Mode register Data buffer area Macro service buffer address macro service pointer Note Bits 20 to 23 must be set to 0 418 User s Manual U12697EJ4V
415. mbination with the assembler package and device file sold separately Caution on using in PC environment Although the C compiler package is a DOS based application it can be used in the Windows environment by using the Project Manager included in the assembler package on Windows Part number uSxxxxCC78K4 DF784225Note Device file File containing device specific information Use this in combination with the tools sold separately RA78K4 CC78K4 SM78KA ID78K4 NS ID78K4 The supported OS and host machine differ depending on the tool combinations Part number uSxxxxDF784225 CC78K4 L C library source file Function source file configuring the object library included in the C compiler package This is required when changing the object library included in the C compiler package to accord with the user s specifications Because this is a source file the operating environment does not depend on the OS Part number uSxxxxCC78K4 L Note The DF784225 can be used commonly for all the RA78K4 CC78K4 SM78K4 ID78K4 NS and ID78K4 User s Manual U12697EJAV1UD 603 APPENDIX DEVELOPMENT TOOLS Remark The xxxx part number differs depending on the host machine and operating system used LSxxxxSP78K4 AB17 BB17 USxxxxRA78K4 USxXxxxCC78K4 PC 9800 series IBM PC AT compatibles Host Machine PC 9800 series IBM PC AT compatibles Japanese Windows English Windows Japanese Window
416. mem2 bit User s Manual U12697EJ4V1UD 539 CHAPTER 28 INSTRUCTION OPERATION Mnemonic Operand Bytes CY saddr bit Operation CY saddr bit Flag s Z AC P V CY CY sfr bit CY lt CY gt sfr bit CY X bit CY CY xv X bit CY A bit CY CY xv A bit CY PSWL bit CY CY v PSWL bit CY PSWH bit CY CY v PSWh bit CY laddr16 bit CY CY xv laddr16 bit CY laddr24 bit CY CY lladdr24 bit N N N N N N CY mem2 bit CY lt CY v mem2 bit saddr bit ied saddr bit saddr bit sfr bit sfr bit sfr bit X bit X bit X bit A bit A bit A bit PSWL bit PSWL bit PSWL bit PSWH bit PSWH bit lt PSWh bit laddr16 bit laddr16 bit addr16 bit lladdr24 bit lladdr24 bit lt laddr24 bit N N N mem2 bit mem2 bit mem2 bit CY CY lt CY sadar bit saddr bit 1 sfr bit sfr bit 1 X bit X bit 1 A bit A bit 1 PSWL bit PSWL bit lt 1 PSWH bit PSWh bit lt 1 laddr16 bit laddr16 bit 1 lladdr24 bit lladdr24 bit lt 1 N N Q NO dw N 2 6 2 6 1 _ CY 1 sadar bit saddr bit 0 sfr bit sfr bit 0 X bit
417. memory manipulation instruction RESET input sets ASIS1 and ASIS2 to OOH Figure 16 4 Format of Asynchronous Serial Interface Status Registers 1 and 2 ASIS1 ASIS2 Address OFF72H OFF73H After reset 00H R W Symbol 6 5 4 3 3 Q 0 Parity error not generated Parity error generated when parity of transmit data does not match Framing error flag Framing error not generated Framing error generatedNote 1 when stop bit s is not detected OVEn Overrun error flag Overrun error not generated Overrun error generatedNote 2 When next receive operation is completed before data from receive buffer register is read Notes 1 Even if the stop bit length has been set to 2 bits with bit 2 SLn of asynchronous serial interface mode register n ASIMn stop bit detection during reception is only 1 bit 2 Be sure to read receive buffer register n RXBn when an overrun error occurs An overrun error is generated each time data is received until RXBn is read Remark 1 2 3 Baud rate generator control 1 2 BRGC1 2 BRGC1 BRGC2 are registers used to set the serial clock of the asynchronous serial interface BRGC1 and BRGC2 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets BRGC1 and BRGC2 to OOH User s Manual U12697EJ4V1UD 263 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 Figure 16 5 Format of Baud Rate Genera
418. mmended 2 Connect the VPP pin directly to Vsso or pull down during normal operation When using a system in which on chip flash memory is overwritten on board connectthe VPP pin via a pull down resistor For the pull down connection use of a resistor with a resistance between 470 and 10 is recommended 3 Connect the pin to Vppo 4 Connect the AVss pin to Vsso Remark Whenthe uPD784225 and 784225Y Subseries are used in applications where the noise generated inside the microcontroller needs to be reduced the implementation of noise reduction measures such as supplying voltage to and Vpni individually and connecting Vsso and Vssi to different ground lines is recommended Always use and and Vsso Vss at the same potential User s Manual U12697EJ4V1UD CHAPTER 1 OVERVIEW A8 to A19 Address bus P130 P131 Port 13 ADO to AD7 Address data bus PCL Programmable clock ANIO to ANI7 Analog input RD Read strobe ANOO ANO1 Analog output RESET Reset ASCK1 ASCK2 Asynchronous serial clock RTPO to RTP7 Real time output port ASTB Address strobe RxD1 RxD2 Receive data AVpp Analog power supply SCKO to SCK2 Serial clock AVREF1 Analog reference voltage SCLONote 1 Serial clock AVss Analog ground 5 1 Serial data BUZ Buzzer clock SIO to SI2 Serial input EXA External access status output 500 to SO2 Serial output INTPO to INTP5 Interrupt from periphe
419. mory and SFR in LPD784225 are accessed by priority and the ASTB RD and WD signals are not output remaining at the inactive level The output level of the address bus remains at the previous output level The output of the address data bus has a high impedance Except in the 1 MB expansion mode an address for external output is output in the state that masked the higher side of the address set by the program Example 1 When address 54321H is accessed in the program in the 256 KB expansion mode the address that is output becomes 14321H Example 2 When address 67821H is accessed in the program in the 256 KB expansion mode the address that is output becomes 27821H 440 User s Manual U12697EJAV1UD CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 3 0784224 Memory Map 1 2 a When executing the LOCATION OH instruction FFFFFH External 1 External memory Internal ROM i Internal ROM 17FFFH 10000H OFFFFH Internal ROM OFFEOH OFFCFH SFR Internal RAM Internal RAM Internal RAM 0 100 Internal ROM Internal ROM Internal ROM 00000H Single chip mode 256 KB expansion mode 1 MB expansion mode Notes 1 Area having any expanded size in the unshaded parts 2 External SFR area User s Manual U12697EJ4V1UD 441 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23 3 0784224 Memory Map 2 2 b When executing the LOCATION OFH instruction FFFF
420. mounted NP 80GC Emulation probe Probe used to connect the in circuit emulator and the target system This is for an 80 pin plastic QFP GC 8BT type EV 9200GC 80 Conversion socket refer to Figures B 2 and B 3 Conversion socket to connect the NP 80GC and a target system board on which an 80 pin plastic QFP GC 8BT type can be mounted Remarks 1 The NP 80GK and NP 80GC are products made by Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg Co Ltd TEL 81 45 475 4191 2 The TGK 080SDW is a product made by Tokyo Eletech Corporation For further information contact Daimaru Kogyo Ltd Tokyo Electronics Department TEL 81 3 3820 7112 Osaka Electronics Department TEL 81 6 6244 6672 3 The EV 9200GC 80 is sold in sets of 5 4 The TGK 080SDW is sold individually User s Manual U12697EJAV1UD 605 APPENDIX B DEVELOPMENT TOOLS B 3 1 Hardware 2 2 2 When using in circuit emulator IE 784000 R IE 784000 R In circuit emulator The IE 784000 R is an in circuit emulator common to the 78K IV Series and is used in combination with IE 784000 R EM and IE 784225 NS EM1 which are sold separately This in circuit emulator debugs the connected host machine An integrated debugger ID78K4 and device file sold separately are required to enable debugging in C language and structured assembly language at the source program level More efficient debugging and program verific
421. mption of the CMOS IC sometimes increases in this case the CMOS IC overheats and is sometimes destroyed In this case output a suitable level or use pull up or pull down resistors The setting method for the output level differs depending on the port mode e Since the output level is determined by the state of the internal hardware when the port is in the control mode the output level must be set considering the state of the internal hardware The output level can be set by writing to the output latch of the port and the port mode register by software when in the port mode When the port enters the control mode the port mode is changed by simply setting the output level 2 Is the input level to each input pin appropriate Set the voltage level input to each pin within a range from the Vss voltage to the Vpn voltage If a voltage outside 3 of this range is applied not only does the current consumption increase but the reliability of the 0784225 is negatively affected In addition do not increase the middle voltage Are internal pull up resistors needed Unnecessary pull up resistors increase the current consumption and are another cause of device latch up Set the pull up resistors to the mode in which they are used only for the required parts When the parts needing pull up resistors and the parts not needing them are mixed together externally connect the pull up resistors where they are needed and set the
422. n 1 Pulse width measurement with free running counter and one capture register If the edge specified by prescaler mode register 0 PRMO is input to the TIOO P35 pin when 16 bit timer counter 0 TMO is used as a free running counter refer to Figure 8 10 the value of TMO is loaded to 16 bit capture compare register 01 CRO1 and an external interrupt request signal 01 is set The edge is specified by using bits 4 and 5 500 and 501 of prescaler mode register 0 The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected through sampling at the count clock cycle selected by prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected twice Therefore noise with a short pulse width can be eliminated Figure 8 10 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register a 16 bit timer mode control register 0 TMCO 03 02 01 OVFO mco o jo 0 0 0 1 9 0 b Capture compare control register 0 CRCO Free running mode CRC02 CRC01 CRC00 eno o jo jo joo 1 04 o CR00 used as compare register 01 used as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the pulse width measurement function For details refer to Figures 8 2 and 8 3 User s Manual U12697EJAV1UD 159
423. n the first clock pulse is generated after the hold time 2 To fill the undefined area of the SCLO falling edge it is necessary for the device to provide an internal SDAO signal on with at least 300 ns of hold time 3 If the device does not extend the SCLO signal low level hold time tow only the maximum data hold time tup par needs to be satisfied 4 The high speed mode bus be used in a standard mode I C bus system In this case the conditions described below must be satisfied e f the device does not extend the SCLO signal low level hold time tsu Dar 2 250 ns e f the device extends the SCLO signal low level hold time Be sure to transmit the data bit to the SDAO line before the SCLO line is released tRmax tsu 1 000 250 1 250 ns by standard mode 1 bus specification 5 Cb Total capacitance per bus line unit pF User s Manual U12697EJAV1UD 565 CHAPTER 29 ELECTRICAL SPECIFICATIONS 4 Clock Output Operation Ta 40 to 85 C Voo AVpp 1 8 to 5 5 V Vss AVss 0 V Parameter Conditions PCL cycle time 4 5 V lt lt 5 5 V nT 31 250 PCL high low level 4 5 V 5 5 V 0 5T 10 15 615 width PCL rising falling time 4 5 lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 1 8 V lt Voo lt 2 7 V Remark T tcyk 1 fxx fxx Main system clock frequency n Divided frequency ratio set by software in the CPU e Whe
424. n Operation by Hardware Start When Falling Edge Is Specified ADM overwrite ADM overwrite ADCS 1 TRG 1 ADCS 1 TRG 1 Standby Standby Standby A D conversion ANIn status ANIn status ANIm ANIm Note If bit 0 ADCE of the A D converter mode register is not set to 1 the value of the first A D conversion is undefined immediately after A D conversion starts Poll the A D conversion end interrupt request INTAD and discard the first A D conversion result 236 User s Manual U12697EJAV1UD CHAPTER 13 A D CONVERTER 2 A D conversion operation by software start A D conversion of the voltage applied to the analog input pin specified with the A D converter input selected register ADIS is started by setting 0 to bit 6 TRG and 1 to bit 7 ADCS of the A D converter mode register ADM When A D conversion ends the conversion result is saved in the A D conversion result register ADCR and an interrupt request signal INTAD is issued When an A D conversion operation that was started completes the first A D conversion the next A D conversion starts immediately A D conversion operations are performed continuously until new data is written to ADM The A D conversion process will be suspended if ADCS is overwritten during A D conversion and an A D conversion operation for the newly selected analog input channel will be started If during A D conversion data where ADCS is 0 is written to ADM the A
425. n WTIMO 1 extended code received after restart Al A2 4 5 6 7 1 50 0010 010 2 50 0010 110 50 0010 00 A4 11 50 0010x010B A5 50 0010x110B 6 50 0010xx00B 7 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJAV1UD 323 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY d Start Code Data Start Address Data Stop lt 1 gt When WTIMO 0 no address match after restart not an extended code Al A2 A3 4 A1 50 0010x010B A2 50 0010x000B 50 00000x10B 4 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care lt 2 gt When WTIMO 1 no address match after restart not an extended code 3 A4 Al A2 A A5 A1 50 0010x010B A2 50 0010x110B 50 0010xx00B A4 IICS0 00000x10B 1 50 00000001B Remarks A Always generated A Generated only when SPIE0 1 x Don t care 4 Not participating in communication a Start Code Data Data Stop A1 A1 IICSO 00000001B Remarks Generated only when SPIE0 1 324 User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 5 Arbitration failed operation operates as the slave after arbitration fails a When arbitration failed du
426. n be specified in 1 bit units a Port mode These pins function as an 8 bit I O port Input or output can be specified 1 bit units by means of the port 2 mode register Regardless of whether the input mode or output mode is specified pull up resistors can be connected in 1 bit units using pull up resistor option register 2 b Control mode These pins function as the data I O pins clock I O pins clock output pins and buzzer output pins of the serial interface Pins P25 to P27 can be specified as N channel open drain by the port function control register PF2 only in the uPD784225Y Subseries i 510 51 500 501 SDA0 t These pins are the I O pins for serial data in the serial interface ii SCKO SCK1 These pins are the I O pins for the serial clock of the serial interface iii RxD1 TxD1 These pins are the I O pins for serial data in the asynchronous serial interface Note Only in the wPD784225Y Subseries iv ASCK1 This is the input pin for the baud rate clock of the asynchronous serial interface v PCL This is the clock output pin vi BUZ This is the buzzer output pin User s Manual U12697EJ4V1UD CHAPTER 2 PIN FUNCTIONS 4 P30 to P37 Port 3 These pins constitute an 8 bit I O port In addition to I O port pins they also function as timer I O The following operation modes can be specified in 1 bit units a b Port mode These pins function as an 8 bit I O port Input
427. n frequency fxr Subsystem clock oscillation frequency 2 Interval timer The watch timer generates an interrupt request INTTM3 at time intervals specified in advance Table 11 1 Interval Time of Interval Timer Interval Time fxx 12 5 MHz fxx 4 19 MHz 211 x 1 fxx fxr 32 768 kHz 212 x 1 fxx 213 x 1 fxx 214 x 1 fxx 215 x 1 fxx 216 x 1 fxx Remark Main system clock oscillation frequency fxr Subsystem clock oscillation frequency User s Manual U12697EJ4V1UD 215 CHAPTER 11 WATCH TIMER 11 2 Configuration The watch timer includes the following hardware Table 11 2 Configuration of Watch Timer Configuration Counter 5 bits x 1 Prescaler 9 bits x 1 Control register Watch timer mode control register WTM Figure 11 1 Block Diagram of Watch Timer 5 bit counter Clear Selector fxx 2 Selector fxt INTTM3 Selector __ Watch timer mode control register WTM Internal bus Remark Main system clock oscillation frequency fxt Subsystem clock oscillation frequency fw Watch timer clock oscillation frequency 27 or fxr 216 User s Manual U12697EJAV1UD CHAPTER 11 WATCH TIMER 11 3 Watch Timer Control Register Watch timer mode control register WTM This register enables or disables the count clock and operation of the watch timer sets the int
428. n mode of the 16 bit timer and the clear mode output timing and overflow detection of 16 bit timer counter 0 TMO TMCO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets TMCO to 00H Caution 16 bit timer counter 0 TMO starts operating when 02 and TMCO3 are set to values other than 0 0 operation stop mode To stop the operation set TMC02 and TMCOS to 0 0 150 User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 2 Format of 16 Bit Timer Mode Control Register 0 TMC0 Address OFF18H After reset OOH R W Symbol 7 6 5 4 3 TMCO Selection of operation mode clear mode Operation stop TMO is cleared to 0 2 1 Selection of TOO output timing Not affected Generation of interrupt Not generated Free running mode Match between TMO and CR00 or match between TMO and CR01 Match between TM0 and CR00 match between TM0 and CR01 or valid edge of TIOO Clears and starts at valid edge of TIOO Match between TMO and CROO or match between TMO and CRO1 Match between TMO and CROO match between TMO and CR01 or valid edge of TIOO Clears and starts on match between TMO and CROO OVFO Detection of overflow of 16 bit timer counter 0 Overflow Match between TMO and CROO or match between TMO and CRO1 Match between TMO and CROO match between and 01 or valid edge o
429. n of A D u asua acusa nennen nennen stadia aate rasas taataan 226 13 2 Resistance and Capacitance Values for Equivalence Circuits Reference Values 247 14 1 Configuration of D A Converter z u u tede tre rite tp ei ie nA SEE YER E TO E ERE EX ENTE alatas 248 16 1 Differences in Names Between UART1 IOE1 and 2 2 255 16 2 Serial Interface Operation Mode Settings 257 16 3 Configuration of Asynchronous Serial Interface 2 222 000 eene 258 16 4 Relationship Between Main System Clock and Baud Rate 272 28 User s Manual U12697EJ4V1UD LIST OF TABLES 2 3 Table No Title Page 16 5 Causes p ep 277 16 6 Wire Serial VO Config ratlOh cucurrit Reet 279 17 1 3Wire Serial VO Configuration A u s s G eee eine 285 17 2 Serial Interface Operation Mode Settings 288 18 1 FO Bus Mode Config tation l l ll ehe etr eret u Cep ge S ENSE 293 18 2 INTIICO Generation Timing and Wait Control 332 18 3 Definitions of Extended Code Bits u n nie cere die Prater EE eri 334 18 4 Arbitration Generation States and Interrupt Request Generation Timing
430. n released through NMI input INTPO to INTP5 input INTWT 278 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 16 4 3 Wire Serial I O Mode This mode is used to perform 8 bit data transfer with the serial clock SCK1 SCk2 serial output SO1 SO2 and serial input SI1 SI2 lines The 3 wire serial I O mode supports simultaneous transmit receive operations thereby reducing the data transfer processing time The start bit of 8 bit data for serial transfer is fixed as the MSB The 3 wire serial I O mode is effective when connecting peripheral I O or a display controller with an on chip clocked serial interface 16 4 1 Configuration The 3 wire serial I O mode includes the following hardware Figure 16 11 shows the block diagram for the 3 wire serial I O mode Table 16 6 3 Wire Serial I O Configuration Configuration Registers Serial I O shift registers 1 2 5101 S102 Control registers Serial operation mode registers 1 2 CSIM1 CSIM2 User s Manual U12697EJAV1UD 279 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O Figure 16 11 Block Diagram in 3 Wire Serial I O Mode 8 611 512 O SIO1 SIO2 Serial I O shift registers 1 2 Serial clock counter SCK1 SCK2 O Serial clock controller gt 501 502 O lt D lt Interrupt generator Selector Serial I O shift registers 1 a
431. n system clock Remark For the resonator selection and oscillator constant customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation User s Manual U12697EJAV1UD 555 CHAPTER 29 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constants Main system clock Ceramic resonator connection Ta 40 to 85 C Manufacturer Murata Mfg Oscillation Frequency fxx MHz Product Name CSA2 00MG040 Recommended Oscillator Constants Oscillation Voltage Range C1 pf C2 pf MIN V MAX V Oscillation Stabilization Time MAX Tost ms CST2 00MG040 CSA3 00MG CST3 00MGW CSA4 00MG CST4 00MGW CSA6 00MG CST6 00MGW CSA8 00MTZ CST8 00MTW CSA12 0MTZ CST12 0MTW Kyocera PBRC2 00AR A PBRC4 00HR KBR 4 0MKC PBRC8 00HR KBR 8 0MKC PBRC12 50BR FCR4 0MC5 FCR6 0MC5 FCR8 0MC5 Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation Oscillation frequency precision is not guaranteed For applications requiring oscillation frequency precision the oscillation frequency must be adjusted on the implementation circuit For details please contact directly the manufacturer of the resonator you will use 556 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Cha
432. n to the macro service counter in the macro service channel The SFR involved with the access is specified by the SFR pointer SFRP The lower 8 bits of the SFR address are written to SFRP 406 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 24 Type A Macro Service Channel a 1 byte transfers 4 Higher addresses Macro service counter MSC SFR pointer SFRP Macro service buffer 1 MSC 1 Macro service Macro service buffer 2 MSC 2 channel Macro service buffer n MSC n Macro service Channel pointer control word Mode register Lower addresses Macro service buffer address channel pointer macro service counter 1 b 2 byte transfers 7 0 4 Higher addresses Macro service counter MSC SFR pointer SFRP Macro service Higher byte eo punter 1 Lower byte Macro service Macro service _ Higher byte MSC 2 buffer 2 Lower byte i Higher byte 7 MSC n buffer n Lower byte Macro service Channel pointer control word Mode register Lower addresses Macro service buffer address channel pointer macro service counter x 2 1 User s Manual U12697EJAV1UD 407 CHAPTER 22 INTERRUPT FUNCTIONS 3 Example of use of type A An example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in internal RA
433. n using the main system clock n 1 2 4 8 16 32 64 When using the subsystem clock n 1 5 Other Operations Ta 40 to 85 C Voo AVpp 1 8 to 5 5 V Vss AVss 0 V Parameter Conditions NMI high low level width INTP input high low INTPO to INTP5 level width RESET high low level width 566 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS A D Converter Characteristics Ta 40 to 85 C AVpp 1 8 to 5 5 V Vss AVss 0 V Parameter Conditions Resolution Overall errorNotes 1 2 6 25 MHz lt bx lt 12 5 MHz 4 5 V lt Voo lt 5 5 V 3 125 MHz lt fxx lt 6 25 MHz 2 7 V lt 5 5 V AVpp 2 MHz lt fxx lt 3 125 MHz 2 0 V lt Voo lt 5 5 V AVpp 2 MHz 1 8 V lt lt 5 5 V Conversion time tconv 14 Sampling time tsAMP 24 fxx Analog input voltage VIAN AVss Reference voltage AVpp Vpp Resistance between Ravrero A D conversion is not performed AVppo AVss Notes 1 Excludes quantization error 0 2 FSR 2 This value is indicated as a ratio to the full scale value FSR Remark fxx Main system clock frequency D A Converter Characteristics TA 40 to 85 C AVpp 1 8 to 5 5 V Vss AVss 0 V Parameter Conditions Resolution Overall errorNotes 1 2 2
434. n with the assembler package RA78K4 and device file DF784225 sold separately lt Caution on using in PC environment gt This real time OS is a DOS based application With Windows use the RX78K IV at the DOS prompt Part number 78 4 Caution When purchasing the RX78KA fill out the purchase application and sign the license agreement Remark The xxxx and AAAA part numbers vary depending on the host machine and operating system used uSxxxxRX78KA AAAA Product Overview Maximum Number Used During Production Evaluation object Do not use in mass produced products Production object 100 000 1 000 000 10 000 000 Source program Source program for the production object Host Machine Supply Medium PC 9800 series Japanese WindowsNote 3 5 inch 2HD FD IBM PC AT and compatibles Japanese WindowsNete 3 5 inch 2HC FD English WindowsNete HP9000 series 700 HP UX Rel 10 10 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD Solaris Rel 2 5 1 1 4 inch CGMT Note Also operates in DOS environment User s Manual U12697EJ4V1UD 613 APPENDIX D REGISTER INDEX D 1 Register Index A A D conversion result register ADCR 227 A D converter input selection register ADIS 230 A D converter mode register ADM 228 Asynchronous serial interface mode register 1 ASIM1 260 261 267 Asynchronous serial interface mode
435. ncy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales represent
436. nd 2 SIO1 5102 INTCSI1 INTCSI2 TO2 fxx 8 fxx 16 These are 8 bit registers that perform parallel serial conversion and serial transmission reception shift operation in synchronization with the serial clock SIOn is set by an 8 bit memory manipulation instruction When bit 7 CSIEn of serial operation mode register n CSIMn is 1 serial operation can be started by writing reading data to from SlOn During transmission data written to SlOn is output to the serial output pin SOn During reception data is read into SIOn from the serial input pin RESET input sets SIO1 and SIO2 to 00H Caution During atransfer operation do not access SlOn other than access as a transfer start trigger read and write are prohibited when MODEn 0 and MODEn 1 respectively Remark 1 2 280 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 16 4 2 Control registers Serial operation mode registers 1 and 2 CSIM1 CSIM2 CSIM1 and CSIM are used to set the serial clock operation mode and operation enable disable in the 3 wire serial I O mode CSIM1 and SCIM2 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 and CSIM2 to 00H Figure 16 12 Format of Serial Operation Mode Registers 1 and 2 CSIM1 CSIM2 Address OFF91H OFF92H After reset 00H R W Symbol 6 5 4 3 2 1 0 SIOn operation enable disable setting Shift register op
437. nd string instructions The TDE WHL VVP and UUP 24 bit registers operands can be described by DE HL VP and UP However when DE HL VP and UP are described they are handled as TDE WHL VVP and UUP 24 bit registers User s Manual U12697EJ4V1UD 523 CHAPTER 28 INSTRUCTION OPERATION 28 2 List of Operations 1 8 bit data transfer instruction MOV Mnemonic Operand Bytes r byte Operation r byte Flag s Z AC P V CY saddr byte saddr byte sfr byte sfr lt byte laddr16 byte 16 lt byte lladdr24 byte addr24 lt byte nr rer A r Aer A saddr2 A lt saddr2 r saddr r saddr saddr2 A saddr2 A saddr r saddr r A sfr lt sfr sfr r sfr sfr A sfr A sfr r sfr r saddr saddr saddr saddr r laddr16 r addr16 laddr16 r addr16 r r lladdr24 r addr24 aja CO OINI N O N lladdr24 r addr24 r A saddrp A lt saddrp A saddrg lt saddrg lt saddrp saddrp A saddrg A saddrg A a mem A mem A PSWL byte PSW lt byte PSWH byte PSWA lt byte PSWL A PSW lt A PSWH A PS
438. nerated Framing error generatedNote 1 when stop bit s is not detected Overrun error flag Overrun error not generated Overrun error generatedNote 2 When next receive operation is completed before data from receive buffer register is read Notes 1 Even ifthe stop bit length has been set to 2 bits with bit 2 of asynchronous serial interface mode register n ASIMn stop bit detection during reception is only 1 bit 2 Be sure to read receive buffer register n RXBn when an overrun error occurs An overrun error is generated each time data is received until RXBn is read Remark n 1 2 User s Manual U12697EJ4V1UD 269 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 c Baud rate generator control registers 1 and 2 BRGC1 BRGC2 BRGC1 and BRGC2 are set by a 1 bit or 8 bit memory manipulation instruction RESET input sets BRGC1 and BRGC2 to OOH Address OFF76H OFF77H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 BRGCn 0 TPSn2 TPSn1 TPSn0 MDLn3 MDLn2 MDLni MDLn0 5 bit counter source clock selection External clock ASCKn fxx 12 5 MHz fxx 2 6 25 MHz fxx 4 3 13 MHz fxx 8 1 56 MHz fxx 16 781 kHz fxx 32 391 kHz TO1 TM1 output Baud rate generator input clock selection fsck 16 fsck 17 fsck 18 fsck 19 fsck 20 fsck 21 fsck 22 0 0 0 0 0 0 0 0 fsck 23 fsck 24 NI
439. ng A D conversion the A D conversion value will not be obtained as expected because of coupling noise Therefore do not apply a pulse to other analog input pins during A D conversion Input impedance of AVppo pin In the u PD784225 the AVpp can also be used as the reference voltage source and a series resistor string of approximately 46 kQ is connected between the AVpp and AVss pins Therefore if the output impedance of the reference voltage source is high connecting in series a series resistor string between the AVpp and AVss pins will result in a large reference voltage error User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER 7 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the A D converter input selection register ADIS is changed Owing to this there will be cases when the A D conversion result and ADIF that correspond with the pre amended analog input immediately prior to ADM overwriting will be set if the analog input pin is amended during A D conversion It must therefore be noted that the ADIF will be set regardless of whether the A D conversion for the amended analog input has finished or not when ADIF is read immediately after ADIS has been overwritten Moreover if A D conversion is stopped once and then resumed clear ADIF before resuming conversion Figure 13 16 A D Conversion End Interrupt Request Generation Timing ADIS write ADIF is set but ANIm ANIm conversion sta
440. ng restarts 12 3 2 Interrupt priority order The watchdog timer interrupt INTWDT can be specified as either maskable or non maskable according to the interrupt selection control register SNMI setting When writing 0 to bit 1 SWDT of SNMI the watchdog timer interrupt can be used as a non maskable interrupt In addition to INTWDT non maskable interrupts include the interrupt NMI from the NMI pin By setting bit 4 of the watchdog timer mode register WDM the acknowledgment order when INTWDT and NMI are simultaneously generated can be set If acknowledging the NMI is given priority even if INTWDT is generated in an NMI servicing program that is being executed INTWDT is not acknowledged but is acknowledged after the NMI servicing program ends 224 User s Manual U12697EJAV1UD CHAPTER 12 WATCHDOG TIMER 12 4 Cautions 12 4 1 General cautions when using the watchdog timer 1 The watchdog timer is one way to detect an inadvertent program loop but not all the program loops can be detected Therefore in a device that demands particularly high reliability the inadvertent program loop must be detected early not only by the on chip watchdog timer but by an externally attached circuit and when returning to the normal state or while in the stable state processing like stopping the operation must be possible 2 The watchdog timer cannot detect inadvertent program loops in the following cases 1 lt 2 gt lt 3 gt
441. nications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions
442. ning counter Addition of caution to Figure 8 15 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified Addition of caution to Figure 8 17 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with Rising Edge Specified Addition of caution to Figure 8 19 Timing of Pulse Width Measurement by Restarting with Rising Edge Specified Modification of description in 8 4 4 Operation as external event counter Modification of Figure 8 26 Timing of One Shot Pulse Output Operation by Software Trigger User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 621 APPENDIX E REVISION HISTORY Edition 2nd edition 622 Contents Modification of Figure 9 1 Block Diagram of 8 Bit Timer Event Counters 1 and 2 Modification of caution in 1 8 bit timer counters 1 and 2 TM1 TM2 Modification of caution in 2 8 bit compare registers 10 and 20 CR10 CR20 Modification of Figure 9 2 Format of 8 Bit Timer Mode Control Register 1 TMC1 Modification of Figure 9 3 Format of 8 Bit Timer Mode Control Register 2 TMC2 Modification of caution in Figure 9 4 Format of Prescaler Mode Register 1 PRM1 Modification of caution in Figure 9 5 Format of Prescaler Mode Register 2 PRM2 Modification of setting method in 9 4 4 Operation as 8 bit PWM output Modification of Figure 9 8 Timing of PWM Output 2 4 Applied to CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2
443. nly to the wPD784225Y Subseries PU Pull up resistor option register PF Port function control register PM Port mode register RD Port 2 read signal WR Port 2 write signal User s Manual U12697EJAV1UD 113 CHAPTER 5 PORT FUNCTIONS 5 2 4 Port 3 Port is an 8 bit I O port with an output latch The input mode output mode can be specified for the P30 to P37 pins in 1 bit units using the port 3 mode register A pull up resistor can also be connected in 1 bits units via pull up resistor option register 3 regardless of whether the input mode or output mode is specified Port 3 supports timer I O as an alternate function RESET input sets port 3 to the input mode Figures 5 8 and 5 9 show a block diagram of port 3 Figure 5 8 Block Diagram of P30 to P32 and P37 Voo PU30 to PU32 PU37 P ch A WRport Output latch P30 TOO to P30 to P32 P37 gt M P32 TO2 P37 EXA Internal bus PM30 to PM32 PM37 Alternate function PU Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal 114 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS 7 3 a oO c 2 Figure 5 9 Block Diagram of P33 to P36 Voo PU33 to PU36 P ch Alternate function PU PM RD WR _ P33 TI1 Output latch 4 P34 TI2 P33 to P36 P35 TIOO 6
444. nly when the numerical range expressed in two s complement is exceeded Otherwise the result is reset to 0 Specifically the result is the exclusive OR of the carry from the MSB and the carry to the MSB and becomes the flag contents For example in 8 bit arithmetic operations the two s complement range is 80H 128 to 7FH 127 If the operation result is outside this range the flag is set to 1 If inside the range it is reset to 0 Example The action of the overflow flag when an 8 bit addition instruction is executed is described next When 78H 120 and 69H 105 are added the operation result becomes E1H 225 Since the upper limit of two s complement is exceeded the P V flag is setto 1 Inatwo s complement expression E1H becomes 31 78H 120 0111 1000 69H 105 0110 1001 0 1110 0001 31 P V 1 4 Next since the operation result of the addition of the following two negative numbers falls within the two s complement range the P V flag is reset to 0 5 1111 1011 FOH 16 1111 0000 1 1110 1011 21P V 0 4 CY User s Manual U12697EJAV1UD 71 CHAPTER 3 CPU ARCHITECTURE 3 Interrupt request enable flag IE This flag controls the CPU interrupt request acknowledgement If IE is 0 interrupts are disabled and only non maskable interrupts and unmasked macro services can be acknowledged Otherwise everything is disabled If IE is 1 the interrupt enable state
445. nter the standby status by setting 1 to bit 6 TRG and bit 7 ADCS of the A D converter mode register ADM When an external trigger signal P03 is input conversion of the voltage applied to the analog input pin set with ADIS begins The result of conversion will be stored in the A D conversion result register ADCR when the A D conversion operation has finished and an interrupt request signal INTAD will be issued When the A D conversion operation that was started completes the first A D conversion no other A D conversion operation is started unless an external trigger signal is input The A D conversion process will be suspended if ADCS is overwritten during A D conversion and it will enter a standby mode until a new external trigger signal is input The A D conversion process will be restarted from the beginning when an external trigger signal is input once again The A D conversion process will be started when the next external trigger signal is received when ADCS is overwritten with A D conversion in the standby mode If during A D conversion data where ADCS is 0 is written to ADM A D conversion is immediately stopped Caution When is used as the external trigger input P03 specify the valid edge with bits 1 and 2 0 and 1 of the A D converter mode register ADM and set the interrupt mask flag PMK3 to 1 User s Manual U12697EJAV1UD 235 CHAPTER 13 A D CONVERTER Figure 13 6 A D Conversio
446. ntil the valid level is detected twice Therefore noise with a short pulse width can be eliminated Caution If the valid edge of the TI00 P35 pin is specified to be both the rising and falling edges capture compare register 00 CROO cannot perform its capture operation Figure 8 18 Control Register Settings for Pulse Width Measurement by Restarting a 16 bit timer mode control register 0 TMCO 03 02 01 OVFO o Ts b Capture compare control register 0 CRC0 Clears and starts at valid edge of TIOO P35 pin CRC02 CRC01 CRC00 CR00 used as capture register Captures to CR00 at edge reverse to valid edge of TI00 P35 pin CR01 used as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions be used together with the pulse measurement function For details refer to Figures 8 2 and 8 3 User s Manual U12697EJ4V1UD 165 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 19 Timing of Pulse Width Measurement by Restarting with Rising Edge Specified ewe FT TLE LI U LILI LIS LS LL Two countvaue X po pomo yov KDX Koo y _ TIOO pin input eee 0 INTTM01 D2 xt Caution For simplification purposes delay due to noise elimination is not taken into consideration in the capture operation by TI00 pin input and in the interrupt request generation timing in the above figure Fora more accurate picture refe
447. o either RTBL or RTBH can set data in either register In addition if the addresses of either RTBL and RTBH are specified the data in both can be read together Table 6 2 lists the operations for manipulating RTBL and RTBH Figure 6 2 Configuration of Real Time Output Buffer Register Higher 4 bits Lower 4 bits OFF98H RTBL OFF99H C 1 eus Table 6 2 Operation for Manipulating Real Time Output Buffer Registers Operation Mode Manipulated Register ReadingNete 1 WritingNete 2 Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits 4 bits x 2 channels RTBL Invalid RTBL RTBH Invalid 8 bits x 1 channel RTBH RTBL RTBH RTBL Notes 1 Only the bits specified in the real time output port mode can be read When the bits set in the port mode are read zeros are read 2 After setting the real time output port set the output data in RTBL and RTBH until the real time output trigger is generated User s Manual U12697EJAV1UD 137 CHAPTER 6 REAL TIME OUTPUT FUNCTION 6 3 Control Registers 1 The real time output port is controlled by the following two registers Real time output port mode register RTPM Real time output port control register RTPC Real time output port mode register RTPM This register sets the real time output port mode and port mode selection in 1 bit units RTPM is set by a 1 bit or 8 bit memory manipulation instruction RESET input s
448. oO a AJOJN fsck 25 fsck 26 fsck 27 28 k 29 k fsck 30 A Setting prohibited Cautions 1 If a write operation to BRGC1 and BRGC2 is performed during communication the baud rate generator output will become garbled and normal communication will not be achieved Consequently do not write to BRGC1 or BRGC2 during communication 2 Refer to CHAPTER 29 ELECTRICAL SPECIFICATIONS for details of the high low level width of ASCKn when selecting the external clock ASCKn for the source clock of the 5 bit counter 270 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL Cautions 3 Set the 8 bit timer mode control register 1 TMC1 as follows when selecting TO1 for Remarks 1 2 the source clock of the 5 bit counter TMC16 0 LVS1 0 LVR1 0 TMC11 1 Moreover set TOE1 to 0 when TO1 is not output externally and TOE1 to 1 when TO1 is output externally n 1 2 Figures in parentheses apply to operation at fxx 12 5 MHz 3 fsck Source clock of 5 bit counter 4 5 k Value set in MDLn0 to MDLn3 0 lt k lt 14 m Value set in 5 0 to TPSn2 0 lt m lt 5 The transmit receive clock for the baud rate to be generated is the signal obtained by dividing the 5 bit counter source clock Generation of transmit receive clock for baud rate The baud rate is obtained fr
449. oard Overwrite Mode 515 27 3 4 Selecting communication mode J u tiere cts id ec dd Gis ited 516 27 3 2 On board overwrite mode flunctions r 517 27 33 Coniectino Flashprel m 518 CHAPTER 28 INSTRUCTION OPERATION l l l u u J 520 28 1 CONVENTIONS 4 uiia 520 28 2 2 2 GM 524 28 3 Lists of Addressing 5 u uuu u u J 548 CHAPTER 29 ELECTRICAL SPECIFICATIONS J 552 29 1 Electrical Specifications of uPD784224 784225 784224Y and 784225Y 552 29 2 Electrical Specifications of uPD78F4225 and 78 4225 569 29 3 Timing 588 CHAPTER 30 PACKAGE DRAWINGS ILU enm nido Dun 594 CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS 596 APPENDIX A MAJOR DIFFERENCES BETWEEN THE uPD784225 784225Y SUBSERI
450. of wait states n 2 0 580 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 3 Serial Operation Ta 40 to 85 C AVpp 1 9 to 5 5 V Vss AVss 0 V 1 2 a 3 wire serial mode SCK Internal clock output Parameter SCK cycle time Conditions 4 5 V lt lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V SCK high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 8 V lt Voo lt 2 0 V SI setup time to SCK 2 7 V lt Voo lt 5 5 V 1 9 V lt Voo lt 2 7 V SI hold time from SCK SO output delay time from SCKL SO output hold time from SCKT b 3 wire serial I O Parameter SCK cycle time mode SCK External clock input Conditions 4 5 V lt lt 5 5 V 0 5tkcy1 50 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V SCK high low level width 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V SI setup time to SCK 2 7 V lt Voo lt 5 5 V 1 9 V lt Voo lt 2 7 V SI hold time from SCKT SO output delay time from SCKL SO output hold time from SCKT c UART mode Parameter ASCK cycle time Conditions 45 lt
451. om the following equation T Baud rate gm x 16 Hz We 5 bit counter source clock When using a divided main system clock Main system clock fxx When an external clock ASCKn is selected Output frequency of ASCKn When the timer 1 output TO1 is selected Output frequency of TO1 Value set in TPSnO to TPSn2 0 x m lt 5 Value set in MDLnO to MDLn3 0 k lt 14 User s Manual U12697EJAV1UD 271 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 Baud rate capacity error range The baud rate capacity range depends on the number of bits per frame and the counter division ratio 1 16 k Table 16 3 shows the relationship between the main system clock and the baud rate Table 16 6 shows a baud rate allowable error example Table 16 4 Relationship Between Main System Clock and Baud Rate Baud Rate bx 12 5 MHz bx 6 25 MHz fxx 3 00 MHz bps BRGC Value Error BRGC Value Error BRGC Value Error Remark When 1 output is used 150 to 38400 bps is supported during operation at fxx 12 5 MHz Figure 16 6 Baud Rate Allowable Error Considering Sampling Errors When k 0 Ideal sampling point 32T 64T 256 288T 320T 352T Reference timing D7 Clock period T Start High speed clock for which normal reception is enabled Clock period T Start 30 45 60 9 Low speed clock for which normal reception is enabled C
452. omatically saved to PR3 and automatically restored when a RETCS or RETCSB instruction is executed RESET input resets all of the bits to 0 Always write 0 in the bits indicated by 0 in Figure 3 6 The contents of bits indicated by are undefined when read Figure 3 6 Format of Program Status Word PSW Symbol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Each flag is described below 70 User s Manual U12697EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 1 Carry flag CY This is the flag that stores the carry or borrow of an operation result When a shift rotate instruction is executed the shifted out value is stored When a bit manipulation instruction is executed this flag functions as the bit accumulator The CY flag state can be tested by a conditional branch instruction 2 Parity overflow flag P V The P V flag has the following two actions in accordance with the execution of the operation instruction The state of the P V flag can be tested by a conditional branch instruction Parity flag action The results of executing the logical instructions shift rotate instructions and CHKL and CHKLA instructions setto 1 when an even number of bits is set to 1 If the number of bits is odd the result is reset to 0 However for 16 bit shift instructions the parity flag from only the lower 8 bits of the operation result is valid Overflow flag action The result of executing an arithmetic operation instruction is set to 1 o
453. on diagrams in each case Figure 27 3 Connection of Flashpro Ill 3 Wire Serial I O Mode When Using 3 Wire Serial I O 0 Flashpro Ill UPD78F4225Y Vppo AVDD RESET SCK0 SI0 SO0 Vsso Vssi AVss Figure 27 4 Connection of Flashpro Ill in 3 Wire Serial I O Mode When Using Handshake Flashpro Ill HS VPP2 GND Note 1 2 518 uPD78F4225Y Vopo RESET SCKO 510 500 P24 Vsso Vss1 AVss User s Manual U12697EJ4V1UD CHAPTER 27 uPD78F4225 AND uPD78F4225Y PROGRAMMING Figure 27 5 Connection of Flashpro Ill in UART Mode When Using UART1 Flashpro 111 uPD78F4225Y Vppo AVpp RESET RxD1 TxD1 Vsso Vssi AVss Note 1 2 Caution Connect the VPP pin directly Vss or pull down For the pull down connection use of resistors with a resistance between 470 Q and 10 kQ is recommended User s Manual U12697EJ4V1UD 519 CHAPTER 28 INSTRUCTION OPERATION 28 1 Conventions 1 Operand format and descriptions 1 2 r pNote 1 X RO A R1 C R2 B R3 R4 R5 R6 R7 R8 R9 R10 R11 E R12 D R13 L R14 H R15 r1Note 1 X RO A R1 C R2 B R3 R4 R5 R6 R7 r2 R8 R9 R10 R11 E R12 D R13 L R14 H R15 r3 V U T W rp rp Note 2 AX RP0 BC RP1 RP2 RP3 VP RP4 UP RP5 DE RP6 HL RP7 rp1Note 2 AX RP0 BC RP1 RP2 RP3 rp
454. ondition diagrams for the emulation probe conversion socket and conversion adapter are shown below Design the system considering the shape of components etc to be mounted on the target system in accordance with this configuration Figure B 2 Distance Between In Circuit Emulator and Conversion Socket In circuit emulator IE 78K4 NS Target system Emulation board IE 784225 NS EM1 CN2 connection 150 mm Se Emulation probe CN2 NP 80GC NP 80GK Conversion socket EV 9200GC 80 Conversion adapter TGK 080SDW Figure B 3 Target System Connection Conditions 1 Emulation probe Emulation board NP 80GC 1 784225 5 25 mm bic 50 mm 35 mm Conversion socket ee Sa EV 9200GC 80 10 mm 2 Zin 1 p 35 mm SU Target system Remark NP 80GC is a product made by Naito Densei Machida Mfg Co Ltd 608 User s Manual U12697EJAV1UD APPENDIX B DEVELOPMENT TOOLS Figure B 4 Target System Connection Conditions 2 Emulation probe NP 80GK Emulation board IE 784225 NS EM1 11mm Conversion adapter TGK 080SDW Target system Remark NP 80GK is a product made by Naito Densei Machida Mfg Co Ltd TGK 080SDW is a product made by TOKYO ELETECH CORPORATION User s Manual U12697EJAV1UD 609 APPENDIX B DEVELOPMENT TOOLS B 5 Conversion Socket EV 9200GC 80 and Conversion Adapte
455. ontrol register 0 TMCO to 0 0 as soon as the timer operation has been halted The valid edge is specified with bits 4 and 5 of prescaler mode register 0 ES00 ES01 6 Cautions on edge detection 1 When the TIOO TIO1 pin is high level immediately after system reset it may be detected as a rising edge after the first 16 bit timer event counter operation is enabled Bear this in mind when pulling up etc lt 2 gt Regardless of whether interrupt acknowledgement is disabled DI or enabled El the edge of the external input signal is detected at the second clock after the signal is changed TIOO TIO1 pin input Interrupt acknow ledgement status Interrupt disabled 01 Interrupt enabled El LI LI LE LI LJ LJ LILI LI LILI LI LI Edge detection User s Manual U12697EJAV1UD 177 CHAPTER 8 16 BIT TIMER EVENT COUNTER 7 Trigger for one shot pulse The software trigger bit 6 OSPT of 16 bit timer output control register 0 TOC0 1 and the external trigger 00 input are always valid in one shot pulse output mode If the software trigger is used in one shot pulse output mode the TIOO pin cannot be used as a general purpose port pin Therefore fix the TIOO pin to either high level or low level 8 Re triggering one shot pulse a One shot pulse output by software When a one shot pulse is output do not set OSPT to 1 Do not output the one shot pulse again until INTTMOO which oc
456. option register Port 6 supports the address bus function and the control signal output function in external memory expansion mode as alternate functions RESET input sets port 6 to the input mode Figures 5 12 to 5 14 show block diagrams of port 6 120 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS Figure 5 12 Block Diagram of P60 to P63 WRPuo PUO6 RDpuo Vpp amp MMO to MM3 WRpeme PM60 to PM63 2 E 5 5 WR P6 S gt mi P60 A16 to g 5 Output latch P63 A19 P60 to P63 RD e o o o o a o o iD PUO Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal to Bits 0 to of the memory expansion mode register User s Manual U12697EJ4V1UD 121 CHAPTER 5 PORT FUNCTIONS 122 Internal bus Figure 5 13 Block Diagram of P64 P65 and P67 WRPuo PUO6 RDPuo WReme 64 5 Eo PM67 RDpme External expansion mode Timing signal for external expansion Selector RDpe Output latch P64 P65 P67 lt P64 RD P65 WR P67 ASTB PUO Pull up resistor option register PM Port mode register RD Port 6 read signal WR Port 6
457. or Therefore if you want a short oscillation stabilization time consult the manufacturer of the crystal ceramic oscillator OSTS can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets OSTS to 00H Figure 24 4 shows the OSTS format User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Figure 24 4 Format of Oscillation Stabilization Time Specification Register OSTS Address OFFCFH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 External clock selection Crystal ceramic oscillation used External clock used Oscillation stabilization time selection 219 fxx 42 0 ms 218 fxx 21 0 ms 217 fxx 10 5 ms 216 b 5 3 ms 215 fxx 2 6 ms 214 fxx 1 3 ms 213 fxx 0 7 ms 212 fxx 0 4 ms 512 fxx 41 0 us Cautions 1 When using crystal ceramic oscillation always clear the EXTC bit to 0 When the EXTC bit is set to 1 oscillation stops 2 If the STOP mode is used when an external clock is input always set the EXTC bit to 1 and then set the STOP mode Using the STOP mode in the state where the EXTC bit is cleared 0 while the external clock is input may destroy uPD784225 or reduce reliability 3 When the EXTC bit is set to 1 when an external clock is input input to pin X2 a clock that has the inverse phase of the clock input to pin X1 If the EXTC bit is set to 1 uPD784225 only operates with the clock that is input to the X2 pin R
458. or D A converter Positive power supply for A D converter Connect to Ground for A D converter and D A converter Connect to Vsso Positive power supply for ports Ground potential for ports Positive power supply excluding ports Ground potential excluding ports Connect directly to Vsso or pull down IC test pin For the pull down connection use of a resistor with a resistance between 470 and 10 kQ is recommended Flash memory programming mode setting High voltage application pin during program write verify Connect via a pull down resistor in flash memory programming mode For the pull down connection use of a resistor with a resistance between 470 Q and 10 kQ is recommended Note The VPP pin is provided only in the uPD78F4225 and 78F4225Y 46 User s Manual U12697EJ4V1UD CHAPTER 2 PIN FUNCTIONS 2 2 Pin Function Description 1 2 P00 to P05 Port 0 These pins constitute 6 bit I O port In addition to I O port pins they also function as external interrupt request inputs The following operation modes can be specified in 1 bit units a Port mode These pins function as a 6 bit I O port Input or output can be specified in 1 bit units by means of the port 0 mode register Regardless of whether the input mode or output mode is specified pull up resistors can be connected in 1 bit units using pull up resistor option register 0 b Control mode These pin
459. or output can be specified in 1 bit units by means of the port 3 mode register Regardless of whether the input mode or output mode is specified pull up resistors can be connected in 1 bit units using pull up resistor option register 3 Control mode These pins function as timer I O i TI00 This is the external clock input pin to the 16 bit timer event counter This is also used as the pin for capture trigger signal input to capture compare registers 00 and 01 ii 01 This is the pin for capture trigger signal input to capture compare register 00 iii TH 2 These are pins for external clock input to the 8 bit timer counter iv TOO to TO2 These are timer output pins 5 P40 to P47 Port 4 These pins constitute an 8 bit I O port In addition to I O port pins they also function as an address data bus LEDs can be directly driven The following operation modes can be specified in 1 bit units a b Port mode These pins function as 8 bit I O port Input or output can be specified in 1 bit units by means of the port 4 mode register When used as an input port pull up resistors can be connected in 8 bit units with bit 4 PUO4 of the pull up resistor option register Control mode These pins function as the lower address data bus pins ADO to AD7 when in the external memory expansion mode If PUO4 1 pull up resistors can be connected User s Manual U12697EJAV1UD 49 CHAPTER 2 PIN FUNCTIONS 6
460. ore the change the timer must be restarted after CR50 and CR60 change Figure 10 10 Timing After Compare Register Changes During Timer Counting CR50 CR60 N X TM5 TM6 count value X 1 E 7 0000H 0001H 0002H Caution Except when the TI5 TI6 input is selected always set TCE5 0 TCE6 0 before setting the STOP mode Remark N gt X gt M 3 TM5 TM6 read out during timer operation Since reading out TM5 and TM6 during operation occurs while the selected clock is temporarily stopped select a high or low level waveform that is longer than the selected clock When reading TM5 and TM6 in cascade connection mode to avoid reading while the count is changing take measures such as obtaining a count match by reading twice using software 214 User s Manual U12697EJAV1UD CHAPTER 11 WATCH TIMER 11 1 Function The watch timer has the following functions Watch timer nterval timer The watch timer and interval timer functions can be used at the same time 1 Watch timer The watch timer generates an interrupt request INTWT at time intervals of 214 fw or 25 by using the main system clock of 4 19 MHz or subsystem clock of 32 768 kHz Caution A time interval of 0 5 second cannot be generated by the 12 5 MHz main system clock Use the 32 768 kHz subsystem clock to generate the 0 5 second time interval Remark fw Watch timer clock oscillation frequency fxx 27 or fxr x Main system clock oscillatio
461. oscillation frequency 2 x Don t care 2 Oscillation mode selection register CC This register specifies whether clock output from the main system clock oscillator with the same frequency as the external clock or clock output that is half of the original frequency is used to operate the internal circuits CC is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CC to 00H Figure 4 3 Format of Oscillation Mode Selection Register CC Address OFF7AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 emer o o o o o Main system clock selection Half of original oscillation frequency Through rate clock mode Cautions 1 If the subsystem clock is selected via the standby control mode register STBC the ENMP bit specification becomes invalid 2 The ENMP bit cannot be reset by software This bit is reset by a system reset 94 User s Manual U12697EJ4V1UD CHAPTER 4 CLOCK GENERATOR 3 Clock status register PCS This register is a read only 8 bit register that indicates the CPU clock operation status By reading bit 2 and bits 4 to 7 of PCS the relevant bit of the standby control register STBC can be read PCS is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PCS to 32H Figure 4 4 Format of Clock Status Register PCS Address OFFCEH After reset 32H R Symbol 7 6 5 4 3 2 1 0 SBK Feedback resistor status of subsystem clock 0 Inte
462. otes 1 If WTIMO 1 bit 3 1 in I C bus control register 0 IICCO an interrupt request is generated at the timing of the falling edge of the ninth clock If WTIMO 0 and the slave address of the extended code is received an interrupt request is generated at the timing of the falling edge of the eighth clock 2 When arbitration is possible use the master to set SPIEO 1 Remark SPIEO Bit 5 in 12 bus control register 0 IICCO User s Manual U12697EJAV1UD 335 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 13 Wake up function This is a slave function of the 12 bus and generates an interrupt request INTIICO when the base address and extended code are received When the address does not match an unused interrupt request is not generated and efficient processing is possible When the start condition is detected the wake up standby function is entered Since the master can become a slave in an arbitration failure when a start condition was output the wake up standby function is entered while the address is transmitted However when the stop condition is detected the generation of interrupt requests is enabled or disabled based on the setting of bit 5 SPIEO in I C bus control register 0 IICCO unrelated to the wake up function 336 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 14 Communication reservation When you want the master to communicate after being in
463. ou have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics User s Manual uPD784225 784225Y Subseries 16 8 Bit Single Chip Microcontrollers Hardware uPD784224 uPD784224Y uPD784225 uPD784225Y uPD78F4225 uPD78F4225Y Document U12697EJ4V1UD00 4th edition Date Published August 2005 N CP K NEC Electronics Corporation 1997 2000 2002 Printed in Japan MEMO 2 User s Manual U12697EJ4V1UD NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vit MAX and MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vit MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devi
464. owing hardware Table 13 1 Configuration of A D Converter Item Configuration Analog input 8 channels ANIO to ANI7 Control registers A D converter mode register ADM A D converter input selection register ADIS Registers Successive approximation register SAR A D conversion result register ADCR 226 User s Manual U12697EJAV1UD CHAPTER 13 A D CONVERTER Figure 13 1 Block Diagram of A D Converter ANI0 ANI1 m r T O9 AVoo ANI2 5 Sample amp hold circuit Voltage 18 5 comparator 2 ANI4 3 E E 9 Lo ANI5 ANI6 x tl Successive ANI7 approximation l em O AVss register SAR Controller INTAD Edge Note L 1 Trigger enable A D converter mode register ADM A D converter input selection register ADIS A D conversion result register ADCR Internal bus Note Valid edge specified with bit 3 EGP3 EGN3 of external interrupt rising edge falling edge enable register 0 EGP0 EGN0 Refer to Figure 21 1 Format of External Interrupt Rising Edge Enable Register 0 EGP0 and External Interrupt Falling Edge Enable Register 0 EGN0 User s Manual U12697EJ4V1UD 227 CHAPTER 13 A D CONVERTER 1 2 3 4 5 6 7 8 228 Successive approximation register
465. p8 if A bit 1 PSWL bit addr20 PC lt PC 3 jdisp8 if PSWL bit 1 PSWH bit addr20 PC lt PC 3 jdisp8 if PSWH bit 1 laddr16 bit addr20 PC lt PC 3 jdisp8 if laddr16 bit 1 lladdr24 bit addr20 PC lt PC 3 jdisp8 if addr24 bit 1 mem2 bit addr20 G OO O wl ws GO O PC lt PC 3 jdisp8 if mem2 bit 1 saddr bit addr20 PC lt PC 4Note 2 jdisp8 saddr bit lt 0 if saddr bit 1 sfr bit addr20 PC lt PC 4 jdisp8 sfr bit 0 if sfr bit 1 X bit addr20 PC PC 3 jdisp8 X bit 0 if X bit 1 A bit addr20 PC PC 3 jdisp8 A bit lt 0 if A bit 1 PSWL bit addr20 PC PC 3 jdisp8 if PSW bit 1 PSWL bit lt 0 PSWH bit addr20 PC lt PC 3 jdisp8 if PSWH bit 1 PSWu bit lt 0 laddr16 bit addr20 PC lt PC 3 jdisp8 if laddr16 bit 1 laddr16 bit 0 lladdr24 bit addr20 PC PC 3 jdisp8 if lladdr24 bit 1 lladdr24 bit 0 mem2 bit addr20 PC PC 3 jdisp8 if mem2 bit 1 mem2 bit lt 0 Notes 1 This is used when the number of bytes is three When four it becomes lt PC 4 jdisp8 2 This is used when the number of bytes is four When five it becomes lt PC 5 jdisp8 User s Manual U12697EJ4V1UD 545 CHAPTER 28 INS
466. package is 0 65 mm or more wave soldering can also be performed For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating Remark Products that have the part numbers suffixed by A are lead free products 598 User s Manual U12697EJAV1UD APPENDIX MAJOR DIFFERENCES BETWEEN THE 4PD784225 784225Y SUBSERIES CPU uPD784216A SUBSERIES AND 4PD780058A SUBSERIES Series Name 784225 Subseries 16 bit CPU uUPD784216A Subseries 780058 Subseries 8 bit CPU Minimum instruction execution time When the main system clock is selected 160 ns 12 5 MHz operation 400 ns 5 0 MHz operation When the subsystem clock is selected 61 us 32 768 kHz operation 122 us 32 768 kHz operation Memory space 1 MB 64 KB ports Total 67 86 68 CMOS inputs 8 8 2 CMOS I O 59 72 62 N ch open drain I O 6 4 Pins with added functionsNote Pins with pull up resistors 57 70 66 62 for flash memory versions LED direct drive outputs 16 22 12 Middle voltage pins 6 4 Timer counters 16 bit timer
467. pare register 01 CRO1 and an external interrupt request signal 01 is set The value of TMO is also loaded to 16 bit capture compare register 00 00 when an edge reverse to the one that triggers capturing to CRO1 is input The edge of the TIOO P35 pin is specified by bits 4 and 5 500 and 501 The rising or falling edge can be specified The valid edge of TIOO P35 pin is detected through sampling at the count clock cycle selected by prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected twice Therefore noise with a short pulse width can be eliminated Caution If the valid edge of the TI00 P35 pin is specified to be both the rising and falling edges capture compare register 00 CROO cannot perform its capture operation Figure 8 16 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers a 16 bit timer mode control register 0 TMCO TMC03 02 01 OVFO mole o olo b Capture compare control register 0 CRC0 Free running mode CRC02 CRC01 CRC00 CR00 used as capture register Captures to CR00 at edge reverse to valid edge of TI00 P35 pin CR01 used as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used together with the pulse width measurement function For details refer to Figures 8 2 and 8 3 User s Manual U12697EJ4V1UD 163
468. pare registers 10 and 20 CR10 CR20 is output from TO1 and TO2 Set the width of the active level of the PWM pulse in CR10 and CR20 The active level can be selected by bit 1 TMC11 TMC12 of TMC1 and TMC2 The count clock can be selected by bits 0 to 2 TCLnO to TCLn2 of prescaler mode registers 1 and 2 PRM1 PRM2 The PWM output can be enabled and disabled by bit 0 TOE1 TOE2 of TMC1 and TMC2 1 Basic operation of the PWM output lt Seiting method gt lt 1 gt Set the port latch which also functions as a timer output pin and the port mode register to 0 lt 2 gt Set the active level width in 8 bit compare register n CRn0 lt 3 gt Select the count clock in prescaler mode register n PRMn 4 Setthe active level in bit 1 TMCn1 of TMCn 5 Set bit 0 of TMCn TOEn to 1 to enable timer output 6 f bit 7 TCEn of TMCn is set to 1 counting starts When counting stops set TCEn to 0 PWM output operation 1 When counting starts the PWM output output from TOn outputs the inactive level until an overflow occurs 2 When an overflow occurs the active level is output The active level is output until CRnO and the count of 8 bit timer counter n TMn match 3 The PWM output after CRn and the count value match is the inactive level until an overflow occurs again 4 Steps 2 and 3 repeat until counting stops 5b f counting is stopped by TCEn 0 the PWM output goes to the inactive
469. pecified Count clock A Rising edge detection __ 3 dL CRO01 n INTTM01 Figure 8 15 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified _t gt 1 1 X po X Kor X Kerek Koe X TI00 pin input J I n Mn ee oe _ INTTM01 J 01 pin input i I Value loaded dH 1 dq Nis CROO A INTTM00 ovo x S MEME 00100 7 10000H D1 D2 x t D3 D2 xt 7 10000H D1 D2 1 xt u Note D2 1 Caution For simplification purposes delay due to noise elimination is not taken into consideration in the capture operation by TIOO and TIO1 pin input and in the interrupt request generation timing in the above figure For a more accurate picture refer to Figure 8 14 CR01 Capture Operation with Rising Edge Specified 162 User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 3 Pulse width measurement with free running counter and two capture registers When 16 bit timer counter 0 TM0 is used as a free running counter refer to Figure 8 16 the pulse width of the signal input to the TI00 P35 pin can be measured When the edge specified by bits 4 and 5 ES00 and 501 of prescaler mode register 0 PRMO is input to the TIOO P35 pin the value of TMO is loaded to 16 bit capture com
470. peration as interval timer 16 bit operation Cascade connection 16 bit timer mode By setting bit 4 TMC64 of 8 bit timer mode control register 6 TMC6 to 1 the timer enters the timer mode with 16 bit resolution With the count preset in 8 bit compare registers 50 and 60 CR50 CR60 as the interval the timer operates as an interval timer by repeatedly generating interrupt requests Setting method 1 2 lt 3 gt lt 4 gt Set each register e PRM5 5 selects the count clock TM6 connected in cascade is not used for setting e CRn0O Compare values each compare value can be set from to FFH TMOn Select the clear and start mode when TMn and CRnO match TM5 TMC5 0000xxx0B x Don t care is 6 0001xxx0B x Don t car Setting TCE6 1 for TMC6 and setting TCE5 1 for 8 bit timer mode control register 5 TMC5 starts the count operation If the values of TMn of all timers connected in cascade and CRn0 match INTTM5 of TM5 is generated TM5 and TM6 are cleared to OOH INTTM5 are repeatedly generated at the same interval Cautions 1 Always set the compare register CR50 CR60 after stopping timer operation 2 If the TM6 count value matches CR60 even when used in a cascade connection INTTM6 of TM6 is generated Always mask TM6 in order to disable interrupts 3 Set 5 and TCE6 in TM6 first Set TM5 last 4 Restarting and stopping the count is possible by setting 1 or 0 onl
471. peration disabled Clear Port functionNote Operation enabled Counter operation Serial function port enabled function Transfer operation mode flag Operation mode Transfer start trigger SOn output Transmit receive mode SIOn write Normal output Receive only mode SIOn read Fix to low level Clock selection External clock to SCKn 8 bit timer counter 2 TM2 output TO2 fxx 8 1 56 MHz bo 16 781 kHz Notes 1 When CSIEn 0 SIOn operation stop status pins connected to SIn SOn and SCKn can be used as ports 2 Set the external clock and TO2 to fxx 8 or below when selecting the external clock SCKn and TM2 output TO2 for the clock Remarks 1 1 2 2 Figures in parentheses apply to operation at fxx 12 5 MHz User s Manual U12697EJAV1UD 283 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O b Communication operation The 3 wire serial mode performs data transfer in 8 byte units Data is transmitted and received one byte at a time in synchronization with the serial clock The shift operation of the serial I O shift register n SIOn is performed in synchronization with the falling edge of the serial clock SCKn Transmit data is held in the SOn latch and is output from the SOn pin Receive data input to the SIn pin is latched to SIOn at the rising edge of the SCKn signal SIOn operation is automatically stopped when 8 bit transfer ends and an interrupt r
472. posure limit 3 daysNote after that prebake at 125 C for 20 to 72 hours Wave soldering For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating Remark Products that have the part numbers suffixed by A are lead free products 5 uPD784224YGC xxx 8BT A 80 pin plastic QFP 14 x 14 uPD784225GC xxx 8BT A 80 plastic 14 x 14 uPD784225YGC xxx 8BT A 80 pin plastic QFP 14 x 14 uPD78F4225GC 8BT A 80 pin plastic QFP 14 x 14 uPD78F4225YGC 8BT A 80 plastic QFP 14 14 uPD784224GK xxx 9EU A 80 plastic TQFP fine pitch 12 x 12 uPD784224YGK xxx 9EU A 80 pin plastic TQFP fine pitch 12 x 12 uPD784225YGK xxx 9EU A 80 pin plastic TQFP fine pitch 12 x 12 uPD78F4225GK 9EU A 80 pin plastic TQFP fine pitch 12 x 12 uPD78F4225YGK 9EU A 80 plastic fine pitch 12 x 12 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or IR60 207 3 higher Count Three times or less Exposure limit 7 daysNete after that prebake at 125 C for 20 to 72 hours Wave soldering When the pin pitch of the
473. priority maskable interrupt service program The PRSL bitNete 5 is cleared to 0 while executing an interrupt service program at priority level 3 Acknowledges interrupt requests Executing a maskable interrupt service program with the same priority This excludes executing an interrupt service program in priority level 3 when the PRSL bitNete 5 is cleared to 0 Executing a high priority interrupt Service program Execute the instruction following the MOV STBC byte instruction The interrupt request that released the IDLE mode is held pendingNete 4 Interrupt mask bit in each interrupt request source 2 Macro service enable flag that is in each interrupt request source oP 490 Interrupt enable flag in the program status word PSW Bit in the interrupt mode control register IMC User s Manual U12697EJ4V1UD Holds the IDLE mode The pending interrupt request is acknowledged when acknowledgement is possible CHAPTER 24 STANDBY FUNCTION Figure 24 9 Operations After Releasing IDLE Mode 1 2 1 Interrupt after IDLE mode Main routine MOV STBC byte IDLE mode 2 Reset after IDLE mode Interrupt request gt IDLE mode release Interrupt servicing Main routine MOV STBC byte IDLE mode RESET input Normal reset operations User s Manual U12697EJ4V1UD 491 CHAPTER 24 STANDBY FUNCTION Figure 24 9 Operations After
474. processing for the interrupt request corresponding to that flag The interrupt mask contents are not changed by the start of interrupt servicing etc and are the same as the interrupt mask register contents refer to 22 3 2 Interrupt mask registers MK1 Macro service processing requests are also subject to mask control and macro service requests can also be masked with this flag This flag can be manipulated by software RESET input sets all bits to 1 Interrupt request flag xxIF An interrupt request flag is set 1 by generation of the interrupt request that corresponds to that flag When the interrupt is acknowledged the flag is automatically cleared 0 by hardware This flag can be manipulated by software RESET input sets all bits to 0 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 1 Interrupt Control Register xxICn 1 3 Address OFFEOH to OFFE6H OFFE8H After reset 43H R W om 0 s 2 O WDTIC WDTIF WDTMK WDTISM WDCSE 0 0 WDTPR1 WDTPRO PICO PIFO PMKO PISMO PCSEO 0 0 PPRO1 PPROO PIC1 PIF1 PMK1 PISM1 PCSE1 0 0 PPR11 PPR10 PIC3 PIF3 PMK3 PISM3 PCSE3 0 0 PPR31 PPR30 PIC4 PIF4 PMK4 PISM4 PCSE4 0 0 PPR41 PPR40 PIC5 PIF5 PMK5 PISM5 PCSE5 0 0 PPR51 PPR50 CSIICO CSIIFO CSIMKO CSIISMO CSICSEO 0 0 CSIPRO1 CSIPROO Interrupt request generation No interrupt request interrupt signal is not generated Interrupt request in
475. pt for the peripheral RAM area 2 x Don t care 3 Programmable wait control register 2 PWC2 In the uwPD784225 Subseries wait cycle insertion control can be performed for the entire address space operation using programmable wait control register 1 PWC1 However in the in circuit emulator the address space is partitioned and wait control is performed for each area separately using both the PWC1 and PWC2 registers Consequently when performing programmable debugging using the in circuit emulator wait control must be performed by setting both the PWC1 register and programmable wait control register 2 PWC2 Set as shown in Table 23 3 below Note that the settings in PWC2 and PWC1 except bits 1 and 0 are invalid in the wPD784225 Subseries and therefore have no negative effect Table 23 3 Settings of Program Wait Control Register 2 PWC2 Inserted Wait Cycle uPD784225 Subseries In Circuit Emulator PWC1 PWC1 xx00B xx01B xx10B Low level time input to WAIT pin xx11B User s Manual U12697EJ4V1UD 439 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23 3 Memory Map for External Memory Expansion Figures 23 4 and 23 5 show the memory map during memory expansion Even during memory expansion an external device at the same address as the internal ROM area internal RAM area or SFR area except for the external SFR area OFFDOH to OFFDFH cannot be accessed If these areas are accessed the me
476. quest flag CSIIFO is set User s Manual U12697EJAV1UD 291 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 1 Function Overview 12 Inter IC bus mode supporting multi master This interface communicates with devices that conform to the 12 bus format Eight bit data transfers with multiple devices are performed by the two lines of the serial clock SCLO and the serial data bus SDAO In the I2C bus mode the master can output the start condition data and stop condition on the serial data bus to the slaves The slaves automatically detect the received data by hardware The I C bus control portion of the application program can be simplified by using this function Since SCLO and SDAO become open drain outputs in the I2C bus mode pull up resistors are required on the serial clock line and serial data bus line Cautions 1 If the power to the uPD784225Y is disconnected while uPD784225Y functions are not used I C communication may no longer be possible Even when not being used do not disconnect the power to the 0784225 2 If the 12C bus mode is used set the SCLO P27 and SDAO P25 pins to N channel open drains by setting the port function control register PF2 292 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 1 Serial Bus Configuration Example in 2 Bus Mode Vppo Vppo Master CPU 2 TM Serial data bus CPU 2 DA ave Master CPU 1
477. r a Crystal oscillation b External clock External clock uPD74HCU04 Caution When using a subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the figure above to avoid an adverse effect from wiring capacitance also refer to 4 4 3 Examples of incorrect resonator connection Keep the wiring length as short as possible Donotcross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS1 Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels 98 User s Manual U12697EJAV1UD CHAPTER 4 CLOCK GENERATOR 4 4 3 Examples of incorrect resonator connection Figure 4 8 shows examples of resonators that are connected incorrectly Figure 4 8 Examples of Incorrect Resonator Connection 1 2 a Wiring of connection circuits is too long X2 X1 Vss1 IH Fluctuating high current is too near signal line X2 X1 Vss1 High current Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on
478. r SFR area The special function registers SFRs of the on chip peripheral hardware are mapped to the area from OFFOOH to OFFFFH refer to Figures 3 1 and 3 2 The area from OFFDOH to OFFDFH is mapped as the external SFR area Peripheral I O externally connected in the external memory expansion mode set by the memory expansion mode register MM can be accessed Caution Inthis area do notaccess an address that is not mapped in the SFR area If mistakenly accessed the CPU enters the deadlock state The deadlock state is released only by reset input Remark The addresses here are the addresses only when the LOCATION OH instruction is executed If the LOCATION OFH instruction is executed OF0000H is added to the values here 3 4 3 External SFR area In the products of the uPD784225 Subseries the 16 byte area of the OFFDOH to OFFDFH area during LOCATION OH instruction execution or OFFFDOH to OFFFDFH area during LOCATION OFH instruction execution in the SFR area is mapped as the external SFR area In the external memory expansion mode the address bus and address data bus are used and the externally attached peripheral I O can be accessed Since the external SFR area can be accessed by SFR addressing the features are that peripheral I O operations can be simplified the object size can be reduced and macro service can be used The bus operation when accessing an external SFR area is the same as a normal memory access 3 5 External Memory
479. r TGK 080SDW 1 The package drawing of the conversion socket EV 9200GC 80 and recommended board installation pattern Figure B 5 Package Drawing of EV 9200GC 80 Reference Unit mm D C No 1 pin index G H l EV 9200GC 80 G1E ITEM MILLIMETERS INCHES A 18 0 0 709 B 14 4 0 567 C 14 4 0 567 D 18 0 0 709 E 4 C 2 0 4 C 0 079 F 0 8 0 031 G 6 0 0 236 H 16 0 0 63 18 7 0 736 J 6 0 0 236 K 16 0 0 63 L 18 7 0 736 M 8 2 0 323 N 8 0 0 315 2 5 0 098 P 2 0 0 079 Q 0 35 0 014 R 92 3 90 091 6 1 5 60 059 610 User s Manual U12697EJAV1UD APPENDIX B DEVELOPMENT TOOLS Figure B 6 Recommended Board Installation Pattern of EV 9200GC 80 Reference Unit mm EV 9200GC 80 P1E ITEM MILLIMETERS INCHES A 19 7 0 776 15 0 0 591 0 65 0 02 x 19 12 35 0 05 0 65 0 02 x 19 12 35 0 05 15 0 19 7 6 0 0 05 6 0 0 05 0 35 0 02 J 2 36 0 03 K 2 3 L 1 57 0 03 0 026 0 001 x 0 748 0 486 0 003 0 026 0 201 x 0 748 0 486 0 003 0 591 0 776 0 236 2 003 0 236 2503 0 0142 001 0 093 0 00
480. r end Clocked serial interface OFE16H INTSER1 511 UART reception error INTSR1 511 UART reception end INTCSII CSI1 3 wire transfer end INTST1 ASI1 UART transmission end Asynchronous serial interface clocked serial interface 1 OFE18H OFE1AH OFE1CH INTSER2 ASI2 UART reception error INTSR2 ASI2 UART reception end INTCSI2 CSI2 3 wire transfer end INTST2 ASI2 UART transmission end Asynchronous serial interface clocked serial interface 2 OFE1EH OFE20H OFE22H INTTM3 Reference time interval signal from watch timer Watch timer OFE24H INTTMOO Match signal generation of 16 bit timer register 0 and capture compare register 00 CROO INTTMO 1 Match signal generation of 16 bit timer register 0 and capture compare register 01 CRO1 Timer Counter OFE26H OFE28H INTTM1 Match signal generation of 8 bit timer counter 1 Timer counter 1 OFE2AH INTTM2 Match signal generation of 8 bit timer counter 2 Timer counter 2 OFE2CH INTAD A D converter conversion end A D converter OFE2EH INTTM5 Match signal generation of 8 bit timer counter 5 Timer counter 5 OFE30H INTTM6 Match signal generation of 8 bit timer counter 6 Timer counter 6 OFE32H INTWT Watch timer overflow Note uPD784225Y Subseries only Remarks 1 394 are generated simultaneously 2 ASI As
481. r is performed simply with the RETB instruction an infinite loop will be caused Because the operand error interrupt occurs only in the case of an inadvertent program loop if MOV STBC or byte is described only the correct dedicated instruction is generated in NEC s RA78K4 assembler initialize the system for the program that processes an operand error interrupt Other write instructions such as MOV STBC A AND STBC byte and SET1 STBC 7 are ignored and no operation is performed In other words a write operation to STBC performed and an interrupt such as an operand error interrupt is not generated STBC can be read out any time by a data transfer instruction RESET input sets STBC to 30H Figure 4 2 shows the format of STBC User s Manual U12697EJAV1UD CHAPTER 4 CLOCK GENERATOR Figure 4 2 Format of Standby Control Register STBC Address OFFCOH After reset 30H R W Symbol STBC Cautions 1 When using the STOP mode during external clock input make sure to set the EXTC bit of the oscillation stabilization time specification register OSTS to 1 before setting the STOP mode If the STOP mode is used during external clock input when the EXTC bit of OSTS has been cleared 0 the uPD784225 may be damaged or its reliability may be 7 6 5 4 3 2 1 0 Subsystem clock oscillation control Use oscillator internal feedback resistor is used Stop oscillator internal feedback resistor is not used CPU clock selection fxx 2
482. r table Saving to amp restoring from fixed area in register bank Executed by automatic switching to register bank specified by vector table and branching to service program at address te specified by fixed area in register bank Macro service Hardware firmware Retained Execution of preset service such as data transfer between memory and I O Note The start addresses of all interrupt service programs must be in the base area If the body of a service program cannot be located in the base area a branch instruction to the service program should be written in the base area User s Manual U12697EJAV1UD 359 CHAPTER 22 INTERRUPT FUNCTIONS 22 1 Interrupt Request Sources The uPD784225 has the 28 interrupt request sources shown in Table 22 2 with a vector table allocated to each Table 22 2 Interrupt Request Sources 1 2 Macro Service Vector Control Table Word Address Address Interrupt Default Interrupt Request Generating Control Context Macro Priority Generating Source Unit Register Switching Service Name Type of Interrupt Request Software BRK instruction execution Not Not possible possible BRKCS instruction execution Possible Not possible Operand Invalid operand in MOV STBC Not Not error byte instruction or MOV WDM possible possible byte instruction and LOCATION instruction Non NMI pin input edge detection Edge Not Not maskable detection possible possi
483. r to Figure 8 14 CR01 Capture Operation with Rising Edge Specified 8 4 4 Operation as external event counter The 16 bit timer event counter can be used as an external event counter which counts the number of clock pulses input to the TIOO P35 pin from an external source by using 16 bit timer counter 0 TMO Each time the valid edge specified by prescaler mode register 0 is input to the TI00 P35 pin TMO is incremented To perform a count operation using the TIOO P35 pin input clock specify the TIOO valid edge with bits 0 and 1 of PRMO PRMOO PRMO 1 Set CR00 to a value other than 0000H one pulse count operation is not possible The edge of the TIOO P35 pin is specified by bits 4 and 5 500 and 501 of prescaler mode register 0 PRMO The rising falling or both the rising and falling edges can be specified When using the TIOO pin input as the count clock sampling for valid edge detection is locked by the main system clock fxx and the capture operation is not performed until the valid level is detected twice Therefore noise with a short pulse width can be eliminated 166 User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 20 Control Register Settings in External Event Counter Mode a 16 bit timer mode control register 0 TMC0 TMC03 TMC02 TMC01 OVF0 mco o jo j o o 111 onjo Clears and starts on match between TMO and CROO b Capture compare control register 0 CR
484. racteristics Ta 40 to 85 C Voo AVpp 1 9 to 5 5 V Vss AVss 0 V 2 2 Parameter Conditions Output leakage current Vo 0 V low Output leakage current Vo high Supply voltage Operating 12 5 MHz 5 0 V 10 mode fxx 6 MHz Voo 3 0 V 10 2 MHz Voo 2 0 V 5 HALT mode fxx 12 5 MHz Voo 5 0 V 10 6 MHz Voo 3 0 V 10 2 MHz Voo 2 0 V 5 IDLE mode fxx 12 5 MHz Voo 5 0 V 10 6 MHz Voo 3 0 V 10 2 MHz Voo 2 0 V 5 Operating 32 kHz Voo 5 0 V 10 modeNote fxx 32 kHz 3 0 V 10 32 kHz 2 0 V lt lt 2 7 V 32 kHz 1 9 V lt Voo lt 2 0 V fxx 32 kHz Voo 5 0 V 10 fxx 32 kHz 3 0 V 10 32 kHz 2 0 V lt lt 2 7 V 32 kHz 1 9 V lt Voo lt 2 0 V fxx 32 kHz Voo 5 0 V 10 fxx 32 kHz Voo 3 0 V 10 32 kHz 2 0 V lt lt 2 7 V 32 kHz 1 9 V lt Voo lt 2 0 V Data retention voltage HALT IDLE modes Data retention current STOP mode Voo 2 0 V 5 Voo 5 0 V 10 Pull up resistor Note When the main system clock is stopped and the subsystem clock is operating Remark Unless otherwise specified the characteristics of alternate function pins are the same
485. racteristics Ta 40 to 85 C Vpp AVpp 1 8 to 5 5 V Vss AVss 0 V 1 2 Parameter Conditions Input voltage low 2 2 V lt Voo lt 5 5 V 0 3Vpp 1 8 V lt Voo lt 2 2 V 0 2Vpp P00 to P05 P20 P22 P33 2 2 V lt Voo lt 5 5 V P34 P70 P72 RESET 1 8 V lt Voo lt 2 2 V 0 2Vpp 0 15 P10 to P17 130 131 2 2 V lt Voo lt 5 5 V 0 3Vpp 1 8 V lt Voo lt 2 2 V 0 2Vpp X1 X2 XT1 XT2 2 2 V lt Voo lt 5 5 V 0 2Vpp 1 8 V lt Voo lt 2 2 V 0 1Vpp P25 P27 2 2 V lt Voo lt 5 5 V 0 3Vpp gt 1 8 V lt Voo lt 2 2 V 0 2Vpp Input voltage high 2 2 V lt lt 5 5 V 0 7 1 8 V lt Voo lt 2 2 V 0 8Vop to P05 P20 P22 P33 2 2 V lt Voo lt 5 5 V 0 8Vop P34 P70 P72 RESET 1 8 V Voo lt 2 2 V 0 85Vpp P10 to P17 P130 P131 2 2 V lt Voo lt 5 5 V 0 7Vop 1 8 V lt Voo lt 2 2 V 0 8Vop X1 X2 XT1 XT2 2 2 V lt Voo 5 5 V 0 8Vop 1 8 V lt Voo lt 2 2 V 0 85Vop P25 P27 2 2 V lt Voo lt 5 5 V 0 7Vop 1 8 V lt Voo lt 2 2 V 0 8Vop Output voltage low For pins other than 4 5 V lt Voo lt 5 5 V P40 to P47 P50 to P57 lo 1 6 mANote 2 P40 to P47 P50 to P57 4 5 V Voo 5 5 V lo 8 mANote 2 lo 400 pANote 2 1 8 V lt Von lt 5 5 V Output voltage high lou 1 mANote 2 4 5 V lt Voo
486. rals TEST Test NMI Non maskable interrupt TIOO TIO1 1 TI2 Timer input POO to P05 Port 0 TOO to TO2 Timer output P10 to P17 Port 1 TxD1 TxD2 Transmit data P20 to P27 Port 2 Vppo Power supply P30 to P37 Port 3 VppNote 2 Programming power supply P40 to P47 Port 4 Vsso Vsst Ground P50 to P57 Port 5 WAIT Wait P60 to P67 Port 6 WR Write strobe P70 to P72 Port 7 X1 X2 Crystal Main system clock P120 to P127 Port 12 XT1 T2 Crystal Subsystem clock Notes 1 The SDAO and SCLO pins are provided only for the wPD784225Y Subseries 2 The VPP pin is provided only in the wPD78F4225 and 78F4225Y User s Manual U12697EJ4V1UD 37 CHAPTER 1 OVERVIEW 1 4 Block Diagram uere 0818 j interrup aud rate INTP3 to INTP5 controller ASCK1 SCK1 RxD2 SI2 Timer event n EE TxD2 SO2 TOU counter 16 bits ASCK2 SCK2 Note 1 TH Timer event Clocked SIO SDAO counter 1 8 bits serial 500 TO1 interface SCKO SCLONete 1 TI2 Timer event dam ADO to AD7 TO2 counter 2 8 bits A8 to A15 Timer t A16 to A19 imer even ae counter 5 8 bits Bus I F aD CPU core ROM WAIT Timer event ASTB counter 6 8 bits 7 Port 0 P00 to P05 Watch timer Port 1 P10 to P17 i Watchdog 2 K P20to P27 Pona K gt P30 to P37 RTPO to RTP7 lt Real time Port4 K pao to P47 NMIINTP2 Output port
487. ranted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
488. rding to the number of VPP pulses shown in Table 27 3 Table 27 3 Communication Modes Communication Mode No of Channels Pins Usedete 1 No of Ver Pulses 3 wire serial I O SCKO P27 SCLONete 2 500 26 SIO P25 SDAONete 2 SCK1 ASCK1 P22 SO1 TxD1 P21 SI1 RxD1 P20 SCK2 ASCK2 P72 SO2 TxD2 P71 SI2 RxD2 P70 3 wire serial I O SCKO0 P27 SCLONete 2 handshakeN te 3 500 26 S10 P25 SDAONete 2 P24 BUZ TxD1 SO1 P21 RxD1 SH P20 TxD2 SO2 P71 RxD2 SI2 P70 Notes 1 Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset Therefore if the external devices do not acknowledge the port state immediately after reset handling such as connecting to Voo via a resistor or connecting to Vss via a resistor is required 2 uPD78F4225Y only 3 Other than K standard Caution Select the communication mode by using the number of VPP pulses given in Table 27 3 Remarks 1 The fifth digit from the left in the lot number indicates the standard 2 Handshake mode is the CSI writing mode using P24 This mode is available for PG and FL PR3 3 The standard is applicable only for ES engineering sample products so the operation cannot be guaranteed 516 User s Manual U12697EJAV1UD CHAPTER 27 J4PD78F4225 AND uPD78F4225Y PROGRAMMING Figure 27 2 Format of Communication Mode Selection VPP pulse 10V q VPP Voo Z
489. received after restart Al A2 A3 A4 A5 A6 A1 11 50 0001x110B A2 50 0001xx00B 50 0010x010B A4 50 0010x110B A5 50 0010 00 A6 IICSO 00000001B Remarks Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJAV1UD 319 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY d Start Address Data Start Address Data Stop lt 1 gt When WTIMO 0 no address match after restart not extended code Al A2 A3 A 4 A1 50 0001x110B A2 50 0001x000B 50 00000x10B A4 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care lt 2 gt When WTIMO 1 no address match after restart not extended code Al A2 A3 IN 4 1 50 0001x110B A2 11 50 0001 00 50 00000x10B A4 IICSO 00000001B Remarks A Always generated A Generated only when SPIE0 1 x Don t care 320 User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 3 Slave operation when receiving the extended code a Start Code Data Data Stop lt 1 gt When WTIMO 0 lt 2 gt A1 A2 A3 A4 A1 50 0010x010B A2 50 0010x000B 50 0010 000 4 IICSO 00000001B Remarks Always generated A Generated only when SPIE0 1 x Don t care When WTIMO 1
490. register 0 When using CR01 as compare register The value set to CR01 is always compared with the count value of 16 bit timer counter 0 TM0 When the values of the two match an interrupt request INTTM01 is generated When using CR01 as capture register The valid edge of the TIOO pin can be selected as a capture trigger The valid edge for TIOO is set with prescaler mode register 0 PRMO Table 8 4 shows the conditions that apply when the capture trigger is specified as the valid edge of the TIOO pin Table 8 4 Valid Edge of TIOO Pin and Capture Trigger of CRO1 Valid Edge of TIOO Pin Capture Trigger of CRO1 Falling edge Falling edge Rising edge Rising edge Setting prohibited Setting prohibited Both rising and falling edges Both rising and falling edges CRO01 is set by a 16 bit memory manipulation instruction RESET input sets CRO1 to 0000H Caution Setany value other than 0000H in CRO1 When using the register as an event counter a one pulse count operation is not possible User s Manual U12697EJ4V1UD 149 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 3 Control Registers The following four registers control the 16 bit timer event counter 16 bit timer mode control register 0 TMCO Capture compare control register 0 CRC0 16 bit timer output control register 0 TOCO Prescaler mode register 0 PRMO 1 16 bit timer mode control register 0 TMCO This register specifies the operatio
491. register 2 ASIM2 260 261 267 Asynchronous serial interface status register 1 ASIS1 262 268 Asynchronous serial interface status register 2 ASIS2 262 268 B Baud rate generator control register 1 BRGC1 262 263 269 Baud rate generator control register 2 BRGC2 262 263 269 C Capture compare control register 0 CRC0 152 155 157 Clock output control register 0 CKS 350 351 Clock status register PCS 94 466 D D A conversion setting register 0 DACSO 248 D A conversion setting register 1 DACS1 248 D A converter mode register 0 DAMO 249 D A converter mode register 1 DAM1 249 E External access status enable register EXAE 459 External interrupt falling edge enable register 0 EGNO 356 External interrupt rising edge enable register 0 EGPO 356 1 2 bus control register 0 IICCO 295 296 12 bus status register 0 IICSO 300 In service priority register ISPR 371 Internal memory size switching register IMS 68 513 Interrupt control register ADIC 368 Interrupt mask flag register OH MKOH 369 370 Interrupt mask flag register OL MKOL 369 370 Interrupt mask flag register 1H MK1H 369 370 Interrupt mask flag register 1L MK1L 369 370 Interrupt mode control register IMC 372 Interrupt selection control register SNMI 374 a 614 User s Manual U12697EJ4V1UD APPENDI
492. registers PUO PU2 PU3 PU7 PU12 PUO Port function control register 2 PF2 Note Note Applies only to the PD784225Y Subseries 1 Port mode registers PM2 to PM7 PM12 PM13 These registers are used to set port input output in 1 bit units PMO PM to PM7 12 and 13 are set with a 1 bit 8 bit memory manipulation instruction RESET input sets the port mode registers to FFH When port pins are used as alternate function pins set the port mode registers and output latches according to Table 5 3 Caution Even though port 0 is also used as an external interrupt input when port 0 is not used as an interrupt input pin be sure to set interrupt disabled by using external interrupt rising edge enable register 0 EGPO and external interrupt falling edge enable register 0 EGNO or setting the interrupt enable flag PMKn n 0 to 5 to 1 Otherwise the interrupt request flag is set and unintentional interrupt servicing may be executed when setting ports to output mode and thus changing the output level User s Manual U12697EJAV1UD 129 CHAPTER 5 PORT FUNCTIONS Table 5 3 Port Mode Registers and Output Latch Settings When Using Alternate Functions Alternate Function Alternate Function Pin Name Pin Name Name POO 1 INTPO INTP1 Input P35 P36 TIOO TIO1 Input P02 INTP2 NMI Input P37 EXA Output to P05 INTP3 to INTP5 Input P40 to P47 ADO to AD7 P10 to
493. registers 1 2 TXS1 TXS2 Receive shift registers 1 2 RX1 RX2 Receive buffer registers 1 2 RXB1 RXB2 Control registers Asynchronous serial interface mode registers 1 2 ASIM1 ASIM2 Asynchronous serial interface status registers 1 2 ASIS1 ASIS2 Baud rate generator control registers 1 2 BRGC1 BRGC2 258 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL Figure 16 2 Block Diagram in Asynchronous Serial Interface Mode Internal bus Receive buffer registers 1 2 RXB1 RXB2 Transmit shift registers 1 2 TXS1 TXS2 Receive shift registers 1 2 RX1 RX2 RxD1 RxD2 gt TxD1 TxD2 O lt 1 Receive Transmit Contro INTSR1 control INTST1 parity parity check INTSR2 addition Baud rate generator I I 1 i 5 bit counter x 2 lt 1 fx to fxx 25 Transmission reception Selector tTO I I clock generation 2 ASCK1 ASCK2 User s Manual U12697EJ4V1UD 259 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 O 1 2 3 4 5 260 Transmit shift registers 1 2 TXS1 TXS2 These registers are used to set transmit data Data written to TXS1 and TXS2 is sent as serial data If a data length of 7 bits is specified bits 0 to 6 of the data written to TXS1 and TXS2 are transferred as transmit data Transmission is started by writing data to TXS1 and TXS2 T
494. request f El e servicing pending interrupt request e is acknowledged since PRSL 0 m Notes 1 Low default priority 2 High default priority Remarks 1 to inthe figure above are arbitrary names used to differentiate between the interrupt requests and macro service requests 2 High low default priorities in the figure indicate the relative priority levels of the two interrupt requests 392 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 8 Macro Service Function 22 8 1 Outline of macro service function Macro service is one method of servicing interrupts With anormal interrupt the program counter PC and program status word PSW are saved and the start address of the interrupt service program is loaded into the PC but with macro servicing different processing mainly data transfers is performed instead of this processing This enables interrupt requests to be responded to quickly and moreover since transfer processing is faster than processing by a program the processing time can also be reduced Also since a vectored interrupt is generated after processing has been performed the specified number of times another advantage is that vectored interrupt programs can be simplified Figure 22 17 Differences Between Vectored Interrupt and Macro Service Processing Macro service Macro service Main routine processing Main routine Context Vectored Interrup
495. result register ADCR is read after stopping the A D conversion operation the conversion result may be undefined Therefore be sure to read ADCR before stopping operation of the A D converter 11 Timing that makes the A D conversion result undefined If the timing of the end of A D conversion and the timing of the stop of operation of the A C converter conflict the A D conversion value may be undefined Because of this be sure to read the A D conversion result while the A D converter is in operation Furthermore when reading an A D conversion result after the A D converter operation has stopped be sure to have done so by the time the next conversion result is complete The conversion result read timing is shown in Figures 13 18 and 13 19 below Figure 13 18 Conversion Result Read Timing When Conversion Result Is Undefined A D conversion end A D conversion end ADCR Normal conversion result Undefined value INTAD ADCS Normal conversion A D operation Undefined result read stopped value read Figure 13 19 Conversion Result Read Timing When Conversion Result Is Normal A D conversion end ADCR X Normal conversion result INTAD ADCS operation stopped Normal conversion result read User s Manual U12697EJ4V1UD 245 CHAPTER 13 A D CONVERTER 12 Cautions on board design In order to avoid negative effects from digital circuit noise on the board analog circuits must be placed as far away as po
496. ri lt 4 5 V 1 9 V lt 1 lt 2 7 V Output resistance Ro DACS0 1 55H Reference voltage AVREF1 AVRzr1 current Alpert For only 1 channel Notes 1 Excludes quantization error 0 2 FSR 2 This value is indicated as a ratio to the full scale value FSR 584 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Data Retention Characteristics Ta 40 to 85 C Vpp AVpp 1 9 to 5 5 V Vss 55 0 V Parameter Conditions Data retention voltage STOP mode Data retention current Vpppn 5 0 V 10 Vpppn 2 0 V 5 Vpp rise time Vpo fall time Voo hold time from STOP mode setting STOP release signal input time Oscillation stabilization Crystal resonator 30 wait time Ceramic resonator 5 Input voltage low RESET POO INTPO to PO5 INTP5 0 0 1 Input voltage high 0 9 User s Manual U12697EJ4V1UD 585 CHAPTER 29 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics TA 10 to 40 C Voo AVpp 1 9 to 5 5 V Vss AVss 0 V VPP 9 7 to 10 3 V 1 2 1 Basic characteristics Parameter Conditions Operating frequency 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V Oscillation 4 5 V lt Voo lt 5 5 V Note 1 frequency 94 2 7 V lt Voo lt
497. riggers Eighth or ninth clock of the serial clock set by the WTIMO bitNete e Interrupt request is generated by detecting the stop condition set by the SPIEO bitNete Note WTIMO bit Bit 3 in 12 bus control register 0 IICCO SPIEO bit Bit 4 in 12 bus control register 0 IICCO Serial clock controller In the master mode the clock output to pin SCLO is generated by the sampling clock Serial clock wait controller This circuit controls the wait timing 10 Acknowledge output circuit stop condition detector start condition detector acknowledge detector These circuits output and detect the control signals 11 Data hold time correction circuit This circuit generates the hold time of the data to the falling edge of the serial clock User s Manual U12697EJAV1UD 295 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 3 Control Registers The 12 bus mode is controlled by the following three registers C bus control register 0 IICCO C bus status register 0 IICSO Prescaler mode register 0 for serial clock SPRMO The following registers are also used Serial shift register 0 Slave address register 0 SVAO 1 2 bus control register 0 IICCO The IICCO register enables and disables the 2 bus mode sets the wait timing and sets other 12 bus mode operations IICCO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets IICCO to 296 U
498. ring the transfer of slave address data lt 1 gt When WTIMO 0 Al A2 A3 A4 lt 2 gt A1 A2 A3 A4 50 0101x110B Example Read ALDO during interrupt servicing 50 0001 000 50 0001 000 IICS0 00000001 Remarks A Always generated A Generated only when SPIE0 1 x Don t care When WTIMO 1 T AD6 to ADO D7 to DO D7 to DO ai 2 Al A2 A3 4 A4 50 0101 110 Example Read ALDO during interrupt servicing 50 0001x100B 50 0001xx00B IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJ4V1UD 325 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 326 b When arbitration failed while transmitting an extended code lt 1 gt When WTIMO 0 lt 2 gt Al A2 A3 A4 A1 50 0110x010B Example Read ALDO during interrupt servicing A2 IICSO 0010x000B IICSO 0010x000B 4 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care When WTIMO 1 3 Al A2 A A4 AS A1 50 0110x010B Example Read ALDO during interrupt servicing A2 50 0010x110B IICSO 0010x100B A4 IICSO 0010xx00B IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY
499. rnal feedback resistor is used 1 Internal feedback resistor is not used CK2 CK1 CKO CPU clock operating frequency 0 0 fxx fxx 2 fxx 4 fxx 8 fxt recommended fxr MCK Oscillation status of main system clock 0 Use oscillator 1 Stop oscillator CPU clock status Main system clock operation Subsystem clock operation Caution Timing at which bit 0 CST changes The CPU clock does not switch from the main system clock to the subsystem clock immediately after the standby control register STBC is set but switches after synchronization of both clocks main and subsystem has been detected Consequently CST changes after synchronization detection This is the same as when switching from subsystem clock to main system clock User s Manual U12697EJ4V1UD 95 CHAPTER 4 CLOCK GENERATOR 4 Oscillation stabilization time specification register OSTS This register specifies the operation of the oscillator Either a crystal ceramic resonator or external clock is set by the EXTC bit in OSTS as the clock used The STOP mode can be set even during external clock input only when the EXTC bit is set to 1 OSTS is set by a 1 bit or 8 bit transfer instruction RESET input sets OSTS to 00H Figure 4 5 Format of Oscillation Stabilization Time Specification Register OSTS Address OFFCFH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 EXTC External clock selection Crystal ceramic resonator
500. rocessing specification Processing as vectored interrupt Processing by context switching xxPRn0 Interrupt request priority specification Priority 0 Highest priority Priority 1 Priority 2 Priority 3 User s Manual U12697EJ4V1UD 369 CHAPTER 22 INTERRUPT FUNCTIONS 22 3 2 Interrupt mask registers MK0 MK1 The MKO and MK1 registers are composed of interrupt mask flags MK0 and MK1 are 16 bit registers that can be manipulated in 16 bit units In addition MK0 can be manipulated in 8 bit units as MK0L and MK0H and similarly MK1 can be manipulated as MK1L and MK1H In addition each bit of MK0 and MK1 can be manipulated individually with a bit manipulation instruction in 1 bit units Each interrupt mask flag controls enabling disabling of the corresponding interrupt request When an interrupt mask flag is set 1 acknowledgment of the corresponding interrupt request is disabled When an interrupt mask flag is cleared 0 the corresponding interrupt request can be acknowledged as a vectored interrupt or macro service request Each interrupt mask flag in MKO and MK1 is the same flag as the interrupt mask flag in the interrupt control register MKO and MK1 are provided for blanket control of interrupt masking After RESET input MKO and MK1 are set to FFFFH and all maskable interrupts are disabled 370 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 2 Format of Interrupt
501. rogram inadvertently loops only the correct instruction is generated when MOV STBC byte is specified in the RA78K4 NEC assembler make the program initialize the system Other write instructions i e MOV STBC A STBC byte SET1 STBC 7 are ignored and nothing happens In other words STBC is not written and an interrupt such as an operand error interrupt is not generated STBC can always be read by a data transfer instruction RESET input sets STBC to 30H Figure 24 2 shows the STBC format User s Manual U12697EJ4V1UD 465 CHAPTER 24 STANDBY FUNCTION 466 Figure 24 2 Format of Standby Control Register STBC Address 0FFC0H After reset 30H R W Symbol Cautions 1 7 6 5 4 3 2 1 0 Subsystem clock oscillation control Oscillator operating internal feedback resistors used Oscillator stopped internal feedback resistors not used fxx 2 fxx 4 fxx 8 fxt recommended fxr Main system clock oscillation control Oscillator operating internal feedback resistors used Oscillator stopped internal feedback resistors not used Normal operation mode HALT mode automatically cleared when the HALT mode is released STOP mode automatically cleared when the STOP mode is released IDLE mode automatically cleared when the IDLE mode is released If the STOP mode is used when external clock is input set the STOP mode after setting bit EXTC in the osc
502. rol control by default priority and programmable priority control in accordance with the setting of the priority specification flag In priority control by means of default priority interrupt servicing is performed in accordance with the priority preassigned to each interrupt request default priority refer to Table 22 2 In programmable priority control interrupt requests are divided into four levels according to the setting of the priority specification flag Interrupt requests for which multiple interruption is permitted are shown in Table 22 5 Since the IE flag is cleared 0 automatically when an interrupt is acknowledged when multiple interruption is used the IE flag should be set 1 to enable interrupts by executing the IE instruction in the interrupt service program etc Table 22 5 Multiple Interrupt Servicing Priority of Interrupt Currentl PRSL in y p y ISPR Value IE Flag in PSW Acknowledgeable Maskable Interrupts Being Acknowledged IMC Register No interrupt being 00000000 All macro service requests only acknowledged All maskable interrupts 3 00001000 All macro service requests only All maskable interrupts All macro service requests Maskable interrupts specified as priority 0 1 2 0000x100 All macro service requests only All macro service requests Maskable interrupts specified as priority 0 1 0000xx10 All macro service requests only All macro service requests Maskable inter
503. rom address to EXAL taDEXD Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 0 0 0 Delay time from EXAJ to ASTBL Voo 5 0 V 10 0 5T 20 Voo 3 0 V 10 0 5T 30 Voo 2 0 V 5 0 5T 40 Delay time from to EXAT lExRDS Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 Delay time from WRT to EXAT texwps Voo 5 0 V 10 Voo 3 0 V 10 0 0 0 T T Voo 2 0 V 5 T Delay time from EXAT to ASTBT Remark T 1 fxx fxx Main system clock frequency TEXADR Voo 5 0 V 10 Voo 3 0 V 10 Voo 2 0 V 5 n Number of wait states n 0 578 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 External wait timing 1 2 Parameter Input time from address to WAIT Conditions Voo 5 0 V 10 2 a T 40 Voo 3 0 V 10 2 a T 60 Voo 2 0 V 5 2 a T 300 Input time from ASTBJ to WAITL Voo 5 0 V 10 1 5T 40 Voo 3 0 V 10 1 5T 60 Voo 2 0 V 5 1 5T 260 Hold time from to WAIT Voo 5 0 V 10 0 5 n T4 5 Voo 3 0 V 10 0 5 n T 10 Voo 2 0 V 5 0 5 T 30 Delay time from ASTBI to WAITT ipsrwrH Voo 5 0 V 10 1 5 n T 40 Voo 3 0 V 10 1 5 T 60 Voo 2 0
504. rs Timer event counter Timer counter x 1 Pulse output possible 16 bits Capture compare PPG output register x 2 Square wave output One shot pulse output Timer event counter 1 Timer counter x 1 Pulse output possible 8 bits Compare register x 1 PWM output Square wave output Timer event counter 2 Timer counter x 1 Pulse output possible 8 bits Compare register x 1 PWM output Square wave output Timer 5 Timer counter x 1 8 bits Compare register x 1 Timer 6 Timer counter x 1 8 bits Compare register x 1 Note The pins with added functions are included in the I O pins User s Manual U12697EJAV1UD 39 CHAPTER 1 OVERVIEW a Product Name Serial interfaces 2 2 uUPD784224 784225 78 4225 uPD784224Y uPD784225Y uPD78F4225Y UART IOE 3 wire serial I O 2 channels on chip baud rate generator CSI 2cNote 3 wire serial I O multimaster supporting 12 busNote 1 channel A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Clock output Select from fxx fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 fxx 28 fxx 2 fxr Buzzer output Select from 210 fxx 211 fxx 212 fxx 218 Watch timer 1 channel Watchdog timer channel Standby HALT STOP IDLE modes In the low power consumption mode CPU operation by subsystem clock HALT IDLE mode Interrupts Hardware sources 25 int
505. rt conversion is not complete ADM write ANIn conversion start A D conversion ADCR Remark nz0 1 7 m 0 1 7 Note If bit 0 ADCE of the A D converter mode register is not set to 1 the value of the first A D conversion is undefined immediately after A D conversion starts Take measures such as polling the A D conversion end interrupt request INTAD and discarding the first A D conversion result User s Manual U12697EJAV1UD 243 CHAPTER 13 A D CONVERTER 8 Bit 0 ADCE of A D converter mode register ADM Setting ADCE to 1 allows the value of the first A D conversion immediately after A D conversion operation start to be used 9 Conversion result immediately after A D conversion is started If bit 7 ADCS0 of the A D converter mode register ADM is set to 1 without setting bit 0 ADCE to 1 the value of the first A D conversion is undefined immediately after the A D conversion operation starts Take measures such as polling the A D conversion end interrupt request INTAD and discarding the first conversion result Figure 13 17 Conversion Results Immediately After A D Conversion Is Started A D conversion end A D conversion end A D conversion end ADCR Undefined value Normal conversion result INTAD ADCS A D startup Dummy Reading of conversion result 244 User s Manual U12697EJAV1UD CHAPTER 13 A D CONVERTER 10 Reading A D conversion result register ADCR If the conversion
506. rter 1 eir iereettte a ELAR eb WE ga V Rd Pages 227 13 2 Format of A D Converter Mode Register 230 13 3 Format of A D Converter Input Selection Register 5 231 13 4 Basic Operations of A D Converter 233 13 5 Relationship Between Analog Input Voltage and A D Conversion Result 234 13 6 A D Conversion Operation by Hardware Start When Falling Edge Is Specified 236 22 User s Manual U12697EJ4V1UD LIST OF FIGURES 4 8 Figure No Title Page 13 7 A D Conversion Operation by Software 237 13 8 erige c L X Y 238 13 9 Guartizati D 6 238 18 10 ZerosSCale Emon diee ese ABE EA 239 13211 JFUllESCale Brrr uu ERGS 239 13 12 Integral Linearity Error tugas ret p SSS uQ S ua e hei asia 240 13 13 PDitferential Linearity Errer 2 uiii te teret ta Mace sande 240 13 14 Method to Reduce Current Consumption in Standby 241 19 15 gt Handling oft Analog Input u u l Ll a uu terere eter ter den euo e ese eas 242 13 16 A D Conversion End Interrupt Request Generation Timing 243 13 17 Conversion Results Immediately After A D Conver
507. ru Level 3 Level 2 request s Level 1 servicing s servicing t servicing Interrupt __ request t Fl Multiple acknowledgment of levels 3 to 0 If Level 0 the PRSL bit of the IMC register is set 1 only macro service requests and non maskable interrupts generate nesting beyond this If the PRSL bit of the IMC register is cleared 0 level 3 interrupts can also be nested during level 3 interrupt servicing see Figure 22 16 2 lt 1 gt Interrupt request v Level 0 servicing lt 2 gt Macro service request w Level 3 Even though the interrupt enabled state is set during servicing of level 0 interrupt request u the interrupt request is not Interrupt request __ lt 1 gt acknowledged but held pending even though its priority is 0 However the macro Level 0 lt 2 gt w macro service service request is acknowledged El serviced irrespective of its level even if 2 there is a pending interrupt with a higher v servicing priority level o lt 3 gt Interrupt request y Level 2 x servicing lt 4 gt Interrupt request z Level 2 gt 1 Pending interrupt requests y and z Interrupt request x 4 acknowledged after servicing of interrupt Level 1 request x As interrupt requests y and z 2 have the same priority level interrupt 2 servicing request z which has the higher default priority is acknowledged first irrespective lt 3 4 gt Note 2 o
508. rupt Caution The RETI instruction must not be used to return from a BRK instruction software interrupt 22 4 2 BRKCS instruction software interrupt software context switching acknowledgment operation The context switching function can be initiated by executing the BRKCS instruction The register bank to be used after context switching is specified by the BRKCS instruction operand When the BRKCS instruction is executed the program branches to the start address of the interrupt service program which must be in the base area stored beforehand in the specified register bank and the contents of the program status word PSW and program counter PC are saved in the register bank Figure 22 8 Context Switching Operation by Execution of BRKCS Instruction Register bank 0 to 7 Register bank n n 0 to 7 P Exchange Save Bits 8 to 11 of temporary register Save Register bank switching RBSO RBS2 n 885 lt 0 lt 0 The RETCSB instruction is used to return from a software interrupt generated by the BRKCS instruction The RETCSB instruction must specify the start address of the interrupt service program for when context switching is next performed by the BRKCS instruction This interrupt service program start address must be in the base area Caution The RETCS instruction must not be used to return from a BRKCS instruction software interrupt User s Manual U12697EJAV1UD 377 CHAPTER 22 I
509. rupts specified as priority 0 0 0000xxx1 All macro service requests only Non maskable interrupts 1000xxxx All macro service requests only 0100xxxx 1100xxxx User s Manual U12697EJ4V1UD 387 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 14 Examples of Servicing When Another Interrupt Request Is Generated During Interrupt Servicing 1 3 Main routine a servicing b servicing El El Interrupt request a Level 3 M Interrupt request b Level 2 Since interrupt request b has a higher priority than interrupt request a and interrupts are enabled interrupt request b is acknowledged NA c servicing Interrupt request c Interrupt Level 3 requestd The priority of interrupt request d is Level 2 higher than that of interrupt request c but since interrupts are disabled m interrupt request d is held pending d servicing e servicing EI Interrupt Although interrupts are enabled Level 2 request f interrupt request f is held pending EE since it has a lower priority than N interrupt request e f servicing g servicing Interrupt El Although DE 2 request h interrupt request h is held pending Level since it has the same priority as Interrupt request g Level 1 o interrupt request g h servicing 388 User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 14 Examples of Servicing When Another Interrupt
510. s English Windows Supply Medium 3 5 inch 2HD FD Japanese Windows English Windows HP9000 series 700 HP UXTM Rel 10 10 USxxxxDF784225 USxXxxxCC78K4 L SPARCstation Host Machine PC 9800 series IBM PC AT compatibles SunOS Rel 4 1 4 Solaris Rel 2 5 1 Japanese Windows English Windows Supply Medium 3 5 inch 2HD FD HP9000 series 700 HP UX Rel 10 10 DAT SPARCstation B 2 Flash Memory Writing Tools Flashpro III Part No FL PR3 PG FP3 Flash programmer SunOS Rel 4 1 4 Solaris Rel 2 5 1 3 5 inch 2HD FD 1 4 inch CGMT Dedicated flash programmer for microcontrollers with on chip flash memory FA 80GC 8BT FA 80GK 9EU Flash memory writing adapter Remark The FL PR3 FA 80GC 8BT and FA 80GK 9EU are products made by Naito Densei Machida Mfg Co 604 Ltd Adapter for flash memory writing Used with the Flashpro Ill connected FA 80GC 8BT For 80 pin plastic QFP GC 8BT type FA 80GK 9EU For 80 pin plastic TQFP GK 9EU type For further information contact Naito Densei Machida Mfg Co Ltd TEL 81 45 475 4191 User s Manual U12697EJ4V1UD APPENDIX B DEVELOPMENT TOOLS B 3 Debugging Tools B 3 1 Hardware 1 2 1 When using in circuit emulator IE 78K4 NS IE 78K4 NS In circuit emulator In circuit emulator used to debug hardware and software when developing application systems
511. s 3 ROL RORC ROLC SHR and SHL are identical to ROR 4 XCHM CMPME CMPMNE CMPMNC and CMPMC are identical to MOVM 5 XCHBK CMPBKE CMPBKNE CMPBKNC and CMPBKC are identical to MOVBK 6 When saddr is saddr2 in this combination the instruction has a short code length 548 User s Manual U12697EJAV1UD CHAPTER 28 INSTRUCTION OPERATION 2 16 bitinstructions The values enclosed by parentheses are combined to express AX description as rp MOVM XCHW ADDW SUBW CMPW MULUW MULW DIVUX INCW DECW SHRW SHLW PUSH POP ADDWG SUBWG PUSHU POPU MOVTBLW MACW MACSW SACW Table 28 2 16 Bit Addressing Instructions Second saddrp laddri6 mem 2 saddrp lladdr24 saddrp First operand saddrg MOVW MOVW MOVW MOVW ADDWNotet XCHW XCHW XCHW No S XCHW ADD Note 1 ADDW Nete 1 ADDW Mts 1 3 ADDW Nete 1 MOVW MOVW MOVW MOVW MOVW MULWNote 4 ADDWNotet XCHW XCHW XCHW XCHW INCW ADDW Note 1 ADDWNote1 ADDWNote1 appyNote 1 DECW MOVW movw Nete3 MOVW MOVW INCW ADDWNotet Appw Note1 ADDWNotet XCHW DECW ADDWNote 1 sfrp MOVW MOVW MOVW ADDWNote 1 ADDW Note 1 ADDW Note 1 laddr16 MOVW MOVW MOVW MOVTBLW lladdr24 mem MOVW saddrp saddrg PSW TDE byte Notes 1 SUBW and CMPW are identical to ADDW 2 There is no second operand or the second operand is
512. s 4 and 5 are read only 304 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 5 Format of Prescaler Mode Register 0 for Serial Clock SPRM0 2 2 SMCNote 1 DFCNote 2 Transfer clock fxx setting allowable range fxx 44 2 to 4 19 MHz fxx 86 4 19 to 8 38 MHz 0 0 0 fxx 172 8 38 to 12 5 MHz 0 TM2 output 66 fxx 24 4 to 8 38 MHz fxx 48 8 to 12 5 MHz TM2 output 18 Notes 1 SMC Bit to change operation mode 0 Operates in normal mode 1 Operates in high speed mode 2 DFC Bit to control digital filter operation 0 Digital filter off 1 Digital filter on Cautions 1 Rewrite the SPRMO after clearing the IICEO 2 Set the transfer clock as follows When SMC 0 100 kHz or below When SMC 1 400 kHz or below Remarks 1 0 Bit 7 of I C bus control register 0 IICCO 2 The transfer clock does not change due to the ON OFF setting of bit 2 DFC in high speed mode 3 IIC clock Clock frequency when fxx N is selected NxT tg tr tr N 2 xT tr N 2 xT SCLn A A SCLn inverts SCLn inverts SCLn inverts IIC clock frequency fsc 1 N x T tF T 1 fxx tR SCLn rise time tF SCLn fall time Example When fxx 12 5 MHz N 172 ta 200 ns tr 50 ns IIC clock frequency 1 172 x 80 ns 200 ns 50 ns 71 4 kHz User s Manual U12697EJ4V1UD 305 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 4
513. s been secured by the program before switching back to the main system clock 554 User s Manual U12697EJAV1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Subsystem Clock Oscillator Characteristics Ta 40 to 85 C Resonator Recommended Circuit Parameter Conditions Crystal Oscillation frequency fxr Vss XT2 resonator Oscillation stabilization 4 5 V lt Voo lt 5 5 V N timeNote 1 8 V lt Voo lt 4 5 V External XT1 input frequency fxr clock XT1 input high low level width txt uPD74HCUO4 Note Time required to stabilize oscillation after applying the supply voltage Vpp Cautions 1 When using the subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible e Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as Vss e Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator 2 When the main system clock is stopped and the device is operating on the subsystem clock wait until the oscillation stabilization time has been secured by the program before switching back to the mai
514. s filter 3 AVner pin Handle pins not being used for analog output in either of the following ways when the D A converter is only using one channel with AVrer1 lt VoD Set the port mode register PM13X to 1 input mode and connect to Vsso Set the port mode register PM13X to 0 output mode set the output latch to 0 and output a low level 252 User s Manual U12697EJAV1UD CHAPTER 15 SERIAL INTERFACE OVERVIEW The uPD784225 Subseries has a serial interface with three independent channels Therefore communication outside and within the system can be performed simultaneously using all three channels Asynchronous serial interface UART 3 wire serial I O IOE x 2 channels See CHAPER 16 Clocked serial interface CSI x 1 channel 3 wire serial mode MSB first See CHAPTER 17 C bus mode multimaster compatible only in the uPD784225Y Subseries See CHAPTER 18 User s Manual U12697EJ4V1UD 253 CHAPTER 15 SERIAL INTERFACE OVERVIEW Figure 15 1 Serial Interface Example a UART 12 uPD784225Y master Vppo 1t uPD4711A uPD78054Y slave t SDA SCL RS 232C driver receiver uPD78062Y slave uPD4711A SDA SCL RS 232C driver receiver b UART 3 wired serial I O u PD784225Y master uPD75108 slave uPD4711A 3 wire serial I O Note driver receiver Note Handshake lines 254 User s Manual U12697EJ4
515. s function as external interrupt request inputs i INTPO to INTP5 INTPO to INTP5 are external interrupt request input pins for which the valid edge can be selected rising edge falling edge or both rising and falling edges The valid edge can be specified by the external interrupt rising edge enable register and the external interrupt falling edge enable register INTP2 also becomes the external trigger signal input pin of the real time output port via valid edge input ii NMI This is the external non maskable interrupt request input pin The valid edge can be specified by the external interrupt rising edge enable register and the external interrupt falling edge enable register P10 to P17 Port 1 These pins constitute an 8 bit input only port In addition to general purpose input port pins they also function as the analog inputs for the A D converter On chip pull up resistors are not available a Port mode These pins function as an 8 bit input only port b Control mode These pins function as the analog input pins ANIO to ANI7 of the A D converter The values are undefined when the pins specified for analog input are read User s Manual U12697EJAV1UD 47 CHAPTER 2 PIN FUNCTIONS 3 48 P20 to P27 Port 2 These pins constitute an 8 bit I O port In addition to I O port pins they also function as the data I O clock I O clock output and buzzer output of the serial interface The following operation modes ca
516. se register Furthermore four of the 16 bit general purpose registers can be combined with an 8 bit register for address expansion and used as a 24 bit address specification register The general purpose registers except for the V U T and W registers for address expansion are mapped to the internal RAM These register sets can use eight banks and can be switched by software or context switching RESET input selects register bank 0 In addition the register banks that are used in an executing program can be verified by reading the register bank selection flags RBSO RBS1 RBS2 in the PSW Figure 3 10 Format of General Purpose Register VVP RG4 VP RP4 U R11 R10 UUP RG5 UP RP5 T D R13 1 12 TDE RG6 DE RP6 w H R5 L R14 8 banks WHL RG7 HL RP7 23 15 0 Remark The names in parentheses are the absolute names User s Manual U12697EJ4V1UD 79 CHAPTER 3 CPU ARCHITECTURE Figure 3 11 General Purpose Register Addresses 8 bit processing 8 bit processing FEFFH Nete R15 R14 HL RP7 D R13 h E R12 DE RP6 R11 R10 an UP R5 R9 R8 VP R4 R7 R6 R5 5 R4 RP2 B C R2 BC RP1 FE80H Net A R1 X RO AX RPO
517. sed by the following methods IICCO bit 1 STTO 1 IICCO bit 0 SPTO 1 User s Manual U12697EJAV1UD 313 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 7 12C interrupt request INTIICO This section describes the values of 2 bus status register 0 IICSO at the INTIICO interrupt request generation timing and the INTIICO interrupt request timing 1 Master operation a Start Address Data Data Stop normal communication 1 When WTIMO 0 SPTO 1 A1 A2 A3 A4 A5 A1 50 10xxx110B A2 IICSO 10xxx000B 50 10xxx000B WTIMO 1 A4 50 10xxxx00B ICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care 2 When WTIMO 1 SPTO 1 Al A2 A4 A1 50 10xxx110B A2 IICSO 10xxx100B 50 10xxxx00B A4 IICSO 00000001B Remarks A Always generated A Generated only when SPIEO 1 x Don t care 314 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY b Start Address Data Start Address Data Stop Restart lt 1 gt lt 2 gt When WTIMO 0 STTO 1 SPTO 1 EET BETEIESTI NEIEAESTT IETEISZT se A2 A3 A5 A7 A1 50 10xxx110B A2 50 10xxx000B WTIMO 1 50 10xxxx00B WTIMO 0 A4 IICSO 10xxx110B WTIMO 0 A5 IICSO 10 000 WTIMO 1 A6 IICSO 10xxxx00B A7 1
518. select fxr as the count clock of the watch timer 8 bit timer event counters 1 2 Operational when TI1 and TI2 are selected as the count clocks 8 bit timers 5 and 6 Operational when TI5 and TI6 are selected as the count clocks Watch timer Operational only when fxr is selected as the count clock Watchdog timer Operation disabled A D converter Operation disabled D A converter Operation enabled Real time output port Operational when an external trigger is used or TI1 and TI2 are selected as the count clocks of 8 bit timer counters 1 and 2 Serial interface Except 2 bus Operational only when an external input clock is selected as the serial clock mode bus mode Operation disabled External interrupt INTPO to INTP5 Operation enabled Bus lines during ADO to AD7 High impedance external expansion A8 to A19 High impedance ASTB High impedance WR RD High impedance WAIT Input state is retained Caution Inthe IDLE mode only external interrupts INTPO to INTP5 and the watch timer interrupt INTWT can release the IDLE mode and be acknowledged as interrupt requests All other interrupt requests are held pending and acknowledged after the IDLE mode has been released through NMI input INTPO to INTP5 input and INTWT 502 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION b Releasing the IDLE mode i ii ili Releasing IDLE mode by NMI inpu
519. ser s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 3 Format of I2C Bus Control Register 0 IICCO 1 4 Address OFFBOH After reset OOH R W Symbol PTO Operation disabled Presets the 2 bus status register IICS0 Stops internal operation SCLO and SDAO lines output low level Enables operation Clear condition IICEO 0 Set condition IICEO 1 Cleared by an instruction Setbyan instruction When RESET is input Normal operation Releases microcontroller from the current communication and sets it in the wait state Automatically clears after execution The extended code that is unrelated to the base is used during reception The SCLO and SDAO lines are put in the high impedance state The following flags are cleared STDO ACKDO TRCO COIO EXCO MSTSO STTO Until the following communication participation conditions are satisfied the wait state that released the microcontroller from communication is entered Start as the master after detecting the stop condition Address match or extended code reception after the start condition Clear condition LRELO 0 Nete Set condition LRELO 1 Automatically cleared after execution Setbyan instruction When RESET is input The wait is not released The wait is released After the wait is released it is automatically cleared
520. service 398 User s Manual U12697EJ4V1UD Macro service processing At the end of macro service MSC 0 an interrupt request is generated and acknowledged If the last macro service is performed when the interrupt due to the end of the macro service cannot be acknowledged while other interrupt servicing is being executed etc that interrupt is held pending until it can be acknowledged CHAPTER 22 INTERRUPT FUNCTIONS 2 When VCIE bit is 1 In this mode an interrupt is not generated after macro servicing ends Figure 22 20 shows an example of macro service and interrupt acknowledgment operations when the VCIE bit is 1 This mode is used when the final operation is to be started by the last macro service processing performed etc It is mainly used in the following cases Clocked serial interface receive data transfers INTCSIO INTCSI1 INTCSI2 Asynchronous serial interface data transfers INTST1 INTST2 To stop a stepper motor in the case of stepping motor control by means of macro service type C using the real time output port and timer counter INTTM1 INTTM2 Figure 22 20 Operation at End of Macro Service When VCIE 1 Main routine Macro service request Last macro service request Interrupt request due to the end of the hardware operation started by the last macro service processing EI p User s Manual U12697EJAV1UD Macro service processing Processing of las
521. service is useful when the amount of data to be transferred is small as transfers can be performed at high speed User s Manual U12697EJ4V1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 23 Macro Service Data Transfer Processing Flow Type A Macro service request acknowledgment Read contents of macro service mode register Other Determine channel type To other macro service processing Read channel pointer contents m Read MSC contents n Calculate buffer addressNete Note 1 byte transfer m n 1 2 byte transfer m nx 2 1 Read SFR pointer contents SFR Memo Determine transfer direction gt y Memory gt SFR Read buffer contents then transfer Specified SFR contents then read data to specified SFR transfer read data to buffer MSC MSC 1 Clear 0 interrupt service mode bit ISM lt Clear 0 interrupt request flag IF No Vectored interrupt request generation User s Manual U12697EJ4V1UD 405 CHAPTER 22 INTERRUPT FUNCTIONS 2 Macro service channel configuration The channel pointer and 8 bit macro service counter MSC indicate the buffer address in internal RAM FE00H to FEFFH when the LOCATION 0H instruction is executed or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed which is the transfer source or transfer destination refer to Figure 22 24 In the channel pointer the lower 8 bits of the address are writte
522. set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 00H User s Manual U12697EJAV1UD 229 CHAPTER 13 A D CONVERTER Figure 13 2 Format of A D Converter Mode Register ADM Address OFF80H After reset R W Symbol 9 A D conversion control Conversion stop Conversion enable Software start hardware start selection Software start Hardware start A D conversion time selection Number of clocks fxx 12 5 MHz fxx 6 25 MHz 144 fxx Setting prohibited 120 fxx Setting prohibited 96 fxx Setting prohibited 288 fxx 23 0 us 240 fxx 19 2 us 1 192 fxx 15 4 us _ Setting prohibited External trigger signal valid edge selection No edge detection Detection of falling edge Detection of rising edge Detection of both falling and rising edges Reference voltage circuit control Circuit stoppedNote Circuit operating Note reference voltage circuit operates when ADCS is 1 230 User s Manual U12697EJ4V1UD CHAPTER 13 A D CONVERTER Cautions 1 Set the A D conversion time as follows When 2 7 V to 5 5 V 14 us or more When 2 0 V to 2 7 V 28 us or more When 1 9 V to 2 0 V 48 us or more uPD78F4225 78F4225Y When 1 8 V to 2 0 V 48 us or more uPD784224 784225 784224Y 784225Y 2 When overwriting FRO to FR2 to different data temporar
523. sing a Back to HALT mode INT other than macro service HALT mode release 476 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION Figure 24 5 Operations After Releasing HALT Mode 4 4 6 HALT mode which the interrupt is held which is enabled in an instruction that interrupt requests are temporarily held Main routine Interrupt request Interruption held for the space of eight clocks MOV STBC byte HALT mode release Interrupt servicing L 7 Conflict between HALT mode setting instruction and interrupt Main routine Interrupt request MOV STBC byte HALT mode not executed Execute instruction up to 6th clock Interrupt servicing User s Manual U12697EJ4V1UD 477 CHAPTER 24 STANDBY FUNCTION 1 Releasing HALT mode by a non maskable interrupt When a non maskable interrupt is generated the halt mode is released regardless of the enable state El and disable state DI for interrupt acknowledgement If the non maskable interrupt that released the HALT mode can be acknowledged when the HALT mode is released that non maskable interrupt is acknowledged and execution branches to the service program If it cannot be acknowledged the instruction following the instruction that set the HALT mode MOV STBC byte instruction is executed The non maskable interrupt that released the HALT mode is acknowledged when acknowledgement is possible For d
524. sion Is 244 13 18 Conversion Result Read Timing When Conversion Result Is Undefined 245 13 19 Conversion Result Read Timing When Conversion Result Is 245 13 20 Example of Capacitor Connection Between Vppo AVDD aa 246 13 21 Internal Equivalence Circuit of ANIO to ANI7 Pins 247 13 22 Example of Circuit When Signal Source Impedance 15 High sseeeeee 247 14 1 Block Diagram of D A Converter u su u unu n rp iach ERE EH Fe 249 14 2 Format of D A Converter Mode Registers 0 and 1 DAMO DAM1 250 14 3 Buffer Amplifier Insertion Example 252 15 1 SerialInterface Example irte tm betreten ieu ada aima er aire vag PAS dormi Rec aed 254 16 1 Switching Asynchronous Serial Interface Mode and 3 Wire Serial I O Mode 256 16 2 Block Diagram in Asynchronous Serial Interface Mode 02 0400 259 16 3 Format of Asynchronous Serial Interface Mode Registers 1 and 2 ASIM1 ASIM2 262 16 4 Format of Asynchronous Serial Interface Status Registers 1 and 2 ASIS1 ASIS2 263 16 5 Format of Baud R
525. sition CHAPTER 24 STANDBY FUNCTION Addition of chapter CHAPTER 29 ELECTRICAL SPECIFICATIONS Addition of chapter CHAPTER 30 PACKAGE DRAWINGS Addition of chapter CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS Addition of description on SP78K4 and change of Remark in B 1 Language Processing Software Change of Remark in B 3 2 Software Addition of B 4 Cautions on Designing Target System APPENDIX B DEVELOPMENT TOOLS Deletion of MX78K4 description APPENDIX C EMBEDDED SOFTWARE 4th edition Modification Version 624 Modification of 1 2 Ordering Information CHAPTER 1 OVERVIEW Addition of lead free products to CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS User s Manual U12697EJ4V1UD CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS
526. ss 1 bit data is transmitted A transfer direction specification bit of O indicates that the master transmits the data to the slave A transfer direction specification bit of 1 indicates that the master receives the data from the slave Figure 18 10 Transfer Direction Specification SCLO 1 2 3 4 5 6 7 8 9 Transfer direction noe INTIICO specification Note When the base address or extended code is received during slave operation INTIICO is not generated User s Manual U12697EJ4V1UD 309 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 4 Acknowledge signal ACK The acknowledge signal verifies the reception of the serial data on the transmitting and receiving sides The receiving side returns the acknowledge signal each time 8 bit data is received Usually after transmitting 8 bit data the transmitting side receives an acknowledge signal However if the master receives the acknowledge signal is not output when the last data is received After an 8 bit transmission the transmitting side detects whether the receiving side returned an acknowledge signal If an acknowledge signal is returned the next processing is performed assuming that reception was correctly performed Since reception has not been performed correctly if the acknowledge signal is not returned from the slave the master outputs the stop condition to stop transmission If an acknowledge signal is not returned the following two
527. ssible from digital circuits It is particularly important to prevent analog and digital signal lines from crossing or coming into close proximity as A D conversion characteristics are vulnerable to degradation from the induction of noise or other such factors Connect AVss and Vss to a single stable location on the board 13 AVpp pins AVpo pin functions as the analog circuit power supply pin and the A D converter s reference voltage input pin and also supplies power to the input circuits of ANIO P10 to ANI7 P17 Connect a capacitor between the Vppo and AVpp pins to minimize conversion error caused by noise Note also that the voltage applied to the and AVopo pins following the resumption of A D conversion after it was stopped may be unstable causing a degradation in the accuracy of the A D conversion Be sure to connect a capacitor between the Vppo and pins in this case also An example of capacitor connection is shown in Figure 13 20 below Figure 13 20 Example of Capacitor Connection Between and AVpp Vppo 77 Z O AVpp C2 C4 e AVss Remark C1 C2 4 7 uF to 10 uF reference values C3 C4 0 01 uF to 0 1 uF reference values Connect C3 and C4 as close to the pins as possible 14 Internal equivalence circuit and allowable signal source impedance of ANIO to ANI7 In order to complete sampling within the sampling time and obtain a high enough A D
528. starts again from the instruction following the instruction that set the IDLE mode When acknowledgement is enabled execution branches to the NMI interrupt service program by executing the RETI instruction For details of NMI interrupt acknowledgement refer to 22 6 Non Maskable Interrupt Acknowledgment Operation Releasing IDLE mode by INTPO to INTP5 input and watch timer interrupt If interrupt masking by INTPO to INTP5 input is released and macro servicing is disabled and the valid edge specified by external interrupt edge enable register 0 EGPO EGNO is input to INTPO to INTP5 the IDLE mode is released At the same time a watch timer overflow will occur and the IDLE mode will be released when the watch timer interrupt mask is released and macro services are disabled If interrupts can be acknowledged when the IDLE mode is released and the interrupt enable flag IE is set to 1 execution branches to the interrupt service program If the IE flag is cleared to 0 when acknowledgement is not possible execution starts again from the instruction following the instruction that set the IDLE mode For details of interrupt acknowledgement refer to 22 7 Maskable Interrupt Acknowledgment Operation Releasing of IDLE mode by RESET input When the RESET input rises from low to high and the reset condition is released the oscillator starts oscillating Oscillation stops for the RESET active period After the oscillation stabilization time elapses nor
529. state otherwise subsequent interrupt acknowledgment control may not be performed normally A method of initializing interrupt acknowledgment related hardware in the program is shown below The only way of performing initialization by hardware is by RESET input Example MOVW 0FFFFH MOV MKIL 0FFH IRESL CMP ISPR 0 BZ NEXT MOVG SP RETVAL RETI RETVAL DW LOWW IRESL DB O DB HIGHW IRESL NEXT Mask all maskable interrupts No interrupt service programs running Forcibly change SP location Forcibly terminate running interrupt service program return address IRESL Stack data to return to IRESL with RETI instruction LOWW amp HIGHW are assembler operators for calculating low order 16 bits amp high order 16 bits respectively of symbol NEXT 115 necessary to ensure that a non maskable interrupt request is not generated via the NMI pin during execution of this program After this on chip peripheral hardware initialization and interrupt control register initializa tion are performed When interrupt control register initialization is performed the interrupt request flags must be cleared 0 434 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 13 Cautions 1 2 3 The in service priority register ISPR is read only Writing to this register may result in a malfunction The watchdog timer mode register WDM can only be written to with a dedicated
530. ster PRM1 TM1 selects the count clock TM2 connected in cascade is not used for setting e CRn0 Compare values each compare value can be set from 00H to TMOn Select the clear and start mode when TMn and CRnO match TM1 TMC1 0000xxx0B x Don t care le TMC2 0001xxx0B x Don t a Setting TCE2 1 in TMC2 and finally setting TCE1 1 in TMC1 starts the count operation If the values of TMn of all timers connected in cascade and CRnO match INTTM1 of TM1 is generated TM1 and TMe are cleared to OOH are repeatedly generated at the same interval Cautions 1 Always set the compare register CR10 CR20 after stopping timer operation 2 If the TM2 count value matches CR20 even when used in a cascade connection INTTM2 of TM2 is generated Always mask the higher timer in order to disable interrupts 3 Set TCE1 and TCE2 in TM2 first Set TM1 last 4 Restarting and stopping the count is possible by setting only 1 or 0 in TCE1 of TMC1 to start and stop operation Note however that the TCE1 bit of TMC1 and TCE2 bit of TMC2 must be cleared when setting the compare register CR10 CR20 Figure 9 10 shows a timing example of the cascade connection mode with 16 bit resolution Figure 9 10 Cascade Connection Mode with 16 Bit Resolution MEI M EM UE SERE EE m DUE morum CR10 cR20 0 TCE 4 2 TCE2 J
531. struction MOVG Mnemonic Operand rg imm24 rg imm24 Operation Flag s Z AC P V CY rg rg rg lt rg rg addr24 rg addr24 lladdr24 rg addr24 rg rg saddrg rg saddrg saddrg rg saddrg rg WHL saddrg WHL lt saddrg saddrg WHL saddrg WHL WHL mem1 WHL lt mem1 mem1 WHL mem1 WHL 4 8 bit data exchange instruction XCH Mnemonic Operand Bytes 526 nr rer Operation Flag S Z AC P V CY Aor A saddr2 A e saddr2 r saddr r lt gt saddr r sfr ro sfr saddr saddr saddr lt gt saddr r laddr16 r lt addr16 r lladdr24 r lt gt addr24 A saddrp As saddrp A saddrg A lt gt saddrg A mem A mem User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION 5 16 bit data exchange instruction XCHW Mnemonic XCHW Mnemonic Operand rp rp Operation rp e rp Flag S Z AC P V CY AX saddrp2 AX saddrp2 rp saddrp lt gt saddrp rp sfrp e sfrp AX saddrp AX saddrp AX saddrg AX saddrg AX laddr16 AX gt addr16 AX lladdr24 AX addr24 saddrp saddrp saddrp lt gt
532. sts of the internal RAM area and the special function register area see Figures 3 1 and 3 2 The final address in the internal data area can be set to OFFFFH when executing the LOCATION OH instruction or FFFFFH when executing the LOCATION OFH instruction by the LOCATION instruction The address selection of the internal data area by this LOCATION instruction must be executed once immediately after a reset is cleared After one selection updating is not possible The program following a reset clear must be as shown in the example If the internal data area and another area are allocated to the same address the internal data area becomes the access target and the other area cannot be accessed Example RSTVCT ATO DW RSTSTRT to INITSEG CSEG BASE RSTSTRT LOCATION 0H or LOCATION 0FH MOVG SP STKBGN Caution When the LOCATION OH instruction is executed the program after clearing the reset must not overlap the internal data area In addition make sure the entry address of the servicing routine for a non maskable interrupt such as NMI does not overlap the internal data area The entry area for a maskable interrupt must be initialized before referencing the internal data area User s Manual U12697EJAV1UD 65 CHAPTER 3 CPU ARCHITECTURE 3 4 1 Internal RAM area The uPD784225 has an on chip general purpose static RAM This area has the following configuration Internal RAM area r Peripheral RAM PRAM Int
533. t PC iw lt RP2 RP2 lt addr16 PCuw lt 1 The flag with the highest priority that is set to 1 in the ISPR is cleared to 0 RETCSB laddr16 542 PSW lt lt RP2 RP2 lt addr16 PCuw lt RP8s 11 User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION 17 Unconditional branch instruction BR Mnemonic Operand laddr16 Operation PCuw lt 0 lt addr16 Flag s Z AC P V CY lladdr20 PC lt addr20 rp PCuw lt 0 lt rp rg PC lt rg rp lt 0 lt rp rg PC lt rg addr20 PC lt PC 2 jdisp8 laddr20 Co NO N NN AR PC lt PC 3 jdisp16 User s Manual U12697EJ4V1UD 543 CHAPTER 28 INSTRUCTION OPERATION 18 Conditional branch instructions BNZ BNE BZ BE BNC BNL BC BL BNV BPO BV BPE BP BN BLT BGE BLE BGT BNH BH BF BT BTCLR BFSET DBNZ Flag S Z AC P V CY Mnemonic Operand Operation addr20 PC PC 2 jdisp8 if Z 0 addr20 PC PC 2 jdisp8 if Z 1 addr20 PC PC 2 jdisp8 if CY 0 addr20 PC PC 2 jdisp8 if CY 1 addr20 PC lt PC 2 jdisp8 if P V 0 addr20 PC PC 2 jdisp8 if P V 1 addr20 addr20 addr20 addr20 addr20 addr20 addr20 addr20 PC lt PC 2 jdisp8 if S 0 PC l
534. t When the valid edge set by external interrupt edge enable register 0 EGP0 EGNO is input by NMI input the IDLE mode is released When the IDLE mode is released and non maskable interrupts by NMI pin input can be acknowledged execution branches to the NMI interrupt service program When interrupts cannot be acknowledged when the IDLE mode has been set in the NMI interrupt service program execution restarts from the instruction following the instruction that set the IDLE mode When interrupts can be acknowledged by executing the RETI instruction execution branches to the NMI interrupt service program For details of NMI interrupt acknowledgement refer to 22 6 Non Maskable Interrupt Acknowledgment Operation Releasing IDLE mode by INTPO to INTP5 input and watch timer interrupt If interrupt masking is released through INTPO to INTP5 input and macro servicing is disabled the oscillator restarts oscillating when the valid edge specified by external interrupt edge enable register 0 EGPO EGNO is input to INTPO to INTP5 At the same time a watch timer overflow will occur and the IDLE mode will be released when the watch timer interrupt mask is released and macro services are disabled When the IDLE mode is released and the interrupt enable flag IE is set to 1 if interrupts can be acknowledged execution branches to the interrupt service program When interrupts cannot be acknowledged and when the IE flag is cleared to 0 execution restarts
535. t PC 2 jdisp8 if S 1 PC lt PC 3 jdisp8 if P V VS 1 PC lt PC 3 jidsp8 if PV S 0 PC lt PC 3 jdisp8 if P V 5 5 VZ 1 PC amp PC 3 jidsp8 if P V S VZ 0 PC lt PC 3 jdisp8 if ZVCY 1 2 2 3 3 3 3 3 3 PC lt PC 3 jidsp8 if ZV CY 0 saddr bit addr20 A PC lt PC 4Note jdisp8 if saddr bit 0 sfr bit addr20 PC lt PC 4 jdisp8 if sfr bit 0 X bit addr20 PC lt PC 3 jdisp8 if X bit 0 A bit addr20 PSWL bit addr20 PSWH bit addr20 PC lt PC 3 jdisp8 if A bit 0 PC lt PC 3 jdisp8 if PSW bit 0 PC lt PC 3 jdisp8 if PSWH bit 0 laddr16 bit addr20 PC lt PC 3 jdisp8 if laddr16 bit 0 lladdr24 bit addr20 lt PC 3 jdisp8 if addr24 bit 0 G GOO O GOO GOO GO GO mem2 bit addr20 PC 3 jdisp8 if mem2 bit 0 Note This is used when the number of bytes is four When five it becomes lt PC 5 jdisp8 544 User s Manual U12697EJ4V1UD CHAPTER 28 INSTRUCTION OPERATION Mnemonic BT Operand saddr bit addr20 Operation PC c PC 3Note 1 jdisp8 if saddr bit 1 Flag s Z AC P V CY sfr bit addr20 PC lt PC 4 jdisp8 if sfr bit 1 X bit addr20 PC lt PC 3 jdisp8 if X bit 1 A bit addr20 PC lt PC 3 jdis
536. t function be used conforms to the operating state Never write a combination of codes that have Setting prohibited written in the register description in this manual Characters that are confused 0 zero O capital o 1 one letter I capital i 10 User s Manual U12697EJAV1UD Related Documents ever preliminary versions are not marked as such Documents related to devices Document Name Document No 784225 784225Y Subseries Hardware User s Manual The related documents indicated in this publication may include preliminary versions How This manual 78K IV Series Instruction User s Manual U10905E 78K IV Series Software Basics Application Note Documents related to development tools software user s manuals U10095E Document Name Document No RA78K4 Assembler Package Operation U11334E Language U11162E Structured Assembler Preprocessor U11743E CC78K4 C Compiler Operation U11572E Language U11571E SM78K4 System Simulator Ver 1 40 or Later Reference Windows Based U10093E SM78K Series System Simulator Ver 1 40 or Later External Part User Open Interface Specifications U10092E ID78K Series Integrated Debugger Ver 2 30 or Later Operation Windows Based U15185E ID78K4 Integrated Debugger Windows Based Reference U10440E RX78K4 Real Time OS Fundamental U10603E Installation U10604E
537. t Restore Vectored Save Initialize Interrupt Restore Restore Mai Main routine general general general ain routine registers registers semicing registers PC amp PSW Interrupt request generation Notes 1 When register bank switching is used and an initial value has been set in the register beforehand 2 Register bank switching by context switching saving of PC and PSW 3 Register bank PC and PSW restoration by context switching 4 PC and PSW saved to the stack vector address loaded into PC 22 8 2 Types of macro servicing Macro servicing can be used with the 23 kinds of interrupts shown in Table 22 6 There are four kinds of operations selectable according to the application User s Manual U12697EJ4V1UD 393 CHAPTER 22 INTERRUPT FUNCTIONS Default Priority Table 22 6 Interrupts for Which Macro Servicing Can Be Used Interrupt Request Generation Source INTWDTM Watchdog timer overflow Generating Unit Watchdog timer Macro Service Control Word Address OFEO6H INTPO Pin input edge detection INTP1 Pin input edge detection INTP2 Pin input edge detection INTP3 Pin input edge detection INTP4 Pin input edge detection INTP5 Pin input edge detection Edge detection OFE08H OFEOAH OFEOCH OFEOEH OFE10H OFE12H INTIICO CSIO I C bus transfer end Nete INTCSIO CSIO 3 wire transfe
538. t clears SNMI to 00H Figure 22 6 Format of Interrupt Selection Control Register SNMI Address OFFA9H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Watchdog timer interrupt selection Use as non maskable interrupt Interrupt servicing cannot be disabled with interrupt mask register Use as maskable interrupt Vectored interrupts and macro servicing can be used Interrupt servicing can be disabled with interrupt mask register P02 pin function selection Use as INTP2 Vectored interrupts and macro servicing can be used Interrupt servicing can be disabled with interrupt mask register At this time the standby mode set by the P02 pin is released with a maskable interrupt Use as NMI Interrupt servicing cannot be disabled with interrupt mask register At this time the standby mode set by the P02 pin is released with an NMI User s Manual U12697EJAV1UD 375 CHAPTER 22 INTERRUPT FUNCTIONS 22 3 7 Program status word PSW The PSW is a register that holds the current status of instruction execution results and interrupt requests The IE flag that sets enabling disabling of maskable interrupts is mapped in the lower 8 bits of the PSW PSWL PSWL can be read or written to with an 8 bit manipulation instruction and can also be manipulated with a bit manipulation instruction or dedicated instruction EI DI When a vectored interrupt is acknowledged or the BRK instruction is executed PSWL is saved to the stac
539. t macro service Interrupt servicing 399 CHAPTER 22 INTERRUPT FUNCTIONS 22 8 5 Macro service control registers 1 Macro service control word The uPD784225 s macro service function is controlled by the macro service control mode register and macro service channel pointer The macro service processing mode is set by means of the macro service mode register and the macro service channel address is indicated by the macro service channel pointer The macro service mode register and macro service channel pointer are mapped onto the part of the internal RAM shown in Figure 22 21 for each macro service as the macro service control word When macro service processing is performed the macro service mode register and channel pointer values corresponding to the interrupt requests for which macro service processing can be specified must be set beforehand 400 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 21 Format of Macro Service Control Word Reserved word WTCHP WTMMD CCHP6 CMMD6 CCHP5 CMMD5 ADCHP ADMMD CCHP2 CMMD2 CCHP1 CMMD1 CCHP01 CMMD01 00 CMMD00 CCHP3 CMMD3 STCHP2 STMMD2 SRCHP2 CSICHP2 SRMMD2 CSIMMD2 SERCHP2 SERMMD2 STCHP1 STMMD1 SRCHP1 CSICHP1 SRMMD1 CSIMMD1 SERCHP1 SERMMD1 IICCHP e e CSICHPO IICMMD et CSIMMDO PCHP5 PMMD5 PCHP4 PMMD4 PCHP3 PMMD3 PCHP2 PMMD2 PCHP1 PMMD1 PCHPO PMMDO WDTCHP WDTMMD Address OFE3
540. t timing of CR10 address data area 12H 123409H 123408H Output data area 123400 MPT MPD incremented 1 byte timer data no automatic addition no ring control interrupt request generation at MSC 0 pointer Mode OFH register ddp Internal bus Compare egister CR10 r Lung meinte INTTM1 Output atch Real time latch output trigger Macro service start Timer counter 1 1 Stepper motor Remark Internal RAM addresses in the figure are the values when the LOCATION instruction is executed When the LOCATION OFH instruction is executed 0 0000 should be added to the values in the figure 420 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 33 Data Transfer Control Timing T5 TM1 Count value T3 T4 T6 T7 T1 T2 OH Count starts interrupt Compare register CR10 RTBL 120 121 122 123 User s Manual U12697EJ4V1UD 421 CHAPTER 22 INTERRUPT FUNCTIONS 422 b Examples of use of automatic addition control and ring control i ii Automatic addition control The output timing data At specified by the macro service pointer MPT is added to the contents of the compare register and the result is written
541. t transfer can start Figure 18 13 Wait Signal 1 2 1 The master has a 9 clock wait and the slave has an 8 clock wait Master Transmitting Slave Receiving ACKEO 1 The master returns to Hi Z Wait after the ninth but the slave waits low level clock is output Tem IIC0 data wait release SCL0 6 7 8 9 1 2 3 Slave Wait after the eighth clock is output IIC0 IIC0 FFH or WREL0 lt 1 SCL0 ACKEO H Transfer lines SCLO 6 7 8 9 1 2 3 312 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 13 Wait Signal 2 2 2 Both the master and slave have 9 clock waits Master Transmitting Slave Receiving ACKEO 1 Both the master and slave wait after nine clocks are output lt data wait release SCL0 6 7 8 9 1 2 3 Slave IIC0 WREL0 1 Y SCLO ACKEO H Transfer lines SCLO 6 7 8 9 1 2 3 Output in accordance with the preset ACKEO Remark ACKEO Bit 2 in 2 bus control register O IICCO WRELO Bit 5 in I C bus control register 0 IICCO A wait is automatically generated by setting bit WTIMO of 12 bus control register 0 IICCO Normally when bit 5 WRELO 1 in IICCO or FFH is written to serial shift register 0 the receiving side releases the wait when data is written to IICO the transmitting side releases the wait In the master the wait can be relea
542. tage during subsystem clock operation Vpp 1 9 to 5 5 V Figure 29 2 Power Supply Voltage and Clock Cycle Time CPU Clock Frequency fcpu 10000 8000 500 DO 400 Guaranteed 2 operation range 300 x o 200 160 100 80 Supply voltage V Capacitance Ta 25 C Vpp Vss 0 V Parameter Conditions Input capacitance f 1 MHz Unmeasured pins returned to 0 V Output capacitance capacitance 570 User s Manual U12697EJ4V1UD CHAPTER 29 ELECTRICAL SPECIFICATIONS Main System Clock Oscillator Characteristics Ta 40 to 85 C Resonator Recommended Circuit Parameter Conditions Ceramic Oscillation 4 5 V lt Voo lt 5 5 V resonator frequency fx or crystal 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V resonator 1 9 V lt Voo lt 2 0 V 4 5 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V External X1 input 4 5 V lt Voo lt 5 5 V clock frequency fx 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 1 9 V lt Voo lt 2 0 V uPD74HCU04 1 4 5 V x Voo lt 5 5 V 2 7 V lt Voo lt 4 5 V 2 0 V lt Voo lt 2 7 V 4 4 4 4 2 2 2 2 4 4 4 4 2 2 2 2 1 9 V lt Voo lt 2 0 V 1 input high low level width
543. ter banks 0 to 7 refer to Table 3 4 Three bit information that indicates the register bank selected by executing the SEL RBn instruction is stored Table 3 4 Register Bank Selection Set Register Bank Register bank 0 Register bank 1 Register bank 2 Register bank 3 Register bank 4 Register bank 5 Register bank 6 Register bank 7 9 User flag UF This flag is set and reset by a user program and can be used for program control 72 User s Manual U12697EJ4V1UD CHAPTER 3 CPU ARCHITECTURE 3 7 3 Using the RSS bit Basically always use the RSS bit fixed to 0 The following descriptions discuss using a 78K lll Series program and a program that sets the RSS bit to 1 Reading is not necessary if the RSS bit is fixed to 0 The RSS bit enables the functions in A R1 X R0 B R3 C R2 AX RP0 and BC RP1 to also be used in registers R4 to R7 RP2 RP3 When this bit is effectively used efficient programs in terms of program size and program execution can be written Sometimes however unexpected problems arise if the RSS bit is used carelessly Consequently always set the RSS bit to 0 Use the RSS bit set to 1 only when 78K lll Series programs will be used By setting the RSS bit to 0 in all programs writing and debugging programs become more efficient Even if a program where the RSS bit is set to 1 is used when possible it is recommended to use the program after modify
544. terrupt the main system clock is switched to the subsystem clock which must be in a stable oscillation state Upon detection of Vpp voltage reset due to an interrupt bit 2 MCK of STBC is set to 0 and oscillation of the main system clock is started After lapse of the time required for stabilization of oscillation STBC is rewritten and maximum speed operation is resumed Caution When the main system clock is stopped and the device is operating on the subsystem clock wait 104 until the oscillation time has been secured by the program before switching back to the main system clock User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS 5 1 Digital I O Ports The ports shown in Figure 5 1 which enable a variety of controls are provided The function of each port is described in Table 5 1 Connection of on chip pull up resistors can be specified for ports 0 2 to 7 and 12 by a software setting Figure 5 1 Port Configuration Port 5 Port 0 P10 to P17 Port 1 Port 6 Port 7 Port 2 Port 12 Port 3 Port 13 Port 4 User s Manual U12697EJAV1UD 105 CHAPTER 5 PORT FUNCTIONS Port 0 Pin Name P00 to P05 Table 5 1 Port Functions Function Input or output can be specified in 1 bit units Specification of Software Pull up Resistor Specifiable in 1 bit units Port 1 P10 to P17 Input port Port 2 P20 to P27 Input or output can be specified in 1 bit units Specifiabl
545. terrupt request is acknowledged the program status word PSW and program counter PC are saved in that order to the stack the IE flag is cleared 0 the interrupt disabled status is set and the in service priority register ISPR bit corresponding to the priority of the acknowledged interrupt is set 1 Also data in the vector table predetermined for each interrupt request is loaded into the PC and a branch is performed The return from a vectored interrupt is performed by means of the RETI instruction Caution When a maskable interrupt is acknowledged by vectored interrupt the RETI instruction must be used to return from the interrupt Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used 22 7 2 Context switching Initiation of the context switching function is enabled by setting 1 the context switching enable flag of the interrupt control register When an interrupt request for which the context switching function is enabled is acknowledged the register bank specified by the lowest 3 bits of the lower address even address of the corresponding vector table address is selected The vector address stored beforehand in the selected register bank is transferred to the program counter PC and at the same time the contents of the PC and program status word PSW up to that time are saved in the register bank and branching is performed to the interrupt service program Figure 22 12 Context S
546. terrupt signal is generated Interrupt servicing enable disable Interrupt servicing enabled Interrupt servicing disabled xxISMn Interrupt servicing mode specification Vectored interrupt servicing context switching processing Macro service processing Context switching processing specification Processing as vectored interrupt Processing by context switching xxPRnO Interrupt request priority specification Priority O highest priority Priority 1 Priority 2 Priority 3 User s Manual U12697EJAV1UD 367 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22 1 Interrupt Control Register xxICn 2 3 Address 0FFE9H to 0FFF1H After reset 43H smo O O SERIC1 SERIF1 SERMK1 SERISM1 SERCSE1 SERPR11 SERPR10 SRIC1 SRIF1 SRMK1 SRISM1 SRCSE1 SRPR11 SRPR10 STIC1 STIF1 STMK1 STISM1 STCSE1 STPR11 STPR10 SERIC2 SERIF2 SERMK2 SERISM2 SERCSE2 SERPR21 SERPR20 SRIC2 SRIF2 SRMK2 SRISM2 SRCSE2 SRPR21 SRPR20 STIC2 STIF2 STMK2 STISM2 STCSE2 STPR21 STPR20 TMIC3 TMIF3 TMMK3 TMISM3 TMCSE3 TMPR31 TMPR30 TMICOO TMIFOO TMMKOO TMISMOO TMCSE00 001 TMPROOO TMICO1 TMIFO1 TMMKO1 TMISMO1 TMCSE01 TMPRO11 TMPRO10 Interrupt request generation No interrupt request interrupt signal is not generated Interrupt request interrupt signal is generated Interrupt servicing en
547. ters 1 and 2 ASIM1 ASIM2 Address OFF70H OFF71H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 RxD1 P20 RxD2 P70 TxD1 P21 TxD2 P71 TXEn RXEn Operation mode pin function pin function Operation stop Port function Port function UART mode Serial function Port function Receive only UART mode Port function Serial function Transmit only UART mode Serial function Serial function Transmit Receive Parity bit specification No parity Always add 0 parity during transmission Do not perform parity check during reception parity error not generated Odd parity Even parity CLn Transmit data character length specification 0 7 bits 8 bits Transmit data stop bit length specification 1 bit 2 bits Receive completion interrupt control at error occurrence Generate receive completion interrupt request when error occurs Do not generate receive completion interrupt request when error occurs Note Be sure to write 0 to bit 0 Caution Switch across to the operational mode after stopping serial sending and receiving opera tions Remark 1 2 262 User s Manual U12697EJ4V1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 2 Asynchronous serial interface status registers 1 and 2 ASIS1 ASIS2 ASIS1 and ASIS2 are registers used display the type of error when a receive error occurs ASIS1 and ASIS2 can be read by a 1 bit or 8 bit
548. terval time When using CROO as capture register The valid edge of the TIOO or TIO1 pin can be selected as a capture trigger The valid edges for TIOO and TIO1 are set with prescaler mode register 0 PRMO Tables 8 2 and 8 3 show the conditions that apply when the capture trigger is specified as the valid edge of the TIOO pin and the valid edge of the TIO1 pin respectively Table 8 2 Valid Edge of TIOO Pin and Capture Trigger of CROO Valid Edge of TIOO Pin Falling edge Capture Trigger of CROO Rising edge Rising edge Falling edge Setting prohibited Setting prohibited Both rising and falling edges Valid Edge of TIO1 Pin Falling edge No capture operation Capture Trigger of CROO Falling edge Rising edge Rising edge Setting prohibited Setting prohibited Both rising and falling edges CR00 is set by a 16 bit memory manipulation instruction RESET input sets CROO to 0000H Both rising and falling edges Caution Setany value other than 0000H in CROO When using the register as an event counter a one pulse count operation is not possible 148 User s Manual U12697EJ4V1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 3 Capture compare register 01 CR01 This is a 16 bit register that can be used as a capture register and a compare register Whether it is used as a capture register or compare register is specified by bit 2 CRC02 of capture compare control
549. th falling and rising edges Selection of valid edge of TIOO Falling edge Rising edge Setting prohibited Both falling and rising edges Selection of count clock fxx 4 3 13 MHz bo 16 781 kHz INTTM3 timer output for clock Valid edge of TIOO Caution When selecting the valid edge of TIOO as the count clock do not specify the valid edge of TIOO to clear and start the timer and as a capture trigger Also ensure that the count clock frequency is fxx 4 or lower Remark Figures in parentheses apply to operation at fxx 12 5 MHz User s Manual U12697EJAV1UD 155 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 4 Operation 8 4 1 Operation as interval timer 16 bits The 16 bit timer counter operates as an interval timer when 16 bit timer mode control register 0 TMC0 and capture compare control register 0 CRC0 are set as shown in Figure 8 6 In this case the 16 bit timer event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16 bit capture compare register 00 CR00 When the count value of 16 bit timer counter 0 TM0 matches the set value of CR00 the value of TM0 is cleared to 0 and the timer continues counting At the same time an interrupt request signal INTTM00 is generated The count clock ofthe 16 bittimer event counter can be selected by bits 0 and 1 PRM00 and PRM01 of prescaler mode register 0 PRM0 156 Figure 8 6
550. the XT2 side Caution When XT2and X1 are wired in parallel the crosstalk noise of X1may synergize with XT2 resulting in malfunction To prevent this from occurring it is recommended not to wire XT2 and X1 in parallel b Signal lines intersect each other PORTn n 0 to 10 12 13 d Current flows through the ground line of the oscillator potential at points A B and C fluctuates T X2 X1 Vssi k de High current 77 User s Manual U12697EJ4V1UD CHAPTER 4 CLOCK GENERATOR Figure 4 8 Examples of Incorrect Resonator Connection 2 2 e Signals are fetched X2 X1 Vss1 Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Caution When XT2 and X1 are wired in parallel the crosstalk noise of X1 may synergize with XT2 resulting in malfunction To prevent this from occurring it is recommended not to wire XT2 and X1 in parallel 4 4 4 Frequency divider The frequency divider divides the main system clock oscillator output fxx and generates various clocks 4 4 5 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to Vssi XT2 Leave open In this state however some current may leak via the internal feedback resistor of the subsyst
551. timer output TM0 also used as 14 bit PWM output P31 8 bit timer output TM1 also used as 8 bit PWM output P32 8 bit timer output TM2 also used as 8 bit PWM output Input P20 SI1 Serial data input UART1 P70 SI2 Serial data input UART2 RxD2 TxD1 Output P21 SO1 Serial data output UART1 P71 SO2 Serial data output UART2 TxD2 ASCK1 Input P22 SCK1 Baud rate clock input UART1 P72 SCK2 Baud rate clock input UART2 Input P25 SDA0Note Serial data input 3 wire serial 1 00 P20 RxD1 Serial data input 3 wire serial 1 01 P70 RxD2 Serial data input 3 wire serial 1 02 s s s s s s O O Output P26 Serial data output 3 wire serial 1 00 P21 TxD1 Serial data output 3 wire serial 1 01 P71 TxD2 Serial data output 3 wire serial 1 02 SDA0Note s l l l C C 25 510 Serial data input output 12C bus P27 SCLONote Serial clock input output 3 wire serial 1 00 P22 ASCK1 Serial clock input output 3 wire serial 1 01 P72 ASCK2 Serial clock input output 3 wire serial 1 02 P27 SCKO Serial clock input output 12C bus 1 2 0 2 0 1 2 M 1 0 1 2 K0 K1 K2 SCLoNeote N PO2 INTP2 Non maskable interrupt request input POO P01 2 P03 P04 P05 External interrupt request input Note
552. ting 486 User s Manual U12697EJAV1UD CHAPTER 24 STANDBY FUNCTION 2 Releasing STOP mode by INTPO to INTP5 input and watch timer interrupt If interrupt masking is released through INTP0 to INTP5 input and macro servicing is disabled the oscillator restarts oscillating when the valid edge specified by external interrupt edge enable register 0 EGP0 EGN0 is input to INTPO to INTP5 At the same time a watch timer overflow will occur and the STOP mode will be released when the watch timer interrupt mask is released and macro services are disabled If interrupts can be acknowledged when the STOP mode is released and the interrupt enable flag IE is set to 1 execution branches to the interrupt service program If the IE flag is cleared to 0 when acknowledgement is not possible execution starts again from the instruction following the instruction that set the STOP mode For details of interrupt acknowledgement refer to 22 7 Maskable Interrupt Acknowledgment Operation Figure 24 8 Example of Releasing STOP Mode by INTPO to INTP5 Input STOP STP F F1 STP F F2 INTPO to 5 inputs E the rising Mi edge is specified Oscillator stops Timer count time for oscillation stabilization Time until clock starts oscillating 3 Releasing STOP mode by RESET input When the RESET input rises from low to high and the reset is released the oscillator starts oscillating Oscillation
553. tion of package Before change GK BE9 type After change GK 9EU type Modification of I O circuit Addition of programmable wait control register 2 PWC2 1 4 Applied to Throughout Modification of Table 2 1 Types of Pin I O Circuits and Recommended Connection of Unused Pins CHAPTER 2 PIN FUNCTIONS Modification of stop condition for main system clock oscillator Modification of Figure 4 1 Block Diagram of Clock Generator Addition of caution about CST bit to Figure 4 4 Format of Clock Status Register PCS Modification of CPU clock speed in 4 5 Clock Generator Operations CHAPTER 4 CLOCK GENERATOR Modification of block diagram of ports 0 to 13 Addition of caution to Figure 5 21 Format of Pull up Resistor Option Register CHAPTER 5 PORT FUNCTIONS Modification of Figure 6 1 Block Diagram of Real Time Output Port Addition of caution to Figure 6 4 Format of Real Time Output Port Control Register RTPC Modification of 6 5 Using This Function CHAPTER 6 REAL TIME OUTPUT FUNCTIONS Modification of Table 8 3 Valid Edge of TIO1 Pin and Capture Trigger of CROO Addition of Table 8 4 Valid Edge of TIOO Pin and Capture Trigger of CRO1 Modification of Figure 8 4 Format of 16 Bit Timer Output Control Register TOCO Modification of description in 1 Pulse width measurement with free running counter and one capture register Modification of description in 2 Measurement of two pulse widths with free run
554. tionally stopped during the reset period l l i i l l l RESET input l l Timer count time for oscillation stabilization ome d Time until clock starts oscillating To prevent erroneous operation caused by noise a noise eliminator based on analog delay is incorporated at the RESET input pin 504 User s Manual U12697EJ4V1UD CHAPTER 25 RESET FUNCTION Figure 25 2 Receiving Reset Signal Time until clock starts oscillating Analog Oscillation Analog delay Analog delay delay stabilization time 1 1 e t H l l i l l l l l l i 1 1 l 1 1 1 l i RESET input Internal reset signal l Internal clock Hardware Main system clock oscillator State During Reset RESET L Oscillation stops Table 25 1 State of Hardware During and Atter Reset State After Reset RESET H Oscillation starts Subsystem clock oscillator Not affected by reset Program counter PC Undefined Value in reset vector table set Stack pointer SP Undefined Program status word PSW Initialized to 0000H Internal RAM value is saved before setting standby Undefined However when the standby state is released by a reset the I O lines Input and output buffers off High impedance Other hardware Initialized to the fixed stateNote_ Note
555. to the X2 pin Figure 4 6 shows the external circuit of the main system clock oscillator Figure 4 6 External Circuit of Main System Clock Oscillator a Crystal or ceramic oscillation b External clock External clock uPD74HCU04 Crystal resonator or ceramic resonator Caution When using a main system clock oscillator wire as follows in the area enclosed by the broken lines in the figure above to avoid an adverse effect from wiring capacitance also refer to 4 4 3 Examples of incorrect resonator connection Keep the wiring length as short as possible Donotcross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss1 Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator User s Manual U12697EJ4V1UD 97 CHAPTER 4 CLOCK GENERATOR 4 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator standard 32 768 kHz connected to the XT1 and XT2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the XT1 pin and the reverse phase clock signal to the XT2 pin Figure 4 7 shows the external circuit of the subsystem clock oscillator Figure 4 7 External Circuit of Subsystem Clock Oscillato
556. tor Conirol Registers 1 and 2 BRGC1 BRGC2 Address OFF76H OFF77H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 BRGCn o TPSn2 TPSn1 TPSn0 MDLn3 MDLn2 MDLn1 MDLn0 TPSn1 TPSn0 5 bit counter source clock selection External clock ASCKn fxx 12 5 MHz fxx 2 6 25 MHz fxx 4 3 13 MHz fxx 8 1 56 MHz fxx 16 781 kHz fxx 32 391 kHz TO1 TM1 output Baud rate generator input clock selection fsck 16 fsck 17 18 fsck 19 fsck 20 fsck 21 fsck 22 0 0 0 0 0 0 0 0 fsck 23 fscx 24 a AJOJN 25 26 k fsck 27 28 S N 29 fsck 30 e A Setting prohibited Cautions 1 If a write operation to BRGC1 and BRGC2 is performed during communication the baud rate generator output will become garbled and normal communication will not be achieved Consequently do not write to BRGC1 or BRGC2 during communication 2 Refer to CHAPTER 29 ELECTRICAL SPECIFICATIONS for details of the high low level width of ASCKn when selecting the external clock ASCKn for the source clock of the 5 bit counter 264 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL Cautions 3 Remarks 1 2 3 4 5 Set the 8 bit timer mode control register 1 TMC1 as follows when selecting TO1 for t
557. tput function outputs a rectangular wave with a cycle specified by the count value set in advance to 16 bit capture compare register 00 CROO and a pulse width specified by the count value set in advance to 16 bit capture compare register 01 CRO1 Figure 8 9 Control Register Settings in PPG Output Operation a 16 bit timer mode control register 0 TMCO TMC03 02 01 OVFO mco o jo o tj ojo Clears and starts on match between TMO and CROO b Capture compare conirol register 0 CRCO CRC02 CRC01 CRC00 eno CR00 used as compare register CR01 used as compare register c 16 bit timer output control register 0 TOC0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 Enables TOO output Reverses output on match between TMO and CROO Specifies initial value of TOO output Reverses output on match between and 01 Disables one shot pulse output Remark x Don t care Caution Make sure that CROO and CR01 are set to 0000H lt 01 lt CROO lt FFFFH 158 User s Manual U12697EJAV1UD CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 4 3 Pulse width measurement 16 bit timer counter 0 TM0 can be used to measure the pulse widths of the signals input to the TI00 P35 and TIO1 P36 pins Measurement can be carried out with TMO used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the TIOO P35 pi
558. trol Register 2 PWC2 CHAPTER 24 STANDBY FUNCTION Modification of Figure 24 1 Standby Function State Transition Addition of CHAPTER 29 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 30 PACKAGE DRAWINGS Addition of CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS APPENDIX B DEVELOPMENT TOOLS Addition of description on SP78K4 and change of Remark in B 1 Language Processing Software Modification of Remark in B 3 2 Software Addition of B 4 Cautions on Designing Target System APPENDIX C EMBEDDED SOFTWARE Deletion of MX78K4 description U12967JJ4VOUD00 U12967JJ4V1UD00 Modification of 1 2 Ordering Information Addition of lead free products to CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS The mark x shows major revised points User s Manual U12697EJ4V1UD 7 Target Readers Purpose Organization INTRODUCTION This manual is intended for user engineers who wish to understand the functions of the 784225 784225Y Subseries and design its application systems This manual describes the hardware functions of the uPD784225 and 784225Y Subseries The uPD784225 and 784225Y Subseries User s Manual is divided into two parts Hardware this manual and Instruction Hardware Instruction Pin functions CPU functions Internal block functions Addressing Interrupts Instruction set Other on chip peripheral functions Electrical specifications There are cautions associate
559. ttings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device User s Manual U12697EJ4V1UD EEPROM FIP and IEBus are trademarks of
560. uit for VCRs Enhanced timer uPD784976A On chip VFD controller driver Remark VFD Vacuum Florescent Display is referred to as FIP Florescent Indicator Panel in some documents but the functions of the two are the same 32 User s Manual U12697EJAV1UD CHAPTER 1 OVERVIEW 1 1 Features Inherits the peripheral functions of the uPD780058 Subseries Minimum instruction execution time 160 ns main system clock fxx 12 5 MHz operation 61 us subsystem clock 9 fxr 32 768 kHz operation Instruction set suited to control applications Interrupt controller 4 level priority Vectored interrupt servicing macro service context switching Standby function HALT STOP IDLE modes n the low power consumption mode HALT IDLE modes subsystem clock operation On chip memory Mask ROM 128 KB uPD784225 96 KB uPD784224 Flash memory 128 KB uPD78F4225 RAM 4 352 bytes uPD784225 78F4225 3 584 bytes uPD784224 I O pins 67 Software programmable pull up resistors 57 inputs LED direct drive possible 16 outputs Timers 16 bit timer event counter x 1 unit 8 bit timer event counter x 2 units 8 bit timer x 2 units Watch timer 1 channel Watchdog timer 1 channel Serial interfaces UART IOE 3 wire serial 1 0 2 channels on chip baud rate generator e CSI IICONete 3 wire serial I O multimaster supporting 12C busNete 1 channel A D converter 8 bit resolution x 8 channels D A converter 8 bit resolut
561. unction Pull up resistor option register Port mode register Port 12 read signal Port 12 write signal User s Manual U12697EJ4V1UD P120 RTP0 to P127 RTP7 127 CHAPTER 5 PORT FUNCTIONS 5 2 10 Port 13 This is 2 bit I O port with an output latch The input mode output mode be specified for the P130 and P131 pins in 1 bit units using the port 18 mode register Port 13 does not include pull up resistors Port 13 supports D A converter analog output as an alternate function RESET input sets port 13 to the input mode Figure 5 19 shows a block diagram of port 13 Caution When only one of the D A converter channels is used with AVner lt the other pins that are not used as analog outputs must be set as follows Set the port mode register PM13x to 1 input mode and connect the pin to Vsso Set the port mode register PM13x to 0 output mode and the output latch to 0 to output a low level from the pin Figure 5 19 Block Diagram of P130 and P131 Output latch 4 1 P130 P131 P131 ANO1 Internal bus PM130 PM131 Alternate function PM Port mode register RD Port 13 read signal WR Port 13 write signal 128 User s Manual U12697EJAV1UD CHAPTER 5 PORT FUNCTIONS 5 3 Control Registers The following three types of registers control the ports Port mode registers PMO PM2 to PM7 PM12 PM13 Pull up resistor option
562. unction Transmit only UART mode Serial function Serial function Transmit Receive Note sure to write 0 to bit 0 Caution Switch the operation mode after stopping serial transmission and reception Remark 1 2 266 User s Manual U12697EJAV1UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 16 3 2 Asynchronous serial interface UART mode This mode is used to transmit and receive the 1 byte data following the start bit and supports full duplex operation A UART dedicated baud rate generator is provided on chip enabling communication at any baud rate within a broad range The MIDI standard baud rate 31 25 Kbps can be used by utilizing the UART dedicated baud rate generator 1 Register setting The UART mode is set with asynchronous serial interface mode registers 1 and 2 ASIM1 ASIM2 asynchronous serial interface status registers 1 and 2 ASIS1 ASIS2 and baud rate generator control registers 1 and 2 BRGC1 BRGC2 User s Manual U12697EJAV1UD 267 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE 3 WIRE SERIAL 1 268 a Asynchronous serial interface mode registers 1 and 2 ASIM1 ASIM2 ASIM1 and ASIM2 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM1 and ASIM2 to OOH Address OFF70H OFF71H After reset Symbol ASIMn TXEn RXEn 00H PSn1 R W PSn0 Operation mode Operation stop RxD1 P20 RxD2 P70 pin fun
563. units 6 2 Configuration The real time output port includes the following hardware Table 6 1 Configuration of Real Time Output Port Registers Real time output buffer registers RTBL RTBH Control registers Real time output port mode register RTPM Real time output port control register RTPC User s Manual U12697EJ4V1UD 135 CHAPTER 6 REAL TIME OUTPUT FUNCTION Figure 6 1 Block Diagram of Real Time Output Port Internal bus C gt F Real time output port control register RTPC RTPOE BYTE EXTR Higher 4 bits of Lower 4 bits of Output trigger real time output real time output controller buffer register buffer register RTBH RTBL Real time output port mode register RTPM Port 12 Real time output controller port latch RTPOE bit P12n RTPn pin output n 0 to 7 136 User s Manual U12697EJAV1UD CHAPTER 6 REAL TIME OUTPUT FUNCTION Real time output buffer registers RTBL RTBH These 4 bit registers save the output data beforehand RTBL and RTBH are mapped to independent addresses in the special function register SFR area as shown in Figure 6 2 When the 4 bit x 2 channel operation mode is specified RTBL and RTBH can be independently set with data In addition if the addresses of both RTBL and RTBH are specified the data in both registers can be read together When the 8 bit x 1 channel operation mode is specified writing 8 bit data t
564. unt clock input temporarily stops and the count is read at that time In the following cases the count becomes OOH lt 1 gt RESET is input 2 TCEn is cleared 3 TMn and 0 match in the clear and start mode Caution In cascade connection mode the count becomes 00H by clearing both bit 7 TCE1 of 8 bit timer mode control register 1 TMC1 and bit 7 TCE2 of 8 bit timer mode control register 2 TMC2 Remark 1 2 8 bit compare registers 10 and 20 CR10 CR20 The values set in CR10 and CR20 are compared to the count value in 8 bit timer register 1 TM1 and 8 bit timer counter 2 TM2 respectively If the two values match an interrupt request INTTM1 INTTM2 is generated except in the PWM mode The values of CR10 and CR20 can be set in the range of 00H to FFH and can be written during counting Caution Be sure to stop the timer before setting data in cascade connection mode To stop the timer operation clear both bit 7 of TMC1 TCE1 and bit 7 of TMC2 TCE2 User s Manual U12697EJAV1UD 183 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 2 9 3 Control Registers The following four registers control 8 bit timer event counters 1 and 2 8 bit timer mode control registers 1 and 2 TMC1 TMC2 Prescaler mode registers 1 and 2 PRM1 PRM2 1 8 bit timer mode control registers 1 and 2 TMC1 TMC2 TMC1 and TMC2 make the following six settings 184 1 2 3 4 5 6 Control
565. ure 10 1 Block Diagram of 8 Bit Timers 5 and 6 1 2 1 8 bit timer 5 Internal bus TM6 compare match Edge detector 8 bit compare INTTM5 22 register 50 50 3 fux 28 fxx 24 2 fxx 28 3 fxx 2 8 bit timer fxx 29 counter 5 TM5 to TM6 Clear NTTM6 Wn Prescaler mode 8 bit timer mode register 5 PRM5 control register 5 TMC5 Internal bus Tees mos o User s Manual U12697EJAV1UD 201 CHAPTER 10 8 BIT TIMERS 5 6 Figure 10 1 Block Diagram of 8 Bit Timers 5 and 6 2 2 2 8 bit timer 6 Internal bus 6 O Edge detector 8 bit compare fxx 2 register 60 CR60 5 i me 5 y Match fxx 24 5 25 fux 2 T 8 bit timer fxx 29 counter 6 TM6 TM5 overflow Clear TCL62 TCL61 TCL60 TCE6 TMC66 TMC64 Prescaler mode 8 bit timer mode register 6 PRM6 control register 6 TMC6 Internal bus 202 User s Manual U12697EJ4V1UD CHAPTER 10 8 BIT TIMERS 5 6 1 8 bit timer counters 5 and 6 TM5 TM6 2 TM5 and TM6 are 8 bit read only registers that count the count pulses The counter is incremented in synchronization with the rising edge of the count clock When the count is read out during operation the count clock input temporarily stops and the count is read at that time In the following cases the
566. us mode the master can select a specific slave device by transmitting the slave address Address matching can be detected automatically by the hardware When the base address is set in slave address register 0 SVAO if the slave address transmitted from the master matches the address set in SVAO or if the extended code is received an INTIICO interrupt request occurs 18 5 10 Error detection In the 2 bus mode since the state of the serial bus SDAO during transmission is input to serial shift register 0 IICO of the transmitting device transmission errors can be detected by comparing the IICO data before and after the transmission In this case if the two data differ it can be judged that a transmission error occurred User s Manual U12697EJAV1UD 333 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 18 5 11 Extended codes 1 If the most significant four bits of the receiving address are 0000 or 1111 an extended code is received and the extended code received flag EXCO is set The interrupt request INTIICO is generated at the falling edge of the eighth clock The local address stored in slave address register 0 SVAO is not affected 2 In 10 bit address transfers the following occurs when 111110XX is setin SVAO and 111110XX0 is transferred from the master However INTIICO is generated at the falling edge of the eighth clock Higher 4 bits of data match EXCO 1Note 7 bit data match COIO 1Not
567. us register 0 IICSO Bit 4 in I C bus status register 0 IICSO EXCO 5 in 12 bus status register 0 IICSO MSTSO Bit 7 in I C bus status register 0 IICSO 300 User s Manual U12697EJAV1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY 2 12 bus status register 0 IICS0 The 50 register displays the status of the 12C bus IICSO is set by a 1 bit or 8 bit memory manipulation instruction IICSO can only be read RESET input sets IICSO to OOH Figure 18 4 Format of I2C Bus Status Register 0 50 1 3 Address OFFB6H After reset 00H R Symbol 5 MSTSO Master state Slave state or communication wait state Master communication state Clear condition MSTSO 0 Set condition MSTSO 1 When the stop condition is detected When start condition is generated When ALDO 1 Cleared by LRELO 1 When IICEO 1 0 When RESET is input No arbitration state or arbitration win state Arbitration failed state MSTSO is cleared Clear condition ALDO 0 Set condition ALDO 1 Automatically cleared after IICSO is readNote When arbitration failed When IICEO 210 When RESET is input EXCO Extended code reception detection The extended code is not received The extended code is received Clear condition EXCO 0 Set condition EXCO 1 When the start condition is detected When the most significant four bits of the rece
568. utput clock in addition to setting the PCL output clock User s Manual U12697EJAV1UD 351 CHAPTER 19 CLOCK OUTPUT FUNCTION 352 Figure 19 3 Format of Clock Output Control Register CKS Address OFF40H After reset OOH R W Symbol Remarks 1 2 3 4 7 6 5 4 2 3 1 0 BZOE Buzzer output control Refer to Figure 20 2 BCS1 BCSO Buzzer output frequency selection Refer to Figure 20 2 Clock output control Clock output stop Clock output start Clock output frequency selection fxx 12 5 MHz fxx 2 6 25 MHz fxx 4 3 13 MHz fxx 8 1 56 MHz bo 16 781 kHz fxx 32 391 kHz fxx 64 195 kHz fxx 128 97 7 kHz fxr 32 768 kHz Other than above fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency Setting prohibited Figures in parentheses apply to operation at fxx 12 5 MHz or fxr 32 768 kHz User s Manual U12697EJAV1UD CHAPTER 19 CLOCK OUTPUT FUNCTION 2 Port 2 mode register PM2 This register sets input output for port 2 in 1 bit units When using the P23 PCL pin for clock output set the output latch of PM23 and P23 to 0 PM2 is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 19 4 Format of Port 2 Mode Register PM2 Address OFF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 PM27 P
569. uyl n Vss Vpop RESET Vss Flash writing mode 27 3 2 On board overwrite mode functions By transmitting and receiving various commands and data by the selected communication protocol operations such as writing to the flash memory are performed Table 27 4 shows the major functions Table 27 4 Major Functions of On Board Overwrite Mode Function Description Area erase Erase the contents of the specified memory area Area blank check Checks the erase state of the specified area Data write Writes to the flash memory based on the start write address and the number of data written the number of bytes Area verify Compares the data input to the contents of the specified memory area Flash memory verification entails supplying the data to be verified from an external source via a serial interface and then outputting the existence of unmatched data to the external source after referencing the relevant area or all of the data Consequently the flash memory is not equipped with a read function and it is not possible for third parties to read the contents of the flash memory using the verification function User s Manual U12697EJAV1UD 517 CHAPTER 27 J4PD78F4225 AND uPD78F4225Y PROGRAMMING 27 3 3 Connecting Flashpro lll The connection between Flashpro Ill and the uPD78F4225 differs depending on the communication mode 3 wire serial or UART Figures 27 3 to 27 5 show the connecti
570. ve device process IIC0 lt FFHNete FFHNote ACKD0 STD0 SPD0 WTIMO H ACKEO H MSTSO L STTO L SPTO L WRELO INTIICO When SPIEO 1 Note Note TRCO L Receive Note Release the slave wait by either IICO FFH or setting WRELO 346 User s Manual U12697EJ4V1UD CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 21 Slave Master Communication Example When Master and Slave Select 9 Clock Wait 1 3 1 Start condition Address Master device process ACKD0 IIC0 STD0 SPD0 WTIMO H ACKE0 H MSTS0 STTO SPTO wes tn INTIICO TRCO Transfer lines SCLO 1 2 3 4 5 6 07 XD6 X D5 X D4 X D3 XD2 SDA0 Start condition Slave device process IIC0 IIC0 Data ACKD0 m STDO WTIMO H d ACKEO H MSTSO L STTO L SPTO L WRELO L NE INTIICO TRCO Note Release the slave wait by either IICO FFH or setting WRELO User s Manual U12697EJ4V1UD 347 CHAPTER 18 2 BUS MODE uPD784225Y SUBSERIES ONLY Figure 18 21 Slave Master Communication Example When Master and Slave Select 9 Clock Wait 2 3 2 Data Master device process IIC0 IIC0 FFH Note IIC0 FFHN0te ACKD0 N MSTSO q Receive TRCO L Transfer lines scio 8 SDAO DO MACK Slave device process IIC0 STDO ACKEO H
571. voltage application pin when setting the flash memory programming mode and writing or verifying the program In the normal operation mode connect directly to Vsso or pull down For the pull down connection use of a resistor with a resistance between 470 and 10 kQ is recommended 20 TEST This is the pin used in the IC test Connect directly to Vsso or pull down For the pull down connection use of a resistor with a resistance between 470 and 10 is recommended 52 User s Manual U12697EJ4V1UD CHAPTER 2 PIN FUNCTIONS 2 3 Pin I O Circuits and Recommended Connection of Unused Pins The I O circuit type of each pin and recommended connection of unused pins are shown in Table 2 1 For the I O circuit configuration of each type refer to Figure 2 1 Table 2 1 Types of Pin I O Circuits and Recommended Connection of Unused Pins 1 2 Circuit Type Recommended Connection of Unused Pins POO INTPO Input Independently connect to Vsso via a resistor PO1 INTP1 Output Leave open P02 INTP2 NMI PO3 INTP3 to POS INTP5 P10 ANIO to P17 ANI7 Connect to Vsso or Vppo P20 RxD1 SI1 Input Independently connect to Vsso via a resistor P21 TxD1 SO1 Output Leave open P22 ASCK1 SCK1 P23 PCL P24 BUZ P25 SDAQNete s o P26 SO0 P27 SCLONote SCKO P30 TOO to P32 TO2 P33 TI1 P34 TI2 P35 TI00 P36 TIO1 P37 EXA P40 ADO to P47 AD7 P50 A8 to P57 A15 P60 A16 to
572. wer consumption mode In this mode the CPU operating clock is stopped to decrease power consumption for the entire system Low power consumption IDLE mode This is a standby function in the low power consumption mode In this mode the oscillator continues operating while the rest of the system is stopped decreasing power consumption for the entire system These modes are programmable Macro servicing can be started from the HALT mode and the low power consumption HALT mode After macro service execution the device is returned to the HALT mode Figure 24 1 shows the standby function state transitions User s Manual U12697EJ4V1UD 463 CHAPTER 24 STANDBY FUNCTION Figure 24 1 Standby Function State Transition Macro service Low power Low power consumption IDLE mode set Low power consumption HALT mode set Low power consumption mede NMI INTPO to INTPS input consumption Subsystem JINTWT ote IDLE mode N Standby Interrupt ES ass t request for kj 2 masked interrupt gt E i 8 masked interrupt o 9 5 NI ES 38 8 ole Macro service request operation ti i Mis See One time processing ends clock Macro service ends x lt x So lt S R Q c 0 lt 8 x E e E Interrupt Interrupt S request for request Interrupt STOP masked for request Standby interrupt
573. witching Operation by Generation of an Interrupt Request Register bank switching RSBO RSB2 n Vector table 0000B Register bank Transfer 0 to 7 Q a T F o P Save Temporary register bits 8 to 11 User s Manual U12697EJAV1UD 385 CHAPTER 22 INTERRUPT FUNCTIONS The RETCS instruction is used to return from an interrupt that uses the context switching function The RETCS instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next This interrupt service program start address must be in the base area Caution The RETCS instruction must be used to return from an interrupt serviced by context switching Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used Figure 22 13 Return from Interrupt That Uses Context Switching by Means of RETCS Instruction Register bank n n 0 to 7 Restoration RETCS instruction operand Restoration Transfer Restoration To original register bank 386 User s Manual U12697EJAV1UD CHAPTER 22 INTERRUPT FUNCTIONS 22 7 3 Maskable interrupt priority levels The uPD784225 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt Multiple interrupts can be controlled by priority levels There are two kinds of priority cont
574. y generated at the same interval When counting stops set TCEn 0 Remark n 5 6 208 User s Manual U12697EJAV1UD CHAPTER 10 8 BIT TIMERS 5 6 Figure 10 6 Timing of Interval Timer Operation 1 3 a Basic operation TMn count value aa Y 01H Y XN X count starts eid Clear CRno N ae ar N TCEn INTTMn Interrupt request Interrupt request acknowledgement acknowledgement Interval time Interval time Interval time Remarks 1 Interval time N 1 xt N 00H to FFH 2 5 6 User s Manual U12697EJ4V1UD 209 CHAPTER 10 8 BIT TIMERS 5 6 Figure 10 6 Timing of Interval Timer Operation 2 3 b When CRn0 00H Count clock 1 h n m TMn OOH OOH I I ii CRn0 QOH OOH D teen 5 01 5 0 34 nrm LUU UUU 1 1 I Interval time c When CRn0 FFH t 1 l l Count cock_ T 1 l o j Tren oon rra l I l CRn0 FFH FH LL FH l TCEn INTTMn A A Interrupt request acknowledgement Interrupt request acknowledgement i Interval time Remark n 5 6 210 User s Manual U12697EJAV1UD CHAPTER 10 8 BIT TIMERS 5 6 Figure 10 6 Timing of Interval Timer Operation 3 3 d Operated by CRn0 transition M lt
575. y in TCE5 of TMC5 Note however that TCE5 of TMC5 and bit 7 TCE6 of TMC6 must be cleared when setting CR50 and CR60 Figure 10 8 shows a timing example of the cascade connection mode with 16 bit resolution Figure 10 8 Cascade Connection Mode with 16 Bit Resolution p sibi db isl CLIE inlet OOH TINTIN 2 TEL 2 TEESE TEIG T NIGRI 2 TA TR TM6 re eo CR50 P 5 TCE6 1 4 508 _ lt j Interval time Operation enabled Interrupt Operation Count starts request stopped generated Level inverted Counter cleared User s Manual U12697EJ4V1UD 213 CHAPTER 10 8 BIT TIMERS 5 6 10 5 Cautions 1 Error when the timer starts An error of up to 1 clock occurs before the match signal is generated after the timer is started This is because 8 bit timer counters 5 and 6 TM5 TM6 are started asynchronously to the count pulse Figure 10 9 Start Timing of 8 Bit Timer Counter Count pulse TM5 TM6 count value Timer starts 2 Operation after the compare register is changed while the timer is counting If the value after 8 bit compare registers 50 and 60 CR50 CR60 changes is less than the value of 8 bit timer counters 5 and 6 TM5 TM6 counting continues overflows and counting starts again from 0 Consequently when the value M after CR50 and CR60 change is less than the value N bef
576. ynchronous serial interface CSI Clocked serial interface User s Manual U12697EJ4V1UD Watch timer OFE38H The default priority is a fixed number This indicates the priority order when macro service requests CHAPTER 22 INTERRUPT FUNCTIONS 1 2 3 4 There are four kinds of macro services as shown below Type A One byte or one word of data is transferred between a special function register SFR and memory each time an interrupt request is generated and a vectored interrupt request is generated when the specified number of transfers have been performed Memory that can be used in the transfers is limited to internal RAM addresses 0FE00H to OFEFFH when the LOCATION instruction is executed and addresses to OFFEFFH when the LOCATION OFH instruction is executed The specification method is simple and is suitable for low volume high speed data transfers Type B As with type A one byte or one word of data is transferred between a special function register SFR and memory each time an interrupt request is generated and a vectored interrupt request is generated when the specified number of transfers have been performed The SFR and memory to be used in the transfers is specified by the macro service channel the entire 1 MB memory space can be used This is a general version of type A suitable for large volumes of transfer data Type C Data is transferred from memory to two specia

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