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USER`S MANUAL

1. 7 17 7 7 IOM2ICRD 2 IC Channel Receive Data 022 7 17 7 8 IOM2CITDO IOM2 Channel Transmit Data 7 18 7 9 IOM2CIRDO IOM2 Channel Receive Data Register 7 18 7 10 IOM2CITD1 IOM2 1 Channel Transmit Data 7 19 7 11 IOM2CIRD1 IOM2 1 Channel Receive Data Register 7 19 7 12 IOM2MTD 2 Monitor Channel Transmit Data 2 7 20 7 13 IOM2MRD 2 Monitor Channel Receive Data Register 7 20 7 14 IOM2STRB Strobe Register 7 21 8 1 HDLC External Pin Multiplexed 8 3 8 2 TSA Special 8 4 9 1 Special Registers 9 3 9 2 and GDMACON1 Registers 9 4 9 3 Control Register 9 4 9 3 Control Register Description 9 5 9 3 Control Register Description 9 6 9 4 GDMASRCO 1 and GDMADSTO 1 Registers 9 8 9 5
2. 3 29 Shifted Register 3 29 Bytes and Words 3 29 5 AMPLE 3 31 Restriction The Use of Base Register 3 31 Dat ADON 5 DEC MEM MM rcr T 3 31 Instruction Cycle Times 3 31 Assembler 3 32 3C4520A RISC MICROCONTROLLER Table of Contents Continued Table of Contents Continued Chapter 3 Instruction Set Continued Halfword and Signed Data Transfer LDRH ASTRHVWLDRSB LDRSH Offsets Auto Indexing pp Halfword Load and Stores pt Signed Byte and Halfword Endianness Byte Halfword RVD Ak A E DatasADOMS Instruction Cycle Times Assembler Syntax pp Block Data Transfer LDM Register List Addressing Modes pp Address ERE e Use ot The S BIS Use of R15 as The Inclusion of The Base In The Register LiSt 8 PRECEPIT e XP Instruction Cycle 5
3. 12 1 Merna pP 12 1 91 et Ci 12 1 Timer Operation Guidelines 5 5 5 35 2 12 2 TamerMode Reglslef 2 55 36 E tote eL 12 3 Timer Data 12 4 12 4 53 4520 RISC MICROCONTROLLER xi Table of Contents Concluded Chapter 13 Ports 13 1 Port Special Registers 13 2 I O Port Mode Register 0 13 2 Port Control Register 1 2 2 13 4 I O Port Data Register 13 9 Chapter 14 Interrupt Controller IRI p 14 1 Interr pt SoUlC6S A ta 14 2 Interrupt Controller Special Registers pp 14 3 Interrupt Mode Heglster 1 oie a 14 3 nterrupt Pending Registera 14 4 Interrupt Mask Red IE 14 5 Priority Registers 14 6 Interrupt Offset BeglSteres 14 7 Interrupt Pending By Priority Register 14 8 Interrupt Pending Test Register
4. 11 7 11 5 SIE Block Dla QAM P 11 9 11 6 mn 11 12 11 7 Used E E 11 14 11 8 Meis nte 11 16 11 9 WU SBINT REGISTE lies 2 11 18 11 10 WU SBEPINTE REJISTE eaa Genet eR RRR 11 20 11 11 11 22 11 12 USBFNL USBFNH 11 24 11 13 11 26 11 14 USBDISCONNECT 11 28 11 15 WSBMAXP REOISUC Mais D nU pem MIU mis E 11 30 11 16 USBIGSRT EPO ueteri Pe E P EE EE ENS 11 33 11 17 tsi E 11 36 11 18 5 2 695 6 11 38 11 19 USBOGSRi Beglslot sa 11 41 11 20 USBOGSR2 BSQlISIOL citet eno eua HEY E E 11 42 11 21 USBOWCL USBOWCH 11 44 11 22 USBEPO0 USBEP1 USBEP2 FIFO 11 46 11 23 USBEP3 USBEP4 FIFO Registers 11 46 12 1 Timer Output Signal 0 12 1 12 2 32 Bit Timer Block Diagram 12 2 12 3 Timer Mode Register
5. 14 6 14 6 INITOEESET BOISIOE rr Ee ni RENNES 14 7 14 7 INTENDPRI Register otn etr REP enr Pra trim er RENE E EIUS 14 8 14 8 INTENDIST EUER 14 8 15 1 Absolute Maximum 15 1 15 2 Recommended Operating Conditions pp 15 1 15 3 D C Electrical Characteristics 15 2 15 4 A C Electrical 15 3 A 1 PUIG INSTRUCTIONS 53 4520 RISC MICROCONTROLLER xxiii 53 4520 RISC MICROCONTROLLER PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION Samsung s S3C4520A 16 32 bit RISC microcontroller is a cost effective high performance microcontroller solution for ISDN TA Integrated Service Digital Network Terminal Adaptor Also provides the full rate USB Universal Serial Bus function The S3C4520A is built around an outstanding CPU core the 16 32 bit ARM7TDMI RISC processor designed by Advanced RISC Machines Ltd The ARM7TDMI core is a low power general purpose microprocessor macro cell that was developed for use in application specific and custom specific integrated circuits Its simple elegant and fully static design is particularly suitable for cost sensitive and power sensitive applications Most of the on chip function blocks have been designed using the Verilog HDL synthesizer and the S3C4520A has been fully verified in
6. Fours poemos vemo poe oc Rc OPERATION The Time Slot Assigner TSA controllers are configured as follows 1 Configure the TSAxCFG register Define the start bit position for each TSA Define the stop bit position for each TSA Determine operating mode for each TSA DCE PCM highway non multiplexed or multiplexed and IOM2 interface 2 Enable TSA by setting TSAEN bit in IOM2CON 13 to 1 3 Program each intended HDLC channel Clock Divide In PCM mode the TSA provides each HDLC channel with proper clock according to its programmed timeslot In this process the clock frequency is either the same as or 1 2 times that of the external clock When the Divide bit in TSAxCFG is set to 1 each HDLC channel is provided with half frequency clock of external clock and the tx data is shifted out every two external clock When the Divide bit in TSAxCFG is 0 each HDLC channel is provided with the external clock and the tx data is shifted out every one clock ELECTRONICS 8 3 TSA TIME SLOT ASSIGNER 3C4520A RISC MICROCONTROLLER TSA SPECIAL REGISTERS Table 8 2 TSA Special Registers
7. 3 83 Format 11 SP Relative Load Store 3 84 Operation rex 3 84 Instruction Cycle 5 3 84 Format 12 Load Addres cette eee 3 85 NN kk Cr 3 85 Instruction Cycle 5 3 86 Format 13 Add Offset Stack 3 87 a we CM Nos rer m 3 87 Instruction Cycle Times 4 3 87 Format 14 Push POP 3 88 DSK ALON ccc 3 88 Instruction Cycle 3 89 Format 15 Multiple 3 90 Operation x 3 90 Instruction Cycle 5 3 90 Format 16 Conditional Branch 3 91 Operation eh eect ALL DUAE 3 91 Instruction Cycle 3 92 Format 17 Software 3 93 lt 22 Wc 3 93 Instruction Cycle 44 4 00000010000 3 93 Format 18 Unconditional Branch 3 94 rrr 3 94 Format 1
8. 10 16 10 6 UART Receive Buffer 10 17 10 7 UART Baud Rate Divisor Register 10 18 10 8 UART Baud Rate Generator BRG 10 19 10 9 UART Control Character 1 Register 10 20 10 10 UART Control Character 2 Register 10 21 10 11 When Signal is Asserted During Transmit Operation 10 23 10 12 When CTS Signal is Deasserted During Transmit Operation 10 23 10 13 Normal Received Rx 10 24 10 14 CD Lost During Rx Data 10 24 10 15 Interrupt Based Serial Timing Diagram Tx and Rx Only 10 25 10 16 DMA Based Serial I O Timing Diagram TX 10 26 10 17 DMA Based Serial I O Timing Diagram Rx Only 10 26 10 18 Serial Frame Timing Diagram Normal 10 27 10 19 Infra Red Transmit Mode Frame Timing 10 27 10 20 Infra Red Receive Mode Frame Timing 10 28 xvi 53 4520 RISC MICROCONTROLLER List of Figures Concluded Figure Title Page Number Number 11 1 DOF Packet 3 11 2 11 2 frau 11 3 11 3 USB Erame Formiat 11 4 11 4 USB Core Block
9. 4 26 ROM SRAM FLASH Control Registers ROMCON 4 32 DRAM Control 4 37 DRAM Interface 4 45 DRAM Bank 4 47 DRAM Refresh and External I O Control 020 4 49 Chapter 5 Unified Instruction Data Cache VOT VIC EN HEP Rd 5 1 Cache 5 1 Cache Replace OperationsS pp 5 3 Gache Disable Enable 2 2 iiit XR ERREUR I RE a 5 4 Gache Flush Op ration e e eH 5 4 Non Cacheable Area Control 5 4 viii 53 4520 RISC MICROCONTROLLER Table of Contents Continued Chapter 6 HDLC Controller ie ae aa i hee 6 1 6 2 Function nnne 6 3 HDLC Frame 6 4 6 6 E M 6 6 Zero Insertion and Zero Deletion 6 6 locam Ea Mc 6 6 9 2 and 6 6 6 7 DMA SUPPORT A aS otk A cr 6 7 Baud Rate Gen
10. High renis PRIORITY20 High Priority Low Priority Figure 14 4 Interrupt Priority Register INTPRIn 14 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT OFFSET REGISTER The interrupt offset register INTOFFSET contains the interrupt offset address of the interrupt which has the highest priority among the pending interrupts The content of the interrupt offset address is bit position value of the interrupt source lt lt 2 If all interrupt pending bits are 0 when you read this register the return value is 0 0000005 This register is valid only under the IRQ FIQ mode in the ARM7TDMI In the interrupt service routine you should read this register before changing the CPU mode INTOSET_FIQ INTOSET_IRQ register can be used to get the highest priority interrupt without CPU mode change Other usages are similar to INTOFFSET NOTE If the lowest interrupt priority priority 0 is pending the INTOFFSET value will be 0 00000000 The reset value will therefore be changed to 0x0000005C to be differentiated from interrupt pending priority 0 Table 14 6 INTOFFSET Register INTOFFSET 0x424 interrupt offset register 0x0000005C INTOSET 0x430 FIQ interrupt offset register 0 0000005 INTOSET_IRQ 0x434 IRQ
11. S3C4520A BAO Figure 4 29 SDRAM Application Example 2 components have the following features 1M x 8bit x 2Banks 9bit column 11bit row address 4 48 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER DRAM REFRESH AND EXTERNAL I O CONTROL REGISTER The S3C4520A DRAM interface supports the CAS before RAS CBR refresh mode for EDO FP DRAM and auto refresh for SDRAM Settings in the DRAM refresh and external I O control register REFEXTCON control DRAM refresh mode refresh timings and refresh intervals REFEXTCON also contains the 5 bit base pointer value for the external I O bank 0 NOTE Whenever the S8C4520A CPU writes one of system manager registers the validity of special register field that is the VSF bit is automatically cleared and the external bus is disabled To reactivate external bus you must set the VSF bit to 1 using a STMIA instruction It is recommended that programmers always use STMIA instructions to write the 12 system manager special registers The instruction used to set the VSF bit should always be the last instruction in the register write sequence ELECTRONICS 4 49 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER 21 20 19 17 16 15 14 External I O Bank 0 Base Pointer REFEXTCON Refresh Count Value 4 0 External I O bank 0 base pointer base address This value is the start address of I O external I O bank 0 Start address is defined as external I O ba
12. A 3 57 RAD eL 3 57 Instruction Cycle Times 3 57 Assembler SyntaX 3 57 Undefined Instruction 3 58 Instruction Cycle Times 7 3 58 Assembler 3 58 Using The Conditional InstructionsS 3 59 Pseudo Random Binary Sequence 3 61 Multiplication By Constant Using The Barrel Shifter pp 3 61 Thumb Instruction Set 3 64 FORMAL SUMMARY edite Ue dini cte 3 64 OPCOUESUMMMALY EROR 3 65 Format 1 Move Shifted Register 3 67 OPT ATOM eee TEC 3 67 Instruction Cycle Times 3 67 Format 2 3 68 Golem ER Pc v 3 68 Instruction Cycle Times 3 69 Format 3 Move Compare Add Subtract Immediate 3 70 ies x EE 3 70 Instruction Cycle Times 3 70 Format 4 Alu 3 71 PST ATOM peers 3 71 Instruction Cycle Times 3 72 Format 5 Hi R
13. 4 25 4 13 External I O Access Control Registers EXTACONO 4 27 4 14 External I O Read Timing 1 4 0 tags 1 4 28 4 17 External MO Write Timing with nEWAIT 1 7 8 0 tagg 1 4 31 4 18 ROM SRAM FLASH Control Registers ROMCONO 1 4 33 4 19 ROM SRAM Flash Read Access 4 34 4 20 ROM Flash Page Read Access 4 35 4 21 ROM SRAM Flash Write Access 4 36 4 22 DRAM Control Registers 4 38 4 23 EDO FP DRAM Bank Read Timing Page Mode 4 39 4 24 EDO FP DRAM Bank Write Timing Page Mode 4 40 4 25 EDO FP DRAM Bank Read Write Timing Page 4 41 4 26 SDRAM Power up 4 42 4 27 Non burst Read Write Read Cycles CAS Latency 2 Burst Length 1 4 43 4 28 SDRAM Burst Radnim aen a ea ENE a aa an aa aeai 4 44 4 29 SDRAM Application Example Nt 4 48 4 30 DRAM Refresh and External I O Control Register REFEXTCON 4 50 4 31 External I O Bank Address 4 51 4 32 EDO FP DRAM Refresh
14. 4 13 4 13 Byte Access Store Operation with Little Endian 4 14 4 14 Byte Access Load Operation with 4 14 4 15 Bus Priorities for Arbitration pp 4 15 4 16 SYSGEG Register Pepe pese ea qu sae ERR 4 16 4 17 PROREWV Reglslet cre rera pex xe eR 4 18 4 18 GER ROGISTE a 4 19 4 19 WDT ERR 2 4 20 4 20 Watch Dog Timer Timeout Value WDTVAL X Don t 4 21 4 21 CLK CON Register 4 22 4 22 Register Description Nt 4 22 4 23 External I O Access Control Register Description 4 26 4 24 ROM SRAM Flash Control Register Description 4 32 4 25 DRAM and External I O Control Register Description 4 37 4 26 CAN and Address MUX 4 47 6 1 HDLC Data Frame 6 4 6 2 Baud Rate Example 6 8 6 3 HDLC SETUP HOLD Time Table ena 6 13 6 4 HDLC Channel A Special Registers 6 20 6 5 HDLC Channel B Special Registers 6 21 6 6 HDLC Channel Special 6 22 6 7
15. Bi E IR Tx IR Tx Encoder RxBuffer Register Receiver FIFO UCON IR 32 Bytes 7 RxDn 2 Shift Nu A BaudRate Generator and Detector UCLK 49 10 2 UCLK Figure 10 1 Serial I O Block Diagram ELECTRONICS 3C4520A RISC MICROCONTROLLER UART UART SPECIAL REGISTERS Table 10 1 UART Special Registers Overview URXBUF 0 receive butter register ooo ELECTRONICS 10 3 UART 3C4520A RISC MICROCONTROLLER UART CONTROL REGISTERS Table 10 2 UART Control Registers UCON 0 00 UART control register Table 10 3 UART Control Register Description Bit Number Reset Value 1 0 Transmit mode TMODE This two bit value determines which function is currently able to write Tx data to the UART transmit buffer register UTXBUF 00 disable Tx mode 01 interrupt request 10 GDMA request 11 Reserved 3 2 Receive mode RMODE This two bit value determines which function is currently able to write Tx data to the UART transmit buffer register UTXBUF 00 disable Rx mode 01 interrupt request 10 GDMA request 11 Reserved Send Break SBR Set this bit to one to cause the UART to send a break If this bit value is zero a break does not send A break is defined as a continuous Low level signal on the transmit data output with the duration of more than one frame transmission time 1 External UCLK Auto Baud Rate Detect
16. 1 PADDR12 output2 X amp 168 1 PADDR13 output2 amp 167 1 PADDR14 output2 amp 166 1 PADDR15 output2 amp 165 1 PADDR16 output2 amp 164 1 PADDR17 output2 amp 163 1 PADDR18 output2 amp 162 1 PADDR19 output2 amp 161 1 PADDR20 output2 amp 160 1 PADDR21 output2 amp 159 4 PXDATAO observe_only X amp 158 BC_1 control 1 amp 157 1 PXDATAO output3 X 158 1 2 amp 156 4 PXDATAt observe_only amp 155 1 PXDATA1 output3 X 158 1 2 amp 154 4 PXDATA2 observe_only amp 153 1 PXDATA2 output3 X 158 1 2 amp 152 4 observe only X amp 151 1 output3 X 158 1 2 amp 150 4 PXDATA4 observe_only X amp 149 BC_1 PXDATA4 output3 X 158 1 Z amp 148 BC_4 PXDATAS observe only X amp 147 BC 1 PXDATAS output3 X 158 1 2 amp 146 4 PXDATAG observe only X amp 145 BC 1 PXDATAG output3 X 158 1 Z amp 144 4 observe only X amp 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER 143 1 142 4 PXDATAS 141 1 PXDATAS 140 4 PXDATAQ 139 1 PXDATAQ 138 4 PXDATA10 137 1 PXDATA10
17. Js L T B 1 0 SIO transmit mode selection TMODE 00 Disable 01 Interrupt request 10 GDMA channel 0 1 2 request 11 Reserved 3 2 SIO receive mode selection RMODE 00 Disable 01 Interrupt request 10 GDMA channel 0 1 2 request 11 Reserved 4 Send Break SBR 0 Normal TxData send 1 Send Break signal 5 Serial Clock Selection CKSL 0 Internal systen clock divided 2 MCLK2 1 External UART clock UCLK zmn woor 6 Auto Baud Rate Detect AUBD 0 Normal operating mode 1 Auto Baud Rate Detect mode 7 Loopback mode LOOB 0 Normal operating mode 1 Enable Loopback mode only for test 10 8 Parity mode PMD 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 11 Stop Bits STB 0 1 stop bit 1 2 stop bits 13 12 Word Length WL 00 5 bit 01 6 bit 10 7 bit 11 8 bit 14 Infra red mode IR 0 normal operating mode 1 Infrared Tx Rx mode 15 Reserved This bit should be cleared Figure 10 2 UART Control Register 10 7 UART 3C4520A RISC MICROCONTROLLER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 W 15 L T B 16 Transmit FIFO Enable TFEN 0 Disable Transmit FIFO 1 Enable Transmit FIFO 17 Receive FIFO Enable RFEN 0 Disable Receive FIFO 1 Enable Receive FIFO 18 Tranmit FIFO Reset TFRST
18. 0 tacc 7 tcos 1 17 External I O Write Timing with nEWAIT Figure 4 4 31 ELECTRONICS SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER ROM SRAM FLASH CONTROL REGISTERS ROMCONO The System Manager has two control registers for ROM SRAM and flash memory see Table 4 24 These registers correspond to the up to two ROM SRAM Flash banks that are supported by 53 4520 For ROM SRAM Flash bank 0 the external data bus width is determined by the signal at the BOSIZE When BOSIZE 0 the external bus width for ROM SRAM Flash bank 0 is 8 bits When BOSIZE 1 the external bus width for ROM SRAM Flash bank 0 is 16 bits You can determine the start address of a special register s bank by the value of the corresponding special register bank base pointer The control register s physical address is always the sum of the register s bank base pointer plus the register s offset address NOTE If you attach SRAM to ROM SRAM Flash bank you must set the page mode configuration bits ROMCONn 1 0 in the corresponding control register to 00 normal ROM Table 4 24 ROM SRAM Flash Control Register Description ROMCONO 0x30C R W ROM SRAM Flash bank 0 control register 0 01000160 ROMCON 1 0x310 R W ROM SRAM Flash bank 1 control register 0x00000060 4 32 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER 1098 7 6 4 3 2 ROM SRAM Flash ROM SRAM Flash ROMCON Bank Next Pointer EN Ba
19. 3 7 Assembler rns 3 8 D ta PROCESSING NERONE D 3 9 GPSR FAQS RPM DTE 3 11 ricer eerie ne i EIC MEE 3 12 Immediate Operand RotateS 3 16 dcc TT E 3 16 Using R15 as an 3 16 TST and 3 16 Instruction Cycle Times 3 17 Assembler nnns 3 17 PSR Transfer MRS 3 19 Operand Restrictions Nt 3 19 5 8 yak teh eL 3 21 Instruction Cycle Times 3 21 Assembler 3 22 Multiply And Multiply Accumulate MUL MLA 3 23 CRSP BAGS a ute Skt keke KW cx 3 24 Instruction Cycle Times 3 24 Assembler 2 00 10 3 24 Multiply Long And Multiply Accumulate Long MULL MLAL 600000 3 25 Operand 8 3 25 GROR BIAS A 3 26 Instruction Cycle Times 3 26 Assembler SyntaX 10 3 27 Single Data Transfer LDR 3 28 Offsets and
20. by copying the current values of the PC and CPSR into them The value of the saved PC and SPSR is not defined Forces M 4 0 to 10011 Supervisor mode sets the and F bits in the CPSR and clears the CPSR s T bit Forces the PC to fetch the next instruction from address 0 00 4 Execution resumes in ARM state 2 16 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set a0nd the THUMB instruction set in the ARM7TDMI core FORMAT SUMMARY The ARM instruction set formats are shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 ome fs m PeR Traneier cond Rm Ca 6 Cond ofofo fofola Single data swap e ekk eE EERE E hee e Branch and exchange _ register offset Ofen Offset Single data transfer fpf Ce Le T 9m Pre 0m em Cem ore Sr Ban Ignored by processor Software Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2 1 0 Figure 3 1 ARM Instruction Set Format NOTE Some instruction codes are not def
21. 1 1 pticu JTAGTestModeSelec TD 1 jJTAGTestDataln 1 O pot jJTAGTestDataOu 1 pticu JTAG NotReset O Interface 55 ADDR 10 AP Auto Precharge Control Pin 15 0 16 ptbsut6 External bidirectional 16 bit data bus E nSDCS 1 0 Chip Select for SDRAM E 7 nSDRAS Not row address strobe for SDRAM E 7 A nSDCAS Not column address strobe for SRAM 1 Clockenablesignalfor SDRAM _ nDWE 1 O jNotWrteEnabe nECSISO 4 0 Notexemall O Chip select nEWAT 1 1 NotExtemalwaitsignal 2 0 NotROM SRAM Flash Chip select 1 1 pre Bank 0 Data Bus Access m 1 O jNotouputenable DMQ 1 0 Data inpu output mask signal for SDRAM USBD 1 pbusb fs Internal USB transceiver differential VO USBD 1 pbusb fs Internal USB transceiver differential VO T USB XCLKO USB clock source 1 i USB CLKSEL 1 _ USB Clock Select USB_FILTER Filter for USB PLL PLL1 ELECTRONICS 1 13 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 2 S3C4520A Pin List and PAD Type Continued Pin Type Pad Type Description Counts IOM2_DU 1 B O ptbst4sm IOM 2 Data Upstream Open D
22. 14 8 Chapter 15 Electrical Data LV 15 1 Absolute Maximum Ratings 3 15 1 Recommended Operating Conditions 15 1 D C Electrical 15 2 Chapter 16 Mechanical Data OVOIVIOW 16 1 RAAN EA ol a E E E E 1 Boundary Scam ote A 3 Instruction 1270 A 3 Boundary Scan Definition A 4 xii 3C4520A RISC MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C4520A Block 1 4 1 2 S3C4520A Pin Assignment Diagram pp 1 5 1 3 Reset Timing DIA Grains rere root Er Rege 1 18 1 4 ARMTTDMI Core Block Diagrarmn 1 19 2 1 Big Endian Addresses of Bytes within 2 2 2 2 Little Endian Addresses of Bytes Words Ne 2 2 2 3 Register Organization in ARM 2 5 2 4 Register Organization in THUMB 2 6 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 7 2 6 Program Status Register 2 8 3 1 ARM Instruction Set Format pp 3 1 3 2 Branch and Exchange 3 5
23. Controller Block Diagram 9 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER DMA CONTROLLER GDMA SPECIAL REGISTERS Table 9 1 GDMA Special Registers Overview Registers Description Reset vae ELECTRONICS 9 3 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER GDMA CONTROL REGISTERS Table 9 2 GDMACONO and GDMACON Registers Registers GDMACONO 0xB00 GDMA controller channel 0 control register 0x00000000 GDMACONt 0xB80 GDMA controller channel 1 control register 0x00000000 GDMACON2 Table 9 3 GDMA Control Register Description Bit Number Reset Value Run enable disable Setting this bit to 1 starts DMA operation To stop DMA you must clear this bit to 0 You can use the GDMA run bit control address GDMACON offset address 0x20 to manipulate this bit By using the run bit control address other GDMA control register values are not affected 1 Busy status When DMA starts this read only status bit is automatically set to 1 When it is 0 DMA is idle 3 2 mode selection 4 sources group can initiate a DMA operation 1 software memory to memory 2 an external DMA request 3 UART mode only GDMAO0 1 2 4 mode 4 Destination address This bit controls whether the destination address will be direction decremented 1 or incremented 0 during a DMA operation 5 Source address direction This bit controls whether the source address will be
24. 12 3 12 4 Timer Data Registers TDATAO TDATA 12 4 12 5 Timer Counter Registers 0 TCNTT 12 4 13 1 VO Port Function Diagram isien iaaea peg pezin neu tu Rn RR 13 1 13 2 MO Port Mode Register IOPMODO 13 2 13 3 Port Mode Register IOPMOD1 13 3 13 4 MO Port Control Register 0 13 5 13 6 Port Control Register 2 13 8 13 7 Port Data RegisterO 13 9 13 9 External Interrupt Request Timing Active High 13 10 13 10 External Interrupt Request Timing Active 1 0 13 10 14 1 Interrupt Mode Register INTMOD 14 3 14 2 Interrupt Pending Register 14 4 14 3 Interrupt Mask Register 14 5 14 4 Interrupt Priority Register 14 6 A 1 TAP Controller State Machine A 2 3C4520A RISC MICROCONTROLLER xvii List Tables Table Title Page Number Number 1 1 S3C4520A Signal Descriptions 1 6 1 2 53 4520 Pin List and PAD Type 1 13 1 3 SICADZ0A PAD M 1 17 1 4 S3C4520A CPU 1 23 1 5 S3C4520A Special 1 24 2 1 PSR Mode Bit Values ienser enar E e E E 2 10 2 2 Exception ina eaa E aN
25. 136 4 PXDATA11 135 1 PXDATA11 134 4 PXDATA12 133 1 PXDATA12 132 4 PXDATA13 131 1 PXDATA13 130 4 PXDATA14 129 BC 1 PXDATA14 128 4 PXDATA15 127 1 PXDATA15 126 4 PUCLK_PP16 125 1 control 124 BC 1 PUCLK 16 122 BC 1 control 121 BC 1 PUTXD PP17 120 BC 4 PURXD 8 119 BC 1 control 118 1 PURXD 8 117 4 PnUDSR_PP19 116 BC 1 control 115 BC_1 PnUDSR_PP19 output3 X 158 1 Z amp observe only amp output3 158 1 Z amp observe only X amp output3 158 1 Z amp observe only X amp output3 X 158 1 Z amp observe only X amp output3 158 1 Z amp observe only amp output3 X 158 1 2 amp observe only amp output3 158 1 Z amp observe only X amp output3 X 158 1 2 amp observe only amp output3 158 1 Z amp observe only amp 1 amp output3 X 125 1 Z amp observe only X amp 1 amp output3 X 122 1 Z amp observe only X amp 1 amp output3 X 119 1 Z amp observe only X amp 1 amp output3 X 116 1 Z amp 114 4 PnUDTR_PP20 observe only amp 113 BC 1 control 1 112 1 PnUDTR_PP20 output3 X 113 1 2 amp 111 BC 4 PnURTS_PP21 observe
26. 18 Tx abort TxABT 0 Normal 1 eight consecutive 1s are transmitted 19 Tx preamble 0 Transmit a mark idle is time fill bit pattern 1 Transmit the content of HPRMB 20 Tx data terminal ready TxDTR 0 nDTR goes high level 1 nDTR goes low level 21 Tx request to send TxRTS 0 nRTS changes automatically 1 nRTS goes low level 22 Rx echo mode RXECHO 0 Disable Tx auto echo mode 1 Enable Rx Tx block is reset 23 Rx frame discontinue RXDISCON 0 Normal 1 Ignore the currently received frame 24 Tx No CRC TxNOCRC 0 Disable 1 CRC is not appended by hardware 25 Rx No CRC RxNOCR 0 Disable 1 Receiver does not check CRC by hardware CRC is treated as data in any case 26 Rx STOP RxSTOP 0 normal 1 receiver stops receiving 27 Auto enable AutoEN 0 The nCTS and nDCD doesn t affects the transmitter and the receiver 1 The nDCD and nCTS affects the transmitter and the receiver 29 28 Data Sample SMPL 00 2 cycle before nDCD transition 01 1 cycle before nDCD transition 10 0 cycle before nDCD transition same cycle 11 1 cycle after nDCD transition 31 29 Reserved Figure 6 11 HDLC Control Register HCON Continued ELECTRONICS 6 31 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC STATUS REGISTER HSTAT NOTE Reading the HDLC status register is a non destructive process The method used to clear a High lev
27. 19 Transmit FIFO Empty TFEMT 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 20 Transmit FIFO full TFFUL 0 Transmit FIFO is full 1 Transmit FIFO is full 31 21 Reserved Figure 10 3 UART Status Register Continued ELECTRONICS 10 13 UART 3C4520A RISC MICROCONTROLLER Table 10 6 UCON Interrupt Enable Registers UINTEN OxE08 UART Interrupt Enable register Table 10 7 UART Interrupt Enable Register Description 0 2 3 4 5 6 7 DCDLIE DCD High at receiver checking time interrupt enable RFREAIE Receive FIFO Data trigger level reach interrupt enable 9 Reseved 1 10 OVFFIE Receive FIFO overrun interrupt enable Reserved 12 RxTOIE Receive Event time out interrupt enable 1811 Reserved OSO 16 E CTSIE CTS Event occurred interrupt enable Reseved 18 THEIE Transmit Holding Register Empty interrupt enable Reserved o o SOS B CCDIE Control Character Detect interrupt enable 10 14 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 m m nm o m r couojo m m o 0 Receive Data Valid Interrupt Enable RDRIE 1 Break Signal Detected Interrupt Enable BSDIE 2 Frame Error Interrupt Enable FERIE 3 Parity Error Interrupt Enable PERIE 4 Overrun Error Interrupt Enable OVEIE 5 Control Character Detect In
28. 4 52 4 33 Auto Refresh Cycle of SDRAM 4 53 3C4520A RISC MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 5 1 Memory Configuration for 4 Kbyte 5 2 5 2 Cache Replace Algorithm State 5 3 6 1 HDLC Module Block 6 3 6 2 Baud Rate Generator Block Diagrarmn pp 6 7 6 3 Block BIET CES 6 9 6 4 Clock Usage Method Diagram 6 9 6 5 Data Encoding Methods and Timing 6 12 6 6 Data Setup and Hold Timing 6 13 6 7 NCTS already Asserted Nt 6 18 6 8 CTS Lost during Transmissigon 6 18 6 9 6 19 6 10 Ren pee RR ep rapa rb 6 25 6 11 HDLC Control Register Nt 6 30 6 12 HDEG Status 00 6 35 6 13 HDLC Interrupt Enable Register 6 38 6 14 HDLC Tx FIFO Function Diagram 6 39 6 15 HDLC Rx FIFO Function 6 40 6 16 HDLC Time Constant Register 6 41 6 17 HDLC Preamble Constant Register 6 42 6 18 Address 6 43 6 19 HDLC Station Address and HMASK 6 44
29. 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BC 4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ELECTRONICS APPENDIX A PnDCDA xDACK3 PP37 output3 X 62 1 2 amp PTXDA DU observe only X amp PTXDA DU output2 1 59 1 Weak1 amp drain output DD observe only X amp PRXDA DD output2 1 57 1 1 8 open output PnDTRA output2 amp PnRTSA_STRB output2 amp observe only X amp control 1 amp output3 X 53 1 Z amp PRXCA DCL observe only X amp PnCTSB_xDREQ4 observe only X amp E control 1 amp PnCTSB XDREQA output3 X 49 1 2 amp PnDCDB_xDACK4_PP1 observe_only X amp control 1 amp PnDCDB_xDACK4_PP1 output3 X 46 1 Z amp PTXDB_PP2 observe only X amp 7 control 1 amp 2 output3 X 43 1 2 amp observe only X amp control 1 amp PRXDB PP3 output3 X 40 1 Z amp PnDTRB observe only X amp E control 1 amp PnDTRB_PP4 output3 X 37 1 Z amp PnRTSB PP5 observe only X amp control 1 amp PnRTSB_ PP5 output3 X 34 1 2 a
30. Figure 1 4 ARM7TDMI Core Block Diagram ELECTRONICS 1 19 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER INSTRUCTION SET The S3C4520A instruction set is divided into two subsets a standard 32 bit ARM instruction set and a 16 bit THUMB instruction set The 32 bit ARM instruction set is comprised of thirteen basic instruction types which can in turn be divided into four broad classes e Four types of branch instructions which control program execution flow instruction privilege levels and switching between an ARM code and a THUMB code e Three types of data processing instructions which use the on chip ALU barrel shifter and multiplier to perform high speed data operations in a bank of 31 registers all with 32 bit register widths e Three types of load and store instructions which control data transfer between memory locations and the registers One type is optimized for flexible addressing another for rapid context switching and the third for swapping data e Three types of co processor instructions which are dedicated to controlling external co processors These instructions extend the off chip functionality of the instruction set in an open and uniform way NOTE All 32 bit ARM instructions can be executed conditionally The 16 bit THUMB instruction set contains 36 instruction formats drawn from the standard 32 bit ARM instruction set The THUMB instructions can be divided into four functional groups e Four branch in
31. Number of access cycles for each DRAM bank and CAS strobe time CAS pre charge time RAS to CAS delay RAS pre charge time The refresh and external I O control register REFEXTCON controls DRAM refresh operations and external bank accesses The S3C4520A eliminates the need for an external refresh signal by automatically issuing an internal CAS before RAS refresh or auto refresh control signal The S3C4520A generates row and column addresses for DRAM accesses with 25 bit internal address bus It also supports symmetric or asymmetric DRAM addressing by changing the number of column address lines from 8 to 11 EDO Mode DRAM Accesses The timing for accessing a DRAM in EDO mode is comparable to DRAM accesses in normal fast page mode However in EDO mode the 53 4520 CPU fetches data when read one half clock later than in normal fast page mode This is possible because EDO mode can validate the data even if CAS goes High when RAS is Low In this way gives the CPU sufficient time to access and latch the data so that the overall memory access cycle time can be reduced Synchronous DRAM Accesses Synchronous DRAM interface features are as follows e MRS cycle with address key program CAS latency 2 cycles Burst length 1 Burst type Sequential e Auto refresh e Four word burst transfer for cache line fill operation e SDRAM interface signal SDCLK nSDCS 1 0 nSDCAS nSDRAS DQM 1 0 ADDR 10 AP The add
32. a1 a1 0 ip a4 a2 ASR 32 a2 a2 0 Effectively zero a4 as top bit will be shifted out later Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS BEQ just CMP MOVLS BLO div CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV ELECTRONICS a3 a1 divide by zero a2 LSR 1 a3 LSL 1 S loop a2 a3 a4 a4 a4 a2 a2 a3 a3 a1 a3 LSR 1 S loop2 al a4 ip ip ASL 1 a1 a1 0 a2 a2 0 Ir Justification stage shifts 1 bit at a time NB LSL 1 is always OK if LS succeeds 3 99 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code Thumb Code udiv10 Take argument in a1 returns quotient in a1 remainder a2 MOV a2 al LSR a3 a1 2 SUB a1 a3 LSR a3 al 4 ADD al a3 LSR a3 a1 8 ADD al LSR 16 ADD al LSR al 3 ASL a3 a1 2 ADD a3 a1 ASL 1 SUB a2 a3 CMP a2 10 BLT ADD al 1 SUB a2 10 0 MOV Ir ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB a1 al a1 Isr 2 ADD a1 a1 a1 Isr 4 ADD a1 a1 a1 Isr 48 ADD al a1 al
33. sss nennen nennen nnne 11 35 USB In CSR register 2 7 11 37 USBICSR2 11 37 USB Out CSR register 1 2 0 0 nnn nnn nnn nnns nnns 11 39 USBOCSR 1 11 39 USBOCSR2 11 40 USB Out Write Count register 1 2 11 43 05 1 2 3 4 5 ens 11 45 TMOD Register pp 12 3 TDATAO and TDATA1 Registers 12 4 1 12 4 53 4520 RISC MICROCONTROLLER List of Tables concluded Table Title Page Number Number 13 1 eld optime E 13 2 13 2 IOPMOD 31 H89glslet M RRRRED 7 13 3 13 3 2 13 4 13 4 IOPCONT ITem 13 6 13 5 2 13 7 13 6 io dB qp 13 9 13 7 Em 13 9 14 1 S3C4520A Interrupt Sources 14 2 14 2 INTDMOD REGIS M n 14 3 14 3 IRR IBEecie m E 14 4 14 4 INT Register e Ete er PEINE 14 5 14 5 Interrupt Priority Register 0012 1 00000
34. ELECTRONICS 4 1 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER REGISTERS To control the external memory operations the System Manager uses a dedicated set of special registers see Table 4 1 By programming the values in the System Manager special registers you can specify such things as Memory type External bus width access cycle Control signal timing RAS and CAS for example Memory bank locations The sizes of memory banks to be used for arbitrary address spacing The System Manager uses some special registers to control the generation and processing of the control signals addresses and data that are required by the external devices in a standard system configuration The special registers are also used to control access to two banks of ROM SRAM Flash two banks of DRAM four banks of the external I O banks and a special register mapping area The address resolution for each memory bank base pointer is 1M bytes 20 bits And the base address pointer is 5 bits This gives a total addressable memory bank space of 16 M Half words NOTE When writing a value to a memory bank control register from ROMCONO to REFEXTCON locations 0x30C to 0x31C as shown in Table 4 1 you must always set the register using a single STM Store Multiple instruction Additionally the address spaces for successive memory banks must not overlap in the system memory map 4 2 ELECTRONICS 3C4520A RISC MICROCONTROLLE
35. Ee control PxIREQ3 PP27 PTOUTO PP28 E control PTOUTO PP28 PTOUT1_PP29 control PTOUT1_PP29 PxDREQO PP30 control PxDREQO PP30 PxDACKO PP31 control PxDACKO_PP31 PxDREQ1_PP322 control PxDREQ PP32 PxDACK1 PP33 control PxDACK1 PP33 PxDREQ2 PP34 E control PxDREQ2 PP34 PxDACK2 PP35 e control PxDACK2 PP35 observe only X amp 1 amp output3 X 101 1 Z amp observe only X amp 1 amp output3 98 1 Z amp observe_only X amp 1 amp output3 X 95 1 Z amp observe_only X amp 1 amp output3 X 92 1 2 amp observe only X amp 1 amp output3 X 89 1 2 amp observe only X amp 1 amp output3 X 86 1 2 amp observe_only amp 1 amp output3 X 83 1 Z amp observe only X amp 1 amp output3 X 80 1 Z amp observe_only X amp 1 amp output3 X 77 1 2 amp observe only X amp 1 amp output3 X 74 1 Z amp observe only amp 1 amp output3 X 71 1 Z amp observe only X amp 1 amp output3 X 68 1 2 amp PnCTSA_xDREQ3_PP36 observe only X amp control PnCTSA_xDREQ3_PP36 output 1 amp PnDCDA_xDACK3_PP37 observe only X amp uh control 1 amp X 65 1 Z amp 53 4520 RISC MICROCONTROLLER ELECTRONICS 3C4520A RISC MICROCONTROLLER 61 60 59
36. LL M Acknowledge End of Trnasmission EOM End of Trnasmission Monitor transmit bit active low MR Monitor receive bit active low MD Monitor data Figure 7 2 Monitor Channel Handshake Protocol 7 4 ELECTRONICS 53 4520 RISC MICROCONTROLLER IOM2 CONTROLLER The monitor protocol is illustrated in figure7 2 Before the data IOM2MTD register is transmitted The IOM2 controller should verify that the transmission is idle that is MX MR is inactive 1 for two or more than 2 frames When idle status is detected the IOM2 controller forces the MX bit to go active 0 indicating the presence of valid monitor data in the corresponding frame As a result the receiver stores the monitor data and generates MRxBA Monitor Rx Buffer Available interrupt When the IOM2MRD is read by the CPU in response to the interrupt the receiver forces MR bit to go active 0 indicating the acknowledge of received data In response to the acknowledge the transmitter generates MTxBA Monitor Tx Buffer Available interrupt and the CPU writes data to IOM2MTD The MX bit is still in the active The transmitter indicates a new byte in monitor channel by returning the MX bit active after sending it once in the inactive state When the MRxBA interrupt is generated and the IOM2MRD is read by the CPU the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state This in turn causes
37. Pre indexed word store Calculate the target address by adding together the value in Rb and the value in Ro Store the contents of Rd at the address STRB Rd Rb Ro STRB Rad Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rb Ro LDR Rad Rb Ro Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into Rd LDRB Rb Ro LDRB Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro Load the byte value at the resulting address ELECTRONICS 3 77 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R3 R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 RO R7 Loadinto R2 the byte found at the address formed by adding R7 to RO 3 78 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALFWORD 15 14 13 12 11 10 9 8 6 5 3 2 0 mw hm 2 0 Destination Register 5 3 Base Register 8 6 Offset R
38. RO and set condition codes ELECTRONICS 3 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 5 HI REGISTER OPERATIONS BRANCH EXCHANGE 15 14 13 12 11 10 9 8 7 6 5 3 2 0 T9 T mm I rama 2 0 Destination Register 5 3 Source Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 3 34 Format 5 OPERATION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 3 12 NOTE In this group only CMP Op 01 sets the CPSR condition codes The action of H1 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used ELECTRONICS 3 73 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER Table 3 12 Summary of Format 5 Instructions EJEJES THUMB Assembler ARM Equivalent ADD Rd Hs ADD Rd Rd Hs EN M a register in the range 8 15 to a register in the range 0 7 1 ADD Hd Rs ADD Hd Hd Rs Add a register in the range 0 7 to a register in the range 8 15 olila ADD Hd Hs ADD Hd Hs Add two registers in the range 8 15 01 1 Rd Hs CMP Rad Hs Compare a register in the range 0 7 witha register in the range 8 15 Set the condition code flags on the result 01 1 CMP Hd R
39. Table 6 8 HMODE Register Description Continued Bit Bit Name Description Number 18 16 DPLL clock select Using this setting you can configure the clock source for DPLL to one of DPLLCLk the following pins TXC RXC MCLK BRGOUT1 or BRGOUT2 To select one of these pins set the DPLLCLK bits to 000 001 010 011 or 100 respectively BRG clock select If this bit is 1 MCLK2 is selected as the source clock for the baud rate BRGCLK generator If this bit is 0 the external clock at the RXC pin is selected as the BRG source clock Tx clock select TxCLK Using this setting you can configure the transmit clock source to one of the following pins TXC RXC DPLLOUTT BRGOUT1 or BRGOUT2 To select one of these pins set the TxCLK bits to 000 001 010 011 or 100 respectively 26 24 Rx clock select RxCLK Using this setting you can configure the receive clock source to one of the following pins TXC RXC DPLLOUTR BRGOUT1 or BRGOUT2 To select one of these pins set the RxCLK bits to 000 001 010 011 or 100 respectively 30 28 TXC output pin select If you do not use the clock at the TXC pin as the input clock you can use TXCOPS the TXC pin to monitor TXCLK RxCLK BRGOUT1 BRGOUT2 DPLLOUTT and DPLLOUTR To select the clock you want to monitory set the TXCOPS to 000 001 010 011 or 100 respectively eU 6 24 ELECTRONICS 53 4520 RISC M
40. You can clear this bit by writing TXDATA into UTXBUF or Transmit FIFO 19 Transmit FIFO Empty This bit is only for CPU to monitor UART TFEMT When Transmit FIFO is empty this bit is set to 1 After reset default value is 1 20 Transmit FIFO full This bit is only for CPU to monitor UART TFFUL When Transmit FIFO is full this bit is set to 1 After reset default value is 0 31 21 Not applicable up ELECTRONICS 10 11 UART 3C4520A RISC MICROCONTROLLER 2 O xm 0 Receive Data Valid RDV 0 No valid data Receive FIFO top URXBUF 1 Valid data present Receive FIFO top or URXBUF 1 Break Signal Detected BKD 0 No Break Signal Receive FIFO top or URXBUF 1 Break received 2 Frame Error FER 0 No Frame Error Receive FIFO top or URXBUF 1 Frame Error occured 3 Parity Error PER 0 No Parity Error Receive FIFO top or URXBUF 1 Parity Error occured 4 Overrun Error OER 0 No Overrun Error Receive FIFO top or URXBUF 1 Overrun Error occured 5 Control Character Detect CCD 0 No Control Character Receive FIFO top or URXBUF 1 Control character present Receive FIFO top or URXBUF 6 Data Carrier Detect Lost DCDL 0 DCD pin nUDCD is Low at the receiver checking time 1 DCD pin nUDCD is High at the receiver checking time 7 Receive FIFO Data Trigger Level Reach RFREA 0 No valid data in URXBUF or Not reached to
41. _ gt i CTS Figure 6 8 CTS Lost during Transmission When the condition of nCTS is shifted from Low to High it is detected at the falling edge of Tx clock where nRTS also goes High For about 5 to 13 cycles after nRTS enters High the data transmission continues nRTS remains High for a maximum of 22 cycles and goes back to the Low condition if there remains any data to be transmitted in HTxFIFO If nCTS is still High even when nRTS went back to Low not the data in HTxFIFO but a mark idle pattern is transmitted when AutoEn bit set to one 6 18 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS TxClock 5 12 cycles __ gt RTS CTS Figure 6 9 CTS Delayed on If nCTS remains still High for a while after nRTS enters Low to allow data transmission from HTxFIFO the data transmission starts 5 12 cycles after nCTS is shifted to Low ELECTRONICS 6 19 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC SPECIAL REGISTERS The HDLC special registers are defined as read only or write only registers according to the direction of information flow The addresses of these registers are shown in Table 6 4 6 5 and 6 6 The transmitter FIFO register can be accessed using two different addresses the frame terminate address and the frame continue address The functions of these addresses are discussed in detail in the FIFO secti
42. 0 Normal operation 1 Reset Transmit FIFO 19 Receive FIFO Reset RFRST 0 Normal operation 1 Reset Receive FIFO 21 20 Transmit FIFO Trigger Level TFTL 00 30 32 byte data 01 24 32 byte data woor 10 16 32 byte data 11 8 32 byte data empty Tx data TxFIFO depth 23 22 Receive FIFO Trigger Level RFTL 00 1 32 byte data 01 8 32 byte data 10 18 32 byte data 11 28 32 byte data valid Rx data RxFIFO depth 24 Data Terminal Ready to pin DTR 0 nDTR goes high level 1 nDTR goes low level 25 Request To Send to pin RTS 0 nRTS goes high level 1 nRTS goes low level 27 26 Reserved This bit should be cleared 28 Hardware Flow Control Enable HFEN 0 Disable Hardware Flow Control 1 Enable Hardware Flow Control 29 Software Flow Control Enable SFEN 0 Disable Software Flow Control 1 Enable Software Flow Control 31 30 Reserved This bit should be cleared Figure 10 2 UART Control Register Continued 10 8 ELECTRONICS 53 4520 RISC MICROCONTROLLER UART STATUS REGISTERS UART Table 10 4 UART Status Registers USTAT 0 04 UART status register 0 0900 Table 10 5 UART Status Register Description Bit Number Reset Value Receive Data Valid RDV Frame Error FER Parity Error PER 1 Break Signal Detected BSD ELECTRONICS This bit automatically set to one when Receive FIFO top or URXBUF contains a valid dat
43. 010 then 16 If USBMAXP 2 0 011 then 24 If USBMAXP 2 0 100 then 32 If USBMAXP 2 0 101 then 40 USBMAXP 2 0 110 then 48 USBMAXP 2 0 111 then 56 USBMAXP 3 0 1000 then 64 ELECTRONICS 11 29 USB 3C4520A RISC MICROCONTROLLER 31 4 3 0 77 3 0 USB MAX Packet Size 2 0 000 MAX packet size is 0 byte 2 0 001 MAX packet size is 8 bytes 2 0 010 MAX packet size is 16 bytes 2 0 011 MAX packet size is 24 bytes 2 0 100 MAX packet size is 32 bytes 2 0 101 MAX packet size is 40 bytes 2 0 110 MAX packet size is 48 bytes 2 0 111 MAX packet size is 56 bytes 3 0 1000 MAX packet size is 64 bytes 31 4 Reserved Figure 11 15 USBMAXP Register 11 30 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB IN CSR REGISTER 1 ENDPOINT 0 This register has the control and status bits for endpoint 0 Since a control transaction involves both IN and OUT tokens there is only one CSR register mapped to the IN CSR1 register To access endpoint 0 CSR user must write 0 at index register USBINDEX Table 11 22 USB In CSR register 1 USBICSR1 0x44 USB In CSR register 1 0x00 EPO ELECTRONICS 11 31 USB 53 4520 RISC MICROCONTROLLER Table 11 23 USBICSR1 for Description USBORDY USB IN packet Set R ReaDY USBINRDY USB SenT Clear R STALL USBSTSTALL USB
44. DMA Rx Select DRxSEL 0 Interrupt mode 1 DMA Rx Service 4 Tx enable 0 Tx disabled 1 Tx enabled 5 Rx enable 0 Rx disabled 1 Rx enabled 6 DPLL enable DPLLEN 0 Disable 1 Enable 7 BRG enable BRGEN 0 Disable 1 Enable 8 Tx 4 word burst mode TxAWD 0 1 word mode selected 1 4 word mode selected 9 Rx 4 word burst mode Rx4WD 0 1 word mode selected 1 4 word mode selected 11 10 Tx widget algnment TxWA 00 No invalid byte 01 1 invalid byte 10 2 invalid byte 11 invalid byte 13 12 Rx widget algnment RxWA 00 No invalid byte 01 1 invalid byte 10 2 invalid byte 11 invalid byte 14 Tx flag idle TxFLAG 0 Enter mark idle mode a bit pattern of consecutive ones 1 Enter time fill mode a bit pattern of consecutive opening closing flag as in string 01111110 01111110 15 Tx single flag TxSFLG 0 Double flag mode 1 Single flag mode 16 Tx loop back mode TxLOOP 0 Normal operation 1 internal loopback mode Figure 6 11 HDLC Control Register HCON 6 30 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 OmOOZxZu J rmx Do r mo x UO Oromxz o 3 17 Tx abort extension TXABTEXT 0 At least consecutive eigth 1s are transferred 1 At least 16 consecutive 1s are transferred
45. Isr 16 MOV a1 a1 Isr 3 ADD a3 a1 a1 asl 2 SUBS a2 a2 asl 1 ADDPL at a1 1 ADDMI a2 a2 10 MOV Ir 3 100 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER SYSTEM MANAGER OVERVIEW The S3C4520A System Manager has the following functions To arbitrate system bus access requests from several master blocks based on fixed priorities or round robin method by SYSCFG 3 register value To provide the required memory control signals for external memory accesses For example if a master block such as the DMA controller or the CPU generates an address that corresponds to a DRAM bank the System Manager s DRAM controller generates the required normal EDO or SDRAM access signals The interface signals for normal EDO or SDRAM can be switched by SYSCFG 31 To provide the required signals for bus traffic between the S3C4520A and ROM SRAM and the external I O banks To compensate for differences in bus width for data flowing between the external memory bus and the internal data bus S3C4520A supports both little and big endian for external memory or I O devices NOTE By generating an external bus request an external device can access the S38C4520A s external memory interface pins In addition the 53045204 can access slow external devices by using a Wait signal The Wait signal which is generated by the external device extends the duration of the CPU s memory access cycle beyond its programmable value
46. R15 LDMFD SP R15 STMFD R13 RO R14 53 4520 RISC MICROCONTROLLER Unstack 3 registers Save all registers R15 SP CPSR unchanged R15 SP CPSR lt SPSR mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SPI RO R3 R14 2 somewhere i LDMED SP RO R3 R15 3 46 Save RO to R3 to use as workspace and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS 3 4520 RISC MICROCONTROLLER INSTRUCTION SET SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 D w ww o D 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory m
47. Register TSAACFG 0xA30 TSA A Configuration Register 0x00000000 TSABCFG 0 4 TSA Configuration Register 0x00000000 TSACCFG 0xA38 TSA C Configuration Register 0x00000000 TSAACFG TSA A Configuration Register TSAACFG 0xA30 TSA A Configuration Register 0x00000000 11 0 START The location of start bit of time slot assigned to HDLCA 23 12 STOP The location of stop bit of time slot assigned to HDLCA 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 2 11 highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock Gem 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 d pee stop sr 11 0 The location START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 PCM Highway multiplexed 26 Divide 0 1 x Clock mode 1 0 5 x Clock mode Figure 8 2 TSA A Configuration Register 8 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER TSA TIME SLOT ASSIGNER TSABCFG TSA B Configuration Register TSABCFG 4 TSA Configuration Register 0x00000000 11 0 START The location of start bit of time slot assigned to HDLCB 23 12 STOP The location of stop bit of time slot assigned to HDLCB 25 24 MODE 00 DCE 01 PCM highway non multipl
48. Table 3 23 The Conditional Branch Instructions Continued Code THUMB ARM Equivalent Assembler 1011 BLT label BLT label Branch if N set and V clear or N clear and V set less than 1100 BGT label BGT label Branch if Z clear and either N set and V set or N clear and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be halfword aligned i e with bit O set to 0 since the assembler actually places label gt gt 1 in field SOffset8 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 23 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples 45 Branch if RO gt 45 BGT over Note that the THUMB opcode will contain the number of halfwords to offset over D Must be halfword aligned 3 92 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 17 SOFTWARE INTERRUPT 15 14 13 11 1 7 1 12 0 9 8 y 7 0 Comment Field Figure 3 46 Format 17 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM s
49. USB POWER MANAGEMENT REGISTER This register is used for suspend resume and reset signaling The different bits in this register are explained below Table 11 4 USB Power Management register USBPM USB Power Management register Table 11 5 USBPM Description USB Suspend 1 Enable Suspend mode Enable USBSE cu use R W 0 Disable Suspend mode Default If this bit is a zero the device will not enter suspend USB Suspend R Clear R W bit is set by the USB when it enters suspend mode Mode USBSM It is cleared under the following conditions USB ResUme W R M The MCU sets this bit for a duration of 10ms maximum The MCU clears the USB RESUme bit to end resume signaling The MCU reads USB Interrupt Register for the USB Resume Interrupt mode USBRU of 15ms to initiate a resume signaling The USB generates resume signaling while this bit is set in suspend mode The USB set this bit if reset signaling is received from the host This bit remains set as long as reset signaling persists on the bus Used for ISO Mode only If set waits for a SOF token from the time USBINRDY was set to send the packet USBRST 6 4 USB Iso Update USBIU USB RESET M If an IN token is received before a SOF token then zero length data packet will be sent up ELECTRONICS 11 13 USB 11 14 53 4520 RISC MICROCONTROLLER 8 7 6 5 4 3 2 1 0 0 USB Suspend Enable USBS
50. amp PBOSIZE 12 amp PUSB_CK 13 amp CKS 14 amp PRXCA DCL 15 amp 16 amp PXDATA1 17 amp PXDATA2 18 amp ELECTRONICS out out out out out out out out out out bit bit bit bit bit bit bit bit bit bit APPENDIX A A 7 APPENDIX 8 PXDATA3 19 amp PXDATA4 20 amp PXDATA5 21 amp PXDATA6 22 amp PXDATAT 23 amp PXDATA8 24 amp PXDATA9 25 amp PXDATA10 26 amp PXDATA11 27 amp PXDATA12 28 amp PXDATA13 29 amp 30 amp PXDATA15 31 amp DP 32 amp PUSB DM 33 amp PnCTSA xDREQS 6 34 amp xDACKS PP37 35 amp PTXDA DU 36 amp PRXDA DD 37 amp PTXCA FSC 38 amp PnCTSB xDREQA PP0 39 amp PnDCDB xDACKA PP1 40 amp PTXDB PP2 41 amp PRXDB PP3 42 amp PnDTRB 4 43 amp PnRTSB 5 44 amp PTXCB_PP6 45 8 PRXCB PP7 46 amp PnCTSC_xDREQ5_PP8 47 amp PnDCDC_xDACK5_PP9 48 amp PTXDC_PP10 49 amp PRXDC_PP11 50 amp PnDTRC PP12 51 amp PnRTSC PP13 52 amp PP14 53 amp PRXCC PP15 54 amp PUCLK PP16 55 amp PUTXD PP17 56 amp PURXD PP18 57 amp PnUDSR PP19 58 amp PnUDTR PP20 59 amp 53 4520 RISC MICROCONTROLLER ELECTRONICS 3C4520A RISC MICROCONTROLLER APPENDIX A P
51. and then by 2 Multiply by 10 and add in extra number ADD ADD Ra Ra Ra LSL 2 Multiply by 5 Ra Rc Ra LSL 1 Multiply by 2 and add in next digit General recursive method for Rb Ra C C a constant 1 If C even say 2 n D D odd D 1 MOV Rb Ra LSL n Rb Ra D Rb Rb LSL n 2 If C MOD 4 1 say 24n D 1 D odd gt 1 D 1 ADD ADD Rb Ra Ra LSL n Rb Ra D Rb Ra Rb LSL n 3 If C MOD 4 3 say 2 n D 1 D odd gt 1 D 1 RSB RSB Rb Ra Ra LSL n Rb Ra D Rb Ra Rb LSL n This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB RSB ADD rather than by ADD ADD 3 62 Rb Ra Ra LSL 2 Multiply by Rb Ra Rb LSL 2 Multiply by 4 3 1 11 Rb Ra Rb LSL 2 Multiply by 4 11 1 45 Rb Ra Ra LSL 3 Multiply by 9 Rb Rb Rb LSL 2 Multiply by 5 9 45 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Rc Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Rc LSL Rb Enter with address in Ra 32 bits uses Rb result in Rd Note must be less than e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes how in bits and test if aligned Produce bottom of result word if no
52. except for the HTxFIFO and the status bits associated with transmit operation are cleared Data cannot be loaded into the HTxFIFO If this bit is set to 1 the idle pattern is sent continuously In this case the data can be loaded into HTxFIFO and then sent 5 Rx enable RxEN When the RxEN bit is 0 the receiver enters a disabled state and can not detect the flag pattern if any In this case receiver block is cleared except for the HRXFIFO and the status bits associated with receiver operation are cleared Data cannot be received If this bit is set to 1 the flag pattern is detected In this case the data 6 received be loaded into the HRXFIFO and moved to system memory DPLL enable Setting this bit enables the causing the DPLL to enter search mode In Search mode the DPLL searches for a locking edge in the incoming data stream After DPLL is enabled in NRZI mode for example the DPLL starts sampling immediately after the first edge is detected In FM mode the DPLL examines the clock edge of every other bit to decide what correction must be made to remain in sync If the DPLL does not detect an edge during the expected window it sets the one clock missing bit If the DPLL does not detect an edge after two successive attempts it sets the two clock missing bit and the DPLL automatically enters the Search mode To reset both clocks missing latches you can disable and re enable the DPLL u
53. following any sequence of five 1s within a frame the receiver deletes a binary 0 that follows a sequence of five 1s within a frame ABORT The function of early termination of a data link is called an abort The transmitter aborts a frame by sending at least eight consecutive 1s immediately after the abort transmitter control bit TXABT in HCON is set to 1 Setting this control bit automatically clears the HTxFIFO The abort sequence can be extended up to at least 16 consecutive 1s by setting the abort extend control bit TxABTEXT in HCON to 1 This feature is useful for forcing the mark idle state The receiver interprets the reception of seven or more consecutive 1s as an abort The receiver responds the abort received as follows abort in an out of frame condition an abort has no meaning during the idle or the time fill Anabort in frame after less than 25 bits are received after an opening flag under this condition no field of the aborted frame is transferred to the HRXFIFO The HDLC module clears the aborted frame data in the receiver and flag synchronization The aborted reception is indicated in the status register Anabort in frame after 25 bits or more are received after an opening flag in this condition some fields of the aborted frame may be transferred to the HRXFIFO The abort status is set in the status register and the data of the aborted frame in the HRXFIFO is cleared Flag synchronizat
54. nRAS 1 0 DRAM banks One nRAS output is provided for each bank nSDCS 1 0 nSDCS 1 0 are chip select pins for SDRAM 1 Not column address strobe for DRAM The two nCAS outputs nCAS O indicate the byte selections whenever a DRAM bank is accessed nSDRAS nSDRAS is row address strobe signal for SDRAM Latches row addresses on the positive going edge of the SDCLK with nSDRAS nCAS 1 low Enable row access and precharge nSDCAS nSDCAS is column address strobe for SDRAM Latches column addresses on the positive going edge of the SDCLK with nSDCAS low Enables column access ELECTRONICS 1 7 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 1 S3C4520A Signal Descriptions Continued Signal Pinno is clock enable signal for SDRAM Masks SDRAM system clock SDCLK to freeze operation from the next clock cycle SDCLK should be enabled at least one cycle prior to new command Disable input buffers of SDRAM for power down in standby Not DRAM Write Enable This pin is provided for DRAM bank write operations nWBE 1 0 is used for write operations to the ROM SRAM flash memory banks Not External I O Chip Select Four external I O banks are provided for external memory mapped I O operations Each I O bank stores up to 256 Kbytes nECS signals indicate which of the four external I O banks is selected Not External Wait This signal is activated when an external I O nECS 3 0 60 63 uH nEWAIT
55. vawes Software interrupt 1 1 1 olol os Unconditional branch KA KA KA KA C Long branch with ink 15 14 13 12 1110 9 8 7 6 Figure 3 29 THUMB Instruction Set Formats 3 64 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET OPCODE SUMMARY The following table summarises the THUMB instruction set For further information about a particular instruction please refer to the sections listed in the right most column Table 3 7 THUMB Instruction Set Opcodes pep wer Codes Set me AND AND V B QUnond olbranh y Conditionalbranch Branch and exchange lt lt lt lt MN 5 MVN NEG lt BS PUSH POR jRetterght o Move negative register ELECTRONICS 3 65 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER Table 3 7 THUMB Instruction Set Opcodes Continued een em Emm Operand Operand Codes Set SBC Subtractwithcany SA soenpe v sm j swwd v STRB STRH Store halfword Software interrupt SW Software interrupt Subtract __ NNUS CMM NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instru
56. where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be halfword aligned ie bit 0 set to 0 since the assembler places label gt gt 1 in the Offset11 field Examples here B here Branch onto itself Assembles to OXE7FE Note effect of PC offset B jimmy Branch to jimmy m Note that the THUMB opcode will contain the number of halfwords to offset Jimmy us Must halfword aligned 3 94 ELECTRONICS 3 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 19 LONG BRANCH WITH LINK 15 10 14 13 12 11 ptt 10 0 Long Branch and Link Offset High Low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 3 48 Format 19 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit 0 which must be 0 and creates two THUMB instructions Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address i
57. 2 S3C4520A Pin List and PAD Type Continued Pin Type Pad Type Description Counts GPIOs PP10 TXDC 1 B O ptbst4sm General I O Port HDLC B 8 HDLC Ch C Transmit Data PP11 RXDC 1 B I ptbst4sm General I O Port HDLC Ch C Receive Data PP12 nDTRC 1 B O ptbst4sm General I O Port HDLC Ch C Data Terminal Ready PP13 nRTSC 1 B O ptbst4sm General I O Port HDLC Ch C Request To Send PP14 TXCC 1 B B ptbsut1 General Port HDLC Ch C Transmitter Clock PP15 RXCC 1 B I ptbsut1 General Port HDLC Ch C Receiver Clock PP8 xDREQ5 1 ptbst4sm General I O Port nCTSC External DMA Request 5 HDLC Ch C Clear To Send PP9 xDACKC 1 ptbst4sm General I O Port nDCDB External DMA Acknowledge 5 HDLC Ch C Data Carrier Detected ELECTRONICS 1 15 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 2 S3C4520A Pin List and PAD Type Concluded Pin Type Pad Type Description Counts UCLK PP16 1 ptbst4sm External UART clock input General I O Port UTXD PP17 1 O B ptbst4sm UART Transmit Data General I O Port URXD PP18 1 ptbst4sm UART Receive Data General I O Port nUDSR PP19 1 ptbst4sm Not UART Data Set Ready General I O Port nUDTR PP20 1 O B ptbst4sm Not UART Data Terminal Ready General I O Port nURTS PP21 1 O B ptbst4sm Not UART Request To Send General I O Port nUCTS PP22 1 VB ptbst4sm Not UART Clear To Send General I O Port nUDCD PP23 1 VB ptbst4sm Not UART Data Ca
58. 24 XIRQO 4 Port 24 for xIRQO 0 Disable 1 Enable 3 0 Active Low 1 Active High 2 0 Filtering off 1 Filtering on 0 1 00 Level detection 01 Rising edge detection 10 Falling edge detection 11 Both edge detection 9 5 Control external interrupt request 1 input for port 25 xIRQ1 See control external interrupt request 0 14 10 Control external interrupt request 2 input for port 26 xIRQ2 See control external interrupt request 0 19 15 Control external interrupt request 3 input for port 27 xIRQ3 See control external interrupt request 0 Figure 13 5 Port Control Register 1 IOPCON1 13 6 ELECTRONICS 53 4520 RISC MICROCONTROLLER Table 13 5 IOPCON2 Register IOPCON2 0x510 port control register ELECTRONICS PORTS Reset Value 0x00000000 13 7 PORTS 3C4520A RISC MICROCONTROLLER 31 3029 2827 2625 2423 2221 2019 18 17 15 14 13 8 2 0 Control external DMA request 0 input for port 30 DRQO 2 Port 30 for 0 Disable 1 Enable 1 0 Filtering off 1 Filtering on 0 0 Active Low 1 Active High 5 3 Control external DMA request 1 input for port 32 DRQ1 See control external DMA request 0 8 6 Control external DMA request 2 input for port 34 DRQ2 See control external DMA request 0 11 9 Control external DMA request 3 input for port 36 DRQ3 11 Port 36 for or for nCTSA 0 Disable nCTSA 1 Enable 10 0 Fi
59. 24 to 31 are significant to ARM7TDMI The remaining bits are used by coprocessors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP field is used to contain an identifying number in the range 0 to 15 for each coprocessor and a coprocessor will ignore any instruction which does not contain its number in the CP field The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field and possibly in the CP field on the contents of CRn and CRm and place the result in CRd ELECTRONICS 3 51 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop S and are defined as sequential S cycle and internal I cycle ASSEMBLER SYNTAX CDP cond p lt expression1 gt cd cn cm lt expression2 gt cond p lt expression1 gt cd cn and cm lt expression2 gt Examples CDP CDPEQ 3 52 Two character condition mnemonic See Table 3 2 The unique number of the required coprocessor Evaluated to a constant and placed in the CP Opc field Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively Where present is evaluated to a constant and placed in the CP field p1 10 c1 c2 c3 Reque
60. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 Delo 0 Cl 0 Buffer Available 0 normal 1 CIO buffer available 1 Reserved 2 1 Buffer Available CI1BA 0 normal 1 buffer available 3 Reserved 4 Monitor Received End of Frame MRxEOM 0 normal 1 monitor channel transmission terminated successfully 5 Monitor Received Abort MRxABT 0 normal 1 monitor channel transmission aborted 6 Monitor Collision MCOL 0 normal 1 monitor channel collision detected 7 Monitor Transmit Buffer Available MTxBA 0 normal 1 monitor tx buffer empty 8 Monitor Receive Buffer Available MRxBA 0 normal 1 monitor rx buffer data ready 9 Monitor Transmit Abort Detected MTxABT 0 normal 1 10 IC Buffer Available ICBA 0 normal 1 IC buffer available 11 ALIVE ALIVE 0 2 bus is in the inactive state DCL 1 1 2 bus is in the active state DCLK is clocking 12 NEWFSC NEWFSC 0 normal 1 fsc rising edge detected Figure 7 7 2 Status Register ELECTRONICS 7 13 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER Table 7 4 IOM2INTEN Register Interrupt Enable Register Register Description Resevaue IOM2INTEN 0xA08 Interrupt Enable Register 0x00000000 CIOBAIE Channel Buffer Available Interrupt Enable pe 2 CHBAIE 1 Channel Buffer Available Interrupt Enable 3 MRxABTIE Monitor Channel
61. 5 R1 PLACE Store R1 at R2 R4 both of which are registers and write back address to R2 Store R1 at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load R1 from contents of R2 4 Conditionally load byte at R6 5 into R1 bits 0 to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 33 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 65 4 3 Lus Des Dom 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfwords 1 1 Signed byte 1 1 Signed half words 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to
62. 9 5 External DMA Requests Single Mode ELECTRONICS 9 11 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER Block Mode The assertion of only request or an internal request causes all of the data as specified by the control register settings to be transmitted in a single operation The GDMA transfer is completed when the transfer counter value reaches zero The nXDREQ signal can be de asserted after checking that nXDACK has been asserted nxDREQ nxDACK Figure 9 6 External DMA Requests Block Mode Demand Mode In demand mode the continues transferring data as long as the request input is held active nxDREQ 14722 nxDACK Figure 9 7 External DMA Requests Demand Mode 9 12 ELECTRONICS 53 4520 RISC MICROCONTROLLER DMA CONTROLLER DMA TRANSFER TIMING DATA Figure 9 8 provides detailed timing data for data transfers that are triggered by external DMA requests Please note that read write timing depends on which memory banks are selected To access ROM banks which are in multiplexing bus mode by 4 data burst mode refer to Figure 4 19 and Figure 4 20 of Chapter 4 for read write timing of ROM bank 1 M AR NN ERN MCLK 1 tXDRs tXDRh i gt nxDACK Min 3 cycles tXDAf delay 2 79 nsec 9 7
63. Assembler Syntax Qe ee aa aa aaa aaa aaa ai eee Single Data Swap Bytes Word Sg NCC CCCII A n t A E A AE E EE E ADON Skaitiniai Instruction Cycle 5 Assembler Syntax ee ee Software Interrupt SWI Return From The nnn Comment cM I c Instruction Cycle Times 9 Assembler Syntax Coprocessor Data Operations Coprocessor Annn EEES Ennan ennn Enna The Coprocessor 5 Instruction Cycle Assembler Syntax Coprocessor Data Transfers 5 The Coprocessor 5 Addressing Modes pp Address Alignment pp BEO A RO xc ADOM Instruction Cycle 5 Assembler Syntax pp 53 4520 RISC MICROCONTROLLER Table of Contents Continued Chapter 3 Instruction Set Continued Coprocessor Register Transfers MRC 3 56 The Coprocessor FieldS 3 56
64. But when this bit is set to 1 the transmitter can send data only if the nCTS is 0 and the receiver can receive data only if the nDCD is 0 In transparent mode this bit selects the receiver synchronization method inline sync and external sync When this bit is 0 the receiver gets synchronization by inline sync method When this bit is 1 the receiver gets synchronization by external sync method The nCTS pin affects the transmitter the same way as HDLC mode 29 28 Transparent Sample This bit is valid for only transparent mode and external synchronization SMPL mode This bit determines which bit of received data stream is the first bit of valid byte in transparent and external synchronization mode 00 the first valid bit is a bit 2 cycle before nDCD transition 01 the first valid bit is a bit 1 cycle before nDCD transition 02 the first valid bit is a bit 0 cycle before nDCD transition same cycle 03 the first valid bit is a bit 1 cycle after nDCD transition 31 29 Not applicable ELECTRONICS 6 29 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 VOHMX 2 ODNN0OZxK 2 4xmoawupx 4 Q rmxa 4 zmr ruo 0 Tx reset TxRS 0 Normal 1 TxFlFOmand Tx block are reset 1 Rx reset RxRS 0 Normal operation 1 RxFIFO and Rx block are reset 2 DMA Tx Select DTxSEL 0 Interrupt mode 1 Tx Sevice
65. DMA get ready to transmit data If request signal is transmitted by UART Txdata of UART in memory is written into Tx buffer FIFO or Rxdata of Rx buffer FIFO is written into memory When DMA transmits data of UART data is written into UART Rx buffer FIFO or data of UART Tx buffer FIFO is written into the memory as unit of byte It is nothing to do with the value of control register 13 12 If it is requested by UART only 1 byte is transmitted and waits the following request At this time if GDMA count register is zero the operation is ended HDLC Mode GDMA Channel 0 Transmit data of HDLC Channel A GDMA Channel 1 Transmit data of HDLC Channel B GDMA Channel 2 Transmit data of HDLC Channel C GDMA Channel 3 Transmit data of HDLC Channel A and so on If it receives request from HDLC DMA read 1 word margin with UART from Memory and writes into the HDLC Tx FIFO or read from Rx FIFO and writes into memory Like UART DMA transfer HDLC data whenever receives request signal of HDLC UART transmits data as a unit of 1 byte on the hand HDLC transmits data as a unit of 1 word In the HDLC Rx Mode data transmit of DMA controller is terminated when DMA controller transmits the received HDLC last data or DMA Count register is consumed And DMA controller generates Interrupt To request DMA operation set the 0 bit of control register and DMA control registers 9 10 ELECTRONICS 53 4520 RISC MICROCONTROLLER DMA CONTROLLER GDMA FUNCTION DESCRIPTIO
66. Enable IOM2EN 0 Disable 1 Enable 1 Data Bus Reverse DBREV 0 DU upstream DD downstream 1 DU downstream DD upstream 2 Monitor Enable MEN 0 Disable 1 Enable 3 TIC Bus Enable TICEN 0 Disable 1 Enable 4 D channel Collision Enable DCOLEN 0 Disable 1 Enable 5 Monitor Abort Request MAR 0 normal 1 abort request asserted 6 Monitor Address Valid MAV 0 address received is not valid 1 address received is valid 7 Monitor Transmit End Of Frame MTxEOM 0 normal 1 monitor sends end of frame 8 Bus Request BREQ 0 normal 1 request TIC bus to send data 9 Monitor Channel Select MSEL 0 Monitor 0 selected 1 Monitor 1 selected 10 IC channel Select ICSEL 0 IC 0 selected 1 1 selected 11 AWAKE AWAKE 0 normal 1 request the transceiver to deliver DCLK 12 LoopBack LOOP 0 normal 1 loopback mode 13 TSA Enable TSAEN 0 Disable 1 Enable Figure 7 6 IOM2 Control Register ELECTRONICS 7 11 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER Table 7 3 IOM2STAT Register Status Register Register omst AW Description ResetVawe 0 Channel Buffer Available CIOBA 0 C IO receive data is valid 1 IOM2CIORD is valid to read 1 Channel Buffer Available CI1BA 0 C I1 receive data is not valid 1 IOM2CI1RD is valid to read 4 Monitor Channel Receive End of 0 The EOM has not a
67. Figure 12 3 Timer Mode Register TMOD ELECTRONICS 12 3 32 BIT TIMERS 3C4520A RISC MICROCONTROLLER TIMER DATA REGISTERS The timer data registers TDATAO and TDATAt contain a value that specifies the time out duration for each timer The formula for calculating the time out duration is Timer data 1 cycles Table 12 2 0 TDATA1 Registers TDATAO 0x604 Timer 0 data register 0x00000000 1 0x608 Timer 1 data register 0x00000000 31 0 31 0 Timer 0 1 data value Figure 12 4 Timer Data Registers TDATAO TDATA1 TIMER COUNT REGISTERS The timer count registers TCNTO and contain the current timer 0 1 count value respectively during normal operation Table 12 3 TCNTO and TCNT1 Registers 31 0 31 0 Timer 0 1 count value Figure 12 5 Timer Counter Registers TCNTO TCNT1 12 4 ELECTRONICS 53 4520 RISC MICROCONTROLLER PORTS PORTS OVERVIEW The S3C4520A has 38 programmable I O ports You can configure each I O port to input mode output mode or special function mode To do this you write the appropriate settings to the IOPMODO 1 and IOPCONO 1 2 registers User can set filtering for the input ports using 1 2 registers If you want to use the port as input or output port mode you must set the IOPCONO 1 2 as input or output mode Also you can use the port as special function If you set the IOPCONO 1 2 as special function mode you can
68. Figures Continued Figure Title Page Number Number 8 1 M 8 2 8 2 TSA A Configuration Register 8 4 8 3 TSA B Configuration Register esses 8 5 8 4 TSA C Configuration Register 8 6 9 1 Controller Block Diagram 9 2 9 2 Control 9 7 9 3 Source Destination Address Register pp 9 8 9 4 DMA Transfer Count 9 9 9 5 External DMA Requests Single 9 11 9 6 External DMA Requests Block Moge 9 12 9 7 External DMA Requests Demand 9 12 9 8 External DMA Requests Detailed 9 13 9 9 MCLKO and 9 14 9 10 Single and One Data Burst Mode 9 15 9 11 Single and Four Data Burst Mode Timing 9 16 9 12 Block and One Data Burst Mode 9 17 9 13 Continuous and One Burst Mode Timing Nt 9 18 9 14 Demand and One Data Burst Mode Timing 9 19 10 1 Serial Block 10 2 10 2 UART Control 10 7 10 3 WART Status Registre 10 12 10 4 UART Interrupt Enable Register 10 15 10 5 UART Transmit Buffer Register
69. GDMAOCNTO 1 2 3 4 5 Registers 9 9 10 1 UART Special Registers 10 3 10 2 UART Control 10 4 10 3 UART Control Register Description 10 4 10 4 UART Status 10 9 10 5 UART Status Register 10 9 10 6 Interrupt Enable 0 00000 10 14 10 7 UART Interrupt Enable Register 10 14 10 8 UXT BUF ior meter entre 10 16 10 9 UART Transmit Register 10 16 10 10 UXRBUF 10 17 10 11 UART Receive Register 10 17 10 12 UBRDIVO and UBRDIVO 10 18 10 13 Typical Baud Rates Examples of UART eesssssesssesessssrnrrssssrrrirrrnrssssrrrrrnssssssrrnns 10 19 10 14 CONCHAR 1 Registers nrnna aaa ear a oaaae ran a arin N a 10 20 10 15 2 Registers 10 21 3C4520A RISC MICROCONTROLLER Table Number 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18 11 19 11 20 11 21 11 22 11 23 11 24 11 25 11 26 11 27 11 28 11 29 11 30 11 31 11 32 12 1 12 2 12 3 List of T
70. No operation 1 Stall handshake transmitted 6 USB Clear Toggle 0 No operation 1 Data toggle flag set to 0 31 7 Reserved Figure 11 17 USBICSR1 Register 11 36 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB IN CSR REGISTER 2 This register is used to configure IN endpoints Table 11 26 USB In CSR register 2 Table 11 27 USBICSR2 Description up USB IN MoDe This bit is used only for endpoints whose transfer type is USBINMD programmable i e TYPE IN OUT If this bit is 1 then Endpoint Direction will be IN If this bit is 0 then Endpoint Direction will be OUT Default 1 USB AuTo SET If set whenever the MCU writes MAXP data USBINRDY USBATSET will be automatically be set by the core without any intervention from MCU If the MCU writes less than MAXP data then USBINRDY bit has to be set by the MCU Default 0 6 USB ISO mode This bit is used only for endpoints whose transfer type is USBISO programmable i e TYPE ISO BULK If this bit is 1 then Endpoint will be ISO mode If this bit is 0 then Endpoint will be BULK mode Default 0 ELECTRONICS 11 37 USB 11 38 53 4520 RISC MICROCONTROLLER Amo uoc 4 0 Reserved 0 Not ready for IN mode 1 Ready for In operation 5 USB IN Mode 0 Indexed endpoint set to OUT 1 Indexed endpoint set to IN 6 USB ISO Mode 0 Bulk Interrupt mode 1 ISO mode 7 USB Auto SET 0 No operation 1 Auto setting US
71. O EX x xi tf of of X at oto of of 2 59 O rq oj o oj oj o N 29 1118 hs Table 11 18 USB DISCONNECT register USBDIS1 0x24 USB DISCONNECTI1 register USBDIS2 0x28 USB DISCONNECT register USBDIS3 0 2 USB DISCONNECTS register Table 11 19 USB DISCONNECT Description 7 0 USB Disconnect Higher disconnect duration time register 8bits can be writable USBDIS1 USBDIS1 7 is enable bit 7 0 USB Disconnect Middle disconnect duration time register 8bits can be writable USBDIS2 7 0 USB Disconnect Lower disconnect duration time register 8bits can be writable USBDIS3 ELECTRONICS 11 27 USB 3C4520A RISC MICROCONTROLLER 8 7 6 DISCONNECT1 6 0 22 16 bit of WDT CNT 22 0 7 Enable bit 31 8 Reserved 8 7 0 7 0 15 8 bit of WDT CNT 22 0 31 8 Reserved 8 7 0 7 0 7 0 bit of CNT 22 0 31 8 Reserved Figure 11 14 USBDISCONNECT Register 11 28 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB MAXP REGISTER This register has the maximum packet size for IN OUT endpoints The packet size is varied in multiple of 8 bytes IF the MCU writes a value greater than the FIFO size the MAXP register will remain the FIFO size Table 11 20 USB register Table 11 21 USBMAXP Description 2 0 USB W R If USBMAXP 2 0 000 then 0 register If USBMAXP 2 0 001 then 8 USBMAXP If USBMAXP 2 0
72. Receive Abort Interrupt Enable MCOLIE Monitor Channel Collision Detected Interrupt Enable MTxBAIE Monitor Channel Tx Buffer Available Interrupt Enable MRxEOMIE Monitor Channel Receive End of Message Interrupt Enable pe _ EMEN 5 6 7 8 7 14 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 m U x 4Zz o 0 02 0 Cl 0 Buffer Available Interrupt Enable CIOBAIE 0 Disable 1 Enable 1 Reserved 2 1 Buffer Available Interrupt Enable Cl1 BAIE 0 Disable 1 Enable 3 Reserved 4 Monitor Received End of Frame Interrupt Enable MRxEOMIE 0 Disable 1 Enable 5 Monitor Received Abort Interrupt Enable MRxABTIE 0 Disable 1 Enable 6 Monitor Collision Interrupt Enable MCOLIE 0 Disable 1 Enable 7 Monitor Transmit Buffer Available Interrupt Enable MTxBAIE 0 Disable 1 Enable 8 Monitor Receive Buffer Available Interrupt Enable MRxBAIE 0 Disable 1 Enable 9 Monitor Transmit Abort Detected Interrupt Enable MTxABTIE 0 Disable 1 Enable 10 IC Buffer Available Interrupt Enable ICBAIE 0 Disable 1 Enable 11 ALIVE Interrupt Enable ALIVEIE 0 Disable 1 Enable 12 NEWFSC Interrupt Enable NEWFSCIE 0 Disable 1 Enable Figure 7 8 IOM2 Interrupt Enable Register ELECTRONICS 7 15 IOM2 CONTROLLER 3C4520A RISC MICRO
73. Samsung s state of the art ASIC test environment Important peripheral functions include six channel general purpose DMAs IOM 2 Interface by three channel HDLCs with transparent mode one UART with autobaud detection a USB peripheral controller two 32 bit timers one 16 bit watchdog timer and 38 programmable ports On chip logic includes an interrupt controller DRAM controller and a controller for ROM SRAM and flash memory The System Manager includes an internal 32 bit system bus arbiter and an external memory controller The following integrated on chip functions are described in detail in this user s manual e Architecture e System Manager e Unified Instruction Data Cache e HDLC with Transparent Mode e 2 Interface e TSA Time Slot Assigner e General Purpose DMA UART e USB Interface e 32 bit Timer e Programmable Ports e Interrupt controller e Electrical Data ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES Architecture e 16 32 bit RISC ARM7TDMI embedded e Little Big Endian mode supported Basically the internal architecture is big endian So the little endian mode only support for external memory e Cost effective JTAG based debug solution e Boundary scan System Manager e 8 16 bit external bus support for ROM SRAM flash memory DRAM and external MO Support for 2 bank SRAM ROM Flash e Support for 2 bank EDO Normal or SDRAM e Support for 4 bank external I Os e Programmable acces
74. Table 3 3 3 10 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected the C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the Z flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions Assembler Mnemonic Adon AND EOR SUB RSB ADD SBC TST az CMP CMN 208 100 Operandi O Operand2 1 is ignored BIC Operand1 AND NOT operand2 Bit clear MVN NOT operand2 is ignored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of a possible error if the operands were 2 s complement signed The C flag will be set to the carry out of bit 31 of th
75. That is it passes the eight bits to the CPU or memory during reception The CPU is responsible for how the control field is handled and what happens to it Information Field The information 1 field follows the control C field and precedes the frame check sequence FCS field The information field contains the data to be transferred Not every frame however must actually contain information data The word length of the I field is eight bits in the 53 4520 HDLC module And Its total length can be extended by 8 bits until terminated by the FCS field and the closing flag Frame Check Sequence FCS Field The 16 bits that precede the closing flag comprise the frame check sequence FCS field The FCS field contains the cyclic redundancy check character CRCC The polynomial x16 x12 x5 1 is used both for the transmitter and the receiver Both the transmitter and the receiver polynomial registers are all initialized to 1 prior to calculating of the FCS The transmitter calculates the frame check sequence of all address bits control bits and information fields It then transmits the complement of the resulting remainder as the FCS value The receiver performs a similar calculation for all address control and information bits as well as for all the FCS fields received It then compares the result to FOB8H When a match occurs the frame valid RxFV status bit is set to 1 When the result does not match the receiver sets the CRC
76. USB Out CSR register 2 USBOWCL USB Out fifo Write Counter register Lower byte USBOWCH USB Out fifo Write Counter register Higher byte USB FIFO Registers USB FIFO USB EP1 FIFO 3 USBMAXPregister jUSBInCSRregsteri jUSBInCSRregster2 Reseved jUSBOWCSRregsteri USB Out CSR register2 USB Out fifo Write Counter register Lower byte USB Out fifo Write Counter register Higher byte USB EP3 FIFO USB EP4 FIFO ELECTRONICS 11 11 USB 3C4520A RISC MICROCONTROLLER USB FUNCTION ADDRESS REGISTER This register maintains the USB Device Address assigned by the host The MCU writes the value received through a SET_ADDRESS descriptor to this register This address is used for the next token Table 11 2 USB Function Address register USBFA USB Function Address register Table 11 3 USBFA Description USB Fuction R W The MCU write the address to these bits Address Field USBFAF USB Address Set R Clear The MCU sets this bit whenever it updates the USB UPdate Function Address Field USBFAF in this register The USBAUP USBFAF is used after the Status phase of a Control transfer which is signaled by the clearing of the DATA END bit in the Endpoint 0 CSR 6 0 USB Function Address Field USBFAF 7 USB Address Update USBAUP 31 8 Reserved Figure 11 6 USBFA Register 11 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB
77. USBSE 0 Suspend interrupt disable 1 Suspend interrupt enable 1 Reserved 2 USB Reset interrupt Enable USBRSTE 0 Reset interrupt disable 1 Reset interrupt enable 3 USB Disconnet Enable USBDISE 0 Disconnect interrupt disable 1 Disconnect interrupt enable 31 4 Reserved Figure 11 11 USBINTE Register 11 22 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB FRAME NUMBER REGISTER 1 2 These registers maintain the Frame Number within SOF Packet Frame Number within SOF Packet are 1161 USBFNRL is a lower byte and USBFNRH is a higher bits The only 3 bits in USBFNRH are valid Table 11 14 USB Frame Number register 1 2 Offset Address Description Reset Value Value USBFNL 0x18 USB Frame Number register Lower bits 0x00 USBFNH 0x1C USB Frame Number register Higher bits 0x00 Table 11 15 USBFN1 2 Descriptions umber use 0 USB Frame Lower byte Frame Number from SOF packet Number register L USB Frame Higher bits Frame Number from SOF packet Number register USBFNH ELECTRONICS 11 23 USB 3C4520A RISC MICROCONTROLLER 31 8 7 0 7 0 Frame Number Lower Bits 31 8 Reserved 2 0 Frame Number Higher Bits 31 3 Reserved Figure 11 12 USBFNL USBFNH Registers 11 24 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB INDEX REGISTER The 53 4520 has six enpoints So It need a mux selection method to
78. W bit if is present 3 38 ELECTRONICS 53 4520 RISC MICROCONTROLLER Examples LDRH STRH LDRSB LDRNESH HERE STRH FRED ELECTRONICS R1 R2 R3 R3 R4 14 R8 R2 223 R11 RO R5 PC FRED HERE 8 INSTRUCTION SET Load R1 from the contents of the halfword address contained in R2 R3 both of which are registers and write back address to R2 Store the halfword in at R14 14 but don t write back Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 Conditionally load R11 with the sign extended contents of the halfword address contained in RO Generate PC relative offset to address FRED Store the halfword in R5 at address FRED 3 39 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load LDM or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data around main memory THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can
79. access cannot be performed until the status bus free is indicated in two consecutive frames If none of the devices connected to the IOM interface request access to the D and channels the TIC bus address 7 will be present The device with this address will therefore have access by default to the D and channels ELECTRONICS 7 7 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER The availability of the S T interface D channel is indicated in bit5 Stop Go of the DD last byte of channel2 Figure7 5 Stop Go Figure 7 5 Structure of Last Byte of Channel 2 on DD The 2 controller checks the S G bit to determine if the D channel is available to access If the D channel is available S G 0 an HDLC frame is transmitted If the D channel is busy with other device the 2 controller should halt the transmission Bits 7 and 6 are the D channel Echo bits from the S interface echo back the two D channel bits of the current frame and are used to determine D channel collisions The echo bits are compared with the sent D channel bits to determine if a collision has occurred The 2 controller does not support the bit IC Channel Operation The 2 controller can have access to two IC channels by reading the IOM2ICRD and writing the IOM2ICTD register Only one channel must be accessed at a time since the 2 controller has registers for one channel The IC channel0 is accessed by setting the ICSEL bit to 0
80. an acceptable time interval as for example in a DRAM refresh operation NOTE You can use continuous mode together with a software request mode DMA CONTROLLER 3C4520A RISC MICROCONTROLLER Table 9 3 GDMA Control Register Description Continued Bit Number Reset Value 15 Demand mode Setting this bit speeds up external DMA operations When 15 1 the DMA transfers data when the external DMA request signal nXDREQ is active The amount of data transferred depends how long nXDREQ is active When nXDREQ is active and DMA gets the bus in Demand mode DMA holds the system bus until the nXDREQ signal becomes non active Therefore the period of the active nXDREQ signal should be carefully timed so that the entire operation does not exceed an acceptable interval as for example DRAM refresh operation NOTE In demand mode you must clear the single block and continuous mode control bits to O NOTE To ensure the reliability of DMA operations the GDMA control register bits must be configured independently and carefully 9 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER DMA CONTROLLER ELECTRONICS 16 151413121110 9 8 7 6 5 4 3 2 1 0 Run enable RE 0 Disable DMA operation 1 Enable DMA operation 1 Busy status BS 0 DMA is idle 1 DMA is active 3 2 Mode selection MODE 00 Software mode memory to memory 01 External EXTDREQ mode for external devices 10 UART block 11 HD
81. base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 16 Halfword and Signed Data Transfer with Register Offset 3 34 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET 28 27 2524 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 Les es epe om ne 3 0 Immediate Offset Low Nibble 6 5 S H 0 02 SWP instruction 01 11 11 Unsigned halfwords Signed byte Signed half words 11 8 Immediate Offset High Nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset
82. be loaded into the HTxFIFO TxFA register In 1 word transfer mode the TxFA status bit is set to 1 when the first register of the HTxFIFO is empty In 4 word transfer mode TxFA 1 when the first four 32 bit registers of the HTxFIFO are empty The TxFA status condition is automatically cleared when HTxFIFO is no longer available During DMA Tx operation this bit is always 0 so not generating interrupt Tx clear to send The nCTS input is projected to this status bit If the level at the nCTS input TxCTS pin is Low this status bit is 1 If nCTS input pin is High level TxCTS is 0 This bit does not generate an interrupt Tx stored clear to send This bit is set to 1 each time a transition in nCTS input occurs You can TxSCTS clear this bit by writing 1 to this bit Tx under run TxU When the transmitter runs out of data during a frame transmission an underrun occurs and the frame is automatically terminated by transmitting an abort sequence The underrun condition is indicated when TxU is 1 You can clear this bit by writing 1 to this bit Tx Good Frame TxGF This bis is set to 1 whenever a frame is successfully transmitted This is independent of TxFIFO state Refer to TxFC Rx FIFO available This status bit indicates when the data received can be read from the Rx RxFA FIFO When RxFA is 1 it indicates that data other than an address or a final data word is available in the HRXFIFO In 1 word tr
83. bit a STALL handshake is issued STALL to an IN token due to the MCU setting SEND STALL bit When the USB issues a STALL handshake USBINRDY is cleared USB CLear data W R Clear When the MCU writes a 1 to this bit the data toggle bit is TOGgle cleared This is a write only register USBCLTOG Lom USBSTSTALL USB Fifo FLUSH W R Clear The MCU sets this bit if it intends to flush the IN FIFO USBFFLUSH This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in progress the USB waits until the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding USBINRDY bit for that packet is cleared 0 1 2 3 4 51 6 7 ELECTRONICS 11 35 USB 3C4520A RISC MICROCONTROLLER QO r oouocio 407 40 00 rr o0o00Uoc s c ocr mmudoci io JAmozcuocqim UIz uocio 0 USB IN Packet Ready 0 Not ready for IN mode 1 Ready for In operation 1 USB FIFO Not Empty 0 Not data packet FIFO 1 There is at least one packet of data in FIFO 2 USB Under Run 0 No operation 1 Received IN token but not ready ISO 3 USB FIFO Flush 0 No operation 1 FIFO flush 4 USB Send STALL 0 No operation 1 Stall handshake transmit state 5 USB Sent STALL 0
84. bit field to match the expression If this is impossible it will give an error lt shift gt lt Shiftname gt lt register gt or lt shiftname gt expression or RRX rotate right one bit with extend lt shiftname gt s p LSR ASR ROR ASL is a synonym for LSL they assemble to the same code ELECTRONICS 3 17 INSTRUCTION SET Examples ADDEQ TEQS SUB MOV MOVS R2 R4 R5 R4 3 R4 R5 R7 LSR R2 PC R14 PC R14 3C4520A RISC MICROCONTROLLER If the Z flag is set make R2 R4 R5 Test R4 for equality with 3 The S is in fact redundant as the assembler inserts it automatically Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into R4 Return from subroutine Return from exception and restore CPSR from SPSR mode ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the data processing operations and are implemented using the TEQ TST CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the or SPSR_ lt mode gt to be moved to a general register The MSR instruction allows the contents of a general regis
85. comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution 28 27 2423 2120 19 16 15 12 11 7 5 4 3 ome om I 9 i om 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP field is used as for all coprocessor instructions to specify which coprocessor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 56 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM7TDMI has 1
86. control register TCON An interrupt request is generated whenever a timer count out down count occurs INTERVAL MODE OPERATION In interval mode a timer generates a one shot pulse of a preset timer clock duration whenever a time out occurs This pulse generates a time out interrupt that is directly output at the timer s configured output pin TOUTn In this case the timer frequency monitored at the TOUTn pin is calculated as TOGGLE MODE OPERATION In toggle mode the timer pulse continues to toggle whenever a time out occurs An interrupt request is generated whenever the level of the timer output signal is inverted that is when the level toggles The toggle pulse is output directly at the configured output pin Using toggle mode you can achieve a flexible timer clock range with 50 duty In toggle mode the timer frequency monitored at the TOUTn pin is calculated as follows frout 2 Timer data value Interval Mode 1 _ Time out i Time out Time out 46 7 Initial TOUTn is 0 Toggle Mode Figure 12 1 Timer Output Signal Timing ELECTRONICS 12 1 32 BIT TIMERS 3C4520A RISC MICROCONTROLLER TIMER OPERATION GUIDELINES The block diagram in Figure 12 2 shows how the 32 bit timers are configured in the S3C4520A The following guidelines apply to timer functions When atimer is enabled it loads a data value to its count register and begins decrement the
87. count register value When the timer interval expires the associated interrupt is generated The base value is then reloaded and the timer continues decrement its count register value Ifatimer is disabled you can write a new base value into its registers Ifthe timer is halted while it is running the base value is not automatically re loaded 32 Bit Timer Data Register TDATAn Auto Re load INTPND and INTMSK fMCLK 32 Bit Timer Count Interrupt Register TCNTn gt TMOD TEn gt Down Counter Pulse TMOD TMDn Gereralor TMOD TCLRn Port 16 Port 17 IOPCON TOENn Data Out Figure 12 2 32 Bit Timer Block Diagram 12 2 ELECTRONICS 53 4520 RISC MICROCONTROLLER 32 BIT TIMERS TIMER MODE REGISTER The timer mode register TMOD is used to control the operation of the two 32 bit timers TMOD register settings are described in Figure 12 3 Table 12 1 TMOD Register 0 Timer 0 enable TEO 0 Disable timer 0 1 Enable timer 0 1 Timer 0 mode selection TMDO 0 Interval mode 1 Toggle mode 2 Timer 0 initial TOUTO value TCLRO 0 Initial TOUTO is 0 in toggle mode 1 Initial TOUTO is 1 in toggle mode 3 Timer 1 enable TE1 0 Disable timer 1 1 Enable timer 1 4 Timer 1 mode selection TMD1 0 Interval mode 1 Toggle mode 5 Timer 1 initial TOUT1 value TCLR1 0 Initial TOUT1 is 0 in toggle mode 1 Initial TOUT1 is 1 in toggle mode
88. device ROM SRAM flash memory needs more access cycles than those defined in the corresponding control register nRCS 1 0 66 67 Not ROM SRAM Flash Chip Select The 53 4520 can access up to one external ROM Flash banks By controlling the nRCS signals you can map CPU addresses into the physical memory banks follows 0 one byte 1 half word Not Output Enable Whenever a memory access occurs the nOE output controls the output enable port of the specific memory device BOSIZE Bank 0 Data Bus Access Size Bank 0 is used for the boot program You use these pins to set the size of the bank 0 data bus as Not Write Byte Enable Whenever a memory write access occurs the nWBE output controls the write enable port of the specific memory device except for DRAM For DRAM banks CAS 3 0 and nDWE are used for the write operation DQM is data input output mask signal for SDRAM 70 71 E 0 DQMI1 0 USB Interface Internal USB transceiver differential input output Internal USB transceiver differential input output USB_SOF USB SOF USB start of frame 1 kHz frame pulse used to USB XCLKO synchronize USB isochronous transfers to an external device on a frame by frame basis USB clock source output USB_XCLK 1 USB clock source input USB_CLKSEL 27 Clock Select When USB CLKSEL is O low level PLL output clock can be used as the USB clock When USB CLKSEL is 1 high level the
89. echo bit from the transceiver is compared to detect D channel collision Monitor Channel Abort Request 0 auto cleared after transmitting MR abort MAR 1 The remote transmitter is forced to abort the current transmission This enforces the local receiver to set the MR bit to 1 Monitor Channel Sends End of 0 cleared after the EOM is sent Message MTxEOM 1 The monitor transmitter is forced to send an End of Message EOM Bus Request for BREQ 0 The TIC bus is released 1 The IOM controller starts to access the TIC bus for channel Monitor Channel Select MSEL 0 Monitor channel 0 is selected 1 Monitor channel 1 is selected 10 IC Channel Select ICSEL 0 ICO is selected 1 IC1 is selected 11 Awake Request 0 Normal AWAKE 1 The 2 controller pulls DU to low which requests the transceiver to deliver DCLK 12 Test Loop Back 0 normal LOOP 1 The DD and DU are internally connected together The Data from the transceiver will not be forwarded to the 2 controller 13 TSA Enable 0 TSA disabled TSAEN 1 TSA enable Bap o 5 LLL Monitor Channel Address Valid 0 cleared before the first byte is received MAV 1 The CPU indicates the monitor receiver that the first byte address received is valid 2 3 5 6 7 8 9 07 7 10 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER 14 13 12 11 10 zomxca4s lt 0 IOM2
90. error bit RXCRCE to 1 The transmitter and the receiver automatically perform these FCS generation transmission and checking functions The S3C4520A HDLC module also supports NO CRC operation mode In NO CRC mode transmitter does not append FCS to the end of data and the receiver also does not check FCS In this mode the data preceding the closing flag is transferred to the HRXFIFO In CRC mode the FCS field is transferred to the HRXFIFO ELECTRONICS 6 5 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER PROTOCOL FEATURES INVALID FRAME A valid frame must have at least the A C and FCS fields between its opening and closing flags Even if no CRC mode is set the frame size should not be less than 32 bits There are three invalid frame conditions Short frame a frame that contains less than 25 bits between flags Short frames are ignored Invalid frame a frame with 25 bits or more having a CRC compare error or non byte aligned Invalid frames are transferred to the HRXFIFO then the invalid frame error flag RXCRCE RxNO in the status register is set to indicate that an invalid frame has been received Aborted frame a frame aborted by the reception of an abort sequence is handled as an invalid frame ZERO INSERTION AND ZERO DELETION The zero insertion and zero deletion feature which allows the content of a frame to be transparent is handled automatically by the HDLC module While the transmitter inserts a binary 0
91. interrupt offset register 0x0000005C ELECTRONICS 14 7 INTERRUPT CONTROLLER 3C4520A RISC MICROCONTROLLER INTERRUPT PENDING BY PRIORITY REGISTER The interrupt pending by priority register INTPNDPRI contains interrupt pending bits which are re ordered by the INTPRIn register settings INTPNDPRI 22 is mapped to the interrupt source of whichever bit index is written into the priority 22 field of the INTPRIn registers This register is useful for testing To validate the interrupt pending by priority value you can obtain the highest priority pending interrupt from the interrupt offset register INTOFFSET Table 14 7 INTPNDPRI Register INTPNDPRI 0x428 interrupt pending by priority 0x00000000 INTERRUPT PENDING TEST REGISTER The interrupt pending test register INTPNDTST is used to set or clear INTPND and INTPNDPRI If user writes data to this register it is written into both the INTPND register and INTPNDPRI register The interrupt pending test register INTPNDTST is also useful for testing For INTPND the same bit position is updated with the new coming data For INTPNDPRI the mapping bit position by INTPRIn registers is updated with the new coming data to keep with the contents of the INTPND register Table 14 8 INTPNDTST Register INTPNDTST 0 42 Interrupt pending test register 0x00000000 4 8 ELECTRONICS 53 4520 RISC MICROCONTROLLER ELECTRICAL DATA ELECTRICAL DATA OVERVIEW This chapter desc
92. is connected to RXD as in local loop back mode but the receiver still monitors the RXD input 6 28 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS Table 6 10 HCON Register Description Continued Bit Bit Name Description Number 23 Rx frame discontinue When this bit is set the frame currently received is ignored and the data in RxDISCON this frame is discarded Only the last frame received is affected There is no effect on subsequent frames even if the next frame enters the receiver when the discontinue bit is set This bit is automatically cleared after a cycle 24 Tx no CRC TxNOCRC When this bit is set to 1 the CRC is not appended to the end of a frame by hardware Rx no CRC RxNOCRC When this bit is set to 1 the receiver does not check for CRC by hardware CRC data is always moved to the HRXFIFO Transparent Rx Stop This is valid for transparent mode This bit should not be changed in HDLC RxSTOP mode When this bit is set to 1 the receiver stops receiving the data in transparent mode and the receiver returns to sync search state Auto enable AutoEN This bit programs the function of both nDCD and nCTS However and RxEN must be set before the nCTS and nDCD pins can be used The AutoEN bit functions differently in HDLC mode and transparent mode In HDLC mode When this bit is 0 the nCTS and the nDCD pin doesn t effect the transmitter and the receiver respectively
93. is equal to bit 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values INSTRUCTION CYCLE TIMES MULL takes 1 m 1 l and MLAL 15 m 2 I cycles to execute where m is the number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed Instructions SMULL SMLAL e f bits 31 8 of the multiplier operand are all zero or all one e If bits 31 16 of the multiplier operand are all zero or all one e f bits 31 24 of the multiplier operand are all zero or all one In all other cases For Unsigned Instructions UMULL UMLAL e If bits 31 8 of the multiplier operand are all zero e If bits 31 16 of the multiplier operand are all zero e If bits 31 24 of the multiplier operand are all zero In all other cases 5 and are defined as sequential S cycle and internal respectively 3 26 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions Mnemonic Desorption Pupos UMULL cond S RdLo Rm Rs Unsigned multiply long 32x 32 64 UMLAL cond S Rm Rs Unsigned multiply amp Accumulate long 32 x 32 64 64 SMULL cond S Rm Rs Signed multiply long 32 x 32 64 SMLAL c
94. nECS 3 0 nRCS 1 0 and nWBE 1 0 are generated by the system manager according to a pre configured external memory scheme see Table 4 2 This is applied to SDRAM signals as same method Table 4 2 Address Bus Generation Guidelines Data Bus Width External Address Pins ADDR 21 0 Accessible Memory Size A21 A0 internal 4M bytes A22 A1 internal 4M half words Data bus width configuration 8 bit 16 bit External Address Pins 22 bit SA 21 0 ADDR 21 0 EM 22 bit System address bus SA 24 0 External 4 Internal Figure 4 3 External Address Bus Diagram 4 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER CONNECTION OF EXTERNAL MEMORY WITH VARIOUS DATA WIDTH As another example let us see how the 53 4520 maps CPU address spaces to physical addresses in external memory When the CPU issues an arbitrary address to access an external memory device the S3C4520A compares the upper 5 bits of the issued address with the address pointers of all memory banks It does this by consecutively subtracting each address pointer value from the CPU address There are two reasons why this subtraction method is used check the polarities of the subtraction result so as to identify which bank corresponds to the address issued by the CPU derive the offset address for the corresponding bank When the bank is identified and the offset has been derived the corresponding bank selection signal
95. or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Microprocessor business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Ri Kiheung Eup Yongin City Kyunggi Do Korea C P O Box 37 Suwon 449 900 TEL 82 31 209 8311 FAX 82 31 209 2839 Home Page URL http www samsungsemi com Printed in the Republic of Korea Table Contents Chapter 1 Product Overview keh EM Nae Ux T EE 1 1 RU cR est Mek 1 2 Signal Descriptions m 1 6 CPU Core Overview 1 19 MSTFUCTION AAA NCC xc tee ky octane tee Ant 1 20 Memory Interface onere dk ek aka 1 21 Operating States 1 21 Operating ModeS RR 1 21 RegisteTS n
96. output TxD is internally connected to the receiver data input RxD In Loop back mode nCTS and nDCD inputs are ignored For normal operation this bit should always be 0 17 Tx abort extension When this bit is set to 1 the abort pattern that is initiated when TxABTEXT 1 is extended to at least 16 bits of 1s in succession and the mark idle state is entered Tx abort TxABT When this bit is set to 1 an abort sequence of at least eight bits of 1s is transmitted The abort is initiated and the HTxFIFO is cleared TxABT is then cleared automatically by hardware Tx preamble TxPRMB When this bit is set to 1 the content of the HPRMB register is transmitted as many TxPL bit values in interrupt mode instead of mark idle or time fill mode This is useful for sending the data needed by the DPLL to lock the phase In DMA mode this bit is meaningless 20 Txdata terminal ready The TxDTR bit directly controls the nDTR output state Setting this bit TxDTR forces the nDTR pin to Low level When you clear the TxDTR bit nDTR goes High 21 Tx request to send When this bit is 0 the level of the nRTS pin changes automaitically TxRTS depending on hardware flow control Setting this bit forces the nRTS pin to Low level 0 If you clear this bit nRTS pin changes by hardware flow control 22 Rx echo mode Setting this bit to 1 selects the auto echo mode of operation In this mode RxECHO the TXD pin
97. preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and the address will be incremented by one word for each subsequent transfer ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system USE OF R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried INSTRUCTION CYCLE TIMES Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where n The number of words transferred b The n
98. set in LDM STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruction is then SPSR mode is transferred to CPSR at the same time as R15 is loaded STM with R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the user bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the user bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked register during the following cycle inserting a dummy instruction such as MOV after the LDM will ensure safety USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 43 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is writte
99. sets are valid and when the content of the cache must be replaced due to a cache miss the CS value becomes 10 at specified line This indicates that the content of set 0 SO was replaced When CS is 10 and when another replacement is required due to a cache miss the content of set 1 1 is replaced by changing the CS value to 01 To summarise at its normal steady state the CS value is changed from 01 or 10 to 10 or 01 This modification provides the information necessary to implement a 2 bit pseudo LRU Least Recently Used cache replacement policy NVALID 00 Set 0 set 1 all invalid Chahe miss occurs SO only 01 Set 0 valid set 1 invalid Hit Status does not change on hit Read miss AV_S1D All valid and set 1 is dirty asooo Dirty means to access just before status does not change on hit AV_SOD All valid and set 0 is dirty Figure 5 2 Cache Replace Algorithm State Diagram ELECTRONICS 5 3 UNIFIED INSTRUCTION DATA CACHE 3C4520A RISC MICROCONTROLLER CACHE DISABLE ENABLE To disable the cache disable entirely following a system reset you must set SYSCFG 1 to CACHE FLUSH OPERATION To flush cache lines you must write a zero to Tag memory bits 31 and 30 respectively The 2 Kbyte set 0 RAM area 2 Kbyte set 1 RAM area and the 512byte Tag RAM area total 128 words can be accessed from locations 0x10000000H 0x10800000H and 0x11000000H respectively Y
100. the RxFIFO 11 Rx flag detected RxFD 0 Normal operation 1 This bit is set when the last bit of the flag sequence is received 12 Rx data carrier detected RxDCD 0 nDCD input is High 1 2 nDCD input pin is Low 13 Rx stored data carrier detected RXSDCD 0 Normal operation 1 When a transition of the nDCD input occurs this bit is set 14 Rx frame valid RxFV 0 Normal operation 1 The last data byte if a frame is transgerred into the last location of RxFIFO Figure 6 12 HDLC Status Register ELECTRONICS 6 35 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER 31 30 29 28 27 26 25 24 23 22 21 zZ rrug zorro 2 15 idle RxIDLE 0 Normal operation 1 A minimum 15 consecutive 1s have been reveived 16 Rx abort 0 Normal operation 1 Seven or more consecutive 1s have been received in frame condition 17 Rx CRC error RXCRCE 0 Normal operation 1 frame Rx operation is completed with a CRC error 18 Rx non octet align RxNO 0 Received frame is octet 1 Received frame is not octet 19 Rx overrun RxOV 0 Normal operation 1 Received data is transferred into the RxFIFO when it is full 20 DPLL one clock missing DPLLOM 0 Normal operation 1 2 Set in FM Machester mode when DPLL does not detect an edge on the first entry 21 DPLL two clock missing DPLLTM 0 Normal operation 1 DPLL was not detected on two consecuti
101. the data input line RXD during time fill can cause this kind of invalid frame The received data which is clocked by the external TXC or RXC or by an internal DPLL or BRG source enters a 56 bit or 32 bit shift register before it is transferred into the HRXFIFO Synchronization is established when a flag is detected in the first eight locations of the shift register When synchronization has been achieved data is clocked through to the last byte location of the shift register where it is transferred into the HRXFIFO In 1 word transfer mode when the HRXFIFO available bit RxFA is 1 data is available at least in one word In 4 word transfer mode the RxFA is 1 when data is available in the last four FIFO register locations registers 4 5 6 and 7 The nDCD input is provided for a modem or other hardware interface If AutoEN bit in HCON 27 is set to 1 the receiver operation is dependent on the nDCD input level Otherwise receiver operation is free of the nDCD input level Receiver Interrupt Mode Whenever data is available in the HRXFIFO an interrupt is generated by RxFA if the interrupt is enabled The CPU reads the HDLC status register either in response to the interrupt request or in turn during a polling sequence When the received data available bit RxFA is 1 the CPU can read the data from the HRXFIFO If the CPU reads normal data or address data from the HRXFIFO the RxFA bit is automatically cleared In CRC mode th
102. the transmitter to generate an MTxBA interrupt When the last byte has been transmitted and acknowledged the CPU set the MTxEOM End of Message Request to 1 This enforces inactive state in the MX bit Two frames of MX inactive indicate the end of a message When the MX bit is received in the inactive state in two consecutive frames the receiver generates the MRxEOM End of Message Received interrupt and enforces an inactive state in the MR bit This terminates the Monitor channel transmission Transmission error During the transmission process the transmission is aborted only if errors in the MX MR handshake protocol occur An abort is indicated by setting the MR bit inactive for two or more frames The transmitter must react with EOM This situation is illustrated in the following figure7 3 Transmitter MX Receiver MR Figure 7 3 Abortion of Monitor Channel Transmission ELECTRONICS 7 5 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER Monitor channel collision detection When more than two devices is attached to IOM2 bus the S3C4520A resolves the collision by waiting inactive in the MX MR bits before sending and a per bit check on the transmitted data Monitor channel access priority is determined by the address of the monitor message contained in the first monitor byte transmitted Once the transmitter detects inactive and starts to transmit the first byte a per bit check is performed on each transmitted monitor bit If any
103. the value of the multiplier operand specified by Rs Its possible values are as follows 1 If bits 32 8 of the multiplier operand are all zero or all one 2 If bits 32 16 of the multiplier operand are all zero or all one 3 If bits 32 24 of the multiplier operand are all zero or all one 4 In all other cases ASSEMBLER SYNTAX MUL cond S Rd Rm Rs MLA cond S Rd Rm Rs Rn cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 Examples MUL R1 R2 R3 1 2 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 setting condition codes 3 24 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results Signed and unsigned multiplication each with optional accumulate give rise to four variations 28 27 23 22 21 20 19 16 15 12 11 ooo wm mas 05 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply an
104. this bit is set to 0 then the data on the system bus should be in Big endian Therefore the bytes will be swapped in Big endian This bit determines whether Tx data is in Little or Big endian TxLittle format HTxFIFO is in Little endian If this bit is set to 1 the data on the system bus is Little endian If this bit is set to 0 the data on the system bus is in Big endian that is the data bytes are swapped to be Little endian format This bit is valid for transparent mode In HDLC mode the bit stream order is fixed by HDLC protocol and this bit should always be set to 0 When this bit is set to 1 the receiver receives the data in reverse order MSB first This bit is valid for transparent mode In HDLC mode the bit stream order is fixed by HDLC protocol and this bit should always be set to 0 When this bit is set to 1 the transmitter reverse the bit stream order transmitting the MSB of each byte first These bits determine the length of preamble to be sent before the opening flag when the TxPRMB bit is set in the control register 000 1byte 001 2bytes and 111 8bytes will be sent When the DF bits are 000 data is transmitted and received in the NRZ data format When DF is 001 the NRZI zero complement data format is selected DF 010 selects the data format DF 011 the FM1 data format and DF 100 the Manchester data format 6 23 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER
105. time the request was fulfilled The current frame number as returned by the host Host Controller or HCD is at least 32 bits although the Host Controller itself is not required to maintain more than 11 bits Frame N 1 EOF Interval Frame E EOF Interval Frame N 4 EOF Interval Frame 1 Figure 11 1 SOF Packets 11 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB All full speed functions including hubs receive the SOF packets Frame timing sensitive functions which do not need to keep track of frame number e g a hub need only decode the SOF PID they can ignore the frame number and its CRC If a function needs to track frame number it must comprehend both the PID and the time stamp Full speed devices that have no particular need for bus timing information may ignore the SOF packet The SOF token holds the highest priority access to the bus Babble circuitry in hubs electrically isolates any active transmitters during the End of Frame EOF interval providing an idle bus for the SOF transmission sesona corses Stereo Audio i Low Speed BULK Stereo Audio Rx Voice Interrupt Control CD Figure 11 2 Frame Model ELECTRONICS 11 3 USB 3C4520A RISC MICROCONTROLLER PACKET FORMATS All packets begin with a synchronization SYNC field which is a coded sequence that generates a maximum edge transition density The SYNC field appears on the bus as IDLE followed by t
106. times to guarantee the data and clock lock Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire transmission The data one that ends the Sync Pattern is counted as the first one ina sequence Bit stuffing by the transmitter is always enforced without exception If required by the bit stuffing rules a zero bit will be inserted even if it is the last bit before the end of packet EOP signal BULK TRANSACTIONS The bulk transfer type is designed to support devices that need to communicate relatively large amounts of data at highly variable times where the transfer can use any available bandwidth Requesting a pipe with a bulk transfer type provides the requester with the following Access to the USB on a bandwidth available basis Retry of transfers in the case of occasional delivery failure due to errors on the bus Guaranteed delivery of data but no guarantee of bandwidth or latency Bulk transfers occur only on a bandwidth available basis For a USB with large amounts of free bandwidth bulk transfers may happen relatively quickly for a USB with little bandwidth available bulk transfers may trickle out over a relatively long period of time A bulk pipe is a stream pipe and therefore always has communication flowing either into or out of the host for a given pipe If a device requires bi directional bulk communication flow two bulk pipes must be used one in each direction CONTROL TRANSACTION
107. trigger level 1 In RxFIFO mode RxFIFO has valid data and reach trigger level In non FIFO mode URXBUF has valid data 8 Receive FIFO Empty RFEMT 0 Receive FIFO is not empty 1 Receive FIFO is empty 9 Receive FIFO Full RFFUL 0 Receive FIFO is not full 1 Receive FIFO is full 10 Receive FIFO Overrun OVFF 0 Receive FIFO is not occured 1 Receive FIFO overrun occured 11 Receiver in IDLE IDLE 0 Receiver is IDLE state 1 Receiver is in active state Figure 10 3 UART Status Register 10 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART 21110 m 2 lt 0 jo 12 Receive Event Time out E_RxTO 0 A promised time is not elapsed during receiving 1 Valid data in a promised time NOTE A promised time is determined according to WL Word Length Promised time 4 WL 12 14 Data Set Ready DSR 0 DSR pin nUDSR goes High 1 DSR pin nUDSR goes Low 15 Clear To Send CTS 0 CTS pin nUCTS goes High 1 CTS pin nUCTS goes Low 16 CTS event occured E CTS 0 CTS pin nUCTS has changed 1 CTS pin nUCTS keep it s level 17 Transmit Complete TC 0 Transmit is in progress 1 Transmit complete no data for Tx 18 Transmit Holding Register Empty THE 0 TxFIFO at trigger level or tranmit holding register is not empty 1 TxFIFO mode TxFIFO at trigger level is empty In non FIFO mode transmit holding register is empty
108. two input clocks 50 MHz and 48Mhz 50 MHz clock is used to special registers access and USB to system bus interfacing 48 MHz clock is used for SIE 12 MHz clock is generated from 48 MHz and used for transmitting data throughout physical cable FIQ IRQ interrupt routine should be used for USB service Max packet size is programmable with special registers Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO Endpoint 3 FIFO Interface 2 I He Endpoint 4 FIFO System Bus System Bus UC Interface Figure 11 4 USB Core Block Diagram ELECTRONICS 11 7 USB 53 4520 RISC MICROCONTROLLER SIE Serial Interface Engine Block Overview The SIE is the front end of this hardware and handles most of the protocol described in chapter 8 of the USB specification The SIE typically comprehends signaling upto the transaction level The functions that it handles could include Packet recognition transaction sequencing SOP EOP RESET RESUME signal detection generation Clock Data separation Data encoding decoding and bit stuffing CRC generation and checking Token and Data Packet ID PID generation and checking decoding Serial Parallel Parallel Serial Conversion The typical SIE has to deal with four clock zones in three domains 12 USB host 12Mhz clock or receive clock Internal 4x clock 48Mhz and transmit clock divided by 4 version SIE back side clock or interface clock 11 8 ELECTR
109. 0 1 Each channel has an associated pair of MX and MR handshake bits that control data flow Command and Indicate Channels Three Command and Indicate channels C I1 and C I2 provide real time status between devices connected via the IOM2 bus Intercommunication channels Two intercommunication data channels IC1 and IC2 provide 64 Kbit s data paths between user devices TIC bus One D channel accesses bus TIC bus The TIC function is implemented using 4 bits of the C I2 channel and allows multiple layer2 devices to individually gain access to the D and channels located in the first sub frame ELECTRONICS 7 3 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER CHANNEL OPERATION Monitor channel operation The monitor channel is a handshake protocol for high speed information exchange between 53 4520 and other devices The monitor channel operates on an asynchronous basis While data transfers on the bus take place synchronized to frame sync the flow of data is controlled by a handshake procedure using MX monitor transmit and MR monitor receive For example data is placed onto the monitor channel and the bit is activated This data will be transmitted repeatedly once per 8 KHz frame until the transfer is acknowledged via the MR bit Transmitter MX n MX MD 1st byte 1st Byte Acknowledge Receiver MX MD 2nd byte 2nd Byte Nth Byte MX MD Nth byte Acknowledge th byte
110. 0 E XDATA Bit Num A 0 E E Ext Memory Data Timing Sequence 31 0 abcd 31 0 abcd WA 4th read T ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER Table 4 11 and 4 12 Using little endian and half word access Program Data path between register and external memory HA Address whose LSB is 0 2 4 6 8 X Don t care CAS1 0 nWBE1 0 0 means active and 1 means inactive Table 4 11 Half Word Access Store Operation with Little Endian STORE CPU Reg External Memory CPU Register Data abcd abcd Bit Num 31 0 31 0 31 0 CPU Data Bus 31 0 31 0 31 0 Internal SD Bus CAS1 0 nWBE1 0 XX00 XXX0 XXX0 Bit Num 15 0 70 70 d 15 0 70 70 Ext Memory Data cd d Timing Sequence tstwrite 2nd write Table 4 12 Half Word Access Load Operation with Little Endian LOAD CPU Er om lt External Memory Ext Memory Type Halfword word Bit Num E F 15 0 CPU Register Data ba CPU Address cae Bit Num 31 0 31 0 31 0 CPU Data Bus abab Bit Num 31 0 31 0 31 0 Internal SD Bus abab Bit Num 15 0 7 0 7 0 XDATA ab a b Bit Num 15 0 70 70 Ext Memory Data ab a b Timing Sequence 19 2nd read ELECTRONICS 4 13 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER Table 4 13 and 4 14 Using little endian and b
111. 0 ELECTRONICS 53 4520 RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 1 S3C4520A Signal Descriptions Continued UART and General Purpose Ports UCLK PP16 119 The external UART clock input PLL generated clock can be used as the UART clock You can use UCLK with an appropriate divided by factor if a very precious baud rate clock is required General I O Port UTXD PP17 120 O B UART Transmit Data TXD is the UART output signal for transmitting serial data General I O Port URXD PP18 121 UART Receive Data RXD is the UART input signal for receiving serial data General I O Port nUDSR PP19 122 VB Not UART Data Set Reagy This input signals the UART that the peripheral or host is ready to transmit or receive serial data General I O Port nUDTR PP20 124 O B Not UART Data Terminal Ready This output signals the host or peripheral that the UART is ready to transmit or receive serial data General I O Port nURTS PP21 125 O B Not UART Request To Send General I O Port nUCTS PP22 126 UART Clear Send General I O Port nUDCD PP23 127 VB Not UART Data Carrier Detected General I O Port ELECTRONICS 1 11 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 1 53 4520 Signal Descriptions Concluded General Purpose I O Ports PP24 27 128 129 General I O ports xINTREQ 3 0 131 132 External Interrupt Request lines PP28 TOUTO 133 O B General I O port Timer 0 out PP29 TOUT1
112. 00 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR_ lt current mode gt 31 28 Condition Field MRS transfer register contents or immediate value to PSR flag bits only 31 28 27 26 25 24 23 22 21 12 11 e 22 Destination PSR 0 CPSR 1 SPSR_ lt current mode gt 25 Immediate Operand 0 Source operand is a register 1 SPSR_ lt current mode gt 11 0 Source Operand 0 3 0 Source Register 11 4 Source operand is an immediate value 11 8 7 0 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 11 PSR Transfer ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET RESERVED BITS Only twelve bits of the PSR are defined in ARM7TDMI Z T amp M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM7TDMI programs and future processors the following rules should be observed e reserved bits should be preserved when changing the value in a PSR e Programs should not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the app
113. 031 00064 95859 o1 26 0 960061 00064 _ 192901 05 18 0 1911315 045 0 6 13 9 0 9 9000 12 o 9 381098 9 NE SN x _ 1920 15200 13 230400 6 5 9 smma os s 587037 047 Memor 047 ar o Jaera 47 5203334 mor 4 9 ELECTRONICS 10 19 UART 3C4520A RISC MICROCONTROLLER UART CONTROL CHARACTER 1 REGISTER This Control Character registers can be used for Software Flow control In Software Flow Control mode you should write control characters into this registers If not the reset value will be used as control character For example even if you want to use one control character all control characters will have same value with it Table 10 14 Registers OxE18 UART control character1 register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 87 6 5 4 3 2 1 CONCHAR3 CONCHAR2 CONCHAR1 CONCHARO 7 0 Control Character 0 15 8 Control Character 1 23 16 Control Character 2 31 24 Control Character 3 Figure 10 9 UART Control Character 1 Register 10 20 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART UART CONTROL CHARACTER 2 REGISTER This Control Character registers can be used for Software Flow control In Software Flow Control mode you should write control characters into this registers If not the r
114. 134 O B General port Timer 1 out PP30 xDREQO 135 General I O ports PP31 xDACKO 136 External DMA Request 0 and Acknowledge 0 PP32 xDREQ1 138 General I O ports PP33 xDACK1 139 External DMA Request 1 and Acknowledge 1 PP34 xDREQ2 140 General I O ports PP35 xDACK2 141 External DMA Request 2 and Acknowledge 2 Powers VDD 1 19 37 52 Power Power 3 3V 65 73 87 101 109 123 137 10 44 46 GND Ground 59 72 80 94 108 116 130 ND Power Power for the internal USB transceiver 3 3V Ground for the internal USB transceiver Power Analog power for PLLO and PLL1 3 3V Analog Bulk ground for PLLO and PLL1 NOTES 1 DRAM or EDO normal DRAM interface signal pins are shared functions Its function will be configured by SYSCFG 31 2 The select mode for 66MHz internal system clock are prepared to the future 66MHz operation Device S3C4520A 1 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 2 S3C4520A Pin List and PAD Type Description eine ins E System nRESET 1 Not Reset ssid Reset Configurations 1 1 S304520A System Clock SDCLK SDRAM Clock ClKSEL 1 jClckSeec CLKOEN 1 1 ptc clockoutEnablepisabe Tope 1 1 ptc TestMode ume 1 1 plcd Litte endian mode selectpin Control 5 1 1
115. 14 Branch and Exchange ADR R1 0utof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outofTHUMB USING R15 AS AN OPERAND INSTRUCTION SET PC PC R5 but don t set the condition codes CMP Set the condition codes on the result of R4 R12 Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outof THUMB into R1 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUMB state is entered ie ARM state here Now processing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit 0 cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution ELECTRONICS 3 75 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 6 PC RELATIVE LOAD 7 0 15 14 13 12 11 10 8 Wore y 7 0 Immediate Value 10 8 Destination Register Figure 3 35 Format 6 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The THUMB assembler syntax is shown below Table 3 13 Summary of PC Relative Load Instruction THUMB Assembler ARM Equivalent LDR Rd PC lmm LDR Rd R15 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOT
116. 15 amp PADDR18 116 amp PCKE 117 amp PTDO 118 attribute TAP_SCAN_IN of PTDI signal is true attribute TAP_SCAN_MODE of PTMS signal is true attribute TAP_SCAN_OUT of PTDO signal is true Note 2 Uncomment TAP_SCAN_CLOCK attribute below and insert maximum operating frequency of PTCK in Hertz attribute SCAN CLOCK of PTCK signal is 1 0e6 BOTH attribute TAP_SCAN_RESET of PnTRST signal is true attribute COMPLIANCE PATTERNS of S3C4520A01 entity is PTMODE 0 attribute INSTRUCTION LENGTH of S3C4520A01 entity is 4 attribute INSTRUCTION OPCODE of S3C4520A01 entity is BYPASS 1111 amp SAMPLE 0011 amp EXTEST 0000 amp 10 ELECTRONICS 53 4520 RISC MICROCONTROLLER APPENDIX A IDCODE 1110 attribute INSTRUCTION CAPTURE of S3C4520A01 entity is 0001 attribute IDCODE_REGISTER of 53 4520 01 entity is 0001 amp version 1111000011110000 amp part number 11110000111 amp manufacturer s identity 1 required by 1149 1 attribute REGISTER_ACCESS 53 4520 01 entity is Bypass BYPASS amp Boundary SAMPLE EXTEST amp Device ID IDCODE attribute BOUNDARY LENGTH of S3C4520A01 entity is 205 attribute BOUNDARY REGISTER of S3C4520A01 entity is num cell port function safe ccell disval rslt 204 4 PnRESET input 4 203 4 PXCLK observe only X amp 202 BC 1 P
117. 2 tee Etre 7 9 lOM2 Special Registers imieni 7 9 53 4520 RISC MICROCONTROLLER Table of Contents Continued Chapter 8 TSA Timer Slot Assigner scence st Me e D Re Met M M 8 1 TSA Block Diagram e PM 8 2 HDLC External Pin Multiplexed Signals 4 8 3 Operations stk ed uui catch REL 8 3 TSA Special 8 4 Chapter 9 DMA Controller 9 1 GDMA Special Regislers 2 reete ete ette betae 9 3 Source Destination Address 9 8 DMA Transfer Count Registers 9 9 DMA Mode Operation t2 enin intente reae e ER ER REEL D RERR ERR RR LEER TR ERRARE AER EELEE 9 10 GDMA F nction DescfIptOf 9 11 9 11 Starting Ending 9 11 Data Transter ttt 9 11 Transfer Timing 9 13 Glock DeSGriptions E 9 14 Single and One Data Burst Mode GDMACON 11 0 9 0 9 15 Single and Four Data Burst Mode
118. 22 S3 C4520A 032001 USER S MANUAL 53 4520 32 RISC Microprocessor Revision 2 ELECTRONICS Product Overview Programmer s Model Instruction Set System Manager Unified Instruction Data Cache HDLC Controller 2 Controller TSA Timer Slot Assigner DMA Controller UART USB 32 Bit Timers Ports Interrupt Controller Electrical Data Mechanical Data Appendix A Product Overview Programmer s Model Instruction Set System Manager Unified Instruction Data Cache HDLC Controller 2 Controller TSA Timer Slot Assigner DMA Controller UART USB 32 Bit Timers Ports Interrupt Controller Electrical Data Mechanical Data Appendix A S3C4520A 32 BIT RISC MICROPROCESSOR USER S MANUAL Revision 2 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights
119. 3 3 Branch2Instr elioss zfs pe IS 3 7 3 4 Data Processing Instructions Ne 3 9 3 5 3 12 3 6 efe SHIT MOTE nr 3 12 3 7 Logical Shit Right 3 13 3 8 Arthmete SMit 3 13 3 9 acis EE 3 14 3 10 Rotate Right 3 14 3 11 PSR 3 20 3 12 Multiply 3 23 3 13 Multiply Long Instructions Nt 3 25 3 14 Single Data Transfer 3 28 3 15 Little Endian Offset Addressing Nt 3 30 3 16 Halfword and Signed Data Transfer with Register 3 34 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing 3 35 3 18 Block Data Transfer InstructionsS pp 3 40 3 19 Post Increment 55 pp 3 41 3 20 Pre Increment Addressing pp 3 42 3 21 Post Decrement Addressing 3 42 3 22 Pre Decrement 3 43 3 23 Swap 3 47 3 24 Software Interrupt 3 49 3 25 Coprocessor Data Operation Instruction 3 51 3 26 Coprocessor Data Transfer 3 53 3 27 Coprocessor Register Transfer Instructions pp 3 56 3 28 Undefined Instr ctllOn
120. 3 8 Used to request the branch with link form of the instruction If absent R14 will not be affected by the instruction A two character mnemonic as shown in Table 3 2 If absent then AL Always will be used The destination The assembler calculates the offset here Assembles to OXEAFFFFFE note effect of PC offset there Always condition used as default R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue fred Continue to next instruction sub ROM Call subroutine at computed address R1 1 Add 1 to register 1 setting CPSR flags onthe result then call subroutine if sub the C flag is clear which will be the case unless R1 held OxFFFFFFFF ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 4 28 27 26 25 24 21 20 19 16 15 12 11 0 fe mm ao 15 12 Destination register 0 Branch 1 Branch with Link 19 16 1st operand register 0 Branch 1 Branch with Link 20 Set condition codes 0 Do not after condition codes 1 Set condition codes 24 21 Operation code 0000 Op1 AND 0001 EOR Rd Op1 EOR Op2 0010 SUB Rd Op1 Op2 0011 RSB Rd Op2 Op1 0100 ADD Rd Op1 Op2 0101 ADC Rd 1 2 0110 SBC R
121. 37 PO NOTE If the port is used for a special function such as an external interrupt request an external DMA request or acknowledge signal or HDLC signal or timer outputs or UART signal its mode is determined by the IOPCONO 1 2 register not by IOPMODO Table 13 1 IOPMODO Register IOPMODO 0x500 port mode register 0x00000000 31 1 0 Bex uox x x x E oe x o x px oe e ox x oe ee E 0 port mode bit for port 0 0 Input 12 Output 1 port mode bit for port 1 0 Input 12 Output 2 port mode bit for port 2 0 Input 12 Output 31 port mode bit for port 31 0 Input 12 Output Figure 13 2 Port Mode Register IOPMODO 13 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER PORTS Table 13 2 IOPMOD 1 Register IOPMOD1 0 504 port mode register 0x00000000 31 6543421 0 0 port mode bit for port 32 0 Input 1 Output 1 port mode bit for port 33 0 Input 1 Output 2 port mode bit for port 34 0 Input 12 Output 5 port mode bit for port 37 0 Input 12 Output Figure 13 3 Port Mode Register IOPMOD1 ELECTRONICS 13 3 PORTS 3C4520A RISC MICROCONTROLLER PORT CONTROL REGISTER IOPCONO 1 2 The I O port control register IOPCONO 1 2 is used to configure the port pins P37 PO The is used to configure HDLC A B C interface signals UART modem interface signals Timer signals external re
122. 4 external I O banks External I O Bank 1 End Address of External I O Bank 0 128 K Half words Start Address of fixed for all I O banks External I O Bank 0 Start address of external I O bank n External I O bank 0 base pointer lt lt 20 256 Kbytes x End address of external I O bank External I O bank 0 base pointer lt lt 20 256 Kbytes x n 1 1 Where n is an external I O bank number 0 1 2 3 Figure 4 31 External I O Bank Address ELECTRONICS 4 51 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER Address Figure 4 32 EDO FP DRAM Refresh Timing 4 52 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER nSDRAS nSDCAS Precharge All banks Refresh Command Figure 4 33 Auto Refresh Cycle of SDRAM NOTE At auto refresh cycle DRAM bank 0 s tRP bit field is used as RAS pre charge time parameter ELECTRONICS 4 53 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER NOTES 4 54 ELECTRONICS 53 4520 RISC MICROCONTROLLER UNIFIED INSTRUCTION DATA CACHE UNIFIED INSTRUCTION DATA CACHE OVERVIEW The S3C4520A CPU has a unified internal 4 Kbyte instruction data cache To raise the cache hit ratio the cache is configured using two way set associative addressing The replacement algorithm is pseudo LRU Least Recently Used The cache line size is four words 16 bytes When a miss occurs four words must be fetched consecutively from external memory Typically RISC proc
123. 5 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of the transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer TRANSFERS FROM R15 A coprocessor register transfer from ARM7TDMI with R15 as the source register will store the PC 12 INSTRUCTION CYCLE TIMES MRC instructions take 1S 1 1C incremental cycles to execute where S and C are defined as sequential S cycle internal I cycle and coprocessor register transfer C cycle respectively MCR instructions take 1S bl 1C incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop ASSEMBLER SYNTAX lt MCR MRC gt cond p lt expression1 gt Rd cn cm lt expression2 gt MRC Move from coprocessor to ARM7TDMI register L 1 MCR Move from ARM7TDMI register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field Rd An expression evaluating to a valid ARM7TDMI register number cn and cm Expressions evaluating to the valid coprocessor register numbers CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field Examples MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 on c5 c6 and transfer th
124. 5 nsec falling tXDAr delay 9 63 nsec 12 66 nsec rising Figure 9 8 External DMA Requests Detailed Timing ELECTRONICS 9 13 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER CLOCK DESCRIPTION The internal clock In MCLK This is the operating clock on the 53 4520 differs MCLKO pad out clock For more clear description internal clock In is used at this timing diagram Following Figure 9 9 is the relationship of internal clock In_MCLK and MCLKO pad out clock You must think one more step that is the concern with MCLKO Internal Clk IN MCLK MCLKO gt ie MIN 9 71 ns MAX 9 47 ns NOTE Each clock is 20 ns Figure 9 9 MCLKO and SCLK In_MCLK 9 14 ELECTRONICS 53 4520 RISC MICROCONTROLLER DMA CONTROLLER SINGLE AND ONE DATA BURST MODE GDMACON 11 0 9 0 DREQ and DACK signals are active low Recommand deasserted time In_MCLK nxDREQ nxDACK NOTES 1 In this region DMA operation is independent of the number of DREQ signal pulse For example although DREQ signal pulses 3 times in the l region GDMAC transfers data only one time from source address to destination address Current DREQ signal is idle state deasserted when DACK siganl is idle state high Otherwise GDMAC recognizes current DREQ signal as next one and transfers next data recommand that DREQ signal is deasserted when DACK signal is active three more cycles 3 a cycles The a is inte
125. 6 20 Received Byte Count Register 6 45 6 21 HDLC Synchronization Register 6 46 7 1 IOM2 Channel Structure in 7 2 7 2 Monitor Channel Handshake 400 7 4 7 3 Abortion of Monitor Channel Transmission 7 5 7 4 Structure Last Byte of Channel 2 DU sssssssssseeissssssssrrersssssrrrrirnrsssssrrrrrre 7 7 7 5 Structure of Last Byte of Channel 2 on DD 7 8 7 6 IOM2 Control 7 11 7 7 IOM2 Status Register ariran 7 13 7 8 2 Interrupt Enable 7 15 7 9 2 TIC Bus Address Register 7 16 7 10 IOM2 IC Channel Transmit Data Register 7 17 7 11 2 IC Channel Receive Data Register 7 17 7 12 2 Channel Transmit Data 7 18 7 13 2 Channel Receive Data 7 18 7 14 IOM2 1 Channel Transmit Data 7 19 7 15 IOM2 1 Channel Receive Data 7 19 7 16 IOM2 Monitor Channel Transmit Data Register 7 20 7 17 IOM2 Monitor Channel Receive Data Register 7 20 7 18 IOM2 Strobe Beglsler o tete eet ete pee ium eim be uetus ae 7 21 53 4520 RISC MICROCONTROLLER xv List of
126. 9 24 Link bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instructions contain a signed 2 s complement 24 bit offset This is shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the prefetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and R14 1 0 are always cleared To return from a routine called by branch with link use MOV PC R14 if the link register is still valid Rn PC if the link register has been saved onto a stack pointed to by Rn INSTRUCTION CYCLE TIMES Branch and branch with link instructions take 2S 1N incremental cycles where S and are defined as sequential S cycle and internal I cycle ELECTRONICS 3 7 INSTRUCTION SET ASSEMBLER SYNTAX 3C4520A RISC MICROCONTROLLER Items are optional Items in lt gt must be present B L cond lt expression gt L cond lt expression gt Examples here BAL CMP BEQ BL ADDS BLCC
127. 9 Long Branch With 3 95 et Aceh Ae ccc 3 95 Instruction Cycle 3 96 Instruction Set Examples 4 3 97 Multiplication By a Constant Using Shifts And 3 97 Division 3 100 53 4520 RISC MICROCONTROLLER vii Table of Contents Continued Chapter 4 System Manager OVEIVICW MeN p pre M aah ch 4 1 System Manager Registers 4 2 External Address Translation Method Depends on the Width of External Memory 4 6 Connection of External Memory With Various Data Width Ne 4 7 ITEM 4 8 BUS Arbitr tiori i 4 15 Control Register Saaana anaa naaa ea Pak mne rd 4 16 System Configuration Register 4 16 Product Code and Revision Number Register 4 18 Peripheral amp SDRAM Clock Enable Register CER 4 19 Watch Dog Timer Register 4 20 System Clock and Mux Bus Control 4 22 Clock Control Register CLKCON 4 22 3s ccc 4 23 USB4 MHZ COCK 4 24 External I O Access Control Registers EXTACONO 1
128. ATA Bit Num Ext Memory Data Timing Sequence LOAD CPU Reg lt External Memory Ext Memory Type Half Word 7 0 Bit Num CPU Register Data 7 a CPU Address BA Bit Num CPU Data Bus Bit Num Internal SD Bus External Address CAS1 0 nWBE1 0 Bit Num Ext Memory Data Timing Sequence ELECTRONICS 4 11 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER Table 4 9 and 4 10 Using little endian and word access Program Data path between register and external memory WA Address whose LSB is 0 4 8 X Don t care CAS1 0 nWBE1 0 0 means active and 1 means inactive Table 4 9 Word Access Store Operation with Little Endian STORE CPU Reg gt External Memory Ext Memory Type Half Word Bit Num 31 0 31 0 CPU Register Data abcd abcd CPU Address A Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 CPU Data Bus abcd abcd abcd abcd abcd abcd Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 Internal SD Bus abcd abcd abcd abcd abcd abcd LO wat wae Ext Memory Data pis Bit Num 2 0 x E 0 XDATA Timing Sequence 4th write Table 4 10 Word Access Load Operation with Little Endian LOAD CPU Reg lt External Memory Ext Memory HaffWord 31 0 31 0 CPU Register Data E abcd CPU Address Bit Num 31 0 31 0 31 0 31 0 31 0 CPU Data Bus XXXd XXcd Xbcd Bit Num 31 0 31 0 31 0 31 0 31 0 Internal SD Bus XXcd abcd XXXd XXcd Xbcd Bit Num 14
129. ATA ABORTS If the address used for the swap is unacceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 11 incremental cycles to execute where S are defined as squential S cycle non sequential and internal I cycle respectively ASSEMBLER SYNTAX lt SWP gt cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers Examples SWP RO R1 R2 Load RO with the word addressed by R2 and Store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and Store bits 0 to 7 of R3 at SWPEQ RO RO R 1 Conditionally swap the contents of the word addressed by R1 with RO 3 48 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 28 27 24 23 0 1111 Comment Field Ignored by Processor 31 28 Condition F
130. An access request to the TIC bus may either be generated by the software CPU access to the C I channel or by the HDLC controller transmission of HDLC frame in the D channel An software access request to the bus is activated by setting the BREQ bit to 1 In the case of an access request the 2 controller checks the BAC bit 5 of DU last byte of channel2 for the status bus free BAC 1 If the bus is free the IOM2 controller starts to transmit its own TIC bus address programmed in the IOM2TIC register When the 2 controller transmits the TIC bus address TAD on DU it compares the bit with the value on DU If any bit mismatches that is a sent bit set to 1 is read back as 0 the 2 controller withdraws immediately from the TIC bus If more than one device attempt to access the bus simultaneously the one with the lowest address values wins If all the TIC bus address bits match the TIC bus is immediately occupied by the 2 controller by setting the BAC to 0 in the subsequent frame until the access request is withdrawn Figure 7 4 shows the channel2 of IOM2 interface TIC Bus Address Bus Access 0 Occupied 1 Accessible Figure 7 4 Structure of Last Byte of Channel 2 on DU When the TIC bus is occupied by one device the bus is identified to other devices as occupied via the BAC 0 After a successful bus access the 2 controller is automatically set into a lower priority class that is a new bus
131. B 11 1 USB BUS Topology and Physical 11 1 Frame Generation pp 11 2 PACKELFOFMALS CNRC 11 4 Bit Stuffing NRZI Coding 11 5 BULK 11 5 Control Transactions REM 11 5 Isochronous Transactions 4 11 6 Interrupt 11 6 S3C4520A USB Block 2 6 11 7 53 4520 USB Function Features pp 11 10 USB Function Address Register pp 11 12 USB Power Management 11 13 USB Endpoint Interrupt Register 11 15 rcc D 11 15 USB Interrupt 11 17 USB Endpoint Interrupt Enable Register 11 19 USB Interrupt Enable Register 11 21 USB Frame Number Register 1 2 11 23 USB Index Register 11 25 USB Disconnect Register 11 27 USB In CSR Register 1 ENDPOINT 11 31 USB In CSR Register 1 ENDPOINT1 ENDPOINT4 nnn 11 34 USB In CSR Register 2 11 37 USB Out CSR Register1 2 11 39 USB Out Write Count Register 1 2 11 43 USB d dde doli NE 11 45 Chapter 12 32 Bit Timers III
132. BINRDY bit when size packet loaded 31 8 Reserved Figure 11 18 USBICSR2 Register ELECTRONICS 3C4520A RISC MICROCONTROLLER USB USB OUT CSR REGISTER1 2 There are two CSR registers OUT CSR1 and OUT CSR2 which are used to control OUT endpoints by the MCU OUT CSR1 maintains status information while OUT CSR2 is used to configure the endpoint Table 11 28 USB Out CSR register 1 2 Offset Address EH Description ResetValue Value USBOCSR1 0x50 USB Out CSR register 1 0x00 USBOCSR2 0x54 USB Out CSR register 2 0x00 Table 11 29 USBOCSR 1 Description Bit Bit Name Description Number USB Out packet R Clear The USB sets this bit once it has loaded a packet of data ReaDY into the FIFO Once the MCU reads the FIFO for the USBORDY entire packet this bit should be cleared by MCU USB Fifo FULL R W Indicates no more packets can be accepted USBFFULL 1 0 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet lt FIFO size or 1 packet of gt FIFO size 2 USB OVER run Set This bit is valid only in ISO mode This bit is set if the USBOVER core is not able to load an OUT ISO packet into the FIFO USB Data R W This bit is valid only in ISO mode This bit should be ERRor sampled with USBORDY When set it indicates the data USBDERR packet due to be unloaded by the MCU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second packet has an
133. Because the data output is open drain the unused IC channel and all High bits of the chosen IC channel are placed in a high impedance state unless used by an HDLC frame 7 8 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER PIN DIRECTION REVERSAL The data signals on the IOM2 bus are defined as Data Upstream DU and Data Downstream DD In terminal mode a device may be required to transmit both upstream and downstream based on which channel is being transmitted at any one time As a result the actual data pins of the S8C4520A IOM2 interface need to be both inputs and outputs When the DBREV bit in IOM2CON is set the DU pin is used to receive downstream data and the DD pin is used to send upstream data IOM2 SPECIAL REGISTERS Table 7 1 IOM2 Special Registers Register RW Description Reset vae ELECTRONICS 7 9 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER Table 7 2 IOM2CON Register Control Register L Reise oft Description reset vaus IOM2CON 0xAO0 Control Register 0x00000000 2 Enable IOM2EN 0 Disable 1 Enable Data Bus Reverse DBREV 0 DD downstream DU upstream 1 00 upstream DU downstream Monitor Channel Enable MEN 0 Monitor channel is disabled 1 Monitor channel transmission is allowed TIC Bus Enable TICEN 0 TIC bus access is disabled 1 TIC bus access is enabled 4 D Channel Collision Control Enable 0 Ignore the echo bit DCOLEN 1 The
134. CONTROLLER Table 7 5 IOM2TBA Register TIC Bus Address Register Register Offset AW Description Reset Value IOM2TBA OxAOC R W TIC Bus Address 0x00000007 2 0 TIC Bus Address TBA This field defines device specific address used to gain access to TIC bus for D channel 31 5 Reserved 2 0 TIC Bus Address Figure 7 9 IOM2 TIC Bus Address Register 7 16 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER Table 7 6 IOM2ICTD 2 IC Channel Transmit Data Register Reges Description IOM2ICTD 0xA10 IC Channel Transmit Data 0x000000FF 79 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 FLEET TET TTT 7 0 IC Channel Transmit Data Figure 7 10 2 IC Channel Transmit Data Register Table 7 7 IOM2ICRD IOM2 IC Channel Receive Data Register Register RW Description ResetVaue IOM2ICRD OxA14 R W IC Channel Receive Data 0x00000000 sl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 er 7 0 IC Channel Receive Data Figure 7 11 2 IC Channel Receive Data Register ELECTRONICS 7 17 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER Table 7 8 IOM2CITDO IOM2 Channel Transmit Data Register Rester onsa RW Description IOM2CITDO 0 18 Chan
135. CS 3C4520A RISC MICROCONTROLLER UART lt RECEIVER gt UTXDn Start Data Bits 5 8 es Start THRE V 4 WR_THR INT_TXD X lt RECEIVER gt URXDn Start Data Bits 5 8 Data Bits INT_RXD URXBUF Previous Receive Data Valid Receive Data Figure 10 15 Interrupt Based Serial I O Timing Diagram Tx and Rx Only ELECTRONICS 10 25 UART 3C4520A RISC MICROCONTROLLER lt Transmitter gt Select Mode THRE p WR_THR nXDREQ nXDACK Figure 10 16 DMA Based Serial I O Timing Diagram Tx Only RECEIVER TxE lt Select DMA Mode URXDn Start Data Bits 5 8 res Start Data Bits URXBUFn Previous Receive Data Valid Receive Data nXDREQ A nXDACK A Figure 10 17 DMA Based Serial I O Timing Diagram Rx Only 10 26 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART SIO Frame Data Bits Figure 10 18 Serial Frame Timing Diagram Normal UART IR Transmit Frame Data Bits Bit frame T 7 16 6 16 Figure 10 19 Infra Red Transmit Mode Frame Timing Diagram ELECTRONICS 10 27 UART 3C4520A RISC MICROCONTROLLER IR Receive Frame Data Bits Bit frame 13 16T Figure 10 20 Infra Red Receive Mode Frame Timing Diagram 10 28 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB USB FEATURES USB products are easy to use for end users Electrical details such as bus terminati
136. CS 53 4520 RISC MICROCONTROLLER One UART e 32 byte FIFO for each Rx and Tx supported programmable trigger level with timer e Up to 460Kbps baudrate e Automatic baudrate detection e Hardware flow control e Eight control character comparison for software control GDMA based or Interrupt based operation e Programmable transmit and receive data length 5 8 bits e Programmable baud rates e Programmable 1 or 2 stop bits e Odd even force no parity mode e Break generation and detection e Parity overrun frame error detection 16 clock mode e Infra red Tx Rx support IrDA USB with Transceiver e USB specification 1 1 compliant e Full speed 12Mbps operation with internal transceiver only e Use interrupts to handle FIFO data for any endpoint e 1 control endpoint with 64 byte FIFO 2 interrupt enpoint with 16 byte FIFO EP1 2 and 2 data endpoints with 64 byte FIFOs EP3 and e Data endpoints are programmable as to direction IN or OUT transfer type bulk or interrupt and maximum packet size The maximum packet size of EP4 can be programmed to 8 16 32 or 64bytes e Fully integrated transceiver e Supports USB peripheral function not host or hub functions Two 32 bit Timers e Interval mode or toggle mode operation ELECTRONICS PRODUCT OVERVIEW Interrupt Controller 23 interrupt request sources i e 6 for three HDLOs 2
137. CS2 nECS1 nECSO VSS nDWE CKE nCAS1 nSDCAS nCASO nSDRAS nRAS1 nSDCS1 nRASO nSDCSO VDD LITTLE TMODE CLKOEN CLKSEL MCLKO SDCLK VSS XCLK VSS nRESET TDI TMS nTRST TCK TDO VDD 53 4520 144 st 10 VDD IOM2 DU TXD FILTER C 35 PP2 TXDB 11 PPS RXDB C 12 PP4 nDTRB 13 PP5 nRTSB CJ 14 PPe TXCB C 15 PP7 RXCB C 16 PP8 xDREQ5 nCTSC C 17 PP10 TXDC 20 PP11 RXDC C 21 PP12 nDTRC 22 PP14 TXCC 24 PP15 RXCC C 25 USB SOF XCLKO C 26 USB XCLK 28 VSS USB CJ 29 USB 30 VDD USB CJ 32 IOM2 DD RXD IOM2 BCL nDTR IOM2 DCL RXC USB FILTER C 34 PP13 nRTSC 23 USB CLKSEL C 27 IOM2 STRB RRTS IOM2 FSC TXC PP9 XDACKS nDCDC C 18 PP0O xDREQ4 nCTSB PP1 xDACK4 nDCDB 9 1 5 Assignment Diagram 53 4520 2 1 ELECTRONICS PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER SIGNAL DESCRIPTIONS Table 1 1 53 4520 Signal Descriptions System Signals nRESET 43 Not Reset nRESET is the global reset input for the S8C4520A For a system reset and to allow for internal digital filtering nRESET must be held to Low level for at least 64 master clock cycles Refer to Figure 3 S3C4520A reset timing diagram for more details about reset timing XCLK 53 4520 System Clock source If CLKSEL is Low PLL output clock is used as the 53 4520 internal system clock I
138. DREQ5 HDLCC nCTSC or port8 0 1 nDREQ5 nCTSC 9 nDACK5 HDLCC nDCDC or 9 0 9 1 xDACK5 nDCDC 10 HDLCC TXDC or port10 0 port10 1 TXDC 11 RXDC or port11 0 port11 1 RXDC 12 HDLCC nDTRC or port12 0 port12 1 nDTRC 13 HDLCC nRTSC or port13 0 port13 12 nRTSC 14 TXCC or port14 0 4 1 15 RXCC or port15 0 port15 1 RXCC 16 UART UCLK or port16 0 port16 1 UCLK 17 UART or port17 0 port17 1 UTXD 18 UART URXD or port18 0 port18 1 URXD 19 UART nUDSR or port19 0 port19 12 nUDSR 20 UART nUDTR or por20 0 port20 12 nUDTR 21 UART nURTS or port21 0 port21 12 nURTS 22 UART nUCTS or port22 0 port22 12 nUCTS 23 UART nDCD or port23 0 port23 12 nDCD 24 TOUTO or port28 0 port28 1 25 TOUT1 port29 0 port29 1 TOUT1 26 xDREQ3 HDLCA nCTSA or port36 0 port36 1 xDREQ3 nCTSA 27 xDACK3 HDLCA nDCDA or port37 0 port37 1 xDACK3 nDCDA Figure 13 4 I O Port Control Register 0 ELECTRONICS PORTS gt 13 5 PORTS 3C4520A RISC MICROCONTROLLER Table 13 4 IOPCON1 Register 0x50C port control register 0x00000000 4 0 Control external interrupt request 0 input for port
139. Data END USBDEND USB SETup END USBSETEND USB SenD STALL USBSDSTALL USB SerViced Out ReaDY USBSVORDY USB SerViced SETup end USBSVSET 0 1 2 3 4 51 6 7 11 32 This is a Read Only bit The USB sets this bit once a valid token is written to the FIFO An interrupt is generated when the USB sets this bit The MCU clears this bit by writing a 1 to the USBSVORDY The MCU sets this bit after writing a packet of data into endpoint 0 FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet For a zero length data phase the MCU sets USBINRDY and USBDEND at the same time The USB sets this bit if a control transaction is ended due to a protocol violation An interrupt is generated when this bit is set The MCU sets this bit after loading the last packet of data into the FIFO at the same time USBINRDY is set While it clears USBORDY after unloading the last packet of data For a zero length data phase when it clears USBORDY and sets USBINRDY This is a read only bit The USB sets this bit when a control transfer ends before USBDEND is set The MCU clears this bit by writing a 1 to the USBSVSET bit When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO When MCU acce
140. E 0 Suspend mode disable 1 Suspend mode enable 1 USB Suspend Mode USBSM 0 Normal operation 1 Suspend state 2 USB Resume USBRU 0 Normal or suspend state 1 Resume signal generation in suspend state 3 USB Reset USBRST 0 Normal operation 1 Reset received state 6 4 Reserved 7 USB ISO Update USBIU 0 ISO data updated zero data packet send 1 150 data updated 31 8 Reserved Figure 11 7 USBPM Register ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB ENDPOINT INTERRUPT REGISTER This 53 4520 has six endpoints EPO EP4 Each bit in this register corresponds to the respective endpoint number All interrupts corresponding to endpoints whose direction is programmable Type IN OUT are mapped to this register Table 11 6 USB EndPoint INTerrupt register USBEPINT USB EndPoint INTerrupt register Table 11 7 USBEPINT Description 0 USB Interrupt of R Clear This bit corresponds to endpoint 0 interrupt 0 USBIEO The USB sets this bit under the following conditions 1 USBORDY bit is set 2 USBINRDY bit is cleared 3 USBSTSTALL bit is set 4 USBSETEND bit is set 5 USBDEND bit is cleared Indicates End of control transfer For Out Mode The USB sets this bit under the following conditions 1 USBORDY set 2 USBOVER set 3 USBSTSTALL set NOTE Conditions 1 and 2 are mutually exclusive ERN USB Interrupt of R Clear For In Mode Ep1 Ep4
141. E The value specified by lmm is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places 1 gt gt 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value 3 76 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 7 LOAD STORE WITH REGISTER OFFSET 15 14 13 12 11 10 9 8 6 5 3 2 0 mw hm 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 3 36 Format 7 OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 3 14 Table 3 14 Summary of Format 7 Instructions STR Rb Ro STR Rd Rb Ro
142. E E EAE 2 12 2 3 EXCOPUON V OClOIS deae phe e e nun 2 14 3 1 The ARM Instruction Set 4 3 2 3 2 Condition Code Summary 3 4 3 3 ARM Data Processing Instructigns essen 3 11 3 4 Incremental Cycle 3 17 3 5 Assembler Syntax Descriptions 3 27 3 6 Addressing Mode 3 45 3 7 THUMB Instruction Set 5 3 65 3 8 Summary of Format 1 3 67 3 9 Summary of Format 2 InstructionsS 3 68 3 10 Summary of Format InstructionsS 3 70 3 11 Summary of Format 4 3 71 3 12 Summary of Format 5 3 74 3 13 Summary of PC Relative Load 3 76 3 14 Summary of Format 7 3 77 3 15 Summary of format 8 5 3 79 3 16 Summary of Format 9 InstructionsS 3 81 3 17 Halfword Data Transfer 3 83 3 18 SP Relative Load Store Instructions 3 84 3 19 l oad Addr65S er ne penna E RR P UE 3 85 3 20 The ADD SP Instr CllOn ette 3 87 3 21 PUSH and POP Instructions uentrem EEE E Ea 3 88 3 22 The M
143. EQ instruction used in earlier ARM processors must not be used the PSR transfer operations should be used instead The action of TEQP in the ARM7TDMI is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode 3 16 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET INSTRUCTION CYCLE TIMES Data processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Normal data processing Data processing with register specified shift 1 11 Data processing with PC written 25 1 Data processing with register specified shift PC written 25 1 1I NOTE 5 as defined sequential S cycle non sequential N cycle and internal respectively ASSEMBLER SYNTAX e MOV MVN single operand instructions lt opcode gt cond S Rd lt Op2 gt e CMP CMN TEQ TST instructions which do not produce a result lt opcode gt cond Rn lt Op2 gt e AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt Op2 gt where lt Op2 gt Rm lt shift gt or lt expression gt cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number lt gt If this is used the assembler will attempt to generate shifted immediate 8
144. GDMA mode is software or external DMA request mode This bit is used to specify the direction of a DMA operation when the mode bits 3 2 are set to 10 Peripheral from to memory or 11 Peripheral from to memory If this bit is 1 DMA operates in the memory to peripheral direction e g to the parallel port or Peripheral When it is 0 DMA operates in the peripheral to memory direction This bit determines the number of external DMA requests nXDREQs that are required for DMA operation In Single mode when 11 0 the S8C4520A requires an external request for every DMA operation In Block mode when 11 1 the S8C4520A requires only external DMA request during the entire DMA operation An entire DMA operation is defined as the operation of DMA until the counter value is zero NOTE You should not use block mode together with demand mode or single mode in conjunction with continuous mode These bits determine the transfer data width to be one byte one half word or one word If you select a byte transfer operation the source destination address will be incremented or decremented by one with each transfer Each half word transfer increments or decrements the address by two and each word transfer by four This bit let the DMA controller hold the system bus until the DMA transfer count value is zero You must therefore manipulate this bit carefully so that DMA transfer operations do not exceed
145. GDMACON 11 0 9 1 9 16 Block and One Data Burst Mode GDMACON 11 1 9 0 9 17 Block and Four Data Burst 111 1 01 1 9 17 Continuous and One Burst Mode GDMACON 14 1 9 0 9 18 Continuous Four Data Burst Mode GDMACON 14 1 9 1 9 18 Demand and One Data Burst Mode GDMACON 15 1 9 0 9 19 Demand amp Four Data Burst Mode GDMACON 15 1 9 1 9 19 Chapter 10 UART Oo Chi 10 1 UART Special Registers 10 3 UART Control Registers pp 10 4 UART Status 10 9 UART Transmit Buffer 10 16 UART Receive Buffer 10 17 UART Baud Rate Divisor 10 18 UART Baud Rate 10 19 UART Control Character 1 Register 2 10 20 UART Control Character 2 Register 10 21 UART Operati 10 22 53 4520 RISC MICROCONTROLLER Table of Contents Continued Chapter 11 USB US
146. HDLC CONTROLLERS HDLC DATA SETUP AND HOLD TIMING WITH CLOCK You can see the timing of TxD and RxD in terms of TxC and RxC HDLC clock in Figure 6 6 Table 6 3 HDLC SETUP and HOLD Time Table 7 edge delay ime see 106 m Ted RxD taling edge delay ime 10 40 ns TXC gt qe 1 lc TXD gt gt lt 1 9 82 ns 10 66ns Figure 6 6 Data Setup and Hold Timing Diagrams Tx data will be sent with delayed 9 82nsec to 10 66nsec from the falling edge of Tx Clock The data of the red period should not be changed That is the RxD should be stable from 0 2nsec to 1 0nsec after RxC rising edge It does not allow data transition during this period The RxC will be Rx receiver clock through Rx clock selection part with some delay And this RxC delay is larger then RxD delay In Figure 6 6 the dotted clock is real internal Rx clock used by the receiver Therefore there should not be transit in Rx data to avoid setup or hold violation ELECTRONICS 6 13 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC TRANSMITTER OPERATION The HTxFIFO register cannot be pre loaded when the transmitter is disabled After the HDLC Tx is enabled the flag or mark idle control bit TXFLAG in HCON is used to select either the mark idle state inactive idle or the flag time fill active idle state This active or inactive idle state will continue until data is loaded into the HTxFIFO The content of th
147. HMODEA HMODEB HMODEC 6 23 6 8 HMODE Register 6 23 6 9 HCONB and HCONC esses 6 26 6 10 HCON Register 6 26 6 11 HSTATA HSTATB HSTATC Register 6 32 6 12 HSTAT Register 6 33 6 13 HINTENA HINTENB and HINTENC 6 37 6 14 HINTEN Register Description 6 37 6 15 HBRGTCA HBRGTCB HRBGTCC 6 41 6 16 HPRMBA HPRMBB and HPRMBC 6 42 6 17 Preamble Reference Pattern 6 42 6 18 HSADR and HMASK Register 6 43 6 19 Received Byte Count Register 6 45 6 20 Synchronization 6 46 3C4520A RISC MICROCONTROLLER List of Tables continued Table Title Page Number Number 7 1 IOM2 Special Registers 7 9 7 2 IOM2CON Register Control 7 10 7 3 IOM2STAT Register Status Register 7 12 7 4 IOM2INTEN Register Interrupt Enable Register 7 14 7 5 IOM2TBA Register TIC Bus Address 7 16 7 6 IOM2ICTD IOM2 IC Channel Transmit Data
148. HUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The following table shows the exception vector addresses Table 2 3 Exception Vectors Ades Exepion MedeiEmy 777 Ox000000 Abort ata ra 2 14 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL Exception Priorities When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority Reset Data abort FIQ IRQ Prefetch abort a fF won Lowest priority 6 Undefined Instruction Software interrupt Not All Exceptions Can Occur at Once Undefined Instruction and Software Interrupt are mutually exclusive since they each correspond to particular non overlapping decoding of the current instruction If a data abort occurs at the same time as a FIQ and FIQs are enabled ie the CPSR s F flag is clear enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The ti
149. I General I O Port HDLC Ch B Receive Data See the RXDA description PP4 nDTRB 13 B O General I O Port HDLC Ch B Data Terminal Ready See the nDTRA description PP5 nRTSB 14 B O General I O Port HDLC Ch B Request To Send See the nRTSA description PP6 TXCB 15 B B General I O Port HDLC Ch B Transmitter Clock See the TXCA description PP7 RXCB General I O Port HDLC Ch B Receiver Clock See the RXCA description General I O Port External DMA Request 4 HDLC Ch B Clear To Send See the nCTSA descriptions PP1 xDACK4 General I O Port nDCDB External DMA Acknowledge 4 HDLC Ch B Data Carrier Detected See the nDCDA description General Purpose I O Ports and HDLC C PP10 TXDC 20 B O General I O Port HDLC Ch C Transmit Data See the TXDA description PP11 RXDC 21 B I General I O Port HDLC Ch C Receive Data See the RXDA description PP12 nDTRC 22 B O General I O Port HDLC Ch C Data Terminal Ready See the nDTRA description PP13 nRTSC 23 B O General I O Port HDLC Ch C Request To Send See the nRTSA description PP14 TXCC 24 B B General I O Port HDLC Ch C Transmitter Clock See the TXCA description PP15 RXCC General I O Port HDLC Ch C Receiver Clock See the RXCA description PP8 xDREQ5 General I O Port External DMA Request 5 HDLC Ch C Clear To Send See the nCTSA descriptions PP9 xDACK5 General I O Port nDCDC External DMA Acknowledge 5 HDLC Ch C Data Carrier Detected See the nDCDA description 1 1
150. IAN FORMAT In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher address 31 0 Word address Lower address Most significant byte is at lowest address Word is addressed by byte address of most signficant byte Figure 2 1 Big Endian Addresses of Bytes within Words NOTE The data locations in the external memory are different with Figure 2 1 in the 3 4520 Please refer to the chapter 4 system manager LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 Higher address 31 Word address Lower address Most significant byte is at lowest address Word is addressed by byte address of least signficant byte Figure 2 2 Little Endian Addresses of Bytes Words 2 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state Data Types supports byte 8 bit half word 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries OPERATING MODES A
151. ICROCONTROLLER 31 30 TXC RxCLK TxCLK 28 27 26 24 23 22 20 19 18 16 15 14 12 11 10 8 7 DPLL 0 Rx Transparent Mode RxTRANS 0 HDLC mode 1 Transparent mode 1 Tx Transparent Mode TxTRANS 0 HDLC mode 1 Transparent mode 2 Rx Clock Inversion RxCINV 0 Rx clock rising 1 Rx clock falling 3 Tx Clock Inversion TxCINV 0 Tx clock falling 1 Tx clock rising 4 Rx Little Endian Mode RxLittle 0 The Rx data on the system bus is in Big Endian format 1 The Rx data on the system bus is in Little Endian format 5 Tx Little Endian Mode TxLittle 0 The Tx data on the system bus is in Big Endian format 1 The Tx data on the system bus is in Little Endian format 6 Rx Reverse Data RxXREV 0 LSB first 1 MSB first 7 Tx Reverse Data TxREV 0 LSB first 1 MSB first 10 8 Tx Preamble Length TxPL 000 1 byte 100 5 byte 001 2 byte 101 6 byte 010 byte 110 7 byte 011 4 byte 111 8 byte 11 Reserved 14 12 Data Format DF 000 NRZ data format 001 NRZI 010 FMO 001 FMI 100 Machester 15 Reserved 18 16 DPLL Clock Select DPLLCLK 000 TXC pin 001 RXC pin 010 MCLK 011 BRGOUT1 100 BRGOUT2 19 Clock Select BRGCLK 0 RXC pin is selected 1 MCLK2 is selected 22 20 Tx Clock Select TxCLK 000 TXC pin 001 RXC pin 010 DPLLOUTT 011 BRGOUT1 100 BRGOUT2 27 Reserved 30 28 TXC Output Pin Select TXC
152. ICROCONTROLLER SYSTEM MANAGER Mode Register Set MRS og z nSDRAS nSDCAS 1 0 0 Figure 4 26 SDRAM Power up Sequence ELECTRONICS 4 42 SYSTEM MANAGER 53 4520 RISC MICROCONTROLLER nSDRAS nSDCAS Precharge all banks e 2 a c o gt x g lt Q o 5 9 5 c 5 c o E gt 5 E 2 o o r 2 1 confliction All DQM signals go to zero during read operation 2 Only valid singnals go to zero during write operation 3 2 Burst Length 1 Figure 4 27 Non burst Read Write Read Cycles CAS Latency 4 43 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER nSDRAS nSDCAS Address o LL o LL o LL o LL Row active Precharge all banks Figure 4 28 SDRAM Burst Read ELECTRONICS 4 44 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER DRAM INTERFACE FEATURES The S3C4520A provides a fully programmable external DRAM interface You can easily modify the characteristics of this interface by manipulating the corresponding DRAM control registers Programmable features include External data bus width Control fast or EDO mode DRAMCON O Select fast page EDO mode or SDRAM mode by SYSCFG
153. ISC MICROCONTROLLER PORTS PORT DATA REGISTER IOPDATAO 1 The I O port data register IOPDATAO contains one bit read values for ports that are configured to input mode and one bit write values for ports that are configured to output mode Bits 31 0 of the 32 bit I O port register0 value correspond directly to the 32 port pins P31 PO Bits 5 0 of the 6 bit I O port register1 IOPDATA1 value correspond directly to the 6 port pins P37 P32 Table 13 6 IOPDATAO Register IOPDATAO 0x514 port data register Undefined 31 0 port read write values for port 31 0 PO P31 NOTE The values in the I O port data register reflect the signal level on the respective I O port pins When the ports are configured to output mode the bit reflects the ports write value When the port is configured to input mode the bit reflects the ports read value Figure 13 7 Port Data Register0 Table 13 7 IOPDATA1 Register IOPDATA1 0x518 port data register Undefined 5 0 port read write values for port 37 32 P32 P37 NOTE The values in the I O port data register reflect the signal level on the respective I O port pins When the ports are configured to output mode the bit reflects the ports write value When the port is configured to input mode the bit reflects the ports read value Figure 13 8 I O Port Data Register1 IOPDATA1 ELECTRONICS 13 9 VO PORTS 3C4520A RISC
154. LC block 4 Destination address direction DA 0 Increase destination address 1 Decrease destination address 5 Source address direction SA 0 Increase source address 1 Decrease source address 6 Destination address fix DF 0 Increase decrease destination address 1 Do not change destination address fix 7 Source address fix SF 0 Increase decrease source address 1 Do not change source address fix 8 Stop interrupt enable 1 0 Do not generate a stop interrupt when DMA stops 1 Generate a stop interrupt when DMA stops 9 Four data burst enable FB 0 Disable 4 data burst mode 1 Enable 4 data burst mode 10 Transfer direction for Peripheral only TD 0 Peripheral to memory 1 Memory to Peripheral 11 Single block mode SB 0 One initiates a single DMA operation 1 One nXDREQ initiates a whole DMA operation 13 12 Transfer width TW 00 Byte 8 bits 01 Half word 16 bits 10 Word 82 bits 11 use 14 Continuous mode 0 Normal operation 1 Hold system bus until the whole DMA operation stops 15 Demand mode DM 0 Normal external DMA mode 1 Demand mode Figure 9 2 GDMA Control Register DMA CONTROLLER 3C4520A RISC MICROCONTROLLER GDMA SOURCE DESTINATION ADDRESS REGISTERS The GDMA source destination address registers contain the 26 bit source destination addresses for GDMA channels 0 1 2 3 4 and 5 Depending on the settings yo
155. MAO and HDLCA DMA1 and DMA4 to and 5 to HDLCC For example DMAO can service ether HDLCA tx channel or rx channel and is the same DMAO channel is assigned to HDLC tx channel by setting DTxSEL in HCON to 1 To use operation with HDLC you must program the HDLC tx channel firstly and then program selected DMA channel During DMA setting you must set MODE in GDMACON 3 2 to 11 binary When transfers data to TxFIFO successfully DMA interrupt will be generated In response to the interrupt you can reprogram HDLC and DMA channel and the same procedure is repeated ELECTRONICS 6 15 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC RECEIVER OPERATION The HDLC receiver is provided with data and a pre synchronized clock by means of the RXD and the internal DPLL clock the TXC pin or the RXC pin The data is a continuous stream of binary bits One of the characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort flag or idle condition occurs The receiver continuously searches bit by bit for flags and aborts When a flag is detected the receiver synchronizes the frame to the flag timing If a series of flags is received the receiver re synchronizes the frame to each successive flag If the frame is terminated because of a short frame condition frame data is less than 32 bits after an opening flag the frame is simply ignored Noise on
156. MI pipelining Examples LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2 c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from R5 write this address back to R5 and use long transfer option probably to store multiple words NOTE Although the address offset is expressed in bytes the instruction offset field is in words The assembler will adjust the offset appropriately ELECTRONICS 3 55 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER COPROCESSOR REGISTER TRANSFERS MRC MCR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between ARM7TDMI and a coprocessor An example of a coprocessor to ARM7TDMI register transfer MRC instruction would be a FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM7TDMI register A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the ARM7TDMI CPSR flags As an example the result of a
157. MICROCONTROLLER xINTREQn Internal INTREQn IOPCON xIROn 1 0 00 IOPCON xIROn 1 0 01 IOPCON xIRQn 1 0 10 IOPCON xIRQn 1 0 11 Figure 13 9 External Interrupt Request Timing Active High xINTREQn Internal INTREQn IOPCON xIROn 1 0 00 IOPCON xIROn 1 0 01 IOPCON xIRQn 1 0 10 IOPCON xIRQn 1 0 11 Figure 13 10 External Interrupt Request Timing Active Low 13 10 ELECTRONICS 53 4520 RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The S3C4520A interrupt controller has a total of 23 interrupt sources Interrupt requests can be generated by internal function blocks and at external pins The ARM7TDMI core recognizes two kinds of interrupts a normal interrupt request IRQ and a fast interrupt request FIQ Therefore all 53045204 interrupts can be categorized as either IRQ or The S3C4520A interrupt controller has an interrupt pending bit for each interrupt source Four special registers are used to control interrupt generation and handling Interrupt priority registers The index number of each interrupt source is written to the pre defined interrupt priority register field to obtain that priority The interrupt priorities are pre defined from 0 to 22 Interrupt mode register Defines the interrupt mode IRQ or FIQ for each interrupt source Interrupt pending register Indicates that an interrupt r
158. N The following sections provide a functional description of the GDMA controller operations GDMA TRANSFERS The transfers data directly between a requester and a target The requester and target are memory UART HDLC USB endpoints or external devices An external device requests GDMA service by activating nXDREQ signal A channel is programmed by writing to registers which contain requester address target address the amount of data and other control contents UART HDLC external I O or Software memory can request GDMA service UART and HDLC are internally connected to the GDMA STARTING ENDING GDMA TRANSFERS starts to transfer data after the receives service request from nXDREQ signal UART HDLC or Software When the entire buffer of data has been transferred the GDMA becomes idle If you want to perform another buffer transfer the GDMA must be reprogrammed Although the same buffer transfer will be performed again the GDMA must be reprogrammed DATA TRANSFER MODES Single Mode A request nXDREQ or an internal request causes one byte one half word or one word to be transmitted if 4 data burst mode is disable state or four times of transfer width if 4 data burst mode is enable state Single mode requires a GDMA request for each data transfer The nXDREQ signal can be de asserted after checking that nXDACK has been asserted nxDREQ A A Figure
159. O as long as data is written to the frame continue address The HDLC logic keeps track of the field sequence within the frame The frame is terminated when the last frame data is written to the Tx FIFO s frame terminate address The FCS field is automatically appended by hardware along with a closing flag Data for a new frame can be loaded into the Tx FIFO immediately after the previous frame data if TxFA is 1 The closing flag can serve as the opening flag of the next frame or separate opening and closing flags can be transmitted If a new frame is not ready to be transmitted a flag time fill or mark idle pattern is transmitted automatically If the Tx FIFO becomes empty at any time during the frame transmission an underrun occurs and the transmitter automatically terminates the frame by transmitting an abort The underrun state is indicated when the transmitter underrun status bit TxU is 1 Whenever you set the transmission abort control bit TxABT in HCON the transmitter immediately aborts the frame transmits at least eight consecutive 1s clearing the Tx FIFO If the transmission abort extension control bit TXABTEXT is set at the time an idle pattern at least 16 consecutive 1s is transmitted An abort or idle in an out of frame condition can be useful to gain 8 or 16 bits of delay time between read and write operations Transmitter DMA Mode In S3C4520A each DMA channel promises to service its specific HDLC channel D
160. ODE REGISTER Table 6 7 HMODEA HMODEB HMODEC Register Registers RW Description Resetvaue HMODEA 0x700 HDLCA Mode register 0x00000000 HMODEB 0x800 HDLCB Mode register 0x00000000 0x900 HDLCC Mode register 0x00000000 Table 6 8 HMODE Register Description Bit Bit Name Description Number 0 Rx Transparent Operation RXTRANS 1 Tx Transparent Operation 8 2 Rx clock inversion RXCINV 3 Tx clock inversion TXCINV 4 Rx Little Endian mode RxLittle 5 6 7 TxLittle Rx Reverse Mode RxREV Tx Little Endian mode Tx Reverse Mode TxREV 10 8 Tx preamble length TxPL Not applicable 14 12 Data formats DF up ELECTRONICS if this bit is set to 0 the receiver operates in hdlc mode If this bit is set to 1 the receiver operates in transparent mode if this bit is set to 0 the transmitter operates in hdlc mode If this bit is set to 1 the transmitter operates in transparent mode If this bit set to 0 the receive clock samples the data at the rising edge If this bit set to 1 the receive clock samples the data at the falling edge If this bit set to 0 the transmit clock shifts the data at the falling edge If this bit set to 1 the transmit clock shifts the data at the rising edge This bit determines whether the data is in Little or Big endian format HRXFIFO is in Little endian If
161. ON SET MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 28 27 22 21 20 19 16 15 12 11 15 12 11 8 3 0 Operand Registers 19 16 Destination Register 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs Rn is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 complement or unsigned integers The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplicatio
162. ONICS 3C4520A RISC MICROCONTROLLER USB fun_bit_stuff fun crc fun sync detect crc out RXD nrzi dec out fun_shiftreg nrzi_dec_out fun_tx_mux tx_mux_out 7 0 tx_mux_out 7 0 shiftreg_out 7 0 tx_buf_out 7 0 fun_pid_dec RX DATA T7 0 shiftreg out 7 0 gt S fun eop detect TX DATA syn VPIN rxd fun rst detect VPIN VMIN Figure 11 5 SIE Block Diagram ELECTRONICS 11 9 USB 3C4520A USB FUNCTION FEATURES Fully Compliant to USB 1 1 Specification Supports Only Full Speed Function 12 Mbps Complete Device Configuration Compatible with both and Intel UHCI Standards Support 5 Endpoints Control 1 Interrupt 3 Data Endpoints 64 Bytes Control Status Endpoint EP1 2 16 Bytes Interrupt Endpoint In Out 4 64 Bytes Data Endpoints In Out Support interface Supports Bulk or ISO Data Transfer CRC16 Generation and CRC5 CRC16 Checking NRZI Encoding Decoding Suspend Resume Control 11 10 53 4520 RISC MICROCONTROLLER ELECTRONICS 3C4520A RISC MICROCONTROLLER USB Table 11 1 USB Registers Non Indexed Registers Time Period Middle Time Period Low Indexed Registers USBMAXP USB register USBICSRI USB In CSR register 1 USBICSR2 USB In CSR register 2 Reserved USBOCSRI USB Out CSR register 1 USBOCSR
163. ONTROLLER HDLC CONTROLLERS Receiver DMA Mode In S3C4520A each DMA channel promises to service its specific HDLC channel DMAO and DMA3 HDLCA and DMA4 to HDLCB and 5 to HDLCC For example DMAO can service ether HDLCA tx channel or rx channel and is the same DMAO channel is assigned to HDLC rx channel by setting DRxSEL in HCON to 1 To use DMA operation with HDLC you must program the HDLC rx channel firstly and then program selected DMA channel During DMA setting you must set MODE GDMACON 3 2 to 11 binary When transfers data from RxFIFO successfully DMA interrupt will be generated and HRBCNT register keeps the byte count of data transferred by DMA In response to the interrupt you can reprogram HDLC and DMA channel and the same procedure is repeated TRANSPARENT OPERATION The S3C4520A can transmit or receive the data from the CPU without any modification in the transparent mode In this mode no protocol conversion such as zero insertion deletion flag insertion detection abort transmission detection in HDLC frame is performed by the hardware Instead any protocol can be implemented on the transmission channel by the software The S3C4520A performs simply a serial to parallel and parellel to serial conversion Transparent transmitter operation The transmitter enters in transparent mode by setting TXTRANS to 1 in HMODE The transmitter starts to send 1 until a new data is writte
164. OPS This pin is used for output only when it is not used as an input clock for th DPLL TxCLK or RxCLK 000 Tx clock 001 Rx clock 010 BRGOUT1 011 BRGOUT2 100 DPLLOUTT 101 DPLLOUTR 31 Reserved Ar oOmxu m x mx3 Figure 6 10 HMODE Register ELECTRONICS HDLC CONTROLLERS gt 2 gt 2 2 6 25 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC CONTROL REGISTER Table 6 9 HCONA HCONB and HCONC Register HCONA 0x704 R W HDLC channel A control register 0x00000000 R W HCONB 0x804 R W HDLC channel B control register 0x00000000 HCONB 0x904 HDLC channel C control register 0x00000000 Table 6 10 HCON Register Description Bit Bit Name Description Number 0 Tx reset TxRS Set this bit to 1 to reset the Tx block Tx block comprises HTxFIFO and a transmitter block 1 Rx reset RxRS Set this bit to 1 to reset the Rx block Rx block comprises HRXFIFO and a receiver block 2 DMA Tx Select If the transmission is serviced by this bit should be set to 1 But DTxSEL when DMA service is not required this bit should be 0 3 DMA Rx Select If the receiver is serviced by this bit should be set to 1 But when DRxSEL service is not required this bit should be 0 Tx enable When the TxEN bit is 0 the transmitter enters a disabled state and the line becomes high state In this case the transmitter block is cleared
165. R SYSTEM MANAGER 1 747 0x1FF8000 16M Half words 16M X 16 bits SA 24 0 0x0000000 NOTE ELECTRONICS Reserved 2K Half words fixed _ Continuous 512 Half Words External I O bank 1 for 4 external I O banks External I O bank 0 128K Half words Fixed for all I O banks DRAM SDRAM bank 1 DRAM SDRAM bank 0 ROM SRAM Flash bank 1 You can define banks anywhere within the 32 Mbyte address space Figure 4 1 S3C4520A System Memory 4 3 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER SYSTEM MEMORY MAP Following are several important features to note about the S8C4520A system memory The size and location of each memory bank is determined by setting the registers for current bank base pointer and current bank end pointer You can use this base next bank pointer concept to set up a consecutive memory map To do this you set the base pointer of the next bank to the same address as the next pointer of the current bank Please note that when setting the bank control registers the address boundaries of consecutive banks must not overlap This rule should be applied even if one or more banks are disabled Four external banks are defined in a continuous address space A programmer can only set the base pointer for external I O bank 0 Then the start address of the external I O bank 1 is the start address of the external I O bank 0 256KB Similarly the start addr
166. R14_svc upon reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending on the state of the ISYNC input signal When ISYNC is LOW nFIQ nIRQ are considered asynchronous and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14_fiq 4 may be disabled by setting the CPSR s F flag but note that this is not possible from User mode If the F flag is clear ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction 2 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL IRQ The IRQ Interrupt Request exception is a normal interrupt caused by a LOW level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting the bit in the CPSR though this can only be done from a privileged non User mode Irrespective of whether the exception was entered from ARM or Th
167. RCSO PnRCS1 PnOE PnWBEO PnWBE1 PADDRO PADDR PADDR2 PADDR3 PADDR4 PADDR5 PADDR6 PADDR7 PADDR8 PADDR9 PADDR11 PADDR12 PADDR13 PADDR14 PADDR15 PADDR16 PUSB SOF inout inout inout inout inout inout inout out out out out out out out out out out out out out out out out out out out out out out out out out out bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit 53 4520 RISC MICROCONTROLLER ELECTRONICS 53 4520 RISC MICROCONTROLLER PADDR21 PADDR20 PADDR10 PADDR19 PADDR17 PnDTRA BCL PnRTSA STRB PADDR18 PCKE PTDO use STD 1149 1 1994 all attribute COMPONENT CONFORMANCE S3C4520A01 entity is STD 1149 1 1993 attribute MAP of S3C4520A01 entity is PHYSICAL PIN Note 1 Insert pin map strings for different packages here An example pin map string for this design is shown below constant 144 LQFP 2020AN PIN MAP STRING 1 amp PXCLK 2 amp PCLKSEL 3 amp PCLKOEN 4 amp PTMODE 5 amp PLITTLE 6 amp PTCK 7 amp PTMS 8 amp 9 amp PnTRST 10 amp PnEWAIT 11
168. RISC MICROCONTROLLER PXDATA11 PXDATA12 PXDATA13 PXDATA14 PXDATA15 PUSB DP PUSB DM PnCTSA xDREQ3 PP36 PnDCDA xDACKS PP37 PTXDA DU PRXDA DD PTXCA FSC PnCTSB xDREQA4 PnDCDB 2 PRXDB_PP3 PnDTRB_PP4 PnRTSB_PP5 PTXCB_PP6 PRXCB_PP7 PnCTSC_xDREQ5_PP8 PnDCDC_xDACK5_PP9 PTXDC_PP10 PRXDC_PP11 PnDTRC PP12 PnRTSC PP13 PTXCC PP14 PRXCC PP15 PUCLK PP16 PUTXD PP17 PURXD PP18 PnUDSR PP19 PnUDTR PP20 PnURTS PP21 PnUCTS PP22 PnUDCD PP23 PxIREQO PP24 PxIREQ1 PP25 PxIREQ2 PP26 PxIREQ3_PP27 PxDREQO_PP30 ELECTRONICS inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit APPENDIX A A 5 APPENDIX 6 PxDACKO PP31 PxDREQ1 PP32 PxDACK1 PP33 PxDREQ2 PP34 PxDACK2 PP35 PTOUTO PP28 PTOUT1 PP29 PFILTER PUSB FLT PSDCLK PnRASO PnRAS1 PnCASO PnCAS1 PnDWE PnECSO PnECS1 PnECS2 PnECS3 Pn
169. RM7TDMI supports seven modes of operation e User usr The normal ARM program execution state e FIQ Designed to support a data transfer or channel process e RQ irq Used for general purpose interrupt handling e Supervisor svc Protected mode for the operating system e Abort mode abt Entered after a data or instruction prefetch abort e System sys A privileged user mode for the operating system e Undefined und Entered when an undefined instruction is executed Mode changes may be made under software control or may be brought about by external interrupts or exception processing Most application programs will execute in User mode The non user modes known as privileged modes are entered in order to service interrupts or exceptions or to access protected resources ELECTRONICS 2 3 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER REGISTERS has total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode dictate which registers are available to the programmer The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non User modes mode specific banked registers are switched in Figure 2 3 shows which registers are available in each mode the banked registers are marked with a shaded triangle The ARM state regis
170. S Control Transfers are bursty non periodic host software initiated request response communication typically used for command status operations Control transfers allow access to different parts of a device Control transfers are intended to support configuration command status type communication flows between client software and its function A control transfer is composed of a Setup bus transaction moving request information from host to function zero or more Data transactions sending data in the direction indicated by the Setup transaction and a Status transaction returning status information from function to host The Status transaction returns success when the endpoint has successfully completed processing the requested operation Control transfers are supported via bi directional communication flow over message pipes As a consequence when a control pipe is configured it uses both the input and output endpoint with the specified endpoint number ELECTRONICS 11 5 USB 3C4520A RISC MICROCONTROLLER ISOCHRONOUS TRANSACTIONS In non USB environments isochronous transfers have the general implication of constant rate error tolerant transfers In the USB environment requesting an isochronous transfer type provides the requester with the following Guaranteed access to USB bandwidth with bounded latency Guaranteed constant data rate through the pipe as long as data is provided to the pipe Inthe case of a delivery failur
171. SDCLK output2 amp 201 4 PCLKSEL observe only X amp 200 BC 4 PCLKOEN observe only X amp 199 4 PLITTLE observe only X amp 198 BC 1 PnRASO output2 amp 197 1 PnRAS1 output2 amp 196 1 PnCASO output2 X amp 195 1 PnCAS1 output2 X amp 194 BC_1 PCKE output2 amp 193 1 PnDWE output2 amp 192 1 PnECSO output2 191 1 PnECS1 output2 amp 190 1 PnECS2 output2 amp 189 1 PnECS3 output2 amp 188 4 PnEWAIT observe only amp 187 1 PnRCSO output2 amp 186 1 PnRCS1 output2 amp 185 4 PBOSIZE observe only amp ELECTRONICS 11 APPENDIX 3C4520A RISC MICROCONTROLLER 184 BC_1 PnOE output2 amp 183 1 PnWBEO output2 amp 182 1 PnWBE1 output2 amp 181 1 PADDRO output2 X amp 180 1 PADDR1 output2 amp 179 1 PADDR2 output2 amp 178 1 PADDR3 output2 amp 177 1 PADDR4 output2 amp 176 1 output2 amp 175 1 PADDR6 output2 amp 174 1 PADDR7 output2 amp 173 1 PADDRS8 output2 172 1 PADDR9 output2 amp 171 1 PADDR10 output2 amp 170 1 PADDR11 output2 amp 169
172. STATES From a programmer s point of view the ARM7TDMI core is always in one of two operating states These states which can be switched by software or by exception processing are e state when executing 32 bit word aligned ARM instructions and THUMB state when executing 16 bit half word aligned THUMB instructions OPERATING MODES The ARM7TDMI core supports seven operating modes e User mode a normal program execution state e Fast Interrupt Request mode for supporting a specific data transfer or channel processing e IRQ Interrupt Request mode for general purpose interrupt handling e Supervisor mode a protected mode for the operating system e Abort mode entered when a data or instruction pre fetch is aborted e System mode a privileged user mode for the operating system e Undefined mode entered when an undefined instruction is executed Operating mode changes can be controlled by software They can also be caused by external interrupts or exception processing Most application programs execute in user mode Privileged modes that is all modes other than User mode are entered to service interrupts or exceptions or to access protected resources ELECTRONICS 1 21 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER REGISTERS The S3C4520A CPU core has a total of 37 registers 31 general purpose 32 bit registers and 6 status registers Not all of these registers are always available Whether a registers is av
173. Setting this bit causes the UART to enter Auto Baud Rate Detect ABRD mode In this mode UART try to get the baud rate from input data Loop back mode Setting this bit causes the UART to enter Loop back mode In LOOPB Loop back mode the transmit data output is sent High level and the transmit buffer register UTXBUF is internally connected to the receive buffer register URXBUF NOTE This mode is provided for test purposes only For normal operation this bit should always be 0 Serial Clock Selection This selection bit specifies the clock source UCLK 0 Internal MCLK2 4 51 6 7 10 8 The 3 bit parity mode value specifies how parity generation and checking are to be performed during UART transmit and receive operations Oxx no parity 100 odd parity 101 even parity 110 parity is forced checked as a 1 111 parity forced checked as a 0 11 Number of Stop bits This bit specifies how many stop bits are used to signal end of STB frame EOF 0 one stop bit per frame 1 two stop bit per frame 10 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART Table 10 3 UART Control Register Description Continued Bit Number Reset Value 13 12 Word Length WL This two bit word length value indicates the number of data bits to be transmitted or received per frame 00 5bits 01 6bits 10 7bits 11 8bits 14 Infra red mode IR The S3C4520A UART block suppor
174. TDMI instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some mostly they just save code USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Rn p BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q BEQ Label Absolute Value TEQ Rn 0 RSBMI Rn Rn 0 Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 CMP Rb 5 ADDCS Rc Rc Ra ADDHI Rc Rc Ra Combining Discrete and Range Tests TEQ 127 CMPNE 1 MOVLS ELECTRONICS If Rn p OR Rm q THEN GOTO Label If condition not satisfied try other test Test sign and 2 s complement if necessary Multiply by 4 Test value Complete multiply by 5 Complete multiply by 6 Discrete test Range test IF lt OR Rc ASCII 127 THEN 3 59 INSTRUCTION SET Division and Remainder 3C4520A RISC MICROCONTROLLER A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross development toolkit available from your supplier A short general purpose divide routine follows MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Div1 Div2 Rent 1 Rb 0x80000000 Rb Ra Rb Rb ASL 1 Rent Rent ASL 1 Div1 0 Ra Rb Ra Ra Rb Rc Rc Rent Rcnt Rent LSR 1 Rb Rb LSR 1 Div2 Overfl
175. The USB sets this bit under the following conditions USBIE1 1 USBINRDY clear USBIE4 2 USBUNDER set 3 USBFFLUSH clear 4 USBSTALL set ELECTRONICS 11 15 USB 3C4520A RISC MICROCONTROLLER 0 USB Endpoint 0 interrupt Enable USBEOE 0 Endpoint 0 interrupt set 1 Endpoint 0 interrupt set 1 USB Endpoint 1 interrupt Enable USBE1E 0 Endpoint 1 interrupt set 1 Endpoint 1 interrupt set 2 USB Endpoint 2 interrupt Enable USBE2E 0 Endpoint 2 interrupt set 1 Endpoint 2 interrupt set 3 USB Endpoint 3 interrupt Enable USBE3E 0 Endpoint interrupt set 1 Endpoint 3 interrupt set 4 USB Endpoint 4 interrupt Enable USBE4E 0 Endpoint 4 interrupt set 1 Endpoint 4 interrupt set 31 6 Reserved Figure 11 8 USBEPINT Register 11 16 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB INTERRUPT REGISTER This register maintains interrupt status flags for bus signaling conditins viz Suspend Resume Reset Table 11 8 USB INTerrupt register Table 11 9 USBINT Description USB Suspend R Clear The USB sets this bit when it receives suspend signaling Interrupt USBSI This bit is set whenever there is no activity for 3ms on the bus Thus if the MCU does not stop the clock after the first suspend interrupt it will be continue to be interrupted every 3ms as long as there is no activity on the USB bus By default this interrupt is disabled The USB set this bit when it r
176. USB_XCLK is used as the USB clock USB_FILTER 34 AO If the PLL is used 820pF capacitor should be connected between the pin and analog ground VSS A 1 8 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 1 S3C4520A Signal Descriptions Continued NE 2 Interface and HDLC A IOM2 DU TXDA IOM 2 Data Upstream Open Drain Output HDLC Ch A Transmit Data The serial data output from the transmitter is decoded in NRZ NRZI FM Manchester data format IOM2 DD RXDA 2 Data Downstream Schmitt Trigger Input HDLC Ch A Receive Data The serial input data received by the device should be coded in NRZ NRZI FM Manchester data format The data rate should not exceed the rate of the S3C4520A internal master clock IOM2 BCL 2 Bit Clock 768kHz nDTRA HDLC Ch A Data Terminal Ready NDTRA output indicates that the data terminal device is ready for transmission and reception 2 STRB IOM 2 Data Strobe 8kHz programmable signal for selecting an 8 bit nRTSA timeslot or 16 bit timeslot HDLC Ch A Request To Send The nRTSA output is controlled by the Tx Request to Send control bit When the TxRTS bit set to 1 the nRTS output is driven Low When the TxRTS bit clear to 0 the nRTS output remains still Low until 1 when the sending frame is reached to end and 2 when there is no more data in the TxFIFO for sending a new frame 2 Frame Synchronization Clock Schmitt Trigger Input HDLC Ch A Transmitte
177. WI cond lt expression gt 3C4520A RISC MICROCONTROLLER cond Two character condition mnemonic Table 3 2 lt expression gt ignored by ARM7TDMI Examples SWI ReadC SWI Writel k SWINE 0 Supervisor code Evaluated and placed in the comment field which is Get next character from read stream Output a k to the write stream Conditionally call supervisor with 0 in comment field The previous examples assume that suitable supervisor code exists for instance 0x08 B Supervisor EntryTable DCD ZeroRtn DCD ReadCRin DCD WritelRtn Zero EQU 0 ReadC EQU 256 Writel EQU 512 Supervisor STMFD 13480 82 814 LDR RO R14 4 BIC RO RO 0xFFO000000 MOV R1 RO LSR 8 ADR R2 EntryTable LDR R15 R2 R1 LSL 2 WritelRtn LDMFD R13 RO R2 R15 3 50 SWI entry point Addresses of supervisor routines SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13 svc points to a suitable stack Save work registers and return address Get SWI instruction Clear top 8 bits Get routine offset Get start address of entry table Branch to appropriate routine Enter with character in RO bits 0 7 Restore workspace and return restoring processor mode and flags ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruc
178. When is not set to be 111 nEWAIT will not have any effect If nEWAIT is activated at the first SCLK falling edge after 7 cycles of nOE or nWBE active the access time will be delayed until nEWAIT is deasserted In case of ROM bank nRCS and nOE nWBE signals are activated simultaneously that is there is no control parameter as like tCOS EXTACONO is used to set the access timings for external I O banks 0 and 1 is used to set the external access timings for I O banks 2 and 3 NOTE The base pointer for external I O bank 0 is set in the REFEXTCON register REFEXTCON register is in DRAM control registers part Table 4 23 External Access Control Register Description EXTACONO 0x304 R W External I O access timing register 0 0x0000_0000 EXTACON1 0x308 R W External I O access timing register 1 0x0000_0000 4 26 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER 31 30 29 2827 25 24 2221 19 18 16 15 14 13 12 11 exracono o o pun won oTo owo vom exracon oo owe teow To o owe tone 2 0 Chip selection set up time on nOE tcoso tcos2 18 16 tcos1 tcos3 000 0 cycle 001 1 cycle 010 2 cycles 011 cycles 5 3 Address set up time before nECS tacso tacs2 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles 21 19 51 tacs3 000 0 cycle 001 1 cycle 010 2 cycle
179. _R_ Product Code and Revision No register 0x4520 0010 System Manager interrupt Controller Port Controller Timer Controller 1 24 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 5 S3C4520A Special Registers Continued HDLC 0x700 0x0000 0000 Ch A 0x704 0x0000 0000 0x708 0x0000 1040 0 70 RW 0x0000 0000 0 710 frame continue register 0x730 0x730 HDLC 0x800 Ch B 0x804 0x808 0x810 0x810 0x824 0x830 0x838 0x830 0x840 TxFIFO frame continue register TxFIFO frame terminate register HDLC RxFIFO entry register 0x0000_0000 RW 0 0000 0000 RW 0x0000_0000 RW 0x0000_0000 RW 0x0000_0000 RW 0 0000 0000 RW 0x0000_0000 HDLC mask register 040000 0000 Received Byte Count Register 0000 Synchronization Register Test Register _ 0x0000_007E R W HDLC mask register R W Received Byte Count Register R W Synchronization Register Test Register 0x0080_07FF R W HDLC mode register 0x0000_0000 R W HDLC control register 0x0000_0000 R W HDLC interrupt enable register 0x0000_0000 R W HDLC status register 0x0000_ 1040 TxFIFO frame continue register TxFIFO frame terminate register HDLC RxFIFO entry register 0x0000_0000 R W HDLC Preamble Constant 0x0000_0000 R W HDLC station address 0 R W HDLC station address 1 0 0000 0000 RAW HDLC station address 2 0 0000 0000 0x0000 0000 R W HDLC station addre
180. a received over the serial port The received data can be read from Receive FIFO top or URXBUF When this bit is 0 there is no valid data According to the current setting of the UART receive mode bits an interrupt DMA request is generated when USTAT O is 1 In case UCON 3 2 01 and UINTEN 0 1 interrupt requested and 21 10 or 11 DMA request occurred You can clear this bit by reading Receive FIFO or URXBUF NOTE Whether Receive FIFO top or URXBUF is depends on the UCON 17 RFEN This bit automatically set to one to indicate that a break signal has been received in Receive FIFO top or URXBUF If the BSD interrupt enable bit UINTEN 1 is 1 a interrupt is generated when break occurs You can clear this bit by writing 1 to this bit This bit automatically set to 1 whenever a frame error occurs during a serial data receive operation A frame error occurs when a zero is detected instead of the Stop bit s If the FER interrupt enable bit UINTEN 2 1 1 a interrupt is generated when a frame error occurs You can clear this bit by writing 1 to this bit This bit automatically set to 1 whenever a parity error occurs during a serial data receive operation If the PER interrupt enable bit UINTEN 3 is 1 a interrupt is generated when a parity error OCCUIS You can clear this bit by writing 1 to this bit 10 9 UART 3C4520A RISC MICROCONTROLLER Table 10 5 UART Status Regis
181. a0 destination address1 and destination data1 destination address2 and destination data2 gt destination address2 and destination data2 destination address3 and destination data3 gt NOTE If you want to use continuous mode you must set block mode not single mode If you want to use demand mode you must set single mode not block mode ELECTRONICS 9 19 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER NOTES 9 20 ELECTRONICS 53 4520 RISC MICROCONTROLLER UART SERIAL UART OVERVIEW The S3C4520A UART Universal Asynchronous Receiver Transmitter unit provides one independent asynchronous serial I O SIO ports UART can operate in interrupt based or DMA based mode Only Used DMAO 1 2 That is the UART can generate internal interrupts or DMA requests to transfer data between the CPU and the serial I O ports The most important features of the S3C4520A UART include Programmable baud rates 32 byte Transmit FIFO and 32 byte Receive FIFO source clock selectable Internal clock MCLK2 External clock EUCLK Infra red IR transmit receive Insertion of one or two Stop bits per frame Selectable 5 bit 6 bit 7 bit or 8 bit data transfers Parity checking SIO unit has a baud rate generator transmitter receiver and a control unit as shown in Figure 10 1 The baud rate generator can be driven by the internal system clock divided by 2 MCLK or by the external cl
182. ables continued Title Page Number USB 11 11 USB Function Address register 11 12 USBFA Descriptigm 11 12 USB Power Management 11 13 USBPM 11 13 USB INTerrupt 11 15 USBEPINT 11 15 USB INTerrupt 11 17 USBINT Description 11 17 USB INTerrupt Enable 11 19 USBEPINTE Description 11 19 USB INTerrupt Enable 11 21 USBINTE Description 11 21 USB Frame Number register 1 11 23 USBFN 1 2 11 23 USB INDEX register 11 25 USBIDX Description 11 25 USB DISCONNECT 11 27 USB DISCONNECT 11 27 USB register 11 29 USBMAXP Description een 11 29 USB In CSR register 1 11 31 USBICSR1 for EPO 11 32 USB In CSR register 11 34 USBICSR1 Description
183. access special registers in each endpoint that they have a same function registers but these registers are existed independently The USB INDEX register USBINDEX select one endpoint among six endpoints In Indexed Registers and Out indexed Registers at Table 12 1 are listed to show registers are selected by USB INDEX register Table 11 16 USB INDEX register Table 11 17 USBIDX Description USB InDex R W Index to access one among six endpoints register 000 EPO indexed register can be accessed USBIDX ELECTRONICS 11 25 USB 11 26 53 4520 RISC MICROCONTROLLER 2 0 USB InDeX 000 Endpoint 0 indexed register can be accessed 001 Endpoint 1 indexed register can be accessed 010 Endpoint 2 indexed register can be accessed 011 Endpoint 3 indexed register can be accessed 100 Endpoint 4 indexed register can be accessed 31 3 Reserved Figure 11 13 USBIDX Register ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB DISCONNECT REGISTER This register makes bus state disconnected state You first set the disconnect interval time in the disconnect register and then set the enable bit USBDIS1 7 The Disconnect logic keep the line state in SEO After 10us any hub detect our usb disconnected So bus reset will be started again You can calculate wait time period by below WDT_CNT 22 0 Table 2 mee 2 1 0 Count gimeowswe x 2083331 N 2702 67 hs EX x x x foo
184. aded into bits 16 through 31 of the register A shift operation is then required to move and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 word store STR should generate word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 3 30 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET USE OF R15 Write back must not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When R15 is the source register Rd of a register store STR instruction the stored value will be address of the instruction plus 12 RESTRICTION ON THE USE OF BASE REGISTER When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the
185. agement hardware makes suitable use of this hardware SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word B 0 between an ARM7TDMI register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM7TDMI core The two possible configurations are described below Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correc
186. ailable to the programmer at any given time depends on the current processor operating state and mode NOTE When the S3C4520A is operating in ARM state 16 general registers and one or two status registers can be accessed at any time In privileged mode mode specific banked registers are switched in Two register sets or banks can also be accessed depending on the core s current state the ARM state register set and the THUMB state register set e The ARM state register set contains 16 directly accessible registers RO R15 All of these registers except for R15 are for general purpose use and can hold either data or address values An additional 17th register the CPSR Current Program Status Register is used to store status information e The THUMB state register set is a subset of the ARM state set You can access 8 general registers RO R7 as well as the program counter PC a stack pointer register SP a link register LR and the CPSR Each privileged mode has a corresponding banked stack pointer link register and saved process status register SPSR The THUMB state registers are related to the ARM state registers as follows e THUMB state RO R7 registers and ARM state RO R7 registers are identical e THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical e THUMB state SP LR and PC are mapped directly to ARM state registers R13 R14 and R15 respectively In THUMB state registers R8 R15 are not part of
187. ain 26 as the Word7 value and 1 ELECTRONICS 3 87 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 14 PUSH POP REGISTERS 15 14 13 12 11 10 7 0 9 8 2 7 0 Register List 8 PC LR Bit 0 Do not store LR Load PC 1 Store LR Load PC 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 43 Format 14 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 3 21 NOTE The stack is always assumed to be full descending Table 3 21 PUSH and POP Instructions L THUMB ARM Equivalent Assembler PUSH Rlist STMDB R13 Rlist Push the registers specified by Rlist onto the stack Update the stack pointer 1 PUSH Rlist LR STMDB R13 Rlist R14 Push the Link Register and the registers specified by Rlist if any onto the stack Update the stack pointer 1 POP Rlist LDMIA R13 Rlist Pop values off the stack into the registers specified by Rlist Update the stack pointer 1 1 POP Rlist LDMIA R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer 3 88 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM ins
188. al channels The various channels are time multiplexed over a four wire serial interface Data is clocked by a Data Rate Clock DCL that operates at twice the data rate Frames are delimited by an 8 kHz Frame Synchronization Clock FSC Data is carried over Data Upstream DU and Data Downstream DD signals Three additional signals are specified in the terminal mode to facilitate connecting components that do not directly support IOM2 These are a 1x Bit rate Clock BCL and two Serial Data Strobes that identify the location of the B channels 5051 5052 The 53 4520 includes two optional signals BCL and 8051 5051 is called STRB S3C4520A In S3C4520A the terminal mode operation is supported but line card mode is not supported Figure7 1 shows the 2 channel structure in terminal mode x ded s MR MX l Figure 7 1 IOM2 Channel Structure in Terminal DU DD 7668 kbit s DU data upstream output DD data downstream input DCL 1536 kHz input Double Data Rate FSC 8 kHz input 768 kHz output STRB strobe signal for non IOM2 device 7 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER B channels The B1 and B2 provide two clear 64 Kbit s user data channels to from the network D channel The 16 Kbit s D channel provides a connection between the layer 2 and layer 1 components Monitor channels There are two programming channels monitors
189. al clock must be used USB 48 MHz Clock OTES If USB is 1 the PLL block became to the state of power down MF means multiplication factor Figure 4 11 USB 48 MHz Clock Circuit 4 24 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER For the purpose of power save Clock Control Register CLKCON can be programmed at low frequency When the internal system clock is divided by CLKCON its duty cycle is changed If CLKCON is programmed to zero the internal system clock remains the same as the internal clock ICLK In other cases the duty cycle of internal system clock is no longer 50 Figure 4 12 shows the internal system clock MCLK waveform according to the clock dividing value MCLK CLKCON 0 MCLK CLKCON 1 MCLK CLKCON 2 Figure 4 12 Divided System Clocks Timing Diagram ELECTRONICS 4 25 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER EXTERNAL I O ACCESS CONTROL REGISTERS 1 The System Manager has two external I O access control registers These registers correspond to up to four external I O banks that are supported by 53 4520 Table 4 23 describes two registers that are used to control the timing of external I O bank accesses You can control the external I O access cycles using either a specified value or an external wait signal nEWAIT Especially to obtain access cycles that are longer than tACC of 7 cycles you can delay the active time of nOE or nWBE by nEWAIT assertion
190. also transfer to and from the user bank see below The register list is a 16 bit field in the instruction with each bit corresponding to a register A 1 in bit 0 of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 28 27 25 24 23 22 21 20 19 16 15 0 Lus pw ejes um 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 40 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre post bit P and the up down bit U The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lo
191. anager is warned to treat them as inseparable This class of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The lock output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation BYTES AND WORDS This instruction class may be used to swap a byte B 1 or a word B 0 between an ARM7TDMI register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers In particular the description of Big and Little Endian configuration applies to the SWP instruction USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction ELECTRONICS 3 47 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER D
192. ansfer mode RxFA bit set to 1 when received data is available in the last FIFO register In 4 word transfer mode it is set to 1 when the data received is available in the last four 32 bit FIFO registers Even if the data reside in FIFO for only two words when the Last bit is set Rx FIFO is regarded as valid The received data available condition is cleared automatically when the data received is no longer available During DMA Rx operation this bit is always 0 so does not generate an interrupt Rx flag detected RxFD This bit is set to 1 when the last bit of the flag sequence is received This bit generates an interrupt if enabled You can clear this bit by writing a 1 to this bit Rx data carrier detected The DCD status bit mirrors the state of the nDCD input pin If nDCD input RxDCD pin is low this status bit is 1 If nDCD input pin is High it is 0 This bit does not generate an interrupt ELECTRONICS 6 33 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER Table 6 12 HSTAT Register Description Continued Bit Bit Name Description Number Rx stored data carrier detected RxSDCD Rx frame valid RxFV Rx idle RxIDLE Rx abort RxABT DPLL one clock missing DPLLOM DPLL two clock missing DPLLTM This bit is set to 1 when a transition in nDCD input occurs and can generate interrupt if enabled You can clear this bit by writing 1 to this bit This bit signals frame s ending bound
193. ansfers Because the design of 53 4520 bus allows only one bus master at a time a bus controller is required to arbitrate when two or more internal units simultaneously request bus mastership The 53 4520 can support fixed priority and round robin method by register setting When the bus mastership is granted to an internal function block other pending requests are not acknowledged until the previous bus master has released the bus To facilitate bus arbitration priorities are assigned to each internal 53 4520 function block The bus controller arbitration requests for the bus mastership according to these fixed priorities In the event of contention mastership is granted to the function block with the highest assigned priority In case of round robin bus contention does not occurred Fixed priorities are listed in Table 4 15 Table 4 15 Bus Priorities for Arbitration SDRAM self refresh controller DRAM memory refresh controller General DMA 5 GDMA 5 General DMA 4 GDMA 4 General DMA 3 GDMA 3 General DMA 2 GDMA 2 General DMA 1 GDMA 1 General DMA 0 GDMA 0 B 6 Lowest priority in Group B Writer buffer C 1 Highest priority in Group C Bus router C 2 Lowest priority in Group C NOTE The internal function blocks are divided into three groups Group A Group B and Group C Within each group the bus arbitration priorities are fixed according to the assigned level only when set to one In this cas
194. ary to the CPU and also indicates that no frame error occurred It is set when the last data byte of a frame is transferred into the last location of the Rx FIFO and is available to be read The RxIDLE status bit indicates that a minimum of 15 consecutive 1s have been received The event is stored in the status register and can be used to trigger a receiver interrupt The RxIDLE bit continues to reflect the inactive idle condition until a 0 is received You can clear this bit by writing a 1 to this bit The RxABT status bit is set to 1 when seven or more consecutive 1s abort sequence have been received When an abort is received in an in frame condition the event is stored in the status register triggering an interrupt request You can clear this bit by writing a 1 to this bit The RxOV status bit is set to 1 if the data received is transferred into the HRXFIFO when it is full resulting in a loss of data Continued overruns destroy data in the first FIFO register When operating FM Manchester mode the DPLL sets this bit to 1 if it does not detect an edge in its first attempt You can clear this bit by writing a 1 to this bit When it is operating in the FM Manchester mode the DPLL sets this bit to 1 if it does not detect an edge in two successive attempts At the same time the DPLL enters Search mode In NRZ NRZI mode and while the DPLL is disabled this bit is always 0 You can clear this bit by writing a 1 to t
195. assumes a 25 MHz clock from MCLk2 a 24 576 MHz clock from RxC showing a time constant for a number of commonly used baud rates Table 6 2 Baud Rate Example of HDLC BRGoura ONT Freq Devic ONTO cT CNT Frea 12001 oo 1 12000 oo e o 1 24000 oo mo see 1 8000 oo 9e e o 95659 oo o 1941 os v 3 192000 o os s 1 esoo o os o semeo 12 797171 puewi 3 uemse 26 57600 115200 4 3 6 8 ELECTRONICS 53 4520 RISC MICROCONTROLLER HDLC CONTROLLERS DIGITAL PHASE LOCKED LOOP DPLL The HDLC module contains a digital phase locked loop DPLL function to recover clock information from a data stream with or FM encoding The DPLL is driven by a clock that is normally 32 16 FM times the data rate The DPLL uses this clock along with the data stream to construct the clock This clock may then be used as the receive clock the transmit clock or both Figure 6 3 shows a block diagram of the digital phase locked loop It consists of a 5 bit counter an edge detector and a pair of output decoders RxD Edge Receive Clock Count Modifier Decoder gt dplloutR Transmit clo
196. ate Program Status Register CPSR CPSR CPSR CPSR CPSR CPSR SPSR svc M SPSH abt SPSR NSPSH und banked register Figure 2 3 Register Organization in ARM State ELECTRONICS 2 5 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER The THUMB State Register Set The THUMB state register set is a subset of the ARM state set The programmer has direct access to eight general registers RO R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked stack pointers link registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State General Registers and Program Counter Supervisor THUMB State Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR fiq M SPSHR svc M SPSH abt SPSR und banked register Figure 2 4 Register Organization in THUMB State 2 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way THUMB state RO R7 and ARM state RO R7 are identical THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state program counter maps onto the ARM state program counter R15 This relationshi
197. ats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour USE OF R15 Write back should not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 should not be specified as the register offset Rm When R15 is the source register Rd of a Half word store STRH instruction the stored address will be address of the instruction plus 12 DATA ABORTS A transfer to or from legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input high whereupon the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 15 1N 11 LDR H SH SB PC take 2S 2N 11 incremental cycles S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STRH i
198. bit 0 the corresponding interrupt is disabled 0 4 interrupt If bit 1 the corresponding interrupt is enabled Enable ELECTRONICS 11 19 USB 3C4520A RISC MICROCONTROLLER 0 USB Endpoint 0 interrupt Enable USBEOE 0 Endpoint 0 interrupt disable 1 Endpoint 0 interrupt enable 1 USB Endpoint 1 interrupt Enable USBE1E 0 Endpoint 1 interrupt disable 1 Endpoint 1 interrupt enable 2 USB Endpoint 2 interrupt Enable USBE2E 0 Endpoint 2 interrupt disable 1 Endpoint 2 interrupt enable 3 USB Endpoint 3 interrupt Enable USBE3E 0 Endpoint 3 interrupt disable 1 Endpoint 3 interrupt enable 4 USB Endpoint 4 interrupt Enable USBE4E 0 Endpoint 4 interrupt disable 1 Endpoint 4 interrupt enable 31 6 Reserved Figure 11 10 USBEPINTE Register 11 20 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB INTERRUPT ENABLE REGISTER Corresponding to each USB INTerrupt Register USBINT there is an interrupt enable bit at USB Interrupt Enable Register Bank USBINTE By default all interrupts except suspend are enabled Table 11 12 USB INTerrupt Enable register USBINTE USB INTerrupt Enable register Table 11 13 USBINTE Description USB Interrupt R W If bit 0 the corresponding interrupt is disabled Enable Register If bit 1 the corresponding interrupt is enabled Bank ELECTRONICS 11 21 USB 3C4520A RISC MICROCONTROLLER E m doUuU0oc mvm 0 USB Suspend interrupt Enable
199. bit is set to 1 also An interrupt or DMA request is generated when USTATT 7 is 1 In case of UCON 3 2 01 and UINTEN 7 1 interrupt requested and UCON 3 2 10 or 11 DMA request occurred You can clear this bit by reading Receive FIFO or URXBUF with a good data If any error this bit is cleared by writing 1 to corresponding error bit in USTAT register 8 Receive FIFO empty This bit is only for CPU to monitor UART When Receive FIFO is empty this bit is set to 1 After reset default value is 1 This bit is only for CPU to monitor UART When Receive FIFO is full this bit is set to 1 After reset default value is 0 Receive FIFO overrun This bit is set to 1 when Receive FIFO overrun occurs during the RFOV Receive FIFO mode You can clear this bit by writing 1 to this bit 11 Receiver in idle RIDLE This bit is only for CPU to monitor UART The RxIDLE status bit indicates that the inactive state of RXDATA 10 10 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART Table 10 5 UART Status Register Description Continued Bit Number Reset Value 12 Receive Event time out During Receive FIFO mode if there is a valid data in URXFIFO or E_RxTO Receive FIFO within a promised time internal which is determined according to WL Word Length this bit is set 1 URXFIFO is for non FIFO mode and Receive FIFO is for FIFO mode If the E RxTO interrupt enable bit UINTEN 12 is 1 an interrupt is generat
200. bit mismatches the transmitter immediately withdraws from the monitor channel by setting the all remaining bits to 1 the monitor channel collision detection interrupt is generated and the transmitter reverts back to waiting for the idle condition Channel Operation The channel carries the commands and indications between the 53 4520 and layer 1 device to control the activation deactivation procedures channel access may be arbitrated via the TIC bus access protocol The CPU have access to channel by using two registers IOM2CITDO in transmit direction and IOM2CIRDO in receive direction The data written to IOM2CITDO is continuously transmitted until new data is to be sent The 2 receiver generates interrupt whenever the receive data changes and is stable for two frames double last look criterion The 1 channel carries the real time status information between the S3C4520A and 2 devices other than layer 1 device The C I1 channel is accessed via IOM2CITD1 and IOM2CIRD1 7 6 ELECTRONICS 53 4520 RISC MICROCONTROLLER IOM2 CONTROLLER TIC Bus Access The TIC bus capability enables more than one device to access IOM2 bus The arbitration mechanism is implemented in the last byte of channel2 of IOM2 interface This allows external communication controllers up to 7 to access the and D Channel in the channelO of IOM2 interface The TIC bus access is enabled by setting the TICEN to 1
201. bits of the result are filled with zeros and the high bits of Rm which do not map into the result are discarded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 Contents of Rm Value of Operand 2 00000 Figure 3 6 Logical Shift Left NOTE LSL 0 is a special case where the shifter carry out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A logical shift right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET 31 5 4 0 Contents carry out 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 82 to be specified An arithmetic shift right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complem
202. ble Table 3 18 SP Relative Load Store Instructions THUMB Assembler Equivalent STR Rd SP Imm STR R13 Imm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR Rd LDR Rd R13 Add unsigned offset 255 words 1020 bytes Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied 1 is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places Imm gt gt 2 in the Word8 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value 3 84 ELECTRONICS 3 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 12 LOAD ADDRES 15 14 13 7 0 1 12 11 10 8 woas 7 0 8 bit Unsigned Constant 10 8 Destination Register 11 Source 0 PC 1 SP Figure 3 41 Format 12 OPERATION These instructions calculate an address by adding an 10 bit constant to either the PC or the SP and load the resultin
203. bserve only X end 3C4520A01 A 16 ELECTRONICS
204. ck 5 bit Counter dplloutT BRGOUT1 BRGOUT2 18 16 Figure 6 3 DPLL Block Diagram CLOCK USAGE METHOD BRGCLK DPLLCLK BRGOUT1 TxC gt DPLLOUTT Meck DPLL MCLK2 Generator BRGOUT1 BRGOUT2 BRGOUT j DPLLORTR RxCLK TxC gt Transmit RxC Receive Receive Transmitter DPLLOUTT Receiver Data BRGOUT1 gt Clock Data BRGOUT2 BRGOUT2 NOTE BRGCLK HMODE 19 DPLLCLK HMODE 18 16 TxCLK HMODE 22 20 RxCLK HMODE 26 24 Figure 6 4 Clock Usage Method Diagram ELECTRONICS 6 9 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER In the NRZ NRZI mode the DPLL source clock must be 32 times the data rates In this mode the transmit and receive clock outputs of the DPLL are identical and the clocks are phased so that the receiver samples the data in the middle of the bit cell The DPLL counts the 32x clock using an internal 5 bit counter As the 32x clock is counted the DPLL searches the incoming data stream for edges either positive or negative transition The output of DPLL is High while the DPLL is waiting for an edge in the incoming data stream When it detects a transition the DPLL starts the clock recovery operation The first sampling edge of the DPLL occurs at the counter value of 16 after the first edge is detected in the incoming data stream The second sampling edge occurs following the next 16 When the
205. cludes the data received on the 1 channel This data is sure to be valid by double last look criterion valid during two successive frames 31 6 o Reseved i O 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 4 32 1 0 TET TET TTT TET cmn 5 0 1 Channel Receive Data Figure 7 15 2 C I1 Channel Receive Data Register ELECTRONICS 7 19 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER Table 7 12 IOM2MTD IOM2 Monitor Channel Transmit Data Register Regste RW Bescipon Resetvaue IOM2MTD 0 28 R W Monitor Channel Transmit Data 0x000000FF 7 0 MTxD This field includes the data to be transmitted on the monitor channel selected by MSEL if MEN 1 31 8 Reseved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 FLEET TET TTT TTT TE nr 7 0 Monitor Channel Transmit Data Figure 7 16 IOM2 Monitor Channel Transmit Data Register Table 7 13 IOM2MRD IOM2 Monitor Channel Receive Data Register Reise oma Description Resevaue 2 2 Monitor Channel Receive Data 0x00000000 7 0 MRxD This field includes the data received on the monitor channel selected by MSEL if MEN 1 This data is sure to be valid by double last look criterion valid during two successive frames 31 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 121110 9 8 7 6 5 4 32 1 0 7 0 Monitor Chan
206. cmmuooci oOm3Jouocio 0 USB Out Packet Ready 0 Not received data packet 1 Revceived packet from host 1 USB FIFO Full 0 Normal operation 1 FIFO full state 2 USB Over Run 0 Normal operation 1 Data received at FIFO full state ISO 3 USB Data Error 0 Normal operation 1 Data error ISO 4 USB FIFO Flush 0 No operation 1 FIFO flush 5 USB Send STALL 0 No operation 1 Stall handshake transmit state 6 USB Sent STALL 0 No operation 1 Stall handshake transmitted 7 USB Clear Data Toggle 0 No operation 1 Data toggle flag set to 0 31 8 Reserved Figure 11 19 USBOCSR 1 Register ELECTRONICS 11 41 USB 3C4520A RISC MICROCONTROLLER 7 5 T L K 5 0 Reserved 6 USB ISO Mode 0 Bulk Interrupt mode 1 ISO mode 7 USB Auto Clear 0 No operation 1 Auto clearing USBORDY bit when data in FIFO unloaded 31 8 Reserved Figure 11 20 USBOCSR2 Register 11 42 ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB OUT WRITE COUNT REGISTER 1 2 There are two register USBOWCRL and USBOWCRH which maintain the write count USBOWCRL maintains the lower bytes while USBOWCRH maintains the higher byte When USBORDY is set for OUT endpoints these registers maintain the number of bytes in the packet due to be unloaded by the MCU Table 11 31 USB Out Write Count register 1 2 USBOWCL 0x58 USB Out Write Count register Lower b
207. ction 2 The condition codes are unaffected by the format 5 version of this instruction 3 66 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 1 MOVE SHIFTED REGISTER 15 10 6 5 3 2 0 14 13 12 11 ote nm 2 0 Destination Register 5 3 Source Register 10 6 Immediate Vale 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 3 30 Format 1 OPERATION These instructions move a shifted value between Lo registers The THUMB assembler syntax is shown in Table 3 8 NOTE All instructions in this group set the CPSR condition codes Table 3 8 Summary of Format 1 Instructions OP THUMB Assembler ARM Equivalent Actiom LSL Rd Rs Offset5 MOVS Rd Rs LSL Offset5 Shift Rs left by a 5 bit immediate value and store the result in Rd 01 LSR Rd Rs Offsets MOVS Rd Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store the result in Rd 10 ASR Rd Rs ZOffset5 MOVS Rd Rs ASR 5 Perform arithmetic shift right on Rs by a 5 bit immediate value and store the result in Rd INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Setcondition cod
208. d 1 2 1 0111 RSC Rd 2 1 1 1000 TST set condition codes AND 1001 TEO set condition codes 1010 CMP set condition codes on 1 2 1011 SMN set condition codes on 1 2 1100 ORR Rd Op1 OR Op2 1101 MOV Rd OP2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd 25 Immediate operand 0 Operand 2 is a register 1 Operand 2 is an immediate Value 11 0 Operand 2 Type selection 11 3 4 0 3 0 2nd Operand Register 11 4 Shift applied to Rm 11 8 7 0 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition field Figure 3 4 Data Processing Instructions ELECTRONICS 3 9 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands The first operand is always a register Rn The second operand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in
209. d When the JTAG mechanism is not active the signal level at this pin must be driven Low TMS 41 JTAG Test Mode Select This pin controls JTAG test operations in the S3C4520A This pin should not be left unconnected When the JTAG mechanism is not active the signal level at this pin must be driven High JTAG Test Data In The TDI level is used to serially shift test data and instructions into the 53 4520 during JTAG test operations This pin should not be left unconnected When the JTAG mechanism is not active the level of this pin must be driven High JTAG Test Data Out The TDO level is used to serially shift test data and instructions out of the 53 4520 during JTAG test operations JTAG Not Reset Asyncronous reset of the JTAG logic Address Bus The 22 bit address bus ADDR 21 0 covers the full 8 ADDR 21 0 M word address range of each ROM SRAM flash memory and ADDR 10 AP DRAM and the external I O banks The 25 bit internal address bus used to generate DRAM address The number of column address bits in DRAM bank can be programmed 8bit to 11bits use by DRAMCON registers ADDR 10J AP is the auto precharge control pin The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR 10 AP XDATA 15 0 External bi directional 16 bit Data Bus The S8C4520A data bus supports external 8 bit and 16 bit bus sizes 1 Not Row Address Strobe for DRAM The S3C4520A supports up to
210. d eues Data Bus Arbiter Controller Receive shift Register Rx FIFO dplloutR DPLL 8 words dplloutT brgout1 Address brgout2 BRG Figure 6 1 HDLC Module Block Diagram ELECTRONICS 6 3 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC FRAME FORMAT The HDLC transmits and receives data address control information and CRC field in a standard format called a frame All frames start with an opening flag beginning of flag BOF 7EH and end with a closing flag end of flag EOF 7EH Between the opening and the closing flags a frame contains an address A field a control C field an information field optional and a frame check sequence FCS field see Table 6 1 Table 6 1 HDLC Data Frame Format Opening Address Control Information Frame Check Closing Flag Field Field Field Sequence Field Flag 01111110 8 bits per byte 8 bits per byte 8 bits per byte 16 bits 01111110 variable length NOTE The address field can be extended up to four bytes using a optional software control setting Flag F A flag is a unique binary pattern 01111110 that is used to delimit HDLC frames This pattern is generated internally by the transmitter An opening flag starts a frame and a closing flag ends the frame Opening flags and closing flags are automatically appended to frames A single flag pattern can optionally serve as both the closing flag of one frame and the opening flag of the next one Th
211. d abcd Bit Num 31 0 31 0 31 0 CPU Data Bus cdcd cdcd cdcd Bit Num 31 0 31 0 31 0 Internal SD Bus cdcd cdcd cdcd CAS1 0 nWBE1 0 0 nWBE1 0 XX00 XXX0 ELTE ji 2 Bit Num Ext Memory Data Timing Sequence Pene 2ndwrite write Table 4 6 Half Word Access Load Operation with Big Endian LOAD CPU Reg lt External Memory Ext Memory Type Half word Bit Num 15 0 15 0 CPU Register Data ab ab Bit Num 31 0 31 0 31 0 CPU Data Bus abab 31 0 31 0 31 0 Internal SD Bus abab CAS1 0 nWBE1 0 0 nWBE1 0 SSS Y Ext Memory Data Timing Sequence _ 2ndread read 4 10 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER Table 4 7 and 4 8 Using big endian and byte access Program Data path between register and external memory BA Address whose is 00 1 2 3 4 5 6 7 8 9 A B C D E F X Don t care BAL Address whose LSB is 0 2 4 6 8 BAU Address whose LBS is 1 3 5 7 9 B D F 0 0 means active 1 means inactive Table 4 7 Byte Access Store Operation with Big Endian STORE CPU Reg External Memory Ext Memory Type Half Word Bit Num 31 0 31 0 CPU Register Data abcd abcd Bit Num 31 0 31 0 CPU Data Bus dddd dddd Bit Num 31 0 31 0 31 0 Internal SD Bus dddd dddd dddd CAS1 0 nWBE1 0 XX10 XX01 XXX0 Bit Num XD
212. d accumulate 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from RdHi The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to RdHi The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write two s complement signed 64 bit result OPERAND RESTRICTIONS e R15 must not be used as an operand or as a destination register RdLo and Rm must all specify different registers ELECTRONICS 3 25 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N
213. d destination data0 source address1 and source data1 destination address1 and destination data1 gt four data burst source addressO and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination addressO and destination data0 destination address1 and destination data1 destination address2 and destination data2 destination address2 and destination data2 destination address3 and destination data3 gt gt NOTE In the four data burst mode GDMA COUNT Register value decreases by 1 after 4 data transfer 9 18 ELECTRONICS 53 4520 RISC MICROCONTROLLER DMA CONTROLLER DEMAND AND ONE DATA BURST MODE GDMACON 15 1 9 0 DREQ and DACK signals are active low 0 S is source address D is destination address If GDMA CNT is zero GDMAC do not transfer data although DREQ signal asserted Figure 9 14 Demand and One Data Burst Mode Timing DEMAND amp FOUR DATA BURST MODE GDMACON 15 1 9 1 This timing diagram is the same with Demand amp one data burst exception four data burst one data burst source addressO and source data0 destination addressO and destination data0 four data burst source addressO and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination addressO and destination dat
214. data shift to FIFO top then UART generates interrupt Transfer unit is byte same as at Tx block FIFO Operation Tx FIFO operation If there is no valid data on trigger level of TX FIFO UART generates Interrupt INT TXD or sends a request signal to GDMA During this operation trigger level should be 33 32 empty depth FIFO depth 24 32 16 32 or 8 32 CPU or GDMA fills data into TX FIFO by byte Rx FIFO Operation If received data are filled up to RX FIFO trigger level UART generate interrupt INT RXD or send request signal to GDMA The size of transferred data is 1 byte If RX data contains error in case of GDMA mode operation UART generates interrupt instead of sending request signal to GDMA Then CPU executes interrupt service routine for error data So GDMA transmits error free valid data only from received data Hardware Flow Control Hardware flow control for Transmit operation When CTS signal is asserted during Transmit operation UART transmits TX DATA to UATxDn line normally When CTS signal is deasserted during Transmit operation If CTS signal is deasserted when UART transmits TX DATA to TXD line UART stops data transmission immediately In this case transmitting TX data will be lost Hardware flow control for receive operation In the hardware flow control during UART receive data from UARxDn UADCDn level have to be low If UACDn level goes high received data will be pull up by UART Rx block
215. dding RO to R3 LDSB R2 R7 R1 Loadinto R2 the sign extended byte found the address formed by adding R1 to R7 LDSH R3 R4 R2 Loadinto R3 the sign extended halfword found the address formed by adding R2 to 3 80 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 10 6 5 3 2 0 14 ome 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transfer word quantity 1 Transfer byte quantity Figure 3 38 Format 9 OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 3 16 Table 3 16 Summary of Format 9 Instructions STR Rd Rb lmm STR Rd Rb Zlmm Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address LDR Rd Rb LDR Rd Rb Calculate the source address by adding together the value in Rb and Imm Load Rd from the address STRB Rd Rb Imm STRB Rd Rb lmm Calculate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address LDRB Rd Rb Imm LDRB Rb Calculate source address by adding together the value in Rb and Imm Load the by
216. ddress bus An important feature of the ARM7TDMI processor that makes itself distinct from the ARM7 processor is a unique architectural strategy called THUMB The THUMB strategy is an extension of the basic ARM architecture consisting of 36 instruction formats These formats are based on the standard 32 bit ARM instruction set while having been re coded using 16 bit wide opcodes As THUMB instructions are one half the bit width of normal ARM instructions they produce very high density codes When a THUMB instruction is executed its 16 bit opcode is decoded by the processor into its equivalent instruction in the standard ARM instruction set The ARM core then processes the 16 bit instruction as it would a normal 32 bit instruction In other words the THUMB architecture gives 16 bit systems a way to access the 32 bit performance of the ARM core without requiring the full overhead of 32 bit processing As the ARM7TDMI core can execute both standard 32 bit ARM instructions and 16 bit THUMB instructions it allows you to mix the routines of THUMB instructions and ARM code in the same address space In this way you can adjust code size and performance routine by routine to find the best programming solution for a specific application Address Register Address Incrementer Instruction Register Bank Decoder and Logic Controll Multiplier Barrel Shifter 32 BIT ALU Instruction Pipeline and Read Write Data Data Register Register
217. decremented 1 or incremented 0 during a DMA operation 9 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER DMA CONTROLLER Table 9 3 GDMA Control Register Description Continued Bit Number Reset Value Destination address fix Source address fix Stop interrupt enable Four data burst enable Peripheral transfer direction Single Block mode 13 12 Transfer width 14 Continuous mode up ELECTRONICS This bit determines whether or not the destination address will be changed during a DMA operation You use this feature when transferring data from multiple sources to a single destination This bit determines whether or not the source address will be changed during a DMA operation You use this feature when transferring data from a single source to multiple destinations To start stop a DMA operation you set clear the run enable bit If the stop interrupt enable bit is 1 when starts a stop interrupt is generated when DMA operation stops If this bit is 0 the stop interrupt is not generated If this bit is set to one GDMA operates under 4 data burst mode Under the 4 data burst mode 4 consecutive source addresses are read and then are written to the consecutive destination addresses If 4 data burst mode is set to one transfer count register should be set carefully because the 4 data burst move is executed during decreasing of the transfer count The 4 data burst mode can be used only when
218. dress MUX Output for SDRAM Table 4 26 CAN and Address MUX Output External Address Pins E GEN Timing Column NM 0 address Row A15 A8 address Column A10 AP 7 0 address Row A16 A9 address A7 A0 ER Row x A22 A21 A20 A19 A18 A17 A10 address NOTES 1 21 to AO depends on external bus width In case of x16 memory A 21 0 is half word address 2 A 21 0 consists of Bank Address Valid Row Address Valid Column Address DRAM BANK SPACE The S3C4520A DRAM interface supports two DRAM banks Each bank can have a different configuration You use the DRAM control registers to program the DRAM access cycles and memory bank locations Each DRAM control register has two 5 bit address pointers one base pointer and one next pointer to denote the start and end address of each DRAM bank The 5 bit pointer values are mapped to the address 24 20 This gives each bank address an offset value of 1M bytes 20 bits The next pointer value will be the DRAM bank s end address 1 System Initialization Values When the system is initialized the two DRAM control registers are initialized to 00000000H disabling all external DRAMs ELECTRONICS 4 47 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER MCLKO SDCLK nRAS nSDCS 0 1 CKE nm nCAS1 nSDCAS 0 nWBE 1 0JDOM 1 0 des 50
219. e Overwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved e The base register is restored to its modified value if write back was requested This ensures recoverability in the case where the base register is also in the transfer list and may have been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 1l and LDM PC takes n 1 S 2N 11 incremental cycles where SN and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STM instructions take n 1 S 2N incremental cycles to execute where nis the number of words transferred 3 44 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET ASSEMBLER SYNTAX lt LDM STM gt cond lt FD ED FA EAIIA IB DA DB gt Rn lt Rlist gt where cond Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 If present requests write back W 1 otherwise W 0 If present set S bit
220. e if any function block is a highest priority within Group then it can seize the system bus continuously though other function block request the system bus If SYSCFG 3 set to zero the function blocks in Group B can seize the system bus as the round robin method The relative priority of Group B and Group C is determined more or less in an alternating manner ELECTRONICS 4 15 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER CONTROL REGISTERS SYSTEM CONFIGURATION REGISTER SYSCFG The System Manager has one system configuration register SYSCFG You use SYSCFG settings to control the write buffer enable the cache enable and the stall enable operations All DRAM banks can be configured to SDRAM banks by setting the Synchronous DRAM mode SYSCFG 31 Table 4 16 SYSCFG Register Registers Ofset RW SYSCFG 0x000 System configuration register 0x0000 0000 4 16 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER 0 Stall enable SE Must be set to zero 1 Cache enable CE When set to 1 cache operations are enabled 2 Write buffer enable WE When set to 1 write buffer operations are enabled 3 Fixed Priority FP 0 Round robin 1 Fixed priority within Group 31 Sync DRAM Mode 0 Normal EDO DRAM interface for 2 DRAM banks 1 Sync DRAM interface for 2 DRAM banks Figure 4 5 System Configuration Register 5 Cache Disable Enable To enable or disable the cache you set t
221. e single 32 bit word result back to R3 MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 R4 and place the result in MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and and transfer the result back to R3 ELECTRONICS 3 57 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER UNDEFINED INSTRUCTION The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction format is shown in Figure 3 28 31 28 27 2524 o DI Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 25 11 1N cycles where S are defined as sequential S cycle non sequential N cycle and internal I cycle ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 58 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET EXAMPLES INSTRUCTION SET The following examples show ways in which the basic ARM7
222. e 16 bits preceding the closing flag are regarded as the FCS and checked by hardware and they are transferred to the HRXFIFO Also in no CRC mode without the hardware checking all data bits preceding the closing flag are transferred to the HRXFIFO When the closing flag is sent to the receiver the frame is terminated Whatever data is present in the most significant byte of the receiver the shift register is right justified and transferred to the HRXFIFO The frame boundary pointer which is explained in the HRXFIFO register section is set simultaneously in the HRXFIFO When the last byte of the frame appears at the 1 word or 4 word boundary location of the HRXFIFO depending on the settings of the Rx4WD control bit the frame boundary pointer sets the frame valid status bit if the frame is completed with no error or the RxCRCE status bit if the frame was completed but with a CRC error If the frame reception is completed an RxCRCE interrupt for a frame error or an RxFV interrupt for normal state is generated At this point the CPU can read the Rx remaining bytes RxRB status bits to know how many bytes of this frame still remain in the HRXFIFO When you set the frame discontinue control bit the incoming frame discard control bit to 1 the receiver discards the current frame data without dropping the flag synchronization You can use this feature to ignore a frame with a non matched address 6 16 ELECTRONICS 3C4520A RISC MICROC
223. e ALU the Z flag will be set if and only if the result was zero and the N flag will be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 11 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER SHIFTS When the second operand is specified to be a shifted register the operation of the barrel shifter is controlled by the shift field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may be contained in an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 11 L 6 5 Shift type 6 5 Shift type 00 logical left 01 logical right 00 logical left 01 logical right 10 arithmetic right 11 rotate right 10 arithmetic right 11 rotate right 11 7 Shift amount 11 8 Shift register 5 bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations Instruction Specified Shift Amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left 151 takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant
224. e HPRMB register be sent out by setting the TxPRMB in HCON for the remote DPLL before the data is loaded into the HTxFIFO The length of preamble to be transmitted is determined by TPL bits in HMODE The availability of data in the HTxFIFO is indicated by the HTxFIFO available bit TxFA in HSTAT under the control of the 4 word transfer mode bit Tx4WD in HCON When you select 1 word transfer mode not 4 word select mode one word can be loaded into the HTxFIFO assuming the TxFA bit is set to 1 When you select 4 word transfer mode four successive words can be transferred to the FIFO if the TxFA bit is set to 1 The nCTS clear to send input nRTS request to send and nDCD data carrier detect are provided for a modem or other hardware peripheral interface In auto enable mode nDCD becomes the receiver enable However the receiver enable bit must be set before the nDCD pin is used in this manner The TxFC status bit in HSTAT can cause an interrupt to be generated upon frame completion This bit is set when there is no data in HTxFIFO and when the closing flag or an abort is transmitted 6 14 ELECTRONICS 53 4520 RISC MICROCONTROLLER HDLC CONTROLLERS Transmitter Interrupt Mode The first byte of a frame the address field should be written into the Tx FIFO at the frame continue address Then the transmission of the frame data starts automatically The bytes of the frame continue to be written into the Tx FIF
225. e LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section ENDIANNESS AND BYTE HALFWORD SELECTION Little Endian Configuration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A halfword load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit O of the supplied address is high then the ARM7TDMI will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH rep
226. e Watch Dog Timer using Watch Dog Timer Register WDT If you set WDT 23 RST to 1 when WDT 81 EN is 1 internal Watch Dog Timer Counter is cleared as 0 Right after WDT 23 RST is automatically cleared as 0 at the next cycle You can set Watch Dog Timer Timeout Value WDTVAL as shown in Table 4 19 If you set two or more bits of WDTVAL the lowest significant bit of those let the watch dog timer time out Table 4 19 WDT Register Registers RW Description ResetValue 0x00C R W Watch Dog Timer Register 0x0000 0000 31 30 29 24 23 22 16 15 0 R Watch Dog Timer Timeout Value WDTVAL 15 0 Wath Dog Timer Timeout Value WDTVAL 23 Watch Dog Timer Counter Reset RST When set 1 Watch Dog Timer Counter is reset 30 Watch Dog Timer Mode M 0 Interrupt Mode 1 Reset Mode 31 Watch Dog Timer Enable EN 0 Disable 1 Enable Figure 4 8 Watch Dog Timer Register WDT 4 20 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER Table 4 20 Watch Dog Timer Timeout Value WDTVAL X Don t Care 15 a 2 countivx20ns 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010 mNooOpraon 22199 1 0 25059 EX X X XIX X X X X x x x 0 0 1 o o o o EX X X XIX X X X X x 1 0 o o
227. e due to error retrying of the attempt to deliver the data While the USB isochronous transfer type is designed to support isochronous sources and destinations it is not required that software using this transfer type actually be isochronous in order to use the transfer type An isochronous pipe is a stream pipe and is therefore always uni directional An endpoint description identifies whether a given isochronous pipe s communication flow is into or out of the host If a device requires bi directional isochronous communication flow two isochronous pipes must be used one in each direction INTERRUPT TRANSACTIONS The interrupt transfer type is designed to support those devices that need to send or receive small amounts of data infrequently but with bounded service periods Requesting a pipe with an interrupt transfer type provides the requester with the following Guaranteed maximum service period for the pipe Retry of transfer attempts at the next period in the case of occasional delivery failure due to error on the bus An interrupt pipe is a stream pipe and is therefore always uni directional An endpoint description identifies whether a given interrupt pipe s communication flow is into or out of the host 11 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB 3C4520A USB BLOCK OVERVIEW USB block in S3C4520A is compatible with USB spec 1 1 6 EP Endpoint s with EPO for control transfer This block uses
228. e han een 1 22 EXCODLUOTIIS E MEL 1 23 Special Registers Ne 1 24 Chapter 2 Programmer s Model ONG INNS WS 2 1 SWICHING State ut A 2 1 Big Endian Formal fait d 2 2 Little Endian Format 2 2 Instructiombengthiss 26844 2 3 Operating E a 2 3 atele DL 2 4 The Program State ROOS OS 2 8 EXCOPUOMS c 2 11 53 4520 RISC MICROCONTROLLER Chapter 3 Instruction Set Instruction Set 3 1 Format Summary 3 1 Instruction A aaa aaa aaa aaiae i 3 2 The Condition Field Ld Rien eate bel 3 4 Branch and Exchange 9 3 5 Instruction Cycle Times 3 5 Assembler Syntax 3 5 Using R15 As 3 5 Branch and Branch With Link B 3 7 MAC EINK Bites Nae x Dec 3 7 Instruction Cycle Times
229. e number DREQ signal pulse But recommand that DREQ sigan is deasserted when DACK signal is active state Figure 9 12 Block and One Data Burst Mode Timing BLOCK AND FOUR DATA BURST GDMACON 1 1 1 9 1 This timing diagram is the same with Single and one data burst exception four data burst one data burst source addressO and source data0 destination addressO and destination data0 four data burst source addressO and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination addressO and destination data0 destination address1 and destination data1 destination address2 and destination data2 gt destination address3 and destination data3 source address4 and source data4 gt gt NOTE In the four data burst mode GDMA COUNT Register value decreases by 1 after 4 data transfer ELECTRONICS 9 17 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER CONTINUOUS AND ONE BURST MODE GDMACON 14 1 9 0 DREQ and DACK signals are active low Recommand time In_MCLK nxDREQ nxDACK S is source address and D is destination address Figure 9 13 Continuous and One Burst Mode Timing CONTINUOUS AND FOUR DATA BURST MODE GDMACON 14 1 9 1 This timing diagram is the same with Continuous and one data burst exception four data burst one data burst source addressO and source data0 destination addressO an
230. e when an exception occurs it will automatically switch into ARM state when the PC is loaded with the exception vector address Action on Leaving an Exception On completion the exception handler 1 Moves the link register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTE An explicit switch back to THUMB state is never needed since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception ELECTRONICS 2 11 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER Exception Entry Exit Summary Table 2 2 summarizes the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14 x MOV PC R14 MOVS PC R14 svc MOVS PC R14 und SUBS R14 fiq 4 SUBS PC R14 irq 4 SUBS PC R14_abt 4 SUBS PC R14_abt 8 NA 1 4 4 2 2 1 3 4 NOTES 1 Where PC is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority 3 Where PC is the address of the Load or Store instruction which generated the data abort 4 The value saved in
231. eats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit 0 of the address is high this will cause unpredictable behaviour 3 36 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET Big Endian Configuration A signed byte load LDRSB expects data on data bus inputs 31 through to 24 if the supplied address is word boundary on data bus inputs 23 through to 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A halfword load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary A 1 1 The supplied address should always be halfword boundary If bit 0 of the supplied address is high then the ARM7TDMI will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repe
232. eceives reset signaling The USB set this bit when it finishes disconnect operation USB ReSeT R Clear Interrupt USBRSTI USB DisConnect R Clear Interrupt USB ResUme R Clear The USB sets this bit when it receive resume signaling Interrupt while in suspend mode USBRUI If the resume is due to a USB reset then the MCU is first interrupted with a Resume Interrupt Once the clocks resume and the SEO condition persists for 3ms USB RESET interrupt will be asserted ELECTRONICS 11 17 USB 11 18 53 4520 RISC MICROCONTROLLER i 00u0oc v 0 USB Suspend Interrupt USBSI 0 No suspend interrupt 1 Suspend interrupt generated 1 USB ResUme Interrupt USBRUI 0 No resume interrupt 1 Resume interrupt generated 2 USB ReSeT Interrupt USBRSTI 0 No reset interrupt 1 Reset interrupt generated 3 USB Disconnect Interrupt USBDIS 0 No reset interrupt 1 Disconnect interrupt generated 31 3 Reserved Figure 11 9 USBINT Register ELECTRONICS 3C4520A RISC MICROCONTROLLER USB ENDPOINT INTERRUPT ENABLE REGISTER Corresponding to each USB Endpoint Interrupt Register Bank USBEPINT there is an interrupt enable bit at USB In Interrupt Enable Register Bank USBEPINTE By default all interrupts are enabled Table 11 10 USB EndPoint INTerrupt Enable register USBEPINTE USB EndPoint INTerrupt Enable register Table 11 11 USBEPINTE Description USB Endpoint R W If
233. ed when a receive event time out is detected and valid data reside in URXBUF or Receive FIFO You can clear this bit by writing 1 to this bit NOTE Event time WL 4 12 This bit set to one when the Rx data resides in RxFIFO 13 Not applicable 14 Data Set ready DSR This bit is only for CPU to monitor UART When nUADSR level is low this bit is set And nUADSR high this bit is cleared 15 Clear To Send CTS This bit is only for CPU to monitor UART When nUACTS level is low this bit is set And nUACTS high this bit is cleared 16 CTS Event occurred This bit is set to 1 whenever nUCTS level changed E CTS If the E CTS interrupt enable bit UINTEN 16 is 1 a interrupt is generated when a CTS event is occurred You can clear this bit by writing 1 to this bit 17 Transmit Complete TC This bit is only for CPU to monitor UART USTAT 17 is automatically set to 1 when the transmit holding register has no valid data to transmit and when the Tx shift register is empty After Reset Default value is 1 18 Transmit Holding In Transmit FIFO mode when Transmit FIFO is empty to trigger Register Empty THE level this bit set to 1 In non FIFO mode when UTXBUF is empty without regarding Tx shift register this bit set to 1 An interrupt DMA request is generated when USTAT 18 is 1 In case of UCON 1 0 01 and UINTEN 18 1 an interrupt requested and UCON 1 0 10 11 DMA request occurred
234. egister 10 Sign Extended Flag 0 Operand sign extended 1 Operand sign extended 11 H Flag Figure 3 37 Format 8 OPERATION These instructions load optionally sign extended bytes or halfwords and store halfwords The THUMB assembler syntax is shown below Table 3 15 Summary of format 8 instructions S H THUMB Assembler ARM Equivalent Acton O Rb STRH Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rb Ro LDRH Rb Ro Load halfword Add to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 LDSB Rd Rb Ro LDRSB Rd Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rb LDRSH Rb Ro Load sign extended halfword Add to base address in Rb Load bits 0 15 Rd from the resulting address and set bits 16 31 of Rd to bit 15 ELECTRONICS 3 79 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R3 RO Store the lower 16 bits of R4 at the address formed by a
235. egister Operations Branch 3 73 Operation NK MI xc 3 73 Instruction Cycle Times 3 74 5 a a a 3 74 Using R15 As An 3 75 Format 6 PC Relative Load 3 76 Operation 3 76 Instruction Cycle Times 3 76 Format 7 Load Store With Register 3 77 Operati c 3 77 Instruction Cycle Times 3 78 Format 8 Load Store Sign Extended 3 79 Operation oe D LAS ex Se Sean 3 79 Instruction Cycle Times 3 80 vi 53 4520 RISC MICROCONTROLLER Table of Contents Continued Chapter 3 Instruction Set Continued Format 9 Load Store With Immediate Offset 3 81 A cer ae eee 3 81 Instruction Cycle 9 3 82 Format 10 Load Store 3 83 ss EA E AL AAA AU M feeit 3 83 Instruction Cycle 0020100
236. el status condition depends on the bit s function and operation mode For details please see the description of each status register Table 6 11 HSTATA HSTATB and HSTATC Register Registers onst RW Description Resetvaue HSTATA 0x708 R W HDLC Channel A Status Register 0X00001040 HSTATB 0x808 R W HDLC Channel B Status Register 0X00001040 HSTATC 0x908 R W HDLC Channel C Status Register 0X00001040 SUMMARY There are two kinds of bits in a status register 1 TxFA TxCTS RxFA RxDCD RxFV RxCRCE RxNO RxIERR and RxOV bits are show each bit s status These bits are set or cleared automatically according to the each bit status 2 All other bits are cleared by the CPU writing 1 to each bit 6 32 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS Table 6 12 HSTAT Register Description Bit Bit Name Description Number 3 0 Rx remaining bytes RxRB 1 indicates how many data bytes are valid in a 1 word or 4 word RxRB boundary when the receiver has received a complete frame In 1 word transfer mode the RxRB value is either 0 1 2 or 3 In 4 word mode it is 0 1 14 or 15 5 4 Tx frame complete This status bit is automatically set to 1 when the two conditions are met 1 there is no data the Tx FIFO 2 either an abort a closing flag is transmitted You can clear this bit by writing 1 to this bit Tx FIFO available If this bit is 1 the data to be sent can
237. ent notation For example ASR 5 is shown in Figure 3 8 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 32 Bit 31 of Rm is again used as the carry output and each bit of operand 2 is also equal to bit 31 of Rm The result is therefore all ones or all zeros according to the value of bit 31 of Rm ELECTRONICS 3 13 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER Rotate right ROR operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example ROR 5 is shown in Figure 3 9 The form of the shift field which might be expected to give ROR 0 is 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 Contents of Rm in Value Operand 2 Figure 3 10 Rotate Right Extended carry out 3 14 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs i
238. equest is pending If the pending bit is set the interrupt pending status is maintained until the CPU clears it by writing a 1 to the appropriate pending register When the pending bit is set the interrupt service routine starts whenever the interrupt mask register is 0 The service routine must clear the pending condition by writing 1 to the appropriate pending bit This avoids the possibility of continuous interrupt requests from the same interrupt pending bit nterrupt mask register Indicates that the current interrupt has been disabled if the corresponding mask bit is 1 If an interrupt mask bit is 0 the interrupt will be serviced normally If the global mask bit bit 23 is set to 1 no interrupts are serviced However the source s pending bit is set if the interrupt is generated When the global mask bit has been set to 0 the interrupt is serviced ELECTRONICS 14 1 INTERRUPT CONTROLLER 3C4520A RISC MICROCONTROLLER INTERRUPT SOURCES The 23 interrupt sources in the S3C4520A interrupt structure are listed in brief as follows Table 14 1 53 4520 Interrupt Sources 7 D 5 i S 2 D 14 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS INTERRUPT MODE REGISTER Bit settings in the interrupt mode register INTMOD specify if an interrupt is to be serviced as a fast interrupt FIQ or a normal interrupt IRQ Table 14 2 INTMOD Regis
239. erator pp 6 7 Digital Phase Locked Loop DPLL 6 9 Clock Usage Method ERR 6 9 HDLC Operational Description 6 11 HDLC 6 11 HDLC Data 6 12 HDLC Data Setup Hold Timing With 6 13 HDLC Transmitter Operation 6 14 HDLC Receiver 6 16 Transparent Operation 6 17 Hardware Flow Control 6 18 HDLC Special Registers pt 6 20 HDLC Global Mode Register 6 23 HDLC Control Register 6 26 HDLC Status Register 6 32 Rt Exc 6 32 HDLC Interrupt Enable Register HINTEN 6 37 HDLC bc RlEO AITXEIFO mc EM 6 39 HDLC Rx FIFO 6 40 HDLC BRG Time Constant Registers 0002 0000 nennen 6 41 HDLC Preamble Constant Register 6 42 HDLC Station Address Registers HSADRO 3 HMASK Register 6 43 Received Byte Count Register 6 45 HDLC Synchronization Register 6 46 Chapter 7 IOM2 Controller CAIUS 7 1 BUS E 7 2 Channel 7 4 Pin Direction Heversal
240. error then this bit gets set only after the first packet is unloaded This is automatically cleared when USBORDY gets cleared USB Fifo FLUSH The MCU writes a 1 to flush the FIFO USBFFLUSH This bit can be set only when USBORDY is set The packet due to be unloaded by the MCU will be flushed The MCU writes a 1 to this bit to issue a STALL STALL handshake to the USB The MCU clears this bit to end USBSDSTALL the STALL condition USB SenT Clear R The USB sets this bit when an OUT token is ended with a STALL STALL handshake The USB issues a stall handshake to USB SenD USBSTSTALL the host if it sends more than MAXP data for the OUT USB CLear data When the MCU writes a 1 to this bit the data toggle TOGgle sequence bit is reset to DATAO USBCLTOG ELECTRONICS 11 39 USB 3C4520A RISC MICROCONTROLLER Table 11 30 USBOCSR2 Description L USB ISO mode This bit is used only for endpoints whose transfer type is USBISO programmable i e TYPE ISO BULK If this bit 1 then endpoint will be ISO mode If this bit 0 then endpoint will be Bulk mode Default 0 USB AUTO Clear If set whenever the MCU reads data from the OUT FIFO USBATCLR USBORDY will automatically be cleared by the core without any intervention form MCU Default 0 11 40 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB rr 0 4o0uU0ocio rr o0ggo0uUocjo r or cmmuoc lt rr
241. es on the result ELECTRONICS 3 67 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 2 ADD SUBTRACT 15 14 13 12 11 10 9 8 6 5 3 2 0 hm 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Vale 9 Opcode 0 ADD 1 SUB 10 Immediate Flag 0 Register operand 1 Immediate oerand Figure 3 31 Format 2 OPERATION These instructions allow the contents of a Lo register or a 3 bit immediate value to be added to or subtracted from a Lo register The THUMB assembler syntax is shown in Table 3 9 NOTE All instructions in this group set the CPSR condition codes Table 3 9 Summary of Format 2 Instructions OP 1 THUMB Assembler ARM Equivalent Action ADD Rs Rn ADDS Rs Rn Add contents of Rn to contents of Rs Place result in Rd 1 ADD Rd Rs Offset3 ADDS Rd Rs Offset8 Add 3 bit immediate value to contents of Rs Place result in Rd 1 SUB Rs Rn SUBS Rs Rn Subtract contents of Rn from contents of Rs Place result in Rd 1 1 SUB Rd Rs Offset3 SUBS Rd Rs 4Offset3 Subtract 3 bit immediate value from contents of Rs Place result in Rd 3 68 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 9 The instruction cycle times for the THUMB instruction are identical to that of the e
242. eset value will be used as control character For example even if you want to use one control character all control characters will have same value with it Table 10 15 CONCHAR2 Registers CONCHAR2 OxE1C UART control character2 register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 CONCHAR7 CONCHAR6 5 7 0 Control Character 4 15 8 Control Character 5 23 16 Control Character 6 31 24 Control Character 7 Figure 10 10 UART Control Character 2 Register ELECTRONICS 10 21 UART 3C4520A RISC MICROCONTROLLER UART OPERATION Data Transmit Operation Flow If there is no data at Tx Buffer FIFO of UART in case of FIFO if data in the Tx FIFO are empty as same amount of trigger level UART generates interrupt or GDMA request signal It depends on UART mode CPU or software or GDMA controller will read data from memory where UART transmit data are stored and send them to Tx Buffer FIFO Transfer unit is byte When data come from UARTxDn data are stored to Rx Buffer FIFO via shift register If valid Rx data are received UART generates interrupt request signal Similar to Tx Block in case of FIFO it is same as Tx block Data should be stored as the same level of trigger level If there is an error on Rx data UART does not generate request signal but generates interrupt even in case of mode Although UART is FIFO mode if error
243. ess of the external I O bank 2 is the start address of the external I O bank 0 512KB and the start address of the external I O bank 3 is the start address of the external I O bank 0 768KB Therefore the total consecutive addressable space of the four external I O banks is defined as the start address of the external I O bank 0 1024 Within the addressable space the start address of each bank is not fixed You can use bank control registers to assign a specific bank start address by setting the bank s base pointer The address resolution is 1M bytes The banks start address is defined as base pointer lt lt 20 and the bank s end address except for external I O banks is next pointer lt lt 20 1 After a power on or system reset all bank address pointer registers are initialized to their default values In this case all bank pointers except for the next pointer of ROM SRAM Flash bank 0 and the base pointer of external banks are set to zero This means that except for ROM SRAM Flash bank 0 and external I O banks all banks are undefined following a system startup The reset values for the next pointer and the base pointer of ROM SRAM Flash bank 0 are 0x10 and 0x00 respectively This means that a system reset automatically defines ROM SRAM Flash bank 0 as a 16 Mbyte space with a start address of zero This initial definition of ROM SRAM Flash bank 0 lets the system power on or reset operation pass control to the user
244. essors take advantage of unified instruction data caches to improve performance Without an instruction cache bottlenecks that occur during instruction fetches from external memory may seriously degrade performance CACHE CONFIGURATION The S3C4520A s 4 Kbyte two way set associative instruction data cache uses a 14 bit tag address for each set The CS bits a 2 bit value in tag memory stores information for cache replacement When a reset occurs the CS value is 00 indicating that the contents of cache set 0 and cache set 1 are invalid When the first cache fill operation occurs while exiting from the reset operation the CS value becomes 01 at the specified line to indicate that only set 0 is valid When the subsequent cache fill occurs the CS value becomes 11 at the specified line indicating that the contents of both set 0 and set 1 are valid ELECTRONICS 5 1 UNIFIED INSTRUCTION DATA CACHE 3C4520A RISC MICROCONTROLLER Enable non cacheable control 28 26 24 23 eme 100 Set 0 direct access 101 Set 1 direct access 110 TAG direct access Height 128 Tag RAM 82 bit Set 1 cache line 4 instruction data 128 bit Set 0 cache line 4 instruction data 128 bit CL dL LL L C Set 0 Hit Set 1 Hit Figure 5 1 Memory Configuration for 4 Kbyte Cache 5 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER UNIFIED INSTRUCTION DATA CACHE CACHE REPLACE OPERATIONS When the contents of two
245. ev 0 0 MinRev 0 7 4 Major Revision Number MajRev 0x0 MajRev 0 31 16 Product Code PC 0x4520 53 4520 Figure 4 6 Product Code and Revision Number Register PROREV 4 18 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER PERIPHERAL amp SDRAM CLOCK ENABLE REGISTER CER You can reduce power dissipation when you don t use any function block using this Peripheral amp SDRAM Clock Enable Register CER You can disable sixteen peripheral clocks by writing 0 0000 to CER 15 0 For the low power operation of SDRAM you can disable SDRAM Clock Enable Pin pin 57 by writing 1 to CER 31 Table 4 18 CER Register CER 0x008 R W Peripheral amp SDRAM Clock Enable 0x0000_FFFF Register 1 30 16 15 0 15 0 Clock Enable of Each Peripheral Each bit can control the following peripheral clock When set to 1 the each peripheral clock is enabled 0 Port Controller 1 Timer 0 2 Timer 1 3 HDLC Channel A 4 HDLC Channel B 5 HDLC Channel C 6 1 2 7 GDMA 0 8 GDMA 1 9 GDMA 2 10 GDMA 3 11 GDMA 4 12 GDMA 5 13 UART 14 USB 15 TSA 31 SDRAM Self Refresh SR When set to 1 SDRAM enter into the self refresh mode The self refresh mode is exited by setting this bit to 0 Figure 4 7 Peripheral amp SDRAM Clock Enable Register CER ELECTRONICS 4 19 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER WATCH DOG TIMER REGISTER WDT You can us
246. exed 10 2 11 highway multiplexed 26 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock pv 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 stop 11 0 The location START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 PCM Highway multiplexed 26 Divide 0 1 x Clock mode 1 0 5 x Clock mode Figure 8 3 TSA B Configuration Register ELECTRONICS 8 5 TSA TIME SLOT ASSIGNER 3C4520A RISC MICROCONTROLLER TSACCFG TSA C Configuration Register Register RW TSACCFG 0xA38 TSA C Configuration Register 0x00000000 11 0 START The location of start bit of time slot assigned to HDLCC 23 12 STOP The location of stop bit of time slot assigned to HDLCC 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 10 2 11 highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock pe 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 pem stop 11 0 The location START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 PCM High
247. f CLKSEL is High XCLK is used as the S3C4520A internal system clock System Clock Out The reverse phase of the internal system clock is monitored from this pin SDCLK is system clock for SDRAM CLKSEL Clock Select When CLKSEL is O low level PLL output clock can be used as the master clock When CLKSEL is 1 high level The XCLK is used as the master clock CLKOEN 49 Clock Out Enable Disable See the pin description for MCLKO 2 50 Test Mode The TMODE bit settings are interpreted as follows TMODE 0 normal operating mode 1 chip test mode This TMODE pin also can be used to change MF of PLL To get 66MHz MCLK internal system clock from 10MHz external input clock 1 high level should be assigned to TMODE and O low level to CLKSEL then MF will be changed to 6 6 LITTLE 51 Little endian mode select pin If LITTLE is High S3C4520A operate in little endian mode If Low then in Big endian mode Default value is low because this pin is pull downed internally FILTER 35 AO If the PLL is used 820pF capacitor should be connected between the pin and analog ground VSS A 1 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 1 S3C4520A Signal Descriptions Continued JTAG Interface Signals TCK 39 JTAG Test Clock The JTAG test clock shifts state information and test data into and out of the S8C4520A during JTAG test operations This pin should not be left unconnecte
248. f Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute where S and N are defined as sequential S cycle and non sequential N cycle respectively ASSEMBLER SYNTAX BX branch and exchange BX cond Rn cond Two character condition mnemonic See Table 3 2 Rn is an expression evaluating to a valid register number USING R15 AS AN OPERAND If R15 is used as an operand the behaviour is undefined ELECTRONICS 3 5 INSTRUCTION SET Examples 3 6 ADR RO Into_THUMB 1 BX RO CODE16 Into_THUMB ADR R5 Back to ARM BX R5 ALIGN CODE32 Back to 53 4520 RISC MICROCONTROLLER Generate branch target address and set bit 0 high hence arrive in THUMB state Branch and change to THUMB state Assemble subsequent code as THUNB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state Branch and change back to ARM state Word align Assemble subsequent code as ARM instructions ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instruction encoding is shown in Figure 3 3 below 31 28 27 25 24 23 0 E
249. ffset after transfer 1 Pre add offset bofore transfer 25 Immediate Offset 0 Offset is an immediate value 0 Offset 0 11 0 Unsigned 12 bit immediate offset 11 4 3 0 3 0 Offset register 11 4 Shift applied to 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 28 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET OFFSETS AND AUTO INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction or a second register possibly shifted in some way The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base value may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed data transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory man
250. flag bits only lt psrf gt lt expression gt The expression should symbolise a 32 bit value of which the most significant four bits are written to the N Z C and V flags respectively Key cond Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 lt psr gt CPSR CPSR all SPSR or SPSR all CPSR and CPSR all are synonyms as are SPSR and SPSR all lt psrf gt or SPSR_flg lt expression gt Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error Examples In User mode the instructions behave as follows MSR CPSR all Rm CPSR 81 228 lt Rm 31 28 MSR CPSR flg Rm CPSR 31 28 lt Rm 31 28 MSR CPSR_flg 0xA0000000 CPSR 81 28 lt set C clear Z MRS Rd CPSR Rd 81 0 lt CPSR 81 0 In privileged modes the instructions behave as follows MSR CPSR all Rm CPSR 31 0 lt Rm 31 0 MSR CPSR flg Rm CPSR 31 28 lt Rm 31 28 MSR CPSR_flg 0x50000000 CPSR 31 28 lt 0x5 set Z V clear C MSR SPSR all Rm SPSR_ lt mode gt 31 0 lt Rm 31 0 MSR SPSR flg Rm SPSR mode 31 28 lt Rm 31 28 MSR flg 420xC0000000 SPSR_ lt mode gt 31 28 lt OxC set Z clear C V MRS Rd SPSR Rd 31 0 lt SPSR mode 31 0 3 22 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTI
251. for two Timers 6 for six GDMAs 2 for one UART 4 external interrupt request 1 for USB 1 for WatchDog Timer and 1 for IOM 2 e Normal or fast interrupt mode IRQ FIQ e Prioritized interrupt handling 16 bit Watchdog Timer e Useful for periodic reset or interrupts Programmable I O Ports e 38 programmable MO ports e individually configurable to input output or mode for dedicated signals e 4external interrupt request input with 3 tap filtering PLLO for system clock e The external clock can be multiplied by on chip PLL to provide high frequency system clock e The input frequency range is 10 40MHz e The output frequency is 5 times of input clock To get 50MHz input clock frequency should be 10MHz PLL1 for USB e The external clock can be multiplied by on chip PLL to provide high frequency USB clock e The input frequency range is 10 40MHz e The output frequency is 4 8 times of input clock To get 48 MHz input clock frequency should be 10 MHz Package Type e 144 LQFP Operating Voltage Range 33V 5 5 V tolerant I O 3 3 V output levels Operating Frequency e Up to 50 MHz 1 3 PRODUCT OVERVIEW 4 Ext INT Req 6 Ext GDMA Req 6 Ext GDMA Ack Timer 0 Output Timer 1 Output XCLK MCLKO CLKSEL FILTER 1 4 53 4520 RISC MICROCONTROLLER ARM7TDMI ICE 32 bit RISC CPU Breaker TAP Controller for JTAG CPU Interface 32 bit System Bus 4 Kbyte Memory Unified Cont
252. from that time 10 22 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART 4 Data Size Start Bit Figure 10 11 When Signal is Asserted During Transmit Operation Data Region Start Bit Stop Bit Figure 10 12 When CTS Signal is Deasserted During Transmit Operation ELECTRONICS 10 23 UART 3C4520A RISC MICROCONTROLLER Data Region Start Bit Figure 10 13 Normal Received Rx Data 4 Data Region Start Bit Stop Bit CD Internal RXD Start Bit Figure 10 14 CD Lost During Rx Data Receive Software Flow Control Software can control UART by control characters UART compares received data with control characters and if they are identical it sets 1 at state bit CCD MSTAT 5 and generates interrupt which masked by Interrupt enable register Auto Baud Rate Detection When Auto Baud Detect bit AUBD UCON 6 is set RX block at UART starts to seek initial low point of RXD It recognize the initial low assert of RXD as a start bit and starts to count It extracts CNTO and CNT1 by counted values When Auto Baud Detect bit AUBD UCON 6 is set block at UART searches the point that level is low And then UART counts low level signal That is start bit by UART clock system clock divided by 2 or external uart clock refer to control register UCLK Finally UART measures and CNT1 from count value 10 24 ELECTRONI
253. ft operation on the 8 bit immediate value This value is zero extended to 32 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 WRITING TO R15 When is a register other than R15 the condition code flags in the CPSR may be updated from the ALU flags as described above When is R15 and the 5 flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When Rad is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state changes which atomically restore both PC and CPSR This form of instruction should not be used in User mode USING R15 AS AN OPERAND If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TEQ TST CMP AND CMN OPCODES NOTE TEQ TST CMP and CMN do not write the result of their operation but do set flags in the CPSR An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic The TEQP form of the T
254. g address into a register The THUMB assembler syntax is shown in the following table Table 3 19 Load Address SP THUMB Assembler Equivalent ADD Rd PC ADD R15 Add to the current value of the program counter PC and load the result into Rd 1 ADD Rd SP lmm ADD R13 Imm Add to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by 1 is full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places Imm gt gt 2 in field Word 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0 The CPSR condition codes are unaffected by these instructions ELECTRONICS 3 85 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 19 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD R2 PC 572 R2 PC 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212 SP R13 212 but don t set the condition codes Note that the THUMB opcode will contain 53 as
255. gister INTMSK contains interrupt mask bits for each interrupt source Table 14 4 INTMSK Register INTMSK 0x408 Interrupt mask register OxOOFFFFFF 31 23 22 2120 19 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 1 INTMSK SEPP ED EDT 22 0 Individual interrupt mask bits NOTE Each ofthe 23 bits in the interrupt mask register INTMSK except for the global mask bit G corresponds to an interrupt source When a source interrupt mask bit is 1 the interrupt is not serviced by the CPU when the corresponding interrupt request is generated If the mask bit is 0 the interrupt is serviced upon request And if global mask bit bit 23 is 1 no interrupts are serviced However the source pending bit is set whenever the interrupt is generated After the global mask bit is cleared the interrupt is serviced The 23 interrupt sources are mapped as follows 22 WatchDog timer 21 Timer 1 interrupt 20 Timer 0 interrupt 19 GDMA channel 5 interrupt 18 GDMA channel 4 interrupt 17 GDMA channel 3 interrupt 16 GDMA channel 2 interrupt 15 GDMA channel 1 interrupt 14 GDMA channel 0 interrupt 13 USB interrupt 12 IOM 2 interrupt 11 HDLC channel C Rx interrupt 10 HDLC channel C Tx interrupt 9 HDLC channel B Rx interrupt 8 HDLC channel B Tx interrupt 7 HDLC channel A Rx interrupt 6 HDLC channel A Tx interrupt 5 UART receive and error interrupt 4 UART transmit interrupt 3 External interrupt 3 2 External interr
256. h s t rt sementem Rege 3 58 3 29 THUMB Instruction Set 3 64 3 30 gelu Mc 3 67 3 31 eet cu IM II M IT 3 68 3 32 EM 3 70 3 33 Formata ete DIN a ness iM CPI 3 71 3 34 PO MIM Ab 3 73 3 35 Formato UI In D IM 3 76 53 4520 RISC MICROCONTROLLER xiii List of Figures Continued Figure Title Page Number Number 3 36 3 77 3 37 3 79 3 38 3 81 3 39 3 83 3 40 3 84 3 41 3 85 3 42 Format 3 87 3 43 3 88 3 44 Format 3 90 3 45 gi 3 91 3 46 3 93 3 47 3 94 3 48 Format 3 95 4 1 S3C4520A System Memory 4 3 4 2 Initial System Memory Map After Reset 4 5 4 3 External Address Bus 4 6 4 4 Data Bus Connection with External Memory Nt 4 8 4 5 System Configuration Register 5 5 02 4 17 4 6 Product Code and Revision Number Register 4 18 4 7 Peripheral amp SDRAM Clock Enable Register CER 4 19 4 8 Watch Dog Timer Register WDT nennen 4 20 4 9 Clock Control Register 4 22 4 10 Systemi ecce erp zc DEEP RE E 4 23 4 11 USB 48 MHZ Clock rre 4 24 4 12 Divided System Clocks Timing
257. handled the current processor state must be preserved so that the original program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a fixed order see exception priorities on page 2 14 Action on Entering an Exception When handling an exception the ARM7TDMI 1 Preserves the address of the next instruction in the appropriate link register If the exception has been entered from ARM state then the address of the next instruction is copied into the link register that is current PC 4 or PC 8 depending on the exception See Table 2 2 on for details If the exception has been entered from THUMB state then the value written into the link register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value that depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions If the processor is in THUMB stat
258. hannel on HDLCB pad interface In DCE interface the internal HDLC can directly be connected to the external serial interface In PCM highway and IOM2 interface the TSA is located between the HDLC and the external serial interface By intervening in between the TSA provides the appropriate HDLC clocks during its programmed timeslot within an 8 KHz frame The TSA can support a maximum data rate of up to 10 Mbps with HDLCs In PCM highway interface up to 156 time slots can be supported with credible data transfer Although the 53 4520 can support up to 4096 bit positions 12bit programmable this requires a lower frequency of FSC or a high frequency of clock rates The IOM2 is pin multiplexed with HDLCA pins and the PCM highway multiplexed is pin multiplexed with HDLCB pin interface and the HDLCC pins are dedicated to DCE interface ELECTRONICS 8 1 TSA TIME SLOT ASSIGNER 3C4520A RISC MICROCONTROLLER TSA BLOCK DIAGRAM DCE IOM2 interface DCE PCM interface DCE interface Figure 8 1 TSA Block Diagram 8 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER TSA TIME SLOT ASSIGNER HDLC EXTERNAL PIN MULTIPLEXED SIGNALS HDLC external pins are multiplexed among the various operating modes The Mode bits in TSAxCFG determines operating mode of each TSA and HDLC external pins are automatically configured according to Mode bits as follows Table 8 1 HDLC External Pin Multiplexed Signals Channel External Interface Default Signal
259. he binary string in its NRZI encoding It is used by the input circuitry to align incoming data with the local clock and is defined to be eight bits in length SYNC serves only as a synchronization mechanism and is not shown in the following packet diagrams The last two bits in the SYNC field are a marker that is used to identify the end of the SYNC field and by inference the start of the PID The PID indicates the type of packet and by inference the format of the packet and the type of error detection applied to the packet The host and all functions must perform a complete decoding of all received PID fields Any PID received with a failed check field or which decodes to a non defined value is assumed to be corrupted and the packet receiver ignores it as well as the remainder of the packet If a function receives an otherwise valid PID for a transaction type or direction that it does not support the function must not respond For example an IN only endpoint must ignore an OUT token Function endpoints are addressed using two fields the function address field and the endpoint field The function address ADDR field specifies the function via its address that is either the source or destination of a data packet depending on the value of the token PID Cyclic redundancy checks CRCs are used to protect all fields in token and data packets In this context these fields are considered to be protected fie
260. he cache enable CE bit of the SYSCFG register to 1 or respectively Because cache memory does not have an auto flush feature you must be careful to verify the coherency of data whenever you re enable the cache You must also carefully check any changes that the DMA controller may make to data stored in memory Usually the memory area that is allocated to DMA access operations must be non cacheable Write Buffer Disable Enable The S3C4520A has four programmable write buffer registers that are used to improve the speed of memory write operations When you enable a write buffer the CPU writes data into the write buffer instead of an external memory location This saves the cycle that would normally be required to complete the external memory write operation The four write buffers also enhance the performance of the ARM7TDMI core s store operations To maintain data coherency between the cache and external memory the 53 4520 uses a write through policy An internal 4 level write buffer compensates for performance degradation caused by write through For more information see Chapter 5 ELECTRONICS 4 17 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER PRODUCT CODE AND REVISION NUMBER REGISTER PROREV There is PROREV register You can read the product code and revision number using this register Table 4 17 PROREV Register PROREV 0x004 Product code and revision number 0x4520 0010 3 0 Minor Revision Number MinR
261. he first word of all the TxWA frames These invalid bytes are removed when the word is moved from memory to TxFIFO 00 No Invalid bytes 01 1 invalid byte 10 2 invalid bytes 11 3 invalid bytes ELECTRONICS 6 27 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER Table 6 10 HCON Register Description Continued Bit Bit Name Description Number 13 12 Rx widget alignment These bits determine how many bytes are invalid in the first memory word RxWA of the frame to be received The invalid bytes are inserted when the word is assembled in the HRXFIFO 00 No Invalid bytes 01 1 invalid byte 10 2 invalid bytes 11 3 invalid bytes 14 Tx flag idle TXFLAG This bit selects the flag time fill mode active idle or the mark idle mode inactive idle for the transmitter The selected active or inactive idle state continues until data is sent after nRESET has return to High level The flag idle pattern is 7EH the mark idle pattern is FFH 15 single flag This bit controls whether separate closing and opening flags are TxSFLAG transmitted in succession to delimit frames When this bit is O independent opening and closing flags are transmitted in order to separate frame When this bit is set to 1 the closing flag of the current frame serves as the opening flag of the next frame 16 Tx loop back mode This bit is used for self testing If this bit is set to 1 the transmit data
262. he implementation of a demand paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 fora prefetch abort SUBS PC R14_abt 8 fora data abort This restores both the PC and the CPSR and retries the aborted instruction ELECTRONICS 2 13 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER Software Interrupt The software interrupt instruction SWI is used for entering Supervisor mode usually to request a particular supervisor function A SWI handler should return by executing the following irrespective of the state ARM or Thumb MOV PC R14 svc This restores the PC and CPSR and returns to the instruction following the SWI NOTE nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM7TDMI CPU core Undefined Instruction When ARM7TDMI comes across an instruction which it cannot handle it takes the undefined instruction trap This mechanism may be used to extend either the T
263. his bit 23 Rx internal error RxIERR This bit is set to 1 when received frame will be detected error possibility due to the receive clock is unstable 6 34 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 z Arruo mOoxoxzzm 3 0 Rx remaining bytes RxRB At 1 word boundary At 4 word boundary 0000 Valid data byte is 1 0000 Valid data byte is 1 0001 Valid data byte is 2 0010 Valid data byte is 3 0011 Valid data byte is 4 1111 Valid data byte is 16 4 Tx frame complete TxFC 0 Normal operation 1 Automatically set if two conditions are met 1 Tx FIFO is empty 2 An abort or a closing flag is transmitted 5 Tx FIFO available TxFA 0 Tx FIFO is not available 1 Tx FIFO is available that is the data to be transmitted can now be loaded into the Tx FIFO 6 Tx clear to send TxCTS 0 Level at the nCTS input pin is High 1 Level at the nCTS input pin is Low 7 Tx stored clear to send TxSCTS 0 Normal operation 1 transition occured at the nCTS input This transition can be used to trigger an interrupt 8 Tx underrun TxU 0 Normal operation 1 The transmitter ran out of data during transmission 9 Tx Good Frame TxGF 0 normal operation 1 A frame is successfully transmitted 10 Rx FIFO available RxFA 0 Normal operation 1 Data is available in
264. hown in Figure 6 2 At a start up the flip flop on the output is set in a High state the value in the time constant register is loaded into the counter and the counter starts counting down The output of the baud rate generator may toggle upon reaching zero the value in the time constant register is loaded into the counter and the process is repeated The time constant may be changed any time but the new value does not take effect until the next load of the counter The output of the baud rate generator may be used as either the transmit clock the receive clock or both It can also drive the digital phase locked loop If the receive or transmit clock is not programmed to come from the TXC pin the output of the baud rate generator may be echoed out via the TXC pin The following formula relates the time constant to the baud rate where MCLK2 or RXC is the baud rate generator input frequency in Hz BRG generates 2 output signals BRGOUT1 BRGOUT2 for transmit receive clocks and the DPLL input clock BRGOUT1 MCLK2 or CNTO 1 169 BRGOUT2 BRGOUT1 1 or 16 or 32 according to CNT2 value of the HBRGTC BRGOUT1 RxC 12 bit counter Divide by Divide by BRGOUT2 MOD 1 or 16 1 or 16 or 32 CNTO HBRGTC 15 4 CNT1 HBRGTC 3 2 CNT2 HBRGTC 1 0 BRGCLK HMODE 19 Figure 6 2 Baud Rate Generator Block Diagram ELECTRONICS 6 7 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER The example in the following Table
265. ield Figure 3 24 Software Interrupt Instruction The software interrupt instruction is used to enter supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR_sve If the SWI vector address is suitably protected by external memory management hardware from modification by the user a fully protected operating system may be constructed RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14_svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and N are defined as squential S cycle and non squential N cycle ELECTRONICS 3 49 INSTRUCTION SET ASSEMBLER SYNTAX S
266. igger This two bit trigger level value determines when the receiver start level RFTL to move the received data in 32 byte receive FIFO 00 1 byte valid 32 byte 01 8 32 10 18 32 11 28 32 24 Data Terminal Ready to This bit directly controls the nUADTR pin Setting this bit to one pin DTR the nUADTR pin goes to Low level If you set this bit to zero it goes High level 25 Request to Send to This bit directly controls the nUARTS pin only when the UART is RTS not hardware flow control mode If this bit set to one nUARTS pin goes Low level Otherwise it remains High level 27 26 This bit should be cleared by zero ELECTRONICS 10 5 UART 3C4520A RISC MICROCONTROLLER Table 10 3 UART Control Register Description Continued Bit Number Reset Value 28 Hardware Flow Control This bit determines whether UART select hardware flow control or Enable HFEN not If this bit set to one UART will control all pins concerning to hardware flow control These pins are nCTS nDCD and nRTS 29 Software Flow Control This bit determines whether UART select software flow control or Enable SFEN not If this bit set to one UART will act in software flow control In this mode you have to use Control Character register 31 30 This bit should be cleared by zero 10 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART 31 30 29 28 27 26 2 ELECTRONICS 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7
267. igned and signed multiplies with a 64 bit result since overflow does not occur in such calculations PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo random numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles Enter with seed in Ra 32 bits Rb 1 bit in Rb Isb uses TST Rb Rb LSR 1 Top bit into carry MOVS Rc Ra RRX 33 bit rotate right ADC Rb Rb Rb Carry into Isb of Rb EOR Rc Rc Ra LSL4H2 involved EOR Ra Rc Re LSR Z20 similarly involved new seed in Ra Rb as before MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2 n 1 2 4 8 16 32 MOV Ra Rb LSL n Multiplication by 24n 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 2 n 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS 3 61 INSTRUCTION SET Multiplication by 6 ADD MOV 3C4520A RISC MICROCONTROLLER Ra Ra Ra LSL 1 Multiply by 3 Ra Ra LSL 1
268. ined but do not cause the Undefined instruction trap to be taken for instance a Multiply instruction with bit 6 changed to a 1 These instructions should not be used as their action may change in future ARM implementations ELECTRONICS 3 1 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set Wemoi 0 Aem 8 O BX Branch and exchange R15 Rn T bit Rn 0 CDP coprocessor specific CMN EOR Exclusive OR Rd Rn AND NOT LDC LDM Stack manipulation Pop LDR Rd address MCR MOV MRC MRS Move PSR status flags to register Rn PSR MSR Move register to PSR status flags PSR Rm MUL Multiply Rd Rm Rs 3 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET Table 3 1 The ARM Instruction Set Continued Mnemonic instruction om a RSB RSC SBC STC STM Stack manipulation push Swi SW ELECTRONICS 3 3 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils the conditions encoded by the field the instruction is executed otherwise it is ignored There are si
269. ing a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Rb LSL n MOV Rb LSL n 2 Multiplication by 24n 1 3 5 9 17 LSL Rt Rb zin ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb zin RSB Rb Rb LSL zin SUB Ra Rt Rb 4 Multiplication by 24n 2 4 8 LSL Ra Rb n MOV Ra Rb LSL n MVN Ra Ra RSB Ra 0 5 Multiplication by 24n 1 3 7 15 LSL Rt Rb n SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by any C 2 1 2 n 1 2 n or 2 n 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra n MOV Ra LSL n ELECTRONICS 3 97 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code Thumb code signed_divide Signed divide of R1 by RO returns quotient in RO remainder in R1 Get abs value of RO into R3 ASR R2 RO 31 Get 0 or 1 in R2 depending on sign of RO EOR RO R2 EOR with 1 OxFFFFFFFF if negative SUB RO R2 and ADD 1 SUB 1 to get abs value SUB always sets flag so go amp report division by 0 if neces
270. ing function blocks are integrated into the HDLC module Digital phase locked loop DPLL block Baud rate generator BRG ELECTRONICS 6 1 HDLC CONTROLLERS FEATURES Important features of the S3C4520A HDLC block are as follows 6 2 Protocol features Flag detection and synchronization Zero insertion and deletion Idle detection and transmission FCS encoding and detection 16 bit Abort detection and transmission Four address station registers and one mask register for address search mode Selectable CRC No CRC mode Automatic CRC generator preset Digital PLL block for clock recovery Baud rate generator NRZ NRZI FM Manchester data formats for Tx Rx Loop back and auto echo mode Tx and Rx clock inversion Tx and Rx FIFOs with 8 word 8 x 32 bit depth Selectable 1 word or 4 word data transfer mode for Tx Rx Data alignment logic Endian translation Programmable interrupts Modem interface Hardware flow control HDLC frame length based on octets 53 4520 RISC MICROCONTROLLER ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS FUNCTION DESCRIPTIONS Figure 6 1 shows the HDLC module s function blocks These function blocks are described in detail in the following sections Tx FIFO FCS Generator 8 Words Flag Abort Idle Zero Generateor and Insertion ncoder Transmitter Flag Abort Idle Registers Detection Zero Control FCS Checker loop auto echo o lt a 3 UJ C UO
271. initial value Example LDR RO R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the data abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S 1N 11 and LDR PC take 2S 2N 11 incremental cycles where S N I are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 31 INSTRUCTION SET ASSEMBLER SYNTAX 3C4520A RISC MICROCONTROLLER lt LDR STR gt cond B T Rd lt Address gt where LDR STR cond Rd Rn and Rm lt Address gt can be 1 lt shift gt 3 32 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 If B is present then byte transfer otherwise word transfer If T is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is n
272. inline sync mode this sync pattern is used to get synchronization from received data Once the pattern in HSYNC pattern is detected on the RxD the data reception will be started Table 6 20 Synchronization Register HSYNCB 0x83C HSYNCC 0x93C HDLC Sync Register 0x0000007E HDLC Sync Register 0x0000007E HSYNCA 0x73C HDLC Sync Register 0x0000007E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2 1 0 7 0 HDLC Sync pattern Figure 6 21 HDLC Synchronization Register 6 46 ELECTRONICS 53 4520 RISC MICROCONTROLLER IOM2 CONTROLLER IOM2 CONTROLLER The IOM2 bus is an industry standard serial bus for interconnecting telecommunication ICs The S3C4520A includes the 2 controller to enable a modular interface to the terminal network such as an ISDN interface FEATURES 2 terminal mode support Inter device communication via IC channel TIC bus access control Monitor channel collision control Optional signals such as BCL and STRB Bus Deactivation Activation via C IO Bus Reversal ELECTRONICS 7 1 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER IOM2 BUS 2 bus provides a symmetrical full duplex communication link containing user data control programming and status channels Both the line card and terminal portions of the IOM2 standard utilize the same basic frame and clocking structure but differ in the number and usage of the individu
273. interrupt source This register has to be cleared at the top of an interrupt service routine Table 14 3 INTPND Register INTPND 0x404 Interrupt pending register 0x00000000 31 232221 20 19 18 17 16 15 14 13 121110 9 8 7 6 5 4 3 2 1 0 mreno 22 0 Interrupt pending bits NOTE Each of the 23 bits in the interrupt mode pending register INTPND corresponds to an interrupt source When an interrupt request is generated its pending bit is set to 1 The service routine must then clear the pending condition by writing a 1 to the apropriate pending bit at start The 23 interrupt sources are mapped as follows 22 WatchDog timer 21 Timer 1 interrupt 20 Timer 0 interrupt 19 GDMA channel 5 interrupt 18 GDMA channel 4 interrupt 17 GDMA channel 3 interrupt 16 GDMA channel 2 interrupt 15 GDMA channel 1 interrupt 14 GDMA channel 0 interrupt 13 USB interrupt 12 IOM 2 interrupt 11 HDLC channel C Rx interrupt 10 HDLC channel C Tx interrupt 9 HDLC channel B Rx interrupt 8 HDLC channel B Tx interrupt 7 HDLC channel A Rx interrupt 6 HDLC channel A Tx interrupt 5 UART receive and error interrupt 4 UART transmit interrupt 3 External interrupt 3 2 External interrupt 2 1 External interrupt 1 0 External interrupt 0 Figure 14 2 Interrupt Pending Register INTPND 14 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER INTERRUPT CONTROLLER INTERRUPT MASK REGISTER The interrupt mask re
274. ion is also cleared and the DMA operation for receiving is aborted too IDLE AND TIME FILL When the transmitter is not transmitting a frame it is in an idle state The transmitter signals that it has entered an idle state in one of the following two ways 1 by transmitting a continuous series of flag patterns time fill or 2 by transmitting a stream of consecutive 1s mark idle The flags and mark idle are not transferred to the HRXFIFO The flag or mark idle selection bit TXFLAG in HCON controls this function when TxFLAG is 0 mark idle is selected when TxFLAG is 1 the flag time fill method is selected 6 6 ELECTRONICS 53 4520 RISC MICROCONTROLLER HDLC CONTROLLERS FIFO STRUCTURE In both transmit and receive directions 32 byte 8 word deep FIFOs are provided for the intermediate storage of data between the serial interface and the CPU Interface DMA SUPPORT In S8C4520A Each DMA Channel promises to service its specific HDLC Channel that is DMA3 service to HDLCA DMA1 and DMA4 to HDLCB and DMAS to HDLCC Following operation section contains detail description about HDLC operation with DMA BAUD RATE GENERATOR The HDLC module contains a programmable baud rate generator BRG The BRG register contains a 16 bit time constant register a 12 bit down counter for time constant value two control bit to divide 16 and another two control bits to divide 16 or 32 A clock diagram of the BRG is s
275. ions of the IEEE Standard 1149 1 Compatible Test Access Port TAP This standard applies to the Test Access Port and Boundary Scan JTAG specification which is supported by the 53 4520 microcontoller In test mode package pads are monitored by the serial scan circuitry This is done to support connectivity testing during manufacturing as well as system diagnostics JTAG control is not used to drive internal data out of the 53 4520 To conform with IEEE 1194 1 the S8C4520A has TAP controller instruction register a bypass register and an ID register These components are described in detail below ELECTRONICS 1 APPENDIX 3C4520A RISC MICROCONTROLLER TAP CONTROLLER The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal It is synchronous state machine which controls the JTAG logic see Figure A 1 In Figure A 1 the value shown next to each curved arrow represents the value of the TMS signal as it is sampled on the rising edge of the TCK signal Test Login Reset 1 0 Run Test ldle l Select DR_Scan Select IR_Scan 0 0 Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Exit2 DR Exit2 IR 1 Update DR Update IR Figure A 1 TAP Controller State Machine A 2 ELECTRONICS 3C4520A RISC MICROCONTROLLER APPENDIX A BOUNDARY SCAN REGISTER The S3C4520A scan chain implementation uses 118 bit boundary scan register This register con
276. is feature is controlled by the double flag FF single flag F or frame separator selection bit the TxSFLG bit in the HCON register Order of Bit Transmission Address field control field and information field bytes are transferred between the CPU and the HDLC module in parallel over the data bus These bytes are transmitted and received LSB first The 16 bit frame check sequence FCS field is however transmitted and received MSB first 6 4 ELECTRONICS 53 4520 RISC MICROCONTROLLER HDLC CONTROLLERS Address A Field The eight bits that follow the opening flag are called address A field The address field are expendable To extend this address byte simply user defined address write to the station address register To check address byte against the incoming data have to be used the MASK register If match occurred the frame s data including address and CRC 16 bit into the HRXFIFO and then moved to system memory If it is not matched simply discarded The S3C4520A allows up to 32 bits address For instance SDLC and LAPB use an 8 bit address LAPD further divides its 16 bit address into different fields to specify various access points one piece of equipment Some HDLC type protocol allows for extended addressing beyond 16 bit Control C Field The eight bits that follow the address field are called the control link control C field The S3C4520A HDLC module treats the control field in the same way as the information field
277. ive Buffer Register ELECTRONICS 10 17 UART 3C4520A RISC MICROCONTROLLER UART BAUD RATE DIVISOR REGISTER The values stored in the baud rate divisor registers UBRDIV let you determine the serial Tx Rx clock rate baud rate as follows BRGOUT MCLK2 or UCLK CNTO 1 16 CNT1 16 Table 10 12 UBRDIVO and UBRDIVO Registers UBRDIV OxE14 UART baud rate divisor register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 om 3 0 Baud divisor value CNT1 xxx0 divide by 1 1 divide by 16 15 4 Time constant value for CNTO Figure 10 7 UART Baud Rate Divisor Register 10 18 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART UART BAUD RATE EXAMPLES UART BRG input clock MCLK2 is the system clock frequency divided by 2 If the system clock frequency is 50 MHz and 2 is selected the maximum BRGOUT output clock rate is MCLK2 16 1 5625 MHz UCLK is the external clock input pin for UART UART BRG input clock MCLK2 UCLK can be selected by register 12 bit Counter Divide by 1 or 16 Divide by 16 BRGOUT Sample Clock NOTE UBTDIVn 15 4 CNT1 UBRDIVn 3 0 SC ULCON 6 Figure 10 8 UART Baud Rate Generator BRG Table 10 13 Typical Baud Rates Examples of UART Baud Rates MCLK2 25 MHz gt 12004 00 1735 120008 0 0064 _ 4002 oo 87 240015 0004 48077 02 0 480
278. j o o 11 0 0 010 0 0 a 1 0 0 010101010 toms 1 010 0 010101010 ESESESESESESESENESESESERESESEZERHNET CIN EE eens 225 671ms EX xj1 ojo ojojojo ojojo o o o o o oj o o 22706 285375 ELECTRONICS 4 21 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER SYSTEM CLOCK AND MUX BUS CONTROL REGISTER CLOCK CONTROL REGISTER CLKCON There is a clock control register in the System Manager This control register is used to divide the internal system clock so the slower clock than the system clock can be made by clock dividing value Table 4 21 CLKCON Register Registers Reset value CLKCON 0x300 Clock control register 0x0000_0000 Table 4 22 CLKCON Register Description Clock dividing value 53 4520 System Clock source If CLKSEL is Low PLL output clock is used as the S3C4520A internal system clock If CLKSEL is High XCLK is used as the 53 4520 internal system clock The internal system clock is divided by this value The clock divided is used to drive the CPU and system peripherals Only one bit can be set in CLKCON 15 0 that is the clock dividing value is defined as 1 2 4 8 16 Internal system clock fietK CLKCON 1 If all bits a
279. lds The PID is not included in the CRC check of a packet containing a CRC All CRCs are generated over their respective fields in the transmitter before bit stuffing is performed Handshake packets are used to report the status of a data transaction and can return values indicating successful reception of data command acceptance or rejection flow control and halt conditions 7 bits 4 bits 5 bits ADDR ENDP CRC5 Token In Out 0 1023 bytes 16 bits DATA CRC16 Data Toggle Handshake Low Speed Preamble 11 bits 5 bits CRC5 Start of Frame Figure 11 3 USB Frame Format 11 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB BIT STUFFING AND NRZI CODING The USB employs NRZI data encoding when transmitting packets In NRZI encoding 1 is represented by no change in level and a 0 is represented by a change in level The high level represents the J state on the data lines encoding and J state means that D is 5 V and D is 0 V A string of zeros causes the NRZI data to toggle each bit time A string of ones causes long periods with no transitions in the data In order to ensure adequate signal transitions the transmitting device employs bit stuffing when sending a packet on USB A zero is inserted after every six consecutive ones the data stream before the data is encoded to force a transition the data stream This gives the receiver logic a data transition at least once every seven bit
280. ler ARM Equivalent EAEC Rb Imm STRH Rd Rb Imm gt lmm to base address Rb and store bits 0 15 of Rd at the resulting address LDRH Rb LDRH Rd Rb Add lmm to base address in Rb Load bits 0 15 from the resulting address into Rd and set bits 16 31 to zero NOTE is a full 6 bit address but must be halfword aligned ie with bit O set to 0 since the assembler places Imm gt gt 1 in the Offset5 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 17 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R6 R1 56 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28 as the Offset5 value LDRH R7 4 Load into R4 the halfword found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value ELECTRONICS 3 83 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 11 SP RELATIVE LOAD STORE 15 14 13 7 0 12 11 10 8 oelofije a Word O 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 40 Format 11 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in the following ta
281. ltering off 1 Filtering on 9 0 Active Low 1 2 Active High 14 12 Control external DMA request 4 input for port 0 DRQ4 14 Port for or for nCTSB 0 Disable nCTSB 1 Enable 13 0 Filtering off 1 Filtering on 12 0 Active Low 1 Active High 17 15 Control external DMA request 5 input for port 8 DRQ5 17 Port 8 for DRQ5 or for nCTSC 0 Disable nCTSC 1 Enable 16 0 Filtering off Filtering on 15 0 Active Low Active High 19 18 Control external DMA acknowledge 0 output for port 31 DACKO 19 Port 31 for DACKO 0 Disable 1 Enable 18 0 Active Low 1 Active High 21 20 Control external DMA acknowledge 1 output for port 33 DACK1 See control external DMA acknowledge 0 23 22 Control external DMA acknowledge 2 output for port 35 DACK2 See control external DMA acknowledge 0 25 24 Control external DMA acknowledge 3 output for port 37 DACK3 25 Port 37 for DACKS or for nDCDA 0 Disable nDCDA 1 Enable 24 0 Active Low 1 Active High 27 26 Control external DMA acknowledge 4 output for port 1 DACK4 27 Port 1 for DACK4 or for nNDCDB 0 Disable nDCDB 1 Enable 26 0 Active Low 1 Active High 29 28 Control external DMA acknowledge 5 output for port 9 DACK5 29 Port 9 for DACKS or for nDCDC 0 Disable nDCDC 1 Enable 28 0 Active Low 1 Active High Figure 13 6 Port Control Register 2 IOPCON2 ELECTRONICS 3C4520A R
282. m 0 05 ET 2 2 2 2 4 4 4 6 6 Low level output voltage to lo 1 B16 1 1 lo mA 1 lo 1 2 2 2mA 2 2mA 4 4 lo 4 4 lo 4 lo 6mA lo 6mA mA Tri state output leakage current ee Maximum operating current 3 6 V NOTES 1 All 5 V tolerant inputs have less than 0 2 hysterics 2 Type B1 means 1mA output driver cells and Type B6 B24 means 6mA 24mA output driver cells 15 2 ELECTRONICS 53 4520 RISC MICROCONTROLLER ELECTRICAL DATA Table 15 4 A C Electrical Characteristics 0 to 70 C 3 0V to 3 6 V Description Memory control signal High Z time ExtMREQ setup time ExtMREQ hold time ExtMACK rising edge delay time ExtMACK falling edge delay time Address hold time Address delay time ROM SRAM Flash bank chip select delay time ROM SRAM or external bank output enable delay ROM SRAM or external I O bank write byte enable delay Read data hold time Write data delay time SRAM or external I O Write data hold time SRAM or external I O DRAM RAS signal active delay DRAM RAS signal release delay 10 68 10 94 DRAM CAS
283. m the programmer s point of view the ARM7TDMI can be in one of two states e ARM state which executes 32 bit word aligned ARM instructions e THUMB state which operates with 16 bit half word aligned THUMB instructions In this state the PC uses bit 1 to select between alternate half words NOTE Transition between these two states does not affect the processor mode or the contents of the registers SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state Entering ARM State Entry into ARM state happens 1 On execution of the BX instruction with the state bit clear in the operand register 2 On the processor taking an exception IRQ FIQ RESET UNDEF ABORT SWI etc In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address MEMORY FORMATS ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to hold the first stored word bytes 4 to 7 the second so on ARM7TDMI can treat words in memory as being stored either in Big Endian or Little Endian format ELECTRONICS 2 1 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER BIG END
284. me for this exception entry should be added to worst case FIQ latency calculations ELECTRONICS 2 15 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER Interrupt Latencies The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchroniser Tsyncmax if asynchronous plus the time for the longest instruction to complete the longest instruction is an LDM which loads all the registers including the PC plus the time for the data abort entry Texc plus the time for FIQ entry 4 At the end of this time ARM7TDMI will be executing the instruction at Ox1C Tsyncmax is processor cycles is 20 cycles is cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser Tsyncmin plus Tfiq This is 4 processor cycles Reset When the nRESET signal goes LOW ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again ARM7TDMI 1 Overwrites R14 svc and SPSR
285. modification may be performed either before pre indexed P 1 or after post indexed P 0 the base register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained if necessary by setting the offset to zero Therefore post indexed data transfers always write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected ELECTRONICS 3 35 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER HALFWORD LOAD AND STORES Setting S 0 and H 1 may be used to transfer unsigned Half words between an ARM7TDMI register and memory The action of LDRH and STRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below SIGNED BYTE AND HALFWORD LOADS The S bit controls the loading of sign extended data When S 1 the H bit selects between Bytes H 0 and Half words 1 The L bit should not be set low Store when Signed S 1 operations have been selected The LDRSB instruction loads the selected Byte into bits 7 to O of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit Th
286. mp PTXCB PP6 observe only X amp control 1 amp PTXCB_PP6 output3 X 31 1 Z amp 7 observe only X amp control 1 amp PRXCB_PP7 output3 X 28 1 Z amp PnCTSC xDREQS5 8 observe only X amp control 1 amp PnCTSC 5 PP8 output3 X 25 1 2 amp PnDCDC_xDACK5_PP9 observe only X amp control 1 amp PnDCDC_xDACK5_PP9 output3 X 22 1 2 amp 15 APPENDIX 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 1 1 4 1 1 4 1 1 4 1 eee 53 4520 RISC MICROCONTROLLER PTXDC_PP10 observe only amp control 1 amp PTXDC_PP10 output3 X 19 1 2 amp PRXDC_PP11 observe only X amp control 1 amp PRXDC_PP11 output3 X 16 1 Z amp PnDTRC_PP12 observe only amp E control 1 amp PnDTRC 2 output3 X 13 1 2 amp PnRTSC observe only X amp control 1 amp PnRTSC_PP13 output3 X 10 1 2 amp PTXCC_PP14 observe_only X amp control 1 amp PP14 output3 X 7 1 2 amp PRXCC_PP15 observe only amp control 1 amp 15 output3 X 4 1 2 amp PUSB_SOF output2 X amp PUSB CKS observe only X amp PUSB CK o
287. n back at the end of the second cycle the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the base second or later in the transfer order will store the modified value A LDM will always overwrite the updated base if the base is in the list DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the abort signal high This can happen on any transfer during a multiple register load or store and must be recoverable if ARM7TDMI is to be used in a virtual memory system Aborts during STM Instructions If the abort occurs during a store multiple instruction ARM7TDMI takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When ARM7TDMI detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible
288. n of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38 If the Operands are Interpreted as Signed Operand A has the value 10 operand B has the value 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands are Interpreted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represented as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Oper and Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct results and Rd Rn and Rs may use the same register when required ELECTRONICS 3 23 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V overflow flag is unaffected INSTRUCTION CYCLE TIMES MUL takes 15 ml and MLA 15 m 1 I cycles to execute where S are defined as sequential S cycle and internal respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by
289. n to TxFIFO When the AUTOEN is 0 and there are data to transmit the transmitter enforces RTS pin to go 0 and starts to send the data from TxFIFO When the AUTOEN is 1 and there are data to transmit the transmitter must wait CTS pin 0 before transmission Once these conditions are met the transmission will be started When the last byte is loaded from TxFIFO the transmitter sends 1 after last byte transmission If the TXREV in HMODE is set to 1 each data byte will be reversed in its bit order before transmission msb first transmitted Transparent receiver operation The receiver enters in transparent mode by setting RXTRANS to 1 in HMODE In this mode the receiver waits to gain synchronization before receiving data Once the reception begins the receiver moves the data from RxD pin to RxFIFO The receiver will not stop receiving data until the RxSTOP in HCON is set to 1 which make the receiver to stop receiving and to go to wait synchroniztion again If the RxREV HMODE is set to 1 each data byte will be reversed in its bit order before entering RxFIFO msb first received Transparent synchronization The S3C4520A must be synchronized before transmitting or receiving data The synchronization method is selectable by software control The transmitter achieves synchornization by monitoring CTS pin depending on AUTOEN in HCON If AUTOEN is O the transmitter is allowed to transmit data anytime there are data in TxFIFO H
290. nRCS 1 0 or nECS 3 0 is generated and the derived offset is driven to address external memory through the 53 4520 physical address bus The 53 4520 can be configured as big endian or little endian mode by external little big selection pin LITTLE pin 51 In Big Endian mode the most significant byte of the external memory data is stored at the lowest numbered byte and the least significant byte at the highest numbered byte For example in case of the external half word memory system Byte 0 of the memory is connected to data lines 16 through 9 D 16 9 In Little Endian mode vice versa See Figure 4 4 External Memory Interface ELECTRONICS 4 7 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER ENDIAN MODES 53 4520 supports both little endian and big endian for external memory or I O devices by setting the pin LITTLE 51 The system diagram for 3 4520 is shown in S3C4520A External Memory CPU ARM7TDMI Memory 0 Bit Number Controller Half Word Address CPU Register Special Register Figure 4 4 Data Bus Connection with External Memory Tables of the next page 4 3 through 4 14 are show the program data path between the CPU register and the external memory using little big endian and word half word byte access 4 8 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER Table 4 3 and 4 4 Using big endian and word access Program Data path between register and external memory WA Addre
291. nURTS_PP21 60 8 PnUCTS PP22 61 amp PnUDCD PP23 62 amp PxIREQO_PP24 63 amp PxIREQ1_PP25 64 amp PxIREQ2_PP26 65 amp PxIREQ3_PP27 66 amp PxDREQO_PP30 67 amp PxDACKO_PP31 68 amp PxDREQ1_PP32 69 amp PxDACK1_PP33 70 amp PxDREQ2_PP34 71 amp PxDACK2_PP35 72 amp ES PTOUTO PP28 73 amp PTOUT1_PP29 74 8 PFILTER 75 amp PUSB FLT 76 amp PSDCLK 77 amp PnRASO0 78 amp PnRAS1 79 amp 50 80 amp PnCAS1 81 amp PnDWE 82 amp 50 83 amp PnECS1 84 amp PnECS2 85 amp PnECS3 86 8 PnRCS0 87 amp PnRCS1 88 amp 89 amp PnWBEO 90 amp PnWBE1 91 amp PADDRO0 92 amp PADDR1 93 amp PADDR2 94 amp PADDR3 95 amp PADDR4 96 amp PADDR5 97 amp PADDR6 98 amp PADDR7 99 amp PADDR8 100 amp ELECTRONICS A 9 APPENDIX 3C4520A RISC MICROCONTROLLER PADDR9 101 amp gt PADDR11 102 amp PADDR12 103 amp PADDR13 104 amp PADDR14 105 amp PADDR15 106 amp PADDR16 107 amp PUSB SOF 108 amp PADDR21 109 amp PADDR20 110 amp PADDR10 111 amp PADDR19 112 amp PADDR17 113 amp PnDTRA_BCL 114 amp PnRTSA_STRB 1
292. nel Receive Data Figure 7 17 IOM2 Monitor Channel Receive Data Register 7 20 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER Table 7 14 IOM2STRB Strobe Register resister Description Reset Vato IOM2STRB Strobe Register 0x00000000 pug 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 7 0 The location of START bit time slot 15 8 The location of STOP bit of time slot Figure 7 18 2 Strobe Register ELECTRONICS 7 21 IOM2 CONTROLLER 3C4520A RISC MICROCONTROLLER NOTES 7 22 ELECTRONICS 3C4520A RISC MICROCONTROLLER TSA TIME SLOT ASSIGNER TSA TIME SLOT ASSIGNER OVERVIEW The S3C4520A includes three time slot assigners TSA which provide flexible data path control between the three HDLCs and external interfaces A variety of data interface can be supported by the S3C4520A with the TSA raw Data Communication Equipment DCE Pulse Code Modulation PCM highway non multiplexed mode and multiplexed mode and ISDN Oriented Modular Interface 2 Each TSA can be programmed to select one between DCE and PCM highway non multiplexed interface Besides DCE PCM highway interface A can afford IOM2 interface to multiplex data from each HDLC channel on HDLCA pad interface and interface can afford PCM highway multiplexed interface to multiplex data from each HDLC c
293. nel Transmit Data 0x0000000F 3 0 CITDO This field includes the data to be transmitted on the channel The data is continuously transmitted until a new code is loaded 31 4 3 0 Channel Transmit Data Figure 7 12 2 Channel Transmit Data Register Table 7 9 IOM2CIRDO 2 10 Channel Receive Data Register IOM2CIRDO 0 1 Channel Receive Data 0x00000000 3 0 CIRDO This field includes the data received on the channel This data is sure to be valid by double last look criterion valid during two successive frames 3 0 Channel Receive Data Figure 7 13 2 Channel Receive Data Register 7 18 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER Table 7 10 IOM2CITD1 IOM2 C I1 Channel Transmit Data Register Reise RW Description Resevaue IOM2CITD1 0xA20 1 Channel Transmit Data 0x0000003F 5 0 CITD1 This field includes the data to be transmitted on the C I1 channel The data is continuously transmitted until a new code is loaded 31 6 Reserved 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 5 0 1 Channel Transmit Data Figure 7 14 2 1 Channel Transmit Data Register Table 7 11 IOM2CIRD1 IOM2 1 Channel Receive Data Register RW IOM2CIRD1 0 24 1 Channel Receive Data 0x00000000 5 0 CIRD1 This field in
294. nk Base Pointer ow tACC ale 1 0 Page mode configuration PMC 00 Normal ROM 01 4 word page 10 8 word page 11 16 word page 3 2 Page address access time tPA 00 5 cycles 01 2 cycles 10 cycles 11 4 cycles 6 4 Programmable access cycle tACC 000 Disable bank 001 2 cycles 010 3 cycles 011 4 cycles 100 5 cycles 101 6 cycles 110 7 cycles 111 8 cycles 8 7 DW 00 Disable 01 Byte 8 bits 10 Half word 16 bits 11 Disable 14 10 ROM SRAM Flash bank base pointer This value is the start address of the ROM SRAM Flash bank The start address is calculated as ROM SRAM FLASH bank base pointer lt lt 20 24 20 ROM SRAM FLASH bank next pointer The start address is calculated as ROM SRAM FLASH bank base pointer lt lt 20 Figure 4 18 ROM SRAM FLASH Control Registers ROMCONO ROMCON 1 ELECTRONICS 4 33 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER Address Data Fetch Point tACC 4 5 cycles Figure 4 19 ROM SRAM Flash Read Access Timing 4 34 ELECTRONICS SYSTEM MANAGER Data Fetch 4 word page 2 3 cycles tPA 1 2 cycles 1 tACC PMC 4 35 53 4520 RISC MICROCONTROLLER Address Data Fetch Data Fetch o 9 5 Figure 4 20 ROM Flash Page Read Access Timing ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER lt 4 5 cycles tACC Fig
295. nk 0 base pointer lt lt 20 The end address of external I O bank 0 is defined as external I O bank 0 base pointer gt gt 20 256 Kbytes 1 NOTE All external I O banks are located in the continuous adress space which begins at the start address of external I O bank 0 The size of each external I O bank is fixed at 256Kbytes The start and end addresses of the other three external I O banks can be derived from the external I O bank 0 base pointer value 15 Validity of spedial register field VSF 0 Not accessible to memory bank 1 Accessible to memory bank 16 Refresh enable REN 0 Disable DRAM refresh 1 Enable DRAM refresh 19 17 CAS hold time tchr ROW cycle time tRC 1 000 1 cycle 001 2 cycles 010 3 cycles 011 4 cycles 100 5 cycles 101 Not used 6 cycles 110 Not used 111 Not used 20 CAS setup time tCSR nete 2 0 1 cycle 1 2 cycles 31 21 Refresh count value duration The refresh period is calculate as 2 11 value 1 fMCK NOTES 1 In EDO normal DRAM mode CAS hold time can be programmed upto 5 cycles But in SDRAM mode this bit fields function are defined as ROW Cycle Time tRC and can be programmed upto 6 cycles In SDRAM mode this bit field is reserved Figure 4 30 DRAM Refresh and External I O Control Register REFEXTCON 4 50 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER Continuous 512 K Half word address External YO Bank space for
296. nstructions take 2N incremental cycles to execute ELECTRONICS 3 37 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER ASSEMBLER SYNTAX lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR Load from memory into a register STR Store from a register into memory cond Two character condition mnemonic See Table 3 2 H Transfer halfword quantity SB Load sign extended byte Only valid for LDR SH Load sign extended halfword Only valid for LDR Rd An expression evaluating to a valid register number lt address gt can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register 3 A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register 4 Rn and Rm are expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining In this case base write back should not be specified Writes back the base register set the
297. nt 1 endpoint 4 The MCU only needs to access this register for an IN endpoint once the endpoint has been configured Table 11 24 USB In CSR register 1 USBICSR1 0x44 USBIn CSR register 1 0x00 EP1 EP4 11 34 ELECTRONICS 3C4520A RISC MICROCONTROLLER USB Table 11 25 USBICSR1 Description USB IN packet Set R Clear The MCU sets this bit after writing a packet of data into ReaDY the FIFO The USB clears this bit once the packet has USBINRDY been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the SEND STALL bit is set by the MCU this bit can not be set Indicate there is at least one packet of data in FIFO USBICR1 1 0 10 gt 1 packet IN FIFO USBICR1 1 0 11 gt 2 packets of lt 1 2 FIFO Or 1 packets of gt FIFO size USB UNDER Clear R Set Valid For ISO Mode Only The USB sets this bit when in USBUNDER ISO mode an IN token is received and the USBINRDY bit is not set The USB sends a zero length data packet for Set USB fifo Not EMPty USBNEMP such conditions and the next packet that is loaded into the FIFO is flushed The MCU writes a 1 to this register to issue a STALL handshake to the USB The MCU clears this bit to end the USB SenD W R STALL USBSDSTALL STALL condition USB SenT R Clear The USB sets this
298. ny Tx preamble length bit values in HMODE 10 8 when the Tx preamble bit TxPRMB is 17 and then the Tx preamble bit is cleared automatically The opening flag follows this preamble pattern and the data will be transmitted Table 6 16 HPRMBA HPRMBB Register Registers onset Description 4 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O eera 7 0 Preamble Pattern Figure 6 17 HDLC Preamble Constant Register The reference for the preamble pattern of each data mode is as follows Table 6 17 Preamble Reference Pattern 6 42 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC STATION ADDRESS REGISTERS HSADRO 3 AND HMASK REGISTER Each HDLC controller has five 32 bit registers for address recognition four station address registers and one mask register Generally the HDLC controller reads the address of the frame from the receiver to check it against the four station address values and then masks the result with the user defined HMASK register A 1 in the HMASK register represents a bit position for which an address comparison should occur A 0 represents a masked bit position If you check the address up to four bytes the HMASK register value should be Dependent on the HMASK register value the frame s address is compared If the address is not matched this frame is discarded Table 6 18 HSADR and HMASK Regi
299. ock UCLK Auto Baud Rate Generator tries to get the baud rate from input data in this mode The transmitter and receiver blocks have independent data buffer registers and data shifters And 32 byte transmit FIFO and 32 byte receive FIFO is also provided which include transmit and receive buffer In non FIFO mode transmit data is written first to the transmit buffer register From there it is copied to the transmit shifter and then shifted out by the transmit data pin UTXDn Receive data is shifted in by the receive data pin URXDn It is then copied from the shifter to the receive buffer register when one data byte has been received Otherwise you can select FIFO mode In FIFO mode transmit and receive use transmit FIFO and receive FIFO instead of Tx Rx buffer register They are controlled by each FIFO trigger level The SIO control units provide software controls for mode selection and for status and interrupt generation In S3C4520A software flow control or hardware flow control can be selected according to the application To use modem interface signal see chapter 12 IOPCON1 register ELECTRONICS 10 1 UART System BUS MCLK2 Transmit Data Transmit Control Transmit Status Control and Status Receive Data Block og Receive Status Control Character Register Baud Rate UART_CLK Divisor 3C4520A RISC MICROCONTROLLER Modem Control Signal TxBuffer Register Transmit FIFO 32 Bytes se ee Shift
300. of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages 3C4520A RISC Microprocessor User s Manual Revision 2 Publication Number 22 S3 C4520A 032001 2001 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended
301. of the HDLC module over the TXC pin if the TXC pin is not being used as an input During idle time you can set the TxPRMB in to send the special pattern required for a remote DPLL to lock the phase In this case the content of the HPRMB register is sent repeatedly The length of preamble is determined by TxPL bit in HMODE 10 8 It is noticed that the frequency of the receive clock RxC should be slower than half of the internal system clock i e MCLK 2 Otherwise the data transfer from receive FIFO to memory could be lost 6 10 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC OPERATIONAL DESCRIPTION The following sections describe the operation of the HDLC module HDLC INITIALIZATION A power on or reset operation initializes the HDLC module and forces it into the reset state After a reset the CPU must write a minimum set of registers as well as any options set based on the features and operating modes required First the configuration of the serial port and the clock mode must be defined These settings include the following Data format select select DPLL clock select Transmit clock select Receive clock select BRG DPLL enable to use internal clock You must also set the clock for various components before each component is enabled Additional registers may also have to be programmed depending on the features you select All settings for the HDLC mode
302. of the data received Data bytes are always transferred from a full register to an adjacent empty register Each register has pointer bits that indicate the frame status When these pointers appear at the last 1 word or 4 word FIFO location they update the LAST bit indicating the last of a frame the OVERRUN bit the CRC error bit or Non octet aligned bit The HRXFIFO data available RxFA status bits indicate the current state of the HRXFIFO When the HRXFIFO data status bit is 1 the HRXFIFO is ready to be read The HRXFIFO data status is controlled by the 4 word or 1 word transfer selection bit Rx4WD When an overrun occurs the overrun frame of the HRXFIFO is no longer valid An frame abort or a High level on nDCD input with the AutoEN bit in HCON is set to 1 the frame is cleared in the HRXFIFO The last byte of the previous frame which is separated by the frame boundary pointer is retained Data in HRXFIFO should be read by word size The HRXFIFO is cleared by the Rx reset bit set to 1 an abort signal received or nRESET RxFIFO Data Valid OV CRCE NO Figure 6 15 HDLC Rx FIFO Function Diagram 6 40 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC BRG TIME CONSTANT REGISTERS HBRGTC Table 6 15 HBRGTCA HBRGTCB HRBGTCC Register Registers onst RW Description ResetValue HBRGTCA 0x71C R W HDLCA BRG Time Constant Register 0x00000000 HBRGTCB 0x81C R W HDLCB BRG Time Constant Regis
303. on are isolated from end users and plug and play is supported There re other merits for users Self identifying peripherals automatic mapping function to driver auto configuration dynamically attach and detach and reconfigurable and so on USB architecture is suitable for wide range of workloads and applications Various device can be attached which bandwidths ranging from a few kbps bits pre sec to several Mbps This also supports multiple connection at the same time up to 127 physical devices Including USB hub USB architecture can be used for real time data transfer such as audio and video with Isochronous transfer On the other hand asynchronous transfer type is supported over the same set of wires Other merits of USB architecture are listed below wide range of packet size wide range of device data rates by accommodating packet buffer size and latencies error handling fault recovery mechanism built into protocol support for identification of faulty devices suitable for development of low cost peripherals lowcost cables and connectors easy architecture upgrade with multiple USB host controllers in a system USB BUS TOPOLOGY AND PHYSICAL CONNECTION There are two kinds of cable connectors A type for hub downstream post and B type for device or called as function Node So end users easily connect cable USB cable physically contains 4 line 2 lines for signal D D 2 lines for power supply to bus po
304. on below Table 6 4 HDLC Channel A Special Registers RW R W mode register 0x00000000 R W HDLC control register 0x00000000 HTxFIFOC 0x710 Frame Continue HTxFIFOT 0 714 Terminate R W status register 0x00001040 R W HDLC interrupt enable register 0x00000000 HTxFIFO frame continue register HTxFIFO frame terminate register RW RW RW RW RW RW RW R W HDLC Received Byte Count register 0x00000000 R W HDLC synchronization register 0x0000007E 6 20 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS Table 6 5 HDLC Channel B Special Registers W HTxFIFO frame continue register HTxFIFOC 0x810 Frame Continue HTxFIFOT 0 814 Terminate R W R W R W R W HTxFIFO frame terminate register 2 R W R W R W R W R W R W R W R W R W ELECTRONICS 6 21 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER Table 6 6 HDLC Channel C Special Registers HDLC mode register 0x00000000 HDLC control register 0x00000000 Resses HTxFIFOC 0x910 W Frame Continue HTxFIFOT 0x914 W Frame Terminate HDLC status register 0x00001040 HDLC interrupt enable register 0x00000000 HTxFIFO frame continue register HTxFIFO frame terminate register W W W W W W W W W W W 2 R R R R R R R R R R W W 6 22 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC GLOBAL M
305. on cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STMIA RO R3 R7 Store the contents of registers R3 R7 Starting at the address specified in incrementing the addresses for each word Write back the updated value of RO 3 90 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 16 CONDITIONAL BRANCH 14 13 12 11 8 7 0 15 7 0 8 bit Signed Immediate 11 8 Condition Figure 3 45 Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 3 23 The Conditional Branch Instructions Code THUMB ARM Equivalent Assembler Branch if Z set equal Branch if Z clear not equal Branch if C set unsigned higher or same Branch if C clear unsigned lower Branch if N set negative Branch if N clear positive or zero Branch if V set overflow Branch if V clear no overflow Branch if C set and Z clear unsigned higher Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Branch if N set and V set or N clear and V clear greater or equal ELECTRONICS 3 91 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER
306. ond S Rm Rs Signed multiply amp Accumulate long 32 x 32 64 64 where cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 Examples UMULL R1 R4 R2 R3 UMLALS R1 R5 R2 R3 RA R1 R2 R5 R1 R2 R3 R5 also setting condition codes ELECTRONICS 3 27 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 1211 0 Lu Lor 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add o
307. ondition codes CMP R2 62 Setcondition codes on R2 62 ADD R1 255 R1 255 and set condition codes SUB R6 145 R6 145 and set condition codes 3 70 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 4 ALU OPERATIONS 15 14 13 12 11 10 9 6 5 3 2 0 2 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 3 33 Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair NOTE All instructions in this group set the CPSR condition codes Table 3 11 Summary of Format 4 Instructions THUMB Assembler ARM Equivale ww necra ns mm 1000 TST Rs TST Rd Rs Set condition codes on Rd AND Rs 0 3 7 ELECTRONICS 3 71 INSTRUCTION SET INSTRUCTION CYCLE TIMES 3C4520A RISC MICROCONTROLLER All instructions in this format have an equivalent ARM instruction as shown in Table 3 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples EOR ROR NEG CMP MUL 3 72 R3 R4 R1 RO R5 R3 R2 R6 RO R7 R8 EOR R4 and set condition codes Rotate right R1 by the value in RO store the result in R1 and set condition codes Subtract the contents of R3 from zero store the result in R5 Set condition codes ie R5 R3 Set the condition codes on the result of R2 R6 RO R7
308. only X amp 110 1 control 1 amp 109 1 PnURTS 21 output3 X 110 1 Z amp 108 4 PnUCTS 22 observe only amp 107 BC 1 control 1 106 1 PnUCTS PP22 output3 X 107 1 2 amp 105 BC 4 PnUDCD PP23 104 BC 1 control 123 BC 4 PUTXD PP17 103 1 PnUDCD PP23 ELECTRONICS observe only X amp 1 amp output3 X 104 1 Z amp APPENDIX A A 13 APPENDIX 14 102 4 101 BC 1 100 BC 1 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 1 4 1 PxIREQO PP24 control PxIREQO PP24 PxIREQ1 PP25 control PxIREQ1_PP25 PxIREQ2_PP26 E control PxIREQ2 PP26 PxIREQ3 PP27
309. or which is required to supply or accept the data and a coprocessor will only respond if its number matches the contents of this field The field and the bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors but by convention is the register to be transferred or the first register where more than one is to be transferred and the N bit is used to choose one of two transfer length options For instance N 0 could select the transfer of a single register and N 1 could select the transfer of all the registers for context switching ELECTRONICS 3 53 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER ADDRESSING MODES is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to 1 or subtracted from 0 the base register Rn this calculation may be performed either before P 1 or after P 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be
310. ot allowed when a pre indexed addressing mode is specified or implied An expression evaluating to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining In this case base write back should not be specified An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm lt shift gt offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt offset of lt expression gt bytes Rn Rm lt shift gt offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS INSTRUCTION SET 53 4520 RISC MICROCONTROLLER Examples STR STR LDR LDR LDREQB STR PLACE ELECTRONICS R1 R2 R4 R1 R2 R4 R1 R2 16 R1 R2 R3 LSL 2 R1 R6
311. ou can do this independently of cache enable bit settings Tag RAM is normally cleared by hardware following a power on reset However if you change the cache or memory bank configuration when the cache is being enabled you will have to clear the Tag RAM area using application software NON CACHEABLE AREA CONTROL BIT Although the cache affects the entire system memory it is sometimes necessary to define non cacheable areas when the consistency of data stored in memory and the cache must be ensured To support this the 53 4520 provides a non cacheable area control bit in the address field ADDR 26 If ADDR 26 in the ROM SRAM flash memory DRAM or external I O bank s access address is 0 then the accessed data is cacheable If the ADDR 26 value is 1 the accessed data is non cacheable NOTE The non cacheable area has the same space in memory as the cacheable area To access the non cacheable area you can change the address of the space in memory using non cacheable control bit A SWAP command must be used within a non cacheable area 5 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC CONTROLLERS OVERVIEW The 53 4520 has three high level data link controllers HDLCs to support three channel serial communications The HDLC module supports a CPU data link interface that conforms to the synchronous data link control SDLC and high level data link control HDLC standards In addition the follow
312. ow Detection in the ARM7TDMI 1 Overflow in unsigned multiply with a 32 bit result UMULL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 2 Overflow in signed multiply with a 32 bit result SMULL TEQ BNE Rd Rt Rm Rn Rt Rd ASR 31 overflow Enter with numbers in Ra and Rb Bit to control the division Move Rb until greater than Ra Test for possible subtraction Subtract if ok Put relevant bit into result Shift control bit Halve unless finished Divide result in remainder Ra 3 to 6 cycles 1 cycle and a register 3 to 6 cycles 1 cycle and a register 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 4 to 7 cycles 1 cycle and a register 4 Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE 3 60 Rd Rt Rm Rn Rt Rd ASR 31 overflow 4 to 7 cycles 1 cycle and a register ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL RI Rh Rm Rn 3to6 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BCS overflow 1 cycle and 2 registers 6 Overflow in signed multiply accumulate with a 64 bit result SMULL RI Rh Rm Rn 3to6 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BVS overflow 1 cycle and 2 registers NOTE Overflow checking is not applicable to uns
313. owever if AUTOEN is 1 the transmitter can start transmission only when the state of CTS pin is low The receiver can be synchronized two ways When AUTOEN is 0 and the receiver is transparent mode the receiver searches the RxD for the pattern in HSYNC register Once the pattern in HSYNC is detected on the RxD the data reception will be started This synchronization method is inline synchronization Another synchronization is achieved when AUTOEN is 1 and the receiver is transparent mode In this condition the receiver monitors DCD pin to find a negative transition and then starts to receive data from RxD Once the data reception begins the transition of DCD pin will be ignored until the new synchronization process begins This synchronization method is external synchronization If the RxSTOP in HCON is set to 1 the receiver stops data reception and goes to wait synchronization again ELECTRONICS 6 17 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HARDWARE FLOW CONTROL TxClock Figure 6 7 nCTS already Asserted When nCTS is active and there exists data to be transmitted in Tx FIFO nRTS enters Low allowing data transmission At the beginning of the data is an open flag while at the end a closing flag If the frame being transferred discontinues nRTS goes back to the High after the data transmission is completed TxClock 1 5 13 cycles RTS lt 14 22 cycles
314. p is shown in Figure 2 5 THUNB State ARM State Lo registers Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers ELECTRONICS 2 7 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER Accessing Hi Registers in THUMB State In THUMB state registers R8 R15 the Hi registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range RO R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions For more information refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM7TDMI contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are e Hold information about the most recently performed ALU operation e Control the enabling and disabling of interrupts e Setthe processor operating mode The arrangement of bits is shown in Figure 2 6 Condition Code Flags Reserved Control Bits 31 30 29 28 27 26 L Mode bits Carry Borrow Extend State bit Overflow Zero FIQ disable Negative Less Than FRQ disable Figure 2 6 Program Sta
315. quest acknowledge signals or port by this register set This register default reset value is zero but P23 P16 is one that is UART function The is used to configure external interrupt request signals IOPCONe to configure external DMA request acknowledge signals For the special input ports external interrupt request signal ports S3C4520A provides 3 tap filtering If the input signal levels are same for the three system clock periods that level is taken as input for dedicated signals such as external interrupt requests and external DMA requests NOTE If the port is used for a special function such as an external interrupt request an external DMA request or acknowledge signal HDLC signal UART signal and timer outputs its mode is determined by the IOPCONO 1 2 register not by IOPMODO 1 Table 13 3 IOPCONO Register IOPCONO 0x508 port control register 0 00 0000 13 4 ELECTRONICS 53 4520 RISC MICROCONTROLLER gt 0 xDREQ4 nCTSB port0 0 0 1 xDREQ4 nCTSB 1 xDACK4 HDLCB nDCDB or 0 port 1 xDACK4 nDCDB 2 HDLCB TXDB or port2 0 port2 1 TXDB 3 HDLCB RXDB or port3 0 port3 1 4 HDLCB nDTRB or port4 0 port4 12 nDTRB 5 HDLCB nRTSB or port5 0 port5 12 nRTSB 6 HDLCB TXCB or 0 port6 1 TXCB 7 HDLCB RXCB or port7 0 port7 1 8 n
316. quivalent ARM instruction Examples ADD RO R3 R4 RO R4 and set condition codes on the result SUB R6 R2 6 R6 R2 6 set condition codes ELECTRONICS 3 69 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 7 0 12 11 10 8 To T ua 7 0 Immediate Vale 10 8 Source Destination Register 12 11 Opcode 0 MOV 1 2 ADD 3 SUB Figure 3 32 Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8 bit immediate value The THUMB assembler syntax is shown in Table 3 10 NOTE All instructions in this group set the CPSR condition codes Table 3 10 Summary of Format 3 Instructions 00 MOV Rd Offset8 5 Rd Offset8 Move 8 bit immediate value into Rd CMP Rd Offset8 CMP Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Offset8 ADDS Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rad Offset8 SUBS Rd Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples MOV RO 128 RO 128 and set c
317. r Clock When this clock input is used as the transmitter clock the transmitter shifts data on the positive or negative transition of the TXCA clock input This can be determined by S W selection If you do not use TXCA as the transmitter clock you can use it as an output pin for monitoring internal clocks such as the transmitter clock receiver clock and baud rate generator output clocks IOM 2 Data Receive and Transmit Clock Schmitt Trigger Input HDLC Ch A Receiver Clock When this clock input is used as the receiver clock the receiver samples the data on the positive or negative edge of RXCA clock This can be determined by S W selection This clock can be the source clock of the receiver the baud rate generator or the DPLL General I O Port External DMA Request 3 HDLC Ch A Clear To Send The S3C4520A stores each transition of nCTS to ensure that its occurrence will be acknowledged by the system PP37 xDACK3 General I O Port nDCDA External DMA Acknowledge 3 HDLC Ch A Data Carrier Detected A High level on this pin resets and inhibits the receiver register Data from a previous frame that may remain in the RxFIFO is retained The S3C4520A stores each transition nDCD ELECTRONICS 1 9 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 1 S3C4520A Signal Descriptions Continued General Purpose I O Ports and HDLC B PP2 TXDB 11 B O General I O Port HDLC Ch B Transmit Data See the TXDA description PP3 RXDB 12 B
318. r mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be applied ELECTRONICS 2 9 PROGRAMMER S MODEL 3C4520A RISC MICROCONTROLLER Table 2 1 PSR Mode Bit Values Visible THUMB State Registers Visible ARM State Registers 10001 R7 RO 7 LR fiq SP fiq R14 fiq R8 fiq PC CPSR SPSR fiq PC CPSR SPSR fiq 10010 R7 R0 12 0 LR R14_irq R13_irq PC CPSR SPSR irq PC CPSR SPSR irq 10011 Supervisor R7 RO R12 R0 LR svc SP svc R14 svc R13 svo PC CPSR SPSR_svc PC CPSR SPSR_svc 10111 Abort R7 R0 12 0 LR abt SP abt R14 abt R13 abt PC CPSR SPSR abt PC CPSR SPSR abt 11011 Undefined R7 RO 12 LR und SP und R14 und R13 und PC CPSR SPSR und PC CPSR Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero 2 10 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be
319. r to 20200 and 0 bit of same register to 1 This mode can transmit data between the memory by sending the data which is assigned to the source address register to the destination address register Data transmission size is byte half word or word and it is determined by setting control register 13 1 2 bit Without special USB mode setting of endpoint read write are possible That is by writing an address of USB endpoint into source address register or destination address register read write is possible Here it is impossible to access from another function register or buffer FIFO except USB by DMA controller External DMA Request Mode of 53 4520 has six external DMA request nDREQ sources nXDREQ signal and nXDACK signal can be commonly used with port signals or signal of HDLC channel So it is used by properly setting an IOPC register IOSFRc refer to IOPC External device inserting nXDREQ transmits data by during receiving nXDACK signal Also external DMA request mode is used by setting GDMA mode selection bit 3 2 of control register go 2 b01 It is similar to the basic operation mode of software but it is different in DMA transmitting the data only after receiving nXDREQ signal UART Mode 53 4520 has only one High Speed UART 83C4510 4530 have two UART The that can transmit the data of UART are DMA channel 0 DMA channel 1 DMA channel 2 and the other DMA have no UART If DMA mode selection bit 27001
320. rain Output TXDA HDLC Ch A Transmit Data IOM2 DD 1 B I ptbst4sm IOM 2 Data Downstream Schmitt Trigger RXDA Input HDLC Ch A Receive Data IOM2_BCL 1 O O pob4 2 Bit Clock 768kHz nDTRA HDLC Ch A Data Terminal Ready IOM2_STRB 1 O O pob4 2 Data Strobe nRTSA HDLC Ch A Request To Send 2 FSC 1 ptbsut1 2 Frame Synchronization Clock TXCA HDLC Ch A Transmitter Clock IOM2 DCL 1 1 1 IOM 2 Data Receive and Transmit Clock RXCA HDLC Ch A Receiver Clock PP36 xDREQ 1 ptbst4sm General I O Port 3 nCTSA External DMA Request 3 HDLC Ch A Clear To Send PP37 xDACK 1 ptbst4sm General I O Port 3 nDCDA External DMA Acknowledge 3 HDLC Ch A Data Carrier Detected GPIOs PP2 TXDB 1 B O ptbst4sm General I O Port HDLC B 8 HDLC Ch B Transmit Data PP3 RXDB 1 B I ptbst4sm General I O Port HDLC Ch B Receive Data PP4 nDTRB 1 B O ptbst4sm General I O Port HDLC Ch B Data Terminal Ready PP5 nRTSB 1 B O ptbst4sm General I O Port HDLC Ch B Request To Send PP6 TXCB 1 B B ptbsut1 General Port HDLC Ch B Transmitter Clock PP7 RXCB 1 B I ptbsut1 General Port HDLC Ch B Receiver Clock PPO xDREQ4 1 ptbst4sm General I O Port nCTSB External DMA Request 4 HDLC Ch B Clear To Send PP1 xDREQ4 1 ptbst4sm General I O Port nDCDB External DMA Acknowledge 4 HDLC Ch B Data Carrier Detected 1 14 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1
321. re zero a non divided clock is used 31 Test bit This bit is for factory use only During the normal operation it must always be 0 31 30 16 15 0 15 0 Clock diving value If all bits are 0 non divided clock is used Only one bit can be set in CLKCON 15 0 That is the clock diving value is defined as 1 2 4 8 16 Internal system clock ficLK CLKCON 1 31 Test bit This bit should be always 0 Figure 4 9 Clock Control Register CLKCON 4 22 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER SYSTEM CLOCK The external clock input XCLK can be used to the internal system clock by assigning to CLKSEL pin Using PLL as the internal system clock CLKSEL pin has to be assigned to In this case the internal system clock is XCLK x MF To get 50MHz of system clock a 10 MHz external clock must be used CLKSEL Internal Clock Divider for System Low Power Control Clock CLKCON MCLK NOTES 1 If CLKSEL is 1 the PLL block became to the state of power down 2 MF means multiplication factor Figure 4 10 System Clock Circuit ELECTRONICS 4 23 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER USB 48 MHz CLOCK The external clock input USB CK can be used to the USB 48 MHz clock by assigning Vpp to USB_CKS pin Using PLL as the USB 48 MHz clock USB CKS pin has to be assigned to Vas In this case the USB 48 MHz clock is USB CK x MF To get 48MHz of USB clock a 10 MHz extern
322. register HMODE and the HDLC control register HCON must be programmed before the HDLC is enabled To enable the HDLC module you must write 1 to the receiver enable bit and or the transmitter enable bit During normal operation you can disable the receiver the transmitter by writing a 0 to the or bit respectively You can disable the receiver and HRXFIFO or the transmitter and HTxFIFO by writing 1 to the RxRS or TxRS bit respectively ELECTRONICS 6 11 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC DATA ENCODING DECODING Data encoding is utilized to allow the transmission of clock and data information over the same medium This saves the need to transmit clocks and data over a separate medium as would normally be required for synchronous data The HDLC provides four different data encoding methods selected by bits in HMODE 14 12 An example of these four encoding methods is shown in figure 6 5 Bit Cell Level High 1 Low 0 Data NRZ No Change 1 NRZI Change 0 Bit Center Transition 1 Transition 1 Biphase Mark No Transition 0 FMO No Transition 1 Biphase Space Transition 0 Manchester High Low 1 Low gt High 0 NRZ NRZI Type TxClock Data RxClock FMO FM1 Manchester type TxClock Data RxClock Figure 6 5 Data Encoding Methods and Timing Diagrams 6 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER
323. ress bits except row and column address among the 23 bit internal address bus can be assigned to Bank select address BA for SDRAM See the SDRAM interface example Figure 4 29 ELECTRONICS 4 45 SYSTEM MANAGER Available Samsung SDRAM Components for S3C4520A Components 53 4520 can support below SDRAM configuration for 1 bank e 4MBytes to 1 bank gt 2 x e 8MBytes to 1 bank gt 4x e 16MBytes to 1bank gt 2 x e 32MBytes to 1bank 5 4 x You can select any combination among them 1Mx16 with 2banks 2Mx8 with 2banks 4Mx16 with 2 4banks 8Mx8 with 2 4banks SDRAM components that are available are as follow x4 SDRAM whose capacity is larger than 16M SDRAM is not supported at S3C4520A 16M bit SDRAM 4 4 with 2banks supported 2Mx8 with 2banks supported 1Mx16 with 2banks supported 64M bit 2Banks SDRAM 16Mx 4 with 2banks not supported 8Mx8 with 2banks supported 4Mx16 with 2banks supported 64M bit 4Banks SDRAM 16 4 with 4banks not supported 8 8 with 4banks supported 4 16 with 4banks supported 4 46 CA0 CA9 8 CA0 CA7 RAO RA12 CA0 CA9 RAO RA12 CA0 CAB8 RAO RA12 CA0 CA7 RAO RA11 CA0 CA9 RAO RA11 CA0 CA8 RAO RA11 CA0 CA7 53 4520 RISC MICROCONTROLLER ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER Relationship Between CAN Column Address Number and Ad
324. ribes the S3C4520A electrical data ABSOLUTE MAXIMUM RATINGS Table 15 1 Absolute Maximum Ratings Symb Um DC input Voltage Vin 3 8 V I O 0 3 to Vpp 0 3 5 V tolerant 0 3 to 5 5 DC input current lin 10 mA Operating temperature 0 to 70 Storage temperature 40 to 125 RECOMMENDED OPERATING CONDITIONS Table 15 2 Recommended Operating Conditions Symbol une Supply Voltage 3 0 to 3 6 Oscillator frequency 10 to 50 External Loop Filter Capacitance 820 Commercial temperature NOTE Itis strongly recommended that all the supply pins be powered from the same source to avoid power latch up ELECTRONICS 15 1 ELECTRICAL DATA 3C4520A RISC MICROCONTROLLER D C ELECTRICAL CHARACTERISTICS Table 15 3 D C Electrical Characteristics Vpp 3 3V 0 3 V 5 0 25 V T4 0 to 70 C di case of 5 V tolerant I O SS eT eS eene High level input voltage LVCMOS interface Low level input voltage LVCMOS V V interface Swichingtheshod VT LVCMOS 14 V Schmitt trigger positive going threshold VT LVCMOS 20 Schmitt trigger negative going VT LVCMOS threshold High level input current Input buffer Input buffer Input buffer with pull up Low level input current Input buffer Input buffer with pull down High level output voltage Type v to lou 1 B1 k
325. rnal system bus acquistion time T signal falls at negative edge MCLK clock after source data is valid Figure 9 10 Single and One Data Burst Mode Timing ELECTRONICS 9 15 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER SINGLE AND FOUR DATA BURST MODE GDMACON 11 0 9 1 DREQ amp DACK signals are active low In the four data burst mode COUNT Register GDMA CNT value decreases by 1 after 4 data transfer Recommand deasserted time In MCLK nxDREQ nxDACK GDMA CNT NOTE Address order is source addressO gt source address1 gt source address 2 gt source address3 destination addressO gt destination address1 destination address2 gt destination address3 and Data order is source data0 gt source data1 gt source data2 gt source data3 gt destination data0 gt destination data1 gt destination data2 gt destination data3 Figure 9 11 Single and Four Data Burst Mode Timing 9 16 ELECTRONICS 3C4520A RISC MICROCONTROLLER DMA CONTROLLER BLOCK AND ONE DATA BURST MODE GDMACON 11 1 9 0 DREQ and DACK signals are active low transfers data from DREQ signal is active till COUNT Register consumes Recommand deasserted time In MCLK nxDREQ nxDACK Source Destination Source Destination Address Data data data data data NOTE fisin the block mode GDMAC starts to operate with first DREQ signal So in the ideal case GDMAC don t care th
326. roller 16 bit Bus Cache with Refresh Control 4 Word 4 Bank Write External Buffer General Purpose DMA 0 1 2 3 4 5 Device lt HDLC A S T Transceiver lt gt HDLC C General I O ports gt HDLC C Interruput Controller lt High Speed UART 32 bit Timer 0 1 Full Speed lt gt Watchdog Timer gt USB_XCKI PLES PLL 1 USB XCKO USB CLKSEL USB FILTER Figure 1 1 53 4520 Block Diagram ELECTRONICS PRODUCT OVERVIEW 53 4520 RISC MICROCONTROLLER 107 XDATA7 106 XDATA6 105 XDATA5 104 XDATA4 103 102 XDATA2 100 XDATA1 99 XDATAO 98 ADDR21 97 ADDR20 96 ADDR19 95 ADDR18 93 ADDR17 92 ADDR16 91 ADDR15 90 ADDR14 89 ADDR13 88 ADDR12 86 ADDR11 85 ADDR10 AP 84 ADDR9 83 ADDR8 82 ADDR7 81 ADDR6 79 ADDR5 78 ADDR4 77 ADDR3 76 ADDR2 75 ADDR1 74 ADDRO VDD XDATA8 XDATA9 XDATA10 XDATA11 XDATA12 XDATA13 VSS XDATA14 5 UCLK PP16 UTXD PP17 URXD PP18 nUDSR PP19 VDD nUDTR PP20 nURTS PP21 nUCTS PP22 nUDCD PP23 PP24 xINTREQO PP25 xINTREQ1 VSS PP26 xINTREQ2 PP27 xINTREQ3 PP28 TOUTO PP29 TOUT1 PP30 xDREQO PP31 xDACKO VDD PP32 xDREQ1 PP33 xDACK1 PP34 xDREQ2 PP35 xDACK2 PP36 xDREQ3 nCTSA PP37 xDACK3 nDCDA VSS VSS nWBE1 DQM1 nWBE0 DQMO nOE BOSIZE nRCS1 nRCSO VDD nEWAIT nECS3 nE
327. ropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction Examples The following sequence performs a mode change MRS RO CPSR Take a copy of the CPSR BIC RO RO 0x1F Clear the mode bits ORR RO RO new_mode Select new mode MSR CPSR RO Write back the modified CPSR When the aim is simply to change the condition code flags in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR_flg 0xFO000000 Set all the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as sequential S cycle ELECTRONICS 3 21 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER ASSEMBLER SYNTAX e MRS transfer PSR contents to a register Rd lt psr gt e MSR transfer register contents to PSR MSR cond lt psr gt Rm e MSR transfer register contents to PSR flag bits only MSR cond lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp flags respectively e MSR transfer immediate value to PSR
328. rrier Detected General I O Port General PP24 27 4 ptbst4sm General I O ports Purpose xINTREQ 3 0 External Interrupt Request lines Ports PP28 TOUTO 1 ptbst4sm General I O port 12 Timer 0 out PP29 TOUT1 1 ptbst4sm General I O port Timer 1 out PP30 xDREQO 2 O B ptbst4sm General I O ports PP31 xDACKO External DMA Request 0 and Acknowledge 0 PP32 xDREQ1 2 O B ptbst4sm General I O ports PP33 xDACK1 External DMA Request 1 and Acknowledge 1 PP34 xDREQ2 2 O B ptbst4sm General I O ports PP35 xDACK2 External DMA Request 2 and Acknowledge 2 1 16 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 3 53 4520 PAD Pad Type I O Current Cell Type Slew Rate Drive Control pic 1 LVCMOS Level LVCMOS Schmitt Trigger Level pticu LVCMOS Level 5V tolerant Pull up resistor LVCMOS Level 5V tolerant Pull down resistor pm Analog input with separate ulk bias 4 LVCMOS Normal Buffer LVCMOS Tri State Buffer 5V tolerant ptbsut6 Tri State Buffer Pull up resistor A A A A i 4 LVCMOS Tri State Buffer 5V tolerant ES vo O O 4 LVCMOS Level Open Drain Buffer LVCMOS Schmit Trigger Level 5V tolerant Medium Tri State Buffer LVCMOS Schmit Trigger Level 5V tolerant Tri State Buffer Pull up resistor pbusbts VO f FulSpedUSBBufer NOTE ptic
329. rrived Message MRxEOM 1 The EOM has arrived on the monitor channel which indicates that the current message transfer has concluded Monitor Channel Collision Detected 0 normal MCOL 1 The monitor channel collision has occurred Monitor Channel Tx Buffer Available 0 Cleared when the IOM2MTD is written MTxBA 1 A new data can be written to IOM2MTD Monitor Channel Rx Buffer Available 0 Cleared when the IOM2MRD is read MRxBA 1 A new data has received on the monitor channel 9 Monitor Channel Tx Abort Received 0 Normal MTxABT 1 Mointor channel Tx abort is received When the Rx channel receives an abrupt disruption of handshake procedure not a normal termination of handshake during monitor channel transmission this bit is set to 1 10 IC Channel Buffer Available 0 Cleared when the IOM2ICRD is read ICBA 1 A new data has received on the IC channel 11 2 Bus Alive ALIVE 0 The IOM2 bus is in the inactive state DCL 1 1 The 2 bus is in the active state DCLK is clocking 12 new frame sync NEWFSC 0 cleared by CPU 1 FSC detected 2 3 5 6 7 8 Monitor Channel Receive Abort 0 normal MRxABT 1 The remote receiver has sent abort request because of transmission errors In this case the local transmitter should respond to this by sending EOM MX 1 during more than two frames 07 7 12 ELECTRONICS 3C4520A RISC MICROCONTROLLER IOM2 CONTROLLER 31 30 29
330. s 011 3 cycles 8 6 Chip selection hold time on oOE tcoHo tcoH2 100 4 cycles 101 5 cycle 110 6 cycle 111 2 7 cycles 24 22 tcoH1 000 0 cycle 001 1 cycle 010 2 cycles 011 cycles 11 9 Access cycles nOE low time tacco tACC2 27 25 1 tacc3 000 0 cycle 001 1 cycle 010 2 cycles 011 3 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles 13 12 Data Bus Width DWO DW2 29 28 DW1 DW3 00 Disable 01 Byte 8 bits 10 Half word 16 bits 11 Disable Figure 4 13 External I O Access Control Registers EXTACONO EXTACON1 ELECTRONICS 4 27 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER o 5 lt nEWAIT 1 tacc 4 tcos 0 tacs 1 Figure 4 14 External Read Timing The nEWAIT Deassertion timing depends on the applied Ext I O devices ELECTRONICS 4 28 SYSTEM MANAGER 53 4520 RISC MICROCONTROLLER o o 79 lt nEWAIT 7 tcos 0 tacs 0 Figure 4 15 External I O Read Timing with nEWAIT 9 tace 4 29 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER o 5 lt nEWAIT 1 tcos 0 tacs 4 Figure 4 16 External 1 0 Write Timing 1 ELECTRONICS 4 30 SYSTEM MANAGER 53 4520 RISC MICROCONTROLLER
331. s CMP Hd Rs Compare a register in the range 8 15 with a register in the range 0 7 Set the condition code flags on the result 01 1 1 CMP Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition code flags on the result 10 1 MOV Rd Hs MOV Rd Hs Move a value from a register in the range 8 15 to a register in the range 0 7 10 1 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 MOV Hd Hs MOV Hd Hs Move a value between two registers in the range 8 15 BX Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction THE BX INSTRUCTION BX performs a branch to a routine whose start address is specified in a Lo or Hi register 0 of the address determines the processor state on entry to the routine Bit 0 0 Causes the processor to enter ARM state Bit0 1 Causes the processor to enter THUMB state NOTE The action of H1 1 for this instruction is undefined and should not be used 3 74 ELECTRONICS 3C4520A RISC MICROCONTROLLER Examples Hi Register Operations ADD PC R5 R4 R12 MOV R15 R
332. s cycle 0 7 wait cycles e 4 word depth write buffer e Cost effective memory to peripheral DMA interface Unified Instruction Data Cache e Two way set associative unified 4 Kbyte cache e Support for LRU least recently used protocol General Purpose DMAs e 6 channel general purpose DMAs e be used for data transfer from memory to memory or I O and from UART or HDLCs to memory or I O or vice versa e The DMA request sources are the external DMA request 0 5 UART and HDLC A B C 1 2 53 4520 RISC MICROCONTROLLER 2 Interface e OM2 TE mode e TIC bus support e Monitor channel collision control Three HDLCs HDLC protocol features Flag detection and synchronization Zero insertion and deletion Idle detection and transmission FCS encoding and detection 16 bit Abort detection and transmission e Address search mode expandable to 4 bytes e Selectable CRC No CRC mode e Automatic CRC generator preset e Digital PLL block for clock recovery e Programmable baud rate generator e NRZ NRZI FM Manchester data formats for Tx Rx e Loop back and auto echo modes e 8 word 8 x 32 bit Tx Rx FIFOs with programmable trigger level 1 or 4 word e GDMA based or Interrupt based operation Data alignment logic e Endian translation e Programmable interrupts e Modem interface e Hardware flow control e HDLC frame length based on octets e Transparant mode ELECTRONI
333. s placed in PC the address of the instruction following the BL is placed in LR and bit 0 of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction ELECTRONICS 3 95 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 3 26 The BL Instruction THUMB Assembler ARMEquivalen EX BL label LR PC OffsetHigh 12 temp next instruction address PC LR OffsetLow lt lt 1 LR temp 1 Examples BL faraway Unconditionally Branch to faraway next E and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned 3 96 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than us
334. s used to determine the shift amount Rs can be any general register other than R15 If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted result will exactly match that of an instruction specified shift with the same value and shift operation If the value in the byte is 32 or more the result will be a logical extension of the shift described above LSL by 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm NO a O P gt ROR by n where n is greater than 32 will give the same result and carry out as ROR by n 32 therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 15 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shi
335. sary BEQ divide by zero Get abs value of R1 by xoring with OXFFFFFFFF and adding 1 if negative ASR RO R1 31 Get 0 or 1 in R3 depending on sign of EOR R1 RO EOR with 1 OXFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value Save signs 0 or 1 in RO amp R2 for later use in determining sign of quotient amp remainder PUSH R2 Justification shift 1 bit at a time until divisor RO value is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes LSR RO R1 1 MOV R2 R3 B just LSL R2 1 0 CMP R2 RO BLS just MOV RO 0 Set accumulator to 0 B FTO Branch into division loop div_ LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 If successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 R3 Terminate when R2 R3 ie we have just BNE div 1 tested subtracting the ones value fix up the signs of the quotient RO and remainder R1 POP R2 R3 Get dividend divisor signs back EOR R3 R2 Result sign EOR RO R3 Negate if result sign 1 SUB RO R3 EOR R1 R2 Negate remainder if dividend sign 1 SUB R2 MOV Ir 3 98 ELECTRONICS INSTRUCTION SET 3C4520A RISC MICROCONTROLLER ARM Code signed_divide ANDS RSBMI EORS ip bit 31 sign of result bit 30 sign of a2 RSBCS a4 a1 amp 80000000
336. signal read active delay 7 46 9 27 DRAM CAS signal release read delay time 7 41 9 21 N DRAM CAS signal write active delay 746 N 9 27 N DRAM CAS signal release write delay time 7 41 9 21 DRAM bank write enable delay time 8 49 9 71 DRAM bank out enable delay time 17 66 N 19 35 N External I O bank chip select delay time 16 39 N 19 13 N DRAM write data delay time DRAM 0 36 0 95 DRAM write data hold time DRAM 0 13 0 81 External wait setup time External wait hold time NOTE The value N is calculated from MCLKO falling The others are from MCLKO rising 10 79 2 08 5 87 5 64 N 5 81 N 10 41 12 57 16 31 N 7 39 N 17 56 8 83 1 19 3 81 7 35 N 11 02 13 02 N 13 44 N 10 56 15 23 18 80 N 9 24 N 19 33 11 65 1 66 7 83 9 27 N ELECTRONICS ns 15 3 ELECTRICAL DATA 3C4520A RISC MICROCONTROLLER NOTES 15 4 ELECTRONICS 53 4520 RISC MICROCONTROLLER MECHANICAL DATA MECHANICAL DATA OVERVIEW 22 00 BSC WAX 144 LQFP 2020 22 00 BSC 20 00 BSC 0 60 0 15 Jr x 0 05 0 15 1 40 x 0 05 1 60 MAX NOTE Dimensions are in millimeters Figure 16 1 53 4520 144 pin LQFP package ELECTRONICS 16 1 MECHANICAL DATA 3C4520A RISC MICROCONTROLLER NOTES 16 2 ELECTRONICS 53 4520 RISC MICROCONTROLLER APPENDIX A APPENDIX A TEST ACCESS PORT This section describes relevent sect
337. sing the reset Rx status 6 26 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS Table 6 10 HCON Register Description Continued Bit Bit Name Description Number BRG enable BRGEN This bit controls the operation of the baud rate generator To enable the counter set the BRGEN bit to 1 To inhibit counting clear the bit to 0 Tx 4 word mode When this bit is 0 and TxFA bit in status register is 1 it is indicated that Tx4WD Tx FIFO is empty for 1 word It means that 1 word data can be loaded to Tx FIFO Similarly when this bit is 1 the same status register bit indicate that 4 words of data can be loaded to Tx FIFO without reading the status bit for a second time Specifically the status register bit affected by the 1 word or 4 word transfer setting are the transmit data available TxFA bit Rx 4 word mode When this bit is 0 and the RxFA bit in the status register is 1 it is Rx4WD indicated that Rx FIFO has 1 word data It means that 1 word data can be moved to memory Similarly when this bit is 1 the same status register bit indicates that 4 words of data can be moved in the memory without reading the status bit for a second time Specifically the status register bit affected by the 1 word or 4 word transfer setting are the receive data available RxFA bit and the residue bytes status bits RxRB 3 0 Tx widget Alignment These bits determine how many bytes are invalid in t
338. ss 3 R W HDLC mask register 0x0000 0000 R W Received Byte Count Register 0x0000 0000 R W Synchronization Register 0x0000 007E 0x0080 07FF 0x0000 0000 R W HDLC Baud rate generate time constant 0x0000 0000 MEE EM EE EE E up ELECTRONICS 1 25 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 5 S3C4520A Special Registers Continued Group Registers Offset Description Resetvak ae RW FF oen w frame continue register oen w rame terminate register HRXFIFO HDLC RxEIFO entry register 0000 0006 07 1 26 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW Table 1 5 S3C4520A Special Registers Continued Group Registers onset Description Resetvak ELECTRONICS 1 27 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER Table 1 5 S3C4520A Special Registers Concluded Group Registers onset AW Description Reservar oreo Aw use use oree wusstparrr uso oreo Rw usstparrr use ore mw ustmmro 11 1 28 ELECTRONICS 53 4520 RISC MICROCONTROLLER PROGRAMMER S MODEL PROGRAMMER S MODEL OVERVIEW 53 4520 was developed using the advanced ARM7TDMI core designed by advanced RISC machines Ltd Processor Operating States Fro
339. ss to the FIFO is invalidated this bit is cleared The MCU writes 1 to this bit at the same time it clears USBORDY if it decodes a invalid token The USB issues a STALL handshake to the current control transfer The MCU writes a 0 to end the STALL condition The MCU writes a 1 to this bit to clear USBORDY The MCU writes 1 to this bit to clear USBSETEND ELECTRONICS 53 4520 RISC MICROCONTROLLER ELECTRONICS 0 USB Out Packet Ready 0 Not received packet or in IN mode 1 Revceived packet from host 1 USB IN Packet Ready 0 Not yet loaded packet to EPO FIFO or OUT mode 1 Loading packet to EPO FIFO completed 2 USB Sent STALL 0 No stall token is transmitted 1 Control transaction is ended due to protocol violation 3 USB Data END 0 Not data end state 1 Data end state 4 USB Setup END 0 Normal operation state 1 Setup end state 5 USB Send STALL 0 Normal operation state 1 Go to stall token transmit state 6 USB Serviced Out Ready 0 No operation 1 USBORDY bit clear 7 USB Serviced Setup End 0 No operation 1 USBSETEND bit clear 31 8 Reserved Figure 11 16 USBICSR1 Register aamo ouoc i UO ouoc o rr Ao0uU0o0uoc jo Ozm muooc XUxIz uoc omxJouoc o USB 11 33 USB 3C4520A RISC MICROCONTROLLER USB IN CSR REGISTER 1 ENDPOINT1 ENDPOINT4 This register maintains the status bits for IN endpoints endpoi
340. ss whose LSB is 0 4 8 C X Don t care CAS1 0 nWBE1 0 0 means active and 1 means inactive Table 4 3 Word Access Store Operation with Big Endian STORE CPU Reg gt gt External Memory Bit Num 31 0 31 0 CPU Register Data abcd abcd Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 CPU Data Bus abcd abcd abcd abcd abcd abcd Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 Internal SD Bus abcd abcd abcd abcd abcd abcd CAS1 0 nWBE1 0 XX00 XX00 XXX0 XXX0 XXX0 XXX0 Bit Num 15 0 15 0 70 15 0 15 0 Ext Memory Data ab cd a Table 4 4 Word Access Load Operation with Big Endian LOAD CPU Reg lt External Memory CPU Register Data abcd abcd Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 CPU Data Bus abXX abcd abXX abcX abcd Bit Num 31 0 31 0 31 0 31 0 31 0 31 0 Internal SD Bus abXX abcd abXX abcX abcd CAS1 0 nWBE1 0 XX00 XX00 XXX0 XXX0 XXX0 XXX0 Bit Num 15 0 15 0 XDATA ab cd Bit Num 15 0 15 0 Ext Memory Data ab cd a d ELECTRONICS 4 9 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER Table 4 5 and 4 6 Using big endian and half word access Program Data path between register and external memory HA Address whose LSB is 0 2 4 6 8 X Don t care CAS1 0 nWBE1 0 0 means active and 1 means inactive Table 4 5 Half Word Access Store Operation with Big Endian STORE CPU EN NAE External Memory Ext Memory Type Half word word Bit Num 31 0 31 0 CPU Register Data abc
341. st coproc 1 to do operation 10 on CR2 and and put the result in 2 5 1 2 3 2 If Z flag is set request coproc 2 to do operation 5 type 2 on CR2 and and put the result in ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC or store STC a subset of a coprocessor s registers directly to memory ARM7TDM is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 28 27 25 24 23 22 21 20 19 16 15 12 11 0 Lu em ow Do 99 _ 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions THE COPROCESSOR FIELDS The CP field is used to identify the coprocess
342. ster Registers AW Description Reset Value NOTE Recognize one 32 bit address NOTE Recognize a single 8 bit address and the 32 bit broadcast address Figure 6 18 Address Recognition ELECTRONICS 6 43 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 32 1 0 First byte Second byte Third byte Fourth byte Station address byte register and MASK register 31 24 First address byte 23 16 Second address byte 15 8 Third address byte 7 0 Fourth address byte Figure 6 19 HDLC Station Address and HMASK Register 6 44 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS RECEIVED BYTE COUNT REGISTER When the receiver is serviced by DMA the DMA moves the data from RxFIFO to memory but the DMA doesn t count the number of byte received The Received Byte Count register RBCNT keeps the exact byte count of frame servieced by DMA To receive new frame this register should be cleared to 0 Table 6 19 Received Byte Count Register Registers Offset Description ResetVaue 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 87 65 4 32 1 0 TET TET TTT TT Received Byte count 15 0 Receive Byte Count Figure 6 20 Received Byte Count Register ELECTRONICS 6 45 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC SYNCHRONIZATION REGISTER When the receiver is operated in transparent and
343. structions e Twelve data processing instructions which is a subset of the standard ARM data processing instructions e Eight load and store register instructions e Four load and store multiple instructions NOTE Each 16 bit THUMB instruction has a corresponding 32 bit ARM instruction with an identical processing model The 32 bit ARM instruction set and the 16 bit THUMB instruction set are good targets for compilers of many different high level languages When an assembly code is required for critical code segments the ARM programming technique is straightforward unlike that of some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies Pipelining is employed so that all parts of the processor and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and the third instruction is being fetched from memory 1 20 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW MEMORY INTERFACE The CPU memory interface has been designed to help the highest performance potential to be realized without incurring high costs in the memory system Speed critical control signals are pipelined so that system control functions can be implemented in standard low power logic These pipelined control signals allow you to fully exploit the fast local access modes offered by industry standard dynamic RAMs OPERATING
344. supplied boot code that is stored in the external ROM This code is located at address 0 in the system memory map When the boot code i e ROM program is executed it performs various system initialization tasks and reconfigures the system memory map according to the application s actual external memory and device configuration The initial system memory map following system start up is shown in Figure 4 2 4 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER OX1FFFFFF Special Function Registers 0 1 8000 Undefined Area 32 MBytes SA 24 0 0X1000000 ROM SRAM FLASH Bank 0 Area Non Accessable ROM SRAM FLASH Bank 0 Area 4 M 21 0 Accessable 0X0000000 Figure 4 2 Initial System Memory Map After Reset Table 4 1 System Manager Registers Registers Offset RW Description Reset Value POCODE oxoo4 Product Code and Revision Number register 4520 0010 ROMCONO DRAMCONO DRAMCONI REFEXTCON ELECTRONICS 4 5 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER EXTERNAL ADDRESS TRANSLATION METHOD DEPENDS ON THE WIDTH OF EXTERNAL MEMORY The S3C4520A address bus is in some respects different than the bus used in other standard CPUs Based on the required data bus width of each memory bank the internal system address bus is shifted out to an external address bus ADDR 21 0 This means that the memory control signals such as nRAS 1 0 nCAS 1 0
345. t aligned Get other shift amount Combine two halves to get result 3 63 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM7TDMI core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restrictions by 16 bit format is fully notified for using the Thumb instructions FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure 15 14 13 12 11 ofo of me Move Shifted register ee Add subtrac Offset8 Move compare add subtract immediate Bee ALU operation H1 H2 Rs Hs Hi regiter operations branch exchange Words PC relative load Load store with register offset HS Load store sign extended byte halfword Offset5 Load store with immediate offset toe tet Load store halfword Ee SP relative load store wo Load adress swoa7 Add offset stack pointer Rit Push pop register Multiple loadistore Conditional branch
346. t by hardware When valid data byte is written to the frame continue address the data valid pointer is set but the last byte pointer is not set When valid data byte is written to the frame terminate address the data valid pointer and last byte pointer are set together To reset these pointers you write 1 to either the TxABT bit or the TxRS bit in the HCON register The pointers continue shifting through the FIFO When the transmitter detects a positive transition in the data valid pointer at the last location of the FIFO it initiates a frame with an opening flag When it detects a negative transition in the last byte pointer at the last location of the FIFO it closes the frame appending the CRC and a closing flag follows The status of the Tx FIFO is indicated by the transmitter FIFO register available TxFA status bit When TxFA 1 the Tx FIFO is available for loading data and data can be loaded into it This function is controlled by the Tx4WD bit The HTxFIFO is reset by writing a 1 to the Tx reset or the TxABT bit or by the nRESET During a reset operation the TxFA status bit is suppressed and data loading is inhibited TxFIFO Data Valid 4 bit Last 1 bit NoCRC Preamble Tx Data Figure 6 14 HDLC Tx FIFO Function Diagram ELECTRONICS 6 39 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC RX FIFO HRXFIFO The Rx FIFO consists of eight 32 bit registers that are used for the buffer storage
347. tains bits for all device signals and clock pins and for associated control signals INSTRUCTION REGISTER The instruction register is four bits in length There is no parity bit The fixed value 0001 is loaded into the instruction register during the CAPTURE IR controller state The TAP machines supports the following public instructions However the S3C4520A boundary scan logic only supports EXTEST IDCODE BYPASS and SAMPLE PRELOAD instructions The remaining instructions are used for ARM7TDMI core testing and debugging Table A 1 Public Instructions Code ELECTRONICS A 3 APPENDIX 53 4520 RISC MICROCONTROLLER BOUNDARY SCAN DEFINITION LANGUAGE Samsung Electronics Co 53 4520 01 BSDL Version 1 0 02 08 01 Package Type 144 LQFP 2020AN entity ks32c50200 is generic PHYSICAL PIN MAP string 144 LQFP 2020AN port PnRESET PXCLK in bit PCLKSEL in bit PCLKOEN in bit PTMODE in bit PLITTLE in bit PTCK in bit PTMS in bit PTDI in bit PnTRST in bit PnEWAIT in bit PBOSIZE in bit PUSB_CK in bit PUSB CKS PRXCA_DCL in bit PXDATAO inout bit PXDATA1 bit PXDATA2 bit inout bit PXDATA4 jnout bit PXDATA5 inout bit PXDATA6 inout bit PXDATA7 bit PXDATA8 inout bit PXDATA9 inout bit PXDATA10 inout bit A 4 ELECTRONICS 3C4520A
348. tate and enters Supervisor SVC mode The THUMB assembler syntax for this instruction is shown below Table 3 24 The SWI Instruction THUMB Assembler ARM Equivalent SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value 8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 24 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples SWI 18 Take the software interrupt exception Enter Supervisor mode with 18 as the requested SWI number ELECTRONICS 3 93 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 18 UNCONDITIONAL BRANCH 15 14 13 10 E 12 11 om 10 0 Immediate Value Figure 3 47 Format 18 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction Table 3 25 Summary of Branch Instruction THUMB Assembler ARMEquivalent Action B label BAL label halfword offset Branch PC relative Offset11 lt lt 1
349. te value at the address into Rd NOTE For word accesses 0 the value specified by 1 is a full 7 bit address but must be word aligned ie with bits 1 0 set to 0 since the assembler places Imm gt gt 2 the Offset5 field ELECTRONICS 3 81 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 16 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 0 13 Store the lower 8 bits of R1 at the address formed by adding 13 to RO Note that the THUMB opcode will contain 13 as the Offset5 value 3 82 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 10 LOAD STORE HALFWORD 10 6 5 3 2 0 14 ua I 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 3 39 Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory Addresses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 3 17 Table 3 17 Halfword Data Transfer Instructions THUMB Assemb
350. ter INTMOD 0 400 Interrupt mode register 0x00000000 31 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 mmo 9 6 3 EEE ESSE ES ES ES ES EE ESS 22 0 Interrupt mode bits NOTE Each ofthe 23 bits in the interrupt mode enable register INTMOD corresponds to an interrupt source When the source interrupt mode bit is set to 1 the interrupt is processed by the ARM7TDMI core in FIQ fast interrupt mode Otherwise it is processed in IRQ mode normal interrupt The 23 interrupt sources are mapped as follows 22 WatchDog timer 21 Timer 1 interrupt 20 Timer 0 interrupt 19 GDMA channel 5 interrupt 18 GDMA channel 4 interrupt 17 GDMA channel 3 interrupt 16 GDMA channel 2 interrupt 15 GDMA channel 1 interrupt 14 GDMA channel 0 interrupt 13 USB interrupt 12 IOM 2 interrupt 11 HDLC channel C Rx interrupt 10 HDLC channel C Tx interrupt 9 HDLC channel B Rx interrupt 8 HDLC channel B Tx interrupt 7 HDLC channel A Rx interrupt 6 HDLC channel A Tx interrupt 5 UART receive and error interrupt 4 UART transmit interrupt 3 External interrupt 3 2 External interrupt 2 1 External interrupt 1 0 External interrupt 0 Figure 14 1 Interrupt Mode Register INTMOD ELECTRONICS 14 3 INTERRUPT CONTROLLER 3C4520A RISC MICROCONTROLLER INTERRUPT PENDING REGISTER The interrupt pending register INTPND contains interrupt pending bits for each
351. ter USTAT 18 should be 1 This is to prevent overwriting of transmit data that may already be present in the UTXBUF Whenever the UTXBUF is written with a new value the transmit register empty bit USTAT 18 is automatically cleared to O 31 8765 43 2 1 0 7 0 Transmit data for UART Figure 10 5 UART Transmit Buffer Register 10 16 ELECTRONICS 3C4520A RISC MICROCONTROLLER UART UART RECEIVE BUFFER REGISTER 3 4520 has 32 byte Receive FIFO and the bottom of FIFO is URXBUF All data to be received are stored in this register at first in FIFO mode if next buffer has invalid data then shifted to next buffer But in non FIFO mode a new received data will be moved to URXBUF The UART receive buffer registers URXBUF contain an 8 bit data value to be received over the UART channel Table 10 10 UXRBUF Registers URXBUF 0XE10 UART receive buffer register Table 10 11 UART Receive Register Description Bit Number Reset Value 7 0 Receive data This field contains the data received over the single channel UART When the UART finishes receiving a data frame the receive data ready bit in the UART status register USTAT 1 should be 1 This prevents reading invalid receive data that may already be present in the URXBUF Whenever the URXBUF is read the receive data valid bit USTAT 1 is automatically cleared to 31 8 765 43 2 1 0 peeve Dats 7 0 Receive data for UART Figure 10 6 UART Rece
352. ter 0x00000000 HBRGTCC 0x91C R W HDLCC BRG Time Constant Register 0x00000000 The HDLC BRG time constant register value can be changed at any time but the new value does not take effect until the next time the constant is loaded into the down counter No attempt is made to synchronize the loading of the time constant into HBRGTC while the clock is driving the down counter For this reason you should first disable the baud rate generator before loading the new time constant into the HBRGTC register The formula for determining the appropriate time constant for a given baud rate is shown below The desired rate is shown in bits per second This formula shows how the counter decrements from N down to zero plus one cycles for reloading the time constant This value is then fed to a toggle flip flop to generate the square wave output BRGOUT1 MCLK2 or RXC CNTO 1 16 1 BRGOUT2 BRGOUT1 1 or 16 or 32 according to CNT2 value of the HBRGTC 31 16 15 43210 1 0 Time constant value for CNT2 00 divide by 1 01 divide by 16 10 divide by 32 3 2 Time constant value for CNT1 00 divide by 1 01 divide by 16 15 4 Time constant value for CNTO Figure 6 16 HDLC BRG Time Constant Register ELECTRONICS 6 41 HDLC CONTROLLERS 3C4520A RISC MICROCONTROLLER HDLC PREAMBLE CONSTANT REGISTER HPRMB The register is used to meet the DPLL requirements for phase locking The preamble pattern is transmitted as ma
353. ter Description Continued Bit Number Reset Value Overrun Error OER This bit automatically set to 1 whenever an overrun error occurs during a serial data receive operation When URXBUF has a previous valid data but a new received data is going to be written into URXBUF during non FIFO mode and when a new received data is going to be written into RXFIFO with FIFO full during FIFO mode USTAT 4 is set 1 If the OER interrupt enable bit UINTEN 4 is 1 a interrupt is generated when a overrun error occurs You can clear this bit by writing 1 to this bit Control Character Detect USTAT 5 is automatically set to 1 to indicate that a control character CCD has been received If the CCD interrupt enable bit UINTEN 5 is 1 an interrupt is generated when a control character is detected You can clear this bit by writing 1 to this bit Data carrier Detect This bit set to 1 if nUADCD pin is high at the time UART Receiver DCD checks a newly received data whether the data is good frame or not If the DCD interrupt enable bit UINTEN 6 is 1 a interrupt is generated when a data carrier is detected This bit can be used for error check bit in hardware flow control mode Receive FIFO Data In Receive FIFO mode this bit indicate Receive FIFO has valid data trigger level reach and reach Rx trigger level So UART request DMA to move data in RFREA Receive FIFO In non FIFO mode if URXBUF has a received data this
354. ter set contains 16 directly accessible registers RO to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register used to store status information Register 14 is used as the subroutine link register This receives a copy of R15 when a branch and link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14_svc R14 irq R14 fiq R14 abt and R14 und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when branch and link instructions are executed within interrupt or exception routines Register 15 holds the Program Counter PC In ARM state bits 1 0 of R15 are zero and bits 31 2 contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC Register 16 is the CPSR Current Program Status Register This contains condition code flags and the current mode bits FIQ mode has seven banked registers mapped to R8 14 R8 figq R14 In ARM state many FIQ handlers do not need to save any registers User IRQ Supervisor Abort and Undefined each have two banked registers mapped to R13 and R14 allowing each of these modes to have a private stack pointer and link registers 2 4 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL ARM State General Registers and Program Counter Supervisor ARM St
355. ter to be moved to the CPSR or SPSR mode register The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags 2 and V of CPSR or SPSR mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RESTRICTIONS e n user mode the control bits of the CPSR are protected from change so only the condition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed e Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state e The SPSR register which is accessed depends on the mode at the time of execution For example only SPSR fiq is accessible when the processor is in FIQ mode e You must not specify R15 as the source or destination register e Also do not attempt to access an SPSR in User mode since no such register exists ELECTRONICS 3 19 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER 3 20 MRS transfer PSR contents to a register 31 28 27 23 22 21 16 15 12 11 0 m 00000000000 15 21 Destination Register 19 16 Source PSR 0 CPSR 1 SPSR_ lt current mode 31 28 Condition Field MRS transfer register contents to PSR 31 28 27 23 22 21 12 11 4 00010 101001111 000000
356. terrupt Enable CCDIE 6 Data Carrier Detect Lost Interrupt Enable DCDLIE 7 Receive FIFO Data Trigger Level Reach Interrupt Enable RFREAIE 9 8 Reserved 10 Receive FIFO overrun Interrupt Enable OVFFIE 11 Reserved 12 Receive Event Time out Interrupt Enable E RXTOIE 15 13 Reserved 16 CTS event occured Interrupt Enable E_CTSIE 17 Reserved 18 Transmit Holding Register Empty Interrupt Enable THEIE This bit used in FIFO mode for interrupt enable when transmit FIFO empty as much transmit data trigger level 31 19 Reserved Figure 10 4 UART Interrupt Enable Register ELECTRONICS 10 15 UART 3C4520A RISC MICROCONTROLLER UART TRANSMIT BUFFER REGISTER 53 4520 has 32 byte Transmit FIFO and the bottom of FIFO is UTXBUF All data to be transmitted are stored into this register at first in FIFO mode if next buffer has invalid data then shifted to next buffer But in non FIFO mode a new data to transmit will be moved from UTXBUF to Tx shift register The UART transmit buffer registers UTXBUF contain an 8 bit data value to be transmitted over the UART channel Table 10 8 UXTBUF Registers UTXBUF 0XEOC UART transmit buffer register Table 10 9 UART Transmit Register Description Bit Number Reset Value 7 0 Transmit data This field contains the data to be transmitted over the single channel UART When this register is written the transmit buffer register empty bit in the status regis
357. the Word 8 value 3 86 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET FORMAT 13 ADD OFFSET TO STACK POINTER 15 14 13 11 10 6 12 9 8 7 1 91 1 11 9 9 09 9 8 6 0 7 bit Immediate Value 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 3 42 Format 13 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 3 20 The ADD SP Instruction S THUMB Assembler ARM Equivalent O 0 ADD SP ADD R13 R13 Add Imm to the stack pointer SP ADD SP Imm SUB R13 R13 Imm Add Imm to the stack pointer SP NOTE The offset specified by Imm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts lmm to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 20 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD SP 268 SP R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the Word7 value and 5 0 ADD SP 104 SP R13 SP 104 but don t set the condition codes Note that the THUMB opcode will cont
358. the standard register set However you can access them for assembly language programming and use them for fast temporary storage if necessary 1 22 ELECTRONICS 3C4520A RISC MICROCONTROLLER PRODUCT OVERVIEW EXCEPTIONS An exception arises when the normal flow of program execution is interrupted e g when processing is diverted to handle an interrupt from a peripheral The processor state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed Multiple exceptions may arise simultaneously To process exceptions the S3C4520A uses the banked core registers to save the current state The old PC value and the CPSR contents are copied into the appropriate R14 LR and SPSR registers The PC and mode bits in the CPSR are adjusted to the value corresponding to the type of exception being processed The S3C4520A core supports seven types of exceptions Each exception has a fixed priority and a corresponding privileged processor mode as shown in Table 1 4 Table 1 4 S3C4520A CPU Exceptions Exception Mode on Enty Prony ist ROmde 4 Undefined instruction Undefined mode 6 SWI 6 lowest ELECTRONICS 1 23 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER SPECIAL REGISTERS Table 1 5 S3C4520A Special Registers Group Registers Offset RW Description Reset Val System Config and 0x004
359. tion encoding is shown in Figure 3 25 This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM7TDMI and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can overlap other activity allowing the coprocessor and ARM7TDMI to perform independent tasks in parallel COPROCESSOR INSTRUCTIONS The S3C4520A unlike some other ARM based processors does not have an external coprocessor interface It does not have a on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S8C4520A These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor can be connected to the 53 4520 the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 28 27 24 23 20 19 16 15 12 11 7 5 4 3 uw Dee om om me 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20 Coprocessor operation code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction THE COPROCESSOR FIELDS Only bit 4 and bits
360. tly loaded into bits 0 through 15 of the register Two shift operations are then required to clear or to sign extend the upper 16 bits word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 ELECTRONICS 3 29 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER memory register LDR from word aligned address memory register LDR from address offset by 2 Figure 3 15 Little Endian Offset Addressing Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly lo
361. to load the CPSR along with the PC or force transfer of user bank when in privileged mode Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes The equivalence between the names and the values of the bits in the instruction are shown in the following table 3 6 Table 3 6 Addressing Mode Names ome Post incrementioad two 9 1 3 1 9 FosDesemebai 3 9 9 SmrA sme o Post increment store smea sma o 1 Pre Decrementstoe smeo smog o 9 Post Decrement sore smeo sm o 9 FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to a full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or descending If ascending a STM will go up and LDM down if descending vice versa IB DA DB allow control when LDM STM are not being used for stacks and simply mean increment after increment before decrement after decrement before ELECTRONICS 3 45 INSTRUCTION SET Examples LDMFD SP RO R1 R2 STMIA RO RO R15 LDMFD SP
362. transition interrupt enable RxSDCDIE 14 Valid frame interruopt enable RxFVIE 15 Idle detected interruot enable RxIDLEIE 16 Abort detected interrupt enable RxABTIE 17 CRC error frame interrupt enable RxCRCEIE 53 4520 RISC MICROCONTROLLER 14 13 12 11 10 m 0000x I m n Ox 4 m 0 00 x4 18 Non dctet aligned frame interrupt enable RxNOIE 19 Rx overrun interrupt enable RxOVIE 20 DPLL one missing interrupt enable DPLLOMIE 21 DPLL two missing interrupt enable DPLLTMIE 22 Not applicable 23 Rx internal error interrupt enable RxIERRIEN 31 24 Not applicable Figure 6 13 HDLC Interrupt Enable Register ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC TX FIFO HTXFIFO The Tx FIFO consists of eight 32 bit registers that are used for buffer storage of data to be transmitted Data is always transferred from a full register to an empty adjacent register The Tx FIFO can be addressed at two different register addresses the frame continue address and the frame terminate address Each register has four pointers data valid pointer bit 4 bits last pointer bit NoCRC pointer bit Preamble pointer bit The data valid pointer bit indicates whether each byte is valid or not The last byte pointer bit indicates whether the frame to be sent has the frame last byte or not The NoCRC pointer bit determines whether the CRC data is to be appended or no
363. transition of incoming data occurs at a count value other than 16 the DPLL adjusts its clock outputs during the next 0 to 31 counting cycle by extending or shortening its count by one which effectively moves the edge of the clock sampling the receive data closer to the center of the bit cell The adding or subtracting of a count of 1 will produce a phase jitter of 5 63 degrees on the output Because the DPLL uses both edges of the incoming signal for its clock source comparison the mark space ratio 5096 of the incoming signal must not deviate more than 1 5 of its baud rate if proper locking is to occur In the FM mode the DPLL clock must be 16 times the data rate The 5 bit counter in the DPLL counts from 0 to 31 so the DPLL makes two sampling clocks during the 0 to 31 counting cycle The DPLL output is Low while the DPLL is waiting for an edge in the incoming data stream The first edge the DPLL detects is assumed to be a valid clock edge From this point the DPLL begins to generate output clocks In this mode the transmit clock output of the DPLL lags the receive clock outputs by 90 degrees to make the transmit and receive bit cell boundaries the same because the receiver must sample the FM data at a one quarter and three quarters bit time You can program the 32X clock for the DPLL to originate from one of the RXC input pins from the TxC pin or from the baud rate generator output You can also program the DPLL output to be echoed out
364. truction as shown in Table 3 21 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine ELECTRONICS 3 89 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 12 11 10 8 1101011 me 7 0 Register List 10 8 Base Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 44 Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 3 22 The Multiple Load Store Instructions THUMB Assembler ARM Equivalent STMIA Rb Rlist STMIA Rb Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address 1 LDMIA Rb Rlist LDMIA Rb Riist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 22 The instructi
365. ts infra red IR transmits and receive operations In IR mode the transmit period is pulsed at a rate of 3 16 that of the normal serial transmit rate when the transmit data value in the UTXBUF register is zero To enable IR mode operation you set UCON 14 to 1 Otherwise the UART operates in normal mode In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value in the receiver buffer register URXBUF as the IR receive data When this bit is 0 normal UART mode is selected When it is 1 infra red Tx Rx mode is selected 15 This bit should be cleared by zero 16 Transmit FIFO enable S3C4520A UART block support 32 byte FIFO If this bit set to one TFEN transmit data moved to Tx FIFO and then sent 17 Receive FIFO enable S3C4520A UART block support 32 byte FIFO If this bit set to one RFEN receive data moved to Rx FIFO 18 Transmit FIFO reset this bit set to one transmit FIFO will be reset In this case if TFRST there is data in transmit shift register it will be sent 19 Receive FIFO reset If this bit set to one receive FIFO will be reset In this case if there RFRST is data in receive shift register it will be received 21 20 Transmit FIFO trigger This two bit trigger level value determines when the transmitter level TFTL start to transmit data in 32 byte transmit FIFO 00 30 byte empty 32 byte 01 24 32 10 16 32 11 8 32 23 22 Receive FIFO tr
366. tus Register Format 2 8 ELECTRONICS 3C4520A RISC MICROCONTROLLER PROGRAMMER S MODEL The Condition Code Flags The N Z C and V bits are the condition code flags These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally see Table 3 2 for details In THUMB state only the branch instruction is capable of conditional execution see Figure 3 46 for details The Control Bits The bottom 8 bits of a PSR incorporating T and M 4 0 are known collectively as the control bits These will change when an exception arises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits The and F bits are the interrupt disable bits When set these disable the IRQ and FIQ interrupts respectively The mode bits The M2 M1 and MO bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode bits define a valid processo
367. u and pticd provides 100K Ohm Pull up down register For detail information about the pad type see Chapter 4 Input Output Cells of the STD90 MDL90 0 35um 3 3V Standard Cell Library Data Book produced by Samsung Electronics Co Ltd ASIC Team LVCMOS Level Tri State Buffer 5V tolerant Pull up resistor 4m m 4m 6m 4m 4m 4m 6m ELECTRONICS 1 17 PRODUCT OVERVIEW 3C4520A RISC MICROCONTROLLER 64 fMCLK 512 fMCLK nRSCO NOTE After the falling edge of nRESET the 53 4520 count 64 cycles for a system reset and needs further 512 cycles for a TAG RAM clear of cache After these cycles the S3C4520A asserts nRCSO when the nRESET is released Figure 1 3 Reset Timing Diagram 1 18 ELECTRONICS 53 4520 RISC MICROCONTROLLER PRODUCT OVERVIEW CPU CORE OVERVIEW The S3C4520A CPU core is a general purpose 32 bit ARM7TDMI microprocessor developed by Advanced RISC Machines Ltd ARM The core architecture is based on Reduced Instruction Set Computer RISC principles The RISC architecture makes the instruction set and its related decoding mechanism simpler and more efficient than those with microprogrammed Complex Instruction Set Computer CISC systems High instruction throughput and impressive real time interrupt response are among the major benefits of the architecture Pipelining is also employed so that all components of the processing and memory systems can operate continuously The ARM7TDMI has a 32 bit a
368. u make to the control register GDMACON the source or destination addresses will either remain the same or they will be incremented or decremented Table 9 4 GDMASRC0 1 2 3 4 5 GDMADST0 1 2 3 4 5 Registers Registers RW Description Reset Value 31 26 25 0 Source Destination Address 25 0 Source destination address Figure 9 3 GDMA Source Destination Address Register 9 8 ELECTRONICS 3C4520A RISC MICROCONTROLLER DMA CONTROLLER DMA TRANSFER COUNT REGISTERS The DMA transfer count register indicates the byte transfer rate which runs at 24 bit on GDMA channels 0 1 2 3 4 5 Whenever transfer count register transmits the data of it will be diminished by transfer width In other words when transfer width TW is byte it will be diminished at 1 in the case of half word at 2 and word at 4 If it is set in four data burst mode each value of DMA transfer count will be diminished at 4 times Table 9 5 GDMACNTO0 1 2 3 4 5 Registers 31 24 23 0 23 0 Transfer Counter Figure 9 4 DMA Transfer Count Register ELECTRONICS 9 9 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER DMA MODE OPERATION Software Mode It is the mode which is operating GDMA without specific request signal with setting the enable bit of control register with software When we want to enable the operation Data transmission is started setting 3 2 GDMA mode selection bit of control registe
369. ultiple Load Store Instructions 3 90 3 23 The Conditional Branch 3 91 3 24 3 93 3 25 Summary of Branch 3 94 3 26 The BL Instruction 3 96 List of Tables Continued Table Title Page Number Number 4 1 System Manager 4 5 4 2 Address Bus Generation Guidelines 4 6 4 3 Word Access Store Operation with 4 9 4 4 Word Access Load Operation with 4 9 4 5 Half Word Access Store Operation with 4 10 4 6 Half Word Access Load Operation with Big Endian 4 10 4 7 Byte Access Store Operation with 4 11 4 8 Byte Access Load Operation with Big Endian 2 4 11 4 9 Word Access Store Operation with 4 12 4 10 Word Access Load Operation with Little Endian 4 12 4 11 Half Word Access Store Operation with Little Endian 4 13 4 12 Half Word Access Load Operation with
370. umb state an IRQ handler should return from the interrupt by executing SUBS PC R14 4 Abort An abort indicates that the current memory access cannot be completed It can be signalled by the external ABORT input ARM7TDMI checks for the abort exception during memory access cycles There are two types of abort Prefetch abort occurs during an instruction prefetch Data abort occurs during a data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken until the instruction reaches the head of the pipeline If the instruction is not executed for example because a branch occurs while it is in the pipeline the abort does not take place If a data abort occurs the action taken depends on the instruction type Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this The swap instruction SWP is aborted as though it had not been executed Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM instruction The abort mechanism allows t
371. umber of cycles spent in the coprocessor busy wait loop 5 and are defined as sequential S cycle non sequential N cycle and internal respectively 3 54 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC Load from memory to coprocessor STC Store from coprocessor to memory L When present perform long transfer 1 otherwise perform short transfer 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor cd dca evaluating to a valid coprocessor register number that is placed in the ie lt Address gt can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes 3 A post indexed addressing specification Rn lt expression offset of lt expression gt bytes write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARMTTDMI register number NOTE If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM7TD
372. upt 2 1 External interrupt 1 0 External interrupt 0 23 Global interrupt mask bit 0 Enable interrupt requests 1 Disable all interrupt requests Figure 14 3 Interrupt Mask Register INTMSK ELECTRONICS 14 5 INTERRUPT CONTROLLER 3C4520A RISC MICROCONTROLLER INTERRUPT PRIORITY REGISTERS The interrupt priority registers INTPRIO INTPRI5 contain information about which interrupt source is assigned to the pre defined interrupt priority field Each INTPRIn register value determines the priority of the corresponding interrupt source The lowest priority value is priority 0 and the highest priority value is priority 22 The index value of each interrupt source is written to one of the above 23 positions see Figure 14 4 The position value then becomes the written interrupt s priority value The index value of each interrupt source is listed in Table 14 1 Table 14 5 Interrupt Priority Register Overview 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 12 11 10 9 8 43210 7 6 5 mreno 070701 ponnys olofo remm ofofo emommvi 10 0 0 PRORTYO 14 ton Priority NTPRI o o o o o o oloo o o o PRIORITY NTPR o o olofo Pronn fofofo PRIOAITYE o o o PRIORMTVIS o o o PRIORITYTa o o o 0100 Pronn o o o o o o PRIORITYTs o o o 7 o o o
373. ure 4 21 ROM SRAM Flash Write Access Timing ELECTRONICS 4 36 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER DRAM CONTROL REGISTERS The System Manager has two DRAM control registers DRAMCONO DRAMCON1 These registers correspond to the up to two DRAM banks that are supported by 53 4520 A third register REFEXTCON is used to set the base pointer for external I O bank 0 S3C4520A supports EDO normal Synchronous DRAM SDRAM SDRAM mode can be selected by setting SYSCFG 31 If this bit is set to 1 all DRAM banks are selected SDRAM Otherwise EDO FP DRAM banks are selected Table 4 25 DRAM and External I O Control Register Description RW Description ResetValue DRAMCONO 0x314 R W DRAM bank 0 control register 0x00000000 DRAMCON 1 0x318 R W DRAM bank 1 control register 0x00000000 REFEXTCON 0x31C R W Refresh and external I O control register 0x0000801E ELECTRONICS 4 37 SYSTEM MANAGER 3C4520A RISC MICROCONTROLLER 31 30 29 109 876543 2 1 DRAM Bank 0 EDO mode EDO te 1 0 Normal DRAM Fast page mode DRAM 1 EDO DRAM 2 1 CAS strobe time tCS nete 2 00 1 cycle 01 2 cycles 10 3 cycles 11 4 cycles 3 CAS pre charge time tCP nete 1 0 1 cycle 1 2 cycles 5 4 DW 00 Disable 01 Byte 8bits 10 Half word 16bits 11 Disable 7 RAS to CAS delay tRC or tRCD 0 1 cycle 1 2 cycles 9 8 RAS pre charge time tRP 00 1 c
374. use the port special function The HDLC channel A signals nDCDA nCTSA use the port 27 26 the HDLC channel B signals use the port 7 0 the HDLC channel C signals use the port 15 0 depending on the settings in IOPCONO 1 register The UART signals use the port 23 16 depending on IOPCONO register The TIMER signals use the port 25 24 depending on IOPCONO register External interrupt request signals xIRQ 3 0 use the port 27 24 depending IOPCON 1 register DMA Request signals 5 0 use the port 8 0 36 34 30 depending register DMA acknowledge signals DACK 5 0 use the port 9 1 37 35 33 31 depending on IOPCONO register IOPMOD Alternate Functions Port0 XDREQ4 nCTSB XDACK4 nDCDB Output i Latch at 1 1 Write Port32 DRQ1 Port33 DACK1 Port34 DRQ4 IOPDATA Port35 DACK2 Read Port36 xDREQ3 nCTSA Active Port37 xDACK3 nDCDA On Off amp Filter Edge On Off Detection lt m z UJ 4 Interrupt or Request Figure 13 1 Port Function Diagram ELECTRONICS 13 1 PORTS 3C4520A RISC MICROCONTROLLER PORT SPECIAL REGISTERS Seven registers control the I O port configuration IOPMODO 1 IOPCONO 1 2 and 1 These registers are described in detail below PORT MODE REGISTER IOPMODO 1 The port mode register IOPMODO is used to configure the port pins P
375. ve edges an search mode sas entered 22 Not applicable 23 Rx internal error RXIERR 0 Normal operation 1 Received frame is not stable due to receive clock is unstable 31 24 Not applicable Figure 6 12 HDLC Status Register Continued 6 36 ELECTRONICS 3C4520A RISC MICROCONTROLLER HDLC CONTROLLERS HDLC INTERRUPT ENABLE REGISTER HINTEN Table 6 13 HINTENA HINTENB and HINTENC Register Registers Offset Rw Description Reset Value 0 70 HDLCA Interrupt Enable Register 0X00000000 HINTENB 0 80 Interrupt Enable Register 0X00000000 HINTENC 0 90 HDLCC Interrupt Enable Register 0X00000000 Table 6 14 HINTEN Register Description Bit Bit Name Description Number 5 Reserved 4 5 6 Reseved 7 8 9 10 11 i2 Reseved 13 14 15 16 17 18 19 20 21 i o 222 23 ELECTRONICS 6 37 HDLC CONTROLLERS 6 38 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 0 Reserved 4 Tx frame complete interrupt enable TxFCIE 5 Tx FIFO available to write interrupt enable TxFAIE 6 Reserved 7 CTS transition has occurred interrupt enable TxSCTIE 8 Transmit underrun has occured interrupt enable TxUIE 9 Transmit Good Frame interrupt enable TxGF 10 RxFIFO available to read interrupt enable RxFAIE 11 Flag detected interrupt enable RxFDIE 12 Reserved 13 DCD
376. way multiplexed 26 Divide 0 1 x Clock mode 1 0 5 x Clock mode Figure 8 4 TSA C Configuration Register 8 6 ELECTRONICS 3C4520A RISC MICROCONTROLLER DMA CONTROLLER DMA CONTROLLER OVERVIEW The 53 4520 has six channel general DMA controller called the GDMA The six channel GDMA performs the following data transfers without CPU intervention memory to from memory HDLC to memory HDLC to from memory UART to memory serial port to from memory The on chip can be started by software and or an external DMA Request UART request or HDLC request Software can also be used to restart a GDMA operation after it has been stopped The CPU can recognize when a GDMA operation has been completed by software polling and or when it receives an appropriate internally generated interrupt The S8C4520A controller can increment or decrement source destination addresses and conduct 8 bit byte 16 bit half word or 32 bit ward data transfer ELECTRONICS 9 1 DMA CONTROLLER 3C4520A RISC MICROCONTROLLER System BUS Mode Selection nXDREQ 0 1 2 GDMA Channel 0 1 2 UART nDREQ HDLC A B Port 31 33 35 Data GDMA Channel 3 4 5 nDREQ nXDREQ 3 nDACK 4 5 Mode Selection GDMA Port 37 1 9 Data nXDACK 0 A 23 18 nXDACK 3 4 5 5 29 24 Figure 9 1
377. wered device such as mouse keyboard USB 1 1 spec compatibly manufactured cables could be used for USB 2 0 compliant product All cables in markets are not made to fit 1 1 spec correctly but there is no problem for 1 1 or 1 0 compliant products except 2 0 products USB architecture uses bus tree topology There is only one host controller in a root and the hub which lies right next to host controller is called root hub IBM compatible PC with 2 USB ports means that there re one host and a root hub which has one upstream port from host controller and two downstream ports outside PC South bridge chips in PCs such as 82371AB EB contains USB host controller and root hub Compound devices can be designed A monitor that has a CRT and a hub Mouse or keyboard is attached to downstream ports of this monitor inside hub Maximum 5 hubs can lie between a host controller and a function because of signal delay ELECTRONICS 11 1 USB 3C4520A RISC MICROCONTROLLER FRAME GENERATION Frame divides time slot into 1ms units and the separators are SOFs Start of Frames Host broadcasts one SOF packet at a normal rate of once every 1 00ms 0 0005ms All ISO EPs in all devices can one IN OUT per 1ms time period The SOF packet consists of SYNC PID frame number CRC The host transmits the lower 11 bits of the current frame number in each SOF token transmission When requested from the Host Controller the current frame number is the frame number in existence at the
378. west register also gets transferred to from the lowest memory address By way of illustration consider the transfer of R1 R5 and R7 in the case where Rn 0x1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses do not affect the instruction However the bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 0x100C 0x100C 0x1000 0x1000 OxOFF4 1 100 0 1000 OxOFF4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 41 INSTRUCTION SET 3C4520A RISC MICROCONTROLLER 0x100C 0x1 00 PR 0x1000 01000 OxOFF4 2 0 100 0 1000 OxOFF4 5 r L we s 3 Figure 3 21 Post Decrement Addressing 3 42 ELECTRONICS 3C4520A RISC MICROCONTROLLER INSTRUCTION SET 0x100C 0x1 00 0x1000 01000 OxOFF4 1 100 0 1000 OxOFF4 Figure 3 22 Pre Decrement Addressing USE OF THE S BIT When the 5 bit is
379. xteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a branch B in assembly language becomes BEQ for Branch if Equal which means the branch will only be taken if the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary ignored 3 4 ELECTRONICS 53 4520 RISC MICROCONTROLLER INSTRUCTION SET BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the program counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or THUMB instructions 28 27 24 23 20 19 16 15 12 11 3 0 Operand Register If bitO of Rn 1 subsequent instructions decoded as THUMB instructions If bitO o
380. ycle 01 2 cycles 10 cycles 11 4 cycles 14 10 DRAM bank base pointer This value indicates the start address of DRAM bank The start address is calculated as RAM bank base pointer lt lt 20 24 20 DRAM bank next pointer The start address is calculated as DRAM bank base pointer lt lt 20 31 30 Number of column address bits in DRAM bank CAN 00 8 bits 01 9 bits 10 10 bits 11 11 bits NOTES 1 In SDRAM mode these bits are reserved 2 n SDRAM mode this bit affect SDRAM cycle tCS 1 value 0 1 cycle Figure 4 22 DRAM Control Registers DRAMCONO DRAMCON 1 4 38 ELECTRONICS SYSTEM MANAGER 53 4520 RISC MICROCONTROLLER lt 3 o Address Column Addr same page Data Fetch Normal DRAM Data Fetch Normal DRAM Data Fetch EDO DRAM Data Fetch EDO DRAM 1 cycle 0 1 cycle 0 1 cycle 0 tCS 1 2 cycles tRP tRC Figure 4 23 EDO FP DRAM Bank Read Timing Page Mode 4 39 ELECTRONICS 3C4520A RISC MICROCONTROLLER SYSTEM MANAGER lt B Address Figure 4 24 EDO FP DRAM Bank Write Timing Page Mode ELECTRONICS 4 40 SYSTEM MANAGER 53 4520 RISC MICROCONTROLLER tNCASwr Column Addr same page Address cz 5 c Qo 2 Data Fetch EDO DRAM Figure 4 25 EDO FP DRAM Bank Read Write Timing Page Mode 4 41 ELECTRONICS 3C4520A RISC M
381. yte 0x00 USBOWCH 0x5C USB Out Write Count register Higher byte 0x00 ELECTRONICS 11 43 USB 11 44 53 4520 RISC MICROCONTROLLER 31 8 7 0 Write Counter Lower Bits 7 0 Out Write Counter Lower Bits 31 8 Reserved 31 8 7 0 Write Counter 22 1 7 0 Out Write Counter Higher Bits 31 8 Reserved Figure 11 21 USBOWCL USBOWCH Registers ELECTRONICS 53 4520 RISC MICROCONTROLLER USB USB FIFO REGISTER The 53 4520 have five endpoints Each endpoint has FIFO To access to each FIFO data User must use these registers Table 11 32 USBEPO 1 2 3 4 5 Descriptions USBEPO USB FIFO USBEP1 USB EP1 FIFO USBEP2 USB EP2 FIFO USBEP3 USB EP3 FIFO USBEP4 USB EP4 FIFO ELECTRONICS 11 45 USB 3C4520A RISC MICROCONTROLLER 7 0 EndPoint 0 data FIFO 31 8 Reserved 7 0 EndPoint 1 data FIFO 31 8 Reserved 7 0 EndPoint 2 data FIFO 31 8 Reserved Figure 11 22 USBEP0 USBEP1 USBEP2 FIFO Registers 7 0 EndPoint 3 data FIFO 31 8 Reserved 7 0 EndPoint 4 data FIFO 31 8 Reserved Figure 11 23 USBEP3 USBEP4 FIFO Registers 11 46 ELECTRONICS 53 4520 RISC MICROCONTROLLER 32 BIT TIMERS 32 BIT TIMERS OVERVIEW The S3C4520A has two 32 bit timers These timers can operate in interval mode in toggle mode The output signals TOUTO and TOUT1 respectively You enable or disable the timers by setting control bits in the timer
382. yte access Program Data path between register and external memory BA Address whose LSB is 0 1 2 3 4 5 6 7 8 9 A X Don t care BAL Address whose LSB is 0 2 4 6 8 A E BAU Address whose LBS is 1 3 5 7 9 B D F CAS1 0 nWBE1 0 0 means active and 1 means inactive Table 4 13 Byte Access Store Operation with Little Endian STORE CPU Reg External Memory CPU Register Data abcd abcd Bit Num 31 0 31 0 31 0 CPU Data Bus dddd dddd dddd Bit Num 31 0 31 0 31 0 Internal SD Bus dddd dddd dddd External Address BAL BAL CAS1 0 nWBE1 0 XX10 XX01 XXX0 Bit Num 15 0 15 0 15 0 XDATA Xd d Bit Num 7 0 15 8 7 0 Ext Memory Data d d d Timing Sequence __ Table 4 14 Byte Access Load Operation with Little Endian LOAD CPU Reg lt External Memory CPU Register Data b a a BAL BAU Bit Num 31 0 31 0 31 0 CPU Data Bus bbbb aaaa aaaa Bit Num 31 0 31 0 31 0 Internal SD Bus bbbb aaaa aaaa External Address BAL BAL CAS1 0 nWBE1 0 XXXX XXXX Bit Num 15 0 15 0 XDATA ab ab Bit Num Ext Memory Data Timing Sequence 4 14 ELECTRONICS 53 4520 RISC MICROCONTROLLER SYSTEM MANAGER BUS ARBITRATION In the S8C4520A micro controller the term system bus refers to the separate system address and data buses inside the chip The S8C4520A s internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data tr

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