COMPACTPCI-812 PERIPHERAL BOARD USER`S MANUAL
Contents
1. by setting the DMLB bit bit 3 of the TIXC Master Diagnostics register Ox10Ah This mode loops transmit data to receive data just after the analog drivers of the T1 XC CLOCKING OPTIONS In normal operation the transmit clock is derived from the receive data Loop timing is enabled by setting the LOOPT bit bit 4 of the SUNI PDH Configuration Register 0x000h CPCI 812 User s Manual Revision 1 0 August 2000 CYCLONE Microsystems 5 1 5 2 CHAPTER 5 pSOS SOFTWARE DEVELOPMENT INTRODUCTION This chapter is dedicated to aiding pSOS application development using the Cyclone CPCI 812 pSOS BSP It contains information specific to the Cyclone BSP and is intended to be used in conjunction with the pSOS documentation provided by ISI Wind River Systems Note that there are many items within the BSP that a user may want to self configure so users should be readily able to modify and rebuild the BSP when necessary Once an application has been built and linked with the CPCI 812 BSP the image can be downloaded to DRAM via Ethernet using the Cyclone TFTP Bootloader see accompanying documentation on this procedure or downloaded to Flash ROM or DRAM using a JTAG emulator such as Wind River s Visionprobe tool see section 3 10 This chapter is divided into the following sections e Embedded Utilities Memory Block e Endian Considerations e PCI Configuration e EPIC Interrupt Programming e LM75 Temperature Sensors EMBED2. matches the settings in register 120h For other FDL data rates ESF is kept to a one and the value of FMS 1 0 is changed See the T1XC manual for more information 130h 02h TPSC Configuration The T1XC manual says to set the IND bit bit 1 for proper operation IBCD Activate Code The T1XC manual says to set the activate loopback to 08h for ESF frame format operation IBCD Deactivate Code The T1XC manual says to set the deactivate loopback code to 44h for ESF frame format operation SIGX Configuration Setting the ESF bit bit4 selects ESF framing format clearing FMS 1 0 bits 3 2 matches the settings in registers 120h and 12Ch The T1XC says to see the IND bit bit 1 for proper operation XBAS Configuration Setting the ESF bit bit 4 selects ESF framing format and clearing FMS 1 0 bits 3 2 matches the settings in registers 120h 12Ch and 140h Setting the B8ZS bit bit 5 selects B8ZS line coding RPSC Configuration The T1XC manual says to set the IND bit bit 1 for proper operation 150h 02h CPCI 812 User s Manual 4 5 Revision 1 0 August 2000 ATM PROGRAMMING INFORMATION ld 4 3 4 3 1 4 3 2 4 4 4 5 4 6 CYCLONE Microsystems SOFTWARE RESET All six VLSI devices 2 ATM SARs 2 SUNI PDHs and 2 T1XCs can be reset by software The actions required to reset the devices follow and the equivalent of asserting their respective reset pins ATM SARs Software Reset The ATM SAR is
3. outline corner which is shown diagonally across from the J5 designer in the silk screen as in Figure 3 3 CPCI 812 User s Manual Revision 1 0 August 2000 ld HARDWARE Microsystems Figure 3 3 JTAG COP Header Orientation Table 3 3 JTAG COP PIN ASSIGNMENT QACK TRST CHKSTOPIN 3 D GN 3 11 GEOGRAPHIC ADDRESSING CompactPCI backplanes that support 64 bit connector pin assignments are required to provide a unique differentiation based upon which physical slot the board has been inserted The CPCI 812 makes this definition available to the software The definition for GA 4 0 is shown in Figure 3 4 CPCI 812 User s Manual 3 5 Revision 1 0 August 2000 HARDWARE Lal 3 12 3 12 1 3 13 3 6 Microsystems Figure 3 4 Geographic Addressing Register FF60 0000H 12C BUS The CPCI 812 has two temperature sensors attached to the Inter Integrated Circuit I7C bus interface of the MPC8240 processor The I C addresses of the devices are shown in Table 3 4 Table 3 4 12C Device Addresses Desarme Doveo Funion Ads U34 LM75 Temperature Sensor 1001000 LM75 Temperature Sensor 1001001 Temperature Sensors The LM75 temperature sensors have overtemperature trip points that will trigger an interrupt when crossed The sensors are placed on the board at U34 and U35 and share serial interrupt 5 The sensors should be placed in the interrupt mode by startup code The sensors can be read for a
4. timer2 and timer3 can be set up to automatically start periodic DMA operations for DMA channels O and 1 respectively without using the processor interrupt mechanism LEDS The CPCI 812 has six green LEDs and one blue LED The four green LEDs labeled IOP ACT STATO and STATI are software driven and are controlled by a write only register which is located at address FF20 OOOOH The LED Register bitmap is shown in Figure 3 1 Two green LEDs labelled LINKO and LINKI are under ATM hardware control and indicate a valid DS1 link once the SUNI PDH devices have been initialized by software The blue LED is used for Hot Swap operations Refer to section 3 14 1 for additional information CPCI 812 User s Manual Revision 1 0 August 2000 ld HARDWARE Microsystems Activity Stato Stat1 IOP write only 1 LED on 0 LED off Figure 3 1 LED Register Bitmap FF20 0000H 3 7 PCI INTERFACE The CPCI 812 contains a primary 64 bit PCI bus and a secondary 32 bit PCI bus Both buses are clocked at 33 MHz The primary PCI bus interfaces the 64 bit CompactPCI bus to the 21554 PCI to PCI bridge The secondary side of the 21554 interfaces a 32 bit PCI bus to the MPC8240 and the PCI9080 bridge which interfaces the two ATM SARs 3 7 1 Primary PCI Arbitration The primary PCI bus arbitration is provided by host of the CompactPCI system 3 7 2 Secondary PCI Arbitration Secondary bus arbitration logic between the MPC8240 processor th
5. 800 441 2447 TL16C550C UART Texas Instruments http www ti com sc docs general dsmenu htm PCI 9080 PLX Technology Inc 390 Potrero Avenue Sunnyvale CA 94086 800 759 3735 408 774 2169 Fax http www plxtech com Local ATM SAR Chip User s Manual uPD 98401 NEC Electronics Inc 475 Ellis Street P O Box 7241 Mountain View CA 94039 T1 Framer Transceiver TIXC PM4341A Saturn User Network Interface S UNI PDH PM7345 PMC Sierra Inc 8501 Commerce Court Burnaby BC Canada V5A 4N3 604 668 7300 1 6 CYCLONE Microsystems LM75 Digital Temperature Sensor and Thermal Watchdog National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 800 272 9959 CompactPCI Specification PCI Industrial Computers Manufacturing Group 301 Edgewater Place Suite 220 Wakefield MA 01880 617 224 1100 617 224 1239 Fax PCI Local BIOS Specification Revision 2 1 PCI Special Interest Group 2575 NE Kathryn Street 17 Hillsboro OR 97214 800 433 5177 U S 503 693 6232 International 503 693 8344 Fax LO Specification Revision 1 0 LO Special Interest Group 415 750 8352 http www 1Zosig org CompactPCI Hot Swap Specification PICMG 2 1 R1 0 PCI Industrial Computers Manufacturing Group 301 Edgewater Place Suite 220 Wakefield MA 01880 617 224 1100 617 224 1239 Fax CPCI 812 User s Manual Revision 1 0 August 2000 CYCLONE Microsystems
6. Interrupt Registers e eeeerren ee rena na ereea nar eeaaa era aa na ceeaaanerena 2 3 2 6 2 Error Handling and EXCCDUONS sadia ara Geena te 2 4 CHAPTER 3 HARDWARE A ce a ab ee ee en eet eer 3 1 3 2 CONTROL MEMORY T1XC amp SUNI PDH REGISTERS eres 3 1 do FLASH ROM fissuras ada daa 3 1 at CONSOLESERIALPORA espurio sad base dinda de nho a ap 3 1 do COUNTER TIMERS wicca seats cassia uai ieee Ad aa nda aa ha eee te A Uns ae 3 2 O MEDO Ser So an a Ra PS Goa E ee 3 2 Did RO MINTERRA E O O ane in ada sda nda ga aci aa Sena cosa dna a ad 3 3 Sofi PRIMAry POATA ON atada dr 3 3 de Secondaly IP Gli AMON ALON saesscsesaneacenccecutenter ema da casas RR 3 3 de DMACHANNELS cotas O 3 3 97 MESSAGE UNIT SE A DA 3 4 SAO TAG COR SUPPORT scada o a eo ll SS a a corse 3 4 3 i GEOGRAPHIC ADDRESSING cuida 3 5 DIZ BU hs eee oe ee ee Tea DE sega ee a na a ee 3 6 Sel Zul Temperature Senso Sid 3 6 A O DD A e ceeneue 3 6 313 1 Hor Swap Extraction PrOCESS ais 3 7 Julio MOL Swap INSEMIOM PROCESS tai ninas 3 7 3 14 DSI CONNECTOR und ld a att tos Ges o arabe 3 7 dao BOARDID REGISTER eee a 3 7 CPCI 812 User s Manual Revision 1 0 August 2000 CONTENTS ld Microsystems CHAPTER 4 ATM PROGRAMMING INFORMATION Al INTRODUCTION cartas dt da ee ee ee ee ee ae ltda iaa 4 1 AO DEVICE REGISTIRES ado o e ea le ee ae e rl e e bd o 4 2 42 ATM SAR Mode Registers tic di DA E qelieada 4 2 422 SUNFPDH REGS T A S rios 4 3 duero
7. Upstream Outbound CompactPCI Transactions Preconfiguration of the embedded bridge also sets the size and remap address of upstream PCI memory window O This window can be used to transfer data over the CompactPCI bus from the MPC8240 to the host or other IOP cards The size by default is set to 64 MBytes and the remap value is set to 0x00000000 which in most PCI systems is allocated to the PCI host card Once preconfiguration is complete the embedded bridge is configured by the MPC8240 when it runs the pSOS PCI Auto Configuration suite This creates a 64 MBytes window mapped onto the CompactPCI bus whose base address can be read from Base Address Register 2 Changing the remap translation value for this memory space in the bridge allows this 64 MBytes window to be mapped to a different region on the CompactPCI bus PLX PCI9080 Configuration The PLX PCI9080 is a PCI to local bus bridge chip Its purpose on the CPCI 812 is to interface the local PCI bus with the ATM SAR devices Configuration of the device allows PCI cycles claimed by the PLX PCI9080 to be forwarded with translation through to the local bus where they are claimed by one of the two SAR devices CPCI 812 User s Manual 5 3 Revision 1 0 August 2000 pSOS SOFTWARE DEVELOPMENT ld Microsystems Because there are two SAR devices on the CPCI 812 two PCI regions are required one for each device pSOS configuration sets up the PCI9080 to request two 1 MByte PCI memory re
8. phone jack to DB25 cable supplied with the CPCI 812 board The CPCI 812 is a Full Hot Swap board compliant with PICMG Deli Four 31 bit timers are available to generate interrupts The MPC8240 supports 2 separate DMA channels for high throughput data transfers between PCI bus agents and the local SDRAM memory The CPCI 812 supports the LO specification for interprocessor communication Complete hardware segmentation of user packets to ATM cells including physical layer convergence and transmission over a DS1 1 554Mbit s twisted pair line Complete hardware assembly of ATM cells received on a DS1 1 554Mbit s twisted pair line into user packets Direct memory access of packets stored in host memory for segmentation and reassembly CPCI 812 User s Manual Revision 1 0 August 2000 CYCLONE Microsystems 1 3 1 4 GENERAL INTRODUCTION OVERVIEW The CPCI 812 is a 6U CompactPCI peripheral board with two ATM DSI interfaces which uses three VLSI circuits ATM SAR TIXC amp SUNI PDH The ATM SAR performs hardware segmentation of user packets into ATM cells and hardware reassembly of ATM cells into user packets The SUNI PDH implements the mapping of ATM cells into the DS1 frame structure The TIXC provides the DSI line interface The CPCI 812 has two PCI buses a primary and a secondary The primary PCI bus is the CompactPCI bus The secondary PCI bus is a local bus that supports the MPC8240 and PLX PCI9080 bridge w
9. processor illegal Flash write transactions PCI address and data parity errors accesses to memory addresses out of the range of physical memory memory parity errors memory refresh overflow errors ECC errors PCI master abort cycles and PCI received target abort errors Table 2 2 describes the relative priorities and recover ability of externally generated errors and exceptions Table 2 2 Error Priorities E E JT Power on reset CompactPCl chassis reset switch or Hard reset via JTAG controller Machine check Processor transaction error or Flash error PCI address parity error or PCI data parity error when Machine check the CPCI 812 is acting as the PCI target Rachinecheck Memory select error memory refresh overflow or ECC error PCI address parity error or PCI data parity error when Machine check the CPCI 812 is acting as the PCI master PCI master abort or received PCI target abort CPCI 812 User s Manual Revision 1 0 August 2000 ld Microsystems 3 1 3 2 3 3 3 4 CHAPTER 3 HARDWARE SDRAM The CPCI 812 is equipped with 64 Mbytes of ECC SDRAM mounted on the card The memory is made up of nine 64Mbit SM x 8 devices in an 83M by 72 bit configuration The memory controller unit MCU of the CPCI 812 supports SDRAM burst lengths of four A burst length of four enables seamless read write bursting of long data streams as long as the MCU does not cross the page boundary Page boundaries are naturally ali
10. reset when any value is written to the software reset register at offset 0000 001Ch SUNI PDHs Software Reset The SUNI_PDH is reset when 0x08h or any other value that sets bit 7 to a one is written to the Identi fication and Master Reset Register at offset 0x04h The SUNI PDH will remain reset until a 0x00h or any other value that clears bit 7 to a zero is written to offset Ox04h LOOPBACK The ATM SAR SUNI PDH and TIXC each has one loopback path Loopback paths within the ATM SARs is performed by setting the LP bit bit 14 of the ATM SAR s General Mode Register A multiplexer internal to the ATM SAR allows data to traverse the entire transmit and receive data paths of the ATM SAR See the ATM SAR User s Manual for more reference The diagnostic loopback of the SUNI_PDH is obtained by setting the DLB bit bit 2 of the SUNI PDH s Configuration Register 0x00h Like the ATM SAR loopback the diagnostic loopback connects the transmit data to the receive data allowing data to traverse the transmit and receive data paths of the SUNI PDH Like the loopbacks for the ATM SAR and SUNI PDH the two loopback modes available in the TIXC connect transmit data to receive data The diagnostics digital loopback is enabled by setting the DDLB bit bit 2 of the TIXC Master Diagnostics register 0x10Ah This mode loops transmit data to receive data but does not include the analog drivers of the TI XC The diagnostic metallic loopback is enabled
11. s Manual Revision 1 0 August 2000 CYCLONE pSOS SOFTWARE DEVELOPMENT Microsystems The function PssUnSetIntHandler is used to disconnect an interrupt handler long PssUnSetIntHandler ULONG Level E INCE Nor VECroR number 77 void handler Pointer to handler function VOLO arg Optional argument to handler 5 6 LM75 TEMPERATURE SENSORS The two on board LM75 devices can be used to detect possible temperature problems in the system such as overheating The BSP file Im75 c contains a collection of routines that simplify the use of the devices Included are functions to read and write to registers on the LM75 including the temperature trip and hysteresis registers Before use the LM75 should be placed in interrupt mode When in this mode an LM75 will interrupt if the temperature goes above the value in the trip register and will interrupt again when the temperature falls back below the value in the hysteresis register Also included in the Im75 c file is the function Im75_test which is a simple diagnostic that uses useful LM75 routines to test the devices Developers can use this as an example for writing their own utilities to operate the LM75 and can also call this test in their application to ensure that the devices are operating correctly For further information consult the National Semiconductor LM75 Data Sheet CPCI 812 User s Manual 9 7 Revision 1 0 August 2000 Id Microsystems APPENDIX A PCI LOCAL B
12. structures is created by the pSOS Auto Configuration This list is defined in pcicfg c by PCI LOC pci dev list PCI DEV LIST SIZE This list is important as it contains a PCI LOC structure for all of the PCI devices on the local PCI bus Many pSOS PCI functions such as those to find a particular device in the list require a pointer to this list and the list length as arguments Others such as those that access a particular PCI device require the PCI_LOC element from the list which indicates which device the transaction is to occur on typedef struct pciloc short bus bus number char device device number char functions function number char hostBridges Host PCI bridge number unsigned cfgFlags Configuration flags unsigned claimed Claimed Status unsigned crEdocass Configuration Status unsigned dev vend Devices and Vendor ID unsigned keyValue pSOS Key Value unsigned intrVec Tacerii pt vector number 7 FRCL EOC Figure 5 2 PCI_LOC Structure Definition EPIC INTERRUPT PROGRAMMING The Embedded Programmable Interrupt Controller EPIC is the general purpose interrupt controller internal to the MPC8240 EPIC control and status registers are located in the EUMB CPCI 812 hardware is configured to provide nine dedicated external hardware interrupts which are time division multiplexed onto one serial input on the MPC8240 The EPIC controller also provides four internal timers that can be interrupt s
13. the signal description Table 3 5 DS1 Connector DESCRIPTION Receive Ring 0 Receive Tip 0 Transmit Ring O Transmit Tip O Receive Ring 1 Receive Tip 1 Transmit Ring 1 Receive Tip 1 K Note Pin 3 6 7 8 13 16 17 18 19 and 20 are not connected 3 15 BOARD ID REGISTER The Board ID Register is a read only register that can be used to differentiate between the CPCI 812 and other Cyclone Microsystems MPC8240 based CompactPCI cards It is located at address FF70 0000h on all such cards with each card returning a unique ID value Figure 3 5 shows the board ID for the CPCI 812 Read Only _ BRED Te S E a O Figure 3 5 Board Identification Registers FF70 0000h CPCI 812 User s Manual 3 Revision 1 0 August 2000 HARDWARE 3 8 CYCLONE Microsystems CPCI 812 User s Manual Revision 1 0 August 2000 ld Microsystems CHAPTER 4 ATM PROGRAMMING INFORMATION 4 1 INTRODUCTION The Control Memory the T1XC registers and the SUNI PDH registers are accessed through the ATM SAR The Control Memory the TIXC and the SUNI PDH are accessed using the COMMAND REGISTER CMR COMMAND EXTENSION REGISTER CER and the INDIRECT ACCESS COMMAND of the ATM SAR The INDIRECT ACCESS COMMAND has a two bit field that indicates the target of the access Control Memory 00 ATM SAR registers 01 PHY device 11 The PHY device target should be used to access both the TIXC registers and the SUNI PDH registers The TIXC registers have an offset of 1
14. 00h the SUNI PDH registers reside at 000h through 074h Table 4 1 Secondary Address Map for ATM SAR Registers ATM SAR Registers ATM SAR Offset a 00h GSR 04h IMR O8h ADDR CPCI 812 User s Manual 4 1 Revision 1 0 August 2000 ATM PROGRAMMING INFORMATION Lal Microsystems 4 2 DEVICE REGISTRES The ATM SAR SUNI PDH and TIXC are very flexible devices and therefore have many registers that can be setup to customize device operation The following three sections identify register settings 4 2 1 ATM SAR Mode Registers The ATM SAR device has a mode register that configures the device for various modes of operation Almost all of the bit settings for the mode registers have already been determined and fixed by the hardware design Table 4 2 shows the bit settings for the ATM SAR mode register Entries of D under Val indicate that the entry is a don t care the bit can be set to zero or one An S under Val means that the user can set this for his application Consult the ATM SAR Chipset User s Manual for more information Table 4 2 ATM SAR General Mode Register Status Function PC Bus Parity Disabled Bus Parity Disabled Little endian Byte Ordering Burst Size Determined from Address PM AD 5z e TO f g Wore Bursts Enabled Z OD RA Read RDY Mode Normal o O WA Write RDY Mode Normal S 4 2 CPCI 812 User s Manual Revision 1 0 August 2000 La ATM PROGRAMMING INFORMATION Microsyst
15. 2 1 2 2 2 3 2 4 CHAPTER 2 MPC8240 PROCESSOR MPC8240 PROCESSOR The MPC8240 contains a PowerPC 603e core processor The core is configured to run at 250 MHz This RISC processor utilizes a superscalar architecture that can issue and retire as many as three instruc tions per clock The core features independent 16 Kbyte four way set associative physically addressed caches for instructions and data and on chip instruction and data memory management units MMUs BYTE ORDERING The CPCI 812 is designed to run in big endian mode The byte ordering determines how the core accesses local memory and the PCI bus Big endian stores the most significant byte in the lowest address RESET VECTOR The 8 bit wide Flash ROM is located in the address range FFEO 0000h through FFFF FFFFh See Figure 2 1 the CPCI 812 memory map The MPC8240 reset vector is located at address FFFO 0100h This reset vector location which contains a branch to the rest of the boot code 1s essentially in the middle of the ROM device This positioning results in a break up of continuous memory space and approximately 50 reduction in usable space for boot code To better utilize this device the CPCI 812 re maps the reset vector to FFEO 0100h by inverting memory address 20 A20 for the first two processor accesses to memory These accesses are an absolute jump instruction to the beginning of boot code After this jump A20 functions normally Utilizing this method the ma
16. COMPACTPCI 812 PERIPHERAL BOARD USER S MANUAL P Microsystems Intelligent O Controllers The information in this document has been carefully checked and is believed to be entirely reliable However no responsibility is assumed for inaccuracies Furthermore Cyclone Microsystems Inc reserves the right to make changes to any products herein to improve reliability function or design Cyclone Microsystems Inc neither assumes any liability arising out of the application or use of any product or circuit described herein nor does it convey any license under its right or the rights of others Revision 1 0 August 2000 Cyclone P N 800 0812 Copyright 2000 by Cyclone Microsystems Inc ld CONTENTS Microsystems CHAPTER 1 GENERAL INTRODUCTION al INTRODUCTION estrada tica bata 1 1 kA RENTURES ec bs 1 2 ko OVERVIEW escarola Ro Rad a A dE a DS Den Sa eget RS cece nd RS ee eect aan 1 3 bA SPECIFICAMONS sisal iss p de RO SS S E Rd 1 3 ES ENVIRONMENTAL ss E o iso doo LO 1 4 16 ARENS CAL ENVIRONMENT aaa a A Ce hence 1 5 Er REFERENCE MAINA Sascha Ss ad rata A tena eet tan an ba las 1 6 CHAPTER 2 MPC8240 PROCESSOR 2 MECGS240 PROGESS O Rosero TD as 2 1 22 BYTE ORDERING ss do o a 2 1 O ea a carros qr OO a a Ca CRS PO RO a CR 2 1 2 4 POWERPC MPC603E CORE CACHE BUFFERS ARRAYS eres 2 1 20 MEMORY MAR asd cias sao asia isca Po ES ad een eee Sana 2 2 20 INTERRUPT O oa rte ere ee o io do aid Crato eee 2 3 2 6 1 MPC8240
17. DED UTILITIES MEMORY BLOCK The Embedded Utilities Memory Block EUMB is a relocatable memory block that contains the registers for several of the MPC8240 s embedded features including the Messaging Unit DMA Controller Address Translation Unit ATU PC Controller and Embedded Programmable Interrupt Controller EPIC Figure 5 1 shows the EUMB memory offsets for each of these embedded devices The base of the EUMB is software programmable by setting the EUMB Base Address Register EUMBBAR in the MPC8240 s PCI Configuration Space offset 0x78 pSOS initialization sets this value at startup Users should never modify this value and should read this value when necessary using a local PCI configuration read cycle see section 5 4 For further information on MPC8240 address maps and the EUMB consult chapter 4 of the MPC8240 User s Manual CPCI 812 User s Manual 5 1 Revision 1 0 August 2000 pSOS SOFTWARE DEVELOPMENT ld 9 3 5 4 5 2 Microsystems 0x0 0000 Message Unit 0x0 1000 DMA 0x0 2000 0x0 3000 0x0 4000 0x4 0000 0x8 0000 OxF FFFF Shaded area indicates locations not allowed for the EUMB Figure 5 1 Embedded Utilities Memory Block ENDIAN CONSIDERATIONS The MPC8240 on the CPCI 812 stores data in local memory in a big endian manner most significant byte in the lowest memory address However the PCI bus is a little endian bus least significant byte in the lowest byte lane including access
18. INTRODUCTION Id Microsystems Table 1 1 CPCI 812 Power Requirements Voltage Current Typical Current Maximum 3 3V 2 411 Amps 3 465 Amps 5V 2 197 Amps 3 144 Amps 12V 0 002 Amps 0 003 Amps 1 5 ENVIRONMENTAL The CPCI 812 should be operated in a CompactPCI card cage with good air flow The board can be operated at ambient air temperature of 0 55 degrees Celsius as measured at the board Table 1 2 Environmental Specifications Operating Temperatures O to 55 Degrees Celsius Relative Humidity 0 95 non condensing Storage Temperatures 55 to 125 Degrees Celsius 1 4 CPCI 812 User s Manual Revision 1 0 August 2000 l GENERAL INTRODUCTION Microsystems 1 6 PHYSICAL ENVIRONMENT OSS5E BL Y TIP LPLI BIZ REV E PN 270 DEIZ 07 Figure 1 2 Physical Configuration Figure 1 2 1s a physical diagram of the CPCI 812 Adapter showing the location designators of jumpers connectors and ICs Refer to this figure when component locations are referenced in the manual text CPCI 812 User s Manual 1 5 Revision 1 0 August 2000 GENERAL INTRODUCTION 1 7 REFERENCE MANUALS MPC8240 Integrated Processor User s Manual Order Number MPC8240UM D Rev O Motorola Literature Distribution P O Box 5405 Denver CO 80217 800 441 2447 PowerPC Microprocessor Family The Programming Environments for 32 bit Microprocessors Rev 1 Order Number MPCFPE32B AD Motorola Literature Distribution P O Box 5405 Denver CO 80217
19. MRS TACO I SUSI Said ida 4 4 AS SSOP TV AR eee SW pta ii e bc a EU SORA 4 6 4 3 1 ATM SARS Software Resel erre rn nn rn nn aeee 4 6 4 3 2 SUNI PDHS Software Resetl rara 4 6 AA A O O AA II ia a Rad DO A a 4 6 45 CLOCKING O ON Si s 4 6 CHAPTER 5 pSOS SOFTWARE DEVELOPMENT BA INTRODUCTION aaa erra 5 1 5 2 EMBEDDED UTILITIES MEMORY BLOCK rrenan 5 1 5 3 ENDIAN CONSIDERATON Se ocasiao e ara 5 2 SA PCICONFIGURATDION dde 5 2 5 4 1 Downstream Inbound CompactPCI Transactions ae 5 3 5 4 2 Upstream Outbound CompactPCI Transactions eee 5 3 943 PLX POIS0BO Configuratio a as 5 3 34 4 Changing PCIUCONIQUIANON eite r E 5 4 54 5 pSOS PCI Device Driver Interface ini ia 5 4 5 5 EPIC INTERRUPT PROGRAMMING errar 5 5 5 5 1 Connecting and Disconnecting Interrupt Handlers in pSOS eine 5 6 5 6 LM75 TEMPERATURE SENSORS renata errar ea rear nero rc err r eres rc nan 5 7 APPENDIX A PCI LOCAL BUS SIGNALS A INTRODUCHON cuia e a ETE NS A 1 il CPCI 812 User s Manual Revision 1 0 August 2000 ld CONTENTS Microsystems LIST OF FIGURES Figure i l lt CPGIF812 Block Diada ito 1 1 Figure 1 2 Physical Configuration a pia aa iO 1 5 FIGUFE 2 GPCI SIZ Memory Malaui ias bica nara baia ais dadas ad cada AS lola 2 2 Figure 3 14 LED Register Bitmap FF200000 asas ais nd ps a a EEA 3 3 Figure 3 2 MPC8240 Processor DMA Controller oooonncncconnnconcconncconc
20. US SIGNALS A 1 INTRODUCTION The following tables list the PCI Local Bus signals on AMP Mictor 38 connectors CYCLONE ANALYSIS PROBE LOGIC ANALYZER MICTOR PIN POD CHANNEL NAM POD 1 CLK 16 SPERR a Ds for O 0 us CPCI 812 User s Manual A 1 Revision 1 0 August 2000 PCI LOCAL BUS SIGNALS l Microsystems JO O O e e a A O ee ee eee ee FS RR eee A O A AA ARE LC E O E E AAA a E ee es SO 900 S08 es NO A 2 CPCI 812 User s Manual Revision 1 0 August 2000 ld APPENDIX A Microsystems O RO RR FEE A RC O FOIE E RO RR FUE E RO RR AR RC E E RO RA FRE e gt FI ee E RR RR RN a0 O O o oa K Note Logic Analyzer POD 1 amp 3 MICTOR 1 NO POD 2 amp 4 MICTOR 2 CPCI 812 User s Manual A 3 Revision 1 0 August 2000
21. al section Configuring the TIXC from Reset CPCI 812 User s Manual Revision 1 0 August 2000 La ATM PROGRAMMING INFORMATION Microsystems Table 4 4 T1XC Non Default Register Settings ADDR DATA Register Name and Description T1XC Receive Options 100h 20h Setting the ELSTBYP bit bit5 bypasses the elastic store block of the T1XC keeps the data synchronized to the recovered clock RCLKO and eliminates the need for a BRCLK T1XC Receive DS1 Interface Configuration Setting the SDOEN bit bit 6 103h 40h forces the multifunction input output pins SDP RDP RDD and SDN RDN RLCV to outputs eliminating the need for support of the multifunction pins as digital inputs XPLS Line Length Configuration setting the SM bit bit6 and clearing the ILS 2 0 bits bits 2 1 0 sets the Analog DSX 1 Pulse Generator block to 114h 50h use waveform template corresponding to a line length of O to 100 feet For longer line lengths SM is kept to a one and the value of FMS 1 0 is changed See the T1XC manual for more information FRMR Configuration Setting the ESF bit bit 4 and clearing FMS 1 0 bits 3 2 sets the Framer 120h 10h for ESF framing format and 4Kbit FDL data rate For other FDL data rates ESF is kept to a one and the value of FMS 1 0 is changed See the T1XC manual for more information ALMI Configuration Setting the ESF bit bit 4 sets the Alarm Integrator for ESF framing format 12Ch 10h and clearing FMS 1 0 bits 3 2
22. cnnnonconconncncononcnnnnncononnnnnnnnanenonancnnos 4 2 Table 4 3 SUNI PDH Non Default Register Settings eee rena eree arena 4 3 Table 4 4 T1XC Non Default Register SettingS ccoconcnncconcnnccoconoconononnnnononanonnnoncnnonnnnnnonanenonnnennos 4 5 Table 5 1 PLX PCI9080 Base Address Registers on CPCI 812 n eres 5 4 Tableso 2 TGRGIST2 INterupEV eco Sa sd did 5 6 IV CPCI 812 User s Manual Revision 1 0 August 2000 Id Microsystems CHAPTER 1 GENERAL INTRODUCTION 1 1 INTRODUCTION The CPCI 812 is a high performance CompactPCI peripheral board featuring two ATM SARs for dual DS1 line interface A block diagram is shown in Figure 1 1 The board is based on the MPC8240 PowerPC integrated processor The MPC8240 has a processor core based on the PowerPC603e low power microprocessor and also performs many peripheral functions on chip The peripheral logic integrates a PCI bridge memory controller DMA controller interrupt controller 1 0 controller and an IC controller Software development tools for PowerPC processors are available from a variety of vendors and a Board Support Package BSP for the pSOS operating system is available from Cyclone DS1 DS1 ATMO ATM1 Console Serial Port 2 Mbytes Flash ROM 64 Mbytes SDRAM MPC8240 PCl to SAR Processor Bridge PCI to PCl 32 bit Secondary PCI Bus Bridge 64 bit CompactPCI Bus Figure 1 1 CPCI 812 Block Diagram CPCI 812 U
23. conoconnnnonancncnonancnnnnonncenconancnos 3 4 Figure 3 3 JTAG COP Header ONE MO Misc 3 5 Figure 3 4 Geographic Addressing Register FF60 0000H eee cette eae e eee eea eee eeeeaaaeeeeeeaaeey 3 6 Figure 3 5 Board Identification Registers FF70 OOOON eee ee eeeeeeeeeeeeeeeeeeeesaaeeeesaeeeeeneey 3 7 Figure 5 1 Embedded Utilities Memory BlocCk ooccccocccococococococoncncononnccnnnnonanonnnrononacnconcnconnnnnnos 5 2 Figure 5 2 POL LOC Structure Deo assa tins dee estes DS 5 5 PCI 731 User s Manual iii Revision 1 0 September 2001 CONTENTS ld Microsystems LIST OF TABLES Table 1 1 CPCI 812 Power Requirements erre ererer errar eren aerea are encena nana 1 4 Table 1 2 Environmental SOCCWIICATIONS sra d 1 4 Table 2 1 Serial Interrupt Assignment cer eeerrree er erene ne rreee rare ren ac erene na ce rena nreda 2 3 FADIGA VENON ENOO Sali liad 2 4 Tables Console Por Connector acidente cnica 3 1 Table 3 2 UART Register Addresses scarico ia A ca Edna date da aaa do eadeweiedeuenreveests 3 2 Tables JM AG ICOP PIN ASSIGNMEN Detect atari cnc Db di aia cds 3 5 Table 3 4 12C DEVICE AOS OS junio aa Sed a TD A ea 3 6 Tables DSI GORMNECION assis saia dota dan iso da saia a E nd Dan a Rd Dr ic ar ao ioois 3 7 Table 4 1 Secondary Address Map for ATM SAR Registers seen 4 1 Table 4 2 ATM SAR General Mode Register cooocccccoccncococcnccon
24. coset polynomial to the HCS octet before transmission Clearing the SCR bit bit 2 disables the payload scrambling function Setting the HCSINS bit bit7 forces the calculated HCS to overwrite the HCS octet that is the SUNI PDH generates and inserts the HCS Clearing the FIFODP 1 0 bits bits 4 3 sets the transmit FIFO depth to 4 cells TXCP Interrupt Enable Status Setting the TFULL4 bit bit4 sets the TFIFOFB TCA pin to behave as an almost full indication This was found to work best with the ATM SAR TXCP Idle Unassigned Cell Pattern H4 octet Setting the transmit idle unassigned cell pattern for the H4 octet to 01h Causes idle cells to be generated Clearing it to 00h causes unassigned cells to be generated TXCP Idle Uassigned Cell Pattern H5 octet Setting the transmit idle unassigned cell pattern for the H5 octet to 52h is the correct HCS for idle cells Setting the H5 octet to 55h is the correct HCS for unassigned cells TXCP Idle Unassigned Cell Payload Setting the transmit idle unassigned cell payload to 6Ah is the correct value for idle or unassigned cells The registers listed in the Table 4 4 have been modified from their power up reset default values The TIXC is setup for 24 frame Extended Superframe Format ESF and Bipolar 8 Zero Substitution B8ZS line coding as required by the ATM Forum DS1 Physical Layer Specification All interrupts are disabled Loopback modes are not enabled Also see the T1 XC manu
25. e 21554 bridge and the PCI9080 bridge is contained within the MPC8240 The bus arbitration unit allows fairness as well as a priority mechanism A two level round robin scheme is used in which each device can be programmed within a pool of high or low priority arbitration One member of the low priority pool is promoted to the high priority pool As soon as it is granted the bus it returns to the low priority pool 3 8 DMA CHANNELS The MPC8240 processor features two DMA channels Data movement occurs on the PCI and or memory bus Each channel has a 64 byte queue to facilitate the gathering and sending of data Both the local processor and PCI masters can initiate a DMA transfer Some of the features of the MPC8240 DMA unit include misaligned transfer capability scatter gather DMA chaining and direct DMA modes and interrupt on completed segment chain and error Figure 3 2 provides a block diagram of the MPC8240 DMA unit CPCI 812 User s Manual 3 3 Revision 1 0 August 2000 HARDWARE 3 9 3 10 3 4 CYCLONE Microsystems DMA 1 DMA 0 To memory interface Figure 3 2 MPC8240 Processor DMA Controller MESSAGE UNIT The MPC8240 provides a message unit MU to facilitate communications between the host processor and peripheral processors The MPC8240 s MU can operate with generic messages and doorbell registers and also implements an 1 0 compliant interface The Intelligent Input Output 1 0 specification allows arch
26. e EPIC unit is set to serial interrupt mode Serial interrupt mode allows for a maximum of 16 external interrupts Table 2 1 shows the assignment of devices to serial interrupts on the CPCI 812 all the interrupts are level sensitive The EPIC interface also contains several internal interrupt sources These include the four global timers the two DMA channels the 12C bus and from the Message Unit In addition to the EPIC interface errors detected by the MPC8240 are reported to the processor core by asserting an internal machine check signal Many of the errors detected in the MPC8240 cause exceptions to be taken by the processor core The error reporting 1s provided for three of the primary interfaces processor core interface memory interface and the PCI interface The ATM SARs TIXCs and SUNI_PDHs generate interrupts The SUNI PDHs and T1XCs interrupt via the ATM SARs Thus there are only two interrupts required SARI INT and SAR2 INT If the SUNI PDH or T1XC is the interrupt source the ATM SARs will interrupt the host and will have a bit set in its status register indicating that the SUNI PDH or TIXC was the interrupt source Table 2 1 Serial Interrupt Assignment INTERRUPT INTERRUPT SOURCE POLARITY MIC INTB MIC INTA SAR1 INT SAR2 INT 7 DO meno o MIC INTD MIC INTC 13 Not Used 14 Not Used MPC8240 Interrupt Registers The MPC8240 processor has several different EPIC register maps to facilitate the handling of interrupts
27. ems Normal oopback Mode RE Control Memory Parity Disabled ea 0 eses Sets Registers to Word Boundaries at So for Proper Operation 4 2 2 SUNI PDH REGISTERS The registers listed in Table 4 3 have been modified from their power up reset default values In general the SUNI PDH is setup for direct cell mapping HEC cell delineation and no payload scrambling as required by the ATM Forum DS1 Physical Layer Specification All interrupts are disabled and loopback modes are not enabled Also see the SUNI PDH manual section Basic Operating Modes Table 4 3 SUNI PDH Non Default Register Settings ADDR DATA Register name and Description 000h 08h SUNI_PDH Configuration Setting the FRMRBPP bit bit3 bypasses the DS3 E3 framer SPLR Configuration 028h 80h Setting the FROM 1 0 bits bits 7 6 to 1 0 selects DS1 framing format and clearing the PLCPEN bit bit 2 disables the PLCP framing function of the SMDS PLCP Layer Receiver Block SPLT Configuration 02Ch 80h Setting the FORM 1 0 bits bits 7 6 to 1 0 selects DS1 framing format and clearing the PLCPEN bit bit 2 disables the PLCP framing function of the SMDS PLCP Layer Transmitter block RXCP Control Setting the HCSADD bit bit 5 enables the addition of the coset 040h 98h polynomial to the received HCS octet before comparison with the calculated result Clearing the DSCR bit bit 3 disables the payload descrambling function Setting the BLOCK bit bit3 blocks Id
28. gions As shown in Table 5 1 PCI9080 Base Address 2 1s used to access the registers on SARO and Base Address 3 is used to access SARI User software should read these base address registers and add the appropriate SAR register offset to create a pointer to a particular SAR register Register offsets on the CPCI 812 are incremented by 4 bytes For example to create a pointer to the SAR General Status Register on Unit 1 one would read the value of Base Address 3 on the PCI9080 device and add to it the GSR offset 0x04 Note that PCI9080 configuration places the device into Big Endian mode Therefore no endian conversions are necessary when accessing the SAR registers direct or indirect despite the fact that the PCI bus is little endian However accessing the memory mapped registers on the PCI9080 does require a big to little endian byte swap before writing or after reading Table 5 1 PLX PCI9080 Base Address Registers on CPCI 812 Base Address Size Register Requested PCI Base Address to access memory mapped ene lid PCI9080 Configuration Registers PCI Base Address to access l O mapped ia at PCI9080 Configuration Registers PCI Base Address to access SAR Unit 0 region PRIDE pee is translated to 0OxC00xxxxx on the local bus PCI Base Address to access SAR Unit 1 region SADO RODO is translated to OxC80xxxxx on the local bus 5 4 4 Changing PCI Configuration PCI memory or I O size requests must be configured before PCI initiali
29. gned 2 Kbyte blocks 72 bit SDRAM with ECC running at 100MHz allows a maximum throughput of 800 Mbytes per second The MCU keeps four pages open simultaneously Simultaneously open pages allow for greater performance for sequential access distributed across multiple internal bus transactions CONTROL MEMORY T1XC amp SUNI PDH REGISTERS The CPCI 812 s SRAM is control memory used exclusively by the ATM SARs The control memory can be accessed via the ATM SARs using an INDIRECT_ACCESS command Parity generation and checks are not performed on the control memory As shown in the figure the SUNI PDH and TIXC processor interfaces are also attached to the control memory bus The SUNI PDH and T1XC registers are accessed via the ATM SARs using an INDIRECT ACCESS command FLASH ROM The CPCI 812 provides 2 Mbytes of sector programmable Flash ROM for non volatile code storage The Flash ROM is located in local memory space at address FFEO 0000h through FFFF FFFFh The mapping ensures that after a reset the MPC8240 processor can execute the hard reset exception handler located at FFFO 0100h CONSOLE SERIAL PORT A single console serial port with an RS 232 line interface has been included on the CPCI 812 The port is connected to a RJ 11 style phone jack on the adapter and can be connected to a host system using the included phone jack to DB 25 cable Cyclone P N 530 2002 The pinout of the console connector is as shown in Table 3 1 Table 3 1 Con
30. hich interfaces the ATM SARs The CPCI 812 uses an Intel 21554 Embedded PCI to PCI Bridge to bridge between the primary CompactPCI bus and the secondary local PCI bus This device complies with the PCI Local Bus Speci fication revision 2 1 It provides concurrent bus operation allows buffering for both read and write transactions and provides support for Hot Swap operation The primary PCI interface is 64 bit data but will operate correctly when the CPCI 812 is plugged into a 32 bit CompactPCI slot Although the secondary PCI bus of the 21554 is 64 bit data the local bus of the CPCI 812 is 32 bit the MPC8240 and PCI9080 are 32 bit PCI devices The data path to memory of the CPCI 812 is 64 bit The memory controller resides on the MPC8240 The Flash ROM on the CPCI 812 can be reprogrammed by software through a JTAG COP interface Utilities to perform this programming are available from software development tool vendors Additional information on the JTAG COP interface can be found in section 3 10 SPECIFICATIONS Physical Characteristics CPCI 812 is a single slot double high CompactPCI peripheral card Height 9 187 233 35mm Double Eurocard 6U Depth 6 299 160mm Width 8 20 32mm Power Requirements The CPCI 812 requires 5V 12V and 3 3V from the CompactPCI backplane J1 connector The following table represents the power consumption of the CPCI 812 CPCI 812 User s Manual 1 3 Revision 1 0 August 2000 GENERAL
31. itecture independent I O subsystems to communicate with an OS through an abstraction layer The specification is centered around a message passing scheme An LO compliant peripheral IOP is comprised of memory processor and input output devices The IOP dedicates a certain space in its local memory to hold inbound from the remote processor and outbound to the remote processor messages The space is managed as memory mapped FIFOs with pointers to this memory maintained through the MPC8240 LO registers Please refer to the MPC8240 User s Manual for LO register descriptions FIFO descriptions and an LO message queue example JTAG COP SUPPORT The MPC8240 provides a Joint Test Action Group JTAG interface Additionally the JTAG interface is also used for accessing the common on chip processor COP function of PowerPC processors The COP function of PowerPC processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor The 16 pin COP header sample part is Samtec HTSW 108 07 S S is located at J5 The COP header adds many benefits including breakpoints watchpoints register and memory examination modification and other standard debugger features The COP header definition is shown in Table 3 3 The location of pin 1 on the header is indicated by the cut off
32. jority of the 2 Mbyte Flash ROM can be used POWERPC MPC603E CORE CACHE BUFFERS ARRAYS The processor core provides independent on chip 16 Kbyte four way set associative physically addressed caches for instructions and data and on chip instruction and data memory management units MMUs The MMUs contain 64 entry two way set associative data and instruction lookaside buffers TLB that provide support for demand paged virtual memory address translation and variable sized block translation The processor also supports block address translation BAT arrays of four entries each As an added feature to the MPC603e core the MPC8240 can lock the contents of one to three ways in the instruction and data cache or the entire cache CPCI 812 User s Manual 2 1 Revision 1 0 August 2000 MPC8240 PROCESSOR T CYCLONE 2 5 MEMORY MAP Figure 2 1 shows the CPCI 812 memory map Flash ROM dias A On board Devices FFOO 0000 Board ID Register read only PCI INT ACK FF70 0000h FEFO 0000 Geographic Address LED Register write only FF20 0000h PCI Config ADDR FFOO 0000h PCI I O Space PCI Memory Space 8000 0000 4000 0000 0000 0000 Figure 2 1 CPCI 812 Memory Map 2 2 CPCI 812 User s Manual Revision 1 0 August 2000 ld Microsystems 2 6 2 6 1 GENERAL INTRODUCTION INTERRUPTS The CPCI 812 interrupt scheme is based upon the MPC8240 processor s embedded programmable interrupt controller EPIC Th
33. le Unassigned cells from the receiver FIFO RXCP Framing Control 041h 01h Setting the DELIN bit bit0 enables the ATM cell Delineator ATMF Block That is HEC based cell delineation is enabled RXCP Idle Unassigned Cell Pattern H4 octet Setting the receive idle unassigned cell pattern for the H4 octet to 01h causes idle cells to be filtered and clearing to OOh causes unassigned cells to be filtered if the mask pattern for the H4 octet is configuring to look at all bits in the octet See the setting of the RXCP Idle Unassigned Cell Mask H4 octet ADDR 04Ah 047h RXCP Idle Unassigned Cell Mask H1 octet 048h FFh RXCP Idle Unassigned Cell mask H2 octet 046h 01h CPCI 812 User s Manual 4 3 Revision 1 0 August 2000 ATM PROGRAMMING INFORMATION Lal 4 4 T1XC Registers Microsystems RXCP Idle Unassigned cell Mask H3 octet Setting the receive idle unassigned cell mask for the H1 H2 and H3 octets to FFh causes all bits in all three octets to be compared with their corresponding RXCP Idle Unassigned Cell Patterns RXCP Idle Uassigned Cell Mask H4 octet Setting the receive idle unassigned cell mask for the octet to Feh cause all bits except bit O of the H4 octet to be compared with their corre sponding RXCP Idle Uassigned Cell pattern With this setting both idle cells H4 01h and unassigned cells H4 00h get filtered from the receive FIFO TXCP Control Setting the HCSADD bit bit5 enables the addition of the
34. ources and handles internal interrupts from the I C LO and 2 DMA channels Table 5 2 shows the EPIC hardware interrupts and the assigned default interrupt priorities These interrupt priorities can be modified by the application programmer by changing the vector priority values in the table called priTable_812 in the BSP file epic c and recompiling the BSP Priority values are in the range of 15 to O with 15 being the highest priority O inhibiting the interrupt altogether For further information on the MPC8240 EPIC consult chapter 4 of the MPC8240 User s Manual CPCI 812 User s Manual 5 5 Revision 1 0 August 2000 pSOS SOFTWARE DEVELOPMENT ld Microsystems Table 5 2 CPCI 812 Interrupt Vectors INT INT NUMBER VECTOR SOURCE PRIORITY LEVEL DESCRIPTION 2 E E 1 1 2 DMAO Interrupt from DMA Channel 0 2 DMA1 Interrupt from DMA Channel 1 23 MSG_UNIT Interrupt from Messaging Unit 5 5 1 Connecting and Disconnecting Interrupt Handlers in pSOS 2 5 20 Interrupt from PC Controller 1 2 PSOS utilities for connecting and disconnecting interrupt handlers to these interrupts can be found in the BSP file isr c The function PssSetIntHandler is used to connect and enable an interrupt handler long PssSetIntHandler ULONG Level J Inte rrupt vector number void handler Pointer to handler function VOLO Haro Optional argument to handler ULONG type Optional wrapper type 2 6 CPCI 812 User
35. ser s Manual 1 1 Revision 1 0 August 2000 GENERAL INTRODUCTION Id CYCLONE Microsystems 1 2 1 2 FEATURES MPC 8240 Processor 21554 PCI to PCI Bridge SDRAM CompactPCI Interface Flash ROM Console Serial Port Hot Swap Timers DMA Controller LO Messaging Hardware Segmentation Hardware Assembly Memory Access The microprocessor is Motorola s integrated MPC8240 PowerPC The device integrates a Motorola 32 bit superscalar PowerPC 603e core running at 250 MHz internally and Peripheral Components Interconnect PCI The core boasts a 16 Kbyte instruction cache a 16 Kbyte data cache and floating point support Memory can be accessed through the memory controller to the core processor or from the PCI bus The 21554 is a non transparent PCI to PCI bridge with a 64 bit primary bus interface and a 64 bit secondary interface A non transparent bridge allows the local processor to configure and control the local subsystem The 21554 primary bus interfaces with the 64 bit CompactPCI bus and the secondary bus interfaces with the 32 bit PCI bus of the MPC8240 64 MBytes of ECC SDRAM is standard on the CPCI 812 The CPCI 812 meets the PICMG 2 0 Rev 2 1 Specification for system slot adapters The PCI bus runs at 33MHz 2 Mbytes of in circuit sector programmable Flash ROM An RS 232 serial port is provided for a console terminal or workstation connection The serial port supports up to 115 Kbps and uses a
36. sole Port Connector Signal Description A Not Used Ground T Transmit Data R Receive Data Not Used ts CPCI 812 User s Manual 3 1 Revision 1 0 August 2000 HARDWARE ld 3 5 3 6 3 2 Microsystems Note Pin 1 is the contact to the extreme left look in the console port opening with the tab notch facing down The serial port is based on a 16C550 UART clocked at 1 843 MHz The device may be programmed to use this clock with the internal baud rate counters The serial port is capable of operating at speeds from 300 to 115200 BPS and can be operated in interrupt driven or polled mode The 16C550 register set is shown in Table 3 2 For a detailed description of the registers and device operation refer to the 16C550 databook Table 3 2 UART Register Addresses Address Write Register FFOO 0000H Transmit Holding Register FFOO 0008H Interrupt Enable Register FFOO 0010H FIFO Control Register FFOO 0018H Line Control Register FFOO 0020H Modem Control Register FFOO 0028H Unused FF00 0030H Unused FF00 0038H Scratchpad Register COUNTER TIMERS The MPC8240 processor is equipped with four 31 bit on chip counter timers which count at 1 8 the frequency of the SDRAM CIK signal or 12 5MHz Users should refer to the Processor User s Manual for the functionality and programming of the counters The timers can be individually programmed to generate interrupts to the processor when they count down to zero Two of the timers
37. sponsible for configuring the secondary side of the bridge as well as the PLX PCI9080 resident on the local PCI bus Downstream Inbound CompactPCl Transactions PCI BIOS software on the CompactPCI host is responsible for configuring the embedded bridge for inbound PCI transactions However the MPC8240 must first pre configure the device while the host s configuration cycles are being retried Preconfiguration of downstream PCI memory window 0 allows the host to assign a CompactPCI address to the CPCI 812 in Base Address Register 2 of the bridge that will translate to a valid PCI address on the local PCI bus This preconfiguration includes setting the PCI memory size request to the size of DRAM 64 MBytes and setting the translation value to 0x00000000 Once the preconfiguration is complete the retry condition is cleared on the bridge allowing the host to assign a CompactPCI address range to the device As a result all inbound PCI transactions claimed by the bridge are forwarded onto the local PCI bus where it is claimed by the MPC8240 and mapped to its respective address in DRAM As configured after system initialization the CompactPCI host or any other IOP card in the system can perform a PCI memory read or write to the 64 Mbytes that starts at the value stored in Base Address Register 2 of the embedded bridge This transaction will be translated to a local memory read or write with the base address mapping to DRAM address 0x00000000
38. temperature reading at any time reading after an interrupt clears the interrupt The sensor will not interrupt again until the temperature has dropped below the hysteresis setting Consult the LM75 data sheet for more details on programming the temperature sensors HOT SWAP The CPCI 812 is a PICMG 2 1 compliant Hot Swap board The CPCI 812 is a Full Hot Swap board with both Hardware and Software Connection control The CPCI 812 can be used on all platform types Non Hot Swap platform for a conventional system Hot Swap platform for a Full Hot Swap system and on High Availability platform for a High Availability system See the Hot Swap specifi cation for further explanation of platform board and system types CPCI 812 User s Manual Revision 1 0 August 2000 ld HARDWARE Microsystems 3 13 1 Hot Swap Extraction Process Removal of the CPCI 812 in a Full Hot Swap or High Availability system is the same The operator first only opens the ejector handles of the board A switch on the CPCI 812 signals to the system that it is to be extracted In response the system will illuminate the blue Hot Swap LED when extraction is permitted 3 13 2 Hot Swap Insertion Process Insertion of the CPCI 812 is the same in any Hot Swap system The operator slides the CPCI 812 into the desired slot and latches the handles 3 14 DS1 CONNECTOR The CPCI 812 uses a shielded RJ48C connector for the DS1 line interface Table 3 5 lists the pin connections and
39. to all registers in the EUMB Care must be taken to byte swap data transferred from memory to the PCI bus or EUMB registers pSOS provides the following functions to read and write data to from the PCI bus and EUMB They perform all required byte swapping The following function declarations are from pci pcihdr h void PciWrite32 ULONG addr ULONG value void PciWritel6 ULONG addr ULONG value void PciWrite8 ULONG addr ULONG value ULONG PciRead32 ULONG addr ULONG PciRead16 ULONG addr ULONG PciRead amp 8 ULONG addr PCI CONFIGURATION There are two PCI buses on the CPCI 812 The CompactPCI bus interconnects the CPCI 812 with the CompactPCI host and the other IOP cards in the system The local PCI bus connects the MPC8240 with the PLX PCI 9080 allowing access to the NEC SAR devices CPCI 812 User s Manual Revision 1 0 August 2000 CYCLONE Microsystems 5 4 1 5 4 2 5 4 3 pSOS SOFTWARE DEVELOPMENT The two buses are interconnected via the Intel 21554 embedded PCI to PCI bridge The primary side of this bridge is connected to the CompactPCI bus and the secondary side is connected to the MPC8240 PCI bus Because the 21554 is an embedded bridge non transparent PCI configuration cycles are not forwarded through it The device has two configuration spaces one for the primary side one for the secondary Therefore the CompactPCI host is responsible for configuring the primary side of the bridge and the MPC8240 is re
40. which are briefly mentioned below These registers occupy a 256Kbyte range of the embedded utilities memory block EUMB and can be read and written by software Please refer to the Motorola MPC8240 User s Manual for more details CPCI 812 User s Manual 2 3 Revision 1 0 August 2000 MPC8240 PROCESSOR hdl 2 6 2 2 4 Microsystems Global EPIC Registers Provides programming control for resetting configuration and initial ization of the external interrupts Additionally a vector register is provided to be returned to the processor during an interrupt acknowledge cycle for a spurious vector Global Timer Registers Each of the four global timers have four individual configuration registers The registers are the Current Count register the Base Count register the Vector Priority register and the Destination register Interrupt Source This group of registers are made up of the vector priority and Configuration destination registers for the serial and internal interrupt sources This includes the masking polarity and sense Processor Related Registers This group describes the processor related EPIC registers They are made up of the Current Task Priority register the Interrupt Acknowledge register and the End of Interrupt register Error Handling and Exceptions Errors detected by the MPC8240 are reported to the processor core by asserting an internal machine check signal mcp The MPC8240 detects illegal transfer types from the
41. zation occurs be it on the CompactPCI or local PCI bus Therefore any required changes to the default PCI configuration described above must be done in the BSP file pcicfg c All PLX PCI9080 pre PCI configuration occurs in the function preconfig 9080 and all pre PCI configuration on the 21554 embedded bridge device occurs is preconfig 21554 For further information on PCI configuration consult the Intel 21554 Embedded PCI to PCI data sheet the PLX PCI9080 data sheet chapter 8 of the MPC8240 User s Manual and chapter 6 of the pRISM Advance Topics Guide 5 4 5 pSOS PCI Device Driver Interface The CPCI812 BSP uses pSOS PCI Auto Configuration to configure the PCI devices on the local PCI bus This procedure creates and maintains a list of PCI information in a PCI device list Thus device driver developers can use any of the functions described in chapter 6 of the pRISM Advance Topics Guide to find claim or access either the embedded bridge or the PCI9080 and thus the SCA devices In addition the PCI header file pci pcihdr h provides useful prototypes and important macros for dealing with PCI devices 5 4 CPCI 812 User s Manual Revision 1 0 August 2000 CYCLONE Microsystems 5 5 pSOS SOFTWARE DEVELOPMENT One important definition in this header file is the PCI LOC structure which is used to define the PCI location of a particular device This structure is defined below in Figure 5 2 At PCI configuration a list of PCI_LOC
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