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FASTCOM™: ESCC-ISA HARDWARE MANUAL

Contents

1. 8 Factory Switch Settings EET ER 8 Installing the Windows NT ESCC 8 Testing The Installation Building ihe Loopback Pyg TT eae 11 INT TS E E EEA EEEE 11 Windows 95 13 REFERENCE Switch Descriptions ATA tal f 16 17 17 DMA Channel 18 AA 19 19 PROTECTS 20 a Ci HIE I E 21 Termination nnzzzzznnznzzzzzzanzzzzz 22 PROGRAMMABLE CLOCK GENERATOR Cypress ICD2053B 23 DETERMINING AND SELECTING BAUD 24 TECHNICAL SUPPORT 000 0 ccccccccceccecceeccecceeccecceecceccecceeececnescaeccecsesecesneesseccesseseeesessseenes 31 APPENDIX A Register Map amp Address 55 5 5 gt 5555 aoa a koxkkkkbiakkkakakamkakktikiu 32 APPENDIX B SAB 82532 Technical Data acu 39 COMNVTECH COMMUNICATION TECHNOLOGIES EU ROPEAN UNION DECLARATION OF CONFORMITY Information Technology Equipment The Compa
2. 282H MODE MODE MODE MODE MODE MODE 283H TIMR TIMR TIMR TIMR TIMR TIMR 284H XAD1 XAD1 od SVNL SYNL 285H XAD2 XAD2 SYNH SYNH 286H RAH1 TCR TCR TCR 287H RAH20 DAFO DAFO DAFO 288H RAL1 RAL1 RFC RFC RFC 289H RHCR RAL2 28AH RBCL XBCL RBCL XBCL RBCL XBCL 28BH RBCH XBCHH RBCH XBC RBCH XBCH 28CH CCRO CCRO CCRO CCRO CCR CCRO 28DH CCR1 CCR1 CCR1 CCR1 CCR1 CCR1 28EH CCR2 CCR2 CCR2 CCR2 CCR2 CCR2 28FH CCR3 CCR3 CCR3 CCR3 290H 291H TSAR 292H XCCR 293H RCCR 294H VSTR BGR VSTR BGR VSTR BGR 295H 296H PRE PRE d PRE PRE 297H 298H GIS IVA GIS IVA GIS IVA 299H IPC IPC IPC IPC IPC 29AH ISRO IMRO ISRO IMRO ISRO IMRO 29BH ISR1 IMR1 ISR1 IMR1 ISR1 IMR1 29CH PVR PVR PVR PVR PVR PVR 29DH PIS PIM PIS PIM PIS PIM 29EH PCR PCR PCR PCR PCR PCR 29FH do 2A0H FIFO FIFO FIFO FIFO FIFO FIFO PVR Register The 82532 has an 8 bit I O port PVR that has the following functions on the FASTCOM ESCC ISA Bit 0 Channel select 4 DTR channel 2 output 0 channel 1 1 channel 2 5 DSR channel 1 input 1
3. 3136 3200 3264 3328 3392 d80h 3456 dooh 3520 e00h 3584 e40h 3648 eBOh 3712 3776 fO0h 3840 f40h 3904 f80h 3968 36 Hex Decimal 1000h 4096 120408 4160 1080h 4224 I0cOh 4288 1100h 4352 H140h 4416 111808 4480 1200h 4608 112408 4672 11280h 4736 4800 1300h 4864 1340h 4928 1380h 4992 13c0h 5056 1400h 51200 1440h 5184 1480h 5248 14c0h 5312 H500h 5376 1540h 5440 1580h 5504 15c0h 5568 1600h 5632 1640h 5696 1680h 5760 16c0h 5824 1700h 5888 1740h 59520000 1780h 6016 17e0h 6080 1800h 6144 1840h 6208 2345678 eee eo EN 10111101 911142904 TIVE TES 01011101 10011101 00011101 ere v 01101101 10101101 135902301 01001101 10001101 00001101 ENTUM EN 10110101 00110101 hd oa on d 01010101 28043904591 00010101 LERS TADE 01100101 10100101 00100101 11000101 UTEM 10000101 00000101 eter os Hex Decimal 1880h 6272
4. 18c0h 6336 1900h 64000 1940h 6464 1980h 6528 1900h 6592 6656 iladoh 6720 HaBOh 6784 lacoh 6848 6912 HIb40h 6976 7040 Hoch 7232 7296 73600 7424 7552 7616 le00h 76800 1744 ile8Oh 7808 Hec h 7872 1 00h 7936 15408 8000 8064 1fo0h 8128 2000h 8192 2040h 8256 2080h 8320000 2000h 8384 2345678 0444004 00111001 11011001 01011001 10011001 00011001 11101001 Hex Decimal 12100h 8448 12140h 8512 2345678 01011110 20014410 Le oa nae 01101110 10101110 00101110 11001110 01001110 10001110 00001110 Qd 0 6 10110110 00110110 020101160 01010110 10010110 00010110 11100110 01100110 10100110 00100110 11000110 01000110 10000110 00000110 Legere ao 01111010 10111010 00111010 5014010 01011010 Hex Decimal 234567 8 1969110429 00011010 11101010 01101010 10101010 00101010 11001010 01001010 10001010 00001010 11110010 TETTEN 10110010 00110010 11010010 01010010 10010010 00010010 11100010 01100010 10100010 00100010 11000010 0100001
5. 5 DMA SELECT 5 4 MODE 1 CONFIG 50 5 MODE RS 422 DMA DISABLED TXCLK IS OUTPUT MODE 2 CONFIG SW6 NO LOOPBACK 485 CTS DISABLED INSTALLING THE WINDOWS NT 2000 ESCC DRIVER NT 2000 driver for the FASTCOM ESCC ISA is the ESCCDRV SYS It is a kernel mode driver The NTINSTALL EXE program is intended to simplify the process of adding registry information about the base address interrupt and DMA information about each channel INSTALL DRIVER Pressing this button will copy the ESCCDRV SYS file to your C winnt system32 drivers subdirectory It will create the following subkey in the registry HKEY_LOCAL_MACHINE SYSTEM CurrentControlSet Services esccdrv In that key it adds the following information DisplayName REG_SZ esccdrv ErrorControl REG_DWORD 0x01 ImagePath REG_EXPAND_SZ 7 C WINNT System32 Drivers esccdrv sys Start REG_DWORD 0x02 Type REG_DWORD 0x01 These values are actually created by the CreateService API call The CWINNT part of the image path will should reflect your installed system directory i e the system drive and where your Windows files are installed and could be different depending on how you originally installed Windows Start parameter is set to automatic This will load and run the driver every time that Windows is started If you want to start and stop it manually you can change the start type by using the Control Panel g
6. RED TRANSMIT ACTIVE FASTCOM ESCC ISA CARD GREEN RECEIVE ACTIVE CABLE ASSEMBLY FASTCOM CD If an omission has been made please call technical support for a replacement FASTCOM ESCC ISA DB37 FEMALE CONNECTOR PIN DESCRIPTION GND 2RT 1RT 1DSR 2RD 2CTS 25 2DCD 1RD 1CTS 1ST 1DCD 2SD 2RTS 2TT 1SD 1RTS 1 1DTR 1 2 3 4 5 6 7 8 9 The cable provided splits each channel from this DB37 to individual RS 530 pin out DB25 male connectors The DB25 pin outs are shown on the next page FASTCOM ESCC ISA ersi DB25 CABLE CONNECTOR ST B DESCRIPTION RS 530 pin out D GND RT Bon J8 Brom DSR RTS RTS RT PIN DESCRIPTIONS GND d PIN DESCRIPTION 422 TYPE CONNECTED TO 530 CIRCUIT 1 SHIELD GROUND GND 7 SIGNAL GROUND GND AB 2 TRANSMIT DATA A SD BA 14 TRANSMIT DATA B SD BA 3 RECEIVE DATA A RD BB 16 RECEIVE DATA B RD BB 4 REQUEST TO SEND A RTS CA 19 REQUEST TO SEND B RTS CA 5 CLEAR TO SEND A CTS CB 13 CLEAR TO SEND B CTS CB The RS 422 A side is 0 volts when 1 is on the line A side is the negative terminal of the 422 driver 6 DATA SET READY DSR INPUT 20 DATA TERMINAL READY DTR OUTPUT CLOCK SIGNALS PIN DESCRIPTION 422 TYPE CONNECTED TO 530 CIRCUIT 8 DATA CARRIER DETECT A DCD CF 10 DATA CARRIER DETECT B DCD CF 24 TRANSMIT CLOCK OUT A TT DA 11 TRANS
7. So by selecting a value for input clock that is less than 10 MHz since the bit rate is slow we will want to use master clock mode which will require a 10 MHz or less clock we can then calculate the value needed for N to get a 19200 bps output will pick 7 372800 MHz for the input clock To get the programming word for this frequency run bitcalc and enter the reference frequency 18 432 MHz and the desired frequency and get the following values clkbits 0x0E9920 the stuffed hex programming word and 27 E numbits 23 the number of bits in the stuffed programming word counted from the stuffed binary word Calling the IOCTL_ESCCDRV_SET_CLOCK ioctl function with these parameters will get us an input clock of 7 3728 MHz referred to as OSC in table 5 Then solving for N we get 19200 7 3728E6 N 1 2 N 191 0x0BF Checking the notes to make sure we did not violate anything Fm Fx 7 3728E6 19200 384 gt 2 5 we are OK on this one Fr Fm rxclk input 7 3728E6 lt 3 assuming a 19200 clock input 19200 7 3728E6 0026 lt 3 we are OK on this one amp Ox3f lt 0 checking the value of n to make sure it isn t forced to zero due to the glitch in the 82532 Important Register Settings MODE 0x88 This sets the 82532 in transparent HDLC mode 0 This will use a frame structure as Ox7E data CRC CRC Ox7E No address recognition is used The timer is in external mode RTS is handled
8. COMMUNICATION TECHNOLOGIES 9011 E 37th Street North Chief Engineer Wichita KS 67226 2006 316 636 1131 Fax 316 636 1163 INTRODUCTION The new FASTCOM ESCC ISA is a very high speed dual channel synchronous asynchronous serial communications adapter based upon the Siemens 82532 Enhanced Serial Communication Controller ESCC The FASTCOM ESCC ISA is designed to support data rates up to 10 Mbits second and to reduce the hardware and software overhead needed for serial communications Each sync async channel on the FASTCOM ESCC ISA has its own DPLL encoder decoder and programmable protocol support The FASTCOM ESCC ISA directly supports HDLC X 25 LAP B ISDN LAP D SDLC ASYNC and BISYNC protocols and features a high speed RS 422 RS 485 interface conforming to ANSI EIA TIA 530 A 1992 configuration RS 530 The FASTCOM ESCC ISA features two fully independent channels Async and bisync protocol support allow for greater data handling flexibility HDLC features include choice of CRC polynomial CRC CCITT or CRC 32 expanded line encoding methods FM and Manchester and preamble transmission In addition a built in 64 byte FIFO and DMA capability provide the FASTCOM ESCC ISA with a very high throughput as well as requiring less system CPU time than other HDLC adapters Many engineers have avoided using synchronous communication adapters because of their programming complexity The FASTCOM ESCC ISA provides high speed data
9. bit 5 CCR2 amp 0xC0 2 BGR or if you prefer Most significant Least significant bit m CCR2 bit 8 CCR2 bit 7 BGR bit 7 BGR bit 6 n BGR 5 BGR 4 BGR 3 BGR 2 BGR 1 BGR 0 N CCR2 8 CCR2 7 BGR 7 BGR 6 BGR 5 BGR 4 BGR 3 2 BGR 1 0 If you are using the DPLL you should try to set its input clock to be as close to the actual bit frequency as possible This will allow for optimal clock recovery Also clock recovery relies on edges in the data stream if you transmit long segments of Os or 1s using an encoding method that produces no edges the results will be non optimal The ideal encoding for clock recovery is Manchester or a non 1 idle pattern i e constant flag sequences on idle if HDLC is used etc Let s start with something easy Let s say that you want to set up an ESCC channel to run in HDLC mode at 19200 bps that the device in question supplies a clock with its data receive clock and that we need to generate transmit a clock that matches our transmitted data To achieve this we should set the 82532 to clock mode Ob Set the mode switch position 5 or 7 to on enabling the txclk output driver selecting txclk as an output on TT The baudrate function bitrate input clock N 1 2 will be used If there are no other constraints other than operating one channel at 19200 bps then we can select both the input clock and N arbitrarily so long as we do not violate any of the notes
10. 00 PM Central Time If you purchased your board from Kontron America please call their 7 24 technical support line at 1 800 480 0044 2 Ask for technical support for the FASTCOM ESCC ISA Be ready to describe the problem your computer system your application and your software 3 If necessary our staff will give you an RMA number Return Material Authorization Use this number on the mailing label and in all references to your board Put the board back in its static bag and in its box Ship the board back to us as directed 4 If you prefer you may FAX a description of the problem to us at 316 636 1163 or we can be reached on the Internet at http Awww commtech fastcom com or by email at techsupport commtech fastcom com Kontron America can be reached by telephone at 800 480 0044 or on the web at http www kontron com support index cfm APPENDIX A FASTCOM ESCC ISA REGISTER MAP AND O ADDRESS SETTINGS 33 a FASTCOM ESCC ISA REGISTER MAP The following chart illustrates the register map of the FASTCOM ESCC ISA using the factory default address of 280H Refer to the Siemens SAB 82532 User s Manual for additional information on the registers HDLC SDLC ASYNC BISYNC Address Read Write Read Write Read Write 280H STAR CMDR STAR CMDR STAR CMDR 281H
11. 115200 32E6 16 N 1 2 7 68 Using 7 aa aa 29 bitrate 32E6 16 7 1 2 125000 bps Using N 8 bitrate 32E6 16 8 1 2 111111 bps The ideal situation would be to adjust the 32 MHz clock such that the deviation between the desired and actual rates is spread between both channels with the DPLL recovering the clock the actual clock that feeds it is not as critical as a clock mode that uses the clock directly Clock modes Ob 3b 4 and 7b are more sensitive to the selected rate in synchronous modes as there is no oversampling The rate you select is the rate you will get whereas oversampling modes using the DPLL or ASYNC BCR are more tolerant to differences between the rate you set and the rate you want On the following page is a block diagram representation of the clocking concept 30 Clocking Concept Block Diagram Pe ER 00 oa Clock Generator ICD2053B Channel 1 3 o d Switch positions 5 amp 6 EJ Channel 2 Switch positions 7 amp 8 Oscillator fBRG fTxCLK 3 x x 4 o G xc x 0 MM a ae e a a 4 Ob 2b 1 0 4 2alb 3b 0a b 7a 3b 6b 5 2a 7b 1 7b 6a 6a b 5 Ta fTRM fREC CCRO MCE 1 i Core Transmitter Receiver 31 TEC
12. ICD2053B clock 6 DSR channel 2 input 2 ICD2053B data 7 TC from ISA bus input 3 DTR channel 1 output from PC s DMA controller 34 ADDRESS SETTINGS The FASTCOM ESCC ISA requires 33 contiguous bytes of address space The following are I O addresses devices that are typically assigned to them You may use any address that is not used by a device installed in your system HEX RANGE 000 01F 020 040 05F 060 06F 070 07 080 09 0 0 ODF OEO OEF OFO OFF 100 1EF 1F8 1F9 1FF 200 207 208 20B 20C 20D 20E 21E 21F 220 22F 230 23F 240 277 278 27F 280 2AF 2 0 2DF 2E0 2E7 2E8 2EF 2F0 2F7 2F8 2FF 300 31F 320 32F 330 35F 360 36F 370 377 378 37F 380 38F 390 393 394 3AF 3D0 3DF 3E0 3E7 3E8 3EF 7 8 DEVICE DMA CONTROLLER 1 INTERRUPT CONTROLLER 1 TIMER KEYBOARD REAL TIME CLOCK DMA PAGE REGISTER INTERRUPT CONTROLLER 2 DMA CONTROLLER 2 UNUSED 16 contiguous bytes MATH COPROCESSOR UNUSED 240 contiguous bytes FIXED DISK UNUSED 7 contiguous bytes GAME PORT UNUSED 4 contiguous bytes RESERVED UNUSED 16 contiguous bytes RESERVED UNUSED 16 contiguous bytes BUS MOUSE UNUSED 56 contiguous bytes PARALLEL PORT SECONDARY UNUSED 48 contiguous bytes ALTERNATE EGA UNUSED 8 contiguous bytes C
13. baud rates can be derived from one clock value Changing the clock generator output will affect the baud rates of both channels ESCCO ESCC1 26 If you are using HDLC or Bisync as a data format there is not a BCR setting no oversampling However if you select a clock mode that uses the DPLL as a source it will effectively add a divide by 16 to your function Selecting the appropriate clock mode is a matter of identifying what clock signals are available external to the Fastcom card and what clock signals are required by the external device The simplest mode is using external clocks only mode 0a in this mode both the receive and transmit timing are taken from the connector RT for receive ST for transmit The rest of the modes are a mix of external signals and internally generated clocks clock recovery The DPLL modes only operate up to 2 MHz If the bitrate is above that you should use a non DPLL mode The bitrate functions are similar to the async case If you are not using a clock mode that uses the DPLL the formula is bitrate input clock BGR If you are using the DPLL the formula is bitrate input clock BGR 16 The input clock will depend on the clock mode It is usually either the OSC input or the RXCLK RT input see table 5 page 84 of the 82532 data sheet If BDF 1 BGR 1 If BDF 0 BGR N 1 2 If BDF 0 and EBRG 1 BGR 1 2 V 3 x of the 82532 silicon only The BDF bit is in CCR2
14. by the 82532 active while transmitting Timer resolution is 32768 clocks CCRO 0xCO This sets the 82532 in power up mode Master clock mode is enabled NRZ is the encoding type HDLC mode is selected CCR1 0x10 This selects clock mode O b The tx pin is using a push pull output required Time fill is all 1 s idle pattern Oxff CCR2 0x38 This selects the BGR N 1 2 divisor Selects txclk to be an output Selects clock mode Ob the B part Enables the CRC CCITT polynomial CCR3 0x00 No preamble output CRC reset level Oxffff CRC is in use both transmit and receive not including CRC in received Data not returned to the user Not using extended window for DPLL CCR4 0x00 Not using master clock 4 Not using enhanced baud rate generator FIFO threshold is 32 bytes mandatory for NT driver in HDLC mode 28 BGR 0xBF This sets the output clock rate to 19200 given that the input clock was previously set to 7 3728 MHz and the above registers are set as shown CCRO CCR1 CCR4 and BGR are the most critical registers that effect the bitrate the rest are shown for completeness and depending on the system you can easily change some parameters without affecting the bitrate i e line encoding address recognition crc type etc And now for something a bit more difficult Let s say that you want to run one channel asynchronously at 38400 bps and the second channel synchronously using HDLC at 2 Mbps How woul
15. communications to designers and engineers while greatly reducing development time and system complexity The FASTCOM ESCC ISA is also available for the PC 104 bus FASTCOM ESCC 104 and for the PCI bus FASTCOM ESCC PCI The following diagram illustrates the basic structure of the FASTCOM ESCC ISA PC BUS CHANNEL 1 OF 2 RS 530 T xa 0 SD 25 5 82532 m SD o COMMUNICATION RD A13 a lt CONTROLLER 2 i RD 50 RTS NE RTS m N m 3 non o CTS Y T lt 3i ul beo lt TEE DATA DCD Ta DSR D15 DTR RT RA dt o RT 5 E ST 229 T5 E INTERRUPT RIT so Er zag 50 SE ESO TT lt 2 3 IRQ 15 Z 6 2 HW O DMA 1 Tos DMA 3 cte 549 DMA5 BES EZH DMA7 3 SPECIFICATIONS COMMUNICATION CONTROLLER DRIVERS RECEIVERS CONNECTOR CONFIGURATION POWER REQUIREMENTS BUS INTERFACE ENVIRONMENT Operating Temperature Range Humidity FEATURES High speed up to 10Mbits s SIEMENS 82532 RS 422 RS 485 ANSI EIA TIA 530 A 1992 5V 300mA TYPICAL 16 BIT ISA IBM AT 386 486 0 to 70C 0 to 90 non condensing Much easier to program and use than other HDLC adapters Supports HDLC SDLC ISDN LAP D and X 25 LAP B ASYNC BISYNC Drivers RS 422 RS 485 multi drop Excellent noise
16. on RS 422 mode The DMA enable switch es control the connection to the ISA DMA channels In the on position DMA is enabled for that channel both RX and TX DMA channel selects will be active for that channel In the off position DMA is The TXCLK input output switch connects the TXCLK pin on the 82532 to either the TT signal lines to output the transmit timing or the ST signal lines to input the transmit timing If the input selection is made with position 6 or 8 on do not configure the 82532 TXCLK pin as an output SWITCH 6 MODE 2 SWITCH CTS Disable Channel 2 CTS Disable Channel 1 SD RD loopback Channel 2 SD RD loopback Channel 2 SD RD loopback Channel 1 SD RD loopback Channel 1 The Mode 2 switch controls the RS 485 loopback feature connecting the SD signals to the RD signals internally so you don t have to make the connection on your cable It also controls the CTS disable feature Since the 82532 will only transmit when its CTS pin is active this switch allows the 82532 to see the CTS input as active all the time regardless of the signal at the connector The loopback switch positions are provided for RS 485 mode and should be used in pairs Positions 1 and 2 should either be on creating a loopback for RS 485 mode or off for RS 422 mode Likewise positions 3 and 4 should either both be on or both off The CTS disable switch is used to force CTS into the active state in the
17. on position to allow the 82532 to transmit data if the CTS signal line is not used In the off position the CTS signal from the connector is connected to the 82532 and the 82532 will not transmit unless the external CTS signal is active 20 PROGRAMMING Refer to the ESCC Tools on this CD for example programs product updates and software for testing your installation Refer to the Siemens SAB 82532 User s Manual for register information This CD contains software drivers and example programs for the Fastcom ESCC ISA It will also contain any current notes on the hardware or software NOTES Do not select the same channel for both DMA receive and DMA transmit Always set the 82532 port configuration register PCR to Always set the 82532 interrupt port configuration IPC to 03H Always set the 82532 CCR1 ODS bit to 1 21 RS 422 RS 485 Most engineers have worked with RS 232 devices at least once in their career If you have never worked with RS 422 or RS 485 devices you will be pleased to know that working with the FASTCOM ESCC ISA is not much different from working with an RS 232 device The RS 422 standard was developed to correct some of the deficiencies of RS 232 In commercial and industrial applications RS 232 has some significant problems First the cable length between RS 232 devices must be short usually less than 50 feet at 9600 Baud Second many RS 232 errors are the result of cables picki
18. rejection cable lengths up to 4000 feet Use low cost twisted pair cable RS 485 mode Up to 32 FASTCOM ESCC ISA adapters can share the same twisted pair Driver control is automatic via the RTS line Serial Interface Internal or External Clock Source Asynchronous Monosync Bisync and HDLC SDLC data formatting 1X isosynchronous or 16X oversampling for Asynchronous format Different modes of data encoding NRZ NRZI FMO FM1 Manchester CRC CCITT or CRC 32 for HDLC SDLC modes CRC CCITT or CRC 16 for BISYNC mode Modem control lines RTS CTS DTR DCD DSR Collision resolution Programmable bit inversion Transparent RD SD of data bytes without HDLC framing Protocol Support HDLC SDLC Types of protocol support Automatic Manual Transparent Handling of bit oriented functions in all modes Handling of and S frames in Auto mode Modulo 8 and 128 operation 64 byte FIFOs per direction Storage of up to 17 short received frames ee FASTCOM ESCC ISA BOARD LAYOUT DMA CHANNEL SELECT MODE 1 l MODE 2 y gt LEDs B CHANNEL 1 TR CHANNEL 2 70 SL aL tu DB37 c CONNECTOR e lt b LL IRQ LEVEL BASE ADDRESS TERMINATION REFERENCE CHANNEL 1 CHANNEL 2 SIGNAL REF SIGNAL REF RD R12 RD R18 CTS R13 CTS R19 ST R14 ST R20 DCD R15 DCD R21 RT R11 RT R17 LED INDICATORS PACKING LIST
19. sent to the ICD2053B part you will need to obtain the bitcalc3 program from Cypress It can be found on the web at http www cypress com cypress tech_sup web_tech sw clocks html After you have downloaded and installed it select Devices gt programmable products 2ICD2053B PCLKOUT from the menu Type in 18 432 MHz for the reference frequency for the ESCC ISA and ESCC PCI for the HSCX type in 16 000 MHz Enter the desired frequency keeping in mind all of the restrictions noted above and press the calculate button Write down the Hex programming word stuffed and count the number of bits in the binary word These are the parameters that need to be passed to the IOCTL ESCCDRV SET CLOCK function to program the ICD2053B to get the desired frequency output An important fact about the clock generator There is only one ICD2053B part and only 1 OSC input to the 82532 chip The clock generator can be programmed from either channel ESCCO or ESCC1 but it programs the same part The result is that while the baud rate generators are unique on a per channel basis the OSC input is not i e the baud rate generators are independent but the clock that feeds them is the same If you change the clock generator output you will change the input clock to both channels The practical thing to note about this is that if you have multiple baud rates that must be generated on multiple channels you should select the input clock ICD 2053B output such that all
20. 0 10000010 00000010 01111100 00111100 11011100 01011100 10011100 00011100 37 38 Hex De cimal Hex De cimal APPENDIX B SIEMENS 82532 TECHNICAL DATA
21. 0 1234567890 123456789012345678901234 56789012345678901234567890 12345678901 2345678901 234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890123456789012345678901234 56789012345678901234567890 1234567890 1234567890 1234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 12345678901 23456789012345678901234 56789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890
22. 123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 Read returned 3001 bytes Valid CRC OK check status STATUS DECODE Receive Frame Start Transmit Done read frame should get 2001 bytes The I O operation is pending WAIT OBJECT 0 post GET OVERLAPPED RESULT 012345678901234567890123456789012345
23. 2345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567896 Read returned 4001 bytes Valid CRC OK check status STATUS DECODE Receive Frame Start All Sent read frame should get 3001 bytes The I O operation is pending Read Timeout WAIT_OBJECT_0 post GET_OVERLAPPED_RESULT 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890 12345678901 2345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 123456789
24. 34567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890 12345678901 2345678901 2345678901 23456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890 12345678901 2345678901 2345678901 234567890123456789012345678901234567890123456789012345678901234567896 Read returned 2001 bytes Valid CRC OK check status STATUS DECODE All Sent Transmit Done Press a key to send again esc to exit exiting prog This program assumes the factory default switch settings address 0x280 IRQ 5 If you do not have those resources available you must recompile the example with the address and IRQ to match your board settings Troubleshooting tips 1 Incorrect loopback faulty wiring 2 IRQ conflict with other hardware 3 Address conflict with other hardware 16 SWITCH DESCRIPTIONS There are six dip switches on the FASTCOM ESCC ISA labeled SW1 SW2 SW3 SW4 SW5 and SW6 See Board Layout Illustration for location Switch 1 labeled ADDRESS is used to set the I O address of the FASTCOM ESCC ISA board Switches 2 and 3 labeled IRQ SELECT serve two functions they select the IRQ level for the board and are used to enable disable interrupt sharing Switch 4 DMA CHA
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26. 67890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 15 56789012345678901234567890 1234567890 1234567890 1234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 12345678901 23456789012345678901234 56789012345678901234567890 1234567890 1234567890 1234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 12345678901 23456789012345678901234 56789012345678901234567890 1234567890 1234567890 12345678901234567890123456789012345678901234567890123456789012
27. 890 1234567890123456789012345678901234567890123456789012345678901234567890123456789 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890123456789012345678901234 56789012345678901234567890 1234567890 1234567890 1234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890 1234567890 1234567890 1234567890 123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 56789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789 01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234 567890123
28. A Se Channel 2 TX DMA Se Channel 2 TX DMA Se ect ect ect ect ect ect ect The DMA Select switch sets the DMA receive and transmit channels Do not set the transmit and receive channels to be the same It is not possible to set the transmit and receive channels to be the same DMA channel If the same DMA channel is selected for more than one function TX RX Channel 1 Channel 2 that DMA channel will be disabled DMA Channel 1 3 5 T Transmit 1 Position 5 On On Off Off Position 6 On Off On Off Receive Position 7 On On Off Off Position 8 On Off On Off Transmit 2 Position 1 On On Off Off Position 2 On Off On Off Position 3 On On Off Off Boston On Off On Off SWITCH 5 MODE 1 SWITCH TXCLK input Channel 2 TXCLK output Channel 2 TXCLK input Channel 1 TXCLK output Channel 1 DMA Enable Channel 2 DMA Enable Channel 1 485 Driver Control Channel 2 485 Driver Control Channel 1 disabled 19 esc The Mode 1 switch serves three functions it selects either RS 422 or RS 485 driver mode enables or disables DMA and selects the direction of the transmit clock input or output The 485 driver control switch es control the transmitter enable for the SD signals In the on position the RTS output controls the enable RS 485 mode in the off position the SD driver is always
29. ET DSR not SET waiting for a key read thread started status thread started the first DSR not SET could be a DSR SET if you have a DTR gt DSR loopback wired 5 Press the letter on the keyboard You should see WRITEFILE esccadrv 1024 3 12 returned TRUE waiting for a key STATUS Receive Frame Start STATUS All Sent received 1025 bytes aaaaaaaaaaaaa 12 complete lines and one partial line of a s 1024 of them The last character is not Press esc to exit the program You can test channel 1 in a similar manner by running D fastcom_disks escc nt escctest escctest 1 h Make sure that you move your loopback to cable 2 before running the test on channel 2 You can test other operating modes by changing the last letter async test D fastcom_disks escc nt escctest escctest 0 a HDLC test D fastcom_disks escc nt escctest escctest 0 h Bisync test D fastcom_disks escc nt escctest escctest 0 b In async you will get a STATUS Receive Timeout after the All sent message and possibly at the beginning before you press a key The bisync test will geta STATUS SYN detected instead of a receive frame start message The async test should receive 1024 bytes displayed as 12 8 lines of the key you pressed The HDLC test should receive 1025 bytes displayed as 12 8 lines of the key you pressed The bisync test should receive 1025 bytes di
30. FASTCOM ADAPTERS FASTCOM ESCC ISA High Speed Dual Channel Sync Async Interface Hardware Reference M anual U ILL LL iip CONNVTBCH bam m uri Manufactured by CERTIFIED CONWVTECH C 9011 E 37th St Wichita KS 67226 2006 ONWVIECH 9011 E 37TH STREET N WICHITA KANSAS 67226 2006 316 636 1131 FAX 316 636 1163 http www commtech fastcom com COPVRIGHT C 1999 2002 2003 All rights reserved including those to reproduce this document or parts thereof in any form without permission in writing from Commtech Inc FASTCOM and SMART 14 are trademarks of Commtech Inc IBM is a registered trademark of International Business Machines Corporation Microsoft is a registered trademark of Microsoft Corporation WINDOWS is a trademark of Microsoft Corporation REVISION NOTES REVISION PAGE NUMBER CHANGES MADE 2 1 31 Changed warranty to 2 years 2 2 31 Updated contact information 2 3 31 Changed warranty period to lifetime 2 4 24 Fixed BDF error CONTENTS PE LERTII ET c 1 INTRODUCTION Description Block Diagram cissie 3 Specifications Features ERR tata 4 ierti i Eer E E 5 6 DB25 Connector Pin Description retten Dotnet 7 INSTALLATION Installation 0 0 0 0 60
31. FASTCOM ESCC ISA you will SIGNALS need to build a loop back plug Materials needed are a DB25 female 1 receptacle solder cup style and a few short pieces of 20 or 24 AWG 2 2 SD stranded wire Jumper the pins together on the DB25 as illustrated 3 x A 4 NOTE You can also create a loop back condition on the FASTCOM 5 7 GND ESCC ISA without building an adapter plug by setting the Mode 2 6 9 RT Switch SW6 as follows 7 i t MODE 2 E 14 SD 10 16 RD 11 17 RT 12 20 13 24 Both ESCC channels are looped back However we recommend that you make the loop back plug for two reasons one the clock circuit can be tested and two you will not have to change switch settings from the factory defaults In addition our technical support engineers can better service your technical questions if you have made the loop back plug If you have made the loop back plug do not change the setting of the Mode switch FASTCOM ESCC ISA WINDOWS NT 2000 TEST 1 Make sure that the driver was installed with DMAT DMAR 0 as the test program was compiled to run in interrupt mode 2 Attach a loopback plug to the cable 1 ESCCO port 0 3 From the Start button menu select Run Enter D fastcom_disks escc nt escctest escctest 0 h Click the OK button 4 You should see Created esccdrv ESCCO ESCC 82532 version status 82 receive buffers ready 0 resetting HDLC settings SETTINGS SUCCESSFUL 168 DTR SET DSR not SET DTR not S
32. HNICAL SUPPORT All products manufactured by Commtech are warranted against defective materials and workmanship for the lifetime of the product This warranty is available only to the original purchaser Any product found to be defective will at the option of Commtech be repaired or replaced with no charge for labor or parts not excluded by the warranty This warranty does not apply to any products that have been subjected to misuse abuse or accident or as a result of service or modification by anyone other than Commtech In no case shall Commtech liability exceed the original product purchase price If any Commtech product is damaged such that it cannot be repaired you can return it to Commtech for replacement under our Non Repairable Replacement policy regardless of the cause of damage Commtech will replace the unit at 60 of the then current list price Commtech provides extensive technical support and application suggestions Most of the problems that occur with the FASTCOM ESCC ISA can be corrected by double checking the switch positions your cables and your program We recommend that you build the loop back plug that is described in the Programming section of this manual With that plug you can quickly isolate the problem to the board cables or software If you still have unresolved questions use the following procedure to get technical support 1 Call our Technical Support Staff at 316 636 1131 They are on duty from 9 00 AM to 5
33. MIT CLOCK OUT B TT DA 17 RECEIVE CLOCK IN A RT DD 9 RECEIVE CLOCK IN B RT DD 15 TRANSMIT CLOCK IN A ST DB 12 TRANSMIT CLOCK IN B ST DB These are opposite of RS 422 in order to invert the signals going to the FASTCOM ESCC ISA The 530 specification states that data is valid on the rising edge of the clock 0 gt 1 transition whereas the FASTCOM ESCC ISA clocks on the falling edge 1 gt 0 transition DCD is inverted because 1 at DCD means active to the FASTCOM ESCC ISA but the 530 specification requires a at DCD to be active On the same note if you are using Clock Mode 1 and you are not using DCD it must be strapped Active to allow data reception NOTE The DTR and DSR signals are single ended unbalanced as required by ANSI EIA TIA 530 specifications c CUN INSTALLATION Important Observe Electrostatic Discharge ESD precautions when handling the FCESCC board Unpack the FCESCC Keep the box and static bag for warranty repair returns 2 Check the switches to be sure that they are set as illustrated below Factory Switch Settings 3 Select an open slot in your PC 16 bit slot 4 After removing the blank bracket from your PC install the FCESCC in the PC by pressing it firmly into the slot Install the bracket screw to hold it firmly in place 5 Re install the cover on your PC FACTORY SWITCH SETTINGS ADDRESS SELECT SW1 280H IRQ SELECT SW2 amp SW3
34. NNEL SELECT selects the DMA channels to be used by each ESCC port Switch 5 MODE 1 CONFIG selects either RS 422 or RS 485 mode enables DMA and determines the direction of the TXCLK signal if the transmit clock is received or transmitted Switch 6 MODE 2 CONFIG controls the loopback function for RS 485 and the CTS disable feature SWITCH 1 ADDRESS Switch 1 decodes the PC address lines as follows Address lines A6 through A13 are decoded by the setting of SW1 and set the base address of the FASTCOM ESCC ISA Address lines AO A5 are used on the board to select configuration and control registers on the 82532 chip Address Line Hex value A13 2000 The above diagram illustrates a base address of 280 Hex factory A12 1000 default Note that when a switch is ON it represents a O in the 11 800 corresponding bit position not 1 as you might expect Also a 10 400 switch that is OFF represents 1 in the corresponding bit A9 200 position If you would like to know why this is reversed read the A8 100 technical data for the address decoder chip 7415682 A7 80 A6 40 So the SW1 diagram can be decoded as follows A13 A12 A11 A10 A9 A8 AT A6 0 0 0 0 1 0 1 0 You can determine the I O address of the board by adding the Hex values for each address line that is set to a 1 In the illustration only address lines A9 and A7 are set to 1 So add the Hex value of A9 200H and A7 80H and the result is the I
35. O base address 200H 80H 280H We have provided a comprehensive guide to setting the address switch in Appendix A Please note that not all of the I O address space in a PC is available for your use We have selected 280H as a default because it does not conflict with devices normally installed in a PC However if you wish to select another address refer to Appendix A I O Address Usage Table and select an address that does not conflict with devices installed in your PC Keep in mind that the FASTCOM ESCC ISA requires 33 contiguous bytes of address space If you want to install more than one FASTCOM ESCC ISA board in your computer be sure to set each to a unique I O address We recommend the following addresses for a multi board system FASTCOM ESCC ISA BOARD 1 280H FASTCOM ESCC ISA BOARD 2 2C0H FASTCOM ESCC ISA BOARD 3 300H Remember that a single IRQ level can be shared between multiple FASTCOM ESCC ISA boards in a PC and that DMA channels cannot be shared LL 17 SWITCHES 2 AND 3 INTERRUPTS Switches 2 and 3 serve two functions they select the IRQ level for the FASTCOM ESCC ISA and enable disable interrupt sharing The following illustrates the IRQ select switch on the FASTCOM ESCC ISA IRQ SELECT ON ON 123 4 1 2 3 4 5 6 7 8 IRQ LEVELS IRQ LEVELS BOARD BOARD 1 SHARE Select only 1 IRQ level at a tim
36. OMA UNUSED 8 contiguous bytes COM2 UNUSED 32 contiguous bvtes DISK CONTROLLER UNUSED 48 contiguous bytes NETWORK CARD UNUSED 8 contiguous bytes PARALLEL PORT PRIMARY UNUSED 16 contiguous bytes CLUSTER UNUSED 28 contiguous bytes MONOCHROME DISPLAY PARALLEL PORT TERTIARY EGA CGA UNUSED 8 contiguous bytes COM3 DISKETTE CONTROLLER COM1 35 FCESCC ADDRESS SWITCH SETTINGS ADDRESS Hex Decimal Oh 0 40 80h 128 coh 192 1000 256 140h 3200000 1800 384 2008 512 2405 576 280h 640 3000 768 3400 832 380h 896 3e0h 9600 4008 1024 4405 1088 4805 1152 4o0h 1216 5006 1280 540h 1344 580h 1408 i Sc0h 1472 600 1536 640h 1600 680n 1664 7000 1792 T40h 1856 780h 19200 1984 SWITCH 1 POSITION 12345678 1 ON 0 Hex Decimal OFF 123 45 6 7 8 i 800h 2048 8406 2112 8806 2176 8cOh 2240 9006 2304 940n 2368 980n 2432 9c0h 2496 a00h 2560 adh 2624 2688 2752 2816 b40h 2880 b80h 2944 3008 c00h 3072
37. chnical support if you need to modify the resistor You may also order the FASTCOM ESCC ISA without the termination resistor installed it is easier to add the resistor than to remove it Observe the resistors in the following drawings and remember that they are built into the FASTCOM ESCC ISA Typical RS 422 DRIVERS RX TX R2 sRX TX R1 TX RECEIVERS R1 amp R2 Line Termination 100 Ohms Typical RS 485 23 PROGRAMMABLE CLOCK GENERATOR Cypress ICD2053B The FASTCOM ESCC ISA features the ICD2053B Programmable Clock Generator which offers a fully user programmable phase locked loop in a single 8 pin package The output may be changed on the fly to any desired frequency value between 391 kHz and 90 MHz the FASTCOM ESCC ISA maximum is 33 MHz The ability to dynamically change the output frequency adds a whole new degree of freedom for the designer Programming the ICD2053B is simple requiring only a bitcalc program This program is provided on the Fastcom CD The data sheet for the ICD2053B also explains the operation of this program Open data sheet FEATURES e Clock outputs ranging from 391 kHz to 90 MHz the FASTCOM ESCC ISA maximum is 33 MHz e Phase Locked Loop oscillator input derived from external reference clock 18 432 MHz on the FASTCOM ESCC ISA e Three State output control disables output for test purposes Sophisticated internal
38. d you go about it Start with the fastest bit rate and determine if there is an external clock that is received with that data or if the clock must be recovered DPLL mode Let s say that you want to recover the clock from the data there are no clock lines in the system and that the data is Manchester encoded To get a 2 Mbps clock rate using a DPLL we will need to use the bitrate input clock 1 16 function This will require a 32 MHz input clock To get this input clock using bitcalc as before clkbits 0 500 60 numbits 23 using the following register settings MODE 0x88 CCRO 0x98 CCR1 0x16 CCR2 0x18 CCR3 0x00 CCR4 0x00 The receive source will be recovered from the data stream The transmit source will be the BGR 16 output Now for the async channel We are locked into the 32 MHz input clock so we will try to find a value for N that gets our desired 38400 bps 38400 32E6 16 N 1 2 N 25 04 we cannot attain non integer values for N If we use N 25 we would get bitrate 32E6 16 25 1 2 38462 bps If we use N 26 we would get bitrate 32E6 16 26 1 2 37037 bps Using the closest value and setting the registers to MODE 0x08 CCRO 0xC3 CCR1 Ox1F CCR2 0x38 CCR3 0x00 CCR4 0x80 and BGR 0x19 will yield an asynchronous data format with 16X oversampling at about 38400 bps If later you decide that you need to get 115200 bps on the async channel you will find
39. e SWITCH PC AT 386 SWITCH PC AT 386 POSITION IRQ Assigned POSITION IRQ Assigned SW3 2 9 UNUSED SW2 1 10 UNUSED 3 3 COM2 2 11 UNUSED 4 4 COM1 3 12 UNUSED 5 5 UNUSED 4 15 UNUSED LPT2 6 6 FLOPPY 7 7 LPT1 You can use any IRQ that is not assigned to a device installed in your PC INTERRUPT SHARING An important feature of the FASTCOM ESCC ISA is its ability to share one IRQ level with several FASTCOM ESCC ISA boards in the same computer This is important because there are very few unassigned IRQs in the PC Switch 3 positions 1 and 8 control the interrupt sharing circuit on the FASTCOM ESCC ISA Position 1 Enables interrupt sharing in the OFF position and Disables sharing in the ON position Position 8 is called the Board 1 switch In the interrupt sharing mode this switch must be ON for the first FASTCOM ESCC ISA board in your system and OFF on all other FASTCOM ESCC ISA boards Switch 3 Position1 8 ON OFF Disables IRQ sharing OFF ON Enables IRQ sharing first board OFF OFF Enables IRQ sharing second board For example let s assume that you have two FASTCOM ESCC ISA boards in your PC and want to share IRQ 5 Set Switch 3 as follows for the first board Any additional FASTCOM ESCC ISA boards that share IRQ5 would be set the same as the second board SWITCH 4 DMA CHANNEL SELECT Channel 1 RX D Channel 1 RX D Channel 2 RX D Channel 2 RX D MA Se MA Se Channel 1 TX DMA Se Channel 1 TX DMA Se MA Se M
40. ery DPLL 2 If BGR is used is the BDF bit 1 or 0 2 The setting of the clock generator ICD2053B that feeds the OSC input to the 82532 only a factor if an internal clock mode is used i e BGR or DPLL is involved 3 The physical switch settings of the Fastcom ESCC ISA A The switch determines the routing of the TXCLK pin as either an input or output B The switch also determines if the OSC is fed the output of the clock generator or just the output of the onboard clock an option on the ESCC PCI and the HSCX the ESCC ISA does not have this option 4 The revision of the ESCC 82532 chip silicon A Therev 3 2 silicon incorporates an enhanced baud rate mode We will start with the simplest case If you are using the Asynchronous data mode then the most likely clock mode that you should use is 7b It is possible to use the other clock modes however mode 7b is the most straightforward to work with The bitrate will be determined by the output of the baud rate generator The baud rate generator is clocked by the OSC input which is set by the ICD2053B clock generator So you have If you are not using oversampling BCR 0 the formula is bitrate input clock BGR If you are using oversampling BCR 1 the normal case for async the formula is bitrate input clock BGR 16 If BDF 0 then BGR 1 If BDF 1 then BGR N 1 2 If BDF 1 and EBRG 1 then BGR n 1 2 The BCR bit is in CCR1 bit 3 The BDF bit is
41. in CCR2 bit 5 The EGRG bit is in CCR4 bit 6 CCR2 amp 0xC0 2 BGR or if you prefer Most significant Least significant bit n BGR bit 5 BGR bit 4 BGR bit 3 BGR bit 2 BGR bit 1 BGR bit 0 m CCR2 8 CCR2 7 BGR 7 BGR 6 N CCR2 8 CCR2 7 BGR 7 BGR 6 BGR 5 BGR 4 BGR BGR 2 BGR 1 BGR 0 Some things to keep in mind The range on the ICD2053B output is 391kHz to 90MHz The usable range if the master clock enable bit is clear not using master clock is 391kHz to 33Mhz If the master clock is set then the range is from 391kHz to 10MHz Using master clock mode also places a restriction on the ratio of receive transmit clock to the master clock frequency as per note 2 on page 84 of the 82532 data sheet 25 Fmaster Ftransmit gt 2 5 Freceive Fmaster lt 3 or 1 5 if CCR3 bit 4 RADD is set and an address recognition mode is used in HDLC To use Master clock mode or not to use Master clock mode that is the question The 82532 operating in standard non master clock mode uses the transmit clock source refer to table 5 page 84 of the data sheet to run the internal timing of the chip If your transmit clock source is running very slow or it is not running continuously if external clock is supplied then it is a good idea to switch to master clock mode Each command issued to the 82532 any write to the CMDR register can take up to 2 5 clocks to complete If the clock is very slow or sto
42. ing sequence Press Stop Esccdrv button Press Add Board Remove Board as necessary Press Start Esccdrv button Press OK Exit If you do not have any boards channels installed and press the start button you must manually delete the esccdrv sys and the esccdrv subkey before rebooting or any attempt to stop the driver could cause Windows to go into its bug check mode Blue Screen Of Death The NTINSTALL EXE program does not do any checking on the values that you enter If you enter unreasonable values for address irq dma there is a very good chance that Windows will become unstable bug check mode The driver only looks at the registry information on startup If you add boards while the driver is running the new devices will not exist until the system is restarted or you stop and restart the driver For example if you Press Install Driver Press Add Board enter channel 0 info Press Add Board enter channel 1 info Press Start Esccdrv Press Add Board enter channel 0 info Press Add Board enter channel 1 info Run example program esccmfc the only devices that would be available would be ESCCO and ESCC1 If you try to open ESCC2 or ESCC3 you will get a can t get a handle message To use ESCC2 or ESCC3 you must press the STOP ESCCDRV button then press the START ESCCDRV button or reboot to allow the driver to recognize the additional board 11 p TESTING THE INSTALLATION To fully test the installation of your
43. loop filter requires no external components or manufacturing tweaks as commonly required with external filters Low power consumption makes device ideal for power and space critical applications Programmable using the FASTCOM ESCC ISA PVR register bits 1 and 2 5V operation High speed CMOS technology PROGRAMMING NOTE Revision 3 2A of the Siemens 82532 utilizes both standard and enhanced modes of the Baud Rate Generator Register BGR In standard mode the following formula is used to calculate the divisor for baud rate generation N 1 2 The following hexadecimal values of N are equivalent to N equaling zero 0x000 0x100 0x200 0x300 0x040 0x140 0x240 0x340 0x080 0x180 0x280 0x380 OxOCO 0x1C0 0 2 0 0x3C0 This is a known bug of the 82532 24 DETERMINING AND SELECTING BAUD RATES Selecting the bit rate can either be very easy or quite complicated depending on a number of factors The best place to start is to determine the big picture broad perspective and narrow down the options using the various constraints that the hardware imposes There are four basic things that make up what the actual bitrate will be They are 1 Register settings of the 82532 chip These include A Operating mode HDLC Bisync Async 1 If async is used is it truly async oversampled BCR 1 or 2 isosynchronous async format with no oversampling B Clock mode internal or external clocks 1 If internal clocks does it use clock recov
44. ng up normal industrial electrical noises such as fluorescent lights motors transformers and other EMF sources Third RS 232 data rates are functionally limited to 19 2K Baud On the other hand the newer RS 422 standard makes cable lengths up to 5000 feet possible and is highly immune to most industrial noises Data rates are also improved the FASTCOM ESCC ISA features data rates up to 10 Mega Baud These improvements were made possible by differentially driving and receiving the data as opposed to the single ended method employed by the RS 232 standard With the RS 422 standard the transmit signal TX in RS 232 is a differential signal consisting of SD and SD the receive signal RX in RS 232 consists of RD and RD Another draw back of RS 232 is that more than two devices cannot share a single cable This is also true of RS 422 and that s why the RS 485 standard was developed RS 485 offers all of the benefits of RS 422 and also allows multiple units up to 32 to share the same twisted pair RS 485 is often referred to as a multi drop or two wire half duplex network because the drivers transmitters and receivers share the same two lines In fact up to 32 stations can share the same twisted pair In order for an RS 485 system to work only one driver transmitter can occupy the network at a time This means that each station on the network must control the enabling disabling of their drivers in order to avoid network conflicts If
45. ny COMM TECH IN C declares under its own and full responsibility that the product Fastcom ESCC ISA Revision 1 4 on which is attached this Certificate is compliant to the 89 336 EEC Directive amended by 92 31 EEC and 93 88 EEC The product identified above complies with the requirements of the above EU Directive by meeting the following standards EN 50081 1 1992 EMC Generic Emission Standard Part 1 Residential Commercial and Light Industry EN 55022 1995 CISPR 22 1993 Limits and Methods of Measurement of Radio Disturbance Characteristics of Information Technology Equipment 30 MHz 1 GHz Class B Limits EN 50082 1 1992 EMC Generic Immunity Standard Part 1 Residential Commercial and Light Industry IEC 801 2 1984 M ethod of Evaluating Susceptibility to Electrostatic Discharge Level 4 IEC 801 3 1984 Radiated Electromagnetic field Requirements Level 3 IEC 801 4 1988 Electrical Fast Transient Burst Requirements Level 2 Products listed on this declaration are exempt from the requirements of the 73 23 EEC directive due to the input voltage specification as stated in Article 1 of the directive The technical documentation required to demonstrate that this product meets the requirements of the EMC Directive has been compiled by the signatory below and is available for inspection by the relevant enforcement authorities In WICHITA KS on December 3lst of 1995 p L 2 CONWVIE Mr Glen R Alvis
46. ould operate in interrupt only mode You can manually add delete these registry entries if you wish But earlier version s of the driver will crash if you do not define any boards and start stop start the driver You can manually add a value in the esccdrv parameters ESCCx subkey Buffers REG_DWORD OxYY This controls the number of receive buffers frames that the driver will allocate and use The default value is 10 and can be any value from 2 to 100 10 REMOVE BOARD Pressing this button will delete the subkey and its values for the selected board channel START Pressing this button will load the driver It is equivalent to using Control Panel gt Devices gt Start with the esccdrv selected STOP Pressing this button will stop unload the driver It is equivalent to using Control Panel gt Devices gt Stop with the esccdrv selected REMOVE DRIVER Pressing this button will attempt to stop the driver if it is started and will delete the esccdrv subkey and all of its subkevs It will not delete the esccdrv sys file from your winnt system32 drivers directory If you want to completely remove the driver you must delete this file manually The intended sequence of events is Press Install Driver button Press Add Board button 2 times per board installed Fill in address irq dma information Press Start Esccdrv button Press OK Exit If you want to change add a board later you would need to follow the follow
47. ps from time to time this can be a significant amount of time and allows for the possibility of a command being lost written but not executed because a previous command is not complete If your baud rate is slow 1MHz or you are using a gated external clock you should use master clock mode to allow the PC interface to the 82532 to continue to execute quickly If this mode is used then the OSC input must be less than 10MHz the speed rating of the internals of the 82532 If you have a 82532 rev 3 x silicon then you can cause the master clock to be OSC 4 by setting bit 7 MCK4 thus allowing the 10MHz restriction to be lifted If you are using a clock mode that uses external clocks you should respect the restriction on the ratio of receive to transmit clock frequency given in note 2 of table 5 Freceive Ftransmit lt 3 or 1 5 If you are running in not extended baud rate mode do not set BGR bits 5 0 to all 0 or the chip will assume that all of the BGR bits are 0 This is a glitch in the 82532 rev 3 2 and makes the following values for N identical 0 000 0 040 0 080 0 0 0 0x100 0x140 0x180 0x1C0 0 200 0 240 0 280 0 2 0 0 300 0 340 0 380 0 3 0 Setting the baud rate generator to any of these values will produce the same affect as setting it to 0 000 If you use the Enhanced baud rate generator and set m 0 the clock output will be asymmetric non 50 50 duty cycle To determine the parameters that need to be
48. splayed as 12 8 lines of the key you pressed The exceptions to this are the keys t r i p and h pressing t will reset the transmitter and flush the transmit queue pressing r will reset the receiver and flush the receive queue pressing i will start the timer which will eventually result in a STATUS Timer expired message It takes about a minute in HDLC mode for the timer to timeout pressing p will stop the timer which will prevent the STATUS Timer expired message pressing h will issue a hunt command in bisync mode TEST 2 1 Press the Start Button select the Run command Enter D fastcom_disks escc nt esccmfc esccmfc Click OK 2 From the main menu select Options gt Port Enter 0 click OK this selects port 0 make sure you have your loopback on cable 1 3 From the main menu select Options Settings the settings dialog will open Click OK the TXD status indicator on the screen should turn green 4 Type a short message on the keyboard press enter to send it The message you typed should appear in the lower window and the RXD RFS and ALLS status indicators should turn green if it was a short message 32 bytes or so a long message will likely only get a RXD status indicator If when running any of these tests you do not get the expected result check your switch settings and the driver 757 mTaooaoaomummmeme ia 13 install settings to make sure that they match If it still doesn t work tr
49. t Devices gt Startup button after the driver is installed The Type parameter is kernel mode ADD BOARD Pressing this button will add the information to the registry about where a particular ESCC channel is located It will create a subkey under the esccdrv parameters such as esccdrv parameters ESCCO The dialog that appears when you press ADD BOARD needs to have the Base Address Interrupt and DMA information for the card you are installing For example if you use the factory defaults do not change any of the switch settings you would press the ADD BOARD button two times The first time you would enter Base 0x280 IRQ 5 DMAR 0 DMAT 0 Channel 0 The second time you would enter Base 0x280 IRQ 5 DMAR 0 0 Channel 1 This will create two subkeys esccdrv parameters ESCCO and esccdrv Parameters ESCC1 The value that you enter for Base should match setting of the base address switch on the board The value that you enter for IRQ should match the setting of the IRQ LEVEL switch on the board The value s that you enter for DMAR and DMAT will determine if the driver uses DMA or not If they are both zero then DMA is not used interrupt only mode If they are both nonzero and not equal i e DMAR DMAT 0 then DMA mode is used The example program is compiled assuming that DMA is not used i e DMAR DMAT 0 Specifically the DMA bit in the XBCH register of the 82532 is clear indicating that the 82532 sh
50. two drivers engage the network at the same time data from both will be corrupted In RS 485 mode the receivers are always enabled For a more detailed description of RS 422 and RS 485 we recommend the following references LINEAR AND INTERFACE CIRCUITS APPLICATIONS Volume 2 Line Circuits Display Drivers By D E Pippenger and E J Tobaben Published 1985 by Texas Instruments ISBN 0 89512 185 9 Note This book may be difficult to find in a bookstore The best place to get it is directly from Texas Instruments or from one their component dealers Publication SLYAOO2 Driver Receiver Family Extends Data Link Performance ELECTRONIC PRODUCTS January 15 1985 By Dale Pippenger and Joe Miller 22 TERMINATION RESISTANCE In both the RS 422 and the RS 485 mode the receiver end of the cable between two stations must be terminated with a resistor equal to the characteristic impedance of the wire This is to prevent signal reflections in the wire and to improve noise rejection However you do not need to add a terminator resistor to your cables when you use the FASTCOM ESCC ISA The termination resistance is built in We have installed a terminator resistor for each receiver between each RD and RD and between CTS and CTS for each channel If you are using the FASTCOM ESCC ISA in a multi drop network the termination resistor should be removed from all units except the first and last see the RS 485 illustration below Call for te
51. y a different address irq combination to remove a possible address or irq conflict Troubleshooting tips 1 Incorrect loopback faulty wiring 2 Interrupt conflict 3 Address conflict FASTCOM ESCC ISA WINDOWS 9x TEST Install loopback on cable 1 ESCCO portO From the Start button menu select Run Enter D fastcom_disks escc w9x escctest Click OK 4 The display should be gt obtained handle to esccdrv try to add port port added ports active 2 Set ICD2053b ICD2053B set to 16MHz starting settings INIT OK Getting VSTR VSTR contents 82 WRITE REG CMDR gt XRES Write Reg successful check status STATUS DECODE Transmit Done flushing rx RX flushed flushing tx TX flushed read frame The I O operation is pending write frame 1 Write successful WAIT_OBJECT_0 post GET OVERLAPPED RESULT 01234567890123456789012346 Read returned 26 bytes Valid CRC OK write frame 1 Write 1successful write frame 2 Write 2 successful write frame 3 should pend no more tbufs The I O operation is pending write frame 4 should fail bufs full Tx buffers full try again later read frame should get 4001 bytes The I O operation is pending Read Timeout 14 post GET_OVERLAPPED_RESULT 012345678901234567890123456789012345678901234567890123456789012345678901234567890 1234567890 12345678901 23456789012345678901234 56789012345678901234567890 1234567890 1234567

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