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DE2 Development and Education Board User Manual

1. Tu 78 81 2 Terasic DE4 User Manual www ra asic com www terasic com Eee 82 S T TEMPERATURE MONITOR ces sta RE Um DIS 83 Oy 44 95 86 MM SU drm 87 88 CHAPTER 4 DE4 SYSTEM BUILDER 5 ese vac veo 90 AE LINTRODUCTION 90 a GBENBEALIDBSION 9 4 3 USING DE4 SYSTEM BUILDER oer tet v FERRE Rene ZR o rar rest s a v bsp d OR a nf bw ed UR 92 5 EXAMPLES OF ADVANCED DEMONSTRA TION cccccccccccccccccccccccccsscccccccccccscccccccccccccscccccces 103 103 U M 111 5 3 ETHERNET SIMPLE SOCKET SERVER ccccsccscceccecccc
2. 19 2 yS TATUS EEFMENT O ACT cre 20 21 223 HIGH SPEED MEZZANINE CARDS EUa AED EDA 25 2 0 OPTIO 36 UD 40 A Serr 48 LE 51 22 UNIS TT P 56 2 I2 CHGABE B PHBRNET GIGB UM DM CRI MEI LL DE 59 62 Ie 64 M MOR MIR E DL EPIS 65 66 c 68 2 19 TEMPERATURE SENSORS eR REM ORDINES RM RA MERI UMS MM MR AMEN MM ree ere eee ee 68 t M U 69 CHAPTERS S COI TOOL TF ANE 71 SENE CONTROLFANEE UNI 71 5 2 CONTROLLING THE LEDS AND SEGMENT DISPLAYS 75
3. 172 ADDITIONAL INFORMA TON c c ecce eee eee ee eee e etes es eee e esses esset eese esee sess eee eseseeeese sese sese 177 www terasic com Chapter 1 Overview This chapter provides an overview of the DE4 Development Board and details the components and features of the board 1 1 General Description The DEA Development Board provides the ideal hardware platform for system designs that demand high performance serial connectivity and advanced memory interfacing Developed specifically to address the rapidly evolving requirements in many end markets for greater bandwidth improved jitter performance and lower power consumption The DE4 is powered by the Stratix IV device and supported by industry standard peripherals connectors and interfaces that offer a rich set of features that 1s suitable for a wide range of compute intensive applications The advantages of the 5 IV GX FPGA platform with integrated transceivers have allowed the DE4 to fully compliant with version 2 0 of the PCI Express standard This will accelerate mainstream development of PCI Express based applications enabling customers to deploy designs for a broad range of high speed connectivity applications The DEA coupled with serial ATA SATA interfaces offer a solution for developing storage applications The DEA delivers fully tested and supported connec
4. Default Setting Defautt Setting Load Setting Save Setting Load Setting Load Setting Save Setting Save Setting Generate amm et Figure 4 10 Project Settings B Project Generation When users press the Generate button the DEA System Builder will generate the corresponding Quartus II files and documents as listed in the Table 4 1 in the directory specified by the user Table 4 1 The files generated by DEA System Builder No Filename Description 1 Projecname v level verilog file for Quartus ll 2 EXT External PLL configuration controller IP lt Project Quartus II Project File Project name gt qsf Quartus II Setting File Project name gt sdc Synopsis Design Constraints file for Quartus Il Project name gt htm Pin Assignment Document 101 www terasic com Terasic DE4 User Manual www terasic com Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof In addition External Programmable PLL Configuration Controller IP will be instantiated in the Quartus II top level file as listed below ext pll ctrl ext pll Inst 05 50 OSC 50 2 SOMHZ Istn rstn device 1 REFCLK clk1 set wr clkl set wr clk1 set rd device 2 HSMB REFCLK 2 set wr clk2 set wr
5. so cs gt MS ues m 4 r em 1000 UNIVERSITY d 19 gt i 4 mr 199 H 3 L zi Aerie eS lem Figure 5 41 HSMC port A loopback design setup 152 Terasic DE4 User Manual www terasic com NNN HSMC Port B Loopback Test B Demonstration Source Code Quartus Project directory DE4 HSMB LOOPBACK TEST FPGA Bit Stream DE4 HSMB LOOPBACK TEST sof B Demonstration Setup Check that Quartus II and NIOS II are installed on your Power on the DEA board e Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e Program the DEA using the 4 LOOPBACK TEST sof through Quaruts II programmer Press RESET pushbutton 0 of DE4 board to initiate the verify process e LED 7 0 will flash once to indicate the loopback test passed 153 Terasic DE4 User Manual www terasic com www Lterasic com Chapter 6 Express Reference Design PCI Express is commonly used in consumer server and industrial applications to link motherboard mounted peripherals From this demonstration it will show how the PC and FPGA communicate with each other through the PCI Express interface 6 1 PCI Express System Infrastructure The system consists of two primary components the FPGA hardware i
6. udin gt 4GB DDR2 SODIMM X36 Switch 8 PCle X8 4GB Slide Sw 4 Interface DDR2 SODIMM Button 4 LED 8 Figure 1 3 Block diagram of the DEA board Below is more detailed information regarding the blocks in Figure 1 3 8 Terasic DE4 User Manual www terasic com Stratix IV GX FPGA EPASGX230C2 O O O O 228 000 logic elements LEs 17 133K total memory Kbits 1 288 18x18 bit multipliers blocks 2 PCI Express hard IP blocks 744 user I Os 6 phase locked loops PLLs EPASGX530C2 O O O O Configuration device and USB Blaster circuit 531 200 logic elements LEs 27 376K total memory Kbits 1 024 18x18 bit multipliers blocks 4 PCI Express hard IP Blocks 744 user I Os 6 phase locked loops PLLs MAXII CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration On board USB Blaster for use with the Quartus II Programmer Programmable PLL timing chip configured via MAX II CPLD Support mode Memory devices 64MB Flash 32M x16 with a 16 bit data bus 2MB SSRAM x 16 2Kb EEPROM www terasic com Two DDR2 SO DIMM sockets Upto 8GB capacity in total Maximum memory clock rate at 4000M Hz e Theortical Bandwidth over 102Gbps SD Card socket e Provides SPI and 4 bit SD mode for SD Card access General user 1 e 8 user controllable LEDs e 2seven segment displays e 6 user DIP switche
7. ext ext pl set wr E us ah _ E ext ext set a o ext ext pil rd E ext ext set rd T amp E et ext set rd oh HBrextplcttu ext T ext ready Hame m H Pll etru ext ctrijconf wr RARRARRARRRRSRRRRSSAZESRZHREEREERSENEEAHEEAEAEHEARSARRAASAAEAASARERAERAERAERERSERRRRRRRSRRSRRERRERITHRTAERRRSXEXHERIRRIRRARARRERERARRRRG R RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRTRRISRRERERIERIRRARS H ext ext set wer ext ctriu ext ctrilclk2 set wer E ext set wer ext ext rd ext ext rd ext ext ctri cik2 set rd ext ext set rd a ext ext etrilcanf ready 999999999 Figure 5 27 Write timing waveform Read Timing Waveform As Button PB2 is pressed conf signal is on the rising edge the user settings are read back immediately once the conf ready signal is on the falling edge as shown in Figure 5 28 A
8. Host clack divisor Info automatically selected in 10710071 000 Mb Ethernet with 100 0g ss E XSGMI PCS core ve Figure 5 33 MAC Options Configuration From the PCS SGMII Options section enable SGMII bridge logic to add SGMII clock and rate adaptation logic to the PCS block as shown in Figure 5 34 143 Terasic DE4 User Manual www terasic com www terasic com 8 Triple Speed Ethernet mac Triple Speed Ethernet gout Documentation Parameter Settings Core Configuration MAC Options gt FIFO Options 5 PCS SGMII Options PCS SGMII PHY ID 32 bit 0500000000 Enable SGMII bridge Export transceiver povverdown signal Enable transceiver dynamic reconfiguration Info iz automatically selected in 00 000 Mb Ethernet MAC with core va J Figure 5 34 PCS SGMII Options Configuration Once the Triple Speed Ethernet IP configuration has been completed and the necessary hardware connections have been made click on Generate to build the interconnect logic automatically as shown in Figure 5 35 144 Terasic DE4 User Manual www terasic com www terasic com Alera DEA spe board ka mad nberincs Technoigem inc cc Orbite TERAS
9. B System Configuration Under System Configuration users are given the flexibility of enabling their choice of components on DE4 as shown in Figure 4 4 Each component of the DEA is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component 15 enabled the DE4 System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standards Note The pin assignments for some components for e g DDR2 and SATA require associated controller codes in the Quartus project otherwise Quartus will result in compilation errors Therefore do not select them 1f they are not necessary in your design To use the DDR2 controller please refer to the DDR2 SDRAM demonstration in Chapter 5 94 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 100 System Confiquration NU S RYAN asic 9 UNIVERSITY 54 Board Type DE4 230 PR www terasic com Project Name 4 CLOCK Slide Switch x 4 LED x 8 7 Segement x 2 Button x 4 DIP Switch x 8 Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM SSRAM 2MB Programmable PLL Programmable PLL Ethernet x 4 HSMA REFCLK O DDR SODIMM 1 O DDR SODIMM 2 HSMB REFCLK O Sata Host 0 O Sata Host 1 O Sata Devi
10. Figure 5 2 Software stack of the USB Host demonstration Each block encapsulates the specific implementation details of that block providing a data abstraction for the block above The following is a description of each block Nios II PIO The Nios PIO block provided by Nios II system that supports basic IO functions IORD and IOWR to access hardware directly The function prototypes are defined in the header file lt io h gt ISP 1761 HAL The ISP 1761 HAL block implements functions to access internal registers and memories of the USB chip ISP 1761 and high full low speed transfer functions for isochronous interrupt control and bulk transfers USB Host Controller The USB host controller block implements control functions for ISP1761 host controller USB Protocol The USB protocol block implements USB protocol including USB Hub protocol USB Mouse Class Driver The USB mouse class driver implements functions to communicate with HID USB mouse USB mass storage Class Driver The USB mass storage Class Driver implements functions to communicate with Bulk Only Transport USB mass storage based on USB Floppy Interface command set UFI is defined based on the SCSI 2 and SFF 80701 command set 105 4 User Manual www terasic com FAT File System The FAT file system block implements reading functions for FAT16 and FAT32 file system Long filename is supported in th
11. Source DM Controller Merry barged Sen Memony dispo Matter werde Quien Memory bange hacer m write n Streaming Sani memory On CFin Memory FAM or i 1 Memory higad Taree eS rw cea 0 clock bo lhe dala edis of ed pios 1 whe accede Tem PL e me 4 Figure 5 12 builder for Ethernet Simple Socket Server In the Triple Speed Ethernet IP Core configuration the interface 1s set to SGMII as well as using the internal FIFO shown in Figure 5 13 118 Terasic DE4 User Manual www terasic com www terasic com Triple 3peed Ethernet Triple Speed Ethernet meum Parameter Settings Core Configuration PCSISGMII Options Core variation 10 1007 000b Ethernet with 1 00 PCS 0050005 Ethernet Interface misc Use internal FIFO Humber of ports 1 rT 0 BASE XISGMII PCS Use transceiver block L vDS IO Info automatically selected in 104 004000 Mb Ethernet with 00 PCS core l
12. 3 3 HSMC power HSMC ports A and B 70 www terasic com Chapter 3 Control Panel The DEA board comes with a PC based Control Panel that allows users to access various components onboard The host computer communicates with the board via USB port The tool can be used to verify the functionality of components This chapter presents some basic functions of the Control Panel illustrates its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel software utility is located in the directory Tools DE4_ControlPanel in the System CD To execute the program simply copy the whole folder to your host computer and launch the control panel by double clicking the DE4_ControlPanel exe Note Please make sure Quartus II and USB Blaster Driver are installed before launching DEA Control Panel In addition before the DE4 control panel is launched it is imperative the fan is installed on the Stratix IV GX device to prevent excessive high temperature on the FPGA To activate the Control Panel perform the following steps Make sure Quartus II is installed successfully on your PC Connect the supplied USB cable to the USB Blaster port and the supplied power cord to 14 Turn the power switch ON e Verify the connection on the USB blaster is available and not occupied or used between Quartus and DEA Start the executable DEA ControlPanel exe on t
13. Figure 5 21 Display SD Card information for the SD Card demonstration 127 Terasic DE4 User Manual www terasic com 5 9 DDR2 SDRAM Many applications use a high performance RAM such as a DDR2 SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how the two DDR2 SDRAM SODIMMSs on the DEA can be accessed We describe how the DDR2 SDRAM High Performance Controller IP is used to create a DDR2 SDRAM controller and how NIOS processor 15 used to read and write the SDRAM for hardware verification The DDR2 SDRAM controller handles the complex aspects of using DDR2 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals The required DDR2 SDRAM SODIMM module should be at least IG Bytes DDR2 800 With two on board DDR2 SDRAM SODIMMSs with DE4 board users have the option of selecting one to perform the demonstration B System Block Diagram Figure 5 22 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The DDR2 controller is configured as a IGbytes DDR2 800 controller The DDR2 IP generates one 400 MHz clock as SDRAM s data clock and half rate system clock 200 MHz for those controllers e g NIOS processor accessing the SDRAM In the SOPC NIOS and On Chip Memory are designed running with the 200 MHz clock and the other c
14. Please input file name de4_hboard_update_portal sof Figure 2 5 Enter sof name to be program 5 The following lines will appear during flash programming Extracting Option bits SREC Extracting FPGA Image SREC and Deleting intermediate files If these lines don t appear on the windows command programming on the flash memory is not successfully setup Please make sure Quartus II 9 1 SP2 and Nios II 9 1 IDE SP2 or later is used II EDS 9 1 Info Peak virtual memory 325 megabytes Info Processing ended Thu Jul 01 20 31 52 2010 Info Elapsed time 99 00 42 Info Total time Con all processors 42 Extracting Option bits Extracting FPGA Image SREC Deleting intermediate files Modify de4_hu map flash file ok Load board update portal file into FPGA please wait Info ee ee ee ee ee ee ee ee Ra kaka RE RE ERE EE EE ERE RE RE EE RE E E E E RE E E E REC RE ERE ERE RE RE BERE EE ERE BERE ERE RE RE RE RE E E Info Running Quartus II Programmer Info Version 9 1 Build 350 03 24 2010 Service Pack 2 J Full Version Info Copyright lt C 19791 2616 Altera Corporation All rights reserved Info Your use of Altera Corporation s design tools logic functions Info and other software and tools and its AMPF partner logic Info functions and any output files from any of the foregoing Info Cincluding device programming or simulation files gt and any associ
15. TERA TRIETATE _ Lite ary dahon Vericanon Sule E and Adapers ery Aviah MIN DDR pg m p ag El D an Wiemory Mapped aive ENG m c rp LUI Agmina esis paripherel cock cross Only ander corripere tha dala vedi al Bec pi ail pier buben plo iron iig bang sel ad aaa ful ede ade fall paripharal mida clack croaaing Only comedponding Vs the data witha of roo noi at fin Acci ting than mec MBA in HDA ODDO Mb Elhernel MAC wilh 1000BAEE avit pis galt n not hane in Dic Ur res dua will red daring PE are nol hardened in bench Undefined values vell be read Irom during simulation flant Path menory capaci CEST E tek ere flesh A 320 MByles 33554452 t RI m so Figure 5 35 SOPC builder 145 Terasic DE4 User Manual www terasic com Figure 5 36 shows a block diagram of the PCS function with embedded PMA MAC Side Ethernet Ethernet MAC with Internal
16. 9 2 Prefix Name Default Setting Load Setting Save Setting Figure 4 8 HSMC Expansion Group The Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty Note if the same HSMC daughter card is selected in both HSMC A and HSMC B expansion prefix name is required to avoid pin name duplication as shown in Figure 4 9 otherwise System Builder will prompt an error message 99 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 100 System Confiquration ADER 4 UNIVERSITY Board Type DE4 230 PROGRAM Project Name DE4 CLOCK Slide Switch x 4 LEDx 8 1 x 2 Button x 4 DIP Switch x 8 SMA Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM SSRAM 2MB RS 232 Programmable PLL Programmable PLL Ethernet x 4 HSMA REFCLK O DDR2 SODIMM 1 O DDR2 SODIMM 2 O Sata Host 0 O Sata Host 1 O Sata Device 0 O Sata Device 1 PLL CLKIN SATA REFCLK O PCle REFCLK GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 D5M 5M Pixel Camera DVI TX RX D5M 1 1 Prefix Name 1 Prefix Name GPIO 1 Header HSMC B Transceiver x 8 4 3 LCD and Touch Gay DVI DXRX Prefix Nam
17. 9 at GATA on Memory Fan Otherwise ple ase follow the s tens below A tt aS zm u l o J Figure 3 15 SATA loopback verification test performed through the Control Panel 3 11 HSMC Choose the HSMC tab to reach the window shown in Figure 3 16 This function is designed to verify the functionality of signals found on the HSMC connectors of ports A and B using a loopback approach Before running the loopback verification HSMC test select the desire HSMC connector to be tested on Follow the instruction noted under Loopback Installation section and click on Verify Please note to turn off the DE4 board before the HSMC loopback adapter is installed to prevent any damage to the DE4 board Note the Control Panel HSMC loopback test does not tests the transceiver signals on the HSMC interface For HSMC transceiver loopback test please refer to the demonstration section 87 Terasic DE4 User Manual www terasic com www terasic com A 1 om 4 F ini i NT ul T Ll b m m LE 1 1 md 1 Flease make sure the HSMC loopback Memory adapter has connected to Eoo connector of DE 4 Ctherwise please follow the s teps below 20 Card M wm Figure 3 16 HSMC loopback verification test performed un
18. E e UNIVERSITY lt PROGRAM th es 54 ei els i gt hum Figure 2 13 Connection setup between THCB HMF2 adapter card and HSMC B JTAG Chain HSMC The JTAG chain on HSMC can be activated through the 3 position DIP switch SW8 If there is no connection established on the HSMC connectors the 3 position DIP switch SW8 are to set On where the signals on the HSMC connectors are bypassed illustrated in Figure 2 14 27 Terasic DE4 User Manual www terasic com WWW CLOFOSIC COT M Ci na Y7 MH DE4 Board 3 Do gt Ge gt HSMC HSMC PCle Port A Port B Connector SW8 ON ON ON ON Figure 2 14 JTAG chain for a standalone DE4 board If the HSMC based daughter card connected to HSMC connector uses the interface 3 position DIP switch 5 9 is set to to which HSMC port is used In this case from Figure 2 15 HSMC port is used where position of the SWS 15 set to Similarly if the JTAG interface isn t used on the HSMC based daughter card position of SWS is set t
19. NIOS II Program usb device elf e USB Driver for Windows XP terasic_usb sys and terasic_usb inf e USB Test Program for Windows XP Terasic_UsbControl exe 115 Terasic DE4 User Manual www terasic com www Lterasic com AN DTE RAN B Demonstration Setup e tis suggested to run this demonstration under Windows XP e Make sure Quartus and NIOS II are installed Power on the DEA board Connect USB Blaster to DEA board and install USB Blaster driver if necessary e Execute the demo batch file test bat under the batch file folder DE4 USBNlemo batchNasb device Users may remove the USB Blaster once the FPGA configuration is completed Connect USB cable from a host computer to the mini AB port in DEA as shown in Figure 5 10 e For the first time the USB port of the host computer is connected to the mini AB port of the DEA board a dialog will pop up to request a USB driver to be installed The required driver 15 available in the demo batch folder 4 USBNdemo batchNusb device e Launch Terasic UsbControl exe under the batch file folder 4 USBNlemo batchNasb device e Click Connect in UsbControl window e After connection established the button status on the DE4 will be updated to the program interface and users can start to configure the LED status now USB Cable namnam A lt lt lt Terasic USB Driver terasic usb sys terasic usb inf USB Port Figure 5 10 Con
20. CcIK2 set rd device 3 CLKIN SATA REFCLK set wr clk3 set wr cIK3 set rd setting trigger conf_wr conf_wr 50MHz conf 50MHz status conf ready conf ready 2 wire interface max sclk MAX SCLK max SDAT If dynamic PLL configuration 15 required users need to modify code according to users desired PLL behavior www terasic co 102 Terasic DE4 User Manual www terasic com Chapter 5 Examples of Advanced Demonstration This chapter introduces several advanced designs that demonstrate Stratix IV GX features using the DE4 board The provided designs include the major features on board such as the SATA HSMC Gigabit Ethernet SD card USB host and device and DDR2 For each demonstration the Stratix IV GX FPGA configuration file is provided as well as full source code in Verilog HDL and C All of the associated files can be found in the DE4_demonstrations de4_ lt Stratix device folder from the DE4 System CD For each of demonstrations described in the following sections we give the name of the project directory for its files which are sub directories of the DE4_demonstrations de4_ lt Stratix_device gt folder 5 1 USB Host USB Universal Serial Bus is a well known communication standard used in many peripherals The DEA board provides a complete USB solution for both host and device applications In this d
21. d quentia ead address 00000000 Length T Figure 3 8 Access DDR2 SO DIMM memory 80 Terasic DE4 User Manual www terasic com www terasic com i BERE S333 PT E Modi aad 13058 zm mar i ID DR SODIMM 1 0000000h WORDS 1 oM Address EFF rDAT A SEGT Power gt eee Address Length File Length le T lt Card Address Length EM Entire Memory o 1a CH A DISCONNECT Figure 3 9 Writing the hexadecimal value 7EFF to location 0x100 3 5 USB2 0 OTG Choose the USB tab to reach the window in Figure 3 10 This function is designed to monitor the status of USB Host Hub in real time Plug a USB device to any USB port of FPGA board and both the device type and speed will be displayed on the control window Figure 3 10 shows a USB storage device plugged into port 3 81 Terasic DE4 User Manual www terasic com www terasic com FPE L2 VLA sia 4 c r m in 4 E Bn Piz EE 7 i m y m k mid wi 1 S mi mt 1 EN High Speed USB Storage E Figure 3 10 Monitoring status of USB ports 3 6 SD CARD Choose the SD CARD tab to the window shown in Figure
22. frequency Table 5 2 EXT PLL CTRL Instruction Ports clk set wr clk2 set wr Output Frequency MHz Description set wr 4 b0001 X Clock Generator Disable 4 b0010 62 5 Setting External Clock Generator 4 b0011 75 4 b0100 100 4 b0101 125 4 b0110 150 4 b0111 156 23 4 b1000 187 4 b1001 200 4 b1010 250 4 b1011 312 5 4 b1100 625 others X Setting Unchanged B The EXT_PLL_CTRL IP Timing Diagram In this reference design the output frequency 15 set to 62 5 75 and 100 MHz with the following timing diagrams illustrated below When the EXT IP receives the conf signal the user needs to define set wr cIk2 set wr and clk3 set wr to set the External Clock Generator When ext pll IP receives conf signal it will read the value back to clkl set rd 2 set rd and set rd Write Timing Waveform As ButtonO 1 is pressed the conf wr signal 1s on the rising edge serial data 1s transfered immediately with the ready signal in the transmission period starting at falling edge level as shown in Figure 5 27 As the transfer is complete the ready signal returns back to original state at high level 135 Terasic DE4 User Manual www terasic com www terasic com ANU RYAN Hame 1024 2048 3072 4096 5120 E144 7168 ext ext wr LE pi ext ext set wr Ec 5
23. 14 HSMB 14 HSMB TX p15 HSMB 15 HSMB TX 15 Terasic DE4 User Manual rasic com LVDS bit 6 or CMOS I O LVDS TX bit or CMOS I O LVDS bit 6n or CMOS LVDS TX bit 7 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS TX bit 7n or CMOS LVDS RX bit 7n or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS or differential clock input LVDS RX or CMOS LVDS RX or CMOS or differential clock input LVDS TX bit 8 or CMOS I O LVDS RX bit 8 or CMOS I O LVDS TX bit 8n or CMOS I O LVDS RX bit 8n CMOS I O LVDS TX bit 9 or CMOS I O LVDS RX bit 9 or CMOS I O LVDS TX bit 9n or CMOS I O LVDS RX bit 9n or CMOS I O LVDS TX bit 10 or CMOS I O LVDS RX bit 10 or CMOS I O LVDS TX bit 10n or CMOS I O LVDS bit 10n or CMOS I O LVDS TX bit 11 or CMOS I O LVDS bit 11 or CMOS I O LVDS TX bit 11n or CMOS I O LVDS bit or CMOS I O LVDS TX bit 12 or CMOS I O LVDS RX bit 12 or CMOS I O LVDS TX bit 12n or CMOS I O LVDS bit 12n or CMOS I O LVDS TX bit 13 or CMOS I O LVDS RX bit 13 or CMOS I O LVDS TX bit 13n or CMOS I O LVDS RX bit 13n or CMOS I O LVDS TX bit 14 or CMOS I O LVDS RX bit 14 or CMOS I O LVDS TX bit 14n or CMOS I O LVDS RX bit 14n or CMOS I O LVDS TX bit 15 or CMOS I O LVDS RX bit 15 or CMOS I O LVDS TX bit 15n or CMOS I O 32 LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V
24. J18 M2 DDR2 WE n DDR2 Write Enable SSTL 18 Class PIN P18 M2 DDR2 CS n0 DDR2 Chip Select 0 SSTL 18 Class PIN H19 M2 DDR2 CAS n DDR2 Column Address Strobe 55 18 Class PIN A13 M2 DDR2 ODTO DDR2 On Die Termination SSTL 18 Class PIN D19 M2 DDR2 CS ni DDR2 Chip Select 1 SSTL 18 Class PIN B13 M2 DDR2 A13 DDR2 Address 13 SSTL 18 Class PIN C19 M2 DDR2 ODT1 DDR2 On Die Termination SSTL 18 Class PIN A14 M2 0082 0032 DDR Data 32 SSTL 18 Class PIN N22 46 Terasic DE4 User Manual rasic com www terasic com M2 DDR2 DQ36 M2 DDR2 DQ33 M2 0082 0037 M2 DDR2 008 n4 M2 DDR2 DM4 M2 0082 DQS p4 M2 DDR2 DQ38 M2 DDR2 DQ34 M2 0082 0039 M2 0082 0035 M2 0082 0044 M2 0082 0040 M2 0082 0045 M2 DDR2 0041 M2 0082 008 n5 M2 DDR2 DM5 M2 DDR2 005 p5 M2 DDR2 DQ42 M2 0082 0046 M2 0082 0043 M2 0082 0047 M2 0082 0048 M2 0082 0052 M2 0082 0049 M2 0082 0053 M2 DDR2 CLK 1 M2 DDR2 CLK n1 M2 0082 005 n6 M2 DDR2 005 M2 DDR2 DM6 M2 DDR2 DQ50 M2 DDR2 DQ54 M2 DDR2 DQ51 M2 DDR2 DQ55 M2 DDR2 DQ56 M2 DDR2 DQ60 M2 DDR2 DQ57 DDR Data 36 DDR Data 33 DDR Data 37 DDR2 Data Strobe n 4 DDR2 Data Mask 4 DDR2 Data Strobe p 4 DDR Data 38 DDR Data 34 DDR Data 39 DDR Data 35 DDR Data 44 DDR Data 40 DDR Data 45 DDR Data 41 DDR2 Data Strobe n 5 DDR2 Data Mask 5 DDR2 Data Strobe p 5 DDR Data 42 DDR Data 46 DDR Data 43 DDR Data 47 DDR Data 48 DDR Dat
25. User Manual World Leading FPGA Based Products and Design Services 1010101000101010101010101010100101010111010100T0T0T0010010101010101001010101010101010101010010 1101010 H0 T2 DOO TO E 10101010100010101010101010101010010101011 lt lt 00000002 101010101000101010101010101010100101010199 010010010101010101001010101010101010101010010 10101010100010101010101 01010101001010101910101001010100100101010101010010107010101 10101010100010101010101010101010010101011101010010T0T100100101010101010010101010101070101010100101101701011011000101111010011010 3 10101010100010101010101010101010010101011101010010101001001010101010100101010101010101010101001001010101 10 HOOOTOEEDTOTOO TO TOS 10101010100010101010101010101010010101011101010010T0T00700101010101010010101010101010101010100101 101010 HU T1000 TOT THO TOO TIO TO ejir HET n 7 4 ter www terasic com Copyright 2003 2010 Terasic Technologies Inc All Rights Reserved CONTENTS Ss GHAPTER T QOUERVIE 4 LUGENERAE DESCRIPTION P 4 5 6 PIBLO Oc nrc 7 CHAPTER2 USING THE DES BOARD in Pr REPERIO 13 CONFIGURA 13 2 2 IUP
26. management Figure 5 15 Nios program software architecture B Design Tools e Quartus II NIOS IL IDE B Demonstration Source Code e Quartus Project directory DEA Simple Socket ServerDEA Ethernet Ethernet Port gt FPGA Bit Stream DE4_Ethernet sof NIOS II Workspace DEA Simple Socket ServerDE4 Ethernet Ethernet Port gt software simple_socket_server 121 Terasic DE4 User Manual www terasic com B Nios IL Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean B Demonstration Batch File Demo Batch File Folder DE4_Simple_Socket_Server de4_ lt Stratix device gt _ethernet_test_batch demo_batch_ lt Ethernet port gt The demo batch file folders include the following files e Batch File de4_net bat de4_net_bashrc open_telnet bat e FPGA Configuration File DE4_Ethernet sof e NIOS II Program simple_socket_server elf B Demonstration Setup e Make sure Quartus and NIOS II are installed e Power on DEA e Connect USB cable to DEA The PC will need to install the USB Blaster driver for the first time use e Execute the demo batch file de4 net bat under the batch file folder where the IP address and port numbers are assigned as shown below in Figure 5 16 122 Terasic DE4 User Manual www terasic com www Lterasic com t3
27. 6 SSTL i8Class AW28 Mi DDR2 007 DDR Data 7 77 8517018 Class AW27 Mi DDR2 042 DDR Data 2 SSTL 8Class AW29 Mi DDR2 pDDRDat3 7 SSTL i8Class AV28 Mi DDR2 DQ12 DDR Data 12 8571 18 Class 41 Terasic DE4 User Manual www terasic com M1 DDR2 0013 M1 DDR2 M1 DDR2 Dag M1 DDR2 DM1 M1 DDR2 DQS n1 M1 DDR2 CLK M1 DDR2 DQS 1 DDR2 M1 DDR2 M1 DDR2 DQ14 M1 DDR2 DQ11 M1 0082 DQ15 M1 0082 0016 1 0082 0020 M1 0082 0017 M1 0082 0021 M1 0082 005 n2 M1 0062 005 p2 M1 0082 DM2 M1 DDR2 DQ18 M1 DDR2 DQ22 1 DDR2 0019 1 DDR2 0023 M1 0082 0024 M1 0082 0028 1 0082 0025 1 0082 0029 M1 DDR2 DM3 M1 DDR2 DQS n3 M1 DDR2 005 1 DDR2 0026 M1 DDR2 DQ30 M1 DDR2 0027 M1 DDR2 M1 DDR2 CKEO M1 DDR2 M1 DDR2 A15 DDR Data 13 DDR Data 8 DDR Data 9 DDR2 Data Mask 1 DDR2 Data Strobe n 1 Clock for DDR2 DDR2 Data Strobe p 1 Clock nO for DDR2 DDR Data 10 DDR Data 14 DDR Data 11 DDR Data 15 DDR Data 16 DDR Data 20 DDR Data 17 DDR Data 21 DDR2 Data Strobe n 2 DDR2 Data Strobe p 2 DDR2 Data Mask 2 DDR Data 18 DDR Data 22 DDR Data 19 DDR Data 23 DDR Data 24 DDR Data 28 DDR Data 25 DDR Data 29 DDR2 Data Mask 3 DDR2 Data Strobe n 3 DDR2 Data Strobe p 3 DDR Data 26 DDR Data 30 DDR Data 27 DDR Data 31 Clo
28. 8 position DIP switch 2 seven segment displays e Clock system O O On board clock oscillators SOMHz and 100MHz SMA connectors for external clock input SMA connectors for clock output www terasic com ANU S RYA e Other interfaces o USB 2 0 high speed host device OTG o Current sensor for FPGA current measurement o Temperature sensor 1 3 Board Overview Figure 1 1 and Figure 1 2 1s the top and bottom view of the DE4 board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to this figure for relative location when the connectors and key components are introduced in the following chapters USB Blaster 2 USB Host Stratix GX Port Type Ports DDR2 SO DIMM EPASGX230KF40C2 support upto 468 or EPASGX530KH40C2 T segment amp User 8 Position USB 4 Serial 12V and 3 3V Power Displays LEDs DIP Switch mini AB Port Ports Supply Connector cir 4 SER i gl 22 12 0 p cll Power Switch 4 Slide alala 54 Switches ug CPU Reset QS un k LIRR LE ILE Push button n 85 232 4 Push buttans a 4 PE E 2 b Clock ae 4 Input Output uis e wr e dian a SMA Connectors Gigabit gt Taun PEL 100MH
29. GPIO 0 GPIO 1 Clock Input GPIOO DO GPIOO 01 GPIOO DO 0 6 GPIO1 D1 Clock Input GPIOO D2 GPIOO 03 1 02 1 03 GPIOO 04 GPIOO 05 1 04 1 05 GPIOO 06 6 GPIOO 07 1 06 GPIO1 07 GPIOO 08 oq GPIOO D9 1 08 oq 1 09 6 GND GND GPIOO D10 GPIOO 011 1 010 GPIO1 011 GPIOO 012 GPIOO 013 1 0112 GPIO1 013 GPIOO 014 E GPIOO 015 1 014 GPIO1 D15 GPIOO D16 A 017 1 016 a 1 017 GPIOO 018 21 GPIOO 019 1 018 22 1 019 GPIOO 020 22 GPIOO 021 GPIO1 020 7 GPIO1 D21 GPIOO 022 DE 023 GPIO1 022 GPIO1 023 GPIOO 024 025 1 024 GPIO1 025 3 3V GND 3 3V GND GPIOO D26 GPIOO 027 1 026 GPIO1 D27 GPIOO 028 GPIOO 029 GPIO1 028 1 029 GPIOO D30 031 GPIO1 030 1 031 GPIOO 032 033 GPIO1 032 1 033 GPIOO 034 035 GPIO1 034 1 035 Figure 2 18 Pin distribution of the GPIO expansion headers Finally Figure 2 19 shows the connections between the GPIO expansion headers and Stratix IV GX GPIOO 35 0 AAU 8 RYAN Stratix IV GPIO1 35 0 Figure 2 19 Connection between the GPIO expansion headers and Stratix IV Terasic DE4 User Manual www terasic com www terasic com B External 14 pin Expansion Header An external 14 expansion header JP6 is prov
30. HSMA 16 HSMA TX 16 HSMA RX n16 HSMA CLKOUT 2 HSMA CLKIN p2 HSMA CLKOUT n2 HSMA CLKIN n2 Note for Table 2 11 signals SDA and E HSMC SCL level shifted from 3 3V FPGA to 1 8V HSMC LVDS bit 15 or CMOS I O LVDS TX bit 15n or CMOS I O LVDS RX bit 15n or CMOS I O LVDS TX bit 16 or CMOS I O LVDS bit 16 or CMOS I O LVDS TX bit 16n or CMOS I O LVDS RX bit 16n or CMOS I O LVDS or CMOS I O or differential clock input output LVDS RX or CMOS or differential clock input LVDS or CMOS I O or differential clock input output LVDS RX or CMOS or differential clock input 2 6 GPIO Expansion Headers The DE4 Board consists of two 40 pin expansion headers as shown in Figure 2 18 Each header has 36 pins connected to the Stratix IV GX FPGA with the other 4 pins providing DC 5V VCC5 DC 3 3 VCC33 and two GND pins Among these 36 I O pins for connector JP3 there are 2 pins connected to the differential clock inputs of the FPGA The I O pins on the expansion headers have a 3 0 V I O standard 36 Terasic DE4 User Manual www terasic com LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V PIN AN32 PIN AM29 PIN AP33 PIN AK30 PIN AT34 PIN AL30 PIN AR34 PIN AG34 PIN AF34 PIN AG35 PIN AE35 www terasic com JP3
31. HSMC TMS HSMA TDO HSMA TDI HSMA OUTO HSMA CLKINO HSMA DO HSMA 1 02 HSMA D3 HSMA TX pO HSMA TX HSMA TX 1 HSMA 1 HSMA TX n1 n1 HSMA TX 2 HSMA 2 TX n2 n2 HSMA p3 HSMA HSMA TX n3 HSMA RX n3 HSMA TX p4 HSMA TX n4 HSMA RX n4 HSMA TX p5 HSMA 5 TX n5 Terasic DE4 User Manual Transceiver RX bit 2n Transceiver TX bit 1 Transceiver RX bit 1 Transceiver TX bit 1n Transceiver RX bit 1n Transceiver TX bit 0 Transceiver RX bit 0 Transceiver TX bit On Transceiver RX bit On Management serial data Management serial clock JTAG clock signal JTAG mode select signal JTAG data output JTAG data input CMOS I O Dedicated clock input LVDS TX or CMOS LVDS RX CMOS I O LVDS TX or CMOS LVDS RX or CMOS I O LVDS TX bit 0 or CMOS I O LVDS bit 0 or CMOS I O LVDS TX bit On or CMOS I O LVDS RX bit or CMOS I O LVDS TX bit 1 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS TX bit 1n or CMOS I O LVDS RX bit 1n or CMOS I O LVDS TX bit 2 or CMOS I O LVDS bit 2 or CMOS I O LVDS TX bit 2n or CMOS LVDS bit 2n or CMOS I O LVDS TX bit 3 or CMOS I O LVDS bit CMOS I O LVDS TX bit 3n or CMOS I O LVDS RX bit 3n or CMOS I O LVDS TX bit 4 or CMOS I O LVDS bit 4 or CMOS I O LVDS TX bit or CMOS LVDS bit 4n
32. This function is designed to monitor status of switches and buttons from a graphic interface in real time It can be used to verify the functionality of switches and buttons 77 Terasic DE4 User Manual www terasic com www terasic com sou im Ba um m IH F KT mus pd Ja m Buttons Button Buttoni Button Figure 3 7 Monitoring Switches and Buttons 3 4 Memory Controller The Control Panel can be used to write read data to from the DDR2 SO DIMM Flash SSRAM EEPROM memory on the DE4 board Note only the read function is supported on the flash memory of the DE4 Control Panel We will describe how the DDR2 SO DIMM 15 accessed Click on the Memory tab to reach the tab window shown in Figure 3 8 A 16 bit value can be written into the DDR2 SO DIMM memory by three steps namely specifying the address of the desired location entering the hexadecimal data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 9 depicts the result of writing the hexadecimal value 7EFF to location 0 100 followed by reading the same location 78 Terasic DE4 User Manual www terasic com www terasic com The Sequential Write function of the Control Panel is used to write the contents of a file to the serial configuration device as described below e Specify the starti
33. application readme txt 8 15 usb host svslib DES SOPC Figure 5 4 Source code list of the USB Host demonstration B Nios Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project 15 cleaned first from the Project menu of Nios followed by Clean 109 Terasic DE4 User Manual www terasic com www teresic com B Demonstration Batch File Demo Batch File Folder USB BatchNusb host The demo batch file folders include the following files e Batch File test bat test bashrc FPGA Configuration File DE4_USB sof NIOS II Program usb host elf B Demonstration Setup e Make sure Quartus II and NIOS II are installed Power on DEA e Connect USB cable to DEA The PC will need to install the USB Blaster driver for the first time use e Execute the demo batch file test bat under the batch file folder DEA USBMdemo batchNusb host The LED D13 D15 of the three USB ports will be light after USB ports are configured completed For USB mass storage demonstration copy test files to the root directory of USB Disk Plug USB mass storage device or HID USB Mouse into the USB ports in DEA as shown in Figure 5 5 e The device information will be displayed in nios2 terminal as shown in Figure 5 6 B Reference 15 1761 Hi Speed Universal Bus On The Go controller Rev 04 5 March 2007 e Universal Serial Bus Spec
34. otherwise System Builder will prompt an error Message 977 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 100 System Configuration S RYAN asic 9 UNIVERSITY 2 Board Type 4 230 PROGRAM www terasic com Project Name DE4 CLOCK Slide Switch x 4 LEDs 7T Segement x 2 Button x 4 DIP Switch x 8 SMA Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM SSRAM 2MB RS 232 Programmable PLL Programmable PLL Ethernet x 4 HSMA REFCLK O DDR2 SODIMM 1 O DDR SODIMM_2 HSMB REFCLK Sata Host 0 O Sata Host 1 Sata Device 0 Sata Device 1 PLL_CLKIN SATA_REFCLK O PCle GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 D5M 5M Pixel Camera None Name 5410 Name Name 5410 GPIO 1 Header HSMC B Transceiver x 8 D5M Pixel Camera None Prefix Name 25 _2 Prefix Name Default Setting Load Setting Save Setting Figure 4 7 Specify Prefix Name for GPIO Expansion Board B HSMC Expansion Users can connect HSMC interfaced daughter cards onto either HSMC A or HSMC B located on the DE4 board shown in Figure 4 8 Select the daughter card you wish to add to your design under the appropriate HSMC connector where the daughter card 15 connec
35. shown in Figure 6 9 PCIe Driver Install EJ Figure 6 9 PCle Driver Installation Program Click Install to begin installation process It takes several seconds to install the driver When installation 15 complete the following dialog window will popup shown in Figure 6 10 Click and then Exit to close the installation program Ierasic PCIe Driver Instal ee Information Congraturation CLD The PCIe driver installed successfully Figure 6 10 PCle driver installed successfully Once the driver 15 successfully installed users can view the device under the device manager window shown in Figure 6 11 161 Terasic DE4 User Manual www terasic com www terasic co m i Device Manager loj x iy Computer Ee Disk drives E E Display adapters 89 8 9 Human Interface Devices INE 7 Mice and other pointing devices d Monitors H E Network adapters H i Ports amp LPT EE Processors 1 Sound video and game controllers 4 System devices Universal Serial Bus controllers Figure 6 11 Device Manager B Create a Software Application All necessary files to create a PCIe software application are located in the PCle_SDK Library which includes the following files TERASIC PCIE h TERASIC PCIE DLL Below lists the procedures to use the SDK files in users
36. 0 Controller and an Altera MAX II CPLD Current configuration will be lost when the power is turned off Figure 2 1 illustrates the configuration scheme for the DEA 13 Terasic DE4 User Manual www terasic com www terasic com To download a configuration bit stream into the Stratix IV GX FPGA perform the following steps e Make sure that power is provided to the DEA board Connect the USB cable supplied directly to the USB Blaster port of the DE4 board e The FPGA can now be programmed in the Quartus II Programmer by selecting a configuration bit stream file with the sof filename extension Please refer to DEA Getting Started Guide pdf for more detailed procedure of FPGA programming DE4 Board l JTAG HSMA EN SW8 1 HSMB SWB 2 TCK TMS PCI EXPRESS TDI EDGE TDO Connector __ PCIE EN SWB 3 Figure 2 1 JTAG configuration scheme B Flash Programming DEA development board contains a common flash interface CFI flash memory to meet the demands for a larger FPGA configuration storage The parallel flash loader PFL feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the Stratix IV GX FPGA Figure 2 2 depicts the connection setup between the CFI flash memory Max II CPLD and Stratix IV GX 14 Ter
37. 15 designed to configure the external programmable PLL on the DEA There are 3 programmable clocks for the DE4 board that generates reference clocks for the following signals HSMA REFCLK HSMB REFCLK and PLL_CLKIN SATA_REFCLK The clock frequency can be adjusted to 62 5 75 100 125 150 156 25 187 5 200 250 312 5 and 625MHz Choose the PLL tab to reach the window shown in Figure 3 14 To set the desire clock frequency for the associated clock signal click on Set 85 Terasic DE4 User Manual www terasic com www terasic com mesi 5557 n ii t EX TR Memory SS 1 Figure 3 14 Programmable External PLL configured through Control Panel 3 10 SATA Choose the SATA tab to reach the window shown in Figure 3 15 This function is designed to verify the functionality of the transceiver signals found on the SATA interface using a loopback approach Before running the Loopback verification SATA test follow the Installation and click on Verify 86 Terasic DE4 User Manual www terasic com www terasic com 18 Wr Cds insu Ls ss relie i estar 1 1 ae 4 E L te Uum I im a 5 D Lp EL 1 m 1 Flease make sure two SATA cables are connected between HOST DEM S
38. 3 11 This function 15 designed to read the identification and specification of SD Card 4 bit SD MODE 15 used to access the SD Card This function can be used to verify the functionality of SD CARD interface To gather the information simply insert a SD Card to the FPGA board and press the Read button The SD CARD identification and specification will be displayed on the control window 82 Terasic DE4 User Manual www terasic com www terasic com a 4 Buda Qi inim Bm LEX oe E 1 i L Loue JI il Temp Manufacturer ID 1Bh OEN Application 4D5 3h Product Revision 1 Serial Mo 7 Date Code Memory fmm Y ead A Time 1000 uz Ts amp Time ME ACTU 100 cycle Figure 3 11 Reading the SD Card Identification and Specification 3 7 Temperature Monitor Choose the Temperature tab to reach the window shown in Figure 3 12 This function is designed to control temperature sensor through Control Panel The temperatures of Stratix IV GX and DE4 board are shown on the right hand side of the Control Panel When the temperature of Stratix IV GX exceeds the maximum setting of Over Temperature or Alert a warning message will be shown on the Control Panel Click Read button to get current settings for Over temperature
39. 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V PIN A29 PIN J27 PIN G26 PIN F26 PIN G28 PIN B26 PIN D17 PIN F16 PIN AF16 PIN AJ14 PIN AD15 PIN AE15 PIN AE16 PIN AH14 PIN AM13 PIN AN15 PIN AP15 PIN AG18 PIN AG19 PIN AM19 PIN AN19 PIN AV16 PIN AT17 PIN AV17 AU17 PIN AW18 PIN AT18 PIN AU18 PIN AR19 PIN AW20 AW21 PIN AF19 PIN AE19 PIN AE18 PIN AD19 PIN G13 PIN M16 PIN M27 PIN K27 PIN L26 PIN P19 PIN AR22 PIN N19 PIN AJ20 www terasic com OTG DC IRQ Peripheral Controller IRQ 1 8 V PIN AT22 OTG RESET n OTG Reset 1 8 V PIN AU22 OTG DMA Controller request for TG HC DRE 1 8 V PIN 21 OTG_HC_ Host Controller OTG HC DACK OTG DMA Controller request 18 PIN AT21 Acknowledgement OTG DC DREQ Pu DMA Controller request for 1 8 V PIN AP21 Peripheral Controller OTG DC DACK Peripheral Controller DMA 1 8 V AH20 request acknowledgement USB 12MHZ OTG CLK input PSW1 Power Switch for port 1 DM1 Downstream data minus port 1 DP1 Downstream data plus port 1 USB ID ID input to detect the default PSW2 Power Switch for port 2 DM2 Downstream data minus port 2 DP2 Downstream data plus 2 PSW3 Power Switch for port 3 DM3 Downstream data minus port 3 DP3 Downstream data plus port 2 9 SD Card The DEA 1s equipped with a SD card socket and can be accessed as an optional external memory in both SPI and 4 bit SD
40. Batch File Folder DE4 EXT batch The demo batch file folders include the following files e Batch File FPGA Configuration File 4 EXT PLL sof B Demonstration Setup e Make sure Quartus II is installed on your Power on the DEA board Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e Execute the demo batch file test bat under the batch file folder DE4 EXT PLINdemo batch e Press ButtonO or Button for the write and read operations respectively on the EXT CTRL PLL demonstration 5 7 Power Measurement The Power Measurement demonstration illustrates how to measure the DE4 power consumption based on the built in power measure circuit The power measurement 15 implemented using two multi channel differential 24 bit Linear Technology LT2418 delta sigma analog to digital converters ADC with sense resistors to measure the small voltage drop across the resistors The ADCs is connected to the FPGA via serial peripheral interface SPI bus 137 Terasic DE4 User Manual www terasic com rasic com AN DTE RAN This demonstration uses an embedded NIOS II processor to read the voltage drop value from the ADC through the SPI interface Based on the voltage drop values and sense resistors the program can calculate the associated current and power consumption The relative information is populated on the NIOS Terminal and is updated every two seconds B Sy
41. C C project e Create users C C project e Include TERASIC_PCIE h in the C C project e Copy TERASIC_PCIE DLL to the folder where the project exe is located e Dynamically load TERASIC_PCIE DLL in C C project To load the DLL please refer to two examples below e Call the SDK API to implement desired application B TERASIC PCIE DLL Software API Using the TERASIC PCIE DLL software API users can easily communicate with FPGA through the PCIe bus The API details are described below 162 Terasic DE4 User Manual www terasic com www terasic com PCIE ScanCard unction Lists the PCIe cards which matches the given vendor ID and device ID Set Both ID to zero to lists the entire PCIe card Prototype BOOL PCIE ScanCard WORD wVendorID WORD wDevicelD DWORD pdwDeviceNum PCIE CONFIG szConfigList arameters w VendorID Specify the desired vendor ID A zero value means to ignore the vendor ID wDevicelD Specify the desired device ID A zero value means to ignore the produce ID pdwDeviceNum A buffer to retrieve the number of PCIe card which is matched by the desired vendor ID and product ID szConfigList A buffer to retrieve the device information of PCIe Card found which is matched by the desired vendor ID and device ID Return Value Return TRUE if PCIe cards are successfully enumeated otherwise FALSE is return PCIE_Open unction Open a specified PCIe card with vendor ID devi
42. DEA SDCARD elf B Demonstration Setup e Make sure Quartus and NIOS II are installed on your Power on the DEA board e Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e Execute the demo batch file test bar under the batch file folder DE4 SDCARDdemo batch e After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Copy test files text txt created by the user to the root directory of the SD Card e Insert the SD card into the SD Card socket of DE4 as shown in Figure 5 20 e Press Button3 of the DE4 board to start reading SD Card e The program will display SD Card information as shown in Figure 5 21 126 Terasic DE4 User Manual www terasic com www Lterasic com 3 I Lr 4T un d a LN ie eo T3 ATURA lt c NEAR nen 6 LTMiBO V Mode Figure 5 20 Insert SD Card for the SD Card demonstration n x niozsZ terminal l amp sB Blaster 5 device 1 instance nios2 terminal lt Use the IDE stop button or Gtrl G to terminate DE4 SDCARD Demo Processing sdcard mount success Root Directory Item Count 6 lmicrium_ www lpresentations 2 3 JAltera_EEK_Applications 4 1 MAGE 5 1TEST test txt dump Test Done Press BUTTONS to test again
43. Data 42 DDR Data 46 DDR Data 43 DDR Data 47 DDR Data 48 DDR Data 52 DDR Data 49 DDR Data 53 Clock p1 for DDR2 Clock n1 for DDR2 DDR2 Data Strobe n 6 DDR2 Data Strobe n 6 DDR2 Data Mask 6 DDR Data 50 DDR Data 54 DDR Data 51 DDR Data 55 DDR Data 56 DDR Data 60 DDR Data 57 DDR Data 61 DDR2 Data Mask 7 DDR2 Data Strobe n 7 DDR2 Data Strobe p 7 DDR Data 58 DDR Data 59 DDR Data 62 DDR Data 63 DDR2 2 Data DDR2 2 Clock DDR2 Presence detect address input 0 DDR2 Presence detect address input 1 Terasic DE4 User Manual rasic com 44 SSTL 18 Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class 1 8 V 1 8 V 1 8 V 1 8 V AT16 PIN AP16 PIN AU16 PIN AU15 PIN AW16 PIN AT15 AW11 PIN AW14 PIN AW12 PIN AV14 PIN AE20 PIN AF20 PIN AW13
44. FIFO Buffers 1000 Receive Control SGMII amp 1 25 Gbps T gt De encapsullation 8b 10b 4 pe S Serial Converter amp Al Recei i I Decoder serializer a Synchronization a i 1 l 1 1 1 1 1 1 1000 Base X PCS Transmit Control i 1 25 Gbps MISMI gt Transmit Serial Converter Transmit 8b 10b Encapsulation Status Configuration L LEDs 1 1 1 1 Avalon MM Interface Figure 5 36 1000BASE X SGMII PCS with PMA After the SOPC hardware project being built develop the SOPC software project and the basic architecture is shown in Figure 5 37 The top block contains the Nios II processor and the necessary hardware to be implemented into the DE4 host board The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work The HAL API block provides the interface for the software device drivers while the Micro C OS II provides communication services to the NicheStack and Web Server The NicheStack TCP IP Stack software block provides networking services to the application block where it contains the tasks for Web Server 146 Terasic DE4 User Manual www terasic com www terasic com Figure 5 37 Nios Il program software architecture To start with the Web Server program will initiate the MAC and ne
45. Functions Board Schematic VO Stratix IV GX Description Reference Signal Name Standard Pin Number SWO SLIDE SWO High logic level when SW in the UPPER 2 5 V PIN J7 Swi SLIDE_SW1 position 2 5 V PIN K7 SW2 SLIDE SW2 3 0 V PIN AK6 SW3 SLIDE SW3 2 5 V PIN L7 Table 2 6 DIP Switch Pin Assignments Schematic Signal Names and Functions Board Schematic mm VO Stratix IV GX Description Reference Signal Name Standard Pin Number SW6 SWO User Defined DIP switch connected to 3 0 V PIN AB13 SW6 SW1 FPGA device When the switch is in the 3 0 V PIN AB12 SW6 SW2 ON position a logic 0 is selected 3 0 V PIN AB11 SW6 SW3 similarly when the switch is in the OFF 4 PIN AB10 SW6 SWA position a logic 1 is selected 3 0 V PIN AB9 SW6 SW5 3 0 V PIN AC8 SW6 SW6 3 0 V PIN AH6 SW6 SW7 3 0 V PIN AG6 po Terasic DE4 User Manual www terasic com www terasic com The DEA board consists of 8 user controllable LEDs to allow status and debugging signals to be driven to the LEDs from the designs loaded into the Stratix IV device Each LED is driven LEDs directly by the Stratix IV FPGA The LED 15 turned on or off when the associated pins are driven to a low or high logic level respectively A list of the pin names on the FPGA that are connected to the LEDs is given in Table 2 7 Table 2 7 User LEDs Pin Assignments Schematic Signal Names and Functions Schematic Board Signal Reference ame D1 LEDO D2 LED1 D
46. IInterNiche Portable 1 23 1 Copyright 1996 2008 by InterMiche Technologies All rights reserved Iprep tse mac Your Ethernet MAC address is 12 34 56 prepped 1 interface initializing tse init INFO TSE MAC Found at address INFO PHY Marvell 88 1111 found at PHY address 12 of MAC GroupI6 INFO Automatically mapped to tse_mac_devicel6 Restart Auto Negotiation checking PHY link Auto Negotiation FAILED Enabling auto crossover PHY reset PHYIB B Checking link Link not yet established restart auto negotiation PHY H 6 Restart Auto Negotiation checking PHY link PHY 9 9 Auto Negotiation FAILED 9 91 Link could not established Auto Negotiation not completed Speed 188 Duplex Full COMFIG BxBBBBBBHB MAC post initialization CMD_CONF1 G 8x64608283 tse_sgdma_read_init descriptor chain desc depth created mctest init called address of eti 192 168 1 234 Created Inet main task 2 Created clock tick task 3 DHCP timed out going back to default IP addresses Simple Socket Server starting up sss_task Simple Socket Server listening on port Created simple socket server task Prio 4 gt Figure 5 16 Simple socket server To establish connection start the t
47. PCML PIN T36 PCIE TX n6 NET Add in card transmit bus 1 4 V PCML PIN T37 PCIE TX p7 NET Add in card transmit bus 1 4 V PCML PIN P36 PCIE TX n7 NET Add in card transmit bus 1 4 V PCML PIN P37 PCIE RX pO Add in card receive bus 1 4 V PCML PIN AUS38 PCIE RX nO Add in card receive bus 1 4 V PCML AU39 PCIE Add in card receive bus 1 4 V PCML PIN AR38 PCIE RX n1 Add in card receive bus 1 4 V PCML AR39 PCIE RX p2 Add in card receive bus 1 4 V PCML PIN AJ38 PCIE RX n2 Add in card receive bus 1 4 V PCML PIN AJ39 PCIE RX p3 Add in card receive bus 1 4 V PCML PIN AG38 5m Terasic DE4 User Manual www terasic com www terasic com PCIE RX n3 Add in card receive bus 1 4 V PCML PIN AG39 PCIE RX p4 Add in card receive bus 1 4 V PCML PIN 8 PCIE RX n4 Add in card receive bus 1 4 V PCML PIN 9 PCIE RX p5 Add in card receive bus 1 4 V PCML PIN AC38 PCIE RX n5 Add in card receive bus 1 4 V PCML PIN AC39 PCIE RX p6 Add in card receive bus 1 4 V PCML PIN U38 PCIE RX n6 Add in card receive bus 1 4 V PCML PIN U39 PCIE RX p7 Add in card receive bus 1 4 V PCML PIN R38 1 4 V PCIE RX n7 Add in card receive bus PCML PIN R39 PCIE REFCLK p Motherboard reference clock HCSL PIN 38 PCIE REFCLK n Motherboard reference clock HCSL PIN AN39 PCIE PREST n Reset 2 5 V PIN V30 PCIE SMBCLK SMB clock 2 5 V PIN R31 PCIE SMBDAT SMB data 2 5 V PIN W33 PCIE WAKE n Wake signal 2 5 V PIN U35 PCIE PRSNT1n Hot plug detect Hot plug detect x1 PCle
48. When oFIFO MEM SEL is set to high oDMARD ADDR bus is a FIFO ID that is used to indicate that which FIFO buffer is selected by PC API Read data bus Read signal Read data valid When oFIFO MEM SEL is set to low it is address bus of DMA transfer and the value of address bus is cumulative by PCle IP and it is 128 bit data per address When oFIFO MEM SEL is set to high oODMARD ADDR bus is a FIFO ID that is used to indicate that which FIFO buffer is selected by PC API Write data bus Write signal Indicates that DMA channel is memory mapping interface or FIFO link interface When this signal is asserted high DMA channel FIFO link interface When the signal is asserted low it is memory mapping interface 4 5 6 7 8 9 oDMARD_ADDR OD DATA 0 5 oDMARD READ 1 RDVALID 11 oFIFO SEL Low Level 1 2 clock cycles Figure 6 4 Read transaction waveform of the PCle channel on memory mapping mode Terasic DE4 User Manual www terasic com 157 www terasic com 1 2 3 4 5 6 7 8 9 l NOM NC NOM NF NM oDMAWR X_n XA A2 4 gt oDMAWR DO X D X 02 X 03 X 04 gt 1 1 oDMAWR WRITE oFIFO MEM SEL Figure 6 5 Write transaction wavefo
49. mode Table 2 19 lists the pin assignments of the SD card socket with Stratix IV GX FPGA The connection between the SD card and Stratix IV GX device 1s presented in Figure 2 22 5 Terasic DE4 User Manual www terasic com www terasic com DATO DATI DAT2 Stratb IV CLK CMD WP n Figure 2 22 Connections between the SD card and Stratix IV GX Table 2 19 SD Card Socket Pin Assignments Schematic Signal Names and Functions Schematic e Stratix IV GX Pin Description Standard Signal Name Number E SD CLK Clock for SD 1 8 V PIN AT19 SD WP n Write protection for SD 1 8 V PIN AH18 E SD DATO Data bit 0 for SD 1 8 V PIN AR20 E SD Data bit 1 for SD 1 8 V PIN AT20 E SD DAT2 Data bit 2 for SD 1 8 V PIN AU19 E SD DAT3 Data bit 3 for SD 1 8 V PIN AU20 E SD CMD Command for SD 1 8 V PIN AV20 2 10 Clock Circuitry B Stratix IV GX FPGA Clock Inputs and Outputs DEA development board contains three types of clock inputs which include 16 global clock inputs pins external PLL clock inputs and transceiver reference clock inputs The clock input sources of the Stratix GX FPGA originate from two on board oscillators a 50M Hz and 1OOMHz driven through the clock buffers as well as other interfaces including HSMC GPIO expansion headers and SMA connectors The overall clock distribution of the DEA is presented in Figure 2 23 Table 2 20 depicts the clock options available and their associated DIP switch set
50. slot enabled using SW9 dip switch Hot plug detect x4 PCle slot enabled using SW9 dip switch Hot plug detect x8 PCle slot enabled using SW9 dip switch PCIE PRSNT2n x1 PCIE PRSNT2n x4 PCIE PRSNT2n x8 B Trigger Switch The DEA provides 2 pin header JP2 with one pin connected directly to the Stratix IV GX FPGA while the other pin connected to GND The 2 pin header 15 intended to be used as a trigger switch not included in the DEA kit package It is placed in a location where the PCIe bracket is installed which conveniently allows users to install a trigger switch to the 2 pin header as the DE4 is connected to the PC through the PCIe slot shown in Figure 2 25 Users can incorporate the trigger switch in their design as a reset or trigger function Table 2 24 shows the pin assignments of the 2 pin header Table 2 24 2 header Pin Assignments Schematic Signal Names and Functions Schematic Stratix IV GX Pin Description Standard Signal Name Number EXT IO General Purpose 3 0 V PIN AC11 58 Terasic DE4 User Manual www terasic com www terasic com Figure 2 25 PCle bracket setup with the trigger switch connected to 2 header JP2 2 12 Gigabit Ethernet GigE The DE4 development board is equipped with four Marvell Integrated 10 100 1000 Gigabit Ethernet transceiver devices The device is an auto negotiating Ethernet PHY with a default SGMII MAC interface The Marvell device is po
51. store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Return TRUE if write data 1s successful otherwise FALSE 15 returned 6 4 Fundamental Communication The application reference design shows how to implement fundamental control and data transfer In the design basic I O is used to control the BUTTON and LED on the DE4 High speed data transfer is performed by DMA Both Memory Mapped and FIFO memory types are demonstrated in the reference design The demonstration also lists the associated PCIe cards B Demonstration Files Location The demo file 1s located in the folder PCIE FundamentaNDemo batch The folder includes following files e PC Application Software PCIe Fundamental Demo exe FPGA Configuration File 4 Fundamental sof e Library TERASIC PCIE DLL Demo Batch File test bat 168 Terasic DE4 User Manual www terasic com rasic com AN DTE RAN B Demonstration Setup e Install DEA on your e Download the DEA Fundamental sof into the DEA using Quartus II Programmer e Restart Windows e Install PCIe driver if necessary The driver is located in the folder PCIe SDKNDriver e Launch the demo program PCIe Fundamental Demo exe shown in Figure 6 12 Select FPGA Board 1721 PID E001h Refresh Register Read write Button Register 0x04 LED Register 0x04 3 rCustom Registers
52. supported By calling the exported FAT functions users can browse files under the root directory of the SD card Furthermore users can open a specified file and read the contents of the file The main block implements main control of this demonstration When the program i1s executed it detects whether a SD card 15 inserted If a SD card is found it will check whether the SD card 1s formatted as FAT file system If a FAT file system 1s found it searches all files in the root directory of the FAT file system and displays their names in the nios2 terminal If a text file named test txt is found it will dump the file contents If users press BUTTONG of the DEA board the program will perform above process again Figure 5 19 Software stack of the SD Card demonstration B Design Tools e Quartus II NIOS IL IDE B Demonstration Source Code e Project directory DE4 SDCARD e Bit stream used DE SDCARD sof NIOS II Workspace DE4 SDCARDNSoftware 125 Terasic DE4 User Manual www terasic com B Nios IL Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean B Demonstration Batch File Demo Batch File Folder DE4 SDCARD Demo_ Batch The demo batch file includes following files e Batch File test bat test bashrc FPGA Configure File DE4_SDCARD sof NIOS II Program
53. the main block is implemented to communicate with a host computer It calls bulk read functions to receive commands from the host computer and calls bulk write function to return data to the host computer From the host computer test program named UsbControl exe is used to communicate with the DEA as shown in Figure 5 8 Users that are connecting the DE4 USB device port for the first time a dialog window will appear requesting a USB driver to be installed The driver 15 available in the current demo folder named terasic_usb sys and terasic_usb inf After the driver is installed users can launch the test program to communicate with the DEA 113 Terasic DE4 User Manual www terasic com www Lterasic com Terasic Controller Y 2 0 0 LED LED LED6 LEDS LED4 LEDS LED LEDI LEDO PPP Pee ey Dip Switch ETE E iE fa Slide Switch Button mm mm Disconnect met Led success Figure 5 8 User interface of the Terasic UsbControl exe B Design Tools e Quartus II e NIOS II IDE B Demonstration Source Code e Quartus Project directory 4 USB e FPGA Bit Stream 4 USB sof NIOS II Workspace DEA USBNSoftwareWroject Usb Device The NIOS II source code list is shown in Figure 5 9 Users can modify terasic debug h to configure the debug message Note that any debug message may affect the USB performance or even cause malfunction in this demonstration 114 Terasic DE4 User Manual w
54. 1 GPIO1 D32 GPIO1 D33 GPIO1 D34 GPIO1 D35 GPIO Expansion 1 IO 30 GPIO Expansion 1 IO 31 GPIO Expansion 1 1032 GPIO Expansion 1 IO 33 GPIO Expansion 1 IO 34 GPIO Expansion 1 IO 35 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V PIN AF13 PIN AE13 PIN AE10 PIN AP10 PIN AE12 PIN AE11 Table 2 14 External 14 pin Expansion Header JP6 Pin Assignments Schematic Signal Name GPIOO DO GPIOO D1 GPIOO D2 GPIOO D3 GPIOO D4 GPIOO D5 GPIOO D6 Schematic Signal Names and Functions Description GPIO Expansion 0 IO 0 Clock In GPIO Expansion 0 IO 1 Expansion 0 IO 2 Clock In Expansion 0 IO 3 Expansion 0 IO 4 GPIO Expansion 0 IO 5 GPIO Expansion 0 IO 6 2 7 DDR2 SO DIMM Two 200 pin DDR2 SO DIMM sockets are provided as a flexible and efficient form factor volatile memory for user applications The two DDR2 SODIMM socket is wired to support a maximum capacity of 8GB with a 64 bit data bus Using differential DQS signaling for the DDR2 SDRAM interfaces it 15 capable of running at or above 400M Hz memory clock for a maximum theoretical bandwidth of over 102Gbps Figure 2 20 shows the connections between the DDR2 SO DIMM Standard 3 0 V or LVDS 3 0 V 3 0 V or LVDS 3 0 V 3 0 V 3 0 V 3 0 V Stratix IV GX Pin Number PIN AF6 PIN AU9 PIN 5 PIN AR8 PIN AN9 PIN AP9 PIN AV5 socket and Stratix IV GX device The pin assignments are listed in Table 2 15 and Table 2 16 Terasic DE4 User M
55. 1000 PCS 101005 000b Ethernet Interface Use internal FIFO Number of ports 1 Info is automatically selected in 00 1000 Mb Ethernet with 1 000BSsE x GMI PCS core Figure 5 32 SGMIl interface MAC Configuration In the Mac Options section the Ethernet MAC Options can be equipped selectively according to the users the MDIO module that controls the PHY Management Module is included associated with the MAC block as shown Figure 5 33 The host Clock divisor is to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100 MHz and the desired MDC clock frequency is 2 5 MHZ so a host clock divisor of 40 should be use 142 Terasic DE4 User Manual www terasic com www terasic com Triple Speed Ethernet mac Triple Speed Ethernet Parameter Settings Core Configuration Options P FIFO Options PCS SGMII Options Ethernet MAC Options Enable 10700 half duplex support _ Enable local loopback MILCGMILRGMII Enable supplemental MAC unicast addresses Include statistics counters Enable 64 bit statistics byte counters Include multicast hashtable Align packet headers to 32 bit boundary Enable full duplex flow control Enable detection Enable magic packet detection Module Include MOM module
56. 17 M1 DDR2 DQ36 DDR Data 36 SSTL 18 Class PIN AG16 M1 DDR2 DQ33 DDR Data 33 SSTL 18 Class PIN 17 M1 0082 0037 DDR Data 37 SSTL 18 Class PIN AH17 M1 0082 DQS n4 DDR2 Data Strobe 4 on 1 8 V SSTL BN AL16 M1 DDR2 DM4 DDR2 Data Mask 4 SSTL 18 Class PIN AL17 M1 DDR2 DQS DDR2 Data Strobe p 4 ii ia 1 8 SSTL BN M1 DDR2 DQ38 DDR Data 38 SSTL 18 Class AF17 M1 DDR2 DQ34 DDR Data 34 SSTL 18 Class PIN AH16 M1 DDR2 DQ39 DDR Data 39 SSTL 18 Class AE17 M1 DDR2 DQ35 DDR Data 35 SSTL 18 Class PIN AJ16 M1 DDR2 0044 DDR Data 44 SSTL 18 Class PIN AN17 M1 DDR2 0040 DDR Data 40 SSTL 18 Class PIN AR17 M1 DDR2 DQ45 DDR Data 45 SSTL 18 Class PIN AP17 M1 DDR2 0041 DDR Data 41 SSTL 18 Class PIN AN16 M1 0082 005 n5 DDR2 Data Strobe n 5 Perea Sali Class 43 Terasic DE4 User Manual rasic com www terasic com 1 0082 DM5 M1 DDR2 DQS p5 1 0082 0042 1 0082 0046 1 0082 0043 1 0082 0047 M1 0082 0048 1 0082 0052 M1 0082 0049 M1 0082 0053 M1 0062 CLK 1 DDR2 CLK n1 M1 0082 005 n6 M1 DDR2 005 M1 DDR2 DM6 M1 DDR2 DQ50 M1 DDR2 DQ54 M1 DDR2 DQ51 M1 DDR2 DQ55 M1 DDR2 DQ56 M1 DDR2 DQ60 M1 DDR2 DQ57 M1 DDR2 0061 M1 DDR2 DM7 M1 DDR2 008 n7 M1 DDR2 095 p7 M1 0082 DQ58 1 0082 DQ59 1 DDR2 0062 M1 DDR2 DQ63 M1 DDR2 SDA M1 DDR2 SCL M1 DDR2 SAO M1 DDR2 SA1 DDR2 Data Mask 5 DDR2 Data Strobe p 5 DDR
57. 3 FSM A10 Address bus 2 5 V PIN F34 FSM A11 Address bus 2 5 V PIN G35 FSM A12 Address bus 2 5 V PIN E34 FSM A13 Address bus 2 5 V PIN J32 FSM A14 Address bus 2 5 V PIN F35 FSM A15 Address bus 2 5 V PIN C24 FSM A16 Address bus 2 5 V PIN A24 FSM A17 Address bus 2 5 V PIN D23 FSM A18 Address bus 2 5 V PIN D24 FSM A19 Address bus 2 5 V PIN T27 FSM A20 Address bus 2 5 V PIN T28 FSM DO Data bus 2 5 V PIN K29 FSM D1 Data bus 2 5 V PIN J30 FSM D2 Data bus 2 5 V PIN K30 FSM D3 Data bus 2 5 V PIN L29 FSM D4 Data bus 2 5 V PIN K31 FSM D5 Data bus 2 5 V PIN E32 FSM D6 Data bus 2 5 V PIN F32 FSM 07 Data bus 2 5 V PIN H32 FSM D8 Data bus 2 5 V PIN B32 FSM D9 Data bus 2 5 V PIN C32 FSM D10 Data bus 2 5 V PIN C35 FSM D11 Data bus 2 5 V PIN D35 FSM D12 Data bus 2 5 V PIN M22 FSM D13 Data bus 2 5 V PIN M28 FSM D14 Data bus 2 5 V PIN C31 FSM D15 Data bus 2 5 V PIN D31 SSRAM CLK Clock 2 5 V PIN M31 SSRAM BWA n Synchronous Byte lane A Write Input 2 5 V PIN R27 SSRAM BWB n Synchronous Byte lane B Write Input 2 5 V PIN N31 SSRAM OE n Output enable 2 5 V PIN H34 SSRAM WE n Write enable 2 5 V PIN 131 67 Terasic DE4 User Manual rasic com www terasic com SSRAM CKE n Clock enable 2 5 V PIN N28 SSRAM CE n Synchronous Chip enable 2 5 V PIN R28 SSRAM ADV Address valid 2 5 V PIN H35 SSRAM MODE Mode SSRAM CE2 Synchronous Chip enable SSRAM CE2 n Synchronous Chip enable SSRAM ZZ Sleep 2 17 I2C Serial EEPROM A 24LC02B Microchip 2kbit Elect
58. 3 LED2 D4 LED3 D5 LED4 D6 LED5 D7 LED6 D8 LED7 Description User Defined LEDs Driving a logic 0 on the I O port turns the LED ON Driving a logic 1 on the I O port turns the LED OFF B 7 Segment Displays The DE4 board has two 7 segment displays As indicated in the schematic in Figure 2 10 the seven segments are connected to pins of the Stratix IV GX FPGA Applying a low or high logic level to a segment to light it up or turns it off Each segment in a display is identified by an index listed from O to 6 with the positions given in Figure 2 11 In addition the decimal point is identified as DP Table 2 8 shows the mapping of the FPGA pin assignments to the 7 segment displays 23 Terasic DE4 User Manual www terasic com VO Stratix IV GX Standard Pin Number 2 5 V 2 5 V 2 5 V 2 5 V 2 5 V 2 5 V 2 5 V 2 5 V PIN V28 PIN W28 PIN R29 PIN P29 PIN N29 PIN M29 PIN M30 PIN N30 www terasic com AAU S RS AN CStratx IV HEX1 VCC2P5 CA1 i gt 2 7 Segment Display mE m gt lt VCC2P5 2 gt 7 Segment Display Figure 2 10 Connection between 7 segment displays and Stratix IV GX FPGA Figure 2 11 Position and index of each segment in a 7 segment display Table 2 8 7 Segment Display Pin Assignments Schematic Signal Names and Functions Schematic Board E VO Stratix IV GX Signal Description Reference Standa
59. 4 95 2622 Erasing Figure 2 7 Erasing flash Programming flash Nios EDS 9 1 5 Info Altera or its authorized distributors Please refer to the Info applicable agreement for further details Info Processing started Fri Jun 11 16 56 38 2618 Info Command quartus_pgm c lUSB Blaster UZsB H l m jtag o pide4_board_update_p ortal sof Using programming cable lSB Blaster 058 01 Started Programmer operation at Fri Jun 11 16 58 43 2010 Configuring device index 1 Device 1 contains JTAG ID code 2407010 Configuration succeeded 1 devicets configured Successfully performed operationts Ended Programmer operation at Fri Jun 11 16 51 85 26180 Info Quartus II Programmer was successful errors warnings Info Peak virtual memory 287 megabytes Info Processing ended Fri Jun 11 16 51 05 2618 Info Elapsed time 35 Info Total CPU time Con all processors 99 98 12 Program flash please wait a few minutes Using cable USE Blaster 058 01 device 1 instance 4x8 Resetting and pausing target processor OK Checksummed read 1B86kB in 41 95 Erased 11648kB 86 75 134 5 36 gt Programming Figure 2 8 Programming flash 18 Terasic DE4 User Manual www terasic com 6 Programming complete Nios EDS 9 1 Program Flash please wait a few minutes Using cable USH Blaster device Resetting and pausing t
60. 4 Display progress and result information for the DDR2 demonstration 131 DE4 User Manual www terasic com 5 6 External Clock Generator The External Clock Generator provides designers using the 3 programmable clock geneators via Texas Instruments chips CDCM61001 RHBT x 2 CDCM61004RHBT the ability to specify clock frequency individually in addition addressing the input reference clock for the Stratix IV GX transceivers The programmable clock is controlled by a control bus connected to the MAX II EPM2210 device This can reduce the Stratix IV GX I O usage while enabling greater functionality on the FPGA device The MAX II 2210 device 15 capable of storing the last entered clock settings at which in the event the board restarts the last known clock settings are fully restored In this demonstration we illustrate how to utilize the clock generators IP to define the clock output using the serial bus The programmable clock output generates clock frequencies of 62 5 75 100 125 150 156 25 187 5 200 250 312 5 and 625 for these clock signals REFCLK PLL CLKIN CDC61004RHBT REFCLK CDCM61101 01 REFCLK CDCM61101 02 Clock signals SATA REFCLK CLKIN are derived from the same programmable clock generator CDCM61004RHBT Users designing SATA applications must use a 100MHz reference clock on the SATA REFCLK signal which would lead to the same clock freque
61. Address 9 1 8 V PIN K28 49 Terasic DE4 User Manual www terasic com www terasic com OTG A10 OTG A11 OTG A12 OTG A13 OTG A14 OTG A15 OTG A16 OTG A17 OTG DO OTG D1 OTG D2 OTG D3 OTG 04 OTG D5 OTG D6 OTG D7 OTG D8 OTG D9 OTG D10 OTG D11 OTG D12 OTG D13 OTG D14 OTG D15 OTG D16 OTG D17 OTG D18 OTG D19 OTG D20 021 022 023 024 025 026 027 028 029 030 031 OTG CS n OTG WE n OTG OE n OTG HC IRQ OTG Address 10 OTG Address 11 OTG Address 12 OTG Address 13 OTG Address 14 OTG Address 15 OTG Address 16 OTG Address 17 OTG Data 0 OTG Data 1 OTG Data 2 OTG Data 3 OTG Data 4 OTG Data 5 OTG Data 6 OTG Data 7 OTG Data 8 OTG Data 9 OTG Data 10 OTG Data 11 OTG Data 12 OTG Data 13 OTG Data 14 OTG Data 15 OTG Data 16 OTG Data 17 OTG Data 18 OTG Data 19 OTG Data 20 OTG Data 21 OTG Data 22 OTG Data 23 OTG Data 24 OTG Data 25 OTG Data 26 OTG Data 27 OTG Data 28 OTG Data 29 OTG Data 30 OTG Data 31 OTG Chip Select OTG Write Enable OTG Output Enable OTG Host Controller IRQ 50 Terasic DE4 User Manual rasic com 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1 8 V 1
62. BUTTON 0 m Register Address 00 BUTTON 1 Register Value BUTTON 2 2 00 BUTTON 3 LES Read Read Status Set LED Write Memory Mapped Write and Read FIFO Write and Read www terasic PCIE Board Connected Figure 6 12 e sure the Selected FPGA Board appear as the target board VID 1172 DID E001 e Press ButtonO 3 in DEA and click the Read Status in this application software Check Uncheck the LEDO 3 in this application software then click Set LED The LED in the DE4 will change e Click Memory Mapped Write and Read to test memory mapped DMA A report dialog will appear when the DMA process is completed e Click FIFO Write and Read to test FIFO DMA A report dialog box will appear when DMA process is completed e The Custom Registers Group is used to test custom design register on the FPGA side Users can use this function to verify custom register design B Demonstration Setup e Quartus II 9 1 SP2 e Borland C Builder 169 Terasic DE4 User Manual www terasic com w rasic com ANU S RYA B Demonstration Source Code Location e Quartus Project PCIE Fundamental e Borland C Project PCIE FundamentalMpc B FPGA Application Design The PCI Express demonstration uses the basic I O interface and DMA channel on the Terasic PCIe IP to control I O Button LED and access
63. CLK p MCB transceiver LVDS PIN AA2 reference clock input HsMB REFCLK SMCPB transceiver LVDS PIN AA1 reference clock input 2 11 Express The DE4 development board is designed to fit entirely into a PC motherboard with x8 or x16 PCI Express slot Utilizing built in transceivers on a Stratix IV device it 15 able to provide a fully integrated PCI Express compliant solution for multi lane 1 4 and x8 applications With the PCI Express hard IP block incorporated in the Stratix IV GX device it will allow users to implement simple and fast protocol as well as saving logic resources for logic application Figure 2 24 presents the pin connection established between the Stratix IV GX and PCI Express The PCI Express interface supports complete PCI Express Genl at 2 5Gbps lane and Gen2 at 5 0Gbps lane protocol stack solution compliant to PCI Express base specification 2 0 that includes PHY MAC Data Link and transaction layer circuitry embedded in PCI Express hard IP blocks The power of the board can be sourced entirely from the PCI Express edge connector when installed into a PC motherboard An optional PCIe external power source can be connected if larger power 15 required on the DEA It is recommended that users connect the PCIe external power connector to the DE4 when either the HSMC or GPIO interface is occupied by a daughter card The PCIE REFCLK P signal 15 a differential input that 15 driven from the PC motherboard on th
64. Class PIN A28 M2 DDR2 DM7 DDR2 Data Mask 7 SSTL 18 Class PIN C30 M2 0082 005 n7 DDR2 Data Strobe n 7 aoe 1 8 V SSTL Bos Differential 1 8 V SSTL M2 DDR2 DQS DDR2 Data Strobe 7 2 8 55 M2 DDR2 DQ58 DDR Data 58 SSTL 18 Class PIN C27 M2 DDR2 DQ59 DDR Data 59 SSTL 18 Class PIN D27 M2 0082 0062 DDR Data 62 SSTL 18 Class PIN B29 M2 0082 0063 DDR Data 63 SSTL 18 Class PIN B31 M2 DDR2 SDA DDR2 I2C Data 1 8 V PIN 15 M2 DDR2 SCL DDR2 I2C Clock 1 8 V PIN K15 M2 DDR2 SAO PONE Presence detect address 1 8 V PIN_A18 input 0 M2 DDR2 SA1 NS PIN B19 The DEA board provides both USB host and device interfaces using Philips ISP1761 single chip Hi Speed Universal Serial Bus USB On The Go Controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at high speed 480 Mbit s full speed 12 Mbit s and low speed 1 5 Mbit s Figure 2 21 shows the connection between the USB and Stratix IV GX device The ISP1761 has three USB ports Port 1 can be configured as a downstream port an upstream port or an OTG port ports 2 and 3 are always configured as downstream ports If the port 1 15 configured as an port users can use SW4 to specify host or peripheral role as listed in Table 2 17 The pin assignments for the associated interface are listed in Table 2 18 48 Terasic DE4 User Manual www terasic com www te
65. DI 1 0 ex Kea X DON T CARE SLEEP DATA INPUT OUTPUT CONVERSION Figure 5 30 SPI input output data timing The FPGA can be used to configure the desired conversion channel of the next transmission by serializing an 8 bit configure data to ADC through the SDI signal In this demonstration SGL is set to zero to specify differential conversion and ODD SIGN is set to zero to specify IN as EVEN channel The FPGA retrieves the conversion result from the serialized data through the SDO pin Note the conversion data is for the target channel specified by previous configuration When ADC is powered on the default selection used for the first conversion is IN IN Address 00000 B Design Tools e Quartus II NIOS II IDE B Demonstration Source Code e Project directory 4 PowerMeasure e Bit stream used DE4 PowerMeasure sof NIOS II Workspace DE4_PowerMeasure Software 139 Terasic DE4 User Manual www terasic com www terasic com B Nios IL Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean B Demonstration Batch File Demo Batch File Folder 4 PowerMeasure Demo_ Batch The demo batch file includes following files e Batch File test bat test bashrc FPGA Configure File 4 PowerMeasure sof NIOS II Program DE4_P
66. DR2 Data Strobe n 3 1 8 V SSTL F18 M2 DDR2 008 DDR2 Data Strobe p 3 ar 18 VSSTL M2 DDR2 DQ26 DDR Data 26 SSTL 18 Class PIN F19 M2 0082 0030 DDR Data 30 SSTL 18 Class F20 M2 0082 0027 DDR Data 27 SSTL 18 Class PIN G19 M2 DDR2 0031 DDR Data 31 SSTL 18 Class PIN G20 M2 DDR2 CKEO Clock Enable pin 0 for DDR2 SSTL 18 Class PIN 011 M2 DDR2 CKE 1 Clock Enable pin 1 for DDR2 SSTL 18 Class PIN K12 M2 DDR2 A15 DDR2 Address 15 SSTL 18 Class PIN M13 M2 DDR2 BA2 DDR2 Bank Address 2 SSTL 18 Class PIN B10 M2 DDR2 A14 DDR2 Address 14 SSTL 18 Class PIN K14 M2 DDR2 A12 DDR2 Address 12 SSTL 18 Class PIN N15 M2 DDR2 A11 DDR2 Address 11 SSTL 18 Class PIN L14 M2 DDR2 A9 DDR2 Address 9 SSTL 18 Class PIN M14 M2 DDR2 A7 DDR2 Address 7 SSTL 18 Class PIN N13 M2 0082 8 DDR2 Address 8 SSTL 18 Class PIN A10 M2 DDR2 A6 DDR2 Address 6 SSTL 18 Class PIN A11 M2 DDR2 5 DDR2 Address 5 SSTL 18 Class PIN C11 M2 DDR2 A4 DDR2 Address 4 SSTL 18 Class PIN C13 M2 DDR2 A3 DDR2 Address 3 SSTL 18 Class PIN R14 M2 DDR2 A2 DDR2 Address 2 SSTL 18 Class PIN 014 M2 DDR2 A1 DDR2 Address 1 SSTL 18 Class PIN B11 M2 DDR2 0 DDR2 Address 0 SSTL 18 Class PIN B14 M2 DDR2 A10 DDR2 Address 10 SSTL 18 Class PIN R18 M2 DDR2 BA1 DDR2 Bank Address 1 SSTL 18 Class PIN C14 M2 DDR2 BAO DDR2 Bank Address 0 SSTL 18 Class PIN C12 M2 DDR2 RAS n DDR2 Row Address Strobe SSTL 18 Class
67. E4 User Manual www terasic com www terasic com USB Host Slave controller Complies fully with Universal Serial Bus Specification Rev 2 0 e Support data transfer at high speed full speed and low speed e Support both USB host and device e Three USB ports one type mini AB for host device and two type A for host e Support Nios II with the Terasic driver Power Standalone DC inputs 12V and 3 3V e PCI Express edge connector power e Optional PCI Express external power source On Board power measurement circuitry 12 Terasic DE4 User Manual www terasic com www terasic com Chapter 2 Using the DE4 Board This chapter gives instructions for using the DEA board and its components It is strongly recommended that users read the 4 Getting Started Guide pdf before using the DEA board The document is located in the Usermanual folder on the DE4 System CD The contents of the document include the following e Introduction to the DEA development board DE4 development kit contents e Key features e Before you begin e Software Installation e Development board setup e Programming the Stratix IV GX device on the DEA board Programming through the Flash memory device 2 1 Configuration Options B JTAG FPGA Programming over USB Blaster The USB blaster 15 implemented on the DE4 board to provide JTAG configuration through onboard USB to JTAG configuration logic using a type B USB connector a FTDI USB 2
68. EA using Quartus II Programmer e Restart Windows e Installed PCIe driver if necessary The driver is located in the folder PCle_SDK Driver e Launch demo program Image Demo exe 173 Terasic DE4 User Manual www terasic com www terasic com Terasic DE4 Image Demo V1 0 ter WWW Cerasic com Download Image Process Image Upload Image Exit FPGA baord is connected 00000000 Click Select Image to select a bitmap or jpeg file for image processing Terasic DE4 PCIe Image Demo V1 0 ter Terasic com Download Image Process Image Upload Image Exit FPGA baord is connected 00000000 Click Download Image to download image raw data into the local memory of FPGA Click Process Image to trigger invert image process Click Upload Image to upload image to PC from local memory of FPGA to be displayed on the window demo application Terasic DE4 PCIe Image Demo 1 0 ter WWW Select Image Download Image Frocess Image 174 Terasic DE4 User Manual www terasic com www terasic com B Design Tools e Quartus II 9 1 SP2 Borland C Builder B Demonstration Source Code Location e Quartus Project PCIE ImageProcess Borland C Project PCIE ImageProcessNpc B FPGA Application Design This demonstration uses the DMA channel of PCIe IP to download upload the image int
69. Express Control DIP switch is provided to enable or disable different configurations of the PCIe Connector Table 2 2 lists the switch controls and description Table 2 2 SW9 PCIe Control DIP Switch Board Reference Signal Name Description Default On Enable x1 presence detect W9 1 PCIE PRSNT2n x1 ff iii Disable x1 presence detect On Enable x4 presence detect IE PRSNT2n x4 ff dibus didi ds Disable x4 presence detect 3 SW9 3 PCIE PRSNT2n x8 On Enable x8 presence detect Off Disable x8 presence detect 2 3 Status Elements The DEA development board includes status LEDs Please refer to Table 2 3 for the status of the LED indicator Table 2 3 LED Indicators Board Reference LED Name Description D9 12 V Power Illuminates when 12 V power is active D10 3 3 V Power illuminates when 3 3 V power is active 5 when FPGA is successfully configured Driven D20 CONF DONE by the MAX II CPLD EPM2210 System Controller Illuminates when the MAX CPLD EPM2210 System Controller is actively configuring the FPGA Driven by the MAX II CPLD D18 Loading EPM2210 System Controller with the Embedded Blaster CPLD Illuminates when the MAX II CPLD EPM2210 System Controller D19 E fails to configure the FPGA Driven by the MAX Il CPLD ibd EPM2210 System Controller USB when USB blaster circuit transmits or receives data D12 Blaster Circuit 20 Terasic DE4 Use
70. L 15 HSMB GXB TX 4 Transceiver TX bit4n __ 14 VPCML 16 5 GXB 4 TransceiverRXbit n 14 VPCML PINNI _ 17 7 HSMB GXB TX p3 Transceiver TXbit3 14 VPCML 18 5 GXB Transceiver RX bit3 14 VPCML 2 19 7 HSMB GXB TX 3 Transceiver TX bit3n 14 VPCML 20 GXB 3 Transceiver RXbit3n __ 14 VPCML 21 1 HSMB GXB TX p2 Transceiver TXbit2 14 VPCML PIN TA _ 22 GXB p2 Transceiver RXbit2 14 VPCML PINU2 23 5 GXB TX 2 Transceiver TX bit2n 14 VPCML 73 24 GXB 2 Transceiver RXbit2n 14VPCML PINUI 25 GXB TX p1 Transceiver TX bit 1 4 VPCML ABA 30 te asic Terasic DE4 User Manual www terasic com 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 47 48 49 50 5 54 55 56 59 60 61 62 65 66 67 68 71 72 73 74 77 78 79 80 83 Terasic DE4 User Manual rasic com HSMB GXB RX HSMB GXB TX HSMB GXB RX ni HSMB GXB TX HSMB GXB RX HSMB GXB TX nO HSMB GXB RX nO E HSMC SDA E HSMC SCL HSMC TCK HSMC TMS HSMB TDO HSMC TDI HSMB OUTO HSMB CLKINO HSMB DO HSMB 01 HSMB D2 HSMB D3 HSMB TX HSMB HSMB TX HSMB RX nO HSMB TX HSMB HSMB TX n1 HSMB RX n1 HSMB TX p2 HSMB RX p2 HSMB TX n2 HSMB
71. LL CTRL controller is able to control the Max II device by specifying the desire clock outputs set by the user By changing IP parameters of the Terasic EXT IP the external clock ouput frequency can be adjusted accordingly Table 5 1 lists the EXT instruction ports EXT PLL CTRL MAXI GENES SEINE AS set wr clk3_ od _ 5 clk3 ce clk2 clk2 set rd set wr sclk MAX SCLK max sclk 2 os E 2 os 14 4 max_sdat 2 2 pr 2 os 2 05 clk2 2 5 osc 50 gt 05 50 gt Eu Figure 5 26 EXT PLL CTRL Instruction Hardware Ports Table5 1 EXT PLL CTRL instruction ports input System Clock 50MHz Synchronous Reset 0 Module Reset 1 Normal m tm Output Frequency Value s s Back Output Frequency Value input to Transfer Serial Data postive edge Start to Read Serial Data postive edge Serial Data Transmission is Complete 0 Transmission in output 1 Transmission Complete output Serial Clock to MAX II Serial Sata to from MAX II 134 Terasic DE4 User Manual www terasic com B The EXT PLL CTRL IP Parameter Setting Users can refer to the following Table 5 2 to set the external clock generator for the output
72. LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V G5 PIN P13 PIN F5 PIN H7 PIN G6 PIN G7 PIN F6 PIN K8 PIN W34 PIN J8 PIN W35 PIN M10 PIN F7 PIN L10 PIN E7 PIN M8 PIN G8 PIN M7 PIN F8 PIN M11 PIN G9 PIN L11 PIN F9 PIN N9 PIN N6 PIN P8 PIN N5 PIN R9 PIN M6 PIN R8 PIN L5 PIN U10 PIN R6 PIN T9 PIN R5 PIN V10 PIN R7 PIN V9 PIN P6 PIN T10 PIN V6 PIN R10 www terasic com 146 HSMB 15 LVDS RX 15n CMOS LVDS or 2 5 V 05 149 HSMB TX 16 LVDS TX bit 16 or CMOSI O LVDS or 2 5 PIN V12 150 HSMB RX p16 LVDS RX bit 16 or LVDS 2 5 V W8 151 HSMB TX n16 LVDS TX bit 16n or CMOS LVDS 2 5 V V11 152 HSMB 16 LVDS 16n or CMOS I O LVDS 2 5 V PIN W7 155 HSMB CLKOUT p2 LVDS 2 5 V PIN W12 differential clock input output 156 HSMB CLKIN p2 LVDS or 2 5 V PIN W6 differential clock input 157 HSMB CLKOUT n2 UA LVDS or 2 5 V PIN W11 differential clock in
73. LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V PIN AC2 PIN AB3 PIN AC1 PIN 04 PIN AE2 PIN AD3 PIN AE1 PIN M19 PIN L19 PIN L8 PIN 5 PIN H10 PIN D6 PIN G10 PIN C6 PIN K9 PIN D5 PIN J9 PIN C5 PIN K10 PIN D10 PIN J10 PIN C10 PIN N11 PIN D9 PIN N10 PIN C9 PIN N12 PIN D8 PIN M12 PIN C8 PIN R12 PIN D7 PIN R11 PIN C7 PIN T13 PIN F10 PIN T12 PIN E10 PIN R13 www terasic com 84 85 86 89 90 91 92 95 96 97 98 101 102 103 104 107 108 109 110 113 114 115 116 119 120 121 122 125 126 127 128 131 132 133 134 137 138 139 140 143 144 145 HSMB HSMB TX n6 HSMB RX n6 HSMB TX p7 HSMB RX p7 HSMB TX n7 HSMB RX n7 HSMB OUT HSMB CLKIN p1 HSMB OUT n1 HSMB CLKIN n1 HSMB TX p8 HSMB p8 HSMB TX n8 HSMB RX n8 HSMB TX p9 HSMB p9 HSMB TX n9 HSMB RX n9 HSMB TX p10 HSMB p10 HSMB TX n10 HSMB RX n10 HSMB TX p11 HSMB 11 HSMB n11 HSMB 11 HSMB TX p12 HSMB 12 HSMB TX 12 HSMB 12 HSMB p13 HSMB 13 HSMB TX 13 HSMB RX n13 HSMB TX 14 HSMB 14 HSMB TX
74. NO High Logic Level when button not 3 0 V PIN AH5 pressed PB2 BUTTON1 High Logic Level when button not 3 0 V PIN AG5 pressed PB3 BUTTON2 High Logic Level when button not 3 0 V PIN AG7 pressed PBA BUTTON3 High Logic Level when button not 3 0 V PIN pressed PB5 CPU RESET n FPGA reset 2 5 V PIN V34 PB6 CONFIGn Max Il EPM2210 System re configuration Terasic DE4 User Manual www terasic com 21 www terasic com A CPU reset push button CPU RESET n 15 an input to the Stratix IV GX device It 15 intended to be the master reset signal for FPGA designs loaded into the Stratix IV device The CONFIGn push button is used to force a reboot the MAX II EPM2210 CPLD device B Slide Switches and DIP Switch There are also four slide switches and one 8 position DIP switch on DE4 board to provide additional FPGA input control Each switch is connected directly to a pin of Stratix IV FPGA When a slide switch is in the DOWN position or the UPPER position it provides a low logic level or a high logic level to the FPGA respectively For 8 position DIP switch when a switch is in the DOWN position or the UPPER position it provides a high logic level or a low logic level to the FPGA Table 2 5 and Table 2 6 lists the signal names and their corresponding Stratix IV GX device pin numbers for slide switches and DIP switch respectively Table 2 5 Slide Switches Pin Assignments Schematic Signal Names and
75. O LVDS TX bit 13n or CMOS I O LVDS RX bit 13n or CMOS I O LVDS TX bit 14 or CMOS I O LVDS bit 14 or CMOS I O LVDS TX bit 14n or CMOS I O LVDS RX bit 14n or CMOS I O LVDS TX bit 15 CMOS 35 Terasic DE4 User Manual LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V PIN AM35 PIN AG31 PIN AM31 PIN AG32 PIN AN31 PIN AG29 PIN AN33 PIN AH29 PIN AP34 PIN 28 PIN AB34 PIN AH28 PIN AA35 PIN AC28 PIN AP32 PIN AC29 PIN AR32 PIN AJ29 PIN AR31 PIN AK29 PIN AT30 PIN AD30 PIN AT33 PIN AD31 PIN AU33 PIN AK32 PIN AU34 PIN AL32 PIN AV34 27 32 27 AU32 AK31 AT31 AL31 AU31 AJ31 AP35 AH30 AR35 129 www terasic com 144 145 146 149 150 151 152 155 156 157 158 HSMA 15 HSMA TX 15 HSMA RX n15 HSMA TX p16
76. Oct 22 92 82 11 PDT 2909 Example designs can be found in cugdrive c altera i nios2zeds examples You may add a startup script c altera 9i niosZzeds user hashrc gt Using cable UZB Blaster 058 01 device instance Resetting and pausing target processor OK Initializing CPU cache Cif present Downloaded 98 1 75 57 6KB s gt Uerified Starting processor at address 1 12 1 nios2 terminal connected to hardware target using JIAG UART on cable nios2 terminal USH Blaster USB 1 device instance nios2 terminal Use the IDE stop button or Ctrl C to terminate DE4 ISPi761 USB Host Demo 93 11 2010 insert USB Storage or and HID 5 attach at port 2 Speed Low Speed 05 LAPP 2 y H Left Button Pressed Figure 5 6 Display device information 5 2 USB Device Most USB applications and products operate as USB devices rather than USB hosts This demonstration will show how the DE4 board is operated as a USB device by connecting it to a host 111 Terasic DE4 User Manual www terasic com www Lterasic com ANU S RYAN computer In this demonstration the USB port 1 mini AB port on the DE4 is configured as a device port to connect with a host computer The NIOS II processor communicates with host computer through USB Bulk Transfer w
77. PIN AG30 PIN V29 PIN M32 PIN L32 PIN K34 PIN K35 PIN K6 PIN K5 PIN AE30 PIN V29 PIN P31 PIN P32 PIN J34 PIN J35 PIN N7 PIN N8 PIN AE31 PIN V29 www terasic com ANU RYAN 2 13 Serial ATA SATA Four Serial ATA SATA ports available on the DEA development board which are computer bus standard with the primary function of transferring data between the motherboard and mass storage devices such as hard drives optical drives and solid state disks Supporting a storage interface 1s just one of many different applications an FPGA can be used in storage appliances The Stratix IV GX device can bridge different protocols such as bridging simple bus I Os like PCI Express PCIe to SATA or network interfaces such as Gigabit Ethernet GbE to SATA The SATA interface supports SATA 3 0 standard with connection speed of 6 Gbps based on Stratix IV GX device with integrated transceivers compliant to SATA electrical standards The four Serial ATA SATA ports include two available ports for device and two available ports for host capable of implementing SATA solution with a design that consists of both host and target device side functions Figure 2 27 depicts the host and device design examples Stratx IV Figure 2 27 PC and storage device connection to the Stratix IV GX FPGA 62 www terasic com The transmitter and receiver signals of the SATA ports are connected directly to the Stratix IV GX transc
78. PIN AV13 PIN AU14 PIN AT14 PIN AU11 PIN AU12 PIN AT12 PIN AP13 PIN AR14 PIN AN14 PIN AP14 PIN AN13 PIN AT13 PIN AR13 PIN AL15 PIN AM14 PIN AL14 PIN AL13 PIN AG24 PIN AH24 PIN AV25 PIN AW25 www terasic com Table 2 16 DDR2 SO DIMM 2 Pin Assignments Schematic Signal Names and Functions Stratix IV GX Pin Schematic Signal Name M2 DDR2 004 M2 DDR2 DQO M2 DDR2 DQ5 M2 DDR2 091 M2 DDR2 DMO M2 DDR2 095 M2 DDR2 095 M2 DDR2 006 M2 0082 007 M2 0082 002 M2 DDR2 M2 0082 0012 M2 0082 0013 M2 DDR2 M2 DDR2 009 M2 DDR2 DM1 M2 DDR2 DQS n1 M2 DDR2 CLK pO M2 DDR2 DQS M2 DDR2 CLK n0 M2 DDR2 0010 M2 DDR2 DQ14 M2 DDR2 DQ11 M2 0082 DQ15 M2 0082 0016 M2 0082 0020 M2 0082 0017 M2 DDR2 0021 M2 DDR2 DOS n2 M2 DDR2 DQS p2 M2 DDR2 DM2 M2 DDR2 DQ18 M2 DDR2 0022 Description DDR Data 4 DDR Data 0 DDR Data 5 DDR Data 1 DDR2 Data Mask 0 DDR2 Data Strobe n 0 DDR2 Data Strobe p 0 DDR Data 6 DDR Data 7 DDR Data 2 DDR Data 3 DDR Data 12 DDR Data 13 DDR Data 8 DDR Data 9 DDR2 Data Mask 1 DDR2 Data Strobe n 1 Clock p0 for DDR2 DDR2 Data Strobe p 1 Clock nO for DDR2 DDR Data 10 DDR Data 14 DDR Data 11 DDR Data 15 DDR Data 16 DDR Data 20 DDR Data 17 DDR Data 21 DDR2 Data Strobe n 2 DDR2 Data Strobe p 2 DDR2 Data Mask 2 DDR Data 18 DDR Data 22 Te
79. Project Name Select the target board type and input project name as show in Figure 4 3 e Board Type Select the appropriate FPGA device according to the DEA board which includes the EPASGX230 and EP4SGX530 devices e Project Name Specify the project name as it is automatically assigned to the name of the top level design entity www terasic com Terasic DE4 User Manual 93 www terasic com Terasic DEA System Builder V 1 0 0 System Confiquration NB SRYA asic UNIVERSITY Board 4 230 PROGRAM www terasic com Project Name 4 CLOCK Slide Switch x 4 LED x 8 7 Segement x 2 Button x 4 DIP Switch x 8 Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM MISSRAM 2MB RS 232 Programmable PLL Programmable PLL Ethernet x 4 HSMA REFCLK O DDR2 SODIMM_1 CO DDR SODIMM 2 O Sata Host 0 O Sata Host 1 O Sata Device 0 O Sata Device 1 PLL_CLKIN SATA_REFCLK Fl PCIe 5 REFCLK GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 D5M 5M Pixel Camera High Speed Prefix Name Prefix Name GPIO 1 Header HSMC B Transceiver x 8 4 3 LCD and Touch aay DVI FullHD TXIRX v Prefix Name Prefix Name Default Setting Load Setting Save Setting Figure 4 3 The 4 Board Type and Project Name
80. RX n2 HSMB TX p3 HSMB HSMB TX n3 HSMB RX n3 HSMB TX p4 HSMB RX p4 HSMB TX n4 HSMB RX n4 HSMB TX p5 HSMB RX p5 HSMB TX n5 HSMB RX n5 HSMB TX p6 Transceiver RX bit 1 Transceiver TX bit 1n Transceiver RX bit 1n Transceiver TX bit 0 Transceiver RX bit 0 Transceiver TX bit On Transceiver RX bit On Management serial data Management serial clock JTAG clock signal JTAG mode select signal JTAG data output JTAG data input CMOS I O Dedicated clock input LVDS TX or CMOS I O LVDS RX CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX bit 0 or CMOS I O LVDS RX bit 0 or CMOS I O LVDS bit On or CMOS I O LVDS RX bit or CMOS I O LVDS TX bit 1 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS TX bit 1n or CMOS LVDS RX bit 1n or CMOS I O LVDS TX bit 2 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS TX bit 2n or CMOS I O LVDS RX bit 2n or CMOS I O LVDS TX bit 3 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS TX bit or CMOS I O LVDS RX bit 3n or CMOS I O LVDS TX bit 4 or CMOS I O LVDS bit 4 or CMOS I O LVDS TX bit 4n or CMOS LVDS RX bit 4n or CMOS I O LVDS TX bit 5 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS TX bit 5n or CMOS I O LVDS RX bit 5n or CMOS I O LVDS TX bit 6 or CMOS I O 3l 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 8 V 1 8 V 2 5 V 2 5 V 2 5 V 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V
81. SS LocalAddress void pData DWORD dwDataSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalAddress Specify the target memory mapped address in FPGA pData 166 Terasic DE4 User Manual www terasic com rasic com A pointer to a memory buffer to store the data which will be written to FPGA dwDataSize Specify the byte number of data which will be written to FPGA Return Value Return TRUE if write data 1s successful otherwise FALSE 15 returned PCIE DmaFifoRead rototype bool PCIE DmaFifoRead PCIE HANDLE hPCIE PCIE LOCAL FIFO ID LocalFifold void pBuffer DWORD dwBufSize A PCIe handle return by PCIE Open function LocalFifold Specify the target memory fifo ID in FPGA pBufter A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBufSize dwBufsSize Specify the byte number of data retrieved from FPGA Return Value Return TRUE if read data 1s successful otherwise FALSE is returned PCIE DmaFifoWrite unction Write data to the memory fifo of FPGA board in DMA function 167 Terasic DE4 User Manual www terasic com rasic com bool PCIE DmaFifoWrite PCIE HANDLE hPCIE PCIE LOCAL FIFO ID LocalFifold void pData DWORD dwDataSize A PCle handle return by PCIE_Open function LocalFifold Specify the target memory fifo ID in FPGA pData A pointer to a memory buffer to
82. a 52 DDR Data 49 DDR Data 53 Clock p1 for DDR2 Clock n1 for DDR2 DDR2 Data Strobe n 6 DDR2 Data Strobe n 6 DDR2 Data Mask 6 DDR Data 50 DDR Data 54 DDR Data 51 DDR Data 55 DDR Data 56 DDR Data 60 DDR Data 57 Terasic DE4 User Manual rasic com 47 SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class SSTL 18 Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class SSTL 18 Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class PIN R22 PIN M23 PIN P22 PIN K23 PIN P23 PIN L23 PIN M24 PIN K24 PIN J24 PIN J25 PIN G24 PIN G25 PIN F24 PIN C25 PIN E25 PIN B25 PIN F25 PIN A26 PIN D25 PIN C26 PIN D26 PIN F27 PIN H26 PIN G27 PIN J26 PIN B17 PIN A17 PIN D29 PIN E29 PIN D28 PIN F28 PIN E28 PIN H28 PIN G29 PIN C29 PIN A27 PIN A31 www terasic com M2 DDR2 0061 DDR Data 61 SSTL 18
83. and Alert Users can enter the maximum and minimum temperatures for Over temperature or Alert as required Click the Write button to update the values entered as Terasi ter Terasic DE4 User Manual www terasic com NAN WW HL m max Read 125 mas write 1125 25 Read E T hist write PRENNE io v T high Read 100 Thigh write HesMC T law Head T_low o EET ie 5 tad Memory Fan Figure 3 12 Accessing the Temperature Sensor through Control Panel 3 8 Power The Power function 15 designed to monitor the power consumption in real time of various blocks the DE4 board Using the 12 power supply rails on the DEA we are able to sense the on board voltage and current for transceiver power Stratix IV GX power and the I O power Choose the Power tab to reach the window shown in Figure 3 13 which depicts all associated power banks of the DE4 board asic Terasi ter Terasic DE4 User Manual www terasic com Era Temp m PES Seo 0 01 31 4 1 B 02 Memory 14 0 595729 1 072311 0 022451 sv 1 0 4 z 0 001 224 Figure 3 13 Power measurement for associated power banks of the DE4 3 9 PLL The PLL function
84. anel is ready If the connection between DE4 board and USB Blaster is not established or the DE4 board is not powered on before running the DE4 ControlPanel exe the Control Panel will fail to detect FPGA and a warning message window will pop up as shown in Figure 3 3 73 TijasiC Terasic DE4 User Manual www terasic com www terasic com E md dits mx 1 ini TIT b mi o i mmn 1 m b 1 Failed to find Please make sure 1 and PC are connected an USB cable 2 is power Figure 3 3 The DEA Control Panel fails to download sof file The concept of the DE4 Control Panel is illustrated in Figure 3 4 The Control Codes which performs the control functions 15 implemented in FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical users interface is used to issue commands to the control codes It handles all requests and performs data transfer between the computer and the DEA board 74 Terasic DE4 User Manual www terasic com www terasic com DE4 Board DDR2 SO DIMM USB Host Device External Power Monitor Temp Monitor SD CARD LEDs Buttons Switches 7 Seg Figure 3 4 The DE4 Control Panel concept The DE4 Control Panel can
85. anual www terasic com 40 www terasic com DDR2 SO DIMM 1 DDR2 SA 1 0 M1 DDR2 CLK p 1 0 M1 DDR2 CLK n 1 0 M1 DDR2 BA 2 0 M1 DDR2 ODT 1 0 M1 DDR2 CS n 1 0 1 DDR2 00163 0 M1 DDR2 DOS 7 0 M1 DDR2 008 n 7 0 0082 A 15 0 M1 0082 DM 7 0 M1 DDR2 CKE 1 0 M1 DDR2 WE n ANU S RYAN M1 DDR2 CAS n E M1 DDR2 RAS n Strat IV M1_DDR2_SDA DDR2 SCL DDR2 SO DIMM 2 E gt gt M2 DDR2 CLK p 1 0 M2 DDR2 CLK n 1 0 M2_DDR2_ BA 2 0 M1 DDR2 ODT 0 M2 DDR CS n 1 0 M2 DDR2 DQ 63 0 M2 DDR2 005 p 7 0 M2 DDR2 005 n 7 0 M2 DDR2 A 15 0 2 DDR2 DM 7 0 M2 DDR2 CKE 1 0 M2 DDR2 WE n M2 DDR2 CAS n 2 DDR2 RAS n M2 DDR2 SDA M2 DDR2 SCL Figure 2 20 Connection between the DDR2 and Stratix IV GX FPGA Table 2 15 DDR2 SO DIMM 1 Pin Assignments Schematic Signal Names and Functions Schematic Stratix IV GX Pin Description Standard Signal Name M1 DDR2 004 DDR Data 4 SSTL 18 Class M1 DDR2 DQO DDR Data 0 SSTL 18 Class Pawa M1_DDR2_DQ5 DDR Data 5 SSTL 18 Class l PIN_AW33 M1_DDR2_DQ1 DDR Data 1 SSTL 18 Class l PIN_AV31 M1 DDR2 DMO DDR2 Data Mask 0 SSTL 18 Class 1 DDR2 005 DDR2 Data Strobe n 0 5 1 8 V SSTL AW30 1 DDR2 DOS DDR2 Data Strobe p 0 1 8 SSTL AV29 Mi DDR2 _ DDR Data
86. ard Itemlndex WORD VID m szPcieInfo n5e1 VendorID WORD DID m szPcieInfo nsSel DbeviceID HSuccess m hPCIE Openi iVID DID U 0 first matched board where nSel is selected index in the Selected FPGA Board poll down menu Based on the return szPcielInfo we can find the associated PID and DID which can use to specifiy the target PCIe card To read the BUTTON status the function is called m HPCIE Read32 DEMO PCIE USER BAR DEMO PCIE IO ADDR amp dwData To set LED status the function 1s called m hPCIE Read32 DEMO PCIE USER DEMO PCIE IO ADDR amp dwData To write and read memory mapped memory call the functions 171 Terasic DE4 User Manual www terasic com www terasic com ff write bouccess m hPCIE DmaWriteiLocal Lddr pWrite nTest5izel ift ib2uccezss i read bouccess m hPCIE DmaReadiLocal ddr pEead nTestsizel To write and read FIFO memory call the functions ff write bouccess m hPCIE DmaFiroWriteiFifoID pWrite nTestsizel if bSuccess i ff reag bouccess m hPCIE DmaFitfoReadiFifoID pRead 6 5 Example 2 Image Process Application This example shows how to utilize computing power of the FPGA for image processing The application demonstrates the invert image processing by utilizing the FPGA The PC and FPGA source code of the application layer are all available in the DE4 system CD allowing users to easily extent the
87. arget processor OK Checksums took 2 35 Erase not required Programmed 11543KB 443 25 426 HKB zs Device contents checksummed OK Leaving target processor paused Using cable lSB Hlaster 05 0 1 device Resetting and pausing target processor OK Checksums took Erase not required Programmed 1KB lt Deuice contents checksummed OK Leaving target processor paused Press key to continuance instance 4x instance 4x Figure 2 9 Programming flash complete 2 2 Setup Elements B JTAG Control DIP Switch The JTAG control DIP switch is provided to either remove or include devices in the active JTAG chain The JTAG signals TDI found on the HSMC connectors and PCIe interface can be enabled using a 3 position DIP switch In the OFF position the TDI and signals are looped similarly in the ON position the JTAG signals are bypassed Table 2 1 lists the position of the DIP switch and their associated interface Board Reference SWe 1 SW8 2 SW8 3 Table 2 1 SWS8 JTAG Control DIP Switch Description Signal Name JTAG HSMA EN JTAG HSMB EN JTAG PCIE EN Terasic DE4 User Manual rasic com On Off On Off On Off 19 Bypass HSMA HSMA In chain Bypass HSMB HSMB In chain Bypass PCI Express PCI Express In Chain Default On On On www terasic com B PCI Express Control DIP switch The PCI
88. asic DE4 User Manual www terasic com www terasic co m AN DTE RAN Please refer to the DE4 Getting Started Guide pdf for the basic programming instruction on parallel flash loader on the CFI flash memory DE4 Board FPGA il T FLASH Programming FLASH Batch Program Memory Figure 2 2 Flash programming scheme B Programming Flash Memory using batch file The DEA provides a program flash batch file demonstrations de4_ lt Stratix device gt de4_board_ update portaldemo batchMWProgram flash to limit the steps that are taken when users program flash memory on the DEA Software Requirements e Quartus II 9 1 SP2 or later e Nios IL IDE tools 9 1 SP2 or later Program flash folder contents e Program flash bat e Program flash pl e Program flash sh deA board update portal sof Before you use the program flash bat batch file to program the flash memory make sure the DE4 is turned on and USB cable is connected to the USB blaster port J5 In addition place the sof and elf file optional you wish to program convert in the Program flash directory 15 Terasic DE4 User Manual www terasic com www terasic co m I H D AYN n pm Programming Flash Memory with sof using Program flash bat 1 Launch the program flash bat batch file from the directory demonstrations de4_ lt Stratix gt 4 board update batchNProgram f
89. ated documentation or information are expressly subject 8855 Programming ram License Subscription Agreement Altera MegaCore Function License Agreement or other applicable license agreement including Figure 2 6 Loading sof file to be program 17 Terasic DE4 User Manual www terasic com www Lterasic com JAN DTE RYA 6 Erasing flash 7 Nios IT EDS 9 1 Info programming logic devices manufactured Altera and sold hy Info Altera or its authorized distributors Please refer to the Info applicable agreement for further details Info Processing started Fri Jun 11 16 58 38 Info Command quartus_pgm c USBHB Blasterl USB Hl m jtag o pide4_board_update_p ortal sof Using programming cable USB Blaster USB HI Started Programmer operation at Fri Jun 11 16 50 43 2618 Configuring device index 1 Device 1 contains JIAG ID code BHxH24H 7BDD Configuration succeeded 1 deuicetzs configured Successfully performed operationts gt Ended Programmer operation at Fri 11 16 51 85 2010 Quartus II Programmer was successful errors warnings Info Peak virtual memory 287 megabytes Info Processing ended Fri Jun 11 16 51 05 2618 Info Elapsed time 6H 06 35 Info Total CPU time all processors 12 Program Flash please wait a few minutes Using cable US B Blaster 058 01 device 1 instance 44H Resetting and pausing target processor OK Checksummed read
90. atic uu Stratix IV GX Pin Description I O Standard Signal Name Number FSM A1 Address bus 2 5 V PIN G22 FSM A2 Address bus 2 5 V PIN G23 FSM A3 Address bus 2 5 V PIN A25 FSM A4 Address bus 2 5 V PIN H22 FSM A5 Address bus 2 5 V PIN H23 FSM A6 Address bus 2 5 V PIN J22 FSM A7 Address bus 2 5 V PIN K22 FSM A8 Address bus 2 5 V PIN M21 FSM A9 Address bus 2 5 V PIN J23 FSM A10 Address bus 2 5 V PIN F34 FSM A11 Address bus 2 5 V PIN G35 FSM A12 Address bus 2 5 V PIN E34 FSM A13 Address bus 2 5 V PIN J32 FSM A14 Address bus 2 5 V PIN F35 FSM A15 Address bus 2 5 V PIN C24 FSM A16 Address bus 2 5 V PIN A24 FSM A17 Address bus 2 5 V PIN D23 FSM A18 Address bus 2 5 V PIN D24 FSM A19 Address bus 2 5 V PIN T27 FSM A20 Address bus 2 5 V PIN T28 FSM A21 Address bus 2 5 V PIN D22 FSM A22 Address bus 2 5 V PIN E23 FSM A23 Address bus 2 5 V PIN N20 Terasic DE4 User Manual www terasic com 65 www terasic com FSM A24 Address bus 2 5 V PIN P20 FSM A25 Address bus 2 5 V PIN C22 FSM DO Data bus 2 5 V PIN K29 FSM D1 Data bus 2 5 V PIN J30 FSM D2 Data bus 2 5 V PIN K30 FSM D3 Data bus 2 5 V PIN L29 FSM D4 Data bus 2 5 V PIN K31 FSM D5 Data bus 2 5 V PIN E32 FSM D6 Data bus 2 5 V PIN F32 FSM 07 Data bus 2 5 V PIN H32 FSM D8 Data bus 2 5 V PIN B32 FSM D9 Data bus 2 5 V PIN C32 FSM D10 Data bus 2 5 V PIN C35 FSM D11 Data bus 2 5 V PIN D35 FSM D12 Data bus 2 5 V PIN M22 FSM D13 Data bus 2 5 V PIN M28 FSM D14 Data bus 2 5 V PIN C31 FSM D15 Data bu
91. be generated using a PLL If a different DDR2 SODIMM is used the memory parameters should be modified according to the datasheet of the DDR2 SODIMM From the PHY Settings tab both Use differential DQS and Enable dynamic parallel on chip termination items should be selected 129 Terasic DE4 User Manual www terasic com www terasic co m B Design Tools e Quartus NIOS II IDE B Demonstration Source Code e Project directory DE4 DDR2 e Bit stream used DE4_DDR2 sof NIOS II Workspace DDR2NSoftware B Nios IL Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean B Demonstration Batch File Demo Batch File Folder 4 DDR2Ndlemo batchNdiml1 DDR2Ndemo batchNdim2 The demo batch file includes following files e DDR2 SODIMM e Batch File test bat test bashrc FPGA Configure File DE4_DDR2 sof NIOS II Program DDR2 elf DDR2 SODIMM 2 e Batch File test bat test bashrc FPGA Configure File DE4_DDR2 sof e NIOS II Program DE4_DDR2 elf B Demonstration Setup Make sure Quartus II and NIOS II are installed on your PC Make sure DDR2 SDRAM SODIMM is installed on your DEA board as shown in Figure 5 23 Power on the DEA board Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e E
92. be used to illuminate the LEDs change the values displayed on 7 segment displays monitoring buttons switches status read write from various memory types in addition to testing various components of the DE4 board 3 2 Controlling the LEDs and 7 Segment Displays One of the functions of the Control Panel is to set up the status of the LEDs and 7 segment displays The tab window shown in Figure 3 5 indicates where you can directly turn all the LEDs on or off individually by selecting them and clicking Light or Unlight Terasic DE4 User Manual www terasic com STAA TN IV DCAD 1 i C TN 1 r T pd ge BUTTON 1 11111 6 e 50 Care Figure 3 5 Controlling LEDs Figure 3 6 shows the interface of the 7 SEG and how to select desired patterns The status of the 7 SEG patterns will be updated immediately 76 Terasic DE4 User Manual www terasic com WWUWW COFOGIC COT c n H Y XA H n i nnn s n n U maaan m 5704 X a BOA ww j E Vu 1 LI Temp Y Power DOT HOT rr uy Figure 3 6 Controlling 7 SEG display 3 3 SWITCH BUTTON Choose the Button tab as shown in Figure 3 7
93. ccccsccecceccuscscaccesccsccuscsecscuscescescesccsecsscscescescessessctscuseusceees 116 OB SIC ABRDREADER EM MEME ME EMEN PIENE 124 ye 1 1 1 342 4 RT ERU 128 5 6 EXTERNAL CLOCK GENER ATOR 132 5 7 POWER MEASUREMENT csccsccecceccecceccccccecceccuccescsceecesccsscsscsscscascescesccsecssceceeceecescesecsecsscuscescescessessctscsceecetees 137 s RESI A 141 SERIAL ATA SATA T 150 S IOTHIGEESPEBP MEZZANINE 151 CHAPTER 6 PCI EXPRESS REFERENCE DES QGNM ccce eee ecce eee eese eee eese eee esos eese sss 154 6 1 PCI EXPRESS SYSTEM INERASTRUGCTU RE Guinn bosses vb RES CER TE Nava vv ER M e 154 6 2 FPGA PCI EXPRESS SYSTEM DESIGN ccccsccecceccccccccscceccescescescecceeccsccsscsscscesceecescesscsscsecescescescesecsscuscuscesceees 155 6 PCPCIEXPRBESS SYSIBM DBSIGN ari 159 0 4 FUNDAMENTAL 168 6 5 EXAMPLE 2 IMAGE PROCESS APPLICATION
94. ce 0 O Sata Device 1 PLL_CLKIN SATA_REFCLK O PCle GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 5 Pixel Camera ADA High Speed Prefix Name Prefix Name GPIO 1 Header HSMC B Transceiver x 8 LTM 4 3 LCD and Touch i DVI TX RX Prefix Name i Prefix Name Default Setting Load Setting Save Setting Figure 4 4 System Configuration Group B Programmable PLL There are three external programmable PLLs on board that provide reference clocks for the following signals HSsMA REFCLK HSMB REFCLK and PLLCLKIN SATA REFCLK To use these PLLs users can select the desired frequency on the Programmable PLL group as show in Figure 4 5 As the Quartus project is created System Builder automatically generates the associated PLL configuration code according to users desired frequency in verilog which facilitates users implementation as no additional control code is required to configure the PLLs Note If users need to dynamically change the frequency they would need to modify the generated control code themselves 95 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 100 System Configuration ATERA wc 9 Md UNIVERS Board Type DE4 230 PROGRAM www terasic com Pr
95. ce ID and matched card index Prototype PCIE HANDLE PCIE Open WORD wVendorID WORD WORD wcCardlIndex Parameters 163 Terasic DE4 User Manual www terasic com rasic com w VendorID Specify the desired vendor ID A zero value means to ignore the vendor ID wDevicelD Specify the desired device ID A zero value means to ignore the device ID wCardIndex Specify the matched card index a zero based index based on the matched verder ID and device ID Return Value Return a handle to presents specified PCIe card A positive value is return if the PCle card is opened successfully A value zero means failed to connect the target PCIe card This handle value is used as a parameter for other functions e g PCIE_Read32 Users need to call PCIE Close to release handle once the handle is no more used PCIE Close unction Close a handle associated to the PCIe card Prototype void PCIE Close PCIE HANDLE hPCIE Parameters hPCIE A PCle handle return by PCIE_Open function Read a 32 bits data from the FPGA board bool PCIE Read32 PCIE HANDLE hPCIE PCIE BAR PcieBar PCIE ADDRESS PcieAddress DWORD pdwData Parameters hPCIE 164 13 51 Terasic DE4 User Manual www terasic com rasic com A PCIe handle return by PCIE Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA pdwData A buffer to retrieve the 32 bit
96. ces have 5 clock inputs and 4 clock outputs 2 differential clock inputs and outputs B I O Standards The HSMC interface has programmable bi directional I O pins that can be used as 2 5 V These pins can also be used as differential I O standard including LVDS B Using THCB HMF2 adapter card The purpose of the HSMC Height Extension Male to Female card THCB HMF2 included in the DEA kit package is to increase the height of the HSMC connector to avoid any obstruction that 26 Terasic DE4 User Manual www terasic com w rasic com ANU S RYA might take place as a HSMC daughter card is connected The 2 adapter card can be connected to either ports or B of the HSMC connector shown in Figure 2 13 TETE nt v T 3 a 11 Lag MEL E mm ent TESI 2 D LT LINEAR Y 4 09304 HL i i war Pine LAM au 7 nee LINEAR LT LINEAR MTM 255 M4601 601 MJ601V wem LM i mi mov LI f III d N38336 0930 90 1 LT N __ 0 p e die bom LLLI 383368 AU Y M s UTR EX Rr Wi am Zw e das T Bu M EPASGX530KH40C2N jt Pn B 4444444 UTE 5998
97. citor 63 Terasic DE4 User Manual www terasic com w ra asic com Differential transmit data output ATA DEVICE TX p1 1 4 V PCML PIN 4 nies before DC blocking capacitor S Host SATA HOST TX pO Differential data 1 4 PCML before DC blocking capacitor SATA HOST TX Differential data 1 4 PCML before DC blocking capacitor SATA HOST RX PIN AR1 after DC blocking capacitor SATA HOST RX Differential ECEE data 14 V PCML PIN AR2 after blocking capacitor SATA HOST TX Differential data 14 V PCML before DC blocking capacitor SATA HOST TX n1 Differential data output 1 4 V PCML PIN_AF3 before DC blocking capacitor SATA_HOST_RX_n1 PIMereHus ay PCM after DC blocking capacitor SATA HOST RX pi Differential receive data input 14 V PCML PIN AG2 after DC blocking capacitor 2 14 RS 232 Serial Port The DEA board uses the ADM3202 transceiver chip and 9 pin D SUB connector for RS 232 communication For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s website or in the Datasheet RS232 folder on the DEA System CD ROM Table 2 28 lists the RS 232 pin assignments signal names and functions Table 2 28 RS 232 Pin Assignments Schematic Signal Names a
98. ck Enable pin 0 for DDR2 Clock Enable pin 1 for DDR2 DDR2 Address 15 42 Terasic DE4 User Manual rasic com SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class PIN AN25 PIN AP25 PIN AV26 PIN AW26 AU26 PIN AP28 PIN AT26 PIN AR28 PIN AU25 PIN AR25 PIN AT25 PIN AN24 PIN AN23 23 23 AR23 AU24 24 AU23 122 23 22 121 AJ22 24 AH23 AJ23 22 123 23 AF22 AF23 23 22 28 27 29 www terasic com M1 DDR2 BA2 DDR2 Bank Address 2 SSTL 18 Cla
99. d through the management interface of the 88 1111 Ethernet device Once the link 15 established an IP address 15 assigned to the Ethernet device along with the port number Through TCP and port number the demonstration uses Telnet client to establish connection with the Simple Socket Server where it 1s continuously listening on the port Once the connection 15 established between the Telnet client and Simple Socket Server the Telnet client 1s able to send packets which are received by the Nios II processor and through the Simple Socket Server it will send server command to the DE4 The packet sent contains LED command which 15 extracted and dispatched to the LED command queue for processing by the LED management tasks 120 Terasic DE4 User Manual www terasic com www terasic com IN DTE RYAN Figure 5 15 shows the software architecture of the Nios program for the Simple Socket Server The top block containing the Nios II processor and the necessary hardware to be implemented into the DEA board The software device drivers contain the necessary device drivers needed for Ethernet and other hardware components to functions The HAL API block provides the interface for the software device drivers while the MicroC OS II provdes communication services to the NichStack and the Simple Socket Server The NicheStack TCP IP stack software block provides networking services to the application where it contains tasks for Simple Socket Server and also LED
100. der Control Panel 3 12 Fan Choose the Fan tab to reach the window shown in Figure 3 17 This function is designed to verify the functionality of the fan components and signals Please make sure the Fan 15 installed on DEA before running this function as Terasi ter Terasic DE4 User Manual www terasic com EET CC aaga Pree xd D mem ot 1 bo NE NC m Figure 3 17 Fan Control of the DEA 89 Terasic DE4 User Manual www terasic com www terasic com Chapter 4 DE4 System Builder This chapter describes how users can create a custom design project on the DE4 board by using DE4 Software Tools DE4 System Builder 4 1 Introduction The DE4 System Builder is a Windows based software utility designed to assist users to create a Quartus II project for the DEA board within minutes The generated Quartus II project files include e Quartus II Project File qpf e Quartus II Setting File qsf e Top Level Design File v e External PLL Contorller v e Synopsis Design Constraints file sdc e Pin Assignment Document htm The DE4 System Builder not only can generate the files above but can also provide error checking rules to handle situation that are prone to errors The common mistakes that users encounter are the following e Board dama
101. e 5 2 Prefix Name 2 Default Setting Load Setting Save Setting Figure 4 9 Specify Prefix Name for HSMC Expansion Board B Project Setting Management The DE4 System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 4 10 Users can save the current board configuration information into a cfg file and load it to the DE4 System Builder 100 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 1 0 0 System Configuration Board Type 4 230 Project Name 4 MCLOCK Slide Switch x 4 2 7 Segement x 2 Button x 4 DIP Switch x 8 SMA Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64 EEPROM SSRAM 2MB ione Programmable PLL Programmable PLL Ethernet x 4 HSMA REFCLK O DDR2 5 1 O DDR2 SODIMM Sata Host 0 C Sata Host 1 O Sata Device 0 O Sata Device 1 PLL CLKIN SATA REFCLK PCle 5 REFCLK GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 D5M 5M Pixel Camera Form Factor Pluggable Prefix Name Prefix Name GPIO 1 Header HSMC B Transceiver x 8 4 3 LCD and Touch SDI SD HDSG Prefix Name Prefix Name
102. e C DE3_SystemBuilderw1 4 2 SOPC ptt Browse CPU cpu select Project Template Runs TCP IP socket server ENS x simple Socket Server uses the industry standard Socket mterface to Hello World Small Thi ia rs que shows how to initialize the Nichestack TCP IP Stack and run a Memory Test simple server application allowing a PC to communicat with a Nios II Simple Socket Server System vis Ethernet Web Server a s This example requires the RTOS and NicheStack Stack Nios Edition software components It also requires several peripherals including 181916111 Ethemet Figure 5 14 Nios Il project simple socket server B Overview The Simple Socket Server uses the industry standard sockets interface to TCP IP It uses DHCP protocol to requests a valid IP from the Gateway During the device initialization process the NichStack TCP IP Stack system code calls get add and get add to get the MAC and IP addresses for the network interface Once the MAC address 15 generated Autonegotiation 15 initiated where both connected devices Ethernet Marvel 88 1111 and Gateway devices broadcasts its transmission parameters speed and duplex mode By default the MAC interface for the Ethernet device is set to SGMII In this demonstration we are using SGMII MAC interface which can be configure
103. eiver channels to provide SATA IO connectivity to both host and target devices To verify the functionality of the SATA host device ports a connection can be established between the two ports by using a SATA cable as Figure 2 28 depicts the associated signals connected Table 2 27 lists the SATA pin assignments signal names and functions 5 54 SATA DEVICE TX_p1 SATA HOST SATA HOST SATA HOST TX n1 SATA HOST RX n1 SATA DEVICE RX p1 SATA DEVICE RX n1 SATA DEVICE n1 SATA DEVICE SATA HOST Figure 2 28 Pin connection between SATA connectors Table 2 27 Serial ATA Pin Assignments Schematic Signal Names and Functions Schematic P Stratix IV GX Pin Description I O Standard Signal Name Number Device Differential receive data input SATA DEVICE 1 4 V PCML PIN AU2 after DC blocking capacitor E SATA DEVICE RX nO PIN AU1 after DC blocking capacitor SATA DEVICE TX EIUS ental Hay ROME PIN AT3 before DC blocking capacitor SATA DEVICE TX OHIDUE acce ii PIN 4 before DC blocking capacitor SATA DEVICE Tece data 1 4 CML PIN AJ2 after DC blocking capacitor SATA DEVICE aT pH tay ME PIN after DC blocking capacitor SATA DEVICE TX n1 Differential transmit data output 14 V PCML AH3 before DC blocking capa
104. el mode driver only supports Windows XP 32 bit Edition provided by Jungle Inc The PCI Express Library is implemented as single DLL called TERASIC PCIE DLL With the DLL exported to the software API users can easily communicate with the FPGA The library provides the following functions Device Scanning on PCIe Bus e Basic Data Read and Write Data Read and Write For high performance data transmission 15 required as the read and write operations are specified under the hardware design on the FPGA 159 Terasic DE4 User Manual www terasic com rasic com ANU S n VAS B PCI Express Software Stack Figure 6 8 shows the software stack for the PCI Express application software The PCI Express driver is incorporated the DLL library called TERASIC PCIE DLL Users can develop their application based on this DLL User Application TERASIC PCIE dll wdapi921 dll User Mode Kernel Mode TERASIC_PCIE inf windrvr6 sys Third Party TERASIC Jungle Figure 6 8 Express Software Stack B Install PCI Express Driver To install the PCI Express driver execute the steps below 1 From the DE4 system CD locate the PCIe driver folder in the directory DE4_CDROM demonstrations lt DE4 device gt PCle_SDK Driver 160 TijasiC Terasic DE4 User Manual www terasic com 2 Double click the PCIe DriverInstall exe executable file to launch the installation program 3 4
105. elnet client session by executing open telnet bat file and include the IP address assigned by the DHCP server provided IP along with the port number as shown below in cx C WINDOWS system32 cmd exe Welcome to Microsoft Telnet Client Escape Character is CIRL 1 Microsoft Telnet help Commands may be abbreviated Supported commands are close close current connection display display operating parameters open hostname port 1 connect to hostname Cdefault port 23 gt quit exit telnet set set options set a list send send strings to server status print status information unset unset options unset for list he lp print help information ft Telnet gt open 192 168 1 234 30 004 2 OC Figure 5 17 Telnet Client 123 Terasic DE4 User Manual www terasic com www Lerasic ANU S RYA Fromthe Simple Socket Server Menu enter the commands in the telnet session Start the session by initializing 7 segment displays by entering the letter 5 followed by a return where it begins incrementing Entering a number from zero through six followed by a return causes the corresponding the LEDs LEDO LEDO to toggle on or off on the DEA board 5 4 SD Card Reader Many applications use a large external storage device such as a SD card or CF card to store data The DE4 board provides the hardware and software needed for SD card access In this demonstration we wil
106. emonstration USB host functions are implemented for USB mass storage and Human interface devices HIDs including a USB Mouse The drivers of the above applications are implemented in NIOS II C code high speed full speed and low speed devices are supported in this demonstration Figure 5 1 shows the hardware system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL generates a 100 MHz clock for NIOS II processor and high speed controllers as well as a 10 MHz clock for low speed peripherals such as buttons A custom defined SOPC ISP1761 controller developed by TERASIC is used to connect ISP1761 USB chip and NIOS II processor Based on this controller NIOS II processor can access the register 103 Terasic DE4 User Manual www terasic com www terasic com ANU S p YAN memory and interrupts of the USB chip PIO pin named usb reset is connected to the USB for performing hardware reset of the USB chip The NIOS II program is stored in the On Chip Memory 50 MHz 7 2 HEN On Chip Memory Controller Button PIO Controller unm ISP1761 Controller Intercoment Fabric Figure 5 1 Hardware block diagram of the USB Host demonstration B Nios II Software Architecture Figure 5 2 shows the architectural layers of a NIOS II software stack of this demonstration 104 DE4 User Manual www terasic com www teresic co
107. ent UCCH I P 21 359 1 Current 6 666688 A A gt 9 734568 lt gt 6 666688 lt A A gt gt 6 617325 AD gt 6 660068 A A gt 0 000099 lt 45 9 003417 lt 9 001351 lt gt 0 lt 9 001113 lt 9 733852 lt gt B agpapacha 8 080080808 hf 8 00008080 f Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power gt 6 661111 W gt 015593 lt gt 0 000143 lt gt 0 008543 0 001486 lt gt 666060 gt 08 001558 CU 66046 7 lt gt 8 000088 8 000080 UolDrop 8 0000514U Current 6 617087 A gt CUCC1P8_34R 1FFFFE18H Neg 1 VolDrop 6 666606 CU gt Current 6 666000 A gt D Power 0 015306 lt gt Pover 8 008808080 U NiosII 08 15 UolDrop 8 8080808088 U UCC1P8 78R 2888881CH Irent 8 888888Cf Current 08 0800008 C80 Pover 8 0000880CU gt Figure 5 31 Power consumption information 5 8 Web Server A web server is implemented based on the socket s application program interface API provided by the NicheStack TCP IP Stack Nios II Edition running on MicroC OS II RTOS to serve web content from the DE4 development board Using DHCP protocol t
108. ged for wrong pin bank voltage assignment e Board malfunction caused by wrong device connections or missing pin counts for connected ends e Performance dropped because of improper pin assignments 90 1 Terasic DE4 User Manual www terasic com rasic com 4 2 General Design Flow This section will introduce the general design flow to build a project for the DEA board via the DEA System Builder The general design flow is illustrated in the Figure 4 1 Users should launch DEA System Builder and create new project according to their design requirements When users complete the settings the DEA System Builder will generate two major files which include top level design file v and the Quartus II setting qsf The top level design file contains top level verilog wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and I O standard for each user defined I O pin Finally Quartus II programmer must be used to download SOF file to DE4 board using JTAG interface 9 Terasic DE4 User Manual www terasic com www Lterasic com Figure 4 1 The general design flow of building a design 4 3 Using DE4 System Builder This section provides the detail procedures how the DEA System Builder is used B Install and launch the DEA System Builder The DEA System Builder is located in the directory Tools DE4 SystemBuilde
109. gle ch GAF Eo EE ITRE 2 amp re x PANDORA 4 KMPlayer CNN 5 YouTube Facebook E Games Amazon Ej subtilize X Weather E Email Options x BEBE 03 Terssic AR Statix IV GX 6 Nios II Example Web Ser x A E oc M MAD 6 Nios Il Web Server Demo for DE4 Board Status Control Design Resource V LEDs 1 Terasic Home Page v Seven Seg 60 ES 22 0 DE4 sweep Fan Control Daughter Board 4 3 LCD Touch Panel 5Mega Pixel Camera This page is being served from a web server running on a configurable Nios Il processor The DE4 is based on Stratix IV GX FPGA EP4SX230 or EP4SGX530 with integrated transceivers that DVI Card operate up to 8 5 Gbps allowing engineers to prototype and test their high speed interfaces quickly and easily The DE4 Development Board is complete and easy to use enabling designs with industry standard high speed serial protocols including PCI Express version 2 0 with up to x8 lane configurations four High Speed AD DA Serial ATA ports Revision 3 0 four Gigabit Ethernet ports two DDR2 SDRAM nine clock sources to drive the clock circuitry of the DE4 Similarly the DE4 includes 16 Mb SSRAM memory 64 Mb flash Card memory for storing FPGA images and embedded USB Blaster for FPGA configuration The conte
110. h a Simple Socket Server The Simple Socket Server continues to 117 Terasic DE4 User Manual www terasic com www terasic co m AN DTE RAN listen for commands on a TCP IP port and operates the DE4 LEDs according to the commands from the telnet client NicheStack TCP IP stack uses the MicroC OS II RTOS multithreaded environment to provide immediate access to a stack for Ethernet connectivity for the Nios II processor The Nios II processor system contains an Ethernet interface or media access control MAC B How the Ethernet demonstration is built In this following section we describe how to build the demonstration through the SOPC builder The SOPC system includes the CPU processor On Chip memory JTAG system ID timer Triple Speed Ethernet Scatter Gather DMA Controllers and peripherals which are linked together contained in the Nios II hardware system that are used when building a project Figure 5 12 presents the overall setup of the SOPC builder from the Ethernet Simple Socket Server project Altera SOFC 4 SOPC MUR osi icio 9 Sample Socket Ethermet MDEA SORC System Merl pe Sytem Contents System Generabon Component Library Target imr Satie P mo Aeon DOA Mem Description Cre Mess AwMon MM E Avalon Me
111. he host computer Figure 3 1 will appear and the Control Panel starts to auto detect the FPGA and download sof files 71 Terasic DE4 User Manual www terasic com www terasic com ANU nA e After the configuration file is programmed to board the FPGA device information will be displayed on the window Note the Control Panel will occupy the USB port users will not be able to download any configuration file into the FPGA before you exit the Control Panel program Windows 7 64 bit Users If an error message that shows a missing client dll file cannot find client dll while the Control Panel is commencing users should re launch the DEA ControlPanel exe from the following directory Tools DE4_ControlPanel win7_64bits The Control Panel is now ready as shown in Figure 3 2 S X FAGA j A b Aii 885735 ET 1 ma AIT Spem ter asic Figure 3 1 Download sof files to the DE4 board T2 Terasic DE4 User Manual www terasic com www terasic com BUTTON Memory i im T NE 1 me Tf Sea Fr 44 4 Temp Power PLL ae 1 Figure 3 2 4 Control P
112. he web server is able to request a valid IP from the Gateway The server can process basic requests to serve HTML JPEG GIF PNG JS CSS SWE ICO files from a single zip file stored onto the flash memory on the DE4 board In addition it also allows you to control various board elements from the web page which includes controlling the LED lights 7 segment display and fan control As Part of the Nios II NicheStack TCP IP Network Stack is a software suite of networking protocols designed to provide an optimal solution for designing network connected embedded devices with the Nios II processor Before you begin to study this demo we assume that you already have a basic knowledge of PHY and MAC In this case the PHY we use 1s Marvell 88E1111 10 100 1000 and the MAC 15 Altera s Triple speed Ethernet Soft Core IP The following describes the SOPC system which contains a Nios II processor On Chip memory JTAG UART timer Triple Speed Ethernet Scatter Gather DMA controller and peripherals which are linked together in the Nios II hardware system to be used when building a project In the Triple Speed Ethernet IP Core configuration the interface is set to SGMII interface as well as using the internal FIFO shown in Figure 5 32 Terasic DE4 User Manual www terasic com 141 www terasic com Parameter Settings Core Configuration MAC Options FIFO Options PCSISGMII Options Core variation 1000 4 000 Ethernet MAC with
113. ic Signal Names and Functions Schematic MS Stratix IV GX Pin Description Standard Signal Name Number TEMPDIODEp reste pin of temperature diode in 2 5 V A9 Stratix IV TEMPDIODEn pin of temperature diode in 2 5 V PIN E11 Stratix IV TEMP SMCLK SMBus clock 1 8 V PIN AN18 TEMP SMDAT SMBus data 1 8 V PIN AP18 TEMP INT n SMBus alert interrupt 1 8 V PIN AP19 FAN CTRL Fan control 1 8 V PIN AP20 2 19 Power The DE4 Development Board has two selective power sources to choose from which include the DC power input and the PCIe edge connector When the DEA is connected to the PCIe slot an optional 6 pin PCIe external power connector can be connected to a PC power supply in case additional power is required on the DEA It 15 recommended that users connect the PCIe external power connector to the DE4 when either the HSMC or GPIO interface is occupied by a daughter card The DC voltage is stepped down to various power rails used by the components on the board and installed into the HSMC connectors B PowerSwitch The slide switch SW5 is the board power switch for the DC power input When the slide switch is in the ON position the board is power on Alternatively when the switch is in the OFF position the board 15 power off B Power Measurement There are 12 power supply rails which have on board voltage and current sense capabilities These 8 channel differential 24 bit ADC devices and rails are split from the pri
114. ided on the DE4 which offers additional connectivity and I Os for general purpose applications The header has 7 pins connected to Stratix IV GX FPGA with the other pins providing a DC 3 3V VCC33 and 6 GND pins Note the 6 data I O pins on the 14 pin expansion header share the same bus with the GPIO expansion header JP3 The pin assignments are given in Table 2 12 Table 2 13 and Table 2 14 Table 2 12 GPIO Expansion Header Pin Assignments Schematic Signal Names and Functions Schematic Description I O Standard Stratix IV GX Pin Number Signal Name GPIOO DO GPIO Expansion 0 lO O Clock In 3 0 or LVDS PIN AF6 GPIOO D1 GPIO Expansion 0 IO 1 3 0 V PIN AU9 GPIOO D2 GPIO Expansion 0 lO 2 Clock In 3 0 LVDS 5 GPIOO D3 Expansion 0 IO 3 3 0 V PIN AR8 GPIOO 04 GPIO Expansion 0 lO 4 3 0 V PIN AN9 GPIOO D5 GPIO Expansion 0 IO 5 3 0 V PIN AP9 GPIOO D6 GPIO Expansion 0 10 6 3 0 V PIN AV5 GPIOO D7 GPIO Expansion 0 IO 7 3 0 V PIN AW6 GPIOO D8 Expansion 0 IO 8 3 0 V PIN AV7 GPIOO D9 GPIO Expansion 0 IO 9 3 0 V PIN AW7 GPIOO D10 GPIO Expansion 0 1 0 10 3 0 V PIN AT5 GPIOO D11 Expansion 0 11 3 0 V GPIOO 012 GPIO Expansion 0 1012 3 0 V PIN AP5 GPIOO D13 GPIO Expansion 0 IO 13 3 0 V PIN AP7 GPIOO D14 GPIO Expansion 0 lO 14 3 0 V PIN AN5 GPIOO D15 GPIO Expansion 0 1 0 15 3 0 V PIN AN10 GPIOO D16 GPIO Expansion 0 IO 16 3 0 V PIN AM5 GPIOO D17 Expansi
115. ification Revision 2 0 April 27 2000 e Enhanced Host Controller Interface Specification for Universal Serial Bus Revision 1 0 March 12 2002 e Universal Serial Bus Mass Storage Class Bulk Only Transport Revision 1 0 September 31 1999 e Universal Serial Bus Mass Storage Class UFI Command Specification Revision 1 0 December 14 1998 Universal Serial Bus Device Class Definition for Human Interface Devices HID Version 1 11 June 27 2001 110 Terasic DE4 User Manual www terasic com www terasic com CMNTITITIT intl Be Bt ee m d eri cr mmm 1 ATL pen 119 JI 1 mW ane LF hE d 1i b nd E p I un TI T ELI Ld A t 4 um p 1 21 E is MM it EE es M ELT pt ym Ath n Abit an Hen UNIVERSITY 1 ig T UEM i 3 EL e r 4 E 4 uc _ E Hus iin E 1 pipa ri H 1 Figure 5 5 Plug USB Devices into 4 EDS 9 1 Welcome to the Nios II Embedded Design Suite Version 7 1 Built Thu
116. ignals situated on the HSMC interface This design also helps you verify the transceiver signals functionality for ports A and B of the HSMC interface A total of 8 transceiver pairs on the HSMC port B are tested while a total of 4 transceiver pairs are tested on HSMC port A HSMC Port A Loopback Test B Demonstration Source Code Quartus Project directory 4 HSMA LOOPBACK TEST FPGA Bit Stream DE4 HSMA LOOPBACK TEST sof 151 Terasic DE4 User Manual www terasic com www terasic com ANU S RYA B Demonstration Setup Check that Quartus II and NIOS II are installed on your e Insert the HSMC loopback daughter card onto the HSMC port as shown in Figure 5 41 e Insert the HSMC loopback daughter card onto the HSMC port A Power on the DEA board e Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e Program the DEA using the 4 LOOPBACK TEST sof through Quaruts programmer Press RESET pushbutton 0 of the DE4 board to initiate the verify process LED 3 0 will flash once indicating the loopback test passed E 4 n 2 29 ETT mcer sic ET j cam gt f 2 fn MERIT IL oad il mam ns zr um n um PATI ERELT Na 2 505 68 2 Ir rb n
117. image process function based on this fundamental reference design In the demonstration a memory mapped memory is designed in the FPGA to work as an image frame buffer The memory size is 320x240x3 bytes with start address 0x00 The raw image is downloaded to and uploaded from FPGA by DMA The image process command and status is controlled by a register which can be accesssed from the PC by basic IO control The register address 15 0x10 under PCIE BARI Writing any value into this register will start the image process The status of the image process 15 reported by a read to this register The PCIe vender ID and device ID is Ox1172 and respectively The block diagram of FPGA PCIe design is shown in Figure 6 14 172 Terasic DE4 User Manual www terasic com rasic com FPGA Tersic PCle IP Basic Register E PCI Express 1 E E Basic I O Interface Figure 6 14 Block Diagram of Image Process in FPGA B Demonstration Files Location The demo file is located in the folder PCIE ImageProcessNlemo batch The folder includes following files e Application Software PCIe Image Demo exe FPGA Configuration File 4 ImageProcess sof e PCIe Library TERASIC PCIE DLL Demo Batch File test bat B Demonstration Setup e Installed DEA on your e Locate demo folder PCIE batch e Download DEA ImageProcess sof into the D
118. ing Stratix IV GX pin numbers Table 2 26 Ethernet PHY Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Ethernet 0 ETH TX pO ETH TX nO ETH RX pO ETH RX nO ETH MDCO ETH MDIOO ETH INT nO ETH RST n Ethernet 1 ETH TX p1 ETH TX n1 ETH RX p1 ETH RX n1 ETH MDC1 ETH MDIO1 ETH_INT_n1 ETH n Ethernet 2 ETH TX p2 ETH TX n2 ETH RX p2 ETH RX n2 ETH MDC2 ETH MDIO2 ETH INT n2 ETH RST n Ethernet 3 ETH TX p3 ETH TX n3 ETH RX p3 ETH RX n3 ETH MDC3 ETH MDIOS3 ETH INT n3 ETH RST n Description TX data TX data RX data RX data Management bus control Management bus data Management bus interrupt Device reset TX data TX data RX data RX data Management bus control Management bus data Management bus interrupt Device reset TX data TX data RX data RX data Management bus control Management bus data Management bus interrupt Device reset TX data TX data RX data RX data Management bus control Management bus data Management bus interrupt Device reset 61 Terasic DE4 User Manual rasic com Standard LVDS LVDS LVDS LVDS 2 5 V 2 5 V 1 8 V 2 5 V LVDS LVDS LVDS LVDS 2 5 V 2 5 V 2 5 V 2 5 V LVDS LVDS LVDS LVDS 2 5 V 2 5 V 2 5 V 2 5 V LVDS LVDS LVDS LVDS 2 5 V 2 5 V 2 5 V 2 5 V Stratix IV GX Pin Number PIN T30 PIN T31 PIN U31 PIN V31 PIN R30 PIN W32 PIN B20 PIN V29 PIN R32 PIN R33 PIN N33 PIN N34 PIN J6 PIN J5
119. is board through the PCIe edge connector DIP switch SW9 is connected to the PCI Express to allow different configuration to enable an x1 x4 or x8 PCIe Table 2 23 summarizes the PCI Express pin assignments of the signal names relative to the Stratix IV GX FPGA 56 Terasic DE4 User Manual www terasic com www terasic com PCIE REFCLK p PCIE REFCLK n ANU S n VAN PCIE TX p 7 0 2 PCIE n 7 0 Stratix GX PCIE RX p 7 0 PCIE n 7 0 Figure 2 24 PCI Express pin connection Table 2 23 PCI Express Pin Assignments Schematic Signal Names and Functions Schematic Stratix IV GX Pin Description Standard Signal Name Number PCIE TX pO NET Add in card transmit bus 1 4 V PCML PIN AT36 PCIE TX nO NET Add in card transmit bus 1 4 V PCML PIN AT37 PCIE TX p1 NET Add in card transmit bus 1 4 V PCML PIN AP36 PCIE TX n1 NET Add in card transmit bus 1 4 V PCML PIN AP37 PCIE TX p2 NET Add in card transmit bus 1 4 V PCML PIN AH36 PCIE TX n2 NET Add in card transmit bus 1 4 V PCML PIN AH37 PCIE TX p3 NET Add in card transmit bus 1 4 V PCML PIN AF36 PCIE TX n3 NET Add in card transmit bus 1 4 PCML PIN AF37 PCIE TX p4 NET Add in card transmit bus 1 4 V PCML PIN AD36 PCIE TX n4 NET Add in card transmit bus 1 4 V PCML PIN AD37 PCIE TX p5 NET Add in card transmit bus 1 4 V PCML PIN AB36 PCIE TX n5 NET Add in card transmit bus 1 4 PCML PIN AB37 PCIE TX p6 NET Add in card transmit bus 1 4 V
120. is function block Main the main block contains the tasks for the application including reading the commands and write functions to the computer The workflow of the main block is shown in Figure 5 3 The standard output of this program is JTAG UART In the demo batch file the output message will be display in nios2 terminal When the program detects an USB mass storage device it will list the files in root directory If a file named test txt 1s found the program will dump the file contents When an HID USB Mouse is detected the program will poll the mouse status continuously and display the relative information in standard output In this demonstration NIOS II uses PIO mode to access the internal memory of ISP1761 For high throughput application DMA implementation and interrupt can enhance data transfer rate significantly rasic com 106 Terasic DE4 User Manual www terasic com otart No 5 USB New Device Yes lt je veg E NO ra mass storage Attached Attached No No USB Mouse Detached No Associated Mouse Instance Exists Yes Figure 5 3 Software workflow of the USB Host demonstration ves i 107 Terasic 4 User Manual www terasic com AN DTE RAN B Design Tools e Quartus NIOS II IDE B Demonstration Source Code e Quartus II Project directory 4 USB e FPGA Bit Stream 4 USB sof NIOS II Workspace DEA USBNS
121. ith user defined command sets The USB device driver 15 implemented in NIOS C code From the host computer side a test program 15 used to communicate with DEA The test program can configure LED status and poll button status through the USB connection B Nios II Software Architecture The hardware system block diagram of this demonstration is the same as the USB Host Figure 5 7 shows the architectural layers of a NIOS II software stack of this demonstration Figure 5 7 Software stack of the USB Device demonstration Each block encapsulates the specific implementation details of that block providing a data abstraction for the block above The following is a description of each block Nios II PIO The Nios PIO block provided by Nios II system that supports basic IO functions IORD and IOWR to access hardware directly The function prototypes are defined in the header file lt 10 h gt 112 Terasic DE4 User Manual www terasic com ISP 1761 HAL The ISP 1761 HAL block implements functions to access internal control data registers of the USB chip ISP 1761 USB Peripheral Controller The USB peripheral controller block implements control functions for ISP1761 peripheral controller USB Protocol The USB protocol block implements USB protocol including USB Hub protocol USB Bulk Driver The USB bulk driver implements a device driver to provide two bulk end points namely Bulk In and Bulk Out Main
122. l show how to browse files stored in the root directory of a SD card and how to read the file contents of a specific file The SD card 15 required to be formatted as FAT File System in advance Long file name 15 supported in this demonstration Figure 5 18 shows the hardware system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL generates a 100 MHz clock for the NIOS II processor and other controllers Seven PIO pins are connected to the SD card socket SD 4 bit Mode is used to access the SD card hardware The SD 4 bit protocol and FAT File System function are all implemented by NIOS II software The software 15 stored 1n on chip memory FPGA gt E gt PIO LED Controller PIO e o em lt gt PIO Controller 50 MHz System Intercoment Fabric Figure 5 18 Block diagram of the SD card demonstration 124 Terasic DE4 User Manual www terasic com www terasic co m ANU RYA Figure 5 19 shows the software stack of this demonstration The NIOS PIO block provides basic IO functions to access hardware directly The functions are provided from NIOS II system and the function prototype 15 defined in the header file io h The SD CARD block implements SD 4 bit mode protocol for communication with SD cards The FAT File System block implements reading function for 16 and FAT 32 file system Long filename is
123. lash of the DE4 system CD ROM 2 The flash program tool shows the menu options DE4 Development Kit Flash Program Tools ver 1 H H H menu JEEE RE RE RE RE RE RE RE RE RE RE RE BERE RE E EEEE Program sof and elf to Flash Cinclude pfl option bit Erase flash Program sof file into the flash Program elf file into the Flash Program web page ZIP file into the flash Program Ethernet address Readme File EE EE EE EE EE ne aT BE 3E AEA AEA EE E E E E EE E E n i ni i AEA AAA EE E BEBE E E E E lli EE EE BE BE BE BE BE BE Enter a number 0 for Done Figure 2 3 Flash program tools 3 Select option 2 DE4 Development Kit Flash Program Tools ver 1 8 0 8 meni E RE RE RE RE RE RE BRE E RE RE ERE E ERE RE RE ERE RE RE ERE ERE RE ERE RE Program sof and 1 to Flash Cinclude pfl option bit Erase Flash Program sof file into the flash Program elf file into the flash Program veh paye amp ZIP file into the flash Program Ethernet MAC address Readme File EEE E E E E E n i E E n n a n E n 7 E E E E 3E E E E E E 3E 3E 3E E E E E 3E 3E RE E E E 8E ERE RE E BE BRE BRE BRE RE BRE RE BRE BE BE Enter a number D for Done 2 Figure 2 4 Option 2 16 Tasic Terasic DE4 User Manual www terasic com N ND 8 RYA 4 Enter the sof file name to be programmed onto the flash memory Nios II EDS 9 1 E 5
124. mary supply plane by a low value sense resistor for the ADC to measure voltage and current A SPI bus connects these ADC devices through level shifters to the Stratix IV GX FPGA Figure 2 29 shows the block diagram for the power measurement circuitry 69 DE4 User Manual www terasic com www terasic com ANU S RYAN Supply R Sense Power 80 supply Load 0 Supply Sense Power 11 Supply Load 11 CSENSE FO 5 evel CSEHSE 500 Ke shifter VI CSENSE SCK CSENSE CS Level Shifter CSENSE CS Figure 2 29 Power measurement circuit Table 2 33 lists the targeted rails The schematic signal name specifies the name of the rail being measured and the device pin denotes the devices attached to the rail Table 2 33 Power Rail Measurements Schematic m Switch Voltage Description Signal Name 0 30V Bank5A amp SClOPreDriver 1 HSMAVCCIO 2 50 2 amp 2C IO 2 25V Bank6A amp 6ClOpower HSMCportB 3 8 BV 3B 3C4A 4B 4ClOpowr 4 NCCIPB 1 8 Bank 7A 7B 7C 8A 8B 8C IO power VCCOP9 9 V FPGA core and periphery power VCCHIP 9 V PCI Express hard IP block 9 V PLL analog power 9 V PLL digital power 1 V Transceiver clock power 4 Transmitter clock power VCC3P3
125. mory Treats JTAG to Avalon Mast Saw bo Avalon firewming ber face a copies x Legecy Components Memory Corirolker amp GOR T ni GDN Ie Cnntroller wi Trais and X Flash CompactFlash EPCS Serial Flash c Memory inferis x Perga ali x PLI Addio A 545 video amd image nci ver Jw boi Memory d pend Saves Fin Memony or Memory Sirve Ayain Tri abe Memory Simon Avain Memory barged Trijata Flash Memory interiace CFT Joao Triade Savers PLL Avalon Memony Sire Stem ID Perera Memony dipped ve JTAG LAAT Aakn Harary biatge Slee re herve Timer avalon Memory Siren Pierval Avalon Memony Sive Tripke esses Aw Mors Streaming ni Siren Sauron Ayalon Memory lapped Serve caer DMA i T5100 ea Tes T5100 ad Te Ihr E Avalon Memory Siren LC d Povsthor Memory biped Maler Avalon Memory happed Marien
126. mplmentation and the PC based application The FPGA hardware component is developed based on Altera PCIe and the PC based application is developed under the Jungle driver Figure 6 1 shows the system infrastructure The Terasic PCIe IP license is located in the DEA System CD under the directory DE4_CDROM License Teresic_PCle_TX_RX This license is required in order to compile the PCle design projects provided below In case the license expires please visit DEA s website www de4 terasic com to acquire and download a new license FPGA TERASIC PCle TERASIC_PCIE DLL Altera PCle User Mode L aq 1 X A o O v varmelMoanc Kernel Mode Figure 6 1 PCI Express System Infrastructure wdapi921 DLL 154 Terasic DE4 User Manual www terasic com www terasic co m 6 2 FPGA PCI Express System Design The DE4 PCI Express connector 15 able to allow interconnection to the PCIe motherboard slots For basic I O control a communication 15 established through the PCI Express bus where it 1s able to control the LEDs and monitor the status of the DEA buttons By implementing an internal RAM and FIFO the demonstration 15 capable of direct memory access transfers B PCI Express Basic I O Transaction Under read operation the Terasic PCIe IP issues a read signal followed by the address of the data Once the address 15 received a 32 bit data will be sent along with a read valid signal Unde
127. n1 HSMA TX p8 HSMA p8 HSMA TX n8 HSMA RX n8 HSMA TX p9 HSMA p9 HSMA TX n9 HSMA RX n9 HSMA TX p10 HSMA p10 HSMA TX n10 HSMA RX n10 HSMA TX p11 HSMA 11 n11 HSMA 11 HSMA 12 HSMA 12 n12 12 HSMA 13 HSMA 13 TX 13 13 HSMA TX p14 HSMA 14 TX n14 14 5 LVDS bit 5n or CMOS I O LVDS TX bit 6 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS TX bit or CMOS I O LVDS RX bit 6n or CMOS I O LVDS TX bit 7 or CMOS I O LVDS bit 7 or CMOS I O LVDS TX bit 7n or CMOS I O LVDS RX bit 7n or CMOS I O LVDS TX or CMOS I O LVDS or CMOS or differential clock input LVDS RX or CMOS I O LVDS or CMOS or differential clock input LVDS TX bit 8 or CMOS I O LVDS bit 8 or CMOS I O LVDS TX bit 8n or CMOS I O LVDS RX bit 8n or CMOS I O LVDS TX bit 9 or CMOS I O LVDS bit 9 or CMOS I O LVDS TX bit 9n or CMOS I O LVDS RX bit 9n or CMOS I O LVDS TX bit 10 or CMOS I O LVDS RX bit 10 or CMOS I O LVDS TX bit 10n or CMOS I O LVDS RX bit 10n or CMOS I O LVDS TX bit 11 or CMOS I O LVDS RX bit 11 or CMOS I O LVDS TX bit 11n or CMOS I O LVDS RX bit 11n or CMOS I O LVDS TX bit 12 or CMOS I O LVDS RX bit 12 or CMOS I O LVDS TX bit 12n or CMOS I O LVDS RX bit 12n or CMOS I O LVDS TX bit 13 or CMOS LVDS bit 13 or CMOS I
128. ncy applied to PLL CLKIN signal At this stage any arbitrary changes to PLL_CLKIN is not allowed as users can only change the PLL_CLKIN clock frequency if the SATA interface is not in use The I O standard for the three clock generators 15 set as LVDS which 18 non configurable An overall block diagram of the external clock generator is shown below in Figure 5 25 132 Terasic DE4 User Manual www terasic com www terasic com ANU S RYAN HSMB REFCLK I 1 19 CLK1 PR1 CLK1 OD2 CLK1 OD1 HSMA REFCLK CLK1 OS1 CLK1 OSO CLK1 CE CLK2 PR1 CLK2 PRO CLK2 OD2 CLK2 ODO CLK2 081 CLK2 CE CLK2 RSTn CLK1 PRO CLK1 000 CLK1 RSTn CLK2 OD1 CLK2 OSO M CLK3 CLK3 PRO CLK3 OD2 CLK3 001 CLK3 ODO CLK3 081 CLK3 OSO CLK3 CE CLK3 RSTn c Figure 5 25 External Clock Generator Block Diagram PLL CLKIN SATA REFCLK B The EXT PLL CTRL IP Port Description This section describes the operation for the EXT instruction hardware port Figure 5 26 shows the EXT CTRL instruction block diagram connected to the MAX EPM2210 device The EXT controller module is defined by a host device the Stratix IV GX FPGA and a slave device the MAX II EPM2210 Through the I2C bus interface the 133 Terasic DE4 User Manual www terasic com www terasic com ANU EXT P
129. nd Functions Schematic ES Stratix IV GX Pin Description I O Standard Signal Name Number UART TXD Receiver Output 2 5 V PIN AN34 UART CTS Receiver Output 2 5 V PIN AN35 UART RXD Transmitter Driver Input 2 5 V PIN AH32 UART RTS Transmitter Driver Input 2 5 V PIN AH33 Note for Table 2 28 RS 232 signals are level shifted from 2 5 V FPGA to 3 3V RS 232 64 Terasic DE4 User Manual www terasic com www terasic com 2 15 FLASH Memory The DEA development board features 64MB PC28F512P30BFA CFI compliant NOR type flash memory device which 1s part of the shared FMS Bus consisting of flash memory SSRAM and the Max II CPLD EPM2210 System Controller The single synchronous flash memory with 16 bit data bus supports 4 word 8 word 16 word and continuous word burst mode provides non volatile storage that can be used for configuration as well as software storage The memory interface can sustain output synchronous burst read operations at 40 MHz with zero wait states The device defaults to asynchronous page mode read when power up 15 initiated or returned from reset This device 15 also used to store configuration files for the Stratix IV FPGA where the MAX II CPLD EPM2210 can access flash for FPP configuration of the FPGA using the PFL Megafunction Table 2 29 hsts the flash pin assignments signal names and functions Table 2 29 Flash Memory Pin Assignments Schematic Signal Names and Functions Schem
130. nect USB ports for the USB Device demonstration 5 3 Ethernet Simple Socket Server The Stratix IV GX device on the DEA consists of built in serializer deserializer SERDES circuitry for high speed LVDS interfaces to support Gigabit Ethernet Ethernet has been the dominant 116 Terasic DE4 User Manual www terasic com www terasic com AN DTE RAN networking protocol providing a simple cost effective option for backbone and server connectivity Gigabit Ethernet builds on top of the Ethernet protocol with speed up to 1000 Mbps or 1 gigabit per second Gbps In this demonstration we will illustrate how to create a simple socket server generated in Nios II using the Gigabit Ethernet devices equipped on the DE4 board As indicated in the block diagram in Figure 5 11 the Nios II processor is used to communicate with the client via Marvell 88 1111 Ethernet Transceiver CAT 5e Cable t Gateway with DHCP Stratix IV Ethernet Driver Nios 1 Simple Socket Server Figure 5 11 Block diagram of the Ethernet demonstration Part of Nios II NicheStack TCP IP Network Stack is a software suite of networking protocols designed to provide an optimal solution for designing network connected embedded devices with the Nios II processor A telnet client application is used to communicate with the Simple Socket Server issuing commands over a TCP IP socket to the Ethernet connected NicheStack TCP IP Stack running on the DE4 board wit
131. ng address in the Address box e Specify the number of bytes to be written in the Length box If the entire file is to be loaded a check mark can be placed in the File Length box instead of giving the number of bytes e To initiate the writing of data click on the Write a File to Memory button When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Sequential Read function is used to read the contents of the serial configuration device and place them into a file as follows e Specify the starting address in the Address box e Specify the number of bytes to be copied into a file in the Length box If the entire contents of the serial configuration device are to be copied then place a check mark in the Entire Memory box e Press Load Memory Content to a File button When the Control Panel responds with the standard Windows dialog box ask for the destination file users can specify the desired file the usual manner 79 DE4 User Manual www terasic com www Lterasic com STRATIX IV VC SOJA o Miu i WES 1 1 i 1 4 LEITET am a eo mii ond a wn cm 1 20000000 worDs 1 meoo Address ET SEG Power M eee
132. nstration on the ETHERNETO in SGMII mode e Project directory DE4 board update portal Nios II Project workspace ded board update portalsoftware Web Server Bit stream used DEA board update portal sof Website content zip file zipfs zip de4 board update portaloftware Web ServerWweb server syslibwo zipfs zip e aunch Quartus II and download the web server demo bit stream into FPGA e Launch Nios II IDE and open the Nios II Project workspace Download the website content zip file into FLASH memory using the Flash Programmer in NIOS II IDE 148 Terasic DE4 User Manual www terasic com www terasic co m AN DTE RAN Plug a CATS cable into the Ethernet port J12 on the DE4 e Click on the RUN button in NIOS II IDE window to run this project e Launch your web browser Use Internet Explorer 7 0 or later e Input the IP into your browser You will see the brand new DE4 web page on your computer illustrated in Figure 5 39 B Nios IL IDE Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean gt Nios Example Web Server Windows Internet Explorer id aaa 243 _ Jer r3 C Documents and SettingsWUserLocal Settings Temp Rar EXO1 110 program_flash html BRO REO RAD TAD HAW x Share Browser WebEx x Goo
133. nts of this website are contained in a read only zip filing system Want to replace this with AD DA Data your own custom web content Follow these steps to do so Conversion 1 Open the file ro zipfs zip in your Nios Il IDE system library project that this web server was built with Add remove your custom web content For best results always include index html and not found html files in the root Other files may follow a directory structure Savethe zip file with the additional files Make sure that compression is OFF Re compile your system library amp re program flash as described in the web server example dacian raarima tt fila Figure 5 39 DE4 Webserver IE Window 149 Terasic DE4 User Manual www terasic com www terasic com 5 9 Serial ATA SATA In this demonstration we illustrate how to use the DE4 board to verify the functionality of SATA host device ports A and B by testing the transmitter and receiver signals SATA cables provided in the kit package are required in this demonstration as it is attached to SATA host and device ports while an associated design 15 loaded into the FPGA The receiver design will synchronize and check for known pattern If there are errors on the RX channel the LED 3 0 for that channel will remain off indicating an error condition If there are zero errors LED 3 0 are illuminated By default the test 15 run at 6 Gbps B Demonstration Source C
134. o bypassing the JTAG signals as shown in Figure 2 16 TDI DE4 Board B 15 0 gt LO HSMC PCle gt TDI a ATERA CStrat x Jv p Port B Connector SW8 OFF ON ON ON Figure 2 15 JTAG chain for a daughter card uses JTAG connected to HSMC port A of the DEA 28 Terasic DE4 User Manual www terasic com www terasic com DE4 Board TDI and TDO signals Bypassed abe TDI TDO gt TDI TDI ATERA HSMC HSMC PCle Stratix v Port A Port B Connector ON ON ON ON Figure 2 16 JTAG chain for a daughter card JTAG not used connected to HSMC port A of the DEA B Multi FPGA high capacity platform through HSMC The DEA offers a choice of two Stratix GX devices EPASGX230 and EPSGX530 which offer logic elements LEs up to 228 000 and 531 200 respectively to provide the flexibility for users to select a suitable device in terms of design capacity In situations where users design exceeds the capacity of the FPGA the HSMC interface can be used to connect to other FPGA system boards creating a multi FPGA scalable system Figure 2 17 illustrates a connection setup between two DE4 boards by connecting through port B and Port A of HSMC connectors using Samtec high speed cable Notice the JTAG switch SW8 configuration set
135. o drive the Stratix IV PLL circuit through the GCLK and RCLK networks Alternatively PLLs through the GCLK and RCLK networks or from dedicated connections on adjacent top bottom and left right PLLs can also drive the PLL circuit The clock outputs of Stratix IV FPGA are derived from various interfaces notably the HSMC and the SMA connectors 54 Terasic DE4 User Manual www terasic com www terasic com B Stratix IV GX FPGA Transceiver Clock Inputs The transceiver reference clock inputs for the serial protocols supported by the Stratix IV GX FPGA transceiver channels include the PCI Express PIPE SATA and through the SMA connectors The DE4 uses three programmable low jitter clock generators with default clock output of 100MHz and an I O standard of LVDS that is non configurable The clock generators are programmed Max II CPLD to generate the necessary clocks for the Stratix IV GX transceiver protocols and interfaces such as SATA and HSMC The PCI Express PIPE transceiver reference clock 15 generated from the PCIe connector The clock frequency for the programmable clock generators can be specified by using the DEA control panel DE4 system builder or the external clock generator demo provided Note that signals CLKIN and SATA REFCLK share the same clock generator which would lead to the same output frequency for both signals The associated pin assignments for clock buffer and SMA connectors to FPGA I O pins are sh
136. o the internal RAM of FPGA and controls the user register that switches the function which inverts the image data from the internal RAM B PC Application Design The software design defines some constant based on FPGA design as shown below define PCIE VID Er Sdefine PCIE DID 1 define IMAGE WIDTH 320 define IMAGE HEIGH 240 1 DEMO PCIE USER PCIE Sdefine DEMO IMAGE REG ADDR Ox 10 define DEMO IMAGE ADDR The vender ID is defined as 0x1172 and the device ID is defined as 001 The image dimension is defined as 320x240 The register address is Ox 10 and memory address is 0x00 A class PCIE is designed to encaptulate the DLL dynamic loading for TERASIC_PCIE DLL A PCIE instance is created with the name m hPCIE To open a connection with FPGA the function 15 called m hPCIE OpeniPCIE VID PCIE DID 0 0 first matched board 175 Terasic DE4 User Manual www terasic com www terasic com To download raw image from PC to FPGA memory the function 15 called m hPCIE DmaWriteiDEMO IMAGE DATA ADDE plmage nlmagesize j where pImage is a pointer of the image raw data and the nImageSize specifies the image size In this reference design nImageSize 320x240x3 byte To start the image process the function is called m hPCIE Write32 DEMO PCIE USER BAR DEMO IMAGE REG ADDR 1 The image process is started whenever the register is written with any val
137. ode e Quartus Project directory DE4 SATA LOOPBACK TEST e FPGA Bit stream SATA LOOPBACK TEST sof B Demonstration Setup Check that Quartus II and NIOS II are installed on your e Make sure a SATA cable provided in the DEA package is connected between SATA host A and SATA device A Similarly a SATA cable 15 connected between SATA host B and SATA device B as shown in Figure 5 40 Power on the DEA board e Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e Program the DEA using the 4 SATA LOOPBACK TEST sof through Quaruts programmer Press RESET pushbutton 0 of board to initiate the verify process LED 3 0 will flash once to indicate the loopback test passed 150 Terasic DE4 User Manual www terasic com www terasic com wane i d Y Soe 4 NM np 1 ELE SLE ATN EAR 27 lt LTM4601V T pModule M N3633E E 0830 438335 E 0830 330M 4 un l2 MEM a Em PROGRAM mmm TTTITEIT TIT 1111 EXPRESS Figure 5 40 Serial loopback design setup 5 10 High Speed Mezzanine Card HSMC The HSMC loopback demonstration reference design observes the traffic flow with a HSMC loopback adapter which provides a quick way to implement your own design utilizing the transceiver s
138. oftwareWroject Usb Host The NIOS II source code list is shown in Figure 5 4 Users can modify ferasic debug h to configure the debug message Note the debug message may affect the USB performance and possibly cause malfunction to the demonstration 108 Terasic DE4 User Manual www terasic com www terasic com m altera components E m usb host Includes tf Debug berasic Fat FAT File System E lh FatFilesvstem h FatInternal h FatFilesstem c lt FatInternal c berasic usb isp1761 class B j usb disk ES usb disk Eransport h USB mass storage Class Driver h usb disk h usb disk Eranspart c usb disk c usb mause usb mause h HID USB Mouse Class Driver ic usb mause c usb class h usb class c hal 81 config h 1 61 hal 2 ispl761 hast regisker h ispl761 register h 15 1 761 kransport h 6 15 1761 config c ispl761 hal 2 15 1 7261 transport usb hast usb h usb hub h usb pratacal h c usb host c Host Controller ic usb hub c ic usb_protocal c terasic debug h ul T n ISP1761 HAL Hardware Abstration Layer E yr E USB Protocol includes h hj n main c E Main Ferasic debug c
139. oject Name 4 CLOCK Slide Switch x 4 LEDx 8 7 Segement x 2 Button x 4 DIP Switch x 8 Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM 1 2 RS 232 Programmable PLL Programmable PLL Ethernet x 4 5 REFCLK LIDDR2 SODIMM 1 110082 SODIMM 2 Sata Host 0 Sata Host 1 O Sata Device 0 O Sata Device 1 PLL_CLKIN SATA_REFCLK OPCle HSMB REFCLK GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 D5M 5M Pixel Camera ADA High Speed ADC DAC Prefix Name Prefix Name GPIO 1 Header HSMC B Transceiver x 8 4 3 LCD and Touch DVI TX RX Prefix Name Prefix Name Default Setting Load Setting Save Setting Figure 4 5 External Programmable PLL B GPIO Expansion Users can connect GPIO expansion card onto either GPIO 0 header or the GPIO 1 header located on the DE4 board as shown in Figure 4 6 Select the daughter card you wish to add to your design under the appropriate GPIO header where the daughter card is connected to The system builder will automatically generate the associated pin assignment including the pin name pin location pin direction and IO standard If a customized daughter board is used users can select GPIO Default followed by changing pin name pin direction and IO standa
140. on 0 IO 17 3 0 V PIN AM10 GPIOO D18 GPIO Expansion 0 1 0 18 3 0 V PIN AL10 GPIOO D19 GPIO Expansion 0 10119 3 0 V PIN 8 GPIOO D20 GPIO Expansion 0 IO 20 3 0 V PIN ALS GPIOO 021 GPIO Expansion 0 10 21 3 0 V PIN AK8 GPIOO D22 Expansion 0 10122 3 0 V PIN AJ11 GPIOO D23 GPIO Expansion 0 IO 23 3 0 V PIN AK7 GPIOO D24 GPIO Expansion 0 1 24 3 0 V PIN AJ5 GPIOO D25 GPIO Expansion 0 IO 25 3 0 V PIN AH12 GPIOO D26 GPIO Expansion 0 10 26 3 0 V PIN AG10 GPIOO D27 GPIO Expansion 0 10 27 3 0 V PIN AG13 38 Terasic DE4 User Manual rasic com www terasic com GPIOO D28 GPIOO D29 GPIOO D30 GPIOO D31 GPIOO 032 GPIOO 033 GPIOO D34 GPIOO 035 Schematic Signal Name GPIO1 DO GPIO1 D1 GPIO1 D2 GPIO1 D3 GPIO1 D4 GPIO1 D5 GPIO1 D6 GPIO1 D7 GPIO1 D8 GPIO1 D9 GPIO1 D10 GPIO1 D11 GPIO1 D12 GPIO1 D13 GPIO1 D14 GPIO1 D15 GPIO1 D16 GPIO1 D17 GPIO1 D18 GPIO1 D19 GPIO1 D20 GPIO1 D21 GPIO1 D22 GPIO1 D23 GPIO1 D24 GPIO1 D25 GPIO1 D26 GPIO1 D27 GPIO1 D28 GPIO1 D29 Expansion 0 10 28 Expansion 0 10 29 GPIO Expansion 0 1030 GPIO Expansion 0 IO 31 GPIO Expansion 0 10 32 GPIO Expansion 0 IO 33 Expansion 0 10 34 Expansion 0 lO 35 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V PIN AG9 PIN AF11 PIN AT9 PIN AF10 PIN AD10 PIN AP10 PIN AD12 PIN AD13 Table 2 13 GPIO Expansion Header JP4 Pin Assignments Schematic Signal Names and Functions Descrip
141. ontrollers are designed running with 10 MHz clock which is generated by the PLL The NIOS program is running in the on chip memory 128 Terasic DE4 User Manual www terasic com www terasic com FPGA EB 50 2 On Chip Memory lt Controller DDR2 gt DDR2 Controller SDRAM 1 JTAG 1 System Intercoment Fabric Timer CEE Figure 5 22 Block diagram of the DDR2 demonstration The system flow is controlled by a NIOS program First the NIOS program writes test patterns into the whole IGBytes SDRAM Then it calls NIOS system function alt dache flush all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal B Altera DDR2 SDRAM High Performance Controller To use Altera DDR2 controller users need to perform three major steps 1 Create correct pin assignment for DDR2 2 Setup correct parameters in DDR2 controller dialog 3 Execute TCL files generated by DDR2 IP under your Quartus project The following section describes some of the import issues in support of the DDR2 controller configuration On the Memory_Setting tab in order to achieve 400 MHz clock frequency reference clock frequency of 50 MHz should be used which can
142. or CMOS I O LVDS TX bit 5 or CMOS I O LVDS bit 5 or CMOS I O LVDS TX bit 5n or CMOS I O 34 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 4 V PCML 1 8 V 1 8 V 2 5 V 2 5 V 2 5 V 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V PIN E39 PIN K36 PIN L38 PIN K37 PIN L39 PIN M36 PIN N38 PIN M37 PIN N39 PIN M19 PIN L19 PIN AF29 PIN AC34 PIN AC26 PIN AC31 PIN AD26 PIN AC32 PIN AB27 PIN AJ32 PIN AB28 PIN AK33 PIN AB30 PIN AH34 PIN AB31 PIN AH35 PIN AD27 PIN AJ34 PIN AE27 PIN AJ35 PIN AD28 PIN AK34 PIN AD29 PIN AK35 PIN AE28 PIN AN30 PIN AE29 PIN AP30 PIN AE26 PIN AM34 PIN AF26 www terasic com 80 83 84 85 86 89 90 91 92 95 96 97 98 101 102 103 104 107 108 109 110 113 114 115 116 119 120 121 122 125 126 127 128 131 132 133 134 137 138 139 140 143 HSMA RX n5 HSMA TX p6 HSMA HSMA TX n6 HSMA RX n6 HSMA TX p7 HSMA 7 TX n7 HSMA RX n7 HSMA OUT HSMA CLKIN 1 HSMA OUT HSMA CLKIN
143. owerMeasure elf B Demonstration Setup e Make sure Quartus and NIOS II are installed on your Power on the DEA board e Connect USB Blaster to the DEA board and install USB Blaster driver if necessary e Execute the demo batch file test bar under the batch file folder PowerMeasureMlemo batch e After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e The program will display current power consumption information as shown in Figure 5 31 The information is updated every two seconds 140 Terasic DE4 User Manual www terasic com www Lterasic com Nios EDS 9 1 Temperature 1 46 45 CUCCD_PLL 1FFFF319H Neg UolDrop 8 8008088 U Current 9 2080906D3H 1 1 0 002204 lt 0 gt Current UCCIOPD 1FFFFE55H Neg 1 UolDrop 8 800808084U Current UCCHIP 2008369 7H 1 UolDrop 8 0000524U Current CUCC1P8_34R 1FFFFF1 H Neg 1 UolDrop 8 00080084U Current CHSMA_UCCIO 1FFFFDSAH Neg VolDrop 4 666808 lt U gt Current CUCC1IP8_78R 2666665DH Pos 1 UolDrop 8 0000884U Current CUCCA_PLL 266 QADFH Pos 1 UolDrop 8 0000184U Current UCCL 28888458 1 UolDrop 8 800080844U Current UolDrop 8 8008088 U Current 9 20090493H Pos Current 1 0 002202 lt 0 gt Current EGPIO UCCIOPD 1FFFFF15H Neg Int UolDrop 8 0008004U Curr
144. own in Table 2 22 Table 2 22 Clock Inputs Outputs Pin Assignments Schematic Signal Names and Functions Board Schematic Stratix IV GX Description I O Standard Reference Signal Name Pin Number OSC 50 B2 MEE 727 AC35 input for bank 2C OSC 50 B3 E clock input for bank 1 8 V AV22 OSC 50 B4 E clock input for bank 18 V AV19 OSC 50 B5 clock input for bank 3 0 V OSC 50 B6 mE clock input for bank 2 5 V AB6 OSC 50 B7 mE clock input for bank 1 8 V 19 GCLKIN 100MHz or SMA CLKIN or 1 8 V PIN A21 GCLKOUT clock input GCLKOUT FPGA Single ended clock output 1 8 PIN AH19 Programmable 100MHz PLL CLKIN p 2 5 V LVDS PIN B22 differential clock input PLL CLKIN n Programmable 100MHz c LVDS PIN A22 differential clock input J15 SMA CLKIN p SMA differential clock input 2 5 V or LVDS PIN B23 55 DE4 User Manual www terasic com www terasic com J19 SMA CLKIN n SMA differential clock input 2 5 V or LVDS PIN A23 SMA GXBCLK p SMA IADSCPIVOT reference LVDS PIN W2 clock input 917 SMA GXBCLK n SMA reference LVDS clock input SATA REFCLK p SATA reference clock input LVDS PIN AN2 SATA REFCLK n SATA reference clock input LVDS PIN AN1 REFCLK p transceiver LVDS PIN J38 reference clock input HsMA REFCLK MCA transceiver LVDS 39 reference clock input REF
145. put output 158 HSMB CLKIN n2 OF LVDS or 2 5 V PIN W5 differential clock input Note for Table 2 10 signals HSMC_SDA and E HSMC SCL level shifted from 3 3V FPGA to 1 8V HSMC Table 2 11 HSMC Port A Pin Assignments Schematic Signal Names and Functions Stratix IV GX HSMC Pin Schematic Signal Name Description Standard Pin Number 1 E 2 E 3 E E 4 5 6 7 E 8 2 E 9 3 E 10 11 12 13 14 15 16 17 HSMA GXB TX p3 Transceiver TX bit 3 1 4 V PCML PIN B36 18 HSMA GXB RX p3 Transceiver RX bit 3 1 4 V PCML PIN C38 19 HSMA TX Transceiver TX bit 3n 1 4 V PCML PIN B37 20 HSMA RX n3 Transceiver RX bit 3n 1 4 V PCML PIN C39 21 HSMA GXB TX p2 Transceiver TX bit 2 1 4 V PCML PIN D36 22 HSMA p2 Transceiver RX bit 2 1 4 V PCML PIN E38 23 HSMA GXB TX n2 Transceiver TX bit 2n 1 4 V PCML PIN D37 Terasic DE4 User Manual rasic com 33 www terasic com 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 47 48 49 50 53 54 55 56 59 60 61 62 65 66 67 68 71 72 73 74 77 78 79 HSMA GXB RX n2 HSMA GXB TX 1 HSMA GXB 1 HSMA GXB TX HSMA GXB RX ni HSMA GXB TX HSMA GXB RX HSMA GXB TX HSMA GXB E HSMC SDA E HSMC SCL HSMC TCK
146. r in the DEA System CD Users can copy the whole folder to a host computer without installing the utility Before using the DE4 System Builder execute the DEA SystemBuilder exe on the host computer as appears in Figure 4 2 92 DE4 User Manual www terasic com www Terasic DE4 System Builder V 100 JNO RAN UNIVERSITY P R www terasic com Programmable PLL HSMA REFCLK HSMB REFCLK PLL CLKIN SATA REFCLK GPIO Expansion GPIO 0 Header 5M Pixel Camera Prefix Name GPIO 1 Header LTM 43 LCD and Touch Prefix Name System Configuration Board Type 4 230 Project Name 4 CLOCK LEB 8 Button x 4 OSMA USB OTG Fan Control Flash 64MB SSRAM 2MB Programmable PLL O DDR2 5 1 O Sata Host 0 O Sata Device 0 HSMC Expansion Slide Switch x 4 T Segement x 2 DIP Switch x 8 Temperature Power Measurement SD CARD EEPROM RS 232 Ethernet x 4 O DDR2 SODIMM 2 O Sata Host 1 O Sata Device 1 HSMC A Transceiver x 4 ADA High Speed ADCIDAC Prefix Name HSMC B Transceiver x 8 DVI FullHD Prefix Name Default Setting Load Setting Save Setting Figure 4 2 The 4 System Builder window B Select Board Type and Input
147. r Manual www terasic com www terasic com HSMC Port Present HSMC Dio Port A Present RXD1 ZART RADARO Expansion 0 IO 7 UART_TXD GPIO TXD1 Expansion 1 IO 9 USB D15 Jack Mini USB AB Port D14 USB TYPE A port Top USB D13 USB TYPE A port Bottom USB Illuminates when the HSMC port B has a board or cable plugged in such that pin 160 becomes grounded Driven by the add in card Illuminates when the HSMC port A has a board or cable plugged in such that pin 160 becomes grounded Driven by the add in card 5 when RS232 receives data or Expansion 0 IO 7 is transmits or receives illuminates when RS232 transmit data or GPIO Expansion 1 10 9 is transmits or receives Illuminates when USB Jack Mini USB port has a device when the USB TYPE port has a device when the USB TYPE port has a device 2 4 General User Input Output B Push buttons The DEA board includes six push buttons that allow you to interact with the Stratix IV GX device Each push button provides a high logic level or a low logic level when it is not pressed or pressed respectively Table 2 4 lists the board references signal names and their corresponding Stratix IV GX device pin numbers Table 2 4 Push button Pin Assignments Schematic Signal Names and Functions Board Schematic T Stratix IV GX Description Reference Signal Name Standard Pin Number PB1 BUTTO
148. r write operation the PCIe IP issues a write signal accompany with the address to be written A 32 bit data is written to the corresponding address with a data enable signal of write operation All the write commands are issued on the same clock cycle Table 6 1 lists the associated port names along with the description Table 6 1 Single Cycle Transaction Signals of Terasic PCIe IP Name Type Polarity Description oCORE CLK Output Clock The reference clock output of PCle local interface oSC RD ADDR 11 0 Output Address bus of read transaction It is a 32 bit data per address iSC RD DATA 31 0 Input Read data bus oSC RD READ Output High Read signal 15 RD DVAL Input High Read data valid oSC WR ADDR 11 0 Output Address bus of write transaction It is a 32 bit data per address oSC WR DATA 31 0 Output Write data bus oSC WR WRITE Output High Write signal 155 Terasic DE4 User Manual www terasic com www terasic com oCORE oSC RD READ N l iSC_RD_DVAL 1 X Figure 6 2 Read transaction waveform of the PCle basic I O interface l l l 2 28 1 4 5 oCORE A Y AY YY X Figure 6 3 Write transaction waveform of the PCle basic I O interface B PCI Express DMA Transaction To support greater bandwidth and to improve latency Terasic PCIe IP provides a high speed DMA channel with
149. rasic DE4 User Manual rasic com 45 Standard SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Differential 1 8 V SSTL Class Differential 1 8 V SSTL Class SSTL 18 Class SSTL 18 Class SSTL 18 Class Number PIN J12 PIN F12 PIN J13 PIN H13 PIN H14 PIN E13 PIN F13 PIN G14 PIN D13 PIN E14 PIN F14 PIN P16 PIN N16 PIN P17 PIN N17 PIN M17 PIN J16 PIN L13 PIN K16 PIN K13 PIN L16 PIN J17 PIN K17 PIN H17 PIN B16 PIN C16 PIN A16 PIN E16 PIN C15 PIN D15 PIN G15 PIN F15 PIN G16 www terasic com M2 0082 0019 DDR Data 19 SSTL 18 Class PIN D16 M2 0082 0023 DDR Data 23 SSTL 18 Class PIN G17 M2 0082 0024 DDR Data 24 SSTL 18 Class PIN C17 M2 0082 0028 DDR Data 28 SSTL 18 Class PIN C18 M2 DDR2 DQ25 DDR Data 25 SSTL 18 Class PIN E17 M2 DDR2 DQ29 DDR Data 29 SSTL 18 Class PIN D18 M2 DDR2 DM3 DDR2 Data Mask 3 SSTL 18 Class PIN F17 M2 DDR2 095 n3 D
150. rasic com OTG A 17 1 D 31 0 DI31 0 SW4 Jack Mini USB AB SW4 0TG MODE ON HOST NOE gt a OFF DEVICE OTG HC Stratix IV pc ISP1761 d n a p L Mn OTG HC DREQ Ls HC DACK OTG DC DREQ OTG DC DACK CLKIN USB TYPE A DOUBLE USB 12MHz 1 1 Figure 2 21 Connections between the USB Stratix IV GX device Detailed information of the ISP1761 device can be found in its datasheet and programming guide both documents are available from the manufacturer s web site or in the Datasheet USB folder of the DE4 System CD Two complete examples for host and device applications each can be found in Sections 5 land 5 2 These demonstrations provide software drivers for the Nios II processor Table 2 17 default host or peripheral setting for port 1 of the ISP1761 SW4 Setting Connectors ON Port 1 set to host OFF Port 1 set to device Table 2 18 USB 2 0 OTG Pin Assignments Schematic Signal Names and Functions Schematic Stratix IV GX Pin Description Standard Signal Name Number OTG A1 OTG Address 1 1 8 V PIN K26 OTG A2 OTG Address 2 1 8 V PIN P25 OTG A3 OTG Address 3 1 8 V PIN N25 OTG A4 OTG Address 4 1 8 V PIN R24 OTG A5 OTG Address 5 1 8 V PIN P24 OTG A6 OTG Address 6 1 8 V PIN M25 OTG A7 OTG Address 7 1 8 V PIN L25 OTG A8 OTG Address 8 1 8 V PIN N23 OTG A9 OTG
151. rd Pin Number Name HEX1 SEG1 DO User Defined 7 Segment Display Driving a logic 0 on 2 5 PIN 1 HEX1 SEG1 01 the port turns the 7 segment signal ON Driving a 2 5 V PIN F31 HEX1 SEG1 D2 logic 1 on the I O port turns the 7 segment signal 2 5 V PIN G31 HEX1 SEG1 03 OFF 2 5 V PIN C34 HEX1 SEG1 D4 2 5 V PIN C33 HEX1 SEG1 D5 2 5 V PIN D33 HEX1 SEG1 D6 2 5 V PIN D34 HEX1 SEG1 DP 2 5 V PIN AL35 Terasic DE4 User Manual www terasic com www terasic com HEXO SEGO DO 2 5 V PIN L34 HEXO SEGO D1 2 5 V PIN M34 HEXO SEGO D2 2 5 V PIN M33 HEXO SEGO D3 2 5 V PIN H31 HEXO SEGO D4 2 5 V PIN J33 HEXO SEGO D5 2 5 V PIN 135 HEXO SEGO D6 2 5 V PIN K32 HEXO SEGO DP 2 5 V PIN AL34 2 5 High Speed Mezzanine Cards The DE4 development board contains two HSMC interfaces called port A and port B The HSMC interface provides a mechanism to extend the peripheral set of an FPGA host board by means of add on cards which can address today s high speed signaling requirement as well as low speed device interface support The HSMC interfaces support clock outputs and inputs high speed serial I O transceivers and single ended or differential signaling Both the HSMC interfaces connected to the Stratix IV GX device are female HSMC connectors with each connector having a total of 172pins including 121 signal pins 120 signal pins 1 PSNTn pin 39 power pins and 12 ground pins The HSMC connector is based on the Samtec 0 5 mm pitch surface mo
152. rd according to the specification of the customized daughter board 96 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 100 System Configuration ADEA j d UNIVERSITY Board Type DE4 230 PROGRAM Project Name DE4 CLOCK Slide Switch x 4 LEDx 8 7 Segement x 2 Button x 4 DIP Switch x 8 v Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM SSRAM 2MB RS 232 Programmable PLL Ethernet x 4 HSMA REFCLK O DDR2 5 1 O DDR2 SODIMM 2 HSMB REFCLK O Sata Host 0 Sata Host 1 O Sata Device 0 O Sata Device 1 CLKIN SATA REFCLK O PCle Programmable PLL HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 5M Pixel Camera ADA High Speed ADC DAC Prefix Name Prefix Name GPIO 1 Header HSMC B Transceiver x 8 LTM 4 3 LCD and Touch TX RX Prefix Name Prefix Name Default Setting Load Setting Save Setting Figure 4 6 GPIO Expansion Group The Prefix Name is an optional feature which denotes the pin name of the daughter card assigned in your design Users may leave this field empty Note If the same GPIO expansion card is selected under GPIO 0 and GPIO 1 a prefix name is required to avoid pin name duplication as shown in Figure 4 7
153. rically Erasable PROM EEPROM is equipped on the DEA which is configured through a 2 wire serial interface The device is organized as one block of 256 x 8 bit memory The detailed pin description between the Stratix IV GX FPGA and EEPROM is shown below in Table 2 31 Table 2 31 EEPROM Pin Assignments Schematic Signal Names and Functions Schematic M Stratix IV GX Pin Description I O Standard Signal Name Number EEP SCL Serial Clock 2 5 V PIN G33 EEP SDA Serial Address Data 2 5 V PIN F33 2 18 Temperature Sensor The DE4 is quipped with a temperature sensor MAX1619 which provides temperature sensing and over temperature alert These functions are accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Stratix IV GX device The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two wire SMBus which is connected to the Stratix IV GX FPGA In addition the 7 bit POR slave address for this sensor is set to 00110005 An optional 3 pin 12V fan located on J10 of the DE4 board is intended to reduce the temperature of the FPGA When the temperature of the FPGA device 15 over the threshold value set by the users the fan will turn on automatically The pin assignments for the associated interface are listed in Table 2 32 68 Terasic DE4 User Manual www terasic com www terasic com Table 2 32 Temperature Sensor Pin Assignments Schemat
154. rm of the PCle DMA channel memory mapping mode 4 1 oCORE 1 oDMARD ADDR K gt lt FIFO ID I oDMARDDATAK lt 00 X Di X D2 X X gt 2 9 1 1 oDMARD READ 51 l I ot a I oDMARD RDVALID LE Y 1 2 clock cycles oFIFO_MEM_SEL l l High Level Figure 6 6 Read transaction waveform of the PCle DMA channel on FIFO link mode 158 Terasic DE4 User Manual www terasic com www terasic com I I N V NV NV Ny Ny E I oDMAWR ADDR EK FIFO ID oDMAWR DATA lt DO lt Di 02 03 04 gt oDMAWR WRITE 7 N I oFIFO MEM SEL Figure 6 7 Write transaction waveform of the PCle DMA channel on FIFO link mode 6 3 PC PCI Express System Design The DE4 CD contains a PC Windows based SDK to allow users to develop their software application The SDK demonstrations de4_ lt Stratix device SDK includes PCI Express Driver e PCI Express Library kernel mode driver requires users to modify the PCIe vender ID VID and device ID DID in the driver INF file to match the design in the FPGA where Windows searches for the associated driver Note the kern
155. s Push buttons 4 user defined inputs Normally high generates one active low pulse when the switch is pressed Slide switches e 4 slide switches for user defined inputs Whena switch is set to the DOWN or UP position it causes logic or respectively On Board Clocking Circuitry 50MHz 100MHz oscillator 2 SMA connector for external transceiver clock input connector for LVDS clock input output 2 SMA connectors for clock output e SMA connector for external clock input 10 DE4 User Manual www terasic com rasic com Four Serial ATA ports SATA 3 0 standard 6Gbps signaling rate Four Gigabit Ethernet ports e Integrated 1 25GHz SERDES PCI Express x8 edge connector e Support connection speed of at 2 5Gbps lane to Gen2 at 5 0Gbps lane e Connection established with PC motherboard with x8 or x16 PCI Express slot Two High Speed Mezzanine Card HSMC e 2 female HSMC connectors e Total of 12 pairs CDR based transceivers at data rate up to 8 5Gbps e Total 38 LVDS transmitter channels at data rate up to 1 6Gbps and 36 LVDS receiver channels I O voltage 2 5V Two 40 pin expansion headers 72 FPGA I O pins as well as 4 power and ground lines are brought out to two 40 pin expansion connectors e 40 header is designed to accept a standard 40 ribbon cable used for IDE hard drives Compatible with I O standard 3 3V 11 Terasic D
156. s 2 5 V PIN D31 FLASH CLK Clock 2 5 V PIN E22 FLASH RESET n Reset 2 5 V PIN D21 FLASH CE n Chip enable 2 5 V PIN F23 FLASH OE n Output enable 2 5 V PIN 21 FLASH WE n Write enable 2 5 V PIN R20 FLASH ADV n Address valid 2 5 V PIN 21 FLASH RDY BSY n Ready 2 5 V PIN 21 FLASH WP n Write protect 2 16 SSRAM Memory The IS6INVP102418 Synchronous Static Random Access Memory SSRAM device featured on the DE4 development board is part of the shared FMS Bus which connects to flash memory SSRAM and the MAX II CPLD EEPM2210 System Controller This device is a Zero bus turnaround ZBT 2MB SRAM device with a 16 bit data bus providing no bus latency synchronous burst SRAM with a simplified interface that fully uses available bandwidth by removing the turnaround cycles between read and write operations Table 2 30 lists the SSRAM pin assignments signal names relative to the Stratix IV GX device in terms of I O setting 66 Terasic DE4 User Manual www terasic com www terasic com Table 2 30 SSRAM Memory Pin Assignments Schematic Signal Names and Functions Schematic 2 Stratix IV GX Pin Description Standard Signal Name Number FSM A1 Address bus 2 5 V PIN G22 FSM A2 Address bus 2 5 V PIN G23 FSM A3 Address bus 2 5 V PIN A25 FSM A4 Address bus 2 5 V PIN H22 FSM A5 Address bus 2 5 V PIN H23 FSM A6 Address bus 2 5 V PIN J22 FSM A7 Address bus 2 5 V PIN K22 FSM A8 Address bus 2 5 V PIN M21 FSM A9 Address bus 2 5 V PIN J2
157. s data Return Value Return TRUE if read data 1s successful otherwise FALSE is returned PCIE_Write32 unction Write a 32 bits data to the FPGA Board Prototype bool PCIE Write32 PCIE HANDLE hPCIE PCIE BAR PcieBar PCIE ADDRESS PcieAddress DWORD Parameters hPCIE A PCle handle return by PCIE_Open function PcieBar Specify the target BAR PcieAddress Specify the target address in FPGA dwData Specify a 32 bits data which will be written to FPGA board Return Value Return TRUE if write data 1s successful otherwise FALSE 15 returned PCIE DmaRead unction Read data from the memory mapped memory of FPGA board in DMA function Prototype 165 13 51 Terasic DE4 User Manual www terasic com rasic com bool PCIE DmaRead PCIE HANDLE hPCIE PCIE LOCAL ADDRESS LocalAddress void pBuffer DWORD dwBufSize Parameters hPCIE A PCIe handle return by PCIE Open function LocalAddress Specify the target memory mapped address in FPGA pBufter A pointer to a memory buffer to retrieved the data from FPGA The size of buffer should be equal or larger the dwBufSize dwBufsSize Specify the byte number of data retrieved from FPGA Return Value Return TRUE if read data 1s successful otherwise FALSE is returned PCIE DmaWrite unction Write data to the memory mapped memory of FPGA board in DMA function Prototype bool PCIE DmaWrite PCIE HANDLE hPCIE PCIE LOCAL ADDRE
158. s the transfer is complete the conf_ready returns back to original state at high level Alias 2048 1024 ms 1024 2048 3072 4096 5120 5144 158 om u m ext ctrtu ext set wr 3h m ext pl ex pl set 4h i ext ext rd ext pl anena EnEn 3h 2 set rd p34 3h pl ext set a haenen onanan 4h 1 ext ext pil ctrilcanf ready LE B 2 4 ctru ext ctrijganf wr H e LE ext set wer H ext ext ctri clkz set wr fF ext ext ctri clk3 wer ext ctru ext ctrilcanf rd fF ext ext ctrilcik set rd pj ext ext ctri clk2 set rd fF ext ext set rd ext ext etrllcanf ready eeeceeeeg 422262224 Figure 5 28 Read timing waveform 136 Terasic DE4 User Manual www terasic com B Design Tools e Quartus B Demonstration Source Code e Project directory DE4 EXT e Bit stream used DE4 EXT PLL sof B Demonstration Batch File e Demo
159. ss AP27 M1 DDR2 A14 DDR2 Address 14 SSTL 18 Class PIN AU29 M1 DDR2 A12 DDR2 Address 12 SSTL 18 Class PIN AP26 M1 DDR2 11 DDR2 Address 11 SSTL 18 Class AU28 1 DDR2 9 DDR2 Address 9 SSTL 18 Class 27 1 DDR2 7 DDR2 Address 7 SSTL 18 Class AT27 DDR2 8 DDR2 Address 8 SSTL 18 Class PIN AL27 M1 DDR2 A6 DDR2 Address 6 SSTL 18 Class AU27 DDR2 5 DDR2 Address 5 SSTL 18 Class PIN AK26 M1 DDR2 A4 DDR2 Address 4 SSTL 18 Class PIN AN26 M1 DDR2 A3 DDR2 Address 3 SSTL 18 Class PIN AM26 M1 DDR2 A2 DDR2 Address 2 SSTL 18 Class PIN AW23 M1 DDR2 A1 DDR2 Address 1 SSTL 18 Class PIN AL25 M1 DDR2 AO DDR2 Address 0 SSTL 18 Class AV23 M1 DDR2 A10 DDR2 Address 10 SSTL 18 Class PIN AJ26 M1 DDR2 BA1 DDR2 Bank Address 1 SSTL 18 Class PIN AD25 M1 DDR2 BAO DDR2 Bank Address 0 SSTL 18 Class PIN AH26 M1 DDR2 RAS n DDR2 Row Address Strobe SSTL 18 Class PIN AE21 M1 DDR2 WE n DDR2 Write Enable SSTL 18 Class PIN AK25 M1 DDR2 CS DDR2 Chip Select 0 SSTL 18 Class PIN AG21 M1 DDR2 CAS n DDR2 Column Address Strobe SSTL 18 Class AJ25 M1 DDR2 ODTO DDR2 On Die Termination 0 SSTL 18 Class PIN AG20 DDR2 CS DDR2 Chip Select 1 SSTL 18 Class PIN AE25 M1 DDR2 A13 DDR2 Address 13 SSTL 18 Class AD21 M1 DDR2 ODT1 DDR2 On Die Termination SSTL 18 Class PIN AE24 M1 DDR2 0032 DDR Data 32 SSTL 18 Class PIN AK
160. stem Block Diagram Figure 5 29 shows the system block diagram of this demonstration which is designed based on SOPC Builder requiring a 50 MHz clock provided by the board In the SOPC builder all the components are designed to run on a 50 MHZ clock The NIOS program is run on a on chip memory The PIO Controllers are used to implement SPI protocol where the SPI signal 15 directly toggled by the Nios II FPGA SOPC 50 MHz Memory ub Controller System Intercoment Fabric Figure 5 29 Block Diagram of the Power Measurement Demonstration B ADC Clock Configuration In this demonstration the FO pin is connected to GND FO as a result the converter uses its internal oscillator and the digital filter first null is located at 60Hz The clock source in SPI transition is configured as External Serial Clock Operation mode by keeping the SCK pin to low at the falling edge of CS pin 138 Terasic DE4 User Manual www terasic com www terasic co m 10 RYA ADC SPI Transmission Figure 5 30 shows the data timing for SPI transmission The SDI signal 15 used to serialize data from the FPGA to ADC and the SDO signal is used to serialize data from ADC to FPGA CS BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 Ee ow X An Nos X nm CONVERSON RESULT ADDRESS CORRESPONDING To RESULT SCK S
161. t gt Figure 5 13 Triple Speed Ethernet core configurations In the MAC options section the module 15 included that controls the PHY Management Module associated with the MAC block The host clock divisor is to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency 15 100 MHz and the desired MDC clock frequency 15 2 5 MHz a host clock divisor of 40 should be used Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections has been made click on Generate to build the interconnect logic automatically In this following section we will describe the steps to create the Simple Socket Server using Nios II We create a new project in Nios II using the project template Simple Socket Server shown in Figure 5 14 The PTF file created using the SOPC builder in Quartus II is used in the Select Target Hardware section 119 Terasic DE4 User Manual www terasic com www terasic co m 7 Hew Nios II C C Application Click Finish to create application with defaull system library as CADES SystemBuilderwl 4 2 0 VCodeGenerated DES NE Tsoftware enet_testtample_socket_server Name sumple socket server w Specify Location Location SvstemBudderw 4 2 9 NETwoftware enet test Select Target Hardware SOPC Builder System PTF Fil
162. t device then calls the get_mac_addr function to set the MAC addresses for the PHY Secondly it initiates the auto negotiation process to check the link between PHY and gateway device If the link exists the PHY and gateway devices will broadcast their transmission parameters speed and duplex mode After the auto negotiation process has finished it will establish the link Thirdly the Web Server program will prepare the transmitting and receiving path for the link If the path is created successfully it will call the get ip addr function to set up the IP address for the network interface After the IP address is successfully distributed The NicheStack TCP IP Stack will start to run for Web Server application Figure 5 38 describes this demo setup and connections on the DE4 The Nios II processor is running NicheStack on the Micro C OS II RTOS 147 Terasic DE4 User Manual www terasic com www terasic com 10 100 1000 Mbps 10 100 1000 Mbps CAT 5e Cable CAT 5e Cable LS amp Gateway with DHCP Figure 5 38 System principle diagram Note your gateway should support DHCP since the DHCP protocol 15 used to request a valid IP from the Gateway and the web server demonstration uses the SGMII interface to access the TCP IP You can switch the MAC Interface Demonstration Setup File Locations and Instructions The Following steps describe how to setup a Web Server demo
163. ted to The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and IO standard If a customized daughter board is used users can select HSMC Default followed by changing the pin name pin direction and IO standard according to the specification of the customized daughter board If transceiver pins are not required on the daughter board please remember to remove it otherwise Quartus will report errors 98 Terasic DE4 User Manual www terasic com www terasic com Terasic DEA System Builder V 1 0 0 System Configuration ABERA UNIVERSITY Board Type 4 230 PROGRAM Project Name DE4 CLOCK Slide Switch x 4 LED T Segement x 2 Button x 4 DIP Switch x 8 SMA Temperature USB OTG Power Measurement Fan Control SD CARD Flash 64MB EEPROM SSRAM 2MB RS 232 Programmable PLL Programmable PLL Ethernet x 4 HSMA REFCLK O DDR2 5 1 O DDR2 SODIMM 2 O Sata Host 0 O Sata Host 1 O Sata Device 0 O Sata Device 1 PLL CLKIN SATA REFCLK O PCle REFCLK GPIO Expansion HSMC Expansion GPIO 0 Header HSMC A Transceiver x 4 5M Pixel Camera SFP Form Factor Pluggable D5M 1 i Prefix Name Prefix Name GPIO 1 Header HSMC B Transceiver x 8 LTM 4 3 LCD and Touch 501 SD HD SG Prefix
164. tings 52 Terasic DE4 User Manual www terasic com www Lterasic com mme DEFAULT LVDS Ouput 100MHz Bank QLO PCIE_REFCLK REFCLK_LO gt 50MHz Bank QL1 Bank QL2 REFCLK_L4 Bank QRO SATA REFCLK REFCLK RO Bank 1 REFCLK_R2 REFCLK_R3 HSMB REFCLK SMA_GXBCLK Bank QR2 Bank 1C HSMA_CLKIN_2 HSMA CLKIN 2 H LKINO PLL 13 FB SS O 90 B2 Bank 3C CLK5n Bank 4C CLK7n PLL B2 CLKOUT osc so 36 p gt i CLK11 100MHz Bank 7C Ww CLK13n mue S o Bank 8C OP gt 0 PLL CLKIN 14 From FPGA CLK45 rumos SSRAM CLK SMA DIFF CLK SEL SW7 Figure 2 23 Clock connections of the DE4 53 DE4 User Manual www terasic com www terasic com Table 2 20 Clock Selections SW7 Ce e j am SMA CLKIN CLK SETSW _ GCLKOUT N A CLK_SETSW7 _ r mi E LEM The Stratix GX FPGA consists of 7 dedicated clock input pins and from those pins 1 dedicated differential clock input listed in Table 2 21 In addition there are a total of 8 PLLs available for the Stratix IV GX device Table 2 21 Dedicated Clock Input Pins The dedicated clock input pins from the clock input multiplexer allow users to use any of these clocks as a source clock t
165. tion GPIO Expansion 1 IO 0 GPIO Expansion 1 IO 1 GPIO Expansion 1 IO 2 GPIO Expansion 1 IO 3 GPIO Expansion 1 IO 4 GPIO Expansion 1 IO 5 GPIO Expansion 1 10 6 GPIO Expansion 1 IO 7 GPIO Expansion 1 IO 8 GPIO Expansion 1 IO 9 GPIO Expansion 1 IO 10 GPIO Expansion 1 IO 11 GPIO Expansion 1 IO 12 GPIO Expansion 1 IO 13 GPIO Expansion 1 IO 14 GPIO Expansion 1 10 15 GPIO Expansion 1 IO 16 GPIO Expansion 1 IO 17 GPIO Expansion 1 IO 18 GPIO Expansion 1 1019 GPIO Expansion 1 10 20 GPIO Expansion 1 IO 21 GPIO Expansion 1 10 22 GPIO Expansion 1 10 23 GPIO Expansion 1 10 24 GPIO Expansion 1 10 25 GPIO Expansion 1 10 26 GPIO Expansion 1 10 27 GPIO Expansion 1 10 28 GPIO Expansion 1 10 29 Terasic DE4 User Manual rasic com Standard 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 3 0 V 39 Stratix IV GX Pin Number AW5 AW8 4 10 AV8 AW10 AU10 AU8 10 AU6 6 07 AR5 AP6 AT7 7 6 16 AM6 15 19 9 AJ6 AJ10 11 AH8 9 12 10 www terasic com GPIO1 D30 GPIO1 D3
166. tivity targeted reference design that integrates built in blocks for PCI Express SATA transceiver verification testing and Gigabit Ethernet protocol The DE4 is supported by multiple reference designs and two High Speed Mezzanine Card HSMC connectors that allow scaling and customization with mezzanine daughter cards For large scale ASIC prototype development it can be established by a cable connecting to multiple DE4 FPGA boards through the HSMC connectors It is highly recommended that users read the 4 Getting Started Guide pdf before using the DEA board 4 Terasic DE4 User Manual www terasic com www terasic com 1 2 Key Features The following hardware is implemented on the DEA board e Featured device O Altera Stratix FPGA EPASGX230C2 EPASGX530C2 e Configuration status and set up elements O O O Built in USB Blaster circuit for programming Fast passive parallel FPP configuration via MAX II CPLD and flash memory Three External Programmable PLL timing chip e Component and interfaces O O 0 Four Gigabit Ethernet GigE with RJ 45 connector Two host and two device Serial ATA SATA II ports Two HSMC connectors Two 40 pin expansion headers PCI Express 2 0 x8 lane connector Memory O O DDR2 SO DIMM socket FLASH SSRAM SD Card socket I2C EEPROM e General user input output O 8 LEDs 4 push buttons and 4 slide switches
167. two internal memories RAM FIFO through the MUX block FPGA LE Address Basic Button Interface Internal RAM PCI Express Terasic PCle IP DMA Channel FIFO Figure 6 13 Hardware block diagram of the PCle reference design B PC Application Design The application shows how to call the TERASIC PCIE DLL exported to API To enumerate all PCIe cards in system call the software design defines some constant based on FPGA design shown below 170 Terasic DE4 User Manual www terasic com www terasic co m Sdefine PCIE VID Hxll7Z Sdefine PCIE DID Lx ELLI define DEMO PCIE USER BAR PCIE BARI define DEMO PCIE IO ADDR 0x04 define DEMO PCIE FIFO ID oxoo The vender ID 15 defined as 0x1172 and the device ID is defined as 0 001 The BUTTON LED register address is 0x04 based on PCIE BARI A class PCIE is designed to encaptulate DLL dynamic loading for TERASIC PCIE DLL A PCIE instance is created with the name hPCIE To enumerate all PCIe cards in system call the function m hPCIE ScanCardi wVendorID wDewiceID amp dwDewviceNMum m szPcielntfoj where wVendorID and wDeviceID zeros The return value dwDeviceNum represents the number of PCIe cards found in the system The m szPcieInfo array contains the detail information for each PCIe card To connect the selected PCIe card the functions are called int noel CaombobBoxBo
168. two modes of interfaces including memory mapping and FIFO link The oFIFO MEM SEL signal determines the DMA channel used memory mapping or FIFO link which is enabled with the assertion of a low and high signal respectively The address bus of DMA indicates the FIFO ID which 1s defined by user from the PC software API Most interfaces experience read latency during the event data is read and processed to the output To mitigate the overall effects of read latency minimum delay and timing efficiency 15 required to enhance the performance of the high speed DMA transfer oDMARD READ signal is asserted the read data valid signal oDMARD RDVALID is inserted high to indicate the data on the iDMARD DATA data bus is valid to be read after two clock cycles 156 Terasic DE4 User Manual www terasic com www terasic com Table 6 2 Name Type oCORE CLK Output oDMARD ADDR 31 0 Output iDMARD DATA 127 0 Input oDMARD READ Output oDMARD RDVALID Input oDMAWR ADDR 31 0 Output oDMAWR DATA 127 0 Output oDMAWR WRITE Output oFIFO MEM SEL Output 11 2 1 oCORE YY SS DMA Channel Signals of Terasic PCIe IP Polarity Description High High High 3 Clock The reference clock output of PCle local interface When oFIFO MEM SEL is set to low it is address bus of DMA transfer and the value of address bus is cumulative by PCle IP and it is 128 bit data per address
169. ue To check whether the 1mage process 15 finished the control register 15 monitored by calling the function m hPCIE Read32 DEMO PCIE USER BAR DEMO IMAGE REG ADDR sdwStatus When the image process 1s finished the value of dwStatus becomes zero To update the processed image from FPGA memory to PC the function 1s called m hPCIE DmaEead DEHMO IMAGE DATA ADDR plImage nlmagesizej 176 Terasic DE4 User Manual www terasic com www terasic com Additional Information Getting Help Here are the addresses where you can get help if you encounter problems e Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web www terasic com DE4 Web de4 terasic com Revision History Date Version Changes 2010 7 First publication 2010 8 1 PCle Driver Installation Modified 177 Terasic DE4 User Manual www terasic com rasic com
170. unt QSH family of high speed board to board connectors The Stratix IV GX device provides 12 V DC and 43 3 V DC power to the mezzanine card through HSMC connector Table 2 9 indicates the maximum power consumption for both HSMC ports A and B Table 2 9 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 3A 3 3V 3A There are three banks in this connector as Figure 2 12 shows the bank arrangement of signals with respect to the Samtec connector Table 2 10 and Table 2 11 show the mapping of the FPGA pin assignments to the HSMC connectors 25 Terasic DE4 User Manual www terasic com rasic com Bank 1 TX Channels CDR RX Channels CDR JTAG CLKIN O Bank 2 Power TX LVDS Channels RX LVDS Channels CLKIN 1 Bank 3 Power TX LVDS Channels RX LVDS Channels CLKIN 2 CLKOUT Figure 2 12 HSMC signal and bank diagram B Distribution The two HSMC interfaces combine have a total of 12 pairs CDR based transceivers operating up to 8 5Gbps 38 pairs LVDS transmitter channels at data rates up to 1 6Gbps and 36 pairs LVDS receiver channels Independently Port A of the HSMC connector consists of 4 pairs CDR based transceivers 19 pairs LVDS transmitter channels and 18 pairs LVDS receiver channels While port B of the HSMC connector consists of 8 pairs CDR based transceivers 19 pairs LVDS transmitter channels and 18 pairs LVDS receiver channels Additionally both ports A and B of the HSMC interfa
171. up where position 2 is set to Off for port B connected on the DEA and position 15 set to for port A connected on DEA allowing JTAG chain to be detected for both DE4 boards 29 Terasic DE4 User Manual www terasic com www Cu gpECO M Vn ris 112 E 4 Bedam 5270 pipi o ONOFF ON ON OFF ON ON ON Figure 2 17 JTAG chain setup between two DE4 boards using HSMC interface Table 2 10 HSMC Port B Pin Assignments Schematic Signal Names and Functions Stratix IV GX HSMC Pin Schematic Signal Name gt Description Standard Pin Number ransceiver TX bit 7 HSMB GXB TX n7 Transceiver TX bit7n 14 VPCML 0 2 0 3 _ A 7 PIN 04 JEN E 4 PINE2 7_______ 5 6 Transceiver TX bit6n 14 VPCML 03 8 HSMB GXB n6 ransceiverRXbit n 14VPCML PINE 9 7 HSMB GXB p5 Transceiver TX bit5 14 VPCML PIN KA 10 5 GXB Transceiver RXbit5 14 VPCML 2 1 HSMB GXB 5 Transceiver RX bit5n __ 14 VPCML 12 GXB 5 Transceiver RX bit5n 14VPCML PINLI 13 GXB Transceiver TX bit4 14 VPCML 14 GXB Transceiver RXbit4 14 VPCM
172. wer 2 5V and power rails and also requiring a 25MHz reference clock driven from a dedicated 25MHz oscillator The transmitter and receiver signals of the Marvell device are connected directly to the LVDS I Os of the Stratix IV GX device with speeds at 1 2Gbps The integrated Ethernet transceiver through internal magnetics to RJ45 can be used to drive copper lines with Ethernet traffic Figure 2 26 illustrates the overall structure and connection between the RJ45 ports and the 88 1111 devices while Table 2 25 lists the default settings for the four chips 59 Terasic DE4 User Manual www terasic com www terasic com ANU S RYA Stratix IV Media Types 10BASE T 100BASE TX 1000BASE T Figure 2 26 Overall connection of the Ethernet devices Table 2 25 Default Configuration for Gigabit Ethernet Ethernet MAC port Default Value PHY Address in MDIO MDC 00000 for Enet0 00001 for Enet1 00010 for Mode Enet2 00011 for Enet3 Enable Pause 0 Default Register 4 11 10 to 00 Auto negotiation configuration for copper modes Enable Crossover 0 Disable Disable 125MHz clock 1 Disable 125CLK 1110 Auto neg advertise all capabilities prefer master Hardware Configuration 0100 SGMII without clock with SGMII DIS FC Disable fibericopper Disable 75 500HM Termination resistance 60 Terasic DE4 User Manual www terasic com www terasic com Table 2 26 lists the Ethernet signal names and their correspond
173. ww terasic com www terasic com i m altera components ush device gt Binaries A Includes H Debug 1 12 SIE hal ispl761 config h ISP1761 HAL Lh isp1761 hal Hardware Abstration Layer 7 register h ispl761 config c 1 61 hal niasz c T e y un nr m Ed eJ 8 5 EJ bulk device h device caentral h ispl761 device central h 15 1 761 device register h usb device h usb praotacal h bulk device c Bulk Driver 761 device control c ISP1761 Peripheral Controller usb device c USB Protocol terasic debug h h includes h E e main c Main debug c application stF B niosz qdb server exe stackdump readme tek usb device_syslib DE3 SOPC Figure 5 9 Source Code List of the USB Device Demonstration B Nios Project Compilation e Before you attempt to compile the reference design under Nios II IDE make sure the project 15 cleaned first from the Project menu of Nios followed by Clean B Demonstration Batch File Demo Batch File Folder DE4 USB Mdemo batch Nusb device The demo batch file includes the following files e Batch File test bat test bashrc FPGA Configure File 4 USB sof
174. xecute demo batch file test bar under the batch file folder 130 Terasic DE4 User Manual www terasic com www terasic com NU M ad DE4 DDR2Ndemo batchNdiml DE4_DDR2 demo_batch dim2 After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Press Button3 Button0 of the DEA board to start SDRAM verify process Press Button0 for continued test and Ctrl C to terminate the test The program will display progressing and result information as shown in us 1 par 577 CLE EF LTMUEDTE rary IIT wer Figure 5 23 Insert DDR2 SDRAM SODIMM for the DDR2 Demonstration n x lerified Starting processor at address WHx41H2H1C8 nios2 terminal connected to hardware target using JIAG UART on cable nios2 terminal USB Blaster USHB 1 device 1 instance nios2 terminal Use the IDE stop button or Ctrl C to terminate DE4 DDH2 Test Program Clock 466 MHZ Size 1024 MBytes Rank 1 Hank 3 Hank s gt Press any BUTTON to start test L BUTTOMH for continued test gt DDR2 Testing Iteration 1 urite 1H 20 302 46 505 6H 705 8H 97H 100 read uerifvy 1H 20 3H 46 505 6H 705 8H 10 DDR2 test pass 12 1 73741824 bytes 71 922 sec gt DDR2 Testing Iteration 2 urite 105 20 Figure 5 2
175. z Ethernet Ports H 4 ee E Z4 Oscillator ue as meno di wn e 1 2 i Edgar TM d en ere PES e D aa OM V re T External PLL 1 3 Position E n Saree C Bei Bose 2 amp s DIP Switch Mu didi nt p ae 4 12V Fan xD Connector PCI Express x8 Edge SSAA FLASH 5OMHz HSMC Il Re Configuration Two 40 pin Connector Oscillator Port CPLD EPM2210 Push button GPIO Connectors Pole System Contraller Switch Port A DDR2 SO DIMM support up to 4GB Figure 1 1 The 4 board Top view DE4 User Manual www terasic com www terasic com External Battery Socket Volatile security key storage 50 CARD Slot in Hn b II sii ih LE TM 1 TEST ss x r 33 3 TI E External Clock 2 EEPROM Figure 1 2 The 4 board Bottom view 1 4 Block Diagram Figure 1 3 shows the block diagram of the DE4 board To provide maximum flexibility for the users all key components are connected with the Stratix IV GX FPGA device Thus users can configure the FPGA to implement any system design TijasiC Terasic DE4 User Manual www terasic com www terasic com Transceiver link _ToFPGA

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