AD5533 (REV. A) - Analog Devices
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1. 0 0020 0 0012 0 0008 Vout ERROR V o o o o o Vin V TPC 1 Vin to Voyr Accuracy after Offset and Gain Adjustment 5V 90 BUSY Vout Ta 25 C Vrerin 3V d t Vi 0 gt 1 5V PESER A A al ene leean lbe ds 1v 2Qus TPC 4 Acquisition Time and Output Settling Time FREQUENCY OFFSET ERROR mV 20 a o OFFSET ERROR 40 0 40 80 TEMPERATURE C TPC 2 Offset Error and Gain vs Temperature 70k T 25 C 60k Vref 3V Vn 1 5V 5 2670 5 2676 5 2682 Vout V TPC 5 ISHA Mode Repeatability 64 K Acquisitions 10 3 535 3 530 3 520 6 4 2 0 2 4 6 SINK SOURCE CURRENT mA TPC 3 Vour Source and Sink Capability REV A FUNCTIONAL DESCRIPTION The AD5533 can be thought of as consisting of an ADC and 32 DACs in a single package The input voltage Vyn is sampled and converted into a digital word The digital result is loaded into one of the DAC Registers and is converted with gain and offset into an analog output voltage Vour0 Vour31 Since the channel output voltage is effectively the output of a DAC there is no droop associated with it As long as power to the device is maintained the output voltage will remain constant until this channel is addressed again To update a single channel s output voltage the require2. 10 uA max 5 uA typ Input Low Voltage 0 8 V max DVcc 5 Vt 5 0 4 V max DVcc 3 Vt 10 Input High Voltage 2 4 V min DVcc 5 Vt 5 2 0 V min DVcc 3 V 10 Input Hysteresis SCLK and CS Only 200 mV typ Input Capacitance 10 pF max DIGITAL OUTPUTS BUSY DOUT Output Low Voltage 0 4 V max DVcc 5 V Sinking 200 pA Output High Voltage 4 0 V min DVcc 5 V Sourcing 200 uA Output Low Voltage 0 4 V max DVcc 3 V Sinking 200 pA Output High Voltage 2 4 V min DVcc 3 V Sourcing 200 HA High Impedance Leakage Current 1 uA max Dour Only High Impedance Output Capacitance 15 pF typ Dour Only REV A AD5533 Parameter A Version Unit Conditions Comments POWER REQUIREMENTS Power Supply Voltages Vop 8 16 5 V min max Vss 4 75 16 5 V min max AVcc 4 75 5 25 V min max DVcc 2 7 5 25 V min max Power Supply Currents Ipp 15 mA max 10 mA typ All Channels Full Scale Iss 15 mA max 10 mA typ All Channels Full Scale Alcc 33 mA max 26 mA typ DIcc 1 5 mA max 1 mA typ Power Dissipation 280 mW typ Vpp 10 V Vss 5 V NOTES 1See Terminology 2A Version Industrial temperature range 40 C to 85 C typical at 25 C 3Guaranteed by design and characterization not production tested 1AD780 as reference for the AD5533 Ensure that you do not exceed Ty max See maximum ratings Outputs unloaded Specifications subject to change without notice Von 8 V to 16 5 V Vss 4 75 V to
3. AD5533 has several advantages no refreshing is required there is no droop pedestal error is eliminated and there is no need for extra filtering to remove glitches Overall a higher level of integration is achieved in a smaller area see Figure 13 PARAMETRIC MEASUREMENT UNIT ACTIVE STORED DATA AND INHIBIT PATTERN PERIOD GENERATION AND DELAY TIMING COMPARATOR SYSTEM BUS Figure 13 AD5533 in an ATE System Typical Application Circuit The AD5533 can be used to set up voltage levels on 32 channels as shown in the circuit below An AD780 provides the 3 V refer ence for the AD5533 and for the AD5541 16 bit DAC A simple 3 wire interface is used to write to the AD5541 Because the AD5541 has an output resistance of 6 25 kQ typ the time taken to charge discharge the capacitance at the Vpy Pin is significant Hence an AD820 is used to buffer the DAC output Note that it is important to minimize noise on Vy and REFIN when laying out this circuit AVcc AVcc DVcc Vss O O O AD5541 AD820 AD5533 Ed En OFFS_OUT REFIN O SCLK DIN SYNC I 1 Vout 0 31 l ADDITIONAL PINS OMITTED FOR CLARITY Figure 14 Typical Application Circuit REV A POWER SUPPLY DECOUPLING In any circuit where accuracy is important careful consideration of the power supply and ground return layout helps to ensure the rated performance The printed circuit board on which the AD5533 is mounted should
4. have been shifted in or out the SCLK is ignored In order for another serial transfer to take place the counter must be reset by the falling edge of SYNC In read back the first rising SCLK edge after the falling edge of SYNC causes Dour to leave its high impedance state and data is clocked out onto the Dour line and also on subsequent SCLK rising edges The Doyr Pin goes back into a high impedance state on the falling edge of the 14th SCLK Data on the Dy line is latched in on the first SCLK falling edge after the falling edge of the SYNC signal and on subse quent SCLK falling edges The serial interface will not shift data in or out until it receives the falling edge of the SYNC signal REV A Parallel Interface The SER PAR Bit must be tied low to enable the parallel interface and disable the serial interface The parallel interface is controlled by nine pins CS Active Low Package Select Pin This pin is shared with the SYNC function for the serial interface WR Active Low Write Pin The values on the Address Pins are latched on a rising edge of WR A4 A0 Five Address Pins A4 MSB of address AO LSB These are used to address the relevant channel out of a possible 32 OFFSET_SEL Offset Select Pin This has the same function as the OFFSET_SEL Bit in the serial interface When it is high the offset channel is addressed and the address on A4 A0 is ignored CAL Same functionality as the CAL Bit in the seri
5. test equipment and can discharge without detection Although the AD5533 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality a ESD SENSITIVE DEVICE REV A PIN CONFIGURATION 23 4 5 67 8 9 10 11 E s O00000000000 00 O O0 lt p OO TOP VIEW OO D E O O AD5533 O O E F OO OO F 6 O O O O se 0O O O O H s 0OO O OO y K O OOOO0O0000 O k ai ibe tie ea 12 3 4 5 6 7 8 9 10 11 74 Lead CSPBGA Ball Configuration CSPBGA Ball CSPBGA Ball CSPBGA Ball Number Name Number Name Number Name Al N C C10 AVccl J10 VO9 A2 A4 C11 REF_OUT Jil Voll A3 A2 D1 VO20 Kl VO17 A4 AO D2 DAC_GND2 K2 VO15 A5 CS SYNC D10 AVcc2 K3 VO27 A6 DVcc D11 OFFS_OUT K4 Vss3 A7 SCLK El VO26 K5 Vssl A8 OFFSET_SEL E2 VO14 K6 Vss4 A9 BUSY E10 AGND1 K7 Vpp2 A10 TRACK RESET Ell OFFS_IN K8 VO2 All N C Fl VO25 K9 VO10 Bl VO16 F2 VO21 K10 VO13 B2 N C F10 AGND2 K11 VO12 B3 A3 F11 VO6 Ll N C B4 Al Gl VO24 L2 VO28 B5 WR G2 VO8 L3 VO29 B6 DGND G10 VO5 L4 VO30 B7 Dw Gll VO3 L5 Vpp3 B8 CAL H1 VO23 L6 Vopl B9 SER PAR H2 Vin L7 Vpp4 B10 Dour H10 VO4 L8 VO31 Bll REF_IN H11 VO7 L9 VOO Cl VO18 Jl VO22 L10 vol C2 DAC_GND1 J2 VO19 L11 N C C6 N C J6 Vss2 N C unconnected REV A 7 AD5533 PIN FUNCTION DESCRIP
6. 16 5 V AVec 4 75 V to 5 25 V DVec 2 7 V to 5 25 V AGND AC CHARACTERISTICS DGND DAC_GND 0 V REF_IN 3 V Output Range from Vss 2 V to Vpp 2 V All outputs unloaded All specifications Tyn to Tmax unless otherwise noted Parameter A Version Unit Conditions Comments Output Settling Time 3 Us max Acquisition Time 16 Us max OFFS_IN Settling Time 10 us max 500 pF 5 kQ Load 0 V 3 V Step Digital Feedthrough 0 2 nV s typ Output Noise Spectral Density 1 kHz 400 nV VHz typ AC Crosstalk 5 nV s typ NOTES 1A Version Industrial temperature range 40 C to 85 C typical at 25 C Guaranteed by design and characterization not production tested Specifications subject to change without notice REV A AD5533 TIMING CHARACTERISTICS PARALLEL INTERFACE Limit at Tins Tmax Parameter A Version Unit Conditions Comments t 0 ns min CS to WR Setup Time ty 0 ns min CS to WR Hold Time ts 50 ns min CS Pulsewidth Low t4 50 ns min WR Pulsewidth Low o ts 20 ns min A4 A0 CAL OFFS_SEL to WR Setup Time t 7 ns min A4 A0 CAL OFFS_SEL to WR Hold Time NOTES ISee Interface Timing Diagram Guaranteed by design and characterization not production tested Specifications subject to change without notice SERIAL INTERFACE Limit at Tmn Tmax Parameter A Version Unit Conditions Comments foLkIN 20 MHz max SCLK Frequency t 20 ns min SCLK High P
7. AGND DAC_GND 0 3 V to 7 V DUE to DGND tada Aol 0 3 V to 7 V Digital Inputs to DGND Digital Outputs to DGND REF_IN to AGND DAC_GND Vin to AGND DAC_GND Vour0 31 to AGND 0 3 V to DVcc 0 3 V 0 3 V to DVcc 0 3 V 0 3 V to AVcc 0 3 V 0 3 V to AVec 0 3 V Vss 0 3 V to Vop 0 3 V OFFS_IN to AGND Vss 0 3 V to Vpp 0 3 V OFFS_OUT to AGND AGND 0 3 V to AVcc 0 3 V AGND to DGND 0ccccccoccooc oo 0 3 V to 0 3 V Operating Temperature Range Industrial 40 C to 85 C Max Power Dissipation 150 C T ya mW Max Continuous Load Current at Ty 70 C per Channel Group NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Transient currents of up to 100 mA will not cause SCR latch up 3 This limit includes load power 4 This maximum allowed continuous load current is spread over eight channels and channels are grouped as follows Group 1 Channels 3 4 5 6 7 8 9 10 Group 2 Channels 14 16 18 20 21 24 25 26 Group 3 Channels 15 17 19 22 23 27 28 29 Group 4 Channels 0 1 2 11 12 13 30 31 For higher ju
8. ANALOG DEVICES 32 Channel Infinite Sample and Hold FEATURES Infinite Sample and Hold Capability to 0 018 Accuracy High Integration 32 Channel DAC in 12 mm x 12 mm CSPBGA Per Channel Acquisition Time of 16 us Max Adjustable Voltage Output Range Output Impedance 0 5 Q Output Voltage Span 10 V Readback Capability DSP Microcontroller Compatible Serial Interface Parallel Interface Temperature Range 40 C to 85 C APPLICATIONS Optical Networks Automatic Test Equipment Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I O GENERAL DESCRIPTION The AD5533 combines a 32 channel voltage translation function with an infinite output hold capability An analog input voltage on the common input pin Vw is sampled and its digital repre sentation transferred to a chosen DAC Register Voyr for this DAC is then updated to reflect the new contents of the DAC register Channel selection is accomplished via the parallel address inputs AO A4 or via the serial input port The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier It is restricted to a range from Vss 2 V to Vpp 2 V because of the headroom of the output amplifier The device is operated with AVcc 5 V 5 DVcc 2 7 V to 5 25 V Vss 4 75 V to 16 5 V and Vpp 8 V to 16 5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN PROD
9. C Mode is not available for the AD5533 To avail of this mode refer to the AD5532 data sheet If you attempt to set up DAC Mode the AD5533 will enter a Test Mode and a 24 clock write will be necessary to clear this Table II Modes of Operation Mode Bit 1 Mode Bit 2 Operating Mode 0 0 ISHA Mode 0 1 DAC Mode Not Available 1 0 Acquire and Read Back 1 1 Read Back 12 1 ISHA Mode In this standard mode a channel is addressed and that channel acquires the voltage on Vm This mode requires a 10 bit write to address the relevant channel Vour0 Vour31 offset channel or all channels MSB is written first 2 Acquire and Readback Mode This mode allows the user to acquire Vin and read back the data in a particular DAC Register The relevant channel is addressed 10 bit write MSB first and Vy is acquired in 16 us max Following the acquisition after the next falling edge of SYNC the data in the relevant DAC Register is clocked out onto the Dovr line in a 14 bit serial format During read back Dyy is ignored The full acquisition time must elapse before the DAC register data can be clocked out 3 Readback Mode Again this is a Readback Mode but no acquisition is performed The relevant channel is addressed 10 bit write MSB first and on the next falling edge of SYNC the data in the relevant DAC Register is clocked out onto the Dour line in a 14 bit serial format The user must allow 400 ns min between t
10. D5533 This microcontroller transfers only eight bits of data during each serial transfer operation therefore two consecutive read write operations are needed for a 10 bit write and a 14 bit read back Figure 11 shows the connection diagram PIC16C6x 7x SCK RC3 SDO RC5 AD5533 SCLK SDI RC4 RA1 ADDITIONAL PINS OMITTED FOR CLARITY Figure 11 AD5533 to PIC16C6x 7x Interface AD5533 to 8051 The AD5533 requires a clock synchronized to the serial data The 8051 serial interface must therefore be operated in Mode 0 In this mode serial data enters and exits through RxD and a shift clock is output on TxD Figure 12 shows how the 8051 is connected to the AD5533 Because the AD5533 shifts data out on the rising edge of the shift clock and latches data in on the falling edge the shift clock must be inverted The AD5533 requires its data with the MSB first Since the 8051 outputs the LSB first the transmit routine must take this into account AD5533 SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 12 AD5533 to 8051 Interface REV A APPLICATION CIRCUITS AD5533 in a Typical ATE System The AD5533 infinite sample and hold is ideally suited for use in automatic test equipment Several ISHAs are required to control pin drivers comparators active loads and signal timing Traditionally sample and hold devices with droop were used in this application These required refreshing to prevent the voltage from drifting The
11. EL 58 A4 A0 TEST BIT a 10 Bit Input Serial Write Word ISHA Mode MSB LSB MSB LSB o a EN de t eee MODE BITS 4 10 BIT SERIAL WORD WRITTEN TO PART TEST BIT 4 14 BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC DB13 MSB OF DAC WORD b Input Serial Interface Acquire and Readback Mode MSB Ld MODE BITS 4 10 BIT SERIAL WORD WRITTEN TO PART MSB LSB LSB te ae eae lin a ar S is eee TEST BIT 4 14 BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC DB13 MSB OF DAC WORD c Input Serial Interface Readback Mode Figure 8 Serial Interface Formats The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs e g PIC16C PIC17C QSPI SPI DSP56000 TMS320 and ADSP 21xx without the need for any glue logic When interfacing to the 8051 the SCLK must be inverted The Microprocessor Interfacing section explains how to interface to some popular DSPs and microcontrollers Figures 3 and 4 show the timing diagram for a serial read and write to the AD5533 The serial interface works with both a continuous and a noncontinuous serial clock The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the Serial Shift Registers Any further edges on SYNC are ignored until the correct number of bits are shifted in or out Once the correct number of bits
12. Page 7103 Data Sheet changed from REV 0 to REV A Term SHA changed to ISHA o AS a aa dee a a Aaa lee des a A o aT AE eas yeas Global Term LEBGA updated to ESPBGA ici A AI A AA ead bad hw a A Global Chaniges to APPLICA TIONS aerie aoea a ST DAN AE PAR Ld AE A A DA aM aU ROR RO SRG 1 Changes to SPECIFICATIONS ona GAA a te se de Ae ee a Ge ie ea are ened A 2 Changes to TIMING CHARACTERISTICS ona reia Sse fac he alae Ss wane Rana S gta ea ean aa 4 Changes to ABSOLUTE MAXIMUM RATINGS 1 2 0 0 ccc eee eben eee eben d aaa 6 Changes to ORDERING GUIDE oia Hob tie eden ete Ged woe Dac Thee va bal GAGA Re be ae AAA Vale Heb rents Sao 6 Edits to PN FUNCTION DESCRIPTION tt a Namen 8 Changes to TERMINOLOGY Anir aii di tie eA actin eee aoa avai RN ace eee erin ee Rd eave ere ear ieee de a ee 9 Changes to FUNCTIONAL DESCRIPTION wo ccc eee cc cee eee e eben eee eee A eee bbe een ee a E ees 11 Changes to Tablet aii abba Leak bias AE aaa dels a de bu bg A AL da adidas peer pial ade 11 Changes to APPLICATION CIRCUITS ira aja E e ete ee A Dae Walang dd ed SOMA ESN ela 15 Updated OUTLINE DIMENSIONS iu seth ia A cabin ei aut y VOR RAYONG AIM eae hale ate bathe aa 16 16 REV A A C00940 0 7 03
13. STR 1 Clock Polarity Bit CPOL 0 and the Clock Phase Bit CPHA 1 The SPI is configured by writing to the SPI Control Register SPCR see 68HC11 User Manual SCK of the 68HC11 drives the SCLK of the AD5533 the MOSI output drives the serial data line Dwm of the AD5533 and the MISO input is driven from Doyr The SYNC signal is derived from a port line PC7 When data is being transmitted to the AD5533 the SYNC line is taken low PC7 Data appearing on the MOST output is valid on the falling edge of SCK Serial data from the 68HC11 is transmitted in 8 bit bytes with only eight falling clock edges occurring in the transmit cycle Data is transmitted MSB first To transmit 10 data bits in ISHA Mode it is important to left justify the data in the 14 SPDR Register PC7 must be pulled low to start a transfer It is taken high and pulled low again before any further read write cycles can take place A connection diagram is shown in Figure 10 AD5533 Dout MISO MC68HC11 SYNC PC7 SCLK SCK ADDITIONAL PINS OMITTED FOR CLARITY Figure 10 AD5533 to MC68HC11 Interface AD5533 to PIC16C6x PIC16C7x The PIC16C6x Synchronous Serial Port SSP is configured as an SPI Master with the Clock Polarity Bit 0 This is done by writing to the Synchronous Serial Port Control Register SSPCON See PIC16 PIC17 Microcontroller User Manual In this example I O port RAI is being used to pulse SYNC and enable the serial port of the A
14. TIONS Pin Function AGND 1 2 Analog GND Pins AVcc 1 2 Analog Supply Pins Voltage range from 4 75 V to 5 25 V Vpp 1 4 Vop Supply Pins Voltage range from 8 V to 16 5 V Vss 1 4 Vss Supply Pins Voltage range from 4 75 V to 16 5 V DGND Digital GND Pins DVcc Digital Supply Pins Voltage range from 2 7 V to 5 25 V DAC_GND 1 2 REF_IN REF_OUT Vour 0 31 Vin A4 A1 A0 CAL CS SYNC WR OFFSET_SEL SCLR Reference GND Supply for All the DACs Reference Voltage for Channels 0 31 Reference Output Voltage Analog Output Voltages from the 32 Channels Analog Input Voltage Parallel Interface 5 Address Pins for 32 Channels A4 MSB of Channel Address AO LSB Parallel Interface Control input that allows all 32 channels to acquire Vy simultaneously This pin is both the Active Low Chip Select Pin for the parallel interface and the Frame Synchronization Pin for the serial interface Parallel Interface Write Pin Active low This is used in conjunction with the CS Pin to address the device using the parallel interface Parallel Interface Offset Select Pin Active high This is used to select the offset channel Serial Clock Input for Serial Interface This operates at clock speeds up to 20 MHz Dn Data Input for Serial Interface Data must be valid on the falling edge of SCLK Dour Output from the DAC Registers for read back Data is clocked out on the rising edge of SCLK and is valid on the fa
15. UCT HIGHLIGHTS 1 Infinite Droopless Sample and Hold Capability 2 The AD5533 is available in a 74 lead CSPBGA with a body size of 12 mm X 12 mm FUNCTIONAL BLOCK DIAGRAM DVec AVec INTERFACE SER PAR 5 SCLK Din Dout Protected by U S Patent No 5 969 657 REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies REF_IN REF_OUT O CONTROL wo pn LOGIC gt E ADDRESS INPUT REGISTER 5 O SYNC CS OFFS_IN Von Vss O Vour 31 O OFFS_OUT A4 A0 CAL OFFSET_SEL One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved AD5533 SPECIFICATIONS Vss 2 V to Vp 2 V All outputs unloaded All specifications Ty to Tmax unless otherwise noted Von 8 V to 16 5 V Vss 4 75 V to 16 5 V AVec 4 75 V to 5 25 V DVec 2 7 V to 5 25 V AGND DGND DAC_GND 0 V REF_IN 3 V Output Range from Parameter A Version Unit Conditions Comments ANALOG CHANNEL Vin t
16. al interface When this pin is high all 32 channels acquire V simultaneously 13 AD5533 MICROPROCESSOR INTERFACING AD5533 to ADSP 21xx Interface The ADSP 21xx family of DSPs are easily interfaced to the AD5533 without the need for extra logic A data transfer is initiated by writing a word to the Tx Register after the SPORT has been enabled In a write sequence data is clocked out on each rising edge of the DSP s serial clock and clocked into the AD5533 on the falling edge of its SCLK In read back 16 bits of data are clocked out of the AD5533 on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK Dy is ignored The valid 14 bits of data will be centered in the 16 bit Rx Register when using this configuration The SPORT Control Register should be set up as follows TFSW RESW 1 Alternate Framing INVRES INVTES 1 Active Low Frame Signal DTYPE 00 Right Justify Data ISCLK 1 Internal Serial Clock TFSR RFSR 1 Frame Every Word IRFS 0 External Framing Signal ITFS 1 Internal Framing Signal SLEN 1001 10 Bit Data Words ISHA Mode Write SLEN 1111 16 Bit Data Words Readback Mode Figure 9 shows the connection diagram ADSP 2101 pr ADSP 2103 AD5533 TFS RFS DT ADDITIONAL PINS OMITTED FOR CLARITY Figure 9 AD5533 to ADSP 2101 ADSP 2103 Interface AD5533 to MC68HC11 The Serial Peripheral Interface SPI on the MC68HC11 is configured for Master Mode M
17. annel will not occur until a rising edge of TRACK At this stage the BUSY Pin will go low until the acquisition is complete at which point the DAC assumes control of the voltage to the output buffer and Vin is free to change again without affecting this output value This is useful in an application where the user wants to ramp up Vy until Vour reaches a particular level Figure 7 Vm does not need to be acquired continuously while it is ramping up TRACK can be kept low and only when Vopr has reached its desired voltage is TRACK brought high At this stage the acquisition of Vw begins In the example shown a desired voltage is required on the output of the pin driver This voltage is represented by one input to a comparator The uC uP ramps up the input voltage on Vm through a DAC TRACK is kept low while the voltage on Vin ramps up so that Vw is not continually acquired When the desired voltage is reached on the output of the pin driver the comparator output switches The uC uP then knows what code is required to be input in order to obtain the desired voltage at the DUT The TRACK input is now brought high and the part begins to acquire Vin BUSY goes low until Vy has been acquired When BUSY goes high the output buffer is switched from Vy to the output of the DAC MODES OF OPERATION The AD5533 can be used in three different modes These modes are set by two mode bits the first two bits in the serial word The 01 option DA
18. be designed so that the analog and digital sections are separated and confined to certain areas of the board If the AD5533 is in a system where multiple devices require an AGND to DGND connection the connection should be made at one point only The star ground point should be established as close as possible to the device For supplies with multiple pins Vss Vpp and AVcc it is recommended to tie those pins together The AD5533 should have ample supply bypassing of 10 uF in parallel with 0 1 uF on each supply located as close to the package as possible ideally right up against the device The 10 uF capacitors are the tantalum bead type The 0 1 uF capacitor should have low effective series resistance ESR and effective series inductance ESI like the common ceramic types that provide a low impedance path to ground at high frequen cies to handle transient currents due to internal logic switching The power supply lines of the AD5533 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs A ground line routed between the Dyy and SCLK lines will help reduce crosstalk between them not required on a multilayer board as there will be a separate ground plane but separating the lines will hel
19. d new voltage level is set up on the Common Input Pin Vm The desired channel is then addressed via the Parallel Port or the Serial Port When the channel address has been loaded provided TRACK is high the circuit begins to acquire the correct code to load to the DAC in order that the DAC output matches the voltage on Vix The BUSY Pin goes low and remains so until the acquisition is complete The noninverting input to the output buffer is tied to Vm during the acquisition period to avoid spurious outputs while the DAC acquires the correct code The acquisition is completed in 16 us max The BUSY Pin goes high and the updated DAC output assumes control of the output voltage The output voltage of the DAC is connected to the noninverting input of the output buffer Since the internal DACs are offset by 70 mV max from GND the minimum Vry in ISHA Mode is 70 mV The maximum Vin is 2 96 V due to the upper dead band of 40 mV max On power on all the DACs including the offset channel are loaded with zeros Each of the 33 DACs is offset internally by 50 mV typ from GND so the outputs Voyr0 to Voyr31 are 50 mV typ on power on if the OFFS_IN Pin is driven directly by the on board offset channel OFFS_OUT i e If OFFS_IN OFFS_OUT 50 mV gt Vour Gain x Vpac Gain 1 x Vorrs Iw 50 mV Analog Input The equivalent analog input circuit is shown in Figure 6 The Capacitor C1 is typically 20 pF and can be attributed to the pi
20. et voltage can be externally supplied by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself The required offset voltage is set up on Vy and acquired by the offset DAC This offset channel s DAC output is directly connected to OFFS_OUT By connect ing OFFS_OUT to OFFS_IN this offset voltage can be used as the offset voltage for the 32 output amplifiers It is important to choose the offset so that Voyr is within maximum ratings DEVICE UNDER TEST O THRESHOLD VOLTAGE ONLY ONE CHANNEL SHOWN FOR SIMPLICITY Figure 7 Typical ATE Circuit Using TRACK Input REV A 11 AD5533 Reset Function The reset function on the AD5533 can be used to reset all nodes on this device to their power on reset condition This is imple mented by applying a low going pulse of between 90 ns and 200 ns to the TRACK RESET Pin on the device If the applied pulse is less than 90 ns it is assumed to be a glitch and no operation takes place If the applied pulse is wider than 200 ns this pin adopts its TRACK function on the selected channel Viy is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK TRACK Function Normally in the ISHA Mode of operation TRACK is held high and the channel begins to acquire when it is addressed However if TRACK is low when the channel is addressed Vy is switched to the output buffer and an acquisition on the ch
21. he last SCLK falling edge in the 10 bit write and the falling edge of SYNC in the 14 bit read back The serial write and read words can be seen in Figure 8 This feature allows the user to read back the DAC Register code of any of the channels Read back is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on Voyr INTERFACES Serial Interface The SER PAR Pin is tied high to enable the serial interface and to disable the parallel interface The serial interface is controlled by the four pins that follow SYNC Din SCLK Standard 3 wire Interface Pins The SYNC Pin is shared with the CS function of the parallel interface Dour Data Out Pin for reading back the contents of the DAC Registers The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK CAL Bit When this is high all 32 channels acquire Vw simultaneously The acquisition time is then 45 us typ and accuracy may be reduced OFFSET_SEL Bit If this bit is set high the offset channel is selected and Bits A4 A0 are ignored Test Bit This must be set low for correct operation of the part A4 A0 Used to address any one of the 32 channels A4 MSB of address AO LSB DB13 DB0 These are used in both Readback Modes to read a 14 bit word from the addressed DAC Register REV A MSB ESA MODE BIT1 MODE BIT 2 MODE BITS LSB CAL OFFSET_S
22. lling edge of SCLK SER PAR This pin allows the user to select whether the serial or parallel interface will be used If the pin is tied low the parallel interface will be used If it is tied high the serial interface will be used OFFS_IN Offset Input The user can supply a voltage here to offset the output span OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the offset channel OFFS_OUT Offset Output This is the acquired offset voltage that can be tied to the OFFS_IN Pin to offset the span BUSY This output tells the user when the input voltage is being acquired It goes low during acquisition and returns high when the acquisition operation is complete TRACK RESET If this input is held high Vy is acquired once the channel is addressed While it is held low the input to the gain offset stage is switched directly to Vin The addressed channel begins to acquire Vw on the rising edge of TRACK See TRACK Function section for further information This input can also be used as a means of resetting the complete device to its power on reset conditions This is achieved by applying a low going pulse of between 90 ns and 200 ns to this pin See section on RESET Function for further details NOTES Internal pull down devices on these logic inputs Therefore they can be left floating and will default to a logic low condition Internal pull up devices on these logic inputs Therefore they can be left floating and will defa
23. n capacitance and 32 off channels When a channel is selected an extra 7 5 pF typ is switched in This Capacitor C2 is charged to the previously acquired voltage on that particular channel so it must charge discharge to the new level It is essential that the external source can charge discharge this additional capacitance within 1 us 2 us of channel selection so that Vpy can be acquired accurately For this reason a low impedance source is recommended ADDRESSED CHANNEL Figure 6 Analog Input Circuit Large source impedances will significantly affect the performance of the ADC This may necessitate the use of an input buffer amplifier Output Buffer Stage Gain and Offset The function of the output buffer stage is to translate the 50 mV 3 V output of the DAC to a wider range This is done by gaining up the DAC output by 3 52 and offsetting the voltage by the voltage on the OFFS_IN Pin Vour 3 52 x Vpac 2 52 X Vorgs_ IN Vbac is the output of the DAC Vorrs n is the voltage at the OFFS_IN Pin Table I shows how the output range on Vopr relates to the offset voltage supplied by the user Table I Sample Output Voltage Ranges Vorrs_1n V Vpac V Vour V 0 0 05 to 3 0 176 to 10 56 1 0 05 to 3 2 34 to 8 06 2 130 0 05 to 3 5 192 to 5 192 Vout is limited only by the headroom of the output amplifiers Vour must be within the maximum ratings Offset Voltage Channel The offs
24. nction temperatures derate as follows Storage Temperature Range 65 C to 150 C Max Continuous Load Current Junction Temperature Ty max 006 150 C T C per Group mA 74 Lead CSPBGA Package Oja Thermal Impedance 41 C W 70 15 5 Reflow Soldering 90 9 025 Peak Temperaturen o oirean idane naa n 220 C 100 6 925 Time at Peak Temperature 10 sec to 40 sec 110 5 175 125 3 425 135 2 55 150 1 5 ORDERING GUIDE Output Output Package Package Model Function Impedance Voltage Span Description Option AD5533ABC 1 32 Channel ISHA Only 0 5 Q typ 10V 74 Lead CSPBGA BC 74 AD5533ABC 1REEL 32 Channel ISHA Only 0 5 Q typ 10V 74 Lead CSPBGA BC 74 AD5533BBC 1 32 Channel Precision ISHA Only 0 5 Q typ 10 V 74 Lead CSPBGA BC 74 AD5532ABC 1 32 DACs 32 Channel ISHA 0 5 Q typ 10V 74 Lead CSPBGA BC 74 AD5532ABC 2 32 DACs 32 Channel ISHA 0 5 Q typ 20V 74 Lead CSPBGA BC 74 AD5532ABC 3 32 DACs 32 Channel ISHA 500 Q typ 10V 74 Lead CSPBGA BC 74 AD5532ABC 5 32 DACs 32 Channel ISHA 1 kQ typ 10V 74 Lead CSPBGA BC 74 AD5532BBC 1 32 DACs 32 Channel Precision ISHA 0 5 Q typ 10 V 74 Lead CSPBGA BC 74 AD5532HS 32 Channel High Speed DAC 0 5 kQ typ 5V 74 Lead CSPBGA BC 74 EVAL AD5532EB AD5532 AD5533 Evaluation Board Separate Data Sheet CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and
25. o Vour Nonlinearity 0 018 max Input Range 100 mV to 2 96 V 0 006 typ After Gain and Offset Adjustment Gain 3 46 3 6 min max 3 52 typ Offset Error 50 mV max ANALOG INPUT Vm Input Voltage Range 0 3 V Nominal Input Range Input Lower Dead Band 70 mV max 50 mV typ Referred to Vw See Figure 5 Input Upper Dead Band 40 mV max 12 mV typ Referred to Vw See Figure 5 Input Current 1 uA max 100 nA typ Vm Being Acquired on One Channel Input Capacitance 20 pF typ ANALOG INPUT OFFS_IN Input Current 1 uA max 100 nA typ Input Voltage Range 0 4 V min max Output Range Restricted from Vss 2 V to Vpp 2 V VOLTAGE REFERENCE REF_IN Nominal Input Voltage 3 0 V Input Voltage Range 2 85 3 15 V min max Input Current 1 uA max lt 1 nA typ REF_OUT Output Voltage 3 V typ Output Impedance 280 kQ typ Reference Temperature Coefficient 60 ppm C typ ANALOG OUTPUTS Voyr 0 31 Output Temperature Coefficient 10 ppm C typ DC Output Impedance 0 5 Q typ Output Range Vss 2 Vpp 2 V min max Resistive Load 5 5 kQ min Capacitive Load 500 pF max Short Circuit Current 7 mA typ DC Power Supply Rejection Ratio 70 dB typ Vpp 15 V 5 70 dB typ Vss 15 Vt 5 DC Crosstalk 250 uV max ANALOG OUTPUT OFFS_OUT Output Temperature Coefficient 10 ppm C typ DC Output Impedance 1 3 kQ typ Output Range 50 to REF_IN 12 mV typ Output Current 10 uA max Source Current Capacitive Load 100 pF max DIGITAL INPUTS Input Current
26. p Note it is essential to minimize noise on Vy and REFIN lines Particularly for optimum ISHA performance the Vy line must be kept noise free Depending on the noise performance of the board a noise filtering capacitor may be required on the Vy line If this capacitor is necessary then for optimum throughput it may be necessary to buffer the source which is driving Vw Avoid cross over of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feedthrough through the board A microstrip technique is by far the best but not always possible with a double sided board In this technique the component side of the board is dedicated to ground plane while signal traces are placed on the solder side As is the case for all thin packages care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process 15 AD5533 OUTLINE DIMENSIONS 74 Lead Chip Scale Ball Grid Array CSPBGA BC 74 Dimensions shown in millimeters A1 CORNER INDEX AREA 12 00 BSC sQ A M 00000000000 B o c D 1 00 gt Borrom 0 E 10 00 BSC TOP VIEW esca 0 Me Sa o H 00000000000 K o0000 gt 9 0000o L gt 1 00 BSC 1 70 DETAIL A MAX E DETAIL A 0 30 MIN i ES Y COBEANAHIT j azo ESR cea PLANE BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO 192ABD 1 Revision History Location
27. the output level of one channel in response to a full scale change in the output of all other channels It is expressed in uV Output Settling Time This is the time taken from when BUSY goes high to when the output has settled to 0 018 Acquisition Time This is the time taken for the Vy input to be acquired It is the length of time that BUSY stays low OFFS_IN Settling Time This is the time taken from a 0 V 3 V step change in input volt age on OFFS_IN until the output has settled to within 0 39 Digital Feedthrough This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to i e CS SYNC is high It is specified in nV s and is measured with a worst case change on the Digital Input Pins e g from all Os to all 1s and vice versa Output Noise Spectral Density This is a measure of internally generated random noise Random noise is characterized as a spectral density voltage per root Hertz It is measured by loading all DACs to midscale and measuring noise at the output It is measured in nV Hz AC Crosstalk This is the area of the glitch that occurs on the output of one channel while another channel is acquiring It is expressed in nV s Za A Y GAIN ERROR OFFSET ERROR 2 96 3V Vin gt UPPER DEAD BAND Figure 5 ISHA Transfer Function REV A AD5533 Typical Performance Characteristics 0 0024 Ta 25 C
28. ulsewidth t2 20 ns min SCLK Low Pulsewidth t3 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time t4 50 ns min SYNC Low Time ts 10 ns min D y Setup Time te 5 ns min Din Hold Time t7 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Read Back tg 20 ns max SCLK Rising Edge to Dour Valid to 60 ns max SCLK Falling Edge to Dour High Impedance tio 400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Read Back yl 7 ns min SCLK Falling Edge to SYNC Falling Edge Setup Time for Read Back NOTES 1See Serial Interface Timing Diagrams Guaranteed by design and characterization not production tested 3These numbers are measured with the load circuit of Figure 2 SYNC should be taken low while SCLK is low for read back Specifications subject to change without notice PARALLEL INTERFACE TIMING DIAGRAM A4 A0 CAL OFFS_SEL t gt lt t Figure 1 Parallel Write ISHA Mode Only TO OUTPUT PIN 1 6V Figure 2 Load Circuit for Doyr Timing Specifications 4 REV A AD5533 SERIAL INTERFACE TIMING DIAGRAMS SCLK SYNC ta t e Din MSB LSB Figure 3 10 Bit Write ISHA Mode and Both Readback Modes SCLK ty Dout MSB LSB Figure 4 14 Bit Read Both Readback Modes REV A 5 AD5533 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Vpp to AGND e vrai rs 0 3 V to 17 V Vss to AGND habe dia Whee ddan akon 0 3 V to 17 V AVcc to
29. ult to a logic high condition 8 REV A TERMINOLOGY Vin to Vour Nonlinearity This is a measure of the maximum deviation from a straight line passing through the endpoints of the Vy versus Vour transfer function It is expressed as a percentage of the full scale span Offset Error This is a measure of the output error when Vw 70 mV Ideally with Vin 70 mV Vour Gain x 70 Gain 1 x Vorrs_1 mV Offset error is a measure of the difference between Voyr actual and Vour ideal It is expressed in mV and can be positive or negative See Figure 5 Gain Error This is a measure of the span error of the analog channel It is the deviation in slope of the transfer function See Figure 5 It is calculated as Gain Error Actual Full Scale Output Ideal Full Scale Output Offset Error where Ideal Full Scale Output Ideal Gain x 2 96 Ideal Gain 1 x Vorrs_w Ideal Gain 3 52 Output Temperature Coefficient This is a measure of the change in analog output with changes in temperature It is expressed in ppm C DC Power Supply Rejection Ratio DC power supply rejection ratio PSRR is a measure of the change in the analog output for a change in the supply voltage Vpp and Vss It is expressed in dBs Vpp and Vss are varied 5 Vout IDEAL OFFSET ERROR ov 70mV qq LOWER DEAD BAND TRANSFER FUNCTION gt ACTUAL TRANSFER FUNCTION DC Crosstalk This is the dc change in
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