FMC645 User Manual
Contents
1. is located on the left corner of the bottom side SeeFigure 3 Pin Signal No Name 1 3V3 2 GP04 3 GP05 4 GP06 5 GP07 6 GND Table 3 GPIO header pinout 3 2 Fixed point DSP TMS320C6455 The Texas Instruments TMS320C6455 is capable of running at 1 2GHz lt is backward compatible to older Texas Instruments DSPs and has the following external peripheral interfaces DDR2 Memory Controller EMIFA FMC645 User Manual www 4dsp com 7 UM013 FMC645 User Manual ft OSH r1 1 McBSP 2x Serial RapidlO PCI66 EMAC 10 100 1000 GPIO 126 Timers Emulator UTOPIA not available dual purpose pins used for PCI66 HPI not available dual purpose pins used for PCI66 For more information please refer TMS320C6455 Texas Instrument datasheets 3 2 1 DDR2 SDRAM Memory In total 512Mbytes DDR2 SDRAM memory are available on the FMC645 Two 16 bit external memory devices MT47H128M16 with 256Mbytes density are implemented Both external memories operate with the DDR2 memory controller of the DSP When the EMAC is used the DDR2 bus speed is restricted to 250MHz 3 2 2 EMIFA Bus External memory interface A connects to the FMC connector The full 64 bit connection is implemented requiring 108 FMC connections Data bus can also be configured to 32 16 and 8 bits wide An external clock AECLKIN has to be provided by the carrier board It is not allowed to use the internal clock SYSC2. 0 VADJ JTAG see section 3 2 12 3 2 12 JTAG 3 2 12 1 Emulator and Trace Header Preferably connect to a 14 pins emulator header see also Texas Instrument datasheet spru655 Key Pin 6 0 100 oo 0 87 Cable Connector Front View Pins 1 3 5 7 9 11 13 Pins 2 4 6 8 10 12 14 p Note All dimensions are in inches and are nominal dimensions unless otherwise specified Figure 4 14 Pins emulator header 14 pins header target source is implemented on the FMC645 board it can be removed when no emulation desired see section3 1 2 FMC 645 User Manual www ddsp com 11 UM013 FMC645 User Manual Lt OS 11 3 2 12 2 JTAG Chain The JTAG chain on the FMC645 is available for configuration and debugging purposes It includes debugging of the C6455 device when the press fit header is mounted MEE TRST TRSTH DO TDO Rs TDI TDI 14 Pin DSP v Header E c6455 P Figure 5 JTAG chain block diagram In a stacked environment the TDI pin will be decoupled from the TDO pin by the PRST_M2C_L signal coming from the bottom connector TRST TCK TMS TDI and TDO are directly connected between top to bottom connector Bottom connector to stacked FMC TRST TCK TMS TDI TDO PRSNT_M2C_L A 1 4 8 b Ve ZN Y TRST TCK TMS TDI TDO PRSNT_M2C_L Top connector to FMC c
3. Spectrum Clocking Auxiliary power management is not supported 3 2 6 EMAC 10 100 1000 module The EMAC module provides an efficient interface between the DSP and the network community The EMAC module conforms to the IEE802 3 2002 standard describing the carrier sense multiple access with collision detection CSMA CD specifications The Ethernet peripheral port of the DSP connects to the FMC connector The GMII interface is connected to the FMC connector 3 2 7 GPIO The general purpose input output peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs The DSP has a GPIO port with 16 I O but only a maximum of 11 are available on the FMC connector depending of the configuration of the device A 6 Pin header is connected for control purposes see section 0 of the GPIO 4 7 In order to have the maximum GPIO signals available the device has to be configured as follow FMC Signal Name Configurations Mode pins setting SYSCLK4 GP 1 AEA4 0 GP 01 CLKX1 GP 3 AEA5 0 GP 3 FSX1 GP 1 1 AEA5 0 GP 11 DX1 GP 9 AEA5 0 GP 9 CLKR1 GP 0 AEA5 0 GP 0 FSR1 GP 10 AEA5 0 GP 10 DR1 GP 8 AEA5 0 GP 8 Table 4 Dual purposes pins 3 2 8 The peripheral port connects to the FMC dedicated pins The FMC645 card carries a small serial EEPROM 24LC02B which is accessible from the carrier card through the I C bus It connects also to the power
4. 120 C 5 2 Cooling Two different types of cooling will be available for the FMC645 5 2 1 Convection cooling The air flow provided by the chassis fans the FMC645 is enclosed in will dissipate the heat generated by the on board components A minimum airflow of 600 LFM is recommended For stand alone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 5 2 22 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C The FMC645 is designed for maximum heat transfer to conduction cooled ribs A customized cooling frame that connects directly to the surface of the devices is allowed contact 4DSP for detailed mechanical information This conduction cooling mechanism should be applied in combination with proper chassis cooling FMC 645 User Manual www 4dsp com 20 UM013 FMC645 User Manual ft OS r1 1 6 Safety This module presents no hazard to the user 7 EMC The FMC645 is designed to operate from within an enclosed host system whic
5. 4AVC16T245 EMIFA RESETSTAT E3 SN74AVC16T245 EMIFA C2M K7 SN74AVC16T245 EMIFA RESETSTAT K8 SN74AVC16T245 EMIFA RESETSTAT J6 SN74AVC16T245 EMIFA RESETSTAT J7 SN74AVC16T245 EMIFA RESETSTAT F7 SN74AVC16T245 EMIFA RESETSTAT K8 SN74AVC16T245 EMIFA RESETSTAT E6 SN74AVC16T245 EMIFA RESETSTAT E7 SN74AVC16T245 EMIFA RESETSTAT 10 SN74AVC16T245 EMIFA RESETSTAT Kil SN74AVC16T245 EMIFA RESETSTAT J9 SN74AVC16T245 EMIFA RESETSTAT J10 SN74AVC16T245 EMIFA RESETSTAT F10 SN74AVC16T245 EMIFA RESETSTAT Fil SN74AVC16T245 EMIFA RESETSTAT E9 SN74AVC16T245 EMIFA RESETSTAT E10 SN74AVC16T245 EMIFA RESETSTAT K13 SN74AVC16T245 EMIFA M2C K14 SN74AVC16T245 EMIFA M2C J12 SN74AVC16T245 EMIFA M2C J13 SN74AVC16T245 EMIFA M2C F13 SN74AVC16T245 EMIFA M2C F14 SN74AVC16T245 EMIFA M2C E12 SN74AVC16T245 EMIFA M2C FMC645 User Manual www 4dsp com 15 UM013 FMC645 User Manual a n SYSCLK4 E13 SN74AVC16T245 EMIFA M2C J15 SN74AVC16T245 EMIFA C2M J16 SN74AVC16T245 EMIFA M2C F16 SN74AVC16T245 EMIFA RESETSTAT F17 SN74AVC16T245 EMIFA RESETSTAT E15 SN74AVC16T245 EMIFA M2C E16 SN74AVC16T245 EMIFA M2C K16 SN74AVC16T245 EMIFA C2M K17 SN74AVC16T245 EMIFA M2C J18 SN74AVC16T245 EMIFA M2C J19 SN74AVC16T245 EMIFA C2M F19 SN74AVC16T245 EMI
6. C16T245 EMIFA AAOE ASOE H8 SN74AVC16T245 EMIFA AAOE ASOE G9 SN74AVC16T245 EMIFA AAOE ASOE G10 SN74AVC16T245 EMIFA AAOE ASOE H10 SN74AVC16T245 EMIFA AAOE ASOE FMC645 User Manual www 4dsp com 13 UM013 FMC645 User Manual a er H11 SN74AVC16T245 EMIFA AAOE ASOE D11 SN74AVC16T245 EMIFA AAOE ASOE D12 SN74AVC16T245 EMIFA AAOE ASOE C10 SN74AVC16T245 EMIFA AAOE ASOE SN74AVCIGT245 EMIFA AAOE ASOE H13 SN74AVCIGT245 EMIFA AAOE ASOE H14 SN74AVC16T245 EMIFA AAOE ASOE G12 SN74AVCIGT245 EMIFA AAOE ASOE G13 SN74AVCIGT245 EMIFA AAOE ASOE D14 SN74AVCIGT245 EMIFA AAOE ASOE D15 SN74AVCIGT245 EMIFA AAOE ASOE C14 SN74AVC16T245 EMIFA AAOE ASOE C15 SN74AVC16T245 EMIFA AAOE ASOE H16 SN74AVCIGT245 EMIFA AAOE ASOE H17 SN74AVCIGT245 EMIFA AAOE ASOE G15 SN74AVCIGT245 EMIFA AAOE ASOE G16 SN74AVCIGT245 EMIFA AAOE ASOE D17 SN74AVCIGT245 EMIFA AAOE ASOE D18 SN74AVCIGT245 EMIFA AAOE ASOE C18 SN74AVCIGT245 EMIFA AAOE ASOE C19 SN74AVCIGT245 EMIFA AAOE ASOE H19 SN74AVCIGT245 EMIFA AAOE ASOE H20 SN74AVCIGT245 EMIFA AAOE ASOE G18 SN74AVCIGT245 EMIFA AAOE ASOE G19 SN74AVCIGT245 EMIFA AAOE ASOE D20 SN74AVCIGT245 EMIFA AAOE ASOE D21 SN74AVCIGT245 EMIFA AAOE ASOE C22 SN74AVCIGT245 E
7. FA M2C F20 SN74AVCI6T245 EMIFA M2C E18 TXTB108 GPIO BIDIR E19 108 GPIO BIDIR K19 108 GPIO BIDIR K20 TXTB108 GPIO BIDIR J21 TXTB108 McBSP BIDIR J22 108 McBSP BIDIR K22 108 McBSP BIDIR K23 108 McBSP BIDIR K25 108 McBSP BIDIR K26 108 McBSP BIDIR J24 108 McBSP GPIO BIDIR J25 108 McBSP GPIO BIDIR F22 108 McBSP GPIO BIDIR F23 108 McBSP GPIO BIDIR E21 108 McBSP GPIO BIDIR E22 108 McBSP GPIO BIDIR F25 108 McBSP BIDIR F26 TXTB108 Clock GPIO BIDIR E24 SN74AVC16T245 EMAC C2M E25 SN74AVC16T245 C2M K28 SN74AVC16T245 EMAC M2C K29 SN74AVC16T245 EMAC C2M J27 SN74AVC16T245 EMAC C2M FMC645 User Manual www 4dsp com 16 Jor UMO013 FMC645 User Manual r1 1 J28 SN74AVCIGT245 EMAC M2C F28 SN74AVCIGT245 EMAC C2M F29 SN7A4AVCIGT245 EMAC C2M E27 SN7A4AVCIGT245 EMAC M2C E28 SN74AVCIGT245 EMAC M2C K31 SN7A4AVCIGT245 EMAC M2C K32 SN7A4AVCIGT245 EMAC M2C J30 SN74AVCIGT245 EMAC M2C J31 SN7A4AVCIGT245 EMAC M2C F31 SN7A4AVCIGT245 EMAC M2C F32 SN74AVCIGT245 EMAC M2C E30 SN74AVCIGT245 EMAC M2C E31 SN7A4AVCIGT245 EMAC M2C K34 SN7A4AVCIGT245 EMAC M2C K35 5 6 245 EMAC M2C J33 SN74AVCIGT245 EMAC M2C J34 SN7A4AVCIG
8. LKA to clock the EMIFA bus All external memories interfacing with the EMIFA bus should operate using AECLKOUT clock Also it is possible to connect four external memory interface CE2 5 for asynchronous or synchronous accesses 3 2 3 McBSP Two McBSPs peripheral ports connect to the FMC connector providing a full duplex communication The McBSP consists of a data path and a control path that connect to the FMC connector Each McBSP interface includes separate pins for transmission and reception of data Four other pins for control information clocking and frame synchronization Due to dual purpose capability the McBSP1 peripheral can be disabled in order to enable the GPIO pins purpose 3 2 4 Serial RapidlO Four SRIO transceivers are connected to gigabit IO on the FMC connector The SRIO peripheral is a master peripheral and requires LVDS clock REF RIO at 125MHz provided by a crystal oscillator on the FMC645 Special care has been taken during the hardware design in order to operate at a data rate of 3 125Gbps differential pair 3 2 5 PCI66 The DSP connects its PCI interface through a PCI PCle bridge Pericom PI7C9X110 to the FMC connector The PCI PCle bridge is set up in transparent bridge and forward mode The PCI bus is operating at 66MHz There is a local clock FMC645 User Manual www 4dsp com 8 UM013 FMC645 User Manual ft OS r1 1 source for the PCI express so the FMC645 cannot be used in environments that use Spread
9. MIFA AAOE ASOE C23 SN74AVCIGT245 EMIFA AAOE ASOE H22 SN74AVCIGT245 EMIFA AAOE ASOE H23 SN74AVCIGT245 EMIFA AAOE ASOE G21 SN74AVCIGT245 EMIFA AAOE ASOE G22 SN74AVCIGT245 EMIFA AAOE ASOE H25 SN74AVCIGT245 EMIFA AAOE ASOE H26 SN74AVCIGT245 EMIFA AAOE ASOE G24 SN74AVCIGT245 EMIFA AAOE ASOE G25 SN74AVCIGT245 EMIFA AAOE ASOE D23 SN74AVCIGT245 EMIFA AAOE ASOE D24 SN74AVCIGT245 EMIFA AAOE ASOE H28 SN74AVCIGT245 EMIFA AAOE ASOE H29 SN74AVCIGT245 EMIFA AAOE ASOE G27 SN74AVCIGT245 EMIFA AAOE ASOE G28 SN74AVCIGT245 EMIFA AAOE ASOE FMC645 User Manual www 4dsp com 14 UM013 FMC645 User Manual a er D26 SN74AVC16T245 EMIFA AAOE ASOE D27 SN74AVC16T245 EMIFA AAOE ASOE C26 SN74AVC16T245 EMIFA AAOE ASOE C27 SN74AVC16T245 EMIFA AAOE ASOE H31 SN74AVC16T245 EMIFA AAOE ASOE H32 SN74AVC16T245 EMIFA AAOE ASOE G30 SN74AVC16T245 EMIFA AAOE ASOE G31 SN74AVC16T245 EMIFA AAOE ASOE H34 SN74AVC16T245 EMIFA AAOE ASOE H35 SN74AVC16T245 EMIFA AAOE ASOE G33 SN74AVC16T245 EMIFA AAOE ASOE G34 SN74AVC16T245 EMIFA AAOE ASOE H37 SN74AVC16T245 EMIFA M2C H38 SN74AVCI6T245 EMIFA M2C G36 SN74AVC16T245 EMIFA M2C G37 SN74AVC16T245 EMIFA M2C F4 SN74AVCI6T245 EMIFA RESETSTAT F5 SN74AVC16T245 EMIFA RESETSTAT E2 SN7
10. NI LVDS to C2M CLK2 BIDIR K5 LVTTL C2M CLK3 BIDIR P J2 CLKIN2 LVDS to C2M CLK3 BIDIR J3 LVTTL C2M GBTCLKO P D4 M2C GBTCLKO N D5 M2C P B30 M2C GBTCLK1_N B21 M2C Table 8 Clock connections FMC Name FMC connector ball name Note VREF A M2C H1 Not connected VREF B M2C K1 Not connected VIO B M2C J39 K40 Connects to VADJ FMC 645 User Manual 18 www 4dsp com UM013 FMC645 User Manual ft OS 11 1 Pulled up with 10K TCK TMS TDI TDO D29 033 030 D31 JTAG signals see section 3 2 12 TRST L and D34 3V3AUX D32 Connects to EEPROM SCL SDA C30 C31 Connect to EEPROM power monitoring C6455 device GAO GA1 G34 G35 Connect to EEPROM PG M2C D1 Connects to a blue LED The LED is PG CoM F1 2 power to carrier is PRSTN_M2C_L H2 Connects to GND Table 9 MISC connections 4 Power characteristics Power to the FMC645 is supplied through 3 3V 12V and VADJ The FMC645 module allows any level between 1 5V and 3 3V on VADJ Voltage pins Max Amps Max Watt 3 3V 4 3A 10 W 12V 2 1A 12 W 3P3VAUX 1 20 mA 66 mW VADJ 1 5 to 3 3V 4 4A 10 W Table 10 FMC standard power specification The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC645 card to minimize the effect of power supply noise on clock generation There is noise filte
11. T245 EMAC M2C F34 SN74AVCIGT245 EMAC M2C F35 SN7A4AVCIGT245 EMAC M2C K37 TXTB108 EMAC BIDIR K38 TXTB108 EMAC BIDIR J36 SN74AVC16T245_ Clock Reset IR C2M NMI Q J37 SN74AVCIGT245 Clock Reset IR C2M POR Q E33 SN74AVCIGT245 Clock Reset IR M2C RESETSTAT Q E34 SN74AVCI6T245 Clock Reset IR C2M RESET Q F37 SN7A4AVCIGT245 Timers C2M F38 SN7A4AVCIGT245 Timers C2M E36 SN74AVCI6T245 Timers M2C E37 SN7A4AVCIGT245 Timers M2C Table 6 LA HA HB Bank connections max 160 single ended I F Transceiver Count FMC Signal Name FMC connector Level translator Signal group Direction ball name type C2 None SRIO C2M C3 None SRIO C2M A22 None SRIO C2M FMC645 User Manual www 4dsp com 17 UM013 FMC645 User Manual ILES n A23 None SRIO C2M A26 None SRIO C2M A27 None SRIO C2M A30 None SRIO C2M A31 None SRIO C2M C6 None SRIO M2C C7 None SRIO M2C A2 None SRIO M2C A3 None SRIO M2C A6 None SRIO M2C A7 None SRIO M2C A10 None SRIO M2C A11 None SRIO M2C A34 None PCle C2M A35 None PCle C2M A14 None PCle M2C A15 None PCle M2C Table 7 MGT connections FMC Name FMC DSP Name Level Direction connector Translation ball name CLKO M2C P H4 SYSCLK4 LVTTL to M2C CLKO_M2C_N H5 LVDS M2C M2C P G2 SYSCLK4 LVTTL to M2C CLK1_M2C_N G3 LVDS M2C CLK2_BIDIR_P K4 CLKI
12. UM013 FMC645 User Manual ft OSH 1 1 FMC645 User Manual 4DSP LLC USA This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2015 UM013 FMC645 User Manual ft OSH r1 1 Revision History 2012 03 01 First draft 2012 03 06 Modifications after first review 2012 03 22 Processed all comments D E E 2014 04 25 Added a section that describes an optional 1 1 modification that is required when targeting Xilinx reference boards FMC645 User Manual www 4dsp com UM013 FMC645 User Manual r1 1 Table of Contents 1 Acronyms and related 224 42 4 4 152 Related DOCUMEN RUE 4 1 2 General descriptioN 5 2 nc Cni esc P vess ts rsrs e n 5 2 1 Requirements and handling instructions essen 5 32 Hardware COS IO ee 5 3 1 Physical SBeollIGallOTS EN 6 SAPE ME UE n gIed 20M 6 221 02 zie s NO MT 6 22153 GPIO Deaden METRI 7 3 2 Fixed point DSP 5320064 5 eina iui das ee cd acea 7 3 2 1 DDR2 SDRAM 8 32 2 EMIFA BUS mam dede e 8 dud ihe Ubi nsi edi i eT 8 32A Senah R
13. and temperature monitoring device ADT7411 The FMC connector allocates two dedicated pins for the 2 peripherals It connects to the DSP the power monitoring device and the EEPROM The following table shows 12 addresses allocation Peripheral Address DSP Software dependent EEPROM 1010 XXX Power Monitoring 1001 XXX Table 5 I2C bus addresses The EEPROM contains information about the FMC as required by the FMC standards Customers are not allowed to make changes to the EEPROM contents FMC645 User Manual www 4dsp com 9 UM013 FMC645 User Manual Lt OS r1 1 3 2 9 Timers The FMC645 has two general purpose timers 0 and Timer1 connected to the FMC connector requiring 4 pins Each of which can be configured as a general purpose timer or a watchdog timer The timers can be used to time events count events generate pulses interrupt the CPU and send synchronization events to the EDMAS channel controller 3 2 10 Clocks and reset The DSP requires two clocks coming from the carrier board 1 CLKIN1 Should be less than 50MHz internal system clock of 1200MHz can be achieved with 40MHz and PLL x30 2 CLKIN2 If EMAC is enabled CLKIN2 frequency must be 25 MHz If EMAC is disabled refer to the datasheet of the DSP for valid range of CLKIN2 Both clocks should be driven from the FMC carrier on the FMC dedicated LVDS clock signals LVDS to LVTTL 3 3V level translator SGN65LVELT23 is implement
14. apidlO er 8 ERR Rem 8 326 10 100 1000 module iore ort lobis apr iere RR iU 9 HQ 9 328 9 222 MNES RR S 10 3 2 10 Clocks and FOSGL 10 3 2 11 wire ERE 11 SA Py o 11 3 2 13 JDevice COPDIOHUEllOr ei Dee o beUi 12 33 iso ied dua 13 3 4 FMC connector Pin p Er sd e eee 13 4 PowercharacterisliCS u idee qu om en EORR RE URN LR MEN PELICULA EI CONTRE RENE 19 gt vo duos 19 5 20 E 20 52 etr DT x T ee 20 EE SO eie ETT 20 324 s d IRA dla UR RERUM UNE 20 21 ZEN e 21 CMM CIV 21 FMC645 User Manual www 4dsp com 3 UM013 FMC645 User Manual ft OSH 1 1 1 Acronyms and related documents 1 1 Acronyms ADC Analog to Digital Converter BLAST Board Level Advanced Scalable Technology DAC Digital to Analog Converter Digitally Controlled Impedance DDR Double Data Rate DSP Digi
15. arrier Figure 6 JTAG connections 3 2 13 Device Configuration On the C6455 device certain device configurations like boot mode pin multiplexing and endianess are selected at device reset The status of the peripherals enabled disabled is determined after device reset The logic level of the AEA 19 0 ABA 1 0 and PCI EN pin is latched at reset to determine the device configuration PCI EN is pulled up on the FMC645 and cannot be driven low by the user To avoid contention the control device should only drive the EMIFA pins when RESETSTAT is low To see the C6455 device configuration pins in detail please refer to the Datasheet TMS320C6455 Rev 06 2011 Texas Instrument The timing diagram of the reset scheme needs to be taken into account 4DSP recommends keeping the RESET pin de asserted all the time and use only the POR pin The configuration pins are latched upon rising edge of the POR pin The configuration should be valid 6 CPU clock cycles before and after this rising edge The RESETSTAT pin is going high after POR with a delay The following configuration sequence is recommended FMC 645 User Manual www 4dsp com 12 UM013 FMC645 User Manual Sr aa The FPGA asserts POR while keeping the configuration pins Hi Z Once RESETSTAT is asserted by the DSP the FPGA can actively drive the configuration pins After a delay of at least 6 CPU clock cycles the FPGA may release POR After a delay of 6 CPU clock cycles the FPGA
16. ed to connect to the DSP FMC connector requires reference clock for the Gigabit block Transceiver 1 GBTCLKO M2C LVDS clock operating at 125MHz 2 GBTCLK1 is connected to the bottom connector see section 0 The following clock reset interrupt signals are connected to the FMC SYSCLK4 GPO01 NMI DSP Non maskable interrupt edge driven POR DSP power on reset Pcie fundamental reset to initialize international state machine RESETSTAT Indicates when the DSP is in reset drive DSP configuration connections Reset and PCI RESET are kept at inactive state Please note Some carrier boards are not capable of driving CLKIN1 and CLKIN2 due to the use of different types of clock buffers on the carrier board Contact factory for a modification to the FMC645 board in case CLKIN1 and CLKIN2 signals are not supported This is typically the case for Xilinx reference boards like the VC707 and ML605 FMC 645 User Manual www 4dsp com 10 UM013 FMC645 User Manual ft OS r1 1 3 2 11 Stacked FMC The FMC connector as defined in ANSI VITA 57 1 is referred as the top FMC connector The FMC645 can be used in a stacked environment when the bottom FMC connector is mounted By default this connector is not mounted The following connections are available between the top and bottom FMC connector e Gigabit data signals DP 5 9 M2C P N DP 5 9 C2M P N Gigabit reference clock GBTCLK1 M2C P N e RESO 3P3VAUX 12
17. h is built to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 8 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional FMC645 User Manual www 4dsp com 21
18. ion 1 and without front panel I O On the top level all the main active components and the FMC connector are placed see Figure 2 Power Supply 12V Figure 2 Top level floorplan On the bottom level a debug header and GPIO headers can be placed see figure 3 TP 1V25C 1 25 0 m 23 mc ge 9 5 ex Figure 3 Bottom level floorplan 3 1 2 Emulator Header The FMC645 includes a 14 pins emulator header for onboard debugging purposes The emulator header Part number 223578 is a press fit removable header located on the left corner of the bottom side See Figure 3 FMC645 User Manual www 4dsp com UM013 FMC645 User Manual ft OSH r1 1 To communicate with the emulator the target source is two rows of seven pins Table 2describes the Emulation signals Pin Signal Description No Name 1 TMS TEST MODE SELECT 2 TRST TEST CLOCK 3 TDI TEST DATA INPUT 4 GND 5 PD PRESENT DETECT Tied to 3 3V 6 No Pin 7 TDO TEST DATA OUTPUT 8 GND 9 RTCK TEST CLOCK RETURN 10 GND 11 TCK TEST CLOCK 12 GND 13 EMUO EMULATION PIN O0 14 EMU1 EMULATION PIN 1 Table 2 Emulator header pinout Note When the debug header is placed the FMC645 board is not anymore compliant with the FMC mechanical specifications 3 1 3 GPIO header The FMC645 offers a 6 pin header for general purpose input output with 0 100mm pitch The header Part name 223080
19. must make the configuration pins Hi Z The FPGA should not wait until the RESETSTAT signal is released by the DSP due to propagation delays in the level translators this could cause collisions 3 3 Level translation Level translation is implemented to translate signals from 3 3V LVTTL DSP side to VADJ FMC side In total that requires 160 level translations Two sorts of level translators are used TXTB108 and SN74AVC16T245 The TXTB108 is a low data rates auto sensing bidirectional buffer The SN74AVC16T245 bidirectional buffer provides higher data rates 3 4 FMC connector Pin list The following table shows the number of connections on the regular I O banks on the FMC which is limited to a maximum of 160 All connections are populated and level translation is implemented from 3 3V on the DSP side to VADJ on the FMC side VADJ can be any level between 1 5V and 3 3V Signal group Pin Count DSP I O Level Translation Clock Reset IRQ LVTTL 3 3V CMOS VADJ Total 160 0 Dual purpose SYSCLK4_GP01 can be used either 01 or SYSCLK4 Dual purpose pins for McBSP1 can be used either McBSP or GPIO 6 Pins FMC Signal Name FMC Level translator Signal group Direction connector ball type name G10 SN74AVC16T245 EMIFA AAOE ASOE G7 SN74AVC16T245 EMIFA AAOE ASOE D8 SN74AVC16T245 EMIFA AAOE ASOE D9 SN74AVC16T245 EMIFA AAOE ASOE H7 SN74AV
20. ring implemented with beads and capacitance on analog power planes Clean voltage at 1 8V is derived from 12V through a switched regulator Clean voltage at 1 25V is derived from 3 3V through a switched regulator TPS63020 Clean voltage at 0 9V is derived from 1 8V The DSP consumes 3 4W assuming the following operating conditions 100 CPU utilization at 1200 MHz DDR2 at 100 utilization 250 MHz EMIFA bus 100Mhz 32 bits two 166 MHz McBSPs at 100 utilization two 75 MHz Timers at 100 utilization and room temperature 25 C In total the maximum power consuming for the FMC645 is 9W 4 1 Power monitoring One ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature of the C6455 device The information can be read out through the 2 bus Refer to the datasheet of the ADT7411 for detailed information Parameter ADT7411 Formula address 1001 000 FMC 645 User Manual www 4dsp com 19 UM013 FMC645 User Manual ft OSH 11 3V3 External AIN1 AIN2 C6455 Temperature External AIN3 1V8 External AIN4 1V25 Core External AIN5 1V25 IO External AIN6 VADJ AIN6 2 External AIN7 3V3AUX 7 2 External AIN8 VREFSSTL Table 11 Monitoring device connections 5 Environment 5 1 Temperature Operating temperature 0C to 60 C Commercial 40 C to 85 Industrial Storage temperature e 40 C to
21. ription The FMC645 is a digital signal processor FMC daughter card based on TI 1 2GHz TMS320C6455 DSP The FMC645 daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The card has a high pin count connector and can be used in a conduction cooled environment There is no front panel I O The card is equipped with power supply and temperature monitoring and offers several power down modes to switch off unused functions and peripheral interfaces FMC HPC 5320 6455 DSP 1 2GHz 64 bit 166MHz McBSP 2 EMAC GMII RocketlO 24LC02B ADT7411 PCle 1 lane 32 bit 66MHz PCle PCI bridge Figure 1 FMC block diagram 2 Installation 2 1 Requirements and handling instructions The FMC645 daughter card must be installed on a carrier card compliant to the FMC standard The FMC carrier card must support the high pin count connector HPC 400 pins The FMC carrier card must support VADJ VIO B voltage of 1 5V to 3 3V LVCMOS LVTTL signaling Do not flex the card and prevent electrostatic discharges by observing ESD precautions when handling the card 3 Hardware design FMC645 User Manual www 4dsp com 5 UM013 FMC645 User Manual Lt SH r1 1 3 1 Physical Specifications 3 1 1 Board Dimensions The FMC645 card fully complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module without reg
22. tal Signal Processing EPROM Erasable Programmable Read Only Memory FBGA Fineline Ball Grid Array FMC FPGA Mezzanine Card FPGA Field Programmable Gate Array GPIO General Purpose Input Output JTAG Join Test Action Group LEB Local Expansion Bus LED Light Emitting Diode LVTTL Low Voltage Transistor Logic level LSB Least Significant Bit s LVDS Low Voltage Differential Signaling MGT Multi Gigabit Transceiver MSB Most Significant Bit s PCB Printed Circuit Board PCI Peripheral Component Interconnect PCl e PCI Express PLL Phase Locked Loop QDR Quadruple Data rate SBC Single Board Computer SDRAM Synchronous Dynamic Random Access memory SOC System On Chip SRAM Synchronous Random Access memory SSP Synchronous Serial Port TTL Transistor Logic level Table 1 Acronyms 1 2 Related Documents FMC Specification ANSI VITA 57 1 2010 Datasheet TMS320C6455 Rev 06 2011 Texas Instrument Datasheet TMS320C645x DSP SRIO Texas Instrument SPRU976 Datasheet TMS320C6000 DSP McBSP Texas Instrument SPRU580 Datasheet TMS320C645x DSP Texas Instrument SPRU971 Datasheet TMS320C645x DSP GPIO Texas Instrument SPRU724a Datasheet 0108 Rev 09 2011 Texas Instrument Datasheet SN74AVC16T245 Rev 08 2005 Texas Instrument FMC645 User Manual www 4dsp com 4 UM013 FMC645 User Manual et OSH 11 1 3 General desc
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