PMC230A PCI Mezzanine Card User`s Manual
Contents
1. UNPACKING AND CARD CAGE BOARD Default Hardware Jumper Configuration Analog Output Ranges amp Corresponding Digital Codes Analog Output Range Hardware Jumper Configuration Software Configuration xm Front Panel Field I O Connector 1 Analog Outputs Noise and Grounding Considerations External Trigger PCI Local Bus Connector 3 0 PROGRAMMING PCI Configuration Address Configuration MEMORY ni Control Register maaa hua teer o uud Calibration Coefficient Access Register Calibration Coefficient Status Register Start Convert Register DAC Channel DAC MODES OF Single Convert From DAC2. Single PMC Module ses 15 11 mm 0 595 in See Drawing 4501 859 Stacking Height 10 0 mm 0 394 in Length eese 149 0 mm 5 866 in Width 74 0 mm 2 913 in Board Thickness 1 59 mm 0 062 in Connectors PCI Local Bus Interface Two 64 pin female receptacle header AMP 120527 1 or equivalent Field x innere 50 pin SCSI 2 female receptacle header AMP 787082 5 or equivalent Power Requirements PMC230A 8 ov Typical 5596 12V 15 12V 5 1 Maximum rise time of 100mS ENVIRONMENTAL Operating Temperature 0 C to 70 C 40 C to 85 C E Versions SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE Note The extended temperature grade version of the DAC714 is no longer available from the manufacturer Acromag has performed operational tests of sampled commercial grade components over the extended temperature range without failure All DAC714s usec on the E version of the PMC230A have been functionally tested by an independent third party laboratory for use in extended temperature applications except for verification of analog output specifications Relative Humidity Storage Temperature Non Isolated Radiated Field Immunity Electromagnetic Interference Imm
3. NOTES 1 SHIELDED CABLE IS RECOMMENDED FOR LOWEST NOISE SHIELD IS CONNECTED TO GROUND REFERENCE AT ONLY ONE END TO PROVIDE SHIELDING WITHOUT GROUND LOOPS ALL 8 CHANNELS ARE REFERENCED TO ANALOG COMMON AT THE PMC230 TO AVOID GROUND LOOPS DO NOT CONNECT GROUNDED CHANNELS TO THE NEGATIVE SIDE OF THE OUTPUT VL lt VO DUE TO VOLTAGE DROPS ACROSS THE LEAD RESISTANCE OF THE WIRE IT IS RECOMMENDED THAT A HIGH RESISTANCE LOAD WITH A SHORT WIRE RUN BE CONNECTED AT THE OUTPUT TO REDUCE THE EFFECTS OF LEAD AND SOURCE RESISTANCE VOLTAGE DROPS IN THE WIRE PMC23 ANALOG OUTPUT CONNECTION DIAGRAM EARTH GROUND CONNECTION AT POWER SUPPLY TYPICAL 4501 864A Quv92 ANINVZZAW IOd VOECOWd SAIYAS FINGOW LAdLNO SOIWNV ALISN3Q HOIH LId 91 8L ANALOG OUTPUT CHANNELS 1 0 NTERFACE P1 EXTERNAL TRIGGER INPUT OR OUTPUT CALIBRATION MEMORY EEPROM crock CHANNEL J3 RANGE SELECTION ANALOG SIGNAL CHANNEL 7 DIGITAL TO ANALOG CONVERTER CHANNEL DATA e CONTROL J10 RANGE SELECTION ANALOG SIGNAL DIGITAL TO ANALOG CONVERTER CHANNEL 7 DATA COMMON I CALIBRATION MEMORY CONTROL LOGIC PARALLEL TO SERIAL CONVERTER sooess oara lt DATA BUS i PCI BUS LOGIC 3 ADDRESS BUS
4. and ranges is given in hex The coefficients are 16 bit values with the most significant byte at the even addresses and the least significant bytes at the odd addresses The calibration coefficients are stored as 1 4 LSB s For additional details on the use of the calibration coefficients refer to the Use of Calibration Data section Table 3 4 Offset and Gain Address Memory Map Offset Coefficient Gain Coefficient Channel Address Hex Address Hex MSB LSB MSB LSB 0 2 2 2 2 0 40 4t 42 4 6 5 59 5A 5 Calibration Coefficient Status Register Read 219H The Calibration Coefficient Status register is a read only register and is used to access the calibration coefficient read data and determine the status of a read cycle initiated by the Calibration Coefficient Access register In addition this register is used to determine the status of a write cycle to the coefficient memory Bit 1 of this register when set indicates the coefficient memory is busy completing a write cycle All read accesses to the Calibration Coefficient Status register initiate an approximately 1m second access to the coefficient memory Thus you must wait 1m second after reading this status register before a new read or write cycle to the coefficient memory can be initiated If not you will get invalid data A read request of the coefficient memory initiated through the Calibration Coefficient Access re
5. Acromag termination panel 5025 552 from the front panel via round shielded cable Model 5028 187 Front panel connector P1 pin assignments are shown in Table 2 3 When reading Table 2 3 note that channel designations are abbreviated to save space For example channel 0 is abbreviated as CH00 amp CH00 for the amp connections respectively Further note the output signals all have the same ground reference CH00 and the minus leads of all other channels are connected to analog common on the module SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE Table 2 3 PMC230A Field I O Pin Connections for P1 Pin Description Number Pin Description Number COMMON 6 COMMON 3 cH2 8 COMMON 3 COMMON 9 10 Notes 1 The minus leads of all channels are connected to analog common on the module Analog Outputs Noise and Grounding Considerations All output channels are referenced to analog common on the module See Drawing 4501 864 for analog output connections but each channel has a separate return minus lead to maintain accuracy and reduce noise Still the accuracy of the voltage output depends on the amount of current loading impedance of the load and the length impedance of the cabling High impedance loads e g loads gt 100KQ provide the best accuracy For low impedance loads the PMC230A can source up to 5mA but the effects of source and c
6. As an output an active low TTL signal can be driven to additional PMC230As thus providing a means to synchronize the conversions of multiple PMC230As The additional PMC230As must program their external trigger for signal input and convert on external trigger only mode The trigger pulse generated is low for typically 125n seconds See section 3 0 for programming details to make use of this signal PCI Local Bus Connector The PMC230A module provides a 32 bit PCI interface to the carrier CPU via two 64 pin connectors These connectors are 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector of the carrier CPU board AMP 120521 1 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric screws and spacers are supplied with the PMC module to provide additional stability for harsh environments see Drawing 4501 859 for assembly details The pin assignments of the PCI local bus connector are standard for all PMC modules according to the PCI Mezzanine Card Specification see Tables 2 4 and 2 5 Table 2 4 PMC Connector Pin Assignments for J1 32 bit PCI SignalName Pin SignalName Pins Te 5 6 BUSMODE1 7 v 8 9 PCFRSVD 10 REQR 18 GND 25 27 SDONE 41 SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE Signal Name P
7. CompactPCI IS 0 540 13 720mm 0 045 1 143mm SEE NOTE 4 PMC MODULE CONNECTORS 9 80 20 32mm INTERBOARD SEPARATION PLANES PMC CARRIER CPU BOARD CONNECTORS PMC MODULE TO PMC CARRIER CPU BOARD MECHANICAL ASSEMBLY 4501 859A Qquv9 ANINVZZAW IOd VOECOWd SAIYAS FINGOW LNdLNO DOWNY ALISNIQ HOIH LIg 9r 9L 2 913 74 00 FIELD 170 INTERFACE l DIMENSIONS ARE IN INCHES MILLIMETERS N G N G mm J1 J2 COMPONENT SIDE VIEW 5 866 LLL 149 00 ANALOG OUTPUT RANGE SELECTION JUMPER SETTINGS DESIRED OUTPUT OUTPUT J3 TO J10 J3 TO J10 ADC OUTPUT SPAN TYPE PINS 1 amp 2 PINS 3 amp 4 RANGE VDC VOLTS THE BOARD IS SHIPPED WITH THE DEFAULT JUMPER SETTING FOR THE 10 TO 1 VOLT DAC OUTPUT RANGE AS SHOWN IN THE ABOVE DIAGRAM PMC23 JUMPER LOCATIONS 4501 863B PMC LOGIC INTERFACE CONNECTORS Qquv9 ANINVZZAW VOECOWd SAIYAS FINGOW LAdLNO SO TVNV ALISN3Q HOIH LIg 94 L x RiEAD R SOURCE Y LI y ii Pd CH7 WW 1 ici WY VL Vo d Pd SEE NOTE 4 SEE NOTE 3 LOAD 7 AAA _ i i LEAD b EXTERNAL TRIGGER bod bod 49 SIGNAL RETURN Od i 1 FOR EXTERNAL TRIGGER a bd 48 lt E 1 gt v ANALOG SHIELD COMMON SEE NOTE E PMC CARRIER PMC230 CPU BOARD Pl ANALOG PMC230 DIGITAL R SOURCE NNN R SOURCE AAA p m NOTE 1
8. INCHES MILLIMETERS 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 TOLERANCE 0 020 10 5 1 3 5 7 9 1113 15 17 19 2123 25 27 29 31 33 35 37 39 41 43 45 47 49 d MODEL 5025 552 TERMINATION PANEL 58 5 4501 464A E FRONT VIEW Quv92 ANINVZZAW IOd VOECOWd SAIYAS FINGOW LAdLNO SO TVNV ALISN3Q HO9IH LIg 94
9. The PMC230A offers a variety of features which makes it an ideal choice for many industrial and scientific applications as described below KEY PMC230A FEATURES e DAC 16 Bit Resolution 16 bit monolithic DAC with bipolar voltage output ranges of 10V 5V and an unipolar output range of 0 to 10V e 10 Conversion Time A maximum recommended conversion rate of 100KHz for specified accuracy is supported The absolute maximum conversion rate of 150KHz is also supported e Reliable Software Calibration Calibration coefficients stored on board provide the means for accurate software calibration for both gain and offset correction for each of the channels of the module e Resetis Failsafe For Bipolar Output Ranges When the module is jumpered for bipolar operation the analog outputs are reset to 0 volts upon power up or issue of a software or hardware reset This eliminates the problem of applying random output voltages to actuators during power on sequences SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE e Individual Output Control Output channels can be individually updated Other channels not updated maintain their previous analog output values e Simultaneous Output Control All output channels are simultaneously updated upon issue of a software or external trigger e Hardware Jumper Setting For Selection of DAC Ranges Both bipolar 5V 10V and unipolar 0 to 10V ranges are
10. Z lt CONTROL BUS NOTE ALL ANALOG OUTPUT CHANNELS ARE REFERENCED TO ANALOG GROUND TO AVOID GROUND LOOPS DO NOT CONNECT GROUNDED LOADS TO THE NEGATIVE SIDE OF THE OUTPUT PMC230 BLOCK DIAGRAM PMC LOGIC INTERFACE J1 J2 lt X 4501 865A ANINVZZAW 19 VOECOWd SAIYAS FINGOW LAdLNO SO TVNV ALISN3Q HOIH LIS 9L 6L GROUND SHIELD ON CABLE SCHEMATIC a TO P2 SHIELDED BACKSHELL P P1 2 e Y 50 50 49 49 48 48 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 32 51 51 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 VU 1 INCH 7 0 25 INCH TO MODEL 5025 552 1 0 TERMINATION TO MODULE FIELD 1 0 CONNECTOR PANEL Jo lt 2 METERS 78 72 INCHES 4 0 0 0 INCHES P2 P1 TOP VIEW STRAIN RELIEF 1004 534 gt gt PIN 49 lt N lt SPRING SHRINK TUBING LATCH CABLE 2006 353 PIN 50 X 2002 358 1 INCH LENGTH IN 25
11. for details on how to read the coefficients from memory Using equation 2 you can determine the corrected count from the ideal count For the previous example equation 1 returned a result 16 384 for the Ideal Count to produce an output of 5 Volts Assuming that a gain error of 185 and an offset error of 43 are read from memory on the PMC230A for the desired channel substitution into equation 2 yields 185 43 Corrected Count 16 384 1 16 361 6875 4565536 4 If this value rounded to 16 362 is used to program the DAC output the output value will approach 5 Volts to within the calibrated error see the specification chapter for details regarding maximum calibrated error Calibration Programming Example Assume it is necessary to program channel 0 with an output of 2 5 Volts Also assume the bipolar range centered around 0 Volts is 10 to 10 Volts The Single Conversion from DAC Register mode of operation which is available on the PMC230A module is used in this example 1 Execute Write of 0100H to Control Register at Base Address 200H a External Software and Internal Hardware timer generated triggers are all enabled b Single Conversion from DAC registers is enabled 2 Read the calibration memory to retrieve channel 0 s unique offset coefficient To obtain the 16 bit offset coefficient two read accesses of the coefficient memory are required To initiate a read of channel 0 s most significa
12. has a D Shell and the IDC connector has a polarizing key to prevent improper installation Schematic and Physical Attributes See Drawing 4501 758 Electrical Specifications 30 VAC per UL and CSA SCSI 2 connector spec s 1 Amp maximum at 5096 energized SCSI 2 connector spec s Operating Temperature 20 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For PMC Module Boards Application To connect field I O signals to the PMC Module Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the PMC Module via a flat ribbon cable Model 5025 551 x Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to field I O pins 1 50 on the PMC module Each PMC module has its own unique pin assignments Refer to the PMC module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperatu
13. o za PIN 50 EE Ba E PLUG CONNECTOR Bg 1004 876 BB SHIELDED BH BACKSHELL BH 1004 877 BB BB PIN 1 BB PIN 26 Hoy ay RIBBON CABLE Z NBI PIN 2 CONNECTOR PIN 1 P2 1004 512 FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX MODEL 5028 187 SCSI 2 TO FLAT RIBBON CABLE SHIELDED 4501 758B Qquv9 ANINVZZAW VOECOWd SAIYAS FINGOW LAdLNO SOIWNV ALISN3Q HOIH LIg 94 02 1 2 34 56 78 9 10111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1 1234 5 6 7 8 9 10 111213 14 15 16 17 18 19 20 2122 2324 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TB1 MODEL 5025 552 TERMINATION PANEL SCHEMATIC i Gas 3 x 6 RAIL DIN MOUNTING SHOWN HERE TERMINATION jim DIN EN 50035 32mm of ACROMAG PART Ro NUMBER 4201 049 T RAIL DIN MOUNTING 3 032 nou SHOWN HERE 77 0 5 DIN EN 50022 35mm TB1 pn as ne pooppoppoooopopopoooppoooopmp LS BRBBBBDBBBBBBBDBDBBBDBDBDBDBDBDDBDBDD Se I Y g Zs SCREWDRIVER SLOT FOR ja 5 315 gt REMOVAL FROM T RAIL 135 0 TOP VIEW SIDE VIEW NOTES DIMENSIONS ARE IN
14. the 16 bit digital values that are to be output to the Digital to Analog Converter s DAC s The contents of the DAC registers are simultaneously transferred to their corresponding converter upon issue of a software or external trigger Table 3 2 lists each of the DAC Channel registers with their corresponding hex address in memory space Writing these registers is possible via 16 or 8 bit data transfers Software or hardware resets will clear the contents of the DAC Channel registers to 0 DAC MODES OF CONVERSION The PMC230A provides two methods of trigggering analog output updates The following sections describe the features of each and how to best use them Single Conversion from DAC Register Mode This mode of operation can be used on the PMC230A module It can be used to update from a single DAC channel to all DAC channels with a new analog output voltage With each conversion initiated by a software or external trigger the digital values in each of the DAC Channel registers are simultaneously moved to their corresponding converter for update of their analog output signal It is possible to keep a given channel s analog voltage unchanged by simply keeping the digital value in the channel s DAC register unchanged Only those channels with updated digital values in their corresponding DAC Channel registers will result in different analog output voltages Each of the DAC Channel register s digital values is moved to its correspond
15. the PCI bus to be free for other system operations while the data is moved to the read register A PCI bus write to the PMC module will result in 1 immmediately accepting the write data and normal cycle termination or 2 issue of a retry termination A retry termination will be issued if the previous write cycle has not completed on the PMC module It will typically take the PMC module 1000ns to write the data to the required internal register Thus if another write cycle is initiated on the PCI bus before the typical 1000ns has lapsed the write cycle will be terminated with a retry A programmable logic device provides the control signals required to operate the board It decodes the selected addresses and produces the chip selects control signals timing required by the DAC s and software registers It also controls the mode selection and triggering to start DAC conversions for the Transparent and Simultaneous Modes The Calibration PROM contains channel specific calibration coefficients to correct both offset and gain errors The coefficients must be used to trim the outputs to within their accuracy specification The PROM software registers and DAC s are all accessed through the PCI bus interface 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE The PMC230A is shipped pre calibrated by Acromag and may be returned at the discretion of the customer to measure the accuracy of the calibration at some defined period Recalibra
16. unipolar or bipolar output ranges J3 to J10 pins 3 and 4 control the selection of output voltage span The configuration of the jumpers for the different ranges is shown in Table 2 2 ON means that the pins are shorted together with a shorting clip OFF means that the clip has been removed The individual jumper locations are shown in Drawing 4501 863 BOARD CONFIGURATION The board may be configured differently depending on the application Jumper settings are discussed in the following sections The jumper locations are shown in Drawing 4501 863 Remove power from the board when configuring hardware jumpers installing PMC modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 859 and the following paragraphs for configuration and assembly instructions Table 2 2 Analog Output Range Selections Jumper Settings Desired Required J3to J10 J3to J10 ADC Output Output Pins 1 amp 2 Pins 3 amp 4 Range VDC Type Default Hardware Jumper Configuration The board is shipped from the factory configured as follows Each analog output range is configured for a bipolar output with a 20 volt span i e a DAC output range of 10 to 10 Volts The default programmable software control register bits at power up are described in section 3 The control registers must be programmed to the desired mode before starting DAC analog output conversions Analog Output Ranges and Correspondi
17. with outputs unloaded Follow the output connection recommendations of Chapter 2 to keep a non ideal grounds from degrading overall system accuracy The maximum uncalibrated error combining the linearity offset and gain errors is 0 461 DAC714P 25 C Linearity Error is 0 011 maximum i e 8 LSB Bipolar Offset Error is 0 2 FSR i e 20V SPAN max Gain Error is 0 25 maximum Settling 10uS to within 0 003 of FSR for a 20V step change load of in parallel with 500pF Conversion Rate per channel 150KHz Maximum 100KHz recommended for specified accuracy Maximum Throughput 8 X conversion rate PMC230A 8 X 150KHz 1 2MHz max 8 X 100KHz 0 8MHz max Output 120 nV VHz typical Output at Reset Bipolar Zero Volts Unipolar 5 Volts See Note 4 Board Warm up 10 minutes minimum Note Analog Output 4 The reset function resets the DAC analog output and the FPGA s internal DAC registers Therefore the DAC output will remain in their reset state after simultaneous DAC output updates until the DAC registers are overwritten with new data Output Impedence 0 10 Typical at 25 C Short Circuit Protection Indefinite at 25 C 13 SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE Ext
18. 4 ANALOG OUTPUT CONNECTIONS 17 4501 865 PMC230A BLOCK DIAGRAM 18 4501 758 CABLE SCSI 2 to Flat Ribbon Shielded 19 5028 187 dese Te ert Re ren 4501 464 TERMINATION PANEL 5025 552 20 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The PCI Mezzanine Card PMC Series PMC230A is a precision 16 bit high density single width PMC module with eight analog voltage output channels Each of the output channels on the PMC230A has a dedicated register from which digital values are read and simultaneously transferred to its corresponding Digital to Analog Converter DAC The PMC230A is available with eight cost effective 16 bit analog output channels The PMC230A is available in standard and extended temperaterue range cards as follows Analog Output Temperature Range Channels PMC230A 8 8 0 to 70 C PMC2304 E 18 40 to 85 C The PMC230A utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density
19. API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PMC boards 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product Inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection V CAUTION SENSITIVE ELECTRONIC DEVICES 00 NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should onl
20. Acromag NM Series PMC230A PCI Mezzanine Card 16 Bit High Density Analog Output Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 2000 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 890 B13C010 SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents Page 1 0 GENERAL KEY PMC230A PCI MEZZANINE CARD INTERFACE FEATUREG SIGNAL INTERFACE PMC MODULE ActiveX CONTROL SOFTWARE PMC MODULE VxWORKS SOFTWARE ui 2 0 PREPARATION FOR
21. C module s FPGA The control logic of the PMC230A is responsible for controlling the operation of a user specified mode of data conversions Once the PMC module has been configured the control logic performs the following e Controls serial transfer of data from the FPGA to the individual DAC registers based on the selected mode of operation e Provides external or internal trigger control e Controls read and write access to calibration memory DATA TRANSFER FROM FPGA To INDIVIDUAL DACs A 16 bit serial shift register is implemented in the PMC230A module s FPGA for each of the supported channels These serial shift registers are referred to as the individual DAC registers in the memory map To control transfer of digital data to the individual converters internal FPGA counters are used to synchronize the simultaneous transfer of serial shift register data to the corresponding converter The DACs can be updated with new digital values or left unchanged The DACs are updated by first writing the individual DAC registers resident in the FPGA Then upon issue of a trigger software or external the contents of the DAC registers are simultaneously transferred to the DACs EXTERNAL TRIGGER The external trigger connection is made via pin 49 of the P1 Field I O Connector For all modes of operation when external trigger input is enabled via bits 6 and 5 of the control register the falling edge of the external trigger will start the si
22. Convert On External Trigger Only PROGRAMMING Single Conversion From DAC Register Example USE OF CALIBRATION DATA Uncalibrated Performance Calibrated Performance Calibration Programming 4 0 THEORY OF FIELD ANALOG OUTPUTG PMC230A CONTROL LOGIC DATA TRANSFER FROM FPGA To INDIVIDUAL DACs EXTERNAL TRIGGER senes CALIBRATION MEMORY CONTROL LOGIC is PCI INTERFACE LOGIC sse PMC MODULE 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE MT PRELIMINARY SERVICE PROCEDURE 6 0 PHYSICAL ENVIRONMETAL 5 tte pde cR RP ANALOG OUTPUTS L EXTERNAL TRIGGER INPUT OUTPUT PCI LOCAL BUS APPENDIX CABLE SCSI 2 to Flat Ribbon Shielded MODEI 5028 187 ttn cedex TERMINATION PANEL MODEL 5025 552 DRAWINGS Page 4501 859 PMC MECHANICAL ASSEMBLY s 15 4501 863 PMC230A JUMPER LOCATION 16 4501 86
23. abling resistance should be considered Output common is electrically connected to the PMC module analog ground which connects to logic ground of the module at the DAC s As such the PMC230A is non isolated between the logic and field I O grounds Consequently the field I O connections are not isolated from the carrier CPU board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog outputs when a high level of accuracy resolution is needed Refer to Drawing 4501 864 for example output and grounding connections External Trigger Input Output The external trigger signal on pin 49 of the P1 connector can be programmed to accept a TTL compatible external trigger input signal or output hardware timer generated triggers to allow synchronization of multiple PMC230A modules As an input the external trigger must be a 5 Volt logic TTL compatible debounced signal referenced to analog common The trigger pulse must be low for a minimum of 125n seconds to guarantee acquisition It must not stay low for more than 6u seconds or additional unwanted conversions may be triggered The actual conversion is triggered within 6 25u seconds of the falling edge of the external trigger signal This type of conversion triggering can be used to synchronize generation of analog output signals to external events
24. available For optimum performance with the 16 bit PMC230A analog output module use of the shortest possible length of shielded cable is recommended Cables Model 5025 187 SCSI 2 to Flat Ribbon Cable Shielded A round 50 conductor shielded cable with a male SCSI 2 connector at one end and a flat female ribbon connector at the other end The cable is used for connecting the PMC230A module to Model 5025 552 termination panels Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to Acromag PMC230A via SCSI 2 to Flat Ribbon Cable Shielded Model 5028 187 IP MODULE DLL CONTROL SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 98 Me NT4 2000 XP 8 applications accessing Acromag PMC I O board products PCI I O Cards and CompactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builder amp and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers PMC MODULE VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of board VxWorks software This software Model PMCSW
25. available These ranges can be selected on a per channel basis e External Trigger Scan Mode All channels simultaneously implement a new conversion with each external trigger This mode allows synchronization of conversions with external events that are often asynchronous e External Trigger Output The external trigger is assigned to a field I O line The external trigger may be configured as an output signal to provide a means to synchronize other PMC230A devices to a master PMC230A module PC MEZZANINE CARD INTERFACE FEATURES e High density Single width PMC Target module e Field Connections All analog output and external power connections are made through a single 50 pin SCSI 2 front panel I O connector e 16 bit I O Control register writes DAC writes and calibration coefficient reads are performed through 16 bit data transfer cycles in the PCI memory space e Compatibility IEEE P1386 1 PMC module which complies to PCI Local Bus Specification Revision 2 2 Provides one multifunction interrupt 5V signaling compliant and 3 3V signaling tolerant SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This PMC Module will mate directly to any standard PMC carrier CPU board that supports one single width PMC mezzanine module Once connected the module is accessed via a 50 pin front panel connector The cables and termination panels described in the following paragraphs are also
26. cific information necessary to 10 0000 program and operate the PMC230A module 1 Not Used Reserved This Acromag PMC230A is a PCI Local Bus Specification 15 version 2 2 compliant PCI bus target only PMC module The carrier CPU connects a PCI host bus to the PMC module MEMORY MAP The PCI bus is defined to address three distinct address f i spaces I O memory and configuration space The PMC module This board is allocated a 4K byte block of memory that is can be accessed via the PCI bus memory space and addressable in the PCI bus memory space to control the configuration spaces only programming of analog outputs to the field As such three types SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE of information are stored in the memory space control status and data The memory space address map for the PMC230A is shown in Table 3 2 Note that the base address for the PMC230A in memory space must be added to the addresses shown to properly access the PMC230A registers Register accesses as 32 16 and 8 bit data in memory space are permitted All the registers of the PMC230A are accessed via data lines DO to D15 The most significant word of a 32 bit access is not used by the PMC230A A 32 bit read will return logic 0 for the most significant word Table 3 2 PMC230A Memory Map Hex MSB D15 D08 Base Adr Control Register Not Used Not Used Not Used Not Used Not Used Rd Calibra
27. configuration registers with the AD 30 AD 29 interrupt request line assigned to the PMC module AD 26 AD 24 Since this PMC module is relocatable and not fixed in 2 2 address space this module s device driver must use the mapping IDSEL 25 AD 23 6 e 1 wine SR CUPS ire a 27 2 information stored in the module s Configuration Space registers 25 E to determine where the module is mapped in memory space AD 16 C BE 2 Configuration Registers PCI RSVD TRDY The PCI specification requires software driven initialization STOP ias via the aan AS space Dos PERR 39 40 PMC module provides 256 bytes of con iguration registers or this SERR purpose The PMC230A contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility 1 AD 14 AD 13 The Configuration Registers are accessed via the AD 10 Configuration Address and Data Ports The most important AD 08 Configuration Registers are the Base Address Registers which AD 07 PCI RSVD must be read to determine the base address assigned to the PMC230A PCI RSVD PCI RSVD Table 3 1 Configuration Registers Dis D7 S O o 10 4 56 Vendor ID 16D5 1 Status Command Class Code 118000 Rev ID 00 Indicates that the signal is active low Cache BOLD ITALIC Signals are NOT USED by this PMC Model 32 bit Memory Base Address for PMC230A 4K Byte Block 3 0 PROGRAMMING INFORMATION Not Used Subsystem Vendor This Section provides the spe
28. d not be initiated unless the write busy status bit 1 is clear set low to 0 A software or hardware reset of the PMC module will also clear this bit to 0 Read accesses to Calibration Coefficient Status register require one wait state and are possible via 16 bit data transfers only A software or hardware reset will clear all bits to O Start Convert Register Write Only 21CH The Start Convert register is a write only register and is used to trigger conversions by setting data bit 0 to a logic The desired mode of conversion must first be configured by setting the Control register This register can be written with either a 16 bit or 8 bit data value Data bit O must be a logic one to initiate data conversions SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE When External Trigger Only mode is selected via bits 6 and 5 of the control register set to 01 the Software Start Convert bit is disabled from starting data conversions Start Convert Register Start Convert Not Used NtUed 07 06 o5 o4 o3 O2 Ot o0 The actual conversion will be initiated 6 625 seconds after setting the Start Convert Bit Thus in single conversion mode you cannot reload the DAC registers with new data until at least 6 625y seconds after a start convert DAC Channel Registers Write Only 220H to 23CH The DAC Channel registers are write only registers and are used to hold
29. ernal Trigger Input Output AS An Input Must be an active low 5 volt logic TTL compatible debounced signal referenced to digital common Conversions are triggered within 6 41 seconds of the falling edge Minimum pulse width 125n sec Maximum pulse width 6u seconds otherwise an additional trigger is produced As An Output Active low 5 volt logic TTL compatible output is generated The trigger pulse is low for 125n seconds typical A maximum of 4 loads are allowed PCI Local Bus Interface Conforms to PCI Local Bus Specification Revision 2 2 and PMC Specification P1386 1 Draft 2 4 See Note 6 Electrical Mechanical Interface Single Width PMC Module PCI Target 5 nene Implemented by Altera FPGA 4K Memory Space Required One Base Address Register PCI commands Supported Configuration Read Write Memory Read Write 32 16 and 8 bit data transfer types supported Signaling 5V Compliant 3 3V Tolerant PCI bus Write Cycle Time 150 nS Typical measured from falling edge of FRAME to the falling edge of TRDY PCI bus Read Cycle Time 150 nS Typical Notes PCI Local Bus Interface 5 Although the typical read or write PCI bus cycle time is only 150 nS the actual read or write implemented on the PMC Module will be typically 1000 nS Thus the PMC Module wi
30. g MIL HDBK 217F Notice 2 8 Single Ended PMC230A 8 Bipolar 5 to 5 Volts Bipolar 10 to 10 Volts Unipolar 0 to 10 Volts 1 The actual outputs may fall short of the range endpoints due to hardware offset and gain errors The software calibration corrects for these across the output range but cannot extend the output beyond that achievable with the hardware Output Current to 5mA Maximum this corresponds to a minimum load resistance of 2KQ with a 10V output DAC Data Format Positive true binary two s complement BTC input codes DAC Programming Simultaneous Input registers of multiple DAC s are directly loaded with new data before simultaneously updating DAC outputs Resolution 16 bits Monotonicity 14 bits PMC230A 13 bits PMC230AE Linearity Error 4 LSB Maximum 25 C Differential Linearity Error 4 LSB Maximum 25 C Maximum Overall Calibrated Error 25 C Max Linearity Max Offset Max Gain Error LSB Error LSB Error LSB Max Total Error LSB 6 0 0091 Notes Calibrated Error 2 Offset and gain calibration coefficients stored in the coefficient memory must be used to perform software calibration in order to achieve the specified accuracy Specified accuracy does not include quantization error and are
31. gister will provide the addressed byte of the calibration coefficient on data bits 15 to 8 of the Calibration Coefficient Status register Although the read request via the Calibration Coefficient Access register is accomplished in less then 800n seconds typically the calibration coefficient will not be available in the Calibration Coefficient Status register for approximately 2 5m seconds Bit 0 of the Calibration Coefficient Status register is the read complete status bit This bit will be set high to indicate that the requested calibration coefficient is available on data bits 15 to 8 of this status register This bit is cleared upon initiation of a new read access of the coefficient memory or upon issue of a software or hardware reset Writes to calibration coefficient memory require a special enable code Writes to coefficient memory are normally only performed at the factory The module should be returned to Acromag if recalibration is needed A write operation to the calibration coefficient memory initiated via the Calibration Coefficient Access register will take approximately 5m seconds Bit 1 of the Calibration Coefficient Status register serves as a write operation busy status indicator Bit 1 will be set high upon initiation of a write operation and bit 1 will remain high until the requested write operation has completed New read or write accesses to the coefficient memory via the Calibration Coefficient Access register shoul
32. in Signal Name Pin The PCI card s configuration registers are initialized by system software at power up to configure the card The PMC230A module is a Plug and Play PCI card As a Plug and AD 02 AD 01 6 Play card the board s base address and system interrupt request AD 00 line are not selected via jumpers but are assigned by system REQ64 software upon power up via the configuration registers A PCI Indicates that the signal is active low bus configuration access is used to access a PCI card s BOLD ITALIC Signals are NOT USED by this PMC Model configuration registers Table 2 5 PMC Connector Pin Assignments for J2 32 bit PCI Configuration Address Space PCI When the computer is first powered up the computer s Signal Name Pin SignalName Pin system configuration software scans the PCI bus to determine what PCI devices are present The software also determines the configuration requirements of the PCI card PCI RSVD 87 3 F The system software accesses the configuration registers to etermine how many blocks of memory space the PMC module PCI RSVD PCI RSVD requires It then programs the PMC module s configuration BUSMODE2 registers with the unique memory address range assigned RST BUSMODE3 BUSMODE4 The configuration registers are also used to indicate that the m PMC module requires an interrupt request line The system PCI RSVD sae software then programs the
33. in Table 3 3 This register can be read or written with either 8 bit or 16 bit data transfers A power up or system reset sets all control register bits to O Table 3 3 Control Register 3 NotUsed 0 4 External Trigger Control 00 External Trigger Input External and Software triggers are all enabled 01 External Trigger Input External triggers are only enabled Software triggers are disabled 10 External Trigger Output Software triggers are output on the External trigger pin of the field I O connector It is possible to synchronize the conversion of multiple PMC230A modules A single master PMC230A must be selected to output the external trigger signal bit 6 and 5 set to 10 while all other modules are selected to input the external trigger signal bit 6 and 5 set to 01 The external trigger signals pin 49 of the field I O connector of all modules to be synchronized must be wired together DAC Conversion Mode 000 Disabled 001 Single Conversion from DAC registers 010 Not Defined 011 Not Defined 100 Not Defined 101 Not Defined 110 111 Not Defined All modes require either the software start convert or an external trigger to initiate DAC conversions 11to 14 Not Used Perform Software Reset when Set Notes Table 3 3 1 All bits labeled Not Used will return the last value written on a read access 2 Bits 11 to 15 will return random values when read Calibrati
34. ing converter for simultaneous conversion upon issue of a software or external trigger Convert On External Trigger Only When bit 6 and 5 of the control register are set to digital code 01 each conversion is initiated by an external trigger only logic low pulse input to the EXT TRIGGER signal of the P1 connector Conversions are performed for each channel simultaneously with each external trigger pulse The interval between conversions is controlled by the period between external triggers The interval timer has no functionality in this mode of operation The external trigger signal is configured as an input for this mode of operation External Trigger Only mode of operation can be used to synchronize multiple PMC230A modules to a single module running in a continuous cycle mode The external trigger of the PMC230A master must be programmed as an output The external trigger signal of that PMC230A must then be connected to the external trigger signal of all other PMC230A modules programmed for external trigger input that are to be synchronized These other PMC230A modules must be programmed for External Trigger Input only mode Data conversion can then be started by writing high to the Start Convert bit of the master PMC230A configured for continuous cycle mode PROGRAMMING CONSIDERATIONS FOR GENERATION OF ANALOG OUTPUTS The PMC230A provides different methods of analog output generation to give the user maximum flexibilit
35. ll issue a RETRY when a new read or write cycle is implemented before the PMC module s 1000 nS read or write has completed When the PMC Module issues a RETRY this frees the PCI bus while the previous read or write operation is completed 6 Due to the unique modular nature of the PMC230A assembly it is impossible to comply with the solder side component height per the PMC Mechanical Standand Refer to Mechanical Assembly Drawing 4501 859 for details You must determine whether there will be adequate clearance for your application APPENDIX CABLE MODEL 5028 187 SCSI 2 to Flat Ribbon Shielded Type Round shielded cable 50 wires SCSI 2 male connector at one end and a flat female ribbon connector at the other end The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 552 termination panel to the PMC230A Module Length Standard lenght is 2 meters 6 56 feet Consult factory for other lenghts It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil braided shield inside a PVC jacket Connectors One End SCSI 2 50 pin male connector with backshell and spring latch hardware Other End IDC 50 pin female connector with strain relief Keying The SCSI 2 connector
36. multaneous conversion of all channels For External Trigger Only mode bits 6 and 5 set to 01 each falling edge of the external trigger causes a conversion at the DAC Once the external trigger signal has been driven low it should remain low for a minimum of 125n seconds and a maximum of seconds or additional unwanted conversions may be triggered CALIBRATION MEMORY CONTROL LOGIC The FPGAs of the PMC230A modules contain control logic that implements read and write access to calibration memory The calibration memory EEPROM contains offset and gain coefficients for each of the ranges and channels Calibration of the individual DACs is implemented via software to avoid the mechanical drawbacks of hardware potentiometers PCI INTERFACE LOGIC The PCI bus interface logic is imbedded within an FPGA This logic includes support for PCI commands including configuration read write and memory read write In addition the PCI target interface performs parity error detection uses a single 4K base address register and implements target abort retry and disconnect J1 and J2 connectors also provide 12V and 5V to power the module SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE A PCI bus read of the PMC module will initially terminate with aretry While the read data is moved to the read register typically 1000ns continued retries will result in retry terminations The retry termination allows
37. ng Digital Codes The PMC230A is designed to accept positive true binary two s complement BTC input codes which are compatible with bipolar analog output operation Table 2 1 indicates the relationship between the data format and the ideal analog output voltage for each of the analog output ranges Selection of an analog output range is implemented via the jumper settings given in Table 2 2 Table 2 1 Full Scale Ranges and Ideal Analog Output Digital Output Code Output Range 10 0toi0V 5 mE 305uV 153uV 153uV DESCRIPTION ANALOG OUTPUT LSB Least Significant Bit Weight Minus One LSB Volts Volts Volts One LSB Below FFFFy 305uV 4 999847 153uV Midscale Volts The board is shipped with the default jumper setting for the 10 volt DAC output range Software Configuration Software configurable control registers are provided for control of external trigger mode and conversion mode selection No hardware jumpers are required for control of these functions These control registers must also be configured as desired before starting DAC analog output conversions Refer to section 3 for programming details CONNECTORS Front Panel Field I O Connector P1 The front panel connector P1 provides the field I O interface connections P1 is a SCSI 2 50 pin female connector AMP 787082 5 or equivalent employing latch blocks and 30 micron gold the mating area per MIL G 45204 Type 11 Grade C Connects to
38. nnector Error checking should be performed on the calculated count values to insure that calculated values below 0 or above 65535 decimal are restricted to those end points Note that the software calibration cannot generate outputs near the endpoints of the range which are clipped off due to hardware limitations i e the DAC 4 0 THEORY OF OPERATION This section contains information regarding the hardware of the PMC230A A description of the basic functionality of the circuitry used on the board is also provided Refer to the Block Diagram shown in Drawing 4501 865 as you review this material FIELD ANALOG OUTPUTS The field I O interface to the PMC230A is provided through the front panel connector P1 refer to Table 2 3 Field I O signals are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring ground loops may cause operation errors and with extreme abuse possible circuit damage Refer to Drawing 4501 864 for example wiring and grounding connections Jumpers on the board control the range selection for the DACs 5 to 5 10 to 10 and 0 to 10 Volts as detailed in 11 chapter 2 Jumper selection should be made prior to powering the unit Channels may use different ranges PMC230A CONTROL LOGIC All logic to control data conversions is imbedded in the PM
39. nt byte of the gain coefficient To initiate a read of channel 0 s least significant byte of the gain coefficient the Calibration Coefficient Access register must be written with data value 8300H at Base Address 214H When bit 0 of the Calibration Coefficient Status register is set to logic high then the data on bits 15 to 8 of this register contains the least significant byte of the gain coefficient 4 Calculate the Ideal Count required to provide an uncorrected output of the desired value 2 5 Volts by using equation 1 Ideal Count 65 536x 2 5 20 8 192 0 5 Calculate the Corrected Count required to provide an accurate output of the desired value 2 5 Volts by using equation 2 Assume the offset and gain coefficients are 43 and 185 respectively Corrected Count 8 192 0x 1 185 4x65 536 43 4 8 196 9687 This value is rounded to 8 197 and is equivalent to DFFB hex as a 2 s complement value 6 Execute Write of DFFB hex to the DAC Channel 0 Register at Base Address 220H 7 Execute Write 0001H to the Start Convert Bit at Base Address 21CH This starts the simultaneous transfer of the digital data in each DAC Channel register to its corresponding converter for analog conversions This will drive channel 0 s analog output to 2 5 volts 8 OPTIONAL Observe or monitor that the specific DAC channel 0 reflects the results of the digital data converted to an analog output voltage at the field co
40. nt byte of the offset coefficient the Calibration Coefficient Access register must be written with data value 8000H at Base Address 214H The offset coefficient can be read by polling the Calibration Coefficient Status register When bit 0 of the Calibration Coefficient Status register is set to logic high then the data on bits 15 to 8 contain the most significant byte of the offset coefficient To initiate a read of channel 0 s least significant byte of the offset coefficient the Calibration Coefficient Access register must be written with data value 8100H at Base Address 214H When bit 0 of the Calibration Coefficient Status register is set to logic high then the data on bits 15 to 8 of this register contains the least significant byte of the offset coefficient 3 Read the calibration memory to retrieve channel 0 s unique 16 bit gain coefficient To obtain the 16 bit gain coefficient two read accesses of the coefficient memory are required To initiate a read of channel 0 s most significant byte of the gain coefficient the Calibration Coefficient Access register must be written with data value 8200H at Base Address 214H The gain coefficient can be read by polling the Calibration Coefficient Status register When bit 0 of the SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE Calibration Coefficient Status register is set to logic high then the data on bits 15 to 8 contains the most significa
41. on Coefficient Access Register Write 215H This register configures access to the calibration coefficient memory Calibration data is provided so that software can adjust and improve the accuracy of the analog output voltage over the uncalibrated state Each channel s unique offset and gain SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE calibration coefficients are stored in this memory These coefficients can be retrieved using this register The Calibration Coefficient Access Register is a write only register and is used to configure and initiate a read cycle to the calibration coefficient memory Setting bit 15 of this register high to a 1 initiates a read cycle The address of the calibration coefficient to be read must be specified on bits 14 to 8 of Calibration Coefficient Access register The address location of each of the gain and offset coefficients is given in table 3 4 Most Significant Byte of Calibration Coefficient Access Reg Read or o a Calibration Coefficient Address 14 13 12 11 10 9 8 Write Write accesses to the Calibration Coefficient Access register require one wait state and are possible via 16 bit data transfers only A software or hardware reset has no affect on this register The address location of each of the gain and offset coefficients is given in table 3 4 The address corresponding to each of the offset and gain coefficients for each of the channels
42. ons into debugged software calibration code Uncalibrated Performance The uncalibrated performance is affected by two primary error sources These are the channel s offset and gain errors The use of channel specific calibration coefficients to accurately adjust offset and gain is important because the worst case uncalibrated error can be significant although the typical uncalibrated errors observed may be much less See the SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE specification chapter for details regarding maximum uncalibrated error Calibrated Performance Accurate calibration of the PMC230A can be accomplished through software control by using calibration coefficients to adjust the analog output voltage Unique calibration coefficients are stored in memory as 1 4 LSB s for each specific channel Once retrieved the channel s unique offset and gain coefficients can be used to correct the data value sent to the DAC channel to accurately generate the desired output voltage See the specification chapter for details regarding maximum calibrated error Data is corrected using a couple of formulas Equation 1 expresses the ideal relationship between the value Ideal count written to the 16 bit DAC to achieve a specified voltage within the selected output range Equation 1 Count Span Desired Voltage Ideal Count Ideal Volt Span where Count Span 65 536 a 16 bit converte
43. r has 2 possible levels Ideal Volt Span 20 Volts for the bipolar 10 to 10 Volt range 10 Volts for the bipolar 5 or unipolar 0 to 10 volt ranges Using equation 1 one can determine the ideal count for any desired voltage within the range For example if it is desired to output a voltage of 5 Volts for the bipolar 10 volt range the Ideal Count of 16 384 results If this value is used to program the DAC output the output value will approach 5 Volts to within the uncalibrated error This will be acceptable for some applications For applications needing better accuracy the software calibration coefficients should be used to correct the Ideal_Count into the Corrected_Count required to accurately produce the output voltage This is illustrated in the next equation Equation 2 Corrected_ Count Ideal_ Count 1 Gain_ Correction Offset_ Correction Ideal Zero Count where Gain Correction Stored Gain Error 4 65 536 Offset Correction Stored Offset Error 4 Ideal Zero Count 0 for bipolar 5 and 10 volt ranges 32 768 for unipolar 0 to 10 volt range Ideal Count is determined from equation 1 given above Stored Gain Error and Stored Offset Error are written at the factory and are obtained from memory on the PMC230A on a per channel basis The Stored Gain Error and Stored Offset Error are stored in memory as two s complement numbers Refer to the Calibration Coefficient Access Register section
44. re 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packaged 14 GL CMC BEZEL IN FRONT PANEL PMC MODULE P1 CON IN FRONT PANEL 0 138 5 500mm SEE NOTE 1 ECTOR NR EM A XL COMPONENT SIDE OF PMC MODULE _ COMPONENT SIDE OF PMC CARRIER CPU ASSEMBLY PROCEDURE BOARD 1 INSERT PMC MODULE P1 CONNECTOR SIDE INTO THE CMC BEZEL IN THE FRONT PANEL OF THE PMC CARRIER CPU BOARD THEN ALIGN THE CONNECTORS ON THE ITEM A 9 595 15 110mm SEE NOTES 2 AND 3 PMC MODULE AND PMC CARRIER CPU BOARD ONCE ALIGNED THEN PUSH TOGETHER STACKING HEIGHT BETWEEN PMC MODULE AND PMC CARRIER CPU BOARD IS 0 394 10 000mm 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF PMC CARRIER CPU BOARD AND INTO PMC MODULE AS SHOWN 4 PLACES THEN TIGHTEN SCREWS NOTE zu 1 U 4 a HIS PMC MODULE EXCEEDS THIS BY 0 055 1 400mm 4 DISTANCE TO INTERBOARD SEPARATION PLANE IS 0 045 1 143mm THE DESIRED SPACING IS 0 100 2 540mm FOR VME AND CompactPCI HE USEABLE SPACE ON THE SOLDER SIDE OF THE PMC MODULE IS 0 075 1 900mm PER MC MECHANICAL STANDARD P1386 1 THIS PMC MODULE EXCEEDS THIS BY 0 063 1 600mm THE TOTAL HEIGHT OFF THE PMC CARRIER CPU BOARD IS 0 532 15 500mm PER MECHANICAL STANDARD P1386 1 THIS PMC MODULE EXCEEDS THIS BY 0 063 1 600mm HE MAXIMUM COMPONENT HEIGHT FOR VME AND
45. tion if required can be performed by the customer if the proper equipment is available to them and is otherwise offered through the Service Department at Acromag for a fee Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed ina burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag 6 0 SPECIFICATIONS PHYSICAL Physical Configuration
46. tion Wr Coefficient Address Calibration Coefficient Read Data Not Used Bits15 to Bit 01 DAC Channel 0 DAC Channel 1 DAC Channel 2 DAC Channel 3 DAC Channel 4 DAC Channel 5 DAC Channel 6 DAC Channel 7 Not Used Not Used Reserved Not Used Calibration Coefficient Write Data Wr Rd Busy Comp Start Convert Bit 0 NOT USED Notes Table 3 2 1 The PMC will respond to addresses that are Not Used This byte is reserved for use at the factory to enable writing of the calibration coefficients 3 All writes are 8 clock cycles except when a previous write is in progress In this case the write cycle will disconnect with retry 4 All initial reads will disconnect without data and a retry will be issued This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Control Register Read Write Base 200H This read write register is used to control the external trigger select one of the digital to analog conversion modes and issue a software reset The function of each of the control register bits are described
47. unity EMI Surge Immunity ESD Protection Electric Fast Transient Immunity EFT Radiated Emissions 5 95 Non Condensing 55 C to 105 C Logic and field commons have a direct electrical connection Designed to comply with IEC1000 4 3 Level 3 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with error less than 0 25 of FSR Error is less than 0 25 of FSR under the influence of EMI from switching solenoids commutator motors and drill motors Not required for signal I O per European Norm EN50082 1 Complies with IEC 1000 2 Level 1 2KV direct contact discharge at input output terminals and European Standard EN50082 1 Complies with IEC1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Meets or exceeds European Norm EN50081 1 for class A equipment Warning This is aclass A product In a domestic environment this product may cause radio interference in which the user may be required to take adequate measures Reliability Prediction Mean Time Between Failure ANALOG OUTPUTS Output Channels Field Access Voltage Non isolated Output Signal Type Output Ranges Jumper selected Note Analog Outputs MTBF TBD hours not available at time of printing 25 C Usin
48. y be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier CPU board plus the installed PMC modules within the voltage tolerances specified SERIES PMC230A PCI MEZZANINE CARD 16 BIT HIGH DENSITY ANALOG OUTPUT MODULE Notes Table2 1 IMPORTANT Adequate air circulation must be provided to 1 power up or software reset the bipolar ranges will output 0 volts while the unipolar range will output 5 volts prevent a temperature rise above the maximum operating temperature The dense packing of the PMC modules to the carrier CPU board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering Analog Output Range Hardware Jumper Configuration The output range of the DACs are individually programmed via hardware jumpers J3 to J10 Jumpers J3 to J10 are used to control channels 0 to 7 respectively The jumpers control the output voltage span and the selection of unipolar or bipolar output ranges J3 to J10 pins 1 and 2 control the selection of
49. y for each application Examples are presented in the following sections to illustrate programming the different modes of operation Single Conversion from DAC Register Example 1 Execute Write of 0100H to Control Register at Base Address 200H a External Software and Hardware timer genterated triggers are all enabled b Single Conversion from DAC registers is enabled 2 Execute Write of 7FFFH to each DAC Channel Register starting at Base Address 220H This will drive each analog output to plus full scale minus one least significant bit 3 Execute Write 0001H to the Start Convert Bit at Base Address 21CH This starts the simultaneous transfer of the digital data in each DAC Channel register to its corresponding converter for analog conversion USE OF CALIBRATION DATA Calibration data is provided in the form of calibration coefficients so the user can adjust and improve the accuracy of the analog output voltage over the uncalibrated state Each channel s unique offset and gain calibration coefficients are stored in memory The use of software calibration allows the elimination of hardware calibration potentiometers traditionally used in producing precision analog outputs Software calibration uses some fairly complex equations Acromag recommends purchase of our ActiveX or VxWorks software to make communication with the board and calibration easy It relieves you from having to turn the equations of the following secti
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