PSoC® 4: PSoC 4100 Family Datasheet Programmable
Contents
1. Document Number 001 87220 Rev A Acronym Description Acronym Description ETM embedded trace macrocell abus analog local bus FIR finite impulse response see also IIR ADC analog to digital converter FPB flash patch and breakpoint AG analog global FS full speed AHB AMBA advanced microcontroller bus archi tecture high performance bus an ARM data GPIO general purpose input output applies to a PSoC transfer bus pin ALU arithmetic logic unit HVI high voltage interrupt see also LVI LVD AMUXBUS analog multiplexer bus IC integrated circuit API application programming interface IDAC current DAC see also DAC VDAC APSR application program status register IDE integrated development environment 2 A PEE ARM advanced RISC machine a CPU architecture I C or Circuit a communications rotoco ATM automatic thump mode IIR infinite impulse response see also FIR BW bandwidth ILO internal low speed oscillator see also IMO CAN Controller Area Network a communications IMO internal main oscillator see also ILO protocol CMRR common mode rejection ratio INL integral nonlinearity see also DNL CPU central processing unit input output see also GPIO DIO SIO USBIO CRC cyclic redundancy check an error checking IPOR initial pow2. Document Number 001 87220 Rev A Page 27 of 35 ER PSoC 4 PSoC 4100 Family CYPRESS Datasheet Part Numbering Conventions PSoC 4 devices follow the part numbering convention described in the following table All fields are single character alphanumeric 0 1 2 9 AB Z unless stated otherwise The part numbers are of the form CY8C4ABCDEF XYZ where the fields are defined as follows Example 4 XYZ Cypress Prefix __ 4 PSoC4 Architecture 1 4100Family Family within Architecture 2 24 MHz Speed Grade 5 32KB Flash Capacity AX TQFP Package Code 1 Industrial Temperature Rang Attributes Set The Field Values are listed in the following table Field Description Values Meaning CY8C Prefix 4 Architecture 4 PSoC 4 A Family within architecture 1 4100 Family 2 4200 Family B CPU Speed 2 24 MHz 4 48 MHz C Flash Capacity 4 16 KB 5 32 KB DE Package Code AX TQFP LQ QFN PV SSOP F Temperature Range Industrial XYZ Attributes Code 000 999 Code of feature set in specific family Document Number 001 87220 Rev A Page 28 of 35 ER PSoC 4 PSoC 4100 Family CYPRESS Datasheet Packaging Table 45 Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature 40 25 00 85 Ty Operating junction temperature 40
3. 2 Input common mode voltage in ultra low 0 Vppp V Guaranteed by power mode 1 15 characterization SID88 CMRR Common mode rejection ratio 50 E E dB Vppp 2 2 7 Guaranteed by characterization SID88A CMRR Common mode rejection ratio 42 dB Vppp lt 2 7 Guaranteed by characterization SID89 lomp4 Block current normal mode 280 Guaranteed by characterization SID248 lomp2 Block current low power mode 50 pA Guaranteed characterization SID259 Block current ultra low power mode 6 by characterization SID90 ZcMP DC input impedance of comparator 35 MO Guaranteed by characterization Table 10 Comparator AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID91 TRESP1 Response time normal mode 38 ns 150 mV overdrive SID258 2 Response time low power mode 70 ns 50 mV overdrive SID92 TRESP3 Response time ultra low power mode 2 3 Hs 200 mV overdrive Document Number 001 87220 Rev A Page 18 of 35 CYPRESS PERFORM Temperature Sensor PSoC 4 PSoC 4100 Family Datasheet Table 11 Temperature Sensor Specifications Spec ID Parameter Description Min T
4. GPIO Table 4 GPIO DC Specifications uf Details Spec ID Parameter Description Min Typ Max Units Conditions SID57 Input voltage high threshold 0 7 x V CMOS Input VDDD SID58 ViL Input voltage low threshold 0 3 x V CMOS Input 510241 LVTTL input Vppp lt 2 7 V 0 7x V VDDD SID242 LVTTL input Vppp lt 2 7 V 0 3 x V SID243 viu LVTTL input Vppp 2 2 7 V 2 0 V SID244 Vu LVTTL input Vppp 2 2 7 V 0 8 V SID59 Vou Output voltage high level Vppp V lon 4 mA at 0 6 3 V Vppp SID60 Vou Output voltage high level Vppp V 1 mA at 0 5 1 8 V Vppp SID61 VoL Output voltage low level 0 6 V loy 4 mA at 1 8 V Vppp SID62 VoL Output voltage low level 0 6 V loj 8 mAat3 V SID62A VoL Output voltage low level 0 4 V 3 mAat3 V 51063 RPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID64 RPULLDOWN Pull down resistor 3 5 5 6 8 5 kQ SID65 lu Input leakage current absolute value 2 nA 25 C 3 0 V SID65A liL Input leakage current absolute value 4 nA for CTBM pins SID66 Cin Input capacitance 7 pF SID67 VuvsTTL Input hysteresis LVTTL 25 40 mV Vppp 2 2 7 V Guaranteed by characterization SID68 VuvscMos Input hysteresis CMOS 0 05 x mV Guaranteed by Vppp characterization SID69 IDIODE Current through protection diode to 100 Guaranteed by Vpp Vss characterization SID69A GPIO Maximum Total Sou
5. Open drain with strong pull up Strong pull up with strong pull down Weak pull up with weak pull down m Input threshold select CMOS or LVTTL m Individual control of input and output buffer enabling disabling in addition to the drive strength modes m Hold mode for latching previous state used for retaining I O state in Deep Sleep mode and Hibernate modes m Selectable slew rates for dV dt related noise control to improve EMI Page 6 of 35 SESJ CYPRESS PERFORM The pins are organized in logical entities called ports which are 8 bit in width During power on and reset the blocks are forced to the disable state so as not to crowbar any inputs and or cause excess turn on current A multiplexing network known as a high speed matrix is used to multiplex between various signals that may connect to an I O pin Pin locations for fixed function peripherals are also fixed to reduce internal multi plexing complexity Data output and pin state registers store respectively the values to be driven on the pins and the states of the pins themselves Every I O pin can generate an interrupt if so enabled and each I O port has an interrupt request IRQ and interrupt service routine ISR vector associated with it 5 for PSoC 4100 since it has 4 5 ports Special Function Peripherals LCD Segment Drive The PSoC 4100 has an LCD controller which can drive up to four commons and up to 32 segments
6. VDD 2 Data and Status Flags External Reference and Bypass optional Reference Selection VDDD VREF Inputs from other Ports Two Opamps CTBm Block The PSoC 4100 has two opamps with Comparator modes which allow most common analog functions to be performed on chip eliminating external components PGAs Voltage Buffers Filters Trans Impedance Amplifiers and other functions can be realized with external passives saving power cost and space The on chip opamps are designed with enough bandwidth to drive the Sample and Hold circuit of the ADC without requiring external buffering Document Number 001 87220 Rev A Temperature Sensor The PSoC 4100 has one on chip temperature sensor This consists of a diode which is biased by a current source that can be disabled to save power The temperature sensor is connected to the ADC which digitizes the reading and produces a temper ature value using Cypress supplied software that includes calibration and linearization Page 5 of 35 PERFORM Low power Comparators The PSoC 4100 has a pair of low power comparators which can also operate in the Deep Sleep and Hibernate modes This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low power modes The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode
7. 100 TJA Package 28 pin SSOP 66 58 C Watt TJA Package 40 QFN 15 34 C Watt TJA Package 44 TQFP 57 16 C Watt Package 28 pin SSOP 26 28 C Watt Tuc Package 40 pin QFN 2 50 C Watt Package 44 pin TQFP 17 47 C Watt Table 46 Solder Reflow Peak Temperature Package Maximum Time at Peak Temperature 28 pin SSOP 260 30 seconds 40 pin QFN 260 C 30 seconds 44 pin TQFP 260 30 seconds Table 47 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 Package MSL 28 pin SSOP MSL 3 40 pin QFN MSL 3 44 pin TQFP MSL 3 Document Number 001 87220 Rev A Page 29 of 35 ON 114 DIA PIN 1 ID PSoC 4 PSoC 4100 Family Datasheet DIMENSIONS IN MILLIMETERS MIN 235 MIN zd 0 65 BSC i GAUGE PLANE MAX 2 00 165 0 25 MAX 185 lC 8 QI 010 5 00 0 05 5 60 021 _ 028 125 REF dad i 038 51 85079 E Figure 10 40 pin QFN Package Outline TOP VIEW SIDE VIEW BOTTOM VIEW 6 00 0 10 PIN 1 ID 40 31 Ale 31 9 0 00 UU 40 30 oD xX X CX XX XX C LO C 0 50 IN aks PIN 1 DOT o D 8 D p g p 8 p cj 02517803 D C
8. 100kHz power high 15 nV rtHz SID297 Cload Stable up to maximum load Perfor 125 pF mance specs at 50 pF Document Number 001 87220 Rev A Page 17 of 35 a x PSoC 4 PSoC 4100 Family 2 CYPRESS Datasheet PERFORM Table 8 Opamp Specifications Guaranteed by Characterization continued Details Spec ID Parameter Description Min Typ Max Units Conditions SID298 Slew rate Cload 50 pF Power High gt 6 2 7 V SID299 T op wake From disable to enable no external RC 300 usec dominating Comp_mode Comparator mode 50 mV drive Trise Tfall approx SID300 TpPp4 Response time power high 150 nsec SID301 Tpp2 Response time power medium 400 nsec SID302 Tpp3 Response time power low 2000 nsec SID303 Vhyst op Hysteresis 10 mV Comparator Table 9 Comparator DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID85 VoFFSET2 Input offset voltage trimmed 4 mV SID86 Vuyst Hysteresis when enabled 10 35 mV Guaranteed by characterization SID87 1 Input common mode voltage in normal 0 Vppp 0 1 V Modes 1 and 2 mode Guaranteed by characterization SID247 Vicm2 Input common mode voltage in low 0 ES Vppp V Guaranteed by power mode characterization SID247A
9. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used both IDACs are available in that case or if CapSense is used without water tolerance one IDAC is available Page 7 of 35 Pinouts lt lt CYPRESS PERFORM PSoC 4 PSoC 4100 Family Datasheet The following is the pin list for the PSoC 4100 Port 2 comprises of the high speed Analog inputs for the SAR Mux P1 7 is the optional external input and bypass for the SAR reference Ports 3 and 4 contain the Digital Communication channels All pins support CSD Capsense and Analog Mux Bus connections Document Number 001 87220 Rev A Pins 44 TQFP 40 QFN 28 SSOP Alternate Functions for Pins as T T Pin Description Name Type Pin Name Pin Name Pin Analog Alt 1 AIt 2 Alt 3 VSSD Power 1 VSS DN Digital Ground P2 0 GPIO 2 P2 0 1 P2 0 sarmux 0 Port 2 Pin 0 Icd csd sarmux P2 1 GPIO 3 P2 1 2 P2 1 sarmux 1 Port 2 Pin 1 Icd csd sarmux P2 2 GPIO 4 P2 2 3 P2 2 5 P2 2 sarmux 2 Port 2 Pin 2 Icd
10. interface supports all programming and debug features of the device Complete debug on chip functionality enables full device debugging in the final system using the standard production device It does not require special interfaces debugging pods simulators or emulators Only the standard programming connections are required to fully support debug The PSoC Creator Integrated Development Environment IDE provides fully integrated programming and debug support for PSoC 4100 devices The SWD interface is fully compatible with industry standard third party tools With the ability to disable debug features with very robust flash protection and by allowing customer proprietary functionality to be implemented in on chip programmable blocks the PSoC 4100 family provides a level of Document Number 001 87220 Rev A Read Accelerator System Interconnect Single Layer AHB Peripheral Interconne PSoC 4 PSoC 4100 Family Datasheet ROM 4 kB SRAM Up to 4 kB SRAM Controller ROM Controller ct MMIO 4x TCPWM Capsense 2x SCB I2C SPI UART 2x LP Comparator Port Interface amp Digital System Interconnect 051 peed Matrix 36x GPIOs security not possible with multi chip application solutions or with microcontrollers The debug circuits are enabled by default and can only be disabled in firmware If not enabled the only way to re enable them is to eras
11. that is aggregate sampling bandwidth is equal to 806 Ksps whether it is for a single channel or distributed over several channels The sequencer switching is effected through a state machine or through firmware driven switching A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements To accommodate signals with varying source impedance and frequency it is possible to have different sample times programmable for each channel Also signal range specification through a pair of range registers low and high range values is implemented with a corresponding out of range interrupt if the digitized value exceeds the programmed range this allows fast detection of out of range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out of range values in software The SAR is able to digitize the output of the on board temper ature sensor for calibration and other temperature dependent functions The SAR is not available in Deep Sleep and Hibernate modes as it requires a high speed clock up to 18 MHz The SAR operating range is 1 71 to 5 5 V Figure 2 SAR ADC System Diagram AHB System Bus and Programmable Logic Interconnect SAR Sequencer Sequencing and Control gt 5 2 HS gt la 15 1 0 n
12. 10 kHz SINAD SID111 A INL Integral non linearity 1 7 2 LSB Vpp 1 71 to 5 5 806 Ksps Vref 1 to 5 5 SID111A INL Integral non linearity 1 5 17 LSB 1 71 to 3 6 806 Ksps Vref 1 71 to Vppp SID111B INL Integral non linearity 1 5 1 7 LSB 1 71 to 5 5 500 Ksps Vref 1 to 5 5 Document Number 001 87220 Rev A Page 19 of 35 Table 13 SAR ADC AC Specifications Guaranteed by Characterization continued PSoC 4 PSoC 4100 Family Datasheet Spec ID Parameter Description Min Typ Max Units Details Conditions SID112 A DNL Differential non linearity 1 m 2 2 LSB Vppp 1 71 to 5 5 806 Ksps Vref 1 to 5 5 10112 DNL Differential non linearity 1 2 LSB 1 71 to 3 6 806 Ksps Vref 1 71 to 5101128 DNL Differential non linearity 1 2 2 LSB 1 71 to 5 5 500 Ksps Vref 1 to 5 5 SID113 A THD Total harmonic distortion 65 dB Fiy 10 kHz CSD Table 14 CSD Block Specification Details Spec ID Parameter Description Min Typ Max Units Conditions CSD Specification SID308 VCSD Voltage range of operation 1 71 5 5 V SID309 IDAC1 DNL for 8 bit resolution 1 1 LSB SID310 IDAC1 INL for 8 bit resolution 3 3 LSB SID311 IDAC2 DNL for 7 bit resolution 1 1 LSB SID312 IDAC2 INL for 7 bit resolu
13. 16 P3 6 tcpwm3 p O Scb1 spi ssel 3 Port Pin 6 gpio csd pwm scb1 P3 7 GPIO 18 P3 7 17 P3 7 tcpwm3_n 0 Port 3 Pin 7 gpio Icd csd pwm VDDD Power 19 VDD Digital Supply 1 8 5 5 V D P4 0 GPIO 20 4 0 18 P4 0 15 P4 0 scbO uart rx scbO 12 scl ScbO spi 4 Pin 0 gpio Icd csd P4 1 GPIO 21 P4 1 19 P4 1 16 P4 1 ScbO uart scbO i2c ScbO spi miso Port 4 Pin 1 gpio Icd csd P4 2 GPIO 22 P4 2 20 P4 2 17 P4 2 csd_c_mo ScbO spi clk Port 4 Pin 2 gpio Icd d csd P4 3 GPIO 23 P4 3 21 18 P4 3 c sh ScbO spi ssel 0 Port 4 Pin 3 gpio tank csd P0 0 GPIO 24 0 22 19 0 1 inp ScbO spi ssel 1 Port 0 Pin 0 gpio csd scb0 comp GPIO 25 1 23 20 1 inn ScbO spi ssel 2 0 Pin 1 gpio csd scb0 comp 2 GPIO 26 0 2 24 2 21 P02 comp2 inp ScbO spi ssel 3 Port 0 Pin 2 gpio Icd csd scb0 comp PO 3 GPIO 27 P0 3 25 P0 3 22 P0 3 comp2 inn Port 0 Pin 3 gpio Icd csd comp P0 4 GPIO 28 26 P0 4 Scb1 uart rx scb1 i2c scl 1 scb1 spi mosi 1 Port 0 Pin 4 gpio Icd 1 csd scb1 5 GPIO 29 27 5 Scb1 uart gt scb1
14. Hibernate where the system wake up circuit is activated by a comparator switch event Fixed Function Digital Timer Counter PWM Block The Timer Counter PWM block consists of four 16 bit counters with user programmable period length There is a Capture register to record the count value at the time of an event which may be an I O event a period register which is used to either stop or auto reload the counter when its count is equal to the period register and compare registers to generate compare value signals which are used as PWM duty cycle outputs The block also provides true and complementary outputs with programmable offset between them to allow use as deadband programmable complementary PWM outputs It also has a Kill input to force outputs to a predetermined state for example this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention Serial Communication Blocks SCB The PSoC 4100 has two SCBs which can each implement an UART or SPI interface Mode The hardware 122 block implements a full multi master and slave interface it is capable of multimaster arbitration This block is capable of operating at speeds of up to 1 Mbps Fast Mode Plus and has flexible buffering options to reduce interrupt overhead and latency for the CPU It also supports 212 that creates a mailbox address range in the
15. Hs by characterization SWD Interface Table 37 SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID213 F SWDCLK1 3 3 V lt Vpp lt 5 5 V 14 MHz SWDCLK lt 1 3 CPU clock frequency SID214 F SWDCLK2 1 71 V lt 3 3 V 7 MHz SWDCLK lt 1 3 CPU clock frequency SID215 T SWDI SETUP T 1 f SWDCLK 0 25 T ns Guaranteed by characterization SID216 T SWDI HOLD 1 f SWDCLK 0 25 T 5 Guaranteed by characterization SID217 T SWDO VALID T 1 SWDCLK 0 5 T ns Guaranteed by characterization 510217 SWDO HOLD T 1 f SWDCLK 1 ns Guaranteed by characterization Document Number 001 87220 Rev A Page 25 of 35 lt lt F CYPRESS PERFORM Internal Main Oscillator Table 38 IMO DC Specifications Guaranteed by Design PSoC 4 PSoC 4100 Family Datasheet Spec ID Parameter Description Min Typ Max Units Details Conditions SID219 limo2 IMO operating current at 24 MHz 325 SID220 limo3 IMO operating current at 12 MHz 225 10221 IMO operating current at 6 MHz 180 SID222 limos IMO operating current at 3 MHz 150 Table 39 AC Specifications Spec ID Parameter Description Min Typ Max Units
16. P KK di 5 d 10 21 21 A gt Cho hoaonanananl 11 20 0 05 20 ar 4 60 0 10 1 HATCH AREA IS SOLDERABLE 2 REFERENCE JEDEC MO 248 3 PACKAGE WEIGHT 68 2 mg 4 ALL DIMENSIONS ARE IN MILLIMETERS Document Number 001 87220 Rev A 001 80659 Page 30 of 35 SEATING PLANE CYPRESS PERFORM Figure 11 44 pin TQFP Package Outline 12 00 0 25 SQ 10 0040 10 SQ 44 34 33 En LII oy En 2 1 Hn 23 HEBBHHEEEERB 12 22 121 1 60 MAX 2 Z sE Yr41005 0 20 re SEE DETAIL Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family STAND OFF 0 05 MIN 0 15 MAX 1 STD REF 5 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS l Datasheet 51 85064 E Page 31 of 35 ER PSoC 4 PSoC 4100 Family 7 CYPRESS Datasheet Acronyms Table 48 Acronyms Used in this Document continued Table 48 Acronyms Used in this Document
17. SIDA IGPIO_ABS Maximum current per GPIO 25 25 mA Absolute max SID5 IGPIO injection GPIO injection current Max for Vip gt 0 5 0 5 mA Absolute max and Min for lt Vss current injected per pin BID44 ESD HBM Electrostatic discharge human body 2200 V model BID45 ESD CDM Electrostatic discharge charged device 500 V model BID46 LU Pin current for Latch up 200 200 Device Level Specifications All specifications are valid for 40 lt TA x 85 and TJ x 100 C except where noted Specifications are valid for 1 71 V to 5 5 V except where noted Table 2 DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID53 Power supply input voltage 1 8 5 5 V With regulator enabled SID255 Power supply input voltage unregulated 1 71 1 8 1 89 V Internally unreg ulated supply SID54 Vccp Output voltage for core logic 1 8 V SID55 External regulator voltage bypass 1 1 3 1 6 UF X5R ceramic or better SID56 CExc Power supply decoupling capacitor 1 UF X5R ceramic or better Active Mode 1 71 to 5 5 V Typical values measured at Vpp 3 3 V SID9 Ipps Execute from Flash CPU at 6 MHz 2 8 mA SID10 Ippe Execute from Flash CPU at 6 MHz 2 2 mA 25 SID12 Execute from Flash CPU at 12 MHz 4
18. and programmable peripherals Industry Standard Tool Compatibility m After schematic entry development can be done with ARM based industry standard development tools San Jose CA 95134 1709 408 943 2600 Revised June 20 2013 LE PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM Contents Block Diagram niai rrr eniin tnn 3 Device Level 13 Functional Definition eere 4 Analog Peripherals 17 CPU and Memory 4 Digital Peripherals eene 21 System ResOUrces riirii 4 pies Ic E 24 Analog BIoCKS iecit en tent tette 5 System ReSOUICOS pea Pa tue 24 Fixed Function 2 6 Ordering Information eere 27 GPIO 6 Part Numbering Conventions 28 Special Function 7 Packaging Esaias 8 Acronyms luv m 11 Document Conventions 34 Unregulated External 11 Units of Measure Regulated
19. by the power system The PSoC 4100 provides Sleep Deep Sleep Hibernate and Stop low power modes Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family Datasheet Clock System The PSoC 4100 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching In addition the clock System ensures that no metastable conditions occur The clock system for the PSoC 4100 consists of the IMO and the ILO internal oscillators and provision for an external clock Figure 1 PSoC 4100 MCU Clocking Architecture IMO HFCLK EXTCLK ILO I gt trek HFCLK Prescaler SYSCLK UDB 7 Dividers UBEn Analog Divider H SAR clock Peripheral H PERXYZ The HFCLK signal can be divided down see PSoC 4100 MCU Clocking Architecture to generate synchronous clocks for the analog and digital peripherals There are a total of 12 clock dividers for the PSoC 4100 each with 16 bit divide capability The analog clock leads the digital clocks to allow analog events to occur before digital clock related noise is generated The 16 bit capability allows a lot of flexibility in generating fine grained frequency values and is fully supported in PSoC Creator IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 41
20. high 10 10276 lout medium 10 10277 louT MAX LO Power low 5 lout 1 71 V 500 mV from SID278 loUT MAX HI Power high 4 mA SID279 lour Max Power medium 4 SID280 loUT MAX LO Power low 2 mA SID281 Charge pump Vppa gt 2 7 V 0 05 VDDA 0 2 V SID282 VcM Charge pump on Vppa gt 2 7 V 0 05 VDDA 0 2 V Vout VppA gt 2 7 V 10283 4 Power high 10 mA 0 5 VDDA 0 5 V 510284 2 Power high 1 mA 0 2 VDDA 0 2 V SID285 Vour 3 Power medium 1 mA 0 2 VDDA 0 2 V 10286 4 Power low 0 1 0 2 VDDA 0 2 V SID288 Vos TR Offset voltage trimmed 1 0 5 1 mV High mode SID288A Vos Offset voltage trimmed 1 mV Medium mode SID288B Vos Offset voltage trimmed 2 mV Low mode SID290 Vos DR TR Offset voltage drift trimmed 10 23 10 uV C High mode SID290A Vos DR TR Offset voltage drift trimmed 10 Medium mode 5102908 Vos Offset voltage drift trimmed E 10 Low mode SID291 CMRR DC 70 80 dB VDDD 3 6V SID292 PSRR At 1 kHz 100 mV ripple 70 85 dB VDDD 3 6 V Noise 510293 VN Input referred 1 Hz 1GHz power 94 uVrms high SID294 VN2 Input referred 1 KHz power high 72 nV rtHz SID295 Input referred 10kHz power lt high 28 nV rtHz SID296 Input referred
21. i2c 1 scb1 spi miso 1 0 Pin 5 gpio Icd csd scb1 P0 6 GPIO 30 6 28 P0 6 23 6 ext clk Scb1 spi clk 1 Port 0 Pin 6 gpio Icd csd scb1 ext clk 0 7 31 7 29 0 7 24 wakeup Scb1 spi ssel O 1 Port 0 Pin 7 gpio Icd csd scb1 wakeup Page 8 of 35 PSoC 4 PSoC 4100 Family Datasheet Pins 44 TQFP 40 QFN 28 SSOP Alternate Functions for Pins J 522 Pin Description Name Type Pin Name Pin Name Pin Analog Alt 1 AIt 2 Alt 3 XRES XRES 32 XRES 30 XRES 25 XRES Chip reset active low VCCD Power 33 VCC 31 26 Regulated supply D connect to 1 cap or 1 8V VDDD Power 34 VDD 32 VDDD 27 VDD Digital Supply 1 8 5 5 V D VDDA Power 35 VDD 33 VDDA 27 VDD Analog Supply 1 8 5 5 A V equal to VDDD VSSA Power 36 VSSA 34 VSSA 28 D VSS Analog Ground N P1 0 GPIO 37 P1 0 35 P1 0 1 1 0 ctb oa0 inp tepwm2 p 1 Port 1 Pin 0 gpio Icd csd ctb pwm P1 1 GPIO 38 P1 1 36 P1 1 2 P1 1 ctb oa0 in tepwm2 n 1 Port 1 Pin 1 gpio Icd m csd ctb pwm P1 2 GPIO 39 P1 2 37 P12 3 P1 2 ctb oa0 out tcpwm3_p 1 Port 1 Pin 2 gpio Icd csd ctb pwm P1 3 GPIO 40 1 3 38 P1 3 ctb oa1 out tcpwm3 n 1 Po
22. is 1 71 to 5 5 V with all functions and circuits operating over that range The PSoC 4100 family allows two distinct modes of power supply operation Unregulated External Supply and Regulated External Supply modes Unregulated External Supply In this mode the PSoC 4100 is powered by an External Power Supply that can be anywhere in the range of 1 8 to 5 5 V This range is also designed for battery powered operation for instance the chip can be powered from a battery system that starts at 3 5 V and works down to 1 8 V In this mode the internal regulator of the PSoC 4100 supplies the internal logic and the VCCD output of the PSoC 4100 must be bypassed to ground via an external Capacitor in the range of 1 to 1 6 uF X5R ceramic or better VDDA and VDDD must be shorted together the grounds VSSA and VSS must also be shorted together Bypass capacitors must be used from VDDD to ground typical practice for systems in this frequency range is to use a capacitor in the 1 uF range in parallel with a smaller capacitor 0 1 uF for example Note that these are simply rules of thumb and that for critical applications the PCB layout lead inductance and the Bypass capacitor parasitic should be simulated to design and obtain optimal bypassing An example of a bypass scheme for the 44 TQFP package follows Figure 6 44 TQFP Package Example VSS lt 7 0 1uF C4 93444
23. memory of the PSoC 4100 and effectively reduces 12 commu nication to reading from and writing to an array in memory In addition the block supports an 8 deep FIFO for receive and transmit which by increasing the time given for the CPU to read data greatly reduces the need for clock stretching caused by the CPU not having read data on time The FIFO mode is available in all channels and is very useful in the absence of DMA The peripheral is compatible with the Standard mode Fast mode and Fast mode Plus devices as defined in the NXP I C bus specification and user manual UM10204 The bus I O is implemented with GPIO in open drain modes The PSoC 4100 is not completely compliant with the 2 spec in the following respects m GPIO cells are not overvoltage tolerant and therefore cannot be hot swapped or powered up independently of the rest of the 2 system Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family Datasheet m Fast mode Plus has an lo specification of 20 mA at a Vo of 0 4 V The GPIO cells can sink a maximum of 8 mA lo with a maximum of 0 6 V m Fast mode and Fast mode Plus specify minimum Fall times which are not met with the GPIO cell Slow strong mode can help meet this spec depending on the Bus Load When the SCB is Master it interposes an IDLE state between NACK and Repeated Start the 2 spec defines Bus free as following a Stop condition so other Active Mas
24. volt Document Number 001 87220 Rev A Page 34 of 35 PSoC 4 PSoC 4100 Family ES CYPRESS Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Automotive cypress com go automotive psoc cypress com solutions Clocks amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Developer Community Lighting amp Power Control cypress com go powerpsoc Community Forums Blogs Video Training cypress com go plc Technical Support Memory cypress com go memory PSoC cypress com go psoc cypress com go support Touch Sensing cypress com go touch USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2013 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agr
25. with respect 0 ns to capturing edge at Slave Table 30 Fixed SPI Slave mode AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units SID170 MOSI valid before Sclock capturing edge 40 ns SID171 Tpso MISO valid after Sclock driving edge 42 3 ns FCPU SID171A Tpso ext MISO valid after Sclock driving edge in Ext 48 ns Clock mode SID172 Tuso Previous MISO data hold time 0 ns SID172A TssELsCK SSEL Valid to first SCK Valid edge 100 ns Document Number 001 87220 Rev A Page 23 of 35 Memory CYPRESS PERFORM Table 31 Flash DC Specifications PSoC 4 PSoC 4100 Family Datasheet Spec ID Parameter Description Min Typ Max Units Details Conditions SID173 Erase and program voltage 1 71 5 5 V Table 32 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID174 Trowwrite Row block write time erase and 20 ms Row block 128 bytes program SID175 Row erase time 13 ms SID176 TROWPROCRAN Row program time after erase 7 ms SID178 TBULKERASEHI Bulk erase time 32 KB 35 ms SID180 TpEvPRoc Total device program time 7 seconds Guaranteed by charac t
26. 00 It is trimmed during testing to achieve the specified accuracy Trim values are stored in nonvolatile latches NVL Additional trim settings from flash can be used to compensate for changes The IMO default frequency is 24 MHz and it can be adjusted between 3 to 24 MHz in steps of 1 MHz IMO Tolerance with Cypress provided calibration settings is 2 ILO Clock Source The ILO is a very low power oscillator which is primarily used to generate clocks for peripheral operation in Deep Sleep mode ILO driven counters can be calibrated to the IMO to improve accuracy Cypress provides a software component which does the calibration Page 4 of 35 Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs The watchdog reset is recorded in the Reset Cause register Reset The PSoC 4100 can be reset from a variety of sources including a software reset Reset events are asynchronous and guarantee reversion to a known state The reset cause is recorded ina register which is sticky through reset and allows software to determine the cause of the Reset An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power on or reconfiguration Voltage Reference The PSoC 4100 reference system generates all internally required refe
27. 2 51013 Execute from Flash CPU at 12 MHz 3 7 mA 25 51016 Ipp44 Execute from Flash CPU at 24 MHz 6 7 mA 25 51017 15512 Execute from Flash CPU at 24 MHz 7 2 mA Sleep Mode Vppp 3 6 to 5 5 V Regulator on 6 MHz SID25 15520 2 wakeup WDT and comparators on 1200 25 Note 1 Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability When used below Absolute Maximum conditions but above normal operating conditions the device may not operate to specification Document Number 001 87220 Rev A Page 13 of 35 ER PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM Table 2 DC Specifications continued Details Spec ID Parameter Description Min Typ Max Units Conditions Deep Sleep Mode Vppp 1 8 to 3 6 V Regulator on SID31 Ipp26 2 wakeup and WDT on 13 25 3 6 SID32 Ipp27 2 wakeup and WDT on 50 185 Deep Sleep Mode Vppp 3 6 to 5 5 V SID34 Ipp2o 2 wakeup and WDT on 15 25 5 5 Deep Sleep Mode Vppp 1 71 to 1 89 V Regulator bypassed SID37 Ipp32 2 wakeup and WDT on 1 7 25 SID38 15533 2 wakeup and WDT on 440 85 H
28. 35 ER PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM Voltage Monitors Table 35 Voltage Monitors DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID195 Vivid LVI A D SEL 3 0 0000b 1 71 1 75 1 79 V SID196 LVI A D SEL 3 0 00016 1 76 1 80 1 85 V SID197 LVI A D SEL 3 0 0010b 1 85 1 90 1 95 V SID198 LVI A D SEL 3 0 00116 1 95 2 00 2 05 V SID199 Vivis LVI A D SEL 3 0 0100b 2 05 2 10 2 15 V SID200 LVI A D SEL 3 0 0101b 2 15 2 20 2 26 V SID201 LVI A D SEL 3 0 01106 2 24 2 30 2 36 V SID202 Vivis LVI A D SEL 3 0 0111b 2 34 2 40 2 46 V SID203 LVI A D SEL 3 0 10006 2 44 2 50 2 56 V SID204 LVI A D SEL 3 0 10016 2 54 2 60 2 67 V SID205 LVI A D SEL 3 0 10106 2 63 2 70 2 77 V SID206 2 LVI A D SEL 3 0 1011b 2 73 2 80 2 87 V SID207 LVI A D SEL 3 0 11006 2 83 2 90 2 97 V SID208 LVI A D SEL 3 0 11016 2 93 3 00 3 08 V SID209 Viyi45 LVI A D SEL 3 0 1110b 3 12 3 20 3 28 V SID210 LVI_A D_SEL 3 0 11116 4 39 4 50 4 61 V SID211 LVI IDD Block current 100 HA Guaranteed by characterization Table 36 Voltage Monitors AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID212 TMONTRIP Voltage monitor trip time 1
29. 43 1uFC 1 C2 01 uF 566 rr 57 Lr E LL 5 1 GPIO P2 2 57 VSS 2 5 84 GPIO P2 6 GPIO PO 3 94 GPIO PO 2 84 GPIO PO 1 44 GPIO PO 0 GPIO PA 3 GPIO P2 7 11 VSS GPIO GPIO GPIO GPIO GPIO Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family Datasheet Power Supply Bypass Capacitors VDDD VSS 0 1 ceramic at each pin C2 plus bulk capacitor 1 to 10 C1 VDDA VSSA 0 1 ceramic at pin C4 Additional 1 uF to 10 bulk capacitor VCCD VSS 1 uF ceramic capacitor at the VCCD pin C5 VREF VSSA The internal bandgap may be bypassed optional with 1 uF to 10 uF capacitor Figure 7 40 pin QFN Example C1 C2 0 1 uF VSSV7 0 1 uF C4 1uF VSSNZ VSS 7 C5 GPIO Pato XRES GPIO 21 poer 296 GPIO Po 7 GPIO 213 GPIO P214 GPIO 215 P2 6 GPIO P217 4 3 lt p GPIO VSS Figure 8 28 SSOP Example GPIO P1 7 GPIO P2 2 GPIO P2 3 24 GPIO PO 7 6 2 GPIO PO 3 GPIO Po 2 GPIO PO 1 GPIO PO 0 GPIO P4 3 GPIO P4 2 GPIO PA 1 GPIO P3 3 GPIO P
30. 5 V operation m 20 nA Stop Mode with GPIO pin wakeup m Hibernate and Deep Sleep modes allow wakeup time versus power trade offs Capacitive Sensing m Cypress Capacitive Sigma Delta CSD provides best in class SNR 55 1 and water tolerance m Cypress supplied software component makes capacitive sensing design easy m Automatic hardware tuning SmartSense Segment LCD Drive m LCD drive supported on all pins common or segment m Operates in Deep Sleep mode with 4 bits per pin memory Cypress Semiconductor Corporation Document Number 001 87220 Rev A 198 Champion Court Serial Communication m Two independent run time reconfigurable Serial Communi cation Blocks SCBs with re configurable I2C or functionality Timing and Pulse Width Modulation m Four 16 bit Timer Counter Pulse Width Modulator TCPWM blocks m Center aligned Edge and Pseudo random modes m Comparator based triggering of Kill signals for motor drive and other high reliability digital logic applications Up to 36 Programmable GPIO m 44 pin TQFP 40 pin QFN and 28 pin SSOP packages m Any GPIO Pin can be Capsense LCD Analog or Digital m Drive modes strengths and slew rates are programmable PSoC Creator Design Environment m integrated Development Environment provides schematic design entry and build with analog and digital automatic routing m Applications Programming Interface API Component for all fixed function
31. A 0 Regulated External Supply In this mode the PSoC 4100 is powered by an external power supply that must be within the range of 1 71 to 1 89 V 1 8 5 note that this range needs to include power supply ripple too In this mode VCCD VDDA and VDDD pins are all shorted together and bypassed The internal regulator is disabled in firmware Page 11 of 35 SESJ CYPRESS PERFORM Development Support The PSoC 4100 family has a rich set of documentation devel opment tools and online resources to assist you during your development process Visit www cypress com go psoc4 to find out more Documentation A suite of documentation supports the PSoC 4100 family to ensure that you can find answers to your questions quickly This section contains a list of some of the key documents Software User Guide A step by step guide for using PSoC Creator The software user guide shows you how the PSoC Creator build process works in detail how to use source control with PSoC Creator and much more Component Datasheets The flexibility of PSoC allows the creation of new peripherals components long after the device has gone into production Component data sheets provide all of the information needed to select and use a particular component including a functional description API documentation example code and AC DC specifications Application Notes PSoC application notes discuss a particular application of PSoC in dept
32. D Parameter Description Min Typ Max Units Details Conditions SID137 Block current consumption at 3 MHz 19 16 bit PWM SID138 IPwM2 Block current consumption at 12 MHz 66 16 bit PWM Table 20 PWM AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID140 TPWMFREQ Operating frequency 24 MHz SID141 TPWMPWINT Pulse width internal 42 5 Document Number 001 87220 Rev Page 21 of 35 lt lt CYPRESS PERFORM PSoC 4 PSoC 4100 Family Datasheet Table 20 PWM AC Specifications Guaranteed by Characterization continued Spec ID Parameter Description Min Typ Max Units Details Conditions SID142 TPWMEXT Pulse width external 42 5 510143 TPWMKILLINT Kill pulse width internal 42 ns SID144 TPWMKILLEXT _ Kill pulse width external 42 5 510145 TPWMEINT Enable pulse width internal 42 ns SID146 TPWMENEXT Enable pulse width external 42 ns SID147 TPwMRESwiNT Reset pulse width internal 42 ns SID148 Tpwmreswext Reset pulse width external 42 5 Table 21 Fixed DC Specifications Guaranteed by Charac
33. Details Conditions SID223 FIMOTOL1 Frequency variation from 3 to 2 With API called 24 MHz calibration SID226 TsTARTIMO IMO startup time 12 5 510227 TJITRMSIMO4 RMS Jitter at 3 MHz 156 ps SID228 TJITRMSIMO2 RMS Jitter at 24 MHz 145 ps Internal Low Speed Oscillator Table 40 ILO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID231 operating current at 32 kHz 0 3 1 05 Guaranteed by Characterization SID233 lit OLEAK ILO leakage current E 2 15 nA Guaranteed by Design Table 41 ILO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID234 TsTARTILO1 ILO startup time 2 ms Guaranteed by charac terization SID236 TiLoDUTY ILO duty cycle 40 50 60 Guaranteed by charac terization SID237 FiLoTRIMA 32 kHz trimmed frequency 15 32 50 kHz 60 with trim Table 42 External Clock Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID305 ExtClkFreq External Clock input Frequency 0 24 MHz by characterization SID306 ExtClkDuty Duty cycle Measured at 2 45 55 Guaranteed by characterization Table 43 Block Specs Spec ID Parameter Description Min Typ Max Units Details Conditions SID257 Tws24 Number of wait states at 24 MHz 0 CPU execution from Flash Guaranteed by characterization SID260 VREFSAR Trimmed internal reference to 1 1 Percen
34. External Supply 11 Sales Solutions and Legal Information 35 Development Support eene 12 Worldwide Sales and Design 35 Docuteritatlon 12 PROGUCUS Em 35 19 fm 12 PSoCO Solutions 2 icto ctor 35 5 12 Cypress Developer 35 Electrical Specifications esses 13 Technical SUPPOFt 0 0 35 Absolute Maximum 5 13 Document Number 001 87220 Rev A Page 2 of 35 gt CYPRESS PERFORM Block Diagram PSoC 4100 FLASH Up to 32 kB FAST MUL NVIC IRQMX System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches Peripherals Clock Clock Control Programmable Analog SAR ADC 12 bit IMO Reset Control XRES Test DFT Logic DFT Analog 1055 GPIO 5x ports Power Modes Active Sleep Deep Sleep Hibernate PSoC 4100 devices include extensive support for programming testing debugging and tracing both hardware and firmware The ARM Serial Wire Debug SWD
35. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages The two methods used are referred to as digital corre lation and PWM Digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family Datasheet the RMS signal zero This method is good for STN displays but may result in reduced contrast with TN cheaper displays PWM pertains to driving the panel with PWM signals to effec tively use the capacitance of the panel to provide the integration of the modulated pulse width to generate the desired LCD voltage This method results in higher power consumption but can result in better results when driving TN displays LCD operation is supported during Deep Sleep refreshing a small display buffer 4 bits 1 32 bit register per port CapSense CapSense is supported on all pins in the PSoC 4100 through a CapSense Sigma Delta CSD block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch CapSense function can thus be provided on any pin or group of pins in a system under software control A component is provided for the CapSense block to make it easy for the user Shield voltage can be driven on another Mux Bus to provide water tolerance capability
36. MFREQ Operating frequency 24 MHz SID119 TCAPWINT Capture pulse width internal 42 5 510120 TCAPWEXT Capture pulse width external 42 ns SID121 TTIMRES Timer resolution 21 5 510122 TTENWIDINT Enable pulse width internal 42 ns SID123 TTENWIDEXT Enable pulse width external 42 5 510124 Trimreswint _ Reset pulse width internal 42 ns SID125 TTIMRESEXT Reset pulse width external 42 ns Counter Table 17 Counter DC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID126 1 Block current consumption at 3 MHz 19 16 bit Counter SID127 IcrR2 Block current consumption at 12 MHz ES 66 pA 16 bit Counter Table 18 Counter AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID129 Operating frequency 24 MHz SID130 Capture pulse width internal 42 ns SID131 TerRPwExr pulse width external 42 ns SID132 TcTRES Counter Resolution 21 ns SID133 pulse width internal 42 ns SID134 TeENwipExr Enable pulse width external 42 ns SID135 Reset pulse width internal 42 ns SID136 TerRRESWExT Reset pulse width external 42 ns Pulse Width Modulation PWM Table 19 PWM DC Specifications Guaranteed by Characterization Spec I
37. O GPO P2 6 275 GPIO PO 3 ER 26 GPIO PO 2 88 10 25 GPIO PO 1 P3 0 11 24e GPIO PO 0 Seteeres GPIO P4 3 TONO Ro orn FFF 260600007 GPIO P2 0 PI ropan rea pats PS GPIO Po 6 GPIO P2 5 GPIO GPIO P2 6 Top View GPIO Es GPIO 1 P3 0 GPIO GPIO 4 3 1 2 3 4 5 6 7 0 1 2 GPIO vss GPIO P1 1 VDDD GPIO P1 2 VCCD GPIO P1 7 XRES GPIO P2 2 GPIO 7 GPIO P2 3 SSOP GPIO Po 6 GPIO P2 4 Top View GPIO 3 GPIO P2 5 GPIO 2 GPIO P2 6 GPIO Po 1 GPIO P2 7 0 GPIO P3 0 GPIO P4 3 GPIO P3 1 GPIO PA 2 GPIO P3 2 GPIO P4 1 GPIO P3 3 GPIO 4 0 Datasheet Page 10 of 35 EP CYPRESS PERFORM Power The following power system diagram shows the minimum set of power supply pins as implemented for the PSoC 4100 The system has one regulator in Active mode for the digital circuitry There is no analog regulator the analog circuits run directly from the VppA input There are separate regulators for the Deep Sleep and Hibernate lowered power supply and retention modes There is a separate low noise regulator for the bandgap The supply voltage range
38. PSoC 4 PSoC 4100 Family Datasheet Programmable System on Chip PSoC PERFORM General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of mixed signal programmable embedded system controllers with an ARM Cortex MO CPU It combines programmable and re configurable analog and digital blocks with flexible automatic routing The PSoC 4100 product family based on this platform is a combination of a microcontroller with digital program mable logic high performance analog to digital conversion opamps with Comparator mode and standard communication and timing peripherals The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs The programmable analog and digital sub systems allow flexibility and in field tuning of the design Features 32 bit MCU Sub system m 24 MHz ARM Cortex MO CPU with single cycle multiply m Up to 32 kB of flash with Read Accelerator m Up to 4 kB of SRAM Programmable Analog m Two opamps with reconfigurable high drive external and high bandwidth internal drive and Comparator modes and ADC input buffering capability m 12 bit 806 Ksps SAR ADC with differential and single ended modes and Channel Sequencer with signal averaging m Two current DACs IDACs for general purpose or capacitive sensing applications on any pin m Two low power comparators that operate in Deep Sleep Low Power 1 71 to 5
39. computing RMS root mean square RTC real time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC CT switched capacitor continuous time SCL 2 serial clock SDA serial data S H sample and hold SINAD signal to noise and distortion ratio SIO special input output GPIO with advanced features See GPIO SOC start of conversion SOF start of frame SPI Serial Peripheral Interface a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug a test protocol Page 33 of 35 PSoC 4 PSoC 4100 Family CYPRESS Datasheet Document Conventions Units of Measure Table 49 Units of Measure Symbol Unit of Measure degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kilo ohm Ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MO mega ohm Msps megasamples per second uH microhenry Hs microsecond uV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Q ohm pF picofarad ppm parts per million ps picosecond S second sps samples per second sqrtHz square root of hertz V
40. cronyms Used in this Document continued PSoC 4 PSoC 4100 Family Datasheet Table 48 Acronyms Used in this Document continued Document Number 001 87220 Rev A Acronym Description Acronym Description PC program counter SWV single wire viewer PCB printed circuit board TD transaction descriptor see also DMA PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor transistor logic PLA programmable logic array TX transmit PLD programmable logic device see also PAL UART Universal Asynchronous Transmitter Receiver a PLL phase locked loop communications protocol PMDD package material declaration data sheet UDE universal digital block POR power on reset USB Universal Serial Bus PRES precise power on reset USBIO 4 PSoC pins used to connect to ep sequence VDAC voltage DAC see also DAC IDAC PS port read data register WDT watchdog timer PSoC Programmable System on Ghip WOL write once latch see also NVL PSRR power supply rejection ratio WRES watchdog timer reset PAM pulsewidth modulator XRES external reset I O pin RAM random access memory XTAL crystal RISC reduced instruction set
41. csd sarmux P2 3 GPIO 5 P2 3 4 P2 3 6 P2 3 sarmux 3 2 3 csd sarmux P2 4 GPIO 6 2 4 5 2 4 P2 4 sarmux 4 tcpwmO p 1 Port 2 Pin 4 gpio Icd csd sarmux pwm P2 5 GPIO 7 2 5 6 2 5 8 P2 5 sarmux 5 tcpwmO n 1 Port 2 Pin 5 gpio Icd csd sarmux pwm P2 6 GPIO 8 2 6 7 2 6 9 P2 6 sarmux 6 tcpwm1 p 1 Port 2 Pin 6 gpio Icd csd sarmux pwm P2 7 GPIO 9 P2 7 8 P2 7 10 P2 7 sarmux 7 tcpwm1_nf 1 Port 2 Pin 7 gpio Icd csd sarmux pwm 10 D VSS 9 0 VSS Package pin to lead N N frame paddle downbond P3 0 GPIO 11 P3 0 10 P3 0 11 P3 0 tcpwmO p 0 scb1 uart rx scb1 i2c scl 0 scb1 spi mosi 0 Port 3 Pin 0 gpio Icd 0 csd pwm scb1 P3 1 GPIO 12 P3 1 11 P3 1 12 P3 1 tcpwm0_n 0 scb1 uart tx O scb1 i2c sda 0 scb1 spi miso 0 Port 3 Pin 1 gpio Icd csd pwm scb1 P3 2 GPIO 13 2 12 P3 2 13 P32 tcpwm1 p O swd io Scb1 spi clk O Port Pin 2 gpio Icd csd pwm scb1 swd P3 3 GPIO 14 P3 3 13 P3 3 14 P3 3 tcpwm1 n O Scb1 spi ssel O 0 Port 3 Pin 3 gpio Icd csd pwm scb1 swd P3 4 GPIO 15 P3 4 14 P3 4 tcpwm2 p O Scb1 spi ssel 1 Pin 4 gpio csd pwm scb1 P3 5 GPIO 16 5 15 P3 5 tcpwm2 n O Scb1 spi ssel 2 Port Pin 5 gpio csd pwm scb1 P3 6 GPIO 17 P3 6
42. e the entire device clear flash protection and reprogram the device with new firmware that enables debugging Additionally all device interfaces can be permanently disabled device security for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences Because all programming debug and test inter faces are disabled when maximum device security is enabled PSoC 4100 with device security enabled may not be returned for failure analysis This is a trade off the PSoC 4100 allows the customer to make Page 3 of 35 SESJ CYPRESS PERFORM Functional Definition CPU and Memory Subsystem CPU The Cortex MO CPU in the PSoC 4100 is part of the 32 bit MCU subsystem which is optimized for low power operation with extensive clock gating It mostly uses 16 bit instructions and executes a subset of the Thumb 2 instruction set This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex M3 and M4 thus enabling upward compatibility The Cypress implementation includes a hardware multiplier that provides a 32 bit result in one cycle It includes a nested vectored interrupt controller NVIC block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller WIC which can wake the processor up from Deep Sleep mode allowing power to be switched o
43. eement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves
44. er on reset protocol IPSR interrupt program status register DAC digital to analog converter see also IDAC VDAC IRQ interrupt request DFB digital filter block ITM instrumentation trace macrocell DIO digital input output GPIO with only digital LCD liquid crystal display capabilities no analog See GPIO Tm LIN Local Interconnect Network a communications DMIPS Dhrystone million instructions per second protocol DMA direct memory access see also TD LR link register DNL differential nonlinearity see also INL LUT lookup table DNU do not use LVD low voltage detect see also LVI DR port write data registers LVI low voltage interrupt see also DSI digital system interconnect LVTTL low voltage transistor transistor logic DWT data watchpoint and trace MAC multiply accumulate ECC error correcting code MCU microcontroller unit ECO external crystal oscillator MISO master in slave out EEPROM electrically erasable programmable read only NC no connect memory nonmaskable interrupt EMI electromagnetic interference NRZ non return to zero EMIF external memory interface NVIC nested vectored interrupt controller EOC end of conversion NVL nonvolatile latch see also WOL EOF end of frame operational amplifier EPSR execution program status register PAL programmable array logic see also PLD ESD electrostatic discharge Page 32 of 35 M au CYPRESS PERFORM Table 48 A
45. erization SID181 FEND Flash endurance 100 K cycles Guaranteed by charac terization SID182 FRET Flash retention TA lt 55 100K 20 years Guaranteed by P E cycles terization SID182A Flash retention TA lt 85 10 K 10 years Guaranteed by charac P E cycles terization System Resources Power on Reset POR with Brown Out Table 33 Imprecise Power On Reset PRES Spec ID Parameter Description Min Typ Max Units Details Conditions SID185 VRISEIPOR Rising trip voltage 0 80 1 45 V Guaranteed by character ization SID186 VFALLIPOR Falling trip voltage 0 75 1 4 V Guaranteed by character ization SID187 Hysteresis 15 200 mV Guaranteed by character ization Table 34 Precise Power On Reset POR Spec ID Parameter Description Min Typ Max Units Details Conditions SID190 VFALLPPOR BOD trip voltage in active and 1 64 V Guaranteed by character sleep modes ization SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1 4 V Guaranteed by character ization Note 3 Itcan take as much as 20 milliseconds to write to Flash During this time the device should not be Reset or Flash operations will be interrupted and cannot be relied onto have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated Document Number 001 87220 Rev A Page 24 of
46. ff to the main processor when the chip is in Deep Sleep mode The Cortex MO CPU provides a Non Maskable Interrupt input NMI which is made available to the user when it is not in use for system functions requested by the user The CPU also includes a debug interface the Serial Wire Debug SWD interface which is a 2 wire form of JTAG the debug configuration used for PSoC 4100 has four break point address comparators and two watchpoint data comparators Flash The PSoC 4100 has a flash module with a flash accelerator tightly coupled to the CPU to improve average access times from the flash block The flash block is designed to deliver 0 wait state WS access time at 24 MHz Part of the flash module can be used to emulate EEPROM operation if required SRAM SRAM memory is retained during Hibernate SROM A supervisory ROM that contains boot and configuration routines is provided System Resources Power System The power system is described in detail in the section Power on page 11 It provides assurance that voltage levels are as required for each respective mode and either delay mode entry on power on reset POR for example until voltage levels are as required for proper function or generate resets Brown Out Detect BOD or interrupts Low Voltage Detect LVD The PSoC 4100 operates with a single external supply over the range of 1 71 to 5 5 V and has five different power modes transitions between which are managed
47. h examples include brushless DC motor control and on chip filtering Application notes often include example projects in addition to the application note document Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family Datasheet Technical Reference Manual The Technical Reference Manual TRM contains all the technical detail you need to use a PSoC device including a complete description of all PSoC registers Online In addition to print documentation the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world 24 hours a day 7 days a week Tools With industry standard cores programming and debugging interfaces the PSoC 4100 family is part of a development tool ecosystem Visit us at www cypress com go psoccreator for the latest information on the revolutionary easy to use PSoC Creator IDE supported third party compilers programmers debuggers and development kits Page 12 of 35 ER PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM Electrical Specifications Absolute Maximum Ratings Table 1 Absolute Maximum Ratings a Details Spec ID Parameter Description Min Typ Max Units Conditions SID1 Vppp ABS Digital supply relative to Vssd 0 5 6 V Absolute max SID2 Vccp ABS Direct digital core voltage input relative 0 5 1 95 V Absolute max to Vssd SID3 ABS GPIO voltage 0 5 Vppt0 5 V Absolute max
48. ibernate Mode Vppp 1 8 to 3 6 V Regulator on Guaranteed by Characterization 51040 15535 GPIO and reset active 150 nA 25 3 6 51041 15036 and reset active 1 85 Hibernate Mode Vppp 3 6 to 5 5 V Guaranteed by Characterization SID43 Ipp3a GPIO and reset active 150 T 25 C 5 5V Hibernate Mode Vppp 1 71 to 1 89 V Regulator bypassed Guaranteed by Characterization 51046 Ipp44 GPIO and reset active 150 25 51047 15542 GPIO and reset active 1 85 Stop Mode Guaranteed by Characterization SID304 Ipp43A Stop Mode current Vpp 3 6 V 20 80 nA XRES Current SID307 155 Supply current while XRES asserted 2 5 Table 3 AC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions 51048 CPU frequency DC 24 MHz 11 71 25 5 51049 TSLEEP Wakeup from sleep mode 0 Hs Guaranteed by characterization SID50 TpEEPSLEEP Wakeup from Deep Sleep mode 25 Hs 24 MHz IMO Guaranteed by characterization SID51 THIBERNATE Wakeup from Hibernate and Stop modes 2 ms Guaranteed by characterization SID52 TaEsETwiprH External reset pulse width 1 Hs Guaranteed by characterization Document Number 001 87220 Rev A Page 14 of 35 _ PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM
49. rce or Sink Chip 200 mA Guaranteed by 7 Current characterization Note 2 must not exceed Vppp 0 2 V Document Number 001 87220 Rev A Page 15 of 35 ER PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM Table 5 GPIO AC Specifications Guaranteed by Characterization Details Spec ID Parameter Description Min Typ Max Units Conditions 1070 TRISEF Rise time in fast strong mode 2 12 ns 3 3 V Vppp Cload 25 pF SID71 TEALLF Fall time in fast strong mode 2 12 5 3 3 V Vppp Cload 25 pF SID72 TRISES Rise time in slow strong mode 10 60 3 3 V Vppp Cload 25 pF 51073 TrFALLS Fall time in slow strong mode 10 60 3 3 V Vppp Cload 25 pF 51074 1 GPIO Fout 3 3 V lt Vppp x 5 5 V Fast 24 MHz 90 10 25 pF strong mode load 60 40 duty cycle 51075 GPIO 1 7 Vx 3 3 V Fast 16 7 MHz 90 10 25 pF strong mode load 60 40 duty cycle 51076 GPIO Fout 3 3 V lt Vppp x 5 5 V Slow 7 MHz 90 1096 25 pF strong mode load 60 40 duty cycle SID245 Fopiout4a GPIO Fout 1 7 V lt 3 3 V Slow 3 5 MHz 90 10 25 pF strong mode load 60 40 duty cycle SID246 FGPIOIN GPIO input operating frequency 24 MHz 90 10 1 71 V lt lt 5 5 V XRES Table 6 XRES DC Specifications Details Spec ID Parameter De
50. rences A 1 voltage reference spec is provided for the 12 bit ADC To allow better signal to noise ratios SNR and better absolute accuracy it is possible to bypass the internal reference using a GPIO pin or to use an external reference for the SAR Analog Blocks 12 bit SAR ADC The 12 bit 806 KSample second SAR ADC can operate at a maximum clock rate of 14 5 MHz and requires a minimum of 18 clocks at that frequency to do a 12 bit conversion The block functionality is augmented for the user by adding a reference buffer to it trimmable to 1 and by providing the choice for the PSoC 4100 case of three internal voltage refer PSoC 4 PSoC 4100 Family Datasheet ences Vpp Vpp 2 and Vggre nominally 1 024 V as well as an external reference through a GPIO pin The Sample and Hold S H aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs which determine its settling time to be relaxed if required System performance will be 65 dB for true 12 bit precision providing appropriate references are used and system noise levels permit To improve performance in noisy conditions it is possible to provide an external bypass through a fixed pin location for the internal reference amplifier The SAR is connected to a fixed set of pins through an 8 input sequencer The sequencer cycles through selected channels autonomously Sequencer scan and does so with zero switching overhead
51. rt 1 Pin 3 gpio Icd csd ctb pwm P1 4 41 P1 4 39 14 ctb oa1 in Port 1 Pin 4 gpio m csd ctb P1 5 GPIO 42 1 5 1 Port 1 Pin 5 Icd csd ctb P1 6 GPIO 43 P1 6 ctb oa0 inp Port 1 Pin 6 gpio Icd _alt csd P1 7 GPIO 44 1 7 40 P1 7 4 P1 7 ctb oa1 inp Port 1 Pin 7 gpio Icd _alt csd ext ref ext vref Descriptions of the Pin functions are as follows VDDD Power supply for both analog and digital sections where there is no pin VDDA Analog Vpp pin where package pins allow shorted to Vppp otherwise VSSA Analog ground pin where package pins allow shorted to VSS otherwise VSS Ground pin Regulated Digital supply 1 8 V 5 Port Pins can all be used as LCD Commons LCD Segment drivers or CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals The following packages are supported 44 pin TQFP 40 pin QFN and 28 pin SSOP Document Number 001 87220 Rev A Page 9 of 35 Document Number 001 87220 Rev A PSoC 4 PSoC 4100 Family Figure 3 44 pin TQFP Part Pinout VCCD GPIO PAO P 2 7 GPIO P2 3 fa 5 GPIO 6 GPIO P2 4 6 GPIO PO 5 GPIO P2 5 7 Top View 288 GPI
52. s SID160 lUART4 Block current consumption at 9 100 Kbits sec SID161 lUART2 Block current consumption at 312 1000 Kbits sec Document Number 001 87220 Rev A Page 22 of 35 PSoC 4 PSoC 4100 Family F CYPRESS Datasheet PERFORM Table 26 Fixed UART AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units SID162 FUART Bit rate 1 Mbps SPI Specifications Table 27 Fixed SPI DC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units SID163 Isp Block current consumption at 1 Mbits sec 360 SID164 Ispi2 Block current consumption at 4 Mbits sec 560 SID165 Ispi3 Block current consumption at 8 Mbits sec 600 Table 28 Fixed SPI AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units SID166 SPI operating frequency master 6X 4 MHz oversampling Table 29 Fixed SPI Master mode AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units SID167 MOSI valid after Sclock driving edge 15 ns SID168 Tpsi MISO valid before Sclock capturing edge 20 ns Full clock late MISO Sampling used SID169 Previous MOSI data hold time
53. scription Min Typ Max Units Conditions SID77 Vin Input voltage high threshold 0 7 x V CMOS Input VDDD SID78 Input voltage low threshold 0 3 x V CMOS Input VDDD SID79 ReuLLuP Pull up resistor 3 5 5 6 8 5 kQ SID80 Cin Input capacitance 3 pF SID81 Input voltage hysteresis 100 mV Guaranteed by characterization SID82 IDIODE Current through protection diode to 100 Guaranteed by Vppp Vss characterization Table 7 XRES AC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID83 Reset pulse width 1 Hs Guaranteed by characterization Document Number 001 87220 Rev A Page 16 of 35 LES E PSoC 4 PSoC 4100 Family CYPRESS Datasheet PERFORM Analog Peripherals Opamp Table 8 Opamp Specifications Guaranteed by Characterization Details Spec ID Parameter Description Min Typ Max Units Conditions Ipp Opamp block current No load 10269 Ipp Power high 1000 1300 SID270 Ipp MED Power medium 320 500 SID271 Low Power low 250 350 GBW Load 20 pF 0 1 mA 2 7 V E E E 510272 GBW HI Power high 6 MHz SID273 GBW MED Power medium 4 MHz SID274 GBW LO Power low 1 MHz loUT MAX gt 2 7 V 500 mV from rail 510275 loUT HI Power
54. tage of Vbg 1 024 V Guaranteed by characterization SID262 Tei kswiTCH Clock switching from clk1 to clk2 in 3 4 Periods Guaranteed by design clk1 periods Tws24 is guaranteed by Design Document Number 001 87220 Rev A Page 26 of 35 LR 2 PSoC 4 PSoC 4100 Family Sa CYPRESS Datasheet PERFORM Ordering Information The PSoC 4100 part numbers and features are listed in the following table Table 44 PSoC 4100 Family Ordering Information Features Package T o z E gt od 46 lt 5 z G E 85 9025 5 5 919 5 lt 5 o E 4 2 5 oz o 19 lt amp iol 8 O Sb 2 alo S a z CY8C4124PVI 432 24 16 4 1 806Ksps 2 4 2 22 wv B 0410 CY8C4124PVI 442 24 16 4 1 v 806 Ksps 2 4 2 22 0411 CY8C4124LQI 443 24 16 4 2 806 Ksps 2 4 2134 0416 o CY8C4124AXI 443 24 16 4 2 806 Ksps 2 4 2 36 041A e CY8C4125AXI 473 24 32 4 2 806Ksps 2 4 2 136 041b CY8C4125PVI 482 24 32 4 1 v 806 Ksps 2 4 2 22 wv 0412 CY8C4125LQI 483 24 32 4 2 806 Ksps 2 4 2134 0417 8 4125 483 24 32 4 2 806 Ksps 2 4 2 36 041C
55. terization Spec ID Parameter Description Min Typ Max Units Details Conditions SID149 Block current consumption at 100 kHz 10 5 SID150 11262 Block current consumption at 400 kHz 135 SID151 li2c3 Block current consumption at 1 Mbps 310 10152 11264 enabled in Deep Sleep mode 1 4 pA Table 22 Fixed AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID153 Bit rate 1 Mbps LCD Direct Drive Table 23 LCD Direct Drive DC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID154 li cpLOW Operating current in low power mode 5 HA 16 x 4 small segment disp at 50 Hz SID155 Ci cDCAP LCD capacitance per segment common 500 5000 pF Guaranteed by Design driver SID156 LCDorrsET Long term segment offset 20 mV SID157 li 1 LCD system operating current 2 mA 32 x 4 segments Vbias 5 V 50 Hz 25 C SID158 2 LCD system operating current 2 mA 32 x 4 segments Vbias 3 3 V 50 Hz 25 C Table 24 LCD Direct Drive AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID159 Ficp LCD frame rate 10 50 150 Hz Table 25 Fixed UART DC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Condition
56. ters do not intervene but a Master that has just become activated may start an Arbitration cycle When the SCB is 12 Slave mode and Address Match on External Clock is enabled AM 1 along with operation i in the internally clocked mode OP 0 then its address must be even UART Mode This is a full feature UART operating at up to 1 Mbps It supports automotive single wire interface LIN infrared interface IrDA SmartCard 1507816 protocols all of which are minor variants of the basic UART protocol In addition it supports the 9 bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines Common UART functions such as parity error break detect and frame error are supported An 8 deep FIFO allows much greater CPU service latencies to be tolerated SPI Mode The SPI mode supports full Motorola SPI TI SSP essentially adds a start pulse used to synchronize SPI Codecs and National Microwire half duplex form of SPI The SPI block can use the FIFO and also supports 25 mode in which data interchange is reduced to reading and writing an array in memory GPIO The PSoC 4100 has 36 GPIOs The GPIO block implements the following m Fight drive strength modes Analog input mode input and output buffers disabled Input only Weak pull up with strong pull down Strong pull up with weak pull down Open drain with strong pull down
57. the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 87220 Rev A Revised June 20 2013 Page 35 of 35 All products and company names mentioned in this document may be the trademarks of their respective holders
58. tion 3 3 LSB SID313 SNR Ratio of counts of finger to noise 5 Ratio Capacitance range Guaranteed by characterization of 9 to 35 pF 0 1 pF sensitivity SID314 IDAC1 CRT1 Output current of Idac1 8 bits in High 612 SID314A IDAC1_CRT2 Output current of Idac1 8 bits Low 306 SID315 IDAC2 CRT1 Output current of Idac2 7 bits in High 304 8 SID315A IDAC2 CRT2 Output current of Idac2 7 bits Low 152 4 range Document Number 001 87220 Rev A Page 20 of 35 lt lt CYPRESS PERFORM Digital Peripherals PSoC 4 PSoC 4100 Family The following specifications apply to the Timer Counter PWM peripheral in timer mode Timer Table 15 Timer DC Specifications Guaranteed by Characterization Datasheet Spec ID Parameter Description Min Typ Max Units Details Conditions SID115 Block current consumption at 3 MHz 19 pA 16 bit timer SID116 2 Block current consumption at 12 MHz 66 pA 16 bit timer Table 16 Timer AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID118 TTI
59. yp Max Units Details Conditions SID93 TsENSACC Temperature sensor accuracy 5 1 5 40 to 85 SAR ADC Table 12 SAR ADC DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID94 A RES Resolution 12 bits SID95 A CHNIS 5 Number of channels single ended 8 8 full speed SID96 A CHNKS D Number of channels differential 4 Diff inputs use neighboring I O SID97 A MONO Monotonicity Yes Based characterization SID98 A GAINERR error 0 1 With external reference Guaranteed by characterization SID99 A OFFSET Input offset voltage 2 mV Measured with 1 Vrer Guaranteed by characterization SID100 A ISAR Current consumption 1 mA SID101 A VINS Input voltage range single ended Vss V Based on device characterization SID102 A VIND Input voltage range differential Vss V Based on device characterization SID103 A INRES Input resistance 2 2 Based on device characterization SID104 A INCAP Input capacitance 10 pF Based on device characterization Table 13 SAR ADC AC Specifications Guaranteed by Characterization Spec ID Parameter Description Min Typ Max Units Details Conditions SID106 A PSRR Power supply rejection ratio 70 510107 CMRR Common mode rejection ratio 66 dB Measured at 1 V SID108 A SAMP Sample rate 806 Ksps SID109 A SNDR Signal to noise and distortion ratio 65 dB
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