Harrier-F VDK - genesys ideation
Contents
1. Use with any Altera development kit with a standard HSMC interface e Upto 8 camera inputs o 6 continuous inputs and 2 multiplexed inputs o Developed to use the Finch Imager e Texas Instruments FPD Link III deserializer transport interfaces Coaxial cable interface Camera power supplied by Harrier daughter card High Speed pixel data up to 1 4Gbps Remote UO for exposure control oO 00 0 Up to 15m coaxial cable connection e FAKRA coaxial interconnect o Positive locking coaxial e Reference design in programmable logic and software o Platform setup o Image capture o Image display 4 genesys ideation proprietary information a Harrier F VDK 1 3 System Block Diagram The system block diagram describing the interfacing between the Fincher Imagers Harrier Daughter Card and Altera Development kit is shown below Each of the Finch Imagers connects to and draws power from the Harrier Daughter Card via the FPD Link III serial interface The Harrier Daughter Card mates directly to the Altera Development Kit via a built in High Speed Mezzanine Card HSMC connector FPD LINK III FAKRA Cable FPD LINK III FAKRA Cable FPD LINK Ill FAKRA Cable FPD LINK Ill FAKRA Cable FPD LINK III FAKRA Cable FPD LINK III FAKRA Cable 12V HSMC Mating Built In Micro USB B via USB Blaster II Video Stream Output Figure 1 1 Harrier F VDK System Block Diagram The Harrier daughter card accommodates multiple imag2. please visit our web site http www genesysideation com support for their specific reference manuals 3 2 Altera Development Boards The Harrier F VDK was developed with the Stratix IV GX Development Board However the VDK can be used for development with any development board that follows the HSMC standard It does not use high speed transceivers on this development board for any of the camera I O For more information on the Stratix IV GX Development Board please visit Altera s web site http www altera com products devkits altera kit siv gx html for specific reference manuals 4 Programmable Logic Reference 4 1 Key Features The Harrier F VDK was developed with the Stratix IV GX Development Board As such the programmable logic reference utilizes some of the features from this development board The subsequent bullet list details some of the more notable features in the logic reference design 9 genesys ideation proprietary information a Harrier F VDK e NIOS II 32 bit RISC Processor e Six parallel video pipelines e 2C interface for serdes control camera configuration and I O expansion e Software controllable video pipeline e DDR3 memory interface e HDMI output at 1920x1080 resolution at 60fps The programmable logic reference is limited to 30 minutes run time If you are interested in further enhancement of the programmable logic reference or wish to have port to a different FPGA platform please contact us a
3. ers 1280 x 720 60 fps and transports the pixel data via the Texas Instruments FPD Link III interfaces for each independent video path Connection between imagers and daughter card is accomplished by a coax cable using the FAKRA interconnect system The platform also includes software and custom logic reference design to enable the developer to quickly realize design goals beyond platform setup image capture and image display 2 Getting Started 2 1 Kit Components The following tables detail the components of the system Table 2 1 Harrier F VDK Components Harrier Daughter card See detail below Finch Imager 8 See detail below FPD Link III Cable 8 Coaxial cable for transmission of the FPD Link III data for each imager HDL Configuration Initialize imagers clock video data in for each video stream allow user I O to control exposure or illumination on the CMOS imager board Software System control and initialization runs on Nios II microcontroller 5 genesys ideation proprietary information a Harrier F VDK Initializes imagers default to 1280 x 720 60 fps 2 1 1 Altera Evaluation Board The demonstration CL and SW are targeted for the Stratix IV GX development kit 2 1 2 FPD Link III SMB Interconnect The system utilizes a coaxial cable for transmission of the FPD Link III data for each imager There are SMB connectors with a FAKRA interconnect system on both the Finch and Harrie
4. genesys ideation Harrier F VDK User s Manual genesys ideation a wholly owned subsidiary of DornerWorks Ltd great ideas begin here 6 9 2014 a Harrier F VDK Contents Ee ee ele EE 1 1 OVER VIGW osc cect eege geed Dee geet E E E T 1 2 FEACUPES ia gege eeneg AER S E 1 3 System Block Diagram wesc eisereen e eege ege adelante 2 Getting Started E 2 1 lee ln CN 2 1 1 Altera Evaluation Board 2 1 2 FPD Link III SMB Interconnect eeeeeeeseceeseeeeeeeceeeeeeaeeeeaeeeteeeeens 2 1 3 Harrier Daughter Card 2 1 4 Finch imager BOSS svsccsvcsscecivesdecdezeasendeue sucdeenssededde duccedeauetsedeesve 2 1 5 HDL CONFUSION weccivevecccdcccoucs fs denceatGvendecsveebeedev cence dudensealesvendateven 2 1 6 SIE 2 2 SO CUD DEE 2 2 1 Finch to Harrier Connectlon cceeeeeeesseceeeceeeeeeeceeeeeaaeeeeaaeeteeeeens 2 2 2 Harrier to FPGA Connection 2 2 3 Powering the Harrier Daughter Card 2 2 4 Powering the Finch Imager cccccssssccececeseesesnaeceeeeessesecteaeeeeeens 2 2 5 ERGA Nell Ee EE 2 3 Power DEE 2 4 Load Your First Project ccccccccccssssssssssecececsesesesneaeeeeeeeseesesneaeeeeeeesessees 3 Fotmmorejntotroatlont eege keekde Sege SEEECe a a Nd 3 1 Genesys Ideation Reference Manuals ssssesssssssssssssereerrssssrsereernsssssene 3 2 Altera Development Boarde 4 Programmable Logic Reference ccccccssscsecsssseceesssaececsesaeeeesesaeeeesesaeeeeseaaes 4 1 Key Features iviine cc vessetea
5. ing software for the Harrier Daughter Card 5 3 2 Finch Devices The Finch board contains the following devices that are controlled via 12C e Texas Instruments DS90UB913Q FPD Link III Serializers Please reference the Finch Imager User Manual for details on the developing software for the Finch Imager 14 genesys ideation proprietary information
6. ited binary library This will allow the demonstrator and the developer to get a flavor of how to use and manipulate the demonstration software to expand its functionality A Nios II microcontroller is implemented on the FPGA to manage the initialization and control of the video streams 2 2 Setup 2 2 1 Finch to Harrier Connection Locate the FPD Link III connector on the Finch Imager board as highlighted in the figure below 6 genesys ideation proprietary information Harrier F VDK Table 2 3 Finch Imager Align the slotted connector housing on the cable with the keys on the Finch board and snap into place be we LA SORTI yt a ene Again align the slotted connector housing on the cable with the keys on the Harrier board and snap into place 7 genesys ideation proprietary information m Harrier F VDK Again align the connector Harrier Deserializer with the keys on the Finch and Harrier boards and snap into place 2 2 2 Harrier to FPGA Connection The Harrier Daughter card connects to the FPGA via the built in HSMC connector 5mm spacers between the two boards are recommended as well as stand offs on the opposite end of the Harrier card 2 2 3 Powering the Harrier Daughter Card There are two options for powering the Harrier Daughter Card Note that 12V will be passed to the Harrier card from the Altera Dev Kit via the HSMC connector Alternatively the board can be powered with 12V from a DC bar
7. r boards 2 1 3 Harrier Daughter Card The Harrier Card accepts up to 8 video signals streamed over multiple FPD Link III interfaces and converts them back into parallel data However only 6 continuous streams of video are available simultaneously The multiplexed inputs can be programmatically switched at run time to allow 2 alternative video streams to be manipulated and displayed Once the high speed bit stream is converted to parallel data the signals will be routed through the HSMC connector and to the FPGA The data is then sent through a video pipeline in the FPGA where the demonstration program software can manipulate the video streams for output 2 1 4 Finch Imager Board s The CMOS Imager Board uses the Aptina AR0132AT HD imager as the source of the video data The imager is initialized by the software for 60 frames of video data per second and 10 bit pixel data depth 2 1 5 HDL Configuration The custom logic used in the Cyclone FPGA initializes the imagers clocks the video data in for each video stream and allows user I O to control exposure on the CMOS imager board The reference design leverages several IP cores from Altera s Video IP Suite A Nios II microcontroller is implemented to manage the initialization and control of the video streams 2 1 6 Software The software running on the Altera development kit is the main source of system control and initialization The software will be available for development as a time lim
8. rel jack i e J1 8 genesys ideation proprietary information a Harrier F VDK 2 2 4 Powering the Finch Imager Power will be supplied to the Finch Imager from Harrier Daughter card via the FPD Link III cable Each imager is powered off by default until software enables the respective power switch 2 2 5 FPGA Connections Connect the power USB and display monitor cables to the FGPA Refer to the manual for your chosen FPGA Dev Kit for specific instructions 2 3 Power Up When the Harrier Daughter card is properly powered see Section 2 2 3 above four status LEDs should be illuminated LD1 signifies that the 12V regulator is working correctly LD2 corresponds to the VADJ_D regulator LD3 to the 3 3V regulator and LD4 to the 1 8V regulator 2 4 Load Your First Project After connecting the system together see Sections 2 2 1 and 2 2 2 above you are ready to load the FPGA with a configuration and software The following steps explain how to run the demonstration software ELF file and how to program the FPGA with the demonstration SOF The demonstration will configure the cameras initialize the video pipelines and tile all 6 streams of video on the HDMI output The demonstration configuration and software can be found on the respective product pages on the Genesys Ideation web site genesysideation com 3 For more information 3 1 Genesys Ideation Reference Manuals For more information on the Harrier Daughter Card and Finch Imager
9. t sales genesysideation com 10 genesys ideation proprietary information u Harrier F VDK 4 2 HDL Block Diagram The following block diagram highlights the various sections of the FPGA configuration 4 3 1 SDA SCL 4 3 2 4 3 9 CAM 1 2 Bayer to RGB gt ClockediVideo iagi Video Pipeline a Input CAM 3 4 Bayer to RGB gt cae Leg Video Pipeline al e 4 3 5 CAM 5 _ Bayer to RGB gt Cocked vides Video Pipeline gt E Input Clocked Video Alpha Blending z Output Mixer Clocked Video CAM 6 Bayer to RGB gt Input gt Video Pipeline a Clocked Video CAM 7 Bayer to RGB LS Input Video Pipeline gt Clocked Video CAM 8 Bayer to RGB Si Input gt Video Pipeline gt Figure 4 1 High Level Multi Camera Custom Logic Design 5 Software Reference 5 1 Key Features The demonstration software available on the Genesys Ideation website performs the following functions e DC configuration of the TI FPD Link III serdes e DC configuration of the Aptina ARO132 CMOS Imager e DC controlled I O Expander used for 11 genesys ideation proprietary information a Harrier F VDK o Imager power control o Locked link indication o Alternate channel selection e DC configura
10. tion of the Krontel HDMI interface e Pipeline configuration and manipulation e UART interface for debugging and demonstration This demonstration software was written for the Stratix IV GX Development Board If you are interested in a port of the software to a different platform please contact sales genesysideation com 12 genesys ideation proprietary information Harrier F VDK 5 2 SW Block Diagram The block diagram of the demonstration software is as follows Device Legend Reset Altera Dev Kit Initialize HDMI Chip Initialize Alpha Blending Mixer Initialize Camera 12C Master Configure UO Port Expanders Enable Camera Power Switches Configure Deserializers Is video valid Configure Clipper j Configure Scaler j Are there more channels to configure Enable valid mixer channels Figure 5 1 High Level VDK Software Algorithm 13 genesys ideation proprietary information a Ee Harrier F VDK 5 3 Software Development Guide The following section includes relevant information for software developers interested in writing custom drivers for the Harrier daughter card and the Finch camera boards 5 3 1 Harrier Devices The Harrier daughter card contains the following devices that are controlled via 12C e Microchip MCP23017 IO Port Expanders e Texas Instruments DS90UB914Q FPD Link III Deserializers Please reference the Harrier Daughter Card User Manual for details on the develop
11. vebacectnatsddcessnccededadeetendebe NERT deg E 4 2 HDL Block Diagram isisisesssnsssirsensississiresirsscnissssenesasrssrakenisun vonis saeknn essre 5 Software Referent ssepe sseccgcoe ca sccgusensensoendssagescesegebcamesncevacseushtneesaeeedes Revete 5 1 Key Features cccccctscdssessacesctssabvslveseacuecss ndacseasucuctessavedessencueveusavelesteucuebsses 5 2 SW Block Diagram ccccccccccsssessssesecececessesesaeceeeesceeseaeaeceeeeessesenaeaeeeesens 5 3 Software Development Guide 5 3 1 Harrier DEVICES EEEE EE E E 2 genesys ideation proprietary information 5 3 2 3 Harrier F VDK Sieste E genesys ideation proprietary information a Harrier F VDK Harrier F VDK User s Manual 1 Introduction 1 1 Overview The Genesys Ideation Harrier F Video Development Kit VDK is a multiple camera daughter card solution for Altera s developer kits The VDK can be used to develop products for the automotive industrial and security industries Automotive industry trends suggest a need for multiple cameras in a vehicle to assist the driver with safety related features Automation incorporating machine vision has been a consistent trend in the Industrial business sector Certain security concerns can be addressed with multiple camera systems utilizing an intelligent computational platform near the video source 1 2 Features A complete VDK has the following features e Altera FPGA with Nios II or HPS o
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