User`s Manual (Rev.1.02)
Contents
1. VR4310 PCI9060ES Switches on the RTE VR4310 PC board SW3 4 is used to specify a ROM monitor type endianess specification only Remarks Monitor represents the factory setting 0 32 bit monitor for little endian mode 1 32 bit monitor for big endian mode Set SW3 1 SW3 2 and SW3 3 to the following values at all times Remarks Not used represents the factory setting OFF This state must be used at all times 32 bit mode ROM address Bank selection represents the factory setting MD32 64 Full bank ROM A15 ROM A16 OFF ENDIAN 41 RTE VR4310 PC User s Manual Rev 1 02 10 1 2 SWA is a general purpose input port switch On the installed ROM monitor SW4 is used to set the RS 232C baud rate Remarks Baud rate JSIO1 dU represents the factory setting 0 115 200 bps 1 38 400 bps OFF 2 19 200 bps OFF 3 9 600 bps Memo For the other communication settings specify 8 bit data no parity and one stop bit at all times Remarks represents the factory setting These states must be used at all times Not to be set OFF Not to be set OFF Not to be set2. 16 RTE VR4310 PC User s Manual Rev 1 02 5 4 6 Interrupt Controller 17 5 4 7 PCI COntrouler 18 G6 BUS CYCLE TIMING tt retire 19 Gils SSRAMACCESS 19 6 2 DRAM AGGESS a 21 6 3 LOCAL BUS ACCESS iia 25 6 4 MEMORY CONTROLLER REGISTER 5 29 EXT BUS 30 7 1 CONNECTOR 30 1 25 SIGNALS zi tatiana tata tidad 31 Tas lt aa Se mud 32 8 SOFTWARE uc A ae uisu tout uncut 33 8 1 INTERRUPT nsns nnn 33 Ctl JntermuptEIDFary asas oii dud ute toten is 33 8 1 2 Int m pt OUTING 34 8 1 8 Sample Program cnn 34 8 2 35 35 6 22 dntert pt A 35 8 2 8 Data 29929
3. LED oo SW RST JPRN JSIO2 160552 VR4310 PCI9060ES Switches on the RTE VR4310 PC Board Select a monitor type with SW3 1 and SW3 4 Remarks 32 64 bit tion MD32 64 it operation represents the factory setting 64 bit mode 32 bit mode Remarks Endianess specification represents the factory setting Little endian Big endian 37 RTE VR4310 PC 9 2 2 Set SW3 2 and SW3 3 to OFF at all times ROM address ROM A15 ROM A16 User s Manual Rev 1 02 Bank selection represents a factory setting OFF ENDIAN MD32 64 Full bank SW4 is a general purpose input port switch On the installed ROM MULTI monitor SW4 is used to set the RS 232C baud rate and profiler timer interval Baud rate JSIO1 Remarks represents the factory setting 0 115 200 bps 1 38 400 bps 2 19 200 bps 3 9 600 bps Memo For the other communication settings specify 8 bit data no parity and one stop bit at all times MULTI profiler interval timer 0 Remarks represents the factory set
4. 41 10 BOARD SET ING edocet pet pei pet NE RI EI ERE 41 10 1 1 Switch Setting AAA O 41 10 1 2 Connection between the Host PC and 42 10 2 PARTNER MONITOR eene 42 10 2 1 Monitor Work 42 702225 Intetrupt itat tta du 42 10 2 8 Interrupt for Forced Break 2 0022 2 2 222 200000000 00000 nnn 42 10 2 4 Stack Selling s lA 42 10 2 5 Special Instruction 43 11 APPENDIX JC1 AND JC2 nnna 44 RTE VR4310 PC User s Manual Rev 1 02 INTRODUCTION This manual describes the RTE VR4310 PC which is an evaluation board for the VR4310 NEC s RISC CPU The board features a VR4310 CPU capable of operating at a maximum speed of 166 MHz SRAM DRAM ROM serial 2 ch and parallel 1 ch interfaces and inputs outputs such as timers These functions enable the RTE VR4310 PC to be used for a wide variety of applications including processor performance evaluation and application program development and to also be used as an engine for demonstration and simulation The GHS MULTI or Midas PARTNER source level debugger can be used as a development software tool with the RTE VR4310 PC The type of monitor to be stored in ROM depends on the debugger type In ROM the monitor specified at the time of
5. SYSAD48 SYSAD49 SYSAD50 SYSAD51 SYSAD52 SYSAD53 SYSAD54 SYSAD55 GND GND SYSAD56 SYSAD57 SYSAD58 SYSAD59 SYSAD60 SYSAD61 SYSAD62 SYSAD63 SCVALID SCMATCH N C GND GND SYSCLKO SYSCLK1 MODECLK GND GND ANRRDY EOK RDRDY N C VALIDOUT PVALID VALIDIN EVALID EXTREQ EREQ RELEASE PMASTER 3 3V 3 3V INTO INT1 INT2 INT3 INT4 INT5 N C RESET NMI GND GND SCCWEO N C SCCWE1 N C SCDCEO SCDCE1 N C SCTCE N C SCCLR N C SCTDE N C N C SCTOE N C SCDOE N C 5V 5V JC1 Pin Arrangement N N 44 RTE VR4310 PC Signal name User s Manual Rev 1 02 Signal name N C SCENABLE SCSIZEO SCSIZE1 N C N C 3 3V 3 3V SYSCMDO SYSCMD1 SYSCMD2 SYSCMD3 SYSCMD4 SYSCMD5 LEN SYSCMD6 UEN SYSCMD7 N C SYSCMDS SYSCMDP GND SYSADCO N C GND SYSADC1 N C SYSADO SYSAD1 SYSAD2 SYSAD3 SYSAD4 SYSAD5 SYSAD6 SYSAD7 GND GND SYSAD8 SYSAD9 SYSAD10 SYSAD11 SYSAD12 SYSAD13 SYSAD14 3 3V SYSAD15 3 3V SYSADC2 N C SYSADC3 N C SYSAD16 SYSAD17 SYSAD18 SYSAD19 SYSAD20 SYSAD21 SYSAD22 SYSAD23 GND GND SYSAD24 SYSAD25
6. 0 9 4 1 1 Standalone Use of the Board RS 232C 9 4 1 2 Insertion into the PCI Slot PCI BUS Connection essen 9 5 7 HARDWARE REFERENCES da 10 Sds RESET aaa nado 10 526 INTERRUP Titanate E a A E St o ela ee Li an 10 5 3 ADDRESS MAP seti e ETENE EEE E ENTARA MEME 11 5 3 1 SRAM Space 0000 0000H to 7 11 5 3 2 DRAM Space 0800 0000H to OFFF FFFFH x800 0000H xFFF FFFFH 11 5 3 3 MEM CNT Space 1000 0000H to 17FF FFFFH 11 5 3 4 Not Used 1800 0000H to 19FF FFFFH e nnns 12 5 3 5 EXT BUS Space 1A00 0000H to 12 5 3 6 NO Space 1C00 0000H to 1EFF FFFFH esses 12 5 3 7 Space 1F00 0000H to 1FFF FFFFH sse 12 545 pepercit RE 12 5 4 1 SRAM Controller 5 0 2 0 0000000090000000044440 13 5 4 2 DRAM Controller sessi nnns nnns 13 5 4 3 General Purpose I O Port 0000022 00000000000 00 nnns 15 5 4 4 Serial Parallel VO SCCO 1 2 2002 00000000000000 16 5455
7. The figure below shows the timing chart for a write cycle LCLK 32 MHz LOCALREQ LOCALACK CPU DATA LOCAL ADDR LOCAL DATA LW R LDSTB LRDY Write Local Bus Write Cycle The states are explained below in the order of clock cycle numbers 0 1 Awrite request to the local bus starts 2 The local bus controller returns an acknowledgement signal and latches the address and write status LW R 3 5 Data is determined two LCLKs after the request is deactivated then access is started by activating the data strobe LDSTB in the next cycle 8 9 When the local bus ready signal LRDY is returned the data strobe is deactivated and the write cycle is terminated 10 15 If the CPU data size is greater than 16 bits the write cycle is repeated by switching to the next address and data 17 Once all the write cycles have been completed the next request is accepted 28 RTE VR4310 PC 6 4 The local bus ready signal LRDY depends on the space allocated to the local bus space table below lists the local bus ready signals Local bus space Ready signal Local bus clock 32 MHz User s Manual Rev 1 02 Remarks The ROM 5 LCLKs About 150 ns Fixed oNete 1 7 LCLKs About 210 ns Fixed EXT BUS ERDY EXT BUS ready PCI controller PCI controller ready signal Not allocated 2 Time over re
8. The monitor does not use SW4 5 to SW4 8 which are to be set to OFF at all times Connection between the Host PC and Board Make a connection with the host PC via the serial or PCI bus as explained in Chapter 4 10 2 PARTNER MONITOR 10 2 1 10 2 2 10 2 3 10 2 4 Monitor Work RAM The monitor uses reserves the SRAM area between the start address and 10000H 64 KB as work RAM In other words user programs are not allowed to use logical addresses 8000 0000H to 8000 FFFFH and A000 0000H to AO00 FFFFH This also applies to these image areas Interrupt When using an interrupt with a user program see Section 8 1 Interrupt for Forced Break The monitor uses the INTO interrupt for a forced break or interrupt for communication Stack Setting The initial value of the stack pointer is set to 8007 FFFCH highest SRAM address by the monitor 42 RTE VR4310 PC User s Manual Rev 1 02 10 2 5 Special Instruction The monitor uses the following instruction for single step breakpoint and system call functions BREAK instruction Breakpoint This instruction cannot be used with user programs 43 RTE VR4310 PC User s Manual Rev 1 02 11 APPENDIX C JC1 AND JC2 CONNECTORS Signal name Signal name SYSADCA N C SYSADC5 N C SYSAD32 SYSAD33 SYSAD34 SYSAD35 SYSAD36 SYSAD37 SYSAD38 SYSAD39 GND GND SYSAD40 SYSAD41 SYSAD42 SYSAD43 SYSAD44 SYSAD45 SYSAD46 SYSAD47 3 3V 3 3V SYSADOS SYSADC7
9. int to monitor can not Break amp Step ResIPnBit SR IP4 ei not Break amp Step di SetIPnBit SR_IP4 If to monitor 0 return 1 return 0 disable all interrupt Save original vector code amp set new vector set function vector table set 4 bit enable all interrupt process disable all interrupt reset IP4 bit remove vector restore original vector code enable all interrupt flag Disable JUSR IRQ interrupt Enable multiple interrupt interrupt operation Enable JUSR IRQ interrupt request monitor handler normal end 34 RTE VR4310 PC User s Manual Rev 1 02 8 2 8 2 1 8 2 2 ROM PROGRAMMING When creating user programs in the ROM on this board use the information provided in this section Initialization After initializing the processor registers the reset processing routine sets the required wait cycles with the memory access controller When using DRAM refresh it by setting timer 2 Internal initialization of the processor Use 0 for offset in little endian mode Use 7 for offset in big endian mode 0xB8000000 offset b lt 1 SRAM 1 wait cycle 0xB8000400 offset b lt 1 DRAM CAS width 2 clock cycles 0xB8000500 offset b lt 4 DRAM RAS access 5 clock cycles 0xB8000600 offset b lt DRAM RAS precharge 4 clo
10. SYSAD26 SYSAD27 SYSAD28 SYSAD30 SYSAD29 SYSAD31 GND GND SCWORDO N C SCWORD1 N C SCLINEO N C SCLINE1 SCLINE2 N C SCLINE3 SCLINE4 N C SCLINES SCLINE6 N C N C N C N C N C SCLINE7 3 3V 3 3V SCLINES SCLINE9 SCLINE10 N C SCLINE12 N C SCLINE11 N C SCLINE13 N C SCLINE14 N C SCLINE15 N C GND GND COLDRESET VCCOK N C MODEIN MODECLK SYSCLK1 N C ENDIAN JTDI JTDO JTMS JTCK N C N C 5V JC2 Pin Arrangement 5V 45 RTE VR4310 PC User s Manual Rev 1 02 Memo RTE VR4310 PC User s Manual M762MNL02 Midas lab 46
11. DRAM ADDR DRAM DATA DRAM RAS DRAM CAS DRAM WE SYSCLK V SYSAD A LLL Y SYSCMD PVALID EOK Write burst 4 words DRAM Write Cycle DataRate DxxDxxDxxDxx The states are explained below in the order of clock cycle numbers 0 1 2 9 16 Usually EOK is inactive A DRAM write cycle is determined and the row address and RAS are activated 3 4 EOK is activated one clock cycle after RAS is activated and a CPU external write cycle starts two clock cycles after EOK First data output This data is latched and held after which the EOK is deactivated DRAM CAS write cycle The Dxx data rate is fixed so that the CAS write pulse width is 2 clock cycles WE is deactivated before the next data is latched then the DRAM address is changed in the next cycle sequential address The write cycle is repeated The last data is written to 15 then RAS and WE are deactivated after two clock cycles When HITEN 1 RAS is held active 23 RTE VR4310 PC User s Manual Rev 1 02 When HITEN 1 RAS is held after DRAM access If a row address match hit occurs in the next access a CAS cycle is executed immediately reducing the number of access clock cycles However this is effective only in a read cycle In a write cycle even if a match occurs EOK is delayed by one clock cycle because of address comparison If a mismatch unhi
12. The table below indicates the states indicated by the LEDs Meaning Remarks Bus time out occurrence Local bus only Lights when the power is turned on 7 segment LED port output The 7 segment LED can be turned on or off by control from a general purpose output port For details see Section 5 4 3 DIVMODE SWITCH SW1 SW1 is used to specify the level of the DIVMODE 2 0 pins of the CPU OFF represents 1 and ON represents 0 Remarks represents a factory setting Dividing ratio Mclk Pclk 1 3 1 2 1 15 1 4 1 3 Caution Ensure that PCLK does not exceed the frequency guaranteed for VR4310 operation ROM BANK SWITCH SW3 SWS is used for ROM bank setting Up to four banks each consisting of 64K bytes can be allocated by manipulating the two high order address bits of the ROM with this switch Remarks 32 64 bit operation MD32 64 operation represents the factory setting ROM address Bank selection ROM A15 ROM A16 represents the factory setting CPU A16 CPU A17 With no bank CPU A16 ENDIAN Endianess only CPU A16 MD32 64 Operation bit mode only ENDIAN MD32 64 Full bank RTE VR4310 PC User s Manual Rev 1 02 3 6 3 7 3 8 Remarks represents the factory setting Endianess specification ON 0 Little endian 1 Big endian The installed monitor uses
13. last cycle according to the WE signal PMASTER DRAM ADDR DRAM DATA DRAM RAS DRAM CAS DRAM WE 0 11 2 3 4 5 6 7 8 9110111 12 13 14 15 16 17 18 19 20 ss LL LU UU U UU UU UU UU e svp GK KT syscmp X Pvaup T TL TL TALL ex ull illl ec EVALID J Read burst 4 words DRAM Read Cycle RCAST 0 MRAS 3 PRAS 3 EDOEN 1 The states are explained below in the order of clock cycle numbers 0 1 2 3 4 5 6 7 8 9 10 15 EOK is activated A DRAM read cycle starts RAS is activated as soon as the row address is determined Upon switching to a column address CAS is activated two clock cycles after RAS The first read data is determined At this time CAS is held until the cycle DRAMC MRAS 1 Data is latched and held then VALIDIN is returned after two clock cycles During the two clock cycles data parity calculation is performed for the SYSADC bus The cycle is repeated until the last data EOD is reached When HITEN 1 or 14 RAS is held active By activating WE the data is placed in the high impedance state 22 RTE VR4310 PC User s Manual Rev 1 02 A DRAM write cycle follows the output data rate of the CPU For DRAM a cycle is started by returning EOK one clock cycle after RAS is activated For DRAM write an early write cycle is used
14. of the JUSR connector INTERRUPT The interrupt sources outside the CPU are listed below Interrupt Related section NMI JUSR 2 NMI Section 3 7 INTO Interrupt controller INTOM Section 5 4 6 INT1 Interrupt controller INT1M Section 5 4 6 INT2 EXT BUS Chapter 7 INT3 JUSR 3 IRQ Section 3 7 INT4 Not used fixed to 1 External interrupts be masked by hardware See Section 5 4 6 RTE VR4310 PC User s Manual Rev 1 02 5 3 5 3 1 5 3 2 5 3 3 ADDRESS MAP The address assignment of the board is shown below Virtual address Physical address OxFFFF FFFF OxtFFF 0x1F00 0000 0 000 0000 i EXT BUS 0x1A00 0000 N 0xA000 0000 0x1800 0000 0 8000 0000 j MEMCNT 0x1000 0000 d DRAM 0x4000 0000 0x0800 0000 i SRAM kseg0 1 0x0000 0000 0x0000 0000 Address Map When the MULTI monitor is used programs are executed in the kernel space 8000 0000H to BFFF FFFFH where a TLB map is not used When a cache is used 8000 0000H is added to physical addresses to determine logical addresses When cache is not used 000 0000 is added SRAM Space 0000 0000H to 07FF FFFFH The SRAM installed on the board has a real space of 512K bytes the remaining area is the image space To access the SRAM set one or more wait cycles with the SRAM controller SRAMC when the external bus clock speed is 40 MHz or higher See Section 5 4 1 This space can be accessed as a cache o
15. the PCI9060ES manufactured by PLX Technology is used The PCI9060ES uses endianess control pins so that the internal registers support both big endian and little endian modes RTE VR4310 PC User s Manual Rev 1 02 6 BUS CYCLE TIMING The RTE VR4310 PC controls the bus cycle according to the type of device used such as SRAM DRAM ROM or I O This section describes the timing of each access cycle 6 1 SRAM ACCESS In the SRAM read cycle access is performed with 0 to 3 wait cycles inserted according to the setting of the SRAM SWAIT register see Section 5 4 1 Access with no wait cycle inserted is possible only when the bus clock SYSCLK speed is 40 MHz or less 0112134151678 9 10 11 12 13 14 15 16 17 18 19 sve UUUUUUUUUUUUUUUUUUUUUL sew JA Fem ex mmu SYSCMD reap 1 XT feo A PVALID EOK PMASTER EVALID SRAM ADDR SRAM DATA SRAM CS SRAM OE Read burst 4 words SRAM Read Cycle SWAIT 2 The states are explained below in the order of clock cycle numbers O An external CPU read cycle starts Usually EOK is inactive 1 3 EOK is activated 3 4 The wait cycles two wait cycles in this example set with SWAIT are inserted 5 SRAM data is determined The SRAM address is changed in the next cycle sub address 5 6 The data is latched and held then EVALID is returned after two clock cycles 7 15 This cycle is repeated
16. the banks as follows ROM address 16 bits For the MULTI 219 0x00000 0x07FFF For little endian 64 bits 0x08000 0xOFFFF For big endian 64 bits 0x10000 0x17FFF For little endian 32 bits 0x18000 0x1FFFF For big endian 32 bits Note With PARTNER only banks 2 and 3 are used GENERAL PURPOSE INPUT SWITCH SW4 SW4 is a data switch for general purpose input ports When a switch contact is open it corresponds to 1 When it is closed it corresponds to 0 See Section 9 2 1 or 10 1 1 and Section 5 4 3 for details USER CONTROLLED PIN JUSR The JUSR connector is a set of control pins which are set to use mainly the ROM in circuit debugger It enables a reset and an interrupt from the ROM in circuit debugger JROMEM Function Remarks RESET input active low 10 kQ pull up resistor NMI input active low 10 kQ pull up resistor INT3 input active low 10 kQ pull up resistor Ground CPU TEST CONNECTORS JC1 JC2 The JC1 and JC2 connectors are connected to the CPU pins These connectors are used for tests such as signal measurement and for CPU board connection For information about the connector pin arrangement see Chapter 11 RTE VR4310 PC User s Manual Rev 1 02 3 9 3 10 SERIAL CONNECTORS JSIO1 JSIO2 JSIO1 and JSIO2 are connectors for the RS 232C interface controlled by the serial parallel controller TL16C552A These are 9 pin D SUB male connectors D SU
17. 3 to 0 For information about ROM banks see Section 3 4 In ROM write with a 16 bit data bus the data byte arrangement may differ from the ROM writer format depending on the endianess for example when big endian mode is used for program code and the ROM writer supports little endian mode such a case write data with a ROM writer that has a function for swapping the low order 8 bits and high order 8 bits of 16 bit data Memo When the ROM emulator is used disable the ROM banks Otherwise the monitor program of the emulator may not operate normally 36 RTE VR4310 PC User s Manual Rev 1 02 9 APPENDIX A MULTI MONITOR This chapter describes how to make the settings required to establish a connection between the MULTI monitor stored in ROM and the MULTI debugger on the host PC It also provides notes on the use of the MULTI monitor 9 1 RTE for Win32 INSTALLATION When the board is used with the MULTI debugger communication software called RTE for Win32 must be installed in the host PC Refer to the RTE for Win32 Installation Manual supplied with this product for installation and test methods When installing the MULTI debugger refer to the manual provided with the debugger 9 2 BOARD SETTING This section describes the settings of the switches on the board 9 2 1 Switch Setting The RTE VR4310 PC board has DIP switches The switch layout is shown below JPOWER JUSR 7SEG LED DRAM SIMM x2
18. 6 A17 A18 19 GND GND RD WR RESET GND GND READY INT GND GND LBCLK GND JEXT Connector Signal Arrangement 30 RTE VR4310 PC User s Manual Rev 1 02 7 2 SIGNALS Signal name Function Remarks 45V Supply voltage of 5 V GND Ground A 1 19 Output Address bus signal A0 Output Byte low enable signal When this signal is low D 0 7 is enabled BHE Output Byte high enable signal When this signal is low D 8 15 is enabled D 0 15 Input Data bus signal used for CPU data bus buffering output RD Output Read cycle timing signal which becomes active only when the EXT BUS Space is accessed WR Output Write cycle timing signal which becomes active only when the EXT BUS Space is accessed Input Positive logic ready signal indicating the end of a cycle It is valid only for the EXT BUS space Itis pulled up with a 1 resistor on the board Input Active low interrupt request signal which is connected to the INT2 pin of the CPU via a buffer It is pulled up with a 1 kQ resistor on the board Output Active low system reset signal Output Bus clock signal fixed at 32 MHz EXT BUS Signals Notes 1 Toensure that the CPU recognizes READY READY must be held active until RD or WR is deactivated 2 This clock signal differs on other RTE series evaluation boards When compatibil
19. 9 36 9 APPENDIX A MULTI rc 37 9 1 RTE for Win32 37 9 25 BOARD SETTING cn 37 DATE Switch Setting 37 9 2 2 Connection between the Host and 38 9 35 MULTMMONITOR tet saine tad ter cutie dec 39 9 3 1 Monitor Work 2 20000000000 0 9 9 969 88 8 39 9 3 2 39 9 3 3 Interrupt for Forced 39 9 3 4 Stack Selling sc RR RREERE AER ERRARE REA AREE ERBRREEARRERRREEEERRRRRIIET 39 9 3 5 Special Instr ction a ea ai 39 9 4 RTE COMMAND S aia 39 941 HELP ita sin nim 40 9A E A E TN 40 9 435 40 9 44 40 9 4 5 SHOWTEB eDRDpobIbobresbien bebe frt 40 9 4 6 IOREAD iens mE REEL 40 94 7 aiii 40 RTE VR4310 PC User s Manual Rev 1 02 10 APPENDIX PARTNER
20. B9 generally used with the PC AT All signals at the connectors are at RS 232C level The pin arrangement and signal assignment are shown and listed below For connection signals connected to the host PC the table gives the wirings for both the D SUB9 pins and D SUB25 pins on the host PC These are general cross cable wirings 1234 5 6 7 8 9 JSIO1 and JSIO2 Pin Arrangement Connector pin number on the host PC D SUB9 D SUB25 JSIOx pin Signal name Input output DCD Input RxD RD Input TxD SD Output DTR DR Output GND DSR ER Input RTS RS Output CTS CS Input RI Input JSIO 1 and JSIO2 o o A N Memo the panel CHO is indicated for JSIO1 while CH1 is indicated for JSIO2 PARALLEL CONNECTOR JPRT The JPRT connector is a printer connector controlled by the serial parallel controller TL16C552A The connector is a 26 pin header pin connector so that a conversion cable is required to use the connector as a general printer connector The figure below shows the pin arrangement and pin number assignment of the connector JPRT Pin Arrangement RTE VR4310 PC User s Manual Rev 1 02 JPRT pin Signal name Input output Remarks 1 STB Output 10 kQ pull up resistor AUTO FD Output 10 kQ pull up resistor DO Output 10 kQ pull up resistor ERROR Input 10 kQ pull up resistor D1 Output 10 pull up resistor INIT Out
21. RAM SIMM size 4M bytes Standard 16M bytes Reserved 8M bytes 5 4 3 General Purpose I O Port SWLED The general purpose l O port exercises on off control on the 7 segment LED and reads the setting of the DIP switch SW4 on the board Logical address Description BC00 0000H 0 Input 1 OFF BC00 0000H 0 Turned on Output 1 Turned off The figure below shows the bit correspondence of the 7 segment LED A F B G D E q e DP Caution Data output to the 7 segment LED cannot be read 15 RTE VR4310 PC User s Manual Rev 1 02 5 4 4 5 4 5 Serial Parallel I O 5 0 1 LPT As the serial parallel I O the TL16C552A manufactured by Tl is used This device includes two serial controllers compatible with NS16550 and a parallel port compatible with the PC AT PS2 standard The table below indicates the assignment of each TL16C552A register Logical address Register Supplement BC01 0000H RBR THR DLL 0100H IER DLM 0200H IIR FCR 0300H LCR 0400H MCR 0500H LSR 0600H MSR 0700H SCR BC02 0000H RBR THR DLL 0100H IER DLM 0200H IIR FCR 0300H LCR 0400H MCR 0500H LSR 0600H MSR 0700H SCR BC03 0000H 0100H 0200H 0300H The frequency of the clock applied to the serial controller is 16 MHz For the function of each register refer to the manua
22. RTE VR4310 PC User s Manual Rev 1 02 Midas lab RTE VR4310 PC User s Manual Rev 1 02 REVISION HISTORY Date Explanation of revision July 4 1998 First edition preliminary September 4 1998 First edition April 10 1999 Riviced Section 5 2 INTERRUPT INT2 INT3 RTE VR4310 PC User s Manual Rev 1 02 CONTENTS T INTRODUCTION ci tii 1 1 1 NUMERIC 1 2 FEATURES AND FUNCTIONS recreare ese cts neat de evenness alada 2 3 BOARD 4 04 3 RESET SWITCH GN BST Fete Ii 3 3 2 POWER SUPPLY CONNECTOR 3 330 St ota 4 3 4 DIVMODE SWITCH 6 1 2 snnt nnns 4 3 5 ROM BANK SWITCH 5 3 4 3 6 GENERAL PURPOSE INPUT SWITCH 52 5 3 7 USER CONTROLLED PIN 05 8 5 3 8 CPU TEST CONNECTORS JC1 JC2 nnn aaa 5 3 9 SERIAL CONNECTORS JSIO1 5102 6 3 10 PARALLEL CONNECTOR 6 3 11 OSCILLATOR 5 7 3 12 DRAM SIMM 5 8 20204 212 0 1000001 000000000000000 7 3413 ROM SOCKE Ts ocu A JR E E RE 7 4 CONNECTION TO THE HOST 4
23. SHOWTLB command lists the contents of the TLB in the CPU IOREAD Format IOREAD BYTE SHORT LONG address The IOREAD command reads memory at the specified address according to the specified size and displays the data Select BYTE SHORT or LONG to specify 8 16 or 32 bits Use this command to access memory mapped l O lt Example gt IOREAD BYTE BC000100 000100 IOWRITE lt Format gt IOWRITE BYTE SHORT LONG data address The IOWRITE command writes the specified data to memory at the specified address according to the specified size Select BYTE SHORT or LONG to specify 8 16 or 32 bits Use this command to access memory mapped l O lt Example gt IOWRITE SHORT 30 0 00 000 40 RTE VR4310 PC User s Manual Rev 1 02 10 APPENDIX B PARTNER MONITOR This chapter describes how to make the settings required to establish a connection between the PARTNER monitor stored in ROM and the PARTNER debugger on the host PC It also provides notes on the use of the PARTNER monitor 10 1 BOARD SETTING This section describes the settings of the switches on the board 10 1 1 Switch Setting The RTE VR4310 PC board has DIP switches The switch layout is shown below JPOWER JUSR 7SEG LED LED H DRAM SIMM x2 SW RST JPRN JSIO2 160552
24. The access time of the ROM chip used here should be 150 ns or less The ROM has four banks that can be selected switching addresses to RTE VR4310 PC User s Manual Rev 1 02 allow for selection of endian and operation mode See Sections 3 4 and 9 2 1 for bank setting RTE VR4310 PC User s Manual Rev 1 02 4 CONNECTION TO THE HOST PC 4 1 1 Standalone Use of the Board RS 232C Connection The RTE VR4310 PC can be connected to the host PC according to the following procedure lt gt Get an RS 232C cable for connection with the host PC and an external power supply 5 V 4 A onhand Especially for the power supply watch for its voltage and connector polarity See Sections 3 9 and 3 2 for RS 232C cable connection and the power supply connector respectively 2 Connect the board to the host PC via an RS 232C cable using the JSIO1 CHO connector Also connect an external power supply to the JPOWER connector then check that the POWER LED on the board lights If the LED does not light turn off the power immediately and check the connection 3 Start the MULTI debugger on the host PC and make a connection via the RS 232C interface If an error occurs check that the serial cable and switch baud rate especially are set correctly Cautions 1 When the power is turned on the CPU and heat sink become very hot After the power is turned off these devices remain hot for a while Be careful not to touch them Place the b
25. ady About 8 us Notes 1 With an I O device the inactive period of the RD WR signal in successive accesses is predetermined So by hardware the local bus controller supports the I O access disable period of 7 LCLKs about 210 ns after an I O access not be inserted by software after an I O access 2 When the time over function is enabled See Section 5 4 6 MEMORY CONTROLLER REGISTER ACCESS Access to SRAM and DRAM memory controller registers is allowed using only a single cycle burst cycle is handled as a bus error in a read and is ignored in a write this space is the same as the SRAM access timing with one wait cycle See Section 6 1 Thus wait cycles need A The timing of access to 29 RTE VR4310 PC User s Manual Rev 1 02 7 EXT BUS SPECIFICATION The EXT BUS is used to expand memory and I O units The local bus on this board is connected to the JEXT connector 7 1 CONNECTOR SPECIFICATION The appearance and the pin arrangement of the JEXT connector are shown below 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 TI 0O00000000000000000000000000000 0O00000000000000000000000000000 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 JEXT Connector Pin Arrangement Signal name Signal name Signal Signal name 5V 5V GND GND DO D1 A8 A9 D2 D3 10 11 D4 D5 12 A13 D6 D7 A14 A15 5V 5V D8 D9 A1
26. ck cycles 0xB8000700 offset b lt 0 EDO HIT disable 0xBC040300 offset b lt Oxb4 Timer 2 mode 2 set at intervals of about 15 us 0xBC040200 offset b lt Ox1f Timer 2 low order count 0xBC040200 offset b lt 0x00 Timer 2 high order count Interrupt When using interrupts initialize the peripheral I O then assign the required interrupts with the interrupt mask register Moreover enable all of INT NMI Example of using timer interrupt 1 lt Disable processor interrupts gt Use 0 for offset in little endian mode Use 7 for offset in big endian mode 0xBC040300 offset b lt 0x74 Timer 1 mode 2 set at intervals of 10 ms 0xBC040200 offset b lt 0x20 Timer 1 low order count 0xBC040200 offset b lt Ox4e Timer 1 high order count 0xBC070100 offset b lt 0x10 Enable INT1M timer 1 0xBC070200 offset b lt 0x10 Clear INTR timer 1 interrupt 0xBC070300 offset b lt 0x02 Enable INT Enable processor interrupts gt Memo Before NMI can be used to control break the connected ROM emulator NMI must be enabled with the monitor program of the emulator 35 RTE VR4310 PC User s Manual Rev 1 02 8 2 3 ROM Data Allocation When ROM data is written the correspondence between the ROM address bank and data bus must be considered With the 272 048 type 128K x 16 bits a bank occurs for every 64K bytes with the switch as standard When using no bank set SW3 2 and SW3
27. e TARGET window is opened The RTE commands can be issued in this window The following table lists the RTE commands Command Description HELP Displays help messages INIT Initializes VER Displays the version number CACHEFLUSH Flushes the cache SHOWTLB Displays the contents of the TLB IOREAD Reads data with a size specified IOWRITE Writes data with a size specified RTE Commands Some commands require parameters All numeric parameters such as addresses and data are assumed to be hexadecimal numbers following numeric representations are invalid 0x1234 1234H 1234 39 RTE VR4310 PC User s Manual Rev 1 02 9 4 1 9 4 2 9 4 3 9 4 4 9 4 5 9 4 6 9 4 7 HELP Format HELP command name The HELP command displays a list of RTE commands and their formats A question mark can also be used in place of the character string HELP If no command name is specified in the parameter part the HELP command lists all usable commands Example HELP INIT Displays help messages for the INIT command INIT Format INIT The INIT command Initializes the RTE environment Usually this command should not be used VER Format VER The VER command displays the version number of the current RTE environment CACHEFLUSH Format CACHEFLUSH The CACHEFLUSH command flushes the contents of the cache in the CPU SHOWTLB Format SHOWTLB The
28. idth cycle is generated by the local bus controller from a clock fixed at 32 MHz that is not synchronous with the CPU The local bus allows single access only A burst cycle is handled as a bus error upon a read but is ignored upon a write The control circuit of the CPU issues a request to the local bus controller and bus arbitration is performed based on the acknowledgement signal returned from the controller In a read cycle on the local bus a request is issued to the local bus controller and an acknowledgement signal is returned to the controller upon data read completion secu LU UU UUUL UUUUUUUUUUUUULUL sysap YA svsanc X _ READ JH PVALID PMASTER EVALID LOCAL ADDR LOCAL DATA LOCALREQ LOCALACK 0 1 2 3 4 5 6 7 8 9110111 12 13 14 15 16 17 18 19 Read Single Local Read Cycle The states are explained below in the order of clock cycle numbers 0 3 4and up 11 13 17 Access to the local bus starts After checking that the acknowledgement signal LOCALACK is inactive an access request LOCALREQ is issued to the local bus The local bus controller recognizes the occurrence of a request then latches the address and starts a read cycle Upon the completion of a read from the local bus an acknowledgement signal is returned The request is released by synchronizing the ack
29. ion 5 4 This space is accessed as a non cache space 5 3 7 ROM Space 1F00 0000H to 1FFF FFFFH The ROM installed on the board has a real space of 256K bytes 272048 the remaining area is the image space The MULTI monitor is built into the installed ROM This space can be accessed only as a non cache space 5 4 WO DETAILS The devices mapped onto the memory space include the memory access controller DUART LPT timer interrupt controller and PCI I O for communication controller The figure below shows the board I O map Virtual address 40x07 0000 77 reserved 0000 0000 I d 40x05 0000 ps TIMER v Fr 40x04 0000 PRT 0 020000 SCC1__ 40x02 0000 EN SCCO 49x01 0000 0 00 0000 SWLED 0000 0x00 07FF 0xB800 0000 0x00 0400 0 000 0000 _ 0 00 0000 These l O devices assume access the kernel noncache space so that the description below uses logical addresses Memo The data bus connected to an I O device is connected to D 7 0 unless otherwise specified This means that endianess needs to be considered when performing byte access For byte access in big endian mode 7 is added to the byte offset because the bus internally handles RTE VR4310 PC User s Manual Rev 1 02 5 4 1 5 4 2 data as 64 bits SRAM Controller SRAMC The SWAIT register exercises wait control on the SRAM space Using this regis
30. ity is important this clock signal should not be used for circuit design 3 Note that the address data bus correspondence varies according to the VR4310 endian mode VR4310 ADDR DATA D31 24 023 16 D15 08 D07 00 EXT BUS ADDR DATA A19 A1 BHE AO 19 1 0 0 D31 24 D23 16 A 0 D15 08 D08 00 A 2 D15 08 D08 00 A 2 D31 24 D23 16 BIG ENDIAN LITTLE ENDIAN 31 RTE VR4310 PC 7 3 EXT BUS TIMING The timing of the EXT BUS is shown below A 0 19 BHE D O 15 READY Read cycle User s Manual Rev 1 02 A 0 19 BHE D O 15 T16 gt lt READY Write cycle EXT BUS Bus Cycle Description RD address setup time RD address hold up time RD cycle time RD cycle interval RD data setup time RD data hold time RD READY WAIT setup time RD READY setup time RD READY hold time WR address setup time WR address hold time WR cycle time WR cycle interval WR data delay time WR data hold time WR READY WAIT setup time WR READY setup time WR READY hold time EXT BUS AC Specifications 32 RTE VR4310 PC User s Manual Rev 1 02 8 SOFTWARE 8 1 8 1 1 INTERRUPT PROGRAMMING This section describes how a user program can handle interrupts by using the monitor Interrupt Library With the VR4310 a set of general e
31. l provided with the TL16C552A Timers The uPD71054 produced by NEC is installed as a timer The uPD71054 is compatible with the 18254 produced by Intel It has three timer counters These timers are used for various types of control Each register of the uPD71054 is assigned as listed below Logical address Register Remarks BC04 0000H PCNTO Timer 0 0100H PCNT1 Timer 1 0200H PCNT2 Timer 2 0300H PCNTL Control For the function of each register refer to the manual provided with the uPD71054 18254 timers are used as indicated below Application Timer interrupt 0 Used by the monitor Timer interrupt 1 Usable by the user DRAM refresh 16 RTE VR4310 PC User s Manual Rev 1 02 5 4 6 Interrupt Controller PIC The PIC mainly exercises interrupt related control The table below indicates the assignment of registers Data bus D4 D3 BC07 0000H INTOM 04 IMOS 0100 14 0200 INTR IR4 IR3 0300H INTEN 0 TOVEN Logical address Register The INTOM and INT1M registers mask interrupts applied to INTO and INT1 respectively When the IMOx or IM1x bit is set to 1 the interrupt is enabled When multiple bits are selected each OR value activates an interrupt The INTR register is an interrupt status register for which 1 is read whenever there is an interrupt request This does not depend on the sta
32. nowledgement signal for two clock cycles after which the data is latched and held then EVALID is returned after two clock cycles The local bus controller recognizes the release of the request then deactivates the acknowledgement signal 25 RTE VR4310 PC User s Manual Rev 1 02 A write to the local bus is performed similarly according to request acknowledgement arbitration However an acknowledgement signal returned from the local bus controller is handled as a write permission and data is written in an acknowledge cycle after the request is released At this time the CPU can execute a second cycle other than a local bus cycle 0 1 2 3 4 5 6 7 8 9110 11 12 13 14 15 1 6 17 18 19 svsek UUU JUL UU UUL svsab JA 1 SYSCMD Write PVALID LOCAL DATA DATA WR LOCALREQ LOCALACK Write Single Local Write Cycle DataRate Dxx The states are explained below in the order of clock cycle numbers 0 1 A write access to the local bus starts 2 After checking that the acknowledgement signal LOCALACK is inactive an access request LOCALREQ is issued to the local bus 5 The local bus controller recognizes the occurrence of a request then latches the address and returns an acknowledgement signal 7 A write cycle is executed by activating EOK for the CPU and synchronizing the acknowledgement signal for two clock cycle
33. oard on insulating surface If you place the board on a conductive surface while it is turned on the board may fail When the board is not inserted into the PCI slot you must install the supplied PCI bus terminator board Insertion into the PCI Slot PCI Bus Connection Insert the board into the PCI slot of the host PC by following the procedure below 1 Open the host PC cabinet then insert the board into a PCI slot Ensure that the board is inserted securely then fasten the board inplace with the fixing screw 2 Turn on the power to the host PC and check that the POWER LED on the board lights If the LED does not light turn off the power to the host PC immediately and make a check Also check whether the host PC starts normally 3 Start the debugger the host PC and make a connection via the PCI bus If an error occurs check that the board and software are installed correctly RTE VR4310 PC User s Manual Rev 1 02 5 5 1 5 2 HARDWARE REFERENCES This chapter describes the hardware functions of the RTE VR4310 PC RESET The factors listed below trigger a reset These factors cold reset the CPU They also system reset the board control circuit e Power on reset Occurs when the power to the board is switched on Reset switch Generated by the reset switch SW RST on the board e Reset from the host Sent via the PCI bus controller at the request of the host PC e JUSR 1 Input at pin 1 RST
34. purchase is stored Even when neither of the debuggers is purchased together with the RTE VR4310 PC they can be purchased at any time subsequently NUMERIC NOTATION This manual represents numbers according to the notation described in the following table Hexadecimal and binary numbers are hyphenated at every four digits if they are difficult to read because of many digits being in each number Letter x is used to represent an arbitrary numeral in a number like 1FxxH Number Notation rule Example Decimal Only numerals are indicated 10 represents number 10 in decimal number Hexadecimal A number is suffixed with letter H 10H represents number 16 in decimal number Binary number A number is suffixed with letter 10B represents number 2 in decimal Number Notation Rules MULTI is a trademark of Green Hills Software Inc in the US RTE VR4310 PC 2 FEATURES AND FUNCTIONS User s Manual Rev 1 02 The overview of each function block of the RTE VR4310 PC is shown below OSC 66 6 2 E PROM SW sw DC 52 Scis CPU board 32 bit bus CPU CONE SYSAD bus SYSAD WF VF Hi SRAM 64 bit bus Memory bus 16 bit bus Local bus EXT BUS Al 7SEG LED DIP SW Block Diagram Features e ROM 256 Kbytes 128K x 16 bits x 1 SRAM 512 Kbytes 64K x 16 bits x 4 DRAM 8 16 or 32 Mbytes standard of 8 Mbytes installed in
35. put 10 kQ pull up resistor D2 Output 10 kQ pull up resistor SELECT Output 10 kQ pull up resistor IN O JA A ow D3 Output 10 kQ pull up resistor D4 Output 10 kQ pull up resistor D5 Output 10 kQ pull up resistor D6 Output 10 kQ pull up resistor D7 Output 10 kQ pull up resistor Input 10 kQ pull up resistor Input 10 kQ pull up resistor Input 10 kQ pull up resistor Input 10 kQ pull up resistor T 26 Not used 10 12 14 16 18 20 22 24 JPRT Connector Signal Table 3 11 OSCILLATOR SOCKET OSC1 OSC1 is a socket for an oscillator to generate clock pulses supplied to the CPU socket is factory equipped with a 66 6 MHz oscillator Caution When you have to cut an oscillator pin for convenience be careful not to cut it too short or otherwise the frame housing of the oscillator may touch a tine in the socket resulting in a short circuit occurring 3 12 DRAM SIMM SOCKETS The RTE VR4310 PC has DRAM SIMM sockets used to install 4 Mbytes standard of SIMM Each socket can hold a 72 pin 4 8 or 16 Mbyte SIMM known as a module for DOS V machines So it is easy to expand the capacity of DRAM The capacity of installed SIMMs can be detected using an l O port See Section 5 4 2 3 13 ROM SOCKET The RTE VR4310 PC has ROM sockets Of these sockets one is used to hold a 40 pin ROM chip to provide standard 256 Kbytes 128K x 16 bits
36. r noncache space DRAM Space 0800 0000H to OFFF FFFFH x800 0000H xFFF FFFFH The DRAM space is provided by a 72 pin DRAM SIMM installed on the board A4M byte SIMM is installed as standard However the memory size can be expanded by replacing this with an 8M byte or 16M byte SIMM an area other than the real space of DRAM SIMM x 2 installed it is used as an image area Set the DRAM access timing with the DRAM controller DRAMC See Section 5 4 2 This space can be accessed as either a cache or non cache space MEM CNT Space 1000 0000H to 17FF FFFFH In this space those registers that are used to exercise control on SRAM and DRAM memory access are mapped For details see Section 5 4 1 and Section 5 4 2 This space be accessed as non cache space RTE VR4310 PC User s Manual Rev 1 02 5 3 4 Used 1800 0000H to 19FF FFFFH When this space is accessed the bus cycle is forcibly terminated by the time over ready signal to generate a time over interrupt provided the time over function is supported 5 3 5 EXT BUS Space 1A00 0000H to 1BFF FFFFH This space is used for the EXT BUS external extension bus and includes a 1M byte real space the other area is an image space This space can be accessed as a non cache space 5 3 6 Space 1C00 0000H to 1EFF FFFFH This space is a memory mapped space where devices for controlling each function on the board are mapped For details of I O mapping see Sect
37. s 12 13 After write data has been written to the local bus the request is deactivated 14 15 The local bus controller recognizes the release of the request then deactivates the acknowledgement signal and writes data 26 RTE VR4310 PC User s Manual Rev 1 02 Upon single access from the CPU the local bus controller accesses the local bus The width of data access from the CPU is 64 bits maximum and the local bus is 16 bits wide So bus sizing is performed and up to four bus cycles are generated The figure below shows the timing chart of a read cycle LCLK 32 MHz LOCALREQ LOCALACK CPU DATA LOCAL ADDR LOCAL DATA LW R LDSTB LRDY Read Local Bus Read Cycle The states are explained below in the order of clock cycle numbers 0 1 Aread request to the local bus starts 2 local bus controller latches the address and read status LW R 4 Access is started by activating the data strobe LDSTB two LCLKs after the address is latched 6 7 When the local bus ready signal LRDY is returned the data strobe is deactivated and the CPU data is latched 8 14 If the CPU data size is greater than 16 bits the read cycle is repeated by switching to the next address 15 Once all the read cycles have been completed and the CPU data has been determined an acknowledgement signal is returned 27 RTE VR4310 PC User s Manual Rev 1 02
38. speed cycle where the DRAM read cycle does not overlap a refresh cycle or RAS precharge of the previous DRAM access 0 11 2 3 4 5 6 7 8 9110111 12 13 14 15 16 17 18 19 20 SYSAD SYSCMD ar Pvaup L L DA ex Alf i liit pmaster L LLL LL DLL To EVALID DRAM ADDR DRAM DATA DRAM RAS DRAM CAS DRAM WE Read burst 4 words DRAM Read Cycle RCAS 1 MRAS 4 PRAS 3 EDOEN 0 The states are explained below in the order of clock cycle numbers 0 EOK is activated 1 A DRAM read cycle starts 2 3 RAS is activated as soon as the row address is determined 4 5 Upon switching to a column address CAS is activated two clock cycles after RAS 7 The first read data is determined At this time CAS is held until cycle DRAMC MRAS 1 8 9 Datais latched and held then EVALID is returned after two clock cycles 10 18 The cycle is repeated until the last data EOD is reached When HITEN 1 RAS remains active 21 RTE VR4310 PC User s Manual Rev 1 02 When EDOEN 1 a CAS precharge cycle occurs with the determination of the read data delayed by one clock cycle In this case the values of DRAMC MRAS and DRAMC RCAS may be decremented by 1 depending on the SYSCLK width With EDO DRAM data is held until RAS is deactivated so control is exercised to turn off the data output in the
39. t occurs access based on a normal RAS CAS cycle is performed after RAS precharge resulting in an increased overhead 0123 4 567 8 9 10 11 12 13 14 15 16 17 18 19 svscuk Lun uuu uit sysap _ Kak Kak XV DRAM ADDR X A DRAM RAS RCAS DRAM CAS DRAM RAS DRAM CAS DRAM Page Hit UnHit Access Cycle HITEN 1 The states are explained below in the order of clock cycle numbers 0 4 Normal DRAM access cycle 5 The next DRAM write access starts 6 Acomparison is made with the previous row address 7 8 lf a match is found read CAS is activated starting with the next cycle If a mismatch is found RAS is deactivated after which RAS precharge is performed 9 lf a match is found read CAS enables page mode access starting with the first cycle 14 If a mismatch is found read CAS enables a normal RAS access cycle When the DRAM is refreshed a CAS before an RAS refresh cycle is performed at intervals of about 15 us according to the setting of timer 2 SYSCLK MRAS PRAS PRAS MRAS lt gt lt gt lt gt DRAM RAS DRAM CAS lt 15 DRAM Refresh Cycle MRAS 4 PRAS 3 24 RTE VR4310 PC 6 3 User s Manual Rev 1 02 LOCAL BUS ACCESS The local bus has a 16 bit data w
40. te of masking Toclear an edge interrupt request the corresponding bit of this register must be set to 1 The table below indicates the interrupt source assigned to each bit of IMO O 7 IM1 0 7 and IR O 7 IMO IM1 IR Interrupt source Request level Timer 0 mode 2 Edge rising Serial 0 Level low Host PC PCI communication Level low Timer 1 mode 2 Edge rising Serial 1 Level low Time over Level low Parallel printer Level low Not used fixed to 0 The INTEN register enables or disables each type of interrupt NMIEN Sets a mask for the non maskable interrupt NMI By masking with this bit NMI can be disabled by hardware At this time the NMI pin is high Sets a mask Reset value Does not set a mask INTEN Sets a mask for the external interrupts INTO 3 used on the board By masking with this bit INTO 3 can be disabled by hardware At this time the INTx pin is high INTO to INT5 Sets a mask Reset value Sets no mask 17 RTE VR4310 PC User s Manual Rev 1 02 TOVEN Sets whether to use the timer over function The time over function is applied to local bus access only If a bus cycle lasts for about 8us the cycle is terminated forcibly Time over Does not use the time over function Reset value Uses the time over function 5 4 7 PCI Controller For PCI bus communication
41. ter O to 3 wait cycles can be set in a read cycle The table below indicates the register assignment Data bus D2 D1 DO B000 0000H SRAMC SWAIT 0 SWAIT1 SWAITO Logical address Register SWAIT 1 0 Sets the number of wait cycles for SRAM read Number of SRAM read wait cycles 0 1 2 3 Reset value Memo Zero can be set as the number of SRAM read wait cycles when the external bus clock SysClock speed is 40 MHz or less with the clock width being 25 ns or more This can be found from the following formula Address delay SRAM access time data setup 5 ns 17 ns 3 ns 25 ns DRAM Controller DRAMC DRAMC exercises DRAM access control DRAMC sets an RAS CAS width as well as the operation modes The table below indicates the register assignment Data bus D2 D1 B000 0400H DRAMC RCAS 0 0 RCAS1 0500H DRAMC MRAS 0 MRAS1 0600H DRAMC PRAS 0 PRAS1 0700H DRAMC DMODE EDOEN Logical address Register RCAS 1 0 Sets the number of CAS clock cycles for DRAM read The number of clock cycles used is the specified value 0 to 3 plus 1 Number of CAS read clock cycles 1 SYSCLK 2 SYSCLKs 3 SYSCLKs 4 SYSCLKs Reset value Memo The number of CAS precharge clock cycles is fixed to one clock cycle 13 RTE VR4310 PC User s Manual Rev 1 02 MRAS 2 0 Sets the number of DRAM RAS access clock cycles The number of clock c
42. ting 0 Does not use the profiler No timer interrupt 1 200 Hz 5 0 ms 2 100 Hz 10 0 ms 3 60 Hz 16 67 ms The MULTI monitor does not use SW4 5 to SW4 8 must be set to OFF at all times Connection between the Host PC and Board Make a connection with the host PC via the serial or PCI bus as explained in Chapter 4 38 RTE VR4310 PC User s Manual Rev 1 02 9 3 9 3 1 9 3 2 9 3 3 9 3 4 9 3 5 9 4 MULTI MONITOR Monitor Work RAM The monitor uses reserves the SRAM area between the start address and 10000H 64 KB as work RAM In other words user programs are not allowed to use logical addresses 8000 0000H to 8000 FFFFH and A000 0000H to AO00 FFFFH This also applies to these image areas Interrupt When using an interrupt with a user program see Section 8 1 Interrupt for Forced Break The monitor uses the INTO interrupt for a forced break or interrupt for communication Stack Setting The initial value of the stack pointer is set to 8007 FFFCH highest SRAM address by the monitor This value can be changed in the MULTI environment using the INIT SP command Special Instruction The monitor uses the following instruction for single step breakpoint and system call functions BREAK instruction Breakpoint This instruction cannot be used with user programs RTE COMMANDS When the monitor and MIDAS server RTESERV are connected with the MULTI debugger th
43. two 72 pin SIMM sockets e RS 232C port 9 pin D SUB connector e Connection pins for ROM in circuit debugger 2 channels RTE VR4310 PC User s Manual Rev 1 02 3 BOARD CONFIGURATION The physical layout of the major components on the RTE VR4310 PC board is shown below This chapter explains each component JPOWER 7SEG LED DRAM SIMM x2 SW RST JPRN JSIO2 160552 PCI9060ES VR4310 CPU board JC1 PLD A PLI JC2 VR4310 Board Top View 3 1 RESET SWITCH SW RST SW RST is a reset switch Pressing this switch causes the entire RTE VR4310 PC board to be reset 3 2 POWER SUPPLY CONNECTOR JPOWER This is a DC jack used to receive power from an external supply The external power to be supplied to JPOWER should be one rated as listed below Voltage 5V Current Maximum of 3 5 A Mating connector Type A 5 5 mm in diameter Polarity Caution When attaching an external power supply to the board be careful about its connector polarity RTE VR4310 PC User s Manual Rev 1 02 3 3 3 4 3 5 LED LAMPS
44. until the end of the data EOD is reached RTE VR4310 PC User s Manual Rev 1 02 An SRAM write cycle follows the output data rate of the CPU For SRAM a cycle is started by returning EOK one clock cycle after address determination 0123 4 567 8 9 10 11 12 13 14 15 16 17 18 19 SYSAD SYSCMD PVALID EOK SRAM ADDR SRAM DATA SRAM CS Py AA sramwe LLY ALY ALLA LS Write burst 4 words SRAM Write Cycle DataRate DxxDxxDxxDxx The states are explained below in the order of clock cycle numbers 0 1 Usually EOK is inactive 2 3 An SRAM write cycle is determined 4 First data output This data is latched and held then the EOK is deactivated and SRAM WE is activated starting from the next cycle 5 6 SRAM write cycle Dxx data rate is fixed so that the write pulse width is 2 clock cycles WE is deactivated before the next data is latched then the SRAM address is changed in the next cycle Sequential address 7 15 The write cycle is repeated 16 Inthe cycle after the last data EOD is written RDRDY is activated 20 RTE VR4310 PC User s Manual Rev 1 02 6 2 DRAM ACCESS For the DRAM the RAS CAS width can be controlled according to the setting of the DRAM controller See Section 5 4 2 The figure below shows a DRAM read cycle when EDOEN 0 FPM DRAM The figure below shows the highest
45. ve error code odd number void SetiPnBit int IPn This function enables an interrupt specified by argument IPn The corresponding bit of the status register is set to 1 void ReslPnBit int IPn This function disables an interrupt specified by argument IPn The corresponding bit of the status register is set to 0 void ei void This function enables all interrupts void di void This function disables all interrupts other than NMI 33 RTE VR4310 PC Interrupt Routine User s Manual Rev 1 02 A user coded interrupt handling routine assumes the use of a C function of type int without the _interrupt qualifier For correct debugging of an interrupt handling routine disable the corresponding interrupt at the start of the interrupt handling routine and enable the interrupt before the end of the interrupt handling routine Once handling has been completed 0 is returned When control is returned to the monitor a value of other than 0 is returned Sample Program A sample program for interrupt handling using the user control pin IRQ INT 3 is provided below include intvect h int main void can not Break amp Step di InitIrqVect SetIrqVect VECT_IP4 int IrqJusr SetIPnBit SR_IP4 can not Break amp Step di ResIPnBit SR IP4 SetIrqVect VECT_IP4 0 TermIrqVect irqJusr int IrgHusr struct _irq_ stack istack
46. xception interrupt vectors is allocated The monitor also uses interrupts So the vectors are shared For this reason an interrupt library attached sample programs Intvect c IntHdr s mip is provided The library hooks vectors and exercises table management for each exception to execute the exception handling routine The eight library functions are described below int InitlrqVect void This function hooks an interrupt vector and initializes the table This function returns O upon normal termination If an error occurs this function returns a negative error code int TermirqVect void This function returns an interrupt vector to the original state This function returns 0 upon normal termination If an error occurs this function returns a negative error code int SetlrqVect int no int func This function registers function func by casting to int type in the interrupt handling table specified by the argument no For the argument no specify a macro defined in INT xxx format in the intvect h file If O is specified in func the previously set handling routine can be disabled This function returns O upon normal termination If an error occurs this function returns a negative error code int GetlrqVect int no This function returns a function address registered in the interrupt handling table specified by the argument no When 0 is returned it means that no function is registered If an error occurs this function returns a negati
47. ycles used is the specified value 0 to 7 plus 1 Number of RAS access clock cycles 1 SYSCLK 2 SYSCLKs 3 SYSCLKs 4 SYSCLKs 5 SYSCLKs 6 SYSCLKs 7 SYSCLKs 8 SYSCLKs Reset value 2 0 0 0 0 1 1 1 1 ojl oil oi iojo PRAS 2 0 Sets the number of DRAM RAS precharge clock cycles The number of clock cycles used is the specified value 0 to 7 plus 1 Number of RAS precharge clock cycles 1 SYSCLK 2 SYSCLKs 3 SYSCLKs 4 SYSCLKs 5 SYSCLKs 6 SYSCLKs 7 SYSCLKs 8 SYSCLKs Reset value Aaa Mm HITEN Sets whether to use the page hit access function of the DRAM controller If HITEN 1 high speed page access is performed when RAS is held after DRAM access completion and a match is found with the load address for the next DRAM access DRAM page address However the RAS cycle hold is released by a refresh request If there is no hit normal access is performed after a precharge cycle DRAM page hit Reset value EDOEN Sets whether the type of DRAM is FPM or EDO When EDOEN 1 the data ready signal at burst read time represents the CAS precharge period So the CAS width can be reduced by one clock cycle DRAM type Reset value RTE VR4310 PC User s Manual Rev 1 02 PD 1 2 Allows the type pins PD 1 2 of DRAM SIMM to be read read only D
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