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X Series User Manual - National Instruments

1. Setting e Battery devices Differential Signal Source DAQ Device Signal Source DAQ Device Al Al or Al Al eee TRE AI GND Non Referenced Signal Source DAQ Device Signal Source DAQ Device Single Ended NRSE Al gt Al SENSE Al SENSE ae TT AI GND Referenced Single Ended Signal Source DAQ Device RSE Al NOT RECOMMENDED Signal Source DAQ Device Al GND Ground loop potential Va Vg are added to measured signal Refer to the Analog Input Ground Reference Settings section for descriptions of the RSE NRSE and DIFF modes and software considerations Refer to the Connecting Ground Referenced Signal Sources section for more information National Instruments 4 11 Chapter 4 Analog Input Connecting Floating Signal Sources What Are Floating Signal Sources A floating signal source is not connected to the building ground system but has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolators and isolation amplifiers An instrument or device that has an isolated output is a floating signal source When to Use Differential Connections with Floating Signal Sources Use DIFF input connections
2. i 1 i 1 r 1 i 1 r 1 i i i i 1 i i i i i Source i fi 1 i IHL LHL 1 HL IHL Buffer 4 2 42 42 42 4 4 4 4 4 4 6 2 6 2 2 2 Sample Clocked Buffered Pulse Measurement A sample clocked buffered pulse measurement is similar to single pulse measurement but a buffered pulse measurement takes measurements over multiple pulses correlated to a sample clock The counter performs a pulse measurement on the Gate On each sample clock edge the counter stores the high and low ticks in the FIFO of the last pulse to complete A DMA controller transfers the stored values to host memory Figure 7 10 shows an example of a sample clocked buffered pulse measurement Figure 7 10 Sample Clocked Buffered Pulse Measurement Counter s i Armed 1 i Gate ES eee I i i Source Sample Clock Buffer EE AEE E ER EPS SS oe N D w 4 E VNT N m Hardware Timed Single Point Pulse Measurement A hardware timed single point HWTSP pulse measurement has the same behavior as a sample clocked buffered pulse measurement A Note Ifa pulse doe
3. fx fx Gate 1 2 3 es N tk Source fk 4 7 N Single Period Period of fx Measurement fk fl Frequency of fx N High Frequency with Two Counters For high frequency measurements with two counters you measure one pulse of a known width using your signal and derive the frequency of your signal from the result Note Counter 0 is always paired with Counter 1 Counter 2 is always paired with Counter 3 In this method you route a pulse of known duration 7 to the Gate of a counter You can generate the pulse using a second counter You can also generate the pulse externally and connect it to a PFI or RTSI terminal You only need to use one counter if you generate the pulse externally Route the signal to measure fx to the Source of the counter Configure the counter for a single pulse width measurement If you measure the width of pulse 7 to be N periods of fx the frequency of fx is N T 7 12 ni com X Series User Manual Figure 7 13 illustrates this method Another option is to measure the width of a known period instead of a known pulse Figure 7 13 High Frequency with Two Counters lt _ Width of Pulse T gt Pulse Pulse Gate 1 2 N fx Source fx 4 4 Pulse Width Width of N N Measurement Pulse aoe N Frequency of fx
4. When CI Freq EnableAveraging is set to false the frequency measurement returns the frequency of the pulse just before the sample clock This single measurement is a single frequency measurement and is not an average between clocks Figure 7 16 Sample Clocked Buffered Frequency Measurement Non Averaging Counter Armed e a it Gate UU Source UU Sample Clock ho Latched 6 Values SG 6 4 6 With sample clocked frequency measurements ensure that the frequency to measure is twice as fast as the sample clock to prevent a measurement overflow National Instruments 7 15 Chapter 7 Counters Hardware Timed Single Point Frequency Measurement Hardware timed single point HWTSP frequency measurements can either be a single frequency measurement or an average between sample clocks Use CI Freq EnableAveraging to set the behavior For hardware timed single point the default is False Refer to the Sample Clocked Buffered Frequency Measurement section for more information Figure 7 17 Hardware Timed Single Point Frequency Measurement Counter Armed gt lt gt i see UUUUUUUUUUUUUULUUU ULLAL oo i Latched Value 6 4 6
5. Counter Timer Signal Default Pin Number Name CTR 0 B 85 PFI 10 CTR 1 SRC 76 PFI 3 CTR 1 GATE 77 PFI 4 CTR 1 AUX 87 PFI 11 CTR 1 OUT 91 PFI 13 CTRIA 76 PFI 3 CTR1Z 77 PFI 4 CTR1B 87 PFI 11 CTR 2 SRC 73 PFI 0 CTR 2 GATE 74 PFI 1 CTR 2 AUX 75 PFI 2 CTR 2 OUT 93 PFI 14 CTR2A 73 PFI 0 CTR2Z 74 PFI 1 CTR2B 75 PFI 2 CTR 3 SRC 78 PFI 5 CTR 3 GATE 79 PFI 6 CTR 3 AUX 80 PFI 7 CTR 3 OUT 95 PFI 15 CTR3A 78 PFI 5 CTR3 Z 79 PFI 6 CTR3B 80 PFI 7 FREQ OUT 93 PFI 14 You can use these defaults or select other sources and destinations for the counter timer signals in NI DAQmx Refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help for more information about how to connect your signals for common counter 7 44 ni com X Series User Manual measurements and generations X Series default PFI lines for counter functions are listed in X Series Physical Channels in the NI DAQmx Help or the LabVIEW Help Counter Triggering Counters support three different triggering actions Arm Start Trigger To begin any counter input or output function you must first enable or arm the counter Software can arm a counter or configure counters to be armed on a hardware signal Software calls this hardware signal the Arm Start Trigger Internally software routes the Arm Start Trigger to the Counter n HW Arm input of the counter For counter outp
6. Al Convert Clock Al Pause Trigger Halt Used on Internal Clock Al External Sample Clock Al Sample Clock LJ L b s OE CLE Al Convert Clock Al Pause Trigger Free Running Used on External Clock Using a Digital Source To use AI Pause Trigger specify a source and a polarity The source can be any of the following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt e Counter n Internal Output e Counter n Gate e AO Pause Trigger ao PauseTrigger e DO Pause Trigger do PauseTrigger e DI Pause Trigger di PauseTrigger The source can also be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source When you use an analog trigger source the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high or vice versa 4 34 ni com X Series User Manual Routing Al Pause Trigger Signal to an Output Terminal You can route AI Pause Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt PXI_STAR or PXIe DSTARC terminal Note Pause triggers are only sensitive to the level of the source not the edge Getting Started with Al Appl
7. A 12 Figure A 9 NI PCIe 6351 and NI PCle PXIe 6361 Pinout A 14 Figure A 10 NIUSB 6351 6361 Screw Terminal Pinout 0 0 eee cesses eeeeeneeeeeee A 15 Figure A 11 NI USB 6361 Mass Termination Pinout cccccceeseesseeeeeceeeeeeeeeeeees A 16 Figure A 12 NI USB 6361 BNC Pinout A 17 Figure A 13 NI PCIe 6353 and NI PCIe PXIe 6363 Pinout 0 cece seeeeeeeeeee A 19 Figure A 14 NI USB 6363 Mass Termination Pinout Figure A 15 NI USB 6353 6363 Screw Terminal Pinout Figure A 16 NI USB 6353 6363 BNC Pinout eee of Figure A 17 NI PXIe 6356 6366 Pinout Figure A 18 NI USB 6366 Mass Termination Pinout Figure A 19 NI USB 6356 6366 Screw Terminal Pinout Figure A 20 NIUSB 6356 6366 BNC Pinout Figure A 21 NI PXTe 6358 6368 Pinout Figure A 22 NI PXIe 6365 Connector 2 Pinout National Instruments xiii Contents Figure A 23 NI PXIe 6365 Connector 0 and Connector 1 Pinout eee Figure A 24 NI PXIe 6375 Connector 2 and Connector 3 Pinout Figure A 25 NI PXIe 6375 Connector 0 and Connector 1 Pinout eee xiv ni com Getting Started The X Series User Manual contains information about using the National Instruments X Series data acquisition DAQ devices with NI DAQmx
8. Hardware Timed Single Point Pulse Width Measurement A hardware timed single point HWTSP pulse width measurement has the same behavior as a sample clocked buffered pulse width measurement Note Ifa pulse does not occur between sample clocks an overrun error occurs Note NI USB 634x 635x 636x Devices USB X Series devices do not support hardware timed single point HWTSP operations For information about connecting counter signals refer to the Default Counter Timer Pinouts section National Instruments 7 7 Chapter 7 Counters Pulse Measurement In pulse measurements the counter measures the high and low time of a pulse on its Gate input signal after the counter is armed A pulse is defined in terms of its high and low time high and low ticks or frequency and duty cycle which is similar to the pulse width measurement except that the inactive pulse is measured as well You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between two edges of the Gate signal You can calculate the high and low time of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Refer to the following sections for more information about X Series pulse measurement options Single Pulse Measurement Implicit Buffer
9. Counter Timer Signal Default Connector 0 Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTRIA 42 PFI 3 CTR1Z 41 PFI 4 7 42 ni com X Series User Manual Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Connector 0 Pin Number Name CTR 1 B 46 PFI 11 CTR 2 SRC 11 PFI 0 CTR 2 GATE 10 PFI 1 CTR 2 AUX 43 PFI 2 CTR 2 OUT 1 PFI 14 CTR2A 11 PFI 0 CTR2Z 10 PFI 1 CTR2B 43 PFI 2 CTR 3 SRC 6 PFI 5 CTR 3 GATE 5 PFI 6 CTR 3 AUX 38 PFI 7 CTR 3 OUT 39 PFI 15 CTR3A 6 PFI 5 CTR3Z 5 PFI6 CTR 3B 38 PFI 7 FREQ OUT 1 PFI 14 Table 7 10 X Series USB Screw Terminal Device Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 81 PFI 8 CTR 0 GATE 83 PFI 9 CTR 0 AUX 85 PFI 10 CTR 0 OUT 89 PFI 12 CTR 0 A 81 PFI 8 CTROZ 83 PFI 9 National Instruments 7 43 Chapter 7 Counters Table 7 10 X Series USB Screw Terminal Device Default NI DAQmx Counter Timer Pins Continued
10. Analog Input Timing Signals On Simultaneous MIO X Series devices each channel uses its own instrumentation amplifier FIFO multiplexer mux and A D converter ADC to achieve simultaneous data acquisition The main blocks featured in the Simultaneous MIO X Series device analog input circuitry are as follows T O Connector You can connect analog input signals to the Simultaneous MIO X Series device through the I O connector Refer to Appendix A Device Specific Information for device I O connector pinouts Instrumentation Amplifier NI PGIA The NI programmable gain instrumentation amplifier NI PGIA can amplify or attenuate an AI signal to ensure that you get the maximum resolution of the ADC The NI PGIA also allows you to select the input range ADC The analog to digital converter ADC digitizes the AI signal by converting the analog voltage into a digital number e Analog Input Timing Signals For information about the analog input timing signals available on Simultaneous MIO X Series devices refer to the Analog Input Timing Signals section AI FIFO Simultaneous MIO X Series devices can perform both single and multiple A D conversions ofa fixed or infinite number of samples A large first in first out FIFO buffer holds data during A D conversions to ensure that no data is lost Simultaneous MIO X Series devices can handle multiple A D conversion operations with DMA or programmed I O 4 36
11. gt Counter Circuitry Figure 11 3 shows the analog trigger circuit on Simultaneous MIO X Series devices Figure 11 3 Simultaneous MIO X Series Device Analog Trigger Circuitry NI PGIA ADC N ee Analog Comparison ne de e Analog Event AO Circuitry Channels Mux Trigger Detection Analog Trigger DIO Circuitry Circuitry Output NI PGIA ADC Counter Circuitry APFI lt 0 1 gt a You must specify a source and an analog trigger type The source can be either an APFI lt 0 1 gt terminal or an analog input channel APFI lt 0 1 gt Terminals When you use either APFI lt 0 1 gt terminal as an analog trigger you should drive the terminal with a low impedance signal source less than 1 kQ source impedance If APFI lt 0 1 gt are left unconnected they are susceptible to crosstalk from adjacent terminals which can cause false triggering Note that the APFI lt 0 1 gt terminals can also be used for other functions such as the 11 2 ni com X Series User Manual AO External Reference input as described in the AO Reference Selection section of Chapter 5 Analog Output Analog Input Channels Refer to the Analog Input Channels on MIO X Series Devices or Analog Input Channels on Simultaneous MIO X Series Devices section depending on your device Analog Input Channels on MIO X Series Devices Select any analog input channel to drive the NI PGIA The NI PGIA amplifies
12. Figure 7 35 Finite Buffered Sample Clocked Pulse Train Generation Counter Armed Sample Clock Counter Load Values 2101010102102102102101010210210 Source H Out 3 2 2 2 3 3 3 3 2 2 3 3 There are several different methods of continuous generation that control what data is written These methods are regeneration FIFO regeneration and non regeneration modes Regeneration is the repetition of the data that is already in the buffer Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out New data can be written to the PC buffer at any time without disrupting the output With FIFO regeneration the entire buffer is downloaded to the FIFO and regenerated from there Once the data is downloaded new data cannot be written to the FIFO To use FIFO regeneration the entire buffer must fit within the FIFO size The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started thereby preventing any problems that may occur due to excessive bus traffic With non regeneration old data is not repeated New data must be continually written to the buffer If the pr
13. ao oe Jl GATE i SOURCE Counter Value 1 2 3 1 2 3 1 2 3 3 3 3 Buffer 3 3 Sample Clocked Buffered Two Signal Separation Measurement A sample clocked buffered two signal separation measurement is similar to single two signal separation measurement but buffered two signal separation measurement takes measurements over multiple intervals correlated to a sample clock The counter counts the number of rising or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO on a sample clock edge On the next active edge of the Gate signal the counter begins another measurement A DMA controller transfers the stored values to host memory National Instruments 7 25 Chapter 7 Counters Figure 7 26 shows an example of a sample clocked buffered two signal separation measurement Figure 7 26 Sample Clocked Buffered Two Signal Separation Measurement Sample Clock i i AUX GATE A l f SOURCE TLL LLL Counter Value 1 2 3 1 2 3 12 3 3 3 Buffer 3 Hardware Timed Single Point Two Signal Separation Measurement A hardware timed single point HWTSP two signal separation
14. Note NI USB 634x 635x 636x Devices USB X Series devices do not support hardware timed single point HWTSP operations Choosing a Method for Measuring Frequency The best method to measure frequency depends on several factors including the expected frequency of the signal to measure the desired accuracy how many counters are available and how long the measurement can take For all frequency measurement methods assume the following f is the frequency to be measured if no error fk is the known source or gate frequency measurement time T is the time it takes to measure a single sample Divide down N is the integer to divide down measured frequency only used in large range two counters fs is the sample clock rate only used in sample clocked frequency measurements 7 16 ni com X Series User Manual Here is how these variables apply to each method summarized in Table 7 2 One counter With one counter measurements a known timebase is used for the source frequency fk The measurement time is the period of the frequency to be measured or 1 fx Two counter high frequency With the two counter high frequency method the second counter provides a known measurement time The gate frequency equals 1 measurement time Two counter large range The two counter larger range measurement is the same as a one counter measurement but now the user has an integer divide down of the signal An internal timebase is
15. N he D N w e w s w N w A w D D PI Pi PI Pi PI PI PI D PI PI PI PI PI D PI Pi D A A A A A A A A A A A A A A A GND GND 0 24 0 23 0 31 0 29 0 20 0 19 0 18 GND 0 26 0 27 0 11 0 15 0 10 GND 0 13 0 8 GND O GND O GND GND 23 AI 23 30 Al 22 GND 21 Al 21 28 Al 20 SENSE 2 27 Al 19 GND 18 Al 18 25 Al 17 GND 116 Al 16 Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments A 19 Appendix A Device Specific Information Figure A 14 shows the pinout of the NI USB 6363 Mass Termination For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 14 NI USB 6363 Mass Termination Pinout AI 0 Al 0 34 Al 8 Al 0 Al 16 Al 16 34 Al 24 Al 16 Al GND 33 Al 1 Al 1 Al GND 33 Al 17 Al 17 Al 9
16. USER 1 USER 2 User Defined Channels 1 and 2 On NI USB 63xx BNC devices the USER lt 1 2 gt BNC connectors allow you to use a BNC connector for a digital or timing I O signal of your choice The USER lt 1 2 gt BNC connectors are internally routed to the USER lt 1 2 gt screw terminals CHS GND Chassis Groundt This terminal connects to the USB 63xx BNC device metal enclosure You can connect your cable s shield wire to CHS GND for a ground connection Though AI GND AO GND and D GND are connected on the X Series device they are connected by small traces to reduce crosstalk between subsystems Each ground has a slight difference in potential USB 63xx Screw Terminal users can connect the shield of a shielded cable to the chassis ground lug for a ground connection The chassis ground lug is not available on all device versions 5 V Power Source The 5 V terminals on the I O connector supply 5 V referenced to D GND Use these terminals to power external circuitry A Caution Never connect the 5 V power terminals to analog or digital ground or to any other voltage source on the X Series device or any other device Doing so can damage the device and the computer NI is not liable for damage resulting from such a connection 3 4 ni com X Series User Manual The power rating on most devices is 4 75 VDC to 5 25 VDC at 1 A Refer to the specifications document for your device t
17. T Large Range of Frequencies with Two Counters By using two counters you can accurately measure a signal that might be high or low frequency This technique is called reciprocal frequency measurement When measuring a large range of frequencies with two counters you generate a long pulse using the signal to measure You then measure the long pulse with a known timebase The X Series device can measure this long pulse more accurately than the faster input signal Note Counter 0 is always paired with Counter 1 Counter 2 is always paired with Counter 3 National Instruments 7 13 Chapter 7 Counters You can route the signal to measure to the Source input of Counter 0 as shown in Figure 7 14 Assume this signal to measure has frequency fr NI DAQmx automatically configures Counter 0 to generate a single pulse that is the width of N periods of the source input signal Figure 7 14 Large Range of Frequencies with Two Counters Signal to Measure fx Source Out Counter 0 Signal of Known Frequency fk Source Out Counter 1 L Gate 0 1 2 8 N CTR_0O_SOURCE l Signal to Measure CTR_0_OUT CTR_1_GATE Interval to Measure CTR_1_SOURCE JUUUUUUUUUUUUU NI DAQmx then routes the Counter 0 Internal Output signal to the gate of Counter 1 You can then route a signal of known frequency fk as a counter timebase to the Counter 1 Source
18. 50 16 Al 113 Al 113 Al 166 Al 166 19 53 Al 174 Al 166 Al 114 Al 114 49 15 Al 122 AI 114 Al 165 AI 165 20 54 AI 173 Al 165 Al 123 Al 115 48 14 Al 115 Al 115 a I Al 172 Al 164 21 55 Al 164 Al 164 Al 124 Al 116 47 13 Al 116 Al 116 o o AIGND 22 56 Al SENSE 4 Al 117 Al 117 46 12 Al 125 Al 117 Q 9 Al 163 Al 163 23 57 AI 171 AI 163 Al 126 AI 118 45 11 Al 118 Al 118 4 a Al 162 Al 162 24 58 AI 170 Al 162 Al 127 Al 119 44 10 Al 119 AI 119 Q Al 169 Al 161 25 59 AI 161 AI 161 AI GND 43 9 AI GND 9 D Al160 Al 160 26 60 AI 168 AI 160 Al 128 Al 128 42 8 Al 136 Al 128 Al 151 Al 151 27 61 AI 159 AI 151 Al 137 Al 129 41 7 Al 129 Al 129 z Al 158 AI 150 28 62 AI 150 AI 150 Al 138 Al 130 40 6 AI 130 Al 130 A1149 Al 149 29 63 Al 157 AI 149 Al 131 Al 131 39 5 Al 139 AI 131 8 Al 148 Al 148 30 64 Al 156 AI 148 Al 140 Al 132 38 4 Al 132 Al 132 AI155 Al 147 31 65 AI 147 AI 147 Al 141 Al 133 37 3 Al 133 Al 133 I Al 146 AI 146 32 66 AI 154 AI 146 Al 134 Al 134 36 2 AI 142 AI 134 Al 145 Al 145 33 67 AI 153 AI 145 Al 143 AI 135 35 1 Al 135 Al 135 Q
19. e Analog Comparison Event an analog trigger AI Sample Clock Timebase is not available as an output on the I O connector AI Sample Clock Timebase is divided down to provide one of the possible sources for AI Sample Clock You can configure the polarity selection for AI Sample Clock Timebase as either rising or falling edge except on 100 MHz Timebase or 20 MHz Timebase Al Convert Clock Signal Use the AI Convert Clock ai ConvertClock signal to initiate a single A D conversion on a single channel A sample controlled by the AI Sample Clock consists of one or more conversions 4 26 ni com X Series User Manual You can specify either an internal or external signal as the source of AI Convert Clock You can also specify whether the measurement sample begins on the rising edge or falling edge of AI Convert Clock With NI DAQmx the driver chooses the fastest conversion rate possible based on the speed of the A D converter and adds 10 us of padding between each channel to allow for adequate settling time This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time If the AI Sample Clock rate is too fast to allow for this 10 us of padding NI DAQmx chooses the conversion rate so that the AI Convert Clock pulses are evenly spaced throughout the sample To explicitly specify the conversion rate use AI Convert Clock Rate DAQmx Timing property node or function Caution Setting the
20. Al 152 AI 144 34 68 AI 144 AI 144 se ee A 36 ni com X Series User Manual Figure A 25 NI PXle 6375 Connector 0 and Connector 1 Pinout AI O Al 0 AI GND AI 9 AI 1 AI 2 AI 2 Al GND Al 11 AI 3 Al SENSE Al 12 Al 4 AI 5 AI 5 AI GND Al 14 AI 6 AI 7 Al 7 Al GND AO GND AO GND D GND PO 0 PO 5 D GND PO 2 PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND w A oO oO ie D w N D N N D D a hm A N w N D bed D er oo a A w N o N HR a a N o Al 8 AI 0 Al 1 Al 1 Al GND Al 10 Al 2 Al 3 Al 3 Al GND Al 4 Al 4 Al GND Al 13 Al 5 Al 6 Al 6 Al GND Al 15 Al 7 AO 0 AO 1 APFI 0 PO 4 D GND PO 1 PO 6 D GND 5V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5 V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 Old Ov SL 0 Iv 0 HOLOANNOO Q4 a Qt p UH o DD pp DD pp pp pp pp pp ppp gt uou gt gt gt gt gt 62 94 Iv L HOLOANNOO 71 A171 78 Al 70 69 Al 69 68 Al 68 75 Al 67 66 Al 66 65 Al 65
21. Figure 4 1 MIO X Series Analog Input Circuitry Al lt 0 207 gt gt 5 Mux 3 DIFF RSE i S or NRSE NI PGIA ADC Al FIFO Al Data O O Al SENSE Input Range AI GND Selection DA Al Terminal Configuration Selection The main blocks featured in the MIO X Series device analog input circuitry are as follows T O Connector You can connect analog input signals to the MIO X Series device through the I O connector The proper way to connect analog input signals depends on the analog input ground reference settings described in the Analog Input Ground Reference Settings section Also refer to Appendix A Device Specific Information for device I O connector pinouts Mux Each MIO X Series device has one analog to digital converter ADC The multiplexers mux route one AI channel at a time to the ADC through the NI PGIA Ground Reference Settings The analog input ground reference settings circuitry selects between differential referenced single ended and non referenced single ended input modes Each AI channel can use a different mode Instrumentation Amplifier NI PGIA The NI programmable gain instrumentation amplifier NI PGIA is a measurement and instrument class amplifier that minimizes National Instruments 4 1 Chapter 4 Analog Input settling times for all input ranges The NI PGIA can amplify or attenuate an AI signal to ensure that you use the maxi
22. PFI O Source PFI 2 Source D GND PFI Filters N7 X Series Device You can enable a programmable debouncing filter on each PFI RTSI PXI STAR or PXIe DSTAR lt A B gt signal When the filters are enabled your device samples the input on each rising edge of a filter clock X Series devices use an onboard oscillator to generate the filter clock The following is an example of low to high transitions of the input signal High to low transitions work similarly 8 4 ni com X Series User Manual Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on N consecutive edges the low to high transition is propagated to the rest of the circuit The value of N depends on the filter setting refer to Table 8 1 Table 8 1 Filters N Filter Pulse Width Clocks Pulse Width Guaranteed Needed to Guaranteed to Not Pass Filter Setting Filter Clock Pass Signal to Pass Filter Filter None 90 ns 100 MHz 9 90 ns 80 ns short 5 12 us 100 MHz 512 5 12 us 5 11 us medium 2 56 ms 100 kHz 256 2 56 ms 2 55 ms high Custom User N N timebase N 1 configurable timebase The filter setting for each input can be configured independently On power up the filters are disabled Figure 8 3 shows an example of a low
23. To locate LabVIEW LabWindows CVI Measurement Studio Visual Basic and ANSI C examples refer to the KnowledgeBase document Where Can I Find NI DAQmx Examples by going to ni com info and entering the Info Code daqmxexp For additional examples refer to ni com examples National Instruments 5 11 Digital I O X Series devices contain up to 32 lines of bidirectional DIO signals on Port 0 In addition X Series devices have up to 16 PFI signals that can function as static DIO signals X Series devices support the following DIO features on Port 0 e Up to 32 lines of DIO e Direction and function of each terminal individually controllable e Static digital input and output e High speed digital waveform generation e High speed digital waveform acquisition e DI change detection trigger interrupt Figure 6 1 shows the circuitry of one DIO line Each DIO line is similar The following sections provide information about the various parts of the DIO circuit Figure 6 1 X Series Digital I O Circuitry DO Waveform Generation FIFO DO Sample Clock Static DO Buffer I O Protection PO x DO x Direction Control Static DI Weak Pull Down DI Waveform Measurement FIFO Filter L DI Sample Clock DI Change Detection The DIO terminals are named P0 lt 0 31 gt on the X Series device I O connector National
24. You can configure the counter to sample on the rising or falling edge of the sample clock 7 4 ni com X Series User Manual Figure 7 4 shows an example of buffered edge counting Notice that counting begins when the counter is armed which occurs before the first active edge on Sample Clock Figure 7 4 Buffered Sample Clock Edge Counting Counter Armed Sample Clock Sample on Rising Edge SOURCE Counter Value 0 ol gt a D ojj N Buffer Controlling the Direction of Counting In edge counting applications the counter can count up or down You can configure the counter to do the following e Always count up e Always count down e Count up when the Counter 0 B input is high count down when it is low For information about connecting counter signals refer to the Default Counter Timer Pinouts section Pulse Width Measurement In pulse width measurements the counter measures the width of a pulse on its Gate input signal You can configure the counter to measure the width of high pulses or low pulses on the Gate signal You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges on the Source signal while the pulse on the Gate signal is active You can calculate the pulse width by
25. pri5P15 PFI 15 P2 7 39 5 PFI 6 P1 6 PFI 7 P1 7 38 4 DGND PFI8 P2 0 37 3 PFI 9 P2 1 D GND 36 2 PFI12 P24 D GND 35 1 PFI 14 P2 6 Sa CONNECTOR 0 Al 0 15 TERMINAL 34 TERMINAL 1 TERMINAL 68 TERMINAL 35 A 16 ni com X Series User Manual a Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help Figure A 12 shows the pinout of the NI USB 6361 BNC For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 12 NI USB 6361 BNC Pinout E gt 5 a 2 g S z 2 DODODDODODOODOODOOODDODODOODOODODOODOOO USER ACCESS mumm E ANALOG OUTPUT DS al jalalajajalajajajalalajajalalajajalalajaalaalaaajaa EE DIGITAL AND TIMING 1 0 mE CHS GND NATION a UB X Series Multifunction DAQ National Instruments A 17 Appendix A Device Specific Information Refer to Table 7 9 X Series PCI Express PXT Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inp
26. 72 Al 64 GND 55 Al 55 54 Al 54 61 AI 53 52 AI 52 51 Al 51 58 AI 50 49 Al 49 48 Al 48 47 Al 39 38 AI 38 37 Al 37 44 Al 36 GND 35 Al 35 34 AI 34 41 AI 33 32 Al 32 23 Al 23 30 Al 22 21 Al 21 20 Al 20 27 Al 19 18 Al 18 17 Al 17 24 Al 16 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 21810 lo olum l cln D w P a oo er o D N N N D oO N R D a D D D NI D N oO oO oO wo oO D oO a w LL AI 79 AI 71 AI 70 AI 70 AI 77 AI 69 AI 76 AI 68 AI 67 AI 67 AI 74 AI 66 AI 73 AI 65 Al 64 Al 64 Al GND Al 63 AI 55 Al 62 AI 54 AI 53 AI 53 AI 60 AI 52 AI 59 AI 51 AI 50 AI 50 AI 57 AI 49 AI 56 AI 48 AI 39 AI 39 AI 46 AI 38 AI 45 AI 37 AI 36 Al 36 Al SENSE 2 Al 43 AI 35 Al 42 AI 34 AI 33 AI 33 AI 40 Al 32 AI 31 AI 23 AI 22 AI 22 AI 29 AI 21 AI 28 AI 20 AI 19 AI 19 AI 26 AI 18 AI 25 AI 17 Al 16 Al 16 Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins
27. Al Al AP PO PO PO 5 PF PFI 5 PFI PF PF PF PF nfwlp alo 1 0o Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Al GND AI 8 AI 0 1 Al 1 10 Al 2 AI 3 AI 3 AI GND Al 4 AI 4 AI GND 13 A15 Al 6 AI 6 AI GND 15 AI 7 AO O0 AO 1 FIO 4 D GND Al 6 D GND v D GND D GND 0 P1 0 1 P1 1 D GND v D GND 5 P1 5 6 P1 6 D GND 9 P2 1 112 P2 4 14 P2 6 TERMINAL 68 TERMINAL 34 TERMINAL 1 TERMINAL 35 CONNECTOR 0 AI 0 15 Ps D 2 Ze fe TERMINAL 35 TERMINAL 1 TERMINAL 34 TERMINAL 68 P0 30 P0 28 P0 25 D GND P0 22 P0 21 D GND 5V D GND P0 17 P0 16 D GND D GND 5V D GND P0 14 P0 9 D GND P0 12 APFI 1 AO 3 AO 2 31 Al 23 GND 22 Al 22 29 Al 21 GND 20 Al 20 GND 19 Al 19 26 Al 18 GND 17 Al 17 24 Al 16 gt gt gt gt gt gt gt gt gt gt gt 5 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 olo o n o N w P a er D e N N N N wo Le D a N
28. External Signal Prescaler Rollover Used as Source by Counter Counter Value 0 X A Prescaling is intended to be used for frequency measurement where the measurement is made on a continuous repetitive signal The prescaling counter cannot be read therefore you cannot determine how many edges have occurred since the previous rollover Prescaling can be used for event counting provided it is acceptable to have an error of up to seven or one ticks Prescaling can be used when the counter Source is an external signal Prescaling is not available if the counter Source is one of the internal timebases 100MHzTimebase 20MHzTimebase or 100kHzTimebase Synchronization Modes The 32 bit counter counts up or down synchronously with the Source signal The Gate signal and other counter inputs are asynchronous to the Source signal so X Series devices synchronize these signals before presenting them to the internal counter Depending on how you configure your device X Series devices use one of three synchronization methods 100 MHz Source Mode External Source Greater than 25 MHz External or Internal Source Less than 25 MHz 7 46 ni com X Series User Manual 100 MHz Source Mode In 100 MHz source mode the device synchronizes signals on the rising edge of the source and counts on the third rising edge of the source Edges are pipelined so no counts are lost as shown in Figure 7 40 Figure 7 40 100 MHz Sou
29. NI 6321 6341 A 4 accessory options A 7 cabling options A 7 PCI Express pinout A 4 PXI Express pinout A 4 specifications A 7 USB BNC pinout A 6 USB pinout A 5 NI 6323 6343 A 8 accessory options A 11 cabling options A 11 PCI Express pinout A 8 USB pinout A 9 NI 6343 USB BNC pinout A 10 USB pinout A 10 NI 6345 6355 A 12 accessory options A 13 cabling options A 13 pinout A 12 specifications A 13 NI 6351 6361 accessory options A 18 cabling options A 18 PCI Express pinout A 14 PXI Express pinout A 14 National Instruments 1 9 Index specifications A 18 USB pinout A 15 A 16 A 20 NI 6353 6363 A 19 accessory options A 24 cabling options A 24 PCI Express pinout A 19 PXI Express pinout A 19 specifications A 24 NI 6356 6366 accessory options A 30 cabling options A 30 PXI Express pinout A 25 specifications A 30 USB pinout A 28 NI 6358 6368 accessory options A 32 cabling options A 32 pinout A 31 specifications A 32 NI 6363 USB BNC pinout A 23 NI 6365 A 33 accessory options A 35 cabling options A 35 pinout A 33 specifications A 35 NI 6375 A 36 accessory options A 38 cabling options A 38 pinout A 36 specifications A 38 NI USB 6361 BNC pinout A 17 NI USB 6356 6366 BNC pinout A 29 NI DAQmx default counter terminals 7 42 documentation B 1 installation 1 1 NI PGIA MIO X Series devices 4 1 Simultaneous MIO X Series devices 4 36 1 10 ni
30. PFI 15 P2 7 5 V NI DAQmx Counter Timer Pins for a list of the default NI DAQm x counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments A 15 Appendix A Device Specific Information Figure A 11 shows the pinout of the NI USB 6361 Mass Termination For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 11 NI USB 6361 Mass Termination Pinout Alo alos 68134 AI8 A10 AI GND 67 33 ald AI 1 Alg Ali 66 32 alGND AI2 A124 65131 alto al2 AI GND 64 30 als Al 3 aAl11 Al3 63 29 Al GND Al SENSE 62 28 ala Al 4 Al 12 Al4 61 27 Al GND AI5 A15 60 26 al 13 Al5 AI GND 59 25 ale Al 6 al14 ale 58 24 Al GND Al7 Al7 57 23 al 15 al7 AI GND 56 22 aoo AO GND 55 21 a01 AO GND 54 20 APFI0 D GND 53 19 Po 4 P0 0 52 18 D GND PO 5 51 17 Po 1 D GND 50 16 Po 6 PO 2 49 15 D GND PO 7 48 141 45V P0 3 47 13 D GND PFI 11 P2 3 46 12 D GND PFI 10 P2 2 45 11 PFIO P1 0 D GND 44 10 PF 1 P1 1 pri2P1 2 431 9 bDano Priap1 3 42 8 45v pria p1 4 latl 7 p np PFI 13 P2 5 40 6
31. RTSI lt 0 7 gt are bidirectional terminals As an output you can drive any ofthe following signals to any RTSI terminal Al Start Trigger ai StartTrigger Al Reference Trigger ai ReferenceTrigger AI Convert Clock ai ConvertClock e AI Sample Clock ai SampleClock e Al Pause Trigger ai PauseTrigger AO Sample Clock ao SampleClock e AO Start Trigger ao StartTrigger e AO Pause Trigger ao PauseTrigger e DI Start Trigger di StartTrigger e DI Sample Clock di SampleClock DI Pause Trigger di PauseTrigger DI Reference Trigger di ReferenceTrigger e DO Start Trigger do StartTrigger DO Sample Clock do SampleClock e DO Pause Trigger do PauseTrigger 10 MHz Reference Clock Counter n Source Gate Z Internal Output Change Detection Event e Analog Comparison Event e FREQ OUT e PFI lt 0 5 gt Note Signals with a are inverted before being driven on the RTSI terminals Using RTSI Terminals as Timing Input Signals You can use RTSI terminals to route external timing signals to many different X Series functions Each RTSI terminal can be routed to any of the following signals e AI Convert Clock ai ConvertClock e AI Sample Clock ai SampleClock e Al Start Trigger ai StartTrigger Al Reference Trigger ai ReferenceTrigger AI Pause Trigger ai PauseTrigger AI Sample Clock Timebase ai SampleClockTimebase 9 6 ni com X Series User Manual e AO Star
32. When the multiplexer switches from channel 0 to channel 1 the input to the NI PGIA switches from 4 V to 1 mV The approximately 4 V step from 4 V to 1 mV is 1 000 of the new full scale range For a 16 bit device to settle within 0 0015 15 ppm or 1 LSB of the 200 mV full scale range on channel 1 the input circuitry must settle to within 0 000031 0 31 ppm or 1 50 LSB of the 10 V range Some devices can take many microseconds for the circuitry to settle this much To avoid this effect you should arrange your channel scanning order so that transitions from large to small input ranges are infrequent In general you do not need this extra settling time when the NI PGIA is switching from a small input range to a larger input range Insert Grounded Channel between Signal Channels Another technique to improve settling time is to connect an input channel to ground Then insert this channel in the scan list between two of your signal channels The input range of the grounded channel should match the input range of the signal after the grounded channel in the scan list Consider again the example above where a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 Suppose the input range for channel 0 is 10 V to 10 V and the input range of channel 1 is 200 mV to 200 mV You can connect channel 2 to AI GND or you can use the internal ground refer to Internal Channels in the NI DAQmx Help Set the input
33. 3 4 Numerics 10 MHz reference clock 9 3 100 kHz Timebase 9 2 100 MHz source mode 7 47 Timebase 9 2 20 MHz Timebase 9 2 A A D converter MIO X Series devices 4 2 AC coupling connections Simultaneous MIO X Series devices 4 43 accessories 2 3 2 7 choosing for your device 1 8 field wiring considerations Simultaneous MIO X Series devices 4 44 NI 6320 A 3 NI 6321 6341 A 7 NI 6323 6343 A 11 NI 6345 6355 A 13 NI 6351 6361 A 18 NI 6353 6363 A 24 NI 6356 6366 A 30 NI 6358 6368 A 32 NI 6365 A 35 NI 6375 A 38 accuracy analog triggers 11 6 acquisitions circular buffered MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 39 digital waveform 6 4 double buffered MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 39 hardware timed MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 38 on demand MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 software timed MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 AI Convert Clock signal 4 26 AI Convert Clock Timebase signal 4 30 AI FIFO MIO X Series devices 4 2 Simultaneous MIO X Series devices 4 36 AI Hold Complete Event signal MIO X Series devices 4 30 Simultaneous MIO X Series devices 4 49 AI Pause Trigger signal MIO X Series devices 4 33 Simultaneous MIO X Series devices 4 53 AI Reference Trigger signal MIO X Series devices 4 32 Simultaneous MIO X Series devices 4
34. 36 Al 198 AI 198 AI 90 AI 82 66 32 AI 82 AI 82 Al 197 Al 197 3 37 AI 205 AI 197 AI 83 AI 83 65 31 Al 91 AI 83 Al 196 AI 196 4 38 AI 204 AI 196 AI 92 AI 84 64 30 AI 84 AI 84 Al 203 AI 195 5 39 AI 195 AI 195 AI 93 AI 85 63 29 AI 85 Al 85 Al 194 AI 194 6 40 AI 202 AI 194 AI 86 AI 86 62 28 AI 94 AI 86 Al 193 Al 193 7 41 AI 201 AI 193 Al 95 AI 87 61 27 Al 87 Al 87 Al 200 AI 192 8 42 Al 192 Al 192 Al 104 Al 96 60 26 Al 96 AI 96 Al GND 9 43 AI GND AI 97 AI 97 59 25 AI 105 AI 97 Al 183 Al 183 10 44 Al 191 AI 183 Al 106 A198 58 24 AI 98 AI 98 Al 182 Al 182 11 45 Al 190 Al 182 Al 107 Al 99 57 23 Al 99 Al 99 Al 189 AI 181 12 46 Al 181 Al 1814 AI SENSE 3 56 22 AI GND AI 180 Al 180 13 47 AI 188 AI 180 AI 100 AI 100 55 21 AI 108 AI 100 Al 179 Al 179 14 48 Al 187 AI 179 Al 109 Al 101 54 20 AI 101 Al 101 Al 186 Al 178 15 49 Al 178 AI 178 AI 110 AI 102 53 19 Al 102 Al 102 Al 177 Al 177 16 50 AI 185 AI 177 Al 103 Al 103 52 18 Al 111 AI 103 Al 176 Al 176 17 51 Al 184 AI 176 Al 120 Al 112 51 17 Al 112 Al 112 Al 175 Al 167 18 52 Al 167 Al 167 Al 121 Al 113
35. 4 42 for floating signal sources Simultaneous MIO X Series devices 4 43 single ended for floating signal sources MIO X Series devices 4 17 single ended RSE configuration MIO X Series devices 4 17 connector information 3 1 NI PCle PXIe 6341 A 4 NI PCle PXIe 6361 A 14 NI PCle PXIe 6363 A 19 NI PCIe 6320 A 2 A 33 NI PCIe 6321 A 4 NI PCIe 6323 6343 A 8 NI PCIe 6351 A 14 NI PCIe 6353 Screw Terminal A 19 NI PXIe 6345 6355 A 12 NI PXIe 6356 6366 A 25 NI PXTe 6358 6368 A 31 NI PXIe 6375 A 36 NI USB 6341 BNC A 6 NI USB 6341 Screw Terminal A 5 NI USB 6343 A 9 NI USB 6343 BNC A 10 NIUSB 6351 6361 Screw Terminal A 15 NI USB 6353 Mass Termination A 20 NI USB 6356 6366 Screw Terminal A 28 NI USB 6361 Mass Termination A 16 NI USB 6363 Screw Terminal A 23 RTSL 3 6 considerations for field wiring MIO X Series devices 4 21 Simultaneous MIO X Series devices 4 44 for multichannel scanning MIO X Series devices 4 6 for PXI Express 10 2 continuous pulse train generation 7 30 controller DMA 10 1 controlling counting direction 7 3 counter input and output 7 42 output applications 7 26 terminals default 7 42 Counter n A signal 7 39 Counter n Aux signal 7 38 Counter n B signal 7 39 Counter n Gate signal 7 38 Counter n HW Arm signal 7 40 Counter n Internal Output signal 7 41 Counter n Sample Clock signal 7 40 Counter n Source signal 7 37 Counter n TC signal 7 41 Counter n Up_Down signal
36. APFI O AI 58 AI 50 15 49 A1 50 Al 50 D GND 53 19 PO 4 Q Al 49 Al 49 16 50 A157 Al 49 P0 0 52 18 D GND Al 48 Al 48 17 51 Al 56 Al 48 PO 5 51117 PO i Al 47 AI 39 18 52 AI 39 AI 39 D GND 50 16 P0 6 AI 38 AI 38 19 53 Al 46 Al 38 PO 2 49 15 D GND Al 37 Al 37 20 54 A1 45 Al 37 PO 7 48 14 5V Al 44 Al 36 21 55 AI 36 Al 36 P0 3 47 13 D GND AI GND 22 56 Al SENSE 2 PFI 11 P2 3 46 12 D GND Al 35 AI 35 23 57 Al 43 Al 35 PFI 10 P2 2 45 11 PFI0 P1 0 Al 34 Al 34 24 58 Al 42 Al 34 D GND 44 10 PFI1 P1 1 Al 41 Al 33 25 59 A133 Al 33 PFI 2 P1 2 43 9 DGND Al 32 Al 32 26 60 Al 40 Al 32 PFI 3 P1 3 42 8 45v Al 23 Al 23 27 61 A1 31 Al 234 PFI 4 P1 4 41 7 D GND Al 30 Al 22 28 62 Al 22 Al 22 PFI 13 P2 5 40 6 PFI5 P1 5 Al 21 Al 21 29 63 Al 29 Al 21 PFI 15 P2 7 39 5 PFI 6 P1 6 Al 20 AI 20 30 64 Al 28 Al 20 PFI 7 P1 7 38 4 D GND Al 27 A119 31 65 Al19 Al 19 PFI 8 P2 0 37 3 PFI9 P2 1 Al 18 Al 18 32 66 A1 26 Al 18 D GND 36 2 PFI 12 P2 4 Al 17 Al 17 33 67 A125 Al 17 D GND 35 1 PFI 14 P2 6 AI 24 Al 16 34 68 Al 16 AI 16 a eee Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer
37. Armed Edge Gate Bouts FL ALE LS Se Le Counter Value 0 od 2 3 11 40 2 1 33 if oB Buffer 1 2 For information about connecting counter signals refer to the Default Counter Timer Pinouts section Frequency Measurement You can use the counters to measure frequency in several different ways Refer to the following sections for information about X Series frequency measurement options e Low Frequency with One Counter High Frequency with Two Counters Large Range of Frequencies with Two Counters Sample Clocked Buffered Frequency Measurement Hardware Timed Single Point Frequency Measurement Low Frequency with One Counter For low frequency measurements with one counter you measure one period of your signal using a known timebase You can route the signal to measure fx to the Gate of a counter You can route a known timebase fk to the Source of the counter The known timebase can be an onboard timebase such as 100 MHz Timebase 20 MHz Timebase or 100 kHz Timebase or any other signal with a known rate National Instruments 7 11 Chapter 7 Counters You can configure the counter to measure one period of the gate signal The frequency of fx is the inverse of the period Figure 7 12 illustrates this method Figure 7 12 Low Frequency with One Counter Interval Measured
38. B gt PFI RTSI DSTAR lt A B gt PXI STAR AO Sample Clock PFI RTSI Analog Comparison Event PXI_STAR Ctr n Internal Output AO Sample Clock Analog Comparison Timebase Programmable Event Clock 20 MHz Timebase Divider 100 kHz Timebase PXI_CLK10 X Series devices feature the following analog output waveform generation timing signals AO Start Trigger Signal e AO Pause Trigger Signal e AO Sample Clock Signal e AO Sample Clock Timebase Signal National Instruments 5 5 Chapter 5 Analog Output Signals with an support digital filtering Refer to the PFI Filters section of Chapter 8 PFI for more information AO Start Trigger Signal Use the AO Start Trigger ao StartTrigger signal to initiate a waveform generation If you do not use triggers you can begin a generation with a software command Retriggerable Analog Output The AO Start Trigger is configurable as retriggerable The timing engine generates the sample clock for the configured generation in response to each pulse on an AO Start Trigger signal The timing engine ignores the AO Start Trigger signal while the clock generation is in progress After the clock generation is finished the counter waits for another Start Trigger to begin another clock generation Figure 5 4 shows a retriggerable AO generation of four samples Figure 5 4 Retriggerable Analog Output rn is rosampece __ LIL Id Using a Digital So
39. Filtered Input When multiple lines are configured with the same filter settings they are considered a bus There are two filtering modes for use with multiple lines line filtering and bus filtering With line filtering each line transitions independently of the other lines in the bus and acts like the behavior described above With bus filtering if any one line in the bus has jitter then all lines in the bus hold the state until the bus becomes stable However each individual line only waits one extra filter tick before changing which prevents a noisy line from holding a valid transition indefinitely With bus mode if all the bus line transitions become stable in less than one filter clock period and the bus period is more than two filter clock periods then all the bus lines are guaranteed to be correlated at the output of the filter The behavior for each transition can be thought of as a state machine If a line transitions and stays high for two consecutive filter clock edges then one of two options occurs e Case 1 If no transitions have occurred on the other lines the transition propagates on the second filtered clock edge as shown in Figure 6 13 Figure 6 13 Case 1 Stable Stable Stable 1 1 1 1 q L 1 1 q Filter Clock Filtered Input A Filtered Input B
40. N NX EH D QD N N Q a w te D A s D a w N fex foo w wo D N w D Le D GND D GND P0 24 P0 23 P0 31 P0 29 P0 20 P0 19 P0 18 D GND P0 26 P0 27 P0 11 P0 15 P0 10 D GND P0 13 P0 8 D GND AO GND AO GND Al 15 GND Al 15 Al 13 GND Al 13 Al 12 NC Al 11 Al 10 GND Al 10 AI 8 GND NC No Connect Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments A 31 Appendix A Device Specific Information NI 6358 6368 Device Specifications Refer to the MI 6358 Specifications for more detailed information about the NI 6358 device Refer to the MI 6368 Specifications for more detailed information about the NI 6368 device NI 6358 6368 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information A 32 ni com NI 6365 X Series User Manual The following sections contain information about the NI PXIe 6365 device NI 6365 Pinout Figure A 22 and Figure A 23 show the pinouts of the NI PXIe 6365 The I O signals appear on three 68 pin
41. Pulse Measurement 7 8 Single Pulse Measurement 1 8 Implicit Buffered Pulse Measurement 7 8 National Instruments ix Contents Sample Clocked Buffered Pulse Measurement 0 cesssscesseeeeeeeceeneeeenees Hardware Timed Single Point Pulse Measurement Pulse versus Semi Period Measurements 0 ccccsesesesseeceeseeeeeseserseeeeeeeseeenees S mi Period Measurement sn rmenene tt nn en MAN RES Single Semi Period Measurement 00 0 0 eee sceeesseeeeseneseceseseeeceeeecaeseeecseseeeeenees Implicit Buffered Semi Period Measurement Frequency Measurement Low Frequency with One Counter High Frequency with Two Counters Large Range of Frequencies with Two Counters 0 cecesseeseseseeeeeeeeeeeneeees Sample Clocked Buffered Frequency Measurement Hardware Timed Single Point Frequency Measurement 7 16 Choosing a Method for Measuring Frequency ccccsccseeseesceseecereeeeeeeeeeeeees 7 16 Period Measurement cc cceessesesseseeseeseeesceseessceeescsaeseeecseceseceesevseaeeevscsaesesaceesets 7 20 Position Measurement 7 21 Measurements Using Quadrature Encoders 7 21 Measurements Using Two Pulse Encoders 7 23 Buffered Sample Clock Position Measurement eseseesee
42. Retriggerable DO 6 15 Using a Digital Source 6 16 Using an Analog Source iii 6 16 Routing DO Start Trigger Signal to an Output Terminal 6 16 DOPause Trigger Sighal ised Tnt nt nn nee der es less 6 16 Using a Digital Source 6 17 Using an Analog Source ccccccecesesseeseeseeseeecescesceseeseeeeeees 6 18 Routing DO Pause Trigger Signal to an Output Terminal 6 18 V O Protection n nene NE eens Meet Gan ete alee dt rte 6 18 Programmable Power Up States 6 18 Di Change Detect oti ericson sires a isei aA AEA NETOS ATIE AAA a Eea 6 19 DI Change Detection Applications 6 20 Digital Filtering eee eeeeeeseeeeeeeeees 6 20 Watchdog Timer s00 0 0 6 22 Connecting Digital I O Signals 6 23 Getting Started with DIO Applications in Software 6 24 Chapter 7 Counters Counter Timing Engine ses 7 2 Counter Input Applications ss 7 3 COUNTING Ed SCS nent n alin a a ed NM Se ES 7 3 Single Point On Demand Edge Counting Buffered Sample Clock Edge Counting 7 4 Controlling the Direction of Counting 5 425 Pulse Width Measur ment senon pee a tins eh jeans EG 7 5 Single Pulse Width Measurement 0 cccecceessesssssesceeceeceecaeaecsecaecsecneeseeneens 7 6 Implicit Buffered Pulse Width Measurement 7 6 Sample Clocked Buffered Pulse Width Measurement 7 7 Hardware Timed Single Point Pulse Width Measurement 7 7
43. The counter can begin the pulse train generation as soon as the counter is armed or in response to a hardware Start Trigger You can route the Start Trigger to the Gate input of the counter You can also use the Gate input of the counter as a Pause Trigger if it is not used as a Start Trigger The counter pauses pulse generation when the Pause Trigger is active Figure 7 33 shows a continuous pulse train generation using the rising edge of Source Figure 7 33 Continuous Pulse Train Generation SOURCE IL OUT Counter Armed Continuous pulse train generation is sometimes called frequency division If the high and low pulse widths of the output signal are M and N periods then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M N For information about connecting counter signals refer to the Default Counter Timer Pinouts section Buffered Pulse Train Generation X Series counters can use the FIFO to perform a buffered pulse train generation Buffered pulse train generation can use implicit timing or sample clock timing When using implicit timing the pulse idle time and active time changes with each sample you write With sample clocked timing each sample you write updates the idle time and active time of your generation on each sample clock edg
44. Using an Analog Source When you use an analog trigger source the acquisition begins on the first rising edge of the Analog Comparison Event signal Routing Al Start Trigger to an Output Terminal You can route AI Start Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The output is an active high pulse All PFI terminals are configured as inputs by default The device also uses AI Start Trigger to initiate pretriggered DAQ operations In most pretriggered applications a software trigger generates AI Start Trigger Refer to the 47 Reference Trigger Signal section for a complete description of the use of AI Start Trigger and AI Reference Trigger in a pretriggered DAQ operation Al Reference Trigger Signal Use AI Reference Trigger ai ReferenceTrigger signal to stop a measurement acquisition To use a reference trigger specify a buffer of finite size and a number of pretrigger samples samples that occur before the reference trigger The number of posttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of pretrigger samples 4 Note NI USB 6356 6366 Devices You can select the buffer on the host or on the NI USB 6356 6366 device To enable a Reference Trigger to Onboard Memory set the AI Data Transfer Request Condition property in NI DAQmx to When Acquisition Complete National Instruments 4 51 Chapter 4 Analog Input Once the acquisit
45. but some do not support analog triggering To find your device triggering options refer to the specifications document for your device National Instruments 6 3 Chapter 6 Digital I O Digital Waveform Acquisition Figure 6 2 summarizes all of the timing options provided by the digital input timing engine Figure 6 2 Digital Input Timing Options 100 MHz Timebase DSTAR lt A B gt PFI RTSI DSTAR lt A B gt PXI_STAR PFI RTSI Analog Comparison Event DI Sample Clock Ctr n Internal Output PXLSTAR DI Sample Clock Analog Comparison _ Timebase Programmable Event hd Clock Divider 20 MHz Timebase 100 kHz Timebase PXI_CLK10 PA You can acquire digital waveforms on the Port 0 DIO lines The DI waveform acquisition FIFO stores the digital samples X Series devices have a DMA controller dedicated to moving data from the DI waveform acquisition FIFO to system memory The DAQ device samples the DIO lines on each rising or falling edge of a clock signal DI Sample Clock You can configure each DIO line to be an output a static input or a digital waveform acquisition Input X Series devices feature the following digital input timing signals DI Sample Clock Signal e DI Sample Clock Timebase Signal DI Start Trigger Signal DI Reference Trigger Signal e DI Pause Trigger Signal Signals with an support digital filtering Refer
46. devices 4 41 signal descriptions 3 2 signal routing RTSI bus 9 4 signal sources floating MIO X Series devices 4 12 Simultaneous MIO X Series devices 4 41 ground referenced MIO X Series devices 4 17 Simultaneous MIO X Series devices 4 41 signals AI Convert Clock 4 26 AI Convert Clock Timebase 4 30 AI Hold Complete Event 4 30 Simultaneous MIO X Series devices 4 49 AI Pause Trigger MIO X Series devices 4 33 Simultaneous MIO X Series devices 4 53 AI Reference Trigger MIO X Series devices 4 32 Simultaneous MIO X Series devices 4 51 AI Sample Clock MIO X Series devices 4 24 Simultaneous MIO X Series devices 4 47 AI Sample Clock Timebase MIO X Series devices 4 26 Simultaneous MIO X Series devices 4 49 AI Start Trigger MIO X Series devices 4 30 Simultaneous MIO X Series devices 4 50 analog input MIO X Series devices 4 22 Simultaneous MIO X Series devices 4 45 analog output 5 5 AO Pause Trigger 5 7 AO Sample Clock 5 8 AO Sample Clock Timebase 5 10 AO Start Trigger 5 6 Change Detection Event 6 19 connecting analog input MIO X Series devices 4 10 connecting analog output 5 5 connecting counter C 2 connecting digital I O 6 23 connecting PFI input 8 4 Counter n A 7 39 Counter n Aux 7 38 Counter n B 7 39 Counter n Gate 7 38 Counter n HW Arm 7 40 Counter n Internal Output 7 41 Counter n Sample Clock 7 40 Counter n Source 7 37 Counter n TC 7 41 Counter n Up_Down 7 39 Counter n Z
47. for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments A 37 Appendix A Device Specific Information NI 6375 Device Specifications Refer to the M 6375 Device Specifications for more detailed information about the NI 6375 device NI 6375 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAO System Overview for more information A 38 ni com Where to Go from Here This section lists where you can find example programs for the X Series device and relevant documentation Example Programs NI DAQmx software includes example programs to help you get started programming with the X Series device Modify example code and save it in an application or use examples to develop a new application or add example code to an existing application To locate NI software examples go to ni com info and enter the Info Code daqmxexp For additional examples refer to ni com examples To run examples without the device installed use an NI DAQmx simulated device For more information in Measurement amp Automation Explorer MAX select Help Help Topics NI DAQmx MAX Help for NI DAQmx and search for simulated devices Related Documentation Each
48. if present in each sub system to ensure efficient data movement e Routes timing and control signals The acquisition generation sub systems use these signals to manage acquisitions and generations These signals can come from the following sources Your X Series device Other devices in your system through RTSI User input through the PFI terminals User input through the PXI STAR terminal Routes and generates the main clock signals for the X Series device Clock Routing Figure 9 1 shows the clock routing circuitry of an X Series device Figure 9 1 X Series Clock Routing Circuitry agen ET 10 MHZ BATEK To RTSI lt 0 7 gt 100 z i Output Selectors Oscillator External 100 MHz RTSI lt 0 7 gt 4 Reference Timebase PXle_CLK100 Clock PLL 20 MHz PXI_LSTAR i Timebase PFI 100 kHz PXle DSTAR lt A B gt 200 F timebase National Instruments 9 1 Chapter 9 Digital Routing and Clock Generation 100 MHZ Timebase The 100 MHz Timebase can be used as the timebase for all internal subsystems The 100 MHz Timebase is generated from the following sources e Onboard oscillator e External signal by using the external reference clock 20 MHz Timebase The 20 MHz Timebase can be used to generate many of the AI and AO timing signals The 20 MHz Timebase can also be used as the Source input to the 32 bit gener
49. m 10 Ib in Figure 1 3 Using the USB X Series Mounting Kit on a Wall or Panel 2 Place the USB X Series device on the backpanel wall mount with the signal wires facing down and the device bottom sitting on the backpanel wall mount lip 3 While holding the USB X Series device in place attach the front bracket to the backpanel wall mount by tightening the two thumbscrews National Instruments 1 5 Chapter 1 Getting Started DIN Rail Mounting Complete the following steps to mount your USB X Series device to a DIN rail using the USB X Series mounting kit with DIN rail clip part number 781515 01 not included in your USB X Series device kit 1 Fasten the DIN rail clip to the back of the backpanel wall mount using a 1 Phillips screwdriver and four machine screws part number 74098 1 01 included in the kit as shown in Figure 1 4 Tighten the screws to a torque of 0 4 N m 3 6 Ib in Figure 1 4 Attaching the DIN Rail Clip to the Backpanel Wall Mount 2 Clip the bracket onto the DIN rail as shown in Figure 1 5 Figure 1 5 DIN Rail Clip Parts Locator Diagram a 1 DIN Rail Clip 2 DIN Rail Spring 3 DIN Rail 3 Place the USB X Series device on the backpanel wall mount with the signal wires facing down and the device bottom sitting on the backpanel wall mount lip 4 While holding the USB X Series device in place attach the front bracket to the backpanel wall mount by t
50. sample clock position measurement You must arm a counter to begin position measurements Refer to the following sections for more information about the X Series position measurement options Measurements Using Quadrature Encoders Measurements Using Two Pulse Encoders Buffered Sample Clock Position Measurement Measurements Using Quadrature Encoders The counters can perform measurements of quadrature encoders that use X1 X2 or X4 encoding A quadrature encoder can have up to three channels channels A B and Z e X1 Encoding When channel A leads channel B in a quadrature cycle the counter increments When channel B leads channel A in a quadrature cycle the counter decrements The amount of increments and decrements per cycle depends on the type of encoding X1 X2 or X4 Figure 7 18 shows a quadrature cycle and the resulting increments and decrements for X1 encoding When channel A leads channel B the increment occurs on the rising edge of channel A When channel B leads channel A the decrement occurs on the falling edge of channel A Figure 7 18 X1 Encoding ChA ChB seed Counter Value 5 X 6 X 7 7 X 6 X 5 X2 Encoding The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A depending on which channel leads the other Each cycle results in two increments or decremen
51. signal is used to accurately synchronize modules using PXIe CLK100 along with those using PXI_CLK10 The PXI Express backplane is responsible for generating PXIe SYNC100 independently to each peripheral slot in a PXI Express chassis For more information refer to the PXI Express Specification at www pxisa org National Instruments 9 7 Chapter 9 Digital Routing and Clock Generation PXI_CLK10 PXI CLK10 is a common low skew 10 MHz reference clock for synchronization of multiple modules in a PXI measurement or control system The PXI backplane is responsible for generating PXI CLK10 independently to each peripheral slot in a PXI chassis Note PXI CLK10 cannot be used as a reference clock for X Series devices PXI Triggers A PXI chassis provides eight bused trigger lines to each module in a system Triggers may be passed from one module to another allowing precisely timed responses to asynchronous external events that are being monitored or controlled Triggers can be used to synchronize the operation of several different PXI peripheral modules On X Series devices the eight PXI trigger signals are synonymous with RTSI lt 0 7 gt Note that in a PXI chassis with more than eight slots the PXI trigger lines may be divided into multiple independent buses Refer to the documentation for your chassis for details PXI_STAR Trigger In a PXI Express system the Star Trigger bus implements a dedicated trigger line between the system t
52. the counter drives the pulse s on the Counter n Internal Output signal The Counter n Internal Output signal can be internally routed to be a counter timer input or an external source for AI AO DI or DO timing signals Routing Counter n Internal Output to an Output Terminal You can route Counter n Internal Output to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal All PFIs are set to high impedance at startup National Instruments 7 41 Chapter 7 Counters Frequency Output Signal The Frequency Output FREQ OUT signal is the output of the frequency output generator Routing Frequency Output to a Terminal You can route Frequency Output to any PFI lt 0 15 gt or PXIe DSTARC terminal All PFIs are set to high impedance at startup The FREQ OUT signal can also be routed to DO Sample Clock and DI Sample Clock Default Counter Timer Pinouts By default NI DAQmx routes the counter timer inputs and outputs to the PFI pins Refer to Table 7 9 for the default NI DAQmx counter timer outputs for PCI Express PXI Express USB Mass Termination and USB BNC devices Refer to Table 7 10 for the default NI DAQmx counter timer outputs for USB Screw Terminal devices Note NI USB BNC devices For NI USB BNC devices the default connector 0 pin number does not apply Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins
53. 14 1 and later X Series devices feature up to 208 analog input AJ channels up to four analog output AO channels up to 48 lines of digital input output DIO and four counters This chapter provides basic information you need to get started using your X Series device Installation Before installing your DAQ device you must install the software you plan to use with the device 1 Installing application software Refer to the installation instructions that accompany your software 2 Installing NI DAQmx The DAQ Getting Started guides packaged with NI DAQmx and also on ni com manual1s contain step by step instructions for installing software and hardware configuring channels and tasks and getting started developing an application 3 Installing the hardware Unpack your X Series device as described in the Unpacking section The DAQ Getting Started guides describe how to install PCI Express PXI Express and USB devices as well as accessories and cables Unpacking The X Series device ships in an antistatic package to prevent electrostatic discharge ESD ESD can damage several components on the device A Caution Never touch the exposed pins of connectors To avoid ESD damage in handling the device take the following precautions e Ground yourself with a grounding strap or by touching a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the device from the packag
54. 2 11 PFIO P1 0 D GND 10 PFI1 P1 1 PFI 2 P1 2 9 DGND PFI 3 P1 3 8 5v PFI 4 P1 4 7 D GND PFI 13 P2 5 6 PFI5 P1 5 PFI 15 P2 7 5 PFI 6 P1 6 PFI 7 P1 7 4 DG ND PFI 8 P2 0 3 PFI 9 P2 1 D GND 2 PFI 12 P24 D GND 1 PFI 14 P2 6 NC No Connect A 2 ni com X Series User Manual Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass a Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help NI 6320 Device Specifications Refer to the NJ 632x Specifications for more detailed information about the NI 6320 device NI 6320 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAO System Overview for more information National Instruments A 3 Appendix A NI 6321 6341 Device Specific Information The following sections contain information about the NI PCIe 6321 NI PCIe PXIe 6341 and NI USB 6341 devices NI 6321 6341 Pinouts Figure A 2 shows the pinout of the NI PCIe 6321 and NI PCIe PXIe 6341 devices For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 2 N
55. 32 Al GND P0 25 3 37 P0 24 Al2 Al2 65 31 Al 10 Al 2 S D GND 4 38 Po 23 AI GND 64 30 Al 3 Al 3 faj T P0 22 5 39 P0 31 Al 11 Al 3 63 29 A1 GND 5e 5 5 P0 21 6 40 P0 29 Al SENSE 62 28 Al 4 Al 4 m 3 w D GND 7 41 P0 20 Al 12 A14 61 27 AI GND 2 Zs 5V 8 42 P0 19 AI 5 Al 5 60 26 Al 13 Al 5 D GND 9 43 P0 18 AI GND 59 25 AI 6 AI 6 P0 17 10 44 D GND Al 14 Al 6 58 24 AI GND PO 16 11 45 P0 26 mono s6fz2 aoa rennais ER Bay TERMINAL 3S DO fastar roar P0 11 AO GND 55 21 AO1 TERMINAL 34 TERMINAL1 45V 14 48 P0 15 AO GND 54 20 NC D GND 1549 P0 10 D GND 53 19 P0 4 P0 14 16 50 D GND P0 0 52 18 D GND P0 9 17 51 P0 13 P0 5 51 17 PO 1 D GND 18 52 P0 8 D GND 50 16 P0 6 P0 12 19 53 D GND P0 2 49 15 D GND NC 20 54 AO GND PO 7 48 14 5V AO 3 21155 AO GND P03 all D GND TERMINAL 1 TERMINAL 34 AO 2 22156 A GND PFI 11 P2 3 46112 DGND TERMINAL 35 EI TERMINAL 68 AI 31 Al 23 23 57 Al 23 Al 23 PF110 P2 2 45 11 PFI 0 P1 0 AI GND 24 58 AI 30 Al 22 D GND 44 10 PFI 1 P1 1 Q Al 22 Al 22 25 59 Al GND PFI 2 P1 2 43 9 D GND NZ we Al 29 Al 21 26 60 Al 21 Al 21 PFI 3 P1 3 42 8 5V AI GND 27 61 Al 28 Al 20 PFI 4 P1 4 41 7 D GND Al 20 AI 20 28 62 Al SENSE 2 PFI 13 P2 5 40 6 PFI
56. 40 ni com X Series User Manual Using an Internal Source To use Counter n Sample Clock with an internal source specify the signal source and the polarity of the signal The source can be any of the following signals e DI Sample Clock di SampleClock e DO Sample Clock do SampleClock e AI Sample Clock ai SampleClock AI Convert Clock ai ConvertClock e AO Sample Clock ao SampleClock e DI Change Detection output Several other internal signals can be routed to Counter n Sample Clock through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source You can route any of the following signals as Counter n Sample Clock e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe_DSTAR lt A B gt e Analog Comparison Event You can sample data on the rising or falling edge of Counter n Sample Clock Routing Counter n Sample Clock to an Output Terminal You can route Counter n Sample Clock out to any PFI lt 0 15 gt terminal The PFI circuitry inverts the polarity of Counter n Sample Clock before driving the PFI terminal Counter n Internal Output and Counter n TC Signals The Counter n Internal Output signal changes in response to Counter n TC The two software selectable output options are pulse output on TC and toggle output on TC The output polarity is software selectable for both options With pulse or pulse train generation tasks
57. 47 A160 A1 52 AO GND 55 21 AO 9 aisialsis 14 48 also A1 51 AO GND 54 20 APFI0 Q Z AI58 A150 1549 also A1 50 D GND 53 19 P0 4 g Alaa Al49 16 50 A157 Al 49 P0 0 52 18 D GND e A148 A148 17 51 alse al 48 P0 5 51 17 Po z Z A47 A39 18 52 A1 30 AI 39 D GND 50 16 Poe z E A138 A1 38 19 53 A146 A138 P0 2 49 15 D GND S A137 Al 37 20 54 Al 45 Al 37 P0 7 48 14 45V 9 Al44 A136 21155 alae al 36 P0 3 47 13 D GND z AI GND 2256 Al SENSE 2 PFI 11 P2 3 46 12 D GND E amp E Al 35 AI 35 2357 A143 Al 35 PFI 10 P2 2 45 11 PFI 0 P1 0 A1 84 A1 34 24 58 Al 42 AI 34 D GND 44 10 PFI 1 P11 Al 41 Al33 25 59 A1 33 Al 334 Pri2Pt2 43 0 DGND A1 82 A182 26 60 A1 40 Al 32 prigp13 42 8 45v Al 23 Al 23 27 61 A131 Al 23 PFi4P14 41 7 DGND A180 Al 22 28 62 a122 Al 22 PFI 13 P2 5 40 6 PFI5 P1 5 A121 A121 29 63 A1 29 al 21 PFI 15 P2 7 39 5 PFI 6 P1 6 A1 20 AI 20 30 64 A1 28 al 20 Pr7piz 38 4 DGND A127 A119 31 65 A119 Al 194 PFI 8 P2 0 37 3 PFI 9 P2 1 Al 18 AI 18 32 66 Ai 26 al 18 D GND 36 2 PFI 12 P2 4 Al 17 Al 17 33 67 A125 A1 174 D GND 35 1 PFI 14 P2 6 Al 24 Al 16 34 68 al 16 AI 16 N oe A 12 ni com X Series User Manual Note Refer to Tab
58. 6 NC No Connect TERMINAL 68 TERMINAL 35 O CONNECTOR 0 Al 0 7 TERMINAL 34 TERMINAL 1 G4 National Instruments A 25 Appendix A Device Specific Information Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass a Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help A 26 ni com X Series User Manual Figure A 18 shows the pinout ofthe NI USB 6366 Mass Termination For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 18 NI USB 6366 Mass Termination Pinout i Al 0 68 34 Al 0 AI 0 GND 67 33 Al 1 Al 1 66 32 Al 1 GND Al 2 65 31 Al 2 Al 2 GND 64 30 Al 3 Al 3 63 29 Al3 GND NC 62 28 Al 4 Al 4 61 27 Al4 GND Al 5 60 26 Al 5 Al 5 GND 59 25 Al 6 Al 6 58 24 Al6 GND Al 7 57 23 Al 7 Al 7 GND 56 22 AOO AO GND 55 21 AO1 AO GND 54 20 APFIO D GND 53 19 PO 4 P0 0 52 18 D GND POS 51 17 Pot D GND 50 16 P0 6 P0 2 49 15 D GND PO 7 48
59. 7 39 Counter n Z signal 7 39 counter signals Counter n A 7 39 Counter n Aux 7 38 Counter n B 7 39 Counter n Gate 7 38 Counter n HW Arm 7 40 Counter n Internal Output 7 41 Counter n Source 7 37 Counter n TC 7 41 Counter n Up_Down 7 39 X Series User Manual FREQ OUT 7 42 Frequency Output 7 42 counters 7 1 cascading 7 45 connecting terminals 7 42 edge counting 7 3 generation 7 26 input applications 7 3 other features 7 45 output applications 7 26 prescaling 7 46 pulse train generation 7 28 retriggerable single pulse generation 7 29 simple pulse generation 7 27 single pulse generation 7 27 single pulse generation with start trigger 7 27 synchronization modes 7 46 timing signals 7 36 triggering 7 45 troubleshooting C 2 counting edges 7 3 crosstalk when sampling multiple channels C 1 CtrnSampleClock 7 40 custom cabling 2 7 D DACs 5 1 DAQ hardware 2 2 system 2 1 DAQ 6202 2 2 DAQ STC3 2 2 data acquisition methods Simultaneous MIO X Series devices 4 38 generation methods 5 3 transfer methods DMA 10 1 programmed I O 10 2 USB Signal Stream 10 2 National Instruments 1 5 Index data acquisition methods MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 DC coupling connections Simultaneous MIO X Series devices 4 43 default counter terminals 7 42 NI DAQmx counter timer pins 7 42 pins 7 42 desktop use 1 5 device information A 1 multiple sy
60. A 10 shows the pinout of the NI USB 6351 6361 Screw Terminal For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 10 NI USB 6351 6361 Screw Terminal Pinout 0 Al 0 8 Al 0 GND 1 Al 14 9 Al 1 GND 2 Al 2 10 Al 2 GND 3 Al 3 11 Al 3 GND SENSE GND AO 0 AO GND gt gt gt DL gt gt gt gt gt gt 4 Note Refer to Table 7 10 X Series USB Screw Terminal Device Default i 2 3 4 5 6 7 8 9 10 11 BO2DOOOODODODDO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Al 4 AI 4 AI 12 Al 4 AI GND AI 5 Al 5 Al 13 AI 5 AI GND AI 6 Al 6 Al 14 AI 6 AI GND AI 7 Al 7 Al 15 AI 7 AI GND APFI O AI GND AO 1 AO GND P0 0 PO 1 PO 2 P0 3 P0 4 PO 5 PO 6 PO 7 PFI 0 P1 0 PFI 1 P1 1 PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 5 P1 5 PFI 6 P1 6 PFI 7 P1 7 _ S NI S X S S NI SI Ss S S 5 S NI SI 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 BO2DOOOODODODDO 89 90 91 92 93 94 95 96 PFI 8 P2 0 D GND PFI 9 P2 1 D GND PFI 10 P2 2 D GND PFI 11 P2 3 D GND PFI 12 P2 4 D GND PFI 13 P2 5 D GND PFI 14 P2 6 D GND
61. AI 1 32 Al GND Al 25 Al 17 32 Al GND Al 2 Al 2 31 Al 10 Al 2 Al 18 Al 18 31 Al 26 Al 18 Al GND 30 Al 3 AI 3 Al GND 30 AI 19 Al 19 Al 11 Al 3 29 Al GND AI 27 AI 19 29 AI GND AI SENSE 28 Al 4 Al 4 Al SENSE 2 28 Al 20 Al 20 Al 12 Al 4 27 AlGND Al 28 Al 20 27 AlGND AI 5 Al 5 26 Al 13 Al 5 Al 21 Al 21 26 Al 29 Al 21 Al GND 25 Al 6 Al 6 Al GND 25 Al 22 Al 22 Al 14 AI 6 24 Al GND Al 30 Al 22 24 Al GND AI 7 Al 7 23 Al 15 Al 7 Al 23 AI 23 23 AI 31 Al 23 AI GND 22 AOO AI GND 22 AO2 AO GND 21 AO 1 AO GND 21 AO 3 AO GND 20 APFIO AO GND 20 APFI 1 D GND 19 P0 4 D GND 19 PO 12 P0 0 18 D GND PO 8 18 D GND POS 17 PO P0 13 17 P0 9 D GND 16 P0 6 D GND 16 PO 14 P0 2 15 D GND P0 10 15 D GND PO 7 1411 5V PO 15 14 5V P0 3 13 D GND PO 11 13 D GND PFI 11 P2 3 12 D GND P0 27 12 D GND PFI 10 P2 2 11 PFI 0 P1 0 P0 26 11 P0 16 D GND 10 PFI1 P1 1 D GND 10 NEO PFI 2 P1 2 9 D GND P0 18 9 D GND PFI 3 P1 3 8 5V P0 19 8 5V PFI 4 P1 4 7 D GND P0 20 7 D GND PFI 13 P2 5 6 PFI 5 P1 5 P0 29 6 P0 21 PEIS P27 5 PFI 6 P1 6 P0 31 5 P0 22 PFI 7 P1 7 4 D GND P0 23 4 D GND PFI 8 P2 0 3 PFI 9 P2 1 P0 24 3 P0 25 D GND 2 PFI 12 P2 4 D GND 2 P0 28 D GND 1 PFI 14 P2 6 D GND 1 P0 30 CONNECTOR 0 CONNECTOR 1 Al 0 15 Al 16 31 TERMINAL 34 TERMINAL 1 TERMINAL 34 TERMINAL 1 er vO am
62. Al GND Using Non Referenced Single Ended NRSE Connections for Floating Signal Sources It is important to connect the negative lead ofa floating signals source to AI GND either directly or through a resistor Otherwise the source may float out of the valid input range of the NI PGIA and the DAQ device returns erroneous data Note NIUSB 6341 6343 6361 6363 BNC Devices To measure a floating signal source on X Series USB BNC devices move the switch under the BNC connector to the FS position Figure 4 8 shows a floating source connected to the DAQ device in NRSE mode Figure 4 8 NRSE Connections for Floating Signal Sources Floating Signal Vs 9 Source o o Al SENSE Sr MIO X Series Device Al Al GND All of the bias resistor configurations discussed in the Using Differential Connections for Floating Signal Sources section apply to the NRSE bias resistors as well Replace AI with AI SENSE in Figures 4 4 4 5 4 6 and 4 7 for configurations with zero to two bias resistors The noise rejection of NRSE mode is better than RSE mode because the AI SENSE connection is made remotely near the source However the noise rejection of NRSE mode is worse than DIFF mode because the AI SENSE connection is shared with all channels rather than being cabled in a twisted pair with the AI signal 4 16 ni com X Series User Manual Using t
63. Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter and saving the counter contents Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal Any of the following signals can be routed to the Counter n Gate input e RTSI lt 0 7 gt e PFI lt 0 15 gt Al Reference Trigger ai ReferenceTrigger AI Start Trigger ai StartTrigger e AO Sample Clock ao SampleClock e DI Sample Clock di SampleClock DI Reference Trigger di ReferenceTrigger e DO Sample Clock do SampleClock e PXI STAR e PXIe DSTAR lt A B gt Change Detection Event e Analog Comparison Event In addition a counter s Internal Output or Source can be routed to a different counter s gate Some of these options may not be available in some driver software Routing Counter n Gate to an Output Terminal You can route Counter n Gate out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal All PFIs are set to high impedance at startup Counter n Aux Signal The Counter n Aux signal indicates the first edge in a two signal edge separation measurement 7 88 ni com X Series User Manual Routing a Signal to Counter n Aux Each counter has independent input selectors for the Counter n Aux signal Any of the following signals can be routed to the Counter n Aux input e RTSI lt 0 7 gt e PFI l
64. Instruments 6 1 Chapter 6 Digital 1 O The voltage input and output levels and the current drive levels ofthe DIO lines are listed in the specifications of your device Digital Input Data Acquisition Methods When performing digital input measurements you either can perform software timed or hardware timed acquisitions Software Timed Acquisitions With a software timed acquisition software controls the rate of the acquisition Software sends a separate command to the hardware to initiate each acquisition In NI DAQmx software timed acquisitions are referred to as having on demand timing Software timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data Each of the X Series DIO lines can be used as a static DI or DO line You can use static DIO lines to monitor or control digital signals Each DIO can be individually configured as a digital input DD or digital output DO All samples of static DI lines and updates of static DO lines are software timed Hardware Timed Acquisitions With hardware timed acquisitions a digital hardware signal di SampleClock controls the rate of the acquisition This signal can be generated internally on your device or provided externally Hardware timed acquisitions have several advantages over software timed acquisitions The time between samples can be much shorter e The timing between samples is determinist
65. LA M De pn TTL Signal Switch di D GND 1 0 Connector T X Series Device A Caution Exceeding the maximum input voltage ratings which are listed in the specifications document for each X Series device can damage the DAQ device and the computer NI is not liable for any damage resulting from such signal connections National Instruments 6 23 Chapter 6 Digital I O Getting Started with DIO Applications in Software You can use the X Series device in the following digital I O applications e Static digital input e Static digital output e Digital waveform generation e Digital waveform acquisition e DI change detection DE Note For more information about programming digital I O applications and triggers in software refer to the NJ DAQmx Help or the LabVIEW Help X Series devices use the NI DAQmx driver NI DAQmx includes a collection of programming examples to help you get started developing an application You can modify example code and save it in an application You can use examples to develop a new application or add example code to an existing application To locate LabVIEW LabWindows CVI Measurement Studio Visual Basic and ANSI C examples refer to the KnowledgeBase document Where Can I Find NI DAQmx Examples by going to ni com info and entering the Info Code daqmxexp For additional examples refer to ni com examples 6 2
66. MIO X Series devices 4 7 Z behavior 7 22 channels analog input 11 3 sampling with AI Sample Clock and AI Convert Clock C 2 charge injection C 1 choosing frequency measurement 7 16 CHS GND screw terminal 1 3 circular buffered acquisition MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 39 clock 10 MHz reference 9 3 external reference 9 2 generation 9 1 PXI PXI Express and trigger signals 9 7 routing 9 1 common mode noise differential ground referenced signals Simultaneous MIO X Series devices 4 42 differential non referenced or floating signals Simultaneous MIO X Series devices 4 44 differential signals Simultaneous MIO X Series devices 4 42 signal rejection considerations differential ground referenced signals Simultaneous MIO X Series devices 4 42 configuring AI ground reference settings in software MIO X Series devices 4 6 Simultaneous MIO X Series devices 4 54 connecting analog input signals MIO X Series devices 4 10 l 4 nicom analog output signals 5 5 counter signals C 2 digital I O signals 6 23 floating signal sources MIO X Series devices 4 12 ground referenced signal sources MIO X Series devices 4 17 PFI input signals 8 4 connecting signals analog input Simultaneous MIO X Series devices 4 41 connections differential for floating signal sources MIO X Series devices 4 17 differential for ground referenced signal sources Simultaneous MIO X Series devices
67. MIO X Series Interval Sampling Channel 0 Channel 1 lt Convert Period lt Sample Period gt AI Convert Clock controls the Convert Period which is determined by the following equation 1 Convert Period Convert Rate 4 22 ni com X Series User Manual Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 14 The sample counter is loaded with the specified number of posttrigger samples in this example five The value decrements with each pulse on AI Sample Clock until the value reaches zero and all desired samples have been acquired Figure 4 14 Posttriggered Data Acquisition Example Al Start Trigger Al Sample Clock AI Convert Clock M i Sample Counter 4 3 2 1 0 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 15 shows a typical pretriggered DAQ sequence AI Start Trigger ai StartTrigger can be either a hardware or software signal If AI Start Trigger is set up to be a software start trigger an output pulse appears on the ai StartTrigger line when the acquisition begins When the AI Start Trigger pulse occurs the sample counter is loaded with the number of pretriggered samples in this ex
68. MIO X Series devices 4 13 using in NRSE mode MIO X Series devices 4 16 using in RSE mode MIO X Series devices 4 17 when to use in differential mode MIO X Series devices 4 12 when to use in NRSE mode MIO X Series devices 4 12 when to use in RSE mode MIO X Series devices 4 13 FREQ OUT signal 7 42 frequency division 7 35 generation 7 34 generator 7 34 measurement 7 11 Frequency Output signal 7 42 G generations analog output data 5 3 buffered hardware timed 5 3 6 12 clock 9 1 continuous pulse train 7 30 digital waveform 6 13 frequency 7 34 hardware timed 5 3 6 11 hardware timed single point 5 3 6 3 6 11 pulse for ETS 7 35 pulse train 7 28 retriggerable single pulse 7 29 simple pulse 7 27 single pulse 7 27 National Instruments 1 7 Index single pulse with start trigger 7 27 software timed 5 3 6 11 getting started 1 1 AI applications in software MIO X Series devices 4 35 AO applications in software 5 10 DIO applications in software 6 24 ghost voltages when sampling multiple channels C 1 Ground 4 41 ground reference connections checking C 1 settings analog input MIO X Series devices 4 3 MIO X Series devices 4 1 4 3 ground referenced signal sources connecting MIO X Series devices 4 17 description MIO X Series devices 4 17 using in differential mode MIO X Series devices 4 19 using in NRSE mode MIO X Series devices 4 20 when to use in differential mode MI
69. NAT a E ner detente dite 2 2 DAQ STC3 2 2 Calibration Circuitry 2 3 Cables and ACCesSOnes aire mnt friandises ts n 9e 2 3 PCI Express PXI Express and USB Mass Termination Device Cables and ACCESSOFIES s stehsiehcsnceneisrssaandan contacs cons EE E aban aaee 2 4 SCX ACCOSSOTES sense its etes 2 4 SCC Accessories 2 4 BNC Accessories 2 5 Screw Terminal Accessories 2 5 RTSI Cablesisssessnsssnihihihinenedrssnnieet lites 2 6 Cables en hale tae ne MN ea ne nie NA se 2 6 Custom Cabling and Connectivity ss 2 7 USB Device Accessories USB Cable Power Supply and Ferrite 2 7 Signal Conditioning ss es Men Ra hese a a r Ene Ea Sensors and Transducers National Instruments v Contents Chapter 3 Connector and LED Information VO Connector Signal Descriptions 3 2 S V Power SOUTCE LL SR RS A en TR ARTS 3 4 USER kand USER Z horie arenae se ni cad dire drone te SE A tes enceinte AY 3 5 PCI Express Device Disk Drive Power Connector 3 5 When to Use the Disk Drive Power Connector 3 5 Disk Drive Power Connector Installation 3 6 RTSLCorinector PINOUt 22 esnan Mimet der tete te Mesrine M INT inate tte 3 6 USB Devic e LED Pattes sisi en ere tue 3 7 Chapter 4 Analog Input Analog Input on MIO X Series Devices 4 1 Analog Input Range 4 2 Working Voltage Rangers Min ie Glace eens 4 3 Analog Input Ground Reference Settings 4 3 Configuri
70. Pee AI3 Al3 10 IS QE A119 A119 42 I A anasa nS S27 AS I7 aaan asl Kl DIS AS A2 Al GND 21 KS Spee AN AI GND 44 S SI Arano AISENSE 13 S Gp 22 47510 AISENSE2 45 I St API AI GND 14 I Sj 20 A eno AI GND 46 I Sf 62 Arann noe HIS S 22 0 GND 47 IS S GN AOGND _ 16 AO GND 48S ooe ee ooo ros oT ie ban PO 1 66 IK P0 9 98 S P02 67 IS SI 83 PFI 9 P2 1 Poio sol IS SI 115 Po 25 P0 3 IS SI PSN Pott 100 Kl 116 D enD P0 4 69 II S 85 PF 10 P2 2 P012 101 KI SI 117 Poz6 PO 5 70 S SI 2 enD Pots 102 Sip 8 DGND P0 6 alls SI 87 PFI 11 P2 3 Poa 103 S SI 119 Po 27 PO 7 72 S 8 D enD Pois 104 KSI SI 120 Dano prapto zasl SE Prt 12724 pots 105 IIT SI 12 P028 pripi zal S99 D ND Po17 106 9 Si 122 DGND priapt gt 75 9 SI 91 PFI 13 P2 5 pois 107 S Gl 123 Po 29 Prisi 76 Sj 22 D GND Pois 108 9 SI 124 DGND PFi4Pi4 77 S SI 98 PFI 14 P2 6 SETA S SI 125 Po 30 prisipt s 78 Sj 24 D GND Pozi 110 9 Si 126 DGND prieipi6 79 ISI S 98 PF 15P27 roo til SI SI 127 Post PFI7 P1 7 80 X NE poz3 112 IS SI 128 D GND A 22 ni com X Series User Manual Note Refer to Table 7 10 X Series USB Screw Terminal Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW
71. RTSI lt 0 7 gt e Analog Comparison Event Change Detection Event e Watchdog timer expired pulse Note Signals with an are inverted before being driven to a terminal that is these signals are active low Using PFI Terminals as Static Digital I Os Each PFI can be individually configured as a static digital input or a static digital output When a terminal is used as a static digital input or output it is called P1 x or P2 x On the I O connector each terminal is labeled PFI x P1 x or PFI x P2 x In addition X Series devices have up to 32 lines of bidirectional DIO signals Using PFI Terminals to Digital Detection Events Each PFI can be configured to detect digital changes The values on the PFI lines cannot be read in a hardware timed task but they can be used to fire the change detection event For example if you wanted to do change detection on eight timed DIO lines but wanted to ensure that the value of the lines was updated every second independent of the eight lines changing you could set a PFI line up for change detection and connect a 1 Hz signal to it National Instruments 8 3 Chapter 8 PFI Connecting PFI Input Signals All PFI input connections are referenced to D GND Figure 8 2 shows this reference and how to connect an external PFI 0 source and an external PFI 2 source to two PFI terminals Figure 8 2 PFI Input Signal Connections PFIO PEI 2
72. Reference Clock Synchronizing Multiple Devices PXI Express D vices sisien iii dunia paneled dean bane PCLExpress D vites nn nn en ee ee net A E E T i WSB Devices npr hennen eena seseo EE eE Ea rS rs Me dr ire Real Time System Integration RTSI 9 4 RISI Connector Pinout isese An MDN AM UE a eae 9 5 Using RIST as Outputs oncer in aE E A EEE 9 6 Using RTSI Terminals as Timing Input Signals 9 6 RESI Filtern iivit renait e A E MINI EN Ge ae ees 9 7 PXI and PXI Express Clock and Trigger Signals e ssssssssesesseseseesrsessesesesstsesreessesesseses 9 7 PXTE CLR TOO Sn aa t EE votes A RE E NET 9 7 PXle SYNC OO cicccciccsccorcstucecunecgeessincnteantacesvnccouesecatsteranstoussesteveusvenresvivesscstehecderesetee 9 7 PXI CLK I Opina ee spa cvasesdoussdds ccuecdsctecubsvesbuceuet poets ins onadasca a 9 8 PRACT PS CLS ororena nn net ne onan tan met sn enr nt 9 8 PXI STAR Tripper item AR es don Mes Rte tt eee 9 8 PXI STAR Filters Dore EN ET rh ons ee 9 8 PXIS DSTARSA Ce nee tate a A ren E os Basse ner 9 8 Chapter 10 Bus Interface Data Transfer M thods inbena isnie reen Er EE E EEE iae 10 1 PCI Express PXI Express Device Data Transfer Methods 10 1 USB Device Data Transfer Methods 0 0 0 0 cece seesssesesseeseseesceeeeseseeeceaesseecseseeseens 10 2 PXI Express Considerations sense 10 2 PXI and PXI Express Clock and Trigger
73. Simultaneous MIO X Series Devices Analog Input Rate Simultaneous MIO X Series Device Single Channel Total Aggregate NI 6356 1 25 MS s 10 MS s NI 6358 1 25 MS s 20 MS s NI 6366 2 MS s 16 MS s NI 6368 2 MS s 32 MS s Note On Simultaneous MIO X Series devices each channel has an ADC so each channel can be acquired at the maximum single channel rate Al Sample Clock Signal Use the AI Sample Clock ai SampleClock signal to initiate a set of measurements Your Simultaneous MIO X Series device samples the AI signals of every channel in the task once for every AI Sample Clock A measurement acquisition consists of one or more samples You can specify an internal or external source for AI Sample Clock You can also specify whether the measurement sample begins on the rising edge or falling edge of AI Sample Clock National Instruments 4 47 Chapter 4 Analog Input Using an Internal Source One of the following internal signals can drive AI Sample Clock e Counter n Internal Output e AI Sample Clock Timebase divided down A pulse initiated by host software Change Detection Event e Counter n Sample Clock e DI Sample Clock di SampleClock e AO Sample Clock ao SampleClock e DO Sample Clock do SampleClock A programmable internal counter divides down the sample clock timebase Several other internal signals can be routed to AI Sample Clock through internal routes Refer to
74. Simultaneous MIO X Series device Figure 4 27 Differential Connection for Floating Signals on Simultaneous MIO X Series Devices ols Simultaneous X Series Device AIO Instrumentation Amplifier Measured Voltage AlO Floating y Signal Vs Source A Bias Resistors pel Current Return Paths m Al 0 GND V AI 0 Connections Shown 1 0 Connector A Note NI USB 6356 6366 BNC Devices To measure a floating signal source on X Series USB BNC devices move the switch under the BNC connector to the FS position Figure 4 27 shows bias resistors connected between AI 0 AI 0 and the floating signal source ground These resistors provide a return path for the bias current A value of 10 kQ to 100 kQ is usually sufficient If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the instrumentation amplifier which saturates the instrumentation amplifier causing erroneous readings You must reference the source to the respective channel ground DC Coupled You can connect low source impedance and high source impedance DC coupled sources e Low Source Impedance You must reference the source to AI GND The easiest way to make this reference is to connect the positive side of the signal to the positive input of the instrumentation amplifier and connect the negative side of the sign
75. Start Trigger do StartTrigger e AO Start Trigger ao StartTrigger The source can also be one of several internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the measurement acquisition stops on the rising edge or falling edge of AI Reference Trigger Using an Analog Source When you use an analog trigger source the acquisition stops on the first rising edge of the Analog Comparison Event signal Routing Al Reference Trigger Signal to an Output Terminal You can route AI Reference Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt PXI Trig lt 0 7 gt or PXIe DSTARC terminal All PFI terminals are configured as inputs by default Al Pause Trigger Signal Use the AI Pause Trigger ai PauseTrigger signal to pause and resume a measurement acquisition The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low as shown in Figure 4 24 In the figure T represents the period and A represents the unknown time between the clock pulse and the posttrigger National Instruments 4 33 Chapter 4 Analog Input Figure 4 24 Halt Internal Clock and Free Running External Clock A T A T E Al Sample Clock
76. X Series User Manual source connected to channel 1 is high enough the resulting reading of channel 1 can be partially affected by the voltage on channel 0 This effect is referred to as ghosting If your source impedance is high you can decrease the scan rate to allow the NI PGIA more time to settle Another option is to use a voltage follower circuit external to your DAQ device to decrease the impedance seen by the DAQ device Refer to the KnowledgeBase document Decreasing the Source Impedance of an Analog Input Signal by going to ni com info and entering the Info Code rdbbis Use Short High Quality Cabling Using short high quality cables can minimize several effects that degrade accuracy including crosstalk transmission line effects and noise The capacitance of the cable can also increase the settling time National Instruments recommends using individually shielded twisted pair wires that are 2 m or less to connect AI signals to the device Refer to the Connecting Analog Input Signals section for more information Carefully Choose the Channel Scanning Order e Avoid Switching from a Large to a Small Input Range Switching from a channel with a large input range to a channel with a small input range can greatly increase the settling time Suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 The input range for channel 0 is 10 V to 10 V and the input range of channel 1 is 200 mV to 200 mV
77. acquisition to stop e When a certain number of points are sampled in finite mode e After a hardware reference trigger in finite mode e With a software command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition Retriggerable DI The DI Start Trigger is configurable as retriggerable When the DI Start Trigger is configured as retriggerable the timing engine generates the sample and convert clocks for the configured acquisition in response to each pulse on a DI Start Trigger signal The timing engine ignores the DI Start Trigger signal while the clock generation is in progress After the clock generation is finished the timing engine waits for another Start Trigger to begin another clock generation Figure 6 4 shows a retriggerable DI of four samples o1sanp cet L L LL NT Note Waveform information from LabVIEW does not reflect the delay between triggers They are treated as a continuous acquisition with constant t0 and dt information Figure 6 4 Retriggerable DI Reference triggers are not retriggerable Using a Digital Source To use DI Start Trigger with a digital source specify a source and an edge The source can be any of the following signals PFI lt 0 15 gt RTSI lt 0 7 gt e Counter n Internal Output National Instruments 6 7 Chapter 6 Digital I O e PXI STAR e PXIe DSTAR l
78. addition to training and certification programs that meet your needs during each phase of the application life cycle from planning and development through deployment and ongoing maintenance To get started register your product at ni com myproducts As a registered NI product user you are entitled to the following benefits e Access to applicable product services e Easier product management with an online account e Receive critical part notifications software updates and service expirations Log in to your National Instruments ni com User Profile to get personalized access to your services Services and Resources e Maintenance and Hardware Services NI helps you identify your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system Visit ni com services for more information Warranty and Repair All NI hardware features a one year standard warranty that is extendable up to five years NI offers repair services performed in a timely manner by highly trained factory technicians using only original parts at a National Instruments service center Calibration Through regular calibration you can quantify and improve the measurement performance of an instrument NI provides state of the art calibration services If your product supports calibration you can obtain the calibration certific
79. application software package and driver includes information about writing applications for taking measurements and controlling measurement devices The following references to documents assume you have NI DAQm x 14 1 or later X Series Documentation The X Services device specifications are available for download at ni com manuals NI DAQmx The N DAQmx Readme lists which devices ADEs and NI application software are supported by this version of NI DAQmx Select Start All Programs National Instruments NI DAQmx NI DAQm x Readme The N DAQmx Help contains API overviews general information about measurement concepts key NI DAQmx concepts and common applications that are applicable to all programming environments Select Start All Programs National Instruments NI DAQmx NI DAQm x Help National Instruments B 1 Appendix B Where to Go from Here LabVIEW Refer to ni com gettingstarted for more information about getting started with LabVIEW Use the LabVIEW Help available by selecting Help LabVIEW Help in LabVIEW to access information about LabVIEW programming concepts step by step instructions for using LabVIEW and reference information about LabVIEW VIs functions palettes menus and tools Refer to the following locations on the Contents tab of the LabVIEW Help for information about NI DAQmx VI and Function Reference Measurement I O VIs and Functions DAQm x Data Acquisition VIs and Functions Descri
80. com NI 6356 6366 X Series User Manual The following sections contain information about the NI PXIe 6356 NI USB 6356 NI PXIe 6366 and NI USB 6366 devices NI 6356 6366 Pinouts Figure A 17 shows the pinout of the NI PXIe 6356 6366 For a detailed description of each signal refer to the 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 17 NI PXle 6356 6366 Pinout 0 0 GND 1 2 2 GND as C 5 5 GND 7 7 GND AO GND AO GND D GND P0 0 P0 5 D GND P0 2 PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 P PI PI PI gt gt gt gt gt Z gt gt gt gt gt gt FI 4 P1 4 FI 13 P2 5 FI 15 P2 7 FI 7 P1 7 PFI 8 P2 0 D GND D GND wa 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 12 45 11 44 10 43 42 41 40 39 38 37 36 35 sIDIoIBR u o o o a 1 1 GND Q 3 3 GND 4 4 GND 5 6 6 GND 7 a R gt gt gt gt gt ad gt O o AO 1 APFI 0 P0 4 D GND PO 1 PO 6 D GND 5V D GND D GND PFI 0 P1 0 REIM PAE D GND 5V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2
81. connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 22 NI PXle 6365 Connector 2 Pinout P D DD DD DD DD pp pp pp pp pp ppp gt ppp gt gt gt gt gt 80 89 Al 80 Al 81 90 AI 82 83 AI 83 92 AI 84 98 AI 85 86 AI 86 95 AI 87 104 Al 96 97 Al 97 106 Al 98 107 Al 99 SENSE 3 100 Al 100 109 Al 101 110 Al 102 103 Al 103 120 Al 112 121 Al 113 114 Al 114 123 Al 115 124 Al 116 117 Al 117 126 AI 118 127 AI 119 GND 128 137 138 131 140 141 134 143 Al 128 Al 129 Al 130 Al 131 Al 132 Al 133 Al 134 Al 135 Al 88 Al 81 Al 82 Al 91 Al 84 Al 85 Al 80 Al 81 Al 82 Al 83 Al 84 Al 85 Al 94 AI 86 Al 87 Al 87 Al 96 Al 96 Al 105 Al 97 Al 98 Al 98 Al 99 Al 99 Al GND Al 108 Al 101 Al 102 Al 111 Al 112 Al 113 Al 122 Al 115 Al 116 Al 125 Al 118 Al 119 Al GND Al 136 Al 129 Al 130 Al 139 Al 132 Al 133 Al 142 Al 135 Al 100 Al 101 Al 102 Al 103 Al 112 Al 113 Al 114 Al 115 Al 116 Al 117 Al 118 Al 119 Al 128 Al 129 Al 130 Al 131 Al 132 Al 133 Al 134 Al 135 Ev L 08 IV Z HOLOANNOO Ge National Instruments A 33 Appendix A Device Specifi
82. counter timing engine on your device internally generates AI Sample Clock unless you select some external source AI Start Trigger starts this counter and either software or hardware can stop it once a finite acquisition completes When using the AI timing engine you can also specify a configurable delay from AI Start Trigger to the first AI Sample Clock pulse By default this delay is set to two ticks of the AI Sample Clock Timebase signal National Instruments 4 25 Chapter 4 Analog Input When using an externally generated AI Sample Clock you must ensure the clock signal is consistent with respect to the timing requirements of AI Convert Clock Failure to do so may result in a scan overrun and will cause an error Refer to the AJ Convert Clock Signal section for more information about the timing requirements between AI Convert Clock and AI Sample Clock Figure 4 16 shows the relationship of AI Sample Clock to AI Start Trigger Figure 4 16 Al Sample Clock and Al Start Trigger Al Sample Clock Timebase Al Start Trigger Al Sample Clock Delay From Start Trigger Al Sample Clock Timebase Signal You can route any of the following signals to be the AI Sample Clock Timebase ai SampleClockTimebase signal e 100 MHz Timebase default 20 MHz Timebase e 100 kHz Timebase PXI CLK10 RTSI lt 0 7 gt PFI lt 0 15 gt e PXI STAR e PXIe DSTAR lt A B gt
83. document for your device Triggering with a Digital Source Your DAQ device can generate a trigger on a digital signal You must specify a source and an edge The digital source can be any of the PFI RTSI or PXI STAR signals The edge can be either the rising edge or falling edge of the digital signal A rising edge is a transition from a low logic level to a high logic level A falling edge is a high to low transition Figure 11 1 shows a falling edge trigger Figure 11 1 Falling Edge Trigger 5V Digital Trigger OV Falling Edge Initiates Acquisition You can also program your DAQ device to perform an action in response to a trigger from a digital source The action can affect the following e Analog input acquisition e Analog output generation e Counter behavior e Digital waveform acquisition and generation National Instruments 11 1 Chapter 11 Triggering Triggering with an Analog Source Some X Series devices can generate a trigger on an analog signal To find your device triggering options refer to the specifications document for your device Figure 11 2 shows the analog trigger circuit on MIO X Series devices Figure 11 2 MIO X Series Device Analog Trigger Circuit Analog e Input e ADC Channels e Al Circuitry Analog Comparison Analog Event gt AO Circuitry Trigger APFI lt 0 1 gt Detection Analog Trigger DIO Circuitry Circuitry Output
84. for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments AS Appendix A Device Specific Information Figure A 4 shows the pinout of the NI USB 6341 BNC For a detailed description of each signal refer to the I O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 4 NI USB 6341 BNC Pinout E gt gt DGND PFI 8 P20 PFI 9P2 1 PFI 10 P22 PFI 11 P2 3 Floating Source FS Ground Ref Source GS D GND PFI 12 P24 PFI 13 P2 5 PFI 14 P2 6 PFI 15 P27 D GND USER 1 USER 2 i RE ANALOG INPUT a 2 be 5 Bt USER ACCESS mumm SSS RS NALOG OUTPUT SSSR ja HABRAR AR ARBAB BEBRBRRRR ARAB RBG 00000000000000000000000000000 D GND e 5V g AIGND PFI 0 P1 0 PFIUPIA PFI 2 P1 2 PFI3 P13 AI SENSE 2 NC NC 5 CHS GND a I PFI AIPA PFI 5 P1 5 PFI 6 P1 6 PFI TPIT asen power ive siete aie ae X Series Multifunction DAQ Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Coun
85. for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the device are greater than 3 m 10 ft The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Two analog input channels AI and Al are available for the signal DIFF signal connections reduce noise pickup and increase common mode noise rejection DIFF signal connections also allow input signals to float within the common mode limits of the NI PGIA Refer to the Using Differential Connections for Floating Signal Sources section for more information about differential connections When to Use Non Referenced Single Ended NRSE Connections with Floating Signal Sources Only use NRSE input connections if the input signal meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 3 m 10 ft DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions In the single ended modes more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of
86. gt e Analog Comparison Event an analog trigger Routing DO Sample Clock to an Output Terminal You can route DO Sample Clock as an active low signal out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal Other Timing Requirements The DO timing engine on your device internally generates DO Sample Clock unless you select some external source DO Start Trigger starts the timing engine and either the software or hardware can stop it once a finite generation completes When using the DO timing engine you can also specify a configurable delay from DO Start Trigger to the first DO Sample Clock pulse By default this delay is two ticks of DO Sample Clock Timebase Figure 6 7 shows the relationship of DO Sample Clock to DO Start Trigger Figure 6 7 DO Sample Clock and DO Start Trigger DO Sample Clock Timebase DO Start Trigger DO Sample Clock Start Trigger 6 14 ni com X Series User Manual DO Sample Clock Timebase Signal The DO Sample Clock Timebase do SampleClockTimebase signal is divided down to provide a source for DO Sample Clock You can route any of the following signals to be the DO Sample Clock Timebase signal e 100 MHz Timebase default e 20 MHz Timebase e 100 kHz Timebase e PXI CLKI10 e PFI lt 0 15 gt RTSI lt 0 7 gt PXI STAR e PXIe DSTAR lt A B gt Analog Comparison Event an analog trigger DO Sample Clo
87. gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt Change Detection Event e Counter n Internal Output Al Reference Trigger ai ReferenceTrigger e AO Start Trigger ao StartTrigger e DO Start Trigger do StartTrigger The source can also be one of several internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the measurement acquisition stops on the rising or falling edge or falling edge of DI Reference Trigger Using an Analog Source When you use an analog trigger source the acquisition stops on the first rising edge of the Analog Comparison Event signal Routing DI Reference Trigger Signal to an Output Terminal You can route DI Reference Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt PXI Trig lt 0 7 gt or PXIe DSTARC terminal All PFI terminals are configured as inputs by default National Instruments 6 9 Chapter 6 Digital I O DI Pause Trigger Signal You can use the DI Pause Trigger di PauseTrigger signal to pause and resume a measurement acquisition The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low as shown in Figure 6 6 In the figure T represents the period and A represents the unknown time between the clock pulse and the posttrigger F
88. how much the electric field differs between the two conductors With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground Refer to the Using Non Referenced Single Ended NRSE Connections for Floating Signal Sources section for more information about NRSE connections 4 12 ni com X Series User Manual When to Use Referenced Single Ended RSE Connections with Floating Signal Sources Only use RSE input connections if the input signal meets the following conditions e The input signal can share a common reference point AI GND with other signals that use RSE e The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 3 m 10 ft DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions In the single ended modes more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between t
89. input NI DAQmx configures Counter 1 to perform a single pulse width measurement Suppose the result is that the pulse width is J periods of the fk clock From Counter 0 the length of the pulse is N fx From Counter 1 the length of the same pulse is J fk Therefore the frequency of fx is given by fx fk N J Sample Clocked Buffered Frequency Measurement Sample clocked buffered point frequency measurements can either be a single frequency measurement or an average between sample clocks Use CI Freq EnableAveraging to set the behavior For buffered frequency the default is True For hardware timed single point AWTSP the default is False A sample clocked buffered frequency measurement with CI Freq EnableAveraging set to True uses the embedded counter and a sample clock to perform a frequency measurement For each sample clock period the embedded counter counts the signal to measure fx and the primary counter counts the internal time base of a known frequency fk Suppose T1 is the number of 7 14 ni com X Series User Manual ticks of the unknown signal counted between sample clocks and T2 is the number of ticks counted of the known time base The frequency measured will be fx fk T1 T2 Figure 7 15 Sample Clocked Buffered Frequency Measurement Averaging Counter Armed ei tI i Sev LUN UN ULL s s tt a Pi
90. makes DMA the fastest available data transfer method NI uses DMA hardware and software technology to achieve high throughput rates and increase system utilization DMA is the default method of data transfer for PCI Express and PXI Express devices NI PCI Express and PXI Express X Series devices have eight fully independent DMA controllers for high performance transfers of data blocks One DMA controller is available for each measurement and acquisition block Analog input Analog output Counter 0 Counter 1 Counter 2 Counter 3 Digital waveform generation digital output Digital waveform acquisition digital input National Instruments 10 1 Chapter 10 Bus Interface Each DMA controller channel contains a FIFO and independent processes for filling and emptying the FIFO This allows the buses involved in the transfer to operate independently for maximum performance Data is transferred simultaneously between the ports The DMA controller supports burst transfers to and from the FIFO Each DMA controller supports several features to optimize PCI Express PXI Express bus utilization The DMA controllers pack and unpack data through the FIFOs This feature allows the DMA controllers to combine multiple 16 bit transfers to the DAQ circuitry into a single 32 bit burst transfer on PCI Express The DMA controllers also automatically handle unaligned memory buffers on PCI Express PXI Express Programmed
91. maximum single channel rate is the fastest you can acquire data on the device from a single channel and still achieve accurate results The maximum aggregate sample rate is the fastest you can acquire on multiple channels and still achieve accurate results For example NI 6351 devices have a single channel maximum rate of 1 25 MS s and aggregate maximum sample rate of 1 MS s so they can sample one channel at 1 25 MS s or two channels at 500 kS s per channel as shown in Table 4 5 Table 4 5 Analog Input Rates for MIO X Series Devices Analog Input Rate Multi Channel MIO X Series Device Single Channel Aggregate NI 6320 6321 6323 250 kS s 250 kS s NI 6341 6343 6345 500 kS s 500 kS s NI 6351 6353 6355 1 25 MS s 1 MS s NI 6361 6363 6365 2 MS s 1 MS s NI 6375 3 846 MS s 1 MS s On several devices the single channel rate is higher than the aggregate rate because while the ADC can sample at that rate the PGIA cannot settle fast enough to meet accuracy specifications Al Sample Clock Signal Use the AI Sample Clock ai SampleClock signal to initiate a set of measurements Your MIO X Series device samples the AI signals of every channel in the task once for every AI Sample Clock A measurement acquisition consists of one or more samples You can specify an internal or external source for AI Sample Clock You can also specify whether the measurement sample begins on the rising edge or falling e
92. mounting 1 5 using low impedance sources MIO X Series devices 4 6 PFI terminals as static digital I Os 8 3 as timing input signals 8 2 to export timing output signals 8 2 RTSI as outputs 9 6 terminals as timing input signals 9 6 shorthigh quality cabling MIO X Series devices 4 7 the disk drive power connector PCI Express 3 5 W waveform generation digital 6 13 signals 5 5 wiring Simultaneous MIO X Series devices 4 44 working voltage range Simultaneous MIO X Series devices 4 3 4 38 X X Series accessories and cables 1 8 accessory options 2 4 cabling options 2 4 information A 1 pinouts 1 8 specifications 1 8 USB devices 1 2 X1 encoding 7 21 X2 encoding 7 21 X4 encoding 7 22 X Series User Manual National Instruments 1 15
93. multiplying the period of the Source signal by the number of edges returned by the counter A pulse width measurement is accurate even if the counter is armed while a pulse train is in progress If a counter is armed while the pulse is in the active state it waits for the next transition to the active state to begin the measurement National Instruments 7 5 Chapter 7 Counters Refer to the following sections for more information about X Series pulse width measurement options Single Pulse Width Measurement Implicit Buffered Pulse Width Measurement e Sample Clocked Buffered Pulse Width Measurement e Hardware Timed Single Point Pulse Width Measurement Single Pulse Width Measurement With single pulse width measurement the counter counts the number of edges on the Source input while the Gate input remains active When the Gate input goes inactive the counter stores the count in the FIFO and ignores other edges on the Gate and Source inputs Software then reads the stored count Figure 7 5 shows an example of a single pulse width measurement Figure 7 5 Single Pulse Width Measurement GATE E source PLAAT Counter Value 0 l 1 2 Latched Value 2 Implicit Buffered Pulse Width Measurement An implicit buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses The counter co
94. ni com X Series User Manual Analog Input Terminal Configuration Simultaneous MIO X Series devices support only differential DIFF input mode The channels on Simultaneous MIO X Series devices are true differential inputs meaning both positive and negative inputs can carry signals of interest For more information about DIFF input refer to the Connecting Analog Input Signals section which contains diagrams showing the signal paths for DIFF input mode A Caution Exceeding the differential and common mode input ranges distorts the input signals Exceeding the maximum input voltage rating can damage the device and the computer NI is not liable for any damage resulting from such signal connections The maximum input voltage ratings can be found in the specifications document for each Simultaneous MIO X Series device Analog Input Range Input range refers to the set of input voltages that an analog input channel can digitize with the specified accuracy The NI PGIA amplifies or attenuates the AI signal depending on the input range You can individually program the input range of each AI channel on your Simultaneous MIO X Series device The input range affects the resolution of the Simultaneous MIO X Series device for an AI channel Resolution refers to the voltage ofone ADC code For example a 16 bit ADC converts analog inputs into one of 65 536 216 codes that is one of 65 536 possible digital values These values are spread fairly
95. number of active edges of the Source input You can also specify the active edge of the Source input rising or falling Figure 7 27 shows a generation of a pulse with a pulse delay of four and a pulse width of three using the rising edge of Source Figure 7 27 Single Pulse Generation Counter Armed SOURCE OUT Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal The pulse appears on the Counter n Internal Output signal of the counter You can route the Start Trigger signal to the Gate input of the counter You can specify a delay from the Start Trigger to the beginning of the pulse You can also specify the pulse width The delay and pulse width are measured in terms of a number of active edges of the Source input After the Start Trigger signal pulses once the counter ignores the Gate input National Instruments 7 27 Chapter 7 Counters Figure 7 28 shows a generation of a pulse with a pulse delay of four and a pulse width of three using the rising edge of Source Figure 7 28 Single Pulse Generation with Start Trigger GATE f h Start Trigger source LCU LILI LI LU LIL I OUT Pulse Train Generation Refer to the following sections for more information about the X Series pulse train generation options e Finite Pulse Train Generation e Re
96. on PCI Express X Series devices 3 6 ni com X Series User Manual USB Device LED Patterns NI USB 634X 635x 636x Devices USB X Series devices have LEDs labeled ACTIVE and READY The ACTIVE LED indicates activity over the bus The READY LED indicates whether or not the device is configured Table 3 2 shows the behavior of the LEDs Table 3 2 LED Patterns POWER ACTIVE READY LED LED LED USB Device State Off or On Off Off The device is not powered or not connected to the host computer or the host computer does not have the correct version of NI DAQmx Refer to Table 2 4 X Series NI DAQmx Software Support for the NI DAQmx support information for your device On Off On The device is configured but there is no activity over the bus On On On The device is configured and there is activity On Blinking On over the bus USB BNC devices only National Instruments 3 7 Analog Input Refer to one of the following sections depending on your device Analog Input on MIO X Series Devices NI 632x 634x 6351 6353 6361 6363 63x5 devices can be configured for single ended and differential analog input measurements Analog Input on Simultaneous MIO X Series Devices NI 6356 6358 6366 6368 devices can be configured for differential analog input simultaneous sampled measurements Analog Input on MIO X Series Devices Figure 4 1 shows the analog input circuitry of MIO X Series devices
97. range of channel 2 to 200 mV to 200 mV to match channel 1 Then scan channels in the order 0 2 1 National Instruments 4 7 Chapter 4 Analog Input Inserting a grounded channel between signal channels improves settling time because the NI PGIA adjusts to the new input range setting faster when the input is grounded e Minimize Voltage Step between Adjacent Channels When scanning between channels that have the same input range the settling time increases with the voltage step between the channels If you know the expected input range of your signals you can group signals with similar expected ranges together in your scan list For example suppose all channels in a system use a 5 V to 5 V input range The signals on channels 0 2 and 4 vary between 4 3 V and 5 V The signals on channels 1 3 and 5 vary between 4 V and 0 V Scanning channels in the order 0 2 4 1 3 5 produces more accurate results than scanning channels in the order 0 1 2 3 4 5 4 Avoid Scanning Faster Than Necessary Designing your system to scan at slower speeds gives the NI PGIA more time to settle to a more accurate level Here are two examples to consider e Example 1 Averaging many AI samples can increase the accuracy of the reading by decreasing noise effects In general the more points you average the more accurate the final result However you may choose to decrease the number of points you average and slow down the scanning rate Su
98. signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090A Desktop rack mountable device with 22 BNCs for connecting analog digital and timing signals NI 63x5 Only BNC 2115 Provides BNC connectivity for 24 differential or 48 single ended analog inputs for connectors 1 2 or 3 of NI 63x5 devices This leaves 8 differential or 16 single ended analog inputs inaccessible on connectors 1 2 or 3 You can use one BNC accessory on connector 0 of any X Series device An additional BNC accessory may be used on connector 1 of any X series device except the NI 63x5 devices Only the BNC 2115 may be used on connectors 1 2 or 3 of the NI 63x5 devices Screw Terminal Accessories National Instruments offers several styles of screw terminal connector blocks All terminal connector blocks require a cable except the TB 2706 to connect an X Series device to a connector block as listed in Table 2 2 National Instruments 2 5 Chapter 2 DAQ System Overview Table 2 2 Screw Terminal Accessories Screw Terminal Accessory Description CB 68LP and CB 68LPR Unshielded connector blocks SCC 68 T O connector block with screw terminals general breadboard area bus terminals and four expansion slots fo
99. single point HWTSP Typically HWTSP operations are used to read single samples at known time intervals While buffered operations are optimized for high throughput HWTSP operations are optimized for low latency and low jitter In addition HWTSP can notify software if it falls behind hardware These features make HWTSP ideal for real time control applications HWTSP operations in conjunction with the wait for next sample clock function provide tight synchronization between the software layer and the hardware layer Refer to the NI DAQmx Hardware Timed Single Point Lateness Checking document for more information To access this document go to ni com info and enter the Info Code daghwtsp Note NI USB 634x 635x 636x Devices X Series USB devices do not support hardware timed single point HWTSP operations Analog Input Triggering Analog input supports three different triggering actions e Start trigger Reference trigger e Pause trigger Refer to the AJ Start Trigger Signal AI Reference Trigger Signal and AI Pause Trigger Signal sections for information about these triggers An analog or digital trigger can initiate these actions All Simultaneous MIO X Series devices support digital triggering but some do not support analog triggering To find your device triggering options refer to the specifications document for your device 4 40 ni com X Series User Manual Connecting Analog Input Signals Table 4 7 summarize
100. the level or the high and low limits in window trigger mode the device adjusts the output of the trigger DACs Refer to the specifications document for your device to find the accuracy or resolution of these DACs which also shows the accuracy or resolution of analog triggers To improve accuracy do the following e Usean AI channel with a small input range instead of APFI lt 0 1 gt as your trigger source The DAQ device does not amplify the APFI lt 0 1 gt signals When using an AI channel the NI PGIA amplifies the AI channel signal before driving the analog trigger circuitry If you configure the AI channel to have a small input range you can trigger on very small voltage changes in the input signal Software calibrate the analog trigger circuitry The propagation delay from when a valid trigger condition is met to when the analog trigger circuitry emits the Analog Comparison Event may have an impact on your measurements if the trigger signal has a high slew rate If you find these conditions have a noticeable impact on your measurements you can perform software calibration on the analog trigger circuitry by configuring your task as normal and applying a known signal for your analog trigger Comparing the observed results against the expected results you can calculate the necessary offsets to apply in software to fine tune the desired triggering behavior 11 6 ni com Device Specific Information This appendix contains devi
101. the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 kQ and produce a 1 gain error AC Coupled Both inputs of the instrumentation amplifier require a DC path to ground in order for the instrumentation amplifier to work If the source is AC coupled capacitively coupled the instrumentation amplifier needs a resistor between the positive input and AI GND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 1 MQ In this case connect the negative input directly to AI GND If the source has high output impedance balance the signal path as previously described using the same value resistor on both the positive and negative inputs be aware that there is some gain error from loading down the source Field Wiring Considerations Environmental noise can seriously affect the measurement accuracy of the Simultaneous MIO X Series device if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to AI signal routing although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use individually shielded twisted pair wires to connect AI signals to th
102. through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source Use one of the following external signals as the source of AO Sample Clock PFI lt 0 15 gt RTSI lt 0 7 gt PXI STAR PXIe DSTAR lt A B gt e Analog Comparison Event an analog trigger Routing AO Sample Clock Signal to an Output Terminal You can route AO Sample Clock as an active low signal out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal Other Timing Requirements The AO timing engine on your device internally generates AO Sample Clock unless you select some external source AO Start Trigger starts the timing engine and either the software or hardware can stop it once a finite generation completes When using the AO timing engine you can also specify a configurable delay from AO Start Trigger to the first AO Sample Clock pulse By default this delay is two ticks of AO Sample Clock Timebase Figure 5 7 shows the relationship of AO Sample Clock to AO Start Trigger Figure 5 7 AO Sample Clock and AO Start Trigger AO Sample Clock Timebase AO Start Trigger AO Sample Clock Start Trigger National Instruments 5 9 Chapter 5 Analog Output AO Sample Clock Timebase Signal The AO Sample Clock Timebase ao SampleClockTimebase signal is divided down to provide a source for AO Sample Cloc
103. timer the outputs go to a 6 22 ni com X Series User Manual user defined safe state and remain in that state until the watchdog timer is disarmed by the application and new values are written the device is reset or the computer is restarted The expiration signal that indicates an expired watchdog will continue to assert until the watchdog is disarmed After the watchdog timer expires the device ignores any digital writes until the watchdog timer is disarmed Note When the watchdog timer is enabled and the computer enters a fault condition ports that are set to tri state remain tri stated and do not go to user defined safe states You can set the watchdog timer timeout period to specify the amount of time that must elapse before the watchdog timer expires The counter on the watchdog timer is configurable up to 232 1 x 8 ns approximately 34 seconds before it expires A watchdog timer can be set for all DIO and PFI lines Connecting Digital I O Signals The DIO signals P0 lt 0 31 gt P1 lt 0 7 gt and P2 lt 0 7 gt are referenced to D GND You can individually program each line as an input or output Figure 6 16 shows P1 lt 0 3 gt configured for digital input and P1 lt 4 7 gt configured for digital output Figure 6 16 shows the switch receiving TTL signals and sensing external device states and shows the LED sending TTL signals and driving external devices Figure 6 16 Digital I O Connections 5 V LED
104. to the PFI Filters section of Chapter 8 PFI for more information DI Sample Clock Signal The device uses the DI Sample Clock di SampleClock signal to sample the Port 0 terminals and store the result in the DI waveform acquisition FIFO You can specify an internal or external source for DI Sample Clock You can also specify whether the measurement sample begins on the rising edge or falling edge of DI Sample Clock 6 4 ni com X Series User Manual Ifthe DAQ device receives a DI Sample Clock when the FIFO is full it reports an overflow error to the host software Using an Internal Source To use DI Sample Clock with an internal source specify the signal source and the polarity of the signal The source can be any of the following signals e DI Sample Clock di SampleClock e DO Sample Clock do SampleClock AI Sample Clock ai SampleClock AI Convert Clock ai ConvertClock e AO Sample Clock ao SampleClock e Counter n Sample Clock e Counter n Internal Output Frequency Output e DI Change Detection output Several other internal signals can be routed to DI Sample Clock through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source You can route any of the following signals as DI Sample Clock e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt e Analog Comparison Event an analog trigger You can
105. 1 USB X Series mounting kit 781514 01 USB X Series lid with thumbscrew fasteners 781661 01 USB cable with locking screw 2 m 780534 01 EMI suppression ferrites 10 2 mm length 78 1233 02 Not for use with NI USB BNC devices Signal Conditioning Most computer based measurement systems involve plug in data acquisition DAQ devices with some form of signal conditioning Sensors and transducers usually require signal conditioning before a measurement system can effectively and accurately acquire the signal The front end signal conditioning system can include functions such as signal amplification attenuation filtering electrical isolation simultaneous sampling and multiplexing In addition National Instruments 2 7 Chapter 2 DAQ System Overview many transducers require excitation currents or voltages bridge completion linearization or high amplification for proper and accurate operation Sensors and Transducers Sensors generate electrical signals to measure physical phenomena such as temperature force sound or light Strain gauges thermocouples thermistors angular encoders linear encoders and resistance temperature detectors RTDs are commonly used sensors To measure signals from these various transducers you must convert them into a form that a DAQ device can accept For example the output voltage of most thermocouples is very small and susceptible to noise You may need to amplify or filter th
106. 14 5V P0 3 47 13 D GND PFI 11 P2 3 46 12 D GND PFI 10 P2 2 45 11 J PFI0 P1 0 D GND 44 10 PFI 1 P1 1 PFI 2 P1 2 43 9 D GND PFI 3 P1 3 42 8 5V PFI 4 P1 4 41 7 DGND PFI 13 P2 5 40 6 Hal 5 P1 5 PRIS P27 39 5 PFI 6 P1 6 PFI 7 P1 7 38 4 p ND PFI 8 P2 0 37 3 PFI 9 P2 1 D GND 36 2 PFI 12 P2 4 D GND 35 1 PFI 14 P2 6 ee NC No Connect CONNECTOR 0 Al 0 7 iach ice 34 TERMINAL 1 AE 68 TERMINAL 35 4 Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of National Instruments A 27 Appendix A Device Specific Information the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help Figure A 19 shows the pinout of the NI USB 6356 6366 Screw Terminal For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 19 NI USB 6356 6366 Screw Terminal Pinout SN 17 al 4 SN 81 PFI 8 P2 0 Al 0 1 P0 0 65 no ells Sis aeo Pa eliS Ses Pear AGN 2 GI 20 Al 5 RU 82 Sll s4 DGND ali SIl 21 A15 pos 68 GJ 85 PFI10 P2 2 AIR 3 SI 22 Al GND Poa se Gl 86 D GND AI GND 6 P0 5 70 RES z GI 23 Al 6 En
107. 17 When to Use Differential Connections with Ground Referenced Signal Sources sistema nantes 4 18 When to Use Non Referenced Single Ended NRSE Connections with Ground Referenced Signal Sources 4 18 When to Use Referenced Single Ended RSE Connections with Ground Referenced Signal Sources 4 19 vi ni com X Series User Manual Using Differential Connections for Ground Referenced Signal Sources 4 19 Using Non Referenced Single Ended NRSE Connections for Ground Referenced Signal Sources 0 cccccececceseesesseeseesecsecsecsecseeseesseaeeeees 4 20 Field Wiring Considerations 4 21 Analog Input Timing Signals 00 0 ccececessessssseseeeececeeceeceaeeaeeseeaecaecaecaecaeeaeeaeeneees 4 22 Aggregate versus Single Channel Sample Rates 4 24 AI Sample Clock Signal ss 4 24 AI Sample Clock Timebase Signal 4 26 AT Convert Clock Signal lt csc i sccchsaeccisstetisestasslacssassassasaduadeads a AR 4 26 AI Convert Clock Timebase Signal 4 30 AI Hold Complete Event Signal 4 30 AI Start Trigger Signal 4 30 AI Reference Trigger Signal 4 32 AI Pause Trigger Signal ccccesesesseessesceeeseeseeeeeeeeeeceeceeceececeseeaecaecaeenaenaeats 4 33 Getting Started with AI Applications in Software 4 35 Analog Input on Simultaneous MIO X Series Devices 4 36 Analog Input Terminal Configuration 4 37 Analog Input Range 4 37 Working Vol
108. 2 ni com X Series User Manual Table 7 1 Counter Timing Measurements Continued Implicit Timing Sample Clocked Measurement Support Timing Support Buffered Frequency Yes Yes Buffered Period Yes Yes Buffered Position No Yes Buffered Two Signal Edge Separation Yes Yes Counter Input Applications The following sections list the various counter input applications available on X Series devices e Counting Edges Pulse Width Measurement Pulse Measurement Semi Period Measurement Frequency Measurement e Period Measurement Position Measurement e Two Signal Edge Separation Measurement Counting Edges In edge counting applications the counter counts edges on its Source after the counter is armed You can configure the counter to count rising or falling edges on its Source input You can also control the direction of counting up or down as described in the Controlling the Direction of Counting section The counter values can be read on demand or with a sample clock Refer to the following sections for more information about X Series edge counting options Single Point On Demand Edge Counting e Buffered Sample Clock Edge Counting National Instruments 7 3 Chapter 7 Counters Single Point On Demand Edge Counting With single point on demand edge counting the counter counts the number of edges on the Source input after the counter is armed On demand refers to th
109. 29 Al 21 gt ie ae EE alk ewes Al2 Al24 7 Al6 al 4g al 18 39 IS Al 22 Al10 AI2 8 SON 24 Al14 ALE Ai 26 ai 18 40 S SH 56 Al 30 Al 22 Al GND 9 9 z see AI GND 4S 9 s7 Nona AI3 Al 3 10 AI7 A119 Al 194 42 S Al 11 Al3 11 GY 27 ALIS AL7 Araz ar19 43 Ke SI 99 A 81 Al 23 AI GND 12 SI 28 AI GND AGND sal Si 60 Areno AISENSE 13 Sj 29_ NC AISENSE2 45 ISI S NC AI GND 14 SI 30 Al GND Al GND 46 IS Gj 62 Al GND re te 32 AO GND 202 AIS S 64 AO END AO GND 16 AO GND 48 S NI S S ST 81 PFI 8 P2 0 113 P0 24 TE co 82 D GND e T 114 D GND PO 2 67 SI 83 PFI 9 P2 1 P0 10 99 115 P0 25 i S 84 D GND i 116 D GND a GI 85 PFI 10 P2 2 aoe 100 117 P026 PO 5 70 II 86 D GND PO13 102 118 D GND BUTS 7 SI 87 PFI 11 P2 3 Oe 4 10e 119 P0 27 PO 7 72 ISl SW 58 D ND P0 15 104 iao Eao PFIO P1 0 73 Gl 89 PFI 12 P2 4 Fo 1e 121 P0 28 PFI1 P1 1 74 S 20 D GND P0 17 106 i DCR PEER GI 91 PFI 19 P2 5 Cae i 123 P0 29 PFI3 P13 76 I 92 D GND P019 108 124 D GND PFI4 P1 4 77 Gl 93 PFI 14 P2 6 020 125 P0 30 PFI 5 P41 5 78 SERRES P0 21 110 126 D GND PFI6 P1 6 79 GI 95 PFI 15 P2 7 PO22 111 127 P0 31 PFI7 P1 7 Bol S 5V P0 23 112 WS eh NC No Connect National Instruments A 9 Appendix A Device Specific Information Figure A 7 shows the pinout of the NI USB 6343 BNC For a detailed description of each signal refer to the 7 0 Connector Sig
110. 356 6358 6366 6368 Devices Simultaneous MIO SMIO X Series devices do not support SCC Programming Devices in Software National Instruments measurement devices are packaged with NI DAQmx driver software an extensive library of functions and VIs you can call from your application software such as LabVIEW or LabWindows CVI to program all the features of your NI measurement devices Driver software has an application programming interface APT which is a library of VIs functions classes attributes and properties for creating applications for your device X Series devices use the NI DAQmx driver NI DAQmx includes a collection of programming examples to help you get started developing an application You can modify example code and save it in an application You can use examples to develop a new application or add example code to an existing application To locate LabVIEW LabWindows CVI Measurement Studio Visual Basic and ANSI C examples refer to the KnowledgeBase document Where Can I Find NI DAQmx Examples by going to ni com info and entering the Info Code daqmxexp For additional examples refer to ni com examples National Instruments 2 9 Chapter 2 DAQ System Overview Table 2 4 lists the earliest NI DAQmx support version for each X Series device Table 2 4 X Series NI DAQmx Software Support Device NI DAQm x Earliest Version Support NI PCle PXIe 632x 634 1 6343 NI DAQmx 9 0 NI PCle PXIe 635 1 63
111. 4 ni com Counters X Series devices have four general purpose 32 bit counter timers and one frequency generator The general purpose counter timers can be used for many measurement and pulse generation applications Figure 7 1 shows the X Series Counter 0 and the frequency generator All four counters on X Series devices are identical Figure 7 1 X Series Counter 0 and Frequency Generator Input Selection Muxes Counter 0 Counter 0 Source Counter 0 Timebase 7a Counter 0 Gate Counter 0 Internal Output Counter 0 Aux V Embedded CtrO a Counter 0 HW Arm FIFO Counter 0 A Counter 0 TC x Counter 0 B Counter 0 Up_Down 7 Counter 0 Z 7 D Counter 0 Sample Clock Input Selection Muxes Frequency Generator D Frequency Output Timebase Freq Out Counters have eight input signals although in most applications only a few inputs are used For information about connecting counter signals refer to the Default Counter Timer Pinouts section Each counter has a FIFO that can be used for buffered acquisition and generation Each counter also contains an embedded counter Embedded Ctrn for use in what are traditionally two counter measurements and generations The embedded counters cannot be programmed independent of the main counter signals from the embedded counters are not routable National Instruments 7 1 Chapter 7 Counters Counter Timing Engine Unl
112. 40 MHz 7 47 synchronizing multiple devices 9 3 T technical support B 4 terminal configuration analog input MIO X Series devices 4 1 Simultaneous MIO X Series devices 4 36 terminals connecting counter 7 42 NI DAQmx default counter 7 42 Timebase 100 kHz 9 2 100 MHz 9 2 20 MHz 9 2 timed acquisitions MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 timing output signals exporting using PFI terminals 8 2 training B 3 transducers 2 8 trigger 11 1 analog actions 11 3 arm start 7 45 pause 7 45 PXI 9 8 PXI_ STAR 9 8 Star Trigger 9 8 start 7 45 triggering 11 1 analog accuracy 11 6 analog actions 11 3 analog edge 11 4 analog edge with hysteresis 11 4 1 14 ni com analog input MIO X Series devices 4 10 Simultaneous MIO X Series devices 4 40 analog input channels 11 3 analog types 11 4 analog window 11 5 APFI lt 0 1 gt terminals 11 2 counter 7 45 with a digital source 11 1 with an analog source 11 2 troubleshooting analog input C 1 analog output C 2 counters C 2 two signal edge separation measurement 7 24 buffered 7 25 single 7 24 types of analog triggers 11 4 U USB BNC 1 5 USB BNC devices 1 3 USB Signal Stream as a transfer method 10 2 USB X Series bulk transfers 10 2 cable strain relief 1 7 desktop use 1 5 device security 1 7 1 8 DIN rail mounting 1 6 panel mounting 1 5 security cable slot 1 7 1 8 USB cable strain relief 1 7 wall
113. 5 P1 5 Al GND 29 63 Al 27 AI 19 PFI 15 P2 7 39 5 PFI 6 P1 6 Al 19 Al 19 30 64 Al GND PFI 7 P1 7 38 4 D GND Al 26 Al 18 31 65 Al 18 Al 18 PFI 8 P2 0 37 3 PFI9 P2 1 Al GND 32 66 Al 25 Al 17 D GND 36 2 PFI 12 P2 4 Al 17 Al 17 33 67 Al GND D GND 35 1 PFI 14 P2 6 Al 24 Al 16 34 68 AI 16 AI 16 J es NC No Connect NC No Connect Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQm x counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help A 8 ni com X Series User Manual Figure A 6 shows the pinout of the NI USB 6343 Screw Terminal For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 6 NI USB 6343 Screw Terminal Pinout J AIO AIO 1 Sf 17 a44 Arie cartes sang S42 A 20 A 204 AIB AIO 2 GI 18 A112 A14 hi al 16 34 fl S 50 A128 a120 EE E E EE E E date Al1 Al1 4 Al 17 Al 17 36 I AIQ Al1 5 Sj 21 AVIS ALS Aras A117 37 SI S5341
114. 51 AI Sample Clock signal MIO X Series devices 4 24 Simultaneous MIO X Series devices 4 47 AI Sample Clock Timebase signal MIO X Series devices 4 26 Simultaneous MIO X Series devices 4 49 AI Start Trigger signal MIO X Series devices 4 30 Simultaneous MIO X Series devices 4 50 ai ConvertClock 4 26 National Instruments 1 1 Index ai ConvertClockTimebase 4 30 ai HoldCompleteEvent MIO X Series devices 4 30 Simultaneous MIO X Series devices 4 49 ai PauseTrigger MIO X Series devices 4 33 Simultaneous MIO X Series devices 4 53 ai ReferenceTrigger MIO X Series devices 4 32 Simultaneous MIO X Series devices 4 51 ai SampleClock MIO X Series devices 4 24 Simultaneous MIO X Series devices 4 47 ai SampleClockTimebase MIO X Series devices 4 26 Simultaneous MIO X Series devices 4 49 ai StartTrigger MIO X Series devices 4 30 Simultaneous MIO X Series devices 4 50 analog comparison event routing 11 4 comparison event signal 11 3 edge triggering 11 4 with hysteresis 11 4 trigger actions 11 3 trigger types 11 4 triggering 11 2 analog input channels 11 3 charge injection C 1 crosstalk when sampling multiple channels C 1 differential troubleshooting C 1 ghost voltages when sampling multiple channels C 1 MIO X Series devices 4 1 AI Convert Clock 4 26 AI Convert Clock Timebase 4 30 AI Hold Complete Event 4 30 l 2 nicom AI Pause Trigger 4 33 AI Reference Trigger 4 32 AI Sa
115. 53 636 1 6363 NI DAQmx 9 0 NI PXIe 6356 6358 6366 6368 NI DAQmx 9 0 2 NI USB 6341 6343 635 1 6353 6361 6363 Screw Terminal NI DAQmx 9 2 NI USB 6356 6366 Screw Terminal NI DAQmx 9 2 1 BNC NI USB 6361 6363 Mass Termination NI DAQmx 9 5 NI USB 6366 Mass Termination NI DAQmx 9 5 NI USB 6341 6343 6356 6361 6363 6366 NI DAQmx 9 5 NIPXIe 6345 6355 6365 6375 NI DAQmx 14 1 2 10 ni com Connector and LED Information The 7 0 Connector Signal Descriptions and 5 V Power Source sections contain information about X Series connector signals and power Refer to Appendix A Device Specific Information for device I O connector pinouts The PCI Express Device Disk Drive Power Connector and RTSI Connector Pinout sections refer to X Series PCI Express device power and the RTSI connector on PCI Express devices The USB Device LED Patterns section refers to the X Series USB device READY POWER and ACTIVE LEDs National Instruments 3 1 Chapter 3 Connector and LED Information I O Connector Signal Descriptions Table 3 1 describes the signals found on the I O connectors Not all signals are available on all devices Table 3 1 I O Connector Signals Signal Name Reference Direction Description AI GND Analog Input Ground These terminals are the reference point for single ended AI measurements in RSE mode and the bias current return point f
116. 7 39 counters 7 36 DI Sample Clock 6 4 DO Sample Clock 6 13 exporting timing output using PFI terminals 8 2 FREQ OUT 7 42 Frequency Output 7 42 minimizing output glitches C 2 output minimizing glitches on 5 2 simple pulse generation 7 27 X Series User Manual single point edge counting 7 4 pulse generation 7 27 retriggerable 7 29 with start trigger 7 27 pulse width measurement 7 6 semi period measurement 7 10 two signal edge separation measurement 7 24 single ended connections for floating signal sources MIO X Series devices 4 17 RSE configuration MIO X Series devices 4 17 software 1 1 AI applications Simultaneous MIO X Series devices 4 54 configuring AI ground reference settings MIO X Series devices 4 6 programming devices 2 9 software timed acquisitions MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 generations 5 3 6 11 specifications device 1 8 NI 6320 A 3 NI 6321 6341 A 7 NI 6345 6355 A 13 NI 6351 6361 A 18 NI 6353 6363 A 24 NI 6356 6366 A 30 NI 6358 6368 A 32 NI 6365 A 35 NI 6375 A 38 stacking 1 5 start trigger 7 45 static DIO 6 2 using PFI terminals as 8 3 strain relief 1 7 switching from a large to a small input range MIO X Series devices 4 7 National Instruments 1 13 Index synchronization modes 100 MHz source 7 47 external source greater than 40 MHz 7 47 external source less than 40 MHz 7 47 internal source less than
117. AIL SAFE PERFORMANCE INCLUDING IN THE OPERATION OF NUCLEAR FACILITIES AIRCRAFT NAVIGATION AIR TRAFFIC CONTROL SYSTEMS LIFE SAVING OR LIFE SUSTAINING SYSTEMS OR SUCH OTHER MEDICAL DEVICES OR ANY OTHER APPLICATION IN WHICH THE FAILURE OF THE PRODUCT OR SERVICE COULD LEAD TO DEATH PERSONAL INJURY SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM COLLECTIVELY HIGH RISK USES FURTHER PRUDENT STEPS MUST BE TAKEN TO PROTECT AGAINST FAILURES INCLUDING PROVIDING BACK UP AND SHUT DOWN MECHANISMS NI EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH RISK USES Contents Chapter 1 Getting Started Tristallatiom 2 0362 firent abcde ccbecbcausescbtes dua ces dea eva desde ii ia 1 1 Unpacking 1 1 Device Self Calibration cccccccesseeseesteeee 1 2 Getting Started with X Series USB Devices 1 2 USB Device Chassis Ground 1 2 Ferrite Installations ne nn emmener a ee dO ee ere ere GS 1 4 Mounting NI USB X Series Devices 1 5 Panel Wall Mounting ss 1 5 DIN Rail Mounting USB Device LEDs USB Cable Strain Relief sae USB Device Security Cable Slot 1 8 Device Pinouts n3 ht te inner A termites 1 8 D vice Specifications sessisccazexstxces stares sohsaydeetzess cha ces EKE AE nE E rentree 1 8 Device Accessories and Cables ss 1 8 Chapter 2 DAQ System Overview DAO Hardware en AR A
118. C Accessories SCC provides portable modular signal conditioning to your DAQ system Use an SHC68 68 EPM shielded cable to connect your X Series device to an SCC module carrier such as the following SC 2345 SC 2350 SCC 68 You can use either connector on MIO X Series devices to control an SCC module carrier with NI DAQmx Note PCI Express users should consider the power limits on certain SCC modules without an external power supply Refer to the device specifications document for your device and the PCI Express Device Disk Drive Power Connector section of Chapter 3 Connector and LED Information for information about power limits and increasing the current the device can supply on the 5 V terminal Note N16356 6358 6366 6368 Devices Simultaneous MIO X Series devices do not support SCC 2 4 ni com X Series User Manual Y Note NI 635x Devices NI 635x devices only support SCC on Connector 0 Refer to the SCC Configuration Guide available by going to ni com info and entering the Info Code rdscav for more information BNC Accessories You can use the SHC68 68 EPM shielded cable to connect your DAQ device to the BNC accessories listed in Table 2 1 Table 2 1 BNC Accessories BNC Accessory Description BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input
119. Continued X Series User Manual Al Ground Reference Signals Routed to the Positive Input of the Signals Routed to the Negative Input of the Settings NI PGIA Vins NI PGIA Vin DIFF AI lt 0 7 gt AI lt 8 15 gt AI lt 16 23 gt AI lt 24 31 gt AI lt 32 39 gt AI lt 40 47 gt AI lt 48 55 gt AI lt 56 63 gt AI lt 64 71 gt AI lt 72 79 gt AI lt 80 87 gt AI lt 88 95 gt AI lt 96 103 gt AI lt 104 111 gt AI lt 112 119 gt AI lt 120 127 gt AI lt 128 135 gt AI lt 136 143 gt AI lt 144 151 gt AI lt 152 159 gt AI lt 160 167 gt AI lt 168 175 gt AI lt 176 183 gt AI lt 184 191 gt AI lt 192 199 gt AI lt 200 207 gt For differential measurements AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0 For a complete list of signal pairs that form differential input channels refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information A Caution The maximum input voltages rating of AI signals with respect to ground and for signal pairs in differential mode with respect to each other are listed in the specifications document for your device Exceeding the maximum input voltage of AI signals distorts the measurement results Exceeding the maximum input voltage rating can also damage the device and the computer NI is no
120. D 64 30 Al3 Al 3 Al 11 Al 3 63 29 AI GND Al SENSE 62 28 Al 4 Al 4 Al 12 Al 4 61 127 AI GND AI 5 Al 5 60 26 Al 13 Al 5 CONNECTOR 0 Al 0 15 AI GND 59 25 Al6 Al 6 Al 14 A16 58 24 Al GND Al7 Al 7 57 23 Al 15 Al 7 TERMINAL 68 TERMINAL 34 AI GND 56 22 Aoo AO GND 55 21 AO1 AO GND 54 20 APFI0 D GND 53 19 PO 4 P0 0 52 18 D GND P0 5 51 17 Po 1 D GND 50 16 Po 6 P0 2 49 15 D GND P0 7 48 14 45v P0 3 47 13 D GND PFI 11 P2 3 46 121 D GND TERMINAL 35 Rog TERMINAL 1 PFI 10 P2 2 45 11 PFIO P1 0 D GND 44110 PFI1 P1 1 PFI 2 P1 2 43 9 D GND PFI 3 P1 3 42 8 45V PFI 4 P1 4 41 7 DGND PFI 13 P2 5 40 6 PFI5 P1 5 PFI 15 P2 7 39 5 PFI6 P1 6 PFI 7 P1 7 38 4 DGND PFI 8 P2 0 37 3 PFI9 P2 1 D GND 36 2 PFI12 P2 4 D GND 35 1 PFI14 P2 6 L A 14 ni com Y Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass X Series User Manual Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help Figure
121. DAQ X Series X Series User Manual NI 632x 634x 635x 636x 637x Devices AH SO ff Fran ais Deutsch A ni com manuals December 2014 7 NATIONAL y INSTRUMENTS 370784F 01 Worldwide Technical Support and Product Information ni com Worldwide Offices Visitni com niglobal to access the branch office websites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support information refer to the MI Services appendix To comment on National Instruments documentation refer to the National Instruments website at ni com info and enter the Info Code feedback 2009 2014 National Instruments All rights reserved Legal Information Limited Warranty This document is provided as is and is subject to being changed without notice in future editions For the latest version refer to ni com manuals NI reviews this document carefully for technical accuracy however NI MAKES NO EXPRESS OR IMPLIED WARRANTIES AS TO THE ACCURACY OF THE INFORMATION CONTAINED HEREIN AND SHALL NOT BE LIABLE FOR ANY ERRORS NI warrants that its hardware products will be free of defects in materials and workmanship that cause the product to fail to substantially conform to the applicable NI published specifications for one 1 year from the date of inv
122. Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source Use one of the following external signals as the source of AI Sample Clock e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe_DSTAR lt A B gt e Analog Comparison Event an analog trigger Routing Al Sample Clock Signal to an Output Terminal You can route AI Sample Clock out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe_DSTARC terminal This pulse is always active high All PFI terminals are configured as inputs by default Other Timing Requirements Your DAQ device only acquires data during an acquisition The device ignores AI Sample Clock when a measurement acquisition is not in progress During a measurement acquisition you can cause your DAQ device to ignore AI Sample Clock using the AI Pause Trigger signal A counter timing engine on your device internally generates AI Sample Clock unless you select an external source AI Start Trigger starts this counter and either software or hardware can stop it once a finite acquisition completes When using the AI timing engine you can also specify a configurable delay from AI Start Trigger to the first AI Sample Clock pulse By default this delay is set to two ticks of the AI Sample Clock Timebase signal 4 48 ni com X Series User Manual Figure 4 30 shows the relationship of AI Sample Clock to AI Start Trigger Figure 4 30 Al Sample Clock and Al Start
123. Generation Methods When performing a digital waveform operation you either can perform software timed or hardware timed generations Software Timed Generations With a software timed generation software controls the rate at which data is generated Software sends a separate command to the hardware to initiate each update In NI DAQmx software timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing a single value out such as a constant digital value Hardware Timed Generations With a hardware timed generation a digital hardware signal controls the rate of the generation This signal can be generated internally on your device or provided externally Hardware timed generations have several advantages over software timed generations The time between samples can be much shorter e The timing between samples can be deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or hardware timed single point HWTSP A buffer is a temporary storage in computer memory for to be transferred samples Hardware timed single point HWTSP Typically HWTSP operations are used to write single samples at known time intervals While buffered operations are optimized for high throughput HWTSP operations are optimized for low latency and low jitter In addition HWTSP ca
124. H AO FIFO m AO Data ao2 pace H AO3 X DAC3 AO Sample Clock AO Reference Select The main blocks featured in the X Series analog output circuitry are as follows e DACs Digital to analog converters DACs convert digital codes to analog voltages e AO FIFO The AO FIFO enables analog output waveform generation It is a first in first out FIFO memory buffer between the computer and the DACs It allows you to download the points of a waveform to your X Series device without host computer interaction e AO Sample Clock The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage AO Reference Selection The AO reference selection signal allows you to change the range of the analog outputs National Instruments 5 1 Chapter 5 Analog Output AO Reference Selection AO reference selection allows you to set the analog output range The analog output range describes the set of voltages the device can generate The digital codes of the DAC are spread evenly across the analog output range So if the range is smaller the analog output has better resolution that is the voltage output difference between two consecutive codes is smaller Therefore the analog output is more accurate The analog output range of a device is all of the voltages between AO Reference and AO Reference The possible settings for AO reference depend on the d
125. Help Figure A 16 shows the pinout of the NI USB 6363 BNC For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 16 NI USB 6363 BNC Pinout 5 a 8 3 I Q z F a lt lt S a ad HABA BBBBABABBRABBABAAABABABABAG Q0000000000000000000000000000 KS KC GCP SHS HNGP GS SHS HSS SHH HSS gg ggggggsg gt HU YUUUUU YUU UYU EU Mmm USER ACCESS a es ANALOG OUTPUT PA 5P15 cHs ND NATIONAL M USB 6363 INSTRUMENTS x Seriea Mltuncton DAG National Instruments A 23 Appendix A Device Specific Information Refer to Table 7 9 X Series PCI Express PXT Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help NI 6353 6363 Device Specifications Refer to the NJ 6353 Specifications for more detailed information about the NI 6353 device Refer to the NJ 6363 Specifications for more detailed information about the NI 6363 device NI 6353 6363 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information A 24 ni
126. I O Programmed T O is a data transfer mechanism where the user s program is responsible for transferring data Each read or write call in the program initiates the transfer of data Programmed I O is typically used in software timed on demand operations Refer to the Analog Output Data Generation Methods section of Chapter 5 Analog Output for more information USB Device Data Transfer Methods The primary ways to transfer data across the USB bus are as follows USB Signal Stream USB Signal Stream is a method to transfer data between the device and computer memory using USB bulk transfers without intervention of the microcontroller on the NI device NI uses USB Signal Stream hardware and software technology to achieve high throughput rates and increase system utilization in USB devices USB X Series devices have eight fully independent USB Signal Stream for high performance transfers of data blocks These channels are assigned to the first eight measurement acquisition circuits that request one Programmed I O Programmed T O is a data transfer mechanism where the user s program is responsible for transferring data Each read or write call in the program initiates the transfer of data Programmed I O is typically used in software timed on demand operations Refer to the Analog Output Data Generation Methods section of Chapter 5 Analog Output for more information PXI Express Considerations PXI clock and trigger signals are
127. I PCle 6321 and NI PCle PXle 6341 Pinout AI O Al 0 Al GND AI 9 AI 1 AI 2 AI 2 Al GND Al 11 Al 3 Al SENSE Al 12 Al 4 AI 5 AI 5 Al GND Al 14 AI 6 AI 7 Al 7 Al GND AO GND AO GND D GND PO 0 PO 5 D GND PO 2 PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND oO A Q oO u D S u N D N N np oo D a Dey A N wo N D D np er e gt a A wo D ala alo l lw s EN Do AI 8 AI 0 Al 1 Al 1 Al GND Al 10 Al 2 Al 3 Al 3 Al GND Al 4 Al 4 Al GND Al 13 Al 5 Al 6 Al 6 Al GND Al 15 Al 7 AO 0 AO 1 NC P0 4 D GND PO 1 P0 6 D GND 5V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 TERMINAL 68 TERMINAL 35 NC No Connect A 4 ni com CONNECTOR 0 Al 0 15 B59 TERMINAL 34 TERMINAL 1 Y Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass X Series User Manual Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this devic
128. Instruments 4 29 Chapter 4 Analog Input Al Convert Clock Timebase Signal The AI Convert Clock Timebase ai ConvertClockTimebase signal is divided down to provide one of the possible sources for AI Convert Clock Use one of the following signals as the source of AI Convert Clock Timebase e AI Sample Clock Timebase e 100 MHz Timebase AI Convert Clock Timebase is not available as an output on the I O connector Al Hold Complete Event Signal The AI Hold Complete Event ai HoldCompleteEvent signal generates a pulse after each A D conversion begins You can route AI Hold Complete Event out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The polarity of AI Hold Complete Event is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed Al Start Trigger Signal Use the AI Start Trigger ai StartTrigger signal to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a software command Once the acquisition begins configure the acquisition to stop e When a certain number of points are sampled in finite mode e After a hardware reference trigger in finite mode e With a software command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes
129. M Keil and Vision are trademarks or registered of ARM Ltd or its subsidiaries LEGO the LEGO logo WEDO and MINDSTORMS are trademarks of the LEGO Group TETRIX by Pitsco is a trademark of Pitsco Inc FIELDBUS FOUNDATION and FOUNDATION are trademarks of the Fieldbus Foundation EtherCAT is a registered trademark of and licensed by Beckhoff Automation GmbH CANopenf is a registered Community Trademark of CAN in Automation e V DeviceNet and EtherNet IP are trademarks of ODVA Go SensorDAQ and Vernier are registered trademarks of Vernier Software amp Technology Vernier Software amp Technology and vernier com are trademarks or trade dress Xilinx is the registered trademark of Xilinx Inc Taptite and Trilobular are registered trademarks of Research Engineering amp Manufacturing Inc FireWire is the registered trademark of Apple Inc Linux is the registered trademark of Linus Torvalds in the U S and other countries Handle Graphics MATLAB Real Time Workshop Simulink Stateflow and xPC TargetBox are registered trademarks and TargetBox and Target Language Compiler are trademarks of The MathWorks Inc Tektronix Tek and Tektronix Enabling Technology are registered trademarks of Tektronix Inc The Bluetooth word mark is a registered trademark owned by the Bluetooth SIG Inc The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by National Instruments is un
130. MHz Timebase e 100 kHz Timebase e PXI CLK10 e RTSI lt 0 7 gt e PFI lt 0 15 gt PXI STAR e PXIe DSTAR lt A B gt Analog Comparison Event an analog trigger Refer to the device routing table in MAX for all additional routable signals To find the device routing table for your device launch MAX and select Devices and Interfaces NI DAQmx Devices Click a device to open a tabbed window in the middle pane Click the Device Routes tab at the bottom of the pane to display the device routing table DI Sample Clock Timebase is not available as an output on the I O connector DI Sample Clock Timebase is divided down to provide one of the possible sources for DI Sample Clock You can configure the polarity selection for DI Sample Clock Timebase as either rising or falling edge except for the 100 MHz Timebase or 20 MHz Timebase You might use DI Sample Clock Timebase if you want to use an external sample clock signal but need to divide the signal down If you want to use an external sample clock signal but do 6 6 ni com X Series User Manual not need to divide the signal then you should use DI Sample Clock rather than DI Sample Clock Timebase DI Start Trigger Signal Use the DI Start Trigger di StartTrigger signal to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a software command Once the acquisition begins configure the
131. NI PXle 6358 6368 Pinout 5 GND 6 7 7 GND AO GND AO GND D GND P0 0 P0 5 D GND P0 2 PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND 2m Hr nzn AO 0 AO 1 APFI 0 P0 4 D GND PO 1 P0 6 D GND 5V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 jnjoj ajajaj NC No Connect dE Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass TERMINAL 68 TERMINAL 34 TERMINAL 1 TERMINAL 35 ECTOR 1 8 15 SN comes Fava TERMINAL 35 TERMINAL 1 TERMINAL 34 TERMINAL 68 P0 30 P0 28 P0 25 D GND P0 22 PO 21 D GND 5V D GND P0 17 P0 16 D GND D GND 5V D GND P0 14 P0 9 D GND P0 12 APFI 1 AO3 AO2 Al 15 Al 14 GND Al 14 Al 13 Al 12 GND Al 12 Al 11 GND Al 11 Al 10 AI 9 GND Al 8 ra a N m o A oo ro w o A a A Es A a N b a w A Ex P gt oo a A D a Oo x a a N or a D a A y a a N N a o nN wo a N N as a D a a D a e
132. National Instruments 6 21 Chapter 6 Digital I O e Case 2 If an additional line on the bus also has a transition during the filter clock period the change is not propagated until the next filter clock edge as shown in Figure 6 14 Figure 6 14 Case 2 Not Stable Not Stable Digital Input PO A O Digital Input PO B Filter Clock Filtered Input A Filtered Input B Figure 6 15 illustrates the difference between line and bus filtering Figure 6 15 Line and Bus Filtering Digital Input PO A Digital Input PO B 1A 2A 3A Filter Clock Filtered Input A a Filtered Input B 2A With line filtering filtered input A would ignore the glitch on digital input PO B and transition after two filter clocks 3A Filtered input A goes high when sampled high for two consecutive filter clocks and transitions on the next filter edge because digital input PO B glitches Watchdog Timer The watchdog timer is a software configurable feature used to set critical outputs to safe states in the event of a software failure a system crash or any other loss of communication between the application and the X Series device When the watchdog timer is enabled if the X Series device does not receive a watchdog reset software command within the time specified for the watchdog
133. O X Series devices 4 18 when to use in NRSE mode MIO X Series devices 4 18 when to use in RSE mode MIO X Series devices 4 19 H hardware 2 2 hardware installation 1 1 hardware timed acquisitions MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 38 generations 5 3 6 11 hardware timed single point acquisitions MIO X Series devices 4 9 l 8 nicom hardware timed generations 5 3 6 3 6 11 hysteresis analog edge triggering with 11 4 T O connector 3 1 NI PCle PXIe 6341 pinout A 4 NI PCle PXIe 6361 pinout A 14 NI PCle PXIe 6363 pinout A 19 NI PCIe 6320 pinout A 2 A 33 NI PCIe 6321 pinout A 4 NI PCIe 6323 6343 pinout A 8 NI PCIe 6351 pinout A 14 NI PCIe 6353 pinout A 19 NI PXIe 6345 6355 pinout A 12 NI PXIe 6356 6366 pinout A 25 NI PXIe 6358 6368 pinout A 31 NI USB 6341 BNC pinout A 6 NI USB 6341 Screw Terminal pinout A 5 NI USB 6343 BNC pinout A 10 NI USB 6343 pinout A 9 NI USB 6343 Screw Terminal pinout A 9 NI USB 635 1 6361 Mass Termination pinout A 16 NI USB 635 1 6361 pinout A 20 NI USB 635 1 6361 Screw Terminal pinout A 15 NI USB 6356 6366 pinout A 28 NI USB 6363 pinout A 23 VO protection 6 18 8 6 implicit buffered pulse width measurement 7 6 semi period measurement 7 10 improving analog trigger accuracy 11 6 input signals using PFI terminals as 8 2 using RTSI terminals as 9 6 insertion of grounded channels between signal cha
134. Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help A 34 ni com X Series User Manual NI 6365 Device Specifications Refer to the M 6365 Device Specifications for more detailed information about the NI 6365 device NI 6365 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information National Instruments A 35 Appendix A Device Specific Information NI 6375 The following sections contain information about the NI PXIe 6375 device NI 6375 Pinout Figures A 24 and Figure A 25 show the pinouts of the NI PXIe 6375 The I O signals appear on four 68 pin connectors For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 24 NI PXle 6375 Connector 2 and Connector 3 Pinout ger x AI 80 AI 80 68 34 AI 88 AI 80 AI 199 AI 199 1 35 Al 207 AI 199 AI 89 AI 81 67 33 Al 81 Al 81 Al 206 AI 198 2
135. R 2 D GND HARRABABRRABRABRAARBBARABRRABBAA CODOOOOOOOOOOODOOOOOODOOOOOOOOO cHs GND NI USB 6356 8 Inputs 16 Bit 1 25 MS s X Series Multifunction DAQ Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments A 29 Appendix A Device Specific Information NI 6356 6366 Device Specifications Refer to the NJ 6356 Specifications for more detailed information about the NI 6356 device Refer to the NJ 6366 Specifications for more detailed information about the NI 6366 device NI 6356 6366 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information A 30 ni com NI 6358 6368 X Series User Manual The following sections contain information about the NI PXIe 6358 and NI PXIe 6368 devices NI 6358 6368 Pinout Figure A 21 shows the pinout of the NI PXIe 6358 6368 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 21
136. Series User Manual Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 NI offers cables and accessories for many applications However if you want to develop your own cable adhere to the following guidelines for best results e For AI signals use shielded twisted pair wires for each AI pair of differential inputs Connect the shield for each signal pair to the ground reference at the source e Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital sections of the cable To prevent noise when using a cable shield use separate shields for the analog and digital sections of the cable For more information about the connectors used for DAQ devices refer to the KnowledgeBase document Specifications and Manufacturers for Board Mating Connectors by going to ni com info and entering the Info Code rdspmb USB Device Accessories USB Cable Power Supply and Ferrite NI offers a variety of products to use with the USB X series devices as shown in Table 2 3 Table 2 3 USB Device Accessories Power Supply and Ferrite Description Part Number Universal power supply with mini combicon 781513 01 connector 12 VDC 2 5 A USB X Series mounting kit with DIN rail clip 781515 0
137. Signals 0 cceseesceesseeeeeceeeecseeenseeeeees 10 2 PE EX PLess se mean AEE E dhadel aux desdesdecaadonsancebeaes 10 3 Chapter 11 Triggering Triggering with a Digital Source ss 11 1 Triggering with an Analog Source 11 2 APPT lt 0 51 gt Trin itial st cis sine sed ossnl shee faseesvevivbanctsbesos and bes cds E 11 2 Analog Input Channels ss 11 3 Analog Input Channels on MIO X Series Devices 11 3 Analog Input Channels on Simultaneous MIO X Series Devices 008 11 3 xii ni com X Series User Manual Analog Trigger ACTIONS esse 11 3 Routing Analog Comparison Event to an Output Terminal 11 4 Analog Trigger Types ss 11 4 Analog Trigger ACCUFAC Yu h en d car Men entr ie ECEE EE KiS 11 6 Appendix A Device Specific Information Appendix B Where to Go from Here Appendix C Troubleshooting Appendix D NI Services Index List of Figures Figure A 1 NI PCIe 6320 Pinout ee eeeeseeecneeeceseeeeecneeeeees 5 arte A2 Figure A 2 NI PCIe 6321 and NI PCle PXIe 6341 Pinout A 4 Figure A 3 NI USB 6341 Screw Terminal Pinout A 5 Figure A 4 NI USB 6341 BNC Pinout ss A 6 Figure A 5 NIPCIE 6323 6343 PinOut s cc cscorssonesssassovsnaseescastesrosvisssessetvecbeonssones A 8 Figure A 6 NI USB 6343 Screw Terminal Pinout 0 0 eeesceeeeeseneeeceeeeeeenees A 9 Figure A 7 NI USB 6343 BNC Pinout eee A 10 Figure A 8 NI PXIe 6345 6355 Pinout
138. StartTrigger e DO Start Trigger do StartTrigger The source can also be one of several internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the measurement acquisition stops on the rising edge or falling edge of AI Reference Trigger 4 52 ni com X Series User Manual Using an Analog Source When you use an analog trigger source the acquisition stops on the first rising edge of the Analog Comparison Event signal Routing Al Reference Trigger Signal to an Output Terminal You can route AI Reference Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt PXI_Trig lt 0 7 gt or PXIe DSTARC terminal All PFI terminals are configured as inputs by default Al Pause Trigger Signal Use the AI Pause Trigger ai PauseTrigger signal to pause and resume a measurement acquisition The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low as shown in Figure 4 33 In the figure T represents the period and A represents the unknown time between the clock pulse and the posttrigger Figure 4 33 Halt Internal Clock and Free Running External Clock A T A T Al Sample Clock Al Pause Trigger Halt Used on Internal C
139. Trigger Al Sample Clock Timebase Al Start Trigger Al Sample Clock Delay From Start Trigger Al Sample Clock Timebase Signal You can route any of the following signals to be the AI Sample Clock Timebase ai SampleClockTimebase signal e 100 MHz Timebase default 20 MHz Timebase e 100 kHz Timebase e PXI CLK10 e RTSI lt 0 7 gt e PFI lt 0 15 gt PXI STAR PXIe DSTAR lt A B gt e Analog Comparison Event an analog trigger AI Sample Clock Timebase is not available as an output on the I O connector AI Sample Clock Timebase is divided down to provide one of the possible sources for AI Sample Clock You can configure the polarity selection for AI Sample Clock Timebase as either rising or falling edge except on 100 MHz Timebase or 20 MHz Timebase Al Hold Complete Event Signal The AI Hold Complete Event ai HoldCompleteEvent signal generates a pulse after each A D conversion begins You can route AI Hold Complete Event out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The polarity of AI Hold Complete Event is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed National Instruments 4 49 Chapter 4 Analog Input Al Start Trigger Signal Use the AI Start Trigger ai StartTrigger sign
140. a A GI 87 PFI 11 P2 3 Ae 8 J S J EE aus LE J S T EE AI GND 9 ll 26 A7 PFIO P1 0 73 S 90 Den Al 3 10 S 27 A7 PFI 1 P1 1 74 Slot PFi13 P25 AI 3 11 Sl2s arano PFI 2 P1 2 75 Se Den ALGND 12 29 APFI0 Prioris 7 GJ 93 PFI 14 P2 6 AI GND 13 SI so Arend PFI 4 P1 4 77 Slls DEN AI GND 14 ll 31 01 PFI5 P1 5 78 Sos PFI 15 P2 7 AO 0 15 Ql 32 Ao GND PFI6 P1 6 79 Ql 96 5v AO GND 16 f PFI7 P1 7 80 i A RE Note Refer to Table 7 10 X Series USB Screw Terminal Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQm x counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help A 28 ni com X Series User Manual Figure A 20 shows the pinout of the NI USB 6356 6366 BNC For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 20 NI USB 6356 6366 BNC Pinout a a Ee GEES ANALOG INPUT SSSR a j 8 PFI 4 P14 mm DIGITAL ANDTIMING 1 0 mm power PFI 5 P15 PFI P1 6 PFI 7P 1 7 USER 2 Mls USER ACCESS DS eazy GEES ANALOG OUTPUT DS NATIONAL INSTRUMENTS A E gt PFI NP23 DGND PFI12 P2 4 PFI 12P25 PFI 14 P2 6 PFI 15 P2 7 D GND USER 1 USE
141. a Re eee 7 37 Routing a Signal to Counter n SOUrCE 0 ceeeececceseeseesecsecsecaeeaeceeeseeneeneeneeeees 7 37 Routing Counter n Source to an Output Terminal 7 38 x ni com X Series User Manual Counter n Gate Sinah oeseri a aei EEA ATEA ere EASA Routing a Signal to Counter n Gate Routing Counter n Gate to an Output Terminal 7 38 Count tn Aux Signalisssstrnneierenermemehnnementemnn Eea EEEE ES 7 38 Routing a Signal to Counter n AUX ss 7 39 Counter n A Counter n B and Counter n Z Signals ccccescsesseeseereeseeeeeeeeeeeees 7 39 Routing Signals to A B and Z Counter Inputs 7 39 Routing Counter n Z Signal to an Output Terminal 7 39 Counter n Up Down Signal ses 7 39 Counter n HW Arm Signal sise 7 40 Routing Signals to Counter n HW Arm Input 7 40 Counter n Sample Clock Signal ss 7 40 Using an Internal Source 0 cccecceseesesseeseesecsecsecsecseeseeeeeeseceeceeceeceaeeaeeaeeneenes 7 41 Using an External Source cccceceseeseeseeseeseeseeseesceseeeeeeeeeseceeceseeaeeaeeaeeaseneenes 7 41 Routing Counter n Sample Clock to an Output Terminal eee eeeeeeeeee 7 41 Counter n Internal Output and Counter n TC Signals 0 ceceeseeseesecseeeeseeeeneeeeees 7 41 Routing Counter n Internal Output to an Output Terminal eee 7 41 Frequency Output Signal ss 7 42 Routing Frequency Output to a Terminal 7 42 Default Counter Timer Pinouts us 7 42 Cou
142. a buffered edge count the counter begins counting when it is armed In other applications such as single pulse width measurement the counter begins waiting for the Gate signal when it is armed Counter output operations can use the arm signal in addition to a start trigger Software can arm a counter or configure counters to be armed on a hardware signal Software calls this hardware signal the Arm Start Trigger Internally software routes the Arm Start Trigger to the Counter n HW Arm input of the counter Routing Signals to Counter n HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input e RTSI lt 0 7 gt e PFI lt 0 15 gt Al Reference Trigger ai ReferenceTrigger e Al Start Trigger ai StartTrigger e PXI STAR e PXIe DSTAR lt A B gt e Analog Comparison Event Change Detection Event A counter s Internal Output can be routed to a different counter s HW Arm Some of these options may not be available in some driver software Counter n Sample Clock Signal Use the Counter n Sample Clock CtrnSampleClock signal to perform sample clocked acquisitions and generations You can specify an internal or external source for Counter n Sample Clock You can also specify whether the measurement sample begins on the rising edge or falling edge of Counter n Sample Clock If the DAQ device receives a Counter n Sample Clock when the FIFO is full it reports an overflow error to the host software 7
143. able section of the EEPROM To return a device to its initial factory calibration settings software can copy the factory calibration constants to the user modifiable section of the EEPROM Refer to the NI DAQmx Help or the LabVIEW Help for more information about using calibration constants For a detailed calibration procedure for X Series devices refer to the B E M S X Series Calibration Procedure available at ni com manuals Cables and Accessories A Caution For compliance with Electromagnetic Compatibility EMC requirements this product must be operated with shielded cables and accessories If unshielded cables or accessories are used the EMC specifications are no longer guaranteed unless all unshielded cables and or accessories are installed in a shielded enclosure with properly designed and shielded input output ports NI offers a variety of products to use with X Series PCI Express PXI Express USB devices including cables connector blocks and other accessories as follows e Shielded cables and cable assemblies and unshielded ribbon cables and cable assemblies Screw terminal connector blocks shielded and unshielded RTSI bus cables e SCXI modules and accessories for isolating amplifying exciting and multiplexing signals with SCXI you can condition and acquire up to 3 072 channels e Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges and RTDs simultan
144. al engine for X Series data acquisition hardware Some key features of this engine include the following e Flexible AI and AO sample and convert timing e Many triggering modes Independent AI AO DI DO and counter FIFOs e Generation and routing of RTSI signals for multi device synchronization e Generation and routing of internal and external timing signals e Four flexible 32 bit counter timer modules with hardware gating e Digital waveform acquisition and generation e Static DIO signals True 5 V high current drive DO e DI change detection DO watchdog timers e PLL for clock synchronization e Seamless interface to signal conditioning accessories e PCI Express PXI Express interface Independent scatter gather DMA controllers for all acquisition and generation functions 2 2 ni com X Series User Manual Calibration Circuitry The X Series analog inputs and outputs have calibration circuitry to correct gain and offset errors You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time No external circuitry is necessary an internal reference ensures high accuracy and stability over time and temperature changes Factory calibration constants are permanently stored in an onboard EEPROM and cannot be modified When you self calibrate the device as described in the Device Self Calibration section of Chapter 1 Getting Started software stores new constants in a user modifi
145. al periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between two edges of the Gate signal You can calculate the semi period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Refer to the following sections for more information about X Series semi period measurement options e Single Semi Period Measurement e Implicit Buffered Semi Period Measurement Refer to the Pulse versus Semi Period Measurements section for information about the differences between semi period measurement and pulse measurement Single Semi Period Measurement Single semi period measurement is equivalent to single pulse width measurement Implicit Buffered Semi Period Measurement In implicit buffered semi period measurement on each edge of the Gate signal the counter stores the count in the FIFO A DMA controller transfers the stored values to host memory 7 10 ni com X Series User Manual The counter begins counting when it is armed The arm usually occurs between edges on the Gate input You can select whether to read the first active low or active high semi period using the CI SemiPeriod StartingEdge property in NI DAQmx Figure 7 11 shows an example of an implicit buffered semi period measurement Figure 7 11 Implicit Buffered Semi Period Measurement Counter Starting
146. al purpose counter timers The 20 MHz Timebase is generated by dividing down the 100 MHz Timebase 100 kHz Timebase The 100 kHz Timebase can be used to generate many of the AI and AO timing signals The 100 kHz Timebase can also be used as the Source input to the 32 bit general purpose counter timers The 100 kHz Timebase is generated by dividing down the 20 MHz Timebase by 200 External Reference Clock The external reference clock can be used as a source for the internal timebases 100 MHz Timebase 20 MHz Timebase and 100 kHz Timebase on an X Series device By using the external reference clock you can synchronize the internal timebases to an external clock The following signals can be routed to drive the external reference clock e RTSI lt 0 7 gt e PFI lt 0 15 gt e PXIe CLK100 PXI STAR e PXIe DSTAR lt A B gt The external reference clock is an input to a Phase Lock Loop PLL The PLL generates the internal timebases A Caution Do not disconnect an external reference clock once the devices have been synchronized or are used by a task Doing so may cause the device to go into an unknown state Make sure that all tasks using a reference clock are stopped before disconnecting it 9 2 ni com X Series User Manual Enabling or disabling the PLL through the use of a reference clock affects the clock distribution to all subsystems For this reason the PLL can only be enabled or disabled when no other tasks a
147. al to AI GND as well as to the negative input of the instrumentation amplifier without using resistors This National Instruments 4 43 Chapter 4 Analog Input connection works well for DC coupled sources with low source impedance less than 100 Q High Source Impedance For larger source impedances this connection leaves the DIFF signal path significantly off balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a DIFF mode signal instead of a common mode signal and the instrumentation amplifier does not reject it In this case instead of directly connecting the negative line to AI GND connect the negative line to AI GND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise This configuration does not load down the source other than the very high input impedance of the instrumentation amplifier You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example
148. al to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a software command Once the acquisition begins configure the acquisition to stop e When a certain number of points are sampled in finite mode e After a hardware reference trigger in finite mode e With a software command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition Retriggerable Analog Input The AI Start Trigger is configurable as retriggerable When the AI Start Trigger is configured as retriggerable the timing engine generates the sample and convert clocks for the configured acquisition in response to each pulse on an AI Start Trigger signal The timing engine ignores the AI Start Trigger signal while the clock generation is in progress After the clock generation is finished the counter waits for another Start Trigger to begin another clock generation Figure 4 31 shows a retriggerable analog input with three AI channels and four samples per trigger Figure 4 31 Simultaneous MIO X Series Retriggerable Analog Input Al Start Trigger IIO OSE Al Sample Clock LUT TITTI A Note Waveform information from LabVIEW does not reflect the delay between triggers They are treated as a continuous acquisition with constant t0 and dt information Note NI USB 6356 6366 Devices Some X S
149. als While buffered operations are optimized for high throughput HWTSP operations are optimized for low latency and low jitter In addition HWTSP can notify software if it falls behind hardware These features make HWTSP ideal for real time control applications HWTSP operations in conjunction with the wait for next sample clock function provide tight synchronization between the software layer and the hardware layer Refer to the N DAQmx Hardware Timed Single Point Lateness Checking document for more information To access this document go to ni com info and enter the Info Code daqhwtsp Note NI USB 634x 635x 636x Devices USB X Series devices do not support hardware timed single point HWTSP operations Buffered In a buffered generation data is moved from a PC buffer to the DAQ device s onboard FIFO using DMA before it is written to the DACs one sample at a time Buffered generation typically allow for much faster transfer rates than non buffered acquisitions because data is moved in large blocks rather than one point at a time National Instruments 5 3 Chapter 5 Analog Output One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous Finite sample mode generation refers to the generation of a specific predetermined number of data samples Once the specified number of samples has been written out the generation stops Continuous generation refers to the gen
150. ample four The value decrements with each pulse on AI Sample Clock until the value reaches zero The sample counter is then loaded with the number of posttriggered samples in this example three Figure 4 15 Pretriggered Data Acquisition Example Al Start Trigger i i Al Reference Trigger n a OU UT UT UT Al Sample Clock Al Convert Clock a Sample Counter 3 2 1 0 2 2 2 1 0 If an AI Reference Trigger ai ReferenceTrigger pulse occurs before the specified number of pretrigger samples are acquired the trigger pulse is ignored Otherwise when the AI Reference Trigger pulse occurs the sample counter value decrements until the specified number of posttrigger samples have been acquired MIO X Series devices feature the following analog input timing signals e AI Sample Clock Signal e AI Sample Clock Timebase Signal AI Convert Clock Signal National Instruments 4 23 Chapter 4 Analog Input AI Convert Clock Timebase Signal AI Hold Complete Event Signal e AI Start Trigger Signal e AI Reference Trigger Signal e Al Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section of Chapter 8 PFT for more information Aggregate versus Single Channel Sample Rates MIO X Series devices are characterized with maximum single channel and maximum aggregate sample rates The
151. anual Table 9 2 describes the three differential star DSTAR lines and how they are used Table 9 2 PXle_DSTAR Line Descriptions Trigger Line Purpose PXIe DSTARA Distributes high speed high quality clock signals from the system timing slot to the peripherals input PXIe DSTARB Distributes high speed high quality trigger signals from the system timing slot to the peripherals input PXIe DSTARC Sends high speed high quality trigger or clock signals from the peripherals to the system timing slot output The DSTAR lines are only available for PXI Express devices when used with a PXI Express system timing module For more information refer to the PXI Express Specification at www pxisa org National Instruments 9 9 Bus Interface The bus interface circuitry of X Series devices efficiently moves data between host memory and the measurement and acquisition circuits X Series devices are available for the following platforms PCI Express PXI Express e USB Data Transfer Methods Refer to the following sections for information about bus interface data transfer methods for X Series devices PCI Express PXI Express Device Data Transfer Methods The primary ways to transfer data across the PCI Express bus are as follows Direct Memory Access DMA DMA is a method to transfer data between the device and computer memory without the involvement of the CPU This method
152. ase ao SampleClockTimebase AO Pause Trigger ao PauseTrigger Counter input signals for all counters Source Gate Aux HW_Arm A B Z Counter n Sample Clock DI Sample Clock di SampleClock DI Sample Clock Timebase di SampleClockTimebase DI Reference Trigger di ReferenceTrigger DO Sample Clock do SampleClock Most functions allow you to configure the polarity of PFI inputs and whether the input is edge or level sensitive Exporting Timing Output Signals Using PFI Terminals You can route any of the following timing signals to any PFI terminal configured as an output 8 2 NI 632X 634x 6351 6353 63 x5 6361 6363 Devices AI Convert Clock ai ConvertClock AI Hold Complete Event ai HoldCompleteEvent AI Reference Trigger ai ReferenceTrigger AI Sample Clock ai SampleClock AI Start Trigger ai StartTrigger AI Pause Trigger ai PauseTrigger AO Sample Clock ao SampleClock AO Start Trigger ao StartTrigger ni com X Series User Manual e AO Pause Trigger ao PauseTrigger e DI Sample Clock di SampleClock DI Start Trigger di StartTrigger e DI Reference Trigger di ReferenceTrigger e DI Pause Trigger di PauseTrigger DO Sample Clock do SampleClock e DO Start Trigger do StartTrigger e DO Pause Trigger do PauseTrigger e Counter n Source Counter n Gate Counter n Internal Output e Counter n Sample Clock e Counter n Counter n HW Arm e Frequency Output e PXI STAR e
153. ate for your product at ni com calibration System Integration If you have time constraints limited in house technical resources or other project challenges National Instruments Alliance Partner members can help To learn more call your local NI office or visit ni com alliance National Instruments D 1 Appendix D NI Services For information about other technical support options in your area visit ni com services Training and Certification The NI training and certification program is the most effective way to increase application development proficiency and productivity Visit ni com training for more information The Skills Guide assists you in identifying the proficiency requirements of your current application and gives you options for obtaining those skills consistent with your time and budget constraints and personal learning preferences Visit ni com skills guide to see these custom paths Nloffers courses in several languages and formats including instructor led classes at facilities worldwide courses on site at your facility and online courses to serve your individual needs Technical Support Support at ni com support includes the following resources Self Help Technical Resources Visit ni com support for software drivers and updates a searchable KnowledgeBase product manuals step by step troubleshooting wizards thousands of example programs tutorials application notes instrumen
154. bes the LabVIEW NI DAQmx VIs and functions Property and Method Reference NI DAQmx Properties Contains the property reference Taking Measurements Contains the conceptual and how to information you need to acquire and analyze measurement data in LabVIEW including common measurements measurement fundamentals NI DAQmx key concepts and device considerations LabWindows CVI The Data Acquisition book of the LabWindows CVI Help contains Taking an NI DAQmx Measurement in LabWindows CVI which includes step by step instructions about creating a measurement task using the DAQ Assistant In LabWindows CVI select Help Contents then select Using LabWindows CVI Data Acquisition This book also contains information about accessing detailed information through the N DAQmx Help The NI DAQmx Library book of the LabWindows CVI Help contains API overviews and function reference for NI DAQmx Select Library Reference NI DAQmx Library in the LabWindows CVI Help Measurement Studio If you program your NI DAQmx supported device in Measurement Studio using Visual C or Visual Basic NET you can interactively create channels and tasks by launching the DAQ Assistant from MAX or from within Visual Studio You can use Measurement Studio to generate the configuration code based on your task or channel Refer to the DAQ Assistant Help for additional information about generating code The NI Measurement Studio Help is fully integrated with t
155. c Information Figure A 23 NI PXle 6365 Connector 0 and Connector 1 Pinout we N Alo Alo 68 34 A18 A10 AI71 Al 714 1 35 A179 al 71 AI GND 67 33 Al 1 Al 14 Al 78 Al 70 2 36 Al 70 Al 704 AI 9 Al 1 66 32 AI GND IS AI 69 Al 69 3 37 Al77 Al 69 Al 2 Al 2 65 31 AI 10 Al 2 8 AI 68 AI 68 4 38 A176 A168 AI GND 64 30 AI 3 AI 3 Z Q Al 75 Al 67 5 39 Al 67 Al 67 Al 11 A1 3 63 29 AI GND Q Z Al 66 Al 66 6 40 Al 74 Al 66 Al SENSE 62 28 AI 4 Al 4 m AI 65 AIl 65 7 41 A173 Al 65 Al 12 Al 4 61 27 Al GND gt 3 Al 72 Al 64 8 42 A164 Al 64 AI 5 AI 5 60 26 Al 13 AI 5 2 AI GND 9 43 AIGND AI GND 59 25 AI 6 AI 6 2 S Al 55 Al 55 10 44 Al 63 Al 55 Al 14 Al 6 58 24 AI GND 2 gt AI 54 AI 54 11 45 Al 62 A154 AI 7 Al 7 57 23 AI 15 AI 7 re 3 Al 61 A153 12 46 A153 Al 53 AI GND 56 22 AOO 3 Al 52 Al 52 13 47 Al 60 AI 52 AO GND 55 21 AO1 F S Al 51 Al 51 14 48 Al 59 Al 51 AO GND 54 20
156. ce pinouts specifications cable and accessory choices and other information for the following X Series devices NI 6320 NI 6321 6341 NI 6323 6343 NI 6345 6355 NI 6351 6361 NI 6353 6363 NI 6356 6366 NI 6358 6368 NI 6365 NI 6375 To obtain documentation for devices not listed here refer to ni com manuals National Instruments A 1 Appendix A Device Specific Information NI 6320 The following sections contain information about the NI PCIe 6320 device NI 6320 Pinout Figure A 1 shows the pinout of the NI PCIe 6320 device For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 1 NI PCle 6320 Pinout AI O AI 0 34 Al 8 Al 0 Al GND 33 AI Al 1 AI 9 AI 1 32 AI GND AI 2 AI 2 31 Al 10 Al 2 o AI GND 30 AIS AI 3 T s Al 11 AI 3 29 AI GND 05 AI SENSE 28 Al 4 Al 4 Zz Al 12 Al 4 27 AI GND 8 AI 5 AI 5 26 Al 13 Al 5 AI GND 25 Al6 Al 6 Al 14 Al 6 24 AI GND AI 7 Al 7 23 Al15 Al7 TERMINAL 68 TERMINAL 34 AI GND 22 Nc NC 21 NC NC 20 NC D GND 19 Po 4 PO 0 18 D GND P0 5 17 Po 1 D GND 16 Po 6 P0 2 15 D GND PO 7 14 45V P0 3 13 D GND PFI 11 P2 3 12 D GND TERMINAL 35 TERMINAL 1 PFI 10 P2
157. ck Timebase is not available as an output on the I O connector You might use DO Sample Clock Timebase if you want to use an external sample clock signal but need to divide the signal down If you want to use an external sample clock signal but do not need to divide the signal then you should use DO Sample Clock rather than DO Sample Clock Timebase DO Start Trigger Signal Use the DO Start Trigger do StartTrigger signal to initiate a waveform generation If you do not use triggers you can begin a generation with a software command Retriggerable DO The DO Start Trigger is configurable as retriggerable When DO Start Trigger is configured as retriggerable the timing engine generates the sample clocks for the configured generation in response to each pulse on a DO Start Trigger signal The timing engine ignores the DO Start Trigger signal while the clock generation is in progress After the clock generation is finished the timing engine waits for another start trigger to begin another clock generation Figure 6 8 shows a retriggerable DO of four samples Figure 6 8 Retriggerable DO DO Start Trigger DO Sample Clock _ National Instruments 6 15 Chapter 6 Digital I O Using a Digital Source To use DO Start Trigger specify a source and an edge The source can be one of the following signals A pulse initiated by host software e PFI lt 0 15 gt e RTSI lt 0 7 gt AI Reference Trigg
158. com non buffered hardware timed acquisitions Simultaneous MIO X Series devices 4 40 non referenced single ended connections using with floating signal sources MIO X Series devices 4 16 using with ground referenced signal sources MIO X Series devices 4 20 when to use with floating signal sources MIO X Series devices 4 12 when to use with ground referenced signal sources MIO X Series devices 4 18 NRSE connections using with floating signal sources 4 16 using with ground referenced signal sources 4 20 when to use with floating signal sources 4 12 when to use with ground referenced signal sources 4 18 O on demand acquisitions MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 edge counting 7 4 timing MIO X Series devices 4 8 Simultaneous MIO X Series devices 4 38 order of channels for scanning MIO X Series devices 4 7 other software installing 1 1 output signal glitches C 2 minimizing 5 2 terminal routing analog comparison events 11 4 outputs using RTSI as 9 6 overview 2 1 P pause trigger 7 45 PCI Express disk drive power connector 3 5 period measurement 7 20 PFI 8 1 connecting input signals 8 4 exporting timing output signals using PFI terminals 8 2 filters 8 4 I O protection 8 6 programmable power up states 8 6 using terminals as static digital I Os 8 3 using terminals as timing input signals 8 2 PFI terminals as static digital I Os 8 3 pin assignments S
159. conversion rate higher than the maximum rate specified for your device will result in errors Using an Internal Source One of the following internal signals can drive AI Convert Clock AI Convert Clock Timebase divided down e Counter n Internal Output e Change Detection Event e Counter n Sample Clock e AO Sample Clock ao SampleClock e DI Sample Clock di SampleClock e DO Sample Clock do SampleClock A programmable internal counter divides down the AI Convert Clock Timebase to generate AI Convert Clock The counter is started by AI Sample Clock and continues to count down to zero produces an AI Convert Clock reloads itself and repeats the process until the sample is finished It then reloads itself in preparation for the next AI Sample Clock pulse Several other internal signals can be routed to AI Convert Clock through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source Use one of the following external signals as the source of AI Convert Clock e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe_DSTAR lt A B gt e Analog Comparison Event an analog trigger National Instruments 4 27 Chapter 4 Analog Input Routing Al Convert Clock Signal to an Output Terminal You can route AI Convert Clock as an active low signal out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal All PFI terminals are co
160. cquisition refers to the acquisition of a specific predetermined number of data samples Once the specified number of samples has been read in the acquisition stops If you use a reference trigger you must use finite sample mode Continuous acquisition refers to the acquisition of an unspecified number of samples Instead of acquiring a set number of data samples and stopping a continuous acquisition continues until you stop the operation Continuous acquisition is also referred to as double buffered or circular buffered acquisition If data cannot be transferred across the bus fast enough the FIFO becomes full New acquisitions overwrite data in the FIFO before it can be transferred to host memory which causes the device to generate an error With continuous operations if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer the buffer could reach an overflow condition causing an error to be generated Hardware timed single point HWTSP Typically HWTSP operations are used to read single samples at known time intervals While buffered operations are optimized for high throughput HWTSP operations are optimized for low latency and low jitter In addition HWTSP can notify software if it falls behind hardware These features make HWTSP ideal for real time control applications HWTSP operations in conjunction with the wait for next sample clock function provide tight synchronization b
161. d by copyright and other intellectual property laws Where NI software may be used to reproduce software or other materials belonging to others you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction End User License Agreements and Third Party Legal Notices You can find end user license agreements EULAs and third party legal notices in the following locations e Notices are located in the lt National Instruments gt Legal Information and lt National Instruments gt directories e EULAs are located in the lt National Instruments gt Shared MDF Legal license directory e Review lt National Instruments gt Legal Information txt for information on including legal information in installers built with NI products U S Government Restricted Rights If you are an agency department or other entity of the United States Government Government the use duplication reproduction release modification disclosure or transfer of the technical data included in this manual is governed by the Restricted Rights provisions under Federal Acquisition Regulation 52 227 14 for civilian agencies and Defense Federal Acquisition Regulation Supplement Section 252 227 7014 and 252 227 7015 for military agencies Trademarks Refer to the NI Trademarks and Logo Guidelines at ni com trademarks for more information on National Instruments trademarks AR
162. d Signal Sources Figure 4 11 shows how to connect ground reference signal sources in NRSE mode Figure 4 11 Single Ended Connections for Ground Referenced Signal Sources NRSE Configuration 1 0 Connector Al lt 0_x gt OO Ground 9 co s Referenced se Signal Ve Instrumentation Source Amplifier o so 4 Input Multiplexers Measured Common Al SENSE Voltage Mods Zy AI GND Noise cm and Ground wae Potential 477 MIO X Series Device Configured in NRSE Mode ei Note NI USB 6341 6343 6361 6363 BNC Devices To measure a ground referenced signal source on X Series USB BNC devices move the switch under the BNC connector to the GS position AI lt 0 31 gt and AI SENSE must both remain within 11 V of AI GND To measure a single ended ground referenced signal source you must use the NRSE ground reference setting Use Table 4 4 to determine how to correctly connect your AI signal Table 4 4 Al Signal Connections Signal Ground Reference AI lt 0 15 gt AI SENSE AI lt 16 79 gt AI SENSE 2 AI lt 80 143 gt AI SENSE 3 AI lt 144 207 gt AI SENSE 4 AI SENSE is internally connected to the negative input of the NI PGIA Therefore the ground point of the signal connects to the negative input of the NI PGIA 4 20 ni com X Series User Manual Any potential difference between the device
163. d by the following equation 1 sample period sample rate Figure C 1 Al Sample Clock and Al Convert Clock Channel 0 Channel 1 lt Convert Period lt Sample Period gt AI Convert Clock controls the convert period which is determined by the following equation 1 convert period convert rate This method allows multiple channels to be sampled relatively quickly in relationship to the overall sample rate providing a nearly simultaneous effect with a fixed delay between channels Analog Output I am seeing glitches on the output signal How can I minimize it When you use a DAC to generate a waveform you may observe glitches on the output signal These glitches are normal when a DAC switches from one voltage to another it produces glitches due to released charges The largest glitches occur when the most significant bit of the DAC code changes You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of the output signal Visit ni com support for more information about reducing glitches Counters How do I connect counter signals to my X Series device The Default Counter Timer Pinouts section of Chapter 7 Counters has information about counter signal connections C 2 ni com NI Services National Instruments provides global services and support as part of our commitment to your success Take advantage of product services in
164. der license The mark LabWindows is used under a license from Microsoft Corporation Windows is a registered trademark of Microsoft Corporation in the United States and other countries Other product and company names mentioned herein are trademarks or trade names of their respective companies Members of the National Instruments Alliance Partner Program are business entities independent from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents Export Compliance Information Refer to the Export Compliance Information at ni com legal export compliance for the National Instruments global trade compliance policy and how to obtain relevant HTS codes ECCNs and other import export data WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS YOU ARE ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY AND RELIABILITY OF THE PRODUCTS WHENEVER THE PRODUCTS ARE INCORPORATED IN YOUR SYSTEM OR APPLICATION INCLUDING THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION PRODUCTS ARE NOT DESIGNED MANUFACTURED OR TESTED FOR USE IN LIFE OR SAFETY CRITICAL SYSTEMS HAZARDOUS ENVIRONMENTS OR ANY OTHER ENVIRONMENTS REQUIRING F
165. dge of AI Sample Clock 4 24 ni com X Series User Manual Using an Internal Source One of the following internal signals can drive AI Sample Clock e Counter n Internal Output AI Sample Clock Timebase divided down e A pulse initiated by host software e Change Detection Event e Counter n Sample Clock e AO Sample Clock ao SampleClock e DI Sample Clock di SampleClock e DO Sample Clock do SampleClock A programmable internal counter divides down the sample clock timebase Several other internal signals can be routed to AI Sample Clock through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source Use one of the following external signals as the source of AI Sample Clock e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt e Analog Comparison Event an analog trigger Routing Al Sample Clock Signal to an Output Terminal You can route AI Sample Clock out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal This pulse is always active high All PFI terminals are configured as inputs by default Other Timing Requirements Your DAQ device only acquires data during an acquisition The device ignores AI Sample Clock when a measurement acquisition is not in progress During a measurement acquisition you can cause your DAQ device to ignore AI Sample Clock using the AI Pause Trigger signal A
166. documentation resources B 4 ni com Troubleshooting This section contains common questions about X Series devices If your questions are not answered here refer to ni com support Analog Input I am seeing crosstalk or ghost voltages when sampling multiple channels What does this mean You may be experiencing a phenomenon called charge injection which occurs when you sample a series of high output impedance sources with a multiplexer Multiplexers contain switches usually made of switched capacitors When a channel for example AI 0 is selected in a multiplexer those capacitors accumulate charge When the next channel for example AI 1 is selected the accumulated current or charge leaks backward through channel 1 If the output impedance of the source connected to AI 1 is high enough the resulting reading can somewhat affect the voltage in AI 0 To circumvent this problem use a voltage follower that has operational amplifiers op amps with unity gain for each high impedance source before connecting to an X Series device Otherwise you must decrease the sample rate for each channel Another common cause of channel crosstalk is due to sampling among multiple channels at various gains In this situation the settling times can increase For more information about charge injection and sampling channels at different gains refer to the Multichannel Scanning Considerations section of Chapter 4 Analog Input I am using my d
167. e Remove the device from the package and inspect it for loose components or any other signs of damage Notify NI if the device appears damaged in any way Do not install a damaged device in your computer or chassis Store the device in the antistatic package when the device is not in use National Instruments 1 1 Chapter 1 Getting Started Device Self Calibration NI recommends that you self calibrate your X Series device after installation and whenever the ambient temperature changes Self calibration should be performed after the device has warmed up for the recommended time period Refer to the device specifications to find your device warm up time This function measures the onboard reference voltage of the device and adjusts the self calibration constants to account for any errors caused by short term fluctuations in the environment You can initiate self calibration using Measurement amp Automation Explorer MAX by completing the following steps 1 Launch MAX 2 Select My System Devices and Interfaces your device 3 Initiate self calibration using one of the following methods e Click Self Calibrate in the upper right corner of MAX e Right click the name of the device in the MAX configuration tree and select Self Calibrate from the drop down menu Note You can also programmatically self calibrate your device with NI DAQmx as described in Device Calibration in the NI DAQmx Help or the LabVIEW Help Get
168. e If the readings from the DAQ device are random and drift rapidly you should check the ground reference connections The signal can be referenced to a level that is considered floating with reference to the device ground reference Even though you are in DIFF mode you must still reference the signal to the same ground level as the device reference There are various methods of achieving this reference while maintaining a high common mode rejection ratio CMRR These methods are outlined in the Connecting Analog Input Signals section AI GND is an AI common signal that routes directly to the ground connection point on the devices You can use this signal if you need a general analog ground connection point to the device Analog Input Timing Signals In order to provide all of the timing functionality described throughout this section Simultaneous MIO X Series devices have a flexible timing engine Refer to the Clock Routing section of Chapter 9 Digital Routing and Clock Generation Simultaneous MIO X Series devices use AI Sample Clock ai SampleClock to perform simultaneous sampling on all active analog channels Since there is one ADC per channel AI Sample Clock controls the sample period on all the channels in the task National Instruments 4 45 Chapter 4 Analog Input An acquisition with posttrigger data allows you to view data that is acquired after a trigger event is received A typical posttrigger DAQ sequence is shown in Fi
169. e For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help Figure A 3 shows the pinout of the NI USB 6341 Screw Terminal For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 3 NI USB 6341 Screw Terminal Pinout SJ 17 A14 Al 4 SI 81 PF18 P2 0 TERE EI i S18 anzar Poo ll 2 D GND AI GND 3 Gi 19 AI GND EG Gl 83 PFI 9 P2 1 Al1 Al1 4 GI 20 Al5 Al 5 P03 68 Gil 84 D GND AIQ AI1 5 G2 AIS A15 54 Gl 85 PFI 10 P2 2 AI GND Es Gl 22 AIGND POE era Gil 86 D GND Al2 Al24 7 Gl 23 _Al 6 AI 6 POG z SI 87 PFI 11 P2 3 Al10 Al2 8 S24 AAA 07 Sll s8 D GND AI GND ona Si 25 AIGND OPIO IS SI 89 PFI 12 P2 4 AIS Al 3 10 9j 26 AI7 AI7 pri 74 J 90 D GND AI 11 Al3 11 GI 27_Al15 AI7 brjop 2 75 QI 91 PFI 13 P2 5 AIGND 12 NIE a PFI 3 P1 3 76 SI 2BPIGND AISENSE 13 S 29 NC PFI4 P1 4 77 GI 93 PFI 14 P2 6 AIGND 14 SIREAIEND PFI 5 P1 5 78 SEET AO 0 15 QI 31 AO 1 PFIG P1 6 79 I 95 PFI 15 P2 7 AOGND 16 SI SESENE PFI7 P1 7 80 QI 96 5V DE Note Refer to Table 7 10 X Series USB Screw Terminal Device Default aes S S 5 S Si S N S 5 S SI NC No Connect NI DAQmx Counter Timer Pins
170. e Idle time and active time can also be defined in terms of frequency and duty cycle or idle ticks and active ticks A Note On buffered implicit pulse trains the pulse specifications in the DAQmx Create Counter Output Channel are ignored so that you generate the number of pulses defined in the multipoint write On buffered sample clock pulse trains the pulse specifications in the DAQmx Create Counter Output Channel are generated after the counters start and before the first sample clock so that you generate the number of updates defined in the multipoint write Finite Implicit Buffered Pulse Train Generation Finite implicit buffered pulse train generation creates a predetermined number of pulses with variable idle and active times Each point you write generates a single pulse The number of pairs of idle and active times pulse specifications you write determines the number of pulses generated All points are generated back to back to create a user defined pulse train National Instruments 7 31 Chapter 7 Counters Table 7 6 and Figure 7 34 detail a finite implicit generation of three samples Table 7 6 Finite Implicit Buffered Pulse Train Generation Sample Idle Ticks Active Ticks 1 2 2 2 3 4 3 2 2 Figure 7 34 Finite Implicit Buffered Pulse Train Generation Counter L
171. e the measured input signal varies as the source floats outside the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the device assuming that the computer is plugged into the same power system as the source Non isolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but the difference can be much National Instruments 4 41 Chapter 4 Analog Input higher if power distribution circuits are improperly connected If a grounded signal source is incorrectly measured this difference can appear as measurement error Follow the connection instructions for grounded signal sources to eliminate this ground potential difference from the measured signal Isolated devices have isolated front ends that are isolated from ground reference signal sources and are not connected to building system grounds Isolated devices require the user to provide a ground reference terminal to which its input signals are referenced Differential Connections for Ground Referenced Signal Sources Figure 4 26 shows how to connect a ground referenced signal source to a channel on an Simultaneous MIO X Se
172. e Train Generation section for detailed information For information about connecting counter signals refer to the Default Counter Timer Pinouts section Pulse Generation for ETS In the equivalent time sampling ETS application the counter produces a pulse on the output a specified delay after an active edge on Gate After each active edge on Gate the counter cumulatively increments the delay between the Gate and the pulse on the output by a specified amount Thus the delay between the Gate and the pulse produced successively increases The increase in the delay value can be between 0 and 255 For instance if you specify the increment to be 10 the delay between the active Gate edge and the pulse on the output increases by 10 every time a new pulse is generated Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger Furthermore suppose you specify the delay increment to be 10 On the first trigger your pulse delay is 100 on the second it is 110 on the third it is 120 the process repeats until the counter is disarmed The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress National Instruments 7 35 Chapter 7 Counters The waveform thus produced at the counter s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that a
173. e an error With continuous operations if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer the buffer could reach an overflow condition causing an error to be generated Hardware timed single point HWTSP Typically HWTSP operations are used to read single samples at known time intervals While buffered operations are optimized for high throughput HWTSP operations are optimized for low latency and low jitter In addition HWTSP can notify software if it falls behind hardware These features make HWTSP ideal for real time control applications HWTSP operations in conjunction with the wait for next sample clock function provide tight synchronization between the software layer and the hardware layer Refer to the NJ DAQmx Hardware Timed Single Point Lateness Checking document for more information To access this document go to ni com info and enter the Info Code daqhwtsp Note NI USB 634x 635x 636x Devices X Series USB devices do not support hardware timed single point HWTSP operations Digital Input Triggering Digital input supports three different triggering actions e Start trigger e Reference trigger e Pause trigger Refer to the DI Start Trigger Signal DI Reference Trigger Signal and DI Pause Trigger Signal sections for information about these triggers An analog or digital trigger can initiate these actions All X Series devices support digital triggering
174. e debouncing filter Figure 8 1 shows the circuitry of one PFI line Each PFI line is similar Figure 8 1 X Series PFI Circuitry Timing Signals Static DO Buffer Static DI lt _ Direction Control To Input Timing Signal Selectors PFI Filters PFI Change Detection lt I O Protection PFI x P1 P2 Weak Pull Down When a terminal is used as a timing input or output signal it is called PFI x where x is an integer from 0 to 15 When a terminal is used as a static digital input or output it is called P1 x or P2 x On the I O connector each terminal is labeled PFI x P1 x or PFI x P2 x The voltage input and output levels and the current drive levels of the PFI signals are listed in the specifications of your device National Instruments 8 1 Chapter 8 PFI Using PFI Terminals as Timing Input Signals Use PFI terminals to route external timing signals to many different X Series functions Each PFI terminal can be routed to any of the following signals NI 632X 634x 6351 6353 63 x5 6361 6363 Devices AI Convert Clock ai ConvertClock AI Sample Clock ai SampleClock AI Start Trigger ai StartTrigger AI Reference Trigger ai ReferenceTrigger AI Pause Trigger ai PauseTrigger AI Sample Clock Timebase ai SampleClockTimebase AO Start Trigger ao StartTrigger AO Sample Clock ao SampleClock AO Sample Clock Timeb
175. e device With this type of wire the signals attached to the AI and AI inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference 4 44 ni com X Series User Manual e Route signals to the device carefully Keep cabling away from noise sources The most common noise source ina PCI DAQ system is the video monitor Separate the monitor from the analog signals as far as possible e Separate the signal lines of the Simultaneous MIO X Series device from high current or high voltage lines These lines can induce currents in or voltages on the signal lines of the Simultaneous MIO X Series device if they run in close parallel paths To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits Refer to the Field Wiring and Noise Considerations for Analog Signals document for more information To access this document go to ni com info and enter the Info Code rdfwn3 Minimizing Drift in Differential Mod
176. e fact that software can read the counter contents at any time without disturbing the counting process Figure 7 2 shows an example of single point edge counting Figure 7 2 Single Point On Demand Edge Counting Counter Armed PLA FLAT 1 2 3 4 5 SOURCE Counter Value 0 You can also use a pause trigger to pause or gate the counter When the pause trigger is active the counter ignores edges on its Source input When the pause trigger is inactive the counter counts edges normally You can route the pause trigger to the Gate input of the counter You can configure the counter to pause counting when the pause trigger is high or when it is low Figure 7 3 shows an example of on demand edge counting with a pause trigger Figure 7 3 Single Point On Demand Edge Counting with Pause Trigger Counter Armed Pause Trigger i Pause When Low i SOURCE 141414 F1 14 Counter Value 0 0 1 2 3 4 5 Buffered Sample Clock Edge Counting With buffered edge counting edge counting using a sample clock the counter counts the number of edges on the Source input after the counter is armed The value of the counter is sampled on each active edge of a sample clock and stored in the FIFO A DMA controller transfers the sampled values to host memory The count values returned are the cumulative counts since the counter armed event That is the sample clock does not reset the counter
177. e for the one counter measurement is lowest but the accuracy is lower Note that the accuracy and measurement time of the sample clocked and two counter large range are the same The advantage of the sample clocked method is that even when the frequency to measure changes the measurement time and error does not For example if you configured a large range two counter measurement to use a divide down of 50 for a 50 kHz signal then you would get the accuracy measurement time and accuracy listed in table 7 3 But if your signal ramped up to 5 MHz then with a divide down of 50 your measurement time would be 0 01 ms but your error would now be 0 001 The error with a sample clocked frequency measurement is not dependent on the measured frequency so at 50 kHz and 5 MHz with a measurement time of 1 ms the error will still be 0 001 One of the disadvantages of a sample clocked frequency measurement is that the frequency to be measured must be at least twice the sample clock rate to ensure that a full period of the frequency to be measured occurs between sample clocks National Instruments 7 19 Chapter 7 Counters Table 7 5 summarizes some of the differences in methods of measuring frequency Table 7 5 Frequency Measurement Method Comparison Measures Measures High Low Number of Number of Frequency Frequency Counters Measurements Signals Signals Method Used Returned Accurately Accurately Low frequency wi
178. e of the output signal Visit ni com support for more information about minimizing glitches 5 2 ni com X Series User Manual Analog Output Data Generation Methods When performing an analog output operation you can perform software timed or hardware timed generations Software Timed Generations With a software timed generation software controls the rate at which data is generated Software sends a separate command to the hardware to initiate each DAC conversion In NI DAQmx software timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing a single value out such as a constant DC voltage Hardware Timed Generations With a hardware timed generation a digital hardware signal controls the rate of the generation This signal can be generated internally on your device or provided externally Hardware timed generations have several advantages over software timed generations e The time between samples can be much shorter e The timing between samples can be deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or hardware timed single point HWTSP A buffer is a temporary storage in computer memory for to be transferred samples Hardware timed single point HWTSP Typically HWTSP operations are used to write single samples at known time interv
179. e thermocouple output before digitizing it The manipulation of signals to prepare them for digitizing is called signal conditioning For more information about sensors refer to the following documents For general information about sensors visit ni com sensors e Ifyou are using LabVIEW refer to the LabVIEW Help by selecting Help Search the LabVIEW Help in LabVIEW and then navigate to the Taking Measurements book on the Contents tab e Ifyou are using other application software refer to Common Sensors in the NI DAQmx Help or the LabVIEW Help Signal Conditioning Options SCXI SCXI is a front end signal conditioning and switching system for various measurement devices including X Series devices An SCXI system consists of a rugged chassis that houses shielded signal conditioning modules that amplify filter isolate and multiplex analog signals from thermocouples or other transducers SCXI is designed for large measurement systems or systems requiring high speed acquisition DE Note NI 6356 6358 6366 6368 Devices Simultaneous MIO SMIO X Series devices only support controlling SCXI in parallel mode System features include the following e Modular architecture Choose your measurement technology e Expandability Expand your system to 3 072 channels Integration Combine analog input analog output digital I O and switching into a single unified platform High bandwidth Acquire signals at high rates e Conn
180. e writes samples to the buffer After the DAQ device captures the specified number of pretrigger samples the DAQ device begins to look for the reference trigger condition If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples the DAQ device ignores the condition Ifthe buffer becomes full the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample This data can be accessed with some limitations before the DAQ device discards it Refer to the KnowledgeBase document Can a Pretriggered Acquisition be Continuous for more information To access this KnowledgeBase go to ni com info and enter the Info Code rdcanq When the reference trigger occurs the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired Figure 4 23 shows the final buffer Figure 4 23 Reference Trigger Final Buffer Reference Trigger Pretrigger Samples Posttrigger Samples ii T Complete Buffer 4 32 ni com X Series User Manual Using a Digital Source To use AI Reference Trigger with a digital source specify a source and an edge The source can be any of the following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe_ DSTAR lt A B gt Change Detection Event e Counter n Internal Output e DI Reference Trigger di ReferenceTrigger e DO
181. ectivity Select from SCXI modules with thermocouple connectors or terminal blocks 2 8 ni com X Series User Manual SCC SCC is a front end signal conditioning system for X Series plug in data acquisition devices An SCC system consists of a shielded carrier that holds up to 20 single or dual channel SCC modules for conditioning thermocouples and other transducers SCC is designed for small measurement systems where you need only a few channels of each signal type or for portable applications SCC systems also offer the most comprehensive and flexible signal connectivity options System features include the following e Modular architecture Select your measurement technology on a per channel basis e Small channel systems Condition up to 16 analog input and eight digital I O lines Low profile portable Integrates well with other laptop computer measurement technologies e Connectivity lIncorporates panelette technology to offer custom connectivity to thermocouple BNC LEMO B Series and MIL Spec connectors Note PCI Express X Series Devices PCI Express users should consider the power limits on certain SCC modules without an external power supply Refer to the specifications for your device and the PCI Express Device Disk Drive Power Connector section of Chapter 3 Connector and LED Information for information about power limits and increasing the current the device can supply on the 5 V terminal DE Note NI 6
182. ed Pulse Measurement Sample Clocked Buffered Pulse Measurement e Hardware Timed Single Point Pulse Measurement Single Pulse Measurement Single on demand pulse measurement is equivalent to two single pulse width measurements on the high H and low L ticks of a pulse as shown in Figure 7 8 Figure 7 8 Single On Demand Pulse Measurement Counter Armed i 1 f 1 i i i i Source i Latched Value i 2 8 4 68 6 7 1 2 9 4 5 6 F amp 9 10 NT i Implicit Buffered Pulse Measurement In an implicit buffered pulse measurement on each edge of the Gate signal the counter stores the count in the FIFO A DMA controller transfers the stored values to host memory The counter begins counting when it is armed The arm usually occurs between edges on the Gate input but the counting does not start until the desired edge You can select whether to read the high pulse or low pulse first using the StartingEdge property in NI DAQmx 7 8 ni com X Series User Manual Figure 7 9 shows an example of an implicit buffered pulse measurement Figure 7 9 Implicit Buffered Pulse Measurement Counter Armed Gate
183. ee pinouts pinouts counter default 7 42 device 1 8 NI PCle PXIe 6341 A 4 NI PCle PXIe 6361 A 14 NI PCIe PXIe 6363 A 19 NI PCIe 6320 A 2 NI PCIe 6321 A 4 NI PCIe 6323 6343 A 8 NI PCle 635 1 6361 A 14 A 15 A 16 A 20 NI PCle 6353 6363 A 19 NIPXIe 6345 6355 A 12 NI PXTe 6356 6366 A 25 NI PXIe 6358 6368 A 31 NI PXIe 6365 A 33 NI PXIe 6375 A 36 NI USB 6343 A 9 NI USB 635 1 6361 A 15 A 16 A 20 NI USB 6356 6366 A 28 NI USB 6363 USB A 23 RTSI connector 3 6 9 5 pins default 7 42 position measurement 7 21 buffered 7 23 power 5 V 3 4 connector PCI Express disk drive 3 5 power up states 6 18 8 6 X Series User Manual prescaling 7 46 programmable function interface PFD 8 1 power up states 6 18 8 6 programmed I O 10 2 programming devices in software 2 9 pulse encoders 7 23 generation for ETS 7 35 train generation 7 28 continuous 7 30 pulse width measurement implicit buffered 7 6 single 7 6 PXI and PXI Express 10 3 clock 10 2 clock and trigger signals 9 7 trigger signals 10 2 triggers 9 8 PXI Express and PXI 10 3 chassis compatibility 10 3 clock 10 2 clock and trigger signals 9 7 considerations 10 2 PXIe CLK100 9 7 PXIe SYNC100 9 7 PXIe DSTAR lt A C gt 9 8 PXI CLK10 9 8 PXI STAR filters 9 8 trigger 9 8 PXIe CLK100 9 7 PXIe SYNC100 9 7 PXIe DSTAR lt A C gt 9 8 Q quadrature encoders 7 21 R range analog input MIO X Series devices 4 2
184. eeceeeesecaeeaeeaeeaecaecaecaecaeeseeaeeeeens 5 5 AO Start Trigger Signal ss 5 6 Retriggerable Analog Output ss 5 6 Using a Digital Source AR NES rm nent 5 6 Using an Analog Source cecceccecceseesecsecseeeescensesenseess n asters 5 7 Routing AO Start Trigger Signal to an Output Terminal 000 eee eeeeeeee 5 7 AO Pause Trigger Signal sssesrtemnhetltenehss dise t rt fer EEEE EE 5 7 Using Digital Source nine hese ete eee eda eee 5 8 Using an Analog Source ii 5 8 Routing AO Pause Trigger Signal to an Output Terminal 5 8 AO Sample Clock Signal 5 8 Using an Internal Source 5 8 Using an External Source ecececesesseesecsecsecseencesceseeeeeeeeeeeeeeeeeeeeeteteeeeeees 5 9 Routing AO Sample Clock Signal to an Output Terminal 0 0 0 eee 5 9 Other Timing Requirements 0 cceccesssscceeceeceseeseseesecaecaecaeceecseeseeneeeeeeeeeeees 5 9 AO Sample Clock Timebase Signal 5 10 Getting Started with AO Applications in Software cccccesccesesseeeesecseeeeeseeseeseeeeeeeees 5 10 Chapter 6 Digital I O Digital Input Data Acquisition Methods Software Timed Acquisitions cee Hardware Timed Acquisitions Digital Input Trig periti Esasen uate Ee Ee ee tn rt tee Digital Waveform Acquisition DI Sample Clock Signal siennes Using an Internal Source Using an External Source Routing DI Sample Clock to an Output Terminal Other Timing Requirement
185. enerates the Frequency Output signal The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16 The Frequency Output Timebase can be either the 20 MHz Timebase the 20 MHz Timebase divided by 2 or the 100 kHz Timebase The duty cycle of Frequency Output is 50 if the divider is either 1 or an even number For an odd divider suppose the divider is set to D In this case Frequency Output is low for D 1 2 cycles and high for D 1 2 cycles of the Frequency Output Timebase Figure 7 37 shows the output waveform of the frequency generator when the divider is set to 5 Figure 7 37 Frequency Generator Output Waveform Frequency Output rimebase LE LI LE LE ITI U U FREQ OUT Divisor 5 o 7 84 ni com X Series User Manual Frequency Output can be routed out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal All PFI terminals are set to high impedance at startup The FREQ OUT signal can also be routed to many internal timing signals In software program the frequency generator as you would program one of the counters for pulse train generation For information about connecting counter signals refer to the Default Counter Timer Pinouts section Frequency Division The counters can generate a signal with a frequency that is a fraction of an input signal This function is equivalent to continuous pulse train generation Refer to the Continuous Puls
186. eous sample and hold circuitry and relays For more specific information about these products refer to ni com Refer to the Custom Cabling and Connectivity section of this chapter and the Field Wiring Considerations section of Chapter 4 Analog Input for information about how to select accessories for your X Series device National Instruments 2 3 Chapter 2 DAQ System Overview PCI Express PXI Express and USB Mass Termination Device Cables and Accessories This section describes some cable and accessory options for X Series devices with one two three or four 68 pin connectors Refer to ni com for other accessory options including new devices SCXI Accessories SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your X Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Note NI 6356 6358 6366 6368 Devices Simultaneous MIO SMIO X Series devices only support controlling SCXI in parallel mode Use Connector 0 of your X Series device to control SCXI in parallel and multiplexed mode NI DAQmx only supports SCXI in parallel mode on Connector 1 2 or 3 Note When using Connector 1 2 or 3 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold Refer to the SCX7 Advisor available by going to ni com info and entering the Info Code rdscad for more information SC
187. er ai ReferenceTrigger AI Start Trigger ai StartTrigger e AO Start Trigger ao StartTrigger e Counter n Internal Output e DI Start Trigger di StartTrigger DI Reference Trigger di ReferenceTrigger Change Detection Event e PXI STAR e PXIe DSTAR lt A B gt The source can also be one of several internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the waveform generation begins on the rising edge or falling edge of DO Start Trigger Using an Analog Source When you use an analog trigger source the waveform generation begins on the first rising or falling edge of the Analog Comparison Event signal Refer to the Triggering with an Analog Source section of Chapter 11 Triggering for more information Routing DO Start Trigger Signal to an Output Terminal You can route DO Start Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The output is an active high pulse PFI terminals are configured as inputs by default DO Pause Trigger Signal Use the DO Pause Trigger do PauseTrigger signal to mask off samples in a DAQ sequence That is when DO Pause Trigger is active no samples occur DO Pause Trigger does not stop a sample that is in progress The pause does not take effect until the beginning of the next sample 6 16 ni com X Series User Manual When you generate digital o
188. eration of an unspecified number of samples Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation There are several different methods of continuous generation that control what data is written These methods are regeneration FIFO regeneration and non regeneration modes e Regeneration is the repetition of the data that is already in the buffer Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out New data can be written to the PC buffer at any time without disrupting the output Use the NI DAQmx write property RegenMode to allow or not allow regeneration The NI DAQmx default is to allow regeneration e With FIFO regeneration the entire buffer is downloaded to the FIFO and regenerated from there Once the data is downloaded new data cannot be written to the FIFO To use FIFO regeneration the entire buffer must fit within the FIFO size The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started thereby preventing any problems that may occur due to excessive bus traffic Use the NI DAQmx AO channel property UseOnlyOnBoardMemory to enable or disable FIFO regeneration e With non regeneration old data is not repeated New data must be continually written to the buffer If the program does not write new data to the buffer at a fast eno
189. erential connections When to Use Non Referenced Single Ended NRSE Connections with Ground Referenced Signal Sources Only use NRSE connections if the input signal meets the following conditions The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 3 m 10 ft The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions In the single ended modes more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground Refer to the Using Non Referenced Single Ended NRSE Connections for Ground Referenced Signal Sources section for more information about NRSE connections 4 18 ni com X Series User Manual When to Use Referenced Single Ended RSE Connections with Ground Referenced Signal Sources Do not use RSE connections with ground referenced signal sources Use NRSE or DIFF connec
190. eries devices internally transfer data in sample pairs as opposed to single samples This implementation allows for greater data throughput However if an acquisition on these devices acquires an odd number of total samples the last sample acquired cannot be transferred To ensure this condition never occurs NI DAQmx adds a background channel for finite acquisitions that have both an odd number of channels and an odd number of samples per channel The background channel is also added when performing any reference triggered finite acquisition Data from the background channel is only visible when reading in RAW mode For maximum efficiency in bus bandwidth and onboard FIFO use use an even number of samples per channel or an even number of channels for finite acquisitions so the background channel is not added 4 50 ni com X Series User Manual Reference triggers are not retriggerable Using a Digital Source To use AI Start Trigger with a digital source specify a source and an edge The source can be any of the following signals PFI lt 0 15 gt e RTSI lt 0 7 gt e Counter n Internal Output e PXI STAR PXIe DSTAR lt A B gt The source can also be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the measurement acquisition begins on the rising edge or falling edge of AI Start Trigger
191. etween the software layer and the hardware layer Refer to the NJ DAQmx Hardware Timed Single Point Lateness Checking document for more information To access this document go to ni com info and enter the Info Code daghwtsp Note NI USB 634x 6351 6353 6361 6363 Devices USB X Series devices do not support hardware timed single point HWTSP operations National Instruments 4 9 Chapter 4 Analog Input Analog Input Triggering Analog input supports three different triggering actions e Start trigger e Reference trigger e Pause trigger Refer to the AJ Start Trigger Signal AI Reference Trigger Signal and AI Pause Trigger Signal sections for information about these triggers An analog or digital trigger can initiate these actions All MIO X Series devices support digital triggering but some do not support analog triggering To find your device triggering options refer to the specifications document for your device Connecting Analog Input Signals Table 4 3 summarizes the recommended input configuration for both types of signal sources 4 10 ni com X Series User Manual Table 4 3 MIO X Series Analog Input Configuration AI Ground Reference Floating Signal Sources Not Connected to Building Ground Ground Referenced Signal Sourcest Examples Ungrounded thermocouples e Signal conditioning with isolated outputs Example e Plug in instruments with non isolated outputs
192. evenly across the input range So for an input range of 10 V to 10 V the voltage of each code ofa 16 bit ADC is 10V 10V _ 305 uV 716 Simultaneous MIO X Series devices use a calibration method that requires some codes typically about 5 of the codes to lie outside of the specified range This calibration method improves absolute accuracy but it increases the nominal resolution of input ranges by about 5 over what the formula shown above would indicate Choose an input range that matches the expected input range of your signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For more information about setting ranges refer to the NI DAQmx Help or the LabVIEW Help National Instruments 4 37 Chapter 4 Analog Input Table 4 6 shows the input ranges and resolutions supported by the Simultaneous MIO X Series device family Table 4 6 Simultaneous MIO X Series Device Input Range and Nominal Resolution Simultaneous MIO Nominal Resolution Assuming X Series Device Input Range 5 Over Range NI 6356 6358 6366 6368 10 V to 10 V 320 uV 5 Vto5V 160 uV 2 V to2 V 64 uV lVtol V 32 uV Working Voltage Range On most Simultaneous MIO X Series devices the PGIA operates normally by amplifying signals of interest while rejecting common mode
193. evice in differential analog input ground reference mode and I have connected a differential input signal but my readings are random and drift rapidly What is wrong In DIFF mode if the readings from the DAQ device are random and drift rapidly you should check the ground reference connections The signal can be referenced to a level that is considered floating with reference to the device ground reference Even if you are in DIFF mode you must still reference the signal to the same ground level as the device reference There are various methods of achieving this reference while maintaining a high common mode rejection ratio CMRR These methods are outlined in the Connecting Analog Input Signals section of Chapter 4 Analog Input AI GND is an AI common signal that routes directly to the ground connection point on the devices You can use this signal if you need a general analog ground connection point to the device Refer to the When to Use Differential Connections with Ground Referenced Signal Sources section of Chapter 4 Analog Input for more information National Instruments C 1 Appendix C Troubleshooting How can I use the AI Sample Clock and AI Convert Clock signals on an MIO X Series device to sample the AI channel s MIO X Series devices use AI Sample Clock ai SampleClock and AI Convert Clock ai ConvertClock to perform interval sampling As Figure C 1 shows AI Sample Clock controls the sample period which is determine
194. evice model For models not described below refer to the specifications for your device NI 6321 6323 634x Devices The AO reference is always 10 V The analog output range equals 10 V NI 635x 636x 63x5 Devices The AO reference of each analog output AO lt 0 3 gt can be individually set to one of the following 10V 5V APFI lt 0 1 gt You can connect an external signal to APFI lt 0 1 gt to provide the AO reference The AO reference can be a positive or negative voltage If AO reference is a negative voltage the polarity of the AO output is inverted The valid ranges of APFI lt 0 1 gt are listed in the device specifications You can use one of the AO lt 0 3 gt signals to be the AO reference for a different AO signal However you must externally connect this channel to APFI 0 or APFI 1 Note When using an external reference the output signal is not calibrated in software You can generate a value and measure the voltage offset to calibrate your output in software Minimizing Glitches on the Output Signal When you use a DAC to generate a waveform you may observe glitches on the output signal These glitches are normal when a DAC switches from one voltage to another it produces glitches due to released charges The largest glitches occur when the most significant bit of the DAC code changes You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and natur
195. formation Counter n Source Signal The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is performing Table 7 8 lists how the terminal is used in various applications Table 7 8 Counter Applications and Counter n Source Application Purpose of Source Terminal Pulse Generation Counter Timebase One Counter Time Measurements Counter Timebase Two Counter Time Measurements Input Terminal Non Buffered Edge Counting Input Terminal Buffered Edge Counting Input Terminal Two Edge Separation Counter Timebase Routing a Signal to Counter n Source Each counter has independent input selectors for the Counter n Source signal Any of the following signals can be routed to the Counter n Source input e 100 MHz Timebase e 20 MHz Timebase e 100 kHz Timebase RTSI lt 0 7 gt e PFI lt 0 15 gt e PXI CLK10 e PXI STAR PXIe DSTAR lt A B gt e Analog Comparison Event Change Detection Event National Instruments 7 37 Chapter 7 Counters In addition TC or Gate from a counter can be routed to a different counter source Some of these options may not be available in some driver software Routing Counter n Source to an Output Terminal You can route Counter n Source out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal All PFIs are set to high impedance at startup Counter n Gate Signal The
196. ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the NI PGIA and this difference is rejected by the amplifier If the input circuitry of a device were referenced to ground as it is in the RSE ground reference setting this difference in ground potentials would appear as an error in the measured voltage Using the DAQ Assistant you can configure the channels for RSE or NRSE input modes Refer to the Configuring AI Ground Reference Settings in Software section for more information about the DAQ Assistant Field Wiring Considerations Environmental noise can seriously affect the measurement accuracy of the device if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to AI signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect AI signals to the device With this type of wire the signals attached to the positive and negative input channels are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic f
197. gure 4 28 The sample counter is loaded with the specified number of posttrigger samples in this example five The value decrements with each pulse on AI Sample Clock until the value reaches zero and all desired samples have been acquired Figure 4 28 Typical Posttriggered DAQ Sequence Al Start Trigger Al Sample Clock Sample Counter 2 1 An acquisition with pretrigger data allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 29 shows a typical pretrigger DAQ sequence The AI Start Trigger signal ai StartTrigger can be either a hardware or software signal If AI Start Trigger is set up to be a software start trigger an output pulse appears on the ai StartTrigger line when the acquisition begins When the AI Start Trigger pulse occurs the sample counter is loaded with the number of pretrigger samples in this example four The value decrements with each pulse on AI Sample Clock until the value reaches zero The sample counter is then loaded with the number of posttrigger samples in this example three Figure 4 29 Typical Pretriggered DAQ Sequence Al Start Trigger Al Reference Trigger Don t Care Al Sample Clock Sample Counter 3 i If an AI Reference Trigger ai ReferenceTrigger pulse occurs before the specified number of pret
198. he Al signals e Treat the DAQ device as you would treat any static sensitive device Always properly ground yourself and the equipment when handling the DAQ device or connecting to it Programmable Power Up States At system startup and reset the hardware sets all PFI and DIO lines to high impedance inputs by default The DAQ device does not drive the signal high or low Each line has a weak pull down resistor connected to it as described in the specifications document for your device NI DAQmx supports programmable power up states for PFI and DIO lines Software can program any value at power up to the PO P1 or P2 lines The PFI and DIO lines can be set as A high impedance input with a weak pull down resistor default e An output driving a 0 e An output driving a 1 Refer to the N DAQmx Help or the LabVIEW Help for more information about setting power up states in NI DAQmx or MAX Note When using your X Series device to control an SCXI chassis DIO lines 0 1 2 and 4 are used as communication lines and must be left to power up in the default high impedance state to avoid potential damage to these signals 8 6 ni com Digital Routing and Clock Generation The digital routing circuitry has the following main functions e Manages the flow of data between the bus interface and the acquisition generation sub systems analog input analog output digital I O and the counters The digital routing circuitry uses FIFOs
199. he DAQ Assistant you can configure the channels for RSE or NRSE input modes Refer to the Configuring AI Ground Reference Settings in Software section for more information about the DAQ Assistant Using Referenced Single Ended RSE Connections for Floating Signal Sources Figure 4 9 shows how to connect a floating signal source to the MIO X Series device configured for RSE mode Figure 4 9 RSE Connections for Floating Signal Sources Al lt 0 31 gt oO So 6 sos Programmable Gain Instrumentation Amplifier Floating s 4 Signal Source SNE g so Input Multiplexers o Al SENSE Measured Voltage 0 AI GND 1 0 Connector Selected Channel in RSE Configuration Note NI USB 6341 6343 6361 6363 BNC Devices To measure a floating signal source on X Series USB BNC devices move the switch under the BNC connector to the FS position Using the DAQ Assistant you can configure the channels for RSE or NRSE input modes Refer to the Configuring AI Ground Reference Settings in Software section for more information about the DAQ Assistant Connecting Ground Referenced Signal Sources What Are Ground Referenced Signal Sources A ground referenced signal source is a signal source connected to the building system ground It is already connected to a common ground point with respect to the device assuming that the computer is plugged into the same p
200. he Microsoft Visual Studio help To view this help file from within Visual Studio select Measurement Studio NI Measurement Studio Help For information related to developing with NI DAQm x refer to the following topics within the NJ Measurement Studio Help e For step by step instructions on how to create an NI DAQmx application using the Measurement Studio Application Wizard and the DAQ Assistant refer to Walkthrough Creating a Measurement Studio NI DAQmx Application B 2 ni com X Series User Manual e For help with NI DAQmx methods and properties refer to the NationalInstruments DAQmx namespace and the NationalInstruments DAQmx ComponentModel namespace e For conceptual help with NI DAQmx refer to Using the Measurement Studio NI DAQmx NET Library and Creating Projects with Measurement Studio NI DAQmx e For general help with programming in Measurement Studio refer to Getting Started with the Measurement Studio Class Libraries To create an NI DAQmx application using Visual Basic NET or Visual C follow these general steps 1 In Visual Studio select File New Project to launch the New Project dialog box 2 Choose a programming language Visual C or Visual Basic NET and then select Measurement Studio to see a list of project templates 3 Select NI DAQ Windows Application You add DAQ tasks as part of this step Choose a project type You add DAQ tasks as a part of this step ANSI C without NI Applicati
201. he signal source and the device ground Refer to the Using Referenced Single Ended RSE Connections for Floating Signal Sources section for more information about RSE connections Using Differential Connections for Floating Signal Sources It is important to connect the negative lead of a floating source to AI GND either directly or through a bias resistor Otherwise the source may float out of the maximum working voltage range of the NI PGIA and the DAQ device returns erroneous data The easiest way to reference the source to AI GND is to connect the positive side of the signal to AI and connect the negative side of the signal to AI GND as well as to AI without using resistors This connection works well for DC coupled sources with low source impedance less than 100 Q DE Note NIUSB 6341 6343 6361 6363 BNC Devices To measure a floating signal source on X Series USB BNC devices move the switch under the BNC connector to the FS position National Instruments 4 13 Chapter 4 Analog Input Figure 4 4 Differential Connections for Floating Signal Sources without Bias Resistors MIO X Series Device Al Floating Signal Source Al Inpedance lt 100 Q Al SENSE Al GND However for larger source impedances this connection leaves the DIFF signal path significantly off balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because
202. ic e Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or hardware timed single point A buffer is a temporary storage in computer memory for to be transferred samples Buffered Data is moved from the DAQ device s onboard FIFO memory to a PC buffer using DMA before it is transferred to application memory Buffered acquisitions typically allow for much faster transfer rates than non buffered acquisitions because data is moved in large blocks rather than one point at a time One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous Finite sample mode acquisition refers to the acquisition of a specific predetermined number of data samples Once the specified number of samples has been read in the acquisition stops If you use a reference trigger you must use finite sample mode Continuous acquisition refers to the acquisition of an unspecified number of samples Instead of acquiring a set number of data samples and stopping a continuous 6 2 ni com X Series User Manual acquisition continues until you stop the operation Continuous acquisition is also referred to as double buffered or circular buffered acquisition If data cannot be transferred across the bus fast enough the FIFO becomes full New acquisitions overwrites data in the FIFO before it can be transferred to host memory which causes the device to generat
203. ications in Software You can use the MIO X Series device in the following analog input applications e Single point analog input on demand e Finite analog input e Continuous analog input e Hardware timed single point You can perform these applications through DMA or programmed I O data transfer mechanisms Some of the applications also use start reference and pause triggers Note For more information about programming analog input applications and triggers in software refer to the NJ DAQmx Help or the LabVIEW Help MIO X Series devices use the NI DAQmx driver NI DAQm x includes a collection of programming examples to help you get started developing an application You can modify example code and save it in an application You can use examples to develop a new application or add example code to an existing application To locate LabVIEW LabWindows CVI Measurement Studio Visual Basic and ANSI C examples refer to the KnowledgeBase document Where Can I Find NI DAQmx Examples by going to ni com info and entering the Info Code daqmxexp For additional examples refer to ni com examples National Instruments 4 35 Chapter 4 Analog Input Analog Input on Simultaneous MIO X Series Devices Figure 4 25 shows the analog input circuitry of the Simultaneous MIO X Series devices Figure 4 25 Simultaneous MIO X Series Analog Input Circuitry NI PGIA ADC Al FIFO Al Data 1 0 Connector ADC
204. ields or high electromagnetic interference Refer to the Field Wiring and Noise Considerations for Analog Signals document for more information To access this document go to ni com info and enter the Info Code rdfwn3 National Instruments 4 21 Chapter 4 Analog Input Analog Input Timing Signals In order to provide all of the timing functionality described throughout this section MIO X Series devices have a flexible timing engine Figure 4 12 summarizes all of the timing options provided by the analog input timing engine Also refer to the Clock Routing section of Chapter 9 Digital Routing and Clock Generation Figure 4 12 Analog Input Timing Options PFI RTSI PEL RTS PXI_STAR PXI_STAR Analog Comparison Event Al Sample Clock Analog Comparison Ctr n Internal Output Le Event Al Sample Clock SW Pulse 4 20 MHz Timebase Timebase Programmable Clock 100 kHz Timebase J Divider a PXI_CLK10 4 PFI RTSI 100 MHz Timebase PXI_STAR Analog Comparison Event Al Convert Clock Ctr n Internal Output Le Al Convert Clock Timebase Programmable e Clock Divider MIO X Series devices use AI Sample Clock ai SampleClock and AI Convert Clock ai ConvertClock to perform interval sampling As Figure 4 13 shows AI Sample Clock controls the sample period which is determined by the following equation 1 Sample Period Sample Rate Figure 4 13
205. ightening the two thumbscrews 1 6 ni com X Series User Manual USB Device LEDs NI USB 634X 635x 636x Devices Refer to the USB Device LED Patterns section of Chapter 3 Connector and LED Information for information about the USB X Series device READY and ACTIVE LEDs USB Cable Strain Relief NI USB 634X 635x 636x Devices You can provide strain relief for the USB cable by using the jackscrew on the locking USB cable included in the USB X Series device kit to securely attach the cable to the device as shown in Figure 1 6 Figure 1 6 USB Cable Strain Relief on USB X Series Devices 1 Locking USB Cable Jackscrew 2 Jackscrew Hole 3 Security Cable Slot National Instruments 1 7 Chapter 1 Getting Started USB Device Security Cable Slot NI USB 634X 635x 636x Devices The security cable slot shown in Figure 1 6 allows you to attach an optional laptop lock to your USB X Series device Note The security cable is designed to act as a deterrent but might not prevent the device from being mishandled or stolen For more information refer to the documentation that accompanied the security cable Note The security cable slot on the USB device might not be compatible with all laptop lock cables Device Pinouts Refer to Appendix A Device Specific Information for X Series device pinouts Device Specifications Refer to the device specifications document for your device X Series device documentatio
206. igure 6 6 Halt Internal Clock and Free Running External Clock A T A T 4 H DI Sample Clock DI Pause Trigger Halt Used on Internal Clock DI External Sample Clock DI Sample Clock DI Pause Trigger Free Running Used on External Clock Using a Digital Source To use DI Pause Trigger specify a source and a polarity The source can be any of the following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt e Counter n Internal Output e Counter n Gate e Al Pause Trigger ai PauseTrigger e AO Pause Trigger ao PauseTrigger e DO Pause Trigger do PauseTrigger The source can also be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source When you use an analog trigger source the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high or vice versa 6 10 ni com X Series User Manual Routing DI Pause Trigger Signal to an Output Terminal You can route DI Pause Trigger out to any RTSI lt 0 7 gt PFI lt 0 15 gt PXI STAR or PXIe DSTARC terminal Note Pause triggers are only sensitive to the level of the source not the edge Digital Output Data
207. igure 7 21 channel Z is never high when channel A is high and channel B is low Thus the reload must occur in some other phase In Figure 7 21 the reload phase is when both channel A and channel B are low The reload occurs when the phase is true and channel Z is high Incrementing and decrementing takes priority over reloading Thus when the channel B goes low to enter the reload phase the increment occurs first The reload occurs within one maximum timebase period after the reload phase becomes true After the reload occurs the counter continues to count as before Figure 7 21 illustrates channel Z reload with X4 decoding Figure 7 21 Channel Z Reload with X4 Decoding ChA chas m Chz Max Timebase L Li Counter Value dal aa fee 0 0 1 NW gt ou il 7 22 ni com X Series User Manual Measurements Using Two Pulse Encoders The counter supports two pulse encoders that have two channels channels A and B The counter increments on each rising edge of channel A The counter decrements on each rising edge of channel B as shown in Figure 7 22 Figure 7 22 Measurements Using Two Pulse Encoders ChA l i ChB r Counter Value 2 X 3 X 4 X 5 X 4 X 3 X 4 For information about connecting counter signals refer to the Default Counter Timer Pinouts section Buffered Sample Clock Position Measureme
208. ike analog input analog output digital input and digital output X Series counters do not have the ability to divide down a timebase to produce an internal counter sample clock For sample clocked operations an external signal must be provided to supply a clock source The source can be any of the following signals e AI Sample Clock e AI Start Trigger AI Reference Trigger e AO Sample Clock e DI Sample Clock DI Start Trigger e DO Sample Clock e CTR Internal Output Freq Out e PFI lt 0 15 gt PXI Trig lt 0 7 gt e PXIe DSTAR lt A B gt Change Detection Event e Analog Comparison Event Not all timed counter operations require a sample clock For example a simple buffered pulse width measurement latches in data on each edge of a pulse For this measurement the measured signal determines when data is latched in These operations are referred to as implicit timed operations However many of the same measurements can be clocked at an interval with a sample clock These are referred to as sample clocked operations Table 7 1 shows the different options for the different measurements 4 Note All hardware timed single point HWTSP operations are sample clocked Table 7 1 Counter Timing Measurements Implicit Timing Sample Clocked Measurement Support Timing Support Buffered Edge Count No Yes Buffered Pulse Width Yes Yes Buffered Pulse Yes Yes Buffered Semi Period Yes No 7
209. iming slot and the other peripheral slots The Star Trigger can be used to synchronize multiple devices or to share a common trigger signal among devices A Star Trigger controller can be installed in this system timing slot to provide trigger signals to other peripheral modules Systems that do not require this functionality can install any standard peripheral module in this system timing slot An X Series device receives the Star Trigger signal PXI_STAR from a Star Trigger controller PXI STAR can be used as an external source for many AI AO and counter signals An X Series device is not a Star Trigger controller An X Series device can be used in the system timing slot of a PXI system but the system will not be able to use the Star Trigger feature PXI_STAR Filters You can enable a programmable debouncing filter on each PFI RTSI PXIe DSTAR or PXI STAR signal Refer to the PFI Filters section of Chapter 8 PFI for more information PXle_DSTAR lt A C gt PXI Express devices can provide high quality and high frequency point to point connections between each slot and a system timing slot These connections come in the form of three low voltage differential star triggers that create point to point high frequency connections between a PXI Express system timing module and a peripheral device Using multiple connections enable you to create more applications because of the increased routing capabilities 9 8 ni com X Series User M
210. ion begins the DAQ device writes samples to the buffer After the DAQ device captures the specified number of pretrigger samples the DAQ device begins to look for the reference trigger condition If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples the DAQ device ignores the condition Ifthe buffer becomes full the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample This data can be accessed with some limitations before the DAQ device discards it Refer to the KnowledgeBase document Can a Pretriggered Acquisition be Continuous for more information To access this KnowledgeBase go to ni com info and enter the Info Code rdcanq When the reference trigger occurs the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired Figure 4 32 shows the final buffer Figure 4 32 Reference Trigger Final Buffer Reference Trigger Pretrigger Samples Posttrigger Samples T Complete Buffer Using a Digital Source To use AI Reference Trigger with a digital source specify a source and an edge The source can be any of the following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt Change Detection Event Counter n Internal Output DI Reference Trigger di ReferenceTrigger e AO Start Trigger ao
211. isition Software sends a separate command to the hardware to initiate each ADC conversion In NI DAQmx software timed acquisitions are referred to as having on demand timing Software timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data 4 8 ni com X Series User Manual Hardware Timed Acquisitions With hardware timed acquisitions a digital hardware signal AI Sample Clock controls the rate of the acquisition This signal can be generated internally on your device or provided externally Hardware timed acquisitions have several advantages over software timed acquisitions The time between samples can be much shorter e The timing between samples is deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or hardware timed single point HWTSP A buffer is a temporary storage in computer memory for to be transferred samples Buffered In a buffered acquisition data is moved from the DAQ device s onboard FIFO memory to a PC buffer using DMA before it is transferred to application memory Buffered acquisitions typically allow for much faster transfer rates than HWTSP acquisitions because data is moved in large blocks rather than one point at a time One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous Finite sample mode a
212. it is connected to ground This noise appears as a differential mode signal instead of acommon mode signal and thus appears in your data In this case instead of directly connecting the negative line to AI GND connect the negative line to AI GND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise This configuration does not load down the source other than the very high input impedance of the NI PGIA Figure 4 5 Differential Connections for Floating Signal Sources with Single Bias Resistor MIO X Series Device Al Floating Signal Vs Source Al R is about 100 times R Al SENSE source O Al GND impedance of sensor You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND as shown in Figure 4 6 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 kQ and produce a 1 gain error 4 14 ni com X Series User Manual Figure 4 6 Differential Connections for F
213. ital output trigger signals 6 12 triggering 6 12 digital routing 9 1 digital signals Change Detection Event 6 19 connecting 6 23 Counter n Sample Clock 7 40 DI Sample Clock 6 4 DO Sample Clock 6 13 digital source triggering 11 1 digital waveform acquisition 6 4 generation 6 13 disk drive power PCI Express 3 5 disk drive power connector PCI Express devices 3 5 DMA as a transfer method 10 1 controllers 10 1 DO Sample Clock signal 6 13 do SampleClock 6 13 documentation related documentation B 1 double buffered acquisition MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 39 E edge counting 7 3 buffered 7 4 on demand 7 4 sample clock 7 4 single point 7 4 edge separation measurement buffered two signal 7 25 single two signal 7 24 encoders quadrature 7 21 encoding X1 7 21 X2 7 21 X4 7 22 equivalent time sampling 7 35 example programs B 1 exporting timing output signals using PFI terminals 8 2 external reference clock 9 2 external source greater than 40 MHz 7 47 less than 40 MHz 7 47 F features counter 7 45 field wiring considerations MIO X Series devices 4 21 Simultaneous MIO X Series devices 4 44 FIFO Simultaneous MIO X Series devices 4 36 X Series User Manual filters PFI 8 4 PXI STAR 9 8 RTSI 9 7 floating signal sources connecting MIO X Series devices 4 12 description MIO X Series devices 4 12 using in differential mode
214. itiator device receive the 10 MHz reference clock from RTSI or PFI This signal becomes the external reference clock A PLL on each device generates the internal timebases synchronous to the external reference clock Once all of the devices are using or referencing a common timebase you can synchronize operations across them by sending a common start trigger out across the RTSI or PFI bus and setting their sample clock rates to the same value National Instruments 9 3 Chapter 9 Digital Routing and Clock Generation USB Devices With the PFI bus and the routing capabilities of USB X Series devices there are several ways to synchronize multiple devices depending on your application To synchronize multiple devices to a common timebase choose one device the initiator to generate the timebase The initiator device routes its 10 MHz reference clock to one of the PFI lt 0 15 gt signals All devices including the initiator device receive the 10 MHz reference clock from PFI This signal becomes the external reference clock A PLL on each device generates the internal timebases synchronous to the external reference clock Once all of the devices are using or referencing a common timebase you can synchronize operations across them by sending a common start trigger out across the PFI bus and setting their sample clock rates to the same value Real Time System Integration RTSI Real Time System Integration RTSD is a signal b
215. k You can route any of the following signals to be the AO Sample Clock Timebase signal e 100 MHz Timebase default 20 MHz Timebase e 100 kHz Timebase PXI_CLK10 e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt Analog Comparison Event an analog trigger AO Sample Clock Timebase is not available as an output on the I O connector You can use an external sample clock signal as AO Sample Clock Timebase signal by dividing the signal down in a DAQ device You can also use it as AO Sample Clock signal without dividing the signal Getting Started with AO Applications in Software You can use an X Series device in the following analog output applications e Single point on demand generation e Finite generation e Continuous generation e Waveform generation You can perform these generations through programmed I O or DMA data transfer mechanisms Some of the applications also use start triggers and pause triggers Note For more information about programming analog output applications and triggers in software refer to the NJ DAQmx Help or the LabVIEW Help 5 10 ni com X Series User Manual X Series devices use the NI DAQmx driver NI DAQmx includes a collection of programming examples to help you get started developing an application You can modify example code and save it in an application You can use examples to develop a new application or add example code to an existing application
216. l DO Start Trigger Signal e DO Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section of Chapter 8 PFI for more information DO Sample Clock Signal The device uses the DO Sample Clock do SampleClock signal to update the DO terminals with the next sample from the DO waveform generation FIFO You can specify an internal or external source for DO Sample Clock You can also specify whether the DAC update begins on the rising edge or falling edge of DO Sample Clock If the DAQ device receives a DO Sample Clock when the FIFO is empty the DAQ device reports an underflow error to the host software Using an Internal Source One of the following internal signals can drive DO Sample Clock e DI Sample Clock di SampleClock e DO Sample Clock do SampleClock AI Sample Clock ai SampleClock e AI Convert Clock ai ConvertClock e AO Sample Clock ao SampleClock e Counter n Sample Clock e Counter n Internal Output National Instruments 6 13 Chapter 6 Digital I O Frequency Output e DI Change Detection output Several other internal signals can be routed to DO Sample Clock through internal routes Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an External Source Use one of the following external signals as the source of DO Sample Clock PFI lt 0 15 gt d RTSI lt 0 7 gt PXI STAR PXIe DSTAR lt A B
217. le 7 9 X Series PCI Express PXI Express USB Mass a Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help NI 6345 6355 Device Specifications Refer to the M 6345 Device Specifications for more detailed information about the NI 6345 device Refer to the M 6355 Device Specifications for more detailed information about the NI 6355 device NI 6345 6355 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAO System Overview for more information National Instruments A 13 Appendix A Device Specific Information NI 6351 6361 The following sections contain information about the NI PCIe 6351 NI USB 6351 Screw Terminal NI PCle PXIe 6361 and NI USB 6361 devices NI 6351 6361 Pinout Figure A 9 shows the pinout of the NI PCIe 6351 and NI PCle PXIe 6361 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 9 NI PCle 6351 and NI PCle PXle 6361 Pinout N Alo Alo 68 34 Als Alo Al GND 67 33 Al1 Al 14 AI9 A11 66 32 Al GND Al2 Al2 65 31 Al 10 Al 2 Al GN
218. loating Signal Sources with Balanced Bias Resistors Bias Resistors see text Instrumentation Amplifier Floating Signal Vs Source PGIA Measured Voltage Vm Bias Current Return Paths so Input Multiplexers AI SENSE AI GND V 1 0 Connector MIO X Series Device Configured in Differential Mode Both inputs of the NI PGIA require a DC path to ground in order for the NI PGIA to work If the source is AC coupled capacitively coupled the NI PGIA needs a resistor between the positive input and AI GND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 1 MQ In this case connect the negative input directly to AI GND If the source has high output impedance balance the signal path as previously described using the same value resistor on both the positive and negative inputs be aware that there is some gain error from loading down the source as shown in Figure 4 7 National Instruments 4 15 Chapter 4 Analog Input Figure 4 7 Differential Connections for AC Coupled Floating Sources with Balanced Bias Resistors AC Coupling MIO X Series Device 1k Al AC Coupled Floating v Signal S Source Al AI SENSE
219. lock Al External Sample Clock Al Sample Clock Al Pause Trigger Free Running Used on External Clock Using a Digital Source To use AI Pause Trigger specify a source and a polarity The source can be any of the following signals e PFI lt 0 15 gt RTSI lt 0 7 gt e PXI STAR e PXIe DSTAR lt A B gt e Counter n Internal Output e Counter n Gate e AO Pause Trigger ao PauseTrigger National Instruments 4 53 Chapter 4 Analog Input e DI Pause Trigger di PauseTrigger e DO Pause Trigger do PauseTrigger The source can also be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information Using an Analog Source When you use an analog trigger source the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high or vice versa Routing Al Pause Trigger Signal to an Output Terminal You can route AI Pause Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt PXI STAR or PXIe DSTARC terminal Note Pause triggers are only sensitive to the level of the source not the edge Getting Started with AI Applications in Software You can use the Simultaneous MIO X Series device in the following analog input applications e Simultaneous sampling e Single point analog input e Finite ana
220. log Input 3 2 ni com X Series User Manual Table 3 1 I O Connector Signals Continued Signal Name Reference Direction Description AI SENSE AI SENSE 2 AI SENSE 3 AI SENSE 4 Input Analog Input Sense In NRSE mode the reference for each AI lt 0 15 gt signal is AI SENSE the reference for each AI lt 16 31 gt signal is AI SENSE 2 the reference for each AI lt 80 143 gt is AI SENSE 3 and the reference for each AI lt 144 207 gt is AI SENSE 4 Also refer to the Connecting Ground Referenced Signal Sources section of Chapter 4 Analog Input AO lt 0 3 gt AO GND Output Analog Output Channels 0 to 3 These terminals supply the voltage output of AO channels 0 to 3 AO GND Analog Output Ground AO GND is the reference for AO lt 0 3 gt All three ground references AI GND AO GND and D GND are connected on the device D GND Digital Ground D GND supplies the reference for PO lt 0 31 gt PFI lt 0 15 gt P1 P2 and 5 V All three ground references AI GND AO GND and D GND are connected on the device PO lt 0 31 gt D GND Input or Output Port 0 Digital I O Channels 0 to 31 You can individually configure each signal as an input or output APFI lt 0 1 gt AO GND or AI GND Input Analog Programmable Function Interface Channels 0 to 1 Each APFI signal can be used as AO external reference inputs for AO lt 0 3 g
221. log input e Continuous analog input You can perform these applications through DMA or programmed I O data transfer mechanisms Some of the applications also use start and reference pause triggers Note For more information about programming analog input applications and triggers in software refer to the NJ DAQmx Help or the LabVIEW Help in version 8 0 or later Simultaneous MIO X Series devices use the NI DAQmx driver NI DAQmx includes a collection of programming examples to help you get started developing an application You can modify example code and save it in an application You can use examples to develop a new application or add example code to an existing application To locate LabVIEW LabWindows CVI Measurement Studio Visual Basic and ANSI C examples refer to the KnowledgeBase document Where Can I Find NI DAQmx Examples by going to ni com info and entering the Info Code daqmxexp For additional examples refer to ni com examples 4 54 ni com Analog Output Many X Series devices have analog output functionality X Series devices that support analog output have either two or four AO channels that are controlled by a single clock and are capable of waveform generation Refer to Appendix A Device Specific Information for information about the capabilities of your device Figure 5 1 shows the analog output circuitry of X Series devices Figure 5 1 X Series Analog Output Circuitry Aoo Daco H aoi paci
222. log window triggering 11 5 analog to digital converter MIO X Series devices 4 2 Simultaneous MIO X Series devices 4 36 ANSI C documentation B 3 AO FIFO 5 1 AO Pause Trigger signal 5 7 AO reference selection 5 1 AO reference selection settings 5 2 AO Sample Clock 5 1 AO Sample Clock signal 5 8 AO Sample Clock Timebase signal 5 10 AO Start Trigger signal 5 6 ao PauseTrigger 5 7 ao SampleClock 5 8 ao StartTrigger 5 6 APFI lt 0 1 gt terminals 11 2 applications counter input 7 3 X Series User Manual counter output 7 26 edge counting 7 3 applying rubber feet 1 5 arm start trigger 7 45 avoiding scanning faster than necessary MIO X Series devices 4 8 B buffered edge counting 7 4 hardware timed acquisitions MIO X Series devices 4 9 Simultaneous MIO X Series devices 4 39 hardware timed generations 5 3 6 12 position measurement 7 23 two signal edge separation measurement 7 25 bus interface 10 1 RTSI 9 4 C cable management 1 5 cables 2 3 2 7 choosing for your device 1 8 custom 2 7 NI 6320 A 3 NI 6321 6341 A 7 NI 6323 6343 A 11 NI 6345 6355 A 13 NI 6351 6361 A 18 NI 6353 6363 A 24 NI 6356 6366 A 30 NI 6358 6368 A 32 NI 6365 A 35 NI 6375 A 38 X Series devices 2 4 calibration 1 2 circuitry 2 3 cascading counters 7 45 cDAQ chassis example programs B 1 National Instruments 1 3 Index Change Detection Event signal 6 19 channel scanning order
223. ls must be in the scan list Analog Trigger Actions The output of the analog trigger detection circuit is the Analog Comparison Event signal You can program your DAQ device to perform an action in response to the Analog Comparison Event signal The action can affect the following e Analog input acquisition e Analog output generation e Digital input behavior e Digital output behavior e Counter behavior National Instruments 11 3 Chapter 11 Triggering Routing Analog Comparison Event to an Output Terminal You can route Analog Comparison Event out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal Analog Trigger Types Configure the analog trigger circuitry to different triggering modes Analog Edge Triggering Configure the analog trigger circuitry to detect when the analog signal is below or above a level you specify In below level analog triggering mode shown in Figure 11 4 the trigger is generated when the signal value is less than Level Figure 11 4 Below Level Analog Triggering Mode Analog Comparison Event In above level analog triggering mode shown in Figure 11 5 the trigger is generated when the signal value is greater than Level Figure 11 5 Above Level Analog Triggering Mode Analog Comparison Event Analog Edge Triggering with Hysteresis Hysteresis adds a programmable voltage region above or below the trigger level that an i
224. lse train timing diagram Figure 7 30 Finite Pulse Train Timing in Legacy Mode Counter 1 Paired Counter Counter 0 Generation Complete Retriggerable Pulse or Pulse Train Generation The counter can output a single pulse or multiple pulses in response to each pulse on a hardware Start Trigger signal The generated pulses appear on the Counter n Internal Output signal of the counter You can route the Start Trigger signal to the Gate input of the counter You can specify a delay from the Start Trigger to the beginning of each pulse You can also specify the pulse width The delay and pulse width are measured in terms of a number of active edges of the Source input The initial delay can be applied to only the first trigger or to all triggers using the CO EnablelnitalDelayOnRetrigger property The default for a single pulse is True while the default for finite pulse trains is False The counter ignores the Gate input while a pulse generation is in progress After the pulse generation is finished the counter waits for another Start Trigger signal to begin another pulse generation For retriggered pulse generation pause triggers are not allowed since the pause trigger also uses the gate input National Instruments 7 29 Chapter 7 Counters Figure 7 31 shows a generation of two pulses with a pulse delay of five and a pulse width of three using the rising edge of Source with CO EnablelnitalDelayOnRe
225. measurement has the same behavior as a sample clocked buffered two signal separation measurement Refer to the Sample Clocked Buffered Two Signal Separation Measurement section for more information Note Ifan active edge on the Gate and an active edge on the AUX does not occur between sample clocks an overrun error occurs Note NI USB 634x 635x 636x Devices USB X Series devices do not support hardware timed single point HWTSP operations For information about connecting counter signals refer to the Default Counter Timer Pinouts section Counter Output Applications The following sections list the various counter output applications available on X Series devices Simple Pulse Generation Pulse Train Generation Frequency Generation e Frequency Division e Pulse Generation for ETS 7 26 ni com X Series User Manual Simple Pulse Generation Refer to the following sections for more information about the X Series simple pulse generation options e Single Pulse Generation e Single Pulse Generation with Start Trigger Single Pulse Generation The counter can output a single pulse The pulse appears on the Counter n Internal Output signal of the counter You can specify a delay from when the counter is armed to the beginning of the pulse The delay is measured in terms of a number of active edges of the Source input You can specify a pulse width The pulse width is also measured in terms of a
226. ment is similar to pulse width measurement except that there are two measurement signals Aux and Gate An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting You must arm a counter to begin a two edge separation measurement After the counter has been armed and an active edge occurs on the Aux input the counter counts the number of rising or falling edges on the Source The counter ignores additional edges on the Aux input The counter stops counting upon receiving an active edge on the Gate input The counter stores the count in the FIFO You can configure the rising or falling edge of the Aux input to be the active edge You can configure the rising or falling edge of the Gate input to be the active edge Use this measurement type to count events or measure the time that occurs between edges on two signals This type of measurement is sometimes referred to as start stop trigger measurement second gate measurement or A to B measurement Refer to the following sections for more information about the X Series edge separation measurement options Single Two Signal Edge Separation Measurement Implicit Buffered Two Signal Edge Separation Measurement Sample Clocked Buffered Two Signal Separation Measurement e Hardware Timed Single Point Two Signal Separation Measurement Single Two Signal Edge Separation Measurement With single two signal edge separation measurement the c
227. mple Clock 4 24 AI Sample Clock Timebase 4 26 AI Start Trigger 4 30 channels sampling with AI Sample Clock and AI Convert Clock C 2 circuitry 4 1 connecting 4 10 connecting signals 4 10 connecting through I O connector 4 1 data acquisition methods 4 8 getting started with applications in software 4 35 ground reference settings 4 1 MUX 4 1 range 4 2 sampling channels with AI Sample Clock and AI Convert Clock C 2 signals 4 22 timing signals 4 22 triggering 4 10 Simultaneous MIO X Series devices AI Hold Complete Event 4 49 AI Pause Trigger 4 53 AI Reference Trigger 4 51 AI Sample Clock 4 47 AI Sample Clock Timebase 4 49 circuitry 4 36 connecting signals 4 41 connecting through I O connector 4 36 data acquisitions 4 38 methods 4 38 fundamentals 4 36 overview 4 36 signals 4 45 terminal configuration 4 37 timing signals 4 45 timing summary 4 46 triggering 4 40 troubleshooting C 1 analog output circuitry 5 1 connecting signals 5 5 data generation methods 5 3 fundamentals 5 1 getting started with applications in software 5 10 glitches on the output signal 5 2 reference selection 5 2 signals 5 5 AO Pause Trigger 5 7 AO Sample Clock 5 8 AO Sample Clock Timebase 5 10 AO Start Trigger 5 6 timing signals 5 5 trigger signals 5 4 triggering 5 4 troubleshooting C 2 analog source triggering 11 2 analog trigger 11 2 accuracy 11 6 actions 11 3 improving accuracy 11 6 ana
228. mum resolution of the ADC MIO X Series devices use the NI PGIA to deliver high accuracy even when sampling multiple channels with small input ranges at fast rates MIO X Series devices can sample channels in any order and you can individually program each channel in a sample with a different input range e A D Converter The analog to digital converter ADC digitizes the AI signal by converting the analog voltage into a digital number AI FIFO MIO X Series devices can perform both single and multiple A D conversions of a fixed or infinite number of samples A large first in first out FIFO buffer holds data during AI acquisitions to ensure that no data is lost MIO X Series devices can handle multiple A D conversion operations with DMA or programmed I O Analog Input Range Input range refers to the set of input voltages that an analog input channel can digitize with the specified accuracy The NI PGIA amplifies or attenuates the AI signal depending on the input range You can individually program the input range of each AI channel on your MIO X Series device The input range affects the resolution of the MIO X Series device for an AI channel Resolution refers to the voltage of one ADC code For example a 16 bit ADC converts analog inputs into one of 65 536 216 codes that is one of 65 536 possible digital values These values are spread fairly evenly across the input range So for an input range of 10 V to 10 V the voltage
229. n either of the following situations National Instruments 3 5 Chapter 3 Connector and LED Information e You need more power than listed in the device specifications e You are using an SCC accessory without an external power supply such as the SC 2345 Refer to the specifications document for your device for more information about PCI Express power requirements and current limits Disk Drive Power Connector Installation Before installing the disk drive power connector you must install and set up the PCI Express X Series device as described in the DAQ Getting Started guides Complete the following steps to install the disk drive power connector 1 Power off and unplug the computer 2 Remove the computer cover 3 Attach the PC disk drive power connector to the disk drive power connector on the device as shown in Figure 3 2 Note The power available on the disk drive power connectors in a computer can vary For example consider using a disk drive power connector that is not in the same power chain as the hard drive Figure 3 2 Connecting to the Disk Drive Power Connector 1 Device Disk Drive Power Connector 2 PC Disk Drive Power Connector 4 Replace the computer cover and plug in and power on the computer RTSI Connector Pinout NI PCle 632x 634x 635x 636x Devices Refer to the RTS Connector Pinout section of Chapter 9 Digital Routing and Clock Generation for information about the RTSI connector
230. n enable the DIO change detection circuitry to detect rising edges falling edges or either edge individually on each DIO line The DAQ devices synchronize each DI signal to the 100 MHz Timebase and then sends the signal to the change detectors The circuitry ORs the output of all enabled change detectors from every DI signal The result of this OR is the Change Detection Event signal Change detection performs bus correlation by considering all changes within a 50 ns window one change detection event which keeps signals on the same bus synchronized in samples and prevents overruns National Instruments 6 19 Chapter 6 Digital 1 O The Change Detection Event signal can do the following e Drive any RTSI lt 0 7 gt PFI lt 0 15 gt or PXI STAR signal e Drive the DO Sample Clock or DI Sample Clock e Generate an interrupt The Change Detection Event signal can also be used to detect changes on digital output events DI Change Detection Applications The DIO change detection circuitry can interrupt a user program when one of several DIO signals changes state You can also use the output of the DIO change detection circuitry to trigger a DI or counter acquisition on the logical OR of several digital signals To trigger on a single digital signal refer to the Triggering with a Digital Source section of Chapter 11 Triggering By routing the Change Detection Event signal to a counter you can also capture the relative time between b
231. n is available on ni com manuals Device Accessories and Cables NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information 1 8 ni com DAQ System Overview Figure 2 1 shows a typical DAQ system which includes sensors transducers signal conditioning devices cables that connect the various devices to the accessories the X Series device programming software and PC The following sections cover the components of a typical DAQ system Figure 2 1 Components of a Typical DAQ System mmi 6 0 Signal Cables and DAQ DAQ Personal Computer Conditioning Accessories Hardware Software or Sensors and Transd PXI Express transducers Chassis National Instruments 2 1 Chapter 2 DAQ System Overview DAQ Hardware DAQ hardware digitizes signals performs D A conversions to generate analog output signals and measures and controls digital I O signals Figure 2 2 features components common to all X Series devices Figure 2 2 General X Series Block Diagram 1 Analog Input Analog Output 5 8 Digital 2 Routing Bus Digital O and Clock Interface BUS O Generation Counters RTSI PFI DAQ STC3 The DAQ STC3 and DAQ 6202 implement a high performance digit
232. n notify software if it falls behind hardware These features make HWTSP ideal for real time control applications HWTSP operations in conjunction with the wait for next sample clock function provide tight synchronization between the software layer and the hardware layer Refer to the N DAQmx Hardware Timed Single Point Lateness Checking document for more information To access this document go to ni com info and enter the Info Code daghwtsp DE Note NI USB 634x 635x 636x Devices USB X Series devices do not support hardware timed single point HWTSP operations National Instruments 6 11 Chapter 6 Digital I O Buffered In a buffered generation data is moved from a PC buffer to the DAQ device s onboard FIFO using DMA before it is written to the output lines one sample at a time Buffered generation typically allow for much faster transfer rates than non buffered acquisitions because data is moved in large blocks rather than one point at a time One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous Finite sample mode generation refers to the generation of a specific predetermined number of data samples Once the specified number of samples has been written out the generation stops Continuous generation refers to the generation of an unspecified number of samples Instead of generating a set number of data samples and stopping a continuous generation continues u
233. n you use an analog trigger source the samples are paused when the Analog Comparison Event signal is at a high level Refer to the Triggering with an Analog Source section of Chapter 11 Triggering for more information Routing DO Pause Trigger Signal to an Output Terminal You can route DO Pause Trigger out to any RTSI lt 0 7 gt PFI lt 0 15 gt or PXIe DSTARC terminal I O Protection Each DIO and PFI signal is protected against overvoltage undervoltage and overcurrent conditions as well as ESD events However you should avoid these fault conditions by following these guidelines Ifyou configure a PFI or DIO line as an output do not connect it to any external signal source ground or power supply e Ifyou configure a PFI or DIO line as an output understand the current requirements of the load connected to these signals Do not exceed the specified current output limits of the DAQ device NI has several signal conditioning solutions for digital applications requiring high current drive e Ifyou configure a PFI or DIO line as an input do not drive the line with voltages outside of its normal operating range The PFI or DIO lines have a smaller operating range than the AI signals e Treat the DAQ device as you would treat any static sensitive device Always properly ground yourself and the equipment when handling the DAQ device or connecting to it Programmable Power Up States At system startup and reset the hard
234. nal Descriptions section of Chapter 3 Connector and LED Information Figure A 7 NI USB 6343 BNC Pinout E gt ANALOG INPUT PA 2P13 R E 2 re 3 I 3 wn n g 4 c Lu 8 O0O000000000000000 0000000000800 DDDOODODODDOODODODOODODOOODODOODODODOODDOOO SOOOOO66606660666666666666666666 gt HHHHHHHHHHHHHHHHHHHHHHHHHHHHHH EE DIGITAL AND TIMING 1 0 mm PFI APIA L PA 7P17 cHs GND NI USB 6343 power 16 Inputs 16 Bit 500 kS s X Series Multifunction DAQ Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help A 10 ni com X Series User Manual NI 6323 6343 Device Specifications Refer to the NJ 6323 Specifications for more detailed information about the NI 6323 device Refer to the MI 6343 Specifications for more detailed information about the NI 6343 device NI 6323 6343 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information National Instruments A 11 Appendix A Device Specific Information NI 6345 6355 The following sections co
235. nchronization 9 3 NI 6320 A 2 NI 6321 6341 A 4 NI 6323 6343 A 8 NI 6345 6355 A 12 NI 6353 6363 A 19 pinouts 1 8 self calibration 1 2 specifications 1 8 DI change detection 6 19 DI Sample Clock signal 6 4 di SampleClock 6 4 DIFF connections using with floating signal sources MIO X Series devices 4 13 using with ground referenced signal sources MIO X Series devices 4 19 when to use with floating signal sources MIO X Series devices 4 12 when to use with ground referenced signal sources MIO X Series devices 4 18 differential analog input troubleshooting C 1 differential connections for ground referenced signal sources Simultaneous MIO X Series devices 4 42 for non referenced or floating signal sources Simultaneous MIO X Series devices 4 43 l 6 ni com using with floating signal sources MIO X Series devices 4 13 using with ground referenced signal sources MIO X Series devices 4 19 when to use with floating signal sources MIO X Series devices 4 12 when to use with ground referenced signal sources MIO X Series devices 4 18 digital waveform acquisition 6 4 waveform generation 6 13 digital I O block diagram 6 1 circuitry 6 1 connecting signals 6 23 DI change detection 6 19 digital waveform generation 6 13 getting started with applications in software 6 24 T O protection 6 18 programmable power up states 6 18 static DIO 6 2 triggering 11 1 waveform acquisition 6 4 dig
236. ne High Variable Clocked Counter Frequency Large Range f 50 000 50 000 50 000 50 000 fk 100 M 100 M 1 000 100 M Measurement time 1 02 1 1 mS N 50 Max frequency error 512 25 1 000 Wa Hz Max error 00102 05 2 001 From these results you can see that while the measurement time for one counter is shorter the accuracy is best in the sample clocked and two counter large range measurements For another example Table 7 4 shows the results for 5 MHz Table 7 4 5 MHz Frequency Measurement Methods Two Counter Sample One High Variable Clocked Counter Frequency Large Range f 5M 5M 5M 5M fk 100 M 100 M 1 000 100 M Measurement time 1 0002 1 1 mS N 5 000 Max Frequency error 50 01 263 k 1 000 50 Hz Max Error 001 5 26 02 001 7 18 ni com X Series User Manual Again the measurement time for the one counter measurement is lowest but the accuracy is lower Note that the accuracy and measurement time ofthe sample clocked and two counter large range are almost the same The advantage of the sample clocked method is that even when the frequency to measure changes the measurement time does not and error percentage varies little For example if you configured a large range two counter measurement to use a divide down of 50 for a 50 k signal then you would get the accuracy measurement time and accuracy listed in Table 7 3 But if your signal ramped u
237. nfigured as inputs by default Using a Delay from Sample Clock to Convert Clock When using the AI timing engine to generate your Convert Clock you can also specify a configurable delay from AI Sample Clock to the first AI Convert Clock pulse within the sample By default this delay is three ticks of AI Convert Clock Timebase Figure 4 17 shows the relationship of AI Sample Clock to AI Convert Clock Figure 4 17 Al Sample Clock and Al Convert Clock Al Convert Clock Timebase Al Sample Clock Al Convert Clock i i i lt gt q gt Delay from Convert Sample Period Clock Other Timing Requirements The sample and conversion level timing of MIO X Series devices work such that some clock signals are gated off unless the proper timing requirements are met For example the device ignores both AI Sample Clock and AI Convert Clock until it receives a valid AI Start Trigger signal Similarly the device ignores all AI Convert Clock pulses until it recognizes an AI Sample Clock pulse Once the device receives the correct number of AI Convert Clock pulses it ignores subsequent AI Convert Clock pulses until it receives another AI Sample Clock However after the device recognizes an AI Sample Clock pulse it causes an error if it receives an AI Sample Clock pulse before the correc
238. ng AI Ground Reference Settings in Software cceceeeeeeeee 4 6 Multichannel Scanning Considerations ccesccescssceseececeeseeseescescescesceeeeeeeneenees 4 6 Analog Input Data Acquisition Methods 4 8 Software Timed Acquisitions 4 8 Hardware Timed Acquisitions 4 9 Analog Input Triggering ss 4 10 Connecting Analog Input Signals 0 ccc cececeesesseeseeseeseeseeseesceseeseeseeeeeeecececeeeaes 4 10 Connecting Floating Signal Sources 4 12 What Are Floating Signal Sources 4 12 When to Use Differential Connections with Floating Signal Sources 4 12 When to Use Non Referenced Single Ended NRSE Connections with Floating Signal Sources 4 12 When to Use Referenced Single Ended RSE Connections with Floating Signal Sources Using Differential Connections for Floating Signal Sources Using Non Referenced Single Ended NRSE Connections for Floating Signal Sources cccccecsessesscescsecsecssescesseseeeseeseesceseeseeeeteeeteeeeeaees 4 16 Using Referenced Single Ended RSE Connections for Floating Signal Sources c eccecsessesecsscececcescessescecseeseeseeseeseeeteeteeseeeeaees 4 17 Connecting Ground Referenced Signal Sources 0 cccscesseeeceeseeeeceteeseeseeeseeeeeees 4 17 What Are Ground Referenced Signal Sources ccceccecceseeseeseeeereeeeneeeeees 4
239. ng applications accuracy is affected by settling time When your MIO X Series device switches from one AI channel to another AI channel the device configures the NI PGIA with the input range of the new channel The NI PGIA then amplifies the input signal with the gain for the new input range Settling time refers to the time it takes the NI PGIA to amplify the input signal to the desired accuracy before it is sampled by the ADC To determine your device settling time refer to the specifications document for your device MIO X Series devices are designed to have fast settling times However several factors can increase the settling time which decreases the accuracy of your measurements To ensure fast settling times you should do the following in order of importance 1 Use Low Impedance Sources To ensure fast settling times your signal sources should have an impedance of lt 1 kQ Large source impedances increase the settling time of the NI PGIA and so decrease the accuracy at fast scanning rates Settling times increase when scanning high impedance signals due to a phenomenon called charge injection Multiplexers contain switches usually made of switched capacitors When one of the channels for example channel 0 is selected in a multiplexer those capacitors accumulate charge When the next channel for example channel 1 is selected the accumulated charge leaks backward through channel 1 If the output impedance of the 4 6 ni com
240. nnels MIO X Series devices 4 7 installation hardware 1 1 NI DAQ 1 1 other software 1 1 instrumentation amplifier MIO X Series devices 4 1 Simultaneous MIO X Series devices 4 36 interface bus 10 1 internal source less than 40 MHz 7 47 L LabVIEW documentation B 2 LabWindows CVI documentation B 2 LED patterns USB devices 3 7 low impedance sources MIO X Series devices 4 6 M Measurement Studio documentation B 2 measurements buffered two signal edge separation 7 25 choosing frequency 7 16 frequency 7 11 implicit buffered pulse width 7 6 implicit buffered semi period 7 10 period 7 20 position 7 21 pulse width 7 5 semi period 7 10 single pulse width 7 6 single semi period 7 10 single two signal edge separation 7 24 two signal edge separation 7 24 using quadrature encoders 7 21 using two pulse encoders 7 23 measuring high frequency with two counters 7 12 large range of frequencies using two counters 7 13 low frequency 7 11 methods data transfer 10 1 10 2 X Series User Manual minimizing glitches on the output signal 5 2 output signal glitches C 2 voltage step between adjacent channels MIO X Series devices 4 8 multichannel scanning considerations MIO X Series devices 4 6 multiple device synchronization 9 3 mux MIO X Series devices 4 1 N NET languages documentation B 3 NI 6320 A 2 accessory options A 3 cabling options A 3 pinout A 2 specifications A 3
241. nput signal must pass through before the DAQ device recognizes a trigger condition and is often used to reduce false triggering due to noise or jitter in the signal Analog Edge Trigger with Hysteresis Rising Slope When using hysteresis with a rising slope you specify a trigger level and amount of hysteresis The high threshold is the trigger level the low threshold is the trigger level minus the hysteresis 11 4 ni com X Series User Manual For the trigger to assert the signal must first be below the low threshold then go above the high threshold The trigger stays asserted until the signal returns below the low threshold The output of the trigger detection circuitry is the internal Analog Comparison Event signal as shown in Figure 11 6 Figure 11 6 Analog Edge Triggering with Hysteresis Rising Slope Example Then signal must go above high threshold before Analog Comparison Event asserts FENG Se High threshold Level Hysteresis Egyel SERRES Low threshold Level Hysteresis 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D 1 1 1 1 1 1 i 1 1 1 1 E EE E EA First signal must go A i below low threshold 1 1 Analog Comparison Event Analog Edge Trigger with Hysteresis Falling Slope When using hysteresis with a falling slope you specify a trigger level and amount of hysteresis The low threshold is the trigger level the high threshold is the trigger level
242. nt With buffered position measurement position measurement using a sample clock the counter increments based on the encoding used after the counter is armed The value of the counter is sampled on each active edge of a sample clock A DMA controller transfers the sampled values to host memory The count values returned are the cumulative counts since the counter armed event that is the sample clock does not reset the counter You can route the counter sample clock to the Gate input of the counter You can configure the counter to sample on the rising or falling edge of the sample clock Figure 7 23 shows an example of a buffered X1 position measurement Figure 7 23 Buffered Position Measurement Counter Sample Clock Armed f Sample on Rising Edge ChA ChB Count Buffer National Instruments 7 23 Chapter 7 Counters Hardware Timed Single Point Position Measurement A hardware timed single point HWTSP position measurement has the same behavior as a buffered sample clock position measurement Note NI USB 634x 635x 636x Devices X Series USB devices do not support hardware timed single point HWTSP operations For information about connecting counter signals refer to the Default Counter Timer Pinouts section Two Signal Edge Separation Measurement Two signal edge separation measure
243. ntain information about the NI PXIe 6345 and NI PXIe 6355 devices NI 6345 6355 Pinouts Figure A 8 shows the pinout of the NI PXIe 6345 and NI PXIe 6355 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 8 NI PXle 6345 6355 Pinout pe N Alo alo 68134 AI8 A10 A171 A171 1 35 AI79 AI71 AI GND 67 33 AI 1 Al 14 Al 78 Al 70 2 36 al 70 Al 704 alg alt 66 32 AI GND A1 69 A169 3 37 A177 A169 Al2 al2 65131 A1t0 A12 Ales Al 68 4 38 al 76 Al 68 AI GND 64 30 AI 3 Al 34 A175 A167 5 39 A167 A1674 ali1 Al3 63 29 A1 GND Al 66 Al 66 6 40 A1 74 Al 66 AISENSE 62 28 al4 Al 44 ales A165 7 41 A173 A165 Al12 A14 61 27 AI GND AI72 A164 8 42 Al 64 Al 64 AI5 A15 60ol26 al 13 A155 Al GND 9 43 A1GND AI GND 59 25 Al6 Al 6 A155 Al 55 10 44 ales Al 55 Al 14 Al6 58 24 al GND A1 54 A154 11 45 A162 4154 AI7 A17 57 23 A115 A17 n A Al61 Al53 12146 Al 53 Al 53 AI GND 56 22 A00 9 A1 52 Al52 13
244. nter Trig serine ss sn Bestar eh ave hia Heme ds cee RM Rent 7 45 Other Counter Features 7 45 Cascading Counters sistema dt n ester es ietesr iress 7 45 Prescalinigs ci caccisecsvvccvcivccuctuces cesses ces aessecde cas cuncuteevcaveanens ses dnsces des dbctoscestessnccdschscvedbentese 7 46 Synchronization Modes 7 46 100 MHz Source Mode sisi 7 47 External Source Greater than 25 MHZ 0 ccceccessssscsseseceecssenceeseeseeseeeceseeeeesees 7 47 External or Internal Source Less than 25 MHZ 7 47 Chapter 8 PFI Using PFI Terminals as Timing Input Signals 0 0 0 ccc ccecseesceeeeeceeeeeeceeceeceseeseeaecnsensense 8 2 Exporting Timing Output Signals Using PFI Terminals ec cceeseeseeseeeeeeeeeeeeeeeeeeees 8 2 Using PFI Terminals as Static Digital I Os occ ccccecscescesseseeseeecceececeecesceaecaecaeenecnaeaeenee 8 3 Using PFI Terminals to Digital Detection Events 8 3 Connecting PEL Input Signals siesena aa 8 4 PED Filters sn aise eda im dt teed Wena eed be espe eat eae 8 4 VO ProteCtOnN ns ee rennes hia ania n head ent 8 6 Programmable Power Up States 8 6 National Instruments xi Contents Chapter 9 Digital Routing and Clock Generation Clock ROUTINE HER a nuls lee Nae HOR MEME eh aii E ls 100 MHZ Timebase savent ent inner ni E 20 MHZ Tit b ase 25222520 rer at erea este mes de dome erreur detente 100 KHZ Timebases sir n a E E Rien ta es External Reference Clock 10 MHz
245. ntil you stop the operation There are several different methods of continuous generation that control what data is written These methods are regeneration FIFO regeneration and non regeneration modes Regeneration is the repetition of the data that is already in the buffer Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out New data can be written to the PC buffer at any time without disrupting the output Use the NI DAQmx write property regenMode to allow or not allow regeneration The NI DAQmx default is to allow regeneration With non regeneration old data is not repeated New data must be continually written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer underflows and causes an error With FIFO regeneration the entire buffer is downloaded to the FIFO and regenerated from there Once the data is downloaded new data cannot be written to the FIFO To use FIFO regeneration the entire buffer must fit within the FIFO size The advantage of using FIFO regeneration is that it does not require communication with the main host memory once the operation is started thereby preventing any problems that may occur due to excessive bus traffic Use the NI DAQmx UseOnlyOnBoardMemeory DO channel property to enable or disable FIFO regeneration Digital Output Triggering Digital output supports two diffe
246. o obtain the device power rating Note PCI Express X Series Devices PCI Express X Series devices supply less than 1 A of 5 V power unless you use the disk drive power connector Refer to the PCI Express Device Disk Drive Power Connector section for more information USER 1 and USER 2 The USER 1 and USER 2 BNC connectors allow you to use a BNC connector for a digital or timing I O signal of your choice The USER 1 and USER 2 BNC connectors are routed internally to the USER 1 and USER 2 screw terminals as shown in Figure 3 1 Figure 3 1 USER 1 and USER 2 BNC Connections Screw Terminal Block e Internal Connection USER 1 BNC ut USER1 aoe ag EE USER 2 er D GND 5V i AI GND D GND i AI SENSE USER 2 BNC l Al SENSE 2 APFI 0 E der dE CHS GND od N7 D GND PCI Express Device Disk Drive Power Connector NI PCle 632x 634x 635x 636x Devices The disk drive power connector is a four pin hard drive connector on PCI Express devices that when connected increases the current the device can supply on the 5 V terminal When to Use the Disk Drive Power Connector PCI Express X Series devices without the disk drive power connector installed perform identically to other X Series devices for most applications and with most accessories For most applications it is not necessary to install the disk drive power connector However you should install the disk drive power connector i
247. oad Values 401021032101010 SOURCE ji OUT i J L_4 i 2 2 3 4 2 2 Counter Armed Continuous Buffered Implicit Pulse Train Generation Continuous buffered implicit pulse train generation creates a continuous train of pulses with variable idle and active times Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation Each point you write generates a single pulse All points are generated back to back to create a user defined pulse train Finite Buffered Sample Clocked Pulse Train Generation Finite buffered sample clocked pulse train generation creates a predetermined number of pulse train updates Each point you write defines pulse specifications that are updated with each sample clock When a sample clock occurs the current pulse idle followed by active finishes generation and the next pulse updates with the next sample specifications Note When the last sample is generated the pulse train continues to generate with these specifications until the task is stopped 7 32 ni com X Series User Manual Table 7 7 and Figure 7 35 detail a finite sample clocked generation of three samples where the pulse specifications from the create channel are two ticks idle two ticks active and three ticks initial delay Table 7 7 Finite Buffered Sample Clocked Pulse Train Generation Sample Idle Ticks Active Ticks 1 3 3 2 2 2 3 3 3
248. of each code of a 16 bit ADC is 10V oo 305 uV 2 MIO X Series devices use a calibration method that requires some codes typically about 5 of the codes to lie outside of the specified range This calibration method improves absolute accuracy but it increases the nominal resolution of input ranges by about 5 over what the formula shown above would indicate Choose an input range that matches the expected input range of your signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For more information about setting ranges refer to the N DAQmx Help or the LabVIEW Help 4 2 ni com X Series User Manual Table 4 1 shows the input ranges and resolutions supported by each MIO X Series device Table 4 1 MIO X Series Device Input Range and Nominal Resolution Nominal Resolution MIO X Series Device Input Range Assuming 5 Over Range NI 632x 634x 10 Vto 10 V 320 uV 5 Vto5 V 160 uV 1 Vtol V 32 uV 200 mV to 200 mV 6 4 uV NI 6351 6353 63x5 10 V to 10 V 320 uV FRS 5 Vto5 V 160 uV 2 V to2 V 64 uV 1 Vtol V 32 uV 500 mV to 500 mV 16 uV 200 mV to 200 mV 6 4 uV 100 mV to 100 mV 3 2 uV Working Voltage Range On most MIO X Series devices the PGIA operates normally by amplifying signals of interest while
249. ogram does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer underflows and causes an error Continuous Buffered Sample Clocked Pulse Train Generation Continuous buffered sample clocked pulse train generation creates a continuous train of pulses with variable idle and active times Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation Each point you write National Instruments 7 33 Chapter 7 Counters specifies pulse specifications that are updated with each sample clock When a sample clock occurs the current pulse finishes generation and the next pulse uses the next sample specifications Frequency Generation You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit as described in the Using the Frequency Generator section Using the Frequency Generator The frequency generator can output a square wave at many different frequencies The frequency generator is independent of the four general purpose 32 bit counter timer modules on X Series devices Figure 7 36 shows a block diagram of the frequency generator Figure 7 36 Frequency Generator Block Diagram Frequency Output 20 MHz Timebase 2 Timebase e Frequency Generator o FREQ OUT 100 kHz Timebase ______ Divisor 1 16 The frequency generator g
250. oice For a period of ninety 90 days from the date of invoice NI warrants that i its software products will perform substantially in accordance with the applicable documentation provided with the software and ii the software media will be free from defects in materials and workmanship If NI receives notice of a defect or non conformance during the applicable warranty period NI will in its discretion i repair or replace the affected product or ii refund the fees paid for the affected product Repaired or replaced Hardware will be warranted for the remainder of the original warranty period or ninety 90 days whichever is longer If NI elects to repair or replace the product NI may use new or refurbished parts or products that are equivalent to new in performance and reliability and are at least functionally equivalent to the original part or product You must obtain an RMA number from NI before returning any product to NI NI reserves the right to charge a fee for examining and testing Hardware not covered by the Limited Warranty This Limited Warranty does not apply if the defect of the product resulted from improper or inadequate maintenance installation repair or calibration performed by a party other than NI unauthorized modification improper environment use of an improper hardware or software key improper use or operation outside of the specification for the product improper voltages accident abuse or neglect or a haza
251. on Software The N DAQmx Help contains API overviews and general information about measurement concepts Select Start All Programs National Instruments NI DAQmx NI DAQmx Help The NI DAQmx C Reference Help describes the NI DAQmx Library functions which you can use with National Instruments data acquisition devices to develop instrumentation acquisition and control applications Select Start All Programs National Instruments NI DAQmx Text Based Code Support NI DAQm x C Reference Help NET Languages without NI Application Software With the Microsoft NET Framework you can use NI DAQmx to create applications using Visual C and Visual Basic NET without Measurement Studio Refer to the N DAOmx Readme for specific versions supported Training Courses If you need more help getting started developing an application with NI products NI offers training courses To enroll in a course or obtain a detailed course outline refer to ni com training National Instruments B 3 Appendix B Where to Go from Here Technical Support on the Web For additional support refer to ni com support Many DAQ specifications and user guides manuals are available as PDFs You must have Adobe Reader 7 0 or later PDF 1 6 or later installed to view the PDFs Refer to the Adobe Systems Incorporated website at www adobe com to download Adobe Reader Refer to the National Instruments Product Manuals Library at ni com manuals for updated
252. only available on PXI Express devices PXI and PXI Express Clock and Trigger Signals Refer to the PXT_CLK10 PXI Triggers PXI STAR Trigger PXI STAR Filters PXTe_DSTAR lt A C gt PXIe CLK100 and PXIe SYNC100 sections of Chapter 9 Digital Routing and Clock Generation for more information about PXI and PXI Express clock and trigger signals 10 2 ni com X Series User Manual PXI Express PXI Express X Series devices can be installed in any PXI Express slot in PXI Express chassis PXI Express specifications are developed by the PXI System Alliance www pxisa org National Instruments 10 3 Triggering A trigger is a signal that causes an action such as starting or stopping the acquisition of data When you configure a trigger you must decide how you want to produce the trigger and the action you want the trigger to cause All X Series devices support internal software triggering as well as external digital triggering Some devices also support analog triggering For information about the different actions triggers can perform for each sub system of the device refer to the following sections The Analog Input Triggering section of Chapter 4 Analog Input The Analog Output Triggering section of Chapter 5 Analog Output The Counter Triggering section of Chapter 7 Counters A Note Notall X Series devices support analog triggering For more information about triggering compatibility refer to the specifications
253. onnect your AI signals to the MIO X Series device Refer to the Connecting Analog Input Signals section for more information Ground reference settings are programmed on a per channel basis For example you might configure the device to scan 12 channels four differentially configured channels and eight single ended channels MIO X Series devices implement the different analog input ground reference settings by routing different signals to the NI PGIA The NI PGIA is a differential amplifier That is the NI PGIA amplifies or attenuates the difference in voltage between its two inputs The NI PGIA drives the ADC with this amplified voltage The amount of amplification the gain is determined by the analog input range as shown in Figure 4 2 Figure 4 2 MIO X Series Device NI PGIA Vins o PGIA Measured o V Voltage in Vm Vins Vin x Gain Table 4 2 shows how signals are routed to the NI PGIA on MIO X Series devices Table 4 2 Signals Routed to the NI PGIA on MIO X Series Devices Signals Routed to the Signals Routed to the Al Ground Reference Positive Input of the Negative Input of the Settings NI PGIA Vin NI PGIA Vin RSE AI lt 0 207 gt AI GND NRSE AI lt 0 15 gt AI SENSE AI lt 16 79 gt AI SENSE 2 AI lt 80 143 gt AI SENSE 3 AI lt 144 207 gt AI SENSE 4 4 4 ni com Table 4 2 Signals Routed to the NI PGIA on MIO X Series Devices
254. or DIFF measurements All three ground references AI GND AO GND and D GND are connected on the device AI lt 0 207 gt Varies Input Analog Input Channels 0 to 207 MIO X Series Devices For single ended measurements each signal is an analog input voltage channel In RSE mode AI GND is the reference for these signals In NRSE mode the reference for each AI lt 0 15 gt signal is AI SENSE the reference for each AI lt 16 79 gt signal is AI SENSE 2 the reference for each AI lt 80 143 gt is AI SENSE 3 and the reference for each AI lt 144 207 gt is AI SENSE 4 For differential measurements on MIO X Series devices AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0 Similarly the following signal pairs also form differential input channels AI lt 1 9 gt AI lt 2 10 gt AI lt 3 11 gt AI lt 4 12 gt AI lt 5 13 gt AI lt 6 14 gt AI lt 7 15 gt AI lt 16 24 gt AI lt 17 25 gt AI lt 18 26 gt AI lt 19 27 gt AI lt 20 28 gt AI lt 21 29 gt AI lt 22 30 gt AI lt 23 31 gt and so on Also refer to the Connecting Ground Referenced Signal Sources section of Chapter 4 Analog Input Simultaneous MIO X Series Devices For differential measurements on Simultaneous MIO X Series devices AI 0 and AI 0 are the positive and negative inputs of differential analog input channel 0 Also refer to the Connecting Analog Input Signals section of Chapter 4 Ana
255. ounter counts the number of rising or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO and ignores other edges on its inputs Software then reads the stored count 7 24 ni com X Series User Manual Figure 7 24 shows an example of a single two signal edge separation measurement Figure 7 24 Single Two Signal Edge Separation Measurement Counter Armed r amp Measured Interval gt 4 AUX GATE i f SOURCE Counter Value 0 D 0 0 1 2 3 4 5 6 7 8 8 8 Latched Value 8 Implicit Buffered Two Signal Edge Separation Measurement Implicit buffered and single two signal edge separation measurements are similar but implicit buffered measurement measures multiple intervals The counter counts the number of rising or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in the FIFO On the next active edge of the Gate signal the counter begins another measurement A DMA controller transfers the stored values to host memory Figure 7 25 shows an example of an implicit buffered two signal edge separation measurement Figure 7 25 Implicit Buffered Two Signal Edge Separation Measurement AUX 4
256. ower system as the source Non isolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but the difference can be much higher if power distribution circuits are improperly connected If a grounded signal source is incorrectly measured this difference can appear as measurement error Follow the connection instructions National Instruments 4 17 Chapter 4 Analog Input for grounded signal sources to eliminate this ground potential difference from the measured signal When to Use Differential Connections with Ground Referenced Signal Sources Use DIFF input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V The leads connecting the signal to the device are greater than 3 m 10 ft The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Two analog input channels AI and AI are available DIFF signal connections reduce noise pickup and increase common mode noise rejection DIFF signal connections also allow input signals to float within the common mode limits of the NI PGIA Refer to the Using Differential Connections for Ground Referenced Signal Sources section for more information about diff
257. p 1e TERMINAL 68 TERMINAL 35 TERMINAL 68 TERMINAL 35 A 20 ni com X Series User Manual Note Refer to Table 7 9 X Series PCI Express PXI Express USB Mass Termination USB BNC Device Default NI DAQmx Counter Timer Pins for a list of the default NI DAQmx counter timer pins for this device For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help National Instruments A 21 Appendix A Device Specific Information Figure A 15 shows the pinout of the NI USB 6353 6363 Screw Terminal For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 15 NI USB 6353 6363 Screw Terminal Pinout noaio ape 7 Ataa aeaea aay Se A20 a 20 aisalo 21 Sips an2a Alza alte 34 I Sf 50 A28 ar20 eei Ss sec Aaea EEE AIT AI TI ANS Al 17 Al 17 36 IS CEE Asang 5 Set aas star 37 KI S5 A29 A21 EUR 8 S 23 ASAIO Aan 38 S S z EE AL2 Al2 7 KS Re Al18 A118 39 IY Al 22 aoa 8 iS Gl 24 Al 14 Al 6 A126 A118 401 Gl 56 Al 30 Al 22 ie AT eee eee
258. p to 5 M then with a divide down of 50 your measurement time is 0 01 ms but your error is now 0 1 The error with a sample clocked frequency measurement is not as dependent on the measured frequency so at 50 k and 5 M witha measurement time of 1 ms the error percentage is still close to 0 001 One of the disadvantages of a sample clocked frequency measurement is that the frequency to be measured must be at least twice the sample clock rate to ensure that a full period of the frequency to be measured occurs between sample clocks Low frequency measurements with one counter is a good method for many applications However the accuracy of the measurement decreases as the frequency increases e High frequency measurements with two counters is accurate for high frequency signals However the accuracy decreases as the frequency of the signal to measure decreases At very low frequencies this method may be too inaccurate for your application Another disadvantage of this method is that it requires two counters if you cannot provide an external signal of known width An advantage of high frequency measurements with two counters is that the measurement completes in a known amount of time e Measuring a large range of frequencies with two counters measures high and low frequency signals accurately However it requires two counters and it has a variable sample time and variable error dependent on the input signal e Again the measurement tim
259. plus the hysteresis For the trigger to assert the signal must first be above the high threshold then go below the low threshold The trigger stays asserted until the signal returns above the high threshold The output of the trigger detection circuitry is the internal Analog Comparison Event signal as shown in Figure 11 7 Figure 11 7 Analog Edge Triggering with Hysteresis Falling Slope Example First signal must go above high threshold High threshold Level Hysteresis c Low threshold Level lt GB La D lt oO o a Then signal must go below low threshold r before Analog Comparison Event asserts Analog Comparison Event i e Analog Window Triggering An analog window trigger occurs when an analog signal either passes into enters or passes out of leaves a window defined by two voltage levels Specify the levels by setting the window Top value and the window Bottom value National Instruments 11 5 Chapter 11 Triggering Figure 11 8 demonstrates a trigger that asserts when the signal enters the window Figure 11 8 Analog Window Triggering Mode Entering Window 1 1 1 1 1 1 i 1 1 1 TOD 8 Se es CR ne ame A An i i 1 1 1 1 i 1 1 1 Analog Comparison Event Analog Trigger Accuracy The analog trigger circuitry compares the voltage of the trigger source to the output of programmable trigger DACs When you configure
260. ppose you want to sample 10 channels over a period of 20 ms and average the results You could acquire 500 points from each channel at a scan rate of 250 kS s Another method would be to acquire 1 000 points from each channel at a scan rate of 500 kS s Both methods take the same amount of time Doubling the number of samples averaged from 500 to 1 000 decreases the effect of noise by a factor of 1 4 the square root of 2 However doubling the number of samples in this example decreases the time the NI PGIA has to settle from 4 us to 2 ts In some cases the slower scan rate system returns more accurate results e Example 2 If the time relationship between channels is not critical you can sample from the same channel multiple times and scan less frequently For example suppose an application requires averaging 100 points from channel 0 and averaging 100 points from channel 1 You could alternate reading between channels that is read one point from channel 0 then one point from channel 1 and so on You also could read all 100 points from channel 0 then read 100 points from channel 1 The second method switches between channels much less often and is affected much less by settling time Analog Input Data Acquisition Methods When performing analog input measurements you either can perform software timed or hardware timed acquisitions Software Timed Acquisitions With a software timed acquisition software controls the rate of the acqu
261. r DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the measurement acquisition begins on the rising edge or falling edge of AI Start Trigger Using an Analog Source When you use an analog trigger source the acquisition begins on the first rising edge of the Analog Comparison Event signal National Instruments 4 31 Chapter 4 Analog Input Routing Al Start Trigger to an Output Terminal You can route AI Start Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The output is an active high pulse All PFI terminals are configured as inputs by default The device also uses AI Start Trigger to initiate pretriggered DAQ operations In most pretriggered applications a software trigger generates AI Start Trigger Refer to the AI Reference Trigger Signal section for a complete description of the use of AI Start Trigger and AI Reference Trigger in a pretriggered DAQ operation Al Reference Trigger Signal Use AI Reference Trigger ai ReferenceTrigger signal to stop a measurement acquisition To use a reference trigger specify a buffer of finite size and a number of pretrigger samples samples that occur before the reference trigger The number of posttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of pretrigger samples Once the acquisition begins the DAQ devic
262. r SCC signal conditioning modules SCB 68 Shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block TB 2706 Front panel mounted terminal block for PXI Express X Series devices TB 2706 not for use with NI 63x5 devices uses Connector 0 of your PXI Express device After a TB 2706 is installed Connector 1 cannot be used RTSI Cables Use RTSI bus cables to connect timing and synchronization signals among PCI PCI Express devices such as X Series M Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables You can use the following cables e SHC68 68 EPM High performance shielded cable designed for M X Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded Note The SHC68 68 EPM cable is recommended for NI 63x5 connector 0 but does not work on NI 63x5 connectors 1 2 or 3 e SHC68 68 Lower cost shielded cable with 34 twisted pairs of wire The cable is recommended for NI 63x5 connectors 1 2 or 3 e RC68 68 Highly flexible unshielded ribbon cable 1 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable works with X Series devices 2 6 ni com X
263. rce Mode ee E TL E a Synchronize Count External Source Greater than 25 MHz With an external source greater than 25 MHz the device synchronizes signals on the rising edge of the source and counts on the third rising edge of the source Edges are pipelined so no counts are lost as shown in Figure 7 41 Figure 7 41 External Source Greater than 25 MHz External Source gt 25 MHz A A Synchronize Count External or Internal Source Less than 25 MHz With an external or internal source less than 25 MHz the device generates a delayed Source signal by delaying the Source signal by several nanoseconds The device synchronizes signals on the rising edge of the delayed Source signal and counts on the following rising edge of the source as shown in Figure 7 42 Figure 7 42 External or Internal Source Less than 25 MHz A Source Synchronize Delayed Source A Count National Instruments 7 47 PFI X Series devices have up to 16 Programmable Function Interface PFI signals In addition X Series devices have up to 32 lines of bidirectional DIO signals Each PFI can be individually configured as the following e A static digital input e A static digital output A timing input signal for AI AO DI DO or counter timer functions A timing output signal from AI AO DI DO or counter timer functions Each PFI input also has a programmabl
264. rd such as lightning flood or other act of nature THE REMEDIES SET FORTH ABOVE ARE EXCLUSIVE AND THE CUSTOMER S SOLE REMEDIES AND SHALL APPLY EVEN IF SUCH REMEDIES FAIL OF THEIR ESSENTIAL PURPOSE EXCEPT AS EXPRESSLY SET FORTH HEREIN PRODUCTS ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND AND NI DISCLAIMS ALL WARRANTIES EXPRESSED OR IMPLIED WITH RESPECT TO THE PRODUCTS INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING THE USE OF OR THE RESULTS OF THE USE OF THE PRODUCTS IN TERMS OF CORRECTNESS ACCURACY RELIABILITY OR OTHERWISE NI DOES NOT WARRANT THAT THE OPERATION OF THE PRODUCTS WILL BE UNINTERRUPTED OR ERROR FREE In the event that you and NI have a separate signed written agreement with warranty terms covering the products then the warranty terms in the separate agreement shall control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation National Instruments respects the intellectual property of others and we ask our users to do the same NI software is protecte
265. re higher in frequency than the Nyquist frequency of the system Figure 7 38 shows an example of pulse generation for ETS the delay from the trigger to the pulse increases after each subsequent Gate active edge Figure 7 38 Pulse Generation for ETS GATE g m y S ji D1 D2 D1 AD D3 D1 2AD OUT For information about connecting counter signals refer to the Default Counter Timer Pinouts section Counter Timing Signals X Series devices feature the following counter timing signals Counter n Source Signal e Counter n Gate Signal Counter n Aux Signal e Counter n A Signal e Counter n B Signal e Counter n Z Signal Countern Up Down Signal Counter n HW Arm Signal Counter n Sample Clock Signal Counter n Internal Output Signal e Counter n TC Signal Frequency Output Signal Note All counter timing signals can be filtered Refer to the PFI Filters section of Chapter 8 PFI for more information 7 86 ni com X Series User Manual In this section n refers to the X Series Counter 0 1 2 or 3 For example Counter n Source refers to four signals Counter 0 Source the source input to Counter 0 Counter 1 Source the source input to Counter 1 Counter 2 Source the source input to Counter 2 or Counter 3 Source the source input to Counter 3 Each of these signals supports digital filtering Refer to the PFI Filters section of Chapter 8 PFI for more in
266. re running in any of the device subsystems 10 MHz Reference Clock The 10 MHz reference clock can be used to synchronize other devices to your X Series device The 10 MHz reference clock can be routed to the RTSI lt 0 7 gt or PFI lt 0 15 gt terminals Other devices connected to the RTSI bus can use this signal as a clock input The 10 MHz reference clock is generated by dividing down the onboard oscillator Synchronizing Multiple Devices The following sections contain information about synchronizing multiple X Series devices PXI Express Devices On PXI Express systems you can synchronize devices to PXIe CLK100 In this application the PXI Express chassis acts as the initiator Each PXI Express module routes PXIe CLK100 to its external reference clock Another option in PXI Express systems is to use PXI STAR The Star Trigger controller device acts as the initiator and drives PXI STAR with a clock signal Each target device routes PXI STAR to its external reference clock PCI Express Devices With the RTSI and PFI buses and the routing capabilities of X Series PCI Express devices there are several ways to synchronize multiple devices depending on your application To synchronize multiple devices to a common timebase choose one device the initiator to generate the timebase The initiator device routes its 10 MHz reference clock to one of the RTSI lt 0 7 gt or PFI lt 0 15 gt signals All devices including the in
267. real time system integration bus 9 4 reciprocal frequency measurement 7 13 National Instruments 1 11 Index reference clock 10 MHz 9 3 external 9 2 referenced single ended connections using with floating signal sources MIO X Series devices 4 17 when to use with floating signal sources MIO X Series devices 4 13 when to use with ground referenced signal sources MIO X Series devices 4 19 related documentation B 1 retriggerable single pulse generation 7 29 routing analog comparison event to an output terminal 11 4 clock 9 1 digital 9 1 RSE configuration MIO X Series devices 4 17 RSE connections using with floating signal sources MIO X Series devices 4 17 when to use with floating signal sources MIO X Series devices 4 13 when to use with ground referenced signal sources MIO X Series devices 4 19 RTSI 9 4 connector pinout 3 6 9 5 filters 9 7 using as outputs 9 6 using terminals as timing input signals 9 6 rubber feet 1 5 S sample clock edge counting 7 4 measurement 7 23 scanning speed MIO X Series devices 4 8 SCC 2 9 SCXI 2 8 self calibration 1 2 l 12 ni com semi period measurement 7 10 implicit buffered 7 10 single 7 10 sensors 2 8 settings analog input ground reference MIO X Series devices 4 3 AO reference selection 5 2 short high quality cabling MIO X Series devices 4 7 signal conditioning options 2 8 signal connections analog input Simultaneous MIO X Series
268. referred to as a posttriggered acquisition Retriggerable Analog Input The AI Start Trigger is also configurable as retriggerable The timing engine generates the sample and convert clocks for the configured acquisition in response to each pulse on an AI Start Trigger signal 4 30 ni com X Series User Manual The timing engine ignores the AI Start Trigger signal while the clock generation is in progress After the clock generation is finished the counter waits for another Start Trigger to begin another clock generation Figure 4 22 shows a retriggerable analog input with three AI channels and four samples per trigger Figure 4 22 Retriggerable Analog Input Al Start Trigger Al Sample Clock ai convert MU UU UU A Note Waveform information from LabVIEW does not reflect the delay between triggers They are treated as a continuous acquisition with constant t0 and dt information Reference triggers are not retriggerable Using a Digital Source To use AI Start Trigger with a digital source specify a source and an edge The source can be any of the following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e Counter n Internal Output PXI STAR e PXIe DSTAR lt A B gt Change Detection Event e AO Start Trigger ao StartTrigger e DI Start Trigger di StartTrigger e DO Start Trigger do StartTrigger The source can also be one of several other internal signals on you
269. rejecting common mode signals under the following three conditions The common mode voltage V m which is equivalent to subtracting AI lt 0 x gt GND from AI lt 0 x gt must be less than 4 10 V This Vom is a constant for all range selections e The signal voltage V which is equivalent to subtracting AI lt 0 x gt from AI lt 0 x gt must be less than or equal to the range selection of the given channel If V is greater than the range selected the signal clips and information are lost e The total working voltage of the positive input which is equivalent to Vem Vs or subtracting AI GND from AI lt 0 x gt must be less than 4 E11 V If any of these conditions are exceeded the input voltage is clamped until the fault condition is removed Analog Input Ground Reference Settings MIO X Series devices support the following analog input ground reference settings Differential mode In DIFF mode the MIO X Series device measures the difference in voltage between two AI signals National Instruments 4 3 Chapter 4 Analog Input Referenced single ended mode In RSE mode the MIO X Series device measures the voltage of an AI signal relative to AI GND Non referenced single ended mode In NRSE mode the MIO X Series device measures the voltage of an AI signal relative to one of the AI SENSE inputs specific for that channel The AI ground reference setting determines how you should c
270. rent triggering actions e Start trigger e Pause trigger An analog or digital trigger can initiate these actions All X Series devices support digital triggering but some do not support analog triggering To find your device s triggering options refer to the specifications document for your device Refer to the DO Start Trigger Signal and DO Pause Trigger Signal sections for more information about these triggering actions 6 12 ni com X Series User Manual Digital Waveform Generation You can generate digital waveforms on the Port 0 DIO lines The DO waveform generation FIFO stores the digital samples X Series devices have a DMA controller dedicated to moving data from the system memory to the DO waveform generation FIFO The DAQ device moves samples from the FIFO to the DIO terminals on each rising or falling edge of a clock signal DO Sample Clock You can configure each DIO signal to be an input a static output or a digital waveform generation output The FIFO supports a retransmit mode In the retransmit mode after all the samples in the FIFO have been clocked out the FIFO begins outputting all of the samples again in the same order For example if the FIFO contains five samples the pattern generated consists of sample 1 2 3 4 5 1 2 3 4 5 1 and so on X Series devices feature the following DO waveform generation timing signals e DO Sample Clock Signal e DO Sample Clock Timebase Signa
271. ries device Figure 4 26 Differential Connection for Ground Referenced Signals on Simultaneous MIO X Series Devices L Simultaneous X Series Device AlO Instrumentation Amplifier Ground Referenced v Signal Source q Al0 Measured Cemmo Voltage Mode Noise Vom and Ground Potential TT AI 0 GND O E ne Al 0 Connections Shown 1 0 Connector 4 Note NI USB 6356 6366 BNC Devices To measure a floating signal source on X Series USB BNC devices move the switch under the BNC connector to the GS position With these types of connections the instrumentation amplifier rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as V m in Figure 4 26 Common Mode Signal Rejection Considerations The instrumentation amplifier can reject any voltage caused by ground potential differences between the signal source and the device In addition the instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the device The instrumentation amplifier can reject common mode signals as long as V and V in input signals are both within the working voltage range of the device 4 42 ni com X Series User Manual Differential Connections for Floating Signal Sources Figure 4 27 shows how to connect a floating or non referenced signal source to a channel on an
272. rigger samples are acquired the trigger pulse is ignored Otherwise when the AI Reference Trigger pulse occurs the sample counter value decrements until the specified number of posttrigger samples have been acquired For more information about start and reference triggers refer to the Analog Input Triggering section Simultaneous MIO X Series devices feature the following analog input timing signals AI Sample Clock Signal AI Sample Clock Timebase Signal AI Hold Complete Event Signal e Al Start Trigger Signal 4 46 ni com X Series User Manual AI Reference Trigger Signal e Al Pause Trigger Signal Signals with an support digital filtering Refer to the PFI Filters section of Chapter 8 PFT for more information Aggregate versus Single Channel Sample Rates Simultaneous MIO X Series devices have one ADC per channel so the single channel maximum sample rate can be achieved on each channel The maximum single channel rate is the fastest you can acquire data on the device from a single or multiple channels and still achieve accurate results The total aggregate determines the maximum bus bandwidth used by the device The total aggregate sample rate is the product of the maximum sample rate for a single channel multiplied by the number of AI channels that the device support Table 4 8 shows the single channels and total aggregate rates for Simultaneous MIO X Series devices Table 4 8 Analog Input Rates for
273. s not occur between sample clocks an overrun error occurs Note NI USB 634x 635x 636x Devices USB X Series devices do not support hardware timed single point HWTSP operations National Instruments 7 9 Chapter 7 Counters For information about connecting counter signals refer to the Default Counter Timer Pinouts section Pulse versus Semi Period Measurements In hardware pulse measurement and semi period are the same measurement Both measure the high and low times of a pulse The functional difference between the two measurements is how the data is returned In a semi period measurement each high or low time is considered one point of data and returned in units of seconds or ticks In a pulse measurement each pair of high and low times is considered one point of data and returned as a paired sample in units of frequency and duty cycle high and low time or high and low ticks When reading data 10 points in a semi period measurement gets an array of five high times and five low times When you read 10 points in a pulse measurement you get an array of 10 pairs of high and low times Also pulse measurements support sample clock timing while semi period measurements do not Semi Period Measurement In semi period measurements the counter measures a semi period on its Gate input signal after the counter is armed A semi period is the time between any two consecutive edges on the Gate input You can route an internal or extern
274. s the rate of the acquisition This signal can be generated internally on your device or provided externally ni com X Series User Manual Hardware timed acquisitions have several advantages over software timed acquisitions The time between samples can be much shorter The timing between samples is deterministic Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or hardware timed single point HWTSP A buffer is a temporary storage in computer memory for to be transferred samples Buffered tIn a buffered acquisition data is moved from the DAQ device s onboard FIFO memory to a PC buffer using DMA before it is transferred to application memory Buffered acquisitions typically allow for much faster transfer rates than HWTSP acquisitions because data is moved in large blocks rather than one point at a time One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous e Finite sample mode acquisition refers to the acquisition of a specific predetermined number of data samples Once the specified number of samples has been read in the acquisition stops If you use a reference trigger you must use finite sample mode Note NI USB 6356 6366 Devices Some X Series devices internally transfer data in sample pairs as opposed to single samples This implementation allows for greater data throughput However if an acquisition on the
275. s the recommended input configuration for different types of signal sources for Simultaneous MIO X Series devices Table 4 7 Simultaneous MIO X Series Analog Input Signal Configuration Floating Signal Sources Not Connected to Ground Referenced Signal Earth Ground Sources Examples Example e Ungrounded thermocouples e Plug in instruments with su u nie non isolated outputs e Signal conditioning with isolated P outputs Input Battery devices Differential ALO ALO DIFF oe OM i AIO 1 Al 0 gt Q R R AI GND AI GND Refer to the Analog Input Terminal Configuration section for descriptions of the input modes Types of Signal Sources When configuring the input channels and making signal connections first determine whether the signal sources are floating or ground referenced Floating Signal Sources A floating signal source is not connected in any way to the building ground system and instead has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolators and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must connect the ground reference of a floating signal to the AI ground of the device to establish a local or onboard reference for the signal Otherwis
276. sample data on the rising or falling edge of DI Sample Clock Routing DI Sample Clock to an Output Terminal You can route DI Sample Clock out to any PFI lt 0 15 gt terminal The PFI circuitry inverts the polarity of DI Sample Clock before driving the PFI terminal Other Timing Requirements Your DAQ device only acquires data during an acquisition The device ignores DI Sample Clock when a measurement acquisition is not in progress During a measurement acquisition you can cause your DAQ device to ignore DI Sample Clock using the DI Pause Trigger signal The DI timing engine on your device internally generates DI Sample Clock unless you select an external source DI Start Trigger starts the timing engine and either software or hardware can National Instruments 6 5 Chapter 6 Digital I O stop it once a finite acquisition completes When using the DI timing engine you can also specify a configurable delay from DI Start Trigger to the first DI Sample Clock pulse By default this delay is set to two ticks of the DI Sample Clock Timebase signal Figure 6 3 DI Sample Clock and DI Start Trigger DI Sample Clock Timebase DI Start Trigger DI Sample Clock Delay From Start Trigger DI Sample Clock Timebase Signal You can route any of the following signals to be the DI Sample Clock Timebase di SampleClockTimebase signal e 100 MHz Timebase default e 20
277. se devices acquires an odd number of total samples the last sample acquired cannot be transferred To ensure this condition never occurs NI DAQmx adds a background channel for finite acquisitions that have both an odd number of channels and an odd number of samples per channel The background channel is also added when performing any reference triggered finite acquisition Data from the background channel is only visible when reading in RAW mode For maximum bus bandwidth and onboard FIFO efficiency use an even number of samples per channel or an even number of channels for finite acquisitions so the background channel is not added e Continuous acquisition refers to the acquisition of an unspecified number of samples Instead of acquiring a set number of data samples and stopping a continuous acquisition continues until you stop the operation Continuous acquisition is also referred to as double buffered or circular buffered acquisition If data cannot be transferred across the bus fast enough the FIFO becomes full New acquisitions overwrite data in the FIFO before it can be transferred to host memory which causes the device to generate an error With continuous operations if the user program does not read data out of the PC buffer fast enough National Instruments 4 39 Chapter 4 Analog Input to keep up with the data transfer the buffer could reach an overflow condition causing an error to be generated Hardware timed
278. seeseeseeneeteeeeees 7 23 Hardware Timed Single Point Position Measurement cc ceeescesereeeeneeees 7 24 Two Signal Edge Separation Measurement ccccsccsessessescenseescesceseeseeseteeceeenees 7 24 Single Two Signal Edge Separation Measurement 7 24 Implicit Buffered Two Signal Edge Separation Measurement eee 7 25 Sample Clocked Buffered Two Signal Separation Measurement 7 25 Hardware Timed Single Point Two Signal Separation Measurement 7 26 Counter Output Applications ss 7 26 Simple Pulse Generation 7 27 Single Pulse Generation 7 27 Single Pulse Generation with Start Trigger 7 27 Puls Train G neration sr ade ein nement 7 28 Finite Pulse Train Generation 7 28 Retriggerable Pulse or Pulse Train Generation 7 29 Continuous Pulse Train Generation ss 7 30 Buffered Pulse Train Generation 7 31 Finite Implicit Buffered Pulse Train Generation 7 31 Continuous Buffered Implicit Pulse Train Generation 7 32 Finite Buffered Sample Clocked Pulse Train Generation 0ceeeeeeeeeees 7 32 Continuous Buffered Sample Clocked Pulse Train Generation c ee 7 33 Frequency Generation 7 34 Using the Frequency Generator ss 7 34 Frequency Divisiona rs nn rene nee net A sean te 7 35 Pulse G n ration for ETS ssscavsteccscviciacs anae AA E Ei 7 35 Counter Timing Signals ses 7 36 Countenn Source Signal cits sien desta ee
279. signals under the following three conditions The common mode voltage V m which is equivalent to subtracting AI lt 0 x gt GND from AI lt 0 x gt must be less than 10 V This V m is a constant for all range selections The signal voltage V which is equivalent to subtracting AI lt 0 x gt from AI lt 0 x gt must be less than or equal to the range selection of the given channel If V is greater than the range selected the signal clips and information are lost The total working voltage of the positive input which is equivalent to V m V5 or subtracting AI lt 0 x gt GND from AI lt 0 x gt must be less than 11 V If any of these conditions are exceeded the input voltage is clamped until the fault condition is removed Analog Input Data Acquisition Methods When performing analog input measurements you either can perform software timed or hardware timed acquisitions 4 38 Software timed acquisitions With a software timed acquisition software controls the rate of the acquisition Software sends a separate command to the hardware to initiate each ADC conversion In NI DAQmx software timed acquisitions are referred to as having on demand timing Software timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data Hardware timed acquisitions With hardware timed acquisitions a digital hardware signal AI Sample Clock control
280. ss 6 5 DI Sample Clock Timebase Signal 6 6 DI Start Trigger Signal ec passsteate o a E tle bd pesados ees iene 6 7 Retriggerable Di at hse eile tee ie Sed i eee ere 6 7 Using Digital Source deiron ena iae a E a A TR 6 7 Using ai Analog Soure sinsnnnennier hisnen hernie aee 6 8 Routing DI Start Trigger to an Output Terminal 6 8 Di Reference Trigger Signal Nave nine nie Met 6 8 Using a Digital Source 6 9 Using an Analog Source sis 6 9 Routing DI Reference Trigger Signal to an Output Terminal 0 ee 6 9 DI Pause Trigger Signal Using a Digital Source Using an Analog Source Routing DI Pause Trigger Signal to an Output Terminal 0 ccc eeeeeneeeeees 6 11 viii ni ccom X Series User Manual Digital Output Data Generation Methods 6 11 Software Timed Generations 6 11 Hardware Timed Generations 0 cccsccesessescseseesecseeeceeceeseceesevscsaeseaecevseasseesceaeaeeas 6 11 Digital Output Triggering eeseeeee Digital Waveform Generation DO Sample Clock Signal Using an Internal Source soenen n E E a iE 6 13 Using an External Source isiscseiscsseestescaccescaciesneetecseeeiies Ghd acesecoetcones 6 14 Routing DO Sample Clock to an Output Terminal 0 eee eeeeseeeeeeeeeeeeees 6 14 Other Timing Requirement 0 ccceseeccsscesceseecescenceesecseeseeseeeceseeeteeseeeeeeees 6 14 DO Sample Clock Timebase Signal 6 15 DO Start Trigger Signal 6 15
281. still used for the source frequency fk but the divide down means that the measurement time is the period of the divided down signal or N fx where N is the divide down Sample clocked For sample clocked frequency measurements a known timebase is counted for the source frequency fk The measurement time is the period of the sample clock fs Table 7 2 Frequency Measurement Methods Two Counter High Variable Sample Clocked One Counter Frequency Large Range fk Known timebase Known 1 Known timebase timebase gating period Measurement 1 1 gating period N time fs fx fx Max fx fx fk fx x x x x y x frequency f PAPE f fk fx f Nx fk fx error S Max error fx fx fk Se o ZTA fk fx fx Nx fk fx fkx 1 S Note Accuracy equations do not take clock stability into account Refer to your device specifications for clock stability National Instruments 7 17 Chapter 7 Counters Which Method Is Best This depends on the frequency to be measured the rate at which you want to monitor the frequency and the accuracy you desire Take for example measuring a 50 kHz signal Assuming that the measurement times for the sample clocked with averaging and two counter frequency measurements are configured the same Table 7 3 summarizes the results Table 7 3 50 kHz Frequency Measurement Methods Two Counter Sample O
282. t drivers and so on Registered users also receive access to the NI Discussion Forums at ni com forums NI Applications Engineers make sure every question submitted online receives an answer Software Support Service Membership the Standard Service Program SSP is a renewable one year subscription included with almost every NI software product including NI Developer Suite This program entitles members to direct access to NI Applications Engineers through phone and email for one to one technical support as well as exclusive access to online training modules at ni com self paced training NI also offers flexible extended contract options that guarantee your SSP benefits are available without interruption for as long as you need them Visit ni com ssp for more information Declaration of Conformity DoC A DoC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electromagnetic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification or contact your local office at ni com contact You can also visit the Worldwide Offices section of ni com niglobal to access the branch office websites which provide up to date contact information support phone numbers email addresses and current events D 2 ni com Index Symbols 5 V power source
283. t or as an analog trigger input APFI lt 0 1 gt are referenced to AI GND when they are used as analog trigger inputs APFI lt 0 1 gt are referenced to AO GND when they are used as AO external offset or reference inputs These functions are not available on all devices Refer to the specifications for your device 5 V D GND Output 5 V Power Source These terminals provide a fused 5 V power source Refer to the 5 V Power Source section for more information National Instruments 3 3 Chapter 3 Connector and LED Information Table 3 1 I O Connector Signals Continued Signal Name Reference Direction Description PFI lt 0 7 gt P1 lt 0 7 gt PFI lt 8 15 gt P2 lt 0 7 gt D GND Input or Output Programmable Function Interface or Digital I O Channels 0 to 7 and Channels 8 to 15 Each of these terminals can be individually configured as a PFI terminal or a digital I O terminal As an input each PFI terminal can be used to supply an external source for AI AO DI and DO timing signals or counter timer inputs As a PFI output you can route many different internal AI AO DI or DO timing signals to each PFI terminal You can also route the counter timer outputs to each PFI terminal As a Port or Port 2 digital I O signal you can individually configure each signal as an input or output NC No connect Do not connect signals to these terminals
284. t 0 15 gt Al Reference Trigger ai ReferenceTrigger AIl Start Trigger ai StartTrigger e PXI STAR e PXIe_ DSTAR lt A B gt e Analog Comparison Event Change Detection Event In addition a counter s Internal Output Gate or Source can be routed to a different counter s Aux A counter s own gate can also be routed to its Aux input Some of these options may not be available in some driver software Counter n A Counter n B and Counter n Z Signals Counter n B can control the direction of counting in edge counting applications Use the A B and Z inputs to each counter when measuring quadrature encoders or measuring two pulse encoders Routing Signals to A B and Z Counter Inputs Each counter has independent input selectors for each of the A B and Z inputs Any of the following signals can be routed to each input e RTSI lt 0 7 gt e PFI lt 0 15 gt PXI STAR e PXIe DSTAR lt A B gt e Analog Comparison Event Routing Counter n Z Signal to an Output Terminal You can route Counter n Z out to any RTSI lt 0 7 gt terminal Counter n Up_Down Signal Counter n Up_Down is another name for the Counter n B signal National Instruments 7 39 Chapter 7 Counters Counter n HW Arm Signal The Counter n HW Arm signal enables a counter to begin an input or output function To begin any counter input or output function you must first enable or arm the counter In some applications such as
285. t A B gt Change Detection Event AI Start Trigger ai StartTrigger e AO Start Trigger ao StartTrigger e DO Start Trigger do StartTrigger The source can also be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the measurement acquisition begins on the rising edge or falling edge of DI Start Trigger Using an Analog Source When you use an analog trigger source the acquisition begins on the first rising or falling edge of the Analog Comparison Event signal Routing DI Start Trigger to an Output Terminal You can route DI Start Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The output is an active high pulse All PFI terminals are configured as inputs by default The device also uses DI Start Trigger to initiate pretriggered DAQ operations In most pretriggered applications a software trigger generates DI Start Trigger Refer to the DI Reference Trigger Signal section for a complete description of the use of DI Start Trigger and DI Reference Trigger in a pretriggered DAQ operation DI Reference Trigger Signal Use the DI Reference Trigger di ReferenceTrigger signal to stop a measurement acquisition To use a reference trigger specify a buffer of finite size and a number of pretrigger samples samples that occur before the reference trigger The number of pos
286. t Trigger ao StartTrigger e AO Sample Clock ao SampleClock e AO Sample Clock Timebase ao SampleClockTimebase e AO Pause Trigger ao PauseTrigger e Counter input signals for all counters Source Gate Aux HW_Arm A B or Z e DI Sample Clock di SampleClock e DI Start Trigger di StartTrigger DI Pause Trigger di PauseTrigger DI Reference Trigger di ReferenceTrigger e DO Sample Clock do SampleClock e DO Sample Clock Timebase do SampleClockTimebase Most functions allow you to configure the polarity of RTSI inputs and whether the input is edge or level sensitive RTSI Filters You can enable a programmable debouncing filter on each PFI RTSI or PXI STAR signal Refer to the PFI Filters section of Chapter 8 PFI for more information PXI and PXI Express Clock and Trigger Signals PXI and PXI Express clock and trigger signals are only available on PXI Express devices PXle_CLK100 PXIe CLK100 is a common low skew 100 MHz reference clock for synchronization of multiple modules in a PXI Express measurement or control system The PXIe backplane is responsible for generating PXIe CLK100 independently to each peripheral slot in a PXI Express chassis For more information refer to the PXI Express Specification at www pxisa org PXle_SYNC100 PXIe SYNC100 is a common low skew 10 MHz reference clock with a 10 duty cycle for synchronization of multiple modules in a PXI Express measurement or control system This
287. t is when AO Pause Trigger is active no samples occur AO Pause Trigger does not stop a sample that is in progress The pause does not take effect until the beginning of the next sample When you generate analog output signals the generation pauses as soon as the pause trigger is asserted Ifthe source of your sample clock is the onboard clock the generation resumes as soon as the pause trigger is deasserted as shown in Figure 5 5 Figure 5 5 AO Pause Trigger with the Onboard Clock Source Pause Trigger l Sample Clock If you are using any signal other than the onboard clock as the source of your sample clock the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received as shown in Figure 5 6 Figure 5 6 AO PauseTrigger with Other Signal Source Pause Trigger Sample Clock National Instruments 5 7 Chapter 5 Analog Output Using a Digital Source To use AO Pause Trigger specify a source and a polarity The source can be one ofthe following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e PXIe_DSTAR lt A B gt e Counter n Internal Output e Counter n Gate e Al Pause Trigger ai PauseTrigger DI Pause Trigger di PauseTrigger e DO Pause Trigger do PauseTrigger The source can also be one of several other internal signals on your DAQ device Refer to Device Rou
288. t liable for any damage resulting from such signal connections AI ground reference setting is sometimes referred to as AI terminal configuration National Instruments 4 5 Chapter 4 Analog Input Configuring Al Ground Reference Settings in Software You can program channels on an MIO X Series device to acquire with different ground references To enable multimode scanning in LabVIEW use NI DAQmx Create Virtual Channel vi of the NI DAQmx API You must use a new VI for each channel or group of channels configured in a different input mode In Figure 4 3 channel 0 is configured in differential mode and channel 1 is configured in RSE mode Figure 4 3 Enabling Multimode Scanning in LabVIEW Differential y DAG mx fs Devi ait 7 To configure the input mode of your voltage measurement using the DAQ Assistant use the Terminal Configuration drop down list Refer to the DAQ Assistant Help for more information about the DAQ Assistant fg Dev 1 aio 7 To configure the input mode of your voltage measurement using the NI DAQmx C API set the terminalConfig property Refer to the M DAQmx C Reference Help for more information Multichannel Scanning Considerations MIO X Series devices can scan multiple channels at high rates and digitize the signals accurately However you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements In multichannel scanni
289. t number of AI Convert Clock pulses are received Figures 4 18 4 19 4 20 and 4 21 show timing sequences for a four channel acquisition using AI channels 0 1 2 and 3 and demonstrate proper and improper sequencing of AI Sample Clock and AI Convert Clock 4 28 ni com X Series User Manual Figure 4 18 Scan Overrun Condition AI Sample Clock Too Fast For Convert Clock Causes an Error Al Sample Clock Al Convert Clock 0123 A Convert Period Channel Measured Figure 4 19 Al Convert Clock Too Fast For Al Sample Clock Al Convert Clock Pulses Are Ignored Al Sample Clock Al Convert Clock Channel Measured 1 0128 0123 0123 a Sample 1 q Sample 2 q Sample 3 gt Figure 4 20 Al Sample Clock and Al Convert Clock Improperly Matched Leads to Aperiodic Sampling Al Sample Clock Al Convert Clock 0 1 2 3 0 Sample 3 Channel Measured 0 1 2 3 i Sample 1 Sample 2 P4 gt gt lt Figure 4 21 Al Sample Clock and Al Convert Clock Properly Matched NAN UU 0123 012 3 Sample 1 Sample 2 e gt q Al Sample Clock UU 0123 Sample 3 gt Al Convert Clock Channel Measured gt it National
290. tage Range 4 38 Analog Input Data Acquisition Methods 4 38 Analog Input Triggering ses 4 40 Connecting Analog Input Signals 4 41 Types of Signal Sources cccecceescesceseeseeseesecseceecaecacesceneeeseeeeeaceseeseeeeeeseeaees 4 41 Differential Connections for Ground Referenced Signal Sources 04 4 42 Differential Connections for Floating Signal Sources 4 43 Field Wiring Considerations 4 44 Minimizing Drift in Differential Mode 4 45 Analog Input Timing Signals 0 cc cccceceseeseesseseeeececeeceeceaesaeeaeeaecaecaecaecaeeaeeaeeneees 4 45 Aggregate versus Single Channel Sample Rates 4 47 Al Sample Clock Signal cose rincer inner 4 47 AI Sample Clock Timebase Signal 4 49 AI Hold Complete Event Signal 4 49 Al Start Trigger Signal 4 50 AI Reference Trigger Signal 4 51 AI Pause Trigger Signal us 4 53 Getting Started with AI Applications in Software 4 54 Chapter 5 Analog Output AO Reference Selection rennes t ner dit ess 5 2 Minimizing Glitches on the Output Signal 5 2 Analog Output Data Generation Methods 5 3 Software Timed Generations 5 3 Hardware Timed Generations 5 3 Analog Output Triggering ss 5 4 National Instruments vii Contents Connecting Analog Output Signals ss 5 5 Analog Output Timing Signals 200 0 cccecessesseescescescescesees
291. ter 1 Getting Started Ferrite Installation NI USB X Series To ensure the specified EMC performance for radiated RF emissions of the NI USB X Series device install the included snap on ferrite bead onto the power cable as shown in Figure 1 2 Ensure that the ferrite bead is as close to the end of the power cable as practical Install the snap on ferrite bead by opening the housing and looping the power cable once through the center of the ferrite Close the ferrite bead until the locking tabs engage securely You can order additional EMI suppression ferrites 10 2 mm length part number 781233 02 from NI Figure 1 2 Installing a Ferrite on an NI USB X Series Device 1 Power Cable 2 Ferrite 3 NI USB X Series Device 1 4 ni com X Series User Manual Mounting NI USB X Series Devices Excluding NI USB BNC X Series Devices You can use your NI USB X Series device on a desktop mount it to a wall or panel as described in the Panel Wall Mounting section or mount it to a standard DIN rail as described in the DIN Rail Mounting section Panel Wall Mounting Complete the following steps to mount your NI USB X Series device to a wall or panel using the USB X Series mounting kit part number 781514 01 not included in your USB X Series device kit Refer to Figure 1 3 1 Use three 8 32 flathead screws to attach the backpanel wall mount to the panel wall Tighten the screws with a 2 Phillips screwdriver to a torque of 1 1 N
292. ter Signals in the NI DAQmx Help or the LabVIEW Help A 6 ni com X Series User Manual NI 6321 6341 Device Specifications Refer to the NJ 6321 Specifications for more detailed information about the NI 6321 device Refer to the MI 6341 Specifications for more detailed information about the NI 6341 device NI 6321 6341 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information National Instruments A 7 Appendix A Device Specific Information NI 6323 6343 The following sections contain information about the NI PCIe 6323 NI PCle 6343 and NI USB 6343 devices NI 6323 6343 Pinouts Figure A 5 shows the pinout of the NI PCIe 6323 6343 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information Figure A 5 NI PCle 6323 6343 Pinout po N AI O AI 0 68 34 AI 8 Al 0 P0 30 1 35 D GND Al GND 67 33 Al 1 Al 1 P0 28 2 36 D GND Al 9 Al 1 66
293. th 1 1 Poor Good one counter High frequency with lor2 1 Good Poor two counters Large range of 2 1 Good Good frequencies with two counters Sample clocked 1 1 Good Good averaged For information about connecting counter signals refer to the Default Counter Timer Pinouts section Period Measurement In period measurements the counter measures a period on its Gate input signal after the counter is armed You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between the two active edges of the Gate signal You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Period measurements return the inverse results of frequency measurements Refer to the Frequency Measurement section for more information 7 20 ni com X Series User Manual Position Measurement You can use the counters to perform position measurements with quadrature encoders or two pulse encoders You can measure angular position with X1 X2 and X4 angular encoders Linear position can be measured with two pulse encoders You can choose to do either a single point on demand position measurement or a buffered
294. the signal as determined by the input ground reference setting and the input range The output of the NI PGIA then drives the analog trigger detection circuit By using the NI PGIA you can trigger on very small voltage changes in the input signal When the DAQ device is waiting for an analog trigger with a AI channel as the source the AI muxes should not route different AI channels to the NI PGIA If a different channel is routed to the NI PGIA the trigger condition on the desired channel could be missed The other channels could also generate false triggers This behavior places some restrictions on using AI channels as trigger sources When you use an analog start trigger the trigger channel must be the first channel in the channel list When you use an analog reference or pause trigger and the analog channel is the source of the trigger there can be only one channel in the channel list Analog Input Channels on Simultaneous MIO X Series Devices With Simultaneous MIO X Series devices every AI channel drives its own NI PGIA The NI PGIA amplifies the signal as determined by the input range The output of the NI PGIA then drives the analog trigger detection circuit By using the NI PGIA you can trigger on very small voltage changes in the input signal Since channels are not multiplexed there are no restrictions on the analog input channel list order or number of channels with reference and pause triggers However the analog input channe
295. ting Started with X Series USB Devices The following sections contain information about X Series USB device best practices and features USB Device Chassis Ground Note NI USB 636x Mass Termination Devices USB Mass Termination X Series devices have chassis ground connection through the I O connector NI USB 634X 635x 636x Screw Terminal Devices For EMC compliance the chassis of the USB Screw Terminal X Series device must be connected to earth ground through the chassis ground The wire should be AWG 16 or larger solid copper wire with a maximum length of 1 5 m 5 ft Attach the wire to the earth ground of the facility s power system For more information about earth ground connections refer to the KnowledgeBase document Grounding for Test and Measurement Devices by going to ni com info and entering the Info Code emcground 1 2 ni com X Series User Manual You can attach and solder a wire to the chassis ground lug of the USB X Series device as shown in Figure 1 1 The wire should be as short as possible Figure 1 1 Grounding an NI Screw Terminal USB 634x 635x 636x Device through the Chassis Ground Lug NI USB 63xx BNC Devices You can attach a wire to a CHS GND screw terminal of any NI BNC USB 63xx device Use as short a wire as possible In addition the wires in the shielded cable that extend beyond the shield should be as short as possible National Instruments 1 3 Chap
296. ting in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the samples are paused when AO Pause Trigger is at a logic high or low level Using an Analog Source When you use an analog trigger source the samples are paused when the Analog Comparison Event signal is at a high level Refer to the Triggering with an Analog Source section of Chapter 11 Triggering for more information Routing AO Pause Trigger Signal to an Output Terminal You can route AO Pause Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal AO Sample Clock Signal Use the AO Sample Clock ao SampleClock signal to initiate AO samples Each sample updates the outputs of all of the DACs You can specify an internal or external source for AO Sample Clock You can also specify whether the DAC update begins on the rising edge or falling edge of AO Sample Clock Using an Internal Source One of the following internal signals can drive AO Sample Clock e AO Sample Clock Timebase divided down e Counter n Internal Output Change Detection Event e Counter n Sample Clock 5 8 ni com X Series User Manual AI Convert Clock ai ConvertClock AI Sample Clock ai SampleClock e DI Sample Clock di SampleClock e DO Sample Clock do SampleClock A programmable internal counter divides down the AO Sample Clock Timebase signal Several other internal signals can be routed to AO Sample Clock
297. tions instead As shown in the bottom rightmost cell of Table 4 3 there can be a potential difference between AI GND and the ground of the sensor In RSE mode this ground loop causes measurement errors Using Differential Connections for Ground Referenced Signal Sources Figure 4 10 shows how to connect a ground referenced signal source to the MIO X Series device configured in differential mode Figure 4 10 Differential Connections for Ground Referenced Signal Sources L Al O D Co Ground o So Referenced Instrumentation Signal Ve i Amplifier Source 8 so Al b Measured Voltage Common So E Mode Noise and ven A ers oo Ground Potential D S77 i 6 Input Multiplexers ol 7 Al SENSE 1 0 Connector ie MIO X Series Device Configured in Differential Mode DE Note NI USB 6341 6343 6361 6363 BNC Devices To measure a ground referenced signal source on X Series USB BNC devices move the switch under the BNC connector to the GS position With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as Ven in the figure AI and AI must both remain within 11 V of AI GND National Instruments 4 19 Chapter 4 Analog Input Using Non Referenced Single Ended NRSE Connections for Ground Reference
298. to high transition on an input that has a custom filter set to N 5 Figure 8 3 Filter Example RTSI PFI or PXI_STAR Terminal Filter Clock J U Filtered Input ES Lin 1 2 Lu Le H 5 ET LUE 3 4 LI II Filtered input goes high when terminal is sampled high on five consecutive filter clocks Enabling filters introduces jitter on the input signal The maximum jitter is one period of the timebase When a RTSI input is routed directly to PFI the X Series device does not use the filtered version of the input signal National Instruments 8 5 Chapter 8 PFI I O Protection Each DIO and PFI signal is protected against overvoltage undervoltage and overcurrent conditions as well as ESD events However you should avoid these fault conditions by following these guidelines e Ifyou configure a PFI or DIO line as an output do not connect it to any external signal source ground or power supply e Ifyou configure a PFI or DIO line as an output understand the current requirements of the load connected to these signals Do not exceed the specified current output limits of the DAQ device NI has several signal conditioning solutions for digital applications requiring high current drive e Ifyou configure a PFI or DIO line as an input do not drive the line with voltages outside of its normal operating range The PFI or DIO lines have a smaller operating range than t
299. trigger set to the default True Figure 7 31 Retriggerable Single Pulse Generation with Initial Delay on Retrigger Counter Load Values gee NO ee Derk Start den E source MULU U UUL OUT 5 3 5 3 Figure 7 32 shows the same pulse train with CO EnablelnitalDelayOnRetrigger set to the default False Figure 7 32 Retriggerable Single Pulse Generation with Initial Delay on Retrigger Set to False Counter Load Values 48210210 43210210 GATE Start Trigger source MULLIN OUT i 5 3 i a Note The minimum time between the trigger and the first active edge is two ticks of the source For information about connecting counter signals refer to the Default Counter Timer Pinouts section Continuous Pulse Train Generation Continuous pulse train generation creates a train of pulses with programmable frequency and duty cycle The pulses appear on the Counter n Internal Output signal of the counter You can specify a delay from when the counter is armed to the beginning of the pulse train The delay is measured in terms of a number of active edges of the Source input You specify the high and low pulse widths of the output signal The pulse widths are also measured in terms of a number of active edges of the Source input You can also specify the active edge of the Source input rising or falling 7 30 ni com X Series User Manual
300. triggerable Pulse or Pulse Train Generation e Continuous Pulse Train Generation Finite Implicit Buffered Pulse Train Generation Continuous Buffered Implicit Pulse Train Generation e Finite Buffered Sample Clocked Pulse Train Generation Continuous Buffered Sample Clocked Pulse Train Generation Finite Pulse Train Generation Finite pulse train generation creates a train of pulses with programmable frequency and duty cycle for a predetermined number of pulses as shown in Figure 7 29 With X Series counters the primary counter generates the specified pulse train and the embedded counter counts the pulses generated by the primary counter When the embedded counter reaches the specified tick count it generates a trigger that stops the primary counter generation Figure 7 29 Finite Pulse Train Generation Four Ticks Initial Delay Four Pulses Counter Armed Source Enablex Ctrx 7 28 ni com X Series User Manual In Legacy Mode the counter operation requires two counters and does not use the embedded counter For example to generate four pulses on Counter 0 Counter 0 generates the pulse train which is gated by the paired second counter The paired counter Counter 1 generates a pulse of desired width Note Counter 0 is always paired with Counter 1 Counter 2 is always paired with Counter 3 The routing is done internally Figure 7 30 shows an example finite pu
301. ts as shown in Figure 7 19 Figure 7 19 X2 Encoding ChA ChB coe l eee 1 1 T 1 1 Counter Value 5X 6 X 7 X 8 X 9 oX8X7XeXs National Instruments 7 21 Chapter 7 Counters e X4 Encoding Similarly the counter increments or decrements on each edge of channels A and B for X4 encoding Whether the counter increments or decrements depends on which channel leads the other Each cycle results in four increments or decrements as shown in Figure 7 20 Figure 7 20 X4 Encoding ChA a L ChB r i Counter Value 5X 6X 7X8 X9 X10KX11X12X13 13X12X11X10X 9X8 X7X6X 5 Channel Z Behavior Some quadrature encoders have a third channel channel Z which is also referred to as the index channel A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle You can program the counter reload to occur in any one of the four phases in a quadrature cycle Channel Z behavior when it goes high and how long it stays high differs with quadrature encoder designs You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B You must then ensure that channel Z is high during at least a portion of the phase you specify for reload For instance in F
302. ttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of pretrigger samples Once the acquisition begins the DAQ device writes samples to the buffer After the DAQ device captures the specified number of pretrigger samples the DAQ device begins to look for the reference trigger condition If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples the DAQ device ignores the condition Ifthe buffer becomes full the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample This data can be accessed with some limitations before the DAQ device discards it Refer to the KnowledgeBase document Can a Pretriggered Acquisition be Continuous for more information To access this KnowledgeBase go to ni com info and enter the Info Code rdcanq 6 8 ni com X Series User Manual When the reference trigger occurs the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired Figure 6 5 shows the final buffer Figure 6 5 Reference Trigger Final Buffer Reference Trigger Pretrigger Samples Posttrigger Samples J y L T Complete Buffer Using a Digital Source To use DI Reference Trigger with a digital source specify a source and an edge The source can be any of the following signals e PFI lt 0 15
303. ugh rate to keep up with the generation the buffer underflows and causes an error Analog Output Triggering Analog output supports two different triggering actions e Start trigger e Pause trigger An analog or digital trigger can initiate these actions All X Series devices support digital triggering but some do not support analog triggering To find your device s triggering options refer to the specifications document for your device Refer to the 4O Start Trigger Signal and AO Pause Trigger Signal sections for more information about these triggering actions 5 4 ni com X Series User Manual Connecting Analog Output Signals AO lt 0 3 gt are the voltage output signals for analog output channels 0 1 2 and 3 AO GND is the ground reference for AO lt 0 3 gt Figure 5 2 shows how to make analog output connections to the device Figure 5 2 Analog Output Connections Analog Output Channels Analog Output Channels Aog Channel 2 a AO GND 2 V a V Load V OUT Load V OUT POT Channel 1 tho as Channel 3 Connector 0 Al 0 15 X Series Device Connector 1 Al 16 31 X Series Device Analog Output Timing Signals Figure 5 3 summarizes all of the timing options provided by the analog output timing engine Figure 5 3 Analog Output Timing Options 100 MHz Timebase DSTAR lt A
304. unts the number of edges on the Source input while the Gate input remains active On each trailing edge of the Gate signal the counter stores the count in the counter FIFO A DMA controller transfers the stored values to host memory 7 6 ni com X Series User Manual Figure 7 6 shows an example of an implicit buffered pulse width measurement Figure 7 6 Implicit Buffered Pulse Width Measurement Counter Value 0 wo SOURCE A A F Buffer Sample Clocked Buffered Pulse Width Measurement A Sample Clocked Buffered pulse width measurement is similar to single pulse width measurement but buffered pulse width measurement takes measurements over multiple pulses correlated to a sample clock The counter counts the number of edges on the Source input while the Gate input remains active On each sample clock edge the counter stores the count in the FIFO of the last pulse width to complete A DMA controller transfers the stored values to host memory Figure 7 7 shows an example of a sample clocked buffered pulse width measurement Figure 7 7 Sample Clocked Buffered Pulse Width Measurement Gate 1 i i Source I l 1 1 i i Sample Clock Buffer i 1 4 i i
305. urce To use AO Start Trigger specify a source and an edge The source can be one of the following signals A pulse initiated by host software e PFI lt 0 15 gt e RTSI lt 0 7 gt Al Start Trigger ai StartTrigger Al Reference Trigger ai ReferenceTrigger e PXI STAR e PXIe DSTAR lt A B gt e Counter n Internal Output Change Detection Event e DI Start Trigger di StartTrigger DI Reference Trigger di ReferenceTrigger e DO Start Trigger do StartTrigger The source can also be one of several internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information 5 6 ni com X Series User Manual You can also specify whether the waveform generation begins on the rising edge or falling edge of AO Start Trigger Using an Analog Source When you use an analog trigger source the waveform generation begins on the first rising edge of the Analog Comparison Event signal Refer to the Triggering with an Analog Source section of Chapter 11 Triggering for more information Routing AO Start Trigger Signal to an Output Terminal You can route AO Start Trigger out to any PFI lt 0 15 gt RTSI lt 0 7 gt or PXIe DSTARC terminal The output is an active high pulse PFI terminals are configured as inputs by default AO Pause Trigger Signal Use the AO Pause Trigger ao PauseTrigger signal to mask off samples in a DAQ sequence Tha
306. us among devices that allows you to do the following e Use a common clock or timebase to drive the timing engine on multiple devices e Share trigger signals between devices Many National Instruments DAQ motion vision and CAN devices support RTSI Ina PCI Express system the RTSI bus consists of the RTSI bus interface and a ribbon cable The bus can route timing and trigger signals between several functions on as many as five DAQ vision motion or CAN devices in the computer In a PXI Express system the RTSI bus is replaced by the PXI and PXI Express trigger signals on the PXI Express backplane This bus can route timing and trigger signals between several functions on as many as seven DAQ devices in the system USB devices do not support the RTSI bus 9 4 ni com X Series User Manual RTSI Connector Pinout NI PCle 632x 634x 635x 636x Devices Figure 9 2 shows the RTSI connector pinout and Table 9 1 describes the RTSI signals Figure 9 2 PCI Express X Series Device RTSI Pinout Terminal 33 Terminal 1 Table 9 1 RTSI Signals RTSI Bus Signal Terminal RTSI 7 34 RTSI 6 32 RTSI 5 30 RTSI 4 28 RTSI 3 26 RTSI 2 24 RTSI 1 22 RTSI 0 20 Not Connected Do not connect signals to these terminals 1 through 18 D GND 19 21 23 25 27 29 31 33 National Instruments 9 5 Chapter 9 Digital Routing and Clock Generation Using RTSI as Outputs
307. us changes You can also use the Change Detection Event signal to trigger DO or counter generations Digital Filtering You can enable a programmable debouncing filter on each digital line on Port 0 When the filters are enabled your device samples the input on each rising edge of a filter clock X Series devices divide down the onboard 100 MHz or 100 kHz clocks to generate the filter clock The following is an example of low to high transitions of the input signal High to low transitions work similarly Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on two consecutive edges and the signal remained stable in between the low to high transition is propagated to the rest of the circuit Table 6 1 Filters Pulse Width Pulse Width Guaranteed to Pass Guaranteed to Not Filter Setting Filter Clock Filter Pass Filter Short 12 5 MHz 160 ns 80 ns Medium 195 3125 kHz 10 24 us 5 12 us High 390 625 Hz 5 12 ms 2 56 ms None 6 20 ni com X Series User Manual The filter setting for each input can be configured independently On power up the filters are disabled Figure 6 12 shows an example of a low to high transition on an input Figure 6 12 Input Low to High Transition Digital Input PO x i 1 1 1 1 2 1 2 Filter Clock
308. ut operations you can use it in addition to the start and pause triggers For counter input operations you can use the arm start trigger to have start trigger like behavior The arm start trigger can be used for synchronizing multiple counter input and output tasks When using an arm start trigger the arm start trigger source is routed to the Counter n HW Arm signal Start Trigger For counter output operations a start trigger can be configured to begin a finite or continuous pulse generation Once a continuous generation has triggered the pulses continue to generate until you stop the operation in software For finite generations the specified number of pulses is generated and the generation stops unless you use the retriggerable attribute When you use this attribute subsequent start triggers cause the generation to restart When using a start trigger the start trigger source is routed to the Counter n Gate signal input of the counter Counter input operations can use the arm start trigger to have start trigger like behavior e Pause Trigger You can use pause triggers in edge counting and continuous pulse generation applications For edge counting acquisitions the counter stops counting edges while the external trigger signal is low and resumes when the signal goes high or vice versa For continuous pulse generations the counter stops generating pulses while the external trigger signal is low and resumes when the signal goes high or
309. utput signals the generation pauses as soon as the pause trigger is asserted If the source of your sample clock is the onboard clock the generation resumes as soon as the pause trigger is deasserted as shown in Figure 6 9 Figure 6 9 DO Pause Trigger with the Onboard Clock Source Pause Trigger Sample Clock If you are using any signal other than the onboard clock as the source of your sample clock the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received as shown in Figure 6 10 Figure 6 10 DO Pause Trigger with Other Signal Source Pause Trigger Sample Clock Using a Digital Source To use DO Pause Trigger specify a source and a polarity The source can be one of the following signals PFI lt 0 15 gt RTSI lt 0 7 gt PXI STAR PXIe DSTAR lt A B gt Counter n Internal Output Counter n Gate AI Pause Trigger ai PauseTrigger AO Pause Trigger ao PauseTrigger DI Pause Trigger di PauseTrigger The source can also be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW Help for more information You can also specify whether the samples are paused when DO Pause Trigger is at a logic high or low level National Instruments 6 17 Chapter 6 Digital 1 0 Using an Analog Source Whe
310. uts refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW Help NI 6351 6361 Device Specifications Refer to the NJ 6351 Specifications for more detailed information about the NI 6351 device Refer to the MI 6361 Specifications for more detailed information about the NI 6361 device NI 6351 6361 Accessory and Cabling Options NI offers a variety of accessories and cables to use with your DAQ device Refer to the Cables and Accessories section of Chapter 2 DAQ System Overview for more information A 18 ni com NI 6353 6363 X Series User Manual The following sections contain information about the NI PCIe 6353 NI USB 6353 Screw Terminal NI PCle PXIe 6363 and NI USB 6363 devices NI 6353 6363 Pinouts Figure A 13 shows the pinout of the NI PCIe 6353 and NI PCIe PXIe 6363 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the O Connector Signal Descriptions section of Chapter 3 Connector and LED Information NI PCle 6353 and NI PCle PXle 6363 Pinout Figure A 13 AI O AI 0 AI GND AI 9 AI 1 AI 2 AI 2 AI GND AI 11 AI 3 AI SENSE AI 12 AI 4 Al 5 Al 5 AI GND Al 14 AI 6 AI 7 AI 7 AI GND AO GND AO GND D GND P0 0 P0 5 D GND P0 2 P0 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND Al Al
311. vice versa When using a pause trigger the pause trigger source is routed to the Counter n Gate signal input of the counter Other Counter Features The following sections list the other counter features available on X Series devices Cascading Counters You can internally route the Counter n Internal Output and Counter n TC signals of each counter to the Gate inputs of the other counter By cascading two counters together you can effectively create a 64 bit counter By cascading counters you can also enable other applications For example to improve the accuracy of frequency measurements use reciprocal frequency measurement as described in the Large Range of Frequencies with Two Counters section National Instruments 7 45 Chapter 7 Counters Prescaling Prescaling allows the counter to count a signal that is faster than the maximum timebase of the counter as shown in Figure 7 39 X Series devices offer 8X and 2X prescaling on each counter prescaling can be disabled Each prescaler consists of a small simple counter that counts to eight or two and rolls over This counter can run faster than the larger counters which simply count the rollovers of this smaller counter Thus the prescaler acts as a frequency divider on the Source and puts out a frequency that is one eighth or one half of what it is accepting Figure 7 39 Prescaling
312. ware sets all PFI and DIO lines to high impedance inputs by default The DAQ device does not drive the signal high or low Each line has a weak pull down resistor connected to it as described in the specifications document for your device NI DAQmx supports programmable power up states for PFI and DIO lines Software can program any value at power up to the PO P1 or P2 lines The PFI and DIO lines can be set as e A high impedance input with a weak pull down resistor default e An output driving a 0 e An output driving a 1 Refer to the N DAQmx Help or the LabVIEW Help for more information about setting power up states in NI DAQmx or MAX 6 18 ni com X Series User Manual Y Note When using your X Series device to control an SCXI chassis DIO lines 0 1 2 and 4 are used as communication lines and must be left to power up in the default high impedance state to avoid potential damage to these signals DI Change Detection You can configure the DAQ device to detect changes on all 32 digital input lines PO P1 and P2 and all 16 PFI lines Figure 6 11 shows a block diagram of the DIO change detection circuitry Figure 6 11 DI Change Detection A Enable P0 0 Synch Re Enable Change Detection Event A Enable P2 7 Synch Re Enable You ca

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