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ad3700 manual - RTD Embedded Technologies, Inc.

1. 1 7 User Configurable 1 8 CHAPTER 2 BOARD INSTALLATION iO roce esent Teste iuo oer 2 1 Board Installation cin E 2 3 Extemal YO saer savas csvesetssstcosscceetinnsstavedeslosscevsdastsnstscadteteadonevddcbecteadnsed 2 3 Connecting the Analog Inputs 2 4 Connecting the Trigger In and Trigger Out Pins Cascading Boards eere 2 4 Connecting the Timer Counters and Digital usurucoscassoaseonssesnessenssnenssesnnnnnnnnnnnennennsonssnnsssnnnnennnnnennnnen essen 2 5 Running 3700DIAG Diagnostics Program n neesesesnssonssenoensnensnssssusnsssssssssnsnnssnsnnnnnnnnensesnonsssnanssnsonnnsnsnenssnsnnen 2 5 CHAPTER 3 HARDWARE DESCRIPTION 2ocsoessecnseonssnssnnsssnsnssnsessnssnensusunnsnsensensessusnnesunusnennee 3 1 A D Conversion OB AAA O 3 3 SA NN 3 3 AJD QT D 3 4 FIFO interface c 3 4 COMMITS 059 erii eere er icut RAI 3 4 DINGE fo rA EE 3 5 CHAPTER
2. 5 E 1 APPENDIX ATAA LIST OF ILLUSTRATIONS 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 2 1 2 3 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 5 1 Board Layout Showing Factory Configured Settings ccccssssssssssecssssssssssscsssscececessssesesecerecesssassesseees 1 4 Input Voltage Range Jumper P3 0 0 csscsssssscsssessssssesssesseessssssscsssessssssesssssonsessususavscacseeseensesecaeserecesseens 1 3 FIFO Full Half Full Flag Jumper s ssssscscsscsscoscsscssecsecsscsesssssssncescosssssutssesssussocoscecessessveneeaceuseecnecs 1 5 Analog Input Polarity Jumper PS s esscsesssssssescsssssssessssssesssssscssesessssessssesscsesesecsessucsesusersesseacsesseesseres 1 5 TC2 Source and OUT Select Jumper PG cris 1 5 Pacer Clock Source Select Jumper PT ccccssssssssssssssssssssscssssssssssscsssssssescsessscscseaceseseesessseusaseaeseseneacacaees 1 6 TC1 Counter 2 Sources Jumper P8 c scsssssssssssscsssscesessnsscesscsvsesesssscscscsesesssssscacsesssesesasscssassesscesscacenes 1 6 External Trigger External Gate Monitor Jumper cccccssssssssssssscssssssssscsesesessssesecacsesscersresescscessetess 1 6 Board Compatibility Select Jumper P10
3. 28 amp ol 2 la 5 o 9 5 5 gt 2 5 2 gt 2 jo 5 ojo aie 5 7 9 IT 1 D 8 5 2 o 4 a 2 3131 4141 IO m m rm rm 91919159 9 2 5 5 5 2 S SI 18 jes gt 0 2 a BA 0 Digital VO Read Write Transfers the 8 bit digital input and digital output data between the board and an external device A read transfers data from the external device through P2 onto the board where it can be placed in user memory a write transfers data from the board to an external device In7 In6 In5 In4 In3 In2 Int Ino 07 05 0 pi po Out7 046 Out5 Out4 Out3 Out2 Outi 4 3 1 Channel Conversion Mode Select Read Write Programs the analog input channel A D conversion mode and the channel select option The conversion modes and channel select options are detailed later in this chapter under Programming the AD3700 D6 and 07 are not used Reading this register shows you the current settings Channel 000 1 001 2 010 3 011 4 Channel Select Option 100 5 O Direct Channel 10126 1 Scan Channel 110 7 111 8 Conversion Mode 00 Single Convert Internal Trigger 01 Multi Convert Internal Gate 10 Single Convert Externa
4. ssssssssssssssssssssscsesccesseccensscssscecesscesesscucssesesesensavscseusaeasavens 1 6 Simultaneous Sample and Hold Normal Operation Jumper P11 cccssscsssssssssssssscsssessssesccesesesecevacees 1 7 Base Address Switch Sl 1 8 Gain Circuitry and Formulas for Calculating Gx 1 8 P2 Connector Pin Assignments a ae 2 3 Analog Input Connections ii dd 2 4 Cascading Two Boards for Simultaneous Sampling seen tette 2 5 AD3 100 Block DIARIA ead aii NE 3 3 8254 Programmable Interval Timer Circuits Block Diagram 3 5 Timing Diagram Single Convert Internal Trigger Direct Channel 4 13 Timing Diagram Single Convert Internal Trigger Scan Channel eerte 4 13 Timing Diagram Multi Convert Internal Gate Direct Channel eee tnn 4 13 Timing Diagram Multi Convert Internal Gate Scan Channel 4 13 Timing Diagram Single Convert External Trigger Direct Channel esee 4 14 Timing Diagram Single Convert External Trigger Scan Channel eerte 4 14 Timing Diagram Multi Convert External Gate Direct
5. AD3700 User s Manual 17227 1509001 AS9100 Certified Real Time Devices Inc Accessing the Analog World AD3700 User s Manual IED REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 USA Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr P O Box 906 State College PA 16804 USA Copyright O 1991 by Real Time Devices Inc All rights reserved Printed in U S A Rev C 9239 Table of Contents INTRODUGCTIQN c eroe e nore esce gan aero Ped uu ere canica sedssoacesocestocsedsarasvivess i 1 Analog to Digital Conversion e eese eese esee saosa i 3 8254 Timer SITZ CET D V aeaea iaat i 3 jouir i 3 What Comes With Y our Board 55 ii inicias i 4 Board ACCeSSOFIeS o ro Rega ete ore Pee aene eee EVEN SES ed LEE Teen RP E nets cin Fe oia VOV paa E eU NN en dee rv occiso i 4 Application Software and Drivers eee eee e eene esent tete tonne ntn nr ssania das eosto i 4 Hard Ware Accessories EERTE EE ARE ENE i 4 Using This Manual nein O 4 When You Need 14 CHAPTER 1 BOARD 5
6. 5 1 1 Factory Configured Switch and Jumper Settings ucenensnsssnsnsnsnensnsnensnsssnsnensnensssnsnsnsnnnnonnnnsnsnsnsasnsnensnesnnensanenenennn 1 3 Input Voltage Range Factory Setting 10V eeesessescssssssssnsnssssnessennensnnnnnnnennnnanensnssenunsnnnnsnsnnsnnnnnnnsnenennn 1 3 FIFO Full Half Full Flag Factory Setting FIFO 1 3 P5 Unipolar Bipolar Analog Input Factory Setting Bipolar eese eet tete 1 5 P6 Timer Counter 2 Source and OUT Select Factory Settings XTAL top 5 1 5 P7 Pacer Clock Source Select Factory Setting XTAL 1 6 P8 TC1 Counter 2 Sources Factory Settings 5V XTAL 1 6 P9 External Trigger External Gate Monitor Factory Setting External Trigger sess 1 6 P10 Board Compatibility Select Factory Setting Jumper on B eee 1 6 P11 Simultaneous Sample and Hold Select Factory Setting NOR eee eese 1 7 S1 Base Address Factory Setting 200 hex 512 decimal
7. fo 00000 50 5 po 53 000000000 00 00000000 ENS sin 919 din sin 80 00000000000 500505555055 0 5 a 8 o srr terre 74HCT74 0000000 74HCT74 74HCT74 noooooo 0000000 5 0000000 74HCT74 0000000 0000000 0000000 0000 E 74HCT153 500000000 6555000 Sale 0000 00000000 0000000000000 00000000000000 000000000000 74HCT153 50000000 0000 74HCT74 d 74HCTO8 A000000 00000000 0000000 0000000 0000000 0000000 noooooo 8 8 0000000 88 0000000 00000000 74HCT74 0000000 noooooo 0000000 0000000 88 CD 38v8 0000 1 4 P4 Fig 1 3 FIFO Full Half Full Flag Jumper P4 PS Unipolar Bipolar Analog Input Factory Setting Bipolar This header connector shown in Figure 1 4 configures the analog input for unipolar 0 to 10 volts or bipolar 5 or 10 volts operation You do not have to recalibrate the board when you change polarity P5 Fig 1 4 Analog Input Polarity Jumper P5 P6 Timer Counter 2 Source and OUT Select Factory Settings XTAL top 5 OUTO This header connector shown in Figure 1 5 configures timer counter 275 clock and gate sources and the selected TIMER output to the I O connector P2 42 The top two pairs of pins XTAL and se
8. s s sssssssssssssscscncsssesesesenesssesescecacassesescacacseseseaessssacensevavsussecesavsvsusnes 4 23 The DMA Controller AAA ease ud ei ubere 4 24 DMA Single Mask Register M 4 24 DMA Mode Register as in dle 4 25 Programming the DMA 4 25 Programming AD3700 for ueesernesssososnenenenennenenenosnenensnssosnenenennenesensesenenennensnnnnanennsnenennnnnensennnne 4 25 Monitoring for DMA Done cccsssssssssssssssscseccsesescsesssssvsssesssesseeseseseaesesessacecsessessssnsssssssecssavsesssseceseres 4 26 Common DMA Problems WTCC M 4 26 Bon nn e 4 26 Digital VO see een 4 28 Example Programs and Flow Diagrams cscscscsssssssessscscessssseseseessessesessenesessacseeacecsecaeseseceusssuesenseesusssscsssaoes 4 29 and Pascal Programs a ia BASIC Programs i DE 4 29 MMC aaa 4 30 Single Convert Flow Diagram Figure 4 12 e cacocococococonononononononanoncronononcncnononeron cr orononanca cu rnononecincorononccarorono 4 30 FIFO Flow Diagram Figure 4 13 4 31 DMA Flow Diagram Figure 4 14 cscsssssssssccsssssssse
9. 00 disabled 001 IRQ2 001 HF high FIFO half full 01 DRQ1 DMA Channel 1 010 1803 010 DMA done high transfer done 10 DRQ3 Channel3 611 IRQ4 011 TC2 OUT1 11 not defined 100 IRQ5 100 external trigger in external gate 101 IRQ6 101 EOC 110 IRQ7 110 TC1 counter out 111 interrupt disabled 111 TC2 timer IRQ BA 7 Clear Reset Board Write only A write to this location clears or resets the board data written is irrelevant This command resets all of the on board registers to 0 It also initializes the A D converter after power up BA 8 TC1 Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is part of the 32 bit on board pacer clock 1 counters 0 and 1 BA 9 TC1 Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is part of the 32 bit on board pacer clock TC1 counters 0 and 1 BA 10 1 Counter 2 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is user configurable for counter applications BA 11 TC1 Control Word Write Only Accesses the TC1 control register to directly control the three TC1 counters BCD Bin
10. CALIBRATION This chapter tells you how to calibrate the AD3700 using the 3700DIAG calibration program included in the example software package and the four trimpots TR1 through TR3 and TR5 on the board These trimpots calibrate the A D converter gain and offset This chapter tells you how to calibrate the A D converter gain and offset The offset and full scale performance of the board s A D converter is factory calibrated Any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjusts as necessary Using the 3700DIAG diagnostics program is a convenient way to monitor conversions while you calibrate the board Calibration is done with the board installed in your PC You can access the trimpots with the computer s cover removed Power up the computer and let the board circuitry stabilize for 15 minutes before you start calibrating Required Equipment The following equipment is required for calibration Precision Voltage Source 10 to 10 volts Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment While not required the 3700DIAG diagnostics program included with example software is helpful when performing calibrations Figure 5 1 shows the board layout The four trimpots used for calibration are located in the upper left area of the board A D Calibration Two procedures are used to calibrate the A D converter fo
11. This is easiest of all triggering modes It can be used in a wide variety of applications such as sample every time a key is pressed on the keyboard sample with each iteration of a loop or watch the system clock and sample every five seconds See the SOFTTRIG sample program in C and Pascal and the SINGLE sample program in BASIC Multi convert internal gate In this mode conversions are continuously performed at the pacer clock rate Sampling is initiated from software To use this mode you must program the pacer clock to run at the desired rate see the pacer clock discussion later in this chapter 1 This is the ideal mode for filling array with data Triggering is automatic so your program is spared the chore of monitoring the pacer clock to determine when to sample See the MULTI sample program in C and Pascal Single convert external trigger In this mode a single conversion is initiated by the rising edge of an external trigger pulse 1 Bas This mode is implemented when an external device is used to determine when to sample See the EXTTRIG sample program in C and Pascal 4 11 Multi convert external gate In this mode channels are sampled at the pacer clock rate The clock is gated on and off by the external trigger line When the external trigger line is held high sampling occurs at the pacer clock rate When the l
12. V V AND 223 OUT PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 2 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 23 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V VOR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 22 2 2 and then write the resulting value to the port In C this is programmed as inportb port address 5 171 outportb port_address To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 2 2 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing ope
13. roro 608 260 10110 624 270 10111 640 280 656 290 11001 672 11010 688 280 rion 106120 01100 sreco 11100 720 09 rre 736 2E0 11110 752 2F0 HERE package When you set the base address for your board record the value in the table inside back cover Figure 1 11 shows the DIP switch set for a base address of 300 decimal 768 switch 5 OPEN Fig 1 11 Base Address Switch S1 Gx User Configurable Gain Gx is provided so that you can easily configure a special gain setting for a specific application Note that when you use this feature and set up the board for a gain of other than 1 all of the input channels will operate only at your custom gain setting Gx is derived by adding resistors R2 and R3 trimpot TR4 and capacitor C51 all located in the upper right area of the board The resistors and trimpot combine to set the gain as shown in the formula in Fig 1 12 Capacitor 51 is provided so that you can add low pass filtering in the gain circuit If your input signal is a slowly changing one and you do not need to measure it at a higher rate you may want to add a capacitor at C51 in order to reduce the input frequency range and in turn reduce the noise on your input signal The formula for setting the frequency is given in the diagram below If you install a custom gain circuit a small trace on the bottom non component side of the board must be cut to activate the
14. A buffer straddles a page boundary if one part of the buffer resides in one page of memory while another part resides in the following page The DMA controller cannot properly write to such a buffer because the DMA controller can only write to one page without reprogramming When it reaches the end of the current page it does not start writing to the next page Instead it starts writing back at the first byte of the current page This can be disastrous if the beginning of the page does not correspond to your buffer More often than not this location is being used by the code portion of your program or the operating system and writing data to it almost always causes bizarre behavior and an eventual system crash You must check to see if your buffer straddles a page boundary and if it does take action to prevent the DMA controller from trying to write to the portion that continues on the next page You can reduce the size of the buffer or try to reposition the buffer However this can be difficult when using large static data structures and often the only solution is to use dynamically allocated memory Setting the DMA Page Register Oddly enough you do not inform the DMA controller directly of the page to be used Instead you put the page to be used into the DMA page register which is separate from the DMA controller as shown in the table below The location of this register depends on the DMA channel being used DMA Channel Location of Page
15. Divider 2 5 MHz 200 kHz 25 5 MHz 200 kHz After you determine the value of Divider 1 x Divider 2 you then divide the result by the least common denomi nator The least common denominator is the value that is loaded into Divider 1 and the result of the division the quotient is loaded into Divider 2 In our example above the least common denominator is 5 so Divider 1 equals 5 and Divider 2 equals 25 5 or 5 also The table with the diagram lists some common pacer clock frequencies and the counter settings using the on board 5 MHz clock source After you calculate the decimal value of each divider you can convert the result to a hex value if it is easier for you when loading the count into the 16 bit counter 4 16 To set up pacer clock on the AD3700 follow these steps 1 Select a clock source 5 MHz on board clock or and external clock source 2 Program TC1 Counter 0 for Mode 2 operation 3 Program TC1 Counter 1 for Mode 2 operation 4 Load Divider 1 LSB 5 Load Divider 1 MSB 6 Load Divider 2 LSB 7 Load Divider 2 MSB Depending on your conversion mode the counters start their countdown and the pacer clock starts running when a trigger occurs 5 MHz TC1 Counter 0 TC1 Counter 1 Fig 4 9 Pacer Clock Block Diagram Divider 1 Divider 2 Pacer Clock decimal hex decimal hex 4 17 Interrupts What Is Interrupt An interrupt is an event that
16. Figures 4 3 and 4 4 show you the Multi Convert Internal Gate mode timing Figures 4 5 and 4 6 show you the Single Convert External Trigger mode timing and Figures 4 7 and 4 8 show you the Multi Convert External Gate mode timing 4 12 Internal Trigger 1 FE 2 A D Trigger Sampled Channel 1 1 1 1 1 Tus Fig 4 1 Timing Diagram Single Convert Internal Trigger Direct Channel Internal Trigger TL TL TU TU TL _ AD Trigger 1 TL TL IL IL Sampled Channel 1 2 3 4 5 6 Fig 4 2 Timing Diagram Single Convert Internal Trigger Scan Channel Internal Trigger 1 Pacer Clock __ Tl TL T1 TL on o mo A D Trigger 1 1 1 1 1 1 1 Sampled Channel 1 1 1 1 1 1 1 1 Tr Fig 4 3 Timing Diagram Multi Convert Internal Gate Direct Channel Internal Trigger 1 Pacer Clock A D Trigger 1 1 1 1 1 1 1 Sampled Channel 1 2 3 4 5 6 7 8 ET Fig 4 4 Timing Diagram Multi Convert Internal Gate Scan Channel 4 13 Internal Trigger TU Tigerln ANTL TL OO A D Trigger 1l 1 1 Sampled Channel 1 1 1 1 1 dius Fig 4 5 Timing Diagram Single Convert External Trigger Direct Channel Internal Trigger TD Tagen I Vz AP _ NTL TLL A D Trigger FLI Te TLM Sampled Channel 1 2 3 4 1 2 3 4 Views Fig 4 6 Timing Diagram
17. MEE Clearing Board ii Clearing the FIFO Selecting a Chanel rere terri ese ves dele eost Goto e Conversion Modes and Channel Select Options cssscsssssssssessescscsesecesesssssesescesssscesessessscssecoususssscsvsones Conversion Modes Triggering sssssssssssscssesscscesesessssssssssseccsesesssessscesseseseeeesssacesceasseseceessessssesasssnees Channel Select Options Scans sccsscessssscesssscssssessscssesssssscsesscecesesesesesessseacsssesdscsescecvsvsvassessecseecseasees Timing Diagrams ici Starting an A D Conversion ccccecsssssecescsscccsscesssssseseceesesesessesssesecucesseaesusesessenesesssecessesesssuscnssceeesesesesesessuss Monitoring Conversion Status EF Flag or End of Convert Halting CONV A a Reading Me Converted DAA unse ice nen i Programming the Pacer Clock naar Interrpts RR What Is an 2 4 18 Interr pt Request Lines a a aoi 4 18 8259 Programmable Interrupt Controller sssssssssscecssssssseececscsssescecsseresesssssssssesenseseususcecacaesusueceees 4 18 Interrupt Mask Register IMR cccccsssssssssssscsssssscssssssesssscesestsssscasesesseescesescaeseseaeststsncouseveusesteasecs
18. Register Chip Select A low on this input enables the 82054 to respond to AD and WR signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations Write Control This input is low during CPU write operations Power 5V power supply connection FUNCTIONAL DESCRIPTION sired delay After the desired delay the 82 54 will interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated al od NC 15 1 11 15 25 EE General Some of the other counter timer functions common The 82C54 15 a programmable interval timer counter to microcomputers which can be implemented with designed for use with Intel microcomputer systems the 82 54 are general purpose multi timing element that can be treated as an array of 1 ports in the system e Real time clock software e Even counter e Digital one shot The 82054 solves one of the most common prob Programmable rate generator lems in any microcomputer system the generation e Square wave generator of accurate time delays under software control In Binary rate multiplier stead of setting up timing loops in software the pro Complex waveform generator grammer configures the 82C54 to match his require Complex motor controller ments and programs one of the counters for the de intel 82 54 Block Diagram DATA BUS BUFFER This 3
19. Select any unused full size expansion slot and remove the slot bracket Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag Holding the board by its edges orient it so that its card edge bus connector lines up with the expansion slot connector in the bottom of the selected expansion slot After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the board or to the computer After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer Be sure to observe the keying when connecting your external cable to the 1 O connector External 1 Connections Figure 2 1 shows the AD3700 s P2 connector pinout Refer to this diagram as you make your I O connec tions AIN1 ANALOG GND AIN2 ANALOG GND AIN3 ANALOG GND ANALOG GND AINS ANALOG GND 1 6 ANALOG GND AIN7 ANALOG GND AIN8 ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND DIN DO
20. board The SSH setting adapts the triggering for optimal use on the SSH boards SSH 11 Fig 1 10 Simultaneous Sample and Hold Normal Operation Jumper 11 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal 1 and other peripherals When the AD3700 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the AD3700 has an easily accessible DIP switch S1 which lets you select any one of 32 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your System you can select a different base address simply by setting the switches to any value shown in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Note that switch 5 is the leftmost switch and switch 1 is the rightmost switch when looking at the component side of the board When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch Table 1 2 Base Address Switch Settings S1 Base Address Switch Setting Decimal Hex 54321 Decimal Hex 54321 512 200 19000 528 210 544 220 560 230 EIZE 576 240 10100 5927 50
21. can change your program so that a sample is taken each time an external trigger occurs Clear Board Clear FIFO Select Channel xe Change Channel Start Conversion Check FIFO Empty Flag EF 1 Read MSB Yes Read LSB Fig 4 12 Single Convert Flow Diagram Stop Program 4 30 FIFO Flow Diagram Figure 4 13 This flow diagram shows you how to run the AD3700 from the pacer clock and use the on board FIFO interface to store the converted data You program the clock rate and take samples until the FIFO is full FIFO full flag 0 The samples are then read from the FIFO and displayed A sample is taken each time the pacer clock generates a pulse By using the pacer clock the time interval between samples can be precisely set The total number of samples taken depends on the size of the FIFO on your board Each sample is sent to the FIFO in two 8 bit words the MSB and the LSB A 2K FIFO can hold 1024 samples a 4K FIFO can hold 2048 samples and an 8K FIFO can hold 4096 samples The samples are taken on the channel specified in the bottom three bits of the CHANNEL CONVERSION MODE SELECT register BA 1 By setting the channel select option bit in this register to Scan Channel the converter will incrementally scan through all eight channels and store the data Clear Board Program Pacer Clock Select Pacer Clock Operation Multiconvert internal Gate Select Channel Clea
22. causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your AD3700 board can interrupt the processor when a variety of conditions are met such as FIFO not empty timer countdown finished and others By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt
23. counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un Results Count and status latched for Counter O 82054 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written 68 WR 3 8 5 1 Countero o wiiteinto ountert 2011 Write into Counter 2 1 0 Write Control Word Lo ReadtromCountero 1 0
24. high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again EXTERNAL PAC
25. if you do not want to change other settings also programmed through BA 1 you must preserve them when you set the channel x fone Bar Conversion Modes and Channel Select Options The AD3700 provides several triggering conversion modes and scan channel select options Four conversion modes and two channel select options give you a variety of combinations of triggering and channel selection to meet just about any sampling requirement This section describes the modes and options and includes a series of timing diagrams at the end so that you can see how they are implemented The conversion mode and channel select option are set at port BA 1 Conversion Modes Triggering Internal vs external triggering With internal triggering also called software triggering conversions are initiated by writing a value to the START CONVERT port at BA 4 on the board With external triggering conversions are initiated by applying a high TTL signal to the external TRIGGER IN pin P2 39 Any TTL signal can be used as a trigger source In fact you can use the TIMER OUT P2 42 or COUNTER OUT P2 44 as a trigger source Single convert internal trigger In this mode a single specified channel is sampled whenever a value is written to the START CONVERT port BA 4 The active channel is the one specified in the CHANNEL CON VERSION MODE SELECT port
26. sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the AD3700 board functions A D Conversions The following paragraphs walk you through the programming steps for performing A D conversions Detailed information about the conversion modes and channel select options is presented in this section You can follow these steps on the flow diagrams at the end of this chapter and in our example programs included with the board In this discussion BA refers to the base address Clearing the Board It is good practice to start your program by resetting the AD3700 board You can do this by writing to the CLEAR BOARD port located at BA 7 The actual value you write to this port is irrelevant After writing to this port you should pause several milliseconds and then clear the FIFO to remove any data placed there by the reset process Clearing the FIFO To clear the FIFO write any value to the CLEAR FIFO port located at BA 3 Any data in the FIFO when this port is written to is lost Selecting a Channel To select a conversion channel or a starting channel for a scan of channels you must assign values to bits 0 through 2 in the CHANNEL CONVERSION MODE SELECT port at BA 1 The table below shows you how to determine the bit settings Note that
27. the board through the I O connector A first in first out FIFO interface helps your computer manage the high throughput rate of the A D converter by acting as an elastic storage bin for the converted data Even if the computer does not read the data as fast as conversions are performed conversions can continue until the FIFO is full The converted data can be transferred to PC memory in one of two ways by using the microprocessor or by using direct memory access DMA The mode of transfer and DMA channel are chosen through software The PC data bus is used to read and or transfer data one byte at a time to PC memory In the DMA transfer mode you can transfer a selected block of data in a single data dump or you can make continuous transfers directly to PC memory without going through the processor 8254 Timer Counters Two 8254 programmable interval timers TC1 and TC2 each contain three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters in TC1 are cascaded and used internally for the pacer clock The third is available for counting applications The three timer counters in TC2 are cascaded for timing applications Digital VO The AD3700 has eight input and eight output TTL CMOS compatible digital lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays The input lines have on board
28. the end of this chapter These programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming 42 Defining the VO The map for the AD3700 is shown in Table 4 1 below As shown the board occupies 16 consecutive I O port locations The base address designated as BA can be selected using DIP switch S1 located on the top edge at the rear of the board furthest from I O connector P2 as described in Chapter 1 Board Settings This switch can be accessed without removing the board from the computer The following sections describe the register contents of each address used in the I O map Table 4 1 AD3700 O Address Register Description Read Function Decimal Read 8 digital input lines Program 8 digital output lines 0 g amp D gt w 2 2 o o 2 lt ersion Mode Read A D channel 8 Program A D chamnel 8 Select conversion mode settings conversion mode 1 Read number of channels number of channels Select be active in scan cycle BA 2 Clear FIFO BA 3 Read FIFO data MSB 8 LSB 4 Read interrupt amp DMA Program interrupt source 8 IRQ DMA Select settings channel select DMA select BA 6 reserved reset board BA 7 Used for pacer clock Load count register BA 9 Available for external use Load count register BA 10 To Cle
29. 0 pF 1 and 0 8V for a logic 0 C includes jig capacitance 3 99 APPENDIX D CONFIGURING THE AD3700 FOR SIGNAL MATH Jumper and Switch Settings When running SIGNAL MATH you may have to change some of the AD3700 s on board jumpers from their current positions All jumpers must be set to the factory positions as described in Chapter 1 except for P3 and 5 which can be configured for any of the three possible input ranges S1 Base Address SIGNAL MATH assumes that the base address of your AD3700 is the factory setting of 300 hex 768 deci mal If you change this setting you must run the ADAINST program and reset the base address NOTE When using the ADAINST program you can enter the base address in decimal or hexadecimal notation When entering a hex value you must precede the number by a dollar sign for example 300 Running ADAINST After the jumpers and switch are set and the AD3700 board is installed in the computer you are ready to configure SIGNAL MATH so that it is compatible with your board s settings This is done by running the ADAINST driver installation program After running the program open AD3700 EXE from the Open a File menu You will see a screen similar to the screen shown in Figure D 1 below The factory default settings are shown in the illustration Your settings may or may not match the default settings depending on whether you have made changes to these de
30. 0000 m 00000000 A 000000000n BETA ue 5 8 o 0000000000 0 0060000 00000000 0006000600 1 o un no en so ain 9099098 z o o ame BN BENE MICA ne do 2 INE BEREIT 2 1 5 2 oo o o o o lo 00000000 ojo 28 gt 0 le 9 le sl le 9 le 9 le a le o Are Biu lo ol 2 lo 9 oj jo o 5 o 2 o w 9 8000000000 o zo jo 330 o 9 oslo ollo 015 o o jo 65 o o 2 olzlo BERE 0 5 0 o ol lo 9 0 o 2 5 0 of jo _ 0 0 o 5 9518 9 on 0 o 0 des o BD D a 9 oflo jo 8 o o jo o le of le lo o o 5 Jo 90 0 9 9 Ogio Ojo ol lo o o 3 jo o o 9 o olglo 8 oslo 6555900 Ow 5 O Aet 5 Soe a olflo ojo 9 06 955 29009 78 9 EDAD O p eem CI C sco noo 8 MAA A 0 o 0 E CASCO CO CO 0 0 on 5 4 Table 5 2 A D Converter Bit Weights Bipolar Twos Co
31. 01 1111 0011 0011 5 5 Bipolar Calibration Bipolar Range Adjustments 5 to 5 Volts Two adjustments are made to calibrate the A D converter for the bipolar range of 5 to 5 volts One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR2 is used to make the offset adjustment and trimpot TR1 is used for gain adjustment Before making these adjustments make sure that the jumper on P3 is set for 10V and the jumper on PS is set for Use analog input channel 1 and set it for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 4 99878 volts start a conversion and read the resulting data Adjust trimpot TR2 until it flickers between the values listed in the table below Next set the voltage to 4 99634 volts and repeat the procedure this time adjusting TR1 until the data flickers between the values in the table Data Values for Calibrating Bipolar 10 Range 5 to 5 volts Offset TR2 Converter Gain TR1 Input Voltage 4 99878V Input Voltage 4 99634V 1000 0000 0000 0111 1111 1110 A D Converted Data 1000 0000 0001 0111 1111 1111 Bipolar Range Adjustments 10 to 10 Volts To adjust the bipolar 20 volt range 10 to 10 volts change the jumper on P3 so that it is installed across the 20V pins Leave the PS jumper at Then set the input voltage to 5 0000 volts and adjust until th
32. 1 Read Counters L0 0 1 1 ReadfromCounter2 10 o 1 3 t No Operation 3 State Lo 1 1 I x x no Operation 3 State Figure 14 Read Write Operations Summary If an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 15844 Mode Definitions 10 188 3 The following are defined for use in describing the operation of the 82C54 CLK PULSE a rising edge then a falling edge in that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put pe COUNTER LOADING the transfer of a count from the CR to the CE refer to 9 5 the Functional Descrip tion CW 10 15843 1882 MODE 0 INTERRUPT ON TERMINAL COUNT JUUUUVUVUVV Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will RR remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a 18181581 Loy eye E E new Mode 0 Control Word is written into the Coun bid ter 231244 8 NOTE GATE 1 enables counting GATE 0 disables The Following Conventions Apply To All Mode Timing counting GATE has no effect on OUT Diagrams 1 Counters are programmed for binary no
33. 1 enables counting GATE 0 disables counting GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also 14 158 3 1515151814131 1415134131 231244 10 A GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 82054 Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count o
34. 10 volts depending on your binary range For values of 2047 or less you simply convert the result The key digital codes and their input voltage values are given for each range in the following three tables A D Bipolar Code Table 35V twos complement Input Voltage Output Code 44 998 volts MSB 0111 1111 1111LSB 2 500 volts 0100 0000 0000 O volts 0000 0000 0000 00244 volts 1111 1111 1111 5 000 volts 1000 0000 0000 1 LSB 2 44 millivolts 4 15 10V twos complement Input Voltage 49 995 volts MSB 0111 1111 1111 LSB 5 000 volts 00488 volts 10 000 volts 0 to 10V straight binary Input Voltage 9 99756 volts 5 00000 volts Programming the Pacer Clock Two 16 bit timer counters in the 8254 Timer Counter TC1 are cascaded to form the on board pacer clock shown in Figure 4 9 When you want to use the pacer clock for continuous A D conversions you must program the clock rate To find the value you must load into the clock to produce the desired rate you first have to calculate the value of Divider 1 TC1 Counter 0 and Divider 2 TC1 Counter 1 shown in the diagram The formulas for making this calculation are as follows Pacer clock frequency Clock Source Frequency Divider 1 x Divider 2 Divider 1 x Divider 2 Clock Source Frequency Pacer Clock Frequency To set the pacer clock frequency at 200 kHz using the on board 5 MHz clock source this equation becomes Divider 1 x
35. 13 Figure 20 Mode 5 Low Or Going Low Signal Status Modes 1 Initiates counting 2 Resets output after next clock 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high 1 Disables counting Initiates 2 Sets output counting immediately Initiates counting NOTE O is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts Enables counting high Disables Enables counting counting Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK in Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Modes 1 2 3 and 5 the GATE input is rising edge sensitive in these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE i
36. 4 BOARD OPERATION AND PROGRAMMING 4 1 Defining the YO 4 3 BA 0 Digital Read Write 4 3 1 Channel Conversion Mode Select Read Write s ssscsscsscsessssssssscsssssssceesseasesesresssseescessecessecseeess 4 4 BA 2 Scan Channel Range Select Read Write ccc cssssssssesecsscesesserscecersesescsssccseeessaceacensesceceeesessecssseses 4 4 BA 3 Read Status Clear FIFO Read Write cscccsssecssesssesscsseesssenssssessassessssscaseesseceseasassacaseascnceecorseses 4 4 4 Read FIFO Data Start Conversion Read Write 4 5 BA 5 Clear DMA Done Write Only BA 6 IRQ DMA Select Read Write ccccscsscsscsscscsscecsecceccoecserseesesessossseseecesccessnsensvacesccesenesnecescecensscuses 7 Clear Reset Board Write only cccsesssssssssssssssssssssssssssssssesescscscssssssesscssscossceseccsseccecsseseacsenseres 8 TC1 Counter 0 Read Write ueneesnessssesssssnen
37. Channel eene 4 14 Timing Diagram Multi Convert External Gate Scan 8 Channels eene 4 14 Pacer Clock Block ia as 4 17 8254 Programmable Interval Timer Circuits Block Diagram lt lt 4 27 Digital Input Pull p 4 28 Single Convert Flow Diagram nee ee 4 30 FIFO Flow m 4 31 DMA Flo we DATA A A Eee 4 32 SCAN Flow Diagram FM 4 33 Interrupts Flow Diagram did 4 34 Board Layout Showing Calibration Trimpots sssssssscssccsessssesssesssssssssseesessssessscssessvseseescecsesesscaseceee 5 4 INTRODUCTION The AD3700 DataMaster board turns your IBM PC or compatible computer into a high speed high performance data acquisition and control system Installed within a single expansion slot in the computer the AD3700 features Eight single ended analog input channels 12 bit 5 microsecond analog to digital converter with 200 kHz throughput 5 10 or 0 to 10 volt input range Resistor configurable input gain Four conversion modes and programmable channel scan option On board FIFO interface and DMA transfer Trigger in and trigger out for external triggering or cascading boards Eight digital input and eight
38. Counter 0 Counter 1 Counter 2 Counter 2 Counter 1 Counter 0 Counter 0 Counter 1 Counter 2 000032 a struction sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counter s pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format Counter is programmed to read write two byte counts the following precaution applies A program must not transter control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count Control Word Control Word Control Word LSB of count MSB of count LSB of count MSB of count LSB of count MSB of count Counter 2 Counter 1 Counter 0 Counter 2 Counter 2 Counter 1 Counter 1 Counter 0 Counter 0 000033 gt 200220029 Control Word Control Word LSB of count Control Word LSB of count MSB of count LSB of count MSB of count MSB of count Counter 1 Counter 0 Counter 1 Counter 2 Counter 0 Counter 1 Counter 2 Counter O Counter 2 2020003 0000 gt In al four examples all counters are programmed to read write two byte coun
39. D converter accurately digitizes dynamic input voltages in 5 microseconds for a maximum throughput rate of 200 kHz The AD678 contains a sample and hold amplifier a 12 bit A D converter a 5 volt reference a clock and a digital interface to provide a complete A D conversion function on a single chip Its low power CMOS logic combined with a high precision low noise design give you accurate results Conversions are controlled through software internally triggered or by an external trigger brought onto the board through the connector An on board pacer clock can be used to control the conversion rate Conversion modes and channel select options are described in Chapter 4 Board Operation and Programming FIFO Interface A first in first out FIFO interface helps your computer manage the high throughput rate of the A D converter by providing an elastic storage bin for the converted data Even if the computer does not read the data as fast as conversions are performed conversions will continue until a FIFO full flag or half full flag depending on the setting of the jumper at P4 is sent to stop the converter The size of the FIFO was specified as 2K 4K or 8K when you placed your board order The FIFO does not need to be addressed when you are writing to or reading from it internal addressing makes sure that the data is properly stored and retrieved All data accumulated in the FIFO is stored intact until the PC is able to complete the da
40. ER CLOCK PACER CLOCK 5 MHz XTAL 5 VOLTS 1 CLK 1 1 COUNTER GATE l 1 _ EXTERNAL CLOCK i voita _ 9 VOLTS Lasse sweet 1 PEE EXTERNAL GATE M a gt COUNTER OUT TIMER COUNTER 2 1 1 Den 5 MHz XTAL i GATE I 1 beg 1 5 VOLTS 1 1 1 TIMER OUT 1 io of 1 1 l 1 COUNTER LoLa 2 5 MHz XTAL Fig 4 10 8254 Programmable interval Timer Circuits Block Diagram Digital VO The eight digital input and eight digital output lines can be used to transfer data between the computer and external devices The digital input lines have pull up resistors as shown in Figure 4 11 so that they will be pulled high when input source is disconnected This is ideal to support switching applications The digital input data can be read at I O port BA 0 and transferred into PC memory To output data the desired value is written to I O port BA 0 and sent out to the external device connected to the digital output pins on external I O connector P2 Fig 4 11 Digital Input Pull up Resistors 4 28 Example Programs and Flow Diagrams Included with the AD3700 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C Pascal and BASIC Also included is an eas
41. R O VARPTR BUFFER 4 22 Once you ve determined the segment and offset multiply segment by 16 and add offset to give you the linear address Make sure you store this result in a long integer or DWORD or the results will be meaningless The page number is the quotient of the division of the linear address by 65536 and the offset into the page is the remainder of that division Below are some programming examples for Pascal C and BASIC In Pascal Segment SEG Buffer Offset OFS Buffer Linear Address Segment 16 Offset Page LinearAddress DIV 65536 get segment of buffer get offset of buffer calculate a linear address determine page corresponding to this linear address PageOffset LinearAddress MOD 65536 determine offset into the page In C segment FP SEG amp Buffer get segment of buffer offset FP OFS amp Buffer get offset of buffer linear address segment 16 offset calculate a linear address page linear address 65536 determine page corresponding to this linear address page offset linear address 65536 determine offset into the page In BASIC S VARSEG BUFFER O VARPTR BUFFER LA 5 16 0 PAGE INT LA 65536 POFF LA PAGE 65536 Beware There is one big catch when using page based addresses The DMA controller cannot write properly to a buffer that straddles a page boundary
42. Register 2120 82 190 4 23 The DMA Controller The DMA controller is a complex chip that occupies the first 16 bytes of the PC s I O port space A complete discussion on how it operates is beyond the scope of this manual only relevant information is included here The DMA controller is programmed by writing to the DMA registers in your PC The table below lists these registers Note that when you write 16 bit values to any of these registers such as to the Count registers you must write the LSB first followed by the MSB If you are using DMA channel 1 write your page offset and count to ports 02H and 03H if you are using channel 3 write your page offset and count to ports 06H and 07H The page offset is simply the offset that you calculated for your buffer see discussion above Count indicates the number of bytes that you want the DMA controller to transfer Remember that each digitized sample from the AD3700 consists of 2 bytes so the count that you write to the DMA controller should be equal to the number of samples x 2 1 The single mask register and mode register are described below The clear byte pointer sets an internal flip flop on the DMA controller that keeps track of whether the LSB or MSB will be sent next to registers that accept both LSB and MSB Ordinarily you never need to write to this port but itis a good habit to do so before programming the DMA controller Writing any value to this port cle
43. S product The 82054 is available in 24 pin and 28 pin plastic leaded chip carrier PLCC packages COUNTER 0 TE 1 DATA sus GATE 0 BUFFER CLK GATE 1 2 3 5 e Wooo 1 OUTO GATED GND GATE1CLK1 231244 3 PLASTIC LEADED CHIP CARRIER M CLK 2 WORD REGISTER S a ouT 2 231244 1 Figure 1 82C54 Block Diagram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82054 Pinout September 1989 3 83 Order Number 231244 005 82054 Table 1 Pin Description Pin Number Bel inc RR connected to system data bus 9 10 1 Glock0 ClockinputofCountero to 12 Outputo QutputofCountero nim 8 O Gate 0 Gate input of Counter 0 0 Ground Power supply connection 17 18 1 WR NC Out 1 Output of Counter 1 19 Gate 2 Gate input of Counter 2 20 Out 2 Output of Counter 2 2 Clock 2 Clock input of Counter 2 12 20 19 23 22 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus Ay A Selects 0 0 Counter 0 0 1 1 0 1 1 Counter 1 Counter 2 Control Word
44. Single Convert External Trigger Scan Channel Internal Trigger Trigger A L Lion Pacer Clock lt lt A D Trigger SUUUUUL LL LIL Sampled Channel 1 1 1 1 1 1 1 1 1 1 1 Fig 4 7 Timing Diagram Multi Convert External Gate Direct Channel Internal Trigger e Clock A a L TUUL AD Trigger __ Sampled Channel 1 2 3 4 5 6 7 8 1 2 3 Fig 4 8 Timing Diagram Multi Convert External Gate Scan 8 Channels 4 14 Starting A D Conversion Whether you are using internal triggers external triggers single convert or multi convert you must start the conversion process by writing to the START CONVERT port at BA 4 The value you write is irrelevant For single conversion scan options you must write to this port to initiate every conversion In the multi conversion modes you need to write to this port only once to start the conversion cycle Monitoring Conversion Status EF Flag or End of Convert The A D conversion status can be monitored through the FIFO empty EF flag or through the end of convert EOC bit in the STATUS port at BA 3 Typically you will want to monitor the EF flag for a transition from low to high This tells you that a conversion is complete and data has been placed in the FIFO The EOC line is available for monitoring conversion status in special applications Halting Conversions In the single convert modes a si
45. T EXT GATE 5 VOLTS DIGITAL GND 1 APPENDIX C COMPONENT DATA SHEETS Intel 82 54 Programmable Interval Timer Data Sheet Reprint 82 54 CHMOS PROGRAMMABLE INTERVAL Compatible with all intel and most Three independent 16 bit counters other microprocessors m Low Power CHMOS m High Speed Zero Wait State 1 10 mA 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 m Completely TTL Compatible m Handies Inputs from DC to 8 MHz 10 MHz for 82C54 2 a ET oo Modes Available in EXPRESS ice Standard Temperature Range m Status Read Back Command Extended Temperature Range Available in 24 Pin DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS lll technology which provides low power consumption with performance equal to or greater than the equivalent HMO
46. URPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE F 3 3700 Board User Selected Settings
47. UT7 6 DOUT6 DINS DOUTS DIN4 DOUT4 DIN3 DOUT3 DIN2 DOUT2 DIN DOUT1 DINO DOUTO TRIGGER IN DIGITAL GND CLK TIMER OUT TRIGGER OUT COUNTER EXT CLK EXT GATE 412 VOLTS 5 VOLTS 12 VOLTS DIGITAL GND Fig 2 1 P2 I O Connector Pin Assignments 2 3 Connecting the Analog Inputs Connect the high side of the analog input to one of the analog input channels AIN1 through AINS and connect the low side to the selected channel s dedicated ANALOG GND Figure 2 2 shows how these connections are made NOTE It is good practice to connect all unused channels to ground as shown with channel 8 in the following diagrams Failure to do so may affect the accuracy of your results 3700 VO CONNECTOR 2 Fig 2 2 Analog Input Connections Connecting the Trigger In and Trigger Out Pins Cascading Boards The AD3700 board has an external trigger input P2 39 and output P2 43 so that conversions can be started based on external events or so that two or more boards can be cascaded and run synchronously in a master slave configuration By cascading two or more boards as shown in Figure 2 3 they can be triggered to start an A D conversion at the same time sampling uncertainty is less than 50 nanoseconds When you cascade boards be sure to set each board for a different base address see Chapter 1 or system contention will result NOTE The only delay you must take into account when casca
48. VO T 4 extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C Voc 5V 10 GND 0V Ta 40 C to 85 for Extended Temperature Symbol Conditions Input Low Voltage en o Input High Voltage Output Low Voltage 04 V lu 25mA VoH Output High Voltage 3 0 V lon 2 5 Vcc 0 4 100 pA Input Load Current 20 pA Vin Voc to ov Output Float Leakage Current 10 pA Vour Vocto0 oV loc Vcc Supply Current mA 8MHz 82054 IccsB Vcc Supply Current Standby Vcc Supply Current Standby NN Input Capacitance Capacitance eee Output Capacitance ae A C CHARACTERISTICS Ta 0 C to 70 C Voc 5V 110 GND 0V Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE Parameter 0000 Un Address Stable Before RD CS Stable Before RD 1 o CC All Inputs Data Bus Vcc All Outputs Floating pA CLKFreq DC CS All Other Inputs Pins Outputs Open fe 1 MHz Unmeasured pins returned to GND 5 10 20 d tar tsr TRA al tan ROPweWwdn wwo 9 tao 120 85 tap DataDefayfromaddress 220 188 ms to Data Floating 5 56 tw 1 Comman
49. X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR 4 19 Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR 15 to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called ag
50. ain before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port 20 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at 1 O port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pasca
51. an generate interrupts The IMR is programmed through port 21H as nos nas wen For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOI Command After an interrupt service routine is completed the 8259 interrupt controller must be notified This is done by writing the value 20H to I O port 20H 4 18 What Exactly Happens When Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the AD3700 the interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popp
52. andard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem 1 BOARD SETTINGS The AD3700 board has jumper and switch settings you can change if necessary for your application The board is factory configured with the most often used settings The factory settings are listed and shown on a diagram in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer Also note that by installing two resistors and a trimpot on the board you can define the user configurable gain Gx to be what ever value your application may require A pad for installing a capacitor C51 is also included in the gain circuitry for creating a low pass filter The procedure for customizing Gx is included at the end of this chapter 1 1 Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switches on the AD3700 board Figure 1 1 on the next page shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of S1 the base address switch to avoid address con
53. ars the flip flop DMA Single Mask Register The DMA single mask register is used to enable or disable DMA on a specified DMA channel You should mask disable DMA on the DMA channel you will be using while programming the DMA controller After the DMA controller has been programmed and the AD3700 has been programmed to sample data you can enable DMA by clearing the mask bit for the DMA channel you are using You should manually disable DMA by setting the mask bit before exiting your program or if for some reason sampling is halted before the DMA controller has transferred all the data it was programmed to transfer If you leave DMA enabled and it has not transferred all the data it was programmed to transfer it will resume transfers the next time data appears in the AD3700 FIFO This can spell disaster if your program has ended and the buffer has been reallocated to another application Port Channel Select Mask Bit 00 Channel 0 0 01 Channel 1 1 mask 10 Channel 2 11 Channel 3 4 24 DMA Mode Register The DMA mode register is used to set parameters for the DMA channel you will be using The read write bits are self explanatory the read mode cannot be used with the AD3700 Autoinitialization allows the DMA controller to automatically start over once it has transferred the requested number of bytes Decrement means the DMA controller should decrement its offset counter aft
54. ary 0 binary 1 BCD Counter Select 00 Counter 0 Counter Mode Select 01 Counter 1 000 Mode 0 event count 10 Counter2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 Read load LSB then MSB 101 Mode 5 hardware triggered strobe BA 12 TC2 Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is used for timer operations BA 13 TC2 Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is used for timer operations BA 14 TC2 Counter 2 Read Write read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is used for timer operations BA 15 TC2 Control Word Write Only Accesses the TC2 control register to directly control the three TC2 counters BCD Binary O binary 1 BCD Counter Select 00 Counter 0 Counter Mode Select 01 Counter 1 000 Mode 0 event count 10 Counter 2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 l
55. atching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 read load MSB only 100 Mode 4 software triggered strobe 11 Read load LSB then MSB 101 Mode 5 hardware triggered strobe 4 7 Programming AD3700 This section gives you some general information about programming and the AD3700 board and then walks you through the major AD3700 programming functions These descriptions will help you as you use the example programs included with the board and the programming flow diagrams at the end of this chapter All of the program descriptions in this section use decimal values unless otherwise specified The AD3700 is programmed by writing to and reading from the correct I O port locations on the board These I O ports were defined in the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to I O ports using some popular programming languages wm Data inportb Address Data Port Address Port Address Data Assembly mov dx Address in al dx In addition to being able to read write the I O ports on the AD3700 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an exa
56. by software OUT strobes low N 1 CLK pulses after the new count of N is written CW 18 LSB 3 0 010 0 FF FF FF SEITE CW 18 1583 1515151313131 1416518 18 158 3 158 2 0 1010 0 pala a Te 231244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again 3 94 After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CW A 158 3 1051 1 1583 0 FF 0 FF 158 3 158 5 peapa pae paspa 231244
57. ccrssssscscersceseesssssceceesssssessssssscesssssssssceessssevseeesseses 4 32 Scan Flow Diagram Figure 4 15 scsscssssssscssscscssscesscesssceseccssesssesesesssesecseacecesessesseesesseaseceacesesesensssesenes 4 32 Interrupts Flow Diagram Figure 4 16 s ssssssssssscsssssesssesccecessscnesssssesesenenesesesesesesseseesuscecssescasarsesessssuses 4 32 CHAPTER 5 CALIBRATION cc andas 5 1 Required Equipment iii 5 3 eun PC 5 3 Unipolar Calibration m ECCE 5 5 Bipolar Calibration e 5 6 Bipolar Range Adjustments 5 to 5 Volts eccsssscecccssscssssssscnsesesssensssseneesscacasscsesescnsecsesssesasesssecesssveves 5 6 Bipolar Range Adjustments 10 to 10 Volts ccssscssssesscsssscecessrssssssssccsecesestesescsensessseessesnssaesecassncaseses 5 6 APPENDIX A AD3700 SPECIFICATIONS A 1 APPENDIX B P2 CONNECTOR PIN ASSIGNMENTS B 1 APPENDIX C COMPONENT DATA 5 5 C 1 APPENDIX D CONFIGURING THE AD3700 FOR SIGNAL MATH D 1 APPENDIX E CONFIGURING THE AD3700 FOR
58. ched count is held until it is read or the counter is repro grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the 82 54 count but the first are ignored i e the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits D5 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system D Dg Ds Dg D2 D Do NULL OUTPUT COUNT RW1 wo eco D 1 Out Pin is 1 0 Out Pin is 0 Dg 1 Null count 0 Count available for reading D5 Dg Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but unti
59. cimal or hexadecimal value hex values must be preceded by a dollar sign for example 300 Refer to your board s manual if you need help in determining the correct value to enter EOC TT End of Convert Interrupt In this block enter the IRQ channel number to be used by the end of convert interrupt see BA 6 description in Chapter 4 End of Convert Timer Counter Interrupt Channel Interrupt Channel Base Address Software Interrupt Address AD DMA D A DMA Channel Channel Select Select External Gain External Gain 8 Loss ae amp Loss Bt Bipolar A D Unipolar 3 Bipolar Select D A Unipolar Bipolar Select Fig D 1 ADAINST EXE Screen D 3 Timer IT Timer Counter Interrupt This block is not used on the AD3700 and should be left blank LabTech SW IT LABTECH NOTEBOOK Software Interrupt This sets the software interrupt address where LABTECH NOTEBOOKS labLINX driver is installed The factory setting is 60 This setting can be ignored when running SIGNAL MATH A D Parameters Six A D board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of channels are fixed by the program for your board If you are using DMA transfer you must enter the channel number you are using in the DMA channel block Valid channels numbers are 1 and 3 The next two blocks gain and loss are provided so that you can make adjustments for ex
60. circuit Figure 1 12 shows how the Gx circuitry is config ured To calculate Gx Gx TR4 R2 R3 1 To calculate frequency f 1 21C51 R2 TR4 Fig 1 12 Gain Circuitry and Formulas for Calculating Gx and f 1 8 2 BOARD INSTALLATION The AD3700 board is easy to install in your IBM PC XT AT or compatible computer It can be placed in any full sized slot This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 3700DIAG board diagnostics program included on your example software disk to verify that your board is working Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To install the board 1 2 Turn OFF the power to your computer Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this
61. controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ1 is used by the key board IRQ3 by 2 IRQ4 by COMI and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the AD3700 board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you will need to know how to read and set the 8259 s interrupt mask register IMR and how to send the end of interrupt EOI command to 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for IRQ1 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and c
62. d Recovery Time 200 NOTE 1 AC timings measured at 2 0V Vo 0 8V 3 96 intel 82054 CHARACTERISTICS Continued WRITE CYCLE Min Min taw Address Stable Before WR 0 BENE tsw CSStableBetoreWR 0 BA tow two Max Es NE rem ww o tow Data Setup Time Before 120 two DataHold Time After WR T tay Command Recovery Time 200 CLOCK AND GATE T BELLE m m m m m m Xu 5 EJ m m m m m m _ m m mw m 608 e uw Gate with High 50 Ta ClockRise Time tF tg Gate Hold Time After CLK T 50 2 Top to tw tw tw teL Top tw CLK Delay for Loading 4 Gate Delay for Sampling 4 two OUT Delay from Mode Write tc CLK Set Up for Count Latch NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82 54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwH tpw may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampled 100 tested Ta 25 C 6 If CLK present at Two min then Count e
63. digital output lines Four user configurable 16 bit timer counters which can be used to generate interrupts or as an event counter a frequency counter a programmable one shot a rate generator or for other special functions BASIC Turbo Pascal and Turbo C source code diagnostics program The following paragraphs briefly describe the major functions of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Analog to Digital Conversion The analog to digital A D circuitry receives up to eight single ended analog inputs and converts these inputs into 12 bit digital data words which can then be read and or transferred to PC memory The input voltage range is jumper selectable for bipolar ranges of 5 to 5 volts or 10 to 10 volts or a unipolar range of 0 to 10 volts It is not necessary to recalibrate after changing the input range or polarity The board is factory set for 5 to 5 volts Overvoltage protection to 35 volts is provided at the inputs A user configurable gain Gx is provided so that you can customize a gain for a specific application Gx is set as described in Chapter 1 A D conversions are performed in 5 microseconds with a maximum throughput rate of 200 kHz Conversions are controlled through software by an on board pacer clock or by an external trigger brought onto
64. ding boards is the time it takes for the trigger signal to propagate through the boards Because the sampling uncertainty is less than 50 nanoseconds this should not affect boards operating at lower conversion rates However it may cause timing problems when you operate at higher speeds If you want to make sure of precise simultaneous triggering at higher speeds then connect the trigger signal to the trigger input of each board or use RTD s SSH4 or 55 8 four or eight channel simultaneous sample and hold board If you apply an external trigger to the board s trigger in pin note that the board is triggered on the positive edge of the pulse The pulse duration should be at least 50 nanoseconds 2 4 3700 1 0 CONNECTOR 2 41 MASTER TRIGGER OUT BOARD 2 SLAVE TRIGGER IN Fig 2 3 Cascading Two Boards for Simultaneous Sampling Connecting the Timer Counters and Digital YO For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is connected to any DIGITAL GND Running the 3700DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 3700DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your curr
65. e output matches the data in the table below Data Value for Calibrating Bipolar 20 Volt Range 10 to 10 voits TR3 Input Voltage 5 0000V A D Converted Data 0100 0000 0000 5 6 A 1 APPENDIX A AD3700 SPECIFICATIONS 2 AD3700 Characteristics Typical 25 C Interface IBM PC XT AT compatible Switch selectable base address I O mapped Jumper selectable interrupts Software selectable DMA channel Analog Input 8 single ended inputs Input impedance each gt 10 megohms FANG OS viii inci 5 10 or 0 to 10 volts Overvoltage 35 NE ii 5 usec max AID A A AD678 E Successive approximation Resolution 12 bits 2 44 mV 4 88 mV MET E HEEL 1 LSB typ Conversion Speed anten iiie erret return 5 usec typ Mnt m 200 kHz Pacer Clock Range using on board clock eres 14 minutes to 5 usec 2K 4 or 8K IDT7209 etie A AA 2048 bytes 1024 samples pn EET 4096 bytes 2048 samples 1017205 E 8192 bytes 4096 samples Digital Number of lines cono rn un en nee 8 input 8 output Timer Counters e
66. e three functional blocks are identical in opera tion so only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82C54 WORD LATCH REGISTER E BEER connor LOGIC JE 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter and OL are 8 bit latches OL stands for Output Latch the subscripts M and stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how t
67. eaeense 4 18 End of Interrupt EOI Command ssscescsscsesscresssssscsscscsscesessecescaseceessssssseneessasesssssscensseacsssesensessnes 4 18 What Exactly Happens When an Interrupt 4 19 Using Interrupts in Your 4 19 Writing an Interrupt Service Routine ISR eee e eee testes etna tata tne sa tha ta tnb 4 19 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector eee 4 20 Restoring the Startup IMR and Interrupt Vector ssscsssssssssssccssecesseoeseceesesessssssssssessssususscetsnsssserscsves 4 21 Common Interrupt Mistakes ssscsssssssssceccsssessssserssessnsseseceessensseseesacarsesuseaessesseseseeceassssteceesesenensess 4 21 Data Transfers Using ASS II nee Io eU qune 4 21 Choosing a Channel 4 21 Allocating DMA Buffer ieri erae io eiae tenen ae 4 22 Calculating the Page and Offset of a Buffer ssssssssssssssssesececnscssecesesesessesssssessensscseseseseseeneacecassesees 4 22 Setting DMA Page Register
68. ed from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your AD3700 program disk for a better under standing of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must write an end of interrupt EOI command to the 8259 interrupt controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the fla
69. enenonnnennnnnenensnenessnensnenenenanenenennnnnnnnnssnsnenenenennnensnnnnnensnnnene BA 9 TCI Counter 1 Read Write cscscsssssssssssssssssssscsecesssssscecucsssssessscsssssscsessssescsescacaescneececssecsencecacess __ 10 TC1 Counter 2 Read Write cccscssssccssscssssssesssssssesossoecececseccsssssscsssascacsssacescessscoreccessessscenessones BA 11 TCI Control Word Write Only eese eee esee notatae emen enses tado sns sess Poss soos BA 12 TC2 Counter 0 Read Write ssssssssssssscsssssscsescssssssesessesesescscesensecensessscecesssvasassssuscsessavevscsessoes BA 13 TC2 Counter 1 Read Write cccccsssssscsssssssssssssssssesssssssssessesessssessscccesscessaceecacseceassesassccarserecsaseas BA 14 TC2 Counter 2 15 TC2 Control Word Write Only csssssessscsscssssssssesssssscesssssevscssssssvscneuccscssvesscesescasecosescasssonsesacees Programming AD3700 u 2s0s0002e2e020enensasensnononnenenennesenenensenenenenensesenonensenensnenensnennnsensnenaustesnsnanssnnnnenssausenenenn Clearing and Setting Bits in Port c sssssssssssssscssccscscsoesnsesssersesssstscscscsesesscsesesesenseassesceesesessessseeeacanseusssssseses A D
70. ent base address setting does not contend with another device 3 HARDWARE DESCRIPTION This chapter describes the features of the AD3700 hardware The major circuits are the A D the timer counters and the digital lines The AD3700 board has three major circuits the A D the timer counters and the digital I O lines Figure 3 1 shows the block diagram of the board This chapter describes the hardware which makes up the major circuits 8 ANALOG INPUTS TO 5V 0 TO 10V 10V TO 10V B SE V TRIGGER OUT p KA TIMER OUT 1 0 CONNECTOR DIGITAL IN 5 VOLTS GROUND Fig 3 1 AD3700 Block Diagram A D Conversion Circuitry The AD3700 board performs analog to digital conversions on up to eight software selectable analog input channels The following paragraphs describe the A D circuitry Analog Inputs The input voltage range is jumper selectable for 5 to 5 volts 10 to 10 volts or O to 10 volts user configurable gain Gx lets you amplify lower level signals to more closely match the board s input ranges When 3 3 you increase gain the effective input range decreases by the input range divided by gain You can customize this gain setting by following the instructions at the end of Chapter 1 Overvoltage protection to 35 volts is provided at the inputs A D Converter The AD678 12 bit successive approximation A
71. er each transfer the default is increment We recommend that you use either the demand or single transfer mode when transferring data The demand mode transfers data to the PC on demand The single transfer mode forces the DMA controller to relinquish every other cycle so that the processor can take care of other tasks We recommend that you do not use the block mode since it can tie up the processor and interfere with system operation 87 es A Meee Channel Select Port OBH Transfer Mode Autoinitlalization 00 demand 00 0 01 single transfer 0 disable 01 Channel 1 10 block 1 enable 10 Channel 2 11 cascade 11 Channel 3 Offset Counter 0 increment Read Wi rite 1 decrement 01 write 10 read not used with AD3700 Programming the DMA Controller To program the DMA controller follow these steps 1 Clear the byte pointer flip flop 2 Disable DMA on the channel you are using 3 Write the DMA mode register to choose the DMA parameters 4 Write the LSB of the page offset of your buffer 5 Write the MSB of the page offset of your buffer 6 Write the LSB of the number of bytes to transfer 7 Write the MSB of the number of bytes to transfer 8 Enable DMA on the channel you are using Programming the AD3700 for DMA Once you have set up the DMA controller you must program the AD3700 for DMA The followi
72. ese eee eere eene ener nennen sesssesesseeiens CMOS 82054 Optional NMOS 8254 Six 16 bit down counters 3 per IC Binary or BCD counting Programmable operating modes 6 Interrupt on terminal count programmable one shot rate generator square wave rate generator software triggered strobe hardware triggered strobe Counter input cessere eere External clock 8 MHz max or on board 5 MHz clock Counter outputs Available externally used as PC interrupts Counter gate External gate or always enabled Miscellaneous Inputs Outputs PC bus sourced 5 volts 12 volts Ground Current Requirements AB volts zuerst deve gie pre ea 80 mA aA cH 36 mA 512 34 mA Connector 50 pin right angle shrouded box header Size 3 875 H x 8 7 W 99mm x 221mm APPENDIX P2 CONNECTOR ASSIGNMENTS B 1 AIN1 AIN2 AIN3 AIN4 AIN5 AING AIN7 AIN8 ANALOG GND ANALOG GND ANALOG GND DIN7 DIN6 DINS DIN4 DIN3 DIN2 DIN1 DINO TRIGGER IN XT PACER CLK TRIGGER OUT EXT CLK 12 VOLTS 12 VOLTS eS UE 6969 6969 SIE 6969 QO 6969 OO Qu UE ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND ANALOG GND DOUT7 DOUT6 DOUTS DOUT4 DOUT3 DOUT2 DOUT1 DOUTO DIGITAL GND TIMER OUT COUNTER OU
73. f N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT goes low and the Counter is reloaded wit
74. gs CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function
75. gt o Fig 1 2 Input Voltage Range Jumper P4 FIFO Full Half Full Flag Factory Setting FIFO Full This header connector located above the FIFO at the top of the board is used to halt A D conversions when the FIFO is full FF or half full HF The advantage of setting the FIFO to stop conversions when it is half full is the assurance that there is room in the FIFO to store both bytes of the current conversion before shut off It is possible to lose the LSB of a conversion when the jumper is set to FIFO full since the FF flag signals that only one 8 bit slot remains in the FIFO to be filled and each 12 bit conversion requires two 8 bit slots one for the MSB and one for the LSB Figure 1 3 shows P4 with the jumper installed so that conversions are halted when the FIFO is full 1 3 noke Om 89 Go W3LSAS JOHLNOO 9 NOLLISINDOV V VQ 0991 ed emis sn 9 2 2 o E 21 TTA 00000000 0000000 00000000 0000000 00000000 00000000 un zin ein sin MX 0000000000 0000000 BEEEUUUT 828 0000000000 0000000 moral ET name BENNETT ee y poosocecos s INE
76. h the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts OUT will be high for N 1 2 counts and low for N 1 2 counts 158 4 A 12 CW 16 15845 GATE transition should occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con from the new count two byte count is writ ten the following happens 82 54 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered
77. he 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called CRm and CR for Count Register Both are normally referred to as one unit aad called just CR When a new count is written to the Counter the count is stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral 1 ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ap Ay connect to the Ap A1 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger s
78. he CHANNEL CONVERSION MODE SELECT register When the board increments through the number of channels programmed at BA 2 it automatically starts over at the first channel in the sequence By changing the value in the CHANNEL CONVERSION MODE SELECT register you can change your program so that a sample is taken each time an external trigger occurs Clear Board Clear FIFO Select Channel Scan Mode Number of Channels to Scan Start Conversion Check FIFO Empty Flag EF 1 Read MSB Read LSB Fig 4 15 Scan Flow Diagram Yes Continue Stop Program 4 33 Interrupts Flow Diagram Figure 4 16 Clear Board Save startup IMR value Save startup interrupt vector Set IRQ bit in IMR Vector new interrupt service routine ISR Program interrupt source Set IRQ amp interrupt source bits in IRQ DMA register Clear FIFO Clear IRQ bit in IMR Body of user program Set interrupt disabled bit in IRQ DMA register Restore startup interrupt vector Restore startup IMR value Fig 4 16 Interrupts Flow Diagram 4 34 This flow diagram shows you how to program an interrupt routine for your AD3700 The diagram parallels the interrupts discussion included in the chapter You can use this diagram in conjunction with the detailed text in this chapter to develop an interrupt program for your AD3700 Stop Program 5
79. ificant byte only Read Write most significant byte only 1 Read Write least significant byte first then most significant byte NOTE Don t care bits X should be O to insure compatibility with future Intel products Binary Counter 16 bits Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 82 54 Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format Specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the Ay Ag inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in Control Word LSB of count MSB of count Control Word LSB of count MSB of count Control Word LSB of count MSB of count Counter 0 Counter 0 Counter 0 Counter 1 Counter 1 Counter 1 Counter 2 Counter 2 Counter 2 200200 o Control Word Counter Word Control Word LSB of count LSB of count LSB of count MSB of count MSB of count MSB of count
80. ine is low sampling is halted 1 This is ideal mode when you want to acquire data for only as long as an external device holds the trigger high See the MULTGATE sample program in C and Pascal Channel Select Options Scans Direct channel In this option the channel specified in the CHANNEL CONVERSION MODE SELECT port is sampled each time a trigger is applied Use direct channel option when you only need to sample from one channel or if the order of channels to be sampled is unknown or not consecutive Scan channel In this option the channel from which to sample is automatically incremented after a conversion is complete The scan starts at the channel specified in the CHANNEL CONVERSION MODE SELECT port After converting channel 8 the AD3700 returns to channel 1 Use the scan channel option when you want to sample from all eight channels in consecutive order Since the channel counter is automatically incremented it is faster and easier than using the direct scan option and setting the channel for each conversion from software Timing Diagrams The following timing diagrams show how each of the eight possible conversion mode channel select option combinations are implemented by the A D converter and associated circuitry Figures 4 1 and 4 2 show you the Single Convert Internal Trigger mode timing
81. ion The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C 3 4 4 TIMER COUNTER 1 I 4 5 MHz XTAL P7 1 1 5 VOLTS ec T NE EXTERNAL PACER CLOCK PACER CLOCK EE 5 MHz XTAL N 5 VOLTS 1 CLK COUNTER GATE 2 EXTERNAL CLOCK 1 vors 5 VOLTS EXTERNAL GATE 1 22 COUNTER OUT 5 MHz XTAL 5 VOLTS TIMER OUT 5 MHz XTAL Fig 3 2 8254 Programmable Interval Timer Circuits Block Diagram Digital O Eight digital input and eight digital output lines can be used to transfer data between the computer and external devices Data transfers through the digital I O lines are independent of other board functions The input lines have pull up resistors All 16 lines are available at the external I O connector 3 5 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your AD3700 board It provides a complete description of the I O map a detailed description of programming operations and operating modes and flow diagrams to aid you in programming The example programs included on the disk in your board package are listed at
82. l Trigger 11 Multi Convert External Gate BA 2 Scan Channel Range Select Read Write Programs the number of channels to be activated for a scan cycle This number coupled with the analog input channel select programmed at BA 1 establishes the sequence for the channel scan For example if you want to do a scan of three channels starting with channel 3 analog input channel select one cycle will convert the input voltages at channels 3 4 and 5 Number of Channels 0000 invalid 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 3 Read Status Clear FIFO Read Write A read provides the eight bit status word defined below The A D converter HALT bit D2 is set to 1 stopping A D conversions whenever the FIFO is full or half full depending on the setting of the jumper on P4 This is the only way conversions can be stopped in the Multi Convert modes D1 is the FIFO full flag This flag is set to 0 whenever the FIFO is full D4 shows the status of either the external trigger in signal P2 39 or the external gate signal P2 46 depending on the setting of jumper P6 4 4 A write clears FIFO data written is irrelevant When the FIFO is cleared using BA 3 the FIFO empties out all data sets the FIFO empty flag EF low and sets the FIFO full flag high Clearing the FIFO also sets the LSB MSB flag to 1 so that the next byte of data read is the MSB and clears the HALT bit enabling A D co
83. l compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the AD3700 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR 15 arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for 1801 and so on 4 20 If you need to program source of your interrupts do tha
84. l the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command D Dg 05 04 D2 Dy Do latched count Description Head back count and status of Counter 0 T 1 9 reas back status of Counter Stats latched or Counter 1 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 Read back count of Counter 2 Count latched for Counter 2 111 1 Read back count and status of Count latched for Counter 1 Counter 1 but not status 1 O Read back status of Counter 1 Command ignored status already latched tor Counter 1 Figure 13 Read Back Command Example 3 90 THIS ACTION A Write to the contro word register B Write to the count register CR 121 C New count is loaded into CE CR 1 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 2 the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte 15 written CAUSES Null count 1 Null count 1 Null count 0 Figure 12 Count Operation lf multiple status latch operations of the
85. mple of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB C 96 amp a b c a b c a b amp c mov dx Address mov al Data out dx al MOD DIV AND a b MOD c a bDIVc b AND c a bORc BASIC MOD backslash AND OR a bMODc a b c a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to an 1 port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the AD3700 4 8 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 2 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress
86. mplement Unipolar Calibration Two adjustments are made to calibrate the A D converter for the unipolar range of 0 to 10 volts One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TRS is used to make the offset adjustment and trimpot TR1 is used for gain adjustment This calibration procedure is performed with the board set up for a O to 10 volt input range Before making these adjustments make sure that the jumper on P3 is set for 10V and the jumper on P5 is set for 4 Use analog input channel 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 1 22070 millivolts start a conversion and read the resulting data Adjust trimpot TRS until it flickers between the values listed in the table below Next set the voltage to 9 49829 volts and repeat the proce dure this time adjusting TR1 until the data flickers between the values in the table Note that the value used to adjust the full scale voltage is not the ideal full scale value for a O to 10 volt input range This value is used because it is the maximum value at which the A D converter is guaranteed to be linear and ensures accurate calibration results Data Values for Calibrating Unipolar 10 Volt Range 0 to 10 volts Offset TR5 Converter Gain TR1 Input Voltage 1 22070 mV Input Voltage 9 49829 V 0000 0000 0000 1111 0011 0010 A D Converted Data 0000 0000 00
87. nd will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires CWz12 158 3 12 4583 12 158 2 41 081513 231244 9 Figure 16 Mode 1 3 92 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE
88. ng steps list this procedure 1 Set the DMA channel bits in the IRQ DMA register 2 Set the channel scan mode 3 Set the triggering mode 4 Program the pacer clock if appropriate 5 Start conversions 6 Monitor the DMA done bit NOTE If the DMA is set up in the single transfer mode each DMA transfer will take two read cycles to complete Therefore when you run the AD3700 at 200 kHz in this mode the DMA transfer rate cannot keep up with the board s conversion rate Single transfers will run with the board up to about 120 kHz Above 120 kHz the FIFO can be used as storage bin for the converted data until the DMA can transfer it to PC memory or the demand mode can be used 4 25 Monitoring for DMA Done There are two ways to monitor for DMA done The easiest is to poll the DMA done bit in the AD3700 status register BA 3 While DMA is in progress the bit is clear 0 When DMA is complete the bit is set 1 The second way to check is to use the DMA done signal to generate an interrupt An interrupt can immediately notify your program that DMA is done and any actions can be taken as needed Both methods are demonstrated in the sample C and Pascal programs the polling method in the program named DMA and the interrupt method in DMASTR Common DMA Problems Make sure that your buffer is large enough to hold all of the data you program the DMA controller to transfer Check to be
89. ngle conversion is performed and the board waits for another START CON VERT command In the multi convert modes conversions are halted when the FIFO is full The HALT bit bit 2 of the Status word BA 3 is set when the FIFO is full disabling the A D converter If you want to stop execution in the middle of a run you can send a CLEAR BOARD command by writing to BA 7 However if you do this note that the contents of the FIFO will be lost Reading the Converted Data Two successive reads of port BA 4 provide the MSB and LSB of the 12 bit A D conversion in the format defined in the I O map section at the beginning of this chapter The MSB line and LSB line toggle with each read The MSB must always be read first followed by the LSB Bit 6 of the Status word BA 3 shows which byte is next This bit is set whenever a FIFO CLEAR command is issued so that the first byte read is the MSB The output code and the resolution of the conversion vary depending on the input voltage range selected Bipolar conversions are in twos complement form and unipolar conversions are straight binary When a bipolar value is read you must first convert the result to straight binary and then calculate the voltage The conversion formula is simple for values greater than 2047 you must subtract 4096 from the value to get the sign of the voltage For example if your output is 2048 you subtract 4096 2048 4096 2048 This result corresponds to 5 volts or
90. nput is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 10 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there 3 95 82 54 Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 510 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7 sections of this specification is not implied Ex Voltage on any Input GND 2Vto 6 5V to absolute maximum rating conditions for Volt Output GND 0 5V to Voc 0 5V 7 oltage any Output tO
91. nver sions DMA Done EF FIFO Empty Flag 0 DMA not done 0 FIFO empty 1 DMA done 1 FIFO not empty active in DMA mode only FF FIFO Full Flag LSB MSB Flag 0 FIFO full 0 Next byte read is LSB 1 FIFO not full 1 Next byte read is MSB Halt EOC Status 0 A D enabled 1 A D disabled 0 converting 1 not converting cleared whenever clear FIFO sent External Trigger External Gate Monitors TRIGGER IN or EXTGATE status depending on P9 jumper setting BA 4 Read FIFO Data Start Conversion Read Write Two successive reads provide the MSB and LSB of the A D conversion as defined below write starts a conversion data written is irrelevant Note that the MSB line and LSB line toggle with each read Bit 6 in the Status word BA 3 shows which byte is next x Bit11 10 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O BA 5 Clear DMA Done Bit Write Only Writing to this address clears the DMA done bit at BA 3 bit D7 data written is irrelevant This command lets you perform continuous DMA dumps of 64K from the FIFO into PC memory without losing any data while conversions are in progress BA 6 IRQ DMA Select Read Write Programs the interrupt source and channel and the DMA transfer mode Reading this register shows you the current settings Interrupt Channel Select Interrupt Source oma 000 interrupt disabled 000 halt converter high A D disabled
92. o disk DMA DMA Demonstrates how to use DMA to acquire data to a memory buffer Buffer can be written to disk and viewed with the included VIEWDAT program DMASTR Demonstrates how to use DMA for disk streaming Very high continuous acquisition rates can be obtained BASIC Programs These programs are source code files so that you can easily develop your own custom software for your AD3700 board Analog to Digital SINGLE Demonstrates how to use the single convert internal trigger mode for acquiring data SCAN Shows how to scan channels FIFO FIFO Shows how to run the pacer clock and use on board FIFO DMA DMA Shows how to take samples and transfer them to PC memory using DMA 4 29 Flow Diagrams The following paragraphs provide descriptions and flow diagrams for some of the AD3700 s A D conversion functions These diagrams will help you to build your own custom applications programs Single Convert Flow Diagram Figure 4 12 This flow diagram shows you the steps for taking a single sample on a selected channel A sample is taken each time you send the Start Convert command of the samples will be taken on the same channel until you change the value in the CHANNEL CONVERSION MODE SELECT register BA 1 Changing this value before each Start Convert command is issued lets you take the next reading from a different channel By changing the value in the CHANNEL CONVERSION MODE SELECT register you
93. omponents for accomplishing DMA However software support for DMA is not included as part of the BIOS or DOS leaving you with the task of programming the DMA controller yourself With a little care such programming can be successfully and efficiently achieved The following discussion is based on using the DMA controller to get data from a peripheral device and write it to memory The opposite can also be done the DMA controller can read data from memory and pass it to a periph eral device There are a few minor differences mostly concerning programming the DMA controller but in general the process is the same The following steps are required when using DMA Choose a DMA channel Allocate a buffer Calculate the page and offset of the buffer Set the DMA page register Program the DMA controller Program the device generating data AD3700 Wait until DMA is complete Disable DMA Each step is detailed in the following paragraphs Choosing a DMA Channel There are a number of DMA channels available on the PC for use by peripheral devices The AD3700 can use either DMA channel 1 or DMA channel 3 You can arbitrarily choose one or the other in most cases either choice 15 fine Occasionally though you will have another peripheral device for example tape backup or Bernoulli drive that also uses the DMA channel you have selected This will certainly cause erratic results and can be hard to detect The bes
94. ories for the AD3700 include the MX32 analog input expansion board which can expand a single input channel on your AD3700 to 16 differential or 32 single ended input channels 55 4 55 8 four and eight channel simultaneous sample and hold boards MR series mechanical relay output boards OP series optoisolated digital input boards the OR16 mechanical relay optoisolated digital I O board the TS16 thermocouple sensor board the TB50 terminal board and XB50 prototype terminal board for prototype development and easy signal access EX XT and EX AT extender boards for simplified testing and debugging of prototype circuitry and the XT50 twisted pair flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern st
95. pull up resistors What Comes With Your Board You receive the following items in your AD3700 package AD3700 interface board Software and diagnostics diskette with example programs in BASIC Turbo Pascal and Turbo source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your AD3700 package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Application Software and Drivers Our custom application software packages provide excellent data acquisition and analysis support Use SIGNAL MATH for integrated data acquisition and sophisticated digital signal processing and analysis or ATLANTIS for real time monitoring and data acquisition rtdLINX and labLINX drivers provide full featured high level interfaces between the AD3700 and custom or third party software including LABTECH NOTEBOOK NOTEBOOK XE and LT CONTROL rtdLINX source code is available for a one time Our Pascal and Programmer s Toolkit provides routines with documented source code for custom programming Hardware Accessories Hardware access
96. quals N 2 CLK pulses Two max equals Count N 1 CLK pulse min to count will be either N 1 or N 2 CLK pulses 7 in Modes 1 and 5 if GATE is present when writing a new Count value at Two min Counter will not be triggered at Two max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Tc min CLK will be reflected in count value latched at Tc max CLK will not be reflected in the count value latched Writing a Counter Latch or ReadBack Command between Tc min and Tw max will result in a latched count vallue which is one least significant bit 509 Output Delay tom Gated E 250 LK W L 5 H DG 125 OupuDeayfomCKl 20 EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature Parameter twc CLK Delay for Loading Gate Delay for Sampling t WAVEFORMS WRITE DATA BUS 231244 14 DATA BUS 231244 15 RECOVERY 231244 16 3 98 intel 82054 tc top ar toa 231244 17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT 20 gt TEST POINTS lt 23124418 A C Testing inputs are driven 2 4V for a logic 1 0 45 for a logic 0 Timing measurements are made at 2 0V for a logic 231244 19 Cy 15
97. r FIFO Start Conversion Check FIFO Full Flag 0 Yes Read MSB Check FIFO Read LSB Empty Flag Stop Program EF 0 Fig 4 13 FIFO Flow Diagram 4 31 DMA Flow Diagram Figure 4 14 This flow diagram shows you how to take samples and transfer the data directly into the computer s memory You can use DMA channel 1 or 3 to transfer 1024 samples 2048 bytes to the computer s memory Clear Board Program Pacer Clock Select Pacer Clock Operation Multiconvert Interna Gate Select Channel Select DMA Channel Clear DMA Done Bit Clear FIFO Program DMA Controller Start Conversion converter halted HALT 1 Report Error FIFO full before DMA was done Stop Program if DMA done DONE 1 Stop Program Fig 4 14 DMA Flow Diagram 4 32 Scan Flow Diagram Figure 4 15 This flow diagram shows you how to take samples from a sequence of channels without selecting the channel each time a conversion is started By setting the channel select option bit in the CHANNEL CONVERSION MODE SELECT register BA 1 to Scan Channel and setting the number of channels to be scanned at BA 2 the converter will automatically increment the channel each time the Start Convert command is sent The first channel sampled is the channel that is specified in the bottom three bits of t
98. r all input voltage ranges The first procedure cali brates the converter for the unipolar range 0 to 10 volts and the second procedure calibrates the bipolar ranges 5 10 volts Table 5 1 shows the ideal input voltage for each bit weight for the unipolar straight binary range and Table 5 2 shows the ideal voltage for each bit weight for the bipolar twos complement ranges Table 5 1 A D Converter Bit Welghts Unipolar Straight Binary Ideal Input Voltage millivolts A D Bit Weight 010 10 Volts 1111 1111 1111 9997 6 1000 0000 0000 5000 0 0100 0000 0000 2500 0 0010 0000 0000 1250 0 0001 0000 0000 625 00 0000 1000 0000 312 50 0000 0100 0000 156 250 0000 0010 0000 78 125 0000 0001 0000 39 063 0000 0000 1000 19 5313 0000 0000 0100 9 7656 0000 0000 0010 4 8828 0000 0000 0001 2 4414 0000 0000 0000 0 0000 5 3 nole pieog G 614 W3LSAS 1OHLNOO 9 NOLLISINDOV 8 34 on CD ao IS ne ns ARMA A MIRE A IEEE y ET RN UA 2 Ooti 0000000000 0 0600600000 D 00000000 0000000 00000000 0 0000000 0 00006000 J 60000000 on 010 un zn en sn sin o o C 2 ju 0000000000 A 000
99. rations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 n a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In this is programmed as v inportb port address v v amp 199 40 outportb port_address v A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits O to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for
100. roducts Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read lea
101. s to be entered in decimal notation F 1 APPENDIX F WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR P
102. se clock sources are connected to the timer counters Two gate sources are available for enabling the timer counters a 5 volt source and an external gate source P2 46 The same external gate source is connected to TC1 Counter 2 and the timer counters in TC2 The output from TC1 Counter 2 is available at the COUNTER OUT pin P2 44 on the I O connector where it can be used for interrupt generation as an A D trigger or for counting functions Any one of the three TC2 timer counter outputs or the 5 MHz clock can be connected to the TIMER OUT pin P2 42 on the I O connector where it can be used for interrupt generation as an A D trigger or for timing functions These connections are jumper selectable The timer counters can be programmed to operate in one of six modes depending on your application For example when measuring frequencies the timer counters in TC2 are set up for Mode 3 and TC1 Counter 2 is set up for Mode 0 when using it as an event counter it is set up for Mode 0 and the pacer clock 15 set up for Mode 2 The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to timer counter Mode 1 Hardware Retriggerable One Shot The output 15
103. st significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte Counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 AO A1 11 D 06 Ds D3 2 Do 1 COUNT STATUS 2 1 o Ds 0 Da 0 Latch count of selected counter s Latch status of selected counter s Da 1 Select counter 2 Do 1 Select counter 1 D4 1 Select counter 0 Do Reserved for future expansion must be 0 111 Figure 10 Read Back Command Format The read back command may be used to latch multi counter output latches OL by setting the OUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s lat
104. state bi directional 8 bit buffer is used to in terface the 82054 to the system bus see Figure 3 Sus dumb COUNTER y INTERNAL BUS COUNTER 2 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82054 A and select one of the three counters or the Control Word Regis ter to be read from written into A low on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82C54 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ag 11 the CPU then does a write operation to the 82054 the data is stored in the Control Word Register and 15 interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command INTERNAL BUS 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 Thes
105. sure that your buffer does not straddle a page boundary Remember that the number of bytes for the DMA controller to transfer is equal to twice the number of samples This 15 because each sample 15 two bytes in size If you terminate sampling before the DMA controller has transferred the number of bytes it was programmed for be sure to disable DMA by setting the mask bit in the single mask register Timer Counters Two 8254 programmable interval timers TC1 and TC2 each provide three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts Two of the timer counters in TC1 are cascaded and used for the pacer clock discussed earlier in this chapter The remaining four timer counters Counter 2 in TC1 and Counters 0 1 and 2 cascaded on TC2 are available for your use Figure 4 10 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map section at the beginning of this chapter One of two clock sources the on board 5 MHz crystal or the external clock 2 45 can be jumpered as the clock input to TC1 Counter 2 and or TC2 s timer counters The clock source for the pacer clock is jumper select able for 5 MHz or the external pacer clock P2 41 The diagram shows how the
106. t After the Control Word and initial count are written to for Reading Writing least significant byte meee only 2 a Counter the initial count will be loaded on the next 2 The counter is always selected CS always low CLK pulse This CLK pulse does not decrement the 3 CW stands for Control Word CW 10 means a count so for an initial count of N OUT does not go control word of 10 hex is written to the counter high until N 1 CLK pulses after the initial count is 4 LSB stands for Least Significant Byte of count written 5 Numbers below diagrams are count values The lower number is the least significant byte If a new count is written to the Counter it will be The upper number is the most significant byte Since loaded on the next CLK pulse and counting will con the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertica lines show transitions between count values tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required Figure 15 Mode 0 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 82054 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse a
107. t approach to pinpoint this problem is to read the documentation for the other peripheral devices in your computer and try to determine which DMA channel each uses Allocating DMA Buffer When using DMA you must have a location in memory where the DMA controller will place data from the AD3700 board This buffer can be either static or dynamically allocated Just be sure that its location will not change while DMA is in progress The following code examples show how to allocate buffers for use with In Pascal Var Buffer Array 1 10000 of Byte static allocation Var Buffer Byte dynamic allocation Buffer GetMem 10000 In C char Buffer 10000 static allocation Or char Buffer dynamic allocation Buffer calloc 10000 0 In BASIC DIM BUFFER 5000 Calculating the Page and Offset of a Buffer Once you have a buffer into which to place your data you must inform the DMA controller of the location of this buffer This is a little more complex than it sounds because the DMA controller uses a page offset memory scheme while you are probably used to thinking about your computer s memory in terms of a segment offset scheme Paged memory is simply memory that occupies contiguous non overlapping blocks of memory with each block being 64K one page in length The first page page O starts at the first byte of memory the second page page 1 starts at byte 65536 the
108. t next For example if you are using program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in IMR for the you are using This enables interrupts on the Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to I O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 One of the most common mistakes when writing an ISR is forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR Data Transfers Using DMA Direct Memory Access DMA transfers data between a peripheral device and PC memory without using the processor as an intermediate Bypassing the processor in this way allows very fast transfer rates All PCs contain the necessary hardware c
109. t the clock source for the three cascaded counters in TC2 XTAL connects the counters to the on board 5 MHz clock and connects them to an external clock source brought onto the board through the 1 connector The 5V and EXTGT pins connect the counters gate input to 5 volts or to an external gate brought onto the board through the 1 O connector The bottom four pins OUTO OUT1 2 and XTAL let you select any one of the three counter outputs or the on board 5 MHz clock to be available at the TIMER output on the 1 O connector The timer counters are further described in Chapters 3 and 4 XTAL EXTCK 5V EXTGT OUTO OUT1 OUT2 XTAL Fig 1 5 TC2 Source and OUT Select Jumper P6 P7 Pacer Clock Source Select Factory Setting XTAL This header connector shown in Figure 1 6 connects pacer clock s clock source to the on board 5 MHz XTAL clock or to an external clock applied through I O connector P2 P7 XTAL EXTPCK Fig 1 6 Pacer Clock Source Select Jumper P7 P8 TC1 Counter 2 Sources Factory Settings 45V XTAL This header connector shown in Figure 1 7 configures the clock and gate sources for Counter 2 in TC1 The top two pairs of pins set the gate input for 5 volts or the external gate source The bottom three pairs of pins set the clock source for the on board 5 MHz clock XTAL the external clock source EXTCK or the output of the pacer clock 1 Note that
110. ta transfer Its asynchronous operation means that data can be written to or read from it at any time at any rate When a transfer does begin the data first placed in the FIFO is the first data out The converted data can be transferred to PC memory in one of two ways through the PC data bus or by using direct memory access DMA Data bus transfers take more processor time to execute They use polling and interrupts to determine when data has been acquired and is ready for transfer DMA places data directly into the PC s memory one byte at a time with minimal use of processor time DMA transfers are managed by the DMA controller as a background function of the PC letting you operate at higher throughput rates Timer Counters Two 8254 programmable interval timers TC1 and TC2 provide six 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters in TC1 are cascaded and used for the pacer clock The pacer clock is described in Chapter 4 You can use the remaining four timer counters one from TC1 for counting applications and three cascaded on TC2 for timing applications Figure 3 2 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operat
111. tention when you first use your board in your system Table 1 1 Factory Settings Switch Jumper Function Controlled P3 Sets the A D input voltage range 10 volts Sets the FIFO full FIFO half full flag to halt A D conversions P4 when full or haif full FIFO full Sets the analog input for unipolar or bipolar uw Sets 8254 TC2 s clock and gate sources and TIMER output Sets the pacer clock source Factory Setting Bipolar XTAL top 5V and OUTO XTAL Sets 8254 TC1 Counter 2 s clock and gate sources 5V OUT1 Selects the external trigger in or external gate signal to be available for monitoring TRIGIN Jumper installed on Group B not compatible with earlier boards Jumper setting sets the 3700 to be fully compatible with earlier 3700 boards scan functions limited jumper setting B provides full board capability Configures the 3700 for normal use or for use with RTD s P11 SSH series simultaneous sample and hold boards Sets the base address P3 Input Voltage Range Factory Setting 10V 300 hex 768 decimal This header connector located in the upper right area of the board sets the input voltage range at 10 or 20 volts The 10V setting is for the 5 volts and 0 to 10 volts ranges the 20V setting is for the 10 volt range Figure 1 2 shows P3 with the jumper installed at 10V You do not have to recalibrate the board when you change voltage ranges P3 gt
112. ternal gain or loss including resistor configurable gain circuitry you added to the board For example if you have a gain circuit installed then you must tell SIGNAL MATH this gain If your input signal is externally attenuated then you can adjust for this by setting a value other than 1 for loss Numbers must be entered as whole decimal values The factory default setting for gain and loss is 1 For a bipolar input range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X D A Parameters These settings are not applicable to the AD3700 D 4 APPENDIX E CONFIGURING THE AD3700 FOR ATLANTIS E 1 If you have purchased ATLANTIS data acquisition and real time monitoring application software for your AD3700 please note that the ATLANTIS drivers for your board must be loaded from your driver disk into the same directory as the ATLANTIS EXE program All jumpers must be set to the factory positions as described in Chapter 1 except for P3 and P5 which can be configured for any of the three possible input ranges When running ATLANTIS make sure the base address setting in the program and on the board match S1 Base Address ATLANTIS assumes that the base address of your AD3700 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The ATINST program requires the base addres
113. the external gate and clock sources are the same ones connected to P6 for TC2 P8 45V EXTGT XTAL EXTCK OUT1 Fig 1 7 TC1 Counter 2 Sources Jumper P8 P9 External Trigger External Gate Monitor Factory Setting External Trigger This header connector shown in Figure 1 8 lets you select either the external trigger input P2 39 or the external gate input P2 46 to be available for monitoring at bit 4 of the status word BA 3 P9 TRIGIN EXTGT Fig 1 8 External Trigger External Gate Monitor Jumper P9 P10 Board Compatibility Select Factory Setting Jumper on B This header connector shown in Figure 1 9 allows you to maintain software and hardware compatibility with earlier AD3700 boards board serial numbers 64XXXX By installing a jumpers on the A pins top your new AD3700 will be fully compatible in data acquisition and control systems using the earlier board However the new AD3700 s expanded features such as programmable channel scan cannot be used When the jumper is installed across the B pins factory setting all new AD3700 functions are activated but compatibility with previous boards is lost A P10 B Fig 1 9 Board Compatibility Select Jumper P10 1 6 11 Simultaneous Sample and Hold Select Factory Setting NOR This header connector shown in Figure 1 10 configures the AD3700 to operate normally or with Real Time Devices SSH4 or SSH8 simultaneous sample and hold
114. third page page 2 at byte 131072 and so on A computer with 640K of memory has 10 pages of memory The DMA controller can write to or read from only one page without being reprogrammed This means that the DMA controller has access to only 64K of memory at a time If you program it to use page 3 it cannot use any other page until you reprogram it to do so When DMA is started the DMA controller is programmed to place data at a specified offset into a specified page for example start writing at byte 512 of page 3 Each time a byte of data is written by the controller the offset is automatically incremented so the next byte will be placed in the next memory location The problem for you when programming these values is figuring out what the corresponding page and offset are for your buffer Most compilers contain macros or functions that allow you to directly determine the segment and offset of a data structure but not the page and offset Therefore you must calculate the page number and offset yourself Probably the most intuitive way of doing this is to convert the segment offset address of your buffer to a linear address and then convert that linear address to a page offset address The table below shows functions macros for determining the segment and offset of a buffer FP_SEG FP_OFF 5 FP_SEG amp Buffer FP_OFF amp Buffer Pascal Seg Ofs S Seg Buffer Ofs Buffer BASIC VARSEG VARPTR S VARSEG BUFFE
115. ts These are only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences Read Operations is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82C54 There are three possible methods for reading the counters a simple read operation the Counter 3 68 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result 82 54 COUNTER LATCH COMMAND The second method uses the Counter Latch Com Like a Control Word this command is written to the Control Word Register which is selected when Ag 11 Also like a Control Word the 5 0 SC1 bits select one of the three Counters but two other bits D5 and DA distinguish this command from a Control Word A1 11 CS 0 RD 1 WR 0 D De Ds Da D3 D2 Dy Do o To x x x1x 501 SCO specify counter to be latched 501 SCO Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with future intel p
116. y to use menu driven diagnostics program 3700DIAG which is especially helpful when you are first checking out your board after installation and when calibrating the board Chapter 5 Before using the software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your AD3700 board In the directory AD3700 H and AD3700 INC contain all the functions needed to implement the main C programs H defines the addresses and INC contains the routines called by the main programs In the Pascal directory AD3700 PNC contains all of the procedures needed to implement the main Pascal programs Analog to Digital SOFTTRIG Demonstrates how to use the software trigger mode for acquiring data EXTTRIG Similar to SOFTTRIG except that an external trigger is used MULTI Shows how to fill an array with data using a software trigger MULTGATE Shows how to use the external trigger to gate multiple conversions SCANN Demonstrates channel scanning of five channels Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer Digital DIGITAL Simple program that shows how to read from and write to the digital I O lines Interrupts INTRPTS Shows the bare essentials required for using interrupts INTSTR A complete program showing interrupt based streaming t
117. ys tems ADDRESS BUS 16 0 0 82054 COUNTER 1 OUT GATE OUT GATE CLK OUT GATE CLK 231244 7 i COUNTER COUNTER 9 2 Figure 6 82C54 System interface 3 86 82054 OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format Ap 11 CS 0 RD 1 D De Ds Programming 82054 Counters are programmed by writing a Contro Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when Ay Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ap in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used D2 D Do scr sco awo Bco SC Select Counter Select Counter 0 Select Counter 1 Select Counter 2 Read Back Command See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations Read Write least sign

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