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SYS68K/CPU-60 Technical Reference Manual

1. Table 70 User patch table Offset Default Size Description 0016 SY STRT O DS B 22 Name of the start up file It must be a 0 terminated string 1616 8 DS W 1 I RAM disk disk number MODE 2 rotary switch bit 1 0 and bit 0 0 2048 DS W 1 Number of 256 byte sectors 2048 512 KB 4080 000016 DSL 1 Start address in A32 VME space 8 DS W 1 2 RAM disk disk number MODE 2 rotary switch bit 1 0 and bit 0 1 256 DS W 1 Number of 256 byte sectors 256 64 KB FFCO 80001 DS L 1 Start address in local SRAM NVRAM 8 DS W 1 3 RAM disk disk number MODE 2 rotary switch bit 1 1 and bit 0 0 2048 DS W 1 Number of 256 byte sectors 2048 512 KB FC80 00001 DSL 1 Start address in A24 VME space 2Ei SY DSK 0 DS B 18 Default name of initialized RAM disk must be a 0 termi nated string 401g 4080 000016 DS L 1 Alternatives for the program start address which is jumped FFCO 80001 DS L 1 to after kernel initialization The address actually used can FC80 0000i DS L 1 be selected by bit 3 and bit 2 of the MODE 1 rotary switch ou Pode 1 entry Start program at addr 4080 0000 VME e 2 entry Start program at addr FFCO 80004 NVRAM 3 entry Start program at addr FC80 0000 VME 4 entry Start addr of the VMEPROM shell 5016 USER DS B 4 Disk drivers need this ident to make sure that the data be ginning at 54 is valid 5416 0346
2. Serial I O Ports SCC Installation Table 7 Pinout of the front panel serial I O ports config for RS 485 Pin Signal 1 RX TX 1 O ols 2 GND O O 3 To be connected to GND via RS 485 O O cable 2 O OTS 4 n c 5 5 GND 6 RX TX 7 To be connected to GND via RS 485 cable 8 GND 9 n c IMPORTANT In case of the RS 485 configuration connect the pins 3 and 7 to GND via the RS 485 cable e g by connecting them to the pins 2 and 8 respectively Default port FH 002 installed for RS 232 support setup Asynchronous communication 9600 Baud 8 data bits 1 stop bit no parity Hardware handshake protocol Interface options To easily vary the serial I O interfaces according to the application s needs FORCE COMPUTERS has developed RS 232 RS 422 and RS 485 hybrid modules the FH 002 FH 003 FH 422T and FH 007 The difference between FH 003 and FH 422T is that FH 422T has inter nal termination resistors For each serial I O port one of these 21 pin sin gle in line SIL hybrids is installed on board serial I O port 1 hybrid installed in location J21 serial I O port 2 hybrid installed in location J22 Page 20 syseskcpu co WEE 204077 2 3 June 1999 Installation 2 8 A Switches selecting serial T O options SCSI SCSI After installing the correct hybrid for the port under consideration the port has to be configured accordingly by using the appropriate s
3. R X E SYS68K CPU 60 Page 65 Boot PROM Hardware 3 11 1 Boot PROM Address Map and Factory Options Boot PROM The base addresses of the default and the optional boot PROM are fixed base addresses that means they cannot be changed After booting one of the boot PROM devices is accessible at base address FFEO 00004 regardless of the SW7 1 setting If SW7 1 is in its default setting default OFF see page 12 FFE0 00004g is the base address of the default PROM device in socket 1 Otherwise FFEO 0000 is the base address of the optional PROM device in socket 2 If the optional boot PROM device is installed and if socket 1 is not dis abled by SW7 1 being set to ON the optional boot PROM device is accessible at FFE8 000046 IMPORTANT After reset the boot PROM is mapped to address 0000 00004g After initialization the firmware enables the DRAM at 0000 00004g with an access to any of the RIALTO registers Factory options The following factory options are available for the boot PROM using the listed device types or equivalent Table 36 Boot PROM address map factory options and device types Factory option Offset range for each installed device Device type base address as documented above Total capacity 12V 28F010A 128k 8 0 000046 1 F FFF 16 128 Kbyte 12 V flash memory only in socket 1 default 28F020A 256k 8 0 0000 65 3 FFFF 16 256 Kbyte 12 V fl
4. A R X E SYS68K CPU 60 Page 17 Serial I O Ports SCC Factory option Jumpers and terminations Connector availability Pinout Page 18 Installation The two serial I O ports are available via 9 pin standard D Sub connec tors at the front panel The SERIAL 1 front panel port is also available on the VMEbus P2 connector see section 2 11 VMEbus P2 Connector Pi nout on page 24 All ports may be configured for RS 232 RS 422 and RS 485 standard conformance via installing the respective FORCE COMPUTERS hybrids FH 00x As factory option the SERIAL 2 front panel port is also available on the VMEbus P2 connector see section 2 11 VMEbus P2 Connector Pinout on page 24 The SERIAL 2 on P2 and the wide SCSI factory option are not available simultaneously There are no on board jumpers to configure the serial ports and no line terminations for RS 422 and RS 485 interfaces If termination resistors are required to compensate various cable lengths and to reduce signal re flections they must be installed externally to the SYS68K CPU 60 e g via a cable connector The resistor value is application dependent but a recommended value is 1000 Q Both serial I O ports 1 and 2 are available via a front panel 9 pin D Sub connector per factory default only serial I O port 1 is available via the P2 connector serial I O port 1 is wired to the front panel connector labeled SERIAL 1 and to the VMEbus P2 connector w
5. FFF4 0004i6 00xx xxxxig Bridge configuration reg BCR Bridge Configuration Register The bridge configuration register of the RIALTO bus bridge features sev eral status and control bits to monitor and control the configuration Table 23 Bridge configuration register BCR FFF4 0004 Bit 7 6 5 4 3 2 1 o reserved LAN USER SNOOP 2 0 Value DEC LED LANDEC LANDEC defines the Ethernet decoding space see section 3 21 1 Regis R W ter Access on page 98 0 Ethernet decoding space is FFF0 000046 FFF3 FFFF4g 1 Ethernet decoding space is 0000 000046 0003 FFFF4g svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware FGA 002 Gate Array USERLED Controls the front panel UL LED R W 0 LEDison 1 LED is off SNOOP 2 0 The snoop bits shrink the DRAM accessible from the VMEbus to the val R W ue listed in the table This is done be masking out the higher address lines After power up the SNOOP 2 0 bits show the revision of the RIALTO bus bridge Table 24 Snoop window definition in BCR SNOOP 2 0 Snoop window 0 0 0 32 Mbyte 0 0 1 16 Mbyte 0 1 0 8 Mbyte 0 1 1 4 Mbyte 1 0 0 2 Mbyte 1 0 fl 256 Mbyte 1 1 0 128 Mbyte 1 1 1 64 Mbyte 3 7 FGA 002 Gate Array The FGA 002 controls the I O bus and builds the interface to the VME bus It also includ
6. 6 5 13 SELFTEST Format A N z E SYS68K CPU 60 Perform On Board Selftest SELFTEST This command performs a test of the on board functions of the CPU board It can only run if no other tasks are created If there are any other tasks no self test will be made and an error will be reported SELFTEST tests the memory of the CPU board and all devices on the board The following tests are performed in this order 1 I O test This function tests the DMA controller the SCRIPTS processor and the interrupts of the SCSI controller The floppy disk controller will be checked if it can be initialized Then the access to the registers of the PCnet Ethernet controller will be tested CIO1 and CIO2 will be tested if they are able to generate vector interrupts via a timer If tests fail error messages will be printed to state the type of fault 2 Memory test on the memory of the current task Page 145 Installing a New Hard Disk Using FRMT and INIT VMEPROM IMPORTANT The following procedures are performed Byte test Word test Longword test All passes of the memory test perform pattern reading and writing as well as bit shift tests If an error occurs while writing to or reading from the memory it will be reported Dependent on the size of the main memory this test may last a different amount of time count about one minute per Megabyte 3 Clock test If the CPU does not receive timer inter
7. FRMT 68K PDOS Force Disk Format Utility Possible Disk Controllers Controller 1 is not defined Controller 2 is a FORCE WFC 1 Controller 3 is a FORCE ISCSI 1 Controller 4 is an onboard SCSI Controller 5 is not defined Controller 6 is a FORCE IBC in this System are Drives that are currently FO is controller 4 Fl is controller 4 WO is controller 4 defined in system are drive select 82 drive select 83 drive select 00 All not named drives ar Select Menu Select Drive W WO Main Menu Command 1 W WO W15 Winch 1 Parm 2 BadT 3 Form 4 Veri 5 Part 6 Writ P Togl Q Quit undefined F FO F8 Floppy Q Quit WO Parameters Menu A lter D isplay R ead file Q uit Command A of Heads 10 of Cylinders 1022 Physical Blocks per Track 32 Physical Bytes per Block 256 Shipping Cylinder 0 Step rate 0 Reduced write current cyl 0 Write Precompensate cyl 0 Current Winch Drive 0 Parameters of Heads of Cylinders Physical Blocks per Track Physical Bytes per Block Shipping Cylinder Step rate current cyl Reduced writ Writ 10 1022 S32 256 0 0 0 a X E SYS68K CPU 60 Precompensate cyl Page 147 Installing a New Hard Disk Using FRMT and INIT Page 148 WO Parameters Menu Command Q WO Main Menu A lter P Togl Q Quit Command 3 Sector Interleave 0 Physical Tracks to FORMAT 0 10219 Rea
8. IMPORTANT FDC connectors and pinout FDC register map Table 54 Floppy Disk FDC 37C65C e 2 drive selects DSEL 1 and DSEL 2 generated by the FDC 37C65C 2 signals for motor control on the SYS68K CPU 60 they are tied together to build the motor on signal To start the floppy disk data transfer the FGA 002 on chip DMA control ler has to be configured in the following way e Set the AUX DMA data direction correctly see CIOI port B data reg ister on page 42 F ADDIR bit Set the FGA 002 AUX DMA according to the FORCE Gate Array FGA 002 User s Manual The FDC signals are available at the VMEbus P2 connector see section 2 11 VMEbus P2 Connector Pinout on page 24 An I O back panel can be plugged onto the rear side of the backplane to interface the SYS68K CPU 60 to standard FDC connectors see section 2 11 VMEbus P2 Connector Pinout on page 24 The registers of the FDC are accessible via the 8 bit local I O bus byte mode The following table shows the register layout of the FDC 37C65C for the SYS68K CPU 60 FDC register map Address Register name FF80 3800 D FDC read main status register RO FF80 3801 Read and write data register FF80 3880 6 When read DCHG register When written data rate selection register FF80 3900 Write digital output register WO FF80 3980 6 Access to toggle EJECT line R X E SYS68K CPU 60 Page 95 Ethernet L
9. PDOS BENCHMARK 2 EVENT SET MOVEQ L 32 D1 SELECT EVENT 32 MOVE L 100000 D6 000 XSEV SET EVENT SUBO L 1 D6 DONE BGT S 0000 PN RTS PAGE PDOS BENCHMARK 3 CHANGE TASK PRIORITY MOVEQ L 1 D0 SELECT CURRENT TASK MOVEQ L 64 D1 SET PRIORITY TO 64 MOVE L 100000 D6 8000 XSTP SET PRIORITY SUBQ L 1 D6 DONE BGT S 0000 iN RTS Page 172 Appendix to VMEPROM syseskcpu co WEE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 Appendix to VMEPROM CLR L DO LEA L MESO1 PC A1 MOVE L 100000 D6 PDOS BENCHMARK 4 SEND TASK MESSAGE SELECT TASK 0 POINT TO MESSAGE Benchmark Source Code 8000 XSTM SEND MESSAGE XKTM READ MESSAGE BACK SUBQ L 1 D6 DONE BGT S 0000 iN RTS MESO1 DC B BENCH 13 0 EVEN PAGE PDOS BENCHMARK 5 READ TIME OF DAY MOVE L 100000 D6 000 EQU XRTP SUBQ L 1 D6 DONE BGT S 0000 iN RTS end p id K N E SYS68K CPU 60 Page 173 Modifying Special Locations in ROM Appendix to VMEPROM 7 7 Modifying Special Locations in ROM IMPORTANT Address of user patch table Special locations in the VMEPROM binary image define the default setup of the start up file s name RAM disk addresses and the user program s location The special locations are defined in the user patch table and can be changed by the user to adapt VMEPROM to the actual working environ ment S
10. RTC 72421 in section 5 RTC 72423 features Feature Value Supported port size Byte only D3 0 valid Access mode Byte only Access address FF80 30004 R X E SYS68K CPU 60 Page 71 Real Time Clock RTC 72423 3 14 4 RTC Registers Address Map Hardware The RTC 72423 has a 4 bit data bus which has to be accessed in byte mode The upper four bits 4 7 are don t care during read and write accesses Base address Table 41 FF80 3000y RTC registers address map Default I O base address FF80 300046 Name RTC Offset Register name 0016 RTCISEC 1 second digit reg 0116 RTC10SEC 10 second digit reg 0216 RTCIMIN 1 minute digit reg 0316 RTC10MIN 10 minute digit reg 0416 RTCIHR 1 hour digit reg 0516 RTCIOHR PM AM and 10 hour digit reg 0616 RTCIDAY 1 day digit reg 0716 RTCIO DAY 10 day digit reg 081g RTCIMON 1 month digit reg 0916 RTCIOMON 10 month digit reg 0A1g RTCIYR 1 year digit reg 0B1g RTCIO YR 10 year digit reg 0C1g RTCWEEK Week reg 0D16 RTCCOND Control reg D 0E16 RTCCONE Control reg E OF 16 RTCCONF Control reg F Page 72 syseskicpu co WEE 204077 June 1999 last documentation change with SY SGBK CPU 60 PCB Rev 0 1 Hardware 3 14 2 Reading from or Writing to the RTC 72423 IMPORTANT Example Real Time Clock RTC 72423 Stop the RTC 72423 before reading the date and t
11. SCSI 53C720SE GPCNTL register FFF8 004416 Bit 7 6 5 4 3 2 1 0 GPIO_ GPIO_ Value enl eno Bit 7 2 Do not modify bits 2 through 7 GPIO enl GPIO enl controls if GPIO 1 pin is input or output R W 0 GPIO_1 is output RS 485 interface on serial channel 2 1 GPIO_1 is input RS 232 RS 422 interface on serial channel 2 GPIO en0 GPIO en0 controls if GPIO_O pin is input or output R W 0 GPIO Ois output RS 485 interface on serial channel 1 1 QGPIO is input RS 232 RS 422 interface on serial channel 1 Table 53 SCSI 53C720SE GPREG register FFF8 00041 Bit 7 6 5 4 3 2 1 0 GPIO_ GPIO_ Value 1 0 Bit7 2 Do not modify bits 2 through 7 GPIO 1 GPIO 1 controls the RS 485 TX enable function for serial channel 2 R W 0 RS 485 transmitter is enabled 1 RS 485 transmitter is disabled Page 91 SCSI 53C720SE GPIO 0 R W NOTICE A IMPORTANT Hardware GPIO O0 controls the RS 485 TX enable function for serial channel 1 RS 485 transmitter is enabled RS 485 transmitter is disabled Damage of components Be sure to set the switches SW12 1 and SW12 3 OFF for the RS 485 configuration before configuring the GPIO ports as outputs The serial interface driver of VMEPROM can be used for RS 232 and RS 422 asynchronous communication only It does not support the RS 485 configuration 3 19 SCSI 53C720SE Page 92
12. This file cannot be created It must already exist with correct write per missions filename Name of the file to save data from the local memory into This filename must already exist on the host LE svsesk CPU c0 Page 191 Debugger Commands FGA Boot start address Local start address of the region that should be saved into the file Note that the NETLOAD command on the CPU 60 uses space 0000 0000 6 to 0000 2FFF16 of the main memory for data buffers This region cannot be used for other purposes during the transfer end address Local end address of the region that should be saved into the file ethernet number The ethernet number that should be used for the CPU 60 board for the TFTP transfer It must be specified as 6 two digit hex numbers separat ed colons If the ethernet number is stored on the board this parameter is optional target IP f IP Internet Protocol number of the CPU board server IPf IP Internet Protocol number of the server where the file is located Example The following commands save the memory region 0010 01004 to 0010 011F g into the file test The file s content will be overwrit ten FORCE BOOT BF 100100 100120 Another Test i P FORCE BOOT MD 100100 20 0010 0010 0100 0110 23 20 41 6e 6f 74 68 65 72 20 54 65 73 74 20 23 Another Test 23 20 41 6e 6f 74 68 65 72 20 54 65 73 74 20 23 Another Test FORCE BOOT NETSAVE test 100100 1
13. VMEPROM Table 63 Layout of system flash memory Devices and Interrupts Used by VMEPROM Start address End address Type FF00 00004 amp FF00 0003 Initial supervisor stack pointer FF00 0004 5 FF00 0007 6 Initial program counter FF00 000845 FF00 000Big Pointer to VMEPROM initialization FF00 000Ci FF00 000F amp Pointer to user alterable locations FF00 001016 Pointer to VMEPROM shell Initial pro gram counter BIOS modules kernel file manager ROM resident installable devices and tables Pointer to initialization VMEPROM initialization code Pointer to al terable loca tions User alterable memory locations System tools Pointer to shell VMEPROM shell system tools debugging tools line assembler disassembler FF08 0000 FF3F FFFF g Unused system flash memory 6 4 Devices and Interrupts Used by VMEPROM 6 4 1 Addresses of the On Board I O Devices Table 64 A The following table shows the on board I O devices and their addresses On board I O devices Base address Device FF80 0C00 CIOI Z8536 FF80 0E00 CIO2 Z8536 R X E SYS68K CPU 60 Page 133 Devices and Interrupts Used by VMEPROM Table 64 On board I O devices cont VMEPROM Base address Device FF80 2000 SCC Z85C30 FF80 3000 RTC 72423 FFF8 0000i S
14. command line pointer f 41E char bum beginning of user memory Z 422 char eum end user memory ae 426 char _ead entry address Ef 42A char _imp internal memory pointer f 42E int _aci assigned input file ID 430 int _aci2 assigned input file ID s 432 int len last error number 434 int _sfi spool file id cP 436 BYTE _flg task flags bit 8 command line echo 437 BYTE _slv directory level E 438 char _fec file expansion count s 439 char _sparel reserved for future use m 43A char csc 2 clear screen characters A3C char pserz2 position cursor characters Fo 43E char _sds 3 alternate system disks 441 BYTE sdk system disk ef 442 char ext XEXT address 4 446 char err XERR address dd 44A char cmd command line delimiter 44B BYTE tig task id ur A4C char ecf echo flag ky 44D char _cnt output column counter 44E char _mmf memory modified flag 4 44F char _prt input port 4 4 450 char _spu spooling unit mask A 451 BYTE unt output unit mask xy 452 char ulp unit 1 port 453 char _u2p unit 2 port R 454 char _u4p unit 4 port rd 455 char u8p unit 8 port af 456 char _spare2 26 reserved for system use S EEK K k KKK I kk k kk k k Kk k k k k k Kk Ck k k k k k
15. If this setup is done once for a particular drive the data is stored in the first sector of the Winchester and automatically loaded when the disk controller is installed in VMEPROM To install the driver for the WFC 1 use the install command with the appropriate address see Software version dependent addresses on page 151 INSTALL W FFO2BA00 The default base address of the WFC 1 controller must be set to FCBO 1000 That means the address comparison for 32 bit address has to be enabled and the setup of the most significant 8 addresses must be jumpered VMEPROM supports termination interrupt of the WFC 1 controller If you want to use the WFC 1 in combination with interrupts the corre sponding jumper must be set to enable the interrupt For a detailed description of the address setup and termination interrupt refer to the data sheet of the WFC 1 controller 7 1 5 SYS68K ISCSI 1 Disk Controller Page 156 VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the ISCSI 1 disk controller The floppy drives must be jumpered to drive select 3 and 4 VMEPROM accesses them as disk number 0 and 1 The floppy drives are installed automatically when an ISCSI 1 controller is detected by the coxrzc command or after press ing reset when the front panel switch of the CPU board is set to detect the hardware configuration Only double sided and double density floppy drives which supp
16. VMEPROM Commands Off board interrupt sources IRQ Vector Board base Board level Vector number address address SIO 1 2 4 64 75 404g 4B g 10046 12C g FCB0 000016 ISIO 1 2 4 76 83 4C46 53 6 13046 14Cy6 FC96 0000 WFC 1 3 119 74g 1DCi FCBO 10004 ISCSI 1 4 119 774g 1DCi FCA0 00004 amp The On Board Real Time Clock During the power up sequence the on board real time clock of the CPU board is read and the current time is loaded into VMEPROM This se quence is done automatically and requires no user intervention If the software clock of VMEPROM is set by the zn command the RTC is au tomatically set to the new time and date values VMEPROM Commands Common commands CPU board commands Quick overview Command line syntax The VMEPROM commands are resident and available at any time Most of the commands are common for all versions of VMEPROM For a description of all common VMEPROM commands and for an in depth description of VMEPROM itself refer to the VMEPROM Version 2 32 User s Manual VMEPROM commands which are specific for the hardware of the CPU board are described in this section The HELP command provides a short description of all available VME PROM commands Enter HELP for a description of all commands Enter HELP command for a description of the command command All VMEPROM commands use the following format command parameters
17. 13 0D16 03416 Coprocessor protocol violation 14 OEig 03816 Format error 15 OFig 03Cig Uninitialized interrupt 16 23 101671716 0404 6 05Cig reserved Unassigned 24 1816 06016 Spurious interrupt 25 1916 06416 AVI 26 1Aig 06816 AV2 27 1Big 06Cig AV3 28 1Cig 07016 AVA 29 1Dig 07416 AVS 30 lEig 07816 AV6 31 TEL uro AV7 32 47 2016 2F 0804g 0BC4g TRAP 0 15 instruction vectors 48 3016 0COig FP branch or set on unordered condition gt R X E SYS68K CPU 60 Page 165 Interrupt Vector Table of VMEPROM Appendix to VMEPROM Vector number Vector address Assignment 49 311g 0C41g FP inexact result 50 BO ve 0C8i FP divide by zero 51 3346 0CCig FP underflow 52 341g 0D0 g FP operand error 53 351g OD41 FP overflow 54 3616 0D81g FP signaling NAN 55 3716 ODCi FP unimplemented data type 56 381g 0E0146 PMMU configuration 57 3916 OF 416 PMM U illegal operation 58 3Ai 0E8156 PMMU access level violation 59 3Big OECig reserved Unassigned 60 3C1g 0F0ig Unimplemented effective address 61 3D1g 0F41g Unimplemented integer instruction 62 63 3E g 3Fig OF84g OFCig reserved Unassigned 64 75 4016 4Big 10046 12C4g SIO 1 2 interrupt vectors port 41 6 76 83 4C46 53 amp 13016714C16 ISIO 1 2 interrupt vectors Port 1 2 15 16 84 118 5416 7646 1504g 1D84g User defined vectors 119 Tae lDCig Disk interrupt vector IS
18. 5 FC98 808046 6 FC98 80A016 7 FC98 80C046 8 FC98 80E046 Simultaneous VMEPROM supports up to two serial I O boards These can be either the use of SIO 1 2 SIO 1 2 board the ISIO 1 2 board or a mixture of both and ISIO 1 2 IMPORTANT The first board of every type must be set to the first base address If one SIO 1 board and one ISIO 1 board are used the base address of the boards must to be set to e FCBO 0000 for SIO 1 FC96 00004 for ISIO 1 7 1 4 SYS68K WFC 1 Disk Controller VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the WFC 1 disk controller The floppy drives must be jumpered to drive select 3 and 4 VMEPROM accesses them as disk number 0 and 1 The floppy drives are automati cally installed when a WFC 1 controller is detected by the CoNF IG com mand or after reset when the front panel switch of the CPU board is set to detect the hardware configuration Only double sided and double density floppy drives which support 80 tracks side can be used The step rate is 3 ms The Winchester drives are not installed automatically The FRMT com mand must be used for defining the following factors The physical drive structure i e number of heads number of cylin ders drive select number etc The bad block of the Winchester drive The partitions to be used A R X E SYS68K CPU 60 Page 155 Driver Installation To install driver Appendix to VMEPROM
19. A RARP server and a translation table are required for this task E g on a UNIX system the file etc ethers must contain the board s Ethernet number After the board has received its own IP number a TFTP request is sent to this server which has replied the RARP The server now starts sending the requested file On a UNIX system the file must be located in the t tpboot directory ARP When the board s own target IP and server IP number are given by target IPand server IPf a standard ARP request is broad casted to get the Ethernet number of the server After the board has received the ARP reply a TFTP request is sent to the specified server This server now starts sending the requested file On a UNIX system the file must be located in the t ftpboot directory Parameters filename Name of the file to load from the host to the local memory start address Local start address where the contents of the file should be stored to Note that the NETLOAD command on the CPU 60 uses space 0000 0000 to 0000 2FFF4g of the main memory for data buff ers This region cannot be used for other purposes during the transfer ethernet number The Ethernet number that should be used for the CPU board for the TFTP transfer It must be specified as 6 two digit hex numbers separat ed by colons If the Ethernet number is stored on the board this param eter is optional Page 190 svsesk cPU so R LE ange with FGA Boot Ver
20. ANSI K3T 9 2 compliant CAUTION IMPORTANT SCRIPTS enhancement A Small Computer System Interface SCSI controller is built around a 53C720SE see data sheet SCSI 53C720SE in section 5 The full ANSI K3T 9 2 specification is implemented supporting all stan dard SCSI features including arbitration disconnect reconnect and pari ty As done automatically by FGA Boot the first access to the 53C720SE must set the EA bit in the 53C720SE DCNTL register Accessing the 53C720SE without the EA bit set will lock the CPU bus To guarantee correct bus arbitration the fast arbitration mode must be selected by setting the FA bit in the 53C720SE DCNTL register To make SCSI master cycles snoopable the TT1 bit in the 53C720SE CTESTO register must be set The 53C720SE based SCSI controller uses its own code fetching and SCSI data transfer from the on board DRAM The controller s processor executes so called SCSI SCRIPTS to control the actions on the SCSI and the CPU bus Therefore the controller s processor is also called SCRIPTS processor SCSI SCRIPTS is a specially designed language for easy SCSI protocol handling It substantially reduces the CPU activities The SCRIPTS processor starts SCSI I O operations in approximately 500 ns whereas traditional intelligent host adapters require 2 8 ms svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware IRQ SCSI conn
21. Accessible from 68060 CPU Access address FF80 38001 Port width Byte Interrupt request level Software programmable FGA 002 interrupt Local IRQ 1 The FDC signals are available at the VMEbus P2 connector see section 2 11 VMEbus P2 Connector Pinout on page 24 An I O back panel can be plugged onto the rear side of the backplane to interface to standard FDC connectors see section 2 12 SYS68K IOBP 1 on page 28 2 10 Ethernet LAN A Device LAN AM 79C965A Frequency 68060 CPU bus frequency Package PQ160 Accessible from 68060 CPU Access address FFF0 00001 Port width Word only in 16 bit mode long in 32 bit mode Interrupt request level Software programmable FGA 002 interrupt Local IRQ 7 The Ethernet AUI interface is available at the front panel via a 15 pin D Sub connector As factory option Cheapernet is available via an SMB connector instead of the Ethernet AUI interface R X E SYS68K CPU 60 Page 23 VMEbus P2 Connector Pinout Installation The CPU bus interface is 32 bit wide and able to transfer data via the DMA controller of the AM 79C965A The following table shows the pinout of the factory default Ethernet con nector Table 8 15 pin AUI Ethernet connector Pin Signal 1 GND 1 o gt 5 2 Collision 4 S 3 Transmit data O 4 GND O O e 5 Receive
22. BYTE nokill kill task with no input port FC9 BYTE u mask unit mask for echo ra FCA WORD sysflg system flags used by VMEPROM Z bit 0 display registers short form j bit 1 trace without reg display 4 bit 2 trace over subroutine bit 3 trace over subroutine active EY bit 4 trace over range y bit 5 no register initialization 7 bit 6 output redirection into file 7 and console at the same time FCC LWORD t_range 2 start stop PC for trace over range FD4 LWORD ex regs pointer to area for saved regs A FD8 BYTE sparend 0x1000 0xFD8 make tcb size 1000 bytes char tbe 0 task beginning ange with VMEPROM 32 Vers 2 85 E Page 164 SYS68K CPU 60 KE Appendix to VMEPROM Interrupt Vector Table of VMEPROM 7 5 Interrupt Vector Table of VMEPROM Vector number Vector address Assignment 0 0016 00016 Reset Initial supervisor stack pointer 1 011g 00416 Reset Initial program counter 2 0216 00816 Bus error 3 031g 00Ci Address error 4 0416 01016 Illegal instruction 5 0516 01416 Zero divide 6 0616 01816 CHK CHK2 instruction 7 0716 01Cig FTRAPcc TRAPcc TRAPV instructions 8 0816 02016 Privilege violation 9 0916 02416 Trace 10 OAi6 02816 VMEPROM system calls 11 0Big 02Ci Coprocessor instructions 12 0Ci 03016 reserved Unassigned
23. Standard non privileged data program access Extended supervisory data program access Extended non privileged data program access Via FGA 002 A32 A24 A16 D8 D16 D32 UAT RMW A32 A24 D8 D16 D32 UAT RMW Arbiter Arbiter request modes Single level with arbitration timeout ROR RBCLR REC RAT SYSCLK driver yes IACK daisy chain driver yes Slot 1 function switch yes Mailbox interrupts 8 FORCE Message Broadcast FMB FIFO 0 8 Byte FMB FIFO 1 1 Byte Interrupts VMEbus and local interrupt handler 1 to 7 Programmable IRQ levels for all sources yes Total number of IRQ sources 42 Reset and abort switches yes VMEPROM firmware installed on all board versions 512 Kbyte svsesk ceu so EE 204077 June 1999 Introduction Specification Table 1 Specification for the SYS68K CPU 60 board cont Power requirements for a SYS68K CPU 60D 32 5 V max 3 5 A typical 12 V max 0 1 A typical with no Ethernet MAU plugged 12 V max 0 1 A typical R Backup battery at location BAT 1 CR2032 type lithium battery Front panel features Reset and abort key 4 Status LEDs 7 segment display 2 rotary switches Operating temperature with forced air cooling Storage temperature Without battery With installed battery Relative humidity non condensing 0 C to 55 C 40 C to 85 C 40 C to 60 C 5 96 to 95 Board dimensions 160 mm x 233 mm No of slots us
24. p ICE A SOLECTRON SUBSIDIARY SYS68K CPU 60 Technical Reference Manual P N 204077 Edition 2 3 June 1999 FORCE COMPUTERS Inc GmbH All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS 9 R SCE A SOLECTRON SUBSIDIARY MPUTERS cS f S World Wide Web www forcecomputers com 24 hour access to on line manuals driver updates and application notes is provided via SMART our SolutionsPLUS customer support program that provides current technical and services information Headquarters The Americas Europe Asia FoRCE COMPUTERS Inc FoRcE CoMPUTERS GmbH Force COMPUTERS Japan KK 5799 Fontanoso Way Prof Messerschmitt Str 1 Miyakeya Building 4F San Jose CA 95138 1015 D 85579 Neubiberg Miinchen 1 9 12 Hamamatsucho U S A Germany Minato ku Tokyo 105 Japan Tel 1 408 369 6000 Tel 49 89 608 14 0 Tel 81 03 3437 3948 Fax 1 408 371 3382 Fax 49 89 609 77 93 Fax 81 03 3437 3968 Email support fci com Email support force de Email smiyagawa Gfci com NOTE The information in this document has been carefully checked and is believed to be entirely reliable FORCE COMPUTERS makes no warranty of any kind with regard to the material in this document and assumes no responsibility for any errors which may appear in this document FORCE COMPUTERS reserves the right to make changes without not
25. unimplemented command UNSUP DEV unsupported flash device type 8 3 2 Erase Flash Memories Function number Syntax Parameters IMPORTANT Page 198 The function allows partial erasing of flash memory banks if the devices support page erasing mode The FGA 002 s timer is used for timing dur ing execution of the routine 37 22519 long util 37 flashbank offset length flashbank Base address of the flash memory bank that should be erased offset Relative byte offset within the flash bank see below length Length in bytes see below offset and length must exactly match the page boundaries of the flash devices For example If the system flash bank consists of four 28F008 1 M 8 bit devices in parallel with a page size of 64 Kbyte each the minimum size of one erasable region is 256 Kbyte 64 KB 4 If o set and 1ength are both set to 0 the whole flash bank is erased syseskcpu co EE 204077 June 1999 last documentation change with FGA Boot Vers 4 21 FGA Boot 8 3 3 A Returns CO Tn oO 4 W NY F Cc 11 12 FGA Boot Utility Functions OK OK no errors CLEAR ERROR flash device cannot be set to 0 for erasing INVAL PARMS invalid parameters ERASE ERROR flash device is not erasable WRITE ERROR programming error ILL WIDTH illegal flash bank width was detected UNKNOWN ID unknown flash device identifier CAPACITY device is too small WRITEPROTECT flash bank is write
26. 002 internal registers and the VMEbus address range for the message broadcast area see table 43 Address ranges related to AM codes on page 77 Before erasing or programming the system PROM ensure that you do not destroy the VMEPROM image The VMEPROM image resides in the first 512 Kbyte of the system PROM starting at address FF00 00004 g and ending at FF08 0000j Before erasing or programming the boot PROM ensure that you do not destroy the FORCE COMPUTERS FGA Boot image Before erasing or programming make a copy of the boot PROM device 1 in socket J70 The Ethernet LAN AM 79C965A decodes itself and uses only the first 32 bytes Accesses via this area are terminated by a bus error All other register address spaces are mirrored Always remember the following access rule for any reserved bits in any SYS68K CPU 60 register written as 0 read as undefined All registers must be written or read using the data path width docu mented for the respective register Always remember that in descriptions of data path widths byte refers to 8 bit word to 16 bit and long to 32 bit syseskcpu co RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware SYS68K CPU 60 Memory Map Table 10 SYS68K CPU 60 memory map n amp 2 amp E o9 pes 9 p 2 Access Address range Device gt 3O width 0000 000016 DRAM contributing to sh
27. 010 011 012 014 018 01A 01C 020 021 022 024 025 026 028 038 048 058 068 078 082 084 086 088 098 0A8 0AC 0B0 0BA 0B6 0B8 0B9 0BA 0BB 0BC 0BD 0BE Page 160 char bios char mail unsigned int rdkn unsigned int rdks char rdka char bflg char dflg int _f681 char sram int sparel ine fonty long _tics unsigned char _smon unsigned char _sday unsigned char _syrs 2 unsigned char _shrs unsigned char _smin unsigned char _ssec 2 char _patb 16 char _brkf 16 char _f8bt 16 char _utyp 16 char _urat 16 char _evtb 10 char _evto 2 char _evti 2 char _evts 2 char ev128 16 long _evtm 4 long _bclk ol c i i e oi c e e c har tltp har utcb nt _suim nt _usim har sptn har _utim har tpry har tskn har spare2 har tqux har tlck 2 input buffer wrap around mask f characters port 2 memory page size memory bitmap size number of map bytes file slot size TCB index map index event 41 event 42 Scheduled event TASK entry size bytes per
28. 1 M 8 bit devices in parallel with a page size of 64 Kbyte each the minimum size of one erasable region is 256 Kbyte 64 KB 4 devices R X E SYS68K CPU 60 Page 137 VMEPROM Commands VMEPROM Parameters flashbank Symbolic name or base address of the flash memory bank that should be erased The following symbolic names are supported BOOT FLASH first boot flash BOOT FLASH1 first boot flash BOOT FLASH2 second boot flash SYS FLASH system flash USER FLASH user flash flashoffset Optional relative byte offset within the flash bank length Optional length in bytes If flashoffset and length are not specified the whole bank will be erased Example FERASE Usage FERASE lt flashbank gt flashoffset length Parameter flashbank is the base address of the flash bank or one of the following defines BOOT FLASH1 BOOT FLASH2 SYS FLASH1 USER FLASH1 FERASE BOOT FLASH2 Erasing flash memory done 2 6 5 4 FGA Change Boot Setup for Gate Array Format FGA Some registers of the gate array can be defined by the user The contents of these registers are stored in the on board battery buffered SRAM in a short form The boot software for the gate array will take these values after reset to initialize the gate array The Fea command may be used to enter an inter active node for changing this boot table in the battery buffered SRAM The rca command will show the actual value stored in the ba
29. 32 respectively If the data bus width is set to 16 bit long accesses 32 bit will be trans lated into 2 word accesses each 16 bit by the VMEbus interface Example MEM Data bus width is set to 32 bits MEM 16 MEM Data bus width is set to 16 bits MEM 32 MEM Data bus width is set to 32 bits R X E SYS68K CPU 60 Page 143 VMEPROM Commands VMEPROM 6 5 11 RUNINRAM Run VMEPROM in RAM Format RUNINRAM destination address This command provides an easy way to copy the VMEPROM software from the system flash memory into the DRAM to run it there First the binary image of VMEPROM will be copied to the specified destina tion address then all absolute addresses of the image will be relocated Finally VMEPROM will completely be restarted at its new location Automatic copy It is possible to let VMEPROM automatically copy its image into RAM after reset After copying the image is located at the end of memory and VMEPROM runs there To enable automatic copy use the FGA Boot seTUP command to set the Application Flags to 0001 g see section 8 2 12 SETUP Change Initialization Values on page 193 Per default VMEPROM runs in the system PROM IMPORTANT VMEPROM can not use memory beyond its own base address If for ex ample it is located at address 0020 00004 VMEPROM can only use the memory range from 0000 000046to 0020 000016 Please see also the opposite command RUNINROM Example LT
30. AS 8000 00008000 ORI B 0 D0 MOVE L 123 D1 00008006 ORI B 0 D0 6 move 6 bytes back 00008000 MOVE L 123 D1 Ctrl A recall line MOVE L 123 D1 00008006 ORI B 0 D0 ADDI L 20 D1 0000800c ORI B 0 D0 leave assemler FORCE BOOT gt E SYS68K CPU 60 Page 183 Debugger Commands FGA Boot 8 2 2 BANNER Display Banner Again Format BANNER The BANNER command displays the same information as is displayed when starting the debugger This is useful to get the current settings after modifying values via the SLOT or VMEADDR command 8 2 3 CONT Continue with Calling Routine Format 8 2 4 DI Disassembler Format Page 184 CONT The cont command allows to leave the debugger after it was entered from a users application via BSR entry address stored at FFEO0 00304g or via an exception for setting a vector use the address stored at FFEO 00344 All registers will be restored before leaving the debugger via an RTS or RTE instruction Example FORCE BOOT CONT DI address DI address count The DI command causes the disassembler to be invoked and displays the mnemonic starting at the specified address If the count parameter is given the specified number of lines mnemonics will be displayed If count is omitted a full page is displayed on the terminal and the user is prompted to continue disassembly enter lt Return gt or to abort enter any ot
31. Boot provides a utility function to get the CPU board s Ethernet address see section 8 3 5 Get Ethernet Number on page 200 The Ethernet address can also be read directly from the ID ROM via the IC bus protocol be ginning at the ID ROM offset 324 see table 14 CIO1 port B data reg ister on page 42 A unique 48 bit Ethernet address has been assigned to your SYS68K CPU 60 00 80 42 0D xx xx The CPU board s Ethernet address consists of ageneral part indicating the FORCE COMPUTERS CPU board family it is belonging to 00 80 42 0D for SYS68K CPU 60 followed by the 4 digit CPU board s serial number xx xx The CPU board s serial number consists of the last 4 digits of the number printed below the product bar code on the VMEbus P1 connector The serial number is always taken from the CPU board which contains the Ethernet logic Features of the Compatibility with IEEE 802 3 Ethernet Ethernet Data rate of 10 Mbit per second interface 136 byte transmit and 128 byte receive data buffer between LAN and CPU bus thus improving overall performance and reducing the risk of network overruns or underruns DMA capability nterrupt generation A R X E SYS68K CPU 60 Page 97 Ethernet LAN AM 79C965A 3 21 1 Register Access Page 98 Initializing IMPORTANT Table 55 Normal operation Hardware In order to allow jumperless Ethernet implementations the AM 79C965A has a software implemented addr
32. FDCRPM SCSIDatal O G FDCHLOAD FDC EJECT SCSI Data 2 O Q FDC DSEL2 SCSI Data3 6 G FDC INDEX SCSI Data 4 Q 5 Q FDCDSELI SCSI Data 5 6 G FDC DSEL2 SCSI Data 6 Q G FDC DSELI SCSI Data 7 Q QG FDC MOTOR SCSIDPA O Q FDC DIREC GND Q 10 Q FDC STEPX GND Q FDC WDATA GND O Q FDC WGATE TERMPWR G FDC TRK00 GND O G FDC WPROT GND Q 15 Q FDCRDATA SCSI ATN O G FDC SDSEL GND Q FDC DCHG SCSIBSY O Q ne SCSI ACK Q Q ne SCSIRST 20 Q ne SCSI Data 8 SCSI MSG O Q SCSI Data 9 SCSI SEL G n c SCSI Data 10 SCSI CD Q ne SCSI Data 11 SCSI REQ O Q Serial RX _2 TX _2 SCSIIO O 25 Q nc n c G ne Serial RX _2 TX 2 G GND GND G Serial RX 2 TX 2 n c Q G Serial RX 1 TX 1 nc 30 Q GND GND O G ne Serial RX 1 TX 1 O 32 Q Serial RX I TX I IMPORTANT Serial 1 2 Note that the pins A30 and C31 must be connected to GND externally in case of the serial 1 RS 485 configuration the pins A26 and C26 must be connected to GND externally in case of the serial 2 RS 485 configuration A LE svsesk CPU c0 Page 27 z SYS68K IOBP 1 Installation 2 12 SYS68K IOBP 1 Page 28 NOTICE Figure 6 As a separate price list item FORCE COMPUTERS offers a SYS68K IOBP 1 I O panel which is plugged into the VM
33. Kbyte Socket 2 512 Kbyte 1 Mbyte e ON Socket 1 disabled Socket 2 from 0 1 Mbyte svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware Factory options IMPORTANT Boot sequence Table 35 A Boot PROM There are 3 device type factory options available see section 3 11 1 Boot PROM Address Map and Factory Options on page 66 e flash devices programmable at 12 V e flash devices programmable at 5 V or OTP EPROM devices For the available capacity factory options see table 36 Boot PROM ad dress map factory options and device types on page 66 Ensure that there is always a boot PROM device providing a working boot PROM program installed The 68060 CPU boots from the boot PROM after every power up or re set The boot PROM program boots up the 68060 CPU and initializes the FGA 002 register contents During booting the FGA 002 maps all ad dresses to the boot PROM with the exception of the addresses of FGA 002 internal registers and the local SRAM Boot PROM features Feature Value Data path width 8 bit wide Supported port size Byte word long Number of devices lor2 Default number of devices 1 default boot PROM is 1 Default capacity 128 Kbyte Default device type 28F010A 12 V flash memory Default device speed 100 ns Default address range FFE0 0000 6 FFEl FFFF g Forbidden function code on 111 FLXI bus
34. O Devices 0 000 cece ee eee 133 6 4 2 On Board Interrupt Sources 2 0 0 eects 134 6 4 3 Off Board Interrupt Sources llle 134 6 4 4 The On Board Real Time Clock 0 00 00 135 65 VMEPROM Commands ccc ccc ccc cece cece cece eee e eee n hn 135 6 5 1 ARB Set the Arbiter of the CPU Board 0 0 0 0 0 0c eee eee 136 6 5 2 CONFIG Search VMEbus for Hardware 0 00020 e eee 136 6 5 3 FERASE Erase Flash Memories 0 00 e cee 137 6 5 4 FGA Change Boot Setup for Gate Array 0 2 138 6 5 5 FLUSH Set Buffered Write Mode 0 000 cece eee 139 6 5 6 FMB FORCE Message Broadcast 140 6 5 7 FPROG Program Flash Memories 2 0 0 0 e eee ee eee eee 141 6 5 8 FUNCTIONAL Perform Functional Test 20 000000 142 6 5 9 INFO Information about the CPU Board 02 0000 eee 143 6 5 10 MEM Set Data Bus Width of the VMEbus 2 0000s 143 6 5 11 RUNINRAM Run VMEPROM in RAM 0000 c ee eee 144 6 5 12 RUNINROM Run VMEPROM in ROM 20 0002 eee eee 145 6 5 13 SELFTEST Perform On Board Selftest 0 00000 e eee 145 6 6 Installing a New Hard Disk Using FRMT and INIT eee eee eene 146 Appendix to VMEPROM remis eene hint nut mn nete cn hh lere thin Im hr n ate ce suds sce 151 7 4 Driver Installation e s seesi cesen a ccc cece cece cece hh hh hh nn 151 7
35. OFF see page 13 The bank selection depends on the number of installed memory banks The dual banks architecture implements an interleaved memory orga nization of the DRAM 4 consecutive bytes located in bank 1 the next 4 consecutive bytes in bank 2 etc The single bank architecture implements a non interleaved memory organization of the DRAM every 4 consecutive bytes located in bank 1 Cache Coherence and Snooping To maintain cache coherence in a multimaster system the 68060 CPU has the capability of snooping On a snooped external bus cycle the 68060 CPU invalidates the cache line that is hit Supplying dirty data and sinking dirty data is not supported by the 68060 CPU Snoop hits invali date the cache line in all cases also for alternate master read write cy cles The snooping protocol supported by the 68060 CPU requires that memo ry areas shared with any other bus master is marked as cacheable write through or cache inhibited syseskcpu co RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware IMPORTANT Unpredictable errors Wrong configuration of snoop window and VMEbus slave window caus es unpredictable errors DRAM cache coherence can only be guaranteed if the snoop window in the bridge configuration register of the RIALTO bus bridge see SNOOP 2 0 R W on page 51 is configured correct ly Access to mirrored DRAM locations causes inconsistencies betw
36. Page 185 Debugger Commands FGA Boot Parameters flashbank Symbolic name or base address of the flash memory bank that should be erased The following symbolic names are currently supported BOOT FLASH first boot flash BOOT FLASH1 first boot flash BOOT FLASH2 second boot flash SYS FLASH system flash USER FLASH user flash flashoffset Optional relative byte offset within the flash bank length Optional length in bytes If flashoffset and length are not specified the whole bank will be erased Example FORCE BOOT FERASE Usage FERASE lt flashbank gt lt flashoffset gt lt length gt Parameter lt flashbank gt is the base address of the flash bank or one of the following defines BOOT_FLASH1 BOOT_FLASH2 SYS FLASHI USER FLASHI FORCE BOOT FERASE BOOT FLASH1 Do not reprogram BOOT FLASH1 this would destroy the booter Device is write protected FORCE BOOT FERASE SYS FLASH 80000 40000 Erasing flash memory done FORCE BOOT gt _ 8 2 7 FPROG Program Flash Memories Format FPROG flashbank source FPROG flashbank source flashoffset FPROG flashbank source flashoffset length The FPROG command allows to program flash memory banks Format 1 of the command programs the whole flash memory bank with the data stored at the specified source address Format 2 additionally allows to specify a destination offset within the flash memory bank and programs all remaining sp
37. RSE locumentation change with SYSGBK CPU 60 PCB Rev 0 1 204077 June 1999 last di Please Note The circuit schematics section is an integral part of the SYS68K CPU 60 Technical Reference Manual P N 204077 Yet it is packaged separately to enable easy updating The circuit schematics section will always be shipped together with the Technical Reference Manual Please ws Insert the circuit schematics section P N 204075 now into the SYS68K CPU 60 Technical Reference Manual P N 204077 iS Remove this sheet syseskcpu co R LE Circuit Schematics 4 Circuit Schematics Copies of the SYS68K CPU 60 are found on the following pages syseskcpu co R RLE Please Note The data sheet section is an integral part of the SYS6SK CPU 60 Techni cal Reference Manual P N 204077 Yet it is packaged separately to en able easy updating The data sheet section will always be shipped together with the Technical Reference Manual Please D Insert the data sheet section P N 204076 now into the SYS68K CPU 60 Technical Reference Manual P N 204077 iS Remove this sheet syseskcpu co R LE 204077 June 1999 last documentation change with SYSGBK CPU 60 PCB Rev 0 1 Data Sheets 5 Data Sheets This is a list of all data sheets that are relevant for the SYS68K CPU 60 Copies of these data sheets are found on the following pages 1 CIO Z8536 2 FDC 37C65C 3 LAN AM 79C965A 4 RTC 72421 5 SCC AM 85C30 6 S
38. Referenced manuals separately available from FORCE COMPUTERS X Tab 1 History of manual publication leeeeeeeeee ne xi Tab 2 Fonts Notations and Conventions ssseeeeeeeeeee es xi Tab 3 Specification for the SYS68K CPU 60 board 20 0 eee eee 2 Tab 1 Ordering information for the SYS68K CPU 60 0 0 cee eee eee 6 Tab 2 Block diagram of the SYS68K CPU 60 0 0 0 ee eens 9 Fig 1 Location diagram of the SYS68K CPU 60 schematic 0 10 Fig 2 Swatch s ttigs oc Pan weather di taotake ee cee ieee Va oa EES a 11 Tab 3 Front panel feat res ise e med ee beer hee ne ee 15 Tab 4 Pinout of the front panel serial I O ports config for RS 232 19 Tab 5 Pinout of the front panel serial I O ports config for RS 422 sues 19 Tab 6 Pinout of the front panel serial I O ports config for RS 485 sues 20 Tab 7 15 pin AUI Ethernet connector 0 0 0 0 eee cece es 24 Tab 8 P2 connector pinout with serial I O config for RS 232 00 25 Fig 3 P2 connector pinout with serial I O config for RS 422 0 0 26 Fig 4 P2 connector pinout with serial I O config for RS 485 00 0 27 Fig 5 SYS68K IOBP 1 pin assignment for VME P2 2 0 eee ee eee 28 Fig 6 POST codes indicating boot status 2 0 0 eee eee eee eee 30 Tab 9 SYS68K CPU 60 block diagram 1 eee eee 35 Fig 7 SYS68K CPU 60 m
39. Rev 0 1 imentation ch 204077 June 1999 last docur Hardware VMEBUSTIMER 1 0 R W 00 01 10 11 DRAM VMEBUSTIMER 1 0 controls the WME bustimer timeout see section 3 17 5 VMEbus Timer on page 89 The VME bustimer is disabled timeout 82 us 10 for 25 MHz CPU bus frequency timeout 65 us 10 96 for 33 MHz CPU bus frequency timeout 164 us 10 for 25 MHz CPU bus frequency timeout 130 us 10 for 33 MHz CPU bus frequency timeout 328 us 10 for 25 MHz CPU bus frequency timeout 260 us 10 for 33 MHz CPU bus frequency 3 8 3 Memory Diagnostic Register The memory diagnostic register provides the monitoring of several status flags IMPORTANT A write access to MDR or a power up clears bit 3 0 in the MDR They are not cleared on a normal reset Table 27 Memory diagnostic register MDR FFF4 000B g Bit 7 6 5 4 3 2 1 0 SEL ENPAR SIBK WESYS WDIRO CPUBT BTF PERR Value 25M IN FLASH SEL25M SEL2 5M indicates the 68060 CPU speed 0 33 MHz 1 25 MHz ENPARIN ENPARIN indicates the setting of SW9 2 for DRAM parity check see ENPAR R W on page 54 When reading this bit the software should set the ENPAR bit accordingly FGA Boot conforms to this rule and en ables or disables DRAM parity check according to the sett
40. SET gt LE svsesk CPU c0 Page 169 z Benchmark Source Code MOVEQ L 10 D1 BSR S OVEQ L OVEQ L BSR S OVEQ L OVE W BSR S OVEQ L MOVEQ L 10 D1 BSR S OVEQ L OVEQ L BSR S OVEQ L OVE W BSR S SUBQ L BNE S RTS EDN2 SUB W BEQ S SUBO W BEQ S 010 BFTST DC W DC W SNE RTS 8020 BFSET DC W DC W SNE RTS 0030 BFTST DC W DC W SNE RTS EDN2DAT DC L PAGE BENCH 5 BIT 0x F xXx MOVE L LEA L 002 MOVE L MOVEO L BSR S SUBO L BNE S RTS Page 170 EDN2 1 D0 11 D1 EDN2 1 D0 123 D1 EDN2 3 D0 RESET EDN2 1 D0 11 D1 EDN2 1 D0 123 D1 EDN2 1 D4 8010 2 D0 020 1 D0 030 A0 D1 1 SE8D0 0841 D2 A0 D1 1 SEEDO 0841 D2 A0 D1 1 SE8D0 0841 D2 0 0 0 0 MATRIX TRANSPOSITION 100 000 TIMES TAKEN FROM EDN 08 08 85 100000 D4 EDN3DAT PC A0 7 D0 0 D1 EDN3 1 D4 8002 Appendix to VMEPROM svsesk ceu so RSE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 Appendix to VMEPROM EDN3 8010 8020 OVE ADD OVE BFEX BFEX BFIN BFIN ADD ADDO CMP BNE DBRA MOVEM RTS EDN3DAT DC xoxo xXx B DC B DC B DC B B B B BENCH 6 004 LEA BNE PROGRAM IS 008 010 BSR SUBO BNE RTS DC L PAGE BENCH 7 8010 z g E 8 gt X MOVE FMOV FM
41. Serial I O SCC AM 85C30 on page 89 These ports serve as console port for download and for data communication Interfaces on The following interfaces are available on the 3 row VMEbus P2 connec VMEbus P2 tor see section 2 11 VMEbus P2 Connector Pinout on page 24 connector serial port 1 and 2 see section 3 18 Serial I O SCC AM 85C30 on page 89 note however that serial port 2 is only available if the wide SCSI factory option is not installed the SCSI interface see section 3 19 SCSI 53C720SE on page 92 and the floppy interface see section 3 20 Floppy Disk FDC 37C65C on page 94 Factory options The following factory options are available Page 34 capacity of DRAM see section 3 8 DRAM on page 52 and DRAM on page 2 on board user SRAM with on board battery backup see section 3 9 User SRAM factory option on page 61 and User SRAM on page 2 capacity of system PROM see section 3 10 System PROM on page 62 and System PROM on page 2 capacity and type of boot PROM see section 3 11 Boot PROM on page 64 and Boot PROM on page 2 capacity of local SRAM see section 3 13 Local SRAM on page 69 and Local SRAM on page 3 capacity of user flash see section 3 12 User Flash on page 68 and User flash on page 3 wide fast SCSI instead of the standard SCSI interface see section 3 19 SCSI 53C720SE on page 92 not av
42. Some addressing modes allow omission of arguments These addressing modes can be entered by omitting the argument and typing the dividing character poc Examples CLR W 1 A0 D0 W 2 CLR W 1 A0 2 CLR W A0 A sign followed by the new address changes the address counter to this absolute address An disassembles the same location again A or return disassembles the next location A or sign followed by the number of bytes increases decreases the address counter A or ESC allows to exit the line assembler and returns control to the command interpreter Ctrl A copies the current disassembled opcode in the line buffer This allows editing the current mnemonic All immediate values addresses and offsets used within mnemonics are assumed to be entered in decimal Hex values have to be specified by a dollar sign In addition binary values can be entered by a preceding percent sign octal values by an at sign e The disassembler displays all values in hex representation The line assembler accepts also pseudo opcodes of the form DC B DC w and pc r to define constant data storage An ASCII pattern can be stored by using pc B with the format DC B text All characters after the will be interpreted as ASCII characters and stored in memory The disassembler displays all illegal or unknown opcodes as DC W Example FORCE BOOT
43. Use the DRAMINIT command to initialize the DRAM see DRAMINIT Initialize DRAM on page 185 The common debugger commands are described in the FORCE Gate Ar ray FGA 002 User s Manual Additional commands available for this version of the booter are de scribed in this section To get a short description of all commands enter FORCE BOOT gt cr The shell knows the following control characters for line editing ESC or CONTROL C Break current command line CONTROL A Recall previous command CONTROL B Go to begin of line CONTROL E Go to end of line CONTROL H Move cursor one character left CONTROLL Move cursor one character right CONTROL D Delete character under cursor DEL Delete character left from cursor CONTROL Delete from cursor until end of line CONTROL O Delete whole line CONTROL I Toggle between insert overwrite mode ENTER or RETURN Execute command line 8 2 1 AS Line Assembler Format Page 182 AS address The as command invokes the line assembler of FGA Boot It can assem ble and disassemble all 68020 30 40 mnemonics When the as command is invoked it displays the current address and disassembles the opcode at this location syseskcpu co EE 204077 June 1999 last documentation change with FGA Boot Vers 4 21 FGA Boot z g E 8 A N Debugger Commands After the prompt on the next line the user can enter one of the following 1 A valid 680x0 mnemonic
44. VMEADDR Change VMEbus Slave Address Format IMPORTANT A VMEADDR slave address VMEADDR slave address slave window The vMEADDR command allows modifying the VMEbus slave address without modifying any other settings VMEbus slave address A32 slave address VMEbus slave address A24 slave address A23 0 By means of the first format of the command the size of the VMEbus slave window is set as large as the local memory size of the board The second format allows to specify the size of the VMEbus slave win dow manually After executing this command the INIT command must be executed to re calculate the SRAM checksum and to update the FGA 002 registers and the snooping window size in the RIALTO bus bridge The BANNER com mand may be used to display the current settings Example The following example sets the VMEbus A32 slave address of the board to 8320 0000 and the window size to Mbyte It can now be accessed from 8320 000046 to 832F FFFF The A24 slave window will be set to 20 000044 and is also 1 Mbyte large Note that the A24 slave window must be enabled separately via SETUP S FORCE BOOT VMEADDR 83200000 100000 Use the INIT command to recalculate the SRAM checksum FORCE BOOT INIT FORCE BOOT R X E SYS68K CPU 60 Page 195 FGA Boot Utility Functions FGA Boot 8 3 FGA Boot Utility Functions FGA Boot provides utility functions which can be called from user appli c
45. and 3 see section 3 3 1 MEM 60 DRAM Capacity and CIO1 Timer 3 on page 41 and section 3 3 2 Flash VPP Floppy Disk Control and CIO1 Timer 2 on page 42 The peripheral clock of both CIO devices is connected to a 4 MHz source The interrupt request output of both CIO devices use LIRQ4 of the FGA 002 The interrupt vectors are supplied by the CIO devices CIOI has the higher interrupt priority in the daisy chain The CIO devices are accessible via the 8 bit local I O bus byte mode svsesk ceu so RSE 204077 June 1999 last documentation change with SYS68K CPU 60 PCB Rev 0 1 Hardware SYS68K CPU 60 Parameters and Timers CIO Z8536 Table 12 SYS68K CPU 60 parameters and timers register map and CIO loc CIO On board Address device location Register name FF80 0C00i 1 J35 CIOI port C data reg FF80 0C01jg CIOI port B data reg FF80 0C0246 CIOI port A data reg FF80 0C034 CIO1 ctrl and pointer reg see data sheet CIO Z8536 in section 5 FF80 0E0016 2 J34 CIO2 port C data reg FF80 0E01li CIO2 port B data reg FF80 0E0246 CIO2 port A data reg FF80 0E031 CIO2 ctrl and pointer reg see data sheet CIO Z8536 in section 5 3 3 1 MEM 60 DRAM Capacity and CIO1 Timer 3 Table 13 CIOI port C data register FF80 0C00 gG Bit 7 6 5 4 3 2 J 0 used as masking bits for write MC 2 0 T3IRQ accesses to bit 3
46. and the SERIAL 2 on P2 factory option are not available simultaneously SCSI Bus Termination According to the SCSI specification the interconnecting flat cable must be terminated at both ends Before connecting SCSI devices ensure correct SCSI bus termination If the CPU board is not located at either end of the cable the termi nation must be disabled If the CPU board is located at the cable s end the termination must be enabled On the SYS68K CPU 60 the termination of the SCSI bus is done by ac tive terminators with a disconnect feature This allows the outputs to be shut down to remove the terminator from the SCSI bus It also reduces the standby power The disconnect input of the terminators is controlled by SW11 1 and SW11 2 default OFF OFF wide and 8 bit SCSI see page 14 The power for the terminator of any SCSI device will be provided from the CPU board directly or from the SCSI bus itself If the termination power is not delivered from any other SCSI device it is delivered from the CPU board The TERMPWR terminator power supply from the CPU board is pro tected by a self resetting fuse 1A max and a diode in series as defined in the SCSI specification The on board terminators draw power from the SCSI bus TERMPWR sysesk cpu co RSE 204077 2 3 June 1999 Installation 2 9 Floppy Disk FDC Floppy Disk FDC Device FDC 37C65C Frequency 16 MHz Package 44 pin PLCC
47. ccc ccc ce cee cece cence hn 61 3 9 1 Backup Power for the User SRAM 0 0 eee eee nee 62 syseskcpu co RSE A 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 Contents System PROM 1 5 Ii eI er n er RR HERE EIE aie oe EEN 62 3 10 1 Device Types for the System PROM 0 0 0c eee eee 63 3 10 2 Address Map of the System PROM 0 0 0 eee ee eee eee eee 63 3 10 3 Reading and Programming the System PROM 000 5 64 Boot PROM 2 ccc cece ce cece cece hh hh hn 64 3 11 1 Boot PROM Address Map and Factory Options 2 005 66 3 11 2 Programming the Boot PROM 0 0c eee eee eee 67 User Flash ienei aise eect RU ERE ov sie oye 8H prs n RP un R ES EDIRES T Y 68 3 12 1 Programming the User Flash 0 cece eee eee 68 Local SRAM sue uesebeLoUneRUU DONC PU eis diese oss Wig the e s ERE CORRI CU aoe 69 3 13 1 Local SRAM Organization sese mes 69 3 13 2 Devices Types for the Local SRAM 0 0 0 cee eee eee eee 70 3 13 3 Backup Power for the Local SRAM 0 0 0 0 c eee eee eee eee 71 Real Time Clock RTC 72423 ccc ccc ccc cece cece ee c ee ee creer hn 71 3 14 1 RTC Registers Address Map 0 0 c eee cence eens 72 3 14 2 Reading from or Writing to the RTC 72423 0 eee eee eee 73 3 14 3 Backup Power for the RTC 72423 0 0 0 cece eee eee 74 VMEbus Interface 1 cece cece eee e cence ehh hh hh h
48. control the configuration of the memory controller Table 26 MCR memory configuration register FFF4 0008 6 Bit 15 14 13 12 11 10 9 5 4 2 1 0 reser WD ENWD RESET ENPAR reser VERS VMEBUS ved TIME OUT ved MEM TIMER CTRL 1 0 Value 4 2 WDTIME WDTIME defines the watchdog timeout period R W 0 default 40 ms 30 0 5 s 30 ENWD starts the watchdog timer if set to 1 This bit can only be set to 1 or read setting it to 0 is impossible A reset of the SYS68K CPU 60 clears this bit automatically Watchdog timer is disabled Watchdog timer has been started RESETOUT controls the generation of a reset If the RESETOUT bit in the memory configuration register is set to 1 a reset is generated Setting the RESETOUT bit has the same effect as a reset generated by the watch dog timer No action is taken Generates a reset ENPAR controls whether DRAM parity check is enabled see EN PARIN on page 55 DRAM parity check is disabled DRAM parity check is enabled VERSMEMCTRL indicates the version memory control 1 ENWD R W 0 1 RESETOUT R W 0 1 ENPAR R W 0 1 VERSMEMCTRL 4 2 RO Og 8 E 7g 8th revision of memory control 1st revision of memory control svsesk ceu so RSE ange with SYS6BK CPU 60 PCB
49. do not destroy the FORCE COMPUTERS FGA Boot image Before erasing or programming make a copy of the boot PROM device 1 in socket J70 After enabling programming there is 1 more step to be taken for program ming the boot PROM The step is automatically handled correctly by the software packaged with the SYS68K CPU 60 see section 6 5 3 FE R X E SYS68K CPU 60 Page 67 User Flash 3 12 User Flash Location Base address Device type factory options Table 37 Hardware RASE Erase Flash Memories on page 137 and section 6 5 7 FPROG Program Flash Memories on page 141 and by the assembly process The correct programming voltage Vpp must be applied to the flash devices making up the boot PROM Vpp is generated by the SYS68K CPU 60 and controlled via a register see table 14 CIOI port B data register on page 42 The Vpp generator is shared between the system PROM the user flash and the boot PROM The user flash is a user programmable flash device J31 FFC8 00001g There are 2 device type factory options available flash devices programmable at 12 V and flash devices programmable at 5 V The following factory options are available for the user flash using the device types listed or equivalent User flash factory options and device types Factory option Default configuration is the first option listed Device type Address range 1 28F020 256k 8 FFC8 000046 FFCB FFFF 16
50. k k k CK Ck Ck k k k k k k k k k k k k k k k Ck k k Kk k k kkk kk k k kkk k k VMEPROM variable area area 7 ROR K K KK KK I KK kk k k Kk Ck IKK Kk Ck k k k k k k k k CK k k Kk k k Kk k k Kk Ck Kk k kk k k kk kc ko kk IAA ok ke ke ke k k 470 char linebuf 82 command line buffer 4C2 char alinebuf 82 alternate line buffer 514 char cmdline 82 alternate cmdline for XGNP 566 int allargs gotargs argc save and count for XGNP zJ 56A int argc argument counter AA 56C char argv MAXARG pointer to arguments of the cmd line EJ 594 char odir idir I O redirection args from cmd line j 59Ct int iport oport I O port assignments kJ 5A0 char ladr holds pointer to line in mwb 5A4 LWORD offset base memory pointer a 5A8 int bpcnt num of defined breakpoints 4 5AA LWORD bpadr MAXBP breakpoint address 5D2 WORD bpinst MAXBP breakpoint instruction 5E6 char bpcmd MAXBP 11 breakpoint command A N CE SYS68K CPU 60 Page 163 z Task Control Block Definitions Appendix to VMEPROM 654 WORD bpocc MAXBP of times the breakpoint should be af skipped 668 WORD bpcocc MAXBP of times the breakpoint is already if skipped bay 67C LWORD bptadr temp breakpoint address xy 680 WORD bptinst temp breakpoint instruction EJ 682 WORD bptocc of times the temp b
51. manual Pages referring to the manual IOPI 2 User s Installation 24 SIO User s Manual 152 svsesk ceu so RSE 204077 June 1999 Using This Manual Publication History of the Manual Table 2 History of manual publication Edition Date Description 1 July 1996 First print 2 August 1996 Editorial Changes 2 1 July 1997 Extended NETLOAD and NETSAVE FGA Boot debugger commands Corrected FDC register map correct ed pinout of front panel serial I O port and corrected units for VME BUSTIMER bits memory configura tion register 2 2 January 1999 Switch settings for RS 485 correct ed RS 485 configuration described Fonts Notations and Conventions Table 3 Fonts Notations and Conventions Notation Description 0000 000016 0000g 0000 Typical notation for hexadecimal numbers digits are 0 through F e g used for addresses and offsets Note the dot marking the 4th to its right and 5th to its left digit Same for octal numbers digits are 0 through 7 Same for binary numbers digits are 0 and 1 Program Typical character format used for names values and the like that should be used typing literally the same word Also used for on screen output Variable Typical character format for words that represent a part of a command a programming statement or the like and that will be replaced by an ap
52. must be used for defining the following factors The physical structure of the drive i e number of heads number of cylinders drive select number etc The bad blocks of the Winchester drive The partitions to be used If this setup is done once for a particular drive the data is stored in the first sector of the Winchester and automatically loaded when the disk controller is installed in VMEPROM When viewing the VMEPROM banner the driver for the local SCSI controller is already installed This driver needs memory for hashing The storage for the hashing buffers is allocated at the end of memory A R X E SYS68K CPU 60 Page 157 S Record Formats Appendix to VMEPROM 7 2 S Record Formats S record types 8 types of S records have been defined to accommodate the needs of en coding transportation and decoding functions Table 69 Types of S record format modules and VMEPROM support Type Description SO The header record for each block of S records S1 A record containing code data and the 2 byte ad dress at which the code data is to reside S2 A record containing code data and the 3 byte ad dress at which the code data is to reside S3 A record containing code data and the 4 byte ad dress at which the code data is to reside S5 A record containing the number of S1 S2 and S3 not supported records transmitted in a particular block The count by VMEPROM appears in the address field There is
53. port 2 depending e OFF on SW10 1 SW12 2 and SW12 3 see C3 p SW10 1 SW12 3 OFF SW12 4 Configuration of serial port 1 depending OFF on SW10 2 SW12 1 and SW12 4 see SW10 2 syseskcpu co RSE Installation 2 5 Front Panel Front Panel The features of the front panel are described in the following table For a location diagram see figure 2 Location diagram of the SYS68K CPU 60 schematic on page 10 IMPORTANT Toggling the reset key and the abort key at the same time has a special function which is described in the boot software description of the FORCE Gate Array FGA 002 User s Manual Table 4 Front panel features Device Description RESET Mechanical reset key When enabled and toggled it instantaneously affects the CPU board by generating a reset Depending on SW9 3 the reset generates a VMEbus SYSRESET see SW9 3 on page 13 A reset of all on board I O devices and the CPU is performed when the reset key is pushed to the UP po sition RESET is held active until the key is back in the DOWN position but at least 200 ms guaranteed by a local timer Power fail below approximately 4 7 Volts and power up both lasting at minimum 200 ms to 300 ms also force a reset to start the CPU board For information on enabling the key see SW7 3 on page 12 ABORT Mechanical abort key When enabled and toggled it instantaneously affects the CPU board by generating an interru
54. protected NO VPP no programming voltage SELECT ERROR cannot select the specified flash bank UNIMP CMD unimplemented command UNSUP DEV unsupported flash device type Get System Values in SRAM Function number Syntax Parameter Returns This function sets a pointer to the base address of the system values stored in the SRAM It also returns the size of this structure of bytes 38 226156 long util 38 SYS VALUES pSysValues pSysValues Address of a pointer to structure svs VALUES This pointer will be set by the routine to that location where the system values start in SRAM typedef packed struct unsigned long startModule unsigned short sysFlags SYS_VALUES Size of structure in bytes R X E SYS68K CPU 60 Page 199 FGA Boot Utility Functions FGA Boot 8 3 4 Get Application Values in SRAM Function number Syntax Parameter Returns This function sets a pointer to the base address of the application values stored in the SRAM It also returns the size of this structure of bytes 39 2716 long util 39 APPL VALUES pApplValues pApplValues Address of a pointer to structure APPL VALUES This pointer will be set by the routine to that location where the application values start in SRAM typedef packed struct unsigned short applFlags unsigned long applValue APPL VALUES Size of structure in bytes 8 3 5 Get Ethernet Number Function number Sy
55. rFLASHsystem flash USER FLASHuser flash source Source address of the data to program flashoffset Optional relative byte offset within the flash bank If no offset is speci fied 0 is assumed length Optional length in bytes If no length is specified all the remaining space of the flash bank will be programmed Example Partly programming the second Boot Flash FPROG BOOT FLASH2 100000 0 1375 Programming flash memory O SRSTASTSSEHTHTSASTAHATATRTATESTAATATTTAHSHUHASESTASSS 100 Done 6 5 8 FUNCTIONAL Perform Functional Test Format FUNCTIONAL IMPORTANT This command is designed for FORCE COMPUTERS internal purposes only Page 142 svsesk cPU so R XLE Vers 2 85 mentation change with VMEPROM 32 204077 June 1999 last docur VMEPROM VMEPROM Commands 6 5 9 INFO Information about the CPU Board Format INFO INFO VME The first format is used to display information about the CPU board as documented in the VUEPROM Version 2 32 User s Manual Additional ly the Ethernet address is displayed The second format displays the current setting of the VMEbus A32 and A24 slave window 6 5 10 MEM Set Data Bus Width of the VMEbus Format A MEM MEM 16 MEM 32 This command displays or sets the data bus width of the CPU board on the VMEbus To display the current data bus width enter MEM without arguments To set the data bus width to 16 bits or 32 bits enter MEM 16 Or MEM
56. sector number of RAM disks address of bios rom mail array address ram disk 4 ram disk size ram disk address basic present flag directory flag 68000 68010 flag run module B SRAM reserved for expansion fine counter 32 bit counter month day year hours minutes seconds input port allocation table input break flags port flag bits port uart type port rate table 0 79 event table 80 95 output events 96 111 input events 112 127 system events task 128 events events 112 115 timers clock adjust constant task list pointer user tcb ptr supervisor interrupt mask user interrupt mask Spawn task no user task time task priority must be even current task number reserved task queue offset flag no task lock reschedule flags must be even Appendix to VMEPROM f aA rA E ep f f ans ih y ey RY f as xy x E xy a T x4 E f 4 Ey EA Ef xy x x i7 Ef j d xy kj kf x SYS68K CPU 60 KE 204077 June 1999 last documentation change with VM EPROM32 Vers 2 85 Appendix to VMEPROM System RAM Definitions 0C0O char e122 batch task 4 x 0C1 char _6123 spooler task y 0C2 char _e124 0C3 char e125 0C4 long _cksm system checksum 0C8 int _pnod pnet node x 0CA char bser 6 bus error vector ODO char iler 6 il
57. see section 3 3 4 On board DRAM Capacity and Auto matic A24 Expansion on page 44 additional hardware automatically translates the A24 access to an A32 access to the FGA 002 This means that the standard address modifier code from the VMEbus is automatical ly modified to extended address modifier to the FGA 002 Since during A24 accesses the address lines A31 24 of the VMEbus must not be used for address decoding these address lines are driven to the FGA 002 via an additional driver The value of the A31 24 bits are programmable see section 3 3 6 A24 to A32 Address Translation on page 45 The ad dress lines for the A31 24 bits must be programmed according to the actual A32 access address used by the FGA 002 R X E SYS68K CPU 60 Page 81 VMEbus Interface Programming the A232 access address Enabled modes Table 47 Example Hardware Suppose the DRAM access address for the VMEbus A32 slave win dow is programmed to Start address 1000 000046 End address 1040 000016 Then the CIO2 Port A register must be programmed to 1044 to allow A24 accesses see section Table 18 CIO2 port A data register on page 45 If an A24 master now accesses the address 00 500045 it reaches the same address as an A32 master accessing the address 1000 500046 For information on programming the A32 access address see the FGA 002 Gate Array User s Manual The snooping window must be set appropriately see sectio
58. sensed signals Bus error generation Bus error sensing Hardware The 32 data lines DO D31 are sensed on read cycles The size of the data transfer is defined by the SIZE output signals always driven by the 68060 CPU Cycles are acknowledged by the transfer acknowledge TA signal In case of bus operation a bus error will be generated if a device does not respond correctly A bus error is sensed by the CPU via the TEA signal If a bus error oc curs the current cycle is aborted illegal transfer or incorrect data and exception handling starts VMEbus transfers may also be aborted via TEA If TA and TEA are sensed simultaneously the CPU enters the retry bus operation sequence A retry happens whenever the CPU tries to access a device on the I O bus or the VMEbus and an external master accesses the shared RAM simultaneously 3 4 2 Instruction Set of the 68060 CPU For the 68060 CPU instruction set and for further information concerning programming refer to the 68060 User s Manual 3 4 3 Vector Table of the 68060 CPU Table 19 Page 46 This table lists all vectors defined and used by the 68060 CPU 68060 CPU exception vector assignments Vector Vector number s offset Hex Assignment 0 00016 Reset initial interrupt stack pointer 1 00416 Reset initial program counter 2 00816 Access fault bus error 3 00Cig Address error 4 01016 Illegal instruction 5 01416 Integer divide by zero 6 01816
59. supported All 7 VMEbus interrupt request IRQ signals are connected to the inter rupt handling logic on the FGA 002 e All 7 VMEbus IRQ signals can be separately enabled or disabled Every VMEbus interrupt request level can be mapped to cause an inter rupt to the processor on a different level For example a VMEbus interrupt request on level 2 IRQ2 can be mapped to cause an inter rupt request to the 68060 CPU on level 5 A single level bus arbiter together with several release functions is imple mented with all slot 1 system controller functions see section 3 17 VMEbus Slot 1 on page 86 e SYSRESET driver and receiver SYSCLK driver and IACK daisy chain driver see below In accordance with the VMEbus specification the CPU board includes an IACK daisy chain driver If the CPU board is plugged in slot 1 and con figured accordingly by SW6 1 and SW6 2 the board acts as IACK daisy chain driver Plugged in any other slot the board closes the IACKIN IACKOUT path R X E SYS68K CPU 60 Page 75 VMEbus Interface NOTICE A IOBP 1 Hardware Damaging SYS68K CPU 60 components On the backplane the jumper for IACKIN IACKOUT bypass must be re moved for proper operation This is not necessary on active backplanes For the connections to the SYS68K IOBP 1 I O panel see section 2 12 SYS68K IOBP 1 on page 28 3 15 1 Exception Signals SYSFAIL SYSRESET and ACFAIL SYSFAIL SYSRESET input SYSRES
60. task pri tm evl ev2 size pc tcb eom ports 0 0 64 1 7868 FF027876 00007000 00786000 1 1 0 0 0 RUNINRAM 200000 Copying program from FF000000 to 00200000 0024F181 Relocating program in new area Restarting VMEPROM CK Ck CK kk CK CK Ck Ck Ik CK CK CC IC CK CCS CK CC CK Kk Sk Kk Ck Kk Uk S A KK KG KKK KK KK Fl VMEPROM o SYS68K CPU 60 Version X YZ dd mm yy c FORCE Computers and Eyring Research Ck Ck CK Ck Ck CK CK Ck Ck Ck CK CK Ck CC CC CK CK CC CK Kk kk C KC kk S KK KG KKK ko ko ko LT task pri tm evl ev2 size pc tcb eom ports 0 0 64 1 1726 00227876 00007000 001B6800 1 1 0 0 0 svsesk ceu so R SLE Vers 2 85 ange with VMEPROM 32 mentation ch 204077 June 1999 last docur VMEPROM VMEPROM Commands 6 5 12 RUNINROM Run VMEPROM in ROM Format RUNINROM This command restarts VMEPROM in the system flash memory Example LT task pri tm evl ev2 size pc tcb eom ports 0 0 64 1 1726 00227876 00007000 00186800 1 1 0 0 0 RUNINROM Restarting VMEPROM in ROM KKKK kk CK CK Ck Ck Ck KC CK CK IC IC KOC CK CK CC CK Kk kk C Ck kk S KK KK KKK ko ko KK VMEPROM SYS68K CPU 60 Version X YZ dd mmm yy i c FORCE Computers and Eyring Research e CK CkCk Ck Ck Ck Ck Ck kk CC Ck Ck IC CK CC CK CK KC CK Kk kk C kk Uk S SK KK KU KKK KK KK LT task pri tm evl ev2 size pc tob eom ports 0 0 64 1 7868 FF027876 00007000 007B6000 1 1 0 0 0
61. the board is bolted on the VME rack and shielded by closed housing Damage of components caused by inappropriate floppy drive installation There are floppy disk drives that provide means to connect the floppy disk drive frame electrically with DC ground e g by inserting a jumper on the floppy disk drive Before installing a floppy disk drive always make sure that the floppy disk drive s frame is not electrically connected with DC ground Damaging SYS68K CPU 60 components On the backplane the jumper for IACKIN IACKOUT bypass must be re moved for proper operation This is not necessary on active backplanes R X E SYS68K CPU 60 Page 7 Installation Prerequisites and Requirements Installation 2 2 2 2 1 Page 8 CAUTION Maintenance of the CPU board The board is designed to be maintenance free However note that a Lith ium battery is installed on the board The battery provides a data retention of 7 years summing up all periods of actual battery use Therefore FORCE COMPUTERS assumes that there usually is no need to exchange the Lithium battery except for example in the case of long term spare part handling Observe the following safety notes ncorrect exchange of Lithium batteries can result in a hazardous explosion Exchange the battery before 7 years of actual battery use have elapsed Exchanging the battery always results in data loss of the devices which use the battery as power backup There
62. whether the 12V programming voltage Vpp for the flash W memory system PROM boot PROM and user flash is turned on 0 Vppis turned on 1 Vppis turned off F XXXXXX F_DCHGEN F_ADDIR F_PCVAL and F_DRV control the FDC37C65C W floppy disk drive interface for the signals related to F_DCHGEN F_PCVAL and F DRV see section 3 20 Floppy Disk FDC 37C65C on page 94 F_DRV DRY signal F PCVAL PCVAL signal F ADDIR F ADDIR controls the AUX DMA transfer direction 0 DMA write to FDC 1 DMA read from FDC F_DCHGEN DCHGEN signal T21RQ T2IRO controls the interrupt request output for timer 2 of CIOI The W 16 bit timer can generate interrupt requests at a software programmable Page 42 level Timer 2 can be linked with timer 1 to establish a 32 bit timer The corresponding interrupt request line is connected to the local IRQ 3 of the FGA 002 Additionally the timer 2 of CIOI can be programmed to generate an interrupt on the interrupt request line which is connected to the local IRQ 4 of the FGA 002 For information on the interpretation of the bit value of T2IRQ see data sheet CIO Z8536 in section 5 and the FORCE Gate Array FGA 002 User s Manual svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware SYS68K CPU 60 Parameters and Timers CIO Z8536 3 3 3 MODE x Rotary Switch Setting Rotary switches The MODE x rotary switch
63. write mode will be enabled or disabled When entering a question mark only a message will be dis played which indicates whether the buffered write mode is enabled or disabled A LE svsesk CPU c0 Page 139 z VMEPROM Commands VMEPROM Example FLUSH All modified buffers are flushed FLUSH ON Buffered write is enabled 6 5 6 FMB FORCE Message Broadcast Format Parameters Page 140 FMB slotlist FMB channel message FMB FMB channel The FMB command allows sending a byte message to individual slots in the backplane broadcasting to all boards and getting a pending message Format 1 is used to send a message slotlist is a list of slot numbers and is used to select the slots to which a mes sage is sent Slot numbers are separated by a sign a between two slot numbers defines a range of slot numbers Slot numbers can range from 0 to 21 0 causes the message to be sent to all slots FMB channel defines which FMB channel is used It can be 0 or 1 message is the byte message to be deposited into the FMB channel s Format 2 is used to get messages If no parameter is given one message of each FMB channel is fetched and displayed If FMB channel is speci fied only this channel is addressed and the message will be displayed For detailed information on the FORCE message broadcast see the FORCE Gate Array FGA 002 User s Manual svsesk ceu so WEE Vers 2
64. 0 e g if bit 4 Value is 1 bit 0 cannot be written C 2 0 C 2 0 indicate the capacity of the DRAM installed on the MEM 60 RO memory module see section 3 8 5 Reading the DRAM Capacity on page 57 T3IRQ T3IRO controls the interrupt request output for timer 3 of CIOI The W 16 bit timer can generate interrupt requests at a software programmable level the FORCE Gate Array FGA 002 User s Manual The corre sponding interrupt request line is connected to the local IRQ 2 of the FGA 002 Additionally the timer 3 of CIO1 can be programmed to gen erate an interrupt on the interrupt request line which is connected to the local IRQ 4 of the FGA 002 For information on the interpretation of the bit value of T3IRQ see data sheet CIO Z8536 in section 5 and the FORCE Gate Array FGA 002 User s Manual gt R X E SYS68K CPU 60 Page 41 3 32 SYS68K CPU 60 Parameters and Timers CIO Z8536 Hardware Flash Vpp Floppy Disk Control and CIO1 Timer 2 Table 14 CIOI port B data register FF80 0C01 Bit 7 6 5 4 3 2 1 0 ID SCL ID SDA FLVPP F_DCH F_ F_ FL T2IRQ Value GEN ADDIR PCVAL DRV ID SCL ID SCL controls the ID ROM SCL signal C bus see Ethernet node W address on page 97 ID_SDA ID_SDA controls and indicates the status of the ID ROM serial data sig R W nal C bus see Ethernet node address on page 97 FLVPP FLVPP controls
65. 0011F 00 80 42 03 88 88 Transmi PAC FORCE BOOT gt _ Transmi Transmi tting TFTP REQUEST ET 1 saved 00100100 0010011F 32 bytes LAN controller at address FEF80000 set to Ethernet 00 80 42 03 88 88 tting RARP REQUEST LAN controller at address FEF80000 set to Ethernet 00 80 42 03 88 88 tting RARP REQUEST Reception of RARP REPLY Page 192 svsesk ceu so WEE 204077 June 1999 last documentation change with FGA Boot Vers 4 21 FGA Boot Debugger Commands 8 2 12 SETUP Change Initialization Values A Format SETUP F or SETUP SETUP S The sETUP command is used to change SRAM parameters SETUP F and SETUP allow to modify the initialization values of the FGA 002 as de scribed in the FGA 002 User s Manual setup s allows to set up addi tional system and application values which are also stored in the battery buffered SRAM These values can be read by an application software via the utility interface For further information please see section 8 3 FGA Boot Utility Func tions on page 196 After modifying any entries the INIT command must be executed to re calculate the SRAM checksum and to validate the new values The following entries exist Name Default value Start Module at Address EFEFS EEEF e The user can specify the address of a program module here A module must provide a SSP stack pointer at offset 0 and a PC program counter at
66. 1 1 VMEbus Memory du RR Reg un RE due Re dee ee e 151 7 1 2 SYS68K S1O 1 2 22 b pibe bt babe etu t bed oe dedi 152 7 1 3 SXS68K ISIOS 1 2 meserna aa ecules Boba e ene E e n E Reo RU e rede 153 7 1 4 SYS68K WFC 1 Disk Controller 0 0 0 0 00 155 7 1 5 SYS68K ISCSI 1 Disk Controller 0 0 0 0 0c eee 156 7 1 6 Local SCST Controller eri uw ya xAENIqER S Ved ees Sa ew eae ER 157 7 2 S Record Formats ccc ccc cece cece cece eee e ee ee hh hh hh 158 7 3 System RAM Detinitions 4 seco Heese pi e ESTEE EE Pe oe te 159 R X E SYS68K CPU 60 Page v Contents 7 4 7 5 7 6 7 7 7 8 8 3 Page vi Task Control Block Definitions 0 0 ccc ccc cece eee cece nn 162 Interrupt Vector Table of VMEPROM 00 c cece ccc ecw cence ne nnn 165 Benchmark Source Code ccc cece c cece cece cece ee ee cece ee ee scene 168 Modifying Special Locations in ROM cece wee cece cece eee nnn 174 Binding Applications to VMEPROM cc ccc c cece hh hh nnn 177 7 8 1 Using External Memory 0 0 0 0 0 cece 177 7 8 2 Using System Flash Memory 00 cece eects 177 Boot iei cssatenitize sin soris fette terit eth aea e B ee e ares E losen Sne S ROA 179 Boot Sequence sorrara trpa na XR Eri Re rn oie eis le ENE e nage 179 Debugger Commands 0 ccc ccc ccc cece cece ec ence reece eee hr 182 8 2 1 AS Line Assembler esc coe ce et hate ook ARCH RR s 182 8 2 2 BANNER Display Banner
67. 12 V flash memory 2 28F010 128k 8 FFC8 000046 FFC9 FFFF 16 12 V flash memory 3 29F040 512k 8 FEECS 000015 FECE FEFF 16 5V flash memory 3 12 1 Programming the User Flash Page 68 Writing to the user flash is only enabled when SW10 4 is set appropriate ly OFF writing enabled default OFF see page 12 After enabling programming there is 1 more step to be taken for program ming the user flash The step is automatically handled correctly by the svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware Local SRAM software packaged with the SYS68K CPU 60 see section 6 5 3 FE RASE Erase Flash Memories on page 137 and section 6 5 7 FPROG Program Flash Memories on page 141 and by the assembly process The correct programming voltage Vpp must be applied to the flash devices making up the boot PROM Vpp is generated by the SYS68K CPU 60 and controlled via a register see table 14 CIOI port B data register on page 42 The V pp generator is shared between the system PROM the user flash and the boot PROM 3 13 Local SRAM Location J51 Base address FFC0O 0000 6 Backup 2 backup options are available to provide the current for the local SRAM standby mode see section 3 13 3 Backup Power for the Local SRAM on page 71 Table 38 Local SRAM features Feature Value Data path width Byte Supported port size
68. 16 BADR 15 8 BADR 7 0 416 MCNT 11 8 MCNT 7 0 616 BCNT 11 8 BCNT 7 0 IMPORTANT In 16 bit mode the 32 bit address BADR is built from CSR2 IADR 31 24 Page 100 syseskcpu co WEE 204077 June 1999 last documentation change with SYSGBK CPU 60 PCB Rev 0 1 Hardware Reset Generation 3 22 Reset Generation Voltage sensor unit Reset key Watchdog timer RESETOUT in MCR reset call reset instruction A The reset effects all on board modules and chips When resetting the SYS68K CPU 60 an automatic self test routine checks the functional groups of the board There are 7 sources which may initiate the reset 1 Voltage sensor unit The CPU board is reset as long as the supply volt age is below 4 75 V and above 3 V this is also true during power up After exceeding the threshold the reset timer will assert the RESET signal for approximately 200 ms The reset timer will also be triggered if the voltage has dropped below 4 75 V 2 Front panel reset key It triggers the reset timer to generate a reset see RESET on page 15 3 Watchdog timer If the reset is generated by the watchdog timer the WDIRQ bit in the MDR is set to 1 see section 3 5 Watchdog Timer on page 48 The watchdog reset is a pseudo power up 4 RESETOUT bit in the memory configuration register If the RESETOUT bit in the memory configuration register is set to 1 a reset is generated see table 26 MCR memo
69. 2 PSEUDO DMA 1K BYTES 50 000 TIMES MOVE L 50000 D2 DO 50000 TRANSFERS 8001 MOVE W SFF D3 EACH IS 1K BYTES LEA L 010 PC Al Al POINTS TO SOURCE AND DESTINATION 8002 MOVE L A1 Al DBRA D3 002 SUBQ L 1 D2 BNE S 001 RTS NOP 010 NOP PAGE Page 168 svsesk ceu so RSE ange with VMEPROM 32 Vers 2 85 E E Appendix to VMEPROM Benchmark Source Code BENCH 3 SUBSTRING CHARACTER SEARCH 100 000 TIMES TAKEN FROM EDN 08 08 85 F 0x MOVE L 100000 D4 8002 MOVE L 15 D0 MOVE L 120 D1 LEA L EDN1DAT PC A1 LEA L EDN1DAT1 PC A0 BSR S EDNl SUBQ L 1 D4 BNE S 002 RTS e BEGIN EDN BENCH 41 seeeeee EDN1 MOVEM L D3 D4 A2 A3 A7 SUB W DO D1 MOVE W D1 D2 SUBQ W 2 DO MOVE B A0 D3 e010 CMP B Al D3 8012 DBEQ D1 8010 BNE S 8090 MOVE L A0 A2 MOVE L A1 A3 MOVE W D0 D4 BMI S 8030 0020 CMP B A2 t A3 DBNE D4 0020 BNE S 8012 8030 SUB W D1 D2 8032 MOVEM L A7 D3 D4 A2 A3 RTS 8090 MOVEQ L 1 D2 BRA S 032 END EDN BENCH 1 KKKKKKK EDNIDAT DC B 000000000000000000000000000000 DC B 000000000000000000000000000000 EDNIDAT1 DC B HERE IS A MATCH000000000000000 PAGE BENCH 44 BIT TEST SET RESET 100 000 TIMES TAKEN FROM EDN 08 08 85 OVE L 100000 D4 LEA L EDN2DAT PC A0 8010 OVEQ L 1 D0 TEST OVEQ L 10 D1 BSR S EDN2 OVEQ L 1 D0 OVEQ L 11 D1 BSR S EDN2 OVEQ L 1 D0 OVE W 123 D1 BSR S EDN2 OVEQ L 42 D0
70. 2 000 5 58 Default DRAM access address ranges from the 68060 CPU 59 User SRAM featutes clou ue eR ell uy eb e ERE RE NERO 61 System PROM features ccc ce Sok eed Oe ER Rx d ERR erga 62 System PROM devicetypes lese 63 System PROM address map 1 1 0 ee eee e 63 Boot PROM features 1 0 0 ec m mh 65 Boot PROM address map factory options and device types 66 User flash factory options and device types 0 0 0 e eee eee eee 68 Local SRAM features i sce bises hse ede dnbie Uds dundee Paus 69 Local SRAM factory options and device types 0 0 0 0 0c eee ee 70 RTC 72423 teatutes i Gh cata eed at Aa NUMEN MU eS Ma 71 RTC registers address map 72 Address modifier AM ranges A32 A24 A16 llle eee 77 Address ranges related to AM codes 0 0 0 ccc eee cece eee 77 Bus widths related to address ranges VMEbus master interface 78 VMEbus master transfer cycles defined for D32 data bus width 79 VMEbus master transfer cycles defined for D16 data bus width 79 VMEbus slave AM codes 0 0 0 0 eee eee eee enn 82 Valid configurations for VMEbus release modes 0 0 00000 84 Slot 1 status register RO 2 0 ene eens 88 Serial I O channel register map and hybrid locations 90 Bit 7 of the WRS register eieae e taau eee eens 90 SCSI 53C720SE GPCNTL register 0 2 eee eee 91 SCSI 53C720SE GPREG reg
71. 2 actions A X E SYS68K CPU 60 Page 131 Memory Usage of VMEPROM 6 3 Memory Usage of VMEPROM 6 3 1 Default Memory Usage of VMEPROM VMEPROM By default VMEPROM uses the following memory assignment for the CPU board Table 62 Main memory layout Start address End address Type 0000 000016 0000 03FFi Vector table 0000 040016 0000 0FFF g System configuration data 0000 10001g 0000 5FFFig SYRAM 0000 600016 0000 6FFFig VMEPROM internal use 0000 700016 0000 7FFF16 Task control block 0 0000 8000 User memory of task 0 s hiedgurec T WPA best Mail array Ncc RAM disk optional eet nn End of local memory Hashing buffers for disk I O IMPORTANT The size of the first task cannot be extended beyond the highest on board memory address If more memory is available on VMEbus it can only be used for data storage but not for tasking memory 6 3 2 Default ROM Use of VMEPROM The following table shows the use of the system flash memory including VMEPROM Note that only the first 512 Kbyte will be used by VME PROM the remaining space is available for user applications For detailed information about user alterable locations see section 7 7 Modifying Special Locations in ROM on page 174 and section 7 8 Binding Applications to VMEPROM on page 177 Page 132 svsesk ceu so RSE 204077 June 1999 last documentation change with VMEPROM 32 Vers 2 85
72. 32 RS 422 and RS 485 hybrid modules the FH 002 FH 003 FH 422T and FH 007 For each serial I O channel one of those 21 pin single in line SIL hybrids is installed on board The location of the hybrid related to a serial I O chan nel is listed in the following table which also shows the serial I O register map R X E SYS68K CPU 60 Page 89 Serial I O SCC AM 85C30 Table 50 Serial I O configuration connectors and pinouts Hardware Serial I O channel register map and hybrid locations On board Serial I O hybrid Address channel location Register name FF80 202016 1 J21 SCC channel A control reg FF80 20214g SCC channel A data reg FF80 2000 16 2 J22 SCC channel B control reg FF80 2001 g SCC channel B data reg For the correct configuration of the serial channels the connectors which are available and the connectors pinout see section 2 7 Serial I O Ports SCC on page 17 and section 2 12 SYS68K IOBP 1 on page 28 3 18 1 RS 485 Configuration FH 007 RE signal Table 51 DE signal Page 90 For the RS 485 configuration the FORCE COMPUTERS FH 007 hybrid module must be used It provides 2 enable signals the RE signal on pin 14 for the receiver and the DE signal on pin 16 for the transmitter which must be controlled by the serial driver of an operating system The RE signal on pin 14 is connected to the DTR signal of the SCC and can be controlled by bit 7 of
73. 5 68060 CPU rr REOR EU Y ERNST EERNEYNESFESY WESCE ER EREEM S ES 45 3 4 1 Hardware Interface of the 68060 CPU 0 0 eee eee eee 45 3 4 2 Instruction Set of the 68060 CPU 0 eee eens 46 3 4 3 Vector Table of the 68060 CPU 0 2 eee nee 46 Watchdoe Time 4 I RII ERG I RR ee RU RES EP REF RE 48 3 5 1 Watchdog Operation cao aei aiei EEEE ne eens 48 3 5 2 Watchdog Register Map 1 0 cece eee eee eee 49 RIALTO Bus Bridge cele eked kee ee a we ie 50 3 6 1 R gister Seto vcsctu tats cigunts cide ts oda EECHENIBRG unge fans 50 3 6 2 Bridge Configuration Register 2 02 cece eee eee ee nee 50 FGA 002 Gate Array ve Ens erf t Rer AREK Pe gee Oe Of 51 DRAM iE 3 5 606 8 8 BS Hie NENG Y PESOS SFO ELEG SS PEOR EE S E 52 3 8 1 Register Sets snc sern seo ovate eh bp er ade ee ake niet aae 53 3 8 2 Memory Configuration Register leen 54 3 8 3 Memory Diagnostic Register 55 3 8 4 DRAM Performance 1 0 0 0 ccc ehh m 56 3 8 5 Reading the DRAM Capacity sse 57 3 8 6 DRAM Organization seeeeeee e e eens 57 3 8 7 Cache Coherence and Snooping 0 0 cee eee eee eee eee 58 3 8 8 DRAM Access from the 68060 CPU 0 2 eee nee 59 3 8 9 DRAM Access via the VMEbus 0 000 cece ee 60 3 8 10 DRAM Access from the Ethernet Controller 0 000005 61 3 8 11 DRAM Access from the SCSI Controller 00 eee eee 61 User SRAM factory option 0 0 ccc ccc
74. 5408L FFCO 000046 FFC7 FFFF 16 512k 8 syseskceu co RSE 204077 June 1999 last documentation change with SYS68K CPU 60 PCB Rev 0 1 Hardware Real Time Clock RTC 72423 3 13 3 Backup Power for the Local SRAM 3 14 A Normal operation Power fail VME standby Backup battery Automatic switch over The local SRAM is powered by the backup power circuitry During normal operation the backup power circuitry connects the 5 V power supply to the local SRAM When the 5 V supply fails backup power may be supplied from alter nate sources They are only available with SW5 3 set appropriately ON RTC local and user SRAM default OFF see page 11 If SW5 3 is set appropriately the following two alternate sources are switch selectable from the VMEbus 5VSTDBY line selectable by SW5 1 ON enabled default OFF see page 11 from the backup battery selectable by SW5 2 ON enabled default OFF see page 11 The switch over in case of power fail is fully automatic whichever volt age is higher will be available to the local SRAM Real Time Clock RTC 72423 Backup Data sheet Table 40 The on board RTC 72423 maintains accurate time and date based on its own crystal 2 backup options are available to provide the current for the RTC 72423 even during power failures see section 3 14 3 Backup Power for the RTC 72423 on page 74 See data sheet
75. 6BK CPU 60 PCB Rev 0 1 Hardware A FGA 002 supplied interrupt vectors SYS68K CPU 60 Interrupt Map Interrupt vectors supplied by the FGA 002 all share a basic vector and a fixed vector offset for each source The basic vector is software program mable The table below shows the local interrupt requests of the FGA 002 pro grammed for the local devices For information on the vector offset and on programming the IRQ level refer to the FORCE Gate Array FGA 002 User s Manual Table 11 SYS68K CPU 60 interrupt map Vector supplied Function Device FGA 002IRQ IRQ level by Watchdog timer Memory control LIRQO SW prog FGA 002 Floppy disk FDC 37C65C LIRQ1 SW prog FGA 002 Timer 3 CIO Z8536 CIO1 LIRQ2 SW prog FGA 002 Timer 2 CIO Z8536 CIO1 LIRQ3 SW prog FGA 002 CPU board CIO Z8536 CIO1 and LIRQ4 SW prog CIO or parameters CIO2 FGA 002 SCC SCC AM 85C30 LIRQ5 SW prog SCC or FGA 002 SCSI SCSI 53C720SE LIRQ6 SW prog FGA 002 Ethernet LAN AM 79C965A LIRQ7 SW prog FGA 002 R X E SYS68K CPU 60 Page 39 SYS68K CPU 60 Parameters and Timers CIO Z8536 Parameters timers DRAM ID ROM MODE x A24 to A32 board ID DIAG CIO counters and timers Clock IRQ CIO access Hardware 3 3 SYS68K CPU 60 Parameters and Timers CIO Z8536 The configuration and status information for several SYS68K CPU 60 parameters and s
76. 7 7 1 7 1 1 z g E 8 A N Driver Installation Appendix to VMEPROM Driver Installation INSTALL command IMPORTANT Current configuration VMEbus Memory This appendix summarizes the changes to be made to the default setup of additional VMEbus boards so that they are VMEPROM compatible Drivers described in the following sub sections are available in ROM but not all are installed However drivers for all on board devices are auto matically installed To install a driver use the INSTALL command Software version dependent addresses The addresses given in the examples of this section are only example UART and Disk Driver addresses They may vary across software ver sions To view the current configuration issue the insta11 command as shown in the following example INSTALL THE FOLLOWING UARTS AND DISK DRIVER ARE ALREADY IN EPROM DISK DRIVER FORCE IBC ME ADDR FF029500 DISK DRIVER FORCE ISCSI 1 ADDR FF029700 DISK DRIVER FORCE SCSI CPU 60 ADDR FF02A300 DISK DRIVER FORCE WFC 1 ADDR S FF02BAO00 UART DRIVER FORCE IBC ME ADDR S FF02E200 UART DRIVER FORCE ISIO 1 2 ADDR FFO2E400 UART DRIVER FORCE CPU 60 28530 ADDR S FF02E900 UART DRIVER FORCE SIO 1 2 ADDR FFO2EE00 In general every FORCE memory board can be used together with VME PROM In order to use a memory board within the tasking memory of VME PROM the base address must be set
77. 85 locumentation change with VMEPROM 32 204077 June 1999 last d VMEPROM VMEPROM Commands Example FMB FMB channel 0 is empty FMB channel 1 is empty FMB 1 21 0 EF FMB 1 21 1 10100001 FMB FMB channel 0 SEF FMB channel 1 A1 FMB 1 21 1 77 FMB FMB channel 0 is empty FMB channel 1 77 FMB 1 2 5 7 19 21 0 1 FMB FMB channel 0 01 FMB channel 1 is empty 2 6 5 7 FPROG Program Flash Memories Format FPROG flashbank source FPROG flashbank source flashoffset FPROG flashbank source flashoffset length The FPROG command allows programming flash memory banks Format 1 of the command programs the whole flash memory bank with the data stored at the specified source address Format 2 additionally allows specifying a destination offset within the flash memory bank and programs all the remaining space from offset to end of flash bank Format 3 of the command also specifies the number of bytes to program IMPORTANT If the flash memory is not empty it must be erased before reprogramming it see section 6 5 3 FERASE Erase Flash Memories on page 137 A LE svsesk CPU c0 Page 141 z VMEPROM Commands VMEPROM Parameters flashbank Symbolic name or base address of the flash memory bank that should be programmed The following symbolic names are currently support ed BOOT_FLASH first boot flash BOOT_FLASHifirst boot flash BOOT FLASH2second boot flash svs
78. A X E SYS68K CPU 60 Page 47 Watchdog Timer Hardware 3 5 Watchdog Timer IRQ IMPORTANT There is a watchdog timer installed on the SYS68K CPU 60 to monitor the 68060 CPU activity The watchdog timer is able toissue an interrupt to the 68060 CPU and to generate a pseudo power up pulse whereby the CPU board is reset but in contrast to a normal power up the on board LCAs are not loaded from the serail PROM One timeout is specified for both actions The watchdog interrupt is the LIRQO input of the FGA 002 This input must be configured to be sensitive on a falling edge signal e and to generate level 7 interrupts to the 68060 CPU 3 5 1 Watchdog Operation Trigger event Timeout Starting the watchdog NMI generation Page 48 The SYS68K CPU 60 watchdog timer monitors the 68060 CPU activity by awaiting a trigger event from the 68060 CPU within the watchdog timer s timeout period The watchdog timer is triggered by setting the RESTART bit in the watchdog retrigger register to 0 see table 21 Watchdog retrigger regis ter WDR on page 49 The watchdog timeout is selectable by setting the WDTIME bit in the memory configuration register see table 26 MCR memory configura tion register on page 54 either 40 ms 30 96 or 0 5 s 30 96 The watchdog timer is started by setting the ENWD bit in the memory con figuration register see table 26 MCR memory configuration register o
79. AM 79C9654 regards a bus error acknowledge as normal acknowledge Therefore it does not recognize any failures e g in case of VMEbus transfer errors However if a transfer which has been initiated by the AM 79C9654 is terminated by a buserror the VL adaption enters an exception handling which disables busmastership for the AM 79C965A during the next arbi tration cycle If the AM 79C965A requests busmastership during that cy cle it will not get the bus and therefore will generate a timeout and an interrupt and will set the memory error bit within the CSRO register svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware Ethernet LAN AM 79C965A IMPORTANT The memory error always occurs during the busmastership following the failing busmastership cycle Bus error After toggeling the LANDEC bit within the BCR register in the RIALTO handling cont bus bridge the VL adaption leaves the exception handling IMPORTANT e For proper operation of the AM 79C9654A only use the DRAM address space as memory area For correct LAN arbitration set the FGA 002 bus error timeout to 64 us or less controlled by VMETIMEOUT in the CTL16 register of the FGA 002 Ethernet node The unique Ethernet node address is permanently stored on board It can address be displayed by using the VMEPROM INFO command see section 6 5 9 INFO Information about the CPU Board on page 143 FGA
80. AN AM 79C965A Hardware 3 21 Ethernet LAN AM 79C965A IEEE 802 3 compliant Figure 9 IMPORTANT LAN connector and pinout IRQ Bus error handling Page 96 The CPU board offers a Local Area Network LAN interface based on control logic and the integrated local area communications controller AM 79C965A see data sheet LAN AM 79C965A in section 5 but be aware of the IMPORTANT note concerning the 16 bit mode on page 99 The internal Manchester Encoder Decoder of the AM79C965 is compati ble with the IEEE 802 3 specification The figure below shows a simplified block diagram of the Ethernet inter face Block diagram of the Ethernet interface 68060 AM CPU 79C965A AUI TRANSFORMER CPU bus Set the BSWP bit byte swap bit in the AM 79C965A CSR3 register to 1 to ensure correct data transfer the AM 79C9654 is designed for little and big Endian byte ordering Set the INTLEVEL bit in the BCR2 register to 0 to enable correct interrupt generation For the front panel connector and its pinouts see section 2 5 Front Pan el on page 15 and section 2 10 Ethernet LAN on page 23 The AM 79C96SA is able to interrupt the 68060 CPU on a FGA 002 pro grammable level It is connected to IRQ 7 of the FGA 002 and must be programmed as level sensitive and high active As there is no bus error signalling on the VESA local bus a CPU bus buserror has to be handled in a different way The
81. Again 0 0 0 0 cece ee eee 184 8 2 3 CONT Continue with Calling Routine 0 0 0 0 0008 184 8 2 4 DI Disassembler yne ie cg ican eas cas E RR lease era nda hs 184 8 2 5 DRAMINIT Initialize DRAM 0 0 0 ee eee 185 8 2 6 FERASE Erase Flash Memories 0 0 00 cece cece eee ene 185 8 2 7 FPROG Program Flash Memories 2 0 00sec eee eee ees 186 8 2 8 GO Go to Subroutine 2 eee ene 188 8 2 9 LO Load S Records to Memory 0 0c eee eee eee eee 188 8 2 10 NETLOAD Load File via Network to Memory 04 190 8 2 11 NETSAVE Save Data via Network to File 0000 00005 191 8 2 12 SETUP Change Initialization Values 0 0 0 0 eee 193 8 22 13 SLOT Change Slot Number and VMEbus Slave Address 194 8 2 14 VMEADDR Change VMEbus Slave Address sellers 195 FGA Boot Utility Functions eeeeeeeeeeeeeeee ehh hh han 196 8 3 1 Extended Flash Memory Programming 0 0 00 e eee eee ee 197 8 3 2 Erase Flash Memories 00 ce cece cece eee hh hm 198 8 3 3 Get System Values in SRAM seeeeeesee ee 199 8 3 4 Get Application Values in SRAM 0 0 eee ee eee 200 8 3 5 Get Ethernet Number ic 00a ccc cheese ian E EE Re ERE 200 8 3 6 Get Memory Limits 22224 duke idee d cam dme v Rr nudi 201 svsesk ceu so RSE Tables and Figures List of Tables and Figures Page Tab Fig
82. Byte word long Number of devices 1 Default number of devices 1 Default capacity 128 Kbyte Default device type MS5M 510008L Default device speed 100 ns Default address range FFCO 00004 FFC1L FFFF1 Forbidden function code on 111 FLXI bus 3 13 1 Local SRAM Organization The local SRAM memory is connected to the I O bus providing a byte wide port Consecutive bytes seen by the 68060 CPU are handled in the same manner as consecutive bytes for the local SRAM A R X CE SYS68K CPU 60 Page 69 Local SRAM Hardware Byte word and long word accesses are managed by the dynamic bus siz ing of the RIALTO bus bridge see section 3 6 RIALTO Bus Bridge on page 50 Data can be read from and written to any address odd and even in byte word or long word format Example of data transfers All combinations of the instructions listed below are allowed MOVE X SFFCO 000Y DO X B Byte 1 Byte X W Word 2 Bytes X L Long Word 4 Bytes KKK OK l w Neo 3 13 2 Devices Types for the Local SRAM Page 70 Table 39 The following low power device types marked with L or LL are sup ported as a factory option Local SRAM factory options and device types Factory option Default configuration is the first option listed Device type Address range 1 M5M 510008L FFC0 000046 FFC1 FFFF g 128k 8 2 M5MS5256L FFCO 000046 FFCO 7FFF 16 32k 8 3 M5MS
83. C data register on page 41 respectively Table 28 DRAM capacity encoding at CIOx port C data registers DRAM capacity on board when reading MC 2 0 from CIO2 port C data register e on MEM 60 when reading MC 2 0 from CIO1 MC 2 0 port C data register 0 0 0 32 Mbyte 0 0 1 16 Mbyte 0 1 0 8 Mbyte 0 1 1 4 Mbyte 1 0 0 0 Mbyte no memory module plugged resp 1 0 1 256 Mbyte 1 1 0 128 Mbyte 1 1 1 64 Mbyte 3 8 6 DRAM Organization MEM 60 and on The DRAM is mounted on board or on the MEM 60 memory module board memory The on board DRAM is arranged in 1 or 2 memory banks depending on banks the available overall memory capacity Each memory bank is 36 bit wide 32 data bits plus 4 parity bits A R X E SYS68K CPU 60 Page 57 DRAM 3 8 7 Page 58 Table 29 IMPORTANT Bank selection interleaved non interleaved Hardware DRAM device types and number of used banks a ates Total No of Product Type Capacity capacity banks CPU 60D 4 1M 4 FPM 9 Mbit 4 4 Mbyte 1 CPU 60D 8 1M 4 FPM 18 1 Mbit 4 8 Mbyte 2 CPU 60D 16 4M 4 FPM 9 4Mbit 4 16 Mbyte 1 CPU 60D 32 4M 4 FPM 18 4 Mbit 4 32 Mbyte 2 1 FPM Fast Page Mode A parity bit checks every eight consecutive data bits byte parity The DRAM parity check is only performed when SW9 2 is set appropriately OFF enabled default
84. CHK CHK2 instruction 7 01Cig TRAPcc TRAPV instructions 8 02016 Privilege violation 9 02416 Trace svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware R 68060 CPU Table 19 68060 CPU exception vector assignments cont Vector Vector number s offset Hex Assignment 10 02816 Line 1010 emulator unimplemented A line opcode 11 02Ci1g Line 1111 emulator unimplemented F line opcode 12 03016 Emulator interrupt 13 03416 unused by MC68060 14 03816 Format error 15 03Ci Uninitialized interrupt 16 23 04016 05C4g reserved unassigned 24 06016 Spurious interrupt Interrupt autovector for level 25 06416 1 26 06816 2 27 06Cig 3 29 07416 5 30 07816 6 31 07C1g 7 32 47 080 0BC TRAP 0 15 instruction vectors FPCP 48 0C01g branch or set on unordered condition 49 0C41g inexact result 50 0C8416 divide by zero 51 OCCig underflow 52 ODO1 operand error 53 OD416 overflow 54 0D816 signalling SNAN 55 ODCi unimplemented data type 56 OEO016 unused by MC68060 57 OE41g Defined for 68852 unused by 68060 58 OE81gG Defined for 68852 unused by 68060 59 OECig reserved unassigned 60 OF01g Unimplemented effective address 61 OF4i1g Unimplemented integer instruction 62 63 OF846 0FC4g reserved unassigned 64 255 1004 6 3FC g User defined vectors 192
85. CSI floppy disk drive and one serial I O port SYS68K CABLE 9 25 SET Set of 4 adapter cables 9 pin D Sub male connector to 25 pin D Sub female connector length 2 m SYS68K CPU 60 SYS68K FH002 SET SYS68K FH003 SET SYS68K FH007 SET Hybrids for the serial I O interfaces 10 hybrids per set RS 232 protocol RS 422 protocol RS 485 protocol svsesk ceu so RSE 204077 June 1999 Installation 2 Installation 2 1 Safety Note CAUTION CAUTION NOTICE A A Safety Note To ensure proper functioning of the product during its usual lifetime take the following precautions before handling the board Malfunction or damage to the board or connected components Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime e Before installing or uninstalling the board read this Installation sec tion e Before installing or uninstalling MEM 60 memory modules read the MEM 60 Installation Guide packaged together with the modules e Before installing or uninstalling the board in a VME rack turn off the power e Before touching integrated circuits ensure that you are working in an electrostatic free environment Ensure that the board is connected to the VMEbus via both the P1 and the P2 connectors and that power is available on both of them When operating the board in areas of strong electromagnetic radiation ensure that
86. CSI 1 120 191 78 BFig 1EO04g 2FC4g User defined vectors 192 COi 30016 FGA 002 Mailbox 0 193 Clig 30416 FGA 002 Mailbox 1 194 C216 30816 FGA 002 Mailbox 2 195 C316 30Cig FGA 002 Mailbox 3 196 C4ig 3104 FGA 002 Mailbox 4 197 C516 31416 FGA 002 Mailbox 5 198 C6ig 31816 FGA 002 Mailbox 6 199 C716 31Cig FGA 002 Mailbox 7 200 223 C84g DFig 32046 37C4g reserved Unassigned Page 166 svsesk ceu so EE Vers 2 85 ange with VMEPROM 32 imentation ch 204077 June 1999 last docu Appendix to VMEPROM z Interrupt Vector Table of VMEPROM Vector number Vector address Assignment 224 E016 38016 FGA 002 Timer 225 Eli 38416 reserved 226 E216 38816 reserved 227 E346 38C4g reserved 228 E4ig 39016 FGA 002 FMB1 refused 229 E516 39416 FGA 002 FMBO refused 230 E616 39816 FGA 002 FMB1 message 231 E716 39C16 FGA 002 FMBO message 232 E816 3A016 FGA 002 Abort key 233 E916 3A416 FGA 002 ACFAIL 234 EA16 3A816 FGA 002 SYSFAIL 235 EBig 3ACig FGA 002 DMA error 236 ECig 3B04 amp FGA 002 DMA normal 237 EDi 3B4i reserved 238 z 3B816 reserved 239 EFic 3BCi reserved 240 F01g 3C01g FGA 002 LIRQO watchdog 241 Flie 3C41g FGA 002 LIRQI FDC 37C65 242 F216 3C816 FGA 002 LIRQ2 CIOI PCO timer 3 243 F316 3CC ig FGA 002 LIRQ3 CIO1 PBO timer 2 244 F416 3D016 FGA 002 LIR
87. CSI 53C720SE syseskcpu co R RLE Data Sheets CIO Z8536 5 1 CIO Z8536 syseskcpu co R RLE Data Sheets FDC 37C65C 5 2 FDC 37C65C syseskcpu co R RLE 2 E H Data Sheets LAN AM 79C965A 5 3 LAN AM 79C965A This data sheet copy includes Application note PCnet Family Software Design Considerations Technical description AM 79C965A PCnet 32 single chip 32 bit Ethernet controller syseskcpu co R RLE Data Sheets RTC 72421 5 4 RTC 72421 syseskcpu co R RLE Data Sheets SCC AM 85C30 5 5 SCC AM 85C30 syseskcpu co R RLE locumentation change with SYSGBK CPU 60 PCB Rev 0 1 204077 June 1999 last di Data Sheets SCC AM 85C30 syseskcpu co R RLE 2 E H Data Sheets SCSI53C720SE 5 6 SCSIS3C720SE This data sheet copy intentionally only includes the following chapters which contain all information relevant for the SYS68K CPU 60 Purpose and Audience Additional Information Contents not stripped to the information included in this copy Chapter 1 Introduction Chapter 2 Functional Description Chapter 5 Registers Chapter 6 Instruction Set of the I O Processor Appendix A Register Summary syseskcpu co R RLE VMEPROM 6 VMEPROM This CPU board operates under the control of VMEPROM a ROM resi dent real time multiuser multitasking monitor program VMEPROM pro vides the user with a debugging tool for single and multitasking real time applications Common and All com
88. CSI 53C720SE FF80 3800 g FDC 37C65C FFD0 0000 FGA 002 6 4 2 On Board Interrupt Sources Table 65 The following table shows the on board interrupt sources and levels de fined by VMEPROM All interrupt levels and vectors of the on board I O devices are software programmable via the FGA 002 gate array On board interrupt sources Vector Vector Device IRQ level number address Abort switch 7 232 E8 3A0i1 FGA 002 DMA error 4 235 EB 3ACi FGA 002 DMA ready 4 236 EC 3B01 Watchdog 7 240 FO 3C0ig CIOI timer tic 5 242 F2 3C816 SCC 4 244 F4 3D04g 6 4 5 Off Board Interrupt Sources Page 134 VMEPROM supports several VMEbus boards As these boards are inter rupt driven the level and vectors must be defined for VMEPROM to work properly The following table shows the default setup of the inter rupt levels and vectors of the supported hardware For a detailed description of the boards hardware setup see section 7 Appendix to VMEPROM on page 151 For further information on the supported I O boards together with the base addresses and the interrupt levels and vectors see table below In or der to ensure that these boards work correctly with VMEPROM the list ed interrupt vectors must not be used svsesk ceu so RSE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 VMEPROM 6 4 4 6 5 A R X E SYS68K CPU 60 Table 66
89. D23 D15 D07 Transfer type 24 16 08 00 Byte on odd address X Byte on even address X Word X X Long word x x x x Unaligned word x x Unaligned long word A x x x Unaligned long word B x x x Read modify write byte on odd address x byte on even address x word X X long word x x x x VMEbus master transfer cycles defined for D16 data bus width D31 D23 D15 D07 Transfer type 24 16 08 00 Byte on odd address x Byte on even address x Word X X Read modify write byte on odd address x byte on even address x word X X R X E SYS68K CPU 60 Page 79 VMEbus Interface 3 15 4 Page 80 Hardware Master Interface Burst to VMEbus Bus collision during 1st cycle Bus collision during 2nd to 4th cycle Solution locked RMC transfer To use this feature On the initial cycle of a line transfer a retry causes the 68060 CPU to re try the bus cycle Contrasting to this a retry signaled during the 2nd 3rd or 4th cycle of a line transfer is recognized as a bus error and causes the CPU to abort the line transfer and start an access fault exception subrou tine This different behaviour results in a different behaviour when encounter ing bus collisions during the 1st or during the 2nd 3rd or 4th cycle of a line transfer When the 68060 CPU wants to access a slave on the VMEbus and has already been granted the l
90. D8 SAGE 11 1010 NPA 3916 11 1001 NDA A R X E SYS68K CPU 60 Page 77 VMEbus Interface Hardware Table 43 Address ranges related to AM codes cont Address range AM code Code Address and data bus width FBFF 00004 2D16 10 1101 SDA VMEbus short I O access PBFF FFFF 4 2916 10 1001 NDA A16 D32 D24 D16 D8 FC00 0000 3E1g 11 1110 SPA VMEbus standard access EOE ig 3Dig 11 1101 SDA A24 D16 D8 3A 11 1010 NPA 39 6 11 1001 NDA FCFF 0000 6 2Dig 10 1101 SDA VMEbus short I O access FCFF FFFFjg 2916 10 1001 NDA A16 D16 D8 3 15 3 Master Interface Data Transfer Size Page 78 Fixed and programmable D32 D16 Automatic 32 to 16 bit transformation Table 44 The VMEbus address range is the largest portion of the memory map see section 3 1 SYS68K CPU 60 Memory Map on page 36 It is divided into ranges with address and data bus widths varying between different ranges but fixed within a range A32 A24 A16 and D32 D106 respective ly The VMEbus master interface also contains address ranges where the data transfer size is software programmable to be 16 bit or 32 bit wide When the data transfer bus width for an address range is limited to 16 bit and a 32 bit transfer is attempted the CPU board hardware will automat ically perform two consecutive transfers so that no software overhead is necessary The following table lists
91. DS B 1 BitO If this bit is 0 no message occurs indicating that VMEPROM is waiting until the hard disk is up to speed This bit is only consid ered if bit 1 is set to 1 Bit 1 If it is 0 VMEPROM does not wait until hard disk is up to speed Bits 2 7 reserved should be 0 5516 FFig DS B 1 reserved 5616 071g DS B 1 SCSI controller ID 5716 5 times FF 4 6 DS B 5 reserved SCig 16 DS W 1 Number of 16 Kbyte hashing buffers to improve disk ac cess speed Valid entries are numbers from 1 to 32 SEig 0000 000016 DS L 1 reserved gt R X E SYS68K CPU 60 Page 175 Modifying Special Locations in ROM Appendix to VMEPROM Reprogramming The following procedure describes how to reprogram the on board sys the flash memory tem flash memory IMPORTANT If there is another CPU or memory board available on the VMEbus it should be used to save the current content of the system flash into a file 1 2 Copy the binary image to the local RAM of the other CPU board via the VMEbus BM FFO00000 FF400000 destination Save the binary image into a file After saving the current content of the on board system flash it can be re programmed 1 Page 176 Enter the FGA 002 boot software by simultaneously asserting the reset and abort switch and then releasing the reset switch Initialize the FGA 002 and make the main memory available INIT Check whether switch SW 10 3 is set appropriately to e
92. ET output ACFAIL Page 76 The VMEbus specification includes the signals SYSFAIL SYSRE SET and ACFAIL for signalling exceptions or status The SYSFAIL SYSRESET and ACFAIL signals are connected to the CPU board via buffers switches and the FGA 002 The FGA 002 may be programmed to generate local interrupts when the SYSFAIL signal is active The VMEPROM firmware monitors the SYSFAIL line during the initialization of external intelligent I O boards The VMEbus SYSRESET signal is only monitored by the CPU board if SW9 4 is set appropriately OFF enabled default OFF see page 13 A SYSRESET is generated by the SYS68K CPU 60 for any one of the following reasons the front panel reset key is active a RESET instruction is executed by the 68060 CPU on the local bus the FGA 002 reset register is accessed the watchdog timer is reset power up occurs orthe voltage monitor detects a low voltage condition on board The SYSRESET signal is only passed to the VMEbus if SW9 3 is set appropriately OFF enabled default OFF see page 13 The ACFAIL line is ignored by VMEPROM The VMEbus requester logic in the FGA 002 monitors the ACFAIL signal and may force a re lease of the VMEbus mastership when ACFAIL is asserted The CPU board can never drive the ACFAIL signal svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware VMEbus Int
93. Ebus backplane from its rear To avoid damage to the board do not use the SYS68K IOBP 1 for the SYS68K CPU 60 if serial port 42 is configured as RS 422 The SYS68K IOBP 1 enables easy connection to the I O signals which are available on the CPU board s P2 connector SYS68K IOBP 1 pin assignment for VME P2 A C SCSIDB0 O 1 G SCSIDB 1 co SCSI DB 2 G FDC Drive Select 4 2 SCSI DB 3 Q FDC Index SCSIDB4 O 5 Q FDC Drive Select 1 SCSI DB 5 Q FDC Drive Select 2 SCSI DB 6 FDC Drive Select 3 1 SCSI DB7 G FDC Motor On SCSI DB P G FDC Direction In GND 10 Q FDC Step GND G FDC Write Data GND O G FDC Write Gate SCSI TERMPWR G FDC Track 000 GND O FDC Write Protect GND 15 Q FDC Read Data SCSI ATN G FDC Side Select GND O Q FDC Disk Change SCSIBSY G SCSI ACK Q GND SCSIRST 20 Q GND SCSI MSG O G SCSI SEL g SCSI CD 6 e SCSIREQ O G SCSIIO 25 Q G oO GND O G reserved O Q reserved SER DSR O Q SER DCD SERRTS Q 30 Q SERRXD SER CTS O Q SER TXD SER GND 32 Q SERDTR Instead of FDC DCHG there formerly was FDC READY see note on page 25 The SYS68K IOBP 1 contains the following connectors e P2 for the standard SCSI interface P3 for the floppy disk interface and P5 for the ser
94. FFCF FFFFig FFD0 000046 FGA 002 Gate Array internal reg n a N N 32 16 8 FFDF FFFFigG FFE0 00004 amp Boot PROM N Y N 32 16 8 EFEF FFFF 16 FFFO 00004 Ethernet LAN AM 79C965A N N N 32 16 8 FFE 3 FFFF 16 FFF4 0000i Register area see section3 6 N N N reg REE TEER ig RIALTO Bus Bridge on page 50 depen and section 3 8 1 Register Set on dent page 53 for memory control uFFFF FFFF1 FFF8 000016 SCSI 53C720SE N N N 32 16 8 SFFFB FFFFigG FFFC 00001 amp reserved n a n a n a n a 3 2 SYS68K CPU 60 Interrupt Map Page 38 ACFAIL and SYSFAIL Flexible interrupt programming The FGA 002 monitors the VMEbus and all SYS68K CPU 60 interrupt requests IRQ interrupt requests of all seven VMEbus interrupt levels interrupt requests from on board devices e g from the SCSI and the floppy disk controller and the FGA 002 specific interrupt requests Additionally the VMEbus signals ACFAIL and SYSFAIL can be pro grammed to interrupt the CPU on a software programmable level Every interrupt source including the VMEbus IRQs can be programmed to interrupt the CPU on an individually programmable priority level from 1 through 7 The FGA 002 may supply the interrupt vector or it may initiate an inter rupt vector fetch from the I O device or from the VMEbus svsesk ceu so RSE 204077 June 1999 last documentation change with SYS
95. Generation VMEbus SYSRESET SYSRESET generation IMPORTANT Reset period Status information IMPORTANT Page 102 Hardware Additionally SYSRESET output is asserted by the FGA 002 if it is enabled via the FGA 002 CTRL49 register 7 VMEbus SYSRESET The VMEbus SYSRESET line is received by the SYS68K CPU 60 only if SYSRESET input is enabled that is if SW9 4 is set appropriately OFF enabled Whenever a reset is generated by one of the sources 1 to 6 SYSRESET output is asserted additionally if SW9 3 is set appropriately OFF en abled default OFF see page 13 SYSRESET output is asserted by the IEEE 1014 compatible SYSRESET driver installed on the CPU board The reset generation circuitry operates when the power supply voltage Vcc reaches approximately 3 volts An asserted SYSRESET output sig nal will be held low active for at least 200 ms after all conditions that caused the SYSRESET assertion have been removed The VME SYSRESET generation must be enabled by SW9 3 if the SYS68K CPU 60 is installed in slot 1 see section SYSRESET input on page 76 During power up or after activation of the front panel reset key the CPU board is reset for approximately 200 ms The front panel RUN LED shows the status of the RESET line see RUN on page 16 If RESET is active the LED is illuminated red The LED turns to green if reset is inactive and the processor is not in the halt state In
96. I Register Map llle es 93 3 19 2 Communication across the SCSI bus 0 0 0 0 cece 93 320 Floppy Disk FDC 37C65C coe doce we Scored ene egent t Ren ncm n ae 94 3 21 Ethernet LAN AM 79C965A 2 0 ccc ce ete cece eee hh rnnt 96 3 21 10 Register Access 2i l2s 4D SPA Da A EO Ee eee 98 322 Reset Generation 66 0 35 see 66 55 Stes b DER ERE OH Seo Od SEO DT ERR EE 101 3 23 Information on Front Panel Devices 0 cece cece rece enhn 103 4 Circuit Schematics rl rr c er rer swine eese is paginated separately 5 Data Sheets 5 eese eure nte Racer e a nnt etm eene mun paginated separately 5 1 CIO Z8536 5 2 FDC37C65C 5 3 LAN AM 79C965A 54 RTC 72421 5 5 SCC AM 85C30 5 6 SCSI53C720SE 6 VMEPROM renew vere verse worse eve eaae ua eR RR ETE 125 6 1 Power up Sequence ez zll6 I6 ele p ril give RS Oe eee 126 6 2 Front Panel Related VMEPROM Features 0 0 c cece enhn 127 6 2 1 Reset Key xo See goed el Suse ee Paes TUR eR ea eee ET 127 6 2 2 ANbOrt Key S o ee Wns se tin aE Wie SAI Re 127 6 2 3 Rotary Switches x eds x ees E ON HE HR a as 128 6 3 Memory Usage of VMEPROM eeeeeeeeee eh hh hr hr rns 132 Page iv svsesk ceu so RSE 7 A Contents 6 3 1 Default Memory Usage of VMEPROM sssseeeee eese 132 6 3 2 Default ROM Use of VMEPROM slssessseee ees 132 6 4 Devices and Interrupts Used by VMEPROM eeeeeeee enhn 133 6 4 1 Addresses of the On Board I
97. M write cycles After this the cycle is terminated and the FGA 002 immediately releases the local bus mastership back to the 68060 CPU Si multaneously it completes the fully asynchronous VMEbus access cycle The early release of the memory read or write cycle allows the 68060 CPU to continue processing while the FGA 002 independently manages the VMEbus transaction overhead The early bus release thereby enables early shared RAM accesses by the 68060 CPU but sacrifices the guaran teed indivisibility of VMEbus read modify write shared RAM cycles RMW Since the 68060 CPU includes an on chip cache memory this may not ef fect the 68060 CPU performance at all but the bus band width for un cached devices is broadened A programmable bit within the FGA 002 may be used to disable the early bus release option When the early release is disabled the FGA 002 re tains the local bus mastership until the VMEbus cycle is finished This guarantees that no other local bus master 68060 CPU or DMA control svsesk ceu so EE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware User SRAM factory option ler will access the shared RAM until the VMEbus cycle is completed In case of a read modify write cycle RMW performed by another VME bus master the FGA 002 will perform both transactions a read followed by a write without releasing the local bus This guarantees that the cycle is indivisible 3 8 10 DRA
98. M Access from the Ethernet Controller The AM79C900 Ethernet controller uses DMA transfer cycles to transfer commands data and status information to and from the DRAM 3 8 11 DRAM Access from the SCSI Controller The SCSI 53C720SE uses DMA transfer cycles to run scripts and transfer data and status information to and from the DRAM 3 9 User SRAM factory option Backup Table 31 User SRAM organization A 2 backup options are available to provide the current for the user SRAM standby mode see section 3 9 1 Backup Power for the User SRAM on page 62 User SRAM features Feature Value Data path width 32 Supported port size Byte word long Base address Contiguous to DRAM Number of devices 4 Location J80 83 Supported device types M5M5408L 512k 8 Default device speed 55 ns The user SRAM memory is connected to the memory bus providing a long wide port Burst accesses are supported both for read and write Data can be read from and written to any address odd and even in byte word or long word format R X E SYS68K CPU 60 Page 61 System PROM Hardware 3 9 1 3 10 Page 62 Access address User SRAM and DRAM both contribute to shared RAM and shared range RAM access via the VMEbus is routed by the FGA 002 see section 3 8 9 DRAM Access via the VMEbus on page 60 Backup Power for the User SRAM The user SRAM is powered by the backup power circuitry Norm
99. OV FADD SUBO BNE RTS OVE OVE SUBQ ADDQ OVE OVE OVE OVE SUBQ OVE OVE M L D1 D7 A7 D1 D2 D0 D7 2 D7 1 D1 D1 D3 L D0 D2 L D2 D4 Bee Sf ae TU AO D3 1 D5 TU AO D4 1 D6 S D5 AO D4 1 S D6 AO D3 1 L D0 D3 L 1 D4 L D3 D4 S 020 D7 010 L A7 D1 D7 01001001 01011100 10001110 10100101 00000001 01110010 10000000 CACHE TEST 128KB PROGRAM IS EXECUTED 1000 TIMES CAUTION THIS BENCHMARK NEEDS 128 KBYTE MEMORY L 010 PC A2 L 4 203A0000 D1 OPCODE FOR MOVE L 0 PC DO L 4 20000 4 D2 LENGTH IS 128 KBYTE L D1 A2 LOAD OPCODE TO MEMORY L 1 D2 S 004 W 4E75 A2 APPEND RTS OW LOADED START 1000 TIMES L 1000 D3 S 010 L 1 D3 S 008 0 PROGRAM WILL START HERE FLOATING POINT 1 000 000 ADDITIONS L 41000000 D5 E L 4 0 FPO E L 1 FP1 X FPO FP1 L 1 D5 S 8010 E SYS68K CPU 60 Benchmark Source Code Page 171 Benchmark Source Code BENCH 48 FLOATING POINT 1 000 000 SINUS MOVE L 1000000 D5 FMOVE L 1 FP1 8010 FSIN X FP1 SUBQ L 1 D5 BNE S 8010 RTS PAGE BENCH 9 FLOATING POINT 1 000 000 MULTIPLICATIONS MOVE L 1000000 D5 FMOVE L 1 FP0 FMOVE L 1 FP1 010 FMUL X FPO FP1 SUBO L 1 D5 BNE S 010 RTS PAGE PDOS BENCHMARK 1 CONTEXT SWITCHES MOVE L 100000 D6 8000 XSWP CONTEXT SWITCH SUBQ L 1 D6 DONE BGT S 0000 iN RTS PAGE
100. Page 135 VMEPROM Commands VMEPROM In some cases commands do not use parameters at all If 2 or more pa rameters are entered they must be separated by a space or a comma 6 5 1 ARB Set the Arbiter of the CPU Board Format ARB The ARB command allows the user to set the arbitration modes and the re lease modes of the CPU board for the VMEbus Additionally the VME bus interrupts can be enabled or disabled Example ARB Set arbiter mode for VME BUS STATUS ROR amp RAT amp RBCLR amp FAIR SET Release on bus clear RBCLR Y N Y SET Fair VME BUS arbitration FAIR Y N N Enable 1 Disable 0 VMEbus interrupts by level STATUS Level 7654321 l Iuno olt SET Enter new interrupt mask 1111110 6 5 2 CONFIG Search VMEbus for Hardware Format IMPORTANT Page 136 CONFIG This command searches the VMEbus for available hardware regardless of the rotary switch setting and enables installation of additional memory The conric command also installs Winchester disks in the system and initializes the disk controller if available If a SYSFAIL is active on the VMEbus e g being generated by an ISIO 1 2 or ISCSI 1 controller during self test the command is suspended un til the SYSFAIL signal is no longer active Additional memory installation All boards to be installed must use the addresses documented in section 7 1 Driver Installation on page 151 I
101. Q4 CIO1 CIO2 cascaded 245 F516 3D41g FGA 002 LIRQ5 SCC Z85C30 246 F616 3D816 FGA 002 LIRQ6 SCSI NCR 53C720SE 247 F716 3DC g FGA 002 LIRQ7 LAN Am79C965 248 254 F84g FEg 3E046 3F816 reserved Unassigned 255 FFig 3FCig FGA 002 Empty interrupt CE SYS68K CPU 60 Page 167 Benchmark Source Code 7 6 Benchmark Source Code Appendix to VMEPROM KKKKKKKKKKKKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK E EE EE EE EE E E EE Module name Assembler benchmarks Version 1 0 X date started 20 Apr 87 M S last update 23 Apr 87 M S e Copyright c 1986 87 FORCE Computers GmbH Munich ae KKKKKKKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK E E E EE E EE Ei section 0 opt alt P 68020 P 68881 xdef benchex xdef BENIBEG BEN1LEND xdef BEN2BEG BENZ2END xdef BEN3BEG BEN3END xdef BENABEG BENAEND xdef BEN5BEG BEN5END xdef BEN6BEG BEN6END xdef BEN7BEG BEN7END xdef BEN8BEG BEN8END xdef BEN9BEG BEN9END xdef BENLOBEG BEN1OEND xdef BEN11BEG BEN11END xdef BEN12BEG BEN12END xdef BEN13BEG BEN13END xdef BEN14BEG BEN14END page benchmark execution benchex address movem l di1 a6 a7 move l 15 4 a7 a0 jsr a0 movem l a7 d1 a6 rts BENCH 41 DECREMENT LONG WORD IN MEMORY 10 000 000 TIMES LEA L 08010 PC A0 MOVE L 10000000 A0 020 SUBO L 1 A0 BNE S 08020 RTS 0010 DS L 1 BENCH 4
102. SYS68K CPU 60 uses While the 53C720SE is executing SCRIPTS access only the ISTAT register use SCRIPTS to access all other registers 3 19 2 Communication across the SCSI bus Initiator and target A Communication on the SCSIbus is only allowed between 2 SCSI devices at any given time There may be a maximum of 8 SCSI devices Each SCSI device has a SCSI ID assigned When 2 SCSI devices communicate on the SCSIbus one acts as initiator and the target performs the operation A SCSI device usually has a fixed role as initiator or target but some devices may be able to assume either role Certain SCSIbus functions are assigned to the initiator and other functions are assigned to the target R X E SYS68K CPU 60 Page 93 Floppy Disk FDC 37C65C 3 20 Page 94 Transfer modes Hardware The initiator may arbitrate for the SCSIbus and select a particular tar get An initiator may address up to seven peripheral devices that are connected to a target An option allows the addressing of up to 2048 peripheral devices per target using extended messages The target may request the transfer of COMMAND DATA STATUS or other information on the data bus In some cases it may arbitrate for the SCSIbus and reselect an initiator for the purpose of continuing an operation Information transfers on the data bus are asynchronous and follow a de fined REQ ACK handshake protocol One byte of information may be transferred
103. TCB struct SYRAM pSYRAM For further information see table 63 Layout of system flash memory on page 133 For information on programming the modified image into system flash see section 7 7 Modifying Special Locations in ROM on page 174 syseskicpu co RSE Vers 2 85 ange with VMEPROM 32 locumentation ch 204077 June 1999 last d FGA Boot 8 FGA Boot Boot Sequence The booter on this CPU board is the FGA 002 boot software also called FGA Boot It provides the initialization of the board s hardware debugger commands and utility functions 8 1 Boot Sequence IMPORTANT No modules found Hardware initialization A At first FGA Boot initializes the devices on the board and checks if the board is System Controller slot 1 If so it turns on the user LED UL and enables the FGA 002 arbiter For more details about the slot 1 func tionality please refer to VMEbus Slot 1 on page 86 Then the firmware in the second boot flash at address FFE8 0000 6 or the system flash memory at address FF00 0000 is started It is also possible to specify another module address that will be stored in the battery buffered SRAM see sETUP command The binary images on these locations must be program modules i e they must provide an SSP stack pointer at offset 0 and a PC program counter at offset 4 c If no program modules are found the debugger will be started instead Du
104. Tab 36 Tab 37 Tab 38 Tab 39 Tab 40 Tab 41 Tab 42 Tab 43 Tab 44 Tab 45 Tab 46 Tab 47 Tab 48 Tab 49 Tab 50 Tab 51 Tab 52 Tab 53 Tab 54 Fig 9 Tab 55 Tab 56 Tab 57 Tab 58 Tab 59 Tab 60 Tab 61 Tab 62 Tab 63 Tab 64 Tab 65 Tab 66 Tab 67 Tab 68 Tab 69 Tab 70 Fig 10 Fig 10 Tab 71 204077 June 1999 Using This Manual Using This Manual IMPORTANT A This section does not provide information on the product but on common features of the manual itself its structure special layout conventions and related documents Audience of the Manual This Technical Reference Manual is intended for hard and software de velopers installing and integrating the SYS68K CPU 60 into their sys tems Overview of the Manual This Technical Reference Manual provides a comprehensive hardware and software guide to your board Please take a moment to examine the Table of Contents to see how this documentation is structured This will be of value to you when looking for information in the future It includes brief overview of the product the specifications the ordering infor mation see section 1 Introduction on page 1 the installation instructions for powering up the board see section 2 Installation on page 7 It includes the default configuration switches and the like initialization and connector pinouts The installation instructions also appear
105. U board and pressing reset Example To install the first port of a SIO board with a 9600 baud rate as port number 3 enter the following BP 3 9600 2 FCB00000 svsesk ceu so SEE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 Appendix to VMEPROM A Table 67 Simultaneous use of SIO 1 2 and ISIO 1 2 IMPORTANT SYS68K ISIO 1 2 Driver Installation Base addresses of SIO 1 2 ports SIO board Port Address first 1 FCBO 00004 FCBO 00401 FCB0 0080 FCBO 00C01 FCBO 01001 Nin AJ JN FCBO 01401 m second FCB0 020046 FCBO 02401 FCBO 02801 FCB0 02C0 FCB0 0300 Alaj AJ JN FCBO 03401 VMEPROM supports up to two serial I O boards These can be either the SIO 1 2 board the ISIO 1 2 board or a mixture of both The first board of every type must be set to the first base address If one SIO 1 board and one ISIO 1 board are used the base address of the boards must to be set to e FCBO 0000 for SIO 1 FC96 00004 for ISIO 1 By default the serial I O boards SYS68K ISIO 1 2 are set to the address 96 0000 in the standard VME address range VMEPROM awaits this board at this address FC96 0000 for the CPU 60 changes to the default setup are not necessary An optional second board may be used In this case the address must be set to 98 00004 For a descr
106. VMEbus is routed by the FGA 002 DRAM and user SRAM both contribute to shared RAM The start and end ac cess addresses are programmable in 4 Kbyte steps The write protection of the programmed memory range depends on the VMEbus address modifier codes For example in privileged mode the memory can be read and written while in non privileged mode the mem ory can only be read or a non privileged access can be prohibited alto gether The access address of the shared RAM for other VMEbus masters is pro grammable via the FGA 002 Both the start and the end address of the shared RAM are FGA 002 programmable in 4 Kbyte increments see the FGA 002 Gate Array User s Manual Therefore the address range used by other VMEbus masters is not necessarily the same as the one used by the 68060 CPU for local accesses If a DRAM parity error is detected during a VMEbus slave read access the memory controller terminates the cycle with an error acknowledge Via the RIALTO bus bridge the error is signaled to the FGA 002 which drives the BERR signal Thereby the parity error is signaled to the VME bus master When the FGA 002 detects a VMEbus access cycle to the programmed address range of the shared RAM it requests bus mastership of the CPU bus via the RIALTO bus bridge from the CPU bus arbiter After the arbi ter has granted the CPU bus mastership to the FGA 002 the VMEbus ac cess cycle is executed and all data is latched read cycles or stored to RA
107. ace from offset to end of flash bank Page 186 svsesk cPU so R LE 204077 June 1999 last documentation change with FGA Boot Vers 4 21 FGA Boot Debugger Commands Format 3 of the command also specifies the number of bytes to program Parameters flashbank Symbolic name or base address of the flash memory bank that should be programmed The following symbolic names are currently support ed BOOT FLASH first boot flash BOOT FLASH1 first boot flash BOOT FLASH2 second boot flash SYS FLASH system flash USER FLASH user flash flashoffset Optional relative byte offset within the flash bank If no offset is speci fied 0 is assumed length Optional length in bytes If no length is specified all remaining space of the flash bank will be programmed Example FORCE BOOT FPROG Usage FPROG lt flashbank gt lt source gt lt flashoffset gt lt length gt Parameter flashbank is the base address of the flash bank or one of the following defines BOOT_FLASH1 BOOT_FLASH2 SYS FLASHI USER FLASHI1 FORCE BOOT FPROG BOOT_FLASH1 100000 Do not reprogram BOOT FLASH1 this would destroy the booter Device is write protected FORCE BOOT FPROG BOOT FLASH2 100000 Programming flash memory O FRR EERE EH FE AE HEE HEE HEE HH EE HEE HH EE HERE EEE HE EERE EE 100 Done FORCE BOOT gt _ A LE svsesk CPU c0 Page 187 z Debugger Commands FGA Boot 8 2 8 GO Go to Subro
108. ad board ID from port and initialize 7 Segment Display 0 Initialize CPU registers CACR ITTx and DTTx disable all caches 1 Initialize the front panel serial I O port 1 2 Initialize the CIO devices 3 Identify board features interfaces and read serial ID ROM 4 Determine the processor s clock frequency with cache enabled 5 Determine capacity of main memory 6 Calculate checksum of SRAM parameters register and system values is it correct 4 Set SRAM parameters to default values 7 Check if the board is system controller via bit 0 of the Slot 1 Status Register This bit can be set by the slot 1 autodetection or SW6 1 and SW6 2 N bit 0 0 y Board is System Controller set bit 2 ARBITER in CTL1 value 8 Test for EAGLE modules not applicable for the SYS68K CPU 60 9 Read front panel rotary switches and store to SRAM Page 180 svsesk cPu so R LE 42 ange with FGA Boot Vers locumentation ch 204077 June 1999 last di FGA Boot Boot Sequence Figure 10 Boot up procedure continued 7 Seg Actions State display A Check for Firmware Module to start is variable Start Module at Address even see Note 1 is firmwarebase defined see Note 2 second Boot ROM o firmwaremodule firmwaremodule firmwaremodule firmwaremodule variable firmwarebase BOOT ROM2 SystemFlash Set startModule OK assume firmwaremodule is executa
109. ags 0001 Application Flags 0000 Application Value 00000000 Use the INIT command to recalculate the SRAM checksum FORCE BOOT gt INIT FORCE BOOT gt 8 2 13 SLOT Change Slot Number and VMEbus Slave Address Format IMPORTANT Page 194 SLOT slot number The szor command allows to modify the VMEbus slave address the VMEbus address of the mailbox array register MYVMEPAGE of the FGA 002 and the FMB slot number register FMBCTL as follows VMEbus slave address A32 8000 000046 0400 0000 g slot 1 VMEbus slave address A24 00 00001g Mailbox base address A16 8000 6 0400j 6 slotit 1 FBM slot number slot The size of the VMEbus slave window will be set as large as the local memory size of the board This is exactly the same as setting the rotary switches to the corresponding slot number and asserting the abort key while reset Note that the A24 slave window must be enabled separately via SETUP S After setting a new slot number the INIT command must be executed to recalculate the SRAM checksum and to validate the new values The BANNER command may be used to display the current settings syseskcpu co EE mentation change with FGA Boot Vers 4 21 204077 June 1999 last docur FGA Boot Debugger Commands Example FORCE BOOT gt SLOT 5 Use the INIT command to recalculate the SRAM checksum FORCE BOOT INIT FORCE BOOT gt _ 8 2 14
110. ailable together with the SERIAL 2 on P2 option SERIAL 2 on P2 option wide fast SCSI instead of the standard SCSI interface see section 3 19 SCSI 53C720SE on page 92 not avail able together with the SERIAL 2 on P2 option syseskcpu co RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware Figure 7 SYS68K CPU 60 block diagram Memory control RIALTO bus bridge 060 020 Va Ethernet VL A adaption VESA local bus VL bus R SE SYS68K CPU 60 SCSI SCSIbus Termin FLXI bus 020 bus FGA 002 I O bus AUX DMA FDC RTC Boot Local SRAM NVRAM PROM User flash CIO local flash 4 LEDs Hex Displ 2 rotary sw Reset key Abort key SCSIbus Serial I O l and 2 Page 35 SYS68K CPU 60 Memory Map Hardware 3 1 SYS68K CPU 60 Memory Map Page 36 IMPORTANT The SYS68K CPU 60 is designed to utilize the entire 4 Gbyte address space of the 68060 CPU As the following table and section 3 15 3 Master Interface Data Trans fer Size on page 78 show the memory map of the SYS68K CPU 60 is divided into address ranges for local memory local I O FGA
111. al During normal operation the backup power circuitry connects the 5 V operation power supply to the user SRAM Power fail When the 5 V supply fails backup power may be supplied from alter nate sources They are only available when SW5 3 is set appropriately ON RTC local and user SRAM default OFF see page 11 If SW5 3 is set appropriately the following two alternate sources are switch selectable VME standby e from the VMEbus 5VSTDByY line selectable by SW5 1 ON enabled default OFF see page 11 Backup battery from the backup battery selectable by SW5 2 ON enabled default OFF see page 11 Automatic The switch over in case of power fail is fully automatic whichever volt switch over age is higher will be available to the user SRAM System PROM The system PROM consists of 4 flash memory devices For the available capacity options see System PROM on page 2 Memory The data path of the system flash memory is 32 bit wide It is separated organization into 4 byte paths each byte path is connected to one flash memory de vice Table 32 System PROM features Feature Value Data path width 32 bit wide Supported port size for read Long Word Byte write Long aligned Number of devices 4 svsesk ceu so SEE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware System PROM Table 32 System PROM features cont Feature Valu
112. an up the stack arguments are still on the stack Calling from C Example Calling the utility function ctNo from a C programming language source define BootROM OxFFEO0000 main long util long fctNo long ret util long BootROM 0x0008 ret util 8 3 1 Extended Flash Memory Programming This routine allows partial programming of flash memories The FGA 002 s timer is used for timing during execution of the routine Function number 36 224 4 Syntax long util 36 flashbank source offset length Parameters flashbank Base address of the flash memory bank that is to be programmed source Source address of the data to program offset Relative byte offset within the flash bank length Length in bytes If 1ength is 0 all remaining space of the flash bank will be programmed A R X E SYS68K CPU 60 Page 197 FGA Boot Utility Functions Returns CO Tn oO 4 W NY F Cc 11 12 FGA Boot OK OK no errors CLEAR ERROR flash device cannot be set to 0 for erasing INVAL PARMS invalid parameters ERASE ERROR flash device is not erasable WRITE ERROR programming error ILL WIDTH illegal flash bank width was detected UNKNOWN ID unknown flash device identifier CAPACITY device is too small WRITEPROTECT flash bank is write protected NO VPP no programming voltage SELECT ERROR cannot select the specified flash bank UNIMP CMD
113. ard hardware write protection inde pendent from boot PROM 0 Mbyte factory option 4 Mbyte 8 Mbyte factory option User SRAM 32 bit wide with on board battery and 5VSTDBY line backup accessible from the CPU SCSI and Ether net on chip DMA controller and also from other VMEbus masters 2 Mbyte factory option Boot PROM 12V flash memory 8 bit wide reprogrammable on board in case of flash memory hardware write protec tion in case of flash memory independent from system PROM 32 pin PLCC sockets 128 Kbyte 12V flash mem Factory options 256 Kbyte 12V flash mem 512 Kbyte 12V flash mem 1 Mbyte 5V flash mem 1 Mbyte OTP more configurations possible syseskceu co RSE 204077 June 1999 Introduction A Table 1 Specification Specification for the SYS68K CPU 60 board cont Local SRAM 8 bit wide with on board battery and 5VSTDBY line backup 32 Kbyte factory option 128 Kbyte 512 Kbyte factory option User flash 8 bit wide reprogrammable on board hardware write protectable 128 Kbyte factory option 256 Kbyte 512 Kbyte factory option Serial I O interfaces available via the front panel permitting a console port download and data communication available via the 3 row VME P2 connector RS 232 RS 422 or RS 485 compatible via FORCE hybrids FH 00x SDLC HDLC IBM BISYNC and ASYNC protocol support up to 38 4 Kbit s asynchro n
114. ared Y Y Y 32 16 8 003F FFFF g RAM address range depends on memory capacity 00xx 0000i1 User SRAM factory option con Y Y Y 32 16 8 Q005F FFFFig tributing to the shared RAM consec utive to DRAM 00xx 0000i VME A32 extended address space n a N Y 32 16 8 FAFF FFFF 16 consecutive to DRAM and user SRAM FB00 0000 VME A24 standard address space n a N Y 32 16 8 FBFE FFFF g FBFF 0000 VME A106 short address space n a N Y 32 16 8 FBFF FFFF g FC00 0000 g VME A24 standard address space n a N Y 16 8 WECFE FFFF 1 FCFF 0000 VME A106 short address space n a N Y 16 8 WECFF FFFF 1 FD00 0000 reserved n a n a n a n a FEFF FFFF g FF00 0000 g System PROM address range de N Y Y 32 16 8 QEESF FFFE g pends on system flash capacity SYS68K CPU 60 Parameters and Timers CIO Z8536 FF80 0C004 CIOI N N N 8 FF80 0DFFig FF80 0E004 CIO2 N N N 8 FF80 0FFFig FF80 1000 Slot 1 status register RO N N N 8 FF80 2000 6 Serial I O SCC AM 85C30 N N N 8 FF80 21FFig FF80 3000 6 Real Time Clock RTC 72423 N N N 8 WFF80 31FFi FF80 3800 6 Floppy Disk FDC 37C65C N N N 8 FF80 39FF gt R X CE SYS68K CPU 60 Page 37 SYS68K CPU 60 Interrupt Map Hardware Table 10 SYS68K CPU 60 memory map cont n 2 522 amp E o b 9 p 2 Access Address range Device gt 3O amp width FFCO 00004 Local SRAM N Y N 32 16 8 wFFC7 FFFF 46 FFC8 0000 6 User Flash N Y N 32 16 8 S
115. as the product s installation guide a separate manual delivered together with each product shipped adetailed hardware description see section 3 Hardware on page 33 the circuit schematics of the board for reference purposes The circuit schematics are packaged separately to enable easy updat ing They will always be shipped together with this manual Therefore us Insert the circuit schematics now see section 4 Circuit Schematics R X E SYS68K CPU 60 Page ix Page x Table 1 Using This Manual the data sheets of board components that are relevant for configuring and integrating the board in systems The following data sheets are delivered Motorola 68060 delivered as a separate manual CIO Z8536 FDC 37C65C pin to pin compatible with industry standard WD37C65C LAN AM 79C965A RTC 72421 SCC AM 85C30 SCSI 53C720SE The data sheets are packaged separately to enable easy updating They are always shipped together with this manual Therefore Cu Insert the data sheets now see section 5 Data Sheets adetailed description of VMEPROM and FGA Boot which control the CPU board operations see section 6 VMEPROM on page 125 section 7 Appendix to VMEPROM on page 151 and section 8 FGA Boot on page 179 There is additional space allocated in the manual for user notes modifi cations etc Referenced Manuals Referenced manuals separately available from FORCE COMPUTERS Referenced
116. ash memory only in socket 1 28F020A 256k 8 0 0000465 7 FFFF 16 512 Kbyte 12 V flash memory both in socket 1 and 2 5V 29F040 512k 8 0 0000 6 F FFFF 16 1 Mbyte 5 V flash memory both in socket 1 and 2 Page 66 svsesk cPU o R LE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware Boot PROM Table 36 Boot PROM address map factory options and device types cont Factory option Offset range for each installed device Device type base address as documented above Total capacity OTP 27C040 512k 8 0 00004 65 F FFFF 1g 1 Mbyte OTP EPROM both in socket 1 and 2 Supported device types but not available as factory option 12V 28F512A 64k 8 0 0000 46 0 FFFF 6 n a 12 V flash memory 28C5 12 64k 8 0 0000 46 0 FFFF 16 n a 12 V flash memory 28C010 128k 8 0 000046 1 FFFF 16 n a 12 V flash memory 5V 29F010 128k 8 0 0000 46 1 FFFF 16 n a 5 V flash memory OTP 27C010 128k 8 0 0000j6 1 F FFF 16 n a OTP EPROM 27C020 256k 8 0 000046 3 FFFF 16 n a OTP EPROM 27C080 1M 8 0 0000 4 F FFFF 16 n a OTP EPROM 3 11 2 Programming the Boot PROM IMPORTANT A Writing to the boot PROM is only enabled e when using flash memory devices e and when SW7 4 is set appropriately ON writing enabled default OFF see page 12 Before erasing or programming the boot PROM ensure that you
117. ated VMEPROM Features Power up and reset actions defined by rotary switch MODE 1 MODE 1 status register bit Description and MODE 1 setting at front panel 3 and 2 Bit 3 and bit 2 define the program to be invoked after power up and reset Bit 3 0 and bit 2 0 settings 0 1 2 3 The user program at 4080 0000 is invoked Bit 3 0 and bit 2 1 settings 4 5 6 7 The user program at FFCO 800046 is invoked Bit 3 1 and bit 2 0 settings 8 9 A B The user program at FC80 0000 is invoked Bit 3 1 and bit 2 1 settings C D E F VMEPROM is invoked Bit 1 defines whether VMEPROM tries to execute a start up file after power up and reset Bit 1 0 settings 0 1 4 5 8 9 C D VMEPROM tries to execute a start up file The default filename is SY STRT Bit 1 1 settings 2 3 6 7 A B E F VMEPROM does not try to execute a start up file but comes up with the default banner instead Bit O defines whether VMEPROM takes the follow ing two actions check the VMEbus for availability of any of the following hardware Contiguous memory ISIO 1 2 SIO 1 2 ISCSI 1 WFC I1 wait for SYSFAIL to disappear from the VMEbus For details see section 6 5 2 CONFIG Search VMEbus for Hardware on page 136 BitO 0 settings 0 2 4 6 8 A C E VMEPROM takes both actions BitO 1 settings 1 3 5 7 9 B D F VMEPROM does not take any of the
118. ations Common utility The common utility functions are described in the FORCE Gate Array functions FGA 002 User s Manual The following additional utility functions available for this booter version are described in this section Extended flash memory programming Erase flash memories Get system values in SRAM Get application values in SRAM Get Ethernet number Get memory limits C calling The interface expects C like calling conventions conventions IMPORTANT The utility interface must be called in supervisor mode It does not install its own stack but will use the application s stack All parameters must be placed as 1ong values on the supervisor stack The first parameter must be pushed onto the stack as the last one It must include the function number of the requested function Table 71 Stack frame A7 gt return address 4 function number 8 first argument of function 12 second argument of function Page 196 syseskcpu co EE locumentation change with FGA Boot Vers 4 21 204077 June 1999 last d FGA Boot FGA Boot Utility Functions Calling a utility function Calling sequence 1 Retrieve the entry address from location BootROM 0008 2 Push the parameters 32 bit values onto the stack Remember to push the function number at last 3 Call the FGA Boot utility interface in supervisor mode via JSR 4 Retrieve the return code from the interface register DO 5 Cle
119. ble b while 1 abort startModule ERROR abort amp amp new slot N Y 96 Store new slot number rotaries and halt 926 Print FORCE Boot banner and start debugger SHELL type EXIT to leave the shell C Initialize FGA 002 arbiter User LED and other hardware Set up VMEbus A32 slave window and A24 if enabled d is it a Power On Reset N Y Clear DRAM fill with 0 to initialize parity E Call user program address at offset C46 of the Boot ROM F is firmwaremodule executable N Y off startModule ERROR Start firmwaremodule exit boot software Note 1 This variable can be set with the sETUP s command Note 2 This is an entry at offset 2C1 of the Boot ROM which can be patched by the user A LE svsesk CPU c0 Page 181 z Debugger Commands FGA Boot 8 2 Debugger Commands Automatic start Manual start IMPORTANT Debugger commands Quick overview Line Editor If no program modules are found during the boot sequence the debugger will automatically be started To start the debugger manually both rotary switches must be set to F46 and the abort switch must be kept asserted while reset Note that in this case the hardware needs to be initialized by the INIT command Bus errors When accessing the DRAM from the debugger after a power up this may cause bus errors due to uninitialized parity
120. boot 48064 47872 48064 47872 48064 47872 48064 47872 48064 47872 48064 47872 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 2528 2336 SYS68K CPU 60 KE change with VMEPROM 32 Vers 2 85 E VMEPROM z g E 8 A N Installing a New Hard Disk Using FRMT and INIT WO Partitions Menu A lter D isplay R ecalc Q uit Command Q WO Main Menu 1 Parm 2 BadT 3 Form 4 Veri 5 Part 6 Writ P Togl Q Quit Command 6 Write to Disk Y es N o F ile Y Write to file Y N N WO Main Menu 1 Parm 2 BadT 3 Form 4 Veri 5 Part 6 Writ P Togl Q Quit Command Q Exit to Select Drive Update Param RAM Y N Y System Parameter RAM Updated Select Menu W WO W15 Winch F F0 F8 Floppy Q Quit Select Drive Q After formatting the disk all logical partitions must be initialized using the INIT command Example Initialize the large logical partition number 2 INIT Enter Disk 2 Directory Entries 1024 Disk Name SYSTEM Init Disk 2 Initialize disk Y umber of sectors 47776 Directory entries 1024 Number of sectors 47776 Disk name SYSTEM E SYS68K CPU 60 Page 149 Installing a New Hard Disk Using FRMT and INIT Page 150 VMEPROM svsesk ceu so RSE Vers 2 85 locumentation change with VMEPROM 32 204077 June 1999 last di Appendix to VMEPROM
121. cannot be written C 2 0 C 2 0 indicate the capacity of the installed on board DRAM see RO section 3 8 5 Reading the DRAM Capacity on page 57 A24E A24E controls the availability of the A24 expansion W 0 A24 expansion enabled A24 and A32 enabled 1 A24expansion disabled only A32 enabled 3 3 5 Page 44 Board ID and DIAG Display Table 17 CIO2 port B data register FF80 0E01 Bit 7 6 5 4 3 2 1 0 Value DP SEG G SEG F SEG E SEG D SEG C SEG B SEG A DP and When reading these bits directly after power up or reset these bits indi SEG G cate the CPU board identification number which is assigned to every type SEG A R W of CPU board The CPU identification number does not identify the fac tory options which might be available for CPU speeds memory capacity or installed modules In case of the SYS68K CPU 60 the CPU board identification number is 40 59 2 28 10 1000 gt After the first reading of these bits the bits control the status of the deci mal point DP and the segments SEG G SEG A in the front panel hexadecimal display see figure below for naming conventions The respective part of the display is turned off The respective part of the display is turned on svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware 68060 CPU Figure 8 Naming the parts of the fro
122. correctly That means that the board base addresses of any additional memory boards must be set to be contig uous to the on board memory CE SYS68K CPU 60 Page 151 Driver Installation 7 1 2 SYS68K SIO 1 2 To install driver To install a port IMPORTANT Page 152 Appendix to VMEPROM By default the two serial I O boards SYS68K SIO 1 2 are set to the VME base address BO 00004 VMEPROM expects the first SIO 1 2 boards at FCBO 00004 This is in the standard VME address range A24 D16 D8 with the address B0 000045 The address modifier decoder AM Decoder of the SIO 1 2 boards must be set to Standard Privileged Data Access Standard Non Privileged Data Access Please refer to the SIO User s Manual for the setup If a second SIO 1 2 board will be used the base address must be set to FCBO 0200 The AM decoder setup described above has to be used again Please refer to the S O User s Manual for the address setup of the second SIO board To install the SIO 1 2 board driver use the install command with the appropriate address see Software version dependent addresses on page 151 INSTALL U2 FFO02EEO00 To install one of the ports of the SIO boards in VMEPROM use the BP command The SIO 1 2 boards use the driver type 2 The hardware configuration must be detected before a port can be in stalled This can be done by using the conrre command or by setting a front panel switch on the CP
123. ct as slot 1 system controller a VMEbus requester so that it may access external VMEbus resources 3 16 1 Single Level VMEbus Arbiter IMPORTANT The CPU board contains a single level arbiter which can be enabled or disabled by software see the FORCE Gate Array FGA 002 User s Man ual No additional control of the arbiter is required The arbiter of the FGA 002 will not be set automatically by hardware when detecting slot 1 by switch setting or auto detection It must be enabled by software if the CPU board is system controller e g FGA Boot enables the arbiter automatically For more information on the FGA 002 arbiter please see the FORCE Gate Array FGA 002 User s Manual n accordance with the VMEbus specification the arbiter must be enabled if the CPU board is located in the slot 1 of the VMEbus back plane It must be disabled if the CPU board is located in any other slot e When the on board single level VMEbus arbiter is enabled all other VMEbus masters if any must request VMEbus mastership using only bus request level 3 BR3 signal Otherwise they are not recognized by the SYS68K CPU 60 3 16 2 VMEbus Requester Request arbitration level selection A The SYS68K CPU 60 includes a VMEbus requester so that it may access external VMEbus resources The request level is either selected automatically or by switch setting Ifthe SYS68K CPU 60 detects slot 1 the request level 3 will automat ically be u
124. d ware error occurred FGA Boot cannot be started Off Read board ID from port and initialize 7 segment hexadecimal display 0 Initialize the 68060 CPU registers CACR ITTx and DTTx disable caches FGA Boot has already left the boot mode in this state 1 Initialize the front panel serial I O port 1 2 Initialize the CIO devices 3 Identify board features and pre select initialization se quence to follow Read serial ID ROM 4 Determine CPU clock frequency with cache en abled 5 Determine capacity of main memory 6 Verify local SRAM contents and store default values if checksum is wrong 7 Perform auto configuration check hardware for spe cial conditions such as being plugged in slot 1 If need update SRAM value syseskcpu co RSE 204077 2 3 June 1999 Installation Table 9 System controller Starting a test after booting Correct operation A Testing the CPU Board Using VMEPROM POST codes indicating boot status cont POST code Description 8 Test for EAGLE modules not applicable for SYS68K CPU 60 9 Read front panel rotary switches and store to SRAM A Check for firmware to start default VMEPROM b If the abort key is asserted or if there is no firmware to start display the FGA Boot banner and start the shell C Initialize FGA 002 arbiter user LED and other hard ware Set up VMEbus A32 slave window an
125. d A24 if enabled d Clear DRAM fill with 0 to initialize parity E Call user program F Try to execute the firmware Off Left FGA Boot started firmware If the board is configured as system controller i e SYS68K CPU 60 is installed in slot 1 FGA Boot automatically enables the FGA 002 arbiter and switches on the user LED To test the CPU board for correct operation enter the following command after the prompt SELFTEST SELFTEST does not provide a full featured power on self test Howev er it tests some I O devices the main memory and the system timer tick interrupt The time SELFTEST takes for testing depends on the main memory s size Allow approximately one minute per Mbyte After all tests have been done the following message is displayed VMEPROM Hardware Selftest T O test vans passed Memory test passed CLOCK test aux passed R X E SYS68K CPU 60 Page 31 Testing the CPU Board Using VMEPROM Page 32 Installation svsesk ceu so RSE 204077 2 3 June 1999 Hardware 3 R A iN CE SYS68K CPU 60 Page 33 Hardware Described features DMA controllers The SYS68K CPU 60 is a high performance single board computer pro viding a 32 bit master slave VMEbus interface including DMA It is based on the 68060 CPU see section 3 4 68060 CPU on page 45 e the FORCE gate array FGA 002 see section 3 7 FGA 002 Gate Array on page 51 and the VMEbu
126. d BGOUT on lower and higher slots on the backplane where no board is plugged svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware VMEbus Slot 1 3 17 1 Slot 1 System Controller Functions IMPORTANT 3 17 2 Slot 1 Detection A Auto detection Manual detection When the CPU board is a slot 1 device the hardware of the SYS68K CPU 60 sets up the required system controller functions drive SYSCLK to VME see section 3 17 4 The SYSCLK Driver on page 88 use VMEbus arbitration level 3 instead of the level selected by SW6 3 and SW6 4 default OFF OFF level 3 BR3 see page 12 drive floating bus grant levels 0 1 and 2 to a high level signal and allow the SYS68K CPU 60 bus timer to terminate VME cycles timeout if it is enabled see section 3 17 5 WMEbus Timer on page 89 The arbiter of the FGA 002 will not automatically be set by hardware when detecting slot 1 by switch setting or auto detection It must be en abled by software if the CPU board is system controller e g FGA Boot enables the arbiter automatically For more information on the FGA 002 arbiter see the FORCE Gate Array FGA 002 User s Manual The board s slot 1 auto detection mechanism probes the VMEbus bus grant in level 3 pin BG3IN during power up to see whether it is possi ble to pull this signal down to a low signal level When the SYS68K CPU 60 is plugged into s
127. d and write Page 56 The on board memory control logic is optimized for fast accesses from the 68060 CPU providing the maximum performance Since the 68060 CPU contains an on chip data and instruction cache many CPU accesses are cache line burst fills Within four 4 byte cycles these burst fills at tempt to read 16 consecutive bytes into the 68060 CPU The first read cycle of such a burst usually requires 5 CPU clock cycles 200 ns at 25 MHz Due to the optimized design of the memory control logic each subsequent cycle only requires 1 CPU clock cycle 40 ns to complete This is commonly called a 5 1 1 1 burst transfer Overall the total cache line burst fill operation requires 8 clock cycles to transfer 16 bytes providing a memory bandwidth of over 50 Mbyte s Not all CPU accesses are burst transfers Single read and write transac tions are also supported at maximum speed A single read or write access 1 2 or 4 bytes requires 5 CPU clock cycles Distributed asynchronous svsesk ceu so RSE ange with SYS68K CPU 60 PCB Rev 0 1 locumentation ch 204077 June 1999 last d Hardware DRAM refresh is provided every 14 us and an access during a pending refresh cycle may be delayed by a maximum of 5 additional clock cycles 3 8 5 Reading the DRAM Capacity The installed on board and the MEM 60 DRAM capacity are encoded in 3 bits see MC 2 0 in CIO2 port C data register on page 44 and MC 2 0 in CIO1 port
128. data o9 15 6 GND 7 n c 8 GND 9 Collision 10 Transmit data 11 GND 12 Receive data 13 12 V DC 14 GND 15 n c Ethernet address The CPU board s Ethernet address is displayed in the banner when enter ing FGA Boot 2 11 VMEbus P2 Connector Pinout I O signals The I O signal assignment on the VMEbus P2 connector allows intercon nections using the SYS68K IOBP 1 8 bit SCSI floppy disk and serial I O see section 2 12 SYS68K IOBP 1 on page 28 e and the IOPI 2 8 bit SCSI floppy disk and serial I O see the JOPI 2 User s Installation Manual Page 24 syseskicpu 0 R RLE 204077 2 3 June 1999 Installation IMPORTANT Figure 3 A z VMEbus P2 Connector Pinout In the following 2 figures unbracketed signals are available as factory de fault Additionally e marks the signals which are available with the wide SCSI factory option They are implemented via 0 Ohm resistors e marks the signals which are available with the FDC eject factory option e C089 marks the signals which are available with the SERIAL 2 on P2 factory option e FDC DSEL I is also available at C7 to provide backward compatibility to FDC DESL3 FDC DSEL2 is also available at C3 to provide backward compatibility to FDC DESLA Instead of FDC DCHG there formerly was FDC READY However the manufacturers of floppy disk drives have agreed upon not support ing the FDC READY signa
129. dy to FORMAT Winchester Drive 0 Y Sector Interleave Table D isplay VMEPROM R ead file Q uit 1 Parm 2 BadT 3 Form 4 Veri 5 Part 6 Writ Op 2 5 SA S 617 87 Op 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Issuing Format Drive Command FORMAT SUCCESSFUL WO Main Menu 1 Parm 2 BadT P Togl Q Quit Command 5 WO Partitions Menu Command A of Large partitions 6 of Floppy Partitions 15 First track for PDOS Parts 0 Last track for PDOS Parts A lter 10219 First PDOS disk 2 Current Winch Drive 0 Partitions of Large partitions 6 of Floppy Partitions 15 First track for PDOS Parts 0 Last track for PDOS Parts Total of Logical Tracks Disk YA oO FWD 11 12 13 14 15 16 13 18 19 20 21 22 23 10219 First PDOS disk 2 Logical Trks Base Top 0 1502 1503 3005 3006 4508 4509 6011 6012 7514 7515 9017 9018 9097 9098 9177 9178 9257 9258 9337 9338 9417 9418 9497 9498 9577 9578 9657 9658 9737 9738 9817 9818 9897 9898 9977 9978 10057 10058 10137 10138 10217 10220 Physical Trks Base Top 0 1502 1503 3005 3006 4508 4509 6011 6012 7514 7515 9017 9018 9097 9098 9177 9178 9257 9258 9337 9338 9417 9418 9497 9498 9577 9578 9657 9658 9737 9738 9817 9818 9897 9898 9977 9978 10057 10058 10137 10138 10217 D isplay 3 Form 4 Veri 5 Part 6 Writ R ecalc Q uit PDOS sectors Total
130. e Default capacity 4 Mbyte see System PROM on page 2 Default device type 28F008S A 12 V flash memory Default device speed 85 ns Default address range FF00 0000 4 FF3F FFFF g 3 10 1 Device Types for the System PROM The following device types or equivalent are used as system PROM Table 33 System PROM device types Device type Device speed Total capacity 28FO08SA IM 8 85 ns 4 Mbyte Default configuration 29F016 2M 8 85 ns 8 Mbyte 3 10 2 Address Map of the System PROM The base address of the system PROM is mapped via an address decoder and fixed to FF00 00004g The size of the address range depends on the memory capacity of the used devices Table 34 System PROM address map Start End Total capacity FF00 0000 FF3F FFFFi 4 Mbyte FF00 00001 FF7F FFFF g 8 Mbyte A R X E SYS68K CPU 60 Page 63 Boot PROM Hardware 3 10 3 3 11 Page 64 Reading and Programming the System PROM Reading Read cycles of any port size are allowed Prerequisite for Programming the system PROM is only enabled when SW10 3 is set ap programming propriately OFF writing enabled default OFF see page 13 The current setting of SW10 3 can be read from the WESYSFLASH bit in the MDR see table 27 Memory diagnostic register MDR on page 55 Write Write burst cycles are terminated with a bus error by the memory control termination le
131. e by SW5 2 ON enabled default OFF see page 11 The switch over in case of power fail is fully automatic whichever volt age is higher will be available to the user SRAM sysesk cpu co RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware VMEbus Interface 3 15 VMEbus Interface ANSI VITA compliance Supported transfers RMW cycles Interrupt handler Slot 1 IACK Daisy Chain Driver A The following sections describe the VMEbus interface in detail This sec tion gives a short overview of the VMEbus interface features The SYS68K CPU 60 provides a complete VMEbus interface compliant with ANSI VITA 1 1994 The VMEbus interface supports 8 16 and 32 bit as well as unaligned data transfers The extended standard and short I O address modifier codes are implemented to interface the SYS68K CPU 60 to all existing VMEbus products Read modify write cycles on the VMEbus RMW cycles are also sup ported The address strobe signal is held low during RMW cycles while the data strobe signals are driven low twice once for the read cycle and once for the write cycle and high between both of them The complete VMEbus interrupt management is done by the FGA 002 enabling the use of a high end multiprocessor environment board with distributed interrupt handling The FGA 002 acts as D08 O interrupt handler in compliance with the VMEbus specification 16 bit interrupt vectors are not
132. ectors and pinout SCSI 53C720SE The interrupt request line IRQ of the SCSI controller is connected to the LIRQ6 input of the FGA 002 The 53C720SE cannot supply its own vec tor Therefore the local interrupt control register of the FGA 002 has to be programmed to be level sensitive and to supply the IRQ vector for the SCSI controller Single ended 8 bit SCSI 2 signals are available at row A and C of the VMEbus P2 connector As a factory option also single ended 16 bit SCSI 2 signals are available at the VMEbus P2 connector see section 2 11 VMEbus P2 Connector Pinout on page 24 An I O back panel can be plugged onto the rear side of the backplane to interface the SYS68K CPU 60 to standard 8 bit or 16 bit SCSI connec tors see section 2 11 VMEbus P2 Connector Pinout on page 24 3 19 1 SCSI Register Map SCSI 53C720SE base address IMPORTANT FFF8 00004 amp Unforeseeable interference with the 53C720SE operation In principal all 53C720SE registers listed in the 53C720SE data sheet are accessible via the CPU bus Note however that the only register that the 68060 CPU can access while the 53C720SE is executing SCRIPTS is the ISTAT register Attempts to access other registers will interfere with the operation of the 53C720SE However all registers are accessible via SCRIPTS To get the correct address use the information for the big endian bus mode 2 within the 53C720SE data sheet as this is the bus mode the
133. ed 1 Standards compliance VMEbus interface ANSI VITA 1 1994 A X E SYS68K CPU 60 Page 5 Ordering Information 1 2 Ordering Information Page 6 Table 2 Introduction Ordering information for the SYS68K CPU 60 Product name Product description SYS68K CPU 60D 4 zu Bu 6g 32 MEM 60 8 16 50 MHz 68060 based CPU board 60D in product name with 60E it is based on a 66 MHz 68060 32 bit DMA 4 8 16 32 Mbyte shared memory 2 serial I O channels RS 232 SCSI floppy disk and Ethernet inter face VMEPROM documentation not included SYS68K CPU 60D 8 field upgradable to a total of 16 Mbyte shared memory by installing the MEM 60 8 mem ory module SYS68K CPU 60x 16 field upgradable to a total of 32 Mbyte by MEM 60 16 SYS68K CPU 60Lite 4 50 MHz 68LCO060 based CPU board 32 bit DMA 4 8 16 32 Mbyte shared memory 2 serial I O channels RS 232 VMEPROM documentation not included UM SYS68K CPU 60 SYS68K CPU 60 Technical Reference Manual Set in cluding VMEPROM and FGA 002 manuals UM SYS68K FGA 002 FORCE Gate Array FGA 002 User s Manual UM SYS68K VMEPROM 32 VMEPROM User s Manual for 32 bit CPUs SYS68K IOBP 1 Rear I O paddel panel for single board computers provid ing connectors for 8 bit SCSI floppy disk drive and one serial I O port IOPI 2 Rear I O paddel panel for single board computers provid ing connectors for 8 bit S
134. een the memory and the caches of the 68060 CPU DRAM Never access mirrored DRAM locations Ensure correct configuration Usually the snoop window size equals the VMEbus slave window size If not round up the snoop window size to the next 2 value so that the VMEbus slave window is entirely covered by the snoop window The snoop window in the bridge configuration register of the RIALTO bus bridge must be configured accordingly see SNOOP 2 0 R W on page 51 The VMEbus slave window must be configured accordingly see section 6 5 9 INFO Information about the CPU Board on page 143 and the FORCE Gate Array FGA 002 User s Manual 3 8 8 DRAM Access from the 68060 CPU IMPORTANT After reset the boot PROM is mapped to address 0000 00004 After initialization the firmware enables the DRAM at 0000 00001g with an access to any of the 2 RIALTO registers see table 3 6 1 Register Set on page 50 Table 30 Default DRAM access address ranges from the 68060 CPU Start End Memory capacity 0000 0000 OIFF FFFF g 32 Mbyte 0000 000016 OO0FF FFFFig 16 Mbyte 0000 0000 007F FFFFjg 8 Mbyte 0000 000016 003F FFFFig 4 Mbyte A R X E SYS68K CPU 60 Page 59 DRAM Hardware 3 8 9 DRAM Access via the VMEbus Write protection Programmable access address range DRAM parity error VMEbus access cycle Disabling early release Page 60 Shared RAM access via the
135. el 7 interrupt when the abort key is activated This interrupt cannot be disabled and is therefore the appropriate way to terminate a user program and return to the VMEPROM command level User program tasks with port 0 phantom port as their input port will not be terminated Activating the abort key while a user program is running causes all user registers to be saved at the current location of the program counter e and the message Aborted Task to be displayed along with the con tents of the processor register Activating the abort key while a VMEPROM built in command is exe cuted or the command interpreter is waiting for input causes the message Aborted Task to be displayed contrary to the situa tion above the processor registers are neither modified nor displayed and the control to be transferred to the command interpreter R X E SYS68K CPU 60 Page 127 Front Panel Related VMEPROM Features VMEPROM 6 2 33 Rotary Switches Configuring the action to switch setting correspondence Default correspondence Page 128 The settings of the 2 rotary switches on the front panel of the CPU board are read in by VMEPROM after power up or reset They define the ac tions taken by VMEPROM after power up or reset rotary switch MODE 1 controls the program invoked the start up file executed and the check of the VMEbus for available hardware rotary switch MODE 2 controls the initialization of t
136. emory map 2 n 37 Tab 10 SYS68K CPU 60 interrupt map 2 eee eee 39 Tab 11 SYS68K CPU 60 parameters and timers register map and CIO loc 41 Tab 12 CIOL port C dataregister llle eh 41 Tab 13 CIOI port B dataregister cece ene nee 42 Tab 14 CIOI port A data register including MODE x status register 43 Tab 15 CIO2 port C data registers srono niser uL E RR eR ER EE ESO E 44 Tab 16 CIO2 port B dataregister llle eh 44 Tab 17 Naming the parts of the front panel hexadecimal display 45 Fig 8 CIO2 port A data register eects 45 Tab 18 68060 CPU exception vector assignments llle 46 Tab 19 Watchdog register map superset of the memory controller register map 49 Tab 20 Watchdog retrigger register WDR 49 Tab 21 RIALTO bus bridge register map 2 0 0 0 eee eh 50 Tab 22 Bridge configuration register BCR 0 0 0 cece cece eee eee 50 Tab 23 Snoop window definition in BCR 0 eee eee eee 51 Tab 24 Memory controller register map included in the watchdog register map 53 Tab 25 MCR memory configuration register leere 54 Tab 26 Memory diagnostic register MDR 0 0c cece ee eA 55 Tab 27 DRAM capacity encoding at CIOx port C data registers 0 57 Tab 28 A R X E SYS68K CPU 60 Page vii Tables and Figures Page DRAM device types and number of used banks
137. erface 3 15 2 Master Interface Address Modifier AM Codes The VMEbus defines 3 different address modifier ranges as shown in the following table Table 42 Address modifier AM ranges A32 A24 A16 Address Name lines used Description A32 Al 31 Extended addressing A24 Al 23 Standard addressing Al6 Al 15 Short I O The 4 Gbyte address range of the 68060 CPU is split into address ranges to support all AM codes listed in the table below Additionally the table lists the AM codes which the SYS68K CPU 60 drives and relates them to the address ranges IMPORTANT All VMEbus slave boards which are to be addressed by the SYS68K CPU 60 must recognize one or more of the AM codes in the following table to guarantee proper operation Abbreviations The abbreviations below will be used in the following table SPA Supervisor Program Access SDA Supervisor Data Access NPA Non Privileged Program Access NDA Non Privileged Data Access Table 43 Address ranges related to AM codes Address range AM code Code Address and data bus width 0xx0 000016 OE16 00 1110 SPA VMEbus extended access GESEESEEFETS 0Di1g 00 1101 SDA A32 D32 D24 D16 D8 0A16 00 1010 NPA xx depending on shared memory 0916 00 1001 NDA FA00 000016 ODi1g 00 1101 SDA FORCE message broadcast range a Eie 0916 00 10015 NDA FB00 0000 6 3Eig 11 1110 SPA VMEbus standard access gEBEESEPEE E 3Dig 11 1101 SDA A24 D32 D24 D16
138. es aDMA controller complete interrupt management amessage broadcast interface FMB timer functions and mailbox locations Monitoring the The FGA 002 monitors the 020 bus When any local device is accessed 020 bus the FGA 002 takes charge of all control signals in addition to the address and data signals used Managing the The FGA 002 serves as manager for the VMEbus All VMEbus address VMEbus and data lines are connected to the gate array via buffers Additional functions such as the VMEbus interrupt handler and arbiter are also in stalled on the FGA 002 A R X E SYS68K CPU 60 Page 51 DRAM Start address Registers 3 8 DRAM IMPORTANT Accessibility Burst mode DRAM read parity support Page 52 Hardware The start address of the FGA 002 registers is FFDO 00004g For a detailed description of the FGA 002 registers see the FORCE Gate Array FGA 002 User s Manual The CPU board provides shared dynamic RAM DRAM For the avail able capacity options see DRAM on page 2 The DRAM capacity cur rently installed is software readable see section 3 8 5 Reading the DRAM Capacity on page 57 The DRAM is optimized for fast accesses from the 68060 CPU and the SCSI and Ethernet DMA controllers see section 3 8 4 DRAM Perfor mance on page 56 Snooping is supported To guarantee the cache coherence of the DRAM it is necessary to config ure the snoop window in the bridge configuration
139. es serve a special function in conjunction with resetand abort the reset and abort keys This function is built into the boot PROM and is described in detail in the boot software description of the FORCE Gate Array FGA 002 User s Manual applications For application programs the rotary switches can be used as a general purpose input channel for diagnostics configuration selection or auto matic system boot with different configurations VMEPROM VMEPROM uses the rotary switches for automatic configuration see section 6 2 3 Rotary Switches on page 128 Table 15 CIOI port A data register including MODE x status register FF80 0C02 6 Bit 7 6 5 4 3 2 i o Value RS2B 3 0 RS1B 3 0 RS2B 3 0 RS2B 3 0 is commonly referred to as MODE 2 status register indicat RO ing the setting of the MODE 2 front panel rotary switch F MODEZ2is set to F E MODEZ2issetto E RS1B 3 0 RS1B 3 0 is commonly referred to as MODE status register indicat RO ing the setting of the MODE 1 front panel rotary switch Fjg MODE lis set to F Ejg MODElisset to E FORCE IK EN SYS68K CPU 60 Page 43 3 3 4 SYS68K CPU 60 Parameters and Timers CIO Z8536 Hardware On board DRAM Capacity and Automatic A24 Expansion Table 16 CIO2 port C data register FF80 0E00 gG Bit 7 6 5 4 3 2 1 0 used as masking bits for write MC 2 0 A24E accesses to bit 3 0 e g if bit 4 Value is 1 bit O
140. escription FFFO 0010 Register address port RAP FFFO 0012 Register data port RDP FFFO 0014 Bus configuration register data port BDP FFF0 0016 6 Reset register Example 1 for word swapping The following table shows the initialization block for the AM 79C965A when used in 16 bit mode It includes the hypothetic Ether net address 12 34 56 78 9A BC at the addresses 046 446 and 64e For information on the initialization block and its use see data sheet LAN AM 79C965A in section 5 R X E SYS68K CPU 60 Page 99 Ethernet LAN AM 79C965A Hardware Table 57 Example word swapped init block for LAN AM 79C965A in 16 bit mode Address Contents to be written 016 eth 3416 ethy 1216 216 MODE 15 00 416 eth BC46 eth 9A16 616 eth 7816 eth 5616 816 LADR 31 16 Aic LADR 15 00 Cig LADR 63 48 Eig LADR 47 32 101g RLEN followed by a 0 followed by 3 reserved bits followed by RDRA 23 16 12415 RDRA 15 0 1416 TLEN followed by a 0 followed by 3 reserved bits followed by TDRA 23 16 1616 TDRA 15 0 Example 2 for word swapping Initializing the Receive Descriptor The following table shows the ini tialization of the receive descriptor in 16 bit mode Table 58 Initializing a receive descriptor in 16 bit mode Address Contents to be written 016 Flags BADR 23 16 2
141. ess relocation mode The LAN I O ad dress space is register selectable see Bridge configuration register BCR LANDEC R W on page 50 After power up the AM 79C965A will not respond to any access on the CPU bus However the AM 79C965A will snoop any I O write accesses that may be present The AM 79C965A will wait for a sequence of 12 uninterrrupted long write accesses to address 3784 The 12 long write accesses must occur without intervening accesses to other locations and they must contain the data in the order shown in the table below FGA Boot does this automatically Initializing the LAN AM 79C965A register access Access ASCII no Address Data D7 0 interpretation 1 37816 4116 A 2 37816 4dig M 3 37816 4416 D 4 37816 0lig n a 5 37816 OBASEL 7 0 n a 6 37816 OBASEL 15 8 n a 7 37816 OBASEL 23 16 n a 8 37816 OBASEL 31 24 n a 9 37846 BCR2 7 0 n a 10 37816 BCR2 15 8 n a 11 37816 BCR21 7 0 n a 12 37816 BCR21 15 8 n a After the CPU board initialization and the Ethernet initialization see table 57 Example word swapped init block for LAN AM 79C965A in 16 bit mode on page 100 the AM 79C965A operates without any CPU interaction It transfers prepared data receives incoming packets and stores them into reserved memory locations To signal service requests the AM 79C965A interrupt signal is connected to
142. fined If the reserved supervisor stack space is not sufficient the stack pointer has to be set to point to an appropriate address in RAM 7 8 2 Using System Flash Memory Since the VMEPROM image needs about 512 Kbytes of the system flash memory there are still 3 5 Mbytes of memory available These can be used to hold a user s application For the reprogramming of the flash memory see section 7 7 Modifying Special Locations in ROM on page 174 Binding the 1 Enter the boot software and copy the system flash memory contents Application into RAM 2 Merge your own application with the VMEPROM code in RAM 3 Alter the necessary entries in the VMEPROM binary image Be sure to use the correct addresses They must be calculated for system flash not for RAM Depending on the time the application should be called this will be the Pointer to VMEPROM Initialization early exit one of the 4 entries at offset 4016 in the user patch table see page 175 or Pointer to VMEPROM Shell late exit replacement of the shell In this case the application will be called with the address of the TCB and SYRAM on the stack 4 A7 Long word containing the start address of the TCB and 8 A7 Long word containing the start address of the system RAM SYRAM A R X E SYS68K CPU 60 Page 177 Binding Applications to VMEPROM Appendix to VMEPROM Page 178 A C program at this address could look like this main struct TCB p
143. fore back up affected data before exchanging the battery Always use the same type of Lithium battery as is already installed When installing the new battery ensure that the marked dot on top of the battery covers the dot marked on the chip Used batteries have to be disposed according to your country s legisla tion Installation Prerequisites and Requirements IMPORTANT Requirements Power supply Before powering up check this section for installation prerequisites and requirements and check the consistency of the current switch settings see section 2 4 Switch Settings on page 11 The installation requires only power supply and a VMEbus backplane with P1 and P2 connector The power supply must meet the following specifications e required for the processor board 45 V 3 5 A typical for a SYS68K CPU 60D 32 3 0 A typical for a SYS68K CPU 60D 4 required for the RS 232 serial interface and the Ethernet interface 12 V 0 1 A typical with no Ethernet MAU plugged and 12 V 0 1 A typical svsesk ceu so RSE 204077 2 3 June 1999 Installation 2 2 2 Terminal Connection Installation Prerequisites and Requirements For the initial power up a terminal can be connected to the standard 9 pin D Sub connector of serial port 1 which is located at the front panel see section 2 7 Serial I O Ports SCC on page 17 2 2 3 Functional and Location Overview Figure 1 give
144. hared DRAM is accessible from the 68060 CPU the FGA 002 on chip DMA controller the SCSI on chip DMA controller the LAN on chip DMA controller and also from VMEbus masters The SYS68K CPU 60 incorporates SCSI 2 Ethernet and serial I O on board to provide full single board computer functionality The SYS68K CPU 60 has 2 serial ports at the front panel permitting a console port for download and data communication Both ports use stan dard 9 pin D Sub connectors The 68060 CPU runs at 50 MHz and has cache snooping support for al ternate master access to the shared DRAM A real time clock with battery backup is also available R X E SYS68K CPU 60 Page 1 Specification Introduction 1 4 Specification Table 1 Specification for the SYS68K CPU 60 board CPU type 68060 With snooping support write through for shared data necessary CPU clock frequency 50 MHz CPU bus frequency half of CPU clock frequency 25 MHz Page 2 DRAM CPU 60D 4 CPU 60D 8 CPU 60D 16 CPU 60D 32 32 bit wide byte parity accessible from the CPU FGA 002 SCSI and Ethernet on chip DMA controller and also from other VMEbus masters up to 128 Mbyte DRAM with memory extension module 4 Mbyte on board 8 Mbyte on board Upgradable with MEM 60 8 to 16 Mbyte in total 16 Mbyte on board Upgradable with MEM 60 16 to 32 Mbyte in total 32 Mbyte on board System PROM Flash memory 32 bit wide memory data path repro grammable on bo
145. he RAM disk the default data size on the VMEbus and the memory location of the RAM disk All settings documented below apply for both during power up and dur ing reset unless explicitly stated otherwise The correspondence between the actions VMEPROM takes after power up and reset and the rotary switch settings can be configured by patching the system PROM according to the user s choices For a description of the memory locations to be patched see section 7 7 Modifying Special Locations in ROM on page 174 The following tables show frequently used configuration examples and document the default correspondence between actions and the rotary switch settings as defined for VMEPROM For the correspondence between the rotary switch setting and the bits set in the MODE x status register see section 3 3 3 MODE x Rotary Switch Setting on page 43 svsesk cpu so WEE Vers 2 85 locumentation change with VMEPROM 32 204077 June 1999 last d VMEPROM Front Panel Related VMEPROM Features Table 59 Examples for power up and reset configuration by rotary switches Setting of MODE 2 1 Description of actions after power up and reset F F 32 bit VMEbus data size RAM disk at top of memory Start of VMEPROM 4 C RAM disk initialization e 32 bit VMEbus data size e RAM disk at address 4080 000016 Start of VMEPROM Execution of start up file SY STRT Check for available hardware on the VMEbus a
146. he slot 1 functions manually by setting SW6 2 appropri ately ON enabled default OFF see page 12 For SW6 2 to take any effect SW6 1 must be ON disabled also called manual mode 3 17 3 Slot 1 Status Register IMPORTANT Table 49 The status of the slot 1 detection or manual mode SW6 2 configuration may be read via the slot 1 status register at FF80 1000 It is a read only register Malfunction Writing to the slot 1 status register may cause malfunctions of the CPU board Never write to the slot 1 status register Slot 1 status register RO FF80 10001 Bit 7 s 4 h 2 fa 0 Value reserved S1STAT S1STAT S1STAT indicates whether slot 1 has been detected by auto detection or because of switch setting see SW6 1 and SW6 2 on page 12 Slot 1 has been detected Slot 1 has not been detected 3 17 4 The SYSCLK Driver Page 88 The CPU board contains all necessary circuits to support the SYSCLK signal The output signal is a stable 16 MHz signal with a 50 duty cy cle The driver circuitry for the SYSCLK signal can source a current of 64 mA The SYSCLK signal will be enabled if slot 1 has been detected by auto detection or because of switch setting see SW6 1 and SW6 2 on page 12 svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware 3 17 5 VMEbus Timer Serial I O SCC AM 85C30 The FGA 002 dispo
147. her key The disassembler supports all 68020 30 40 mnemonics syseskcpu co EE ange with FGA Boot Vers 4 21 mentation ch 204077 June 1999 last docu FGA Boot Debugger Commands Example FORCE BOOT DI 8000 5 00008000 MOVE L 123 D1 00008006 ADDI L 14 D1 0000800c ORI B 0 D0 00008010 ORI B 0 D0 00008014 ORI B 0 D0 FORCE BOOT gt _ 8 2 5 DRAMINIT Initialize DRAM Format DRAMINIT The DRAMINIT command will only have an effect if called after power up for the first time It fills the complete DRAM with 0 if dynamic RAM with parity is used on the board This forces the parity bits to be correct and prevents parity errors when reading from memory locations that have not been written previously If there is SRAM on the board it will not be initialized Example FORCE BOOT gt DRAMINIT FORCE BOOT gt _ 8 2 6 FERASE Erase Flash Memories Format IMPORTANT A FERASE flashbank FERASE flashbank flashoffset length The FERASE command allows to erase flash memory banks Format 1 of the command erases the whole flash memory bank Format 2 allows to specify a region to erase This region must exactly match the page boundaries of the flash devices Example If the SYS FLASH bank consists of four 28F008 1 M 8 bit devices in parallel with a page size of 64 Kbyte each the minimum size of one erasable region is 256 Kbyte 64 KB 4 R X E SYS68K CPU 60
148. ial I O port 1 All row A and C pins of the VMEbus P2 connector are routed to the 64 pin male P4 connector on SYS68K IOBP 1 However the P4 connec svsesk ceu so WEE 204077 2 3 June 1999 Installation SYS68K IOBP 1 tor pinout differs from the VME P2 connector by the counting direction pin 1 of P4 pin 32 of P2 pin 32 of P4 pin 1 of P2 A R X E SYS68K CPU 60 Page 29 Testing the CPU Board Using VMEPROM Installation 2 13 Testing the CPU Board Using VMEPROM Page 30 Booting up VMEPROM POST codes Table 9 VMEPROM is a firmware providing a real time multitasking multiuser monitor program It is stored in the on board system PROM To statt VMEPROM automatically during power up or reset the MODE 1 and MODE 2 rotary switches must both be set to F4 c During booting FGA Boot is executed After the successful pass of the self test routine the front panel 7 segment hexadecimal display is switched off and its decimal point is periodically switched on and off If the SYS68K CPU 60 fails during booting the following POST Power On SelfTest codes indicate the status at the time of failure The POST codes are displayed as status information during boot on the front panel 7 segment hexadecimal display The following table lists the POST codes in the order they occur during booting POST codes indicating boot status POST code Description cryptic code When a cryptic code is displayed a general har
149. ice to this or any of its products to improve reliability performance or design FORCE COMPUTERS assumes no responsibility for the use of any circuitry other than circuitry which is part of a product of FORCE COMPUTERS Inc GmbH FORCE COMPUTERS does not convey to the purchaser of the product described herein any license under the patent rights of FORCE COMPUTERS Inc GmbH nor the rights of others All product names as mentioned herein are the trademarks or registered trademarks of their respective companies Contents Table of Contents Using This Manual 25 24 A ES eR Ilem e vt Sadie NN EENE NEEESE DERE ix 1 Introduction sesse euo gr ri rrr es xp error RR er eR rie 1 1 1 Specification ur RI ER RR e RU ER ER RR ES EE ETE 2 1 2 Ordering Information 0 cc ccc cc ccc cece eee eee eee eens ees 6 2 Installation os cece eee ee cweee see te Seesmic scent eee seeet s sees sane 7 2 l Safety Noles ices ovo EI x OS See eee Ie ee EHS ON eea ERE 7 2 2 Installation Prerequisites and Requirements 0 cece eee e cece cence 8 2 2 1 Requirements sss exer eee d or td od as 8 22 2 T rminal Connection uou slo cu mE e hes hes woes y eaae e V he 9 2 2 3 Functional and Location Overview eeeeeeee ees 9 2 3 Automatic Power Up Voltage Sensor and Watchdog Timer 11 24 Switchsettings er oce Sx ted x ted REESE Ve DECR de ee ER 11 2 5 FrontPanel 12 lip E da decirte p ale Tere
150. ime registers The following programming example shows how to read from or write to the RTC 72423 ae 30 Oct 87 M S setclock sy rtc dcontrol 0 register struct rtc7242 rtc register long count 1000001 KK KK KK kk kk kk kk KKK ke read RTC 72423 and load to RAM OKCKCKCKCKCKCk kCk kCk kCk kCk kk kk kckckckck kok kok kok kk ke ee ee e x f register struct SYRAM sy RTC2 hold clock nCannot read Realtime Clock rtc dcontrol 1 while count if rtc dcontrol amp 0x02 break if count printf rtc dcontrol 0 return Sy ssec 0 unsigned char rtc seclO0reg amp 0x07 10 Sy smin unsigned char rtc minlO0reg amp 0x07 10 Sy shrs unsigned char rtc houl0reg amp 0x03 10 Sy syrs 0 unsigned char rtc gt yrl0Oreg amp 0x0f 10 Sy sday unsigned char rtc dayl0reg amp 0x03 10 Sy smon unsigned char rtc monlO0reg amp 0x01 10 start clock rtc gt seclreg amp 0x0f rtc minlreg amp OxOf rtc houlreg amp 0OxOf rtc yrlreg amp 0xOf rtc daylreg amp 0xOf rtc monireg amp OxOf i i i A X E SYS68K CPU 60 z Page 73 Real Time Clock RTC 72423 3 14 3 Page 74 Hardware ROKK RR CK CK CK CK CK CK CK KO kk kk kk Kk Kk Kk ke k k En write RTC 72423 from RAM d ae 30 Oct 87 M S Fe k Ck k Ck k Ck
151. ing of the ENPARIN bit 0 DRAM parity check should be disabled by software 1 DRAM parity check should be enabled by software SIBK SIBK indicates whether a single or both DRAM banks are assembled 0 Both DRAM banks are assembled 1 Only DRAM bank 1 is assembled A R X E SYS68K CPU 60 Page 55 DRAM z ESYSFLASH WDIRO CPUBT BTF Hardware WESYSFLASH indicates the current setting of SW10 3 thereby indicat ing whether write access to the system PROM is enabled SW 10 3 is set to ON SW10 3 is set to OFF OFF writing enabled WDIRQ flags that a watchdog interrupt has been generated To enable detection of a watchdog reset the watchdog NMI handler has to clear WDIRQ on every watchdog interrupt A watchdog reset can then be detected by reading the WDIRQ bit No watchdog interrupt occurred A watchdog interrupt has been generated CPUBT indicates whether a bus error occurred the CPU bustimer termi nates cycles on the CPU bus by generating a timeout bus error No bus error occurred A bus error has been generated BTF write burst to flash This bit is set in case of a write burst to the sys tem flash No BTF bus error detected A BTF bus error has occured PERR parity bus error This bit is set whenever a parity error is detected No parity error detected A parity error has occured 3 84 DRAM Performance 5 1 1 1 burst transfer Single rea
152. iption of the base address setup read the SYS6SK ISIO 1 2 User s Manual R X E SYS68K CPU 60 Page 153 Driver Installation To install driver To install a port IMPORTANT Table 68 Page 154 Appendix to VMEPROM To install the ISIO 1 2 board driver use the insta11 command with the appropriate address see Software version dependent addresses on page 151 INSTALL U3 FF02E400 To install one of the ports of an ISIO board in VMEPROM use the BP command The ISIO 1 2 boards are driver type 3 The hardware configuration must be detected before a port can be in stalled This can be done by using the conrre command or by setting a front panel switch on the CPU board and pressing reset Example To install the first port of an ISIO board with a 9600 baud rate as port number 3 enter the following BP 3 9600 3 FC968000 Base addresses of ISIO 1 2 ports ISIO board Port Address first 1 FC96 8000 D FC96 802016 FC96 80401 FC96 80601 FC96 80A01 2 3 4 5 FC96 80801 6 7 FC96 80C01 8 FC96 80E01 syseskicpu co RSE Vers 2 85 mentation change with VMEPROM 32 204077 June 1999 last docur Appendix to VMEPROM Driver Installation Table 68 Base addresses of ISIO 1 2 ports ISIO board Port Address second 1 FC98 80004 2 FC98 802046 3 FC98 804016 4 FC98 806046
153. ister 0 0 cee ee 91 EDC register mapiya n Melle Ret net bee a eee 95 Block diagram of the Ethernet interface llle 96 Initializing the LAN AM 79C965A register access lle 98 Ethernet controller address layout 16 Bit mode 0000000 ee 99 Example word swapped init block for LAN AM 79C965A in 16 bit mode 100 Initializing a receive descriptor in 16 bit mode 0 000000 100 Examples for power up and reset configuration by rotary switches 129 Power up and reset actions defined by rotary switch MODE 2 130 Power up and reset actions defined by rotary switch MODE 1 131 Main memory layout eseeeeeeee e eens 132 Layout of system flash memory slsseeeeeeee e 133 On board I O devices 133 On board interrupt sources 0 0 eect eee eens 134 Off board interrupt sources 0 0 ccc cece cee ee eens 135 Base addresses of SIO 1 2 ports 0 0 0 0 ee eens 153 Base addresses of ISIO 1 2 ports 0 0 0 eee cee eee 154 Types of S record format modules and VMEPROM support 158 User pateh tablen i5 ote es Oe s e ete s ess ats 175 Bootup procedure iene gee gew ecu ee edges x EE LSU E ERA RR 180 Boot up procedure continued 2 0 0 cece cece ee eens 181 Stack frames cacao ele bows A e RP me RIS DR n ees 196 Page viii svsesk cPU so R LE Tab Fig Tab 29 Tab 30 Tab 31 Tab 32 Tab 33 Tab 34 Tab 35
154. it Address 14 n CD E Byte Count Zee uie E ra a ee T Record Type S9030000FC FC eg pre eg pe ee a EE Check sum OO al a ter ceteri n Data 03 HHFA n Ha H ies Byte Count SOR RS a ee ee Record Type 7 3 System RAM Definitions SYRAM H DEFINITION OF SYRAM BLOCK OF MEMORY 05 Jan 88 Revised to correspond to PDOS 3 3 BRIAN C COOPER EYRING RESEARCH INSTITUTE INC Copyright 1985 1988 define T 64 number of tasks define M NT 3 amp OxFC number of task messages define P 16 number of task message pointers x define D NT 3 amp OxFC number of delay events ay define C 8 number of active channel buffers define F 64 number of file slots define U 15 number of I O UART ports define IZ 6 input buffer size 2 p2p J define Z 0x4000000 maximum memory size define TZ 64 task message size x define TB NT define TM NM define TP NP define CB NC define FS NF define EV ND define IE ND 2 define PS NU 1 define P2P IZ define MZ MZ define TMZ TZ ii K aX CE SYS68K CPU 60 Page 159 System RAM Definitions define define define define define define define define define define define define define IMK OxFF gt gt 8 P2P NCP 1 lt lt P2P 2 MPZ 2048 MBZ MMZ MPZ NMB MBZ 8 FSS 38 TOB 2 TOM TQB 4 TOE TOM 2 TOS TQE 2 TBZ TQS 2 4 BPS 256 RD 4 struct SYRAM 000 004 008 00A 00C
155. ith 7 lines serial I O port 2 is wired to the front panel connector labeled SERIAL 2 As a factory option serial I O port 2 may also be wired to the VMEbus P2 connector not available together with wide SCSI fac tory option For the connection to the IOBP 1 back panel see section 2 12 SYS68K IOBP 1 on page 28 For the front panel pinout of the serial lines see below For the P2 pinout see section 2 11 WMEbus P2 Connector Pinout on page 24 syseskcpu co WEE 204077 2 3 June 1999 Installation Serial I O Ports SCC Table 5 Pinout of the front panel serial I O ports config for RS 232 Pin Signal 1 DCD Data Carrier Detect input No ols 2 RXD Receive Data input and out O65 put S O 3 TXD Transmit Data output O OJo 4 DTR Data Terminal Ready output 5 GND Ground 6 DSR Data Set Ready input and out put 7 RTS Request to Send output 8 CTS Clear to Send input 9 GND Ground output supplied by FH 002 hybrid Table 6 Pinout of the front panel serial I O ports config for RS 422 Pin Signal 1 TXD Transmit Data output io ole 2 RTS Request to Send output 5 O 3 CTS Clear to Send input O A 4 RXD Receive Data input O Og 5 5 GND Signal GND 6 TXD Transmit Data output 7 RTS Request to Send output 8 CTS Clear to Send input 9 RXD Receive Data input gt R X E SYS68K CPU 60 Page 19
156. itial Supervisor Stack Pointer and Program Counter after Reset The first 2 read cycles after reset of the 68060 CPU are operand fetches of the initial supervisor stack pointer ISP and the initial program counter IPC These operands are always fetched from addresses 0000 0000 and 0000 0004 respectively After reset the boot PROM is mapped to address 0000 00004g After initialization the firmware enables the DRAM at 0000 000046 with an access to any of the 2 RIALTO registers see section 3 8 8 DRAM Ac cess from the 68060 CPU on page 59 svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware Information on Front Panel Devices 3 23 Information on Front Panel Devices R RESET key ABORT key 7 Segment hexadecimal display DIAG Rotary switches SYSFLED UL LED A iN CE SYS68K CPU 60 Page 103 See section 3 22 Reset Generation on page 101 and section RESET on page 15 see ABORT on page 15 The status display register is located in CIO2 see section 3 3 5 Board ID and DIAG Display on page 44 For information on the status register of the rotary switches see section 3 3 3 MODE x Rotary Switch Setting on page 43 See section 3 15 1 Exception Signals SYSFAIL SYSRESET and AC FAIL on page 76 See section 3 6 2 Bridge Configuration Register on page 50 Information on Front Panel Devices Page 104 Hardware svsesk ceu so
157. ix 16 bit timers are accessible via 2 CIO Z8536 see data sheet CIO Z8536 in section 5 The following parameters can be read or written reading whether an interrupt request has been generated by one of the timers 2 or 3 from CIOI see table 13 CIO1 port C data register on page 41 and table 14 CIOI port B data register on page 42 e reading the DRAM capacity see table 13 CIO1 port C data register on page 41 and table 16 CIO2 port C data register on page 44 controlling and reading the status of the serial ID ROM signals see table 14 CIO1 port B data register on page 42 for reading the CPU board s Ethernet address see section 3 21 Ethernet LAN AM 79C965A on page 96 reading the setting of the 2 front panel rotary switches see table 15 CIOL port A data register including MODE x status register on page 43 controlling the availability of the automatic A24 expansion see table 16 CIO2 port C data register on page 44 and the A24 to A32 address translation see table 18 CIO2 port A data register on page 45 reading the CPU board identification number see table 17 CIO2 port B data register on page 44 controlling the front panel DIAG 7 segment hexadecimal display see table 17 CIO2 port B data register on page 44 CIOI and CIO2 both offer 3 independently programmable 16 bit timers with 500 ns resolution which can also be used as counters For informa tion on CIOI timer 2
158. k Ck k Ck ck Ck k ckck kck ck ck ck ck ck ck ck ke ke e ke X amp xe amp x f writeclock sy register struct SYRAM sy register struct rtc7242 rtc register long count 1000001 RTC2 rtc gt dcontrol 1 hold clock while count if rtc dcontrol amp 0x02 break if count printf nCannot read Realtime Clock rtc dcontrol 0 return rtc gt fcontrol 5 rtc gt fcontrol 4 rtc gt secl0reg sy ssec 0 10 rtc seclreg sy gt _ssec 0 10 rtc gt minlOreg char sy smin 10 rtc minlreg char sy smin 10 rtc gt houl0reg char sy shrs 10 rtc houlreg char sy gt _shrs 10 rtc gt yrl0reg sy syrs 0 10 rtc yrlreg sy syrs 0 10 rtc daylO0reg sy sday 10 rtc daylreg sy sday 10 rtc monlO0reg sy smon 10 rtc monlreg sy smon 10 rtc dcontrol 0 24 hour clock start clock Backup Power for the RTC 72423 Normal operation Power fail VME standby Backup battery Automatic switch over The RTC 72423 is powered by the backup power circuitry During normal operation the backup power circuitry connects the 5 V power supply to the RTC 72423 When the 5 V supply fails backup power may be supplied from alter nate sources from the VMEbus 5VSTDBY line selectable by SW5 1 ON enabled default OFF see page 11 from the backup battery selectabl
159. l A transfer ac knowledge TA signal is asserted and the cycle completed For all other write cycles byte word the currently valid parity bits stored in the DRAM must be read at first In order to satisfy this condi tion only the necessary data will be written the remaining data already stored in DRAM memory will stay unmodified Additionally the new parity bits generated by the memory controller will be merged with the parity bits read from DRAM memory and finally all four parity bits are written to DRAM memory The transfer acknowledge TA signal is as serted and the cycle completed All write cycles are terminated before they are fully processed so that the master which is writing to DRAM can continue its operations write post ing The following register map shows all internal registers and their corre sponding register addresses Memory controller register map included in the watchdog register map Offset addr Reset value Register name FFF4 0008 xx00 00xx x Memory configuration MCR xx0 00002 Reset value XX00 00xx xxx0 0000 FFF4 000B g xxxx xx00 5 Memory diagnostic register MDR Reset value aaaa a000 a depends on the actual version pur chased see table 27 Memory diag nostic register MDR on page 55 R X E SYS68K CPU 60 Page 53 DRAM 3 8 2 Page 54 Hardware Memory Configuration Register The memory configuration register provides several bits to
160. l any longer and using FDC DCHG disk change only P2 connector pinout with serial I O config for RS 232 A C SCSIData0 Q 1 Q FDCRPM SCSIDatal G FDCHLOAD FDC EJECT SCSIData2 Q Q FDCDSEL2 SCSI Data3 O G FDC INDEX SCSI Data4 Q 5 QG FDCDSELI SCSI Data5 O GQ FDC DSEL2 SCSI Data 6 O O FDCDSELI SCSIData7 O Q FDC MOTOR SCSIDPA O O FDC DIREC GND 10 Q FDCSTEPX GND G FDC WDATA GND O O FDC WGATE TERMPWR 4 G FDC TRK00 GND G FDC WPROT GND Q 15 Q FDCRDATA SCSI ATN 9 G FDC SDSEL GND G FDC DCHG SCSIBSY G ne SCSI ACK G ne SCSIRST Q 20 G ne SCSI Data 8 SCSI MSG 9 Q SCSI Data 9 SCSI SEL G n c SCSI Data 10 SCSICD Q ne SCSI Data 11 SCSIREQ O Q Serial DTR 2 SCSI Data 12 SCSIIO Q 25 Q Serial DSR 2 SCSI Data 13 n c Serial TxD_2 Q Serial RTS 2 SCSI Data 14 n c Serial GND 2 Q Serial CTS 2 SCSI Data 15 n c Serial RxD_2 GQ Serial DCD 2 SCSI DPB Serial DSR 1 G Serial DCD 1 SerialRTS 1 Q 30 Q Serial RxD 1 Serial CTS 1 G Serial TxD 1 Serial GND 1 32 Q Serial DTR 1 LE svsesk CPU c0 Page 25 VMEbus P2 Connector Pinout Page 26 Figure 4 P2 connector pinout with serial I O config for RS 422 A SCSI Data 0 O SCSI Da
161. legal vector 0D6 char ccnt 16 control C count ef 0E6 char wind window id s f OEA char wadr window addresses ey O0EE char chin input stream kir 0F2 char chot output stream ef OF6 char _iord i o redirect ef OFA char _fect file expand count g OFB char _pidn processor ident byte 0FC long begn abs addr of K1 BEGN table 100 int rwcl 14 port row col 1 15 11C char opip i5 output port pointers 1 15 EJ 158 char _uart 16 uart base addresses 1 15 Ay 198 long _mapb memory map bias Aa xf the following change with different configurations e configuration for VMEPROM is defined to Jo NT 64 NF 64 MZ 400000 4 x NOTE the offset on top of each line is calculated only for this configuration pee ef 019C char _maps NMB system memory bitmap ee 119C char port NPS 1 NCP character input buffers 157A char iout NPS 1 NCP character output buffers 1958 char rdtb 16 redirect table P 1968 int _tque NTB 1 task queue 4 19EA char tlst NTB TBZ task list 1DEA char tsev NTB 32 task schedule event table Ef 25EA long _tmtf NTM to from INDEX W 26EA char tmb TMZ NTM task message buffers 36EA char tmsp NTP 6 task message pointers ey 374A char _deigq 2 8 NIE 10 delay event in
162. les of VMEPROM Terminal connection In case of no messages Page 126 The power up sequence is executed upon power up or after resetting the SYS68K CPU 60 All steps documented below also apply for the reset case unless explicitly stated otherwise The 2 front panel rotary switches of the CPU board define the actions taken by VMEPROM after power up or reset see section 6 2 3 Rotary Switches on page 128 After power up the processor retrieves the initial stack pointer and pro gram counter from address locations 0 and 4 These locations are the first 8 bytes of the Boot ROM area where the FGA boot software called FGA Boot resides They are mapped down to address 0 for a defined start Afterwards the boot software is executed see section 8 1 Boot Se quence on page 179 After the boot software has been executed control is transferred to the BIOS modules of VMEPROM to perform all the necessary hardware ini tialization of the CPU The real time kernel is started and the user inter face of VMEPROM is invoked as the first task The real time clock RTC of the CPU board is read and the software clock of the kernel ini tialized If a terminal is connected to the front panel serial I O port 1 the power up sequence will be terminated by displaying the following 2 messages the VMEPROM banner and the VMEPROM prompt VMEPROM is then ready to accept commands If the above messages do not appear check the fol
163. lot 1 it will succeed in pulling the VME signal to a low signal level because BG3IN is float ing on slot 1 Hence the CPU board detects slot 1 When the CPU 60 is not plugged into slot 1 it will receive the BG3IN from a board plugged into a lower slot It will fail trying to pull the VME signal to a low signal level Hence the CPU board does not detect slot 1 The following situation may cause the SYS68K CPU 60 to conclude that slot 1 is detected although being in a different slot A VMEbus system begins with the highest daisy chain priority at slot 1 the left most slot As the slots move right they lose daisy chain priority so slot 2 has higher daisy chain priority over slot 3 and slot 3 has higher daisy chain priority over slot 4 and so on After powering up auto detection may fail when another board is plugged into a slot with lower daisy chain priority This results in the board incorrectly not driving its bus grant out level 3 BG3OUT on the VMEbus to the high signal level as defined by the VME specification R X E SYS68K CPU 60 Page 87 VMEbus Slot 1 Hardware In this situation the SYS68K CPU 60 probes its BG3IN at a low signal level and concludes that slot 1 is detected However the conclusion does not fit the actual system setup To prevent this mismatch you can disable the auto detection by setting SW6 1 appropriately ON dis abled also called manual mode default OFF see page 12 and enable t
164. lowing 1 Check the terminal for the setting of the baud rate and the character format For the default port setup see section 2 7 Serial I O Ports SCC on page 17 2 Check the cable connection between the CPU board and the terminal For the serial I O port pinout and its default setup see section 2 7 Serial I O Ports SCC on page 17 3 Check the power supply for the presence of 5 V 12 V 12 V For the power consumption of the CPU board see table 1 Specification for the SYS68K CPU 60 board on page 2 svsesk ceu so RSE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 VMEPROM Front Panel Related VMEPROM Features 6 2 Front Panel Related VMEPROM Features 6 2 1 6 2 2 A Reset Key IMPORTANT Abort Key IMPORTANT Abort key activation Activating the reset key on the front panel causes all programs to terminate immediately and the processor and all I O devices to be reset Loss of data and user program When the VMEPROM kernel is started it overwrites the first word in the user memory after the task control block with an exit system call XEXT If breakpoints are defined and a user program is running when the reset key is activated the user program will possibly be destroyed While a program is running only activate the reset key as a last resort when all other actions such as pressing c twice or aborting the pro gram have failed VMEPROM causes a lev
165. lt this kind of arbitration locked RMC can be broken on a slave board which is accessible from the VMEbus and from the VME secondary bus svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware VMEbus Interface 3 15 5 Slave Interface Access Address The access address of the shared RAM for other VMEbus masters is pro grammable via the FGA 002 Both the start and the end address of the shared RAM are FGA 002 programmable in 4 Kbyte increments see the FORCE Gate Array FGA 002 User s Manual 3 15 6 Slave Interface DRAM Data Transfer Size The VMEbus slave interface for the shared RAM is 32 bit wide It sup ports 32 bit 16 bit and 8 bit as well as unaligned UAT and read modi fy write transfers 3 15 7 Slave Interface Address Modifier Decoding and A24 Slave Mode A Automatic A24 to A32 translation For VMEbus slave access to the shared RAM extended A32 and stan dard A24 accesses are allowed The on board logic allows accesses in the privileged supervisor or non privileged user mode for both data and program accesses Each access mode can be separately enabled or disabled within the FGA 002 Example Read and write permission can be enabled for supervisor accesses and read permission for user accesses Although A32 and A24 accesses are allowed the FGA 002 only recog nizes A32 accesses If an A24 access occurs and the CIO2 is configured appropriately
166. lways RBCLR No 3 REC No On BRx active after timeout or ROR Always on BCLR active RAT Always RBCLR Yes syseskcpu co RSE 204077 June 1999 last documentation change with SYS68K CPU 60 PCB Rev 0 1 Hardware Release Every Cycle REC Release on Request ROR Release After Timeout RAT Release on Bus Clear RBCLR A VMEbus Arbitration The REC mode causes a release of VMEbus mastership after every VMEbus transfer cycle has been completed A normal read or write cycle is terminated after the address and data strobes are driven high inactive state A read modify write cycle RMW is terminated after the write cy cle is completed by the CPU through deactivation of the address and data strobes If the REC mode is enabled all other bus release functions have no impact don t care The REC mode is only for CPU cycles with accesses to the VMEbus and not for cycles initiated by the on board DMA controller Programming of the REC mode is described in the FORCE Gate Array FGA 002 User s Manual The ROR mode applies only to CPU cycles to the VMEbus and not for cycles initiated by the FGA 002 DMA controller In these cases bus mastership is released when another VMEbus board re quests bus mastership while the CPU board is the current bus master For these purposes the FGA 002 DMA controller can also be the requester causing such a bus release The ROR mode cannot be disabled but it is prog
167. mon commands and system calls are described in the VMEPROM hardware Version 2 32 User s Manual specific details This section describes those parts of VMEPROM which pertain to the hardware of this CPU board Features of Configuration of the board eee Line assembler disassembler Numerous commands for program debugging including breakpoints tracing processor register display and modify Display and modify floating point data registers S record up and downloading from any port defined in the system Time stamping of user programs Built in benchmarks e Support of RAM disk and Winchester disks also allowing disk for matting and initialization Disk support for ISCSI 1 cards Serial I O support for up to two SIO 1 2 or ISIO 1 2 boards EPROM programming utility using the SYS68K RR 2 3 boards On board flash memory boot PROM system PROM and user flash programming utility Full screen editor Numerous commands to control the PDOS kernel and file manager Complete task management O redirection to files or ports from the command line Shell with over 80 commands Over 100 system calls to the kernel supported Data conversion and file management functions Task management system calls in addition to terminal I O functions e Starting an application A R X E SYS68K CPU 60 Page 125 Power up Sequence VMEPROM 6 1 Power up Sequence Power up sequence configuration FGA Boot BIOS modu
168. must be OFF A X E SYS68K CPU 60 Page 11 Switch Settings Page 12 Table 3 Switch settings cont Installation Name and default setting Description SW6 1 Slot 1 auto detection ON OFF OFF enabled j 1 ON disabled also called manual mode g F SW6 2 Slot 1 manual mode only available 2l E OFF when SW6 1 ON C3 pO OFF disabled ON enabled SW6 3 VMEbus arbitration level BRx signals OFF SW6 3 SW6 4 Level SW6 4 OFF OFF level3 BR3 OFE OFF ON level2 BR2 ON OFF level 1 BR1 ON ON level 0 BR0 SW7 1 Boot PROM configuration ON OFF OFF Socket 1 0 512 Kbyte 1 EE Socket 2 512 Kbyte 1 Mbyte 2o L ON Socket 1 disabled 3d c Socket 2 from 0 1 Mbyte 4 cj SW7 2 Abort key OFF OFF enabled ON disabled SW7 3 Reset key OFF OFF enabled ON disabled SW7 4 Boot PROM write protection OFF OFF write protected ON writing enabled syseskceu co RSE 204077 2 3 June 1999 Installation Switch Settings Table 3 Switch settings cont Name and default setting Description SWO 1 Power up detection level ON OFF OFF conforms to VME specification j ON below VME specification F SWO9 2 The switch setting signals to software q OFF DRAM parity check should be c3 p OFF enabled ON disabled SW9 3 VMEbus SYSRESET outp
169. n 3 8 7 Cache Coherence and Snooping on page 58 The A32 mode is always enabled and the A24 mode can be enabled addi tionally see section 3 3 4 On board DRAM Capacity and Automatic A24 Expansion on page 44 and System Flags in section 8 2 12 SET UP Change Initialization Values on page 193 The following table shows the allowed AM codes for VMEbus accesses to the DRAM VMEbus slave AM codes AM Code Function 3E1g 11 1110 Standard supervisory program access 3D1g 11 1101 Standard supervisory data access 3Aig 11 1010 Standard non privileged program access 3916 11 1001 Standard non privileged data access OE16 00 1110 Extended supervisory program access ODi 00 1101 Extended supervisory data access OAi 00 1010 Extended non privileged program access 0916 00 1001 Extended non privileged data access 3 15 8 Slave Interface Locked Cycles Page 82 To support RMW cycles for slave accesses the SHAREDRMW bit bit 0 of the FGA 002 CTL15 register has to be set to 1 VMEPROM sets it to 0 syseskicpu co RSE ange with SYS6BK CPU 60 PCB Rev 0 1 mentation ch 204077 June 1999 last docur Hardware VMEbus Arbitration 3 16 VMEbus Arbitration Each transfer to or from an off board address causes a VMEbus access cycle The VMEbus defines an arbitration mechanism to arbitrate for bus mastership The CPU board includes a VMEbus arbiter so that it may a
170. n 75 3 15 1 Exception Signals SYSFAIL SYSRESET and ACFAIL 76 3 15 2 Master Interface Address Modifier AM Codes 0000 e neue TI 3 15 3 Master Interface Data Transfer Size 1 ee ee 78 3 15 4 Master Interface Burst to VMEbus llle eee 80 3 15 5 Slave Interface Access Address 0 0 cece cece eee eens 81 3 15 6 Slave Interface DRAM Data Transfer Size 2 0 eee eee eee 81 3 15 7 Slave Interface Address Modifier Decoding and A24 Slave Mode 8l 3 15 8 Slave Interface Locked Cycles llle 82 VMEbus Arbitration 0 ccc cece eee ree eee cece hh hh hn 83 3 16 1 Single Level VMEbus Arbiter eee eee 83 3 16 2 VMEbus Regue stef oua i ana cee cnet eee eee 83 3 16 3 VMEbus Release Modes 2 0 00 cc cece enn ene 84 3 164 VMEbus Grant Driver 86 VMEbus Slot 1 5 cee eee eens ehh rer hne hh E rh pss 86 R X CE SYS68K CPU 60 Page iii Contents 3 17 1 Slot 1 System Controller Functions ll een 87 3 172 Slot T Detection a eee eo tee OR S ARA e E seen eeu t 87 347 3 Slot 1 Status Reg1ster ots noe ose e be ne e 88 347 4 The S YSCLK Driver uu oe nO t ee P ARR anata RR aces 88 3 17 5 NM MEDUS Timer zoe ree tet T RP RR RP e pedcs s 89 3 48 Serial LIO SCC AM 85C 30 0 ccc ccc ccc ccc cece cere rere e hh nnn 89 3 18 1 RS 485 Configuration 0 0 neces 90 3 19 SCSI 53C720SE er ib Hye ESSE OS ECKE E ESN Ra ERROR Os 92 3 19 1 SCS
171. n page 54 Once started it cannot be stopped unless a reset occurs In case of a reset the watchdog timer is automatically disabled If the retrigger event occurs within the watchdog timeout period the watchdog timer is restarted If the retrigger event does not occur within the watchdog timeout period the watchdog timer generates an NMI to the 68060 CPU If the retrigger event occurs within the watchdog timeout period after generating the NMI the watchdog timer is restarted svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware 3 52 A R X E SYS68K CPU 60 Timeout period after NMI reset Reset Watchdog Timer If the retrigger event does not occur within the watchdog timeout period after generating the NMI the watchdog timer generates a pseudo power up pulse thereby automatically stopping itself It then must be restarted by setting the ENWD bit in the memory configuration register as already stated above To enable detection of a watchdog reset the watchdog NMI handler has to clear the WDIRQ bit in the memory diagnostic register on every watchdog interrupt see table 27 Memory diagnostic register MDR on page 55 A watchdog reset can then be detected by reading the WDIRQ bit Watchdog Register Map Table 20 Table 21 The watchdog timer is controlled by the contents of the following regis ters Watchdog register map superset of the memo
172. nable writing to the system flash memory OFF writing enabled Copy the VMEPROM binary image of the system flash into RAM BM FF000000 FF040000 0 Modify the code of the VMEPROM image in RAM Erase the page in system flash memory where VMEPROM is stored these are the first 256 Kbytes FERASE SYS FLASH 0 40000 Reprogram the flash memory FPROG SYS FLASH 0 0 40000 Reboot the system to test the changes svsesk ceu so RSE Vers 2 85 locumentation change with VMEPROM 32 204077 June 1999 last d Appendix to VMEPROM Binding Applications to VMEPROM 7 8 Binding Applications to VMEPROM In general there are two ways to bind an application program in the flash memory to the VMEPROM kernel The first way keeps the original flash memory contents unchanged and uses external memory the second needs to reprogram the system flash In all cases the application program is exe cuted in user mode The XSUP system call can be used to switch to super visor mode 7 8 X Using External Memory The application can be put into an external RR 2 or RR 3 EPROM board on the VMEbus In this case the front panel switches of the CPU board must be set so that the application program is started after VMEPROM is booted In this instance the user stack is located at the top of the tasking memory and the supervisor stack is located within the task control block The supervisor stack has a size of 500 bytes Registers are not prede
173. nd wait for SYSFAIL to disappear from the VMEbus B 3 16 bit VMEbus data size e Start of user program at 4080 000016 R X CE SYS68K CPU 60 Page 129 Front Panel Related VMEPROM Features Table 60 Page 130 VMEPROM Power up and reset actions defined by rotary switch MODE 2 MODE 2 status register bit Description and MODE 2 setting at front panel 3 Bit 3 defines whether the RAM disk will be initialized after power up and reset Bit3 0 settings 0 through 7 The RAM disk is initialized after power up and reset as defined by bit O and bit 1 After disk initialization all data on the disk is lost Bit3 1 settings 8 through F The RAM disk will not be initialized after power up and reset 2 Bit 2 defines the default data size on the VMEbus Bit2 0 settings 0 3 8 B The default data size is 16 bit Bit2 1 settings 4 7 C F The default data size is 32 bit 1 and 0 Bit 1 and bit 0 define the default RAM disk usage Bit 1 0 and bit 2 0 settings 0 4 8 C RAM disk at 4080 0000 512 Kbyte Bit 1 0 and bit 2 1 settings 1 5 9 D RAM disk at FFCO 8000 4 64 Kbyte Bit 1 1 and bit 2 0 settings 2 6 A E RAM disk at FC80 0000 512 Kbyte Bit 1 1 and bit 2 1 settings 3 7 B F RAM disk at top of memory 32 Kbyte syseskicpu co WEE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 VMEPROM R Table 61 Front Panel Rel
174. nk 2 1 of 9 MEET L an o l 9 of 9 SW10 Page 10 svsesk cPU so Fe LE 204077 2 3 June 1999 Installation Automatic Power Up Voltage Sensor and Watchdog 2 3 Automatic Power Up Voltage Sensor and Watchdog Timer In the following situations the CPU board will automatically be reset and proceed with a normal power up Voltage sensor The voltage sensor generates a reset when the voltage level drops below 4 75 V Watchdog timer Per factory default the watchdog timer is disabled If the watchdog timer is enabled it generates a non maskable interrupt NMI followed by a pseudo power up when it is not re triggered The watchdog timer can be enabled by software 2 4 Switch Settings R The following table lists the function and the default settings of all switches shown in figure 2 Location diagram of the SYS68K CPU 60 schematic on page 10 IMPORTANT Before powering up the board check the current switch settings for consistency e SW6 1 SW6 2 SW6 3 and SW6 4 will only be read on a power up Description On board power backup from VME standby OFF disabled ON enabled On board power backup from backup battery OFF disabled ON enabled Devices with backup OFF RTC ON RTC local and user SRAM Table 3 Switch settings Name and default setting SWS5 1 ON OFF 1 mb 2 c3 em a L SWS2 c3 E OFF SW5 3 OFF SW5 4 OFF reserved
175. no code data field S7 supported A termination record for a block of S3 records The by VMEPROM address field may optionally contain the 4 byte ad on load only dress of the instruction to which control is to be passed There is no code or data field S8 supported A termination record for a block of S2 records The by VMEPROM address field may optionally contain the 3 byte ad on load only dress of the instruction to which control is to be passed There is no code or data field S9 A termination record for a block of S1 records The address field may optionally contain the 2 byte ad dress of the instruction to which control is to be passed General Only one termination record is used for each block of S records In gener S record type use al S7 and S8 records are only used when control is to be passed to a 3 or 4 byte address Normally only one header record is used but it is also possible that multiple header records occur Page 158 svsesk cPu so R XLE 204077 June 1999 last documentation change with VMEPROM 32 Vers 2 85 Appendix to VMEPROM System RAM Definitions Example S214020000000004440002014660000CB241F8044CB1 214020010203C0000020E428110C1538066FA487AEA4 214020020001021DF0008487A001221DF000C4E750E S21402003021FC425553200030600821FC41444452C2 XX Check sum XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Data O200KX Sea H HSH RS RH ee SSSR SS RSS See 24 b
176. nstall additional memory only by using this command svsesk ceu so RSE Vers 2 85 locumentation change with VMEPROM 32 204077 June 1999 last d VMEPROM Automatic memory detection 6 5 3 A VMEPROM Commands Additional memory must be contiguous to the on board memory of the CPU board This memory is cleared by the conFIG command to allow DRAM boards with parity to be used Please remember that the installa tion of additional memory does not affect the RAM size of the running task However VMEPROM identifies the installed memory area and ev ery time memory is required e g by CT or FM it is taken from this area as long as there is enough free space The following hardware is detected when issuing the command 1 ISIO 1 2 2 SIO 1 2 3 ISCSI 1 4 WFC 1 5 Contiguous memory starting at the highest on board memory address For the setup of all supported boards see section 7 Appendix to VME PROM on page 151 Example CONFIG UART FORCE ISIO 1 2 U3 INSTALLED ISIO 1 2 1 boards available FERASE Erase Flash Memories Format IMPORTANT FERASE flashbank FERASE flashbank flashoffset length The FERASE command allows erasing flash memory banks Format 1 of the command erases the whole flash memory bank Format 2 allows specifying a region to erase This region must exactly match the page boundaries of the flash devices Example If the SYS FLASH bank consists of four 28F008
177. nt panel hexadecimal display ERE oe A _B im _E x deed oDP 3 3 6 A24 to A32 Address Translation Table 18 CIO2 port A data register FF80 0E02 6 Bit 7 6 5 4 3 2 1 0 Value A 31 24 A 31 24 If the automatic A24 expansion is enabled see table 16 CIO2 port C W data register on page 44 A 31 24 control the status of the A31 24 3 4 68060 CPU address lines see section 3 15 7 Slave Interface Address Modifier De coding and A24 Slave Mode on page 81 The 68060 CPU is one of the fundamental components of the SYS68K CPU 60 Therefore the M68060 User s Manual is delivered to gether with this Technical Reference Manual 3 4 1 Hardware Interface of the 68060 CPU CPU driven signals A The 68060 CPU uses a non multiplexed address and data bus The bus in terface supports synchronous data transfers between the CPU and other devices in the system The CPU drives the address signals A0 A31 the size signals SIZO SIZ1 and the transfer cycle modifier TMO TM2 on every cycle inde pendently of a cache hit or miss These signals are used to decode the memory map of the CPU board The hardware on the CPU board is notified by the address and data strobe signals that the current cycle is not a cache cycle and that the decoding outputs are strobed to be valid The 32 data lines DO D31 are also driven by the 68060 CPU on write cycles R X E SYS68K CPU 60 Page 45 68060 CPU CPU
178. ntax Parameters Returns Page 200 This function copies the board s Ethernet number 6 bytes to the speci fied buffer The return value includes the status of this operation 40 228419 long util 40 long intfNumb char pEtherAdr intfNumb Interface number must be set to 0 pEtherAdr Pointer to buffer where the Ethernet number should be stored into OK ERROR no Ethernet number available syseskcpu co EE 204077 June 1999 last documentation change with FGA Boot Vers 4 21 FGA Boot FGA Boot Utility Functions 8 3 6 Get Memory Limits Function number Syntax Parameters Returns A This function determines the start address and the total size of the shared RAM DRAM user SRAM and sets the specified variables to the re specitve values The return value includes the status of this operation 41 229415 long util 41 long pBaseVar char pSizeVar pBaseVar Address of the variable where the start address of the shared RAM is stored into For the SYS68K CPU 60 this variable is always 0 be cause the shared RAM starts at 0 pSizeVar Address of the variable where the total size in Byte of the shared RAM is stored into OK ERROR cannot determine size of shared RAM R X E SYS68K CPU 60 Page 201 FGA Boot Utility Functions Page 202 FGA Boot syseskcpu co EE 42 ange with FGA Boot Vers locumentation ch 204077 June 1999 last di
179. ocal bus and when a master on the VMEbus wants to access the SYS68K CPU 60 s shared RAM and has already been granted the VMEbus a bus collision occurs In this case the FGA 002 signals a retry to the 68060 CPU to resolve the collision on the hardware level Therefore it is not necessary for the software to observe this event Opposite to the situation just described the 68060 CPU initiates a bus er ror when a bus collision occurs during the 2nd 3rd or 4th cycle of a line transfer where the CPU is not able to retry the cycle So the collision ap pears on the software level and can be resolved there but only with con siderable time expense To prevent the software from being concerned the SYS68K CPU 60 im plements the following feature A line transfer from the 68060 CPU is defined as a locked RMC read modify cycle transfer on the FLXI bus So the FGA 002 when being granted the VMEbus does not release the VMEbus until all 4 long cycles of the line transfer are successfully completed or an actual bus error oc curred When using this feature the URMW bit bit 7 of the FGA 002 CTL16 register has to be set to 1 VMEPROM sets it to O Thereby line transfers to a D16 slave are enabled Additionally the FGA 002 thereby is programmed to release ASVME high between the locked RMC similar transfers and not to support real VMEbus compatible RMCs Actual RMC transfers from the 68060 CPU are treated the same way As a resu
180. offset 4 c If a value of FFFF FFFF 4 is set default this entry will be ignored and FGA Boot starts the firmware in the second boot ROM or the sys tem flash memory If the entry contains a valid module base address the specified pro gram will be executed instead Hint If the debugger shell should be started this entry must be set to an address where there is an invalid module e g FF7F FFFO 6 System Flags 000016 This entry is board specific On the CPU 60 it is defined as following bit 15 10 reserved and must be set to 0 bit 9 8 VMEbus timer if the CPU board is system controller bit 9 and 8 are stored in VMEBUSTIMER 1 0 of the mem ory configuration register see table 26 MCR memory configuration register on page 54 bit 7 1 reserved and must be set to 0 bit 0 Enable 1 or disable 0 VMEbus A24 slave window Application Flags 000046 This entry is reserved for an application and will not be used by FGA Boot A call to utility function 39 allows to read it R X E SYS68K CPU 60 Page 193 Debugger Commands FGA Boot Name Default value Application Value 0000 000016 This entry is reserved for an application and will not be used by FGA Boot A call to utility function 39 allows to read it Example FORCE BOOT gt SETUP S Modify system values lt ESC gt or lt C gt terminates the input Start Module at Address SFFFFFFFF System Fl
181. ome user patch table entries serve as a group of pre configured alterna tives e g configuration of RAM disk or of program start address This enables easy configuration selection rather than re configuring the val ues In these cases the front panel rotary switches define the actually used configuration Therefore the user patch table includes the front pan el rotary switch setting for such cases see section 6 2 3 Rotary Switch es on page 128 The address of the user patch table is located at offset 000C relative to the beginning of the VMEPROM image Example Finding the user patch table FFOO FFOO FFOO FFOO FFOO FFOO FFOO M FFOOOOOC L FF00000C FF00EO000 MD FF00EO000 E000 E010 E020 E030 E040 E050 E060 53 00 01 24 40 55 00 70 59 00 00 44 80 52 00 24 00 FF 53 00 45 00 53 00 CO 4B 00 52 00 54 52 54 00 00 00 00 00 00 00 00 00 SYS ST RD vor slay crete les 00 00 00 08 08 00 40 80 00 00 00 08 m 80 00 00 08 08 000rFc8000005359 SY 00 00 00 00 00 00 00 00 00 00 00 00 SDS Re eie decens FF CO 8000 FC 80 00 00 FF 00 DE B6 Crs fu o sd xus 03 FF 07 FF FF FF FF FF 00 10 00 00 USER ore coed 00 00 00 00 00 00 00 00 00 00 00 00 Page 174 syseskicpu co RSE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 Appendix to VMEPROM Modifying Special Locations in ROM
182. ored in the following order EA define VBR 0 define SFC 1 define DFC 2 define CACR 4 define PC 5 define SR 6 define USTACK 7 define SSTACK 8 define MSTACK 9 define DO 10 10917 D0 D7 aA define A0 18 18 24 A0 A6 define N_REGS 25 define BYTE unsigned char define WORD unsigned int define LWORD unsigned long struct TCB 000 char ubuf 256 256 byte user buffer 100 char _clb 80 80 byte monitor command line buffer 150 char _mwb 32 32 byte monitor parameter buffer 170 char _mpb 60 monitor parameter buffer Z 1AC char _cob 8 character out buffer 1B4 char _swb 508 system work buffer task pdos stack ee 3B0 char tsp task stack pointer 3B4 char kil kill self pointer 3B8 long _sfp RESERVED FOR INTERNAL PDOS USE 3BC char svf save flag 68881 support x881 ef 3BD char iff RESERVED FOR INTERNAL PDOS USE 3BE long _trp 16 user TRAP vectors 3FE long _zdv zero divide trap A02 long chk CHCK instruction trap de 406 long _trv TRAPV Instruction trap Xo Page 162 svsesk ceu so RSE ange with VMEPROM 32 Vers 2 85 E Appendix to VMEPROM Task Control Block Definitions 40A long trc trace vector aes 40E long _fpa 2 floating point accumulator 416 long _fpe fp error processor address f 41A char _clp
183. ort 80 tracks side can be used The used step rate is 3 ms The Winchester drives are not installed automatically The VME PROM Frnt command must be used for defining the following factors The physical structure of the drive i e number of heads number of cylinders drive select number etc The bad block of the Winchester drive The partitions to be used If this setup is done once for a particular drive the data is stored in the first sector of the Winchester and automatically loaded when the disk controller is installed in VMEPROM svsesk ceu so WEE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 Appendix to VMEPROM Driver Installation To install driver To install the ISCSI 1 driver use the insta11 command with the appro priate address see Software version dependent addresses on page 151 INSTALL W FF029700 The default base address of the ISCSI 1 controller is AO 00004 in the standard VME address range This is the address FCAO 00004 for the CPU board To this setup no changes have to be made The ISCSI 1 driv er uses interrupts by default This cannot be disabled Please make sure that the interrupt daisy chain is closed so that the controller can work properly 7 1 6 Local SCSI Controller VMEPROM supports up to three Winchester disk drives together with the local SCSI Controller The Winchester drives are not installed auto matically The VMEPROM Frat command
184. ot z g E 8 A N Example Debugger Commands The following program originally located at address 0010 000046 should be loaded to 0010 02001 via a tip connection Original program 00100000 00100006 00100008 0010000a 0010000c MOVE L 123456 D0 NOP SUBO L 1 D0 BNE B 100006 RTS S record file test x 0030000rFC 212100000203C001234564E71538066FA4E7530 S804000000FB 00100200 00100206 00100208 0010020a 0010020c NOP FORCE BOOT gt LO 200 CLocal command cat test x away for 2 seconds FORCE BOOT gt DI 100200 5 MOVE L 123456 D0 SUBO L 1 D0 BNE B 100206 RTS FORCE BOOT gt _ add offset 200 to addresses use C to execute local command use cat test x to transfer file list program E SYS68K CPU 60 Page 189 Debugger Commands FGA Boot 8 2 10 NETLOAD Load File via Network to Memory Format NETLOAD filename start address ethernet number target IP server IPf The NETLOAD command loads the specified binary file via Ethernet to memory It uses the TFTP Trivial File Transfer Protocol to connect the CPU 60 to the server where the file is located Therefore a TFTP server must exist In detail RARE If no IP Internet Protocol numbers are specified target_IP and server IPf NETLOAD sends a RARP packet Reverse Address Resolution Protocol to translate the board s Ethernet num ber into an IP address
185. ous data rate SCC 85C30 2 1 2 as factory option the se cond port is not available with 16 bit wide SCSI option Ethernet interface on front panel Via AM 79C965 AUI via 15 pin D Sub Cheapernet via SMB factory option SCSI interface single ended SCSI 2 68040 compatible DMA controller with burst capability SCSI active termination SCSI port avail able on VMEbus P2 connector Via NCR 53C720SE 8 bit fast 16 bit wide factory option the wide SCSI option is not available with 2 serial ports on the P2 connector Floppy disk interface FDC 37C65C FDC37C65C is pin to pin compatible with industry standard WD37C65C SYS68K CPU 60 parameters controllable Via CIO Z8536 Timers Via 2 CIO Z8536 With 500 ns resolution Six 16 bit timers Watchdog timer Reset NMI Real time clock With on board battery and 5VSTDBY line backup IRQ capability Via RTC 72423 R X E SYS68K CPU 60 Page 3 Specification Introduction Table 1 Specification for the SYS68K CPU 60 board cont VMEbus interface Master Master AM CODES Standard supervisory data program access Standard non privileged data program access Short supervisory access Short non privileged access Extended supervisory data program access Extended non privileged data program access Slave Software programmable FGA 002 A24 logic ac cess address Slave AM CODES Standard supervisory data program access
186. plicable value when actually applied A R X E SYS68K CPU 60 Page xi Page xii CAUTION NOTICE IMPORTANT Using This Manual Icons for Ease of Use Safety Notes and Tips amp Tricks There are 3 levels of safety notes used in this manual which are described below in brief by displaying a typical layout example Be sure to always read and follow the safety notes of a section first before acting as documented in the other parts of the section Dangerous situation injuries of people and severe damage to objects pos sible Possibly dangerous situation no injuries to people but damage to objects possible No danger encountered Only application hints and time saving tips amp tricks or information on typical errors when using the information men tioned below this safety hint syseskcpu co EE 204077 June 1999 Introduction 1 A Introduction Memory Interfaces CPU speed Real time clock The SYS68K CPU 60 is a high performance single board computer pro viding an A32 D32 VMEbus interface including DMA It is based on e the 68060 CPU the FORCE gate array FGA 002 and the VMEbus The SYS68K CPU 60 provides up to 32 Mbyte DRAM on board field upgradable Up to 128 Mbyte DRAM are available with the SYS68K MEM 60 extension module Up to 2 Mbyte user SRAM up to 512 Kbyte local SRAM with battery backup up to 8 Mbyte system PROM and up to 1 Mbyte boot PROM are available The s
187. pt request IRQ on level 7 via the FGA 002 The abort key is activated in UP position and deactivated in DOWN position This allows to implement an abort of the current pro gram to trigger a self test or to start a maintenance program For information on enabling the key see SW7 2 on page 12 DIAG Software programmable hexadecimal display for di agnostics It can be accessed via the CIO2 port B data register A R X E SYS68K CPU 60 Page 15 Front Panel Table 4 Page 16 Installation Front panel features cont Device Description MODE 1 2 hexadecimal rotary switches each decoded with MODE 2 4 bit The status of the rotary switch can be read in the CIOI port A data register including MODE x status register Default for both rotary switches F16 RUN 68060 CPU status green normal operation red the processor is halted or reset is active BM VME busmaster LED green if the CPU board accesses the VMEbus as VMEbus master off otherwise SYSF SYSFAIL LED red if SYSFAIL is asserted from the FGA 002 off otherwise UL User LED Software programmable by the RIALTO Bridge configuration register BCR Possible status green or off SERIAL 1 2 standard 9 pin D Sub connectors for serial interface see section 2 7 Serial I O Ports SCC on page 17 SERIAL 2 ETHERNET 15 pin AUI Ethernet connector for thick wire Ethernet AUI or 802 3 10base5 see section 2 10 Ethe
188. r IMPORTANT Before erasing or programming the system PROM ensure that you do not destroy the VMEPROM image The VMEPROM image resides in the first 512 Kbyte of the system PROM starting at address FF00 00004 g and ending at FF08 0000j All 4 devices can be programmed simultaneously However due to power consumption each device should be erased separately Programming There are 2 more steps to be taken for programming the system PROM Both steps are automatically handled correctly by the software packaged with the SYS68K CPU 60 see section 6 5 3 FERASE Erase Flash Memories on page 137 and section 6 5 7 FPROG Program Flash Memories on page 141 1 A programming voltage Vpp of 12 V must be applied to the flash devices making up the system PROM Vpp is generated by the SYS68K CPU 60 and controlled via a register see table 14 CIOI port B data register on page 42 The Vpp generator is shared between the system PROM the user flash and the boot PROM 2 The device dependent communication sequence has to be performed on each of the 4 byte paths Boot PROM Device selection The boot PROM devices are installed in two 32 pin PLCC sockets J70 default socket 1 2770 for the default boot PROM device J71 optional and socket 2 J71 for the optional boot PROM device The selection of the boot PROM devices to be used is controlled by switch SW7 1 default OFF see page 12 e OFF Socket 1 0 512
189. rammable how long the CPU stays VMEbus master in spite of a pending bus request Programming of the ROR mode is described in the FORCE Gate Array FGA 002 User s Manual After every VMEbus access a 100 us timer within the FGA 002 starts running When the timer runs out the CPU board automatically releases its VMEbus mastership The purpose of the timer is to hold the VMEbus for a short time after every VMEbus transfer so that the overhead of VMEbus arbitration will be avoided if the CPU makes another VMEbus request within this time period The timer is only effective for CPU cycles to the VMEbus and not for cy cles initiated by the FGA 002 DMA controller In these cases it is restart ed after every VMEbus access but not before the ROR timer has expired Therefore the actual time in which the CPU board holds the bus is ap proximately equal to the programmed ROR delay time see above plus 100 us This function cannot be disabled Programming of the RAT mode is described in the FORCE Gate Array FGA 002 User s Manual The RBCLR mode is only effective for CPU cycles to the VMEbus and not for cycles initiated by the FGA 002 DMA controller The RBCLR function allows the VMEbus mastership release if an exter nal arbiter asserts the BCLR signal of the VMEbus This function then overrides the ROR function timing limitations R X E SYS68K CPU 60 Page 85 VMEbus Slot 1 Release When Done RWD Release on ACFAIL ACFAIL Hardwa
190. re Programming of the RBCLR mode is described in the FORCE Gate Ar ray FGA 002 User s Manual The DMA controller within the FGA 002 can also become VMEbus mas ter It always operates in transfer bursts maximum 32 transfers The bus is always released after completion of such a transfer burst The other bus release functions are for CPU mastership to the VMEbus only If the CPU board is programmed to be the ACFAIL handler for the VME bus system and if the ACFAIL signal from the VMEbus is asserted the CPU will not release the VMEbus if it is already the VMEbus master That is REC ROR RAT and RBCLR do not operate in this case If the board is not ACFAIL handler and the ACFAIL signal is asserted the board will release the VMEbus immediately 3 16 4 VMEbus Grant Driver If the CPU board detects itself being plugged in slot 1 see below it will automatically use bus grant level 3 BG3 and drive the 3 remaining bus grant signals BGO BG1 and BG2 to a high level 3 17 VMEbus Slot 1 IMPORTANT Page 86 The SYS68K CPU 60 may be used as system controller when plugged into slot 1 but the slot 1 functions see below are only enabled when the SYS68K CPU 60 is detected as slot 1 device The slot 1 functions are also called system controller functions Malfunction If not on an active backplane remove the jumper on the backplane connecting BG3IN and BG3OUT for the SYS68K CPU 60 slot assemble the jumpers for BGIN an
191. reakpoint should ay be skipped 684 WORD bptcocc of times the temp breakpoint is E already skipped aA 686 char bptcmd 11 temp breakpoint command 691 char outflag output messages yes 1 no 0 7 692 char namebn MAXNAME 8 Name buffer name 6BA char namebd MAXNAME 40 Name buffer data 782 WORD errcnt error counter for test xy 784 LWORD times timee start end time 78C LWORD pregs N REGS storage area of processor regs EJ 7F0 WORD tflag trace active flag 7F2 WORD tcount trace count a 7F4 WORD tacount active trace count Ef 7F6 WORD bpact break point active flag 7E8 LWORD savesp save VMEprom stack during GO T etc EJ TEC char VMEMSP 202 Master stack handle w care 8C6 char VMESSP 802 supervisor stack handle w care BE8 char VMEPUSP 802 vmeprom internal user stack F0A LWORD f fpreg 3 8 floating point data regs x F6A LWORD f fpcr FPCR reg xd F6E LWORD f fpsr FPSR reg f F72 LWORD f fpiar FPIAR reg F76 BYTE f save 0x3c FPSAVE for null and idle FB2 BYTE cleos 2 clear to end of screen parameter FB4 BYTE cleol 2 clear to end of line parameters 7 FB6 char u prompt 10 user defined prompt sign 7 FCO long c save save Cache control register FC4 long exe cnt execution count y FC8
192. register of the RIALTO bus bridge see section 3 8 7 Cache Coherence and Snooping on page 58 The DRAM is accessible from the 68060 CPU including burst mode support FGA 002 Gate Array DMA controller e SCSI 53C720SE DMA controller including burst mode support Ethernet LAN AM 79C965A DMA controller and also from other VMEbus masters Burst mode support is always enabled Advanced on board memory con trol logic routes data to and from the 68060 CPU the SCSI controller and the VMEbus interface For every read cycle all 32 data and all 4 parity bits are read from the DRAM regardless of size byte word long word or cache line and re gardless of master 68060 CPU DMA controllers or VMEbus The 32 data and 4 parity bits are stored in the memory controller Parity is regenerated in the memory controller and compared to the parity bits read from memory If a parity error is detected for an accessed byte a bus error acknowledge is generated and a parity error flag is set in the memory controller see table 27 Memory diagnostic register MDR on page 55 svsesk ceu so RSE 204077 June 1999 last documentation change with SY S6BK CPU 60 PCB Rev 0 1 Hardware 3 8 1 A DRAM write Write posting Register Set Table 25 DRAM Write cycles are handled differently In case of a long word access the DRAM can be written immediately including the parity info generated by the memory contro
193. ring hardware initialization the following steps are performed Leave boot mode of the FGA 002 and the RIALTO bus bridge map boot PROM from 0000 0000 to FFEO 0000 Setup the VMEbus A32 slave window A24 slave window as well if enabled see section 8 2 12 SETUP Change Initialization Values on page 193 The snooping window size is also set Per default the VMEbus window is configured to enable VMEbus accesses to the entire memory For the SCSI device the EA and the FA bit in the DCNTL register are set to 1 e Relocate the LAN device to FFF0 0000 After hardware initializa tion the LAN device still is in 16 bit mode Enable FGA 002 arbiter if the CPU board is system controller R X E SYS68K CPU 60 Page 179 Boot Sequence FGA Boot IMPORTANT Any program starting after FGA Boot has to initialize the CPU registers e g PCR CACR anew as there is no default setting for them when FGA Boot exits Figure 10 Boot up procedure 7 seg Actions State display undef The Boot ROM at address FFE0 0000 6 is mapped to 0000 000046 The CPU loads its initial stack pointer SSP and initial program counter PC from locations 046 and 446 undef Install exception handler and execute C startup code undef Check reset condition and leave FGA 002 s boot mode Now the Boot ROM resides at address FFE0 0000 6 Check if Abort Switch is asserted gt abort off Re
194. rnet LAN 10base2 on page 23 as factory option Cheapernet 802 3 10base2 is available via an SMB connector instead of the Ethernet AUI interface An adapter from SMB type to BNC type connector is available from FORCE COMPUTERS syseskcpu co RSE 204077 2 3 June 1999 Installation SYS68K CPU 60 Parameters and 16 bit Timers CIO 2 6 SYS68K CPU 60 Parameters and 16 bit Timers CIO Devices 2 CIO Z8536 Frequency 4 MHz Package 44 pin PLCC Accessible from 68060 CPU Access address for device 1 FF80 0C001 for device 2 FF80 0E004 Port width Byte Interrupt request level Software programmable FGA 002 interrupt Local IRQ 4 Configurable Via the two CIO Z8536 devices several parameters can be configured or parameters read respectively front panel rotary switch setting front panel status dis play on board and MEM 60 DRAM size code CPU board code avail ability of VME A24 extension AUX DMA direction programming voltage Vpp configuration of FDC 37C65C control signals ID ROM serial EEPROM and the six 16 bit timers Timers Six 16 bit timers with a resolution of 500 ns are available 2 7 Serial I O Ports SCC Device SCC AM 85C30 Frequency 8 MHz 14 7456 MHz Package 44 pin PLCC Accessible from 68060 CPU Access address FF80 20001 Port width Byte Interrupt request level Software programmable FGA 002 interrupt Local IRQ 5
195. rupts from the CIO1 Z8536 an error will be displayed This ensures that VMEPROM can initialize the CIO1 Z8536 properly and the external interrupts from the CIO are working During this process all contents of the memory are cleared Example SELFTEST VMEPROM Hardware Selftest I O test passed Memory test passed Clock test iw passed 2 6 6 Installing a New Hard Disk Using FRMT and INIT Page 146 This section provides an example how to use the rRMT and the INIT com mand to install a new hard disk The FRMT command of VMEPROM may be used to set all hard disk parameters to format the Winchester e and to divide the disk into logical partitions Before starting the FRMT command the number of the last logical block of the Winchester must be known The number of physical blocks per track must be 32 the number of bytes per sector must be 256 svsesk ceu so RSE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 VMEPROM IMPORTANT gt z Installing a New Hard Disk Using FRMT and INIT The number of heads and the number of cylinders may be calculated by using the following equation of heads of cylinders blocks track of last logical block The SCSI ID must be 0 1 or 2 and the maximum number of heads is 16 The number of large and floppy partitions can be defined by the user Example Formatting a CDC 94211 5 Winchester
196. ry configuration register on page 54 Setting the RESETOUT bit has the same effect as a reset generated by the watchdog timer 5 68060 CPU reset call A 68060 CPU reset call is triggered when the 68060 CPU addresses the FGA 002 at FFD0 0E00 either in a read or in a write cycle The 68060 CPU reset call has the same effect as toggling the reset key 6 68060 CPU reset instruction The 68060 CPU reset instruction is designed to reset peripherals under program control without resetting the 68060 CPU itself This instruction is fully supported by the CPU board The reset instruction triggers the reset generator and resets all on board modules and chips driving reset to low The external logic enters boot mode Therefore the shared memory at location 0000 00004g will be disabled causing a failure of the program exe cuted from the shared RAM To run a reset instruction correctly the reset instruction has to be executed from a local bus memory for example the local SRAM Also the execution from the system PROM is possible but be sure that no DRAM access is necessary e g no stack operation After the reset instruction one of the RIALTO bus bridge registers has to be accessed to re enable the shared memory If VMEbus SYSRESET input is asserted before the reset generated by a reset instruction is finished the processor will still not be reset because of lockout logic R X E SYS68K CPU 60 Page 101 Reset
197. ry controller register map Address Register name and access FFF4 000846 Memory configuration reg MCR R W see table 26 MCR memory configuration register on page 54 FFF4 000A Watchdog retrigger reg WDR WO FFF4 000B g Memory diagnostic reg MDR RO see table 27 Memory diagnostic register MDR on page 55 Watchdog retrigger register WDR FFF4 000A 6 Bit 7 6 5 4 3 2 1 0 reserved RE Value START RESTART RESTART retriggers the watchdog timer WO 0 Retriggers the watchdog timer 1 Noaction is taken Page 49 RIALTO Bus Bridge Hardware 3 6 RIALTO Bus Bridge 3 6 1 3 6 2 Page 50 Revision of RIALTO bus bridge Register Set Table 22 The bus bridge is intended to maximize the performance of the CPU board As data and address bridge between the 68040 type CPU bus and the FGA 002 interface chip the RIALTO bus bridge is especially de signed to support fast VMEbus master slave block transfers After power up the SNOOP 2 0 bits in the bridge configuration regis ter BCR show the revision of the RIALTO bus bridge see section 3 6 2 Bridge Configuration Register on page 50 The following register map shows all internal registers and their corre sponding register addresses RIALTO bus bridge register map Offset addr Reset value Register name FFF4 0000 0000 0000 reserved
198. s 4 21 locumentation ch 204077 June 1999 last d FGA Boot Debugger Commands target IP f IP Internet Protocol number of the CPU board server IP IP Internet Protocol number of the server where the file is located Example File test is located in the t t pboot directory of a UNIX system It contains the text This is a test The configuration file etc ethers has an entry with the board s Ethernet number and the name of the board its IP address for example 0 80 42 3 88 88 boardl FORCI PAC LAN control Transmi Transmi LAN control l Transmi Reception of tting TFTP REQUEST BY FORCI 00100000 FORCI E BOOT E BOOT NETLOAD test 100000 00 80 42 03 88 88 ler at address FEF80000 set to Ethernet 00 80 42 03 88 88 tting RARP REQUEST ler at address FEF80000 set to Ethernet 00 80 42 03 88 88 tting RARP REQUEST RARP REPLY loaded 00100000 0010000E 15 bytes E BOOT MD 100000 10 54 68 69 73 20 69 73 20 61 20 74 65 73 74 0a 00 This is a test 8 2 11 NETSAVE Save Data via Network to File Format IMPORTANT Param A z eters NETLOAD filename start address end address ethernet number target IP server IPf NETSAVE filename start address ethernet number The NETSAVE command saves the specified memory region into a file lo cated in a server system Similar to NETLOAD this is done via the TFTP protocol
199. s see section 3 15 VMEbus Interface on page 75 The SYS68K CPU 60 provides on board shared DRAM see section 3 8 DRAM on page 52 system PROM see section 3 10 System PROM on page 62 boot PROM see section 3 11 Boot PROM on page 64 on board local SRAM with on board battery backup see section 3 13 Local SRAM on page 69 and optional on board user SRAM with on board battery backup see section 3 9 User SRAM factory option on page 61 on board real time clock with on board battery backup see section 3 14 Real Time Clock RTC 72423 on page 71 Ethernet interface available at the front panel see section 3 21 Ether net LAN AM 79C965A on page 96 single ended SCSI interface and optional wide fast SCSI instead of the standard SCSI interface see section 3 19 SCSI 53C720SE on page 92 e floppy interface see section 3 20 Floppy Disk FDC 37C65C on page 94 two RS 232 serial I O ports see section 3 18 Serial I O SCC AM 85C30 on page 89 The following devices are collectively referred to as DMA controllers of the SYS68K CPU 60 because they themselves provide an on chip DMA controller FGA 002 Gate Array SCSI 53C720SE and Ethernet LAN AM 79C9654A Hardware Front panel The front panel of the SYS68K CPU 60 provides an Ethernet port see section 3 21 Ethernet LAN AM 79C965A on page 96 and 2 serial ports see section 3 18
200. s a functional overview figure 2 highlights the locations of the important SYS68K CPU 60 components Figure 1 Block diagram of the SYS68K CPU 60 RIALTO bus bridge DRAM 060 020 on board Memory 4 MEM 60 Memory Control VL SCSI adaption SCSIbus Termin Ethernet VESA local bus VL bus gt X E SYS68K CPU 60 z FLXI bus 020 bus FGA 002 I O bus AUX DMA RTC FDC Local SRAM NVRAM Boot PROM CIO User flash local flash 4 LEDs Hex Displ 2 rotary sw Reset key Abort key SCSIbus Serial I O l and 2 Page 9 Installation Prerequisites and Requirements Installation Figure 2 Location diagram of the SYS68K CPU 60 schematic Front panel 10Base2 SERIAL A R 1 2 1 B E O7 SYSF o ORUN option L 1L unas V eG coos T ETHERNET MODE DIAG T 4 LEDs 2rotary Status switches display Ser O1 Ser I O 2 MEM 60 connector LC es ee DRAM Bank 2 SWI2 C 8 of 9 Ethernet Memory control SCC Watchdog timer System PROM JE CIO CIO RIALTO 1 A bus bridge NVRAM User flash 1 2 Boot PROM P2 connector P1 connector SW5 SW6 User SRAM DRAM Ba
201. sed If the SYS68K CPU 60 does not detect slot 1 the request level is switch selectable by SW6 3 and SW6 4 default OFF OFF level 3 BR3 see page 12 For a detailed description of the slot 1 detection see section 3 17 VME bus Slot 1 on page 86 R X E SYS68K CPU 60 Page 83 VMEbus Arbitration IMPORTANT Hardware Note that the selection of the VMEbus request level has no effect upon the VMEbus arbiter located in the FGA 002 3 16 3 VMEbus Release Modes VMEPROM Table 48 Page 84 The CPU board provides several software selectable VMEbus release modes to release VMEbus mastership The bus release operation is inde pendent of the fact whether the on board VMEbus arbiter is enabled and independent of the VMEbus arbitration level Easy handling and use of the VMEbus release modes is provided by the FGA 002 Before the bus is released a read modify write RMW cycle in progress is always completed The VMEPROM ARB command sets the VMEbus release modes see section 6 5 1 ARB Set the Arbiter of the CPU Board on page 136 Each row of the following table lists which of the VMEbus release modes described below can be used simultaneously ROR and RAT are always enabled Valid configurations for VMEbus release modes Release Config mode Enabled VME is released l REC Yes Every cycle ROR Always RAT Always RBCLR Don t care 2 REC No On BRx active or after timeout ROR Always RAT A
202. sert queue 3894 char devt 2 NEV 10 delay events 3Bl6 int bect 32 basic screen command table y 3B56 int _xchi NCB channel buffer queue 3B66 char xchb NCB BPS channel buffers 4366 char xfsl NFS FSS file slots 4CE6 char _121k level 2 lock file prims evnt 120 4CE7 char _131k level 3 lock disk prims evnt 121 ACE8 long _drvl driver link list entry point E ACEC long util utility link list entry point ef 4CFO int rdkl NRD 4 1 RAM disk list F g E 8 z A CE SYS68K CPU 60 Page 161 Task Control Block Definitions Appendix to VMEPROM 7 4 Task Control Block Definitions define MAXARG 10 max argument count of the cmd line define MAXBP 10 max 10 breakpoints aye define MAXNAME 5 max 5 names in name buffer Rf define TMAX 64 Max number of tasks define ARGLEN 20 maximum argument length 4 special system flags for VMEPROM define SOMEREG 0x0001 display only PC A7 A6 A5 vy define T DISP 0x0002 no register display during trace TC gt 1 oe define T_SUB 0x0004 trace over subroutine set xu define T ASUB 0x0008 trace over subroutine active x define T RANG 0x0010 trace over range set 7 define REG INI 0x0020 no register initialization if set define RE DIR 0x0040 output redirection into file and x console at the same time Xy the registers are st
203. ses of a bus timer to terminate VME transfers gener ating a bus error when no acknowledge can be detected after a timeout period In addition to the FGA 002 bus timer the SYS68K CPU 60 provides a VMEbus timer This timer can only be enabled when the CPU board pro vides system controller functions The SYS68K CPU 60 VMEbus timer is controlled by the timer within the memory controller The timeout peri od can be configured by the register for the timer within the memory con troller see section 3 8 2 Memory Configuration Register on page 54 3 18 Serial I O SCC AM 85C30 A Clock inputs IRQ SCC base address Driver modules FH 00x The 2 serial I O channels are implemented by using 1 SCC AM 85C30 serial communication controller see data sheet SCC AM 85C30 in section 5 The operating mode and data format of each channel can be programmed independently from each other The peripheral clock inputs of the SCC are driven by a 8 MHz clock A chip external on board quartz provides the 14 7456 MHz clock necessary for baud rates greater than 9600 Baud The interrupt request of the SCC is connected to the LIRQ5 input of the FGA 002 It is low active To interrupt acknowledge cycles of the 68060 CPU the SCC provides its own vector Instead the FGA 002 can be pro grammed to provide the vector FF80 2000y To easily vary the serial I O interfaces according to the application s needs FORCE COMPUTERS has developed RS 2
204. ta 1 O SCSI Data 2 SCSI Data 3 SCSI Data 4 SCSI Data 5 SCSI Data 6 SCSI Data 7 4 SCSI DPA GND GND GND TERMPWR GND GND SCSI ATN GND SCSIBSY SCSI ACK SCSI RST SCSI MSG SCSI SEL O SCSI CD SCSI REQ SCSIIO O n c Serial CTS _2 n c Serial RXD _2 n c Serial RTS 2 Serial TXD _1 O Serial RTS _1 Serial CTS 1 O Serial RXD 1 O 1 10 15 20 25 30 32 c Q FDC RPM G FDC HLOAD FDC EJECT G FDC DSEL2 G FDCINDEX G FDC DSELI G FDC DSEL2 G FDC DSELI G FDC MOTOR G FDC DIREC G FDC STEPX G FDC WDATA G FDC WGATE G FDC TRK00 G FDC WPROT G FDC RDATA G FDC SDSEL G FDC DCHG G ne G ne G n c SCSI Data 8 G SCSI Data 9 QG ne SCSI Data 10 G ne SCSI Data 11 Q Serial RXD _2 SCSI Data 12 G Serial TXD _2 SCSI Data 13 Q Serial RTS _2 SCSI Data 14 G Serial CTS _2 SCSI Data 15 Q Serial TXD 2 SCSI DPB G Serial TXD 1 G Serial RTS 1 G Serial CTS 1 G Serial RXD _1 svsesk ceu so WEE Installation 204077 2 3 June 1999 Installation VMEbus P2 Connector Pinout Figure 5 P2 connector pinout with serial I O config for RS 485 A C SCSI Data 0 Q 1 Q
205. the FGA 002 s LIRQ7 syseskcpu co WEE 204077 June 1999 last documentation change with SYS68K CPU 60 PCB Rev 0 1 Hardware A Register Access IMPORTANT Table 56 Ethernet LAN AM 79C965A input The FGA 002 has to be programmed to be level sensitive and to supply the vector because the AM 79C9654 has no provision to do so After initialization the AM 79C9654 registers are selected by writing the corresponding register number to address FFF0 00104g Thereafter the register is accessible at address FFF 0 00124 Both addresses must be accessed with word size instructions The AM 79C9654 can be used in two different modes 16 bit and 32 bit mode Regardless of being in 16 bit or 32 bit mode the Ethernet address is to be initialized in byte swapped order as documented in table 57 Exam ple word swapped init block for LAN AM 79C965A in 16 bit mode on page 100 16 bit mode FGA Boot relocates the AM 79C965A to address FFF0 000016 and leaves it in the 16 bit mode If you use the AM 79C965A in 16 bit mode be aware of the fact that in contrast to the statements in the datasheet all registers are word swapped see the 2 examples below 32 bit mode If you use the AM 79C965A in 32 bit mode remember that no reg isters are word swapped For further information on the 32 bit mode see data sheet LAN AM 79C965A in section 5 Ethernet controller address layout 16 Bit mode Address D
206. the VMEbus address ranges and their associated address and data bus widths in detail Bus widths related to address ranges VMEbus master interface Address Start End bus width Data bus width Xxxx 0000 6 FAFF FFFFi A32 Programmable xxxx depends on the shared RAM capacity FB00 0000 FBFE FFFFi A24 Programmable FBFF 0000 FBFF FFFFic A16 Programmable FC00 000046 FCFE FFFFig A24 D16 FCFF 0000 FCFF FFFF s A16 D16 svsesk ceu so RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware VMEPROM Table 45 Table 46 A VMEbus Interface For further information on snooping and read modify write support see section 3 8 7 Cache Coherence and Snooping on page58 and section 3 8 9 DRAM Access via the VMEbus on page 60 VMEPROM automatically reads the setting of the front panel rotary switches to select the data bus size of the VMEbus after reset or power up see section 6 2 3 Rotary Switches on page 128 Thereby VMEPROM allows easy installation of additional memory boards with known data sizes during user program or operating system start Additionally the VMEPROM MEM command can be used to set up the data bus transfer size of the programmable address ranges see section 6 5 10 MEM Set Data Bus Width of the VMEbus on page 143 VMEbus master transfer cycles defined for D32 data bus width D31
207. the WR5 register as shown in table 51 Bit 7 of the WR5 register on page 90 The bit must be cleared to enable the RS 485 receiver If set to 1 the receiver is disabled For details how to write an SCC register see data sheet SCC AM 85C30 in section 5 Bit 7 of the WRS register DTR bit 7 Description 0 Receiver enabled 1 Receiver disabled The DE signal on pin 16 of the FH 007 hybrid is connected to the Gener al Purpose I O GPIO port of the SCSI 53C720SE controller GPIO 0 pin controls the RS 485 transmitter enable TX enable function for the serial interface channel 1 and GPIO 1 pin controls the RS 485 TX enable function for the serial interface channel 2 By default the GPIO pins GPIO 0 and GPIO 1 of the SCSI 53C720SE controller are configured as inputs powerup default svsesk ceu so RSE 204077 June 1999 last documentation change with SYS68K CPU 60 PCB Rev 0 1 Hardware A R X E SYS68K CPU 60 Table 52 Serial I O SCC AM 85C30 To realize the RS 485 interface 2 steps are necessary The corresponding GPIO 7 pin n 0 1 must be configured as output via the General Purpose Control GPCNTL register of the SCSI 53C720SE according to table 52 SCSI 53C720SE GPCNTL register on page 91 The RS 485 interface driver must program the TX enable function via the General Purpose GPREG register of the SCSI 53C720SE accord ing to table 53 SCSI 53C720SE GPREG register on page 91
208. ttery buff ered SRAM To change any value a new one has to be entered in binary format If only a cR is entered no change will be made To step back wards a minus has to be entered If a or ESC is given the Fea com mand returns to the shell Page 138 svsesk cPU so R LE 204077 June 1999 last documentation change with VM EPROM 32 Vers 2 85 VMEPROM VMEPROM Commands IMPORTANT The command uses cursor positioning codes of the selected terminal Use the sr command to set the correct terminal Example FGA gt gt gt Setup for FGA 002 BOOTER lt lt lt Register FGA offset value in SRAM changed value SPECIAL 0420 00100000 00100000 CTL 01 0238 00000111 00000111 CTL 02 023C 00001011 00001011 CTL 05 0264 00001100 00001100 CTL 12 032C 00110011 00110011 CTL 14 0354 01111110 01111110 CTL_15 0358 01000000 01000000 CTL_16 035C 00100000 00100000 BX 00 0000 00000000 BX 01 0004 00000000 BX 02 0008 00000000 BX 03 000C 00000000 BX 04 0010 00000000 BX 05 0014 00000000 BX 06 0018 00000000 BX 07 001C 00000000 E 6 5 5 FLUSH Set Buffered Write Mode Format FLUSH FLUSH FLUSH ON FLUSH OFF This command flushes all modified hashing buffers for disk writing or enables disables buffered write mode for the local SCSI controller If no argument is entered all modified hashing buffers are flushed If the argument ON or OFF is given the buffered
209. ut OFF OFF enabled ON disabled SWO9 4 VMEbus SYSRESET input OFF OFF enabled ON disabled SW10 1 Configuration of serial port 2 depending ON OFF on SW10 1 SW12 2 and SW12 3 i D 20 E Switch Configuration 3c c 10 1 12 2 12 3 s i OFF OFF OFF RS 232 async ON ON OFF RS 232 sync slave OFF OFF ON RS 232 sync master ON ON ON RS 422 ON ON OFF RS 485 SW10 2 Configuration of serial port 1 depending OFF on SW10 2 SW12 1 and SW12 4 Switch Configuration 10 2 12 1 12 4 OFF OFF OFF RS 232 async ON OFF ON RS 232 sync slave OFF ON OFF RS 232 sync master ON ON ON RS 422 ON OFF ON RS 485 SW10 3 System PROM write protection OFF OFF writing enabled ON write protected SW10 4 User flash write protection OFF OFF writing enabled ON write protected A R X E SYS68K CPU 60 Page 13 Switch Settings Page 14 Installation Table 3 Switch settings cont Name and default setting Description SWII 1 SCSI termination ON OFF 1 SWII 1 SW11 2 SCSI termination for L3 2c co SWIL2 OFF OFF wide and 8 bit SCSI e ES MEE OFF ON only upper 8 bits ori s of wide SCSI ON OFF only 8 bit SCSI ON ON none SW11 3 reserved must be OFF OFF SW11 4 reserved must be OFF OFF SW12 1 Configuration of serial port 1 depending ON OFF on SW10 2 SW12 1 and SW12 4 see 1 lt SW10 2 p F SWI2 2 Configuration of serial
210. utine Format GO address The co command calls a subroutine at the specified address To get back into the debugger an RTS instruction must be executed by the subroutine Example FORCE BOOT AS 0 00000000 ORI B 0 D0 RTS 00000002 ORI B 0 D0 FORCE BOOT gt GO 0 FORCE BOOT gt 8 2 2 LO Load S Records to Memory Format Page 188 LO host commands LO offset host commands LO V host commands LO offset V host commands LO E The Lo command allows to load S records from the console port into memory and to verify the memory contents The optional parameter host commands allows to specify a list of com mands that will be sent to the host to initiate the data transfer e g cat testfile Format 1 of the command is a standard download Data will be loaded to the absolute addresses as specified by the S records Format 2 contains a parameter offset that specifies the value that is add ed to the absolute addresses of the S records This allows to modify the storage address while downloading Format 3 and 4 are the same as previously described except that no data will be loaded to memory but a comparison takes place between the memory contents and the S record data This allows to verify the data Format 5 displays the number of errors that occurred during the last download syseskcpu co EE 204077 June 1999 last documentation change with FGA Boot Vers 4 21 FGA Bo
211. wie E pide 15 2 6 SYS68K CPU 60 Parameters and 16 bit Timers CIO eese 17 2 7 Serial I O Ports SCC 0 ccc ccc cc ec cece cece he hh hh nnn 17 2 8 SCBL I do wire deeb ce e AIR ehevV er a Rue ea Nr er Sie eis le OMe wow Es 21 2 9 Floppy Disk FDC lllo ooh ied eb bres er DE ee ee 23 2 10 Ethernet LAN 88 6625 pee ARE Bi pie Rew es OD ee Biel ee Rie err eas 23 2 11 VMEbus P2 Connector Pinout 0 ccc ccc cece ee ee ehh nnn 24 2 12 SYS68K IOBP T bie oe erar hie aw Serb wa gonna err IRR RR ehem geile Suwa se cn ete aUe 28 2 13 Testing the CPU Board Using VMEPROM ccc cece cece cece nnn n 30 3 Hardware o1 lle s Sas Siac ex ecrit eR FE eiu pes epar Bee 33 3 1 SYS68K CPU 60 Memory Map cece ccc cece cece cece cece cece e scenes 36 3 0 SYS68K CPU 60 Interrupt Map cc ccc ccc cece hh hh hn nan 38 A R X E SYS68K CPU 60 Pagei Contents 3 3 3 4 3 5 3 6 3 7 3 8 3 9 Page ii SYS68K CPU 60 Parameters and Timers CIO Z8536 0 ce cece ee cece 40 3 3 1 MEM 60 DRAM Capacity and CIO Timer3 0 000005 41 3 3 2 Flash Vpp Floppy Disk Control and CIO1 Timer 2 esses 42 3 3 3 MODE x Rotary Switch Setting 2 0 eee eee 43 3 3 4 On board DRAM Capacity and Automatic A24 Expansion 44 3 3 5 Board ID and DIAG Display 0 cee eee nee 44 3 3 6 A24 to A32 Address Translation llle eee 4
212. witch set ting Thereby the following options are selectable FH 002 installed RS 232 asynchronous RS 232 synchronous master RS 232 synchronous slave e FH 003 FH 422T installed RS 422 FH 007 installed RS 485 The following switches apply to the port configuration e port 1 SW10 2 SW12 1 SW12 4 see SW10 2 on page 13 e port 2 SW10 1 SW12 2 SW12 3 see SW10 1 on page 13 Device SCSI 53C720SE Frequency CPU bus frequency Package PQ160 Accessible from 68060 CPU Access address FFF8 00004 Port width Long Interrupt request level Software programmable FGA 002 interrupt Local IRQ 6 The SCSI 53C720SE provides an 8 bit SCSI interface which is routed to the VMEbus P2 connector The 8 bit SCSI interface at the VMEbus P2 is pinout compatible to the CPU 30 and CPU 40 with EAGLE 01 or EA GLE 10 11 The local bus interface is 32 bit wide and able to transfer data via the DMA controller of the SCSI 53C720SE R X E SYS68K CPU 60 Page 21 SCSI Page 22 Factory option IMPORTANT SCSI bus terminator power Installation The active termination can be selected by means of switches see SW11 2 and SW11 1 on page 14 TERMPWR is supported A 16 bit single ended SCSI interface wide SCSI which is routed to the VMEbus P2 connector is available as factory option see section 2 11 VMEbus P2 Connector Pinout on page 24 The wide SCSI
213. with each handshake The 53C720SE also supports synchro nous operation for the data transfer see data sheet SCSI 53C720SE in section 5 Floppy Disk FDC 37C65C CAUTION Floppy disk connectors and pinouts Features of the FDC 37C65C The CPU board contains a single chip floppy disk controller the FDC37C65C see data sheet FDC 37C65C in section 5 The FDC 37C65C is connected to the DMA controller of the FGA 002 Damage of components There are floppy disk drives that provide means to connect the floppy disk drive frame electrically with DC ground e g by inserting a jumper on the floppy disk drive Before installing a floppy disk drive always make sure that the floppy disk drive s frame is not electrically connected with DC ground The installed driver receiver circuits allow direct connection of 3 1 2 and 5 1 4 floppy disk drives An I O back panel can be plugged onto the rear side of the backplane to interface to mass storage devices see section 2 11 VMEbus P2 Connec tor Pinout on page 24 Built in data separator Built in write precompensation e 128 256 512 or 1024 byte sector lengths e 3 1 2 or 5 1 4 single and double density Programmable stepping rate 2 to 6 ms 2 data rate selection options 16 MHz and 9 6 MHz controlled via the data rate selection register syseskcpu co RSE 204077 June 1999 last documentation change with SYS6BK CPU 60 PCB Rev 0 1 Hardware gt

SYS68K/CPU-60 Technical Reference Manual

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