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MPC7455 RISC Microprocessor Hardware Specifications

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1. Notes 1 Functional and tested operating conditions are given in Table 4 Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage to the device 2 Caution Vin must not exceed OVpp or GVpp by more than 0 3 V at any time including during power on reset 3 Caution OVpp GVpp must not exceed Vpp AVpp by more than 2 0 V during normal operation this limit may be exceeded for a maximum of 20 ms during power on reset and power down sequences 4 Caution Vpp AVpp must not exceed OVpp GVpp by more than 1 0 V during normal operation this limit may be exceeded for a maximum of 20 ms during power on reset and power down sequences Vig may overshoot undershoot to a voltage and for a maximum duration as shown in Figure 2 BVSEL must be set to 0 such that the bus is in 1 8 V mode BVSEL must be set to HRESET or 1 such that the bus is in 2 5 V mode L3VSEL must be set to 3HRESET inverse of HRESET such that the bus is in 1 5 V mode L3VSEL must be set to 0 such that the bus is in 1 8 V mode 0 L3VSEL must be set to HRESET or 1 such that the bus is in 2 5 V mode Qoo O 0 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 10 Freescale Semiconductor Figure 2 shows the undershoot and overshoot voltage on the MPC7455 OVpp GVpp 20 Electrical and Thermal Ch
2. Microarchitectural Specs MPC7455 MPC7445 MESE yas MPC7400 MPC7410 Scalar floating point unit In Order In Order In Order Branch Processing Resources Prediction structures BTIC BHT Link Stack BTIC BHT Link Stack BTIC BHT BTIC size associativity 128 Entry 4 Way 128 Entry 4 Way 64 Entry 4 Way BHT size 2K Entry 2K Entry 512 Entry Link stack depth 8 8 None Unresolved branches supported 3 3 2 Branch taken penalty BTIC hit 1 1 0 Minimum misprediction penalty 6 6 4 Execution Unit Timings Latency Throughput Aligned load integer float vector 3 1 4 1 3 1 3 1 4 1 3 1 2 1 2 1 2 1 Misaligned load integer float vector 4 2 5 2 4 2 4 2 5 2 4 2 3 2 3 2 3 2 L1 miss L2 hit latency 9 Data 13 Instruction 9 Data 13 Instruction 9 11 1 SFX aDd Sub Shift Rot Cmp logicals 1 1 1 1 1 1 Integer multiply 32 x 8 32 x 16 32 x 32 3 1 3 1 4 2 3 1 3 1 4 2 2 1 3 2 5 4 Scalar float 5 1 5 1 3 1 VSFX vector simple 1 1 1 1 1 1 VCFX vector complex 4 1 4 1 3 1 VFPU vector float 4 1 4 1 4 1 VPER vector permute 2 1 2 1 1 1 MMUs TLBs instruction and data 128 Entry 2 Way 128 Entry 2 Way 128 Entry 2 Way Tablewalk mechanism Hardware Software Hardware Software Hardware Instruction BATs data BATs 8 8 4 4 4 4 L1 I Cache D Cache Features Size 32K 32K 32K 32K 32K 32K Associativity 8 Way 8 Way 8 Way Locking granularity Way Way Full Cache Parity on cache Word Word None Parity on D cache Byte Byte None Number of D cache m
3. CtscrK 4 ns 5 6 Data and ti acLDV 0 60 0 40 0 20 0 00 7 parity Valid times ti scHov tis cLK 4 tis cLK 4 tis cuk 4 tts cuk 4 ns 5 7 All other 0 80 0 60 0 40 0 20 outputs Output hold tiscupx tis cuk 4 m lis ciK 4 z tL3_cLK 4 tis ciK 4 gt ns 5 6 times Data tiscipx 0 40 0 60 0 80 1 00 7 and parity Output hold tiscuox tia cu k 4 lia _ciK 4 tia cuk 4 lis ciK 4 ns 5 7 times All 0 20 0 40 0 60 0 80 other outputs L3_CLK to tLacLpz lia cLK 2 lia ciK 2 lia _ciK 2 tia ciK 2 ns high impedance Data and parity MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 23 Electrical and Thermal Characteristics Table 12 L3 Bus Interface AC Timing Specifications for MSUG2 continued At recommended operating conditions See Table 4 All Speed Grades 8 Parameter Symbol L3OH0 0 L3OH1 0 L3OH0 0 L3OH1 1 L3OH0 1 L3OH1 0 L3OH0 1 L3OH1 1 Unit Notes Min Max Min Max Min Max Min Max L3_CLKto tuscHoz lia cLk 4 tia cik 4 tis cuK 4 lis ciK 4 ns high 2 0 2 0 2 0 2 0 impedance All other outputs Notes 1 2 Rise and fall times for the L3 CLK output are measured from 20 to 80 of GVpp For DDR all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the ris
4. Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor Q hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for
5. 733MHz 867 MHz 933 MHz 1 GHz Typical 7 6 7 6 7 6 7 6 W 1 3 Deep Sleep Mode PLL Disabled Typical 7 3 7 3 7 3 7 3 W 1 3 Notes 1 These values apply for all valid processor bus and L3 bus ratios The values do not include I O supply power OVpp and GVpp or PLL supply power AVpp OVpp and GVpp power is system dependent but is typically lt 5 of Vpp power Worst case power consumption for AVpp 3 mW 2 Maximum power is measured at nominal Vpp see Table 4 while running an entirely cache resident contrived sequence of instructions which keep the execution units with or without AltiVec maximally busy 3 Typical power is an average value measured at the nominal recommended Vpp see Table 4 and 65 C in a system while running a typical code sequence 4 Doze mode is not a user definable state itis an intermediate state between full power and either nap or sleep mode As a result power consumption for this mode is not tested 5 2 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC7455 After fabrication functional parts are sorted by maximum processor core frequency as shown in Section 5 2 1 Clock AC Specifications and tested for conformance to the AC specifications for that frequency The processor core frequency is determined by the bus SYSCLK frequency and the settings of the PLL_CFG 0 4 signals Parts are sold by maximum processor core frequency see Section 11 Orde
6. Cl R1 Low Output BVSEL 8 CKSTP IN F3 Low Input BVSEL CKSTP OUT K6 Low Output BVSEL CLK OUT N1 High Output BVSEL D 0 63 AB15 T14 R14 AB13 V14 U14 AB14 High 1 0 BVSEL W16 AA11 Y11 U12 W13 Y14 U13 T12 W12 AB12 R12 AA13 AB11 Y12 V11 T11 R11 W10 T10 W11 V10 R10 U10 AA10 U9 V7 T8 AB4 Y6 AB7 AA6 Y8 AA7 W8 AB10 AA16 AB16 AB17 Y18 AB18 Y16 AA18 W14 R13 W15 AA14 V16 W6 AA12 V6 AB9 AB6 R7 R9 AA9 AB8 W9 DBG V1 Low Input BVSEL DP 0 7 AA2 AB3 AB2 AA8 R8 W5 U8 AB5 High y o BVSEL DRDY T6 Low Output BVSEL 4 DTI 0 3 P2 T5 U3 P6 High Input BVSEL 13 EXT QUAL B9 High Input BVSEL 9 GBL M4 Low y o BVSEL MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor Table 16 Pinout Listing for the MPC7455 483 CBGA Package continued Pinout Listings Signal Name Pin Number Active VO VF Select Notes GND A22 B1 B5 B12 B14 B16 B18 B20 C3 N A C9 C21 D7 D13 D15 D17 D19 E2 E5 E21 F10 F12 F14 F16 F19 G4 G7 G17 G21 H13 H15 H19 H5 J3 J10 J12 J14 J17 J21 K5 K9 K11 K13 K15 K19 L10 L12 L14 L17 L21 M3 M6 M9 M11 M13 M19 N10 N12 N14 N17 N21 P3 P9 P11 P13 P15 P19 R17 R21 T13 T15 T19 TA T7 T9 U17 U21 V2 V5 V8 V12 V15 V19 W7 W17 W21 Y3 Y9 Y13 Y15 Y20 AA5 AA17 AB1 AB22 GVpp
7. Electrical and Thermal Characteristics Table 5 provides the package thermal characteristics for the MPC7455 Table 5 Package Thermal Characteristics 5 Value Characteristic Symbol Unit Notes MPC7445 MPC7455 Junction to ambient thermal resistance natural Roa 22 20 C W 1 2 convection Junction to ambient thermal resistance natural RgJMA 14 14 C W 1 3 convection four layer 2s2p board Junction to ambient thermal resistance 200 ft min Ro MA 16 15 C W 1 3 airflow single layer 1s board Junction to ambient thermal resistance 200 ft min Reuma 11 11 C W 1 3 airflow four layer 2s2p board Junction to board thermal resistance Rous 6 6 C W 4 Junction to case thermal resistance Rec lt 0 1 lt 0 1 C W 5 Notes 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature airflow power dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal Per JEDEC JESD51 6 with the board horizontal 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package 5 Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the
8. The SYSCLK frequency and PLL_CFG 0 4 settings must be chosen such that the resulting SYSCLK bus frequency CPU core frequency and PLL VCO frequency do not exceed their respective maximum or minimum operating frequencies Refer to the PLL_CFG 0 4 signal description in Section 9 1 PLL Configuration for valid PLL_CFG 0 4 settings Rise and fall times for the SYSCLK input measured from 0 4 to 1 4 V Timing is guaranteed by design and characterization This represents total input jitter short term and long term combined and is guaranteed by design Relock timing is guaranteed by design and characterization PLL relock time is the maximum amount of time required for PLL lock after a stable Vpp and SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep mode Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power on reset sequence 6 The SYSCLK driver s closed loop jitter bandwidth should be 500 kHz at 20 dB The bandwidth must be set low to allow cascade connected PLL based devices to track SYSCLK drivers with the specified jitter Q G I Figure 3 provides the SYSCLK input timing diagram SYSCLK tsvscLk VM Midpoint Voltage OVpp 2 Figure 3 SYSCLK Input Timing Diagram MPC7455 RISC Microprocessor Hardware Specifications R
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10. selected based on high conductivity yet adequate mechanical strength to meet equipment shock vibration requirements There are several commercially available thermal interfaces and adhesive materials provided by the following vendors The Bergquist Company 800 347 4572 18930 West 78 St Chanhassen MN 55317 Internet www bergquistcompany com Chomerics Inc 781 935 4850 77 Dragon Ct Woburn MA 01888 4014 Internet www chomerics com MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 56 Freescale Semiconductor System Design Information Dow Corning Corporation 800 248 2481 Dow Corning Electronic Materials 2200 W Salzburg Rd Midland MI 48686 0997 Internet www dow com Shin Etsu MicroSi Inc 888 642 7674 10028 S 51st St Phoenix AZ 85044 Internet www microsi com Thermagon Inc 888 246 9050 4707 Detroit Ave Cleveland OH 44102 Internet www thermagon com The following section provides a heat sink selection example using one of the commercially available heat sinks 9 8 3 Heat Sink Selection Example For preliminary heat sink sizing the die junction temperature can be expressed as follows T T T Royc Reint Rosa X Pa where T is the die junction temperature T is the inlet cabinet ambient temperature T is the air temperature rise within the computer cabinet Roycis the junction to case thermal resistance Rogjntis the adhesive or interface material thermal resistance Ro
11. toL1 ECHO CLK 2 3 L3 clock jitter 50 ps 5 Notes 1 The maximum L3 clock frequency will be system dependent See Section 5 2 3 L3 Clock AC Specifications for an explanation that this maximum frequency is not functionally tested at speed by Freescale 2 The nominal duty cycle of the L3 output clocks is 50 measured at midpoint voltage 3 Maximum possible skew between L3_CLK0 and L3 CLK1 This parameter is critical to the address and control signals which are common to both SRAM chips in the L3 4 Maximum possible skew between L3_CLK0 and L3 ECHO CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 orlate write SRAM This parameter is critical to the write data signals which are separately latched onto each SRAM part by these pairs of signals 5 Guaranteed by design and not tested The input jitter on SYSCLK affects L3 output clocks and the L3 address data control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L3 timing analysis The clock to clock jitter shown here is uncertainty in the internal clock period caused by supply voltage noise or thermal effects This must be accounted for along with clock skew in any L3 timing analysis MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 20 Freescale Semiconductor Electrical and Thermal Characteristics The L3_CLK timing diagram is shown in Figure 7 li scR lt gt tLacr lt
12. 3 cLk 4 lcHcL L3 CLKO VM VM VM L3 CLK1 VM VM VM VM li scskw1 gt lt For PB2 or Late Write L3 ECHO CLK1 VM VM VM VM tLacskw2 gt lt L3_ECHO_CLK3 VM VM VM VM li scskw2 gt lt Figure 7 L3 CLK OUT Output Timing Diagram 5 2 4 L3 Bus AC Specifications The MPC7455 L3 interface supports three different types of SRAM source synchronous double data rate DDR MSUG2 SRAM late write SRAMs and pipeline burst PB2 SRAMs Each requires a different protocol on the L3 interface and a different routing of the L3 clock signals The type of SRAM is programmed in L3CR 22 23 and the MPC7455 then follows the appropriate protocol for that type The designer must connect and route the L3 signals appropriately for each type of SRAM Following are some observations about the chip to SRAM interface e The routing for the point to point signals L3 CLK 0 1 L3DATA 0 63 L3DP 0 7 and L3 ECHO CLKJ 0 3 to a particular SRAM should be delay matched If necessary the length of traces can be altered in order to intentionally skew the timing and provide additional setup or hold time margin Fora I Mbyte L3 use address bits 16 0 bit 0 is LSB No pull up resistors are required for the L3 interface For high speed operations L3 interface address and control signals should be a T with minimal stubs to the two loads data and clock signals should be point to point to thei
13. 766 863 955 1150 532 1726 1910 10111 12x 2x 600 800 900 996 1200 1600 1800 1992 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 46 Freescale Semiconductor System Design Information Table 17 MPC7455 Microprocessor PLL Configuration Example for 1 0 GHz Parts continued Example Bus to Core Frequency in MHz VCO Frequency in MHz PLL_ B sdp Coreto Bus SYSCLK Frequency CFG 0 4 core vco Multiplier Multiplier 33 3 50 66 6 75 83 100 133 P P MHz MHz MHz MHz MHz MHz MHz 11111 12 5x 2x 600 833 938 1200 1666 1876 01011 13x 2x 650 865 975 1300 1730 1950 11100 13 5x 2x 675 900 1350 1800 11001 14x 2x 700 933 1400 1866 00011 15x 2x 500 750 1000 1000 1500 2000 11011 16x 2x 533 800 1066 1600 00001 17x 2x 566 850 1132 1900 00101 18x 2x 600 900 1200 1800 00111 20x 2x 667 1000 1334 2000 01001 21x 2x 700 1400 01101 24x 2x 800 1600 11101 28x 2x 933 1866 00110 PLL bypass PLL off SYSCLK clocks core circuitry directly 11110 PLL off PLL off no core clocking occurs Notes 1 PLL CFG 0 4 settings not listed are reserved 2 The sample bus to core frequencies shown are for reference only Some PLL configurations may select bus core or VCO frequencies which are not useful not supported or not tested for by the MPC7455 see Section 5 2 1 Clock AC Specif
14. GVpp 0 45 V 2 5 Vou 1 7 V Output low voltage loj 5 mA 1 5 VoL 0 45 V 6 1 8 VoL 0 45 V 2 5 VoL 0 7 V Capacitance L3 interface Cin 9 5 pF 4 Vin 0 V f lt 1 MHz All other inputs 8 0 pF 4 Notes 1 Nominal voltages see Table 4 for recommended operating conditions For processor bus signals the reference is OVpp while GVpp is the reference for the L3 bus signals Excludes test signals and IEEE 1149 1 boundary scan JTAG signals Capacitance is periodically sampled rather than 100 tested The leakage is measured for nominal OVpp GVpp and Vpp or both OVpp GVpp and Vpp must vary in the same direction for example both OVpp and Vpp vary by either 5 or 5 6 Applicable to L3 bus interface only Q G DY Table 7 provides the power consumption for the MPC7455 Table 7 Power Consumption for MPC7455 Processor CPU Frequency Unit Notes 733 MHz 867 MHz 933 MHz 1 GHz Full Power Mode Typical 11 5 12 9 13 6 15 0 W 1 3 Maximum 17 0 19 0 20 0 22 0 W 1 2 Doze Mode Typical Ww 4 Nap Mode Typical 8 0 8 0 8 0 8 0 Ww 1 3 Sleep Mode MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 14 Freescale Semiconductor Electrical and Thermal Characteristics Table 7 Power Consumption for MPC7455 continued Processor CPU Frequency Unit Notes
15. L3 Frequencies Gore ao 2 32 5 3 43 5 4 5 6 500 250 200 167 143 125 100 83 533 266 213 178 152 133 107 89 550 275 220 183 157 138 110 92 600 300 240 200 171 150 120 100 6502 325 260 217 186 163 130 108 6662 333 266 222 190 167 133 111 7002 350 280 233 200 175 140 117 7332 367 293 244 209 183 147 122 8002 400 320 266 230 200 160 133 8672 433 347 289 248 217 173 145 9332 467 373 311 266 233 187 156 10002 500 400 333 285 250 200 166 Notes 1 The core and L3 frequencies are for reference only Note that maximum L3 frequency is design dependent Some examples may represent core or L3 frequencies which are not useful not supported or not tested forthe MPC7455 see Section 5 2 3 L3 Clock AC Specifications for valid L3 CLK frequencies and for more information regarding the maximum L3 frequency Shaded cells do not comply with Table 10 2 These core frequencies are not supported by all speed grades see Table 8 9 2 PLL Power Supply Filtering The AVpp power signal is provided on the MPC7455 to provide power to the clock generation PLL To ensure stability of the internal clock the power supplied to the AVpp input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL A circuit similar to the one shown in Figure 24 using surface mount capacitors with minimum effective series inductance ESL is recommended The circui
16. Mbyte minimum or all of the L3 SRAM space Supports MSUG2 dual data rate DDR synchronous Burst SRAMs PB2 pipelined synchronous Burst SRAMs and pipelined register register late write synchronous Burst SRAMs Supports parity on cache and tags Configurable core to L3 frequency divisors 64 bit external L3 data bus sustains 64 bits per L3 clock cycle MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 5 Features Separate memory management units MMUS for instructions and data 52 bit virtual address 32 or 36 bit physical address Address translation for 4 Kbyte pages variable sized blocks and 256 Mbyte segments Memory programmable as write back write through caching inhibited caching allowed and memory coherency enforced memory coherency not enforced on a page or block basis Separate IBATs and DBATs eight each also defined as SPRs Separate instruction and data translation lookaside buffers TLBs Both TLBs are 128 entry two way set associative and use LRU replacement algorithm TLBs are hardware or software reloadable that is on a TLB miss a page table search is performed in hardware or by system software Efficient data flow Although the VR LSU interface is 128 bits the L1 L2 L3 bus interface allows up to 256 bits The L1 data cache is fully pipelined to provide 128 bits cycle to or from the VRs L2 cache is fully pipelined to provide 256
17. Note that these configurations were different in devices prior to Rev F see Section 11 2 Part Numbers Not Fully Addressed by This Document for more information regarding documentation of prior revisions MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 45 System Design Information Table 17 MPC7455 Microprocessor PLL Configuration Example for 1 0 GHz Parts Example Bus to Core Frequency in MHz VCO Frequency in MHz PLL_ B s to Coreto Bus SYSCLK Frequency CFG 0 4 core vco Multiplier Multiplier 33 3 50 66 6 75 83 100 133 P P MHz MHz MHz MHz MHz MHz MHz 01000 2x 2x 10000 3x 2x 10100 4x 2x 532 1064 10110 5x 2x 500 1000 10010 5 5x 2x 550 1100 11010 6x 2x 600 800 1200 1600 01010 6 5x 2x 540 650 866 1080 1300 1730 00100 7x 2x 525 580 700 931 1050 1160 1400 1862 00010 7 5x 2x 500 563 623 750 1000 1000 1125 1245 1500 2000 11000 8x 2x 533 600 664 800 1066 1200 1328 1600 01100 8 5x 2x 566 638 706 850 1132 1276 1412 1700 01111 9x 2x 600 675 747 900 1200 1350 1494 1800 01110 9 5x 2x 633 712 789 950 1266 1524 1578 1900 10101 10x 2x 500 667 750 830 1000 1000 1333 1500 1660 2000 10001 10 5x 2x 525 700 938 872 1050 1400 1876 1744 10011 11x 2x 550 733 825 913 1100 1466 1650 1826 00000 11 5x 2x 575
18. Zo Typical 33 42 34 42 Q Maximum 31 51 32 44 Q 9 6 Pull Up Pull Down Resistor Requirements The MPC7455 requires high resistive weak 4 7 k 2 pull up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC7455 or other bus masters These pins are TS ARTRY SHDO and SHD1 Some pins designated as being for factory test must be pulled up to OVpp or down to GND to ensure proper device operation For the MPC7445 360 BGA the pins that must be pulled up to OVpp are LSSD MODE and TEST 0 3 the pins that must be pulled down to GND are L1 TSTCLK and TEST 4 For the MPC7455 483 BGA the pins that must be pulled up to OVpp are LSSD MODE and TEST 0 5 the pins that must be pulled down are L1 TSTCLK and TEST 6 The CKSTP IN signal should likewise be pulled up through a pull up resistor weak or stronger 4 7 1 KQ to prevent erroneous assertions of this signal In addition the MPC7455 has one open drain style output that requires a pull up resistor weak or stronger 4 7 KQ if it is used by the system This pin is CKSTP OUT If pull down resistors are used to configure BVSEL or L3VSEL the resistors should be less than 250 2 see Table 16 Because PLL_CFG 0 4 must remain stable during normal operation strong pull up and pull down resistors 1 kQ or less are recommended to configure these si
19. and L3 ECHO CLKO respectively Thus L3 ECHO CLKO0 and L3 ECHO CLK2 are phase aligned with the input clock received at the SRAMs The MPC7455 will latch the incoming data on the rising edge of L3 ECHO CLKO and L3 ECHO CLK2 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 26 Freescale Semiconductor Electrical and Thermal Characteristics Table 13 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11 assuming the timing relationships of Figure 12 and the loading of Figure 8 Table 13 L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs At recommended operating conditions See Table 4 All Speed Grades 5 Parameter Symbol L3OH0 0 L3OH1 0 L3OH0 0 L30H1 1 L30H0 1 L3OH1 0 L3OHO 1 L30H1 1 Unit Notes Min Max Min Max Min Max Min Max L3_CLK rise ti cR a 1 0 m 1 0 m 1 0 1 0 ns 1 5 and fall time ti acr Setup times tL3DVEH 1 5 1 5 1 5 1 5 ns 2 5 Data and parity Input hold ti aDXEH 0 5 0 5 0 5 0 5 ns 2 5 times Data and parity Valid times tL3cHDv i3 cuk 4 i3 cuk 4 w ti5 cLK 4 tls cuk 4 ns 3 4 5 Data and 1 00 4 0 80 0 60 4 0 40 parity Valid times All ti acHOV li ciK 4 lia ciK 4 tL3_cLK 4 lis cLK 4 ns 4 other outputs 1 00 0 80 0 60 0 40 Output hold ti acHDX lia cik 4 tL3_cLK 4 lia ciK 4 tis cLK 4 ns 3 4 5 times Da
20. calculated case temperature The actual value of Roc for the part is less than 0 1 C W 6 Refer to Section 9 8 Thermal Management Information for more details about thermal management C Table 6 provides the DC electrical characteristics for the MPC7455 Table 6 DC Electrical Specifications At recommended operating conditions See Table 4 Nominal Characteristic Bus Symbol Min Max Unit Notes Voltage Input high voltage 1 5 Vin GVpp x 0 65 GVpp 0 3 V 6 all inputs except SYSCLK 1 8 Vin OVpp GVpp x0 65 OVpp GVpp 0 3 V 2 5 ViH 1 7 OVpp GVpp 0 3 V Input low voltage 1 5 Vit 0 3 GVpp x 0 35 V 6 all inputs except SYSCLK 1 8 ViL 03 OVpp GVpp x 0 35 V 2 5 Vi 0 3 0 7 V SYSCLK input high voltage CVin 1 4 OVpp 0 3 V SYSCLK input low voltage CVIL 0 3 0 4 V MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 13 Electrical and Thermal Characteristics Table 6 DC Electrical Specifications continued At recommended operating conditions See Table 4 Nominal Characteristic Bus Symbol Min Max Unit Notes Voltage Input leakage current lin 30 uA 2 3 Vin GVpp OVpp 0 3 V High impedance off state leakage Isi 30 WA 2 3 5 current Vin GVpp OVpp 0 3 V Output high voltage loj 5 mA 1 5 VoH GVpp 0 45 V 6 1 8 Vou OVpp
21. control signals in the negated state after they have been actively negated and released by the MPC7445 and other bus masters 9 These input signals are for factory use only and must be pulled down to GND for normal machine operation 10 This pin can externally cause a performance monitor event Counting of the event is enabled via software 11 Unused address pins must be pulled down to GND 12 This test signal is recommended to be tied to HRESET however other configurations will not adversely affect performance 13 These signals must be pulled down to GND if unused or if the MPC7445 is in 60x bus mode 14 This signal must be asserted during reset by pull down to GND or assertion by HRESET to ensure proper operation Q GQ I MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 37 Pinout Listings Table 16 Pinout Listing for the MPC7455 483 CBGA Package Signal Name Pin Number Active 1 0 VF Select Notes A 0 35 E10 N4 E8 N5 C8 R2 A7 M2 A6 M1 High VO BVSEL 11 A10 U2 N2 P8 M8 W4 N6 U6 R5 Y4 P1 P4 R6 M7 N7 AAS U4 W2 W1 W3 V4 AA1 D10 J4 G10 D9 AACK U1 Low Input BVSEL AP 0 4 L5 L6 J1 H2 G5 High y o BVSEL ARTRY T2 Low y o BVSEL 8 AVpp B2 Input N A BG R3 Low Input BVSEL BMODEO C6 Low Input BVSEL 5 BMODE1 C4 Low Input BVSEL 6 BR K1 Low Output BVSEL BVSEL G6 High Input N A 3 7
22. each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The described product is a PowerPC microprocessor The PowerPC name is a trademark of IBM Corp and used under license All other product or service names are the property of their respective owners Q Freescale Semiconductor Inc 2005 MPC7455EC Rev 4 1 02 2005 o oe Z
23. part numbering nomenclature for the MPC7455 Table 21 Part Numbering Nomenclature xx 74x5 RX nnnn x x Product Part Process Packaqe Processor Application Revision Level Code Identifier Descriptor g Frequency Modifier xc 2 7455 A RX CBGA 733 L 13V 50mV_ F 3 3 PVR 8001 0303 7445 867 0 to 105 C MC 933 G 3 4 PVR 8001 0304 1000 Notes 1 Processor core frequencies supported by parts addressed by this specification only Parts addressed by part number specifications may support other maximum core frequencies 2 The X prefix in a Freescale part number designates a Pilot Production Prototype as defined by Freescale SOP 3 13 These are from a limited production volume of prototypes manufactured tested and Q A inspected on a qualified technology to simulate normal production These parts have only preliminary reliability and characterization data Before pilot production prototypes may be shipped written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes 11 2 Part Numbers Not Fully Addressed by This Document Parts with application modifiers or revision levels not fully addressed in this specification document are described in separate part number specifications which supplement and supersede this document see Table 22
24. up resistors on the bus Other data bus receivers in the system however may require pull ups or that those signals be otherwise driven by the system during inactive periods by the system The data bus signals are D 0 63 and DP 0 7 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 51 System Design Information If address or data parity is not used by the system and the respective parity checking is disabled through HIDO the input receivers for those pins are disabled and those pins do not require pull up resistors and should be left unconnected by the system If all parity generation is disabled through HIDO then all parity checking should also be disabled through HIDO and all parity pins may be left unconnected by the system The L3 interface does not normally require pull up resistors 9 7 JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals The TRST signal is optional in the IEEE 1149 1 specification but is provided on all processors that implement the PowerPC architecture While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals more reliable power on reset performance will be obtained if the TRST signal is asserted during power on reset Because the JTAG interface is also used for accessing the common on chip processor COP function simply tying TRST to HRESET is not practical The COP funct
25. 00 MPC7410 MPC7450 MPC7451 and MPC7441 7 General Parameters 4 9 Electrical and Thermal Characteristics 10 Pin Assignments 33 s Pinout Listings us inae oro nie simt usa C wasi 35 Package Description usss ama esera 41 System Design Information 45 Document Revision History 59 Ordering Information 60 ey oe Z freescale semiconductor Overview 1 1s nb H 1olS ejqeeuoe D c 49394 uononnsu E s ssIW peo1 11 suonueAieju ysnd doous 3 O1 eneno peo1 11 0S1 eneno 9J01S 17 Sseneno JM L1 snieis oX4g z amp L 49018 SSI peo1 ER 591015 nolseO 1 peysiul4 uonelnoleS v3 eulbuy yono 10199A yun eJoiS peo1 s iols pajajdwoy aa ysnd L1 yum 1utod Duneoj3 siejng eureueu 9L oll 2 suonels 3333 uoneAljeseH Anua z suoneis UOIlgAJeseH keny 1vad gua jeuibuo K1u3 82L sus NIN exea euv 1vagl gi wopeus Anug 8Z4 sus NINN uononasul uo eo a l qy zg suononasul p 11g 8Z L 1 g zg 0512018 uq 19 041u02 ayoeg ayoed z1 P HUN 1 qy 9SZ sng eq ig v9 1oejnwnooy sng v S nojse OS21 eneno e1o1s z1 SnijelS she sng SSeJppy 1lg 9 usnqpr anand aos sng g u319J 1q ZI oej
26. 1 reach the valid state V relative to the SYSCLK reference K going to the high H state or input setup time And tkuov symbolizes the time from SYSCLK K going high H until outputs O are valid V or output valid time Input hold time can be read as the time that the input signal I went invalid X with respect to the rising clock edge KH note the position of the reference and its state for inputs and output hold time can be read as the time from the rising edge KH until the output went invalid OX 3 tsyscik is the period of the external clock SYSCLK in ns The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration in ns of the parameter in question 4 According to the bus protocol TS is driven only by the currently active bus master It is asserted low then precharged high before returning to high impedance as shown in Figure 6 The nominal precharge width for TS is 0 5 x teysci y that is less than the minimum tsyscLk period to ensure that another master asserting TS on the following clock will not contend with the precharge Output valid and output hold timing is tested for the signal asserted Output valid time is tested for precharge The high impedance behavior is guaranteed by design 5 Guaranteed by design and not tested 6 According to the bus protocol ARTRY can be driven by multiple bus masters through the clock period immediately following AACK Bus contention is no
27. 2 Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7455 483 CBGA Package MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 44 Freescale Semiconductor System Design Information 8 6 Substrate Capacitors for the MPC7455 483 CBGA Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7455 483 CBGA All capacitors are 100 nF u Corner Pad Number Capacitor 1 2 C1 OVpp GND C2 Vpp GND C3 OVpp GND C4 OVpp GND C5 Vpp GND C6 OVpp GND C7 AVpp GND C8 OVpp GND C9 GVpp GND C10 GVpp GND C11 Vpp GND C12 GVpp GND Figure 23 Substrate Bypass Capacitors for the MPC7455 483 CBGA 9 System Design Information This section provides system and thermal design recommendations for successful application of the MPC7455 9 1 PLL Configuration The MPC7455 PLL is configured by the PLL_CFG 0 4 signals For a given SYSCLK bus frequency the PLL configuration signals set the internal CPU and VCO frequency of operation The PLL configuration for the MPC7455 is shown in Table 17 for a set of example frequencies In this example shaded cells represent settings that for a given SYSCLK frequency result in core and or VCO frequencies that do not comply with the 1 GHz column in Table 8
28. 4 in Figure 21 dimensions were reversed Revised Figure 24 and Section 9 7 JTAG Configuration Signals Revised format of Section 11 2 Part Numbers Not Fully Addressed by This Document and added Table 23 through Table 26 Revised Section 9 8 3 Heat Sink Selection Example and added additional thermal modeling information including Figure 28 Changed maximum heat sink clip spring force in Section 9 8 Thermal Management Information from 5 5 Ibs to 10 Ibs Changed substrate marking for MPC7445 in Figure 29 all MPC744x device substrates are marked MPC7440 Changed substrate marking for MPC7455 in Figure 29 all MPC745x device substrates are marked MPC7450 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 59 Ordering Information Table 20 Document Revision History continued Rev No Substantive Change s 1 1 Removed reference to Note 4 for DTI signals in Table 15 and Table 16 these signals are unused in 60x bus mode and must be pulled down see Note 13 they are not ignored Improved precision of die and package dimensions in Figure 20 and Figure 21 2 Corrected entries in Table 17 for 33 MHz and 50 MHz bus frequencies with multipliers of 24x and higher Corrected typographical errors in heatsink selection example in Section 9 8 3 Heat Sink Selection Example Removed e
29. 441 To achieve a higher frequency the number of logic levels per cycle is reduced Also to achieve this higher frequency the pipeline of the MPC7455 is extended compared to the MPC7400 while maintaining the same level of performance as measured by the number of instructions executed per cycle IPC Table 1 Microarchitecture Comparison Microarchitectural Specs MPC7455 MPC7445 a MPC7400 MPC7410 Basic Pipeline Functions Logic inversions per cycle 18 18 28 Pipeline stages up to execute 5 5 3 Total pipeline stages minimum 7 7 4 Pipeline maximum instruction 3 Branch 3 Branch 2 Branch throughput Pipeline Resources Instruction buffer size 12 12 6 Completion buffer size 16 16 8 Renames integer float vector 16 16 16 16 16 16 6 6 6 Maximum Execution Throughput SFX 3 3 2 Vector 2 Any 2 of 4 Units 2 Any 2 of 4 Units 2 Permute Fixed Scalar floating point 1 1 1 Out of Order Window Size in Execution Queues SFX integer units 1 Entry x 3 Queues 1 Entry x 3 Queues 1 Entry x 2 Queues Vector units In Order 4 Queues In Order 4 Queues In Order 2 Queues MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor Comparison with the MPC7400 MPC7410 MPC7450 MPC7451 and MPC7441 Table 1 Microarchitecture Comparison continued
30. 455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 53 System Design Information 9 8 Thermal Management Information This section provides thermal management information for the ceramic ball grid array CBGA package for air cooled applications Proper thermal control design is primarily dependent on the system level design the heat sink airflow and thermal interface material To reduce the die junction temperature heat sinks may be attached to the package by several methods spring clip to holes in the printed circuit board or package and mounting clip and screw assembly see Figure 27 however due to the potential large mass of the heat sink attachment through the printed circuit board is suggested If a spring clip is used the spring force should not exceed 10 pounds CBGA Package Heat Sink Heat Sink Clip Thermal Interface Material Printed Circuit Board Figure 27 Package Exploded Cross Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the MPC7455 There are several commercially available heat sinks for the MPC7455 provided by the following vendors Aavid Thermalloy 603 224 9988 80 Commercial St Concord NH 03301 Internet www aavidthermalloy com Alpha Novatech 408 749 7601 473 Sapena Ct 15 Santa Clara CA 95054 Internet www alphanovatech com International Electronic R
31. 7 mm 106 mm 33 million Fully static MPC7445 Surface mount 360 ceramic ball grid array CBGA MPC7455 Surface mount 483 ceramic ball grid array CBGA 1 3 V 50 mV DC nominal 1 8 V 596 DC or 1 5 V 5 DC L3 interface only MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor Electrical and Thermal Characteristics 5 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7455 5 1 DC Electrical Characteristics The tables in this section describe the MPC7455 DC electrical characteristics Table 2 provides the absolute maximum ratings Table 2 Absolute Maximum Ratings Characteristic Symbol Maximum Value Unit Notes Core supply voltage Vpp 0 3 to 1 95 V 4 PLL supply voltage AVpp 0 3 to 1 95 V 4 Processor bus supply voltage BVSEL 0 OVpp 0 3 to 1 95 V 3 6 BVSEL HRESET or OVpp OVpp 0 3 to 2 7 V 3 7 L3 bus supply voltage L3VSEL HRESET GVpp 0 3 to 1 65 V 3 8 L3VSEL 0 GVpp 0 3 to 1 95 V 3 9 L3VSEL HRESET orGVpp GVpp 0 3 to 2 7 V 3 10 Input voltage Processor bus Vin 0 3 to OVpp 0 3 V 2 5 L3 bus Vin 0 3 to GVpp 0 3 V 2 5 JTAG signals Vin 0 3 to OVpp 0 3 V Input voltage Processor bus Vin 0 3 to OVpp 0 3 V 2 5 JTAG signals Vin 0 3 to OVpp 0 3 V Storage temperature range Tstg 55 to 150 C
32. 8 C4 Package with Heat Sink Mounted to a Printed Circuit Board Heat generated on the active side of the chip is conducted through the silicon then through the heat sink attach material or thermal interface material and finally to the heat sink where it is removed by forced air convection Because the silicon thermal resistance is quite small for a first order analysis the temperature drop in the silicon may be neglected Thus the thermal interface material and the heat sink conduction convective thermal resistances are the dominant terms 9 8 2 Thermal Interface Materials A thermal interface material is recommended at the package lid to heat sink interface to minimize the thermal contact resistance For those applications where the heat sink is attached by spring clip mechanism Figure 29 shows the thermal performance of three thin sheet thermal interface materials silicone graphite oil floroether oil a bare joint and a joint with thermal grease as a function of contact pressure As shown the performance of these thermal interface materials improves with increasing contact pressure The use of thermal grease significantly reduces the MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 55 System Design Information interface thermal resistance That is the bare Joint results in a thermal resistance approximately seven times greater than the thermal grease Joint Often heat sinks are attache
33. B13 B15 B17 B19 B21 D12 D14 D16 N A 15 D18 D21 E19 F13 F15 F17 F21 G19 H12 H14 H17 H21 J19 K17 K21 L19 M17 M21 N19 P17 P21 R15 R19 T17 T21 U19 V17 V21 W19 Y21 HIT K2 Low Output BVSEL 4 HRESET A3 Low Input BVSEL INT J6 Low Input BVSEL L1 TSTCLK H4 High Input BVSEL 9 L2 TSTCLK J2 High Input BVSEL 12 L3VSEL A4 High Input N A 3 7 L3ADDR 17 0 F20 J16 E22 H18 G20 F22 G22 H20 High Output L3VSEL K16 J18 H22 J20 J22 K18 K20 L16 K22 L18 L3 CLK 0 1 V22 C17 High Output L3VSEL L3 CNTL 0 1 L20 L22 Low Output L3VSEL L3DATA 0 63 AA19 AB20 U16 W18 AA20 AB21 AA21 High yo L3VSEL T16 W20 U18 Y22 R16 V20 W22 T18 U20 N18 N20 N16 N22 M16 M18 M20 M22 R18 T20 U22 T22 R20 P18 R22 M15 G18 D22 E20 H16 C22 F18 D20 B22 G16 A21 G15 E17 A20 C19 C18 A19 A18 G14 E15 C16 A17 A16 C15 G13 C14 A14 E13 C13 G12 A13 E12 C12 L3DP O0 7 AB19 AA22 P22 P16 C20 E16 A15 A12 High yo L3VSEL L3 ECHO CLK 0 2 V18 E18 High Input L3VSEL L3 ECHO CLK 1 3 P20 E14 High yo L3VSEL LSSD MODE F6 Low Input BVSEL 2 7 MCP B8 Low Input BVSEL MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 39 Pinout Listings Table 16 Pinout Listing for the MPC7455 483 CBGA Package continued Signal Name Pin Number A
34. BR CKSTP_OUT DRDY HIT PMON_OUT QREQ SYSCLK to output enable tkHOE 0 5 ns SYSCLK to output high impedance all except TS ARTRY tkHoz 3 5 ns SHDO SHD1 SYSCLK to TS high impedance after precharge tkHTSPZ 1 levscik 3 4 5 Maximum delay to ARTRY SHDO SHD1 precharge tkKHARP 1 levscik 3 5 6 7 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 17 Electrical and Thermal Characteristics Table 9 Processor Bus AC Timing Specifications 1 continued At recommended operating conditions See Table 4 All Speed Grades Parameter Symbol Unit Notes Min Max SYSCLK to ARTRY SHD0 SHD1 high impedance after tKHARPZ 2 tovscLk 3 5 precharge 6 7 Notes 1 All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question All output timings assume a purely resistive 50 O load see Figure 4 Input and output timings are measured at the pin time of flight delays must be added for trace lengths vias and connectors in the system 2 The symbology used for timing specifications herein follows the pattern of t signaly state reference state for inputs and t reference state signal state for outputs For example tyk symbolizes the time input signals
35. BVSEL TDI B9 High Input BVSEL 7 TDO A4 High Output BVSEL TEA L1 Low Input BVSEL TEST 0 3 A12 B6 B10 E10 Input BVSEL 2 TEST 4 D10 Input BVSEL 9 TMS F1 High Input BVSEL 7 TRST A5 Low Input BVSEL 7 14 TS L4 Low VO BVSEL 8 TSIZ 0 2 G6 F7 E7 High Output BVSEL TT 0 4 E5 E6 F6 E9 C5 High 1O BVSEL WT D3 Low Output BVSEL 8 Vpp H8 H10 H12 J7 J9 J11 J13 K8 K10 S N A K12 K14 L7 L9 L11 L13 M8 M10 M12 Notes 1 OVpp supplies power to the processor bus JTAG and all control signals and Vpp supplies power to the processor core and the PLL after filtering to become AVpp To program the I O voltage connect BVSEL to either GND selects 1 8 V or to HRESET selects 2 5 V If used the pulldown resistor should be less than 250 Q For actual recommended value of Vi or supply voltages see Table 4 These input signals are for factory use only and must be pulled up to OVpp for normal machine operation These signals are for factory use only and must be left unconnected for normal machine operation Ignored in 60x bus mode This signal selects between MPX bus mode asserted and 60x bus mode negated and will be sampled at HRESET going high 6 This signal must be negated during reset by pull up to OVpp or negation by 2HRESET inverse of HRESET to ensure proper operation 7 Internal pull up on die 8 These pins require weak pull up resistors for example 4 7 KQ to maintain the
36. CK R1 Low Input BVSEL AP 0 4 C1 E3 H6 F5 G7 High O BVSEL ARTRY N2 Low lO BVSEL 8 AVDD A8 Input N A BG M1 Low Input BVSEL BMODEO G9 Low Input BVSEL 5 BMODE1 F8 Low Input BVSEL 6 BR D2 Low Output BVSEL BVSEL B7 High Input BVSEL 1 7 CI J1 Low Output BVSEL 8 CKSTP_IN A3 Low Input BVSEL CKSTP_OUT B1 Low Output BVSEL CLK_OUT H2 High Output BVSEL D 0 63 R15 W15 T14 V16 W16 T15 U15 High O BVSEL P14 V13 W13 T13 P13 U14 W14 R12 T12 W12 V12 N11 N10 R11 U11 W11 T11 R10 N9 P10 U10 R9 W10 U9 V9 W5 U6 T5 U5 W7 R6 P7 V6 P17 R19 V18 R18 V19 T19 U19 W19 U18 W17 W18 T16 T18 T17 W3 V17 U4 U8 U7 R7 P6 R8 W8 T8 DBG M2 Low Input BVSEL DP 0 7 T3 W4 T4 W9 M6 V3 N8 W6 High y o BVSEL DRDY R3 Low Output BVSEL 4 DTI 0 3 G1 K1 P1 N1 High Input BVSEL 13 EXT QUAL A11 High Input BVSEL 9 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 35 Pinout Listings Table 15 Pinout Listing for the MPC7445 360 CBGA Package continued Signal Name Pin Number Active VO VF Select Notes GBL E2 Low 1 0 BVSEL GND B5 C3 D6 D13 E17 F3 G17 H4 H7 N A H9 H11 H13 J6 J8 J10 J12 K7 K3 K9 K11 K13 L6 L8 L10 L12 M4 M7 M9 M11 M13 N7 P3 P9 P12 R5 R14 R17 T7 T10 U3 U13 U17 V5 V8 V11 V15 HIT B2 Low O
37. CODODUOUC CIOOOO QUOODOCOCCOEC C EDOOOODUCOOOODO OOOOOOOOQOOOOOOOOQOOOOQOQO 1 6 6 0 O66 6 66 6 4 LC C CC OOCOCOCOGOQOOGCOOOOQOOQOQOOQOCQ OOOCGOOOCOGOOOOOQOCGOOOOOCOC0QOQO OQUOOOODOCOOOODOUDOOCCOODODUO QOOCOODOOCOCODODOCCODOOQDU COUDOOOCCUCCODOCUDDUCODOOGDO OOOOCQGCOGOCQOOOQOQOOOQOOOGOQOQOQO OOOOOOOOOOOQOOOQCOOOOOQOO QOOGOCOGCOOOOCQOOOOOGCGQOOOOO QOUDODOCOCOCDDUOOQOC QOOCCIO 6 66 36 S 6S 66 6198 S 66 6 6 6 618 O68 6 6 6 618 C1616 16 6 Ce SO CS 86686 66 ES Ot C4 GES C6 8 6 O S 6 666 6 6 8 66 216 2 ee 6 Not to Scale gt lt Sec cHuovpvzt rxecronmoogwr Part B Substrate Assembly View Encapsulant Figure 19 Pinout of the MPC7455 483 CBGA Package as Viewed from the Top Surface MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 34 Freescale Semiconductor Pinout Listings 7 Pinout Listings Table 15 provides the pinout listing for the MPC7445 360 CBGA package Table 16 provides the pinout listing for the MPC7455 483 CBGA package NOTE This pinout is not compatible with the MPC750 MPC7400 or MPC7410 360 BGA package Table 15 Pinout Listing for the MPC7445 360 CBGA Package Signal Name Pin Number Active 1 0 VF Select Notes A 0 35 E11 H1 C11 G3 F10 L2 D11 D1 C10 High y o BVSEL 11 G2 D12 L3 G4 T2 F4 V1 J4 R2 K5 W2 J2 K4 N4 J3 M5 P5 N3 T1 V2 U1 N5 W1 B12 C4 G10 B11 AA
38. EL 9 5 Output Buffer DC Impedance The MPC7455 processor bus and L3 I O drivers are characterized over process voltage and temperature To measure Zo an external resistor is connected from the chip pad to OVpp or GND Then the value of each resistor is varied until the pad voltage is OVpp 2 see Figure 25 The output impedance is the average of two components the resistances of the pull up and pull down devices When data is held low SW2 is closed SW1 is open and Ry is trimmed until the voltage at the pad equals OVpp 2 Ry then becomes the resistance of the pull down devices When data is held high SW1 is closed SW2 is open and MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 49 System Design Information Rp is trimmed until the voltage at the pad equals OVpp 2 Rp then becomes the resistance of the pull up devices Rp and Ry are designed to be close to each other in value Then Zp Rp Ry 2 OVpp RN Sw2 Pad Data SW1 Hp OGND Figure 25 Driver Impedance Measurement MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 50 Freescale Semiconductor System Design Information Table 19 summarizes the signal impedance results The impedance increases with junction temperature and is relatively unaffected by bus voltage Table 19 Impedance Characteristics Vpp 1 5 V OVpp 1 8 V 5 Tj 5 85 C Impedance Processor Bus L3 Bus Unit
39. Freescale Semiconductor Technical Data MPC7455 RISC Microprocessor Hardware Specifications The MPC7455 and MPC7445 are implementations of the PowerPC microprocessor family of reduced instruction set computer RISC microprocessors This document is primarily concerned with the MPC7455 however unless otherwise noted all information here also applies to the MPC7445 This document describes pertinent electrical and physical characteristics of the MPC7455 For functional characteristics of the processor refer to the MPC7450 RISC Microprocessor Family User s Manual To locate any published updates for this document refer to the website at http www freescale com 1 Overview The MPC7455 is the third implementation of the fourth generation G4 microprocessors from Freescale The MPC7455 implements the full PowerPC 32 bit architecture and is targeted at networking and computing systems applications The MPC7455 consists of a processor core a 256 Kbyte L2 and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface The MPC7445 is identical to the MPC7455 except it does not support the L3 cache interface Figure shows a block diagram of the MPC7455 Freescale Semiconductor Inc 2005 All rights reserved MPC7455EC Rev 4 1 02 2005 Contents L OVeryleWr Soda wep s a eoe C ER daca e Wa ieh 1 PEORES yaa wrap eeen EXER EET 3 Comparison with the MPC74
40. Ji lul sng uiejs S Ayed 49 8 ss nppv eyequg y9 we 8L seq z 10 1 INvuS eue 6 eneno 1nolseo aoe snes uejs sqns Aow N L uun sieyng JeBeyu eujeueH 94 uonels anano uopenos y yono J0199A enss L Anu3 2 enss Hdd wun yoyedsiq psoM ZL eneno uononujsu enss g Anu3 9 1 llonuooS y 7 49 82 Wa 8cb Lun 1 B lul 10129A gun 1 B lul 10199A sJeyng euieueg 9L ell z suoneis ERES uoneAleseu uonels uoneis uoneAJjeseH uoneAieseud enssi z Anu3 v enss Hd5 enss HA Anu3 8r02 LH8 Anu3 8z1 OILA yun Buiss 5oiq uoueig x9oJ9 Jed suononnsul 9914 0 dn sejejduio 3 Srr OdN ut JON Joyejnuinooy sng as as T spel L 0 3908 eur Auu3 91 eneno uon lduoo yun uonajduio zuun wun 1 B lul 9jnuuad J0199A 10129A uonelis uonels uoneAJeseu uonenesey suononuisul 11g 96 JOJUO A eoueuuoueg jueujeBeue N Jewog Jeuueu L eoejueju dOO OVILr JOANN 2012 4e1ueuJoJoe q ie1uno 2 eseg OU e yum uononnsul seJnjeo4 jeuonippv iagram 1 MPC7455 Block D igure F 1 ions Rev 4 icat Hardware Spec Icroprocessor MPC7455 RISC M Freescale Semiconductor Features The core is a high performance superscalar design supporting a double precision floating point unit and a SIMD multimedia unit The memory storage subsystem supports the MPX bus protocol and a sub
41. P 0 1 f to MPC7455 GND Aligned Signals L3 CLK 0 zeno 0 4 L3 DATA 16 31 L3 DP 2 3 GV ua DD L3 ECHO CLK 1 Denotes Transmit MPC7455 to SRAM Aligned Signals L3 ECHO CLK 2 L3 DATA 82 47 L3 DP 4 5 l zz GND L3 CLK 1 L3 DATA 48 63 L3 DP 6 7 GND K Gvpp 2 L3_ECHO_CLK 3 Note 1 Or as recommended by SRAM manufacturer for single ended clocking Figure 11 Typical Synchronous 1 MByte L3 Cache Late Write or PB2 Interface MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 29 Electrical and Thermal Characteristics Figure 12 shows the L3 bus timing diagrams for the MPC7455 interfaced to PB2 or late write SRAMs Outputs L3 CLK 0 1 VM VM L3 ECHO CLK 1 3 ti 3cHov lt li 3CHOX ADDR L3 CNTL i gt mm tLacHDv gt lt ttscrpx L3DATA WRITE gt mm Inputs L3 ECHO CLK 0 2 VM tL3DVEH lt ooxen Parity Inputs L3 Data and Data VM Midpoint Voltage GVpp 2 Figure 12 L3 Bus Timing Diagrams for Late Write or PB2 SRAMs 5 2 5 IEEE 1149 1 AC Timing Specifications Table 14 provides the IEEE 1149 1 JTAG AC timing specifications as defined in Figure 14 through Figure 17 Table 14 JTAG AC Timing Specifications Independent of SYSCLK At recommended operating conditions See Table 4 Parameter Symbol Min Max Unit No
42. This pin can externally cause a performance monitor event Counting of the event is enabled via software 11 Unused address pins must be pulled down to GND 12 This test signal is recommended to be tied to HRESET however other configurations will not adversely affect performance 13 These signals must be pulled down to GND if unused or if the MPC7455 is in 60x bus mode 14 This signal must be asserted during reset by pull down to GND or assertion by HRESET to ensure proper operation 15 Power must be supplied to GVpp even when the L3 interface is disabled or unused 16 These signals are for factory use only and must be left unconnected for normal machine operation 8 Package Description The following sections provide the package parameters and mechanical dimensions for the CBGA package 8 1 Package Parameters for the MPC7445 360 CBGA The package parameters are as provided in the following list The package type is 25 x 25 mm 360 lead ceramic ball grid array CBGA Package outline 25 x25 mm Interconnects 360 19 x 19 ball array 1 Pitch 1 27 mm 50 mil Minimum module height 2 72 mm Maximum module height 3 24 mm Ball diameter 0 89 mm 35 mil MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 41 Package Description 8 2 Mechanical Dimensions for the MPC7445 360 CBGA Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC7445 360 CBGA p
43. ackage A1 CORNER i 0 15 lt NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY Millimeters DIM MIN MAX A 2 72 3 20 A1 0 80 1 00 w A2 1 10 1 30 U A3 0 6 R b 0 82 0 93 i gt A3 D 25 00 BSC k D1 615 TAS D2 1245 12 45 G lt A1 F weil ee j e 1 27 BSC D 25 00 BSC B E1 11 1 E2 745 360X 2 b l os A B c 20 15 A ES 8 75 9 20 Figure 20 Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7445 360 CBGA Package MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 42 Freescale Semiconductor Package Description 8 3 Substrate Capacitors for the MPC7445 360 CBGA Figure 21 shows the connectivity of the substrate capacitor pads for the MPC7445 360 CBGA All capacitors are 100 nF Corner Pad Number Capacitor 1 2 C1 OVpp GND C2 Vpp GND C3 OVpp GND C4 Vpp GND C5 OVpp GND C6 Vpp GND Figure 21 Substrate Bypass Capacitors for the MPC7445 360 CBGA 8 4 Package Parameters f
44. aracteristics OVpp GVpp 5 OVpp GVpp ViH Vit GND GND 0 3 V GND 0 7 V gt lt Not to Exceed 10 of tsysc_k Figure 2 Overshoot Undershoot Voltage The MPC7455 provides several I O voltages to support both compatibility with existing systems and migration to future systems The MPC7455 core voltage must always be provided at nominal 1 3 V see Table 4 for actual recommended core voltage Voltage to the L3 I Os and processor interface I Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3 The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET The output voltage will swing from GND to the maximum voltage applied to the OVpp or GVpp power pins Table 3 Input Threshold Voltage Setting BvSEL Signal Tonada aa sto L3VSEL Sia s 45 pw restos notes 0 1 8V 0 1 8 V 1 4 HRESET Not Available 3HRESET 15V 1 3 HRESET 2 5 V HRESET 2 5 V 1 2 1 2 5 V 1 2 5 V 1 Notes 1 Caution The input threshold selection must agree with the OVpp GVpp voltages supplied See notes in Table 2 2 To select the 2 5 V threshold option for the processor bus BVSEL should be tied to HRESET so that the two signals change state together Similarly to select 2 5 V for the L3 bus tie L3VSEL to HRESET This is the preferred method for selectin
45. bits per processor clock cycle to the L1 cache As many as eight outstanding out of order cache misses are allowed between the L1 data cache and L2 L3 bus As many as 16 out of order transactions can be present on the MPX bus Store merging for multiple store misses to the same line Only coherency action taken address only for store misses merged to all 32 bytes of a cache block no data tenure needed Three entry finished store queue and five entry completed store queue between the LSU and the L1 data cache Separate additional queues for efficient buffering of outbound data such as castouts and write through stores from the L1 data cache and L2 cache Multiprocessing support features include the following Hardware enforced MESI cache coherency protocols for data cache Load store with reservation instruction pair for atomic memory references semaphores and other multiprocessor operations Power and thermal management 1 3 V processor core The following three power saving modes are available to the system Nap Instruction fetching is halted Only those clocks for the time base decrementer and JTAG logic remain running The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ QACK processor system handshake protocol Sleep Power consumption is further reduced by disabling bus snooping leaving only the PLL ina locked and r
46. coupled group of inputs The MPC7450 RISC Microprocessor Family User s Manual refers to logical settings called sample points used in the synchronization of reads from the receive FIFO The computation of the correct value for this setting is system dependent and is described in the MPC7450 RISC Microprocessor Family User s Manual Three specifications are used in this calculation and are given in Table 11 It is essential that all three specifications are included in the calculations to determine the sample points as incorrect settings can result in errors and unpredictable behavior For more information see the MPC7450 RISC Microprocessor Family User s Manual Table 11 Sample Points Calculation Parameters Parameter Symbol Max Unit Notes Delay from processor clock to internal L3 CLK tac 3 4 lia CLK 1 Delay from internal L3 CLK to L3 CLKn output pins tco 3 ns 2 Delay from L3 ECHO CLKn to receive latch teci 3 ns 3 Notes 1 This specification describes a logical offset between the internal clock edge used to launch the L3 address and control signals this clock edge is phase aligned with the processor clock edge and the internal clock edge used to launch the L3_CLKn signals With proper board routing this offset ensures that the L3_CLKn edge will arrive at the SRAM within a valid address window and provide adequate setup and hold time This offset is reflected in the L3 bus interface AC timing specificat
47. ctive VO VF Select Notes No Connect A8 A11 B6 B11 C11 D11 D3 D5 E11 E7 N A 16 F2 F11 G11 G2 H11 H9 J8 OVpp B3 C5 C7 C10 D2 E3 E9 F5 G3 G9 H7 N A J5 K3 L7 M5 N3 P7 R4 T3 U5 U7 U11 U15 V3 V9 V13 Y2 Y5 Y7 Y10 Y17 Y19 AA4 AA15 PLL_CFG 0 4 A2 F7 C2 D4 H8 High Input BVSEL PMON_IN E6 Low Input BVSEL 10 PMON_OUT B4 Low Output BVSEL QACK K7 Low Input BVSEL QREQ Y1 Low Output BVSEL SHD 0 1 L4 L8 Low VO BVSEL 8 SMI G8 Low Input BVSEL SRESET G1 Low Input BVSEL SYSCLK D6 Input BVSEL TA N8 Low Input BVSEL TBEN L3 High Input BVSEL TBST B7 Low Output BVSEL TCK J7 High Input BVSEL TDI E4 High Input BVSEL 7 TDO H1 High Output BVSEL TEA Ti Low Input BVSEL TEST 0 5 B10 H6 H10 D8 F9 F8 Input BVSEL 2 TEST 6 A9 Input BVSEL 9 TMS K4 High Input BVSEL 7 TRST C1 Low Input BVSEL 7 14 TS P5 Low VO BVSEL 8 TSIZ 0 2 L1 H3 D1 High Output BVSEL TT 0 4 F1 F4 K8 A5 E1 High VO BVSEL WT L2 Low Output BVSEL 8 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 40 Freescale Semiconductor Package Description Table 16 Pinout Listing for the MPC7455 483 CBGA Package continued Signal Name Pin Number Active VO WF Select Notes Vpp J9 J11 J13 J15 K10 K12 K14 L9 L11 N A L13 L15 M10 M12 M14 N9 N11 N13 N15 P10 P12 P14 Notes 1 9 OVpp supplies power to
48. cy AltiVec integer instructions such as vector add instructions vaddsbs vaddshs and vaddsws for example Vector integer unit 2 VIU2 handles longer latency AltiVec integer instructions such as vector multiply add instructions vmhaddshs vmhraddshs and vmladduhm for example Vector floating point unit VFPU Three stage load store unit LSU Supports integer floating point and vector instruction load store traffic Four entry vector touch queue VTQ supports all four architected AltiVec data stream operations Three cycle GPR and AltiVec load latency byte half word word vector with one cycle throughput Four cycle FPR load latency single double with one cycle throughput No additional delay for misaligned access within double word boundary Dedicated adder calculates effective addresses EAs Supports store gathering Performs alignment normalization and precision conversion for floating point data Executes cache control and TLB instructions Performs alignment zero padding and sign extension for integer data Supports hits under misses multiple outstanding misses Supports both big and little endian modes including misaligned little endian accesses e Three issue queues FIQ VIQ and GIQ can accept as many as one two and three instructions respectively in a cycle Instruction dispatch requires the following Instructions can be dispatched only fro
49. d to ensure this signal is de asserted when it is not being driven by the tool Note that the pull up and pull down resistors on the QACK signal are MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 52 Freescale Semiconductor System Design Information mutually exclusive and it is never necessary to populate both in a system To preserve correct power down operation QACK should be merged via logic so that it also can be driven by the PCI bridge From Target usai Board Sources if any dede EN o teer Mee E B TRST pu Ce A VDD VDD SENSE CHKSTP OUT e m s B el e eA s COP Connector Physical Pin Out x 7 Ss n o o Notes 1 RUN STOP normally found on pin 5 of the COP header is not implemented on the MPC7455 Cor pin 5 of the COP header to OVpp with a 10 kQ pull up resistor 2 Key location pin 14 is not physically present on the COP header 3 Component not populated Populate only if debug tool does not drive QACK 4 Populate only if debug tool uses an open drain type output and does not actively de assert QACH 5 If the JTAG interface is implemented connect HRESET from the target source to TRST from the header though an AND gate to TRST of the part If the JTAG interface is not implemented cor HRESET from the target source to TRST of the part through a 0 Q isolation reisistor Figure 26 JTAG Interface Connection MPC7
50. d to the package by means of a spring clip to holes in the printed circuit board see Figure 27 Therefore the synthetic grease offers the best thermal performance considering the low interface pressure and is recommended due to the high power dissipation of the MPC7455 Of course the selection of any thermal interface material depends on many factors thermal performance requirements manufacturability service temperature dielectric properties cost etc 2 cop Silicone Sheet 0 006 in t i d T Bare Joint L Floroether Oil Sheet 0 007 in i sc Graphite Oil Sheet 0 005 in Bi Synthetic Grease qd bawa s sa Y wor p P er men L SN I i i i Saas i LU Bee q 4 x B E o D 1 i 1 1 e FS TN 8 L i meme d S 1 1 1 1 D Ge Ske u 1 1 1 1 1 q ote i Dom mgli I ied cc L ee i E x Ed TM E i 3 0 1 1 1 D k 4 o k ae 1 4 O06 tka as Toe Ps as NECEM a Sam SESA oe bue o v I i i coe ee D lt o i i i i i i imis oc eo 0 I I I I I I I 1 0 10 20 30 40 50 60 70 80 Contact Pressure psi Figure 29 Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface Heat sink adhesive materials should be
51. d underfill layer is modeled as 9 10 x 12 25 x 0 069 mm or as a collapsed volume with orthotropic material properties 0 6 W m K in the xy plane and 2 W m K in the direction of the z axis The substrate volume is 25 x 25 x 1 2 mm MPC7445 or 29 x 29 x 1 2 mm MPC7455 and this volume has 18 W m K isotropic conductivity The solder ball and air layer is modeled with the same horizontal dimensions as the substrate and is 0 9 mm thick It can also be modeled as a collapsed volume using orthotropic material properties 0 034 W m K in the xy plane direction and 3 8 W m K in the direction of the z axis Die z Bump and Underfill Conductivity Value Unit Substrate Solder and Air Bump and Underfill Side View of Model Not to Scale ky 0 6 W m K ky 0 6 x x k 2 Substrate Substrate k 18 Solder Ball and Air Die ky 0 034 ky 0 034 k 3 8 Top View of Model Not to Scale Figure 30 Recommended Thermal Model of MPC7445 and MPC7455 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 58 Freescale Semiconductor Document Revision History 10 Document Revision History Table 20 provides a revision history for this hardware specification Table 20 Document Revision History Rev No Substantive Change s Initial release Updated for Rev F devices information specific to R
52. elayed clock is used to capture the data into these latches which comprise the receive FIFO This clock is asynchronous to all other processor clocks This latched data is subsequently read out of the FIFO synchronously to the processor clock The time between writing and reading the data is set by the using the sample point settings defined in the L3CR register MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 22 Freescale Semiconductor Electrical and Thermal Characteristics Table 12 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9 assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8 Table 12 L3 Bus Interface AC Timing Specifications for MSUG2 At recommended operating conditions See Table 4 All Speed Grades 8 Parameter Symbol L3OH0 0 L30H1 0 L3OH0 0 L3OH1 1 L3OHO 1 L3OH1 0 L3OHO 1 L30H1 1 Unit Notes Min Max Min Max Min Max Min Max L3_CLK rise li acp 1 0 1 0 1 0 1 0 ns 1 and fall time tL3cr Setup times tispven 0 1 0 1 0 1 0 1 ns 2 3 Data and lispvEL 4 parity Input hold tispxeH tia cuk 4 lia cuk 4 lia cuk 4 lis ciK 4 ns 2 4 times Data ttu pxEL 0 30 0 30 0 30 0 30 and parity Valid times ti 3cupv ts cik 4 7s cLk 4 C scu 4
53. esearch Corporation IERC 818 842 7277 413 North Moss St Burbank CA 91502 Internet www ctscorp com Tyco Electronics 800 522 6752 Chip Coolers P O Box 3668 Harrisburg PA 17105 3668 Internet www chipcoolers com MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 54 Freescale Semiconductor System Design Information Wakefield Engineering 603 635 5102 33 Bridge St Pelham NH 03076 Internet www wakefield com Ultimately the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity spatial volume mass attachment method assembly and cost 9 8 1 Internal Package Conduction Resistance For the exposed die packaging technology shown in Table 3 the intrinsic conduction thermal resistance paths are as follows The die junction to case actually top of die since silicon die is exposed thermal resistance The die junction to ball thermal resistance Figure 28 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed circuit board External Resistance Radiation Convection Heat Sink gt 3 3 gt Thermal Interface Material Die Package amp Die Junction Package Leads Internal Resistance Printed Circuit Board gt External Resistance Radiation Convection Note the internal versus external package resistance Figure 2
54. essor Hardware Specifications Rev 4 1 18 Freescale Semiconductor Electrical and Thermal Characteristics Figure 5 provides the mode select input timing diagram for the MPC7455 SYSCLK VM VM HRESET Mode Signals X Firs t Sample Second Sample VM Midpoint Voltage OVpp 2 Figure 5 Mode Input Timing Diagram Figure 6 provides the input output timing diagram for the MPC7455 SYSCLK VM VM VM t wa gt She rie tivKH gt Ed rs I MVKH All Inputs m tkHav tKHAX kHDV lkHDx gt lt tkHov All Outputs ___ __ es Ao o P X Except TS i ARTRY SHDO SHD1 tkHOE gt lt t All Outputs Dd Katia Except TS ARTRY SHD0 SHD1 I lt lkHTSPz tkHTSV TS lt lKHARV ARTRY SHDO SHD1 VM Midpoint Voltage OVpp 2 Figure 6 Input Output Timing Diagram MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 19 Electrical and Thermal Characteristics 5 2 3 L3 Clock AC Specifications The L3 CLK frequency is programmed by the L3 configuration register L3CR 6 8 core to L3 divisor ratio See Table 18 for example core and L3 frequencies at various divisors Table 10 provides the potential range of L3 CLK output AC timing specifications as defined in Figure 7 The maximum L3 CLK frequency is the core frequency divided by two Given t
55. ev 4 1 16 Freescale Semiconductor Electrical and Thermal Characteristics 5 2 2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and Figure 5 Timing specifications for the L3 bus are provided in Section 5 2 3 L3 Clock AC Specifications Table 9 Processor Bus AC Timing Specifications At recommended operating conditions See Table 4 All Speed Grades Parameter Symbol 2 Unit Notes Min Max Input setup times ns A 0 35 AP 0 4 GBL TBST TSIZ 0 2 TT 0 3 D 0 63 tavKH 2 0 DP 0 7 AACK ARTRY BG CKSTP IN DBG DTI 0 3 QACK TA livkH 2 0 E TBEN TEA TS EXT QUAL PMON IN SHD 0 1 BMODE 0 1 BVSEL L3VSEL Input hold times ns A 0 35 AP 0 4 GBL TBST TSIZ 0 2 TT 0 3 D 0 63 TAXKH 0 DP 0 7 AACK ARTRY BG CKSTP IN DBG DTI 0 3 QACK TA tixKH 0 a TBEN TEA TS EXT_QUAL PMON_IN SHD 0 1 BMODE 0 1 BVSEL L3VSEL i MXKH Output valid times ns A 0 35 AP 0 4 GBL TBST TSIZ 0 2 TT 0 3 WT CI tKHAV 2 5 TS tkHTSV 2 5 D 0 63 DP 0 7 kHDV 7 s ARTRY SHDO SHD1 KHARY _ a e a a tkHov 2 5 BR CKSTP OUT DRDY HIT PMON OUT QREQ Output hold times ns A 0 35 AP 0 4 GBL TBST TSIZ 0 2 TT 0 3 WT CI tKHAX 0 5 TS tkHTSX 0 5 D 0 63 DP 0 7 tkHDX 0 5 ARTRY SHDO SHDI IKHARX is RD E eed d dr RUNE RR MER D S a tkHox 0 5
56. ev C devices is now documented in a separate part number specifications see Section 11 2 Part Numbers Not Fully Addressed by This Document for more information Removed 600 and 800 MHz speed grades Increased leakage current specifications in Table 6 from 10 to 30 pA Changed core voltage to 1 3 V all instances of Vpp and AVpp updated Updated power consumption specifications in Table 7 Reduced I O power guidance in Table 7 from lt 20 to 596 Added footnote 1 to Figure 9 and Figure 11 Removed CI and WT from Input Setup and Input Hold lists in Table 10 these are output only signals Removed INT HRESET MCP SRESET and SMI from Input Setup and Input Hold lists in Table 10 these are asynchronous inputs Added TT 0 3 to Input Setup Input Hold Output Valid and Output Hold lists in Table 10 these were mistakenly omitted in Rev O Updated Table 13 and Table 14 to reflect new L3 AC timing in Rev F devices Corrected Note 10 in Table 16 and Table 17 this is an event pin not an enable pin Corrected entries for L3 ECHO CLKT 1 3 in Table 17 these are I O pins not input only Added Note 16 to Table 17 all No Connect pins must be left unconnected Changed name of PLL EXT to PLL_CFG 4 and updated all instances Updated Table 18 to reflect PLL configuration settings for Rev F devices Added dimensions D2 and E3 to Figure 20 Transposed dimensions D4 and E
57. g this mode of operation 3 Applicable to L3 bus interface only SHRESET is the inverse of HRESET A 5 Not implemented on MPC7445 If used pulldown resistors should be less than 250 Q MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 11 Electrical and Thermal Characteristics Table 4 provides the recommended operating conditions for the MPC7455 Table 4 Recommended Operating Conditions Recommended Value Characteristic Symbol Unit Notes Min Max Core supply voltage Vpp 1 3 V 50 mV V PLL supply voltage AVpp 1 3 V 50 mV V 2 Processor bus supply voltage BVSEL 0 OVpp 1 8 V 5 V BVSEL HRESET or OVpp OVpp 2 5 V 5 V L3 bus supply voltage L3VSEL 0 GVpp 1 8 V 5 V L3VSEL HRESET or GVpp GVpp 2 5 V 5 V L3VSEL HRESET GVpp 1 5 V 5 V Input voltage Processor bus Vin GND OVpp V L3 bus Vin GND GVpp V JTAG signals Vin GND OVpp V Die junction temperature Tj 0 105 C Notes 1 These are the recommended and tested operating conditions Proper device operation outside of these conditions is not guaranteed 2 This voltage is the input to the filter discussed in Section 9 2 PLL Power Supply Filtering and not necessarily the voltage at the AVpp pin which may be reduced from Vpp by the filter MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 12 Freescale Semiconductor
58. gnals in order to protect against erroneous switching due to ground bounce power supply noise or noise coupling During inactive periods on the bus the address and transfer attributes may not be driven by any master and may therefore float in the high impedance state for relatively long periods of time Because the MPC7455 must continually monitor these signals for snooping this float condition may cause excessive power draw by the input receivers on the MPC7455 or by other receivers in the system These signals can be pulled up through weak 10 kQ pull up resistors by the system address bus driven mode enabled see the MPC7450 RISC Microporcessor Family Users Manual for more information on this mode or they may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw Preliminary studies have shown the additional power draw by the MPC7455 input receivers to be negligible and in any event none of these measures are necessary for proper device operation The snooped address and transfer attribute inputs are A 0 35 AP 0 4 TT 0 4 CI WT and GBL If extended addressing is not used A 0 3 are unused and must be pulled low to GND through weak pull down resistors If the MPC7455 is in 60x bus mode DTI 0 3 must be pulled low to GND through weak pull down resistors The data bus input receivers are normally turned off when no read operation is in progress and therefore do not require pull
59. he high core frequencies available in the MPC7455 however most SRAM designs will be not be able to operate in this mode using current technology and as a result will select a greater core to L3 divisor to provide a longer L3 CLK period for read and write access to the L3 SRAMs Therefore the typical L3 CLK frequency shown in Table 10 is considered to be the practical maximum in a typical system The maximum L3 CLK frequency for any application of the MPC7455 will be a function of the AC timings of the MPC7455 the AC timings for the SRAM bus loading and printed circuit board trace length and may be greater or less than the value given in Table 10 Freescale is similarly limited by system constraints and cannot perform tests of the L3 interface on a socketed part on a functional tester at the maximum frequencies of Table 10 Therefore functional operation and AC timing information are tested at core to L3 divisors which result in L3 frequencies at 200 MHz or less Table 10 L3 CLK Output AC Timing Specifications At recommended operating conditions See Table 4 All Speed Grades Parameter Symbol Unit Notes Min Typ Max L3 clock frequency fis CLK 75 250 MHz 1 L3 clock cycle time tL3_CLK 4 0 13 3 ns L3 clock duty cycle teHCL L3_CLK 50 2 L3 clock output to output skew L1_CLKO to ti scskwt1 200 ps 3 L1 CLK1 L3 clock output to output skew L1 CLK 0 1 ti scskwe 100 ps 4
60. ications for valid SYSCLK core and VCO frequencies 3 In PLL bypass mode the SYSCLK input signal clocks the internal processor directly and the PLL is disabled However the bus interface unit requires a 2x clock to function Therefore an additional signal EXT QUAL must be driven at one half the frequency of SYSCLK and offset in phase to meet the required input setup tiy and hold time tixxy see Table 9 The result will be that the processor bus frequency will be one half SYSCLK while the internal processor is clocked at SYSCLK frequency This mode is intended for factory use and emulator tool use only Note The AC timing specifications given in this document do not apply in PLL bypass mode 4 In PLL off mode no clocking occurs inside the MPC7455 regardless of the SYSCLK input MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 47 System Design Information The MPC7455 generates the clock for the external L3 synchronous data SRAMS by dividing the core clock frequency of the MPC7455 The core to L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits of the L3CR register Generally the divisor must be chosen according to the frequency supported by the external RAMs the frequency of the MPC7455 core and timing analysis of the circuit board routing Table 18 shows various example L3 clock frequencies that can be obtained for a given set of core frequencies Table 18 Sample Core to
61. iming with respect to TCK Guaranteed by design and characterization Q G Iv Figure 13 provides the AC test load for TDO and the boundary scan outputs of the MPC7455 Figure 13 Alternate AC Test Load for the JTAG Interface Figure 14 provides the JTAG clock input timing diagram VM Midpoint Voltage OVpp 2 Figure 14 JTAG Clock Input Timing Diagram Figure 15 provides the TRST timing diagram TRST VM VM trt VM Midpoint Voltage OVpp 2 Figure 15 TRST Timing Diagram MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 31 Electrical and Thermal Characteristics Figure 16 provides the boundary scan timing diagram TCK mee lt px Boundary Input a Data Inputs Data Valid lt Upv gt px Boundary Output Data Valid Data Outputs LJLDZ Boundary Data Outputs Output Data Valid VM Midpoint Voltage OVpp 2 Figure 16 Boundary Scan Timing Diagram Figure 17 provides the test access port timing diagram TCK iva 7 708 Input TDI TMS Data Valid lt tjLov luox TDO Output Data Valid lt tJLOZ TDO Output Data Valid VM Midpoint Voltage OVpp 2 Figure 17 Test Access Port Timing Diagram MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 32 Freescale Semiconductor 6 Pin Assignments Figure 18 in Part A shows the pin
62. ing or falling edge of the input L3 ECHO CLKn see Figure 10 Input timings are measured at the pins For DDR the input data will typically follow the edge of L3 ECHO CLKn as shown in Figure 10 For consistency with other input setup time specifications this will be treated as negative input setup time 13 cLK 4 is one fourth the period of L3 CLKn This parameter indicates that the MPC7455 can latch an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling or falling and rising edges of L8 ECHO CLKn at any frequency All output specifications are measured from the midpoint voltage of the rising or for DDR write data also the falling edge of L3 CLK to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 Q load see Figure 8 For DDR the output data will typically lead the edge of L3 CLKn as shown in Figure 10 For consistency with other output valid time specifications this will be treated as negative output valid time tia _cLK 4 is one fourth the period of L3 CLKn This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90 Therefore there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3 CLK period starting three f
63. ion of these processors allows a remote computer system typically a PC with dedicated hardware and debugging software to access and control the internal operations of the processor The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor If the target system has independent reset sources such as voltage monitors watchdog timers power supply failures or push button switches then the COP reset signals must be merged into these signals with logic The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST while ensuring that the target can drive HRESET as well If the JTAG interface and COP header will not be used TRST should be tied to HRESET through a 0 Q isolation resistor so that it is asserted when the system reset signal HRESET is asserted ensuring that the JTAG scan chain is initialized during power on While Freescale recommends that the COP header be designed into the system as shown in Figure 26 if this is not possible the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations The COP header shown in Figure 26 adds many benefits breakpoints watchpoints register and memory examination modification and other standard deb
64. ions but must also be separately accounted for in the calculation of sample points and thus is specified here This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising or falling edge at the L3CLKn pins This specification is the delay from a rising or falling edge of L8_ECHO_CLKn to data valid and ready to be sampled from the FIFO N 09 5 2 4 1 L3 Bus AC Specifications for DDR MSUG2 SRAMs When using DDR MSUG2 SRAMs at the L3 interface the parts should be connected as shown in Figure 9 Outputs from the MPC7455 are actually launched on the edges of an internal clock phase aligned to SYSCLK adjusted for core and L3 frequency divisors L3 CLK0 and L3_CLK1 are this internal clock output with 90 phase delay so outputs are shown synchronous to L3 CLKO and L3 CLKI Output valid times are typically negative when referenced to L3 CLK7 because the data is launched one quarter period before L3 CLKz to provide adequate setup time at the SRAM after the delay matched address control data and L3 CL Kn signals have propagated across the printed wiring board Inputs to the MPC7455 are source synchronous with the CQ clock generated by the DDR MSUG2 SRAMs These CQ clocks are received on the L3 ECHO CLKn inputs of the MPC7455 An internal circuit delays the incoming L3 ECHO CLKn signal such that it is positioned within the valid data window at the internal receiving latches This d
65. isses load store 5 1 5 1 8 Any Combination Data stream touch engines 4 Streams 4 Streams 4 Streams On Chip Cache Features MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 8 Freescale Semiconductor Table 1 Microarchitecture Comparison continued General Parameters MPC7450 MPC7451 Microarchitectural Specs MPC7455 MPC7445 MPC7441 MPC7400 MPC7410 Cache level L2 L2 L2 tags and controller Size associativity 256 Kbyte 8 Way 256 Kbyte 8 Way OY T T Access width 256 Bits 256 Bits Number of 32 byte sectors line 2 2 Parity Byte Byte Off Chip Cache Support 2 Cache level L3 L3 L2 On chip tag logical size 1MB 2MB 1MB 2MB 0 5MB 1MB 2MB Associativity 8 Way 8 Way 2 Way Number of 32 byte sectors line 2 4 2 4 1 2 4 Off chip data SRAM support MSUG2 DDR LW PB2 MSUG2 DDR LW PB2 LW PB2 PB3 Data path width 64 64 64 Direct mapped SRAM sizes 1 Mbyte 2 Mbytes 1 Mbyte 2 Mbytes 0 5 Mbyte 1 Mbyte 2 Mbytes 3 Parity Byte Byte Byte Notes 1 Numbers in parentheses are for 2 1 SRAM 2 Not implemented on MPC7445 or MPC7441 3 Private memory feature not implemented on MPC7400 4 General Parameters The following list provides a summary of the general parameters of the MPC7455 Technology Die size Transistor count Logic design Packages Core power supply I O power supply 2 5 V 5 DC or 0 18 um CMOS six layer metal 8 69 mm x 12 1
66. m the three lowest IQ entries IQO IQ1 and IQ2 A maximum of three instructions can be dispatched to the issue queues per clock cycle Space must be available in the CQ for an instruction to dispatch this includes instructions that are assigned a space in the CQ but not in an issue queue Rename buffers 16 GPR rename buffers 16 FPR rename buffers 16 VR rename buffers Dispatch unit Decode dispatch stage fully decodes each instruction Completion unit The completion unit retires an instruction from the 16 entry completion queue CQ when all instructions ahead of it have been completed the instruction has finished execution and no exceptions are pending Guarantees sequential programming model precise exception model Monitors all dispatched instructions and retires them in order Tracks unresolved branches and flushes instructions after a mispredicted branch MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 4 Freescale Semiconductor Features Retires as many as three instructions per clock cycle Separate on chip L1 instruction and data caches Harvard architecture 32 Kbyte eight way set associative instruction and data caches Pseudo least recently used PLRU replacement algorithm 32 byte eight word L1 cache block Physically indexed physical tags Cache write back or write through operation programmable on a per page or per block basis Instruction cache ca
67. n provide four instructions per clock cycle data cache can provide four words per clock cycle Caches can be disabled in software Caches can be locked in software MESI data cache coherency maintained in hardware Separate copy of data cache tags for efficient snooping Parity support on cache and tags No snooping of instruction cache except for icbi instruction Data cache supports AltiVec LRU and transient instructions Critical double and or quad word forwarding is performed as needed Critical quad word forwarding is used for AltiVec loads and instruction fetches Other accesses use critical double word forwarding Level 2 L2 cache interface On chip 256 Kbyte eight way set associative unified instruction and data cache Fully pipelined to provide 32 bytes per clock cycle to the L1 caches A total nine cycle load latency for an L1 data cache miss that hits in L2 PLRU replacement algorithm Cache write back or write through operation programmable on a per page or per block basis 64 byte two sectored line size Parity support on cache Level 3 L3 cache interface not implemented on MPC7445 Provides critical double word forwarding to the requesting unit Internal L3 cache controller and tags External data SRAMs Support for 1 and 2 Mbyte L3 caches Cache write back or write through operation programmable on a per page or per block basis 64 byte 1M or 128 byte 2M sectored line size Private memory capability for half 1
68. oad see Figure 10 tia _cLK 4 is one fourth the period of L3 CLKn This parameter indicates that the specified output signal is actually launched by an internal clock delayed in phase by 90 Therefore there is a frequency component to the output valid and output hold times such that the specified output signal will be valid for approximately one L3 CLK period starting three fourths of a clock prior to the edge on which the SRAM will sample it and ending one fourth of a clock period after the edge it will be sampled Timing behavior and characterization are currently being evaluated These configuration bits allow the AC timing of the L3 interface to be altered via software L3OHO L2CR 12 L30H1 L3CR 12 Revisions of the MPC7455 not described by this document may implement these bits differently See Section 11 1 Part Numbers Fully Addressed by This Document and Section 11 2 Part Numbers Not Fully Addressed by This Document for more information on which devices are addressed by this document MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 28 Freescale Semiconductor Electrical and Thermal Characteristics Figure 11 shows the typical connection diagram for the MPC7455 interfaced to PB2 SRAMs such as the Freescale MCM63R737 or late write SRAMs such as the Freescale MCM63R836A MPC7455 L3 ADDR 16 0 SRAM 0 L3 CNTL 0 L3 CNTL 1 Denotes L3 ECHO CLK 0 Receive SRAM L3 DATA 0 15 L3 D
69. or the MPC7455 483 CBGA The package parameters are as provided in the following list The package type is 29 x 29 mm 483 lead ceramic ball grid array CBGA Package outline 20 x 29 mm Interconnects 483 22 x 22 ball array 1 Pitch 1 27 mm 50 mil Minimum module height Maximum module height 3 22mm Ball diameter 0 89 mm 35 mil MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 43 Package Description 8 5 Mechanical Dimensions for the MPC7455 483 CBGA Figure 22 provides the mechanical dimensions and bottom surface nomenclature for the MPC7455 483 CBGA package Capacitor Region A1 CORNER P aA WM NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY 77 7 I i Millimeters Xov KWI III DIM MIN MAX e o2 V A 272 320 y A1 0 80 1 00 Ps A2 1 10 1 30 a A3 0 60 w v 0 82 0 93 r D 29 00 BSC N D1 116 M Aa D2 894 K D3 7 1 H lt A2 G D4 12 15 12 45 F lt A1 E e 1 27 BSC E E 29 00 BSC i E1 11 6 E2 8 94 0 3 A B C E3 a 6 9 e o45 ee E4 8 75 9 20 Figure 2
70. ourths of a clock prior to the edge on which the SRAM will sample it and ending one fourth of a clock period after the edge it will be sampled These configuration bits allow the AC timing of the L3 interface to be altered via software L3OHO L2CR 12 L30H1 L3CR 12 Revisions of the MPC7455 not described by this document may implement these bits differently See Section 11 1 Part Numbers Fully Addressed by This Document and Section 11 2 Part Numbers Not Fully Addressed by This Document for more information on which devices are addressed by this document MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 24 Freescale Semiconductor Electrical and Thermal Characteristics Figure 9 shows the typical connection diagram for the MPC7455 interfaced to MSUG2 SRAMS such as the Freescale MCM64E836 MPC7455 L3ADDR 17 0 eens T U Denotes L8 ECHO CLK 0 BIRK e MPC7455 a ESPATAos Lepoan Aoo Aligned Signals L3_CLK 0 CK L3DATA 16 31 L8DP 2 3 D 18 35 L3 ECHO CLK 1 Denotes Transmit MPC7455 to SRAM Aligned Signals L3ECHO CLK 2 L3 CLK 1 L3DATA 48 63 L3DP 6 7 L3 ECHO CLK 3 Note 1 Or as recommended by SRAM manufacturer for single ended clocking Figure 9 Typical Source Synchronous 2 Mbyte L3 Cache DDR Interface MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 25 Electrical and Thermal Characteristics Figure 10 sh
71. out of the MPC7445 360 CBGA package as viewed from the top surface Part B shows the side profile of the CBGA package to indicate the direction of the top surface view Part A Part B Se lt cADWDVZzZAZrACTAAMIOD gt Y 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 OOODOOCOOODOCOUCOOLD QOC OOCOOOOQUOCOOGQOODOOO0OD OOUDOOCOOOCODUOCOCUDCC CO OOOOOOOOOOOOOOOOOOCO QOODOOCCOOUCOOOOOOC COO OOOOOOOOOOOOOOOOOOO OODODOODOOCOOOOCCCOQOO0 QOOGOGOQOOOOOOOOOQOO0QQ OQOCOCOOODOOCOOOOOOOOOO OOOOOOOOOOOOOOOOOOO QOOOCOCDODGDOODOOOUDOCEC O OOOO OO OOOO OOO OOOO OC EC 61S 6 6 4 8 6 O16 OOCDOOOOODOCOOOGOOOOQ0QOD OQOOOOOOQOCOOOOOOOOOQOOQO OOOOOOOOOOOOOOOOOOO OOO OOO OO C OOOOOOOOOO OOOOOOOOOOQOOOOOOOOO QUODOOOODOQOOCODOOUQO Not to Scale Substrate Assembly View Encapsulant Pin Assignments Figure 18 Pinout of the MPC7445 360 CBGA Package as Viewed from the Top Surface MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 33 Pin Assignments Figure 19 in Part A shows the pinout of the MPC7455 483 CBGA package as viewed from the top surface Part B shows the side profile of the CBGA package to indicate the direction of the top surface view Part A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 QOOOCCOOOOODOOOUDOOOQOCOGCOCOQOO QOOCOODQOGOGCGCCOODODOQDOCO OOQOQOQO0 OQOOOOOQOOQOOOOOOCOCOOQOCOOQOO OODCOCOODQOQCCODUDOOOQQOQDCOCO OCOOOCQOOCOOOCOOOOOOQOQOOCOOO QUO OQCOCOG
72. ows the L3 bus timing diagrams for the MPC7455 interfaced to MSUG2 SRAMs Outputs L3_CLK 0 1 tL3CHOV li 3CHOZ gt gt tL3cHox DE ADDR L3CNTL D iom t aud EE Eee L3DATA WRITE l I tLscHDx gt lt tL3cLDX VM F Voltage GVpp 2 Note tj 3cujpy and tj 4c py as drawn here will be negative numbers that is output valid time will be time before the clock edge Inputs L3 ECHO CLK 0 1 2 3 VM VM VM VM VM li 3DXEL lli 3DVEL ll 3DVEH L3 Data and Data I 4 Parity Inputs i PL ll 3DXEH lt l VM Midpoint Voltage GVpp 2 Note tj 3pygi and tj pyg as drawn here will be negative numbers that is input setup time will be time after the clock edge Figure 10 L3 Bus Timing Diagrams for L3 Cache DDR SRAMs 5 2 4 2 L3 Bus AC Specifications for PB2 and Late Write SRAMs When using PB2 or late write SRAMs at the L3 interface the parts should be connected as shown in Figure 11 These SRAMS are synchronous to the MPC7455 one L3 CLKz signal is output to each SRAM to latch address control and write data Read data is launched by the SRAM synchronous to the delayed L3 CL Kn signal it received The MPC7455 needs a copy of that delayed clock which launched the SRAM read data to know when the returning data will be valid Therefore L3 ECHO CLK1 and L3 ECHO CLK3 must be routed halfway to the SRAMs and then returned to the MPC7455 inputs L3 ECHO CLKO
73. r single load Figure 8 shows the AC test load for the L3 interface Output GVpp 2 R 50 Q Figure 8 AC Test Load for the L3 Interface In general if routing is short delay matched and designed for incident wave reception and minimal reflection there is a high probability that the AC timing of the MPC7455 L3 interface will meet the maximum frequency operation of appropriately chosen SRAMs This is despite the pessimistic guard banded AC specifications see Table 12 Table 13 and Table 14 the limitations of functional testers described in Section 5 2 3 L3 Clock AC Specifications and the uncertainty of clocks and signals which inevitably make worst case critical path timing analysis pessimistic MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 21 Electrical and Thermal Characteristics More specifically certain signals within groups should be delay matched with others in the same group while intergroup routing is less critical Only the address and control signals are common to both SRAMs and additional timing margin is available for these signals The double clocked data signals are grouped with individual clocks as shown in Figure 9 or Figure 11 depending on the type of SRAM For example for the MSUG2 DDR SRAM see Figure 9 L3DATA 0 31 L3DP 0 3 and L3 CLK 0 form a closely coupled group of outputs from the MPC7455 while L3DATA 0 15 L3DP 0 1 and L3 ECHO CLK 0 form a closely
74. rements Added pull up pull down recommendations for CKSTP IN and PLL_CFG 0 4 to Section 9 6 Pull Up Pull Down Resistor Requirements Modified Table 9 Figure 5 and Figure 6 to more accurately show when the mode select inputs BMODE 0 1 LSVSEL BVSEL are sampled and AC timing requirements Figure 20 and Figure 22 Updated corrected dimensions in mechanical drawings 4 1 Document tempate update 11 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 11 1 Part Numbers Fully Addressed by This Document Note that the individual part numbers correspond to a maximum processor core frequency For available frequencies contact your local Freescale sales office In addition to the processor frequency the part numbering scheme also includes an application modifier which may specify special application conditions Each part number also contains a revision level code which refers to the die mask revision number Section 11 2 Part Numbers Not Fully Addressed by This Document lists the part numbers which do not MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 60 Freescale Semiconductor Ordering Information fully conform to the specifications of this document These special part numbers require an additional document called a part number specification 11 1 Part Numbers Fully Addressed by This Document Table 21 provides the Freescale
75. ring Information 5 2 1 Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 3 Table 8 Clock AC Timing Specifications At recommended operating conditions See Table 4 Maximum Processor Core Frequency Characteristic Symbol 733 MHz 867 MHz 933 MHz 1 GHz Unit Notes Min Max Min Max Min Max Min Max Processor frequency fcore 500 733 500 867 500 933 500 1000 MHz 1 VCO frequency fvco 1000 1466 1000 1734 1000 1866 1000 2000 MHz 1 SYSCLK frequency fsyscik 33 133 33 133 33 133 33 133 MHz 1 SYSCLK cycle time tevscik 7 5 30 7 5 30 7 5 30 7 5 30 ns SYSCLK rise and fall time tkp tke 1 0 1 0 1 0 1 0 ns 2 SYSCLK duty cycle tkHKL 40 60 40 60 40 60 40 60 3 measured at OVpp 2 tsyScLk MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 15 Electrical and Thermal Characteristics Table 8 Clock AC Timing Specifications continued At recommended operating conditions See Table 4 Maximum Processor Core Frequency Characteristic Symbol 733 MHz 867 MHz 933 MHz 1 GHz Unit Notes Min Max Min Max Min Max Min Max SYSCLK jitter 150 zx150 150 150 ps 4 6 Internal PLL relock time 100 100 100 100 us 5 Notes 1 Caution
76. rroneous instances of PLL_EXT signal name and changed remaining instances of PLL CFG 0 3 to PLL_CFG 0 4 These were artifacts from older revisions see entry for Rev 1 0 Corrected erroneous instances artifacts mentioning 1 6 V core voltage Core voltage for devices completely covered by this revision and revisions 1 x of this document is 1 3 V Corrected errors in PLL multipliers in Table 17 32x and 25x are not supported ratios 3x and 4x are supported 10 5x and 12 5x PLL settings were incorrect Replaced notes at bottom of Table 17 erroneously missing in revisions 1 x Updated coplanarity specifications in Figure 20 and Figure 21 from 0 2 mm to 0 15 mm 3 Added Revision G Rev 3 4 devices to specifications Added new PowerPC trademarking information 4 Added substrate capacitor information in Section 8 3 Substrate Capacitors for the MPC7445 360 CBGA and Section 8 6 Substrate Capacitors for the MPC7455 483 CBGA Clarified maximum and typical L3 clock frequency in Section 5 2 3 L3 Clock AC Specifications typical L3 frequency now stated as 250 MHz based on changes to L3 AC timing Significantly changed L3 AC timing in Table 12 and Table 13 These changes reflect both updates based on latest characterization and error corrections effects of non zero L3OH values were incorrectly documented in earlier revisions of this document Clarified address bus pull up resistor recommendations in Section 9 6 Pull Up Pull Down Resistor Requi
77. sa is the heat sink base to ambient thermal resistance P is the power dissipated by the device During operation the die junction temperatures T should be maintained less than the value specified in Table 4 The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet An electronic cabinet inlet air temperature T may range from 30 to 40 C The air temperature rise within a cabinet T may be in the range of 5 to 10 C The thermal resistance of the thermal interface material Ros is typically about 1 5 C W For example assuming a T of 30 C a T of 5 C a CBGA package Rgjc 0 1 and a typical power consumption P4 of 15 0 W the following expression for T is obtained Die junction temperature T 30 C 5 C 0 1 C W 1 5 C W Ro X 15 W For this example a Ros value of 3 1 C W or less is required to maintain the die junction temperature below the maximum value of Table 4 Though the die junction to ambient and the heat sink to ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three dimensional heat flow The final die Junction operating temperature is not only a function of the componen
78. set of the 60x bus protocol to main memory and other system resources The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data Note that the MPC7455 is footprint compatible with the MPC7450 and MPC7451 and the MPC7445 is footprint compatible with the MPC7441 2 Features This section summarizes features of the MPC7455 implementation of the PowerPC architecture Major features of the MPC7455 are as follows High performance superscalar microprocessor As many as four instructions can be fetched from the instruction cache at a time As many as three instructions can be dispatched to the issue queues at a time As many as 12 instructions can be in the instruction queue IQ As many as 16 instructions can be at some stage of execution simultaneously Single cycle execution for most instructions One instruction per clock cycle throughput for most instructions Seven stage pipeline control Eleven independent execution units and three register files Branch processing unit BPU features static and dynamic branch prediction 128 entry 32 set four way set associative branch target instruction cache BTIC a cache of branch instructions that have been encountered in branch loop code sequences If a target instruction is in the BTIC it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache Typically a fetch that hits the BTIC provides the first four instruc
79. t an issue because any master asserting ARTRY will be driving it low Any master asserting it low in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second cycle after the assertion of AACK The nominal precharge width for ARTRY is 1 0 tsyscuk that is it should be high impedance as shown in Figure 6 before the first opportunity for another master to assert ARTRY Output valid and output hold timing is tested for the signal asserted The high impedance behavior is guaranteed by design 7 According to the MPX bus protocol SHDO and SHD1 can be driven by multiple bus masters beginning the cycle of TS Timing is the same as ARTRY that is the signal is high impedance for a fraction of a cycle then negated for up to an entire cycle crossing a bus cycle boundary before being three stated again The nominal precharge width for SHDO and SHD1 is 1 0 tevscik The edges of the precharge vary depending on the programmed ratio of core to bus PLL configurations 8 BMODE 0 1 and BVSEL are mode select inputs and are sampled before and after HRESET negation These paramenters represent the input setup and hold times for each sample These values are guaranteed by design and not tested These inputs must remain stable after the second sample See Figure 5 for sample timing Figure 4 provides the AC test load for the MPC7455 Figure 4 AC Test Load MPC7455 RISC Microproc
80. t level thermal resistance but the system level design and its operating conditions In addition to the component s power consumption a number of factors affect the final operating die junction MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 57 System Design Information temperature airflow board population local heat flux of adjacent components heat sink efficiency heat sink attach heat sink placement next level interconnect technology system air temperature rise altitude etc Due to the complexity and the many variations of system level boundary conditions for today s microelectronic equipment the combined effects of the heat transfer mechanisms radiation convection and conduction may vary widely For these reasons we recommend using conjugate heat transfer models for the board as well as system level designs For system thermal modeling the MPC7445 and MPC7455 thermal model is shown in Figure 30 Four volumes will be used to represent this device Two of the volumes solder ball and air and substrate are modeled using the package outline size of the package The other two die and bump and underfill have the same size as the die Dimensions for these volumes for the MPC7445 and MPC7455 are given in Figure 20 and Figure 22 respectively The silicon die should be modeled 9 10 x 12 25 x 0 74 mm with the heat source applied as a uniform source at the bottom of the volume The bump an
81. t should be placed as close as possible to the AVpp pin to minimize noise coupled from nearby circuits It is often possible to route directly from the capacitors to the AVpp pin which is on the periphery of the 360 CBGA footprint and very close to the periphery of the 483 CBGA footprint without the inductance of vias MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 48 Freescale Semiconductor System Design Information 10 Q Vpp SMELL bu AVpp 2 2 UF 2 2 UF Low ESL Surface Mount Capacitors GND Figure 24 PLL Power Supply Filter Circuit 9 3 Decoupling Recommendations Due to the MPC7455 dynamic power management feature large address and data buses and high operating frequencies the MPC7455 can generate transient power surges and high frequency noise in its power supply especially while driving large capacitive loads This noise must be prevented from reaching other components in the MPC7455 system and the MPC7455 itself requires a clean tightly regulated source of power Therefore it is recommended that the system designer place at least one decoupling capacitor at each Vpp OVpp and GVpp pin of the MPC7455 It is also recommended that these decoupling capacitors receive their power from separate Vpp OV pp GV pp and GND power planes in the PCB utilizing short traces to minimize inductance These capacitors should have a value of 0 01 or 0 1 uF Only ceramic surface mount technology SMT capacitors should be
82. ta 0 40 0 60 0 80 1 00 and parity Output hold tL3cHox i3 cuk 4 tL3_cLK 4 i3 cuk 4 i3 cLK 4 ns 4 5 times All other 0 40 0 60 0 80 1 00 outputs L3 CLK to ti acHDZ 2 0 2 0 2 0 E 2 0 ns 5 high impedance Data and parity MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 27 Electrical and Thermal Characteristics Table 13 L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs continued At recommended operating conditions See Table 4 All Speed Grades 5 Parameter Symbol L3OH0 0 L3OH1 0 L3OH0 0 L3OH1 1 L30H0 1 L3OH1 0 L3OHO 1 L3OH1 1 Unit Notes other outputs Min Max Min Max Min Max Min Max L3_CLK to ti scHoz 2 0 x 2 0 2 0 2 0 ns 5 high impedance All Notes 1 2 Rise and fall times for the L3 CLK output are measured from 20 to 80 of GVpp All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L3 ECHO CLKn see Figure 10 Input timings are measured at the pins All output specifications are measured from the midpoint voltage of the rising edge of L3 CLKn to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 O l
83. tes TCK frequency of operation frcLK 0 33 3 MHz TCK cycle time t TCLK 30 ns TCK clock pulse width measured at 1 4 V UL 15 ns TCK rise and fall times tjr and typ 0 2 ns TRST assert time trast 25 ns 2 Input setup times ns 3 Boundary scan data ipvJH 4 TMS TDI tivJH ES Input hold times ns 3 Boundary scan data iDxJH 20 TMS TDI tIXJH 2 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 30 Freescale Semiconductor Electrical and Thermal Characteristics Table 14 JTAG AC Timing Specifications Independent of SYSCLK continued At recommended operating conditions See Table 4 Parameter Symbol Min Max Unit Notes Valid times ns 4 Boundary scan data tJLDV 4 20 TDO tiov 4 25 Output hold times ns 4 Boundary scan data tJLDX TBD TBD TDO tJLOX TBD TBD TCK to output high impedance ns 4 5 Boundary scan data tJLDZ 3 19 TDO tyLoz 3 9 Notes 1 All outputs are measured from the midpoint voltage of the falling rising edge of TCLK to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 Q load see Figure 13 Time of flight delays must be added for trace lengths vias and connectors in the system TRST is an asynchronous level sensitive signal The setup time is for test purposes only Non JTAG signal input timing with respect to TCK Non JTAG signal output t
84. the processor bus JTAG and all control signals except the L3 cache controls LS8CTL 0 1 GVpp supplies power to the L3 cache interface LSADDR 0 17 L3DATA 0 63 L3DP 0 7 L3 ECHO CLK 0 3 and L3 CLK 0 1 and the L3 control signals L8 CNTL 0 1 and Vpp supplies power to the processor core and the PLL after filtering to become AVpp For actual recommended value of Vi or supply voltages see Table 4 These input signals are for factory use only and must be pulled up to OVpp for normal machine operation To program the processor interface I O voltage connect BVSEL to either GND selects 1 8 V orto HRESET selects 2 5 V To program the L3 interface connect L3VSEL to either GND selects 1 8 V or to HRESET selects 2 5 V or to HRESET selects 1 5 V If used pulldown resistors should be less than 250 Q Ignored in 60x bus mode This signal selects between MPX bus mode asserted and 60x bus mode negated and will be sampled at HRESET going high This signal must be negated during reset by pull up to OVpp or negation by 2HRESET inverse of HRESET to ensure proper operation Internal pull up on die These pins require weak pull up resistors for example 4 7 k 2 to maintain the control signals in the negated state after they have been actively negated and released by the MPC7455 and other bus masters These input signals for factory use only and must be pulled down to GND for normal machine operation 10
85. through Table 25 Table 22 Part Numbers Addressed by XPC74x5RXnnnLC Series Part Number Specification Document Order No MPC7455RXLCPNS XPC 74x5 RX nnn L C Product Part Processor TNT sz ia Code Identifier Package Frequency Application Modifier Revision Level XPC 7455 RX CBGA 600 L 1 6 V 50 mV C 2 1 PVR 8001 0201 7445 733 0 to 105 C 800 867 933 PPC 1000 MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 61 Ordering Information Table 23 Part Numbers Addressed by XPC74x5RXnnnNx Series Part Number Specification Document Order No MPC7455RXNXPNS XPC 74x5 RX nnn N C Product Part Processor m za E Code Identifier Package Frequency Application Modifier Revision Level XPC 7455 RX CBGA 600 N 1 3 V 50 mV C 2 1 PVR 8001 0201 7445 733 0 to 105 C 800 Table 24 Part Numbers Addressed by XPC74x5RXnnnPx Series Part Number Specification Document Order No MPC7455RXPXPNS XPC 7455 RX nnn P C Product Part Processor Code Identifier Package Frequency Application Modifier Revision Level XPC 7455 RX CBGA 933 P 1 85 V 50 mV C 2 1 PVR 8001 0201 1000 0 to 65 C Table 25 Part Numbers Addressed by XPC74x5RXnnnSx Series Part Number Specification Document Order No MPC7455RXSXPNS XPC 7455 RX nnnn s C Product Part Processor T Code Identifier Package Frequenc
86. tions in the target stream 2048 entry branch history table BHT with two bits per entry for four levels of prediction not taken strongly not taken taken and strongly taken Upto three outstanding speculative branches Branch instructions that do not update the count register CTR or link register LR are often removed from the instruction stream Eight entry link register stack to predict the target address of Branch Conditional to Link Register belr instructions Four integer units IUs that share 32 GPRs for integer operands Three identical Us IU1a IUIb and IU1c can execute all integer instructions except multiply divide and move to from special purpose register instructions U2 executes miscellaneous instructions including the CR logical operations integer multiplication and division instructions and move to from special purpose register instructions Five stage FPU and a 32 entry FPR file Fully IEEE 754 1985 compliant FPU for both single and double precision operations Supports non IEEE mode for time critical operations Hardware support for denormalized numbers MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 3 Features Thirty two 64 bit FPRs for single or double precision operands Four vector units and 32 entry vector register file VRs Vector permute unit VPU Vector integer unit 1 VIU1 handles short laten
87. ugger features are possible through this interface and can be as inexpensive as an unpopulated footprint for a header to be added when needed The COP interface has a standard header for connection to the target system based on the 0 025 square post 0 100 centered header assembly often called a Berg header The connector typically has pin 14 removed as a connector key There is no standardized way to number the COP header shown in Figure 26 consequently many different pin numbers have been observed from emulator vendors Some are numbered top to bottom then left to right while others use left to right then top to bottom while still others number the pins counter clockwise from pin 1 as with an IC Regardless of the numbering the signal placement recommended in Figure 26 is common to all known emulators The QACK signal shown in Figure 26 is usually connected to the PCI bridge chip in a system and is an input to the MPC7455 informing it that it can go into the quiescent state Under normal operation this occurs during a low power mode selection In order for COP to work the MPC7455 must see this signal asserted pulled down While shown on the COP header not all emulator products drive this signal If the product does not a pull down resistor can be populated to assert this signal Additionally some emulator products implement open drain type outputs and can only drive QACK asserted for these tools a pull up resistor can be implemente
88. unning state All internal functional units are disabled Deep sleep When the part is in the sleep state the system can disable the PLL The system can then disable the SYSCLK source for greater system power savings Power on reset procedures for restarting and relocking the PLL must be followed on exiting the deep sleep state Thermal management facility provides software controllable thermal management Thermal management is performed through the use of three supervisor level registers and an MPC7455 specific thermal management exception Instruction cache throttling provides control of instruction fetching to limit power consumption MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 6 Freescale Semiconductor Comparison with the MPC7400 MPC7410 MPC7450 MPC7451 and MPC7441 e Performance monitor can be used to help debug system designs and improve software efficiency In system testability and debugging features through JTAG boundary scan capability e Testability LSSD scan design IEEE 1149 1 JTAG interface Array built in self test ABIST factory test only Reliability and serviceability Parity checking on system bus and L3 cache bus Parity checking on the L2 and L3 cache tag arrays 3 Comparison with the MPC7400 MPC7410 MPC7450 MPC7451 and MPC7441 Table 1 compares the key features of the MPC7455 with the key features of the earlier MPC7400 MPC7410 MPC7450 MPC7451 and MPC7
89. used to minimize lead inductance preferably 0508 or 0603 orientations where connections are made along the length of the part Consistent with the recommendations of Dr Howard Johnson in High Speed Digital Design A Handbook of Black Magic Prentice Hall 1993 and contrary to previous recommendations for decoupling Freescale microprocessors multiple small capacitors of equal value are recommended over using multiple values of capacitance In addition it is recommended that there be several bulk storage capacitors distributed around the PCB feeding the Vpp GVpp and OVpp planes to enable quick recharging of the smaller chip capacitors These bulk capacitors should have a low equivalent series resistance ESR rating to ensure the quick response time necessary They should also be connected to the power and ground planes through two vias to minimize inductance Suggested bulk capacitors 100 330 uF AVX TPS tantalum or Sanyo OSCON 9 4 Connection Recommendations To ensure reliable operation it is highly recommended to connect unused inputs to an appropriate signal level Unused active low inputs should be tied to OVpp Unused active high inputs should be connected to GND All NC no connect signals must remain unconnected Power and ground connections must be made to all external Vpp OVpp GVpp and GND pins in the MPC7455 If the L3 interface is not used GVpp should be connected to the OVpp power plane and L3VSEL should be connected to BVS
90. utput BVSEL 4 HRESET D8 Low Input BVSEL INT D4 Low Input BVSEL L1_TSTCLK G8 High Input BVSEL 9 L2 TSTCLK B3 High Input BVSEL 12 No Connect A6 A13 A14 A15 A16 A17 A18 A19 3 B13 B14 B15 B16 B17 B18 B19 C13 C14 C15 C16 C17 C18 C19 D14 D15 D16 D17 D18 D19 E12 E13 E14 E15 E16 E19 F12 F13 F14 F15 F16 F17 F18 F19 G11 G12 G13 G14 G15 G16 G19 H14 H15 H16 H17 H18 H19 J14 J15 J16 J17 J18 J19 K15 K16 K17 K18 K19 L14 L15 L16 L17 L18 L19 M14 M15 M16 M17 M18 M19 N12 N18 N14 N15 N16 N17 N18 N19 P15 P16 P18 P19 LSSD MODE E8 Low Input BVSEL 2 7 MCP C9 Low Input BVSEL OVpp B4 C2 C12 D5 E18 F2 G18 H3 J5 N A K2 L5 M3 N6 P2 P8 P11 R4 R13 R16 T6 T9 U2 U12 U16 V4 V7 V10 V14 PLL CFG 0 4 B8 C8 C7 D7 A7 High Input BVSEL PMON IN D9 Low Input BVSEL 10 PMON OUT A9 Low Output BVSEL QACK G5 Low Input BVSEL QREQ P4 Low Output BVSEL SHD 0 1 E4 H5 Low y o BVSEL 8 SMI F9 Low Input BVSEL SRESET A2 Low Input BVSEL SYSCLK A10 Input BVSEL TA K6 Low Input BVSEL MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 36 Freescale Semiconductor Pinout Listings Table 15 Pinout Listing for the MPC7445 360 CBGA Package continued Signal Name Pin Number Active 1 0 VF Select Notes TBEN E1 High Input BVSEL TBST F11 Low Output BVSEL TCK C6 High Input
91. y Application Modifier Revision Level XPC 7455 RX CBGA 1000 S 1 85 V 50 mV C 2 1 PVR 8001 0201 0 to 75 C 11 3 Part Marking Parts are marked as the example shown in Figure 31 MC7445A RX1000LG MMMMMM ATWLYYWWA BGA Notes MMMMMM is the 6 digit mask number ATWLYYWWA is the traceability code MC7455A RX1000LG MMMMMM ATWLYYWWA BGA Figure 31 Part Marking for BGA Device MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 62 Freescale Semiconductor Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC7455 RISC Microprocessor Hardware Specifications Rev 4 1 Freescale Semiconductor 63 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific

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