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ML630Q791 User`s Manual

1. Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S mbol name TmST TmRU Access R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing TMmCONI is a special function register SFR used to control the Timer m Description of Bits e TmRUN bit 0 The TmRUN bit is used for controlling stop start of timer m In the 16 bit timer mode be sure to set this bit to TmRUN Description 0 Stops counting 1 Starts counting e TmSTAT bit 7 The TmSTAT bit is used for indicating counting stopped counting in progress of timer m In the 16 bit timer mode this bit will read 0 TmSTAT Description 0 Counting stopped 1 Counting in progress FEUL630Q791 8 11 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 3 Description of Operation 8 3 1 Timer Mode Operation The timer counters TMnC are set to an operating state 5 are set to 1 on the first falling edge of the timer clocks TnCK that are selected by TnCS bit of the Timer 0 to 7 control register 0 TMnCONO when the TnRUN bits of timer 0 to 7 control register 1 TMnCON1 are set to 1 and increment the count value on the 2nd falling When the TMnC count value coincides the timer 0 to 7 data register TMnD value a timer
2. IRQ 10 SETENA 10 CLRENA 10 SETPEND 10 CLRPEND 10 NVIC IPR2 PRI 10 1 0 IRQ 11 SETENA 11 1 SETPEND 11 CLRPEND 1 1 NVIC_IPR2 PRI_11 1 0 IRQ 12 SETENA 12 CLRENA 12 SETPEND 12 CLRPEND 12 NVIC_IPR3 PRI_12 1 0 IRQ 13 SETENA 13 CLRENA 13 SETPEND 13 CLRPEND 13 NVIC IPR3 PRI 13 1 0 IRQ 14 SETENA 14 CLRENA 14 SETPEND 14 CLRPEND 14 IPR3 PRI 14 1 0 IRQ 15 SETENA 15 CLRENA 15 SETPEND 15 CLRPEND 15 IPR3 PRI 15 1 0 IRQ 16 SETENA 16 CLRENA 16 SETPEND 16 CLRPEND 16 IPR4 PRI 16 1 0 IRQ 17 SETENA 17 CLRENA 17 SETPEND 17 CLRPEND 17 IPR4 PRI 17 1 0 IRQ 18 SETENA 18 CLRENA 18 SETPEND 18 CLRPEND 18 IPR4 PRI 18 1 0 IRQ 19 SETENA 19 CLRENA 19 SETPEND 19 CLRPEND 19 NVIC_IPR4 PRI_19 1 0 IRQ 20 SETENA 20 CLRENA 20 SETPEND 20 CLRPEND 20 IPR5 PRI 20 1 0 IRQ 21 SETENA 21 CLRENA 21 SETPEND 21 CLRPEND 21 IPR5 PRI 21 1 0 IRQ 22 SETENA 22 CLRENA 22 SETPEND 22 CLRPEND 22 NVIC_IPR5 PRI_22 1 0 IRQ 23 SETENA 23 CLRENA 23 SETPEND 23 CLRPEND 23 NVIC IPR5 PRI 23 1 0 IRQ 24 SETENA 24 CLRENA 24 SETPEND 24 CLRPEND 24 NVIC_IPR6 PRI_24 1 0 IRQ 25 SETENA 25 CLRENA 25 SETPEND 25 CLRPEND 25 NVIC_IPR6 PRI_25 1 0 IRQ 26 SETENA 26 CLRENA 26 SETPEND 26 CLRPEND 26 NVIC_IPR6 PRI_26 1 0 IRQ 27 SETENA 7 CLRENA 27 SETPEND 27 CLRPEND 27 NVIC_IPR6 PRI_27 1 0 IRQ 28
3. This bit is not related to the SPI interface function Note PIODIR and PIOCON registers do not need to be set When the secondary function is selected the setting is automatically changed but the value of each register does not change FEUL630Q791 11 42 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 5 2 When Using SPI Interface Four wire Set PA4 bit 17 16 of the PAMOD register to 01 to select the secondary function 5 5 S of PA4 Set PAS bit 21 20 of the PAMOD register to 01 to select the secondary function SDO S of PAS Register PAMOD register address 0x4000 0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 Setting value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting x x x 0 1 x 0 1 value Set the bit 5 of the PIODIR register to 0 to set the input output mode of PAS to output When the secondary function is selected the setting of the bit 4 is automatically changed but the value of the bit does not change Register PIODIR register address
4. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENOS SYSC Symbol name LFLL 2 2 LK Access R RAW R W Initial value 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Depends on the state of FLL FCONI is a special function register SFR to control the high speed clock generation circuit and to select system clock Description of Bits FEUL630Q791 SYSCLK bit 0 The SYSCLK bit is used to select system clock Either low speed clock or high speed clock can be selected Switch the system clock to high speed clock after LFLL bit indicates that FLL oscillation clock is available Do not switch simultaneously the system clock to low speed clock with stop of FLL oscillation by ENOSC bit SYSCLK Description 0 Low speed clock LSCLK initial value 1 High speed clock HSCLK ENOSC bit 1 The ENOSC bit is used to select enable disable of the oscillator circuit of the internal FLL Use the LFLL bit to check that the FLL oscillation clock is available before using the FLL oscillation clock ENOSC Description 0 Stops internal FLL oscillation 1 Enables internal FLL oscillation initial value LFLL bit 7 The LFLL bit is used as a flag to indicate the oscillation state of the internal FLL When LFLL is 1 it indicates that the
5. Setting of PAn pin When output mode is selected When input mode is selected PIODIR n bit 0 PIODIR n bit 1 PIOCONn 1 0 Description 00 High impedance output initial value High impedance input 01 P channel open drain output Input with a pull down resistor 10 N channel open drain output Input with a pull up resistor 11 CMOS output High impedance input 0 6 In output mode the output state of the port varies depending on the settings of PIOCONn 1 0 and PIODAT n as shown in the table below Setting of PAn pin PIODAT n 0 PIODAT n 1 PIOCONn 1 0 Description PAn pin output state 00 High impedance output Hi z Hi z 01 P channel open drain output Hi z 1 10 N channel open drain output 0 Hi z 11 CMOS output 0 1 FEUL630Q791 15 5 LAPIS Semiconductor Co Ltd 15 2 5 GPIO Interrupt Enable Register PIOIE Address 0x4000 A010 Access R W Access size 32 Bits Initial value 0 0000 0000 ML630Q791 User s Manual Chapter 15 GPIO Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name _ _ _ _ _ _ _ _ _ _ _ _ Access z s z E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name PIOIE 6 0 Access RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved b
6. 2 2 Chapter 3 3 gt tena endet RU tun seis e ea e tee mie BERE Re dE 3 1 MERO KM 3 1 3 2 ne ORG Dt ee e REP i ue Gad iubeo 3 1 3 3 Internal Memory iere REDIERE be T ro nero ren e pet pei 3 4 3 3 1 Internal Flash ROM o eet ep RH REESE ERU SE Mert reti Pee OS ED 3 4 38 3 2 WK RAM e n DRE ERU DECR re PATER RO nt ber ran epe E ree gne 3 4 3 4 Memory Controller Function 1 REY RR nter EE SUE Mee e sees b Re SERRE eaten cis 3 5 8 43 Tastof Registets eene n ERE Pee cape PD I FU Qr e reete erp ees Ete ds 3 5 3 4 2 Remapping Control Register SYSCON REMAP CON seeseeeeeeeeeee nennen nennen teen 3 6 3 4 3 Remapping Base Address Register SYSCON REMAP 6 0 3 7 3 4 4 Boot Remapping F nction inocente reete P rere Se e aep 3 8 3 5 Access Response for Ee N eS p EE E EREE 3 8 Chapter 4 4 Reset FUnctiOns 5 oct a IE E eti Het 4 1 4 1 OVerVIew icone tein Solace e Id e it eet oe rte rt e Secs 4 1 4 1 1 Features oett oe n t EE ELE IE eR tts tiros 4 1 4 1 2
7. 1 Min 400us Min Ons Min 400us Min 10ms lt od o E Power on Power off VDD 3 gt Max 10ms Max 10ms RESET_N min 400us min Ous FEUL630Q791 C 8 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix D Application Circuit Example Appendix D Application Circuit Example eOverview Figure D 1 shows the examples of application circuits of ML630Q791 and Table D 1 shows the recommended values of capacitors and resistors in the circuits ML630Q791 SDI SCLK Host SCS interface Debug connector GND SDO SPI four wire NUUS 2 NTO SWD SWC RESET_N HST_RSTN General purpose port From host switch Remapping control switch 32 768 kHz oscillator Figure D 1 Example of Application Circuit of ML630Q791 open 2 interface Table D 1 Recommended Values of Circuit Constants Symbol Recommended value Cv 1 0uF CL 2 2UF eHost Interface With ML630Q791 the interface with the host processor can be selected from either I2C or SPI serial interface by setting the HIFCFG register Connection example for each is shown below 2 Slave Interface To use an I2C interface set the IFSEL bit of HIFCFG register to 1 For ML630Q791 an I2C slave address can be set by the HIFCFG register and the initial value is 17H Figure D 2 shows an I2C connection example FEUL630Q791 D 1
8. For details see 11 4 5Timing of Clearing Interrupt Request Register LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 6 CPURG FIFO Register HIFFIFO Address 0x4005_0010 Access R W Access size 8 32 Bits Initial value 0 0000 00XX Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name j P 5 ii 2 FIFO 7 0 Access RAN RAN R W R W RAW RAW R W RW Initial value 0 0 0 0 0 0 0 0 X X X X X X x x Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register FIFO register HIFFIFO is a special function register SFR consisting of 512 byte FIFO CPU can access this register when FSEL 0 CPU cannot access it when FSEL 1 Description of Bits e FIFO bit 7 0 This bit shows the FIFO data For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 10 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 7 CPURG FIFO Switch Register HIFFSEL Address 0x4005_0014 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name 5 Access Initial value 0
9. so sess For SCLK S 1 For SCLK S 2 For SCLK S 2 For SCLK S 1 SDIO s d4 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 7 e 5 4 3 2 1 of R W data R MSB LSB Internal address MSB LSB MSB LSB Read data Read data k 6 4 Figure 11 11 Read Sequence Three Wire FEUL630Q791 11 35 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 4 Description of Operation 11 4 1 Power down and Resume This LSI can conserve the power consumption by transitioning to the sleep mode while waiting for a command Resume from the sleep mode is possible by entering an external interrupt or writing 1 to the 610 ENT of HSTRG command entry register 0x32 from the host processor Note on the power down is as follows Confirm that both the RLTP and INTP bits of the operation status register HIFST are set to 0 before power down 11 4 2 Command Input and Processing of Response The host processor sets a parameter to the HSTRG parameter register 00 to OF 0x20 to Ox2F and a command to the HSTRG command register 0 and 1 0x30 and 0x31 Then writing 1 to the bit 0 ENT of the HSTRG command entry register 0x32 cau
10. gt Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Symbol name i 1 E 1 5 1 i 1 B 1 T 1 d 1 i 1 1 1 7 0 1 1 Access 0s 0s 2 RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 X X X X X X X X Note Reserved bit for future expansion 0 is read when reading Description of Register UARTRBR is a special function register SFR that provides the following three functions 1 Receiver Buffer Register RBR Read only register for buffering received data The RBR register is a data register for storing 5 bits to 8 bits of data depending on character length The bit 0 of the data word is always the first serial data bit that is transmitted or received When the UART carries out parallel to serial or serial to parallel conversion operation the ACE data register has the double buffer configuration so that read operations can be made For the UARTRBR register only read operations can performed with the program when LCR 7 0 The reset value is undefined 2 Transmitter Holding Register THR Write only register for setting transmitted data The UARTTHR register is a data register for storing 5 bits to 8 bits of data depending on character length When data of less than 8 bits is transmitted the data is right aligned to the LSB The bit O of the data word is always the first serial data bit that is transmitted When the UART carries out parallel to serial o
11. 11 24 11 2 21 HSTRG FIFO Registet FIEO ree tene Ine eo e Ene Peiper 11 25 11 2 22 HSTRG Parameter Register n PRMn 00 to OF essesseseseesseeeeeeenee 11 26 11 2 23 HSTRG Command Register On CMDn 1 0 to 1 enne nnne en nnne entente enne 11 27 11 2 24 HSTRG Command Entry Register ENT essent 11 28 11 2 25 HSTRG Result Register n RSLTn n 00 to 3F esses nene 11 29 1139 Serial Interface ec RE Ie emus E UE 11 30 IDE AMEND SUL RTL RT p Et 11 30 ectetuer e RM Ae M eC Oe 11 30 11 354 2 T CANS FORBAE ck Me D DE 11 31 11 3 2 S PETntetface nete tee digit I E E 11 33 T1 3 2 T SPI Trsnsfer Format me RR edet neis teri utei b etes beret s ae 11 34 11 4 Description of Operation uet HIR beet itin tette eer be EE 11 36 11 4 1 Power down and Resume 1 1 4 122 4 tenen nennen nennen entes senten EER E rennen rennen eren nns 11 36 11 4 2 Command Input and Processing of Response sees 11 36 11 4 3 Write Read Data to from 2 1 172 2 2 1 40 00000000 enne 11 37 11 4 4 Register Access Conflict by Host and CPU sst eripere es seenak spiedes eene nete treten tenere 11 3
12. Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting value Set the bit 1 of the PIODIR register to 0 to set the input output mode of PA1 to output Register PIODIR register address 0x4000 A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PIODIR 6 0 name Setting 0 value Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol 3 Setting value Bit not related to the S function Note The PIOCON register does not need to be set When the tertiary function is selected the setting is automatically changed but the value of the PIOCON register does not change FEUL630Q791 11 45 Chapter 12 2 Bus Interface LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 Bus Interface 12 1 Overview This LSI includes two channels of bus interface master that conforms to the typical bus spe
13. 3 Awaiting MCF interrupt I2CMTX 1 Write I2CRXAK 0 Check I2CRXAK 0 Chect I2CDR Write I2CMCF 0 Write I2CMCF 0 Write I2CMSTA 1 Write I2CDR Write I2CMSTA 0 Write 12 4 2 Waveform Received by Master S p 1 R W D7 T v D MCF HEU MCF biis MCF E ta MCF de jen MCF Em Awaiting MAL or MCF interrupt 7 9 gt 4 2 0 Write 2 0 Check 2 1 Write I2CMSTA 0 Write I2CDR Write I2CMCF 0 Write I2CMCF 0 Write 2 0 Write I2CMSTA 1 Write 2 0 Write I2CDR Read I2CDR Read I2CDR dummy Read 12 4 3 Waveform of Compound Format Master Transmission Master Reception C Pack COTY MCF interrupt 5 MCF TNT interrupt 26 BN Awaiting MAL or MCF interrupt 2 Awaiting MCF Awaiting MCF interrapt 9 6 7 Awaiting MCF interrupt 8 9 MCF interrupt 2 1 Write I2CRXAK 0 Check I2CRSTA 1 Write I2CRXAK 0 Check I2CTXAK 1 Write I2CMSTA 0 Write 2 Write 2 0 Write 2 1 Write I2CMCF 0 Write I2CMCF 0 Write 2 0 Write I2CMSTA 1 Write I2CDR Write 2 0 Write I2CTXAK 0 Write I2CDR Read I2CMCF 0 Write I2CDR Write I2CDR dummy Read I2CDR Read 12 4 4 Waveform of Compound Format Master Reception Master Transmission 5 MCF dons MCF SEU MCF TA MCF sone D
14. interrupt ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 26 LAPIS Semiconductor Co Ltd 6300791 User s Manual Chapter 12 I2C Bus Interface 12 3 2 Flow of Master Transmission START I2CCTL I2CMTX lt 1 I2CSR I2CMBB 0 o No es Ye Set master transmit mode gt Check Bus IDLE Set slave address and B W bit for I2CDR I2CCTL I2CMSTA 1 gt Create start condition Start slaveaddress transmission Create start condition gt Check arbitration lost Transmitting slave address Start Condition Wait for slave address transmission completion Check ACK NACK ES zoo T I p S Y No MES GC Waiting for transmitting I2CSR I2CMCF 0 gt Clear data transfer completion flag nent dato I CSR I2CMIF lt 0 Clear interrupt flag SCL L Write transmit data to 2 gt Set transmit data to start next 1 ____________ byte transmission i Transmitting 1 byte 1 Domee No gt Wait for data transfer completion 21 I2CSR Il2CRXAK 1 gt Check ACK NACK I2CSR I2CMCF 0 l2CSR I2CMIF lt 0 gt Clear data transfer completion flag Waiting for transmitting next data SCL L Clear interrupt flag Final byte transmitted No Yes I2CCTL I2ZCMSTA 0 gt Issue stop condition 2 1 Send stop condition Iw Bus IDLE ML630Q791 12 27
15. 0 1 0000 The internal Flash ROM is remapped to Banko 1 xxx1 The internal RAM is remapped to Banko 1 The area starting at the address set by the REMAP BASE register is x100 remapped to Banko 1 Other than 7 ova Setting prohibited x Don t care Notes on Setting 1 Operation cannot be guaranteed if remapping is performed when the remapping processing program instruction to set the remapping control register is placed in BankO Be sure to place the remapping processing program in a Bank other than BankO when performing the remapping 2 Remapping of is performed as soon as this register is set FEUL630Q791 3 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 3 4 3 Remapping Base Address Register SYSCON REMAP BASE Address 0 4000 0014 Access R W Access size 32 Bits Initial value 0x1001 F000 Bit 91 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbol name REMAP BASE 29 16 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW Intialvaue 0 0 1 0 0 0 0 0 0 0 O0 0 0 1 Bit 1514 4o 12 1 10 9 8 7 6 5 4 3 2 14 0 Symbol name REMAP_BASE 15 12 55 RAN RW RAN RW Initial value 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This is a special function register SF
16. P id p ct TnCS 1 0 Access RAN RAN R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing TMnCONO is a special function register SFR used to control the Timer n Rewrite TMnCONO while the timer n is stopped TnSTAT of the TMnCONI register is 0 Description of Bits e TnCS 1 0 bit 1 0 TnCS 1 0 is used for selecting the operation clock of the timer n LSCLK HTBCLK t2kHz or the external clock can be selected by these bits TnCS 1 0 Description 0 0 LSCLK initial value 0 1 HTBCLK 1 0 t2kHz 2 048 kHz 1 1 External clock PAO TIMER e TxxMI6 bit 2 The TxxM16 bit is used for selecting the operation mode of timer n and timer n 1 n 0 2 4 6 01 23 45 67 In the 8 bit timer mode each of timer n and timer 1 operates independently as an 8 bit timer In the 16 bit timer mode timer n and timer 1 are connected and they operate as a 16 bit timer In the 16 bit timer mode timer n 1 is incremented by a timer n overflow signal A timer n interrupt TMnINT is not generated 16 Description 0 8 bit timer mode initial value 1 16 bit timer mode FEUL630Q791 8 8 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 2 7 Timer m Control Register 0 TMmCONO m 1 3 5 7 Address 0 4000 1418 TMICONO 0x4000 1818 TM3CONO
17. ptite 9 2 92 2 PWM Cycle Registet PWOP rennes imo t UE ten DU Item t ttes neve ete Abie 9 3 9 23 PWM Duty Register PWOD uii tette o UE enn Ue tete preesse mieten quet een 9 4 9 24 PWMO Counter Register PWOG cro rrt PO ere tr rie ER PRECII err e ERES ERRAT E PERS 9 5 9 25 PWMO Control Register 0 205 9 6 9 26 PWMO Control Register PWOCONLL ieri i retener PERO rte ee ee bet rhe recie egenis 9 7 9 3 Description of Operation iere ie He RET ri pei ue iei YR e ep E Dents 9 8 94 Port Register Settings hee e ROO Od p D EP PE Ee bct 9 10 9 4 1 Functioning PAO Pin PWMO as PWM 9 10 9 4 2 Operating PWMO with External Clock PWM sese 9 11 Chapter 10 10 Watebdog Mn ME EE 10 1 VO Via OVervIe Wis stet ie e EN e REP Pee Urbe ete ede a 10 1 1021 Feat tes oia t Geta ee ee iere e eee peu 10 1 10 1 2 Configuration co e RO REIR EO PU Bee eek ade fete cee ete orbe Ire ecd ce 10 1 10 2 Description of Registers nb eee d etri cette ertet eerie c Eee ERR De Ete 10 2 Isque EE 10 2 10 2 2 Watchdog Timer Control Register nenne
18. Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name Setting value Bit not related to the PWM function Note The PIOCON register does not need to be set When the tertiary function is selected the setting is automatically changed to the high impedance output but the value of PIOCON register does not change FEUL630Q791 9 10 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 4 2 Operating PWMO with External Clock PWM Set PAO bit 1 and 0 of the PAMOD register to 10 to select the tertiary function of PAO Register PAMOD register address 0x4000_0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 PA1 PAO name Setting x x x x x x x x 1 0 value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol 2 PA6 5 PA4 name Setting x x x n n n n n n n n x x x n x value Set the bit 0 of the PIODIR register to 1 to set the input output mode of PAO to input Register PIODIR reg
19. aah ymp name Co CAL UART I2C1 12C0 Access RAN R W R W R W RW RAN RAN RAW RAW R W R W RAN RAN RAW RW RW Initial value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1514 1 12 11 10 9 8 7 6 5 4 3 2 1 0 sanama a trage a a OEE Cell sce Ce Ce 4 HTC PWM TM7 TM6 TM5 4 TM2 TM TMO Access RAN RW R W R W R W RAN RAN RAN RW RAN RAW RAN RW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing PECLKEN is a special function register SFR used to start the clock of each peripheral and can be accessed only by writing 1 Access by writing 0 is invalid When the peripheral clock disable register PECLKDIS is accessed by writing 1 the corresponding bit of PECLKEN is automatically reset to 0 The clock enable state of each peripheral 1 indicates the enable state be read when reading Description of Bits Symbol Description Related Bit name PERSTEN PECLKDIS PERSTDIS CETMn To start the operation of Timer n n 0 to 7 RETMn CDTMn RDTMn n 0 7 write 1 to this bit n 0 7 n 0 7 n 0 7 CEPWM To start the operation of PWM write 1 to this REPWM CDPWM RDPWM bit CEHTC To start the operation of high speed clock time REHTC CDHTC RDHTC base counter write 1 to this bi
20. 22 23 16 Access D 1010000007000 RW RW RW RW RW RW RW Initialvalue O0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 14 0 Symbol name FSCPP22E 15 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP22E is a special function register SFR used to set the value to start enabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits FSCPP22E 23 0 bit 23 0 For FSCPP22E 23 0 the write signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 17 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 17 Set Count Program PROG2 2nd Disable Register FLCSCPP22D Address 0 4000 0490 Access R W Access size 32 Bits Initial Value 0x0000 0247 Bit 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 Symbol name 50050040 0 0 3 FSCPP22D 23 16 Access RW RW RW RW RW RW RW Initialvalue 0 0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 14 0 Symbol name FSCPP22D 15 0 Access RW RAN RAN RW RW R
21. FEUL630Q791 13 21 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 6 Error Status a Overrun error An overrun error indicates that the data in the UARTRBR register was not read out before the next character was sent to the UARTRBR register and overwrote the previous character This error will set the LSR 1 bit of the UARTLSR register b Parity error A parity error indicates that the parity of the received data and the received parity bit did not match This error will set the LSR 2 bit of the UARTLSR register Note that this error will only occur when parity is enabled In FIFO mode this error is associated with the leading data in the FIFO Even if a parity error associated with any data other than the leading data in the FIFO had occurred it will not be indicated on the LSR 2 bit of the UARTLSR register c Framing error A framing error indicates that there is no valid stop bit in the received character This error will occur when the stop bit after the last data bit or after the parity bit is 0 spacing level This error will set the LSR 3 bit of the UARTLSR register In FIFO mode this is related to a specific character in the FIFO LSR 3 indicates that an error is present when that character comes to the beginning of the FIFO d Break interrupt A break interrupt indicates that the input data was maintained in the spacing 0 state during the transmission of one frame start bit
22. I2CDR LD Description 0 Data load to the data register is not allowed 1 Data load to the data register is allowed Note This bit is used as a spare function It is not used in the operation sequence I2CMBB bit 5 Indicates the status of the bus This bit is set to 1 when a START condition is detected this bit 1s reset to 0 when a STOP condition is detected By reading this bit it is possible to check whether the bus is currently occupied or released This bit is set to 1 after a START condition is detected at a falling edge of SCL after SDA changes from 1 to 0 when SCL is 1 and is set to 0 after a STOP condition is detected at a rising edge of SDA when SCL is 1 I2CMBB Description 0 The 2 bus is open 1 The bus is occupied Note Before starting a master transmit or master receive transfer read this bit and make sure that the bus is open I2CMCF bit 7 Indicates that data transfer has been completed This bit is set to 1 when the transmission reception of 1 byte data 1 is complete This bit is cleared by writing 0 by software This bit is set to 1 at a rising edge of SCL when a 1 byte transfer is complete and an ACK response is started 1 The data signifies all of the 1 byte transfer which includes the transfer of an address immediately after start repeated start that the master transmits I2CMCF Desc
23. P t Symbol Condition Unit SERIES ymse B Min Typ Max IDD2 CPU stop 1 2 5 120 uA Sleep Power consumption IDD3 CPU 32 768kHz operation 1 0 5 0 7 Low speed operation Foe cone pon IDD4 CPU 32MHz operation 5 0 6 5 mA High speed operation power EDT DOR RESETN pin is Low 0 4 0 6 1 operate with the low speed clock and stop the high speed clock FLL Peripherals except HostlF are initial state eDC Characteristics 2 2 1 7 to 1 9V GND 0V 40 to 85 Condit Standard value Unit arameter ymbo ondition Min Typ ni Output voltage 1 VOH1 SDAO M SCLO M V PAO 1 PA1 1 VOL1 IOL x02 SCL S 2 SDA S 2 Vpop Output voltage 2 VOH2 IOH 2mA 0 45 V Other pins VOL2 IOL 2mA 0 45 Output leakage IOOH YON phis 1 in high impedance state A m VOL 0V E k in high impedance state IIH1Z VIH Vpp 1 inut euren IIL1Z VIL GND 1 A Von pull down 2 200 VIL GND pull up 200 2 VIH1 gt Voo x 0 7 Input voltage V VIL1 x 0 3 1 Output voltage 1 shows the characteristic in case the secondary pin function I2C is selected 2 Output voltage 1 shows the characteristic in case I2C is selected for host interface FEUL630Q791 C 2 LAPIS Semicond
24. Status Register I2CSRO 1 Address 0 4008 3008 Och 0 4008 3408 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symibolnam l2CIS l2CNS 2CAK I2CRB I2CM Il2CMB 2CDR 2 UF CF B _LD F AK Access R W R W R W E R W R W R W RAN R W Initial value 0 0 0 0 0 0 0 0 0 o 0 0 The read data of this register is Reserved bit for future expansion Write 0 when writing Description of Register This register indicates the status of the IC bus The bits other than the 2 I2CMIF I2CSRW I2CMBB I2CRBUF I2CDRSTA and I2CAKMON bits will be cleared by writing 0 Only the I2CMBB bit is used in the buffer mode Description of Bits I2CRXAK bit 0 Indicates the reception status of ACK NACK Acknowledge data to be replied by the receiving device in the transmit mode is stored This bit is updated every time ACK NACK is received and this bit holds the acknowledge data received last even after the bus is released In the transmit mode check this bit at the time of an MCF interrupt If a NACK 15 received finish the transfer I2CRXAK Description 0 Received
25. Transferring baud rate trBRT BRT S Xa BRT BRT Receiving baud rate tRBRT 3 BRT 3 1 Baud rate period including the error of the clock frequency selected set with the UARTO baud rate register UAOBRTL H and the UARTO mode register 0 UAOMODO treRT tRBRT FEUL630Q791 C 4 LAPIS Semiconductor Co Ltd eAC Characteristics Host Interface 2 Slave Interface ML630Q791 User s Manual Appendix C Electrical Characteristics 1 7 to 1 9V GND 0V 40 to 85 C Standard value Parameter Symbol Condition Unit Min Typ Max SCL S clock frequency fscL 400 kHz SCL_S hold time start restart tup sTA 0 6 us condition SCL_S L level time 1 3 us SCL S H level time 0 6 us SCL_S setup time restart condition IsussTA pa 2 SDA S hold time 0 ns SDA S setup time tsu DAT 0 1 us SDA S setup time P Stop condition lsusro 0 6 Hs Bus free time tBuF 1 3 us Start Restart Stop condition condition condition SDA S Y 5 is 7 lt gt lt gt lt gt lt gt EB itBurF i 4 tsusro HD STA low tuu tsu sta HD STA tsu pat tHD DAT FEUL630Q791 C 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual
26. PA4 PAS SDAO M SCLO M 5 2 BRMP VPP 4 GND PAO SWD SWC 3 VDDL PA1 SDA S CLK 2 VDD RESET N PA6 SCL S 1 D C B A 20 pin WL CSP Package S UFLGA20 1 84x2 14 0 40 W Bottom View Figure 1 2 Pin Layout of ML630Q791 Package FEUL630Q791 1 4 LAPIS Semiconductor Co Ltd 1 4 List of Pins ML630Q791 User s Manual Chapter 1 Overview PIN Primary function Secondary function Tertiary function Que Pin name pow Description Description Pinname Description D3 GND Power Supply D1 VDD Power Supply D2 VDDL Power Supply A2 CLK HZ SYSTEM B4 BRMP PD SYSTEM SWC PU DEBUG I F B3 SWD IO PU DEBUG I F C1 RESET N l PU SYSTEM A1 SCL S SCLK 6 HZ HSTIF B2 SDAS 10 SDIO S IO HZ HSTIF SDI_S D5 4 IO HZ GPIO SCS_S HSTIF C5 PA5 IO HZ GPIO SDO S HSTIF B5 SDAO0 M IO HZ 12C0 A5 SCLO M HZ 12C0 C4 PA2 IO HZ GPIO RXDO UART D4 IO HZ GPIO TXDO UART C3 IO HZ GPIO SDA1 M IO 12C1 PWMO IO PWM C2 PA1 IO HZ GPIO SCL1 M 12 1 S HSTIF B1 PA6 IO HZ GPIO INTO S HSTIF
27. to the I2CMSTA bit Because this bit is automatically reset to 0 after sending the repeated START condition if another bit in the control register will be set after this bit is set to 1 set this bit to 0 or keep the previous value If 1 is written again the repeated START condition will be sent at that very moment This bit also indicates the status of ROM controller This bit is 1 during sector erase 1 word write It automatically changes to 0 when sector erase 1 word write is completed ML630Q791 12 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface RCTXAK bit 3 Specifies transmission of ACK or NACK in the receive mode The acknowledge data that was set to this bit in advance is sent to the transmit device after data is received I2CTXAK Description 0 At acknowledge output timing outputs 0 output 1 At acknowledge output timing outputs 1 NACK output I2CMTX bit 4 Selects the data transfer direction I2CMTX Description 0 Received by master 1 Transmitted by master I2CMSTA bit 5 Specifies to transmit a START condition or a STOP condition If this bit is rewritten from 0 to 1 a start sequence is sent to the bus When this bit is cleared a stop sequence is sent I2CMSTA Description 0 Sends a STOP condition 1 Sends a START condition I2CAASIE bit 6 Specifies to ena
28. 0 es Yes 0 S Yes Yes N Write transmit data to I2CDR No Y I2CSR I2CMCF 0 I2CSR I2CMIF 0 Final byte transmitted N M N N No Yes I2CCTL I2CMSTA 0 ML630Q791 Set slave address to start slave address transmission Check arbitration lost Repeated Start Condition Wait for slave address transmission completion Check ACK NACK Clear data transfer completion flag Clear interrupt flag Set transmit data to start next 1 byte transmission Wait for data transfer completion Check ACK NACK Clear data transfer completion flag Clear interrupt flag Issue stop condition ML630Q791 User s Manual Chapter 12 I2C Bus Interface Create repeated start condition Transmitting slave address Waiting for transmitting next data SCL L Transmitting 1 byte Waiting for transmitting next data SCL L Send stop condition To Bus IDLE 12 32 LAPIS Semiconductor Co Ltd 6300791 User s Manual Chapter 12 I2C Bus Interface 12 3 6 Flow When Using Buffer Mode Set slave address for I2CBUFSLV Set sub address for I2CBUFSUB gt Clear buffer 0 Transmit data Yes Write transmit data to IBCDR Set communication format for I2CBUFFOR I2CSR I2CMBB 0 Yes I2CBUFCTL I2CBMSTA lt 1 l2CBUFSTA I2CBMDZ 1 No I2CBUFSTA I2CBMAG 1 Yes No I2CBUFSTA I2CBMIS 1 Yes No I2CBUFSTA I2CBMTO 1 Y
29. 1 to the GPIO interrupt status register PIOIS from CPU the GPIO interrupt status register PIOIS is cleared to 0 and the interrupt is released at the same time If 1 is written to the GPIO interrupt status register PIOIS from CPU while the input signal of GPIO pin is L the GPIO interrupt status register PIOIS is not cleared to 0 and the interrupt is not released If an interrupt source is generated at the same timing as the release of the interrupt from CPU the interrupt generation has priority Figure 15 4 shows an operation example GPIO Port To or 1 1 1 lEn i i ron Mn i n A B ISn i n A B IMASKn n A B INTn 1 y n A B 4 1 1 Period from interrupt assertion to internal interrupt generation Up to 2 cycles at 16 kHz 2 Interrupt status clear disable period after the interrupt source clear GPIO pin is deasserted Up to 2 cycles at 16 kHz Even if the interrupt status is cleared during this period the interrupt signal is not released 3 Interrupt status clear Write 1 to the ISn bit 1 Internal interrupt signal Figure 15 4 Example of L level Input Interrupt Operation For Detection without Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 0010 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when the i
30. 4 VPP TEST 1 The used pin is determined by HSTIF setting FEUL630Q791 1 5 LAPIS Semiconductor Co Ltd 1 4 1 Pin Description ML630Q791 User s Manual Chapter 1 Overview Power Supply Pin name Description Polarity GND VDD IO power supply VDDL Core power supply generated by the internal regulator SYSTEM Pin name Description Polarity CLK Clock input 32 768 kHz BRMP Remapping control input for firmware update mE Based on the BRMP pin setting at the time of the reset release BankO0 is remapped See 3 4 4 Boot Remapping Function for details RESET N Reset input Negative DEBUG Interface Pin name Description Polarity SWC Serial clock of Serial Wire Debug Port SWD IO Serial data of Serial Wire Debug Port Host Interface HSTIF Pin name Description Polarity SCL S SCL of I2C slave interface SDA S IO SDA of I2C slave interface SCLK_S SCLK of SPI slave interface SDIO S IO SDI and SDO of SPI slave interface three wire SDI_S SDI of SPI slave interface four wire 5 5 S SCS of SPI slave interface 1 SDO S SDO of SPI slave interface four wire INTO S Interrupt output 0 for host IF Negative 5 Interrupt output 1 for host IF Negative 1 The polarity can be set by the software 2 3 6V tolerant in case of lC interface I2C master
31. Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T T T T T T T T T T T T T Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TnST TnRU Symbol name AT N 1 1 1 1 1 1 1 1 1 1 1 1 Access R RAN Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing TMnCONI is a special function register SFR used to control the Timer n Description of Bits e TnRUN bit 0 The TnRUN bit is used for controlling stop start of timer n TnRUN Description 0 Stops counting 1 Starts counting TnSTAT bit 7 The TnSTAT bit is used for indicating counting stopped counting in progress of timer n TnSTAT Description 0 Counting stopped 1 Counting in progress FEUL630Q791 8 10 LAPIS Semiconductor Co Ltd 8 2 9 Timer m Control Register 1 TMmCON 1 m 1 3 5 7 Address 0 4000 141C TM1CON1 0x4000 181C TM3CON1 0x4000 5 0x4000 201C TM7CON1 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 ML630Q791 User s Manual Chapter 8 Timer T T T T T T T T T T T T Symbol name
32. Internal PLE Oscillation iet o eret Eee aet Gea tee ebd tr ve eee ehe lus 6 6 6 3 3 Low Speed Time Base Counter tese eei 6 6 6 34 High Speed Time Base Counter teet ite dete deci eie totae eee en e cone 6 6 Chapter 7 Js Ul gel e eerie eee ee eO P e RR RR D PRO DEO 7 1 EE 7 1 T TL 7 1 752 JD seriptoon oF Reglslets T rr rete UR UESTEED 7 2 7225 Listo Registers ce ed oe RT e t PR UE erre E CR PER RB EE 7 2 7 222 Correspondence with Bits iet ete t OPERE HE COT E FE EEG Ee CER E ER reb Dae RETE DERE ES 7 3 7 3 Desertption of Operation t e eS RR GRE e IER ERE eee PEDRO BER EE 7 4 Chapter 8 den EN n UR RN 8 1 8T FOVEEVIEW s ere terit PE eti ise e m d 8 1 8115 Beatures 5o Nd 8 1 8 1 2 Configuration o eiue 8 1 ARCEM DEMONS RR 8 2 8 22 Description of ed tee e e di e eee i e e e e is 8 3 8 2 Tast of Registers os eoe eoe te efe e ee em 8 3 8 2 2 Timer n Data Register TMnD n 0 2 4 6 8 4 8 2 3 Timer m Data Register TMmD m 1 3 5 7 eE N e E EE A RE ENS 8 5 5 24 Tamern Counter Register PMnC n 0 2 4 0 eerte eet He re e P eret 8 6 8 2 5 Tim
33. To communicate with the host processor such as application processors this LSI includes a host interface that has a SPI or interface and interrupt and register functions For interrupts to the CPU see Chapter 7 Interrupt 11 1 1 Features e SPI or I2C can be selected as an interface with the host processor For SPI four wire or three wire can be selected And SCS polarity can be selected For four wire HiZ or Low output can be selected as a data output signal in the no output mode e Controls the interrupt signal to the host processor Two interrupt signals can be controlled individually as usage e WDT overflow causes a notification of abnormal state to the host e When command is input by the host processor a CPU interrupt occurs allowing the CPU to receive the command Note As for SPI if Host keeps SCLK high while communication is standby there are cases when this LSI cannot enter SleepDeep mode until 5 5 S becomes non active 11 1 2 Configuration Figure 11 1 shows the configuration of the host interface PA5 SDO S Beni 512Byte FIFO SDA S SDIO S SDI S0 9 HSTRG 4 5 5 5 gt paeem lt SCL_S SCLK_Si gt CPU interrupt signal HSTINT PA6 INTO_S PATINTI S Ge lt WDT overflow signal APB data bus Figure 11 1 Configuration of Host Interface FEUL630Q791 11 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2
34. 0000 FFFF Bit 31 30 29 28 ML630Q791 User s Manual Chapter 9 PWM 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name E x m E P P P x E zd x P F EB Access gt 2 E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name POP 15 0 Access R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 1 1 1 1 Note Reserved bit for future expansion Description of Register 1 1 1 1 1 1 1 1 1 1 1 0 is read when reading PWOP is a special function register SFR to set the period Note When PWOP is set to 0x0000 the PWMO period buffer PWOPBUF is set to 0x0001 FEUL630Q791 9 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 2 3 PWMO Duty Register PWOD Address 0x4001 4404 Access R W Access size 32 Bits Initial value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name n i E Access E M s 2 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name Access RAN R W R W R W RW RAN RAN R W RAW R W R W RAN RAN RAN RW RW Initial value 0
35. 0x4000 A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PIODIR 6 0 name Setting x x 0 x x x x x value Register PIODIR register address 0x4000_A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol 5 gt 5 z gt Setting value This bit is not related to the SPI interface function Note The PIOCON register does not need to be set When the secondary function is selected the setting is automatically changed but the value of the PIOCON register does not change FEUL630Q791 11 43 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 5 3 When INTO S Is Used Set PAG bit 25 and 24 of the PAMOD register to 01 to select the secondary function of PA6 Register PAMOD register address 0x4000 0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 Setting x value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting 0
36. 1 to use in the buffer mode 2 Description 0 Buffer mode is not used 1 Buffer mode is used Note Set this register in the initial setting flow or before the master transfer start Operation cannot be guaranteed if the value of this register is changed during transfer ML630Q791 12 13 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 8 Buffer Mode Slave Address Register I2CBUFSLVO 1 Address 0 4008 301C Och 0 4008 341C 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access gt s 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name I2CBMSLV 1 5 0 Access RAN R W R W RW R W RAW RAW RAW R W R W R W RAW R W R W RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register I2CBUFSLVV register sets the slave address of the transfer destination device This register is enabled only when the buffer mode is used Description of Bits I2CBMSLV bit 15 0 Sets the slave address of the transfer destination device Set I2CBMSLV7 1 to 7 bit address Set IJCBMSLV 15 8 and 0 to 0 dul dE Mee o t 10 9 8 I2CBUFS ms das ns POS PAS me 0
37. 11 11 11 2 8 CPURG FIFO Write Pointer Register 11 12 11 2 9 CPURG FIFO Read Pointer Register HIFRP 11 13 11 2 10 CPURG Parameter Register HIFPRMF HIFPRMB HIFPRM7 HIFPRMO sse 11 14 11 2 11 CPURG Command Register netten nennen 11 15 11 2 12 CPURG Result Register n 1 00 to 11 16 11 2 13 HSTRG Configuration Register 11 17 11 2 14 HSTRG Interrupt Mask Register 0 INTMSKO 11 18 FEUL630Q791 iii LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents 11 2 15 HSTRG Interrupt Mask Register 1 INTMSK1 esee nennen eene enne enne 11 19 11 2 16 HSTRG Operation Status Register 5 5 11 20 11 2 17 HSTRG Error Code Register 0 ERRORO eeessseseeeeeeeeeee nente nns 11 21 11 2 18 HSTRG Error Code Register 1 1 0 222 0040 1 2 00 000000000000000000000 11 22 11 2 19 HSTRG Interrupt Request Register 0 0 11 23 11 2 20 HSTRG Interrupt Request Register 1 1
38. 14 2 9 Calculation Result Register IL CALRIL 14 10 14 2 10 Calculation Result Register LH CALRIH esses ener nnne nnne enne nenne nennt 14 11 14 3 Description of Operation oie reete eterne EO RI CE Me ee SERE REA 14 12 14 351 DIVISION 5 een ete deii e ed A Rede e EUR UI eet 14 12 14 3 2 Root Op ration ee dre eee dede p mE Er Gene eve eee 14 12 Chapter 15 ICI 15 1 15 1 OVeEVIEWZ a Gier itti eR ER ee otn tea dote eese tette neon e es 15 1 Feat res eo Eee ERU Rao Upon 15 1 IB COMMPULATON E 15 1 IM EM List Of PINS 15 1 15 2 Description of Registers eee Det pe cb p eee ea or EEEE AAE E a iE EEE RESETE Erihs Tes 15 2 15 21 Dist 9f Registers rote Oa ae REOR EP Oe Een Etre HERE ERE 15 2 15 22 GPIO Port Data Register PIODAT 2 rater ehe eei pM erbe a HERR PE 15 3 15 2 3 GPIO Port Direction Register PIODIR E tenen nest tenen nennen en 15 4 15 2 4 GPIO Port Control Register PIOQON y rete AE EP REC REFER SEE i rU 15 5 15 2 5 GPIO Interrupt Enable Register PI
39. 16 2 15 Set Count Program PROG2 1st Disable Register FLCSCPP21D Address 0 4000 0488 Access R W Access size 32 Bits Initial Value 0 0000 0313 Bit 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 Symbol name FSCPP21D 23 16 Access D 10 00000007007 w RW RW RW RW RW RW RW Initialvalue 0 0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 14 0 Symbol name FSCPP21 D 15 0 Access RW RW RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP21D is a special function register SFR used to set the value to start disabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCPP21DI 23 0 bit 23 0 For FSCPP21D23 to FSCPP21D00 the write signal to Flash ROM is disabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 16 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 16 Set Count Program PROG2 2nd Enable Register FLCSCPP22E Address 0x4000 048C Access R W Access size 32 Bits Initial Value 0x0000 0311 Bit 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 Symbol name
40. 2 0 Check I2CBUFSUB Write I2CBMSTA 1 Write I2CBUFLEV 0 Write I2CBUFFOR 0x1C Write Slave address transmission 1 byte Data reception 1 byte gt Repeated START 1 hb Stop SD a A XY N X A7 X e X X 1 X RWX D7 X NACK SCL gt dew ku X fo Nf Nu I2CBMFI interrupt 1 Waiting for transfer completion transfer error I2CBMFI 0 Write I2CDR Read ML630Q791 12 38 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 4 11 Waveform 7 When Using Buffer Mode When data length of sub address 1 data transmission number of transferred bytes 32 Slave address transmission 1 byte Sub address transmission BMSUBO gt SDA zd A7 A6 A1 RI AE SA7 SCL NI Waiting for transfer completion transfer error I2CBUFSLV Write 2 0 Check I2CBUFSUB Write lPICBMSTA 1 Write I2CBUFLEV 0 Write I2CDR Write I2CBUFFOR 0x201 Write Data transmission 32 bytes E gt 0 0 Stop Spa 5 01 X dd SCL rrr I2CBMFI interrupt Waiting for transfer completion transfer error e I2CBMFI 0 Write 12 4 12 Waveform 8 When Using Buffer Mode When data length of sub address 1 data reception number of transferred bytes 32 Slave add
41. Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name TnC 15 8 TnC 7 0 Access RW RW RAW RW RAW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing TMnC is a special function register SFR that functions as an 8 16 bit binary counter When a write operation is performed to TMnC TMnC is set to 0x0000 0000 The data that is written is meaningless In the 16 bit timer mode a write operation to either the TMnC or TM n 1 C register sets 0 0000 0000 to both of them n 0 2 4 6 During timer operation the TMnC content may not be read depending on the conditions of the timer clock and the system clock Table 8 1 shows whether a TMnC read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 1 TMnC Read Enable Disable during Timer Operation i prox TMnC read enable disable LSCLK Read enabled LSCLK Read enabled However to prevent the reading of uncertain data HSCLK during incremental counting read TMnC twice and check that the results match LSCLK Read disabled HSCLK Read enabled Read enabled However to prevent the reading of uncertain data LSCLK during incremental counting read TMnC twice and check that the kHz results match Read enabled However to prevent the rea
42. Appendix C Electrical Characteristics Characteristics Host Interface SPI Slave Interface 1 7 to 1 9V GND 0V 40 to 85 C Standard value P t Symbol Condition Unit arameter ymbo on Min Max SCLK S input cycle tscvc 250 ns SCLK S input pulse width tsw 120 ns 80 ns SCS S setup time 2 80 ns tout 80 ns SCS S hold time tcH2 80 ns SCS S input pulse width 90 ns SDO S output delay time tsp 100 ns SDI S input setup time tss 60 ns SDI S input hold time tsu 60 ns tscyc tsw tsw lt lt SCLK S SCLK S _ ton lt tcw 1 As for SPI if Host keeps SCLK high while communication is standby there are cases when this LSI cannot enter SleepDeep mode until SCS S becomes non active 2 Either High active or Low active can be selected for polarity of SCS S FEUL630Q791 C 6 LAPIS Semiconductor Co Ltd e AC Characteristics I2C Master Interface Standard Mode 100 kHz 1 7 to 1 9V GND 0V 40 to 85 ML630Q791 User s Manual Appendix C Electrical Characteristics 4c Standard value Parameter Symbol Condition Unit Min Typ Max SCLn M clock frequency 100 kHz SCLn M hold time start restart tHD sTA
43. Awaiting MAL or MCF interrupt 2 3 MCF interrupt 4 Awaiting MCF 7 amp awaiting MCF interrupt 9 I awaiting MCF interrupt 7 42 I2CMTX 0 Write 2 0 Write 2 1 Write I2CMCF 0 Wri l2CDR Write 12 0 Write 2 0 Write I2CDR Write 2 0 Write I2CMCF 0 Write I2CRSTA 1 Write I2CDR Write I2CMSTA 0 Write I2CMSTA 1 Write I2CDR dummy Read 2 Read 2 1 Write I2CDR Read ML630Q791 12 36 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 4 5 Waveform 1 When Using Buffer Mode When data length of sub address 0 data transmission number of transferred bytes 1 Slave address transmission 4 1 A Slave address transmission 1 byt byte Data transmission 1 by Data transmission 1 byte SDA wN PE A1 BW CAII D7YX ACK prom j X oU Singh e uo UN I2CBMFI uw Waiting for transfer completion transfer erres 3 I2CBUFSLV Write 1 2 0 Check I2CBUFLEV 0 Write IZCBMSTA 1 Write 2 0 Write I2CDR Write I2CBUFFOR 0x10 Write 12 4 6 Waveform 2 When Using Buffer Mode When data length of sub address 1 data transmission number of transferred bytes 1 Slave address transmission 1 byte Sub address transmission BMSUBO Data transmission q byte
44. Further the receive FIFO generates 3 bits of error data for every byte of received data The CPU can read out the status of ACE at any time The information that can be read out consists of the type and status of the transfer operation under execution and the statuses of errors such as parity overrun or framing errors or break interrupt etc The use of UART requires setting of the secondary functions of Port A For the secondary functions of Port A see Chapter 5 MCU Control Function 13 1 1 Features Full duplex buffer system status reporting function 16 byte transmit and receive FIFOs Independent control of transmit receive line status data set interrupt and FIFO Programmable serial interface 5 6 7 or 8 bits per character Odd parity even parity no parity generation and verification 1 1 5 or 2 stop bits e Communication speed Settings available in the range of 300 bps to 115200 bps FEUL630Q791 13 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 1 2 Configuration Figure 13 1 shows the configuration diagram of the UART RXDO Receive control Baud rate Bus signal 7 generation Transmis sion control 19591 9 joj1uoo sng TXDO 101 XN Interrupt Interrupt control Figure 13 1 Configuration Diagram 13 1 3 List of Pins Table 13 1 List of Pins Interfaced with the Outside of LSI Description UART data input
45. HTBCLK 4 MHz to 250 kHz and an external clock are available 9 1 2 Configuration Figure 9 1 shows the configuration of the PWM circuit Write PWOC PONEG 2 29n0 PAO PWMO Output control PWQINT circuit To Cycle Duty matched Comparator LSCLK gt pwocono HTBCLK gt pwocont 29 2 048 kHz External gt PAO PWMO 32 Data bus PWOP PWMO cycle register PWOPBUF PWMO period buffer PWOD PWMO duty register PWOPBUF PWODBUF 1 PWOP PWOD FEUL630Q791 PWODBUF PWMO duty buffer PWOC PWMO counter register PWOCONO PWMO control register O PWOCON1 PWMO control register 1 p P Figure 9 1 Configuration of PWM Circuit 9 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 1 3 List of Pins Input setting PWMO external clock input pin PAO PWMO Output setting PWMO output pin Used for the tertiary function of the PAO pin 9 2 Description of Registers 9 2 1 List of Registers bits 0x4001 4404 PWMO duty register PWOD R W 32 0x0000 0000 0 4001 440 PWMO control register 0 PWOCONO R W 32 0 0000 0000 0 4001 4410 PWMO control register 1 PWOCON1 0 0000 0040 FEUL630Q791 9 2 LAPIS Semiconductor Co Ltd 9 2 2 PWMO Cycle Register PWOP Address 0x4001 4400 Access R W Access size 32 Bits Initial value 0
46. IIR3 1 bit 3 1 Indicates the interrupt sources ML630Q791 User s Manual Chapter 13 UART IIR7 6 bit 7 6 Indicates operation in FIFO mode IIR3 1 LVL Flag Soruce Reset Process 011 1 Receiver Line Status OverrunError ParityError FramingError Read LSR Breaklnterrupt 010 2 Received Data 16450 compatible mode receive data Read RBR or when Available available FIFO drops below FIFO mode trigger level has been trigger level reached 110 2 Character Timeout At least one character is present in the Read RBR Indication receive FIFO and no other character was placed into or read out within 4 character time 001 3 Transmitter Holding 16450 compatible mode THR write Read IIR or write THR Register Empty enabled THRE FIFO mode transmit FIFO is empty IIR7 6 Description 00 Non FIFO mode 01 Unused 10 Unused 11 FIFO mode FIFO Control Register FCR Write only register for FIFO settings The FCR register is used for enabling and clearing the FIFO The trigger level of the receive FIFO is also set with this register For the FCR register only write operations can be performed with the program bit 0 FIFO Enable bit Enables disables the FIFO Enables FIFO Note FIFO will be cleared when you switch between FIFO enable disable bit 1 RCVR FIFO reset Clears the receive FIFO Description Disables FIFO
47. LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 4 Reset Functions 4 2 Description of Registers SYSRESETREQ is controlled by the SYSRESETREQ bit of the AIRCR register of Cortex MO For details see Cortex M0 Devices Generic User Guide FEUL630Q791 4 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 4 Reset Functions 4 3 Description of Operation 4 3 1 System Reset Mode System reset has the highest priority among all the processing and any other processing being executed up to then is cancelled The system reset mode is set by any of the following causes e Reset by the RESET N pin external reset e Reset by SYSRESETREQ of Cortex MO software reset In the system reset mode the following processing is performed 1 The internal regulator is initialized However it is not initialized by a software reset 2 All the special function registers SFRs whose initial value is not undefined are initialized See Appendix A Registers for the initial values of SFRs However SYSCON REMAP CON SYSCON REMAP BASE are not initialized by a software reset 3 CPU is initialized All the registers in CPU are initialized The program fetches the reset exception vector Note In system reset mode the contents of data memory and those of any SFR whose initial value is undefined are not initialized and are undefined Initialize this area by the software The timing of release of reset di
48. PECLKDIS is a special function register SFR used to stop the clock of each peripheral and can be accessed only by writing 1 Access by writing 0 is invalid When the peripheral clock enable register PECLKEN is accessed by writing 1 the corresponding bit of PECLKDIS is automatically reset to The clock disable state of each peripheral 1 indicates the disable state can be read when reading Description of Bits Symbol Description Related Bit name PECLKEN PERSTEN PERSTDIS CDTMn To stop the operation of Timer n n 0 to 7 CETMn RETMn RDTMn n 0 7 write 1 to this bit n 0 7 n 0 7 n 0 7 CDPWM To stop the operation of PWM write 1 to this CEPWM REPWM RDPWM bit CDHTC To stop the operation of high speed clock time CEHTC REHTC RDHTC base counter write 1 to this bit CDI2CO To stop the operation of I2C bus interface 0 CEI2CO REI2CO RDI2CO write 1 to this bit CDI2C1 To stop the operation of I2C bus interface 1 CEI2C1 REI2C1 RDI2C1 write 1 to this bit CDUART To stop the operation of UART write 1 to this CEUART REUART RDUART bit CDCAL To stop the operation of arithmetic circuit write CECAL RECAL RDCAL 1 to this bit CDHST To stop the operation of host interface write 1 CEHST REHST RDHST to this bit FEUL630Q791 5 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 2 5 Peripheral Reset Ena
49. RDUART To start the operation of UART write 1 to this CEUART CDUART REUART bit 1 RDCAL To start the operation of arithmetic circuit write CECAL CDCAL RECAL 1 to this bit RDHST To start the operation of host interface write 1 CEHST CDHST REHST to this bit To release individual UART stop set CEUART 1 and then execute twice or more to set RDUART 1 FEUL630Q791 5 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 2 7 Port A Mode Setting Register PAMOD Address 0x4000_0260 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 931 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 Symbol name PAgt0 PASO 1 0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RAW RW Intialvalue 0 O0 0 O0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PAG 1 0 gt PA2 1 0 gt E PA1 1 0 gt E PAO 1 0 Access RAN RW R W RAW R W RAN RAN RAN RW RAN RAW RAN RW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing PAMOD is a special function register SFR used to select the primary sec
50. Table 9 1 PWOC Read Enable Disable during PWM Operation Bici men PWOC read enable disable LSCLK 2 048kHz LSCLK Read enabled Read enabled However to prevent the reading of undefined LSCLK 2 048kHz HSCLK data during counting up read consecutively PWOC twice until the last data coincides the previous data HTBCLK LSCLK Read disabled HTBCLK HSCLK Read enabled External clock Read disabled FEUL630Q791 9 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 2 5 PWMO Control Register 0 PWOCONO Address 0x4001_440C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name E E _ E P E E p Access s 2 B E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 db 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name DER M Co 0 is POIS 1 0 POCS 1 0 Access gt 4 RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Description of Register PWOCONO is a special function register SFR to control PWM Description of Bits POCS 1 0 bit 1 0 The POCS 1 0 is used to select the PWMO operation clocks LSCLK HTBCLK 2 048 kHz or the external clock PAO PWMO can be selected by these bits PO
51. The UARTLCR register is used for enabling and clearing the FIFO The trigger level of the receive FIFO is also set with this register For the UARTLCR only write operations can be performed with the program Description of Bits LCRI 0 bit 1 0 and LCRO are used to specify the character length LCRO Description 0 0 5 bit length initial value 0 1 6 bit length 1 0 7 bit length 1 1 8 bit length LCR2 bit 2 LCR2 is used to specify the number of stop bits for the character to be transmitted Description 1 stop bit 1 5 stop bits when character length 5 bits 2 stop bits when character length 6 7 or 8 bits LCR3 bit 3 LCR3 is used to enable disable parity LCR3 Description 0 Disables parity 1 Enables parity FEUL630Q791 13 10 LAPIS FEUL630Q791 ML630Q791 User s Manual Chapter 13 UART Semiconductor Co Ltd LCR4 bit 4 Selects even or odd parity This is enabled when LCR3 1 LCR4 Description 0 Odd parity 1 Even parity LCRS bit 5 Stick Parity bit When parity is enabled LCR 3 1 then parity bit transmission and check will always be logical 1 or 0 When LCR 3 1 AND LCR 5 1 then parity bit transmission and check will be logical 0 if LCR 4 1 If LCR 4 0 then parity bit transmission and check will be logical 1 LCR5 Description 0
52. Twoy of the WDT counter One of 125ms selected WDT 1 0 Description 125ms 500ms 25 initial value 0 0 1 1 0 1 0 1 8s FEUL630Q791 500ms 2s and 8s can be 10 4 LAPIS Semiconductor Co Ltd 10 3 Description of Operation ML630Q791 User s Manual Chapter 10 Watchdog Timer The WDT counter starts incremental counting after the system reset has been released and the low speed clock LSCLK oscillation start The WDT counter can be cleared by writing Ox5A with the internal pointer WDP is 0 then writing 5 with the WDP 1 The WDP is reset to 0 at the system reset or WDT counter overflow and is inverted every writing to WDTCON When the WDT counter cannot be cleared within the WDT counter overflow period Twoy a watchdog timer interrupt WDTINT occurs For the overflow period Twoy of the WDT counter one of 125ms 500ms 25 and 8s be selected by the watchdog timer mode register WDTMOD Clear WDT counter within the clear period of the WDT counter shown in Table 10 1 Table 10 1 Clear Period of WDT Counter FEUL630Q791 WDT 1 0 Twov 0 0 125ms Approximately 121ms 0 1 500ms Approx 496 ms 1 0 2000ms Approx 1996 ms 1 1 8000ms Approx 7996 ms 10 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 10 Watchdog Timer Figure 10 2 shows an example of watchdog t
53. while the system clock is used as a clock for the CPU and memory As the time base counters a low speed time base counter LTBC and a high speed time base counter HTBC are included Low speed time base counter supplies the divided clock by dividing the low speed clock High speed time base counter supplies the divided clock by dividing the high speed clock 6 1 1 Features Low speed clock supplies 32 768 kHz supplied from the external High speed clock supplies a clock generated by the internal FLL Frequency Locked Loop Low speed time base counter generates the divided clock of 2 048 kHz or 256 Hz by dividing the low speed clock High speed time base counter generates the divided clock HTBCLK by dividing the clock of 4 MHz Dividing ratio can be changed 6 2 Configuration Figure 6 1 shows the configuration of the clock circuit 2 048kHz low speed time timer PWM base counter LTBC WDT 32 768kHz H LSCLK HSCLK 32MHz SYSCLK high speed time base counter HTBCLK HTBC Figure 6 1 Configuration of Clock Circuit FEUL630Q791 6 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 6 Clock 6 2 Description of Registers 6 2 1 List of Registers 0 4000 0300 Frequency control register 0 FCONO R W 32 0x0000_0000 0x4000 0304 Frequency control register 1 FCON1 RW 32 0 0000 0002 0x4004 0000 High speed time base counter frequency 32 0 000
54. 0 RSLT2E 7 0 RSLT2D 7 0 RSLT2C 7 0 HIFRLT30W RSLT33 7 0 RSLT32 7 0 RSLT31 7 0 RSLT30 7 0 HIFRLT34W RSLT37 7 0 RSLT36 7 0 RSLT35 7 0 RSLT34 7 0 HIFRLT38W RSLT3B 7 0 RSLT3A 7 0 RSLT39 7 0 RSLT38 7 0 HIFRLT3CW RSLT3F 7 0 RSLT3E 7 0 RSLT3D 7 0 RSLT3C 7 0 11 16 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 13 HSTRG Configuration Register CFG Address 0x00 write 0x80 read Access R W Access size 8 Bits Initial value 0x00 Bit 7 6 5 4 3 2 1 0 Symbol name REGMD INTPW 1 0 INT1EN INTLVL Access RAN R W R W R W R W Initial value 0 0 0 0 0 0 0 0 CFG is a register to set the configuration of the host interface It can be read written from the host processor Description of Bits INTLVL bit 2 This bit controls whether the interrupt signal to the host processor is a level output or pulse output This bit is common to INTO S and INTI S For pulse output the width set in INTPW is used as the pulse width INTLVL Description 0 Pulse output initial value 1 Level output INTIEN bit 3 Controls the S interrupt signal INT1EN Description 0 INT1 S pin is merged with INTO S to be output initial value 1 INT1 S pin is enabled INTPW bit 5 4 This bit indicates the pulse width setting when the interrupt signal is a pulse signal If the pulse width is set to 500 ns or longer an interr
55. 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Description of Register HIFRLTn is a read write special function register SFR that notifies the host processor of the result of command processing If a data is set to this register it is transferred to the register for host access register HSTRG RSLTn which can be read by the host processor Description of Bits RSLTn bit 31 0 n 00 3F Indicates the result of processing to the host processor For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification The following table shows the symbol name for each result register FEUL630Q791 Register Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 HIFRLTOOW RSLTO3 7 0 RSLTO2 7 0 RSLTO1 7 0 RSLTO0 7 0 HIFRLTO4W RSLTO7 7 0 RSLTO6 7 0 RSLTO5 7 0 RSLTO04 7 0 08 RSLTOB 7 0 RSLTOA 7 0 RSLTO9 7 0 RSLTO8 7 0 HIFRLTOCW RSLTOF 7 0 RSLTOE 7 0 RSLTOD 7 0 RSLTOC 7 0 HIFRLT10W RSLT13 7 0 RSLT12 7 0 RSLT11 7 0 RSLT10 7 0 HIFRLT14W RSLT17 7 0 RSLT16 7 0 RSLT15 7 0 RSLT14 7 0 HIFRLT18W RSLT1B 7 0 RSLT1A 7 0 RSLT19 7 0 RSLT18 7 0 HIFRLT1CW RSLT1F 7 0 RSLT1E 7 0 RSLT1D 7 0 RSLT1C 7 0 HIFRLT20W RSLT23 7 0 RSLT22 7 0 RSLT21 7 0 RSLT20 7 0 HIFRLT24W RSLT27 7 0 RSLT26 7 0 RSLT25 7 0 RSLT24 7 0 HIFRLT28W RSLT2B 7 0 RSLT2A 7 0 RSLT29 7 0 RSLT28 7 0 HIFRLT2CW RSLT2F 7
56. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Description of Register PWOD is a special function register SFR used to set the duty of PWMO Note The PWOD data should be smaller than PWOP FEUL630Q791 9 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 2 4 PWMO Counter Register PWOC Address 0 4001 4408 Access R W Access size 32 Bits Initial value 0x0000 0000 Bit 31 22 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name UK i _ j _ i _ _ i _ _ _ _ _ _ _ _ Access 3 5 J 2 z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 1 1 1 5 0 1 1 1 1 1 1 1 Access RAN RAW R W RAW Initial value 0 Note Reserved bit for future expansion 0 0 0 Description of Register PWOC is a special function register SFR that functions as 16 bit binary counter When a write operation is performed to PWOC it is set to 0x0000 The data that is written is meaningless RAN RAV R W RW R W RAN RAN RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 is read when reading The content of PWOC during PWM operation cannot be read depending on the combination of the PWM clock and system clock Table 9 1 shows PWOC read enable disable for each combination of the PWM clock and system clock
57. 0 0 0 0 1 0 aS Initial value after reset FEUL630Q791 iii LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents Table of Contents Chapter 1 NEED IUD M 1 1 IET DIDI M 1 1 1 2 Configuration of Function Blocks ono ente eei e ete iere e e eoe e es 1 3 1 2 1 ME6300791 Block Dias rams iiec ete riti ave et dei etie t de o eden 1 3 1 3 Pin Layout eseon 1 4 153 Pm 1 4 1 31 WE CSP Package nep eet tied e eaa ipee eret ite e eed 1 4 IE udin c 1 5 1 41 Pin Description ise eme RERO TOTO ERR DRIED RIED Ree tt e Ded 1 6 1 4 2 Handling of Unused Pins eremo Dent eth itte tap ten pH ERR 1 8 Chapter 2 2 2 1 2 1 OVerVIEW seeded epe he Hake dig ee aes RH ON a nU 2 1 2412 Beat res ete ERU Oe Ute edet nee ad ERR etes 2 1 2 2 Description of Registers s eter o ERES eee REESE UE ecu See RE e D E SERERE GERE 2 2 2 2 1 Tastof R gistets RUE ERR SERE
58. 0 to 7 interrupt TMnINT is generated on the next timer clock falling edge TMnC is reset to 0x00 and the incremental counting continues When the TnRUN bit is set to 0 TMnC stops incremental counting after counting once the falling of the timer clock TnCK Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 0 7 control register 1 TMnCON1 is 0 When the TnRUN bits are set to 1 again TMnC restart incremental counting from the previous values To initialize TMnC to 0x00 perform write operation in TMnC The timer interrupt period is expressed by the following equation TMnD 1 7 TMI TnCK Hz 0 to 7 TMnD Timer 0 to 7 data register TMnD setting value 0x0000 0001 to 0x0000 OOFF TnCK Clock frequency selected by the Timer O to 7 control register 0 TMnCONO After the TnRUN bit is set to 1 counting starts in synchronization with the timer clock So there may be an error of up to two clocks till the first timer interrupt Subsequent timer interrupt periods are constant Figure 8 2 shows the operation timing diagram of Timer 0 to 7 MELLE ee ee TnSTAT 7 Write TMnC TMnC Xx Y 00 02 Y y 01 Y 8 62 TMnD 88 88 88 88 f f f 0 to 7
59. 0x0000_0068 IRQ 11 0x0000 006C IRQ 12 Timer 2 interrupt 2 0x0000 0070 IRQ 13 Timer 3 interrupt TMSINT 0x0000 0074 IRQ 14 Arithmetic circuit interrupt CALINT 0x0000_0078 IRQ 15 UART interrupt UAINT 0x0000 007C IRQ 16 z 5 0x0000_0080 IRQ 17 0x0000 0084 IRQ 18 Host IF interrupt HSTINT 0 0000 0088 IRQ 19 Port PA5 interrupt 0 0000 008 IRQ 20 bus 1 interrupt I2C1INT 0x0000 0090 IRQ 21 0x0000 0094 IRQ 22 Port PA2 interrupt PA2INT 0x0000 0098 IRQ 23 Port PAS interrupt 0 0000 009 IRQ 24 0x0000 00A0 IRQ 25 0 0000 00A4 IRQ 26 Timer 4 interrupt TM4INT 0x0000_00A8 IRQ 28 Port PA6 interrupt PA6INT 0x0000 00BO IRQ S0 Timer 6 interrupt TM6INT 0x0000_00B8 When multiple interrupts are generated concurrently they are processed starting from the highest priority level and the lower priority interrupts are pending If they have the same priority level the interrupt with a smaller interrupt number has higher priority Please define vector tables for all unused interrupts for fail safe FEUL630Q791 7 4 Chapter 8 Timer LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 Timer 8 1 Overview This LSI includes 8 channels of 8 bit timers For input clocks see Chapter 6 Clock 8 1 1 Features e The timer interrupt TMnINT is generated when the values of timer counter register TMnC n 0 to 7 and timer data register TMnD coincide e
60. 1 value Set the bit 6 of the PIODIR register to 0 to set the input output mode of PA6 to output Register PIODIR register address 0x4000 A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PIODIR 6 0 name Setting 0 value Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol 5 2 Setting value Bit not related to the INTO S function Note The PIOCON register does not need to be set When the secondary function is selected the setting is automatically changed but the value of the PIOCON register does not change FEUL630Q791 11 44 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 5 4 When INT1 S Is Used Set PAI bit 5 and 4 of the PAMOD register to 10 to select the tertiary function of PAI Register PAMOD register address 0x4000 0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 Setting 1 0 value
61. 1 2 2 1 Read receive data from I2CDR ML630Q791 Set master receive mode Check Bus IDLE gt Create start condition Start slave address transmission gt Check arbitration lost Start Condition completion gt Check ACK NACK gt Clear data transfer completion flag Clear interrupt flag Setto send ACK at completion of reception gt Read I2CDR register to start next 1 byte reception First byte after specifying slave device Wait for data transfer completion Clear data transfer completion flag Clear interrupt flag Set to send NACK at completion of reception gt Read I2CDR register to start next 1 byte transmission gt Wait for data transfer completion gt Clear data transfer completion flag Clear interrupt flag gt Create repeated start condition Set master transmit mode gt Read final byte data Create start condition Transmitting slave address Wait for slave address transmission Waiting for receiving next data SCL L Receiving 1 byte Output ACK at completion of reception Waiting for receiving next data SCL L Receiving 1 byte Output ACK at completion of reception Waiting for Repeated Start Condition transmission Waiting for Slave Address transmission SCL L 12 31 LAPIS Semiconductor Co Ltd Set slave address and RW bit for 2 No eM esc T o Y I2CSR I2CMCF
62. 16 3 3 Sector Erase This function erases data in the main area of Flash ROM by sector Erase of the specified sector data is started when you write 0 0000_00 and 0 0000 00 5 to Flash ROM acceptor register FLCACP set the sector address to the Flash ROM address register FLCADR and write 11 to FLE bit of Flash ROM erase register FLCERA The FLCSTA register is 0x0000 0001 during erase When erase is completed the FLCSTA register changes to 0 0000 000 Erase write processing should be executed by a program that is loaded on a memory other than the target Flash ROM It prevents the rewriting program from being lost if it is on Flash ROM due to an unintended operation during erase write processing The CPU enters the waiting state when reading of Flash ROM occurs during erase Write access to the register during erase is prohibited Figure 16 1 shows the processing flow of block erase in the main area Read the selected block or all data of the sector for check after the erase is completed Write 0 0000 00FA to FLCACP Write 0 0000_00 5 to FLCACP Write 0 0000 1000 to FLCADR Write 0 0000 0008 to FLCERA Poll BUSY bit in FLCSTA and wait until it is O Read data from address 0 0000 1000 Compare read data with OxFFFF_FFFF Figure 16 1 Program Flow of Sector Erase When Executed on RAM FEUL630Q791 16 31 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter
63. 16 Flash Programming 16 3 4 1 word Write This function writes data in the main area of Flash ROM in 4 bytes Write to the specified address is started when you write 0x0000 OO0FA and 0x0000 00 5 to Flash ROM acceptor register set the address to the Flash ROM address register FLCADR and write data to Flash ROM write data register FLCWDA During 1 word write the FLCSTA register is 0 0000 0001 When write is completed the FLCSTA register changes to 0 0000 0000 Erase write processing should be executed by a program that is loaded on a memory other than the target Flash ROM The CPU enters the waiting state when reading of Flash ROM occurs during write Write access to the register during write is prohibited Figure 16 2 shows the program flow of 1 word write when executing the code on Flash ROM Check data when the writing is completed Note Data should be written to an erased area on Flash ROM In addition when you want to rewrite data that is written once erase it before writing it again Poll BUSY bit in FLCSTA and wait until it is 0 Read data from address 0 0000 1000 Compare read data with OxFFFF_FFFF Figure 16 2 Flow of 1 word Write When Execute on RAM FEUL630Q791 16 32 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 3 5 Erase Write to Area Where Flash ROM Is Not Implemented It is prohibited to specify an area where Flash ROM is n
64. 16450 compatible mode FCR1 Description 0 Normal operation 1 Clears the receive FIFO Note This bit does not clear the receive shift register FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART e FCR2 IIR2 bit 2 XMIT FIFO reset Clears the transmit FIFO FCR2 Description 0 Normal operation 1 Clears the transmit FIFO Note This bit does not clear the transmit shift register FCR7 6 IIR7 6 bit 7 6 RCVR FIFO Interrupt Trigger Level bit Sets the trigger level of the receive FIFO interrupt as follows FCR7 6 Description 00 1 byte 01 4 bytes 10 8 byte 11 14 bytes FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 2 5 UART Line Control Register UARTLCR Address 0 4008 100C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access gt 5 2 gt 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 23 zi n 2 zd zi J LCR7 LCR6 LCR5 LCR4 LCR3 LCR2 LCR1 LCRO Access z RAN RAN RW RW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Description of Register UARTLCR is a special function register SFR used to control the data character format
65. 2 1 0 Symbolname 2 E E E a NSFL m 4 I2CNS i CLK FLON Access 5 RW 2 RAW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CNF register sets whether or not to use the noise filter for SCL and SDA input Description of Bits I2CNSFLON bit 0 Sets whether or not to use the input noise filter for I2C The initial value is 1 in which case the noise filter is used I2CNSFLON Description 0 Noise filter is not used 1 Noise filter is used NSFLCLK bit 4 Selects a clock used for the input noise filter 1 1 x system clock when system clock 32 MHz functions as a 62 5 ns filter 2 Description 0 1 1 x system clock is used for the noise filter 1 1 2 x system clock is used for the noise filter Table 12 5 Examples of NSFLCLK Setting Values System clock frequency When I2CNSFLCLK 0 When I2CNSFLCLK 1 32MHz 62 5ns 125ns ML630Q791 12 24 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 3 Description of Operation 12 3 1 Flow of Initial Setting This section shows the initial setting flow bit name lt 1 0 represents that software writes 1 0 to this bit The shaded portions show interrupt sources START IPCCTL I2CMEN 1 gt
66. 2 1 0 W MSB LSB MSB LSB MSB LSB R W data Register Write data Write 2 when IFCFG 6 0 0 when IFCFG 6 1 SDO 5 9 Figure 11 8 Write Sequence Four Wire 9 1 5 2 For fSCLK S 1 For SCLK S 2 SCS S For SCLK 6 2 For SCLK S 1 2 0 6 5 4 2 1 7 7 6 5 4 2 1 7 7 6 5 4 2 1 W MSB LSB MSB LSB MSB LSB R W dat Register address Write data Write data Figure 11 9 Write Sequence Three Wire FEUL630Q791 11 34 LAPIS Semiconductor Co Ltd s JIR ML630Q791 User s Manual Chapter 11 Host Interface UUUUUUUU sc s For SCLK S 1 For SCLK S 2 SCS S S For SCLK_S 2 For SCLK S 1 sw s Ut sleli R MSB LSB SB LSB MSB LSB R W data Internal address Read data Read data PSP 0 7 7 e s 4 s 2 1 o Hi Z when IFCFG 6 0 0 when IFCFGI6121 Figure 11 10 Read Sequence Four Wire sax so TIS Juuuuuuu uuuuuuu uU
67. Any combination of timer 0 and timer 1 timer 2 and timer 3 timer 4 and timer 5 or timer 6 and timer 7 can be used as a 16 bit timer e For the timer clock the low speed clock LSCLK high speed time base clock HTBCLK low speed time base clock t2kHz 2 048 kHz or external clock shared with PWM can be selected 8 1 2 Configuration Figure 8 1 shows the configuration of the timers TMnCONO Timer control register 0 TMnCONI Timer control register 1 TMmD TMnD Timer data register TMmC TMnC Timer counter register TMnINT Matched Write TMnC n 0 to 7 Comparator LSCLK gt TMnCONO HTBCLK TMnCON1 8 8 t2kHz gt TnCK PAO PWMO gt gt TMnC TMnD __ Data bus In 8 bit Timer Mode Timers 0 to 7 TMmINT Write TMnC Matched n m 0 1 2 3 4 5 6 7 Write TMmC Comparator 16 LSCLK gt TMnCONO 8 gt TMnCON 1 8 8 t2kHz gt TnCK H PAO PWMO gt gt d TMmC TMnD TMmD Data bus b In 16 bit Timer Mode Timers 0 to 7 Figure 8 1 Timer Configuration FEUL630Q791 8 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 1 3 List of Pins Pinmme VO Description PAO imer external clock input pin Used for the tertiary function of the PAO pin FEUL630Q791 8 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 T
68. BYTE1 enable register FLCSCPB1E 0x0000_0312 0x4000 04AC Set count program BYTE2 enable register FLCSCPB2E 0x0000 0246 0 4000 04B0 0 4000 04B4 0 4000 04BC 0 4000 04B8 Set count program WE disable register FLCSCPWED RW 0x4000 04 0 Set count termination register FLCSCEND 0x0000 0001 FEUL630Q791 16 2 LAPIS Semiconductor Co Ltd 16 2 2 Flash ROM Status Register FLCSTA Address 0 4000 0400 Access R Access size 32 Bits Initial Value 0 0000 0000 ML630Q791 User s Manual Chapter 16 Flash Programming Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name _ _ _ _ _ _ _ _ _ _ _ 1 1 1 1 1 1 1 1 1 Access E E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name _ _ _ _ _ _ _ _ _ _ _ _ _ BUSY Access E z gt S R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future extension 0 is read when reading Description of Register FLCSTA is a read only special function register SFR to indicate a state of the Flash ROM Description of Bits e BUSY bit 0 Indicates a state of the Flash ROM controller This bit is 1 during sector erase 1 word write It automatically changes to 0 when sector erase 1 word write is completed BUSY Description 0 Sector erase 1 word write is completed 1
69. Description of Registers 11 2 1 Register List CPURG for CPU Access Base address 0x4005 0000 Address Name Symbol Symbol Symbol R W Size Initial value Word Half W ord Byte bits 0x00 Configuration register HIFCFG R 32 OxFFFF_2F00 0x04 Reserved 5 0 08 Operation status register HIFST R W 32 0 0000 00 0x0C Interrupt request register HIFRQ R W 32 0x0000_0000 0x10 FIFO register HIFFIFOW HIFFIFO R W 32 8 0x0000_00XX 0x14 FIFO switch register HIFFSEL gt R W 32 0x0000_0000 0x18 FIFO write pointer register HIFWP R W 32 0x0000_0000 0x1C FIFO read pointer register HIFRP R W 32 0x0000_0000 0x20 Parameter register F HIFPRMF R 32 0x0000_0000 0x24 Parameter register B HIFPRMB R 32 0x0000_0000 0x28 Parameter register 7 HIFPRM7 R 32 0x0000_0000 0x2C Parameter register 3 HIFPRM3 R 32 0x0000 0000 0x30 Command register HIFCMD R W 32 0x0000 0000 0x34 Reserved 2 0x3C 0x40 Result register 00 HIFRLTOOW HIFRLTOOH HIFRLTOO R W 32 16 8 0x00 0x41 Result register 01 HIFRLTO1 R W 8 0x00 0x42 Result register 02 HIFRLTO2H HIFRLTO2 R W 16 8 0x00 0x43 Result register 03 HIFRLTOS R W 8 0x00 0x44 Result register 04 HIFRLTO4W HIFRLTO4H HIFRLTO4 R W 32 16 8 0x00 0x45 Result register 05 HIFRLTO5 R W 8 0x00 0x46 Result register 06 HIFRLTO6H HIFRLTOG R
70. Disable Register 8 5 7 5 2 7 Part A Mode Setting Register etie Uie eerie tive be o eoe ML URS EE HEU NE 5 8 9 2 Description of Operation seisena e e p ERREUR UE 5 10 5 941 State Transiti oniani E c e rt tuve iet EUR utet te TUIS EUR URS 5 10 25 242 State of Each Operation Mode o cte E bier d ecole UR 5 11 Chapter 6 6 Clock Abas n grep RU OB E e ete eo Ai eG e DER petite 6 1 6 T oet ERR EROR UE bep a Ree ada eda RE RID 6 1 6 2 6 1 6 12 22 Configuration sensere e hea tA es ee a pete ehe ees 6 1 6 2 D scription of Registers etse metere deeper petunt disp petet etn 6 2 6221 Last of Registers ont S Re areae pet tee een ehe bu 6 2 6 2 2 Frequency Control Register 0 FCONO sess enne enne 6 3 6 2 3 Frequency Control Register 1 FCONI eene nennen trennen rennes 6 4 6 2 4 High Speed Time Base Counter Frequency Divide Register HTBDR eene 6 5 6 3 Description of Operation cse ite eie e hte te ete t tiges ce Inte eese eee cti ce dele ee espe sb eden 6 6 6 3 Js Low Speed Clock i ote Se e e ote tette te d eost IE Roce de rite irte eee ed 6 6 6 32 HigbeSpeed Clock tenes Dee oett niei etie i a eee Adel Pepe be des 6 6 6 3 2 1
71. During sector erase 1 word write FEUL630Q791 16 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 3 Flash ROM Acceptor Register FLCACP Address 0 4000 0404 Access W Access size 32 Bits Initial Value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name i 2 2 E Access gt x y z s s Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name i FAC 7 0 Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note The read data of this register is Reserved bit for future extension Write 0 when writing Description of Register FLCACP is a write only special function register SFR to control enabling disabling sector erase and 1 word write operation for Flash ROM rewrite Description of Bits FAC 7 0 bit 7 0 FAC 7 0 is a register used to restrict sector erase block erase and 1 word write operations in order to prevent an unintended operation Writing of 0x0000 0x0000 O0F5 to FLCACP in this order enables a one time sector erase or 1 word write When you use sector erase or 1 word write in succession you must write 0x0000 00FA 0 0000 00 5 FLCACP every time Eve
72. EE M 4 1 425227 List OE PINS ser e etta et E tret eu de ttes e UE EPE e 4 1 42 DescriptiontoF ReglSters isses te ete ete e etii lor eg dere Ende ptus eee e E edem E Mio dee d e 4 2 4 3 Description of Operation one RU mee ERU c a te toc OU ie uade aaa 4 3 43 1 System Reset Mode s see et AU tote RU teh t tete tae deat ere 4 3 FEUL630Q791 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents Chapter 5 2 MCU Control Funct e ted 5 1 9 1 OVEEVIeW seien vete Pe ete ates 5 1 2211 eed vn 5 1 5 2 Description of Registers oet aco totae ete rete cec PE E reb ite beds 5 2 5 21 List OE Registers secos eee ce mede c ree Re yet Pe ege e ir tee EES deti P 5 2 9 22 Revision Register CIDR terrere eee t ce er eet e ae eese 5 3 5 2 3 Peripheral Clock Enable Register PECLKEN eese nennen nene ren 5 4 5 2 4 Peripheral Clock Disable Register 5 5 5 2 5 Peripheral Reset Enable Register 5 eene nennen 5 6 5 2 6 Peripheral Reset
73. Enables this module 7 gt Sets standard mode or fast mode Set transfer mode for 2 2 Set transfer rate ount value for l2CB gt Set transfer Use buffer CA mode Yes Set slave address for I2CSADR Enable DR_LD interrupt gt Enable DR LD Enable STP interrupt Yes I2CCTL I2CSTPIE 1 Enable MCF interrupt Yes 2 2 lt 1 gt Enable STP gt Enable MCF Enable MAL interrupt Yes gt Enable MAL Enable MAAS interrupt Yes gt Enable MAAS END ML630Q791 12 25 I2CMOD I2CBMEN lt 1 Enable IZCBMDZ interrupt I2CBUFMSK I2CBMDZIE 1 Enable IZCBMAG interrupt I2CBUFMSK I2CBMAGIE lt 1 Enable I2CBMIS interrupt I2CBUFMSK I2CBMISIE lt 1 Enable IZCBMTO interrupt I2CBUFMSK I2CBMTOIE lt 1 Set timeout interval for 2 register Enable 2 interrupt I2CBUFMSK I2CBMNAIE lt 1 Enable 2 interrupt I2CBUFMSK I2CBMALIE lt 1 Enable 2 interrupt I2CBUFMSK I2CBMFIIE lt 1 END ML630Q791 LAPIS Semiconductor Co Ltd gt Enable buffer mode 7 gt Enable I CBMDZ interrupt 7 gt Enable I2CBMAG interrupt 7 gt Enable I2CBMIS interrupt 7 gt Enable ICBMTO interrupt 7 gt Enable 2 interrupt 7 gt Enable I CBMAL interrupt 7 gt Enable 2
74. FSCPCE 15 0 Access RW RAW RW RAN RAN RWW RW RAN RW RAN RW RAN RAN RW RAN RW Initial value 0 0 0 0 0 1 0 0 1 1 1 1 1 0 1 1 Note Reserved bit for future extension 0 is read when reading Description of Register FLCSCPCE is a special function register SFR used to set the initial value of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCPCE 23 0 bit 23 0 FSCSCE 23 0 is a bit used to set the initial value of the erase program counter at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 12 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 12 Set Count Sector Erase WE Enable Register FLCSCSWE Address 0x4000_047C Access R W Access size 32 Bits Initial Value 0x0002_13AA Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name UU FSCSWE 23 16 Access ima CANC a R W R W R W R W R W RW RW R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSCSWE 15 0 Access RW RAW RW RAN RAW RW RW RAN RAN RAN RW RAN RAN RW RAN RW Initial value 0 0 0 1 0 0 1 1 1 0 1 0 1 0 1 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCSWE is a special function register SFR used to s
75. Figure 8 2 Operation Timing Diagram of Timer 0 to 7 Note Even if 0 is written to the TnRUN bits counting operation continues up to the falling edge the timer 0 to 7 status flag TnSTAT is in a 1 state of the next timer clock pulse Therefore the timer 0 to 7 interrupt TMnINT may occur FEUL630Q791 8 12 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 4 Specifying Port Registers To use the timer in the external clock mode the applicable bit of each related port register needs to be set See Chapter 15 GPIO for details about the port registers 8 4 1 Operating Timer with External Clock PWM Set bit 1 and 0 of the PAMOD register to 10 to select the tertiary function of Register PAMOD register address 0x4000 0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 Setting value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting value Set the bit 0 of the PIODIR register to 1 to set the input output mode of PAO to input Register PIODIR register address 0x4000 A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PIODIR 6 0 name Se
76. LAPIS Semiconductor Co Ltd 12 3 3 Flow of Master Reception START Il2CCTL l2CMTX 0 I2CSR I2CMBB o o Yes Set slave address and R W bit for I2CDR es S I2CCTL I2CMSTA lt 1 N No No Y 2 5 2 1 No Ye I2CSR I2CMCF 0 l2CSR I2CMIF lt 0 I2CCTL I2CTXAK 0 Read receive data from I2CDR No I2CSR I2CMCF 0 H MIF lt 0 Final byte 1 i received No Yes I2CCTL I2CTXAK lt 1 Read receive data from I2CDR Yes I2CSR I2CMCF 0 l2CSR I2CMIF 0 I2CCTL I2ZCMSTA 0 Read receive data from I2CDR ML630Q791 gt gt Set master receive mode Check Bus IDLE Create start condition Start slave address transmission Check arbitration lost Start Condition Wait for slave address transmission completion Check ACK NACK Clear data transfer completion flag Clear interrupt flag Set to send ACK at completion of reception Read I2CDR register to start next 1 byte reception First byte after specifying slave device Wait for data transfer completion Clear data transfer completion flag Clear interrupt flag Set to send NACK at completion of reception Read I2CDR register to start next 1 byte transmission Wait for data transfer completion Clear data transfer completion flag Clear interrupt flaa Issue stop condition Read final byte data ML630Q791 User s Manual Chapter 12 I2C Bus Interface Crea
77. LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix D Application Circuit Example ML630Q791 Host processor SDA S SCL S PAG INTO S Figure D 2 Example of Connection with the Host Processor Using I2C e SPI Slave Interface To use an SPI interface set the IFSEL bit of HIFCFG register to 0 ML630Q791 Host processor SDI Figure D 3 Example of Connection with the Host Processor Using SPI FEUL630Q791 D 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix D Application Circuit Example eSensor Interface ML630Q791 has 2 channels of I2C master interface for sensor control The following shows a 0 connection example lt ML630Q791 Proximity sensor Temperature humidity sensor Air pressure sensor Terrestrial magnetism sensor e cEIPE _ UV sensor Figure D 4 Example of Connection with Sensor IC Using I2C FEUL630Q791 D 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix D Application Circuit Example eDebug Interface ML630Q791 has SW DP as the debug interface For details of SW DP see Cortex MO Technical Reference Manual and other references FEUL630Q791 D 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix D Application Circuit Example eFirmware Update With ML630Q791 remapping to the dedicated boot loader program is required to update the firmware The remap
78. List of Registers Address Name Symbol Size Initial value bits 0 4000 0200 Revisionregister 0x0630_7900 0x4000 0220 Peripheral clock enable register PECLKEN 0x8000 0000 Port A mode setting register FEUL630Q791 5 2 LAPIS Semiconductor Co Ltd 5 2 2 Revision Register IDR Address 0 4000 0200 Access R Access size 32 Bits Initial value 0 0630 7900 ML630Q791 User s Manual Chapter 5 MCU Control Function Symbol name Symbol name Description of Bits Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID 11 0 PRV 3 0 Access R R R R R R R R R R R R R R R R Initial value 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 Description of Register IDR holds the 28 bit product ID and 4 bit revision PRV 3 0 bit 3 0 Represent the revision of this LSI PID 27 0 bit 31 4 PIDO to 27 represent the product ID of ML630Q791 It is necessary to refer to the Internal Flash ROM to identify ML630Q791 See Chapter 3 Memory for details 5 3 FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 2 3 Peripheral Clock Enable Register PECLKEN Address 0x4000_0220 Access R W Access size 32 Bits Initial value 0x8000_0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNE ue age
79. PWM TM7 TM6 TM5 4 2 1 TMO Access RAN RW RAW R W R W R W RAN RAN RW RAN RAW RAN R W RAW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing PERSTDIS is a special function register SFR used to release the reset of each peripheral and can be accessed only by writing 1 Access by writing 0 is invalid Set the peripheral clock enable register PECLKEN before setting PERSTDIS to supply a clock to the block When the peripheral reset enable register PERSTEN is accessed by writing 1 the corresponding bit of PERSTDIS is automatically reset to 0 The reset released state of each peripheral 1 indicates the released state can be read when reading Description of Bits Symbol Description Related Bit name PECLKEN PECLKDIS PERSTEN RDTMn To start the operation of Timer n n O to 7 CETMn CDTMn RETMn 0 7 write 1 to this bit 0 7 0 7 0 7 RDPWM To start the operation of PWM write 1 to this CEPWM CDPWM REPWM bit RDHTC To start the operation of high speed clock time CEHTC CDHTC REHTC base counter write 1 to this bit RDI2CO To start the operation of I2C bus interface 0 CEI2CO CDI2CO REI2CO write 1 to this bit RDI2C1 To start the operation of I2C bus interface 1 CEI2C1 CDI2C1 REI2C1 write 1 to this bit
80. Program WE Enable Register 5 16 14 16 2 14 Set Count Program 2 1st Enable Register 16 15 16 2 15 Set Count Program 2 Ist Disable Register 2 16 16 16 2 16 Set Count Program PROG2 2nd Enable Register FLCSCPP22E eese nennen 16 17 16 2 17 Set Count Program PROG2 2nd Disable Register 22 2 16 18 16 2 18 Set Count Program PROG2 3rd Enable Register 23 16 19 FEUL630Q791 vi LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents 16 2 19 Set Count Program PROG2 3rd Disable Register 23 16 20 16 2 20 Set Count Program PROG2 4th Enable Register 2 16 21 16 2 21 Set Count Program PROG2 4th Disable Register FLCSCPP24AD sese 16 22 16 2 22 Set Count Program BYTEI Enable Register FLCSCPBIE eeeseseseeeeereneneenee 16 23 16 2 23 Set Count Program BYTE2 Enable Register 2 nennen nnnm nee 16 24 16 2 24 Set Count Program BYTE3 Enable Register nennen nennen 16 25 16 2 25 Set Count Erase WE Disable Register enne nns 16 26 16 2 26 Set Count Program WE Disable Register 16 27 1
81. Register IBCNFO 1 tette 12 24 12 3 Description of Operation nnt Dep ne DO UE RUP BORED pO 12 25 12 3 1 Flow of Initial Setting Dp dst va cased Oe Die DE 12 25 12 3 2 Flow of Master Transmission sseni 12 27 12 3 3 Flow of Master Reception eon e eere npe ite m ie peret esie ep te iere eret e an 12 28 FEUL630Q791 iv LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents 12 3 4 Flow of Compound Mode Receiving by Master after Transmitting from Master esses 12 29 12 3 5 Flow of Compound Mode Transmitting from Master after Receiving by 2 2 2222 12 31 12 3 6 Flow When Using Buffer Mode 24040 22 20000000000000 12 33 12 3 7 Flow of Mode EIE REA 12 35 12 3 7 1 Flow of Switching to Normal Mode sess 12 35 12 3 7 2 Flow of Switching to Buffer Mode essere en rennen tnnt trennen trennen eene 12 35 12 4 Wayetorman Each Mode eee ote Pre RP PIER OC ME ra E reir ee 12 36 12 4 1 Waveform Transmitted by Master eee nennen renim emet nee etene tenete entren trennen nee 12 36 12 4 2 Waveform Received by Master 2 22220 0 1 000000000000000000 terne tenete trennen trennen 12 36 12 4 3 Waveform of Compound Format Master Transmission Master Reception 12 36 12 4
82. Remarks Remapping E Boot Internal Flash ROM Start address 0x1000 0000 Internal Flash ROM Start address 0x1001 000 Remapping x remapped xd Work RAM The device placed at the address Internal Flash ROM set by the remapping base address responds bl casu DRM above x Don t care the data 3 5 Access Response for Memory Space An access made to a bank that has been set as not allocated returns an error response For specifications of the space in a bank exceeding the allocated memory size see Section 3 3 Operation at error response f an error response is returned for access from CPU a hard fault exception is generated FEUL630Q791 3 8 Chapter 4 Reset Functions LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 4 Reset Functions 4 Reset Functions 4 1 Overview This LSI has the two reset functions shown below If either of them is generated this LSI enters the system reset mode e Reset by the RESET N pin external reset e Reset by SYSRESETREQ of 0 software reset 4 1 1 Features The RESET N pin has an internal pull up resistor 4 1 2 Configuration Figure 4 1 shows the configuration of the reset generation circuit Vpp RESET d D SYSRESETREQ 2 Data bus Figure 4 1 Configuration of Reset Generation Circuit 4 1 3 Listof Pins RESET N Reset input pin FEUL630Q791 4 1
83. Reserved bit for future extension is read when reading Description of Register FLCSCPBS3E is a special function register SFR used to set the value to start enabling bit 3 of byte signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCSCPB3E 23 0 bit 23 0 For FSCSCPB3E 23 0 bit 3 of the byte signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM In addition the other bits of the byte signal are disabled For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 25 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 25 Set Count Erase WE Disable Register FLCSCEWED Address 0x4000_04B4 Access R W Access size 32 Bits Initial Value 0x0000 06AA Bit 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 Symbol name 5005004 0 0 3 FSCEWED 23 16 Access ROR RW RW RW RW RW RW Initalvaue 0 0 0 0 0 0 0 O0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 2 FSCEWED ISO 2 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCEWED is a special function register SFR used to set the value to start disabling the write s
84. W 16 8 0x00 0x47 Result register 07 HIFRLTO7 R W 8 0x00 0x48 Result register 08 HIFRLTO8W HIFRLTO8H HIFRLTO8 R W 32 16 8 0x00 0x49 Result register 09 HIFRLTO9 R W 8 0x00 4 Result register 0A HIFRLTOAH HIFRLTOA R W 16 8 0x00 0x4B Result register 0B HIFRLTOB R W 8 0x00 0x4C Result register 0C HIFRLTOCW HIFRLTOCH HIFRLTOC R W 32 16 8 0x00 0x4D Result register OD HIFRLTOD R W 8 0x00 Ox4E Result register OE HIFRLTOEH HIFRLTOE R W 16 8 0x00 Ox4F Result register OF HIFRLTOF R W 8 0x00 0x50 Result register 10 HIFRLT10W HIFRLT10H HIFRLT10 R W 32 16 8 0x00 0x51 Result register 11 HIFRLT11 R W 8 0x00 0x52 Result register 12 HIFRLT12H HIFRLT12 R W 16 8 0x00 0x53 Result register 13 HIFRLT13 R W 8 0x00 0x54 Result register 14 HIFRLT14W HIFRLT14H HIFRLT14 R W 32 16 8 0x00 0x55 Result register 15 HIFRLT15 R W 8 0x00 0x56 Result register 16 HIFRLT16H HIFRLT16 R W 16 8 0x00 0x57 Result register 17 HIFRLT17 R W 8 0x00 0x58 Result register 18 HIFRLT18W HIFRLT18H HIFRLT18 R W 32 16 8 0x00 0x59 Result register 19 HIFRLT19 R W 8 0x00 0x5A Result register 1A HIFRLT1AH HIFRLT1A R W 16 8 0x00 0x5B Result register 1B HIFRLT1B R W 8 0x00 0x5C Result register 1C HIFRLT1CW HIFRLT1CH HIFRLT1C R W 32 16 8 0x00 0x5D Result register 1D HIFRLT1D R W 8 0x00 0x5E Result register 1E HIFRLT1EH HIFRLT1E R W 16 8 0x00 Ox5F Result register 1F HIFRLT1F R W 8 0x00 0x60 Result register 20 HIFRLT20W
85. above are published by ARM Limited Please ensure that you refer to the latest versions ARM Cortex Thmub are registered trademarks of ARM Limited in the EU and other countries ARMCORTEX Processor Technology FEUL630Q791 ii LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Notation Classification Notation Description Numeric value Oxnn Oxnnnn nnnn Indicates a hexadecimal number Obnn Obnnnn nnnn Indicates a binary number Unit word W 1 word 16 bits byte B 1 byte 8 bits nibble N 1 nibble 4 bits maga M 10 kilo K 2 1024 kilo k 10 1000 milli m 10 micro 10 nano n 10 second s lower case second Terminology level 1 level Indicates high voltage signal levels Vy and Voy as specified by the electrical characteristics L level 0 level Indicates low voltage signal levels and Vo as specified by the electrical characteristics Register description R W Indicates that Read Write attribute R indicates that data can be read and W indicates that data can be written R W indicates that data can be read or written Invalid bit This bit reads 0 when read Write to this bit is ignored Register name MSB LSB 1 LFLL ENOSC SYSCLK R W R R W R W Initial value 1 0
86. depending on the conditions of the timer clock and the system clock Table 8 1 shows whether a TMmC read is enabled or disabled during timer operation for each condition of the timer clock and system clock Table 8 2 TMmC Read Enable Disable during Timer Operation Wi 2 TMmC read enable disable LSCLK Read enabled LSCLK Read enabled However to prevent the reading of undefined HSCLK data during incremental counting read TMmC twice and check that the results match LSCLK Read disabled HSCLK Read enabled Read enabled However to prevent the reading of undefined LSCLK data during incremental counting read TMmC twice and check kHz that the results match Read enabled However to prevent the reading of undefined HSCLK data during incremental counting read TMmC twice and check that the results match LSCLK External clock HSCLK Read disabled FEUL630Q791 8 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 2 6 Timer n Control Register 0 TMnCONO n 0 2 4 6 Address 0 4000 1408 TMOCONO 0x4000 1808 TM2CONO 0x4000 1C08 TM4CONO 0x4000 2008 TM6CONO Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name id x Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name
87. end Clear interrupt flag of transfer data count 0 Clear interrupt flag of transfer data mismatch ML630Q791 User s Manual Chapter 12 I2C Bus Interface Clear I2CBUFCTL I2CBMSTA automatically Clear I2CBUFCTL IZCBMSTA automatically Abnormal Bus end Clear I2CBUFCTL Il2CBMSTA automatically Abnormal Bus end Clear I2CBUFCTL IZCBMSTA automatically Send stop condition To Bus IDLE Clear I2CBUFCTL IZCBMSTA automatically Other master device communicating Clear I2CBUFCTL IZCBMSTA automatically LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 3 7 Flow of Mode Switching 12 3 7 1 Flow of Switching to Normal Mode Disable buffer mode l2CMOD l2CBMEN 0 1 1 I 3 Follow initial setting flow 12 3 7 2 Flow of Switching to Buffer Mode START l 1 1 99 Enable buffer mode I 1 1 7 gt Follow initial setting flow Note Be sure to switch modes before starting I2C transfer ML630Q791 12 35 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 4 Waveform in Each Mode In the figures below the hatched portions are the segments that are driven by the transfer destination 12 4 1 Waveform Transmitted by Master SDA A7 6 07 X K DO SCL MCF interrupt MCF interrupt CD Awaiting MCF interrupt
88. gt gt Q 0 0 O Stop SDA XX a A1 X R W X ACK SA7 X D7 X SCL FPP PARAL PRY 2 7 D Q9 Waiting for transfer completion transfer eror I2CBUFSLV Write 2 0 Check 2 0 Write I2CBUFSUB Write I2CBMSTA 1 Write I2CBUFLEV 0 Write I2CDR Write I2CBUFFOR 0x11 Write 12 4 7 Waveform 3 When Using Buffer Mode When data length of sub address 4 data transmission number of transferred bytes 1 Sub address transmission Sub address transmission Slave address transmission 1 byte BMSUB3 BMSUBO Data transmission 1 byte lt gt o 0 Q 0 O 2 SDA X ATY R WX ACK SA7 SA7 D7 Y ACK SCL 22 I2CBMFI interrupt D Waiting for transmission completion transfer err I2CBUFSLV Write 2 0 Check I2CBUFSUB Write 2 5 1 Write I2CBMFI 0 Write I2CBUFLEV 0 Write I2CDR Write I2CBUFFOR 0x14 Write ML630Q791 12 37 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 4 8 Waveform 4 When Using Buffer Mode When data length of sub address 0 data reception number of transferred bytes 1 Slave address transmission 1 byte Data reception 1 byte gt oto I SDA 1 I2CBMFI T Waiting for transfer comp
89. interrupt source due to the HSTRG INTREQ1 REG n bit initial value n 0 to 7 For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 19 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 16 HSTRG Operation Status Register STATUS Address 0x89 read Access R Access size 8 Bits Initial Value Bit 7 6 5 4 3 2 1 0 Symbol name ST 7 ST 6 ST 5 ST 4 ST 3 ST 2 STH ST 0 Access R R R R R R R R Initial value 1 1 1 1 1 1 1 0 STATUS is a register which indicates the measurement status It can be read from the host processor Write to this bit is ignored Description of Bits e ST 7 0 bit 7 0 Indicates the measurement status For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 20 LAPIS Semiconductor Co Ltd 11 2 17 HSTRG Error Code Register 0 ERRORO Address 0x8A read Access R Access size 8 Bits Initial value 0x00 ML630Q791 User s Manual Chapter 11 Host Interface Bit 7 6 5 4 3 2 1 0 Symbol name ERO 7 ERO 6 ERO 5 ERO 4 ERO 3 ERO 2 ERO 1 ERO 0 Access R R R R R R R R Initial value 0 0 0 0 0 0 0 0 is a read only register that shows the error code Writing is invalid Description of Bits ERO0 7 0 bit 7 0 Represents an error code For details see ML630Q791 User s Gui
90. low speed clock about 15 26 us Internal pointer 1 to 0 When the WDT counter overflows again after the WDTINT the host interface is notified of the abnormal state Note n the sleep mode the watchdog timer operation does not stop If WDT interrupt occurs during the sleep mode the sleep mode is released The watchdog timer cannot detect all the abnormal operations Even if the CPU loses control the watchdog timer cannot detect the abnormality in the operation state in which the WDT counter is cleared FEUL630Q791 10 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 10 Watchdog Timer 10 4 Example of Processing When Not Using Watchdog Timer The WDT counter is a free running counter that starts incremental counting unconditionally when the system reset is released and the low speed clock LSCLK is output Since the WDT counter overflow causes a non maskable interrupt the clearance process of WDT counter needs to be performed even when the WDT function is not used as fail safe Figure 10 3 shows an example of program that clears the WDT counter by the WDT interrupt routine disable irq do WDT gt WDTCON 0x5a while WDT gt WDTCON amp 0x1 1 WDT gt WDTCON 0xa5 enable irq Figure 10 3 Example of Program Description FEUL630Q791 10 7 Chapter 11 Host Interface LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 Host Interface 11 1 Overview
91. monitor register 1 I2CMON1 R 32 0x0000 0003 0x4008 3414 2 bus transfer rate setup counter 1 I2CBC1 R W 32 0x0000_0000 0x4008 3418 mode register 1 I2CMOD1 R W 32 0x0000 0000 0x4008 341C buffer mode slave address register 1 I2CBUFSLV1 R W 32 0x0000_0000 ch1 0 4008 3420 buffer mode sub address register 1 I2CBUFSUB1 R W 32 0x0000 0000 0x4008 3424 buffer mode format register 1 I2CBUFFOR1 R W 32 0x0000_0000 0x4008 3428 lC buffer mode control register 1 I2CBUFCTL1 R W 32 0x0000_0000 0x4008 342C buffer mode interrupt mask register 1 I2CBUFMSK1 R W 32 0x0000 0000 0x4008 3430 buffer mode status register 1 I2CBUFSTA1 R W 32 0x0000 0000 0x4008 3434 buffer mode level register 1 I2CBUFLEV1 R W 32 0x0000 0000 0x4008 3448 timer register 1 I2CTMR1 R W 32 0x0000_0000 0x4008 3450 input noise filter setting register 1 I2CNF1 R W 32 0x0000_0001 ML630Q791 12 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 2 Control Register I2CCTLO 1 Address 0 4008 3004 Och 0 4008 3404 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CDR I2CST 2CCF 2CALII2CME I2CAA 2CMSTI2CMT I2CTX Il2CRS Symbol name JI2CCS PIE I
92. oed e eee e es 13 23 13 4 Specify A Port Reglstets eei ee eo ten te o ee eden 13 24 1321 1 Operatng he eet i e te 13 24 Chapter 14 14 Aritbinetic Circuit iHe ede e hund ae 14 1 1 Ase ean UU RR ee OH UH ae tata RO eR Ue ERRARE 14 1 14 Vals Features ssi eo Rn en Sete 14 1 1421 2 Configuration eee epe ee Hee e PR e eR Rede 14 1 14 2 Description of Registers eene Reden Mee reb aene e PER eret EEE EEE S E EEE 14 2 1421 List BEI CIO 14 2 14 2 2 Operation Status Register CALSTS sess eene rennen 14 3 14 2 3 Operation Input Register AL 14 4 FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents 14 2 4 Operation Input Register AH 44022220400 0 00000 nete tene trennen trente eterne enne ene 14 5 14 2 5 Operation Input Register 22422 01 1 01 000000000000000 14 6 14 2 6 Operation Input Register BH CALBH esee nennen eene enne 14 7 14 2 7 Calculation Result Register OL CALROL 14 8 14 2 8 Calculation Result Register OH 14 9
93. os s 5 1 23 16 Access ROR RW RW RW RW RW RN Intialvalue 0 0 0 0 0 0 0 0 0 Bit 1514 1 12 1 9 8 7 5 4 3 2 4 0 Symbol name FSCSCPB1E 15 0 Access RW RAN RW RW RW RW RW RA RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCPBIE is a special function register SFR used to set the value to start enabling bit 1 of byte signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCSCPBIE 23 0 bit 23 0 For FSCSCPBIE 23 0 bit 1 of the byte signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM In addition the other bits of the byte signal are disabled For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 23 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 23 Set Count Program 2 Enable Register FLCSCPB2E Address 0 4000 04AC Access R W Access size 32 Bits Initial Value 0 0000 0246 Bit 931 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbolname 2 23 16 Access RW RW RW RW RW RN Intialvalue 0 0 0 0 O 0 0 O0 Bit 1514 1 12 1 9 8 7 6 5 4 8 2 4 0 Symbol
94. pin PA2 RXDO IX for the secondary function UART data output pin PAS TXDO EG for the secondary function FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual 13 2 Description of Registers 13 2 1 List of Registers bits 0 4008 1000 UART receive data register UARTRBR R 32 UART transmit data register UARTTHR W UART baud rate dividing register LSB UARTDLL R W 0x4008_1004 UART interrupt enable register UARTIER R W 32 UART baud rate dividing register MSB UARTDLM B 0x4008 1008 UART interrupt status register UARTIIR UART FIFO control register UARTFCR 0x4008 100C UART line control register UARTLCR 0x4008 1014 UART line status register UARTLSR R 32 0x4008 101C UART scratchpad register UARTSCR Note access to addresses 0 4008 1010 and 0 4008 1018 is prohibited Proper operation cannot be guaranteed if accessed FEUL630Q791 Chapter 13 UART Initial value Undefined Undefined 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0001 0x0000 0000 0x0000 0000 0x0000 0060 0x0000 0000 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 2 2 UART Receive Data Register UART Transmit Data Register UART Baud Rate Dividing Register LSB UARTRBR UARTTHR UARTDLL Address 0 4008 1000 Access R W Access size 32 Bits Initial value Undefined Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name 2 2 Access 2
95. register PIODIR described later Set the value to be output to the port pin The value of this register is output to the external pin when the value of the port direction register indicates output Description of Bits PIODAT 6 0 bits 6 0 PIODAT 6 0 is used to set the output value of the Port A pin in output mode and to read the pin level of the Port A pin in input mode PIODAT n Description 0 Output or input level of the PAn pin L 1 Output or input level of the PAn pin H 0 6 FEUL630Q791 15 3 LAPIS Semiconductor Co Ltd 15 2 3 GPIO Port Direction Register PIODIR Address 0 4000 A004 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access Initial value Bit Symbol name Access Initial value Note ML630Q791 User s Manual Chapter 15 GPIO Description of Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 st i m zi 5 PIODIR 6 0 gt 2 5 RW RAW RW RAW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved bit for future expansion 0 is read when reading Description of Register PIODIR is a special function register SFR to select the input output mode of Port A PIODIR 6 0 bits 6 0 PIODIR 6 0 is used to set the input output mode of the Port A pin PIODIR n Description 0 PAn pin Output initial
96. s Manual Chapter 14 Arithmetic Circuit 14 2 Description of Registers 14 2 1 List of Registers Address Name Symbol R W Size bits Initial value Ox4004 5018 Calculation result register OL CALROL 32 0000 0x4004 501 Calculation result registerOH_ CALROH 32 oxoooo 0000 0 4004 5020 Calculation result register iL CALRIL R 32 0x0000 0000 Ox4004 5024 Calculation result register H CALRIH R 32 00000000 FEUL630Q791 14 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 14 Arithmetic Circuit 14 2 2 Operation Status Register CALSTS Address 0 4004 5000 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQST _ DIV E Symbol name S N RW R W Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALSTS is a register for the start control and the status confirmation of the operation circuit Writing 1 to the CALSTS causes the corresponding calculation to begin The status is maintained as 1 during the calculation and cleared to At the same time an interrupt is issued Stopping a current calculation and starting a next calculation during an operation is prohibited If it is wri
97. selected by the high speed time base counter frequency divide register HTBDR is generated as HTBCLK HTBCLK is used as the operation clock of timer and PWM Figure 6 2 shows the output waveform of HTBCLK 4MHz clock 1 n counter output HTBCLK 1 1 1 2 T dividing dividing Tis dividing High speed time base counter frequency divide register OxOF OxOE i 0x0D HTBDR Figure 6 2 Output Waveform of HTBCLK FEUL630Q791 6 6 Chapter 7 Interrupt LAPIS Semiconductor Co Ltd ML630Q791 User s Manual 7 7 1 7 1 Chapter 7 Interrupt Interrupt Overview This LSI has 22 interrupt sources External interrupts 7 sources Internal interrupts 15 sources and a software interrupt SVC For details of the interrupt function see the section about NVIC of Cortex MO Devices Generic User Guide For details of each interrupt see the following chapters Chapter 8 Timer Chapter 9 PWM Chapter 10 Watchdog Timer Chapter 11 Host Interface Chapter 12 Bus Interface Chapter 13 UART Chapter 14 Arithmetic Circuit Chapter 15 GPIO Features Non maskable interrupt source 1 Internal sources 1 Maskable interrupt sources 21 Internal sources 14 External sources 7 Software interrupt SVC Four interrupt priority levels sup
98. set to 1 when a NACK is received and transfer is terminated in address transmission in the transmit mode or receive mode This bit is cleared by writing 0 by software The interrupt by this bit is notified with the same timing as the I2CMCF interrupt when a NACK is received I2CNSTP Description 0 Has not received a NACK 1 Received a NACK and terminated transfer Note This bit is used as a spare function It is not used in the operation sequence 2 bit 15 This bit is set to 1 if a STOP condition has occurred at unexpected timing and the transfer has ended abnormally This bit is set to 1 under any of the following conditions When a STOP condition is detected before the master itself sends a STOP condition while the master is transmitting or receiving This bit is cleared by writing 0 by software I2CISTP Description 0 Has not detected an unexpected STOP condition 1 Detected an unexpected STOP condition Note This bit is used as a spare function It is not used in the operation sequence ML630Q791 12 9 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 4 Data Register I2CDRO 1 Address 0 4008 300C Och 0 4008 340C 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access gt s 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 1
99. the address increment mode successive read and data in the 4 byte boundary 11 4 5 Timing of Clearing Interrupt Request Register Timing of clearing the interrupt request register depends on the INTIEN bit setting of the configuration register HSTRG CFG as described below e When INTIEN 0 INTO S is the logical ORed output of REQO and REQI REQO and 1 are both cleared when REQO is read At this time REQ is saved to the buffer for next transmission If only REQI is read from the host REQI is not cleared Be sure to read REQO and 1 successively e When INTIEN 1 REQO is cleared when REQO is read and REQI is cleared when REQI is read FEUL630Q791 11 39 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 4 6 Error Handling Should an error occurs while processing a command or during any other operation the CPU sets an error code to the CPURG operation status registers ERO and ERI The host processor can read the error code that has been set from the HSTRG error code registers 0x8A and Ox8B Depending on the contents of the error that has been set the host processor needs to handle the situation For the details of error codes see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 40 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 4 7 Error Status Notification If the WDTP of WDT is not cleared and WDT overflow occurs an int
100. x value Set the bits 0 and 1 of the PIODIR register to 0 to set the input output mode of to output Register PIODIR register address 0x4000 A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PIODIR name Setting x x x 10101 value Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol E gt Setting x x x x x x x value Bit not related to the I2C1 function Note The PIOCON register does not need to be set When the secondary function is selected the setting is automatically changed but the value of the PIOCON register does not change ML630Q791 12 41 Chapter 13 UART LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 UART 13 1 Overview This LSI includes a UART with 16 byte transmit and receive FIFOs This UART functions as the input output interface carries out serial to parallel conversion of the data sent from the peripheral devices and also converts the parallel data sent from the CPU into serial data In the FIFO mode it is possible to store 16 bytes of data during transmission and reception
101. 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 E NE X al A Note Set this bit in the initial setting flow or before the master transfer start Operation cannot be guaranteed if the value of this bit is changed during transfer ML630Q791 12 14 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 9 Buffer Mode Sub Address Register I2CBUFSUBO 1 Address 0 4008 3020 Och 0 4008 3420 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name I2CBMSUB3 7 0 I2CBMSUB2 7 0 Access RAN RAW R W R W RW RAN RAN RAW R W RW R W RAN RAN RAW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 144 13 12 11 10 9 7 6 5 4 3 2 1 0 Symbol name I2CBMSUBI 7 0 I2CBMSUBO 7 0 Access RAN RAW R W R W RW RW RAN RAW RAW R W R W RAN RAN R W RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register I2CBUFSUB register sets the sub address sent to the transfer destination device This register is enabled only when the buffer mode is used Description of Bits I2CBMSUBO bit 7 0 This register sets the sub address sent to the transfer destination device 2CBMSUBI bit 15 8 This register sets the sub address 1 sent to the transfer destination device I2CB
102. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSEL L L L L 1 1 1 1 1 1 1 1 1 1 Access R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Description of Register FIFO switch register HIFFSEL is a special function register SFR used to switch whether host processor or CPU can access 512 byte FIFO Description of Bits e FSEL bit 0 FSEL Description 0 Only CPU can access FIFO initial value 1 Only host processor can access FIFO FEUL630Q791 11 11 LAPIS Semiconductor Co Ltd 11 2 8 CPURG FIFO Write Pointer Register HIFWP Address 0 4005 0018 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 ML630Q791 User s Manual Chapter 11 Host Interface 21 20 19 18 17 16 Symbol name i Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name E D AT US FIFOWP B 0 Access RAN RAN RAN R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Descriptio
103. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALRO 15 0 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALROL is a special function register SFR that stores the result data of the operation CALROL register indicates the lower 32 bits of the quotient for division or the decimal part 23 bits and the lower 8 bits of the integer part in the operation result for root operation For details see 14 3 Description of Operation FEUL630Q791 14 8 LAPIS Semiconductor Co Ltd 14 2 8 Calculation Result Register OH CALROH Address 0 4004 501C Access R Access size 32 Bits Initial value 0 0000 0000 ML630Q791 User s Manual Chapter 14 Arithmetic Circuit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name CALRO 63 48 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALRO 47 32 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALROH is a special function register SFR that stores the result data of the operation CALROH register indicates the higher 32 bits of the quotient for division or the upper 16 bits of the integer part in the operation result for root operation For details see 14 3 Description of Operation FEUL630Q791 14 9 LAPIS Semiconductor Co Ltd 14 2 9 C
104. 0 0000 divide register FEUL630Q791 6 2 ML630Q791 User s Manual LAPIS Semiconductor Co Ltd Chapter 6 Clock 6 2 2 Frequency Control Register 0 FCONO Address 0x4000_0300 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 Symbol name CLKDIV 3 0 RAN RAV RW RW Access 0 0 0 0 0 0 0 0 0 Initial value 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing FCONO is a special function register SFR used to control the high speed clock generation circuit Description of Bits CLKDIV 3 0 bit 3 0 This bit selects the frequency of high speed clock CLKDIV 3 0 Description 0 32 MHz CLK output initial value Other than Setting prohibited above 6 3 FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 6 Clock 6 2 3 Frequency Control Register 1 FCON1 Address 0 4000 0304 Access R W Access size 32 Bits Initial value 0x0000 0002 Bit Symbol name E 2 2 Access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
105. 0 TM5D 0x4000 2010 TM7D Access R W Access size 32 Bits Initial value 0 0000 00FF ML630Q791 User s Manual Chapter 8 Timer Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name ar ane eer a TmD 7 0 Access R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 1 1 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing 1 1 1 1 1 1 TMmD is a special function register SFR to set the value to be compared with the timer m counter register TMmC value The value set to TnD 15 8 n 0 2 4 6 is reflected in the 16 bit timer mode Note Set TMmD when the timer m stops When TmSTAT of TMmCONI register is 0 Writing 0x0000 0000 to TMmD works in the same way as 0 0000 0001 FEUL630Q791 8 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 2 4 Timer n Counter Register TMnC n 0 2 4 6 Address 0 4000 1404 TMOC 0x4000 1804 TM2C 0x4000 1C04 0x4000 2004 TM6C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T T T T T T T T T T T T T Symbol name
106. 0000 0000 0x4005 004C Result register 0 HIFRLTOCW R W 32 16 8 0x0000 0000 0x4005 0050 Result register 10 HIFRLT10W R W 32 16 8 0x0000 0000 0x4005 0054 Result register 14 HIFRLT14W R W 32 16 8 0x0000 0000 0x4005 0058 Result register 18 HIFRLT18W R W 32 16 8 0x0000 0000 0x4005 005C Result register 1C HIFRLT1CW R W 32 16 8 0 0000 0000 0x4005 0060 Result register 20 HIFRLT20W R W 32 16 8 0x0000 0000 0x4005 0064 Result register 24 HIFRLT24W R W 32 16 8 0x0000 0000 0x4005 0068 Result register 28 HIFRLT28W R W 32 16 8 0x0000 0000 0x4005 006C Result register 2C HIFRLT2CW R W 32 16 8 0x0000 0000 0x4005 0070 Result register 30 HIFRLT30W R W 32 16 8 0x0000 0000 0x4005 0074 Result register 34 HIFRLT34W R W 32 16 8 0x0000 0000 0x4005 0078 Result register 38 HIFRLT38W R W 32 16 8 0x0000 0000 0x4005 007C Result register 3C HIFRLT3CW R W 32 16 8 0x0000 0000 UART receive data register UARTRBR R Undefined 0x4008_ 1000 UART transmit data register UARTTHR W 32 Undefined UART baud rate dividing register LSB UARTDLL R W 0x0000_0000 UART interrupt enable register UARTIER R W 0x0000_0000 0x4008 1004 pw 32 UART baud rate dividing register MSB UARTDLM R W 0x0000_0000 UART interrupt status register UARTIIR R 0x0000_0001 0x4008_ 1008 32 UART FIFO control register UARTFCR W 0x0000 0000 0 4008 100C UART line control register UARTLCR R W 32 0x0000_0000 0x4008_ 1014 UART line status register UARTLSR R 32
107. 000_2014 Timer 7 counter register TM7C R W 32 0x0000_0000 0x4000_ 2018 Timer 7 control register 0 TM7CONO R W 32 0x0000_0000 0x4000_201C Timer 7 control register 1 TM7CON1 R W 32 0x0000_0000 0 4000 000 GPIO data register PIODAT R W 32 0x0000_0000 0x4000 A004 GPIO direction register PIODIR R W 32 0x0000_0000 0x4000 008 GPIO port control register PIOCON R W 32 0x0000_0000 0x4000 A010 GPIO interrupt enable register PIOIE R W 32 0x0000_0000 0x4000 A014 GPIO interrupt mode register PIOIM R W 32 0x0000_0000 0x4000_A018 GPIO interrupt status register PIOIS R W 32 0x0000_0000 0x4001_ 0400 Watchdog timer control register WDTCON R W 32 0x0000_0000 0x4001_ 0404 Watchdog timer mode register WDTMOD R W 32 0x0000_0002 0 4001_4400 PWMO cycle register PWOP R W 32 0x0000_FFFF 0x4001_ 4404 PWMO duty register PWOD R W 32 0x0000_0000 0x4001_4408 PWMO counter register PWOC R W 32 0x0000_0000 0x4001 440C PWMO control register 0 PWOCONO R W 32 0x0000_0000 0x4001_ 4410 PWMO control register 1 PWOCON 1 R W 32 0x0000_0040 0x4004 0000 High speed time base counter frequency divide HTBDR R W 32 0x0000_0000 register 0x4004_5000 Operation status register CALSTS R W 32 0x0000_0000 0x4004 5008 Operation input register AL CALAL R W 32 0x0000_0000 0x4004 500C Operation input register AH CALAH R W 32 0x0000_0000 0x4004_5010 Operation input register BL CALBL R W 32 0x0000_0000 0x4004_5014 Operation input register BH CALBH R W 32 0x0000_0000 0x4004_5018 Calculation re
108. 008 1008 Access R W Access size 32 Bits Initial value 0 0000 0001 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 25 zi 2 zd zi i IIR7 IIR6 i zh IIR2 IRO Access RAN R W RAN R W R W RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Note Reserved bit for future expansion 0 is read when reading Description of Register UARTIIR is a special function register SFR that provides the following two functions This register will access other registers for read write operations Therefore read modify write is prohibited 1 Interrupt Identification Register IIR Read only register for interrupt information The UARTIIR register stores information indicating that an interrupt with a certain priority level is pending along with the type of that interrupt UARTIIR indicates the interrupt with the highest priority level that is pending other interrupts will not be recognized until the CPU clears the interrupt For the UARTIIR register only read operations can be performed with the program Description of Bits IIRO bit 0 Indicates whether an interrupt was generated IIRO Description 0 Interrupt was generated 1 Interrupt was not generated FEUL630Q791 13 7 LAPIS Semiconductor Co Ltd 2
109. 008 3414 bus transfer rate setup counter 1 I2CBC1 0x0000 0000 0x4008 3418 2 mode register 1 I2CMOD1 0x0000 0000 0x4008 341C buffer mode slave address register 1 I2CBUFSLV1 0x0000 0000 0x4008 3420 2 buffer mode sub address register 1 I2CBUFSUB1 0x0000 0000 0x4008 3424 2 buffer mode format register 1 I2CBUFFOR1 0x0000_0000 0x4008 3428 2 buffer mode control register 1 I2CBUFCTL1 0x0000 0000 0x4008 342C C buffer mode interrupt mask register 1 I2ZCBUFMSK1 0x0000 0000 0x4008 3430 buffer mode status register 1 I2ZCBUFSTA1 0x0000 0000 0x4008 3434 I C buffer mode level register 1 I2CBUFLEV1 0x0000 0000 0x4008 3448 timer register 1 I2CTMR1 0x0000 0000 0x4008 3450 input noise filter setting register 1 I2CNF1 0x0000 0001 0 000 E100 Interrupt set enable register NVIC_ISER 0x0000_0000 0 000 180 Interrupt clear enable register NVIC_ICER 0x0000_0000 0 000 200 Interrupt set pending register NVIC_ISPR 0x0000_0000 OxE000_E280 Interrupt clear pending register NVIC_ICPR 0x0000_0000 0 000 400 Interrupt priority register 0 NVIC_IPRO 0x0000_0000 0 000 E404 Interrupt priority register 1 NVIC IPR1 0x0000 0000 0 000 E408 Interrupt priority register 2 NVIC IPR2 0x0000 0000 OxE000_E40C Interrupt priority register NVIC_IPR3 0x0000_0000 OxE000_E410 Interrupt priority register 4 NVIC_IPR4 0x0000_0000 OxE000_E414 Interrupt priority register 5 NVIC_IPR5 0x0000_0000 OxE000_E418 Interrupt priority register 6 NV
110. 0x0000_0060 0x4008_101C UART scratchpad register UARTSCR R W 32 0x0000_0000 0x4008_ 3004 2 control register 0 I2CCTLO R W 32 0x0000_0000 0x4008_ 3008 C status register 0 I2CSRO R W 32 0x0000_0000 0x4008 300C data register 0 I2CDRO R W 32 0x0000_0000 0x4008 3010 2 bus monitor register 0 I2CMONO R 32 0x0000 0003 0x4008 3014 bus transfer rate setup counter 0 2 0 R W 32 0x0000_0000 0x4008 3018 I C mode register 0 I2CMODO R W 32 0x0000_0000 FEUL630Q791 A 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix A Registers Address Name Symbol R W Size Initial value bits 0x4008 301C 2 buffer mode slave address register 0 I2CBUFSLVO 0x0000 0000 0x4008 3020 buffer mode sub address register 0 I2CBUFSUBO 0x0000 0000 0x4008 3024 2 buffer mode format register 0 I2ZCBUFFORO 0x0000 0000 0x4008 3028 buffer mode control register 0 I2CBUFCTLO 0x0000 0000 0x4008 302C C buffer mode interrupt mask register 0 I2CBUFMSKO 0x0000 0000 0x4008 3030 buffer mode status register 0 I2CBUFSTAO 0x0000 0000 0x4008 3034 I C buffer mode level register 0 I2CBUFLEVO 0x0000 0000 0x4008 3048 timer register 0 I2CTMRO 0x0000 0000 0 4008 3050 input noise filter setting register 0 I2CNFO 0x0000 0001 0x4008 3404 control register 1 I2CCTL1 0x0000 0000 0x4008 3408 lC status register 1 I2CSR1 0x0000 0000 0x4008 340C I C data register 1 I2CDR1 0x0000 0000 0x4008 3410 2 bus monitor register 1 I2CMON1 0x0000 0003 0x4
111. 0x4000 1C18 TM5CONO 0 4000 2018 TM7CONO Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T T T T T T T T T T T T T Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 2 5 2 5 gt TmCS 1 0 Access RAN R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing TMmCONO is a special function register SFR used to control the Timer m Rewrite TMmCONO while the timer m is stopped TmSTAT of TMmCONI register is 0 Description of Bits TmCS 1 0 bits 1 0 TmCS 1 0 is used for selecting the operation clock of the timer m LSCLK HTBCLK t2kHz or the external clock can be selected by these bits When the 16 bit timer mode is selected the value of this bit 1s invalid TmCS 1 0 Description 0 0 LSCLK initial value 0 1 HTBCLK 1 0 t2kHz 2 048kHz 1 1 External clock PAO TIMER FEUL630Q791 8 9 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 2 8 Timer n Control Register 1 TMnCON1 n 0 2 4 6 Address 0x4000 140C TMOCON1 0x4000 180C TM2CON1 0x4000 1COC TM4CON1 0x4000 200C TM6CON 1 Access R W Access size 32 Bits
112. 1 0 Symbol name PIOIM3 3 0 PIOIM2 3 0 PIOIM1 3 0 PIOIMO 3 0 Access RW RW RAN RW RW RW RW RAW RW RAW RAN RAW RAW RW RAW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register Sets the interrupt mode for each GPIO pin Description of Bits PIOIMn 2 0 Sets the interrupt mode for the PAn n 0 6 pin An interrupt occurs under the following conditions according to the PIOIMn setting n 0 6 Value of Interrupt mode PIOIMn 2 0 000 An interrupt occurs at a falling edge 001 An interrupt occurs at a rising edge 010 An interrupt occurs with a L level input 011 An interrupt occurs with a H level input 100 An interrupt occurs at both edges rising falling Other than above Setting prohibited PIOIMn 3 Sets whether the PAn n 0 6 pin interrupt is detected with or without sampling Value of Description PIOIMn S 0 Detects without sampling initial value 1 Detects with sampling The detection with sampling performs two cycles of sampling at 16 kHz FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 2 7 GPIO Interrupt Status Register PIOIS Address 0 4000 A018 Access R W Access size 32 Bits Initial value 0x0000 0000 Bit 31 30 290 28 27 26 25 24 23 22 21 20
113. 11 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 3 CPURG Configuration Register HIFCFG Address 0 4005 0000 Access R W Access size 32 Bits Initial value OXFFFF 2F00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name MSK1 7 0 MSKO 7 0 Access R R R R R R R R R R R R R R R R Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IF REG E x INT1 INT x A Symbol name IFCFG 7 1 SELI mp 7 INTPW 1 0 en ivi Access RAN RAN R W R W RW RW RW RW R R R R R Initial value 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Description of Register Configuration register HIFCFG is a special function register SFR used to indicate the configuration that was set to the register for host access HSTRG CFG by the host processor and to set the serial interface Description of Bits e INTLVL bit 2 This bit indicates whether the interrupt signal to the host processor is a level output or pulse output INTLVL Description 0 Pulse output initial value 1 Level output This bit is common to INTO S and INTI S For pulse output the time set in INTPW 1 0 is used as the pulse width INTIEN bit 3 This bit indicates whether the second interrupt signal to the host processor is allowed
114. 12 2 List of Registers Channel Address Name Symbol R W E Initial value 0x4008 3004 control register 0 I2CCTLO R W 32 0x0000 0000 0x4008 3008 2 status register 0 I2CSRO R W 32 0x0000_0000 0x4008 300C data register 0 I2CDRO R W 32 0x0000 0000 0x4008 3010 bus monitor register 0 I2CMONO R 32 0x0000 0003 0x4008 3014 lC bus transfer rate setup counter 0 I2CBCO R W 32 0x0000_0000 0 4008 3018 mode register 0 I2CMODO R W 32 0x0000 0000 0x4008 301C buffer mode slave address register 0 I2CBUFSLVO R W 32 0x0000_0000 cho 0x4008 3020 buffer mode sub address register 0 I2CBUFSUBO R W 32 0x0000 0000 0x4008 3024 buffer mode format register 0 I2CBUFFORO R W 32 0x0000 0000 0x4008 3028 buffer mode control register 0 I2CBUFCTLO R W 32 0x0000_0000 0x4008 302C buffer mode interrupt mask register 0 I2CBUFMSKO R W 32 0x0000_0000 0x4008 3030 2 buffer mode status register 0 I2CBUFSTAO R W 32 0x0000 0000 0x4008 3034 buffer mode level register 0 I2CBUFLEVO R W 32 0x0000_0000 0x4008 3048 timer register 0 I2CTMRO R W 32 0x0000_0000 0x4008 3050 input noise filter setting register 0 I2CNFO R W 32 0x0000_0001 0x4008 3404 control register 1 I2CCTL1 R W 32 0x0000_0000 0x4008_3408 status register 1 I2CSR1 R W 32 0x0000_0000 0x4008 340C lC data register 1 I2CDR1 R W 32 0x0000 0000 0x4008 3410 l C bus
115. 16 bits of the remainder in the division result for division For details see 14 3 Description of Operation 14 11 FEUL630Q791 LAPIS Semiconductor Co Ltd 14 3 Description of Operation 14 3 1 Division The formats of the input and result of the division are shown below ML630Q791 User s Manual Chapter 14 Arithmetic Circuit Input result Dividend Divisor Quotient Remainder part decimal part Division CALA 63 0 CALB 47 0 CALRO 63 0 CALR1 47 0 Writing 1 to the DIV_EN of CALSTS causes the calculation to begin The quotient in the calculation result of CALA 63 0 CALB 47 0 is stored in CALRO 63 0 and the remainder is stored in CALR1 47 0 When the operation completes the set bit is cleared to and an interrupts is issued Setting the divisor to 0 is prohibited Even if it is set to 0 an interrupt occurs after 48 cycles 14 3 2 Root Operation The formats of the input and result of the root operation are shown below Input result Integer part decimal part Integer part Integer part Decimal part Root operation CALA 47 0 CALRO 47 24 CALRO 23 1 Writing 1 to the SQSTS of CALSTS causes the root calculation to begin The integer part in the calculation result of the square root of CALA 47 0 is stored in CALRO 47 24 and the decimal part is stored in CALRO 23 1 When the operation completes the SQSTS is cleared to 0 and an inte
116. 19 18 17 16 Symbol name _ _ _ _ _ _ _ _ _ _ 1 1 1 1 1 1 1 1 1 z s z E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name PIOIS 6 0 Access RW RW RAW RW RAW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register Holds the interrupt status Only writing 1 is valid By writing 1 to the bit which caused an interrupt the interrupt is cleared Description of Bits PIOIS 6 0 bits 6 0 PIOIS n Description 0 No PAn pin interrupt source exists 1 A PAn pin interrupt source exists n 0 6 Note If 1 is written to a bit with value 0 the bit value is not changed FEUL630Q791 15 8 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 3 Description of Operation 15 3 1 I O Setting For each pin of Port A either output or input is selected by setting the GPIO direction register PIODIR In output mode high impedance output mode P channel open drain output mode N channel open drain output mode or CMOS output mode can be selected by setting the GPIO control registers PACON In the input mode set the GPIO control registers PACON to select any of h
117. 2 12 2 2 IC Control Register ISCCTLO 1 sette 12 3 12 2 3 FC Status Register DCSRU D sei ting beide erben 12 6 12 2 4 Data Register I2CDRO 1 sedens pr teni 12 10 12 2 5 Bus Monitor Register I2CMONO 1 ees olet eee e lee te e e He 12 11 12 2 6 Bus Transfer Rate Setup Counter I2CBQCO T 12 12 12 2 7 PC Mode Register I2CMODO 1 ent utu 12 13 12 2 8 Buffer Mode Slave Address Register I2CBURBSL VO T iere tiere ete ng 12 14 12 2 9 Buffer Mode Sub Address Register 2 5 1 ete ie tee re p RU dese neg 12 15 12 2 10 PC Buffer Mode Format Reeister I2CBUFFOR O31 eec 12 16 12 2 11 PC Buffer Mode Control Register I2CBU FCTLEO 1 12 17 12 2 12 C Buffer Mode Interrupt Mask Register 2 5 1 ccsscssesssessessessssssesssesseesusssessscssecsecsuesseesseesecaes 12 18 12 2 13 PC Buffer Mode Status Register IBCB ESTAQ 12 20 12 2 14 2 Buffer Mode Level Register IDDCBUFLEVO 1 tette tette tette tette tta tret totos 12 22 12215 C Timer Resister ICE MR D a ce abet ete abet olus te latus 12 23 12 2 16 2 Input Noise Filter Setting
118. 2 13 2 Description of Registers nie eee Pea een OO IBe eme 13 3 19 22 List of Registers OR hh AI REDI RR Eee 13 3 13 2 2 UART Receive Data Register UART Transmit Data Register UART Baud Rate Dividing Register LSB UARTRBR UARTTEHR UARTDEL terreri E a a hee e ATARE E VERAT 13 4 13 2 3 UART Interrupt Enable Register UART Baud Rate Dividing Register MSB UARTIER UARTDLM 13 5 13 2 4 UART Interrupt Status Register UART FIFO Control Register UARTIIR 13 7 13 2 5 Line Control Register nennen nennen enne netter tenete trennen een 13 10 13 2 6 UART Line Status Register 5 13 12 13 2 7 UART Scratchpad Register 13 15 13 32 Description of Operation 2 e ettet ie ete rite Actes ete eire UE CHE ee RE n neta dukes 13 16 13 3 1 Dat Trans MISON neant Eee e teri ete eoi posee 13 16 13 3 2 Data Reception soe ee e uie oet temet eae ORE bei 13 17 13 3 3 Baud Rate Clock iei npe e UH PIE HEP EFE HERI HI eer 13 19 13 34 FFO Mode eo erede 13 20 13 5 5 FIBRO Polled Mode 5 oed ee ede e et d ofi tuse 13 21 13 3 6 E E no Stats 4 eh eb ei on ede eee ee en ee eee 13 22 13 3 7 Setting Exanple
119. 2 0 030 2400 0301 0 030 4800 0181 0 100 9600 00 0 0 160 19200 0060 0 160 38400 0030 0 160 57600 0020 0 160 115200 0010 0 160 FEUL630Q791 13 19 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 4 FIFO Mode When the receive FIFO and reception interrupt are both enabled reception interrupts are generated as follows A If the number of characters present within the FIFO exceeds the programmed trigger level a Received Data Available interrupt is generated This interrupt is immediately cleared when the number of characters present within the FIFO drops below the trigger level B As with the Received Data Available interrupt the Received Data Available flag of the UARTIIR register will be set if the number of characters present within the FIFO exceeds the trigger level and cleared when the number of characters drops below the trigger level C The Receiver Line Status interrupt has a higher priority level than the Received Data Available interrupt D The Received Data Available flag is set as soon as the data in the receive shift register is transferred to the FIFO and cleared when the FIFO becomes empty When the receive FIFO and reception interrupt are both enabled Character Timeout interrupts are generated as follows A The Character Timeout interrupt is generated when the following conditions are met e There is at least one character present in the FIFO e amount of time requir
120. 2C connection example When the interrupt signals INTO S S are not used up to four IO ports can be used for other uses ML630Q791 Host processor SCL S SCLK S 5 sws sosL SD S LI SCL M Figure 11 2 I2C Connection Example 11 3 1 1 2 Slave Address The slave address of I2C can be set by IFCFG 7 1 of CPURG configuration register as shown in Figure 11 3 The initial value is Ox17 address for write Ox2E address for read Ox2F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 und Loc ese I Teram FO Figure 11 3 I2C Slave Address Format FEUL630Q791 11 30 ML630Q791 User s Manual Chapter 11 Host Interface LAPIS Semiconductor Co Ltd 2 Transfer Format 11 3 1 2 data is possible as shown in Figure 11 4 When writing from the master to slave sequential writing in the order of internal address internal write data internal write R W 0 write Internal write data Address 0 0 Slave address 05001 01 Internal write data Internal write data Address OxOE Internal write data Address OxOD Address 0 0 S Start condition Input direction P Stop condition L1 Output direction A Acknowledge Figure 11 4 Register Write Transfer Format 11 31 FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface When reading the slave data from the
121. 3 12 11 10 9 8 7 6 5 4 3 2 1 0 XN Symbol name Access RAN R W R W RW R W RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register sets transmit data or stores received data In the buffer mode up to 32 bytes of transmit data can be stored in the buffer by writing this register When receiving data the received data stored in the buffer can be read by reading this register ML630Q791 12 10 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 5 Bus Monitor Register I2CMONO 1 Address 0 4008 3010 Och 0 4008 3410 1ch Access R Access size 32 Bits Initial value 0x0000 0003 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit is dccus Ud dd Sr ce Uc wc che 04 v9 2022240 1 Symbol name DBMON3 DBMON2 DBMON1 A Access R R R AR R AR R R R R R Initial value 0 0 0 0 O0 0 O0 14 1 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register indicates the level of SDA and SCL of the bus Description of Bits I2CSCL bit 0 Mo
122. 3 2 1 0 Symbol name FSCAC 7 0 Access W W W W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future extension Write 0 when writing Description of Register FLCSCACP is a special function register SFR used to control disables enables write to the set count registers other than FLCSCACP Description of Bits e FSCAC 7 0 bit 7 0 FSCACO7 to FSCACOO are registers used to restrict write to set count registers FLCSCACP has state of permitted requested or prohibited State Description Permitted It is possible to write to Flash ROM set count registers Request It is impossible to write to Flash ROM set count registers Prohibited It is impossible to write to Flash ROM set count registers The default is the state of prohibited The conditions of transition to these states are as follows State Condition of transition Permitted Write 0x0000 OOFC data in the requested state Request Write 0x0000 00 data in the prohibited state Prohibi Write any data in the permitted state rohibited Write data other than 0 0000 00FC in the requested data FEUL630Q791 16 10 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 10 Set Count Sector Erase CE Enable Register FLCSCSCE Address 0x4000 046C Access R W Access size 32 Bits Initi
123. 32 bit 16 KB SRAM 4K x 32 bit Interrupt controller Non maskable interrupt 1 source A Maskable interrupt 21 sources Number of internal sources 14 Timer 8 PWM 1 I2C 2 HOSTIF 1 Arithmetic circuit 1 UART 1 Number of external sources 7 e Timer 8 bit x 8 ch also available is 16 bit configuration using Timers 0 and 1 Timers 2 and 3 Timers 4 and 5 or Timers 6 and 7 x 4 ch Watchdog timer WDT x Ich 16 bit PWM x Ich e Serial interface DC interface with master function x 2ch including 8 bit 32 stage FIFO UART interface x Ich two wire full duplex buffer system including 8 bit 16 stage FIFO e Hostinterface Serial interface with slave function SPI I2C selectable x Ich host processor interrupt 512 Byte FIFO RAM for communication e General purpose I O port T bit input output port x Ich External interrupt input available Arithmetic circuit Root operation Division operation e Flash rewrite function Hardware remap supported ISP supported FEUL630Q791 1 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 1 Overview e Operation mode and power consumption control function operation mode Operation with a high speed and low speed clock are supported Sleep mode The sleep mode which stops CPU only is supported Sleep deep mode The sleep deep mode which stops CPU and peripheral blocks is sup
124. 4 Waveform of Compound Format Master Reception Master Transmission 12 36 12 4 5 Waveform 1 When Using Buffer Mode eene nennen en 12 37 12 4 6 Waveform 2 When Using Buffer Mode sess 12 37 12 4 7 Waveform 3 When Using Buffer Mode sess een eene ennt tenerent entren nre 12 37 12 4 8 Waveform 4 When Using Buffer 12 38 12 4 9 Waveform 5 When Using Buffer Mode essere eene 12 38 12 4 10 Waveform 6 When Using Buffer 2 2 004044 0 000 12 38 12 4 11 Waveform 7 When Using Buffer Mode eese 12 39 12 4 12 Waveform 8 When Using Buffer 12 39 125 8 T M 12 40 12 6 Specitymg Poft i e i b ede iih eu de deu en eder eror ee 12 41 12 61 Operating C I do eee teal e ties iate dp dede 12 41 Chapter 13 UAR RSEN Ead A 13 1 13 1 OVervie Wi diei 13 1 13 1D Features e E AE ERROR ORIS O teo aedi RE D EP ROREM 13 1 13 12 Configuration Sete e ETE o RR RR d ad o Hte 13 2 13 1 3 List of Piscine ete REUS OHIO e Ud Gee EUIS MES 13
125. 4 0 us condition SCLn M L level time 4 7 us SCLn M H level time tHIGH 4 0 us SCLn_M setup time restart condition tsu stA B NE 7 B i SDAn M hold time tHp DAT 0 us SDAn M setup time tsu DAT 0 25 us SDAn M setup time P Stop condition lsusro 0 zu Bus free time tBUF 4 7 us Characteristics I2C Master Interface Fast Mode 400 kHz 1 7 to 1 9V GND OV Ta 40 to 85 Standard value Parameter Symbol Condition Unit Min Typ Max SCLn M clock frequency fscL 400 kHz SCLn_M hold time start restart tHD STA 0 6 us condition SCLn_M L level time mE 1 3 us SCLn M H level time tHIGH 0 6 us SCLn M setup time restart condition tsusTa 0 8 SDAn M hold time tHD DAT 0 us SDAn M setup time tsu DAT 0 1 us SDAn_M setup time P Stop condition lsusro 0 8 E Bus free time tBuF 1 3 us Start Restart Stop condition condition condition SDAn M j SCLn M lt gt lt gt lt gt MEE EE b kiso pur lup sTA low tHiGH isu sTA 5 tsu pat 0 1 FEUL630Q791 C 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix C Electrical Characteristics Characteristics Firmware update VDD BRMP
126. 5 AN 7 HTBC x x AN 5 x 12 0 AN 5 x I2C1 x x AN 5 x UART x x AN 5 x Arithmetic circuit x x A 5 A 5 Host interface A 5 A 5 WDT Other blocks 1 FLL is restarted 2 FLL is not restarted the lock state is maintained but the system clock is switched to the low speed clock 3 The internal regulator is restarted by an external reset 4 The internal regulator is not restarted by a software reset 5 It follows the PECLKEN PECLKDIS PERSTEN and PERSTDIS register settings made during the program run mode 6 It follows the PECLKEN PECLKDIS PERSTEN and PERSTDIS register settings made during the program run mode It stops when HTBCLK is selected for the timer clock 7 It follows the PECLKEN PECLKDIS PERSTEN and PERSTDIS register settings made during the program run mode It stops when HTBCLK is selected for the PWM clock FEUL630Q791 5 11 Chapter 6 Clock LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 6 Clock 6 Clock 6 1 Overview The clock of this LSI is supplied from the clock generation circuit and the time base counter Clock generation circuit generates the low speed clock LSCLK high speed clock HSCLK and system clock SYSCLK based on the external clock input and supplies them The low speed clock and high speed clock are used as clocks for the peripheral circuit and the time base counter
127. 6 2 27 Set Count CE Disable Register FLCSCCED eese esee enne en nnne en nnne enne 16 28 16 2 28 Set Count Termination Register 16 29 16 33 Re UR Pe deti oec anre e ae RE EU SEn 16 30 16 3 1 Erase Wnte Flash ROM caer bee i e deest temet aree te aa tease eto deren 16 30 16 3 2 Counter Seting ooh esses eoe o UR ETT eS EC UE It Ue de pede PEU EE dei e iC tribe upto dee tet den 16 30 16 3 3 5 Erase cM M 16 31 16 3 4 1 word Wie iet tU Np PE CR i HE UR Ee dee rb 16 32 16 3 5 Erase Write to Area Where Flash ROM Is Not 16 33 16 3 6 Notesan Use ict ROUES bero uotis 16 33 Chapter 17 17 On Chip Debug Functiion anro tete pee tee er Pere ep RE peii ra bereit retine 17 1 17 1 OVERVIEW eoi ed EO Pa ED RAE pa RPG 17 1 Chapter 18 18 Power Supply Circum aeo Senn ipa qun e EO ROB IE ERES 18 1 OVervie Weite Een iu pet dune RERO n meal petu ies NR 18 1 18221 Features ms 18 1 18 1 2 Configuration eene aute red cede teres be nei biet c 18 1 I8 1 3 Listof PIS fe tei e adus 18 1 Appendixes E
128. 8 0x00 OxE1 Result register 21 RSLT21 R 8 0x00 OxE2 Result register 22 RSLT22 R 8 0x00 Result register 23 RSLT23 R 8 0x00 OxE4 Result register 24 RSLT24 R 8 0x00 OxE5 Result register 25 RSLT25 R 8 0x00 OxE6 Result register 26 RSLT26 R 8 0x00 OxE7 Result register 27 RSLT27 R 8 0x00 OxE8 Result register 28 RSLT28 R 8 0x00 OxE9 Result register 29 RSLT29 R 8 0x00 OxEA Result register 2A RSLT2A R 8 0x00 OxEB Result register 2B RSLT2B R 8 0x00 OxEC Result register 2C RSLT2C R 8 0x00 OxED Result register 2D RSLT2D R 8 0x00 OxEE Result register 2E RSLT2E R 8 0x00 OxEF Result register 2F RSLT2F R 8 0x00 OxFO Result register 30 RSLT30 R 8 0x00 OxF1 Result register 31 RSLT31 R 8 0x00 OxF2 Result register 32 RSLT32 R 8 0x00 OxF3 Result register 33 RSLT33 R 8 0x00 OxF4 Result register 34 RSLT34 R 8 0x00 OxF5 Result register 35 RSLT35 R 8 0x00 OxF6 Result register 36 RSLT36 R 8 0x00 OxF7 Result register 37 RSLT37 R 8 0x00 OxF8 Result register 38 RSLT38 R 8 0x00 OxF9 Result register 39 RSLT39 R 8 0x00 OxFA Result register 3A RSLT3A R 8 0x00 OxFB Result register 3B RSLT3B R 8 0x00 OxFC Result register 3C RSLT3C R 8 0x00 OxFD Result register 3D RSLT3D R 8 0x00 OxFE Result register 3E RSLTSE R 8 0x00 OxFF Result register 3F RSLTSF R 8 0x00 Accessing any of reserved areas is prohibited Operation cannot be guaranteed if you access a reserved area FEUL630Q791
129. 9 7 6 5 4 3 2 1 0 Symbol name 0 I2CBMDL 5 0 I2CBMSL 2 0 Access RW RW RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CBUFFOR register sets the communication format in the buffer mode Set the data length of the sent sub address the data transfer direction and the byte count of the transferred data This register is enabled only when the buffer mode is used Description of Bits I2CBMSL bit 2 0 Sets the data length of the transferred sub address in the buffer mode 000 to 100 can be set When it is set to 000 the sub address is not sent When it is set to a value between 001 and 100 the sub address set for IACBUFSUB register is sent When this bit is set to more than 101 it will be set to 000 I2CBMRW bit 3 Sets the data transfer direction in the buffer mode 1 and 0 indicate data reception and data transmission respectively I2CBMDL bit 9 4 This register sets the transferred byte count in the buffer mode 0 to 32 bytes 00000 to 100000 can be set When this bit is set to more than 100001 it will be set to 000000 When starting transfer with this bit set to 000000 I2CBMDZ will be set to 1 and transfer will not be started Note Set this bit in the initi
130. 9 11 4 5 Timing of Clearing Interrupt Request 11 39 11 4 6 Error Handling e eee cer ss e re tet ipee P e tete Hee pu desee 11 40 1147 Error Status NotifiCatiofi reiecit tete eret rece ce iei tee pe cente ee een 11 41 11 48 Clock Requirements eio deett er ete aate nen eee e e EP Pea tee iei cet 11 41 11 5 Specifymg Port Registers PPP IRURE LEBER DERE ORUM RO DEED 11 42 11 51 When Using SPI Interface Three wire eee eere torte re ter rane steel e doeet rr re ore oh 11 42 11 5 2 When Using SPI Interface Four wire 5 eere etr hecho PH E HERE Lee eR e Fe eere P ne Poen Eh 11 43 11 5 3 When INTO Sts Used TG ditiones 11 44 15 42 When INTI S Is Used nage neun elitm anime opuiei 11 45 Chapter 12 17 XE CBusd ferfice osea uU so LE LM E 12 1 12 1 OVERVIEW te ce eet 12 1 12 13 Beat res eun RERO ees eese m EN INE ae oat 12 1 1222 Configuration cese edm ono oe edic te ble haste eie 12 1 12 1 3 bete metet eie E E QR 12 1 12 2 Description of Reglsters iter RII be eere dee eee eee ee rei S A 12 2 12 2 1 Eistot RE GISTETS er RI RU EN eee 12
131. Address 0x4000 04A0 Access R W Access size 32 Bits Initial Value 0 0000 00AF ML630Q791 User s Manual Chapter 16 Flash Programming Bit 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbolname 24 23 16 Access ROR RW RW RW RW RW RN Initialvalue 0 0 0 0 0 0 0 O0 0 Bit 15 144 13 12 1 30 9 7 6 5 4 3 2 14 0 Symbol name FSCPP24D 15 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 Note 0 0 0 0 0 1 Reserved bit for future extension is read when reading Description of Register 0 1 0 1 1 1 1 FLCSCPP24D is a special function register SFR used to set the value to start disabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCPP24DJ23 0 bit 23 0 For FSCPP24D 23 0 the write signal to Flash ROM is disabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 22 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 22 Set Count Program BYTE1 Enable Register FLCSCPB1E Address 0x4000_04A8 Access R W Access size 32 Bits Initial Value 0 0000 0312 Bit 91 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbolname 900 0000
132. Bits e 2CBMFI bit 0 It is set to 1 when this I2C module finishes the transfer in the buffer mode This bit is cleared by writing 0 by software I2CBMFI Description 0 Transfer in the buffer mode is not completed 1 Transfer in the buffer mode is completed e 2CBMNA bit 2 It is set to 1 when it receives a and the transfer is finished This bit is cleared by writing 0 by software 2 Description 0 Has not received a NACK 1 Received a NACK and terminated transfer I2CBMTO bit 3 It is set to 1 when a timeout occurs before the end of the transfer and the transfer ends abnormally For example when SCL prolonging by the slave device is not terminated in a certain time this bit is set to 1 This bit is cleared by writing 0 by software I2CBMTO Description 0 Timeout has not occurred 1 Timeout has occurred ML630Q791 12 20 LAPIS Semiconductor Co Ltd DCBMIS bit 4 ML630Q791 User s Manual Chapter 12 I2C Bus Interface This bit is set to 1 if a STOP condition occurs at unexpected timing and the transfer ends abnormally This bit is set to 1 if a STOP condition is detected before this I2C device transmits a STOP condition during a transfer in the buffer mode This bit is cleared by writing 0 by software I2CBMAG bit 5 2 5 Description 0 Has not detected an
133. CS 1 0 Description 0 0 LSCLK initial value 0 1 HTBCLK 1 0 2 048kHz 1 1 External clock PAO PWMO POIS 1 0 bit 3 2 The POIS 1 0 is used to select the point at which the PWMO interrupt occurs When the periods coincide when the duties coincide or when the periods and duties coincide can be selected POIS 1 0 Description 0 0 When the periods coincide Initial value 0 1 When the duties coincide 1 When the periods and duties coincide PONEG bit 4 The PONEG bit is used to select the output logic of PWMO The initial value of PWMO output is 1 for the positive logic and 0 for the negative logic PONEG Description 0 Positive logic initial value 1 Negative logic FEUL630Q791 9 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 2 6 PWMO Control Register 1 PWOCON1 Address 0 4001 4410 Access R W Access size 32 Bits Initial value 0x0000_0040 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name n E E Access E M s 2 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbolname E a T x POST POFL 4 E gt PORU G N Access E R R W 2 z E z R W Initial value 0 0 0 0 0 0 0 0 0 1 Note Reserved bit for fu
134. E E N SIE TA X AK TA I2CMD 1 0 Access RW RW RW RAW R W R W RW R W R W R W RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register controls the transmission and reception of the bus This register can be read from or written to by software It controls only the interrupts of the interrupt enable registers namely I2CAASIE I2CALIE I2CCFIE I2CSTPIE I2CDR LDIE I2CISTPIE and I2CNSTPIE and does not control the corresponding bits of the status register The status register will change even if an interrupt is disabled Only the I2CMD and I2CMEN bits are used in the buffer mode Description of Bits e 2CMDI 1 0 bits 0 1 Select the standard mode or the fast mode I2CMD 1 0 Description 00 Selects the standard mode 100 kHz 01 Selects the fast mode 400 kHz 10 Setting prohibited 11 Setting prohibited I2CRSTA bit 2 Specifies to transmit the repeated START conditions If 1 is written to this bit when the module is a bus master a repeated START condition is sent to the bus This bit is automatically reset to 0 after sending a repeated START condition Note When sending a repeated START condition overwrite I2CMSTA as is with the setting of 1 Operation cannot be guaranteed if 1 is written to this bit IACRSTA and 0
135. F interrupt 1 Enables MCF interrupt I2CSTPIE bit 11 Specifies to enable or disable an STP interrupt The I2CSTP status will change even if an interrupt is disabled by this bit I2CSTPIE Description 0 Disables STP interrupt 1 Enables STP interrupt I2CDR LDIE bit 12 Specifies to enable or disable a LD interrupt The I2CDR_LD status will change even if an interrupt is disabled by this bit I2CDR LDIE Description 0 Disables DR LD interrupt 1 Enables DR LD interrupt Note The DR LD interrupt is a spare function It is not used in Section 12 3 Description of Operation Normally disable the DR 1 interrupt by setting this bit to 0 I2CCS bit 13 Specifies to halt SCL SCL stops subsequently to an MCF interrupt that is generated after this bit is set to 1 When inserting a repeated start after executing the transmit mode set this bit to 1 during a 1 byte data transfer period immediately before the insertion After the completion of the transfer set the I2CRSTA bit to 1 and at the same time clear this bit Specifies to enable or disable an STP interrupt The I2CSTP status will change even if an interrupt is disabled by this bit 0 Continues SCL output Stops SCL output upon completion of the next transfer ML630Q791 12 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 3
136. FLL oscillation clock is available When LFLL is it indicates that FLL is inactive or the frequency of the FLL oscillation clock is not within the specification range LFLL is a read only bit LFLL Description 0 FLL oscillation clock is disabled initial value 1 FLL oscillation clock is enabled 6 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 6 Clock 6 2 4 High Speed Time Base Counter Frequency Divide Register HTBDR Address 0x4004 0000 Access R W Access size 32 Bits Initial value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name _ oR _ _ _ _ _ _ iR _ _ _ _ Access s z gt 2 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbolname zi 57 zi ai zi 3 0 Access RW RAN RAN R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing HTBDR is a special function register SFR to set the dividing ratio of the 4 bit 1 n counter Description of Bits e HTD 3 0 bit 3 0 The HTD 3 0 bits are used to set the dividing ratio of the 4 bit 1 n counter The frequency divide ratios selectable include 1 1 to 1 16 The 4 MHz clock is divided to output a clock FEUL630Q791 HTD 3 0 Descriptio
137. G becomes 1 at the next POCK rising edge and PWOC is reset to 0x0000 to continue incremental counting At the same time the value of the PWMO duty register PWOD is transferred to the PWMO duty buffer PWODBUF and the value of PWMO cycle register PWOP to the PWMO period buffer PWOPBUF When the PORUN bit is set to 0 PWOC stops incremental counting after counting once the rising of the PWM clock POCK Confirm that PWOC is stopped by checking that the POSTAT bit of the PWMO control register 1 is 0 When the PORUN bit is set to 1 again the PWOC counter register restarts incremental counting from the previous value on the next rising edge of POCK To initialize PWOC to 0x0000 perform write operation in PWOC At that time POFLG is also set to 1 During count stop PORUN is 0 data written in the PWMO duty register PWOD is transferred to the PWMO duty buffer and data written in the PWMO cycle register PWOP is transferred to the PWMO period buffer PWOPBUF PWM clock the point at which an interrupt of PWMO occurs and the logic of the PWM output are selected by PWMO control register 0 PWOCONO The period of the PWMO signal Tpwp and the first half duration Tpwp of the duty are expressed by the following equations NN PWOP 1 irm POCK Hz PWOD 1 POCK Hz PWOP PWMO cycle registers PWOP setting value 0x0001 to OxFFFF PWOD duty regi
138. G interrupt 1 Enables I2CBMAG interrupt I2CBMDZIE bit 6 Specifies to enable or disable an I2CBMDZ interrupt The IDCBMDZ status will change even if an interrupt is disabled by this bit I2CBMDZIE 0 Disables IPCBMDZ interrupt Enables I2CBMDZ interrupt Note Set this bit in the initial setting flow or before the master transfer start Operation cannot be guaranteed if the value of this bit is changed during transfer ML630Q791 12 19 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 13 Buffer Mode Status Register I2CBUFSTAO 1 Address 0x4008_3030 Och 0x4008_3430 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1514 1 12 11 10 9 7 6 5 4 3 2 i 0 Symbolname gt 2 2 2 2 2 DZ AG IS TO NA FI Access 4 F RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CBUFSTA register indicates each status in the buffer mode Write 0 to each bit to clear it This register is enabled only when the buffer mode is used Description of
139. GPIO port control register PIOCON R W 32 0x0000_0000 0x4000_A010 GPIO interrupt enable register PIOIE R W 32 0x0000_0000 0x4000_A014 GPIO interrupt mode register PIOIM R W 32 0x0000_0000 0x4000_A018 GPIO interrupt status register PIOIS R W 32 0x0000_0000 FEUL630Q791 15 2 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 2 2 GPIO Port Data Register PIODAT Address 0x4000 A000 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 290 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name _ _ _ _ _ _ _ _ _ _ 1 1 1 1 1 1 1 1 1 z s z E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name PIODAT 6 0 Access RW RW RW RW RAW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register is a special function register SFR to set the value to be output to the Port A pin or to read the input level of the Port A pin In output mode the value of this register is output to the Port A pin The value written to PIODAT is readable In input mode the input level of the Port A pin is read when PIODAT is read Output mode or input mode is selected by using the port mode
140. HIFRLT20H HIFRLT20 R W 32 16 8 0x00 0x61 Result register 21 HIFRLT21 R W 8 0x00 FEUL630Q791 11 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface Address Name Symbol Symbol Symbol R W Size Initial value Word Half Word Byte bits 0x62 Result register 22 HIFRLT22H HIFRLT22 R W 16 8 0x00 0x63 Result register 23 HIFRLT23 R W 8 0x00 0x64 Result register 24 HIFRLT24W HIFRLT24H HIFRLT24 R W 32 16 8 0x00 0x65 Result register 25 HIFRLT25 R W 8 0x00 0x66 Result register 26 HIFRLT26H HIFRLT26 R W 16 8 0x00 0x67 Result register 27 HIFRLT27 R W 8 0x00 0x68 Result register 28 HIFRLT28W HIFRLT28H HIFRLT28 R W 32 16 8 0x00 0x69 Result register 29 HIFRLT29 R W 8 0x00 0x6A Result register 2A HIFRLT2AH HIFRLT2A R W 16 8 0x00 0xeB Result register 2B HIFRLT2B R W 8 0x00 0x6C Result register 2C HIFRLT2CW HIFRLT2CH HIFRLT2C R W 32 16 8 0x00 0 60 Result register 2D HIFRLT2D R W 8 0x00 Ox6E Result register 2E HIFRLT2EH HIFRLT2E R W 16 8 0x00 0 6 Result register 2F HIFRLT2F R W 8 0x00 0x70 Result register 30 HIFRLT30W HIFRLT30H HIFRLT30 R W 32 16 8 0x00 0x71 Result register 31 HIFRLT31 R W 8 0x00 0x72 Result register 32 HIFRLT32H HIFRLT32 R W 16 8 0x00 0x73 Result register 33 HIFRLT33 R W 8 0x00 0x74 Result register 34 HIFRLT34W HIFRLT34H HIFRLT34 R W 32 16 8 0x00 0x75 Resul
141. IC_IPR6 0x0000_0000 OxE000_E41C Interrupt priority register 7 NVIC_IPR7 0x0000_0000 0 000 EDOO CPUID register CPUID 0 410 C200 0 000 EDOA4 Interrupt control and state register ICSR 0x0000 0000 0 000 EDOC Application interrupt and reset control register AIRCR OxFA05 0000 OxEO00 ED10 System control register SCR 0x0000 0000 OxEO00 ED14 Configuration and control register CCR 0x0000 0208 OxEO00 ED1C System handler priority register 2 SHPR2 0x0000 0000 OxEO00 ED20 System handler priority register SHPR3 0x0000_0000 FEUL630Q791 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix B Package Dimensions Appendix B Package Dimensions LAPIS Semiconductor Co Ltd S UFLGA20 1 84x2 14 0 40 W NOTES 1 THE DIMENSIONS ON PACKAGE OUTLINE INCLUDES THE TERMINAL SOLDER 2 THE BALL PITCH MEANS THE DISTANCES BETWEEN THE TERMINAL CENTERS Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code and desired mounting conditions reflow method temperature and times FEUL630Q791 1 LAPIS Sem
142. MSUB2 bit 23 16 This register sets the sub address 2 sent to the transfer destination device 2CBMSUB3 bit 31 24 This register sets the sub address 3 sent to the transfer destination device When the value set for I2CBMSL of the I2CBUFFOR register is 000 the setting value of this register is disabled and the sub address is not sent When the setting value of I2CBMSL is 0017 the data in IDDCBMSUBO is sent to the bus When the setting value of IZCBMSL is 0107 the data in IDCBMSUBI and I2ZCBMSUBO is sent to the bus in this order When the setting value of I2CBMSL is 011 the data in I2CBMSUB2 I2CBMSUBI and I2CBMSUBO is sent to the bus in this order When the setting value of I2CBMSL is 100 the data in I2ZCBMSUB3 I2CBMSUB2 I2CBMSUBI and I2CBMSUBO is sent to the bus in this order Note Set this bit in the initial setting flow or before the master transfer start Operation cannot be guaranteed if the value of this bit is changed during transfer ML630Q791 12 15 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 10 Buffer Mode Format Register I ICBUFFORDO 1 Address 0 4008 3024 Och 0 4008 3424 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10
143. MTO bit in the I2CBUFSTA register is set to 1 when it takes the timeout setting value or longer to transmit and receive each one byte in the buffer mode The transfer is stopped when a timeout occurs Description of Bits I2CT 15 0 bits 15 0 The timeout interval can be calculated from the setting value of I2CT as follows Timeout interval I2CT setting value 8 System clock frequency Here are the examples of setting the timeout interval to 1ms and 8ms 2 System clock frequency For 1ms For 8ms interval interval 32MHz OxOFAO 0x7D00 When I2CT is set to 0 a timeout interrupt does not occur Note Set this bit in the initial setting flow or before the master transfer start Operation cannot be guaranteed if the value of this bit is changed during transfer Setting I2CT to less than the time required for the transfer always results in a timeout One byte transfer takes 90 us in the standard mode 100 kbps and 22 5 us in the fast mode 400 kbps ML630Q791 12 23 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 16 Input Noise Filter Setting Register I2CNFO 1 Address 0 4008 3050 Och 0 4008 3450 1ch Access R W Access size 32 Bits Initial value 0 0000 0001 Bit Symbol name Access y s 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3
144. NTE EE uU A 1 Appendix Package Dimensions eene eene eee ero esee bienes eene b B 1 Appendix C Electrical Characteristics nissernes resis o ree nete tene enne C 1 Appendix D Application Circuit Example eene enne D 1 Revision History History t DEEP 1 FEUL630Q791 vii Chapter 1 Overview LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 1 Overview 1 Overview 1 1 Features This LSI is a high performance low power 32 bit microcontroller optimized for the control of various sensor ICs Equipped with a 32 bit CPU core Cortex MO it implements a 128 KB flash memory 16 KB RAM rich interfaces used to control various sensors and host interface with the 512 byte communication register in a very compact package This LSI can efficiently control the power consumption of the whole system by separating the sensor control function from the application processor and its high performance permits sensor fusion using accelerometers magnetic field sensors and gyro sensors which makes it an ideal sensor control microcontroller for smart phones e CPU 32 bit RISC CPU CPU ARM Cortex M0 Thumb Thumb 2 instruction supported Serial Wire Debug Port supported Internal memory 128 KB FLASH ROM 32K x
145. OIE eese eren eene enne Er nennen ES tren 15 6 15 2 6 GPIO Interrupt Mode Register tnnt tenete trennen 15 7 15 2 7 GPIO Interrupt Status Register PIOIS ieri ehe ripetere rie eene 15 8 15 3 Description of Operation tee ete eee PAN E IKRE E AE Reiten 15 9 15 31 MOS ett Sis eet RET e pO eap Me ERE e lee seed es ee RE 15 9 15 3 2 Interrupt Setting Procedure cete ee eet tee repete eMe rte e Eo ee Reste a Pese reete ERE REOR GRE 15 9 15 3 3 Various Interrupt Operations Eo eee VEERE E tren tren 15 9 15 3 3 1 Falling Edge Interrupt Mode ereet rn earan r enne 15 10 15 3 3 2 Rising Edge Int rr pt deer Eten PR cee Hei Ee 15 11 15 3 3 3 E level Input Interrupt eet Ete ete en Ern Poe eMe ee ERE 15 12 15 3 3 4 H Ievel Input Interr pt entree Ero E MIR ee ERE 15 13 15 3 3 5 Both edge Rising Falling Interrupt esee nennen enne nenne nene nennen trennen 15 14 Chapter 16 16 HlashiPrograrmming ing et e et mo ette m EI e E ee Re m Rete eii potent 16 1 16 1 General Description nee lo aet e be RU o t Re ee Ehe o etie toe t p 16 1 DG Velie Eeatures sre RUE atto Se RED ute be ir Rude esi
146. Output odd or even parity 1 Always output 0 or 1 LCR5 LCR4 LCR3 Description 0 0 1 Output odd parity 0 1 1 Output even parity 1 0 1 Parity output 1 is forced 1 1 1 Parity output 0 is forced LCR6 bit 6 Break Control bit Sends out a break signal When LCR 6 1 the serial output TXDO is set to a spacing state 0 The break state can be disabled by setting LCR 6 0 The Break Control bit is valid only for TXDO i e TXDO will be masked but the transmit operation will continue internally Break Control allows the CPU to send an alarm to the terminal of the computer communication system LCR6 Description 0 Normal operation 1 Sends out a break signal LCR7 bit 7 Devisor Latch Access Bit DLAB Selects whether to access UARTDLL UARTDLM to access UARTRBR UARTTHR UARTIER LCR7 Description 0 Normal operation allows access to UARTRBR UARTTHR UARTIER 1 Divisor Latch access allows access to UARTDLL UARTDLM 13 11 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 2 6 UART Line Status Register UARTLSR Address 0 4008 1014 Access R Access size 32 Bits Initial value 0 0000 0060 Bit Symbol name Access gt 5 2 gt 5 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name LSR7 LSR6 L
147. PIOIE to 1 For the interrupt setting procedure see Chapter 15 3 2 Interrupt Setting Procedure FEUL630Q791 15 9 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 3 3 1 Falling Edge Interrupt Mode For Detection with Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 1000 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when a falling edge of the input signal of GPIO pin is detected Note that the assertion period of L after the falling edge must be 125 us two cycles at 16 kHz or longer By writing 1 to the GPIO interrupt status register PIOIS from CPU the GPIO interrupt status register PIOIS is cleared to 0 and the interrupt is released at the same time If an interrupt source is generated at the same timing as the release of the interrupt from CPU the interrupt generation has priority Figure 15 2 shows an operation example GPIO Port PIODIRn 4 21 i n A B PIOCONn o 08 LONE ee LE PIOIEn o a 0 6 i PIOIMn 4000 i o ss pu es PIOISn n 0 6 INTn 1 n 0 6 4 1 2 1 Edge interrupt assertion period At least 125 us at least 2 cycles or longer at 16 kHz 2 Interrupt status clear Write 1 to the PIOISn bit 1 Internal interrupt signal Figure 15 2 Example of Falling Edge Interrupt Oper
148. R used to set the base address of remapping It is enabled only when REMAP EN 1 and REMAP 2 0 100 are set in the remapping control register Description of Each Bit REMAP BASE 29 12 The 4 KB area starting at the address set by this register is assigned starting from address 0 The starting address must be an address in the memory space Flash ROM 0x1000 0000 0x1001 FFFF Work RAM 0 2000 0000 0x2000 3FFF Area assigned to the remapping area is only 4 KB at the remapping by the remapping base address If the space exceeding 4 KB is needed for ISP for example the program needs to jump to the area where the entity such as Flash ROM is placed 0x10000000 and after for Flash ROM to be executed except for the minimum necessary codes such as exception vectors FEUL630Q791 3 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 3 4 4 Boot Remapping Function It is possible to allocate the following devices to BankO after booting by setting REMAP 3 0 of the remapping control register Table 3 3 shows the allocations of BankO during booting and remapping Operation cannot be guaranteed if remapping is performed when the remapping processing program instruction to set the remapping control register is placed in 0 Be sure to place the remapping processing program in a Bank other than when performing the remapping Table 3 3 BankO Allocations during Booting and Remapping Boot Device
149. RAN R W RAW RW R W RAN R W R R Initial value 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Description of Register Operation status register HIFST is a special function register SFR used to indicate the sensor measurement status and notify the host processor of the error code Description of Bits ST bit 15 8 This bit indicates the status of the sensor measurement When this bit is set the set value is transferred to the register for host access HSTRG STATUS For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification ERI ERO bit 31 16 This bit sets the interrupt source of the error code to the host processor When this bit is set the set value is transferred to the register for host access HSTRG ERRORO 1 For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification RLTP bit 1 This bit indicates the write status to the result register Confirm that this bit is set to 0 before power down In case of power down with this bit set to 1 the written data is reflected to the result register after returning from power down RLTP Description 0 No writing to result register initial value 1 Writing to result register INTP bit 0 This bit indicates the write status to the interrupt request register Confirm that this bit is set to 0 before power down after issuing an inte
150. ROHM GROUP L A 2 FEUL630Q791 SEMICONDUCTOR ML630Q791 User s Manual Issue Date Oct 22 2014 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Notes 1 2 3 4 5 7 8 9 10 11 12 13 The information contained herein is subject to change without notice Although LAPIS Semiconductor is continuously working to improve product reliability and quality semiconductors can break down and malfunction due to various factors Therefore in order to prevent personal injury or fire arising from failure please take safety measures such as complying with the derating characteristics implementing redundant and fire prevention designs and utilizing backups and fail safe procedures LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor Examples of application circuits circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products The peripheral conditions must be taken into account when designing circuits for mass production The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products license expressly or implied is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or an
151. SETENA 28 CLRENA 28 SETPEND 28 CLRPEND 28 NVIC IPR7 PRI 28 1 0 IRQ 29 29 CLRENA 29 SETPEND 29 CLRPEND 29 NVIC_IPR7 PRI_29 1 0 IRO 30 SETENA 30 CLRENA 30 SETPEND 30 CLRPEND 30 NVIC IPR7 PRI 30 1 0 IRQ 31 SETENA 31 CLRENA 31 SETPEND 31 CLRPEND 31 NVIC IPR7 PRI 31 1 0 FEUL630Q791 7 3 LAPIS Semiconductor Co Ltd 7 3 Description of Operation ML630Q791 User s Manual Chapter 7 Interrupt For 21 sources which do not include the watchdog timer interrupt WDTINT interrupt enable disable is controlled by NVIC ISER and NVIC ICER WDTINT is a non maskable interrupt When the interrupt conditions are satisfied the CPU reads the exception handler start address from the vector table address determined for each interrupt source and starts executing the exception handler Table 7 2 lists the interrupt sources Note Interrupt number Table 7 2 Interrupt Sources Interrupt source Symbol Vector table address NMI Watchdog timer interrupt WDTINT 0x0000 0008 IRQ O 0x0000 0040 IRQ 1 0x0000 0044 IRQ 2 Port PA1 interrupt PA1INT 0x0000 0048 IRQ 3 Timer 0 interrupt TMOINT 0 0000 004C IRQ 4 Timer 1 interrupt TM1INT 0x0000 0050 295 050000 0054 IRQ 6 Port PAO interrupt PAOINT 0x0000 0058 IRQ 7 C bus 0 interrupt 2 0 0000 005 IRQ 8 0 0000_0060 IRQ 9 Port PA4 interrupt PA4INT 0x0000_0064 IRQ 10
152. SLT0O5 R 8 0x00 OxC6 Result register 06 RSLTO6 R 8 0x00 OxC7 Result register 07 RSLTO7 R 8 0x00 OxC8 Result register 08 RSLT08 R 8 0x00 OxC9 Result register 09 RSLTO9 R 8 0x00 OxCA Result register 0A RSLTOA R 8 0x00 OxCB Result register OB RSLTOB R 8 0x00 OxCC Result register OC RSLTOC R 8 0x00 OxCD Result register OD RSLTOD R 8 0x00 OxCE Result register OE RSLTOE R 8 0x00 11 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface Address Size Initial Write Read Name Symbol R I pitts OxCF Result register OF RSLTOF R 8 0x00 OxDO Result register 10 RSLT10 R 8 0x00 OxD1 Result register 11 RSLT11 R 8 0x00 OxD2 Result register 12 RSLT12 R 8 0x00 OxD3 Result register 13 RSLT13 R 8 0x00 OxD4 Result register 14 RSLT14 R 8 0x00 OxD5 Result register 15 RSLT15 R 8 0x00 OxD6 Result register 16 RSLT16 R 8 0x00 OxD7 Result register 17 RSLT17 R 8 0x00 OxD8 Result register 18 RSLT18 R 8 0x00 OxD9 Result register 19 RSLT19 R 8 0x00 OxDA Result register 1A RSLT1A R 8 0x00 OxDB Result register 1B RSLT1B R 8 0x00 OxDC Result register 1C RSLT1C R 8 0x00 OxDD Result register 1D RSLT1D R 8 0x00 OxDE Result register 1E RSLT1E R 8 0x00 OxDF Result register 1F RSLT1F R 8 0x00 OxEO Result register 20 RSLT20 R
153. SR5 LSR4 LSR3 LSR2 LSR1 LSRO Access R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Description of Register UARTLSR is a special function register SFR used to display the status UARTLSR is normally the first register read out by the CPU for determining the interrupt cause or for polling the status of the serial communication channel When any one of the conditions LSR 1 to LSR 4 is detected it is an error condition for the Receiver Line Status to generate an interrupt interrupt of parity 1 in the Interrupt Identification Register URATIIR This interrupt is enabled by setting IER 2 1 in the UARTIER register Description of Bits 1560 bit 0 Data Ready bit This bit is set to 1 when the input character has been received and transferred to the UARTRBR register This bit is cleared when the UARTRBR register data is read out LSRO Description 0 No valid data in the RBR register 1 Valid data present in the RBR register LSRI bit 1 Indicates that an overrun error occurred Overrun error bit indicates that the CPU did not read the data in the UARTRBR register before the next character was sent to the UARTRBR register and overwrote the previous character In FIFO mode an overrun error occurs after the next character has been completely received when the FIFO is full UARTLSR register read
154. Symbol name Access E 5 E E 2 E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name zi zi E 2 cd zi 55 zr 2 5 0 Access 5 RW RAN RW RW RW 0 0 0 0 0 0 Initial value 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CBUFLEV register indicates the amount of data remaining in the buffer This register is enabled only when the buffer mode is used ML630Q791 12 22 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 15 Timer Register I2CTMRO 1 Address 0x4008_3048 Och 0x4008_ 3448 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access gt s 5 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name I2cT 15 0 Access RAW R W R W R W RAW R W R W RAW RAN RAW RAN R W RAW R W RW R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CTMR register sets the interval of the timeout in the buffer mode This register is enabled only when the buffer mode is used The I2CB
155. TRG FIFO Register FIFO Address 0x10 write 0x90 read Access R W Access size 8 Bits Initial Value ML630Q791 User s Manual Chapter 11 Host Interface Bit 7 6 5 4 3 2 1 0 FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO 6 5 4 3 2 1 0 Access R W R W R W R W R W R W R W R W Initial value x x X x X x x x FIFO register is a register that can be written read from the host processor This register can be written read from the host processor only when FSEL of the CPU register is set to 1 When FSEL is set to 0 writing is disabled and reading gets Undefined Description of Bits FIFO 7 0 bit 7 0 Indicates the FIFO data For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 25 LAPIS Semiconductor Co Ltd 11 2 22 HSTRG Parameter Register n PRMn n 00 to OF Address 0x20 to Ox2F write OxAO to Ox AF read Access R W Access size 8 Bits Initial value 0x00 ML630Q791 User s Manual Chapter 11 Host Interface Bit 7 6 5 4 3 2 1 0 PRMn PRMn PRMn PRMn PRMn PRMn PRMn PRMn Symbol name 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 PRMn is a register that can be written read from the host processor that sets the command parameter Description of Bits PRMn 7 0 bit 7 0 Represents a command parameter For de
156. User s Manual Chapter 3 Memory Space OxEO7F FFFF OxE0O10 0000 OxEO00 04 Nested Vectored Interrupt Controller NVIC OxEO00 00 0xE000_ED40 System Control Block 0xE000_ED00 Address OxE07F_FFFF OxEO00 0000 0xE000_E4F0 Nested Vectored Interrupt e OIEA Controller NVIC 0 000 E100 OxEO00 E020 OxEO00 E010 System Control Block 0 000 E008 0 000 0000 Reserved area 1 Accessing any of reserved areas is prohibited Proper operation cannot be guaranteed if accessed Figure 3 1 2 Cortex MO Peripherals Area Memory Map FEUL630Q791 3 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 0x47FF_FFFC 0 4008 3500 0 4008 3400 0 4008 3100 Co 0 4008 3000 0 4008 1400 UART 0x4008 1000 0x4005 0400 HSTIF 0x4005 0000 0x4004 5400 Address CALBLK 2 0x4004 5000 0x47FF_FFFC 0x4000 0000 APB I O 0x4004 0400 HTBC 0x4004 0000 0 4001 4800 PWM 0x4001_ 4400 0x4001_0800 WDT 0x4001_0400 0x4000_A400 GPIOA 0x4000_A000 0x4000_2400 Timer67 0x4000_ 2000 45 2 0 4000 1 00 Timer23 0x4000_ 1800 01 2 0 4000 1400 0 4000 0800 Internal Flash ROM control 0x4000 0400 Clock control 0x4000 0300 MCU control 0x4000 0200 System control 0 4000 0000 R
157. W RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP22D is a special function register SFR used to set the value to start disabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCPP22DI 23 0 bit 23 0 For FSCPP22D 23 0 the write signal to Flash ROM is disabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 18 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 18 Set Count Program PROG2 3rd Enable Register FLCSCPP23E Address 0 4000 0494 Access R W Access size 32 Bits Initial Value 0x0000 0245 Bit 91 30 29 28 27 2 2 24 28 22 21 20 19 18 17 16 Symbolname 900 0000 00 so 2 23 16 Access RRR RW RW RW RW RN Intialvalue 0 0 0 0 O 0 0 0 0 Bit 15 14 43 12 di 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSCPP23E 15 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP23E is a special function register SFR used to set t
158. a special function register SFR used to store input data for the operation CALBL register sets the lower 32 bits of the divisor for division Setting the divisor to 0 is prohibited For details see 14 3 Description of Operation FEUL630Q791 14 6 ML630Q791 User s Manual Chapter 14 Arithmetic Circuit LAPIS Semiconductor Co Ltd 14 2 6 Operation Input Register BH CALBH Address 0 4004 5014 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALB A7 32 RAN RW RW R W RAN RAN R W RAW R W RW RAN RAN RAW RAW RW RW Access 0 0 0 0 0 0 0 0 0 0 0 0 Initial value 0 0 0 0 CALBH is a special function register SFR used to store input data for the operation CALBL register sets the higher 16 bits of the divisor for division Setting the divisor to 0 is prohibited For details see 14 3 Description of Operation FEUL630Q791 14 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 14 Arithmetic Circuit 14 2 7 Calculation Result Register OL CALROL Address 0 4004 5018 Access R Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name CALRO 31 16 Access R R R R R R R R R R R R R R R R Initial value
159. ailable FIFO at or above tSINT Trigger Level nUARTINT Received Line Status RD LSR read RBR read tSINT 3 Buad rate Clocks tRINT 1 Baud rate Clock Figure 13 5 First Byte of the Receive FIFO Set RDR RXDO Start Data bit 5 8 Stop Sample CLK 7 FIFO below Trigger Level nUARTINT Received Data Available tSINT FIFO at or above Trigger Level nUARTINT Received Line Status Top Byte of FIFO RD RBR read LSR read RBR read Previous Byte read from FIFO tSINT MAX 3 Buad rate Clocks For a timeout 8 Baud rate Clocks tRINT MAX 1 Baud rate Clock Figure 13 6 Remaining Bytes in the Receive FIFO FEUL630Q791 13 18 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 3 Baud Rate Clock Generation A baud rate is obtained by the following expression Baud rate frequency SYSCLK 12 13 DL 15 0 16 The actual baud rate available for communication will depend on the software process Under ideal conditions setting DL 2 should enable communication Make sure that the margin of error between the actual and set baud rates is within a few percent Note Divisor DL 15 0 value cannot be set to 1 Set a value of 0 stop or greater than 2 The following table shows the relation among SYSCLK DL and baud rates Baud rate SYSCLK 32MHz bps DL Hex Error 300 180A 0 002 600 0C05 0 002 1200 060
160. al Value 0x0002 1474 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name RU FSCSCE 23 16 Access Exe IP RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSCSCE 15 0 Access RW RAN RAN RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCSCE is a special function register SFR used to set the initial value of the erase program counter at the time of selector erase of Flash ROM Description of Bits FSCSCE 23 0 bit 23 0 FSCBCE 23 0 is a bit used to set the initial value of the erase program counter at the time of selector erase of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 11 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 11 Set Count Program CE Enable Register FLCSCPCE Address 0 4000 0470 Access R W Access size 32 Bits Initial Value 0x0000 04 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name A RU us FSCPCE 23 16 Access Exe IP RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name
161. al setting flow or before the master transfer start Operation cannot be guaranteed if the value of this bit is changed during transfer ML630Q791 12 16 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 11 Buffer Mode Control Register I2CBUFCTLO 1 Address 0 4008 3028 Och 0 4008 3428 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ _ _ _ _ _ _ I2CBM Symbol name STA 1 1 1 1 1 Access R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CBUFCTL register specifies the start of I2C operation in the buffer mode This register is enabled only when the buffer mode is used Description of Bits I2CBMSTA bit 0 Sets the start of the transfer in the buffer mode For master transmission set the I2CBUFSLV I2CBUFSUB I2CBUFFOR I2CBUFMSK and I2CBUFTMR registers write the transmit data to the buffer and then set this bit to 1 This bit will be cleared to 0 after starting transfer when the transfer of the specified bytes is finished or transfer is stopped due to err
162. alculation Result Register 1L CALR1L Address 0 4004 5020 Access R Access size 32 Bits Initial value 0 0000 0000 ML630Q791 User s Manual Chapter 14 Arithmetic Circuit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name CALR 1 31 16 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALR1 15 0 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALRIL is a special function register SFR that stores the result data of the operation CALRIL register indicates the lower 32 bits of the remainder in the division result for division For details see 14 3 Description of Operation 14 10 FEUL630Q791 LAPIS Semiconductor Co Ltd 14 2 10 Calculation Result Register 1H CALR1H Address 0x4004 5024 Access R Access size 32 Bits Initial value 0 0000 0000 ML630Q791 User s Manual Chapter 14 Arithmetic Circuit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALR1 47 32 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALRIH is a special function register SFR that stores the result data of the operation CALRIH register indicates the higher
163. alue matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 20 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 20 Set Count Program PROG2 4th Enable Register FLCSCPP24E Address 0 4000 049C Access R W Access size 32 Bits Initial Value 0x0000 0179 Bit 91 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbolname 900 0000 uos uso FSCPP24E 23 16 Access ROR RW RW RW RW HW RN Initialvalue 0 O0 0 0 0 0 0 0 0 0 Bit 15 144 13 12 1 30 9 7 6 5 4 3 2 14 0 Symbol name FSCPP24E 15 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP2AE is a special function register SFR used to set the value to start enabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits FSCPP24E 23 0 bit 23 0 For FSCPP24E 23 0 the write signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 21 LAPIS Semiconductor Co Ltd 16 2 21 Set Count Program PROG2 4th Disable Register FLCSCPP24D
164. an ACK 1 Received a NACK I2CMIF bit 1 Indicates that an interrupt has been requested This bit is an interrupt line monitoring bit If interrupt is enabled for MCF interrupt MAAS interrupt MAL interrupt DR LD interrupt STP interrupt NSTP interrupt and ISTP interrupt this bit is set to 1 at the same time that the bit I2ZCMCF I2CDR LD I2CNSTP and I2CISTP for each interrupt source is set to 1 To clear this bit clear an interrupt line it is necessary to write 0 to each of the interrupt source bits I2CMCF I2CDR LD I2CNSTP and I2CISTP I2CMIF Description 0 No interrupt request 1 Interrupt request Note Whether or not to enable each interrupt is set by the I2CCTL register For details refer to I2C Control Register I2CCTLO 1 ML630Q791 12 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface DCDR LD bit 3 This bit indicates that the transmit buffer is emptied and transmit data can be loaded to the I2CDR register After this bit has been set to 417 in the transmit mode the data to be sent next can be written into the data register without destroying the previously transmitted data This bit is cleared by writing 0 by software This bit is set to 1 when the transfer of 2 bits out of 8 bit transmit data is finished at a falling edge of SCL By using this bit interrupt transmit data can be written before an MCF interrupt
165. arithmetic circuit timer PWM are possible Sleep mode SLEEPDEEP bit 1 Cortex M0 sleep mode During the sleep mode the setting of individual block that is set before entering the sleep mode is enabled FLL is automatically stopped when entering the sleep mode Then FLL is started or goes into the stop state according to the setting of the ENOSC bit of the FCON1 register when returning from the sleep mode due to an interrupt In this mode the communication of host interface and the operation of timer PWM based on the low speed clock are possible FEUL630Q791 5 10 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 3 2 State of Each Operation Mode The operation states of CPU FLL and individual block in each operation mode are as follows O Operates x Stopped A Follows the register setting Operation mode After release After release Program run Sleep mode Sleep mode of the system of the system mode SLEEPDEEP 0 SLEEPDEEP 1 reset mode reset mode External Software reset reset CPU FLL O 1 O 2 A Internal regulator O 3 O 4 0 A A 5 A 6 Timer1 x x A A 5 A 6 Timer2 x x A A 5 A 6 Timer3 x x A A 5 A 6 Timer4 x x A A 5 A 6 5 A 5 A 6 Timer6 x x A A 5 A 6 Timer7 x x A A 5 6 A AN
166. ated in the UARTIIR register this bit will be cleared by reading out the UARTIIR register LSR5 Description 0 Transmit data still present in the THR 1 THR ready for transmission FEUL630Q791 13 13 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual LSR6 bit 6 Chapter 13 UART Transmitter Empty This bit is set to 1 when both the UARTTHR register and the Transmitter Shift Register TSR are empty The UARTLSR register will be cleared to 0 when a character is loaded into the UARTTHR register and this 0 state is maintained until that character is transferred out from TXDO This bit will not be cleared to 0 by reading out the UARTLSR register In FIFO mode this bit is set to 1 when both the transmit FIFO and the shift register are empty LSR6 0 Description Transmit data still present in either THR or TSR register 1 THR and TSR registers are both empty LSR7 bit 7 This bit is always 0 in the 16450 compatible mode In FIFO mode this bit is set to 1 when at least one Parity Error Framing Error or Break Interrupt is present in the data within the FIFO This bit will be cleared when the data causing the error is read out from the RBR or when the data causing the error is cleared by first clearing the FIFO and then reading out the LSR LSR7 Description 0 No data error in FIFO mode 1 A parity error framing error or break inte
167. ation For Detection without Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 0000 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when a falling edge of the input signal of GPIO pin is detected Note that the assertion period of L after the falling edge must be one cycle of system clock or longer The interrupt is generated after the pin is asserted or after three sysclk cycles The external input is used after being synchronized with sysclk in two stages For the detection with sampling the input signal is synchronized with sysclk through 16 kHz FEUL630Q791 15 10 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 15 GPIO 15 3 3 2 Rising Edge Interrupt For Detection with Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 1001 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when a rising edge of the input signal of GPIO pin is detected Note that the width of after the rising edge must be 125 us two cycles at 16 kHz or longer By writing 1 to the GPIO interrupt status register PIOIS from CPU the GPIO interrupt status register PIOIS is cleared to 0 and the interrupt is released at the same time If an interrupt source is generated at the same timing as the release of the interrupt from CPU the interru
168. ble Register PERSTEN Address 0 4000 0228 Access R W Access size 32 Bits Initial value 0x0113 11FF Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 a URE HST CAL UART I2C1 l2CO Access RAN R W R W RW RW RAN RAN RAW RAW R W R W RAN RAN R W RW RW Initial value 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 Bit 1514 13 12 11 0 9 8 7 6 5 4 3 2 1 0 aa a N REIRE RE I REI RE RENREN RE HTC PWM TM7 6 TM5 4 2 TM1 TMO Access RW R W R W R W RW RW RAW RW RW RAW RAW RAW RW RW RW RW Initial value 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing PERSTEN is a special function register SFR used to assert the reset of each peripheral and can be accessed only by writing 1 Access by writing 0 is invalid The block can be stopped by setting the peripheral clock disable register PECLKDIS after setting PERSTEN When the peripheral reset disable register PERSTDIS is accessed by writing 1 the corresponding bit of PERSTEN is automatically reset to O The reset asserted state of each peripheral 1 indicates the asserted state can be read when reading Description of Bits Symbol Description Related Bit name PECLKEN PECLKDIS PERSTDIS RETM
169. ble or disable an MAAS interrupt The I2CMAAS status will change even if an interrupt is disabled by this bit I2CAASIE Description 0 Disables MAAS interrupt 1 Enables MAAS interrupt I2CMEN bit 7 Initializes this module Set this bit to 1 when using this module 2 0 _ Initializes this C module Enables this module Note If the I2CMEN bit is set to 0 the bus control section PC status register including the I2CMBB bit buffer level register and buffer mode status register will be initialized The buffer mode format register control register data register bus monitor register bus transfer rate setup counter mode register buffer mode slave address register buffer mode sub address register buffer mode interrupt mask register and I C timer register will not be initialized ML630Q791 12 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface I2CALIE bit 8 Specifies to enable or disable an MAL interrupt The I2CMAL status will change even if an interrupt is disabled by this bit I2CALIE Description 0 Disables MAL interrupt 1 Enables MAL interrupt I2CCFIE bit 9 Specifies to enable or disable an MCF interrupt The I2CMCF status will change even if an interrupt is disabled by this bit I2CCFIE Description 0 Disables MC
170. buffer mode The corresponding bit of the status register is not controlled The status register will change even if an interrupt is disabled Description of Bits I2CBMFIIE bit 0 Specifies to enable or disable an IDDCBMFI interrupt The IZCBMFI status will change even if an interrupt is disabled by this bit I2CBMFIIE Description 0 Disables 2 interrupt 1 Enables I2CBMFI interrupt I2CBMNAIE bit 2 Specifies to enable or disable an DDCBMNA interrupt The I2CBMNA status will change even if an interrupt is disabled by this bit I2CBMNAIE Description 0 Disables 2 interrupt 1 Enables I2CBMNA interrupt I2CBMTOEIE bit 3 Specifies to enable or disable an I2CBTO interrupt The IZCBMTO status will change even if an interrupt is disabled by this bit I2CBMTOIE 0 Disables 2 interrupt Enables I2CBMTO interrupt ML630Q791 12 18 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface I2CBMISIE bit 4 Specifies to enable or disable an I2CBMIS interrupt The I2CBMIS status will change even if an interrupt is disabled by this bit I2CBMISIE Disables I2CBMIS interrupt a 0 Enables I2CBMIS interrupt I2CBMAGIE bit 5 Specifies to enable or disable an I2CBMAG interrupt The I2CBMAG status will change even if an interrupt is disabled by this bit I2CBMAGIE Description 0 Disables I2CBMA
171. ception Read I2CDR register to start next 1 byte reception First byte after specifying slave device shall be dummy read Wait for data transfer completion Clear data transfer completion flag Clear interrupt flag Set to send NACK at completion of reception Read I2CDR register to start next 1 byte transmission Wait for data transfer completion Clear data transfer completion flag Clear interrupt flag Issue stop condition Read final byte data ML630Q791 User s Manual Chapter 12 I2C Bus Interface Waiting for receiving next data SCL L Receiving 1 byte Output ACK at completion of reception Waiting for receiving next data SCL L Receiving 1 byte Output ACK at completion of reception Waiting for sending stop condition Send stop condition To Bus IDLE 12 30 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 3 5 Flow of Compound Mode Transmitting from Master after Receiving by Master START Il2CCTL l2CMTX 0 No Yes Set slave address and R W bit for l2CDR l2CCTL l2CMSTA lt 1 Yes No No Yes No Yes I2CSR I2CMCF 0 I2CSR I2CMIF lt 0 2 2 0 Read receive data from Il2CDR No I2CSR I2CMCF 0 I2CSR I2CMIF lt 0 Final byte 1 i 9 received No I2CCTL I2CTXAK lt 1 Read receive data from I2CDR eee No Yes Yes l2CSR I2CMCF 0 l2CSR I2CMIF 0 l2CCTL Il2CRSTA lt
172. cification 12 1 1 Features e The master function is supported Thecommunication speed can be set based on the system clock Only a 32 system clock is supported 32 byte buffer function is provided Whether or not to use the buffer mode can be selected 12 1 2 Configuration Figure 12 1 shows the configuration diagram of the Internal bus 2 0 module I2C1 module SCL SDA 2 0 interrupt signal I2C1 interrupt signal SCLO 4 SDAO SCL1 M SDA1 M Figure 12 1 Configuration Diagram 12 1 3 Listof Pins Table 12 11 List of Pins Interfaced with the Outside of LSI Pin name y o Initial Initial value Description status SDAO_M y o Serial data input output pin SCLO M O Serial data transfer clock SDA1 M Serial data input output pin PA1 SCL1 M Serial data transfer clock Note The initial statuses initial values of SDA1 M and SCL1 M are the values when the secondary functions of the corresponding pins selected Therefore they are different from the initial values of the LSI pins For details of switching to the secondary functions of the LSI pins see the description of port A mode setting register in Chapter 5 MCU Control Function ML630Q791 12 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 Description of Registers 12 2 1 List of Registers Table
173. cludes the self rewrite function that rewrites the content of the flash memory program memory space using a special function register SFR programmatically 16 1 1 Features The self rewrite function of the flash memory has the following features Supports the writing by word 32 bits Supports the erase by sector 128 words Guarantees 1000 rewritings Supports the software re mapping and the hardware re mapping function with the BRMP pin FEUL630Q791 16 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 Description of Registers 16 2 1 List of Registers 0x4000 0400 Flash ROMstatusregister FLCSTA R 32 0 0000 0000 0x4000 0420 Flash ROMsizeregister FlCRSZ R 32 oxooo2 0000 0x4000 0424 Boot program address register FLCBADR 32 0 0001 00 0x4000 046C Set count sector erase CE enable register FLCSCSCE R W 32 0x0002 1474 0x4000 0470 Set count program CE enable register FLCSCPCE R W 32 0x0000 04FB 0x4000 047C Set count sector erase WE enable register FLCSCSWE 0x0002 13AA R W 0x4000_0480 Set count program WE enable register FLCSCPWE 32 0x0000_0431 0x4000_0488 Set count program PROG2_1st disable register FLCSCPP21D R W 32 0x0000_0313 0x4000_048C 0x4000_0490 0x4000_0494 0x4000_0498 Set count program PROG2_3rd disable register FLCSCPP23D 3 0x0000_017B 0x4000_049C 0x4000_04A0 0x4000_04A8 Set count program
174. data bit parity bit stop bit This error will set the LSR 4 bit of the UARTLSR register In FIFO mode this is related to a specific character in the FIFO LSR 4 indicates that the break character is present at the beginning of the FIFO FEUL630Q791 13 22 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 7 Setting Example UART initial setting I O port setting et Fort A Select whether to enable or disable the FIFO mode UART control register setting Set the trigger level the FIFO mode Setthe UART line control register character length number of stop bits and parity 3 Set the bit 7 DivsorLatchAccessBit of the UART line control register to 1 Set DLL and DLM UART baud rate setting Clear the bit 7 DivisorLatchAccessBit of LinControlRegister to 0 UART transfer control setting Interrupt controller setting X Enables disables various interrupts Set SETENA 15 of the interrupt enable set register NVIC ISER to use interrupts UART initial setting completion FEUL630Q791 13 23 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 4 Specifying Port Registers To use the applicable bit of each related port register needs to be set See Chapter 15 GPIO for details about the port registers 13 4 1 Operating UART Set PA2 bit 9 8 of the PAMOD regi
175. de SDK Sensor Control Host IF Specification FEUL630Q791 11 21 LAPIS Semiconductor Co Ltd 11 2 18 HSTRG Error Code Register 1 ERROR1 Address Ox8B read Access R Access size 8 Bits Initial value 0x00 ML630Q791 User s Manual Chapter 11 Host Interface Bit 7 6 5 4 3 2 1 0 Symbol name ER1 7 ER1 6 ER1 5 ER1 4 ER1 3 ER1 2 ER1 1 ER1 0 Access R R R R R R R R Initial value 0 0 0 0 0 0 0 0 ERRORI is a read only register that shows the error code Writing is invalid Description of Bits ERI 7 0 bit 7 0 Sets the interrupt source of the error code to the host processor For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 22 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 19 HSTRG Interrupt Request Register 0 INTREQO Address 0 8 read Access R Access size 8 Bits Initial value 0x00 Bit 7 6 5 4 3 2 1 0 REQO REQO REQO REQO REQO REQO REQO REQO Symbolnamess Cm 6 5 4 3 2 1 0 Access R R R R R R R R Initial value 0 0 0 0 0 0 0 0 INTREQO is a read only register that shows the interrupt source Each value of this register is cleared by being read by the host processor Writing is invalid Description of Bits REQO 7 0 bit 7 0 Indicates the source of interrupt to the host processor The second
176. ding of uncertain data HSCLK during incremental counting read TMnC twice and check that the results match LSCLK External clock HSCLK Read disabled FEUL630Q791 8 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 8 Timer 8 2 5 Timer m Counter Register TMmC m 1 3 5 7 Address 0 4000 1414 0x4000 1814 TM3C 0 4000 1C14 TM5C 0x4000 2014 TM7C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T T T T T T T T T T T T T T Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 2 t TmC 7 0 Access RW R W R W RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing is a special function register SFR that functions as an 8 bit binary counter When a write operation is performed to TMmC TMmC is set to 0 0000 0000 The data that is written is meaningless In the 16 bit timer mode a write operation to either the TMnC or TM n 1 C register sets 0x0000 0000 to both of them n 0 2 4 6 In the 16 bit timer mode the counter value is read from TnC 15 0 of the timer n counter register n 0 2 4 6 During timer operation the TMmC content may not be read
177. e GPIO interrupt status register PIOIS from CPU the GPIO interrupt status register PIOIS is cleared to 0 and the interrupt is released at the same time If an interrupt source is generated at the same timing as the release of the interrupt from CPU the interrupt generation has priority Figure 15 6 shows an operation example ISn n A B msa y n A B 1 1 1 1 1 INTn 1 1 Period from edge interrupt assertion to internal interrupt generation Up to 2 cycles at 16 kHz During this period the status of GPIO pin must be held 2 Interrupt status clear Write 1 to the ISn bit 1 Internal interrupt signal Figure 15 6 Example of Both edge Rising Falling Interrupt Operation For Detection without Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 0100 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when a falling edge of the input signal of GPIO pin is detected Note that the assertion period of after the falling edge and that of after the rising edge must be one cycle of system clock longer The interrupt is generated after the pin is asserted or after three sysclk cycles FEUL630Q791 15 14 Chapter 16 Flash Programming LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 Flash Programming 16 1 General Description This LSI in
178. e interrupt request from the host processor exists or not ENT Description 0 Interrupt request from the host processor does not exist initial value 1 Interrupt request from the host processor exists FEUL630Q791 11 28 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 25 HSTRG Result Register n RSLTn n 00 to Address 0xCO to OxFF read Access R Access size 8 Bits Initial value 0x00 Bit 7 6 5 4 3 2 1 0 RSLTn RSLTn RSLTn RSLTn RSLTn RSLTn RSLTn RSLTn Symbol name 6 5 4 3 2 1 0 Access R R R R R R R R Initial value 0 0 0 0 0 0 0 0 RSLTn is a read only register that indicates the command processing result Writing is invalid Description of Bits RSLTn 7 0 bit 7 0 Indicates the result of command processing to the host processor For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 29 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 3 Serial Interface DC is selected during reset I2C or SPI three wire or four wire is set by the IFSEL and IFCFG bits of CPURG configuration register HIFCFG after the system reset is released 11 3 1 12C Interface I2C interface can be used for communication with the host processor by setting the IFSEL bit of GPURG configuration register to 1 The following shows I
179. e pins are left open in the high impedance input setting FEUL630Q791 1 8 Chapter 2 CPU LAPIS Semiconductor Co Ltd ML630Q791 User s Manual 2 2 1 Chapter 2 CPU CPU Overview A RISC processor manufactured by ARM It is a 32 bit processor for small size and low power consumption applications and has a 3 stage pipeline configuration It implements the ARMv6 M architecture and operates with 16 bit Thumb instructions and Thumb 2 instructions For details see Cortex MO Technical Reference Manual Cortex amp MO Devices Generic User Guide 2 1 1 Features Multiplier can process 32 bit x 32 bit in one cycle holding the lower 32 bits of the operation result Serial wire debug port Little Endian Built in debug component with four break points and two watch points Wakeup from any interrupt is possible WFI Wait for Interrupts supported WFE Wait for Events not supported SysTick not supported FEUL630Q791 23 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 2 CPU 2 2 Description of Registers 2 2 1 List of Registers ome ow SS 0 000 EDOO CPUID register CPUID R 32 0 410 C200 OxEO00 EDO4 lnterrupt control and state register ICSR 0x0000 0000 OxEO00 EDOC Application interrupt and reset control register AIRCR 0 05 0000 0 000 EDi4 Configuration and control register 7 CCR R 92 0 00000208 For details of the register see Cortex MO Devices Gen
180. ed Proper operation cannot be guaranteed if accessed FEUL630Q791 3 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 3 4 Memory Controller Function 3 4 1 List of Registers Address Initial value 0x4000 0010 Remapping control register SYSCON REMAP CON 0x0000 0000 0x4000 0014 Remapping base address register SYSCON REMAP BASE R W 0x1001_F000 FEUL630Q791 3 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 3 4 2 Remapping Control Register SYSCON REMAP CON Address 0 4000 0010 Access R W Access size 32 Bits Initial value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L LL Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REM Symbol name t i i s AP REMAPT S3 0 Access RAN RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write a 0 for write Description of Register This is a special function register SFR used to set remapping Description of Each Bit REMAP 3 0 bits 0 3 REMAP EN bit 4 REMAP EN REMAP 3 0 Description 0 Based on the BRMP pin that is set after the reset release the following area is remapped to Banko H The firmware update area of Flash ROM is remapped to Banko L The area of address 0 of Flash ROM is remapped to
181. ed to transfer at least 4 characters has elapsed since a character was last received if 2 stop bits are specified the time after the first stop bit is calculated e An amount of time required to transfer at least 4 characters has elapsed since the receive FIFO was last read For example if 1 start bit 8 character bits 1 parity bit 2 stop bits is specified and the transfer speed is 300 baud the said amount of time will be approximately 160 ms B The clock used to calculate the character time is CCLK C When a character is read out from the FIFO the Character Timeout interrupt and timer used for timeout detection will be cleared D When no Character Timeout interrupt is generated the timeout detection timer will be cleared when a character is read out from the FIFO or a new character is received The transmission interrupt is generated as follows when the transmit FIFO interrupts have been enabled A The Transmitter Holding Register Empty interrupt is generated when the transmit FIFO is empty This interrupt is cleared when a character is written to the transmit FIFO or when UARTIIR is read out B When the following conditions are met the Transmitter Holding Register Empty interrupt will be delayed for an amount of time equivalent to time required to transmit one character time when last stop bit occurred e There was a point in time where only one character was present in the FIFO after the THRE Transmitter Holding Registe
182. egister FLCADR is a special function register SFR to set Flash ROM rewrite addresses Description of Bits FA 16 2 bit 16 2 FA 16 2 is a bit used to set the address for sector erase and 1 word write When you write the byte address of the flash memory area in this register the address of the Flash ROM is set in FA 16 2 Note You cannot rewrite this register while BUSY bit of FLCSTA register is 1 In addition it is prohibition that you use sector erase or 1 word write by setting this register to 0 0001 FE last sector address FEUL630Q791 16 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 5 Flash ROM Write Data Register FLCWDA Address 0 4000 040C Access W Access size 32 Bits Initial Value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name FD 31 16 Access W W W W W W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Symbol name FD 1 5 0 Access W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note The read data of this register is Description of Register FLCWDA is a special function register SFR to set Flash ROM rewrite data Description of Bits FD 31 0 bit 31 0 FD 31 0 is a bit used to set write data for 1 word wr
183. emiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 2 Data Reception Figure 13 4 shows the data reception timing Figure 13 5 shows the reception timing when the first byte in the receive FIFO is read out and Figure 13 6 shows the reception timing when the remaining bytes in the receive FIFO are read out The sampling clock is obtained by dividing the baud rate clock by 1 8 First when the start bit is detected from RXDO subsequent data is obtained and transferred to the receive shift register The data in the receive shift register is passed to the receive FIFO to be transferred to the UARTRBR register When the data reaches the UARTRBR register LSRO bit of the UARTLSR register is set to 1 to indicate that valid data is present in the UARTRBR register This bit will be cleared by reading out the UARTRBR register data 8 Clock Baud rate Clock Rf AD Sample CLK N Figure 13 3 Relation between the Baud Rate Clock and Sample Clock RXDO Start Data bit 5 8 Stop Sample CLK h fl f h f nUARTINT Received Data Available nUARTINT Received Line Status RD LSR read RBR read tSINT MAX 1000ns tRINT MAX 1 Baud rate Clock Figure 13 4 Reception Timing FEUL630Q791 13 17 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART RXDO Start Data bit 5 8 Stop Sample CLK y S Trigger Level nUARTINT Received Data Av
184. er m Counter Register TMmC m 1 3 5 Thae ein ise 8 7 8 2 6 Timer n Control Register 0 TMnCONO m 1 3 5 7 nennen entente nnne en nnne enne 8 8 8 2 7 Timer m Control Register 0 TMmCONO 1 3 5 3 8 9 FEUL630Q791 i LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Table of Contents 8 2 8 Timer n Control Register 1 TMnCONI n 0 2 4 6 8 10 8 2 9 Timer m Control Register 1 TMmCONI m 1 3 5 7 sse enne eene nnne en nnne enn 8 11 8 3 Description of Operation ete Rer eet e e tene aeri ertt 8 12 8 3 1 Timer Mode Operation out eese recette re ial quien 8 12 8 4 Specifying Port Registers soie Idee o epe Me eR tenses Rer een esi Pace 8 13 8 4 1 Operating Timer with External Clock nennen trennen nenne 8 13 Chapter 9 n C M 9 1 921 Gebet fete eal eee 9 1 D MET Feature Sonis anio EH 9 1 DAD CONT PUPA HE EH 9 1 9 1 5 EIS OE see merce ete pde ie betreten 9 2 9 2 Description of Reglsters osse uo tont de toe teet teil 9 2 9 2 Last OE Repistets zio ER RR D RR RU UE pp
185. er s Manual Chapter 14 Arithmetic Circuit 14 2 4 Operation Input Register AH CALAH Address 0 4004 500 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name CALA 63 48 Access RAN RAN RAW RW RAW RAV RW RAW RW RAN R W RAW RAW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALA 47 32 Access R W R W R W R W R W R W RW R W R W R W R W R W R W R W RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALAH is a special function register SFR used to store input data for the operation CALAH register sets the higher 32 bits of the dividend for division or the higher 16 bits for root operation For details see 14 3 Description of Operation FEUL630Q791 14 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 14 Arithmetic Circuit 14 2 5 Operation Input Register BL CALBL Address 0 4004 5010 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name CALB 31 16 Access RAN RAN RAW RW RAW RW RW RW R W RAN R W RAW RAW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALB 15 0 Access R W R W R W R W R W R W RW R W R W R W RW R W R W R W RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALBL is
186. eration to prevent an improper rewrite to Flash ROM Writing of 0 0000 00FA and 0x0000 00 5 to the Flash ROM acceptor register FLCACP in this order enables sector erase or 1 word write only once Note Software reset during Flash ROM erase write is prohibited A program that executes Flash ROM erase write should not be placed on Flash ROM The last sector is the test code area Erase Program operation is prohibited 16 3 2 Counter Setting Set the timing of the control signal to Flash ROM in the set count register according to the clock cycle when executing sector erase or 1 word write The initial value supports the clock cycle of 32MHz The setting values of the set count registers are shown in Table 16 1 Table 16 1 Setting Values of Set Count Registers for Clock Cycles FEUL630Q791 Setting value of the set count Register name register by clock cycle FLCSCSCE 0x0002 1474 FLCSCPCE 0x0000 04FB FLCSCSWE 0x0002 13AA FLCSCPWE 0x0000 0431 FLCSCPP21E 0x0000_03DD FLCSCPP21D 0x0000_0313 FLCSCPP22E 0x0000_0311 FLCSCPP22D 0x0000_0247 FLCSCPP23E 0x0000_0245 FLCSCPP23D 0x0000_017B FLCSCPP24E 0x0000_0179 FLCSCPP24D 0x0000 00AF FLCSCPB1E 0x0000 0312 FLCSCPB2E 0x0000 0246 FLCSCPBSE 0x0000 017A FLCSCEWED 0x0000 06AA FLCSCPWED 0x0000 00AE FLCSCCED 0x0000 0006 FLCSCEND 0x0000 0001 16 30 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming
187. eric User Guide FEUL630Q791 2 2 Chapter 3 Memory Space LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 3 Memory Space 3 1 Overview In ML630Q791 various memories and registers are located in a 4 GB memory space which is partitioned into 32 banks of 128 MB each 3 2 Memory Map Figure 3 1 shows the memory map of ML630Q791 Bank 4GB Address Memory space 31 OxF800 0000 30 OxF000 0000 29 OxE800 0000 28 0 000 0000 Cortex MO Peripherals See Figure 3 1 2 27 0 0800 0000 26 0 0000 0000 25 0xC800 0000 24 3GB 0xC000 0000 23 0xB800 0000 22 0 000 0000 21 0xA800 0000 20 0 000 0000 19 0x9800 0000 18 0x9000 0000 17 0x8800 0000 16 2GB 0x8000 0000 15 0x7800 0000 14 0x7000 0000 13 0 6800_0000 12 0 6000_0000 11 0 5800_0000 10 0 5000_0000 9 0 4800_0000 8 1 0 4000_0000 APB I O See Figure 3 1 3 7 0x3800_0000 6 0x3000_0000 5 0x2800_0000 4 0x2000_0000 Work RAM 16 KB 3 0x1800_0000 2 0x1000_0000 Internal Flash ROM 128 KB 1 0x0800_0000 0 OGB 0x0000 0000 Remappable space Reserved area 1 Accessing any of reserved areas is prohibited Proper operation cannot be guaranteed if accessed Figure 3 1 1 ML630Q791 Memory FEUL630Q791 3 1 LAPIS Semiconductor Co Ltd ML630Q791
188. errupt for the host processor is output to notify that this LSI is in the abnormal state When this LSI in the abnormal state only the value OxFF can be read from the HSTRG interrupt request registers 0 and 1 0x8C and Ox8D The host processor determines whether this LSI is in an abnormal state or not through the values of HSTRG interrupt request registers 0 and 1 0x8C and 0 8 If determined as an abnormal state please perform the hardware reset 11 4 8 Clock Requirements The system clock should be operated at 32 2 to use the host IF properly FEUL630Q791 11 41 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 5 Specifying Port Registers When using the SPI interface of the host interface or interrupt INTO S or S related port register bits need to be set See Chapter 15 GPIO for details about the port registers 11 5 1 When Using SPI Interface Three wire Set PA4 bit 17 16 of the PAMOD register to 01 to select the secondary function 5 5 S of PA4 Register PAMOD register address 0x4000 0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Symbol PAS3 2 E E PA1 name Setting value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Symbol PA6 5 gt Setting value
189. es No I2CBUFSTA I2CBMNA 1 Yes No I2CBUFSTA I2CBMAL 1 Yes No No Yes I2CBUFSTA I2CBMFI 0 Transmit data No Read receive data from I2CDR Set number of transferred bytes read write and sub address data length Check Bus IDLE gt Create start condition gt Check transfer data count is 0 gt Check transmit data count mismatch Check illegal stop condition 3 Check time out Create start condition Transmitting slave address 3 Check ACK NACK Transferring data 3 Check arbitration lost OC C gt Wait transfer completion 3 Clear transfer completion interrupt flag Send stop condition Clear I2CBUFCTL I2CBMSTA automatically To Bus IDLE END ML630Q791 12 33 LAPIS Semiconductor Co Ltd I2CBUFSTA I2CBMDZ 0 Error END I2CBUFSTA I2CBMAG 0 Error END I2CBUFSTA I2CBMIS lt 0 Error END I2CBUFSTA I2CBMTO lt 0 Error END I2CBUFSTA I2CBMNA lt 0 Error END I2CBUFSTA I2CBMAL 0 Error END ML630Q791 gt Buffer mode error end gt 7 gt Butter mode error end gt Clear illegal stop condition interrupt flag Buffer mode error end gt Clear time out interrupt flag Buffer mode error end gt Clear NACK interrupt flag Buffer mode error end gt Clear arbitration lost interrupt flag 7 gt Butter mode error
190. escription of Bits CMDI 0 bit 15 0 Indicates the command from the host processor For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification ENT bits 16 Indicates whether the interrupt request from the host processor exists or not For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification When the host processor sets this bit to 1 the CPU is notified of the interrupt and this bit is updated When the host processor sets to this bit the interrupt is not notified to the CPU The value that has been set to this bit is cleared when the CPU writes 1 ENT Description 0 Interrupt request from the host processor does not exist initial value 1 Interrupt request from the host processor exists FEUL630Q791 11 15 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 12 CPURG Result Register n HIFRLTn n 00 to Address 0 4005 0040 to 0 4005 007F Access R W Access size 8 16 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSLTOS T7 0 RSLTO2 7 0 Access RAN RAV R W R W R W RW RAN RAW R W RAW R W RAN RAN RAN RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Symbol name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name RSLT01 7 0 RSLTOO 7 0 Access RW RAN R W RW R W RAN RAN R W RAW R W R W RAV R W RAW RW Initial value 0 0 0 0 0 0 0 0
191. eserved area 1 Accessing any of reserved areas is prohibited Proper operation cannot be guaranteed if accessed 2 During individual block stop state write data is ignored and read data is undefined For details of individual block stop state see Chapter 5 Figure 3 1 3 APB I O Area Memory FEUL630Q791 3 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 3 Memory Space 3 3 Internal Memory 3 3 1 Internal Flash ROM Table 3 1 shows the address range of the Flash ROM of Bank2 Table 3 1 Address Range of Bank2 Memory Address range Internal Flash ROM 128 KB 0x1000 0000 to 0 1001 FFFF 1 Accessing an address out of this address range in the same bank is prohibited Proper operation cannot be guaranteed if accessed Address Range of 0x1001FE00 to 0x1001FFFF are the test data area Erase Program operation is prohibited The address holds the 28 bit product ID and 4 bit revision Address 0 1001 FFFC Access R Access size 32 Bits Initial value 0x0630 7910 Description of Bits e Bit 3 0 Represent the revision of this LSI e Bit 31 4 There bits represent the product ID of this LSI ML630Q791 0 0630791 3 3 2 Work RAM Table 3 2 shows the address range of the work RAM of Bank4 Table 3 2 Bank4 Address Range Address range Work RAM 16 KB 0x2000 0000 to 0x2000_3FFF 1 Accessing an address out of this address range in the same bank is prohibit
192. et i e rtc RS 16 1 16 2 Description of Registers eost oe eto tee 16 2 16 21 List OF tede t RR DR Uum RR Gi tute T A E e ieu 16 2 16 2 2 Flash ROM Status Register 22 2 1 1 0 bone da see enne rentre irte etna 16 3 16 2 3 Flash ROM Acceptor 16 4 16 2 4 Flash ROM Address Register _ 16 5 16 2 5 Flash ROM Write Data Register 16 6 16 2 6 Flash ROM Erase Register FLCERA renneri erii eE E E TE enne nennen en nnne E nnne entren nente en 16 7 16 27 Flash ROM Size 2 ripeto repe gebe 16 8 16 2 8 Boot Program Address Register FLCBADR essere nennen trennen trennen enne 16 9 16 2 9 Set Count Acceptor Register FLCSCACP sesiis er eene 16 10 16 2 10 Set Count Sector Erase CE Enable Register 5 2 0 22020 0 0 01 16 11 16 2 11 Set Count Program CE Enable Register 16 12 16 2 12 Set Count Sector Erase WE Enable Register 16 13 16 2 13 Set Count
193. et the value to start enabling the write signal of the erase program counter at the time of selector erase of Flash ROM Description of Bits e FSCSWE 23 0 bit 23 0 For FSCSWE 23 0 the write signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of selector erase of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 13 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 13 Set Count Program WE Enable Register FLCSCPWE Address 0 4000 0480 Access R W Access size 32 Bits Initial Value 0x0000 0431 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbolname 900 0000 00 so uso FSCPWE 23 16 Access z D 11007007 Ww RW RW RW RW RW RW RW liiavaue 0 0 0 0 O0 0 0 0 Bit 1B 144 13 12 1 10 9 7 6 5 4 2 14 0 Symbol name FSCPWE 15 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPWE is a special function register SFR used to set the value to start enabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCBWE 23 0 bit 23 0 For FSCPWE 23 0 the write signal to Flash ROM is enabled when the erase pro
194. etting x x x x x x x x value Bit not related to the UART function Note The PIOCON register does not need to be set When the secondary function is selected the setting is automatically changed but the value of the PIOCON register does not change FEUL630Q791 13 24 Chapter 14 Arithmetic Circuit LAPIS Semiconductor Co Ltd ML630Q791 User s Manual 14 Arithmetic Circuit 14 1 Overview Chapter 14 Arithmetic Circuit This LSI includes an arithmetic circuit that implements the root operation and division functions 14 1 1 Features Root operation SQRT integer 48 bits integer 24 bits decimal 23 bits operation time 48 cycles e Division unsigned 64 bits 48 bits operation time 64 cycles 14 1 2 Configuration Figure 14 1 shows the configuration of the arithmetic circuit Data bus CALSTS CALAL CALAH CALBL CALBH CALROL CALROH CALR1L CALR1H FEUL630Q791 CALINT Finite State Machine Calculation p o CALAL CALAH CALROL CALROH ALST CALBL CALBH CALR1L CALR1H Operation status register Operation input register A Operation input register B Calculation result register 0 Calculation result register 1 Figure 14 1 Configuration of Arithmetic Circuit 14 1 LAPIS Semiconductor Co Ltd ML630Q791 User
195. ffers between the external reset by the RESET pin and the software reset by SYSRESETREQ The timing diagrams are shown below External reset by the RESET N pin RESET N Max 2 3ms lt gt RESET Software reset by SYSRESETREQ SYSRESETREQ RESET Max 0 2ms FEUL630Q791 4 3 Chapter 5 MCU Control Function LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 MCU Control Function 5 1 Overview This LSI includes power management pin switching control and other functions Operation of this LSI is categorized into the following three statuses 1 System reset mode 2 Program run mode 3 Sleep mode This LSI can operate with a lower current consumption by powering down the unused function blocks reset registers and stop clock supplies 5 1 1 Features Retains the revision of this LSI Uses block control function to power down the circuits of unused function blocks reset registers and stop clock supplies Controls switching of pin functions switching to the secondary or tertiary function Supports the sleep mode by the WFI instruction of Cortex M0 Supports the low power mode selection by using SLEEPDEEP bit For details of WFI instruction and SLEEPDEEP bit see Cortex MO Devices Generic User Guide FEUL630Q791 5 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 2 Description of Registers 5 2 1
196. g edge the PWMO status flag POSTAT is in a 1 state of the next PWM clock pulse Therefore the PWMO interrupt PWOINT may occur FEUL630Q791 9 9 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 4 Port Register Settings To output the PWM waveform the applicable bit of each related port register needs to be set See Chapter 15 GPIO for details about the port registers 9 4 1 Functioning PAO Pin PWMO as PWM Output Set bit 1 and 0 of the PAMOD register to 10 to select the tertiary function of Register PAMOD register address 0x4000 0260 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 Setting x x x x x 1 0 value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting x x x x x x x x value Set the bit 0 of the PIODIR register to 0 to set the input output mode of PAO to output Register PIODIR register address 0x4000 A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 PIODIR 6 0 name Setting k k 0 value
197. gister 0 TM1CONO R W 32 0x0000_0000 0x4000_141C Timer 1 control register 1 TM1CON1 R W 32 0x0000_0000 0x4000_ 1800 Timer 2 data register TM2D R W 32 0x0000 0x4000 1804 Timer 2 counter register TM2C R W 32 0x0000_0000 0x4000_1808 Timer 2 control register 0 TM2CONO R W 32 0x0000_0000 0x4000_180C Timer 2 control register 1 TM2CON1 R W 32 0x0000_0000 0x4000_1810 Timer 3 data register TM3D R W 32 0x0000_00FF 0x4000_1814 Timer 3 counter register R W 32 0x0000_0000 0x4000_1818 Timer 3 control register 0 R W 32 0x0000_0000 0x4000_181C Timer 3 control register 1 1 R W 32 0x0000_0000 0x4000_1C00 Timer 4 data register TM4D R W 32 0 0000 0 4000 1 04 Timer 4 counter register TM4C R W 32 0x0000_0000 0x4000_1C08 Timer 4 control register 0 TM4CONO R W 32 0x0000_0000 0x4000 1COC Timer 4 control register 1 TM4CON1 R W 32 0x0000_0000 0x4000_1C10 Timer 5 data register TM5D R W 32 0x0000_00FF 0x4000_1C14 Timer 5 counter register TM5C R W 32 0x0000_0000 0x4000_1C18 Timer 5 control register 0 TM5CONO R W 32 0x0000_0000 0x4000_1C1C Timer 5 control register 1 TM5CON1 R W 32 0x0000_0000 0x4000_2000 Timer 6 data register TM6D R W 32 0 0000 0 4000 2004 Timer 6 counter register TM6C R W 32 0x0000_0000 0x4000 2008 Timer 6 control register 0 TM6CONO R W 32 0x0000_0000 0x4000 200C Timer 6 control register 1 TM6CON1 R W 32 0x0000_0000 0x4000_2010 Timer 7 data register TM7D R W 32 0x0000_00FF 0x4
198. gram counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 14 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 14 Set Count Program PROG2 1st Enable Register FLCSCPP21E Address 0 4000 0484 Access R W Access size 32 Bits Initial Value 0x0000 03DD Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name FSCPP21E 23 16 Access RAN RAN RAN RW RW RAN RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSCPP 1 E 15 0 Access RW RW RW RW RW RW RW RAW RW RAW RAW RW RW RAW RW RW Initial value 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP721E is a special function register SFR used to set the value to start enabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits FSCPP21E 23 0 bit 23 0 For FSCPP21E 23 0 the write signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 15 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming
199. he value to start enabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits FSCPP23E 23 0 bit 23 0 For FSCPP23E 23 0 the write signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 19 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 19 Set Count Program PROG2 3rd Disable Register FLCSCPP23D Address 0x4000 0498 Access R W Access size 32 Bits Initial Value 0x0000 017B Bit 31 30 29 28 27 2 2 24 23 22 21 20 19 18 17 16 Symbol name FSCPP22D 23 16 Access RW RW RW RW RW RW RW Initialvalue 0 0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 14 0 Symbol name FSCPP22D 15 0 Access RW RAW RW RAN RAW RW RW RAN RW RAN RW RAN RAN RW RAN RAW Initial value 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 1 Note Reserved bit for future extension is read when reading Description of Register FLCSCPP23D is a special function register SFR used to set the value to start disabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCPP23DJ 23 0 bit 23 0 For FSCPP23D 23 0 the write signal to Flash ROM is disabled when the erase program counter v
200. iconductor Co Ltd ML630Q791 User s Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics e Absolute Maximum Ratings GND 0V Parameter Symbol Condition Rating Unit Power supply voltage Ep 2 Digital 1 0 Voo Ta 25 C 0 3 to 4 6 V Power supply voltage 7 Digital CORE 25 0 3 to 1 8 Input voltage ViN Ta 25 C 0 3 to 4 6 V Output voltage Vour 25 0 3 to 4 6 V Output current lour 25 10 to 10 mA Power dissipation PD Ta 25 C 0 8 W Storage temperature Tsra 55 to 150 C Recommended Operating Conditions GND 0V Parameter Symbol Condition Range Unit Ambient temperature Ta 40 to 85 C Power supply voltage Vpp 1 7 to 1 9 V Input voltage IND SARUM 9 Vint 1 0 to 3 6 V Input clock frequency 32 768 1 kHz VDDL pin external C _ 2 24509 F capacitance 1 SCL S SDA S SDAO M 5 0 M PAO 1 using as bus interface eOperating Conditions of Flash Memory GND 0V Parameter Symbol Condition Range Unit Ambient temperature Ta 40 to 85 C Power supply voltage Vpp 1 7 to 1 9 V Rewrite count 1000 times Data retention Ypn 10 years FEUL630Q791 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix C Electrical Characteristics eDC Characteristics 1 2 1 7 to 1 9V Ta 40 to 85
201. igh impedance input mode input mode with a pull down resistor or input mode with a pull up resistor At a system reset high impedance output mode is selected as the initial status In the CMOS output mode L or H level is output to each pin of Port A depending on the value set by the GPIO data register PIODAT In input mode the input level of each pin of Port A is read from the GPIO data register PIODAT 15 3 2 Interrupt Setting Procedure Use the following procedure to set interruption OWrite 0 to the corresponding bit of the GPIO interrupt enable register PIOIE to disable interrupts Set the corresponding bit of the GPIO port direction register PIODIR to 1 input GSet the interrupt mode to the corresponding bit of the GPIO interrupt mode register PIOIM Write 1 to the corresponding bit of the GPIO interrupt status register PIOIS to clear the interrupt status GWirite 1 to the corresponding bit of the GPIO interrupt enable register PIOIE to enable interrupts After the above settings are made the interrupt is enabled for the corresponding bit For the interrupt generation operation see Chapter 15 3 3 Various Interrupt Operations 15 3 3 Various Interrupt Operations Interrupt processing can be set independently for each bit of each port pin For an applicable bit the interrupt can be enabled by setting the GPIO port direction PIODIR to 1 and the GPIO interrupt enable register
202. ignal of the erase program counter at the time of erase of Flash ROM Description of Bits e FSCEWED 23 0 bit 23 0 For FSCEWED 23 0 the write signal to Flash ROM is disabled when the erase program counter value matches with the bit value at the time of erase of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 26 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 26 Set Count Program WE Disable Register FLCSCPWED Address 0x4000 04B8 Access R W Access size 32 Bits Initial Value 0 0000 00AE Bit 31 30 29 28 27 2 25 24 23 22 21 20 19 18 17 16 Symbol name 2 2 FSCPWED 23 16 Access ROR RW RW RW RW RW RW liiavdue 0 0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSCPWED 1 5 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCPWED is a special function register SFR used to set the value to start disabling the write signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCPWED 23 0 bit 23 0 For FSCPWED 23 0 the write signal to Flash ROM is disabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM Fo
203. imer 8 2 Description of Registers 8 2 1 List of Registers bits 1 FEUL630Q791 8 3 LAPIS Semiconductor Co Ltd 8 2 2 Timer n Data Register TMnD n O 2 4 6 Address 0 4000 1400 TMOD 0x4000 1800 TM2D 0 4000 1C00 TM4D 0 4000 2000 TM6D Access R W Access size 32 Bits Initial value 0 0000 00FF ML630Q791 User s Manual Chapter 8 Timer Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name TnD 15 8 TnD 7 0 Access RAN RAV R W RAW RW RW RAN RAN RW RAW RW Initial value 0 0 0 0 0 0 0 0 1 1 1 Note Reserved bit for future expansion 0 is read when reading Write when writing TMnD is a special function register SFR to set the value to be compared with the value RAN RAW RAW RW RW 1 1 1 1 1 timer n counter register TMnC TnD 15 8 can be accessed only when the 16 bit timer mode is set The initial values of TnD 15 8 OxFF in the 16 bit timer mode Note Set TMnD when the timer n stops When TnSTAT of TMnCONI register is 0 Writing 0x0000 0000 to TMnD works in the same way as 0x0000 0001 FEUL630Q791 8 4 LAPIS Semiconductor Co Ltd 8 2 3 Timer m Data Register TMmD m 1 3 5 7 Address 0 4000 1410 TMID 0 4000 1810 TM3D 0 4000 1C1
204. imer operation Low speed clock oscillation starts Occurrence of abnormality RESET S 4 WDTMOD System reset 4 setting Data id OxAB Ox5A 5 LI WDTCON Write WDP Internal pointer Overflow WDT counter K Ty WDTINT Occurrence of VO Notify the host interface WDT interrupt l WDTINT of an abnormal state Twov Twov Overflow period Overflow period Figure 10 2 Example of Watchdog Timer Operation When the system reset is released and the low speed clock LSCLK is output the WDT counter starts incremental counting overflow period of WDT counter Twoy is set to WDTMOD 5 is written to WDTCON Internal pointer 0 to 1 OxAS is written to WDTCON and the WDT counter is cleared Internal pointer 1 to 0 G 0x5A is written to WDTCON Internal pointer 0 to 1 When Ox5A is written to WDTCON after the occurrence of abnormality it cannot be accepted as the internal pointer is set to 1 Internal pointer 1 to 0 Although 0xA5 is written to WDTCON the WDT counter is not cleared since the internal pointer is 0 and the writing of 0x5A is not accepted in Internal pointer 0 to 1 WDT counter overflows and a watchdog timer interrupt request WDTINT is generated At this point the WDT counter and internal pointer are initialized for the half of
205. ing on the INTLVL bit of configuration register HSTRG CFG When INTLVLZ1 level output an interrupt signal is output to the host processor if the either bit is set to 1 and the sensor interrupt mask 0 1 HSTRG INTMSKO0 1 of that bit allows it Then after the host processor reads and clears all the interrupt sources the interrupt signal to the host processor will also be cleared When INTLVL 0 pulse output an interrupt of one cycle is output to the host processor at the next cycle if 1 is set to the 0 cleared bit and the sensor interrupt mask 0 1 HSTRG INTMSKO 1 of that bit allows it Setting 1 to a bit that has been set to 1 does not cause an interrupt However if a WDT overflow signal is input if the WDTP of WDT is not cleared and WDT overflow occurs 0x0000 FFFF is read until the hardware reset is performed Description of Bits REQI 0 bit 15 0 Sets the interrupt source to the host processor For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification CPU can write only 1 to this register Writing 0 is ignored Only read access from the host can clear this register to 0 If CPU writes 1 to any bit with REQ1 or REQO bit set to 1 an interrupt pulse is output at the time of writing when INTLVL O pulse output The interrupt level is held when INTLVL 1 level output The timing of clearing 1 0 depends on the INTIEN bit setting of the configuration register
206. interface Pin name Description Polarity SDAO M SDA of 2 0 master interface SCLO_M SCL of I2C0 master interface SDA1_M IO SDA of I2C1 master interface SCL1_M O SCL of I2C1 master interface 3 6V tolerant FEUL630Q791 1 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 1 Overview UART Pin name Description Polarity RXDO UART received data TXDO O UART transmitted data PWM Pin name Description Polarity PWMO IO Output PWM interface Input PWM and timer clock input GPIO Pin name Description Polarity PAO to PA6 IO GPIO External interrupt function available TEST Pin name Description Polarity VPP FLASH test pin FEUL630Q791 1 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 1 Overview 1 4 2 Handling of Unused Pins Table 1 1 shows methods of terminating the unused pins Table 1 1 Termination of Unused Pins Pin Recommended pin handling VPP Open BRMP Open SWC Connect a pull up resistor Recommended SWD Connect a pull up resistor Recommended SCL_S Connect a pull down resistor SDA_S Connect a pull down resistor PAO to PA6 Open Note SDAO M SCLO M Connect a pull up resistor Note It is recommended to set the unused input ports and input output ports to the input mode with pull down pull up resistor or the output mode since the supply current may become excessively large if th
207. is disabled when FSEL 1 Description of Bits FIFORP bit 8 0 The pointer to specify the address to read from the FIFO For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 13 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 10 CPURG Parameter Register HIFPRMF HIFPRMB HIFPRM7 HIFPRM3 Address 0x4005 0020 to 0x4005 002C Access R Access size 32 Bits Initial value 0x0000 0000 Bit Symbol name Access Initial value Bit Symbol name Access Initial value Note 30 29 28 27 26 25 24 23 22 21 20 19 18 17 416 PRMC 7 0 PRMD 7 0 R R R R R R R R R R R o 0 0 0 0 0 0 0 o 0 0 0 0 0 0 1514 13 12 1 10 9 7 6 5 4 3 2 1 0 PRME 7 0 PRMF 7 0 R R R R R R R R R R 0 0 0 0 o 0 0 0 0 0 0 0 0 Reserved bit for future expansion 0 is read when reading Write when writing Description of Register Parameter register IFPRMF HIFPRMB HIFPRM7 HIFPRM3 is a special function register SFR which indicates the command parameter When the host processor sets a parameter to the register for host access HSTRG PRMn 0 to 9 A to F the parameter of this register is updated Writing to this register from the CPU is disabled Description of Bits PRMC PRMD PRME PRMF 31 0 Indicates the command parameter from the host processor For detai
208. ister address 0x4000_A004 name Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 5 5 2 E 5 PIODIR 6 0 name Setting x x x n n n n n n n n x x x x 1 value Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol gt E gt 5 name Setting x x x value Bit not related to the PWM function Input the operation clock for the PWMO from the PAO pin Note The PIOCON register does not need to be set When the tertiary function is selected the setting is automatically changed to the high impedance input but the value of PIOCON register does not change FEUL630Q791 9 11 Chapter 10 Watchdog Timer LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 10 Watchdog Timer 10 Watchdog Timer 10 1 Overview This LSI includes a watchdog timer WDT which operates in system reset mode unconditionally free run operation in order to detect an undefined state of the MCU If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period the watchdog timer requests a WDT interrupt non maskable interrupt If the second overflow occurs it is determined as an abnormal state If an abnormal state is detected the host interface is notified of it The host CPU should reset this LSI when it receives the abnormal state See Cha
209. ister 0x0000_03DD 0x0000_0313 0x0000_0311 0x0000_0247 0x0000_0245 0x0000_017B 0x0000_0179 0x0000 00AF 0x0000 0312 0x0000 0246 0x0000 017A 0x0000 06AA 0x0000 00AE 0x0000 0006 0x0000 0001 0x0000 OOFF 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 OOFF 0x0000 0000 Set count program 2 1st disable register Set count program PROG2 2nd enable register Set count program PROG2 2nd disable register Set count program PROG2 3rd enable register Set count program PROG2 3rd disable register Set count program 2 4th enable register Set count program 2 Ath disable register Set count program BYTE1 enable register Set count program BYTE2 enable register Set count program BYTES enable register Set count erase WE disable register Set count program WE disable register Set count CE disable register Set count termination register Timer 0 data register Timer 0 counter register Timer 0 control register 0 Timer 0 control register 1 Timer 1 data register Timer 1 counter register FEUL630Q791 A 1 LAPIS Semiconductor Co Ltd Address Name Symbol R W ML630Q791 User s Manual Appendix A Registers Size bits Initial value 0x4000 1418 Timer 1 control re
210. ister that masks the interrupt signal to the host processor that corresponds to the interrupt source It can be read written from the host processor Description of Bits INTMSK0 7 0 bit 7 0 Masks interrupt sources due to the interrupt request register INTMSKO n Description 0 Does not mask the interrupt source due to the HSTRG INTREQO REQO n bit 1 Masks the interrupt source due to the HSTRG INTREQO REQO n bit initial value n 0 to 7 For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 18 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 15 HSTRG Interrupt Mask Register 1 INTMSK1 Address 0x03 write 0x83 read Access R W Access size 8 Bits Initial Value Bit 7 6 5 4 3 2 1 0 INT INT INT INT INT INT INT INT Symbol name MSK1 6 MSK1 5 MSK1 4 MSK1 3 MSK1 2 MSK1 1 MSK1 0 Access R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 INTMSKI is a register that masks the interrupt signal to the host processor that corresponds to the interrupt source It can be read written from the host processor Description of Bits INTMSKI1 7 0 bit 7 0 Masks interrupt sources due to the interrupt request register INTMSK1 n Description 0 Does not mask the interrupt source due to the HSTRG INTREQ1 REG n bit 1 Masks the
211. it for future expansion 0 is read when reading Write O when writing Description of Register Enables disables interrupts However if a bit is set to the output mode by the PIOPMn register the bit does not become an interrupt source regardless of the value of the PIOIE register Description of Bits PIOIE 6 0 bits 6 0 PIOIE n Description 0 Disables PAn pin interrupt 1 Enables PAn pin interrupt 0 6 The pin state is notified to GPIO even when the secondary function is selected for the pin as an external pin of LSI the GPIO function is not selected If the IE bit of a pin set to use the secondary function is set to 1 an interrupt from GPIO is notified to CPU according to the state of the pin as the secondary function When the secondary function is used and the interrupt processing from GPIO is not required set the applicable IE bit to 0 FEUL630Q791 15 6 ML630Q791 User s Manual Chapter 15 GPIO LAPIS Semiconductor Co Ltd 15 2 6 GPIO Interrupt Mode Register PIOIM Address 0x4000 A014 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T T Symbol name PIOIMS 3 0 PIOIMS 3 0 PIOIMA 3 0 Access RW RAW RAN RW RW RW RAW RW RAW RAN RAW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
212. ite Write to FD 31 0 starts the 1 word write Note Clear the contents of the target write addresses in advance The content of an overwritten address is not guaranteed You cannot rewrite this register while BUSY bit of FLCSTA register is 1 After high speed clock is selected as the system clock you can rewrite Flash ROM data Rewriting Flash ROM data while low speed clock is selected as the system clock cannot be guaranteed For details of clock selection see Chapter 6 Clock FEUL630Q791 16 6 LAPIS Semiconductor Co Ltd 16 2 6 Flash ROM Erase Register FLCERA Address 0 4000 0410 Access R W Access size 32 Bits Initial Value 0x0000 0000 ML630Q791 User s Manual Chapter 16 Flash Programming Bit 31 30 22 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name _ _ _ _ _ _ _ i _ _ _ t Access gt x y z s s Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbolname SECRETA zi si T Stee F FLE 1 0 Access RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future extension is read when reading Write 0 when writing Description of Register FLCERA is a special function register SFR used to start sector erase of Flash ROM Description of Bits FLE 1 0 bit 1 0 FLE is a bit used to specify the type and start of era
213. lave address transmission gt Check arbitration lost gt Start Condition Wait for slave address transmission completion 3 Check ACK NACK gt Clear data transfer completion flag gt Set transmit data to start next 1 byte transmission Wait for data transfer completion 3 Check ACK NACK gt Clear data transfer completion flag Clear interrupt flag gt Create repeated start condition Set master receive mode gt Check arbitration lost gt Repeated start condition Wait for slave address transmission completion gt Check ACK NACK Create start condition Transmitting slave Waiting for transmitting next data Transmitting 1 byte Waiting for transmitting next data SCL L Waiting for Repeated Start Condition transmission Waiting for Slave Address transmission Create repeated start condition Transmitting slave address Waiting for receiving next data SCL L 12 29 LAPIS Semiconductor Co Ltd I2CSR I2CMCF 0 l2CSR I2CMIF 0 2 2 0 Read receive data from I2CDR I2CSR I2CMCF 0 l2CSR I2CMIF lt 0 Final byte 1 received I2CCTL I2CTXAK lt 1 Read receive data from Il2CDR Yes I2CSR I2CMCF 0 I2CSR I2CMIF lt 0 I2CCTL I2CMSTA 0 Read receive data from Il2CDR ML630Q791 gt Clear data transfer completion flag Clear interrupt flag Set to send ACK at completion of re
214. letion transfer erret 3 I2CBUFSLV Write 2 0 Check I2CBUFLEV 0 Write IZCBMSTA 1 Write 12 1 0 Write I2CBUFFOR 0x18 Write I2CDR Read 12 4 9 Waveform 5 When Using Buffer Mode When data length of sub address 1 data reception number of transferred bytes 1 Slave address transmission 1 byte Sub address transmission BMSUBO gt gt Start hy hy SDA y Ay J A1 Y RW X ACKX SA7Y ACK X 5 Waiting for transfer completion transfer error I2CBUFSLV Write 2 0 Check I2CBUFSUB Write I2CBMSTA 1 Write I2CBUFLEV 0 Write 2 0 19 Write Slave address transmission 1 byte Data reception 1 byte Repeated START l M 07 I e Stop SDA Y N X AX 6 X X RW X D7 X SCL o XE NOMEN OX AG XX Nf I2CBMFI interrupt 0 Waiting for transfer completion transfer error I2CBMFI 0 Write I2CDR Read 12 4 10 Waveform 6 When Using Buffer Mode When data length of sub address 2 data reception number of transferred bytes 1 Slave address transmission 1 byte Sub address transmission BMSUB3 Sub address transmission BMSUBO Start J o 0 o SDA NX AT A1 X R W X SA7 ACK X SA7 X Y RR up m 2 Waiting for transfer completion transfer error gt I2CBUFSLV Write
215. ls see ML630Q791 User s Guide SDK Sensor Control Host IF Specification The following table shows the symbol name for each parameter register FEUL630Q791 Register Bit 31 24 Bit 23 16 Bit 15 8 Bit 7 0 HIFPRMF PRMC 7 0 PRMDI7 0 PRME 7 0 PRMF 7 0 HIFPRMB 8 7 0 PRM9 7 0 PRMA 7 0 PRMB 7 0 HIFPRM7 PRM4 7 0 PRMB5 7 0 PRME6 7 0 PRM7 7 0 PRMO 7 0 PRM1 7 0 PRM2 7 0 PRM3 7 0 11 14 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 11 CPURG Command Register HIFCMD Address 0 4005 0030 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name ENT Access R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CMD1 7 0 CMDO 7 0 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Description of Register Command register HIFCMD is a read only special function register SFR which indicates the command from the host processor When the host processor sets a command to the register for host access HSTRG CMDn the command of this register is updated Writing from CPU is invalid D
216. m clock frequency x 1 05 2 setting value x 8 6 Therefore I2CBC System clock frequency x 1 05 TC bus transfer rate bps x 8 6 The following table gives examples of setting values I2CBC 100 kbps I2CMD 00 400 kbps I2CMD 01 32MHz 42 0x2A 10 0x0A System clock frequency If 0 is set in the I2CBC register the timing generation counter stops Note e Set the system clock to 32 MHz Set the I2CBC register above before setting the I2CCTL register ML630Q791 12 12 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 7 1 Mode Register I2CMODO 1 Address 0x4008_3018 Och 0x4008_3418 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ _ _ _ _ _ _ _ 2 Symbol name EN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Access R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register selects whether or not to use the buffer mode for the master transfer master transmission and master reception Description of Bits e 2CBMEN bit 0 Set this bit to
217. master write access is required in order to set the internal read address This address is maintained until updated 1 Read using the restart condition Successive read can be performed by repeating the R W 1 read R W 0 write i Slave address 05001 0111 Internal address Address 0x01 Slave address 00001 0111 Internal read data Internal read data Internal read data REGMD 0 Address 0x01 REGMD 0 Address 0x02 REGMD 0 Address 0x03 REGMD 1 Address 0x01 REGMD 1 Address 0x01 REGMD 1 Address 0x01 2 Read using the stop condition After the dummy write process successive read is possible by performing read R W 0 write Internal address Address 0x01 Slave address 0b001_0111 Slave address 05001 0111 REGMD 0 Address 0x01 REGMD 0 Address 0x02 REGMD 0 Address 0x03 REGMD 1 Address 0x01 REGMD 1 Address 0x01 REGMD 1 Address 0x01 Internal read Slave address 0b001 0111 Internal read Internal read REGMD 0 Address 0x01 REGMD O Address 0x02 REGMDs 1 Address 0x01 REGMD 1 Address 0x01 S Start condition E Input direction P Stop condition Output direction A Acknowledge Sr Restart condition Figure 11 5 Register Read Transfer Format FEUL630Q791 11 32 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chap
218. miconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information Please use the Products in accordance with any applicable environmental laws and regulations such as the RoHS Directive For more details including RoHS compatibility please contact a ROHM sales office LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non compliance with any applicable laws or regulations When providing our Products and technologies contained in this document to other countries you must abide by the procedures and provisions stipulated in all applicable export laws and regulations including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act This document in part or in whole may not be reprinted or reproduced without prior consent of LAPIS Semiconductor Copyright 2014 LAPIS Semiconductor Co Ltd LAPIS Semiconductor Co Ltd 2 4 8 Shinyokohama Kouhoku ku Yokohama 222 8575 Japan http www lapis semi com en FEUL630Q791 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Preface This manual describes the hardware and operation of the ML630Q791 32 bit microcontrollers Please ensure that you refer to the latest versions The following manuals are also provided Read them as necessary m Cortexe MO Technical Reference Manual DDI0432 m Cortexe MO Devices Generic User Guide DUI0497 The documents
219. n Dividing ratio 1 16 Initial value 1 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 oj oiljo l5 5Iioj iojjoi ioji io 1 2 8l o ojoo ojojojo 1 1 6 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 6 Clock 6 3 Description of Operation 6 3 1 Low Speed Clock For the low speed clock an external input clock is used The clock of 32 768 kHz should be input 6 3 2 High Speed Clock For the high speed clock HSCLK a clock of 32 MHz generated by the internal FLL is used A clock of 4 MHz to which the high speed clock divided is input to High Speed Time Base Counter 6 3 2 1 Internal FLL Oscillation The internal FLL oscillation generates a clock of 31 998 MHz 5 to which the clock of 32 768 kHz Low Speed clock is multiplied When the frequency of high speed oscillation clock reaches within 31 998 MHz 5 the LFLL flag of FCONI is set to 1 6 3 3 Low Speed Time Base Counter Each of the low speed time base counter LTBC outputs is used as an operation clock for peripheral circuits 6 3 4 High Speed Time Base Counter The high speed time base counter is configured as a 4 bit 1 n counter n 1 to 16 In the 4 bit 1 n counter the divided clock 1 16 x 4MHz to 1 1 x 4MHz
220. n To stop the operation of Timer n n 0 to 7 CETMn CDTMn RDTMn 0 7 write 1 to this bit 0 7 0 7 0 7 REPWM stop the operation of PWM write 1 to this CEPWM CDPWM RDPWM bit REHTC To stop the operation of high speed clock time CEHTC CDHTC RDHTC base counter write 1 to this bit REI2CO To stop the operation of I2C bus interface 0 CEI2CO CDI2CO RDI2CO write 1 to this bit REI2C1 To stop the operation of I2C bus interface 1 CEI2C1 CDI2C1 RDI2C1 write 1 to this bit REUART To stop the operation of UART write 1 to this CEUART CDUART RDUART bit RECAL To stop the operation of arithmetic circuit write CECAL CDCAL RDCAL 1 to this bit REHST To stop the operation of host interface write 1 CEHST CDHST RDHST to this bit FEUL630Q791 5 6 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 2 6 Peripheral Reset Disable Register PERSTDIS Address 0x4000_022C Access R W Access size 32 Bits Initial value 0x8000_0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 S mbol name RD we _ _ _ _ an RD _ _ RD _ RD RD y HST CAL UART 1261 2 0 Access RAN RAW R W R W RW RW RAN RAW RAW R W R W RAW RAN RAW RW RW Initial value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Siinmaa seen ERE a a ROAI FID AD 4 HTC
221. n if another instruction is inserted between 0 0000 O0FA and 0x0000 00 5 written to FLCACP the sector erase or 1 word write is enabled However if you write data other than 0 0000 00F5 in FLCACP after writing 0x0000 00FA it is disabled Therefore you must write from 0 0000 00FA again to enable it In addition if you write to FLCACP without executing erase or 1 word write after writing 0 0000 00FA and 0x0000 00 5 it is disabled regardless of the value Therefore you must write 0000 00FA and 0x0000_00F5 in this order again to enable it Note If you write 00 in FLE field with the FLCACP register enabled it is still maintained as enabled FEUL630Q791 16 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 4 Flash ROM Address Register FLCADR Address 0x4000 4008 Access R W Access size 32 Bits Initial Value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 2215 Access 2 x RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FA 15 2 i Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future extension is read when reading Write 0 when writing Description of R
222. n nennen rennen enne ne tere 10 3 10 2 3 Watchdog Timer Mode Register WDTMOD sese 10 4 10 3 Description of cte de oes e pere to ebur exe 10 5 10 4 Example of Processing When Not Using Watchdog Timer eese nennen enne nennen nnne 10 7 Chapter 11 11 Host Intetface oases ere a ehe te RR ERE REUTERS 11 1 11 12 OVErVIGW PR pe REPE TU NER IER ER OR YU UU EROR 11 1 LET 11 1 Confipurations e Ae cle Ae esl oe ROA AAS Ail Noi RAR e BS 11 1 11 2 Description of Registers roi eee rrr peret orienter erret pee eremo ele aeree en erede e pneter 11 2 11 2 1 Register List CPURG for CPU Access eene nnne innen nnne nnne 11 2 11 2 2 Register List HSTRG for Host Access 11 4 11 2 3 CPURG Configuration Register HIFCFQ sees teen een eene ener nennen trennen 11 6 11 2 4 CPURG Operation Status Register HIFST essere trennen 11 8 11 2 5 CPURG Interrupt Request Register HIFRQ essessseseseseseeeeee eene rennen eene tentent trennen 11 9 11 2 6 CPURG FIFO Register HIEFIEQ iit ees eter inerte her iet rete Ee eate e ent eie 11 10 11 2 7 CPURG FIFO Switch Register HIFFSEL esee
223. n of Register FIFO write pointer register HIFWP is a special function register SFR that has the pointer to specify the address to write to the FIFO This register can be rewritten by the CPU only when FSEL 0 CPU access enabled Rewriting by the CPU is disabled when FSEL 1 Description of Bits FIFOWP bit 8 0 The pointer to specify the address to write to the FIFO For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 12 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 9 CPURG FIFO Read Pointer Register HIFRP Address 0 4005 001C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name id 5 i FIFORP 8 0 Access RAN RW RW RAW RW RAN RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write when writing Description of Register FIFO read pointer register is a special function register SFR that has the pointer to specify the address to read from the FIFO This register can be rewritten by the CPU only when FSEL 0 CPU access enabled Rewriting by the CPU
224. name FSCSCPB2E 15 0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCPB2E is a special function register SFR used to set the value to start enabling bit 2 of byte signal of the erase program counter at the time of programming of Flash ROM Description of Bits e FSCSCPB2E 23 0 bit 23 0 For FSCSCPB2E 23 0 bit 2 of the byte signal to Flash ROM is enabled when the erase program counter value matches with the bit value at the time of programming of Flash ROM In addition the other bits of the byte signal are disabled For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 24 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 24 Set Count Program Enable Register FLCSCPB3E Address 0 4000 04BO Access R W Access size 32 Bits Initial Value 0x0000 017A Bit 91 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbolname 900 0000 00 uso A FSCSCPBSE 23 16 Access ROR RW RW RW RW RW RN Intialvalue 0 0 0 0 O 0 0 0 Bit 1514 1 12 1 40 9 8 7 6 5 4 8 2 1 0 Symbol name 2 FSCSCPBSE IS0 Access RW RAN RW RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 0 Note
225. nction of Port PA6 PAe 1 0 Description 00 General purpose input output pin 01 Host interface INTO S pin 10 Prohibited 11 Prohibited FEUL630Q791 ML630Q791 User s Manual Chapter 5 MCU Control Function 5 9 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 3 Description of Operation 5 3 1 State Transition Figure 5 1 shows an operating state transition diagram External reset System reset Release reset lt External reset Software reset Program run mode mode External reset WFI SLEEPDEEP Interrupt Sleep mode Figure 5 1 Operating State Transition Diagram Operation mode Function System reset mode The operating state goes into the system reset mode by an external reset RESET pin or software reset SYSRESETREQ The internal regulator special function register SFR and CPU are initialized For details see Section 4 3 1 System Reset Mode Program run mode CPU can operate in this mode The FLL control and the function stop control of each block are possible Sleep mode SLEEPDEEP bit 0 Cortex MO sleep mode During the sleep mode the settings of FLL and individual block that are set before entering the sleep mode are enabled In this mode the communication of I2C master UART host interface and the operation of
226. nitors the level of the SCL line I2CSDA bit 1 Monitors the level of the SDA line DBMONI bit7 4 Monitors the status of SCL bit counter DBMON2 bit 11 8 Monitors the status of the SCL state machine DBMONG3 bit 15 12 Monitors the status of the main state machine Note This bit is for debugging Do not manipulate it for normal operation ML630Q791 12 11 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 6 1 Bus Transfer Rate Setup Counter I2CBCO 1 Address 0 4008 3014 Och 0 4008 3414 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access i E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name s I2CBC 6 0 Access RAW RAW R W R W RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register sets the count value for the counter that generates the transfer timing of the bus from the system clock Normally it is used to generate SCL SDA Description of Bits I2CBC bit 6 0 The relationship between the setting value of I2CBC and the transfer rate of the bus is as follows bus transfer rate bps Syste
227. nput signal of GPIO pin goes into the L level Note that the assertion period of L must be one system clock cycle or longer The interrupt is generated after the pin is asserted or after three sysclk cycles FEUL630Q791 15 12 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 3 3 4 Input Interrupt For Detection with Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 1011 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when the input signal of GPIO pin goes into the level By waiting at least 125 us two cycles at 16 kHz after the input signal of pin goes into the L level and then writing 1 to the interrupt status register PIOIS from CPU the GPIO interrupt status register PIOIS is cleared to 0 and the interrupt is released at the same time If 1 is written to the GPIO interrupt status register PIOIS from CPU while the input signal of pin is the GPIO interrupt status register PIOIS is not cleared to 0 and the interrupt is not released If an interrupt source is generated at the same timing as the release of the interrupt from CPU the interrupt generation has priority Figure 15 5 shows an operation example ISn n A B IMASKn s n A B INTn 1 y n A B 1 Period from interrupt assertion to internal i
228. nterrupt see 11 2 5 CPURG Interrupt Request Register HIFRQ For commands and responses of results see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 36 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 4 3 Write Read Data to from FIFO Access to CPURG HIFFIFO or HSTRG FIFO means writing reading data to from 512B FIFO An example is shown below The CPU and the host write read in the units of one byte WP FWP8 to FWPO m RP FRP8 to FRPO Initial status FIFO lt Ox1lFF Write data1 data2 and data3 to CPURG HIFFIFO in this order WP points 0x003 0x000 0 001 When writing data to CPURG HIFFIFO FSEL of 0x002 HIFFSEL register should be 0 0x003 Data written while HIFFSL 1 is invalid Also WP is not updated Ox1FF Data1 is read and RP points 0x001 0x000 0x001 When reading data from HSTRG FIFO HIFFSL 0x002 should be 1 Data read while HIFFSL 0 is undefined Also RP is 0x003 i not updated i Ox1FF i Write dataX dataY dataZ to CPURG HIFFIFO in this order while WPzOx1FF Data is written to 0x1FF 0x000 and 0x001 At this time the data held in 0x000 and 0x001 are 0x000 updated 0x001 i 0x002 Then the appropriate RP needs to be set by the 0x003 software since the data in the address 0x001 that was to be read by the host processor in the next process i
229. nterrupt generation Up to 2 cycles at 16 kHz 2 Interrupt status clear disable period after the interrupt source clear GPIO pin is deasserted Up to 2 cycles at 16 kHz Even if the interrupt status is cleared during this period the interrupt signal is not released 3 Interrupt status clear Write 1 to the ISn bit 1 Internal interrupt signal Figure 15 5 Example of H level Input Interrupt Operation For Detection without Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 0011 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when the input signal of GPIO pin goes into the H level Note that the assertion period of H must be one system clock cycle or longer The interrupt is generated after the pin is asserted or after three sysclk cycles FEUL630Q791 15 13 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 3 3 5 Rising Falling Interrupt For Detection with Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 1100 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when a rising or falling edge of the input signal of GPIO pin is detected Note that the width of L after the falling edge and the width of after the rising edge must be 125 us two cycles at 16 kHz or longer By writing 1 to th
230. ondary tertiary function of port Description of Bits PAO bit 1 0 PAO is used to select the primary secondary tertiary function of Port PAO PAO 1 0 Description 00 General purpose input output pin 01 I2C1 SDA pin 10 PWM PWM pin 11 Prohibited PAI bit 5 4 is used to select the primary secondary tertiary function of Port 1 PA1 1 0 Description 00 General purpose input output pin 01 I2C1 SCL pin 10 Host interface S pin 11 Prohibited PA2 bit9 8 PA2 is used to select the primary secondary function of Port PA2 PA2 1 0 Description 00 General purpose input output pin 01 UART RXDO pin 10 Prohibited 11 Prohibited bit 13 12 PA3 is used to select the primary secondary function of Port PA3 PA3 1 0 Description 00 General purpose input output pin 01 UART TXDO pin 10 Prohibited 11 Prohibited 5 8 FEUL630Q791 LAPIS Semiconductor Co Ltd PAA bit 17 16 is used to select the primary secondary function of Port PA4 PA4 1 0 Description 00 General purpose input output pin 01 Host interface 5 5 pin 10 Prohibited 11 Prohibited PA5 bit 21 20 PAS is used to select the primary secondary function of Port PAS 5 1 0 Description 00 General purpose input output pin 01 Host interface SDO S pin 10 Prohibited 11 Prohibited PA6 bit 25 24 is used to select the primary secondary fu
231. operation performed after an overrun error will clear the overrun error Although the character in the shift register is not transferred to the FIFO it will be overwritten This bit is cleared when the UARTLSR register data is read out LSR1 Description 0 No overrun error 1 Overrun error occurred FEUL630Q791 13 12 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART LSR2 bit 2 Indicates that a parity error occurred This is enabled only when parity is enabled This bit is cleared when the UARTLSR register data is read out Also in FIFO mode this bit indicates that the error is associated with the leading data in the FIFO Even if a parity error associated with any data other than the leading data in the FIFO had occurred it will not be indicated by LSR 2 LSR2 Description 0 No parity error 1 Parity error occurred LSR3 bit 3 Indicates that a framing error occurred A framing error indicates that there is no valid stop bit in the received character This bit is set to 1 when the stop bit after the last data bit or after the parity bit is 0 spacing level This bit will be cleared when the CPU reads out the UARTLSR register In FIFO mode the framing error is related to a specific character in the FIFO LSR 3 indicates that an error is present when that character comes to the beginning of the FIFO LSR3 Description 0 No framing error 1 Framing erro
232. or not Description 0 INT1 S is merged with INTO S to be output initial value 1 INT1 S is output independently Note Separately set the port PA1 to output INTI 5 INTPW bit 5 4 This bit indicates the pulse width setting when the interrupt signal is a pulse signal INTPW 1 0 Description 00 250 ns 4 MHz cycle initial value 01 500 ns 2 MHz cycle 10 1000 ns 1 MHz cycle 11 2000 ns 500 kHz cycle FEUL630Q791 11 6 LAPIS Semiconductor Co Ltd REGMD bit 7 This bit shows the register access mode of the serial interface SPI I2C When set to 0 the internal address is incremented by 1 each time a 1 byte data is transmitted received When set to 1 the address is fixed to the same address REGMD Description 0 Address increment enabled initial value 1 Address increment disabled FIFO register FIFO and result register 3F RSLT3F are excluded from the address increment If FIFO register or result register is accessed with this bit set to the address increment is not executed IFSEL bit 8 This bit indicates whether the serial interface is I2C or SPI IFSEL Description 0 SPI interface 1 I2C interface initial value IFCFG bit 15 9 The function of this bit depends on the IFSEL setting This bit should be set after setting IFSEL IFSEL 1 I2C selected Indicates the I2C slave address The initial value of
233. ors such as NACK reception unexpected STOP condition and timeout If the number of transferred bytes is different from the value of the buffer mode level register the transmission does not start This bit will be cleared to 0 and an 2 interrupt will occur If the number of transferred bytes is 0 the transmission and reception does not start This bit will be cleared to 0 and an I2CBMDZ interrupt will occur I2CBMSTA Description 0 Transfer in the 12C buffer mode is stopped 1 Transfer in the 12C buffer mode is started ML630Q791 12 17 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 12 Buffer Mode Interrupt Mask Register I2CBUFMSKO 1 Address 0 4008 302 Och 0 4008 342C 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 1413 12 1 9 9 8 7 6 5 4 3 2 1 0 Symbol name gt gt 2 2 2 2 4 DZIE AGIE ISIE TOIE NAIE FIIE Access RRR RW RW RN Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register The I2CBUFMSK register controls each interrupt signal in the
234. ot implemented to execute sector erase or 1 word write If it is executed the Flash ROM is not updated The BUSY field of the Flash ROM status register FLCSTA changes to 1 but goes back to 0 in a short time because the Flash ROM is not updated 16 3 6 Notes in Use If the power is down or the operation is terminated forcibly during sector erase or 1 word write retry the sector erase and rewrite the area FEUL630Q791 16 33 Chapter 17 On Chip Debug Function LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 17 On Chip Debug Function 17 On Chip Debug Function 17 1 Overview This LSI implements a SW DP serial wire debug port as the debug interface The connection example is shown in Figurel7 1 For details see the debugger manual Note The timer and WDT clock are stopped at break in the debugger Power Supply debug connector ML630Q791 VDD SWD SWC RESET_N Figure17 1 Connection with Debug Connector FEUL630Q791 17 1 Chapter 18 Power Supply Circuit LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 18 Power Supply Circuit 18 Power Supply Circuit 18 1 Overview This LSI includes a voltage regulator for the internal logic 18 1 1 Features GPIO and the regulator operate with voltage supplied from VDD Internal logic circuit FLASH RAM FLL operate with voltage that the regulator outputs to VDDL 18 1 2 Configuration Figure 18 1 shows the configuration of the powe
235. overflow of WDT results in REQO 7 0 OxFF REQO n Description 0 No interrupt source initial value 1 Interrupt source exists n 0 to 7 For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 23 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 20 HSTRG Interrupt Request Register 1 INTREQ1 Address 0x8D read Access R Access size 8 Bits Initial value 0x00 Bit 7 6 5 4 3 2 1 0 REQ1 1 REQ1 REQ1 REQ1 REQ1 1 REQ1 Symbol name 6 5 4 3 2 1 0 Access R R R R R R R R Initial value 0 0 0 0 0 0 0 0 is a read only register that shows the interrupt source Each value of this register is cleared by being read by the host processor Writing is invalid Description of Bits REQI 7 0 bit 7 0 Indicates the source of interrupt to the host processor The second overflow of WDT results in REQ1 7 0 20xFF REQ1 n Description 0 No interrupt source initial value 1 Interrupt source exists n 0 to 7 For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification The timing of clearing INTREQ1 0 depends on the INT1EN bit setting of the configuration register HSTRG CFG For details see 11 4 5Timing of Clearing Interrupt Request Register FEUL630Q791 11 24 LAPIS Semiconductor Co Ltd 11 2 21 HS
236. ping can be performed in one of two ways through software software remap or forcing it by entering an appropriate sequence to the external pin hardware remap Figure D 5 shows circuit examples for the hardware remap The additional circuit is not necessary for the software remap 1 8V T ML630Q791 Host processor I O port I O port Figure D 5 Example of Circuit to Perform Firmware Update by External Pin To begin the remapping sequence using the external pin enter L level to the RESET_N pin Next after enter level to the BRMP pin enter level to the RESET pin Based on the BRMP pin that is set during this reset period the area containing boot loader is re mapped to reset vector For details of the remapping timing see Appendix C Electrical Characteristics FEUL630Q791 D 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix D Application Circuit Example eClock Input Circuit ML630Q791 inputs an external 32 768 kHz clock to the CLK pin 32 768 kHz Oscillator ML630Q791 CLK Figure D 6 External Clock Input Pin FEUL630Q791 D 6 Revision History LAPIS Semiconductor Co Ltd Revision History Document No Date Previous Current Edition Edition PEUL630Q791 01 23 2014 FEUL630Q791 01 Oct 22 2014 ES FEUL630Q791 ML630Q791 User s Manual Revision History Description Preliminary Edition issued Final Edition issued R 1
237. ported e Input clock 32 768 kHz External clock input e Power supply voltage Vpp 17 to 1 9V Digital core section 1 35V to 1 65V supplied by the internal voltage regulator Supply current Typ High speed operation 32 MHz 5 0 mA Low speed operation 32 768 kHz 0 5 mA sleepdeep mode 2 5uA e Operating frequency High speed clock FLL 32 MHz Low speed clock 32 768 kHz e Operating temperature 40 C to 85 C e Package 20 pin WL CSP 0 4 mm pitch 2 1 mm x 1 8 mm FEUL630Q791 1 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 1 Overview 1 2 Configuration of Function Blocks 1 2 1 ML630Q791 Block Diagram SWD CPU SWC 0 RS Program General Memory Purpose I O Flash 128KB eon 7 bit 1ch 4 RAM 16KB SDAS SCLS HOST IF 90925 SPI 12C Ses Cortex M0 565 5 SCLK S INTO S INT1 S SDAO M imer I2C Master SCLO M 8 bit 8ch 2ch SDA1 SCL1 M PWMO PWM 1 UART ich RXDO0 WDT 1 Clock Arithmetic CLK Circuit Controller VDD RESET N Reset Regulator VDDL z Controller GND 1 Selectable 2 or SPI interface 2 Secondary function 3 Tertiary function Figure 1 1 Block Diagram of ML630Q791 FEUL630Q791 1 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 1 Overview 1 3 Pin Layout 1 3 1 Pin Layout 1 3 1 1 WL CSP Package
238. ported FEUL630Q791 7 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 7 Interrupt 7 2 Description of Registers 7 2 1 List of Registers bits 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 0 0000 0000 For details of the interrupt registers see the section about NVIC of Cortex MO User Guide FEUL630Q791 7 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 7 Interrupt 7 2 2 Correspondence with Bits Table 7 1 shows the bit of each register for each interrupt number Table 7 1 Corresponding Bits interrupt NVIC_ISPR NVIC_ICPR NVIC IPRn number IRQ 0 SETENA O0 CLRENA 0 SETPENDJ 0 CLRPENDIO NVIC IPRO PRI O 1 0 IRQ 1 SETENA 1 CLRENA 1 SETPEND 1 CLRPEND 1 IPRO PRI 1 1 0 IRQ 2 SETENA 2 CLRENA 2 SETPEND 2 CLRPEND 2 IPRO PRI 2 1 0 IRQ 3 SETENA S3 CLRENA 3 SETPEND 3 CLRPENDJ3 NVIC_IPRO PRI_3 1 0 IRQ 4 SETENA 4 CLRENA 4 SETPEND 4 CLRPEND 4 NVIC IPR1 PRI 4 1 0 IRQ 5 SETENA 5 CLRENA 5 SETPEND 5 CLRPEND 5 NVIC_IPR1 PRI_5 1 0 IRQ 6 SETENA 6 CLRENA 6 SETPEND 6 CLRPEND 6 NVIC_IPR1 PRI_6 1 0 IRQ 7 SETENA T CLRENA T SETPEND 7 CLRPEND T7 NVIC_IPR1 PRI_7 1 0 NVIC_IPR2 PRI_8 1 0 IRQ 8 SETENA 8 CLRENA 8 SETPEND 8 CLRPEND 8 IRQ 9 SETENA 9 CLRENA 9 SETPEND 9 CLRPEND 9 IPR2 PRI 9 1 0
239. pt generation has priority Figure 15 3 shows an operation example E n A B lEn 1 n A B Mn 001 n A B ISn n A B IMASKn 2 n A B INTn 1 n A B 1 Edge interrupt assertion period At least 125 us at least 2 cycles or longer at 16 kHz 2 Interrupt status clear Write 1 to the ISn bit 1 Internal interrupt signal Figure 15 3 Example of Rising Edge Interrupt Operation For Detection without Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 0001 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when a rising edge of the input signal of GPIO pin is detected Note that the assertion period of after the falling edge must be one cycle of system clock or longer The interrupt is generated after the pin is asserted or after three sysclk cycles FEUL630Q791 15 11 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 3 3 3 Level Input Interrupt For Detection with Sampling If the interrupt function is enabled and the GPIO interrupt mode register PIOIM is set to 1010 the GPIO interrupt status register PIOIS is set to 1 to generate an interrupt when the input signal of GPIO pin goes into the L level By waiting at least 125 us two cycles at 16 kHz after the input signal of GPIO pin goes into the H level and then writing
240. pt request register O INTREQO R 8 0x00 Ox8D Interrupt request register 1 INTREQ1 R 8 0x00 OxOE Ox8E Reserv d _ _ Ox8F 0x10 0 90 FIFO register FIFO R W 8 OxXX 0 11 0 91 die 188999 0x20 0 0 Parameter register PRMF R W 8 0x00 0x21 OxA1 Parameter register OE PRME R W 8 0x00 0x22 2 Parameter register 0D PRMD R W 8 0x00 0x23 Parameter register PRMC R W 8 0x00 0x24 4 Parameter register OB PRMB R W 8 0x00 0x25 0xA5 Parameter register 0A PRMA R W 8 0x00 0x26 OxA6 Parameter register 09 PRM9 R W 8 0x00 0x27 OxA7 Parameter register 08 PRM8 R W 8 0x00 0x28 0xA8 Parameter register 07 PRM7 R W 8 0x00 0x29 0 9 Parameter register 06 PRM6 R W 8 0x00 2 OxAA Parameter register 05 PRM5 R W 8 0x00 0x2B OxAB Parameter register 04 PRM4 R W 8 0x00 0x2C OxAC Parameter register 03 R W 8 0x00 0 20 OxAD Parameter register 02 PRM2 R W 8 0x00 0 2 OxAE Parameter register 01 PRM1 R W 8 0x00 Ox2F OxAF Parameter register 00 PRMO R W 8 0x00 0x30 OxBO Command register 0 CMDO R W 8 0x00 0x31 0xB1 Command register 1 CMD1 R W 8 0x00 0x32 0xB2 Command entry register ENT R W 8 0x00 0x33 0xB3 Reserved _ _ _ Ox3F OxBF OxCO Result register 00 RSLTOO R 8 0x00 OxC1 Result register 01 RSLTO1 R 8 0x00 OxC2 Result register 02 RSLT02 R 8 0x00 OxC3 Result register 03 RSLTO3 R 8 0x00 OxC4 Result register 04 RSLT04 R 8 0x00 OxC5 Result register 05 R
241. pter 7 Interrupt for interrupts and Chapter 11 Host Interface for abnormal state notification 10 1 1 Features Free running cannot be stopped One of four types of overflow periods 125ms 500ms 2s and 8s selectable by software Non maskable interrupt requested by overflow Operation at the second overflow Notification of abnormal state to the host interface 10 1 2 Configuration Figure 10 1 shows the configuration of the watchdog timer Interrupt I Notification to the host interface WDT counter _ control 256HZ gt gt R WDTINT Non maskable interrupt WDT overflow RESET S WDTCON System reset 5 detection detection O WDTMOD WDTCON Write Data bus WDTCON Watchdog timer control register WDTMOD Watchdog timer mode register Figure 10 1 Configuration of Watchdog Timer FEUL630Q791 10 1 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 10 Watchdog Timer 10 2 Description of Registers 10 2 1 List of Registers Address Name Symbol R W Size Initial value bits 0x4001 0400 Watchdog timer control register WDTCON R W 32 0x0000 0000 0x4001 0404 Watchdog timer mode register WDTMOD RAW 32 0x0000 0002 FEUL630Q791 10 2 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 10 Watchdog Timer 10 2 2 Watchdog Timer Con
242. r 16 Flash Programming 16 2 8 Boot Program Address Register FLCBADR Address 0 4000 0424 Access Access size 32 Bits Initial Value 0x0001 F000 Bit 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name E a xi zd BPA 27 16 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 8 7 6 5 4 3 2 1 Symbol name BPA 15 12 zd 22 zi zu zi oe zi PA zi zi R R R R R R R R R R R R R R R R Initial value 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future extension is read when reading Description of Register FLCBADR is a special function register SFR used to indicate the start address of the boot program area Description of Bits e BPA 27 12 bit 27 12 BPA 27 12 is a bit used to indicate the start address of the boot program area by the initial value FEUL630Q791 16 9 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 9 Set Count Acceptor Register FLCSCACP Address 0 4000 0460 Access W Access size 32 Bits Initial Value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name i 2 2 E Access gt x y z s s Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4
243. r Empty was last set e THRE was set FEUL630Q791 13 20 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 5 FIFO Polled Mode When FIFO is enabled AND IER 3 0 is all set 0 the UART will operate in FIFO polled mode Since the receiver section and transmitter section can be controlled separately either one or both can be set to FIFO polled mode In FIFO polled mode the states of the receiver and transmitter sections must be checked by reading out the LSR since no interrupt is generated e A state in which at least one character is present in the receive FIFO can be confirmed by the value 1 set to LSR 0 e When IER 2 is cleared to 0 an interrupt will not be generated even if an error is detected while receiving a character The error state will not be indicated on the IIR value Therefore the error type must be checked with the values for LSR 4 1 e state in which the transmit FIFO is empty can be confirmed by the value 1 set to LSR 5 e A state in which the transmit FIFO and transmit shift register are both empty can be confirmed by the value 1 set to LSR 6 e A state in which the character associated with an error at the time of reception is present in the receive FIFO can be confirmed by the value 1 set to LSR 7 In FIFO polled mode FIFO will operate however trigger level and timeout detection will not be performed since they are only notified by interrupts
244. r occurred LSR4 bit 4 Indicates that a break interrupt occurred This bit is set to 1 when the input data is maintained in the spacing 0 state during the transmission of one frame start bit data bit parity bit stop bit This bit will be cleared when the CPU reads out the UARTLSR register In FIFO mode this is related to a specific character in the FIFO This bit reflects the break interrupt state when the break character comes to the beginning of the FIFO If the related character comes to the beginning of the FIFO before the first UARTLSR register is read the CPU erases this error When a break interrupt occurs only one zero character will be loaded into the FIFO Description No break interrupt Break interrupt occurred LSRS bit 5 Transmitter Holding Register Empty THRE This bit indicates that preparations have been made for calling a new character to be transmitted by the ACE This bit is set to 1 when the character in the UARTTHR register is transferred to the Transmitter Shift Register UARTTHR register write operation will clear this bit to 0 This bit will not be cleared by reading out the UARTLSR register In FIFO mode this bit is set when the transmit FIFO is empty This bit is cleared when one byte is written to the transmit FIFO When THRE interrupt has been enabled by IERI THRE generates an interrupt in the UARTIIR register with an interrupt priority level 3 When THRE is the interrupt source indic
245. r register FLCACP W 32 0x0000_0000 0x4000_0408 Flash ROM address register FLCADR R W 32 0x0000_0000 0x4000 040C Flash ROM write data register FLCWDA 32 0 0000 0000 0 4000 0410 0 4000 0420 0x4000 0424 FLCERA FLCRSIZ FLCBADR Flash ROM erase register 0x0000 0000 0x0002 0000 0x0001 F000 Flash ROM size register Boot program address register 0x4000 0460 Set count acceptor register FLCSCACP 0x0000 0000 0x4000 046C 0x4000 0470 Set count sector erase CE enable register Set count program CE enable register FLCSCSCE FLCSCPCE 0x0002 1474 0 0000 04FB 0x4000 047C Set count sector erase WE enable register FLCSCSWE 0x0002 13AA 0x4000 0480 Set count program WE enable register FLCSCPWE 0x0000 0431 0x4000 0484 0x4000 0488 0x4000 048C 0x4000 0490 0x4000 0494 0x4000 0498 0x4000 049C 0x4000 04A0 0x4000 04A8 0x4000 04AC 0x4000 04BO 0 4000 04B4 0x4000 04B8 0x4000 04BC 0x4000 04CO 0x4000 1400 0x4000 1404 0x4000 1408 0x4000 140C 0x4000 1410 0 4000 1414 FLCSCPP21E R W 32 FLCSCPP21D R W 32 FLCSCPP22E R W 32 FLCSCPP22D R W 32 FLCSCPP23E R W 32 FLCSCPP23D R W 32 FLCSCPP24E R W 32 FLCSCPP24D R W 32 FLCSCPB1E R W 32 FLCSCPB2E R W 32 FLCSCPB3E R W 32 FLCSCEWED R W 32 FLCSCPWED R W 32 FLCSCCED R W 32 FLCSCEND R W 32 TMOD R W 32 TMOC R W 32 TMOCONO R W 32 TMOCON1 R W 32 TM1D R W 32 TM1C R W 32 Set count program PROG2_1st enable reg
246. r serial to parallel conversion operation the ACE data register has the double buffer configuration so that write operations can be made For the UARTTHR register only write operations can be performed with the program when LCR 7 0 3 Divisor Latch LSB DLL 16 bit divisor latch LSB for the baud rate generator DLL register read write operations can be performed with the program when LCR 7 1 For details see Baud rate clock generation FEUL630Q791 13 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 2 3 UART Interrupt Enable Register UART Baud Rate Dividing Register MSB UARTIER UARTDLM Address 0 4008 1004 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access y s 5 z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name IER2 IER1 IERO L L L L L L L L L L L Access RAN RAN RAW R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Description of Register UARTIER is a special function register SFR that provides the following two functions 1 Interrupt Enable Register IER Register used to enable interrupts IER is used for independently enabling the four serial communication channel interrup
247. r supply circuit VDD 1 7 1 9V ypp TET 1 GPIO jj General j ipurpose port CL i VDDL Voltage j Regulator Logic FLASH RAM FLL Circuit s I 1 1 78 jr Figure 18 1 Configuration of Power Supply Circuit 18 1 3 List of Pins VO VDDL Positive power supply pin for the internal logic circuits FEUL630Q791 18 1 Appendixes LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix A Registers Appendix A Registers Address Size bits Initial value SYSCON RE 0x4000 0010 Remapping control register 0x0000 0000 MAP CON SYSCON RE MAP BASE Revision register IDR R 32 PECLKEN R W 32 PECLKDIS R W 32 PERSTEN R W 32 PERSTDIS R W 32 0x4000_0014 Remapping base address register 0x1001_F000 0x4000_0200 0x4000_0220 0x4000_0224 0x4000_0228 0x4000 022C 0x0630 7900 0x8000 0000 0 0113 11FF 0 0113 11FF 0x8000 0000 Peripheral clock enable register Peripheral clock disable register Peripheral reset enable register Peripheral reset disable register 0x4000 0260 Port A mode setting register PAMOD R W 32 0x0000_0000 0x4000_0300 Frequency control register 0 FCONO R W 32 0x0000_0000 0x4000_0304 Frequency control register 1 1 R W 32 0x0000_0002 0x4000_0400 Flash ROM status register FLCSTA R 32 0x0000 0000 0x4000 0404 Flash ROM accepto
248. r the setting value see 16 3 2 Counter Setting FEUL630Q791 16 27 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 27 Set Count CE Disable Register FLCSCCED Address 0x4000 04BC Access R W Access size 32 Bits Initial Value 0x0000 0006 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name RU FSCCED 23 16 Access Exe IP RW RW RW RW RW RW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSCCED 15 0 Access RW RAN RAN RW RW RW RW RA RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Note Reserved bit for future extension is read when reading Description of Register FLCSCCED is a special function register SFR used to set the value to start disabling the chip enable signal of the erase program counter at the time of erase or programming of Flash ROM Description of Bits e FSCCCED 23 0 bit 23 0 For FSCCED 23 0 the chip enable signal to Flash ROM is disabled when the erase program counter value matches with the bit value at the time of erase or programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 28 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 16 Flash Programming 16 2 28 Set Count Termination Register FLCSCEND Addres
249. ress transmission 1 byte Sub address transmission BMSUBO Start 0 0 SDA NX A7 by 1 XY RW XY ACKY SA7 i SCL Dex uc IUe ms Waiting for transfer completion transfer error I2ZCBUFSLV Write 2 0 Check I2ZCBUFSUB Write I2CBMSTA 1 Write I2CBUFLEV 0 Write I2CBUFFOR 0x209 Write Slave address transmission 1 byte Data reception 32 bytes Repeated START 1 mq Stop SDA Y NX X A7 X A6 X LX M X RW X D7 hinack SCL J ONSE X px AS OW 8 I2CBMFI interrupt d Waiting for transfer completion transfer erret Y 3 2 0 Write I2CDR Read ML630Q791 12 39 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 5 Restrictions I2C Master transmission mode e f there is NACK response after data is transferred in the I2C master transmit mode a STOP condition is automatically sent at the same time it enters the IDLE state To resume the transmission it is necessary to set the MSTA of the control register to 1 and send a START condition again In the I2C master transmit mode be sure to write the first byte of the transmit data before setting MSTA 1 sending START condition The data transmission is automatically started after sending START condition Write subsequent bytes of the transmit data after the DR LD status is set to 1 Any transmit data written to
250. ription Before data transfer start or 9 during data transfer 1 Data transfer is completed Note In the receive mode clear this bit by writing 0 to it after reading the receive data from the I2CDR register If any data is left in the receive buffer this bit cannot be cleared even if 0 is written to it ML630Q791 12 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface I2CRBUF bit 8 This bit indicates the existence of receive buffer data If this bit is 1 it indicates that the receive buffer has data and the I2CMCF bit is also 1 When the received data is read from the I2CDR register this bit is cleared to 0 I2CRBUF Data absent in receive buffer Data present in receive buffer Note This bit is used as a spare function It is not used in the operation sequence I2CAKMON bit 11 This bit is used to monitor the transmission or reception status of ACK NACK The ACK NACK bit can be monitored in all modes regardless of transmission and reception The value is updated at the timing of the ACK NACK bit I2CAKMON Description 0 Received or transmitted an ACK 1 Received or transmitted a NACK Note This bit is used as a spare function It is not used in the operation sequence ML630Q791 12 8 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 2CNSTP bit 14 This bit is
251. rrupt occurred in FIFO mode FEUL630Q791 13 14 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 2 7 UART Scratchpad Register UARTSCR Address 0x4008 101C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit Symbol name Access gt 5 2 gt Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name 23 zi n 2 zd zi SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCHR1 SCRO Access d 5 z E RAN R W RW RW RW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Description of Register UARTSCR is a special function register SFR intended for storing data temporarily This register does not affect ACE s transmit and receive operations FEUL630Q791 13 15 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 3 Description of Operation The ACE s serial communication channel is programmed by the control registers UARTLCR UARTIER UARTDLL and UARTDLM These control words define the character length number of stop bits parity baud rate etc Although the order of writing the control registers is immaterial since UARTIER controls the interrupt enabling it is necessary to write the UARTIER register in the end Once the serial communication channel is programmed and becomes ready to operate these registe
252. rrupt request to the host processor In case of power down with this bit set to 1 the written data is reflected to the interrupt request register after returning from power down Therefore an interrupt signal to the host is not asserted before returning from power down INTP Description 0 No writing to interrupt request register initial value 1 Writing to interrupt request register FEUL630Q791 11 8 LAPIS Semiconductor Co Ltd 11 2 5 CPURG Interrupt Request Register HIFRQ Address 0 4005 000C Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 ML630Q791 User s Manual Chapter 11 Host Interface Symbol name Access Initial value 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 REQ1 7 0 Symbol name REQQ 70 Access RAN RAN R W RAW R W RAN RAN RW RAW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 RAN RAV RW RW RW 0 0 0 0 0 FEUL630Q791 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register Interrupt request register HIFRQ is a special function register SFR used to notify the host processor of the interrupt request When this register is set the set value is transferred to the register for host access HSTRG INTREQO 1 causing an interrupt for the host processor The operation of interrupt differs depend
253. rrupts is issued FEUL630Q791 14 12 Chapter 15 GPIO LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 GPIO 15 1 Overview 7 bit x 1ch general purpose I O Input or output can be selected for each bit The interrupt is available with any bit The interrupt mask and the interrupt mode level edge and positive negative polarity can be set for all of the bits 15 1 1 Features Input output selectable for each bit Interrupt available with any bit The interrupt mask and the interrupt mode level edge positive negative polarity can be set for all the bits The sampling mode can be set 15 1 2 Configuration Figure 15 1 shows the configuration of the GPIO Interrupt signal Figure 15 1 Configuration of GPIO 15 1 3 List of Pins Table 15 1 List of Pins Interfaced with the Outside of LSI Pin name Initial Initial Description status value 7 bit general purpose port GPIOA Note For details of switching to the secondary tertiary functions of the port pin see Chapter 5 MCU Control Function FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 15 GPIO 15 2 Description of Registers 15 2 1 List of Registers Table 15 2 List of Registers Address Name Symbol R W Size Initial value bits 0x4000_A000 GPIO data register PIODAT R W 32 0x0000_0000 0x4000 A004 GPIO direction register PIODIR R W 32 0x0000_0000 0x4000_A008
254. rs can be updated at any time when data is not being transmitted or received 13 3 1 Data Transmission Figure 13 2 shows the data transmission timing Writing data to the UARTTHR register will transfer the contents through the transmit FIFO to the transmit shift register Within 16 baud rate clocks after the THRE bit rise is detected the start bit is sent followed by the data one bit at a time from the least significant bit When the data to be transmitted is 7 bit the most significant bit will not be sent If parity is enabled with the LCR3 bit of the UARTLCR register then the parity bit is sent This is followed by the stop bit which indicates the end of transmitting one frame of data After the data is transmitted LSR5 bit of the UARTLSR register is set to 1 to indicate that it is ready for the next transmission This bit is cleared when one byte is written to the transmit FIFO Also when the THRE interrupt has been enabled by IERI THRE generates an interrupt in the UARTIIR register with an interrupt priority level 3 When THRE is the interrupt source indicated in the UARTIIR register this bit will be cleared by reading out the UARTIIR register TXDO Statt Data bit 226 Parity Y Stop Start lt 10r2 iIRS tSTI nUARTINT THRE WR THR RD IIR Read tIRS 16 Baud rate Clocks 151 8 16 Baud rate Clocks tSTI 8 Baud rate Clocks Figure 13 2 Transmission Timing FEUL630Q791 13 16 LAPIS S
255. s 1 lost 1 1 FEUL630Q791 11 37 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface Write data1 to the CPURG HIFFIFO from the initial state and then read from HSTRG FIFO three times FIFO 0x001 Invalid data Data1 is read If data is read beyond WP the data is invalid 0x003 exceed WP A 0x002 invalide Control by software is required so that RP does not Ox1FF FEUL630Q791 11 38 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 4 4 Register Access Conflict by Host and CPU Only the interrupt request register and the result register among the host interface registers can be accessed without handshake at conflict The other registers should be controlled to prevent access conflicts by handshake between the host and the CPU Notes For FIFO register access the FIFO switch register CPURG HIFFSEL should be controlled The interrupt request register and result register are controlled as follows Interrupt request register 0 1 If a conflict occurs on this register writing from the CPU is executed after clearing by reading from the host The INTP bit of the CPUG operation status register is set to 1 while writing from the CPU is held Result register 00 3F The host can read data by write data unit of the CPU 2 byte or 4 byte while keeping a consistency However it is only true with the host in
256. s 0x4000 04CO Access R W Access size 32 Bits Initial Value 0x0000 0001 Bit 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 Symbolname 900 0000 00 0 FSCCENDI 23 16 Access RN RW RW RW RW RW RN Initialvalue 0 0 0 0 0 O0 0 0 0 0 Bit 1514 1 12 1 0 9 7 6 5 4 3 2 1 0 Symbol name FSCCEND 15 0 Access RW RAN RAN RW RW RW RW RAN RAN RW RW RW RAN RAN RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Note Reserved bit for future extension 0 is read when reading Description of Register FLCSCEND is a special function register SFR used to set the completion judgment value of the erase program counter at the time of erase or programming of Flash ROM Description of Bits e FSCCEND 23 0 bit 23 0 FSCCEND 23 0 terminates the erase or programming processing when the erase program counter value matches with the bit value at the time of erase or programming of Flash ROM For the setting value see 16 3 2 Counter Setting FEUL630Q791 16 29 ML630Q791 User s Manual Chapter 16 Flash Programming LAPIS Semiconductor Co Ltd 16 3 Description of Operation 16 3 1 Erase Write Flash ROM It is possible to execute sector erase and 1 write It is needed to access the register of the Flash ROM controller from the CPU according to the procedure It includes the flash rewrite acceptor function which restricts the rewrite op
257. se Write to FLE starts erase according to the data It automatically changes to 00 when the erase is completed Write to 00 is prohibited FLE 1 0 Description 00 01 Erase completed initial value Setting prohibited 10 Setting prohibited 11 Note After high speed clock is selected as the system clock you can erase Flash ROM data Erasing Flash ROM sector while low speed clock is selected as the system clock cannot be guaranteed For details of clock selection see Chapter 6 Clock FEUL630Q791 Start sector erase 16 7 LAPIS Semiconductor Co Ltd 16 2 7 Flash ROM Size Register FLCRSIZ Address 0 4000 0420 Access Access size 32 Bits Initial Value 0 0002 0000 ML630Q791 User s Manual Chapter 16 Flash Programming Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name FSI 31 16 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name FSI 15 0 Access R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description of Register FLCRSIZ is a special function register SFR used to indicate the size of Flash ROM in bytes Description of Bits e FSI 31 0 bit 31 0 FSI 31 0 is a bit used to indicate the size of Flash ROM in bytes FEUL630Q791 16 8 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapte
258. ses an interrupt to the CPU for the command processing After the CPU accepts the command and 1 is written to the bit 16 ENT of the CPURG command register the HSTRG command entry register 0xB2 is cleared The host processor can set the next parameter and command after confirming that the bit 0 ENT of HSTRG command entry register 0xB2 is cleared If the next command or parameter is set before the CPU accepts the command malfunction occurs The CPU processes the accepted command sets the result to the CPURG result register 00 to 3F and then sets the interrupt source to the CPURG interrupt request register 0 and 1 At this time an interrupt can be output to the host processor if no interrupt mask is set to the HSTRG interrupt mask registers 0 and 1 0x82 and 0x83 The operation of interrupt signal differs depending on the INTIEN bit of configuration register CPURG HIFCFG as follows For INTIEN 0 ORed sources of the interrupt request register 0 and are output from INTO_S e For INTIEN 1 The sources of the interrupt request register 0 and are output from INTO_S and INT1_S respectively When the host processor receives the interrupt it reads HSTRG interrupt request register 0 and 1 0x82 and 0x83 Then it reads the data that has been written to the CPURG result register from the HSTRG result register 00 to 3F 0xCO to OxFF The interrupt to the host processor is output in the negative logic For setting and clearing the i
259. ster to 01 to select the secondary function RXDO of PA2 Set bit 13 12 of the PAMOD register to 01 to select the secondary function TXDO of PA2 Register PAMOD register address 0x4000 0260 MU UU IM E Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 _ Setting 0 1 g x x 0 1 0 1 x x x x x value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting x x x x x x x x value Set the bit 2 of the PIODIR register to 1 to set the input output mode of PA2 to input Set the bit 3 of the PIODIR register to 0 to set the input output mode of to output Register PIODIR register address 0x4000 A004 2 2 er a motel Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol PIODIR name 4 Setting x x x x 0 1 x x value Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol 2 i 5 a 5 7 E _ S
260. sters PWOD setting value 0x0000 to OxFFFE POCK Clock frequency selected by the PWMO control register 0 FEUL630Q791 9 8 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM After the PORUN bit is set to 1 counting starts in synchronization with the PWM clock This causes an error of up to clock pulse to the time the first PWM interrupt is issued The PWM interrupt period from the second time is fixed Figure 9 2 shows the operation timing of PWMO Lt Lt Lt UN 05 PUR Ut L5 01 PORUN POSTAT 7 7 Write PWOC Pwoc XXXX y 0000 0007 0002 7 8000 8001 8002 000 000 0000 0001 PWOD Y 8000 BAR T 7777 7 PWODBUF 3000 8000 8000 7777 PWOP Y A000 BBBB Y BBBB BBBB PWOPBUF Y A00 Y R000 Y A000 7 BBBB PWOINT ub EY POFLG PWMO Positive logic 7 PWMO negative logic i i s Figure 9 2 1 2 Operation Timing Diagram of PWMO QJ SSEEREUEGEJEXESENESESESE PORUN POSTAT PWOCH L J2600j2001 2002 2003 2004 2005 2006 2007 2008 POFLG Figure 9 2 2 2 Operation Timing Diagram of PWMO Note Even if 0 is written to the PORUN bit counting operation continues up to the risin
261. sult register OL CALROL R 32 0x0000_0000 FEUL630Q791 2 LAPIS Semiconductor Co Ltd Address Name Symbol ML630Q791 User s Manual Appendix A Registers Size bits Initial value 0x4004 501C Calculation result register OH CALROH R 32 0x0000 0000 0x4004 5020 Calculation result register 1L CALR1L R 32 0x0000 0000 0x4004 5024 Calculation result register 1H CALR1H R 32 0x0000 0000 0x4005 0000 Configuration register HIFCFG R W 32 OxFFFF_2F00 0x4005 0008 Operation status register HIFST R W 32 0x0000 00 0x4005 000C Interrupt request register HIFRQ R W 32 0x0000_0000 0x4005_0010 FIFO register HIFFIFOW R W 32 8 0x0000_00XX 0x4005_0014 FIFO switch register HIFFSEL R W 32 0x0000_0000 0x4005_0018 FIFO write pointer register HIFWP R W 32 0x0000_0000 0x4005 001C FIFO read pointer register HIFRP R W 32 0x0000_0000 0x4005_0020 Parameter register F HIFPRMF R 32 0x0000_0000 0x4005_0024 Parameter register B HIFPRMB R 32 0x0000_0000 0x4005_0028 Parameter register 7 HIFPRM7 R 32 0x0000 0000 0 4005 002C Parameter register 3 HIFPRMS R 32 0x0000 0000 0x4005 0030 Command register HIFCMD R 32 0x0000 0000 0x4005 0040 Result register 00 HIFRLTOOW R W 32 16 8 0x0000 0000 0x4005 0044 Result register 04 HIFRLTO4W R W 32 16 8 0 0000 0000 0x4005 0048 Result register 08 HIFRLTO8W R W 32 16 8 0x
262. t CEI2CO To start the operation of I2C bus interface 0 REI2CO CDI2CO RDI2CO write 1 to this bit CEI2C1 To start the operation of I2C bus interface 1 REI2C1 CDI2C1 RDI2C1 write 1 to this bit CEUART To start the operation of UART write 1 to this REUART CDUART RDUART bit CECAL To start the operation of arithmetic circuit write RECAL CDCAL RDCAL 1 to this bit CEHST To start the operation of host interface write 1 REHST CDHST RDHST to this bit FEUL630Q791 5 4 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 5 MCU Control Function 5 2 4 Peripheral Clock Disable Register PECLKDIS Address 0x4000_0224 Access R W Access size 32 Bits Initial value 0x0113_11FF Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 e ee MOOR 268 AST CAL UART I2C1 12C0 Access RAN R W R W R W RW RAN RAN R W RAW R W R W RAN RAN RAW RW RW Initial value 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 Bit 1514 1 12 11 10 9 8 7 6 5 4 3 2 1 0 a dee cue 2 4 HTC PWM TM7 6 TM5 TM2 1 TMO Access RW R W RW RW RW RW RAW RW RW RAW RAW RAW RW RW RW RW Initial value 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing
263. t register 35 HIFRLT35 R W 8 0x00 0x76 Result register 36 HIFRLT36H HIFRLT36 R W 16 8 0x00 0x77 Result register 37 HIFRLT37 R W 8 0x00 0x78 Result register 38 HIFRLT38W HIFRLT38H HIFRLT38 R W 32 16 8 0x00 0x79 Result register 39 HIFRLT39 R W 8 0x00 Ox7A Result register 3A HIFRLTSAH HIFRLT3A R W 16 8 0x00 0x7B Result register 3B HIFRLT3B R W 8 0x00 0x7C Result register 3C HIFRLT3CW HIFRLT3CH HIFRLT3C R W 32 16 8 0x00 0x7D Result register 3D HIFRLT3D R W 8 0x00 Ox7E Result register 3E HIFRLTSEH HIFRLT3E R W 16 8 0x00 Ox7F Result register 3F HIFRLTSF R W 8 0x00 Accessing any of reserved areas is prohibited Operation cannot be guaranteed if you access a reserved area FEUL630Q791 LAPIS Semiconductor Co Ltd 11 2 2 Register List HSTRG for Host Access ML630Q791 User s Manual Chapter 11 Host Interface FEUL630Q791 Address Size Initial Write Read no dd bits value 0x00 0x80 Configuration register CFG R W 8 0x00 0x01 0x81 Reserved 0x02 0x82 Interrupt mask register 0 INTMSKO R W 8 OxFF 0x03 0x83 Interrupt mask register 1 INTMSK1 R W 8 OxFF 0x04 0 84 _ _ 0x08 0x88 0 89 Operation status register STATUS R 8 OxFE Ox8A Error code register 0 ERRORO R 8 0x00 0x8B Error code register 1 ERROR1 R 8 0x00 Ox8C Interru
264. tails see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 26 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 28 HSTRG Command Register 0n CMDn n 0 to 1 Address 0x30 0x31 write OxBO OxB1 read Access R W Access size 8 Bits Initial value 0x00 Bit 7 6 5 4 3 2 1 0 CMDn CMDn CMDn CMDn CMDn CMDn CMDn CMDn Symbol name 6 5 4 3 2 1 0 Access R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 CMDn is a register that can be written read from the host processor that sets the command Description of Bits CMDn 7 0 bit 7 0 Represents a command For details see ML630Q791 User s Guide SDK Sensor Control Host IF Specification FEUL630Q791 11 27 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 24 HSTRG Command Entry Register ENT Address 0x32 write OxB2 read Access R W Access size 8 Bits Initial value 0x00 Bit 7 6 5 4 3 2 1 0 Symbol name 5 z ENT Access E R W Initial value 0 0 0 0 0 0 0 0 ENT is a register to request an interrupt for CPU When this register is set to 1 an interrupt to CPU is generated The value that has been set to this register is cleared when the CPU writes 1 to the bit 16 of the command register CPURG HIFCMD Description of Bits ENT bit 0 Indicates whether th
265. te start condition Transmitting slave address Waiting for receiving next data i SCL L l 1 Receiving 1 byte i Output ACK at completion of reception 1 Waiting for receiving next i data i Receiving 1 byte 1 Output ACK at completion 1 A ri for sending stop condition SCL L Send stop condition To Bus IDLE 12 28 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 3 4 Flow of Compound Mode Receiving by Master after Transmitting from Master Set slave address and B W bit for I2CDR 2 2 lt 1 lt BR 7T No I2CSR I2CMCF 0 I2CSR I2CMIF lt 0 Write transmit data to I2CDR No MM TT is No CSR I2CRXAK 12 ML630Q791 START I2CCTL I2CMTX lt 1 I2CSR I2CMBB 0 Yes S Ye Transmit data is final byte 37 No Ye No l2CCTL l2CCS lt 1 Yes Final byte transmitted Yes Set slave address and R W bit for I2CDR I2CCTL I2CRSTA lt 1 I2CCTLI2CMTX 0 I2CCTL I2CCS 0 Yes No Yes S Yes Yes 0 I2CSR I2CMCF 0 l2CSR I2CMIF 0 gt Set master transmit mode gt Check Bus IDLE gt Create start condition Start s
266. ter 11 Host Interface 11 3 2 SPI Interface SPI interface can be used for communication with the host processor by setting the IFSEL bit of GPURG configuration register to 0 Three wire or four wire be selected by IFCFG 7 Figure 11 6 and Figure 11 7 show examples of connection with the host processor IFCFG 6 sets Hi Z or 0 output for data output in the SPI no output mode IFCFG 5 sets the polarity of the chip select signal SCS 5 ML630Q791 Host processor SCL S SCLK S SCLK M SDA S SDIO S SDO M PA5 SDO S SDI M PA4 SCS S SCS S PA1 INT1 S 6 0 S INTO M Figure 11 6 SPI Four Wire Connection Example ML630Q791 Host processor SCL S SCLK S SCLK M SDO M SDI M SCS S INT M PCO INTO S INTO M Figure 11 7 SPI Three Wire Connection Example FEUL630Q791 11 33 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 3 2 1 SPI Transfer Format Figure 11 8 and Figure 11 9 show the transfer format of the write sequence Figure 11 10 and Figure 11 11 show the transfer format of the read sequence seks SH X UUUUUUUU UUUUUUUU uult LI 5 2 UUUUUUULJUUUUUUULJUUUUUWUU For SCLK S 1 For SCLK S 2 5556 5 6 2 For SCLK S 1 si s 2 o eL 5 4 3 2 1 0 7 7 6 5 4 s 2 3 o v e s a 8
267. the data register with the DR LD status set to 0 cannot be guaranteed e In the I2C master transmit mode be sure to set the STOP condition MSTA 0 after transferring the data after the MCF status is set to 1 The STOP condition sending is started after the ACK response cycle If it is set at any other timing than an ACK cycle the STOP condition will be sent immediately which may cause a failure ML630Q791 12 40 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 6 Specifying Port Registers To use I2C1 the applicable bit of each related port register needs to be set See Chapter 15 GPIO for details about the port registers 12 6 1 Operating I2C1 Set PAO bit 1 0 of the PAMOD register to 01 to select the secondary function SDA1_M of PAO Set PA1 bit 5 4 of the PAMOD register to OT and then select the secondary function of PAI SCL1 M Register PAMOD register address 0x4000 0260 LC A Ue ui E el Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol 2 1 _ Setting jae boris g x x x 0 1 x x 0 1 value Register PAMOD register address 0x4000 0260 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol PA6 PA5 4 Setting x x x x x x
268. the I2C slave address is 0x17 When using I2C set the I2C slave address from the CPU IFSEL 0 SPI selected The function of each bit is shown below IFCFG 7 Description 0 Sets SPI slave to three wire initial value 1 Sets SPI slave to four wire IFCFG 6 Description 0 SPI output data is Hi Z initial value in the no output mode 1 SPI output data is 0 in the no output mode IFCFG 5 Description 0 CS of SPI is 0 active 1 CS of SPI is 1 active initial value MSK1 0 bit 31 16 This bit masks interrupt sources due to the interrupt request register MSKO n Description MSK1 n 0 Does not mask the interrupt source due to the HSTRG INTREQO REQO n bit 1 Masks the interrupt source due to the HSTRG INTREQO REQO n bit initial value n 0 to 7 FEUL630Q791 ML630Q791 User s Manual Chapter 11 Host Interface LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 11 Host Interface 11 2 4 CPURG Operation Status Register HIFST Address 0 4005 0008 Access R W Access size 32 Bits Initial value 0 0000 FE00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name ER1 7 0 ERO 7 0 Access RW RAV RAN RAW RAN RW RW RW RAN RAN RAN RAW RAN RAW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name ST 7 0 E RLTP INTP Access RAN
269. trol Register WDTCON Address 0 4001 0400 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name 2x E E E m P E P E Access 8 M 2 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 141 10 9 8 7 86 5 4 83 2 1 0 Symbol name 5 5 s a5 a2 d 07 Access 1 5 gt 5 7 Initial value 0 0 0 0 0 0 0 0 oz oz oz oz oz W W RW 0 Note Reserved bit for future expansion 0 is read when reading Description of Register WDTCON is a special function register SFR to clear the WDT counter When WDTCON is read the value of the internal pointer WDP is read from bit 0 Description of Bits WDP d0 bit 0 The value of the internal pointer WDP is read from this bit The WDP is reset to 0 at the system reset or WDT counter overflow and is inverted every writing to WDTCON e 47 40 bit 7 0 This bit is used to write data to clear the WDT counter The WDT counter can be cleared by writing OxSA with the internal pointer WDP is 0 then writing 0xA5 with the WDP 1 Note When the WDT interrupt WDTINT occurs by the first overflow of WDT counter the WDT counter and internal pointer WDP are initialized for the half of low speed clock about 15 us Then writing to WDTCON during this period is in
270. ts that make the interrupt active UARTIER register read write operations can be performed with the program when LCR 7 0 Description of Bits TERO bit 0 Enables disables Received Data Available interrupt in FIFO mode this includes character timeout interrupt IERO Description 0 Disables Received Data Available interrupt in FIFO mode this includes character timeout interrupt 1 Enables Received Data Available interrupt in FIFO mode this includes character timeout interrupt IERI bit 1 Enables disables Transmitter Holding Register Empty interrupt Description Disables Transmitter Holding Register Empty interrupt Enables Transmitter Holding Register Empty interrupt IER2 bit 2 Enables disables Receiver Line Status interrupt IER2 Description 0 Disables Receiver Line Status interrupt 1 Enables Receiver Line Status interrupt bit 3 Reserved bit Always set to 0 FEUL630Q791 13 5 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 2 Divisor Latch MSB DLM 16 bit divisor latch MSB for the baud rate generator DLM register read write operations can be performed with the program when LCR 7 1 For details see Baud rate clock generation FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 13 UART 13 2 4 UART Interrupt Status Register UART FIFO Control Register UARTIIR UARTFCR Address 0 4
271. tten the operation result is not guaranteed Setting multiple operations at a time is prohibited Description of Bits e DIV EN bit 0 DIV_EN indicates the start and status of an unsigned division operation DIV_EN Description 0 Division unsigned operation stopped initial value 1 Division unsigned operation proceeding e SQSTS bit 3 SQSTS indicates the start and status of a root operation SQSTS Description 0 Root operation stopped initial value 1 Root operation proceeding FEUL630Q791 14 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 14 Arithmetic Circuit 14 2 3 Operation Input Register AL CALAL Address 0 4004 5008 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name CALA 31 16 Access RAN RAN R W R W RAW RW RW RW RW R W RAW RAW RW RW RAN RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name CALA 15 0 Access RAN RW RW RW R W RAN R W RAW RW R W RAN RAN RAW RAW RW RW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALAL is a special function register SFR used to store input data for the operation CALAL register sets the lower 32 bits of the dividend for division or the lower 32 bits for root operation For details see 14 3 Description of Operation FEUL630Q791 14 4 LAPIS Semiconductor Co Ltd ML630Q791 Us
272. tting value 1 Register PIODIR register address 0x4000 A004 name Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol gt E gt gt E name Setting value Bit not related to the timer function Input the operation clock for the timer from the PAO pin Note The PIOCON register does not need to be set When the tertiary function is selected the setting is automatically changed to the high impedance input but the value of PIOCON register does not change FEUL630Q791 8 13 Chapter 9 PWM LAPIS Semiconductor Co Ltd 9 PWM 9 1 Overview This LSI includes one channel of 16 bit PWM Pulse Width Modulation The PWM output PWMO and PWM input are assigned to the tertiary function of PAO Port A For functions of Port A see Chapter 15 GPIO 9 1 1 Features ML630Q791 User s Manual Chapter 9 A PWM signal using a clock of 250 ns HTBCLK 4 MHz to about 0 5 s 2 048 kHz can be generated and output to the external e The output logic of the PWM signal be switched to the positive or negative logic e At the coincidence of PWM signal period duties and period amp duty a PWM interrupt PWOINT occurs e For the PWM clock a low speed clock LSCLK 2 048 kHz a high speed time base clock
273. ture expansion 0 is read when reading Description of Register PWOCONI is a special function register SFR to control PWMO Description of Bits bit 0 The PORUN bit is used to control count stop start of PWMO PORUN Description 0 Stops counting Initial value 1 Starts counting POFLG bit 6 The POFLG bit is used to read the output flag of PWMO When a write operation is performed to PWOC it is set to 1 POFLG Description 0 PWMO output flag 0 1 PWMO output flag 1 initial value POSTAT bit 7 The POSTAT bit indicates counting stopped or counting in progress of PWMO POSTAT Description 0 Counting stopped Initial value 1 Counting in progress FEUL630Q791 9 7 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 9 PWM 9 3 Description of Operation The PWMO counter registers PWOC are set to an operating state POSTAT is set to 1 on the first rising edge of the PWM clock POCK that are selected by the PWMO control register O PWOCONO when the PORUN bit of PWMO control register 1 PWOCONI is set to 1 and increment the count value on the 2nd rising edge When the count value of the PWOC coincides the value of the PWMO duty buffer PWODBUF the PWM flag POFLG is set to 0 on the next rising edge of POCK When the count value of the PWOC and the value of the PWMO period buffer PWOPBUF coincide the POFL
274. uctor Co Ltd ML630Q791 User s Manual Appendix C Electrical Characteristics Characteristics Clock 1 7 to 1 9V GND Ta 40 to 85 Standard value Parameter Symbol Condition f Unit Min Typ Max Input clock frequency 32 768 2 1 1 Input clock Typ Typ High pulse width Tous m a 15259 HS Input clock Typ Typ Low pulse width q 15259 i ai System clock frequency fsvs 32 768kHz Typ 32 Typ MHz 5 5 FLL activation time Tas 32 768 2 ms Normal activation FLL activation time Fast activation True fork 32 768kHz E 19 H T i 1 CLK clock input pin gt 1 fsys FLL output clock Z M 152913 e AC Characteristics Reset Vpp 1 7 to 1 9V GND Ta 40 to 85 Standard value Parameter Condition Unit Min Typ Max Reset pulse width Prst 400 Reset noise elimination P a E 011 Us pulse width nash RESET N VIL 1 VIL1 VIL 1 ml P lt gt Pur RESET N pin reset Reset noise elimination FEUL630Q791 C 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Appendix C Electrical Characteristics Characteristics UART 1 7 to 1 9V GND 0V 40 to 85 Standard value Parameter Symbol Condition Unit
275. unexpected STOP condition 1 Detected an unexpected STOP condition This bit is set to 1 if the number of transferred bytes set in I2ZCBMDL and the value of I2CBML do not match at the start of the transmission when I2CBMRW 15 set to 0 and 1 is written to I2CBMSTA In this case the transfer is not started This bit is cleared by writing 0 by software I2CBMAGIE Description 0 The number of transferred bytes and the buffer capacity match at the start of the transmission The transmission has not been started because the number of transferred bytes and the buffer capacity do not match at the start of the transmission I2CBMDZIE bit 6 This bit is set to 1 if the number of transferred bytes set in I2CBMDL is 0 at the start of the transmission when 1 is written to IZCBMSTA In this case the transfer is not started This bit is cleared by writing 0 by software I2CBMDZ 0 Description The number of transferred bytes is not 0 at the start of transmission The transmission has not been started because the number of transferred bytes is 0 at the start of transmission ML630Q791 12 21 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 12 I2C Bus Interface 12 2 14 C Buffer Mode Level Register I2CBUFLEVO 1 Address 0x4008_3034 Och 0x4008_3434 1ch Access R W Access size 32 Bits Initial value 0 0000 0000 Bit
276. upt pulse may not be output depending on the timing when the CPU writes to the interrupt request register In this case use the level output as the interrupt signal instead of the pulse output INTPW 1 0 Description 00 250 ns 4 MHz cycle initial value 01 500 ns 2 MHz cycle 10 1000 ns 1 MHz cycle 11 2000 ns 500 kHz cycle REGMD bit 7 This bit shows the register access mode of the serial interface SPI I2C When set to 0 the internal address is incremented by 1 each time a 1 byte data is transmitted received When set to 1 the address is fixed to the same address REGMD Description 0 Address increment enabled initial value 1 Address increment disabled FIFO register FIFO and result register 3F RSLT3F are excluded from the address increment If FIFO register or result register is accessed with this bit set to the address increment is not executed FEUL630Q791 11 17 LAPIS Semiconductor Co Ltd 11 2 14 HSTRG Interrupt Mask Register 0 INTMSKO Address 0x02 write 0x82 read Access R W Access size 8 Bits Initial Value OXFF ML630Q791 User s Manual Chapter 11 Host Interface Bit 7 6 5 4 3 2 1 0 INT INT INT INT INT INT INT INT Symbol name wskorz MSKO 6 MSKo p MSKo 4 MSKo 3 MSKO 2 MSKO 1 MSKO O Access R W R W R W R W R W R W R W R W Initial value 1 1 1 1 1 1 1 1 INTMSKO is a reg
277. valid and WDP does not invert Therefore in the case of that you have program codes handle to clear the WDT when the first overflow WDT interrupt occurs and also the codes run at high speed system clock please check the WDP gets reversed after writing to WDTCON to see if the writing was surely successful For example of the program code see Section 10 4 Example of Processing When Not Using Watchdog Timer FEUL630Q791 10 3 LAPIS Semiconductor Co Ltd ML630Q791 User s Manual Chapter 10 Watchdog Timer 10 2 3 Watchdog Timer Mode Register WDTMOD Address 0x4001 Access R W 0404 Access size 32 Bits Initial value 0x0000 0002 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Symbol name UK _ j _ i _ _ i _ _ _ _ _ _ _ Access 3 5 J 2 z Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol name zi 3 ci el it SA oo 4 22 WDTT 0 Access E 5 R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Note Reserved bit for future expansion 0 is read when reading Description of Register WDTMOD is a special function register SFR to set the overflow period of the WDT counter Description of Bits WDTY 1 0 bit 1 0 These bits are used to select an overflow period of the watchdog timer The WDTT 1 0 is set an overflow period
278. value 1 PAn pin Input n 0 6 15 4 FEUL630Q791 LAPIS Semiconductor Co Ltd ML630Q791 Users Manual Chapter 15 GPIO 15 2 4 GPIO Port Control Register PIOCON Address 0 4000 A008 Access R W Access size 32 Bits Initial value 0 0000 0000 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ako uu uA cu ue POCONG 27 an SPIOGONS 7 7 PIOGONA y 1 0 1 0 1 0 Access RAN RAW RAN RAW RAN RAW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 3 Se PIOGONT ux PIOGONO y 1 0 1 0 1 0 1 0 Access RAN RAW RN RW RAN RAW RAN RAW Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Reserved bit for future expansion 0 is read when reading Write 0 when writing Description of Register This register is a special function register SFR to select input output state of the Port A pin The input output state is different between input mode and output mode Input or output is selected by using the PIODIR register Description of Bits e PIOCONn 1 0 n 0 6 PIOCONn 1 0 n 0 6 is used to select high impedance output P channel open drain output N channel open drain output or CMOS output in output mode and to select high impedance input input with a pull down resistor or input with a pull up resistor in input mode
279. y third party with respect to the information contained in this document therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute concerning such rights owned by third parties arising out of the use of such technical information The Products are intended for use in general electronic equipment i e AV OA devices communication consumer systems gaming entertainment sets as well as the applications indicated in this document The Products specified in this document are not designed to be radiation tolerant For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representative transportation equipment i e cars ships trains primary communication equipment traffic lights fire crime prevention safety equipment medical systems servers solar cells and power transmission systems Do not use our Products in applications requiring extremely high reliability such as aerospace equipment nuclear power control systems and submarine repeaters LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non compliance with the recommended usage conditions and specifications contained herein LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document However LAPIS Semiconductor does not warrant that such information is error free and LAPIS Se

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