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1. thing It does however tend to create some confusion reading the DOC files In the source file the user should still use whatever pin name is given in the declaration sec tion All references to the pin or FB feedbacks will be ad justed by the software to reflect the changes automat ically Case 3c Combinatorial ISTYPE INVERT Declaration OUT pin 14 ISTYPE invert assume 14 is an I O pin equations OUT A B C The compiler would pick Figure 4 to implement the logic For combinatorial equations it is best to leave out the ISTYPE statement and let the optimizer choose the best DeMorgan equivalent implementation ABC Figure 1 H Pin name HD p ABC Figure 2 Pin name Dee ABC Figure 3 Pin name ae OUT ABC Figure 4 Pin name OUT Note Case 4 Registered no ISTYPE definition Beware Declaration OUT pin 14 assume 14 is an I O pin equations OUT A B CG OUT c CLK OUT ar ARI The pre processor will warn you for not specifying the ISTYPE of the output In this case the compiler will use the fewest product term implementation Figure 6 This might not be what the user is expecting 1 Note 1 Figure 5 and Figure 6 do not produce identical results In Fig ure 5 at power up or after a reset the output pin appears to be a 0 Unlike Figure 5 Figure 6 powers up and resets to a 1 on the output Preset and pre2. Combinatorial Active Low pin 14 OUT OUT A B C The compiler will choose figure 20 to implement the logic The on the OUT pin declaration indicates that an active low output is required CUPL will invert the logic once to obtain the correct output polarity Case 2 registered Active High Pin 14 Out OUT d A B C OUT ck clk OUT ar AR The compiler will choose Figure 21 to implement the logic CUPL will invert the logic twice to obtain the correct output polarity Case 2a Registered Active Low Pin 14 Out OUT d A B C OUT ck clk OUT ar AR The compiler will choose Figure 22 to implement the logic The on the OUT pin declaration indicates that an active low output is required CUPL will invert the logic once to obtain the correct output polarity Pin name OUT Pin name OUT Pin name OUT gt Pin name OUT Note 1 Because of the fixed inverting outputs all flip flops for these devices will reset during power up or through Asynchronous Reset logic to a High or 1 state regardless or how the logic is implemented AMEL 8 79
3. tween the pin declaration OUTC and the equation name OUTC tells the compiler to have an inverter on the out put and to implement the equations as specified by the equation CUPL maintains the OUTC on the pinout dia gram documentation and equation name OUTC in the re duced equation portion of the documentation Both ABEL and CUPL conventions for handling signal po larity have drawn praises and criticisms Help on the soft ware is readily available from Data I O Corporation ABEL Logical Devices Incorporated CUPL and At mel Don t hesitate to call for help U O Figure 12 A B T U O Figure 13 A B F J Figure 14 AB O 5 To Pin name OUT Pin name OUT Pin name OUT Pin name gt OUT AMEL 8 77 AIMEL Polarity Control for Atmel s Flash 16V8 and 20V8 Devices This section discusses the ABEL and CUPL syntax for de vices with fixed inverting output buffers and output polarity control such as Atmel s Flash 16V8 and 20V8 devices 1 Configuring Polarity with ABEL The following examples have A B and C defined as in puts and OUT as the output Only ISTYPE Com for com binatorial or ISTYPE Reg for registered outputs should be used 2 This allows ABEL to optimize the logic to gen erate an implementation with the fewest number of prod uct terms Case 1 Combinatorial High True Output Declaration OUT pin 14
4. ISTYPE Com Equations OUT A B C The compiler will pick Figure 15 to implement the logic To make the output high true the compiler will invert the logic twice to obtain correct output polarity Figure 15 Figure 16 A XOR Polarity Fuse is blown Figure 17 A XOR Polarity Fuse is not blown Figure 18 kK Dl D x Ol XOR Polarity Fuse is blown To cae DE Notes 1 Because of the fixed inverting outputs all flip flops for these devices will reset during power up or through Asynchronous Reset logic to a High or 1 state re gardless or how the logic is implemented 8 78 CMOS PLD Case 1a Combinatorial Low True Output Declaration OUT pin 14 ISTYPE Com Equations IOUT A B C Equivalent to Out A amp B amp C The compiler will pick Figure 16 to implement the logic To make the output low true put a in front of OUT in the logic equations section The compiler will invert the logic three times to obtain the correct output polarity Case 2 Registered High true Output Declaration OUT pin 14 ISTYPE Reg The Reg ISTYPE should be used Equations Out A B C Vis is required to specify a Registered Output OUT clk clk OUT ar AR The compiler will choose Figure 17 to implement the logic To make the output high true the compiler will invert the logic twice to obtain th
5. Using the Programmable Polarity Control The output programmable polarity con trol in PLDs brings efficiency in logic re duction and control of output polarity to the customers Unfortunately it also brings confusion to customers who are not familiar with the software syntax to properly configure the output polarity This application note shows the proper usage of the popular ABEL and CUPL syntax to configure the output polarity of Atmel PLDs Configuring Polarity with Atmel ABEL 4 x or higher The optimization level best suited for At mel PLDs is the default option reduce by pin and auto polarity This reduction level will take advantage of the polarity control when performing logic optimiza tion one output at a time This will over ride the ISTYPE NEG and ISTYPE POS used in ABEL 3 x source files check the user manual on backward compatibility for detail Therefore the NEG and POS extensions are not rec ommended The following examples have A B and C defined as inputs and OUT or OUT as the output Case 1 Combinatorial no ISTYPE definition or ISTYPE COM Declaration OUT pin 14 assume 14 is an I O pin equations OUT A B C In this case the compiler will consider both Figure 1 on set and Figure 2 off set and automatically select the imple mentation requiring fewer product terms for the same function The outcome is represented by Figure 2 Since Figur
6. e 5 ean a ee Figure 6 eae Figure 7 ABC n Figure 8 ABC AH y Case 8 Registered ISTYPE INVERT Declaration OUT pin 14 ISTYPE invert assume 14 is an I O pin equations OUT A B C OUT c CLK OUT ar ARI1 The compiler will only consider Figure 8 off set because the ISTYPE INVERT overrides the automatic selection In ABEL documentation the pin name will be stripped of the It will replace all pin name references with an addi tional on the right hand side of the equations Pin name OUT Pin name OUT Pin name OUT Pin name OUT ey Me y Note 1 For cases 4 through 8 if you used the dot extension D T etc in your output equations like Out d A B C then the compiler will only consider the Buffer condition on set even when the invert ISTYPE is specified for these outputs The Buffer condition is also only considered when you specify REG_T REG_G REG_JK or REG_SR in your ISTYPE statement AMEL 8 75 AIMEL Configuring Polarity with Internal Nodes Internal nodes do not have programmable polarity control Do notuse any ISTYPE extensions Think of it as positive Case 2 Figure 10 Declaration logic only Case 1 Figure 9 OUT node 50 assume 50 is an internal node Declaration equations OUT node 50 OUT d A B C assume 50 is an inter
7. e correct output polarity Pin name OUT Po Pin name Toma Pin name OUT Pin name OUT 2 The compiler will not compile correctly if the ISTYPE such as Reg_D Buffer Invert Pos or Neg are used Case 2a Registered Low True Output Declaration OUT pin 14 ISTYPE Reg Equations IOUT A B C Equivalent to OUT d A amp B amp IC OUT clk clk OUT ar AR The compiler will choose Figure 18 to implement the logic To make the output low true put a in front of OUT in the logic equations section The compiler will invert the logic three times to obtain the correct output polarity Configuring Polarity with CUPL Polarity is controlled in CUPL at the pin declaration just like other Atmel PLD and CPLD devices CUPL will opti mize the logic equations to match the pin polarity 1 Case 1 Combinatorial Active High Pin 14 OUT OUT A B C The compiler will choose Figure 19 to implement the logic The pin polarity on the pin declaration indicates an active high output CUPL will invert the logic twice to obtain the correct output polarity Figure 19 XOR Polarity Fuse is blown ABC eS E XOR Polarity Fuse is not blown Figure 20 Figure 21 ABTG nq XOR Polarity Fuse is blown H ABC ia sos XOR Polarity Fuse is not blown Figure 22 aD Case 1a
8. es 1 and 2 are each DeMorgan equivalent Erasable Programmable Logic Device of the other either one is logically cor rect Case 2 Combinatorial ISTYPE BUFFER Declaration OUT pin 14 ISTYPE buffer assume 14 is an I O pin equations OUT A B C In this case the compiler will only con sider the on set because the ISTYPE BUFFER overrides the automatic se lection The outcome is represented by Application Note Figure 1 Case 3a Combinatorial ISTYPE INVERT Declaration OUT pin 14 ISTYPE invert assume 14 is an I O pin equations OUT A B C In this case the compiler will only con sider Figure 2 off set because the ISTYPE INVERT overrides the automat ic selection The outcome is represented by Figure 2 Case 3b Combinatorial no ISTYPE definition Declaration OUT pin 14 assume 14 is an I O pin equations OUT A B C The compiler would pick Figure 3 to im plement the logic because it takes fewer product terms In ABEL documentation signals on the right side of the equation do not have as part of their names ABEL preprocessor will remove the from the pin name on the right side of the equation and replace all references on the left side with an additional Logically this does not change any AMEL continued 0424B 8 73 AIMEL Configuring Polarity with Atmel ABEL 4 x or higher Continued
9. load behave differ ently between the two as well In some applications where power up State of a register is not important and it never resets or presets Figures 5 and 6 become identical Only in this case are they logically equivalent When using a registered output always specify the ISTYPE desired 1 The buffer or invert ISTYPE has no effect for combinatorial outputs in Atmel ABEL 5 x Case 5 Registered ISTYPE BUFFER Declaration OUT pin 14 ISTYPE buffer assume 14 is an I O pin equations OUT A B C OUT c CLK OUT ar AR1 The compiler will only consider Figure 5 on set because the ISTYPE BUFFER overrides the automatic selection Case 6 Registered ISTYPE INVERT Be careful Declaration OUT pin 14 ISTYPE invert assume 14 is an I O pin equations OUT A B C OUT c CLK OUT ar AR1 The compiler will only consider Figure 6 off set because the ISTYPE INVERT overrides the automatic selection see Note 1 on Case 4 continued 8 74 CMOS PLD ee Configuring Polarity with Atmel ABEL 4 x or higher Continued Case 7 Registered ISTYPE BUFFER Confusing don t use Declaration OUT pin 14 ISTYPE buffer assume 14 is an I O pin equations OUT A B C OUT c CLK OUT ar ARI The compiler will only consider Figure 7 on set because the ISTYPE BUFFER overrides the automatic selection ABC Figur
10. nal node P a d ar aie B C The above example is the only legal method of assign ing equations to nodes Figure 9 ABC node name OUT Figure 10 ABC d OUT noae name 8 76 CMOS PLD aea a Configuring Polarity with CUPL Note that CUPL has no buffer invert ISTYPE state ment Output polarity is controlled by pin declaration versus equation polarity Case 1 Combinatorial PIN 14 OUTC assume 14 is an I O pin OUTC A B C The compiler would choose Figure 11 It does not choose the better DeMorgan equivalent automatically If your equation does not fit you should check to see if you can rewrite it as PIN 14 OUTC OUTC A amp B amp C Case 2 Combinatorial PIN 14 OUTC assume 14 is an I O pin OUTC A B C The compiler would choose Figure 12 The difference be tween the pin declaration OUTC and the equation name OUTC tells the compiler to have an inverter on the out put and to implement the equations as specified by the equation O Figure 11 A B Case 3 Registered PIN 14 OUTC assume 14 is an I O pin OUTC d A B C OUTC ck CLK The compiler would choose Figure 13 The pin name and the equation name are identical the compiler does not place an inverter on the output Case 4 Registered PIN 14 OUTC assume 14 is an I O pin OUTC d A B C OUTC ck CLK The compiler would choose Figure 14 The difference be
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