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HMC835LP6GE - Hittite Microwave Corporation

1. ty SDI setup time to SCLK Rising Edge 3 ns to SCLK Rising Edge to SDI hold time 3 ns tg SEN low duration 10 ns t4 SEN high duration 10 ns t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns te Recovery Time 10 ns Max Serial port Clock Speed 50 MHz A typical WRITE cycle is shown in Fig 45 a The Master host places 24 bit data d23 d0 MSB first on SDI on the first 24 falling edges of SCLK b the slave HMC835LP6GE shifts in data on SDI on the first 24 rising edges of SCLK c Master places 5 bit register address to be written to r4 r0 MSB first on the next 5 falling edges of SCLK 25 29 d Slave shifts the register bits on the next 5 rising edges of SCLK 25 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 30 32 Hittite reserves chip address a2 a0 000 for HMC835LP6GE Slave shifts the chip address bits on the next 3 rising edges of SCLK 30 32 Master asserts SEN after the 32nd rising edge of SCLK gt a gt Slave registers the SDI data on the rising edge of SEN i Master clears SEN to complete the WRITE cycle For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o e O gt T C5 LLI H 22 UE l A
2. fag MEN ERR rara daa 0 500 1000 1500 2000 2500 3000 3500 4000 OUTPUT FREQUENCY MHz 30 100 300 1000 4000 FREQUENCY MHz 27C 40C 85C 10C 1 85C 6 The HMC835LP6GE features an internal AutoCal process that seamlessly calibrates the HMC835LP6GE when a frequency change is executed Once calibrated at any temperature the calibration setting holds across the entire operating range of the HMC835LP6GE 40 C to 85 C Fig 10 shows that the tuning voltage of the HMC835LP6GE is maintained within a narrow operating range for worst case scenarios where calibration was executed at one temperature extreme and the HMC835LP6GE is operating at the other extreme 7 100 MHz Xtal 50 MHz PD frequency Loop Filter Type 1 with CP and Leakge scaling Phase Noise integrated from 1 kHz to 100 MHz 8 Gain setting Reg 16h 7 6 11 over the operated frequency range in divider mode Reg 16h 10 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION v03 0413 HMC835LP6GE RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E Figure 13 Typical Single Ended Output Power vs Frequency and Temp Max Gain 11 OUTPUT POWER dBm 100 1000 OUTPUT FR
3. CJHillllE _____________ uwcessieece MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Figure 7 Free Running VCO Phase Noise at Figure 8 Free Running VCO Phase Noise at 3600 MH 4100 MHz 40 40 60 60 8 80 b 100 100 2 2 9 120 120 E 140 140 160 160 180 i Lu 180 AL 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 OFFSET KHz OFFSET KHz Figure 10 Typical Tuning Voltage After Calibration 5 Figure 9 Typical VCO Sensitivity 60 KVCO MHz V A o TUNE VOLTAGE AFTER CALIBRATION V 0 1 p p MB 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 TUNING VOLTAGE V VCO FREQUENCY MHz ML core Tuning Cap 15 core Tuning Cap 7 Calibrated at 85C Measured at 85C MH core Tuning Cap7 CL core Tuning Cap 15 heres z L core Tuning Cap 15 core Tuning Cap 15 a Rd Fe MORD Figure 11 Open Loop Phase Noise Figure 12 Single Sideband Integrated vs Temp Phase Noise r 100 0 3 110 Lo e a 120 i 2 N 130 140 150 2 PHASE NOISE dBc Hz INTEGRATED JITTER ps a 160 no 0 054 170 111 100 MHz Offset p
4. Fia 9 2 MHz V ig H gt O O gt t H Z JE 05 l l A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com C Hittite MICROWAVE CORPORATION v03 0413 HMC835LP6GE RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E Typical Performance Characteristics Figure 1 Closed Loop Fractional Phase Noise at 4100 MHz Divided by 1 to 6211 PHASE NOISE dBc Hz 10 100 1000 10000 100000 OFFSET KHz 33 4100 MHz Figure 2 Closed Loop Fractional Phase Noise at 3600 MHz Divided by 1 to 62 100 120 140 PHASE NOISE dBc Hz 160 180 H arene 1 10 100 1000 10000 100000 OFFSET KHz Figure 3 Closed Loop Phase Noise at 3300 MHz Divided by 1 to 62 PHASE NOISE dBc Hz 100000 1 10 100 1000 10000 OFFSET KHz Figure 5 Closed Loop Phase Noise at 3300MHz for different Loop Filter Figure 4 Closed Loop Phase Noise at 3300 MHz Divided by 1 to 62 rss PHASE NOISE dBc Hz 100000 40 80
5. H gt 0 O gt T H za IL 05 l l A CHitiiiE HmosssLPece MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz Figure 45 Serial Port Timing Diagram WRITE 1 8 2 Serial Port READ Operation A typical READ cycle is shown in Fig 46 In general the LD_SDO line is always active during the WRITE cycle During any SPI cycle LD_SDO will contain the data from the current address written in Reg OOh 4 0 If Reg OOh 4 0 is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in progress If it is desired to READ from a specific address it is necessary in the first SPI cycle to write the desired address to Reg OOh 4 0 then the next SPI cycle the desired data will be available on LD_SDO An example of the two cycle procedure to read from any address follows a The Master host on the first 24 falling edges of SCLK places 24 bit data d23 d0 MSB first on SDI as shown in Fig 46 d23 d5 should be set to zero 04 00 address of the register to be READ on the next cycle b the slave HMC835LP6GE shifts in data on SDI on the first 24 rising edges of SCK c Master places 5 bit register address r4 r0 the READ ADDRESS register MSB first on the next 5 falling edges of SCK 25 29 4 0 00000 d Slave shifts the register bits on the next 5 ri
6. HMC960LPA4E HMC9OOLPSE Figure 37 HMC835LP6GE in a typical receive chain For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o O O gt lt H za IE 65 l l A eerttite mmosasLPece MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY Tunable Reference 3 MHz to 100 MHz Crystal Oscillator HMC835LP6GE HMC835LP6GE Figure 38 FRACTIONAL N PLL WITH INTEGRATED VCO used as a tunable reference for HMC835LP6GE Using the HMC835LP6GE with a tunable reference as shown in Fig 38 it is possible to drastically improve spurious emissions performance across all frequencies Example shown in Fig 23 Fig 24 shows that it is possible to achieve spurious emissions as low as 95 dBc Hz at 3 GHz Please contact Hittite s application support to obtain detailed tunable reference configuration Power Supply The HMC835LP6GE is a high performance low noise device In some cases phase noise and spurious performance may be degraded by noisy power supplies To achieve maximum performance and ensure that power supply noise does not degrade the performance of the HMC835LP6GE it
7. lock detect window sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0 5 1 82 2 96 3 256 4 512 5 2048 6 8192 7 65535 10 3 R W Reserved 8 8 Reserved 0 LD disable 1 LD enable 19 12 R W Reserved 8 0 Reserved 0 to 1 transition triggers the training Lock Detect Training is only required after changing Phase Detector frequency After changing PD frequency a toggle Reg 07h 20 from 0 to 1 retrains the Lock Detect 2 0 R W Ikd wincnt max 3 4 11 R W LD Enable 1 1 20 R W Lock Detect Training 9 0 Cycle Slip Prevention enable When enabled if the phase error becomes larger than approx 70 of the PFD period the charge pump gain is increased by approx 6mA for the duration of the cycle 23 22 R W Reserved 2 0 Reserved 21 R W CSP Enable 1 1 2 10 Reg 08h Analog EN Register DEFAULT 1BFFF h Reserved Reserved 0 Pin LD SDO disabled 1 and RegFh 7 1 Pin LD SDO is always driven this is 5 B W i Purpose Output Pin 1 14 required for use of port 1 and RegFh 7 0 LDO_SPI is off if chip address not equal to 000 b allowing a shared SPI with other compatible parts 9 6 R W Reserved 4 15d Reserved 0 VCO Buffer and Prescaler Bias Disable 10 R W Eus Proscaler 1 1d 4 VCO Buffer and Prescaler Bias Enable Only applies to External VCO 20
8. gt a o n o o oo n ped VDDCP 1 CONTROL lt 30 VTUNE 2 29 2 cei 3 H COL as 1 CcP2 4 J V 27 101_ RVDD 5 L 1 26 1 1_ XREFP 6 GR N pre 25 CHIP EN 2 DVDD 7 24 AL 23 N C 9 22 N C 10 21 N C I ie fe fel fl PACKAGE S S amp S 8 35 amp 8 2 2 BASE z z 0 n a y o GND Dod X gt 9 o 5 N a gt lt gt lt gt lt 2 2 2 lt For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY General Description The HMC835LP6GE is a low noise wide band Fractional N PLL that features an integrated VCO with a fundamental frequency of 2050 to 4100 MHz and an integrated VCO Output Divider divide by 2 4 6 60 62 that together enable the HMC835LP6GE to generate frequencies from 33 MHz to 4100 MHz Integrated Phase Detector PD and a delta sigma modulator capable of operating at up to 100 MHz enable wider loop bandwidths faster frequency changes along with excellent spectral performance Two independent RF outputs with independent gain contr
9. m is 0 2 4 or 5 as determined by Reg OAh 14 13 The expected number of VCO counts V is given by V floor N 2 EQ 4 The nominal VCO frequency measured fycom is given by n D onm V ET 2 R EQ 5 where the worst case measurement error ferr is ni m za 2 EQ 6 Reg02 CALIBRATION WINDOW Tmmt RTytai x2 RegA 14 13 Start Stop RegA 2 0 0 2 4 5 0 1 2 5 5 6 7 8 50 MHz Max for V FSM VSPI Clocks c Figure 41 VCO Calibration A 5 bit step tuned VCO for example nominally requires 5 measurements for calibration worst case 6 measurements and hence 7 VSPI data transfers of 20 clock cycles each Total calibration time worst case is given by 128 OT pp 2 7 20T poy EQ 7 cal or equivalently T a T 6R 2 140 3 128 2 EQ 8 For guaranteed hold of lock across temperature extremes the resolution should be better than 1 8 the frequency step caused by a VCO sub band switch change Better resolution settings will show no improvement 1 2 1 411 VCO AutoCal Example The HMC835LP6GE must satisfy the maximum fpg limited by the two following conditions a N 16 fin N gt 20 0 fiac where N fycofoq b fga lt 100 MHz For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support
10. 1 Enables the PD DN output see also Reg OBh 10 8 7 R W Reserved 2 0 Reserved Program to Od 9 R W Force CP UP 1 0 Forces CP UP output on if is not forced down Use for Test only 10 R W Force CP DN 1 0 Forces CP DN output on if CP is not forced up Use for Test only Force CP Mld Rail Use for Test only if Force CP UP or Force CP i1 RW Force Mig Hal B DN are enabled they have precedence 23 12 R W Reserved 12 cu Reserved 2 14 Reg OCh Exact Frequency Register Comparison Frequency divided by the correction rate Must be an integer Frequencies at exactly the correction rate will have zero frequency error Only works in modulator Mode B 3rd order recommended modulator type in Reg06 3 2 Reg OCh must be 0 if 23 0 R W Number of Channels per Fpd 24 0 using ohter DSM type 0 Disabled 1 Invalid gt 2 valid max 224 1 FFFFFFh 16 777 215d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 ROHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 15 Reg OFh GPO Register Select signal to be output to SDO pin when enabled DEFAULT LOCK DETECT Data from RegOF 5 Lock Detect
11. 11 R W Reserved 10 55d Reserved 21 R W High Frequency Reference 1 0 Program to 1 for XTAL gt 200 MHz 0 otherwise Output Logic Level on LD SDO pin 22 R W SDO Output Level 1 0 0 1 8 V Logic Levels 1 DVDDSV Logic Level 23 R W Reserved 1 1d Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o e O gt t C5 LLI H Z UE l A CJHitlllE uwcessieece MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 11 Reg 09h Charge Pump Register DEFAULT 527264 h Charge Pump DN Gain Control 20 pAystep Affects fractional phase noise and lock detect settings Od 7 OHA 6 0 R W CP DN Gain 7 64h 1d 20 pA 2d 40 uA 127d 2 54mA Default 2mA Charge Pump UP Gain Control 20 pA per step Affects fractional phase noise and lock detect settings 1 9 0 13 7 R W CP UP Gain 7 64h 1d 20 pA 2d 40 pA 127d 2 2 54mA Default 2mA Charge Pump Offset Control 5 pA step Affects fractional phase noise and lock detect settings 0 0 20 14 R W Offset Magnitude 7 81d 1 5 2d 10 pA 127d 635 pA Default 405 21 R W Offset UP enable 1 0 Sets D
12. 16 3 Input Crystal Reference 32 11 R W AutoCal Disable 1 0 16 15 R W Reserved 2 0 Reserved 0 Does not attempt to relock if lock is lost 17 R W Auto relock one Try 1 0 1 Attempts to relock if Lock Detect fails for any reason Only tries once 23 18 R W Reserved 5 0 Reserved H gt op e gt t C5 LLI H Z UE l A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt O gt e t C5 LLI H Z JE 65 l mM CJHillllE uwcessieece MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 13 Reg OBh PDICP Register DEFAULT 78061 h 3 0 R W Reserved 4 1 Reserved Inverts the PD polarity program to O 0 Use with a positive tuning slope VCO and Passive Loop Filter default when using internal VCO 4 RIW Pi Phare Selget 9 1 Use with a Negative Slope VCO or with an inverting Active Loop Filter with a Positive Slope VCO Only recommended when using an External VCO and an active loop filter 5 R W PD Up Output Enable 1 1 Enables the PD UP output see also Reg OBh 9 6 R W PD Down Output Enable 1
13. Channel spacing 240 KHz Exact Frequency Mode ON 12 122 88 Xtal PD 61 44 Loop Filter Type 1 from Table 1 is used Channel spacing 240 KHz Exact Frequency Mode OFF 13 100 MHz Xtal PD Frequency 50 MHz Loop Filter Type 3 from Table 1 is used CP 2 54 mA Set to Integer Mode For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt ep e O gt lt C5 LLI H 22 HE A H gt 0 O gt T am H za IL 65 l l A C Hittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz Figure 20 Typical Spurious Emissions at 3000 1 MHz Fixed Reference EARTH FRIENDLY Figure 19 Low Frequency Performance 120 20 40 60 80 100 120 PHASE NOISE dBc Hz o 140 PHASE NOISE dBc Hz a 3 160 180 0 1 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 OFFSET kHz OFFSET kHz Carrier Frequency 33 0645 MHz Carrier Frequency 50 MHz Carrier Frequency 100 MHz Figure 21 Typical Spurious Emissions at 3000 1 MHz Tunable Reference Figure 2
14. Delta Sigma modulator immediately when the register is written with no adjustment to the VCO Small steps in frequency in fractional mode with AutoCal enabled Reg OAh 11 0 usually only require a single write to the fractional register Worst case 3 Main Serial Port transfers to the HMC835LP6GE could be required to change frequencies in fractional mode If the frequency step is small and the integer part of the frequency does not change then the integer register is not changed In all cases in fractional mode it is necessary to write to the fractional register Reg 04h for frequency changes Registers Required for Frequency Changes in Integer Mode A change of frequency in integer mode Reg O6h 11 0 requires Main Serial Port writes to 1 VCO register e Reg 15h only required for manual control of VCO if Reg OAh 11 1 AutoCal disabled e 16h is required to change the VCO Output Divider value if needed 2 The integer register Reg 03h e In integer mode an integer register write triggers AutoCal if Reg OAh 11 0 and is loaded into the prescaler automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the VCO Normally changes to the integer register cause large steps in the VCO frequency hence the VCO switch settings must be adjusted AutoCal enabled is the recommended method for integer mode frequency changes
15. For use with a NEGATIVE slope VCO or with a ACTIVE loop filter Use HMC835LP6GE as PLL with off board external VCO The evaluation board is provided with external VCO input ports J10 EXT VCO Pand J11 EXT_VCO_N Prepopulated loop filter can be modified according to external VCO characteristics For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz HMC835LP6GE Application Information Large bandwidth 33 MHz to 4100 MHz excellent phase noise and spurious performance and phase noise floor 165 dBc Hz coupled with a high level of integration make the HMC835LP6GE ideal for a variety of applications as an RF or IF stage LO HMCB835LP6GE uf 7 gt N gt HMC83SLP6GE HMC1044LP3E HMCSOOLPSE HMC795LPSE Figure 36 HMC835LP6GE in a typical transmit chain HMC835LP6GE HMCAD1520 CMIO V H gt ep O O gt t C5 LLI H 22 UE l A 9 PLL HMC835LP6GE HMC1044LP3E HMC597LP4E
16. If AutoCal is disabled Reg OAh 11 1 a prior knowledge of the correct VCO switch setting and the corresponding adjustment to the VCO is required before executing the integer frequency change VCO Output Mute Function The HMC835LP6GE features an intelligent output mute function with the capability to disable the VCO output while maintaining the PLL and VCO subsystems fully functional The mute function is automatically controlled by the HMC835LP6GE and provides a number of mute control options including 1 Always mute Reg 16h 5 0 Od This mode is used for manual mute control 2 Automatically mute the outputs during VCO calibration Reg 17h 7 1 that occurs during output frequency changes This mode can be useful in eliminating any out of band emissions during freqeuncy changes and ensuring that the system emits only desired frequencies It is enabled by writing Reg 17h 7 1 Typical isolation when the HMC835LP6GE is muted is always better than 60 dB and is 30 dB better than disabling the output buffers of the HMC835LP6GE via Reg 17h 5 4 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v E 1 3 1 3 1 1 3 1 1 FRACTIONAL N PLL WITH INTEGRATED VCO
17. Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable EKIT01 HMC835LP6G CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software Hittite PLL Design Software For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz Changing Evaluation Board Reference Frequency amp CP Current Configuration The evaluation board is provided with a 50 MHz on board reference oscillator and Type 1 loop filter configuration shown in Table 1 186 kHz bandwidth The default register configuration file included in the Hittite PLL Evaluation software sets the comparison frequency to 50 MHz R 1 ie Reg 02h 1 As with all PLL s and PLL with Integrated VCOs modifying the comparison frequency or Charge Pump CP current will result in changes to the loop dynamics and ultimately phase noise performance When making these changes there are several items to keep in mind e CP Offset Current setting Refer to Section 1 3 1 e 10 Configuration Refer to Section 1 3 5 To redesign the loop filter for a particular application download Hittite s PLL Design software tool by clicking on the Software Download l
18. Output Lock Detect Trigger Lock Detect Window Output Ring Osc Test Pullup Hard from CSP PullDN hard from CSP Reserved Reference Buffer Output 9 Ref Divider Output 10 VCO divider Output 11 Modulator Clock from VCO divider 12 Auxiliary Clock 13 Aux SPI Clock 14 Aux SPI Enable 15 Aux SPI Data Out 16 PD DN 17 PD UP 18 SD3 Clock Delay 19 SD3 Core Clock 20 AutoStrobe Integer Write 21 Autostrobe Frac Write 22 Autostrobe Aux SPI 23 SPI Latch Enable 24 VCO Divider Sync Reset 25 Seed Load Strobe 26 29 Not Used 30 SPI Output Buffer En 31 Soft RSTB 5 R W GPO Test Data 1 0 1 GPO Test Data when Select 0 SNOARONDZO 4 0 R W GPO 5 1 H e O gt t am C5 LLI H Z uH A 1 Outputs GPO data only 6 R W Prevent Auto mux SDO 0 0 Automuxes between SDO data 7 R W Reserved 1 0 Reserved Program to 1 if external pull ups are used on the SDO line 8 FUME Disable PRET 0 Prevents conflicts on the SPI bus Program to 1 if external pull downs are used on the SDO line Prevents conflicts on the SPI bus 9 R W Disable NFET 1 0 23 10 R W Reserved 14 0 Reserved 2 1 Reg 10h Tuning Register Read Only 80h VCO selection resulting from AutoCalibration 7 0 R VCO Tune Curve 8 0 0 maximum frequency 1111 1111 b minimum frequency Indicates if the VCO tuning is
19. Select 1 1 1 R W SPI Chip Enable 1 1 keeps internal bias generators on ignores Chip enable 2 R W Keep Bias On 1 0 control 3 R W Keep PFD Pn 1 0 keeps PFD circuit on ignores Chip enable control 4 R W Keep CP On 1 0 keeps Charge Pump on ignores Chip enable control keeps Reference buffer block on ignores Chip enable 5 R W Keep Reference Buffer ON 1 0 control 6 R W Keep VCO on 1 0 keeps VCO divider buffer on ignores Chip enable control 7 R W Keep GPO Driver ON 1 0 keeps GPO output Driver ON ignores Chip enable control 9 8 R W Reserved 2 0 reserved 2 4 02h REFDIV DEFAULT 1h Reference Divider R Value EQ 8 13 0 R W rdiv 14 1 1 max max 214 1 3FFFh 16383d Divider Integer part used in all modes see EQ 10 Fractional Mode min 20d 18 0 R W Integer Setting 19 max 219 4 7FFFCh 524 284d Integer Mode min 16d max 219 1 7FFFFh 524 287d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H e O gt t C5 LLI H Z uH H O O gt lt H Z IE l l CJHitlllE uw
20. Settling After Frequency Change Manual Calibration s Settling Time to lt 5 Degrees Phase Error PHASE ERROR DEGREES iNote Loop Filter Bandwidth 186 kHz Loop Filter Phase Margin 48 degrees This result is directly affected by loop filter design Faster settling time tis possilbe with wider loop filter bandwidth and lower margin 0 20 40 60 80 100 TIME us 22 The HMC835LP6GE features an internal AutoCal process that seamlessly calibrates the HMC835LP6GE when a frequency change is executed Typical frequency settling time that can be expected after any frequency change Reg 03h or Reg 04h writes is shown in Fig 31 with AutoCal enabled Reg 11 0 Frequency hop of 5 MHz is shown in Fig 31 however the settling time is independent of the size of the frequency change Any size frequency size hop will have a similar settling time with AutoCal enabled Loop filter BW 186 kHz Loop Filter Type 1 in Table 1 23 For applications that require fast frequency changes the HMC835LP6GE supports manual calibration that enables faster settling times Manual calibration needs to be executed only once for each individual HMC835LP6GE at any temperature and is valid across all temperature operating range of the HMC835LP6GE More information about manual calibration is available in section 1 2 1 6 Frequency hop of 5 MHz is shown in Fig 33 and Fig 34 however the settling time is i
21. as a static port along with Reg 14h 3 1 Aux GPO Values 3 0 3 Output values can be set indivually when Reg 10h 0 1 0 1 8 V output out of the Auxiliary GPO pins when Reg 10h 0 1 Aux GPO 3 3 V 1 m 1 3 3 V output out of the Auxiliary GPO pins when Reg 10h 0 1 Reserved 4 1 Reserved When set CHIP EN pin is used as a trigger for phase synchronization Can be used to synchronize multiple 1 HMC835LP6GE or to along with the Reg 1Ah value to phase step the output Exact Frequency Mode must be enabled Phase Sync 1 Option to send GPO multiplexed data ex Lock Detect to one of the auxiliary outputs 0 None 1 to 0 2 to 1 3 to 2 11 10 Aux SPI GPO Output 2 When disabled 0 Outputs Z 0 1 Outputs stay driven 2 Outputs driven to high 3 Outputs driven to low 13 12 Aux SPI Outputs 2 23 14 Reserved 10 0 Reserved 2 21 Reg 15h Manual VCO Config Register Default F48A0 h rane 1 VCO subsystem manual calibration enabled 0 ManyalGalibration 1 0 VCO subsystem manual calibration disabled 5 1 R W Capacitor Switch Setting 5 Vs capacitor switch setting 8 6 R W Manual VCO Selection 3 2 selects the VCO core sub band 1 Manual VCO tuning enabled 9 R W Manual VCO Tune Enable 1 0 0 Manual VCO tuning disabled 15 10 R W Reserved 6 Ted Reserved 12h Enable Auto Scale CP cur 1 Automatically scale CP current bas
22. cleanly 4 R W Synchronous SPI Mode 1 0 Exact Frequency Mode 1 Exact Frequency Mode Enabled 5 R W Enable 1 o 0 Exact Frequency Mode Disabled 6 R W Reserved 1 0 Reserved 0 Use Modulator Required for Fractional Mode 1 Bypass Modulator Required for Integer Mode Note When enabled fractional modulator output is ignored but 7 R W Fractional Bypass 1 0 fractional modulator continues to be clocked if Reg O6h 11 1 This feature can be used to test the isolation of the digital frac tional modulator from the VCO output in integer mode 1 loads the modulator seed start phase whenever the fractional 8 R W Autoseed EN 1 1 register Reg 04h is written 0 when fractional register Reg 04h write changes frequency modulator starts at previous value phase 10 9 R W Reserved 2 3 Reserved 11 R W Delta Sigma Modulator 1 1 0 Disable DSM used for Integer Mode Enable 1 Enable DSM Core required for Fractional Mode 23 12 R W Reserved 12 ies Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 ROHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 9 Reg 07h Lock Detect Register DEFAULT 200844 h
23. different Gain settings from 0 to 3 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o e O gt T g LLI H 22 UE l A CJHillllE ___________ uwcessieece MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Electrical Specifications Continued 100 MHz Offset E dBc Hz Figure of Merit FOM Floor Integer Mode Fig 28 Normalized to 1 Hz 230 dBc Hz Floor Fractional Mode Fig 28 Normalized to 1 Hz 227 dBc Hz Flicker Both Modes Fig 28 Normalized to 1 Hz 268 dBc Hz VCO Characteristics Measured with 2 5 V VCO Tuning Sensitivity at 3862 MHz 15 MHz V on VTUNE see Fig 9 Measured with 2 5 V VCO Tuning Sensitivity at 3643 MHz 14 5 MHz V on VTUNE see Fig 9 ais Measured with 2 5 V VCO Tuning Sensitivity at 3491 MHz 16 2 MHz V on VTUNE see Fig 9 m Measured with 2 5 V VCO Tuning Sensitivity at 3044 MHz 14 6 MHz V on VTUNE see Fig 9 m Measured with 2 5 V VCO Tuning Sensitivity at 2558 MHz 15 4 MHz V on VTUNE see Fig 9 Measured with 2 5 V VCO Tuning Sensitivity at 2129 MHz 14 8 MHz V on VTUNE seeFig 9 Measured with 2 5 V VCO Supply Pushing
24. on using the GPO pin while in SPI Mode please see section 1 8 Serial Port Overview For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION 03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 0 PLL Register Map 2 1 ii oon ID DEFAULT C7701A h 23 0 chip ID 24 C7701A Chip ID Number 2 2 iia 00h AdoressiRST dis siad aiiis Only 4 0 WO Read Address 5 WRITE ONLY Read Address for next cycle 5 WO Soft Reset 1 WRITE ONLY Soft Reset set to 0 during operation 23 6 WO Not Defined 18 Not Defined set to write Oh 2 3 Reg 01h Chip Enable Register DEFAULT 3h 1 Chip enable via CHIP EN pin Reg 01h 0 1 and CHIP EN pin low places the HMC835LP6GE in Power Down Mode 0 Chip enable via SPI Reg 01h 0 0 CHIP EN pin ignored see Power Down Mode description for more details Controls Chip Enable Power Down if Reg O1h 0 0 Reg O1h 0 20 and Reg 01h 1 1 chip is enabled CHIP EN pin don t care Reg 01h 0 0 and Reg 01h 1 0 chip disabled CHIP EN pin don t care see Power Down Mode description for more information 0 R W Chip Enable Pin
25. registers with the value written via Reg 15h 8 1 immediately Registers required for Frequency Changes in Fractional Mode A large change of frequency in fractional mode Reg O6h 11 1 may require Main Serial Port writes to 1 The integer register intg Reg 03h only required if the integer part changes 2 Manual VCO Tuning Reg 15h only required for manual control of VCO if Reg OAh 11 1 AutoCal For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt 0 O O gt t C5 LLI H Z UE l A H gt 0 O gt lt H za IE 65 l l A mmosasLPece MICROWAVE CORPORATION v03 0413 RoHS v E 1 2 3 1 2 4 FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz disabled 3 VCO Divide Ratio and Gain Register e Reg 16h 5 0 is required to change the VCO Output Divider value if needed e 16h 10 6 is required to change the Output Gain if needed 4 The fractional register Reg 04h The fractional register write triggers AutoCal if Reg OAh 11 0 and is loaded into the Delta Sigma modulator automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the fractional frequency change is loaded into the
26. that AutoCal typically adds about 8 6 us to the normal time to achieve frequency lock Hence AutoCal should be used for all but the most extreme frequency hopping requirements Table 3 AutoCal Example with F 50 MHz 1 mz 0 0 0 1 0 02 4 92 25 MHz 1 1 2 0 04 5 04 12 5 MHz 2 2 4 0 08 5 28 6 25 MHz 3 3 8 0 16 5 76 3 125 MHz 4 5 32 0 64 8 64 781 kHz 5 6 64 1 28 12 48 390 kHz 6 7 128 2 56 20 16 195 kHz 7 8 256 5 12 35 52 98 kHz Manual VCO Calibration for Fast Frequency Hopping If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating the VCO in advance and storing the switch number vs frequency information in the host This can be done by initially locking the HMC835LP6GE on each desired frequency using AutoCal then reading and storing the selected VCO switch settings The VCO switch settings are available inReg 15h 8 1 after every AutoCal operation The host must then program the VCO switch settings directly when changing frequencies Manual writes to the VCO switches are executed immediately as are writes to the integer and fractional registers when AutoCal is disabled Hence frequency changes with manual control and AutoCal disabled requires a minimum of two serial port transfers to the HMC835LP6GE once to set the VCO switches and once to set the PLL frequency If AutoCal is disabled Reg OAh 11 1 the VCO will update its
27. the switching charge pump set in Reg O9h 6 0 13 7 CP Current 2 5 mA H gt 0 O gt lt H za IE 65 l l A CP Current 2 mA RECOMMENDED OFFSET CURRENT uA 0 20 40 60 80 100 PHASF DETECTOR FREOI IENCY MHzY Recommended CP offset current vs PD frequency for typical CP gain currents Calculated using EQ 9 The required CP offset current should never exceed 25 of the programmed CP current It is recommended to enable the Up Offset and disable the Down Offset by writing Reg 09h 22 21 10 b Operation with CP offset influences the required configuration of the Lock Detect function Refer to the description of Lock Detect function in section 1 3 5 When operating with PD frequency gt 80MHz the CP Offset current should be disabled for the frequency change and then re enabled after the PLL has settled If the CP Offset current is enabled during a frequency change it may not lock For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz RTH FRIENDLY x 7 3 1 4 Phase Detector Functions Phase detector register Reg OBh allows manual access to control s
28. 2 Typical Spurious vs Offset from 3 GHz Fixed vs Tunable Reference 20 50 tr sans 40 f Quay ita essc eee a m x 80 a E En AE EE EE i 9 00 9 120 RU UE EE E RUNE 140 L 00 160 180 100 1 10 100 1000 10000 100000 3GHz 1kHz 3GHz 10kHz 3GHz 100kHz 3GHz 1000kHz OFFSET kHz Figure 23 Reference Input Sensitivity Square Wave OUTPUT FREQUENCY Fixed 50 MHz Reference Tunable Reference Figure 24 Reference Input Sensitivity Sinusoidal Wave 220 222 224 5 Ky um i 226 E g E 228 Z 5 3 230 E 232 234 15 12 9 6 3 0 3 REFERENCE POWER dBm REFERENCE POWER dBm 14 MHz Square Wave 50 MHz Square Wave 14 MHz sin 50 MHz sin 25 MHz Square Wave 100 MHz Square Wave 25 MHz sin 400 MHz sin 14 100 MHz Xtal PD Frequency 50 MHz Loop Filter Type 1 from Table 1 is used The plot shows an integer boundary spur inside the loop filter bandwidth 15 The tunable reference is used to change the reference frequency from 50 MHz in Fig 22 to 47 5 MHz in Fig 23 in order to distance the integer boundary spur away from the carrier frequency so that it is filtered by the loop filter Loop Filter Type 1 from Table 1 is used 16 The plot is generated by recoding the magnitude of the largest spur only at any offset at
29. 3 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTI Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device 0 3 V to 455 V This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating 65 C to 150 C conditions for extended periods may affect device 150 reliability Absolute Maximum Ratings D DVD VECHE 0 3 V to 43 6 V 0 3 V to 45 5 V 40 C to 85 C 9 C W 260 C 40 sec Class 1B Recommended Operating Conditions Temperature Junction Temperature 17 125 C Ambient Temperature 40 85 C Supply Voltage AVDD RVDD DVDD VCCPD VCCHF VCCPS 3 1 3 3 3 5 V VPPCP VDDLS VCC1 VCC2 V DDCP 4 8 5 5 2 V H O gt lt H Z IE l l aL 1 Layout design guidlines set out in Qualification Test Report are strongly recommended For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line a
30. 33 4100 MHz PLL Overview Charge Pump CP amp Phase Detector PD The Phase detector PD has two inputs one from the reference path divider and one from the RF path divider When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each other We refer to the frequency of operation of the PD as fpa Most formulae related to step size delta sigma modulation timers etc are functions of the operating frequency of the PD fpa fpa is also referred to as the comparison frequency of the PD The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals The output current varies linearly over a full 27 radians X360 of input phase difference Charge Pump A simplified diagram of the charge pump is shown in Fig 42 The CP consists of 4 programmable current sources two controlling the CP Gain Up Gain Reg O9h 13 7 and Down Gain Reg O9h 6 0 and two controlling the CP Offset where the magnitude of the offset is set by Reg 09h 20 14 and the direction is selected by Reg 09h 21 1 for up and Reg 09h 22 1 for down offset CP Gain is used at all times while CP Offset is only recommended for fractional mode of operation Typically the CP Up and Down gain settings are set to the same value Reg 09h 13 7 Reg 09h 6 0 UP Off
31. 44x108 3072d C00h gt J sed r00109 61 44105 20000 3 To program Reg 04h the closest integer N boundary frequency fy that is less than the desired VCO frequency fyco must be calculated fy fpp Njyr Using the current example fy fopx Nr 45 61 44 108 2764 8 MHZ 224 f f 224 2800 2 x10 2764 8 106 96665600 938000h 61 44 x108 Then Reg04h ceil PD 1 3 7 7 7 Hittite Exact Frequency Channel Mode If it is desirable to have multiple equally spaced exact frequency channels that fall within the same interval ie fy lt fycoy lt fy j where fyco is shown in Fig 44 and 1 lt k x 224 it is possible to maintain the same integer N Reg 03h and exact frequency register Reg OCh settings and only update the fractional register Reg 04h setting The Exact Frequency Channel Mode is possible if EQ 16 is satisfied for at least two equally spaced adjacent frequency channels i e the channel step size To configure the HMC835LP6GE for Exact Frequency Channel Mode initially and only at the beginning integer Reg 03h and exact frequency Reg OCh registers need to be programmed for the smallest fyco frequency fyco in Fig 44 as follows 1 Calculate and program the integer register setting Reg 03h Ny floor fyco fgp where is shown in Fig 44 and corresponds to minimum channel VCO frequency Then the lower integer boundar
32. 6GE RoHS compliant Low Stress Injection Molded Plastic 100 matte Sn MSL1 XXXX 1 4 Digit lot number XXXX For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o e O gt T am C5 LLI H 22 A H gt O gt t C5 LLI H Z IE 65 l l A MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY Evaluation PCB eseece ee see The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The evaluation circuit board shown is available from Hittite upon request Evaluation PCB Schematic To view this Evaluation PCB Schematic please visit www hittite com and choose HMC835LP6GE from the Search by Part Number pull down menu to view the product splash page Evaluation Order Information HMC835LP6GE Evaluation PCB USB
33. 78 250 3343 or apps hittite com H gt ep O O gt t C5 LLI H 22 UE l A H gt ep O O gt e T H za IE 65 l l A eerttite mmosasLPece MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY Use HMC835LP6GE as PLL with external VCO Configuration In general in order to configure HMC835 with external VCO Reg17h needs to be configured to disable the on chip VCO and VCO to PLL path while enable external buffer CP2 link and External IO switch The recommended value for Reg 17h is to be set as 3157d Reg 19h 20 19 is also available to adjust the EXT VCO amp Input depending on the external VCO RF output level Use HMC835LP6GE as PLL with on board external VCO In order to demonstrate the ablity of using HMC835LP6GE as a PLL alone with external VCO the evaluation board is provided with a on board external VCO HMC384LP4E and Loop Filter Type 4 configuration shown in Table 1 17 kHz bandwidth A 0 resister on C40 and a 0 001 uF capcitor on C58 need to be soldered in order to convert the standard HMC835LP6GE evaluation board to work with on board external VCO configuration Jumper J4 needs to be put on for HMC384LP4E power supply Reg OBh 4 PFD invert needs to be set to 1 in order to work with on board active loop filter O For use with positive tuning slope VCO and PASSIVE loop filter 1
34. AC coupled externally Q 7 DVDD Digital supply 3 3 V nominal 8 9 10 11 H 12 21 22 N C No Connect lt 23 24 13 AUXO 500 Auxiliary SDO digital output t 14 AUX1 SCK Auxiliary SCK digital output 15 AUX2 SEN Auxiliary SEN digital output H 16 VDD1 Analog supply 3 3 V nominal Z 17 GND Ground T 18 LO2 P RF Output LO2 P positive side used for differential or dual outputs only 19 LO2_N RF Output LO2_N negative side used in single ended differential or dual output mode m 20 GND Ground z 25 CHIP EN Chip Enable input 6A 26 LO1 N RF output LO N negative side used for single ended differential or dual output mode 27 LO1 P RF output LO P positive side used for differential or dual outputs only Q 28 VCC1 VCO analog supply 1 29 VCC2 VCO analog supply 2 30 VTUNE VCO varactor tuning port input 31 SEN Serial Port Enable CMOS logic input 32 SDI Serial Port Data CMOS logic input 33 SCK Serial Port Clock CMOS logic input 34 LD SDO Lock Detect or Serial Data Output CMOS logic output 35 EXT VCO N External VCO negative input 36 EXT VCO P External VCO positive input 37 VCCHF Analog supply 3 3 V nominal 38 VCCPS Analog supply Prescaler 3 3 V nominal 39 VCCPD Analog supply Phase Detector 3 3 V nominal 40 VDDLS Analog supply Charge Pump 5 0 V nominal For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 337
35. ANALOG HittiLc DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK H gt o O O gt lt g LLI H za HE 1 A C Hittite MICROWAVE CORPORATION v03 0413 RoHS v E Features Wideband 33 4100 MHz Maximum Phase Detector Rate 100 MHz Low Phase Noise 110 dBc Hz in Band Typical PLL FOM 230 dBc Hz Integer Mode 227 dBc Hz Fractional Mode lt 160 fs Integrated RMS Jitter 1 kHz to 100 MHz Low Noise Floor 165 dBc Hz 2 Differential RF outputs Typical Applications MIMO Radio Architectures Cellular Infrastructure Cellular backhaul Communication Test Equipment CATV Equipment HMC835LP6GE FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz External LO Input Exact Frequency Mode 0 Hz Fractional Frequency Error Programmable RF Output Phase Output Phase Synchronous Frequency Changes Output Phase Synchronization Programmable Output Phase RF Output Mute Function 40 Lead 6x6 mm SMT Package 36 e Phased Array Applications DDS Replacement Functional Diagram n z o uo a uo 2 g S MI a a 1 1 7 a o o o E E 1 x z a xXx xXx Q o a gt gt gt
36. EQUENCY MHz 85C 40C 27C Figure 15 Fractional Spurious Performance at 904 MHz Exact Frequency Mode ON 20 PHASE NOISE dBc Hz 1 10 100 1000 10000 100000 OFFSET kHz Figure 17 Fractional Spurious Performance at 2646 96 MHz Exact Frequency Mode ON 40 60 100 120 PHASE NOISE dBc Hz 140 160 Ago 1 1000 10000 100000 OFFSET KHz 33 4100 MHz Figure 14 Typical Output Power vs Frequency and Gain Single Ended is OUTPUT POWER dBm o a 500 1000 1500 2000 2500 3000 3500 4000 OUTPUT FREQUENCY MHz Gain 00 Gain 10 Gain 01 Gain 11 Figure 16 Fractional Spurious Performance at 1804 MHz Exact Frequency Mode ON PHASE NOISE dBc Hz 1 10 100 1000 10000 100000 OFFSET kHz Figure 18 Fractional Spurious Performance at 2646 96 MHz Exact Frequency Mode OFF 121 PHASE NOISE dBc Hz 100 120 140 160 180 1 40 60 80 10 100 1000 10000 100000 OFFSET KHz 9 For overall power flatness accorss the operating frequency range choose Gain setting 11 in divider mode and Gain setting 01 in fo mode 10 100 MHz Xtal PD 50 MHz Channel Spacing 200 KHz Loop Filter Type 1 from Table 1 Exact Frequency Mode on 11 122 88 Xtal PD 61 44 Loop Filter Type 1 from Table 1 is used
37. Fig 44 fall between the same integer N boundaries fy lt fycox lt fy 1 In that case ceil 96665600 938000h 224 2800 3x10 2764 8x10 6144x108 9693867d 93EAABh and soon a x Reg 04h ceil Seed Register The start phase of the fractional modulator digital phase accumulator DPA may be set to any desired phase relative to the reference frequency The phase is programmed in Reg 1Ah and Exact Frequency Mode is required Phase 27 x Reg1Ah 22 via the seed register Reg 1Ah 23 0 The HMC835LP6GE will automatically reload the start phase seed value into the DPA every time a new fractional frequency is selected Certain zero or binary seed values may cause spurious energy correlation at specific frequencies For most cases a random or non zero non binary start seed is recommended Soft Reset amp Power On Reset The HMC835LP6GE features a hardware Power on Reset POR All chip registers will be reset to default states approximately 250 us after power up The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg 00h Power Down Mode Power down the HMC835LP6GE by pulling CEN pin pin 17 low assuming no SPI overrides Reg O1h 0 1 This will result in all analog functions and internal clocks disabled Current consumption will typically drop below 10 pA in Power Down state The serial port will still respond to normal communication in Power Down mode It is possible to ignore t
38. Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v E 1 2 1 5 1 2 2 FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz Suppose the HMC835LP6GE output frequency is to operate at 2 01 GHz Our example crystal frequency is 50 MHz R 1 and m 0 Fig 41 hence 20 ns 50 MHz Note when using AutoCal the maximum AutoCal Finite State Machine FSM clock cannot exceed 50 MHz see Reg OAh 14 13 The FSM clock does not affect the accuracy of the measurement it only affects the time to produce the result This same clock is used to clock the 16 bit VCO serial port If time to change frequencies is not a concern then one may set the calibration time for maximum accuracy and therefore not be concerned with measurement resolution Using an input crystal of 50 MHz R21 and fpd 50 MHz the times and accuracies for calibration using EQ 6 and EQ 8 are shown in Table 3 Where minimal tuning time is 1 8 of the VCO band spacing Across all VCOs a measurement resolution better than 800 kHz will produce correct results Setting m 0 5 provides 781 kHz of resolution and adds 8 6 us of AutoCal time to a normal frequency hop Once the AutoCal sets the final switch value 8 64 us after the frequency change command the fractional register will be loaded and the loop will lock with a normal transient predicted by the loop dynamics Hence as shown in this example
39. RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY Table 7 SPI Read Timing Characteristics 801 setup time Rising Edge ns SCK Rising Edge to SDI hold time 3 ns SEN low duration 10 ns SEN high duration 10 ns SCK Rising Edge to SDO time 8 2ns 0 2ns pF ns Recovery Time 10 ns SCK 32 Rising Edge to SEN Rising Edge 10 ns H gt 0 O O gt t C5 LLI H Z UE l A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o O O gt Lu T am H za IL 05 l A calite MICROWAVE CORPORATION v03 0413 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz FIRST CYCLE 1 18 19 20 24 25 29 30 31 32 uut t t7 2 te SDI d5 ao r4 r3 2 al a0 x READ Address Register Address 00000 Chip Address 000 ts LD_SDO AO ECE EEE TRI STATE SEN LD GPO SECOND CYCLE SCK SDI SEN Note Read back on LD_SDO can function without SEN Hoewer SEN rising edge is required to return the LD_SDO to the GPO state Figure 46 Serial Port Timing Diagram READ For more information
40. Settling After Frequency Change AutoCal Enabled 21 2 02 2 015 2 01 2 005 FREQUENCY GHz 1 995 SERE te Loop Filter Bandwidth 186 kHz Loop Filter Phase Margin 48 degrees This result is directly 199 bes affected by loop filter design Faster settling time is possilbe with wider loop filter bandwidth and lower phase margin E 1 985 198 q 20 40 60 80 100 TIME us Figure 33 Frequency Settling After Frequency Change Manual Calibration 2 02 2 015 BeeM amp M dei m Settling Time to 5 Degrees 201 F Phase Error 2 005 1 995 FREQUENCY GHz EE Note Loop Filter Bandwidth 186 kHz Loop Filter 7 5 Phase Margin 48 degrees This result is directly 1 99 affected by loop filter design Faster settling time 4 _ is possilbe with wider loop filter bandwidth and lower _ 1 985 1 98 d 20 40 60 80 100 TIME us 33 4100 MHz Figure 32 Phase Settling After Frequency Change AutoCal Enabled 1 200 150 100 Settling Time to lt 5 Degree 50 Error 0 50 PHASE ERROR DEGREES 100 Note Loop Filter Bandwidth 186 kHz Loop Filler Phase Margin 48 degrees This result is directly affected by loop filter design Faster settling time is possilbe with wider loop filter bandwidth and lower 7 iphase margin 150 200 0 60 TIME us Figure 34 Phase
41. T FREQUENCY MHz OUTPUT FREQUENCY MHz 18 Loop Filter Type 1 from Table 1 used The plot is capture by using two identical HMC835LP6GE eval boards driven by the same 10MHz external reference source from instrument via on board HMC1031MS8E to generate a 50 MHz reference frequency to lock with HMC835LP6GE and captured with 26GHz 50 high speed Oscilloscope Seed value in Reg1A for both HMC835LP6GE is set to 0 19 Same configuration and set up as 19 execpt setting HMC835LP6GE 1 seed value Reg 1Ah as 0 HMC835LP6GE 2 seed value 400000 HEX The method of calculating the seed value is desire phase adjust degree 360 2 20 Same configuration and set up as 19 HMC835LP6GE 1 seed value Reg 1Ah as 0 HMC835LP6GE 2 seed value 800000 HEX 21 Both LO1 and LO2 Output Buffer Enabled in Reg 17h 5 4 as 11 Differential or single ended mode programmed in Reg 17h 9 8 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o e O gt lt C5 LLI H 22 A H gt ep O O gt T am H za IL 65 l l A Hittite MICROWAVE CORPORATION v03 0413 HMC835LP6GE RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO EARTH FRIENDLY Figure 31 Frequency
42. TION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY 1 3 7 2 2 Integer Frequency Tuning In integer mode the digital A modulator is shut off and the N divider Reg 03h may be programmed to any integer value in the range 16 to 219 1 To run in integer mode configure Reg 06h as described then program the integer portion of the frequency as explained by EQ 12 ignoring the fractional part a Disable the Fractional Modulator Reg 06h 11 0 b Bypass the delta sigma modulator Reg 06h 7 1 c To tune to frequencies lt 2050 MHz select the appropriate output divider valueReg 16h 5 0 1 3 7 3 Fractional Mode The HMC835LP6GE is placed in fractional mode by setting the following registers a Enable the Fractional Modulator Reg 06h 11 1 b Connect the delta sigma modulator in circuit Reg O6h 7 0 1 3 7 4 4 Fractional Frequency Tuning This is a generic example with the goal of explaining how to program the output frequency Actual variables are dependant upon the reference in use The HMC835LP6GE in fractional mode can achieve frequencies at fractional multiples of the reference The frequency of the HMC835LP6GE fico is given by fico m Nint Nac fint ftrac EQ 12 fout fvcol EQ 13 Where fout is the output frequency after any potential dividers k is 1 for fundamental or k 2 4 6 58 60 62 depending on the selected output divider value Reg 16h 5 0 Nint is the i
43. VIDER Reg17h 05 EN Reg17h 09 Single Ended EN LO2 N 102_ Figure 39 HMC835LP6GE PLL VCO Block Diagram 1 1 PLL Overview The PLL divides down the VCO output to the desired comparison frequency via the N divider integer value set in Reg 03h fractional value set in Reg 04h compares the divided VCO signal to the divided reference signal reference divider set in Reg 02h in the Phase Detector PD and drives the VCO tuning voltage via the Charge Pump CP configured in Reg 09h to the VCO subsystem Some of the additional PLL subsystem functions include e Delta Sigma configuration Reg 06h e Exact Frequency Mode Configured in Reg OCh Reg 06h Reg 03h and Reg 04h e Lock Detect LD Configuration Reg 07h to configure LD and Reg OFh to configure LD_SDO output pin e External CEN pin used as hardware enable pin Typically only writes to the divider registers integer part Reg 03h fractional part Reg 04h VCO Divide Ratio part Reg 04h are required for HMC835LP6GE output frequency changes Divider registers of the PLL Reg 03h and Reg 04h set the fundamental frequency 2050 MHz to 4100 MHz of the VCO Output frequencies ranging from 38 MHz to 2050 MHz are generated by tuning to the appropriate fundamental VCO frequency 2050 MHz to 4100 MHz by programming N divider Reg 03h and Reg 04h and programming the output divider divide by 1 2 4 6 60 62 programmed in Reg 16h in the VCO r
44. appropriate Output Divider setting divide by 2 4 6 60 62 in Reg 16h 5 0 The HMC835LP6GE automatically controls frequency tuning in the fundamental band of operation for more information see 1 2 1 VCO Calibration To tune to frequencies below the fundamental frequency range 2050 MHz it is required to tune the HMC835LP6GE to the appropriate fundamental frequency then select the appropriate output divider setting divide by 2 4 6 60 62 in Reg 16h 5 0 Integer Mode The HMC835LP6GE is capable of operating in integer mode For Integer mode set the following registers a Disable the Fractional Modulator Reg 06h 11 0 b Bypass the Modulator circuit Reg 06h 7 1 In integer mode the VCO step size is fixed to that of the PD frequency Integer mode typically has 3 dB lower phase noise than fractional mode for a given PD operating frequency Integer mode however often requires a lower PD frequency to meet step size requirements The fractional mode advantage is that higher PD frequencies can be used hence lower phase noise can often be realized in fractional mode Charge Pump offset should be disabled in integer mode Reg 09h 22 14 Oh For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORA
45. as round 0 1 x 224 224 0 100000024 At fpp 50 MHz this translates to 1 2 Hz error Hittite s exact frequency mode addresses this issue and can eliminate quantization error by programming the channel step size to Fpp 10 in Reg OCh to 10 in this example More generally this feature can be used whenever the desired frequency fyco can be exactly represented on a step plan where there are an integer number of steps x2 across integer N boundaries Mathematically this situation is X satisfied f fico mod 0 9cd fycopfpp and fog gt E EQ 16 Where gcd stands for Greatest Common Divisor fy maximum integer boundary frequency lt fyco fpp frequency of the Phase Detector and fyco are the channel step frequencies where 0 lt k lt 224 1 As shown in Fig 44 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz fvco fvco2 Integer Integer Boundary Boundary gt fy fco2 fvco4 fvcoZ 2 fcoZt fco2 1 1 fo Figure 44 Exact Frequency Tuning Some fractional PLLs are able to achieve this by adjusting shortening the length of the Phase Accumu
46. cessieece MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 6 Reg 04h Frequency Register Fractional Part DEFAULT 0h 3 Divider Fractional part 24 bit unsigned see Fractional Frequency Tuning Fractional Division Value Reg4 23 0 2 24 23 0 R W Fractional Setting 24 0 Used in Fractional Mode only min 0 max 224 1 FFFFFFh 16 777 215d 2 7 5h Reserved me vame 23 0 Reserved Reserved 2 8 Reg 06h Delta Sigma Modulator Register DEFAULT 30F0Ah 1 0 R W Reserved 2 2 Reserved Program to Oh Select the Delta Sigma Modulator 0 1st order 1 2nd Order 2 3rd Order Recommended 3 Reserved 3 2 R W DSM Order 2 2 0 Normal SPI Load all register load on rising edge of SEN 1 Synchronous SPI registers Reg 03h Reg 04h Reg 1Ah wait to load synchronously on the next internal clock cycle Normally When this bit is 0 SPI writes into the internal state machines counters happen asynchronously relative to the internal clocks This can create freq phase disturbances if writing register 4 1A When this bit is enabled the internal SPI registers are loaded synchronously with the internal clock This means that the data in the SPI shifter should be held constant for at least 2 PFD clock periods after SEN is asserted to allow this retiming to happen
47. ders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Reg 17h Modes Register Default 1AB h 2 23 Master enable for the entire VCO Subsystem 0 R W VCO SubSys Master Enable 1 1 d B Chip Enable is also required to set as enable mode 1 R W VCO Enable 1 1 2 R W External VCO Buffer Enable 1 0 ili d to output stage enable Only used when locking 3 R W PLL Buffer Enable 1 1 PLL Buffer Enable Used when using an internal VCO 4 R W LO1 Output Buffer Enable 1 0 Enables LO1 LO P amp LO N pins output buffer 5 R W LO2 Output Buffer Enable 1 1 Enables the LO2 LO2 N amp LO2 P pins output buffer 6 R W External Input Enable 1 0 Enables External VCO input 7 R W Pre Lock Mute Enable 1 1 Mute both output buffers until the PLL is locked Enables Single Ended output mode for LO output LO1 Output Single Ended 1 Single ended mode LO N pin is enabled and LO P pin is 8 R W Enable 1 1 disabled 0 Differential mode both LO_N and LO_P pins enabled Please note that single ended output is only available on LO_N pin Enables Single Ended output mode for LO2 output 1 Single end
48. each output frequency while using a fixed 50MHz reference and a tunable 47 5 MHz reference See detail procedure discussed in 17 Contact Hittite Apps Support to obtain the required configuration to achieve similar spurious performance throughout the operating range of the HMC835LP6GE 17 Measured from a 50 source with a 100 external resistor termination For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz Figure 25 Phase Adjust at 0 degrees Figure 26 Phase Adjust at 90 degree 1000 1000 e a AMPLITUDE mV AMPLITUDE mV o 500 1000 1000 500 400 300 200 100 0 100 200 300 600 400 200 0 200 TIME ps TIME ps Figure 27 Phase Adjust at 180 degree 2 Figure 28 Figure of Merit 1000 500 Typ FOM vs Offset AMPLITUDE mV o 500 NORMALIZED PHASE NOISE dBc Hz 1000 600 400 e 0 200 OFFSET His Figure 29 RF Output Return Loss Diff 21 Figure 30 RF Output Return Loss Diff iz Retum Loss LO SINGLE ENDED OUTPOUT Return Loss LO DIFFERENTIAL OUTPOUT RETURN LOSS dB RETURN LOSS dB 100 1000 100 1000 OUTPU
49. ed mode LO2 N is enabled and 02 P is 9 R W Lge e Ended 1 0 disabled 0 Differential mode both LO2_N and LO2_P pins enabled Please note that single ended output is only available on LO2_N pin 10 R W Reserved 1 0 Reserved Connects CP to CP1 or CP2 output 11 R W Charge Pump Output Select 1 0 0 CP1 1 CP2 23 12 R W Reserved 12 0 Reserved 2 24 Reg 18h Bias Register Default 54C1 h Default 21697d 18 0 R W Reserved 4 1 Reserved External Input buffer BIAS 19 R W External Input buffer BIAS bitO bito External Input buffer BIAS 20 R W External Input buffer BIAS bit1 bit1 23 21 R W Reserved Reserved 2 25 Reserved Reserved Program to AB2h For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H e O gt t am C5 LLI H Z uH rnwcessipece MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY 2 26 Reg 1Ah Seed Register Default B29DOBh Used to program output phase relative to the reference frequency wen Exact Frequency Mode required When not using Exact Frequency Delta Si
50. ed on VCO frequency and 16 R W rent 1 1 capacitor setting 0 Don t scale CP current 23 17 R W Reserved 7 7d Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H e O gt t am H Z UE 05 l A MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY 2 22 Reg 16h Gain Divider Register Default 6C1 h 0 Mute VCO and PLL buffer On RF output stages Off 1 Fo 2 Fo 2 3 invalid defaults to 2 4 Fo 2 xg 5 invalid defaults to 4 5 0 R W RF Divide Ratio 6 1 6 Fo 6 60 Fo 60 61 invalid defaults to 60 62 Fo 62 62 invalid defaults to 62 3 Max Gain LO Output Buffer Gain 2 Max Gain 3 dB 7 6 R W Control 1 Max Gain 6 dB 0 Max Gain 9 dB Max Gain LO2 Output Buffer gain 2 Max Gain 3 dB 9 8 R W Control 2 1 Max Gain 6 dB 0 Max Gain 9 dB Divider Output Stage Gain 1 Max Gain 10 RAN Control 1 0 Max Gain 3 dB 23 11 R W Reserved 13 0 Reserved H gt gt t C5 LLI H Z ep l A For price delivery and to place or
51. egister For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt 0 e O gt T C5 LLI H 22 A H gt 0 O gt lt C5 LLI H za IE 65 l l A MICROWAVE CORPORATION v03 0413 RoHS v E 1 2 1 2 1 1 2 1 1 FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz For detailed frequency tuning information and example please see 1 3 7 Frequency Tuning section VCO Overview The VCO consists of a capacitor switched step tuned VCO and an output stage In typical operation the VCO is programmed with the appropriate capacitor switch setting which is executed automatically by the PLL AutoCal state machine if AutoCal is enabled Reg OAh 11 0 see section 1 21 VCO Calibration for more information The VCO tunes to the fundamental frequency 2050 MHz to 4100 MHz and is locked by the CP output from the PLL subsystem The VCO controls the output stage of the HMC835LP6GE enabling configuration of e VCO Output divider settings configured in Reg 16h divide by 2 4 6 60 62 to generate frequencies from 33 MHz to 2050 MHz or divide by 1 to generate fundamental frequencies between 2050 MH
52. eo 100 F E89 3 F 120 100 9 E a W 420 z 160 ME 180 160 200 L LLLA A180 ET E 0000 100000 1 10 100 1000 10000 100000 OFFSET Kho OFFSET KHz INT MODE Loop Filter BW 186 KHz Integrated Jitter 94 fs 4090 MHz 3570 MHz 2627 MHz FRAC MODE Loop Filter BW 186 KHz Integrated Jitter 124 fs det Fas sooie Bsiz INT MODE Loop Filter BW 58 KHz Integrated Jitter 141 fs FRAC MODE Loop Filter BW 58 KHz Integrated Jitter 141 fs 1 Measured with 122 88 MHz Xtal 61 44 MHz PD frequency Loop Filter Type 1 CP 2 54 mA Leakage Dn 435 uA 2 Measured with 100 MHz Xtal 50 MHz PD frequency Loop Filter Type 1 CP 2 54 mA Leakge Dn 435 uA 3 Measured with 100 MHz Xtal 50 MHz PD frequency Loop Filter Type 2 CP 2 54 mA Leakge Dn 435 uA 4 Measured with 100 MHz Xtal 50 MHz PD frequency Loop Filter Type 1 and 2 2 54 mA Leakge Dn 435 uA Phase Noise integrated from 1 kHz to 100 MHz 5 Loop Filter designs are provided in Table 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt V e O gt t C5 LLI H 22 IE l A H gt 0 O gt Q lt H za IL 05 l l A
53. equency is counted for Tim the period of a single AutoCal measurement cycle T amt T adi pes EQ 1 n is set by Reg OAh 2 0 and results in measurement periods which are multiples of the PD period T 4jR R is the reference path division ratio currently in use Reg 02h is the period of the external reference crystal oscillator The VCO AutoCal counter will on average expect to register N counts rounded down floor to the nearest integer every PD cycle N is the ratio of the target VCO frequency fyco to the frequency of the PD fpa where N can For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt V e O gt t C5 LLI H 22 UE l A H gt ep O O gt T H za JE 05 l l A mmosasLPece MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz be any rational number supported by the N divider N is set by the integer Reg 03h and fractional Nj Reg 04h register contents N 27 EQ 2 int frac The AutoCal state machine runs at the rate of the FSM clock Trs where the FSM clock frequency cannot be greater than 50 MHz m Tes 2 EQ 3
54. equired Reg 07h settings to appropriately program the Digital LD window size From Table 5 simply select the closest value in the Digital LD Window Size columns to the one calculated in EQ 10 and program Reg 07h 9 8 and Reg 07h 7 5 accordingly Table 5 Typical Digital Lock Detect Window LD 1 Digital 1 Fastest 00 6 5 8 11 17 29 53 100 195 01 7 8 9 12 8 21 36 68 130 255 10 74 9 2 13 3 22 38 72 138 272 Slowest 11 7 6 10 2 15 4 26 47 88 172 338 1 3 5 2 Digital Window Configuration Example Assuming fractional mode with a 50 MHz PD and e Charge Pump gain of 2 mA Reg 09h 13 7 64h Reg 09h 6 0 64h e Down Offset Reg 09h 22 21 10 b e Offset current magnitude of 400 pA Reg 09h 20 14 50h Applying EQ 11 the required LD window size is 0 4x10 A 1 2 66 x10 50x 10 Hz x 2x10 A 50x 10 Hz LD Window seconds _ _ _ 13 33 11 Locating the Table 5 value that is closest to the EQ 11 result in this case 13 3 13 33 To set the Digital LD window size simply program Reg 07h 9 8 10 b and Reg 07h 7 5 010 b according to Table 5 There is always a good solution for the lock detect window for a given operating point The user should understand however that one solution does not fit all operating points As observed from EQ 11 If charge pump offset or PD frequency are changed signif
55. etect otherwise e Set GPO Select Reg OFh 4 0 00001 b which is default e Set Prevent GPO driver disable Reg OFh 7 1 e Always drive Lock Detect e Set Prevent AutoMux of SDO Reg OFh 6 1 e Set GPO Select Reg OFh 4 0 00001 which is default e Set Prevent GPO driver disable Reg OFh 7 1 The signals available on the GPO are selected in Reg OFh 4 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY 1 7 Chip Identification The chip id information may be read by reading the content of read only register chip ID in Reg 00h For HMC835LP6GE chip id is C7701Ah 1 8 SERIAL PORT Overview The SPI protocol has the following general features a 3 bit chip address enable the use of up to 8 devices connected to the serial bus b Simultaneous Write Read during the SPI cycle c 5 bit address space d 3 wire for Write Only capability 4 wire for Read Write capability Typical serial port operation can be run with SCLK at speeds up to 50 MHz 1 8 1 Serial Port WRITE Operation AVDD DVDD AGND DGND Table 6 SPI WRITE Timing Characteristics
56. gma Modulator 24 11705611d Mode and Auto seed Enable RegO6h 8 1 Reg1Ah sets the start Seed B29DOBh phase of output signal If AutoSeed disable RegO6h 8 20 Reg1Ah is the start phase of the signal after every frequency changel LO Phase 2n x Reg1Ah 224 23 0 R W H gt O O gt e t 5 LLI H Z IE z l A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY Notes H gt o e O gt t C5 LLI H 22 UE l A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com
57. he CEN pin by setting Reg O1h 0 0 Control of Power Down Mode then comes from the serial port register Reg O1h 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt 0 e O gt T C5 LLI H 22 A MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz It is also possible to leave various blocks on when in Power Down see Reg 01h including a Internal Bias Reference Sources Reg 01h 2 b PD Block Reg 01h 3 c CP Block Reg 01h 4 d Reference Path Buffer Reg 010 5 e VCO Path buffer Reg O1h 6 f Digital I O Test pads Reg 01h 7 To mute the output but leave the PLL and VCO locked please refer to 1 2 4 section 1 6 General Purpose Output GPO Pin The PLL shares the LD SDO Lock Detect Serial Data Out pin to perform various functions While the pin is most commonly used to read back registers from chip via the SPI it is also capable of exporting a variety of signals and real time test waveforms including Lock Detect It is driven by a tri state CMOS driver with 200 Rout It has logic associated with it to dynamically select whether the driver is enabled and to decide which data to exp
58. his ensures optimum selection of VCO switch settings vs time and temperature The user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the AutoCal routine The accuracy required in the calibration affects the amount of time required to tune the VCO The calibration routine searches for the best step setting that locks the VCO at the current programmed frequency and ensures that the VCO will stay locked and perform well over it s full temperature range without additional calibration regardless of the temperature that the VCO was calibrated at Auto Calibration can also be disabled allowing manual VCO tuning Refer to section 1 2 1 6 for a description of manual tuning 1 2 1 2 2 Auto reLock on Lock Detect Failure It is possible by setting Reg OAh 17 to have the VCO subsystem automatically re run the calibration routine and re lock itself if Lock Detect indicates an unlocked condition for any reason With this option the system will attempt to re Lock only once 1 2 1 3 3 VCO AutoCal on Frequency Change Assuming Reg OAh 11 0 the VCO calibration starts automatically whenever a frequency change is requested If it is desired to rerun the AutoCal routine for any reason at the same frequency simply rewrite the frequency change with the same value and the AutoCal routine will execute again without changing final frequency 1 2 1 4 4 VCO AutoCal Time amp Accuracy The VCO fr
59. icantly then the lock detect window may need to be adjusted For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H O O gt t C5 LLI H Z UE l QA H gt ep O O gt T C5 LLI H za IE 65 l l A MICROWAVE CORPORATION v03 0413 RoHS v E 1 3 5 3 1 3 6 1 3 7 1 3 7 1 FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz Configuring LD SDO Pin for LD Output Setting Reg OFh 4 0 1 will display the Lock Detect Flag on LD_SDO pin of the HMC835LP6GE If locked LD_SDO will be high As the name suggests LD SDO pin is multiplexed between LD and SDO Serial Data Out signals Hence LD is available on the LD SDO pin at all times except when a serial port read is requested in which case the pin reverts temporarily to the Serial Data Out pin and returns to the Lock Detect Flag after the read is completed LD can be made available on LD_SDO pin at all times by writing Reg OFh 6 1 In that case the HMC835LP6GE will not provide any read back functionality because the SDO signal is not available Cycle Slip Prevention CSP When changing VCO frequency and the VCO is not yet locked to the reference the
60. in process 8 R VCO Tuning Busy 1 1 1 Busy 0 Not Busy For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt O gt t C5 LLI H Z JE l aL Hmcasstpece MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 17 Reg 11 SAR Register Read Only 219 1d 7FFEFh SAR Error Magnitude Count SAR Error Sign 19 R SAR Error Sign 0 positive 1 negative Reserved Reserved 2 18 Reg 12h GPO LD Register Re NAME 0 R GPO Out 1 0 1 R Lock Detect Out 1 0 Lock Detect Output 23 2 R Reserved 22 7h Reserved 16 0 R Reserved 16 Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION 03 0413 ROHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 2 gister 1 Use the 3 outputs as an SPI port cial 1 0 Use the 3 outputs
61. ink on the HMC835LP6GE product page at www hittite com Hittite PLL Design enables users to accurately model and analyze performance of all Hittite PLLs PLLs with Integrated VCOs and Clock Generators It supports various loop filter topologies and enables users to design custom loop filters and accurately simulate resulting performance For evaluation purposes the HMC835LP6GE evaluation board is shipped with an on board low cost low noise 100 ppm 50 MHz VCXO enabling evaluation of most parameters including phase noise without any external references Exact phase or frequency measurements require the HMC835LP6GE to use the same reference as the measuring instrument To accommodate this requirement the HMC835LP6GE evaluation board includes the HMC1031MS8E a simple low current integer N PLL that can lock the on board VCXO to an external 10 MHz reference input commonly provided by most test equipment To lock the HMC835LP6GE to external 10 MHz reference simply connect the external reference output to J2 input of the HMC835LP6GE evaluation board and change the HMC1031MS8E integer divider value to 5 by changing the switch settings D1 1 SW1 4 closed and DO 0 SW2 3 open for more information please see the HMC1031MS8E data sheet For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 9
62. instantaneous frequencies of the two PD inputs are different and the phase difference of the two inputs at the PD varies rapidly over a range much greater than 2 radians Since the gain of the PD varies linearly with phase up to 27 the gain of a conventional PD will cycle from high gain when the phase difference approaches a multiple of 271 to low gain when the phase difference is slightly larger than a multiple of 0 radians The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle This can make the VCO frequency actually reverse temporarily during locking This phenomena is known as cycle slipping Cycle slipping causes the pull in rate during the locking phase to vary cyclically Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal Laplace analysis The HMC835LP6GE PD features an ability to reduce cycle slipping during frequency tunning The Cycle Slip Prevention CSP feature increases the PD gain during large phase errors Frequency Tuning HMC835LP6GE VCO subsystem always operates in fundamental frequency of operation 2050 MHz to 4100 MHz The HMC835LP6GE generates frequencies below its fundamental frequency 33 MHz to 2050 MHz by tuning to the appropriate fundamental frequency and selecting the
63. irection of Reg 09h 20 14 Up 0 UP Offset Off 22 R W Offset DN enable 1 1 Sets Direction of Reg 09h 20 14 Down 0 DN Offset Off Only recommended with external VCOs and Active Loop Filters When enabled the HMC835LP6GE increases CP current by 3 mA thereby improving phase noise perfor mance and increasing loop bandwidth 23 R W HiK charge pump Mode 1 0 H gt 0D O gt t H Z JE 65 l A For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY 2 12 Reg 0Ah VCO AutoCal Configuration Register DEFAULT 2046 h Used by internlan AutoCal state machine R Divider Cycles 2 0 R W Vtune Resolution 3 6d 7 256 div cycles for frequency measurement Measurement should last gt 4 usec Note 1 does not work if R divider 1 10 3 R W Reserved 8 16d Reserved 0 AutoCal Enabled 1 AutoCal disabled 12 R W Reserved 1 0 Reserved Set the AutoCal FSM and VSPI Clock 50 MHz maximum 0 Input Crystal Reference 14 13 R W FSM VSPI Clock Select 2 1 1 Input Crystal Reference 4 2 Input Crystal Reference
64. is highly recommended to use Hittite s low noise high PSRR Power Supply Rejection Ratio regulator the HMC1060LPSE Using the HMC1060LP3E lowers the design risk and cost and ensures that the performance shown in Typical Performance Characteristics can be achieved Power supply noise contribution to the PLL output phase noise can easily be modelled in the Hittite PLL Design tool To download Hittite s PLL Design software tool click on the Software Download link on the HMC835LP6GE product page at www hittite com For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com tJ Hittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz 1 0 Theory of Operation The block diagram of HMC835LP6GE PLL with Integrated VCO is shown in Figure 39 EXT VCO P EXT VCO N VTUNE VCO CAL LOOP Reg15h 09 FILTER VOLTAGE Reg17h 06 Regt7n 01 EN Regi7h 03 vco EN Single Ended EN EN Reg 7h 08 Regi7h 11 EN CP1 N T gt 2s 10 DIVIDER PHASE So CHARGE FREQUENCY NS m LO N ox DETECTOR EN 2 4 6 62 leg16h 7 6 2 Reg17h 02 Reg16h 10 XREFP Reg16h 9 8 R DI
65. l Specifications Continued Power Supply Currents 5V Analog Charge Pump VDDCP 6 Single Ended Output 4 99 110 5V VCO core LO1 Buffer Only VCC2 Differential Output 4 104 129 Single Ended Output 99 110 5V VCO core LO2 Buffer Only VCC2 Differential Output 4 104 129 Single Ended Output 108 130 mA 5V VCO core LO1 Buffer LO2 Buffer VCC2 Differential Output M 118 168 Fo 1 Mode 27 5V VCO Divider and RF PLL Buffer VCC1 Fo N 1 2 4 62 Mode 52 73 3 3V VCCPD VCCPS VCCHF DVDD 48 RVDD Power Down Crystal Off Peg 18 0 10 Crystal Not Clocked f Reg 01h 0 Power Down Crystal On 100 MHz Crystal Clocked 100 MHz 5 mA Power on Reset Typical Reset Voltage on DVDD 700 mV Min DVDD Voltage for No Reset 1 5 V Power on Reset Delay 250 us VCO Open Loop Phase Noise at fo 4 GHz 10 kHz Offset 78 dBc Hz 100 kHz Offset 108 dBc Hz 1 MHz Offset 134 5 dBc Hz 10 MHz Offset 156 dBc Hz 100 MHz Offset 171 dBc Hz VCO Open Loop Phase Noise at fo 9 3 GHz 2 1 5 GHz 10 kHz Offset 89 dBc Hz 100 kHz Offset 119 dBc Hz 1 MHz Offset 143 7 dBc Hz 10 MHz Offset 160 7 dBc Hz 100 MHz Offset 165 dBc Hz VCO Open Loop Phase Noise at fo 3 GHz 30 100 MHz 10 kHz Offset 111 dBc Hz 100 kHz Offset 142 dBc Hz 1 MHz Offset 165 dBc Hz 10 MHz Offset 170 dBc Hz 4 Minimum and Maximum current various by
66. lator the denominator or the modulus of the Delta Sigma modulator so that the Delta Sigma modulator phase accumulator repeats at an exact period related to the interval frequency fycox fyvco k 1 in Fig 44 Consequently the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period or at harmonic frequencies of fycok fycog 1 For example in some applications these intervals might represent the spacing between radio channels and the spurious would occur at multiples of the channel spacing The Hittite method on the other hand is able to generate exact frequencies between adjacent integer N boundaries while still using the full 24 bit phase accumulator modulus thus achieving exact frequency steps with a high phase detector comparison rate which allows Hittite PLLs to maintain excellent phase noise and spurious performance in the Exact Frequency Mode 1 3 7 6 6 Using Hittite Exact Frequency Mode If the constraint in EQ 16 is satisfied HMC835LP6GE is able to generate signals with zero frequency error at the desired VCO frequency Exact Frequency Mode may be re configured for each target frequency or be set up for a fixed fgcg which applies to all channels 1 3 7 6 1 1 Configuring Exact Frequency Mode For a Particular Frequency 1 Calculate and program the integer register setting Reg 03h floor fyco fpp where the floor functio
67. n AutoCal of the step tuned VCO The AutoCal fixes the VCO tuning voltage at the optimum mid point of the charge pump output then measures the free running VCO frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency This procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor A typical tuning curve for a step tuned VCO is shown in Fig 40 Note how the tuning voltage stays in a narrow range over a wide range of output frequencies such as fast frequency hopping For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz TUNE VOLTAGE AFTER CALIBRATION V 0 b x de gt i 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 VCO FREQUENCY MHz Calibrated at 85C Measured at 85C Calibrated at 85C Measured at 40C Calibrated at 40C Measured at 40C Calibrated at 40C Measured at 85C Calibrated at 27C Measured at 27C Figure 40 Typical VCO Tuning Voltage After Calibration The calibration is normally run automatically once for every change of frequency T
68. n is the rounding down to the nearest integer Then the integer boundary frequency fy Nint fep 2 Calculate and program the exact frequency register value Reg OCh where fgca gCd fyco fpp 224 foor fy 3 Calculate and program the fractional register setting Reg 04h where ceil is the ceiling function meaning round up to the nearest integer Example To configure the HMC835LP6GE for exact frequency mode at fyco 2800 2 MHz where Phase Detector PD rate fpp 61 44 MHz Proceed as follows Check EQ 16 to confirm that the exact frequency mode for this fyco is possible f fca 9 ed fco fep and gt L3 61 44 x108 sa 8750 9d 2800 2 108 61 44 x 10 12010 gt Since EQ 16 is satisfied the HMC835LP6GE can be configured for exact frequency mode at 2800 2 MHz as follows For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt V e O gt T am H 22 ae l A MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz f 2800 2 x10 1 Reg 03h floor Y floor 45d 2Dh INT fep 61 44 106 fep E 61 44x109 _ 61
69. nal Mode 3 DC 100 MHz PD Frequency Integer Mode DC 100 MHz Charge Pump Output Current 0 02 2 54 mA Charge Pump Gain Step Size 20 pA PD Charge Pump SSB Phase Noise 50 MHz Ref Input Referred 1 kHz 143 dBc Hz 10 kHz Add 2 dB for Fractional 150 dBc Hz 100 kHz Add 3 dB for Fractional 153 dBc Hz Logic Inputs 9 Vsw 40 50 60 Sun Logic Outputs VOH Output High Voltage DVDD VOL Output Low Voltage 0 Output Impedance 100 200 Maximum Load Current 1 5 mA Power Supply Voltages 3 3 V Supplies dL E 34 3 8 3 5 V 5 V Supplies VCC1 VCC2 VDDLS VDDCP 4 8 5 5 2 V 1 Measured with 100 external termination See Reference Input Stage section for more details 2 Slew rate of gt 0 5 ns V is recommended see Reference Input Stage section for more details Frequency is guaranteed across process voltage and temperature from 40 C to 85 C 3 This maximum PD frequency can only be achieved if the minimum N value is respected eg In the case of fractional mode the maximum PD frequency fvco 20 or 100 MHz whichever is less For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION 1 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Electrica
70. ndependent of the size of the frequency change Any size frequency size hop will have a similar settling time with AutoCal disabled Reg OAh 11 1 Loop filter BW 186 kHz Loop Filter Type 1 in Table 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION 030413 RoHSv FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz Figure 35 Forward Transmission Gain 24 Figure 36 HMC835LP6GE with External VCO HMC384LP4E at 2213MHz 1 40 60 80 100 120 PHASE NOISE dBc Hz 140 FORWARD TRANMISSION GAIN dB 160 400 800 1200 1600 2000 2400 2800 UM 10 100 1000 10000 OUTPUT FREQUENCY MHz OFFSET KHz Figure 37 HMC835LP6GE Mute and Isolations 0 Signal on LO2 pin when LO2 Buffer is on _ _ LO2 Single Ended Mode is on signal on LO1 P pin when LO1 Buffer is on Mode is on Reg 17h 5 4 1d Reg Th 9 8 0d Off Signal on L 2 P pin when LO2 Buffer is off ISOLATION dB LO buffer is on Reg 17h 5 4 1d Reg17h 9 8 3d Mute when unlock Reg 17h 7 1 Ji Mute On Reg16h 5 0 09 1 100 3000 1000 FRQUENCY MHz 24 Odbm IN External Buffer Bias is configured in Reg 18h 20 19 as 11 Both LO1 and LO2 Out
71. nteger division ratio Reg 03h an integer number between 20 and 524 284 is the fractional part from 0 0 to 0 99999 N 4 Reg 04h 224 R is the reference path division ratio Reg 02h fetal is the frequency of the reference oscillator input fod is the PD operating frequency fyta R As an example La 1402 5 MHz k 2 lies 2 805 MHz fria 50 MHz R 1 fod 50 MHz Nint 56 04 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt o e O gt t C5 LLI H 22 l A H gt 0 O gt lt H za IE 65 l l A MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz EARTH FRIENDLY Reg 04h round 0 1 x 224 round 1677721 6 1677722 50e6 1677722 fico 56 2805 MHz 1 192 Hz error EQ 14 fount iu 1402 5 MHz 0 596 Hz error EQ 15 In this example the output frequency of 1402 5 MHz is achieved by programming the 19 bit binary value of 56d 38h into intg reg in Reg O3h and the 24 bit binary value of 1677722d 19999Ah into frac reg in Reg 04h The 0 596 Hz quantization error can be eliminated using the exact frequenc
72. oise It is designed for 50 MHz PD frequency CP 2 mA in Fractional Mode 27 Loop Filter Type 2 is suggested to use for best far out phase noise It is designed for 50 MHz PD frequency CP 2 mA in Fractional Mode 28 Loop Filter Type 3 is suggested to use for best low frequency phase noise used as reference source It is designed for 50 MHz PD frequency CP 2 mA in Integer Mode 29 Loop Filter Type 4 is a example to use HMC835LP6GE as a PLL and connect with external VCO For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Table 2 Pin Descriptions 1 VDDCP E Power Supply for charge pump analog section External bypass decoupling for precision bias circuits 1 920 V 2 mV gt 2 BIAS NOTE BIAS ref voltage cannot drive an external load Must be measured with 10 GO meter such as Agilent 34410A normal 10 MO DVM will read erroneously I 3 CP1 Charge Pump output 1 O 4 CP2 Charge Pump output 2 5 RVDD Reference supply 3 3 V nominal gt 6 XREFP Reference Input DC bias is generated internally Normally
73. ol enable the HMC835LP6GE to distribute identical frequency and phase signals to multiple destinations at optimal signal levels tailored to each output External VCO input allows the HMC835LP6GE to lock external VCOs and enables cascaded LO architectures for MIMO radio applications Two separate Charge Pump CP outputs enable separate loop filters optimized for both integrated and external VCOs and seamless switching between integrated or external VCOs during operation Programmable RF output phase feature can further phase adjust and synchronize multiple HMC835LP6GEs enabling scalable MIMO and beam forming radio architectures Additional features include configurable output mute function that mutes RF outputs during frequency changes Exact Frequency Mode that enables the HMC835LP6GE to generate fractional frequencies with 0 Hz frequency error and the ability to synchronously change frequencies without changing the phase of the output signal Electrical Specifications VPPCP VDDLS VCC1 VCC2 5 V RVDD AVDD DVDD VCCPD VCCHF VCCPS 3 3 V Min and Max Specified across Temp 40 C to 85 C RF Output Characteristics Output Frequency 33 4100 MHz VCO Frequency at PLL Input 2050 4100 MHz RF Output Frequency at fyco 2050 4100 MHz Output Power RF Output Power at fundmental frequency Max Gain Setting 2050 MHz Reg 16h 7 6 11d 7 Across all Frequencies seeFig 13 Single Ended Output Power Cont
74. or sinusoid can be used The following table shows the recommended operating regions for different reference frequencies If operating outside these regions the part will normally still operate but with degraded reference path phase noise performance For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt O O gt e Lu t H Z JE 05 l l A CJ Hittite MICROWAVE CORPORATION v03 0413 FRACTIONAL N PLL WITH INTEGRATED VCO RoHS v 1 3 3 1 3 4 1 3 5 1 3 5 1 Table 4 Reference Sensitivity Table HMC835LP6GE 33 4100 MHz Recommended Min Max Recommended 10 YES 0 6 2 5 x x x 10 YES 0 6 25 x x x 25 YES 0 6 2 5 ok 8 15 50 YES 0 6 2 5 YES 6 15 100 YES 0 6 2 5 YES 5 15 150 ok 0 9 2 5 YES 4 12 200 ok 12 2 5 YES 3 8 Input referred phase noise of the PLL when operating at 50 MHz is between 148 and 150 dBc Hz at 10 kHz offset depending upon the mode of operation The input reference signal should be 10 dB better than this floor to avoid degradation of the PLL noise contribution It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required fo
75. ort from the chip In its default configuration after power on reset the output driver is disabled and only drives during appropriately addressed SPI reads This allows it to share the output with other devices on the same bus The pin driver is enabled if the chip is addressed ie The last 3 bits of SPI cycle 000 b before the rising edge of SEN If SEN rises before SCK has clocked in an invalid non zero chip address the HMC835LP6GE will start to drive the bus The FRACTIONAL N PLL WITH INTEGRATED VCO will naturally switch away from the GPO data and export the SDO during an SPI read To prevent this automatic data selection and always select the GPO signal set Prevent AutoMux of SDO Reg OFh 6 1 The phase noise performance at this output is poor and uncharacterized The GPO output should not be toggling during normal operation because it may degrade the spectral performance H gt o O O gt lt C5 LLI H za IE 65 l l A Note that there are additional controls available which may be helpful if sharing the bus with other devices e To disable the driver completely set Reg O8h 5 0 it takes precedence over all else e disable either the pull up or pull down sections of the driver Reg OFh 8 1 or Reg OFh 9 1 respectively Example Scenarios e Drive SDO during reads tri state otherwise to allow bus sharing e No action required e Drive SDO during reads Lock D
76. pecial phase detector features Setting Reg OBh 5 0 masks the PD up output which prevents the charge pump from pumping up Setting Reg OBh 6 0 masks the PD down output which prevents the charge pump from pumping down Clearing both Reg OBh 5 and Reg OBh 6 tri states the charge pump while leaving all other functions operating internally PD Force UP Reg OBh 9 1 and PD Force DN Reg OBh 10 1 allows the charge pump to be forced up or down respectively This will force the VCO to the ends of the tuning range which can be useful in VCO testing 1 3 2 Reference Input Stage AC couple 1000 Figure 43 Reference Path Input Stage H gt o e O gt lt C5 LLI H 22 A The reference buffer provides the path from an external reference source generally crystal based to the R divider and eventually to the phase detector The buffer has two modes of operation controlled by Reg 08h 21 High Gain Reg 08h 21 0 recommended below 200 MHz and High frequency Reg 08h 21 1 for 200 to 350 MHz operation The buffer is internally DC biased with 100 internal termination For 50 match an external 100 resistor to ground should be added followed by an AC coupling capacitor impedance 1 then to the XREFP pin of the part Atlow frequencies a relatively square reference is recommended to keep the input slew rate high At higher frequencies a square
77. put Buffer Enabled in Reg 17h 5 4 as 11 Differential or single ended mode programmed in Reg 17h 9 8 25 50MHz PFD with Loop Filter Type 4 is used In order to configure HUC835LP6GE to use with external VCO Reg 17h need to be configured to disable the on chip VCO and VCO to PLL path while enable External Buffer second CP link and External IO switch Reg 17h 0 11 as 3157d Reg OBh 4 21 PFD SWAP might be needed to be selected for active loop filter Reg OBh 4 0 For use with positive tuning slope VCO and PASSIVE loop filter Reg OBh 4 1 For use with a NEGATIVE slope VCO or with a ACTIVE loop filter For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt 0 e O gt lt C5 LLI H 22 A H O gt e Lu t H Z JE l l aL mmosasLPece MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTI Table 1 Loop Filter Designs Used in Typical Performance Characteristics Graphs 0292 17 66 3300 330 1500 4700 75 75 12 26 Loop Filter Type 1 is suggested to use for best integrated phase n
78. r operates with zero offset The divided reference signal and the divided VCO signal arrive at the phase detector inputs at the same time Integer mode does not require any CP Offset current When operating in Integer Mode simply disable CP offset in both directions Up and down by writing Reg 09h 22 21 00 b and set the CP Offset magnitude to zero by writingReg O9h 20 14 0 In Fractional Mode CP linearity is of paramount importance Any non linearity degrades phase noise and spurious performance In fractional mode these non linearities are eliminated by operating the PD with an average phase offset either positive or negative either the reference or the VCO edge always arrives first at the PD ie leads A programmable CP offset current source is used to add DC current to the loop filter and create the desired phase offset Positive current causes the VCO to lead negative current causes the reference to lead The CP offset is controlled via Reg 09h 20 14 The phase offset is scaled from degrees that is the reference and the VCO path arrive in phase to 360 degrees where they arrive a full cycle late The specific level of charge pump offset current Reg 09h 20 14 is provided in EQ 9 It is also plotted in Fig 43 vs PD frequency for typical CP Gain currents Required CP Offset min 4 810 x Fpp lop 0 25x lop EQ 9 where Fpp Comparison frequency of the Phase Detector Hz lop is the full scale current setting A of
79. r the system goals Reference Path R Divider The reference path R divider is based on a 14 bit counter and can divide input signals by values from 1 to 16 383 and is controlled via Reg 02h RF Path N Divider The main RF path divider is capable of average divide ratios between 219 5 524 283 and 20 in fractional mode and 219 1 524 287 to 16 in integer mode Lock Detect The Lock Detect LD function indicates that the HMC835LP6GE is indeed generating the desired frequency It is enabled by writing Reg O7h 11 1 The HMC835LP6GE provides LD indicator in one of two ways e As an output available on the LD_SDO pin of the HMC835LP6GE Configuration is required to use the LD_SDO pin for LD purpose for more information please see 1 8 Serial Port Open Mode and 1 3 5 3 Configuring LD_SDO Pin for LD Output section e Or reading from Reg 12h 1 where Reg 12h 1 1 indicates locked and Reg 12h 1 0 indicates an unlocked condition The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a user specified time period window repeatedly Either signal may arrive first only the difference in arrival times is significant The arrival of the two edges within the designated window increments an internal counter Once the count reaches and exceeds a user specified value Reg 07h 2 0 the HMC835LP6GE declares lock Failure in registering the two edges in any one windo
80. rd MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v E 1 3 8 1 4 1 5 FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz If EQ 16 is satisfied for at least two of the equally spaced interval channel frequencies fyco1 fyco2 fvco3 fycow as it is above Hittite Exact Frequency Channel Mode is possible for all desired channel frequencies and can be configured as follows 2800 2 10 g floor E floor 22 45d 2Dh 1 Begin fep 61 44x108 _ 61 44 106 _ 61 44x108 9 ged t00 109 61 44100 20000 where fycoxs1 is the desired channel spacing 100 kHz in this example 3072d 2 RegOCh 3 program Reg 04h the closest integer N boundary frequency fy that is less than the smallest channel VCO frequency fyco must be calculated fy floor fyco7 fpp Using the current example 2800 2x108 fy fpp x floor NEN Jesse aeo 2764 8 224 PD Reg 04h em for channel 1 where 2800 2 MHz 224 2800 2x10 2764 8x10 61 44x108 4 change from channel 1 fyco 2800 2 MHz to channel 2 fyco2 2800 3 MHZ only Reg 04h needs to be programmed as long as all of the desired exact frequencies fyco
81. rol range 3 dB Steps 9 dB Harmonics for Fundamental Mode fo Mode at 2 GHz 2nd 3rd 4th 26 20 39 dBc fo 2 Mode at 2GHz 2 1 GHz 2nd 3rd 4th 27 17 35 dBc fo 30 Mode at 3 GHz 30 100 MHz 2nd 3rd 4th 26 10 38 dBc fo 62 Mode at 3999 MHz 62 64 5 MHz 2nd 3rd 4th 23 10 31 dBc VCO Output Divider VCO RF Divider Range 1 2 4 6 8 62 1 62 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt 0 O O gt T C5 LLI H 22 UE l A H gt 0D O gt t H Z ep l A HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Electrical Specifications Continued PLL RF Divider Characteristics 19 Bit N Divider Range Integer Max 219 1 16 524 287 19 Bit N Divider Range Fractional jeans Hohen E 20 524 283 REF Input Characteristics Max Ref Input Frequency 350 MHz Ref Input Level AC Coupled 1 6 12 dBm Ref Input Capacitance 5 pF 14 Bit R Divider Range 1 16 383 Phase Detector PD 2 PD Frequency Fractio
82. set Reg09 21 UP Gain 1 0 635uA RegO9 1 3 7 Y 0 2 54mA SuA Step 20uA Step Reg09 20 14 UP REF PATH PP e Filter VCO PATH DN DN Offset Reg09 22 DN Gain 0 635uA Reg09 6 0 1 5uA Step 0 2 54mA Reg09 20 14 20uA Step Figure 42 Charge Pump Gain amp Offset Control 1 3 1 2 2 Charge Pump Gain Charge pump Up and Down gains are set by Reg 09h 13 7 and Reg O9h 6 0 respectively The current gain of the pump in Amps radian is equal to the gain setting of this register divided by 2rr Typical CP gain setting is set to 2 to 2 5 mA however lower values can also be used Values 1 mA may result in degraded Phase Noise performance For example if both Reg 09h 13 7 and Reg O9h 6 0 are set to 50d the output current of each pump will be 1 mA and the phase frequency detector gain k 1 mA 2r radians or 159 pA rad For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com H gt ep O O gt lt C5 LLI H 22 UE l A MICROWAVE CORPORATION v03 0413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz 1 3 1 3 3 Charge Pump Phase Offset In Integer Mode the phase detecto
83. sing edges of SCK 25 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCK 30 32 Chip address is always 000 b Slave shifts the chip address bits on the next 3 rising edges of SCK 30 32 Master asserts SEN after the 32nd rising edge of SCK ze gt Slave registers the SDI data on the rising edge of SEN Master clears SEN to complete the the address transfer of the two part READ cycle j If one does not wish to write data to the chip during the second cycle then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle k Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK I Slave HMC835LP6GE shifts the SDI data on the next 32 rising edges of SCK On these same edges the slave places the desired read data ie data from the address specified in Reg OOh 4 0 of the first cycle on LD_SDO which automatically switches to SDO mode from LD mode disabling the LD output m Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock Detect on LD_SDO For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413
84. t www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION 030413 RoHS FRACTIONAL N PLL WITH INTEGRATED VCO 33 4100 MHz EARTH FRIENDLY Outline Drawing IOP VIEW BOTTOM VIEW 240 6 10 012 0 30 1232 5 90 008 0 20 PIN 40 40 51 JUUUUUUUUI 1 30 E c PIN 1 7 88 88 s H835 is MS qt Lo exui LJ u XXXX gs mE CN CN I 10 21 C 11 20 Las LOT NUMBER 187 4 75 saine 008 E A MIN 035 0 90 cds ES 012 0 30 REF 051 0 80 E 0 30 002 0 05 000 0 00 El SEATING Y PLANE A 003 0 08 C e NOTES 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY 3 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN 4 DIMENSIONS ARE IN INCHES MILLIMETERS 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 PAD BURR LENGTH SHALL BE 0 15mm MAX PAD BURR HEIGHT SHALL BE 0 25mm MAX 7 PACKAGE WARP SHALL NOT EXCEED 0 05mm 8 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND 9 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Package Information 835 HMC835LP
85. w resets the counter and immediately declares an un locked condition Lock is deemed to be reestablished once the counter reaches the user specified value Reg 07h 2 0 again Lock Detect Configuration Optimal spectral performance in fractional mode requires CP current and CP offset current configuration discussed in detail in section 1 3 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC835LP6GE MICROWAVE CORPORATION v03 0413 RoHS v FRACTIONAL N PLL WITH INTEGRATED VCO E 33 4100 MHz These settings in Reg 09h impact the required LD window size in fractional mode of operation To function the required lock detect window size is provided by EQ 10 lome A _ 2 66 x10 sec Fpp Hz x Ice A Feo Hz LD Window seconds in Fractional Mode B EQ 10 LD Window seconds in Integer Mode where Fpp is the comparison frequency of the Phase Detector lop offset S the Charge Pump Offset Current Reg O9h 20 14 Icp is the full scale current setting of the switching charge pump Reg O9h 6 0 or Reg 09h 13 7 If the result provided by EQ 10 is equal to 10 ns Analog LD can be used Reg 07h 6 0 Otherwise Digital LD is necessary Reg 07h 6 1 Table 5 provides the r
86. y frequency is given by fy H gt 0 O gt lt C5 LLI H za IE 65 l l A 2 Calculate and program the exact frequency register value Reg OCh fpp fgca where foca gcd fycok 1 fycoj fpp greatest common divisor of the desired equidistant channel spacing and the PD frequency fycok 1 fvcok and fpp Then to switch between various equally spaced intervals channels only the fractional register Reg 04h needs to be programmed to the desired VCO channel frequency fycox the following manner 27 ico fu the smallest channel VCO frequency that is greater than fy Reg 04h ceil where fy floor fyco fpp andfyco as shown in Fig 44 represents Example To configure the HMC835LP6GE for Exact Frequency Mode for equally spaced intervals of 100 kHz where first channel Channel 1 fyco 2800 200 MHz and Phase Detector PD rate fpp 61 44 MHz proceed as follows First check that the exact frequency mode for this fyco 2800 2 MHz Channel 1 and fyco2 2800 2 MHz 100 kHz 2800 3 MHz Channel 2 is possible f 9C d ficos fep and foi gt t3 gcd fycos fop and 2 8 61 44 x108 fedi god 2800 2 108 61 44106 120x10 gt o 61 44x108 buie gcd 2800 3 109 61 44x108 20103 gt 750 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsfo
87. y mode if required In this example the VCO output fundamental 2805 MHz is divided by 2 Reg 16h 5 0 2h 1402 5 MHz 1 3 7 5 5 Exact Frequency Tuning Due to quantization effects the absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fractional modulator For example a 24 bit fractional modulator has frequency resolution set by the phase detector PD comparison rate divided by 224 The value 224 in the denominator is sometimes referred to as the modulus Hittite PLLs use a fixed modulus which is a binary number In some types of fractional PLLs the modulus is variable which allows exact frequency steps to be achieved with decimal step sizes Unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period channel step size For this reason Hittite PLLs use a large fixed modulus Normally the step size is set by the size of the fixed modulus In the case of a 50 MHz PD rate a modulus of 224 would result in a 2 98 Hz step resolution or 0 0596 ppm In some applications it is necessary to have exact frequency steps and even an error of 3 Hz cannot be tolerated Fractional PLLs are able to generate exact frequencies with zero frequency error if N can be exactly represented in binary eg 50 0 50 5 50 25 50 75 etc Unfortunately some common frequencies cannot be exactly represented For example Nia 0 1 1 10 must be approximated
88. z and 4100 MHz e Output gain settings Reg 16h 7 6 Reg 16h 9 8 e Single ended or differential output operation Reg 17h 9 8 e Always Mute Reg 16h 5 0 e Mute when unlock Reg 17h 7 VCO Calibration VCO Auto Calibration AutoCal The HMC835LP6GE uses a step tuned type VCO A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center frequency of the VCO to be adjusted or stepped by switching in out VCO tank capacitors A step tuned VCO allows the user to center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near the mid voltage tuning point of the HMC835LP6GE s charge pump This enables the PLL charge pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning sensitivity kvco The VCO switches are normally controlled automatically by the HMC835LP6GE using the Auto Calibration feature The Auto Calibration feature is implemented in the internal state machine It manages the selection of the VCO sub band capacitor selection when a new frequency is programmed The VCO switches may also be controlled directly via register Reg 15h for testing or for other special purpose operation To use a step tuned VCO a closed loop the VCO must be calibrated such that the HMC835LP6GE knows which switch position on the VCO is optimum for the desired output frequency The HMC835LP6GE supports Auto Calibratio

HMC835LP6GE - Hittite Microwave Corporation

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