MDGG-8 User Manual
Contents
1. Parameters Reg in which ScalerInputSelector register to read 1 or 2 Return Value On success the value of the specified ScalerInputSelector register is returned Otherwise the return value is 0 Remarks 4 3 22 setLogicalMask The setLogicalMask function writes a given value to the specified LogicalMask register int setLogicalMask int reg unsigned long value j Parameters Reg in which LogicalMask register to write 1 or 2 value in the value to write to the LogicalMask register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks WIENER Plein amp Baus GmbH 28 www wiener d com Werk Sr Industrie elektironik WIENER 2 i ee efekivonit Plein amp Baus Elektro Regekon s 4 3 23 getLogicalMask The getLogicalMask function returns the value of the specified LogicalMask register unsigned long getLogicalMask int reg D Parameters Reg in which LogicalMask register to read 1 or 2 Return Value On success the value of the specified LogicalMask register is returned Otherwise the return value is 0 Remarks 4 3 24 getScalerData The getScalerData function returns the scaler value currently stored for a specified channel The number of values currently stored for a given channel can be read via the getScalerMultiplicity function unsigned long getScalerData int channel Parameters channel in which2. Baus Elektro Regeson s Parameters Reg in which FGGStopSelector register to write 1 or 2 value in the value to write to the FGGStopSelector register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 19 getFGGStopSelector The getFGGStopSelector function returns the value of the specified FGGStopSelector register unsigned long getFGGStopSelector int reg Parameters Reg in which FGGStopSelector register to read 1 or 2 Return Value On success the value of the specified FGGStopSelector register is returned Otherwise the return value is 0 Remarks 4 3 20 setScalerinputSelector The setScalerInputSelector function writes a given value to the specified ScalerInputSelector register int setScalerInputSelector int reg unsigned long value i Parameters Reg in which ScalerInputSelector register to write 1 or 2 value in the value to write to the ScalerInputSelector register WIENER Plein amp Baus GmbH 27 www wiener d com Werk Sr Industrie elekivonik WIENER i Toli efekivonit Plein amp Baus Elektro Regeln s Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 21 getScalerinputSelector The getScalerInputSelector function returns the value of the specified ScalerInputSelector register unsigned long getScalerInputSelector int reg
3. channel RO 16 2 3 15 Scaler Multiplicity Registers 0x120 4 channel RO 16 2 3 16 Coincidence Register 0x120 4 channel RO 16 3 Register Comparison MDGG8 vs MDGG I16 uuu0ssssssssnnnnnnnnensnsssnnnnnnn 17 4 S ftware SUPPO eek 19 4 1 Microsoft Windows Support cccccccessecesssasccaseessacasssssacccacastsnsdsssaacsansstcnsaes 19 4 2 LinX SU PONG E 19 43 MDGG 8 Lbray seien a 19 4 3 1 EES 19 4 3 2 EE 20 4 3 3 BellslobalResister essen el 20 4 3 4 SEI OBRIREF IT een 20 4 3 5 I ee 21 4 3 6 EE eege 21 4 3 7 SEID Ay Mine 22 4 3 8 BelDelay en nie 22 4 3 9 setActionRegister GARMBBRRSERSPEREHRNRERRGE SEORENIOLEEFEESEENTEERUOREEREEUVENSE AEUELERRERTE OHERERDDE 23 43 10 SEPP Onl PU Alon see 23 4 3 11 geifG6GConfiguration n sesenseine kn 23 4 3 12 setScalerConfiguration E 24 413 13 getScalerConfigurati h ee 24 43 14 setFGGInputSelector unsere 25 43 13 PEtPGOGIMPUISSle Cur rennen 25 WIENER Plein amp Baus GmbH 3 www wiener d com Plein amp Baus Elektronik 43 16 SEIN MOutpulSeleeier ass a 25 4 3 17 getNIMOutputSelector nee geed Eed EE 26 CNN ee 26 4 3 19 Bet POG ee 21 4 3 20 Een 27 4321 gelscalerinpulseleeor nn 28 4 3 22 setLogicalMask uniaseieainiieee elek 28 43 23 SED gen 29 BOOM Bet Scaler Aa E 29 4 3 25 getScalerMulitplicity u a ea 29 4 3 26 gelGoineidenceBesisten en 30 5 FitmwWw re BT
4. 8 base address of 0x10 0000 A24 2 2 Firmware programming The firmware can be changed via VME Jumper 25 should be in Normal RUN position right for standard use To program a new firmware please set this jumper to the PROGRAM position left Please see chapter 5 for firmware upgrade instructions WIENER Plein amp Baus GmbH 8 www wiener d com Werk Rir Indusivie elektronik WIENER Ke ee elekronik Plein amp Baus Elektro Regeln dos D 2 3 VME Register Map Offset Register Access Type 0x000 Firmware ID Read only 0x004 Global Register Read write 0x008 Auxiliary Register Read write 0x040 channel 8 Delay FGG channel Read write 0x044 channel 8 Gate FGG channel Read write 0x080 Action Register Write only 0x084 FGG Configuration Read write 0x088 Scaler Configuration Read write 0x08C FGG Input Selector A Read write 0x090 FGG Input Selector B Read write 0x094 NIM Output Selector A Read write 0x098 NIM Output Selector B Read write 0x09C FGG Stop Selector A Read write 0x0A0 FGG Stop Selector B Read write Ox0A4 Scaler Input Selector A Read write 0x0A8 Scaler Input Selector B Read write 0x0AC Combination Gate Mask A Read write OxOBO Combination Gate Mask B Read write 0x100 channel 4 Scaler Data channel Read only 0x120 channel 4 Scaler Latch Multiplicity channel Read only 0x140 Coinc
5. I Flash ROM Operations Stack Builder LED NIM Multiplexers Registers Stack Readback YME Operations 1 r Options Addr Mode 7 Hit Register Cais az H Wite z SC 7 Use Hit Pattern CAR r GC MELT IT Get BLT Count f F Prom WT No Auto Iner Data Bytes GE DE It GIS CEA Ce tot kort tt E Result DC A0 0100 Repeat r Stack Operations 0 Main IRQ X DAQ Test 1 Add Item Clear Start EvtTrig SclTrig Stop Coed Ze Read USB Buffer USBRes Display Execute ExeStack1 M Run Using YM USB VM0167 Running Firmware Yersion 58010903 gt Response 5C40 0100 3 Program new Firmware Set Jumper 25 into left Programm Position Run XXUSBWinAppli exe Start Go to Flash ROM Operations tab Select MDGGE WIENER Plein amp Baus GmbH 31 www wiener d com Werk f r WIENER ES Plein amp Baus Elektronik Regekmas fe Type in value for Base Address bits 19 to 23 is 2 for factory default Click on program and select the right firmware file Organize New folder z Fr Favorites Documents library PER ER E Desktop z Firmware E Downloads Se El Recent Places A MacroFiles RR Desktop J StackFiles ER Libraries _ mdgg16_082312 bit En mdgg16_0100_051612 bi Documents C emdgg8 102410 TYPE BIT File a Music GE Size 277 KB El Pictures _ dgg8R3_78001202_0708 H Date modified 8 27 2012 2 05 Ply B Videos Gel
6. On success the content of the MDGG 8 firmware revision register is returned Otherwise the return value is 0 Remarks 4 3 3 getGlobalRegister The getGlobalRegister function will return the content of the MDGG 8 global register unsigned long getGlobalRegister D Parameters Return Value On success the content of the MDGG 8 global register is returned Otherwise the return value is 0 Remarks 4 3 4 setGlobalRegister The setGlobalRegister function will write value into the global register of the MDGG 8 int setGlobalRegister unsigned long value WIENER Plein amp Baus GmbH 20 www wiener d com Plein amp Baus Elektronik j Parameters value in value that will be written to the MDGG 8 global register Return Value On success the return value will be gt 0 Otherwise the value will be lt 1 Remarks 4 3 5 setGate The setGate function writes a gate value to the specified FGG gate register int setGate int channel unsigned long gate j Parameters channel in the FGG channel whose gate should be set valid values 1 8 gate in the length to which the gate should be set in terms of 8ns steps Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 6 getGate The getGate function returns the gate of the specified FGG gate register unsigned long getGate int channel D Parameters channel in the FGG channel for which y
7. Registers 0x08C 0x090 RW There are two NIM output Selector Registers which are used to determine what signal is present on each of the NIM outputs O1 O8 Each NIM Ouput Selector Register sets 4 outputs The signal for each NIM output is specified by a 5 bit configuration word which specifies which signal will be present on the NIM connector The table below shows the valid values for the configuration word and which code corresponds to each available signal Code Output Signal Comments 0 7 FGG1 FGG8 The output will be a FGG signal 8 15 TrEdg1 TrEdg8 The output will be a signal on the trailing edge of FGG1 FGG8 16 19 CG1 CG 4 The output will be one of the combined gates CG1 CG2 The NIM output selection configuration words are combined into the two NIM output selector registers NIM Output Selector A 0x094 RW 4 Bits24 28 Bits 16 20 Bits 8 12 Bits 0 4 NIMOutSel 4 NIMOutSel 3 NIMOutsel 2 NIMOutSell NIM Output Selector B 0x098 RW Bits24 28 Bits 16 20 Bits 8 12 Bits 0 4 NIMOutSel 8 NIMOutSel 7 NIMOutSel 6 NIMOutSel 5 WIENER Plein amp Baus GmbH 2 3 11 FGG Stop Selector Registers 0x094 0x098 RW There are two Stop Selector Registers which are used to determine what signal resets an FGG that is set as set reset gate SRG A FGG set as a SRG will start the gate upon a trigger signal as set in the FGG Input selecto
8. any means with the express written permission of W Ie Ne R MDGG 8 is designed by JTEC Instruments WIENER Plein amp Baus GmbH 2 www wiener d com Werk Sr Industrie elektronik WIENER ez a ee efekivonit Plein amp Baus Elektro Regeln s Table of contents 1 General Kee E 5 1 1 Hardware AU rooe eene e da iota E EE A AEE SaS 5 1 2 Release firmware features preliminary eesssseessesseressrerressrersrsrrereserrrerssreees 6 2 E 8 2 1 VME Bas Nee 8 2 2 Finmware Pro er ane eege EEN 8 2 3 VME Register Map snedaamaubadaendansiadees 9 2 3 1 Firmware ID Register 0x000 ROT 9 2 3 2 Global Register 0x004 RW 9 2 3 3 Auxiliary Register 0x008 RW 10 2 3 4 Delay FGG 0x040 8 channel RWI nenne 10 2 3 3 Gate FGG 0x044 8 channel RW 22uesnsseeeeenneeneeen 11 2 3 6 Action Register 0x080 WO 11 2 3 7 FGG Configuration 0x084 RW REENEN 12 2 3 8 Scaler Configuration 0x088 RWI 12 2 3 9 FGG Input Selector Registers 0x08C 0x090 RW 13 2 3 10 NIM Output Selector Registers 0x08C 0x090 RW 14 2 3 11 FGG Stop Selector Registers 0x094 0x098 RW 14 2 3 12 Scaler Input Selector Registers 0x0A4 0x0A8 RW 15 2 3 13 Combination Gate Mask Registers 0x0AC 0x0B0 RW 15 2 3 14 Scaler Data Registers 0x100 4
9. setting up and reading the MDGG 8 This executable is an extension of the XXUSBwin program shipped with the VM USB 4 2 Linux Support WIENER supports Linux users by providing an open source C library to allow for easy setup and readout of the MDGG 8 when used in combination with the WIENER VM USB 4 3 MDGG 8 Library The WIENER supplied open source library has the same structure for both Windows and Linux users While the library is designed to work with the WIENER VM USB users should be able to modify to work with their VME crate controller as well since the source code is available The CMDGG 8 library provides the CMDGG 8 class for performing all of the necessary tasks for setting up and reading an MDGG 8 module 4 3 1 CMDGG The CMDGG is the constructor of the MDGG 8 class It creates a CMDGG object that all the member function will act upon CMDGG usb_dev_handle hdev unsigned long base D Parameters hdev in Pointer to the VM USB device handle Returned by xx_usb_device_open from the xx_usb library Base WIENER Plein amp Baus GmbH 19 www wiener d com Werk Fir Industrie WIENER Plein amp Baus Elektronik Regelungs technik in Base address of the MDGG 8 you wish to control Return Value Returns aMDGG object Remarks 4 3 2 getFirmware The getFirmware function will return the contents of the MDGG 8 firmware revision register unsigned long getFirmware D Parameters Return Value
10. specified value to the Scaler configuration register int setScalerConfiguration unsigned long value Parameters value in the value to write to the Scaler configuration register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 13 getScalerConfiguration The getFGGConfiguration function returns the value in the FGG Configuration register unsigned long getScalerConfiguration D Parameters Return Value On success the value of the ScalerConfiguration register is returned Otherwise the return value is 0 Remarks WIENER Plein amp Baus GmbH 24 www wiener d com Werk Rir Industrie elektironik WIENER i ee efekivonit Plein amp Baus Elektro Regeson s 4 3 14 setFGGInputSelector The setFGGInputSelector function writes a given value to the specified FGGInputSelector register int setFGGInputSelector int reg unsigned long value j Parameters Reg in which FGGInputSelector register to write 1 or 2 value in the value to write to the FGGInputSelector register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 15 getFGGinputSelector The getFGGInputSelector function returns the value of the specified FGGInputSelector register unsigned long getFGGInputSelectorf int reg D Parameters Reg in which FGGInputSelector register to read 1 o
11. 31 WIENER Plein amp Baus GmbH 4 www wiener d com WIENER ES 1 GENERAL DESCRIPTION The MDGG 8 is a single width VME module performing multifunction gate and delay generator and logic functions Most firmware revisions will allow users to create delay and gate generators count triggers perform logic AND s and digital FAN IN FAN OUT This manual will strive to describe the functionality of the of the latest firmware revision Details about how particular firmware revisions differ can be found in the appendix for that specific revision 1 1 Hardware features Although the functionality of the MDGG 8 is determined by the firmware that is loaded the firmware capabilities must fall within the parameters of the hardware The MDGG 8 is based on an XCS3S400 XLINX FPGA running with a 125MHz clock The module consists of INPUTS 8 channel inputs 1 common LEMO 00 OUTPUTS 8 channel outputs LEMO 00 LEDS 12 Diagnostic LED s driven by signal stretchers FIRMWARE Programmed via VME INTERFACE VME A24 D32 base address via jumpers VME IRQ Capable of asserting VME IRQ level selected via jumper POWER 5V 1A WIENER Plein amp Baus GmbH 5 www wiener d com Werk Sr Industrie elektronik WIENER 2 ie ee efekivonit Plein amp Baus Elektro Regeinge technik 1 2 Release firmware features preliminary The MDGG 8 can hold two separate firmware revisions in memory The user selects which firmware will load at startu
12. G signals or the 4 combined gates e Diagnostic LEDs LED 1 FPGA status e ON FPGA not configured e Flashing flash memory being configured e OFF MDGG 8 configured LED 2 DTACK Indicates VME access LED 3 Indicates signal on COMMON input WIENER Plein amp Baus GmbH 6 www wiener d com Werk Sr Industrie eiekvond WIENER i er efekivonit Plein amp Baus Elektroni Regeln s LED 4 Indicates signal on one or more of I1 I8 LED 5 12 Indicates signal on the corresponding output e VETO Reset input The common input can be configured as a VETO signal to block any of the eight regular inputs or as a reset to clear or latch the internal scalers e VME Resets and Triggering The internal scaler devices can be reset via VME Additionally the FGGs can be triggered or SRG can be reset through the VME interface e VME Interrupts VME interrupt support features depend on firmware WIENER Plein amp Baus GmbH 7 www wiener d com Plein amp Baus Elektronik 2 VME INTERFACE The MDGG 8 is access via the VME bus using A24D32 read writes or BLT reads 2 1 VME Base Address The 24 bit MDGG 8 base address is set via jumpers on the PCB A jumper that is inserted counts as a 1 in the base address bit pattern A23 A22 A21 A20 A19 AIS A17 A16 SN4 SN3 SN2 SN1 SNO 0 0 0 The factory default setting is with SN1 1 and a corresponding MDGG
13. G14 Gate DGG14 Delay FGG1 Gate FGG1 Delay FGG2 Gate FGG2 Delay FGG3 Gate FGG3 Delay FGG4 Gate FGG4 Delay FGG5 Gate FGG5 Delay FGG6 Gate FGG6 Delay FGG7 Gate FGG7 Delay FGG8 Gate FGG8 Action Register FGG Configuration Scaler Configuration FGG Input Selector A FGG Input Selector B NIM Output Selector A NIM Output Selector B FGG Stop Selector A FGG Stop Selector B Scaler Input Selector A Scaler Input Selector B Logical AND Mask A Logical AND Mask B IRQ 17 Access Type Read only Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Write only Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write Read write www wiener d com Werk Sr Industrie elektironik WIENER i ee elektronik Plein amp Baus Elektro Regekon s 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 Scaler Data 1 Scaler Data 2 Scaler Data 3 Scaler Data 4 Scaler Data 5 Scaler Data 6 Scaler Data 7 Scaler Data 8 Scaler Latch Multiplicity 1 Scaler Latch Multi
14. Werk f r Industrie elekivonik WIENER Af f ee elekronik Plein amp Baus Elektroni Regelungs Ber MDGG 8 User Manual WIENER Plein amp Baus GmbH 1 www wiener d com Firmware revision 0100 Werk Sr Industrie elekivonik WIENER i ee efekivonit Plein amp Baus Elektro Regeln s General Remarks The only purpose of this manual is a description of the product It must not be interpreted a declaration of conformity for this product including the product and software W Ie Ne R revises this product and manual without notice Differences of the description in manual and product are possible W Ie Ne R excludes completely any liability for loss of profits loss of business loss of use or data interrupt of business or for indirect special incidental or consequential damages of any kind even if W Ie Ne R has been advises of the possibility of such damages arising from any defect or error in this manual or product Any use of the product which may influence health of human beings requires the express written permission of W Ie Ne R Products mentioned in this manual are mentioned for identification purposes only Product names appearing in this manual may or may not be registered trademarks or copyrights of their respective companies No part of this product including the product and the software may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form by
15. channel RO The Coincidence register shows the coincidence pattern of I1 I8 during a gate This pattern can be read out via VME and must be cleared before it will accept the next gate WIENER Plein amp Baus GmbH 16 www wiener d com Werk Rir Industrie elektronik WIENER Ke er elekronik Plein amp Baus Elektro Regeln s 3 REGISTER COMPARISON MDGG8 VS MDGG 16 Offset 0x000 0x004 0x008 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0BO 0x0B4 MDGG 8 Register Firmware ID Global Register Auxiliary Register Delay FGG1 Gate FGG1 Delay FGG2 Gate FGG2 Delay FGG3 Gate FGG3 Delay FGG4 Gate FGG4 Delay FGG5 Gate FGG5 Delay FGG6 Gate FGG6 Delay FGG7 Gate FGG7 Delay FGG8 Gate FGG8 Action Register FGG Configuration Scaler Configuration FGG Input Selector A FGG Input Selector B NIM Output Selector A NIM Output Selector B FGG Stop Selector A FGG Stop Selector B Scaler Input Selector A Scaler Input Selector B Combination Gate Mask A Combination Gate Mask B WIENER Plein amp Baus GmbH MDGG 16 Register Firmware ID Global Register Auxiliary Register Delay DGG9 Gate DGG9 Delay DGG10 Gate DGG10 Delay DGG11 Gate DGG11 Delay DGG12 Gate DGG12 Delay DGG13 Gate DGG13 Delay DG
16. channel will trigger that FGG ResCReg Writing 1 to bit 24 of the Action Register will reset the Coincidence register WIENER Plein amp Baus GmbH 11 www wiener d com Werk Sr Indusivie elektronik WIENER He se efekivonit Plein amp Baus Elektro Regekon dos D 2 3 7 FGG Configuration 0x084 RW The eight FGG devices can be configured as a non retriggerable DGG a set reset gate a pulser a retriggable DGG a 1 n prescaler or a complimentary 1 1 n prescaler Additionally each FGG can be configured to be blocked via the VETO signal The settings for each FGG is stored in the FGG Configuration register The settings for each FGG is set in a 4 bit configuration word 3 Bits 0 2 VETO Behavior Valid values for the Behavior bits are Value Behavior Description 0 FGG off FGG will not respond to triggers 1 DGG FGG will act as a standard DGG that retriggers every time a trigger is received 2 SRG FGG will start the gate The gate will stay set until the reset signal is received 3 PG FGG will act as a pulser with the period equal to gate delay 4 RDGG FGG will act as a retriggable DGG The gate will be extended by the gate length if a new trigger arrives while the gate is still active 5 PSG FGG will act as a 1 n prescaler I need to research how exactly this will work 6 CPSG FGG will act as a 1 1 n prescaler This will make more sense af
17. ee be ellie sc Hamenroun File name mdggl6_082312 bit FPGA Configuration Files bit When programming the red F LED will flash and the red V LED will be flashing very fast be nearly on VME bus activitity Ofk ter D Ap Jar OU File Options Applictions Macro Help Flash ROM Operations Stack Builder if LED NIM Multiplexers Registers Atmel PEROM Operations Pram Made Reboot Get ID C XxUSB maa 2 here C CMDGG C CFB ULM52C IT Zero C Users andreas 8 27 2012 2 05 33 PM Done Using YM USB YM0167 TRunning Firmware Version 5801 0903 4 Check new Firmware Version with XXUSBWinAppli exe WIENER Plein amp Baus GmbH 32 www wiener d com Plein amp Baus Elektronik Return Jumper JP 25 into right RUN position Power VME crate Run XXUSBWinAppli exe Read A24 from Address 100000 hex should return firmware ID Compare with original version WIENER Plein amp Baus GmbH 33 www wiener d com
18. elektronik WIENER 2 2 ee efekivonit Plein amp Baus Elektro Regeln s t e ue pa me 8 10 delay For given register value ryatue the delay time tac ay can be calculated by reet 8 10 gate value 2 3 5 Gate FGG 0x044 8 channel RW The Gate FGG registers store the 32 bit gate length There are eight Gate FGG registers each corresponding to one of eight FGG Delay registers The Gate can be set with 8ns granularity with a maximum of 34s For a given gate length tate the register value ryalue can be calculated by t gate r value 8 10 For given register value Tyatue the gate length tgate can be calculated by toe a Lee gate value 2 3 6 Action Register 0x080 WO The Action Register allows the user to trigger FGGs reset SRGs reset scalers and or reset the coincidence register The action register automatically clears all bits 16ns after they are set Bit 24 Bits 16 23 Bits 8 15 Bits 0 7 ResCREG TrigFGG1 8 ResSclr1 8 ResFGG1 8 ResFGG1 8 Bits 0 7 correspond to FGG1 FGG 8 respectively Writing 1 to the bit corresponding to a given FGG channel will reset that SRG ResSclr1 8 Bits 8 15 correspond to SCL1 SCL 8 respectively Writing 1 to the bit corresponding to a given scaler channel will reset that scaler ResFGG1 8 Bits 16 23 correspond to FGG1 FGG 8 respectively Writing 1 to the bit corresponding to a given FGG
19. er Input Selector Registers 0x0A4 0x0A8 RW There are two Scaler Input Selector Registers which are used to determine which trigger signal is counted by a particular scaler Each FGG Input Selector Register sets the input trigger for 4 FGGs The input for each scaler is specified by a 5 bit configuration word which specifies which input or signal will be counted The table below shows the valid values for the configuration word and which corresponds to each countable signal Code Trigger Signal 0 7 I1 I8 8 15 FGG1 FGG8 16 19 CG1 CG 4 20 Common Input The FGG input selection configuration words are combined into the two FGG input selector registers Scaler Input Selector A 0x0A4 RW Bits24 28 Bits 16 20 Bits 8 12 Bits 0 4 SclrInSel 4 SclrInSel 3 SclrInSel 2 SclrInSel 1 Scaler Input Selector B 0x0A8 RW Bits24 28 Bits 16 20 Bits8 12 Bits 0 4 NIMOutSel 8 NIMOutsSel 7 NIMOutsSel 6 NIMOutSel 5 2 3 13 Combination Gate Mask Registers 0x0AC 0x0B0 RW There are two Combination Gate Mask Registers which are used to setup the 4 combination gates CG in the MDGG 8 The combination gates allow the user to trigger a gate based on a combination of logic ANDs and Ors of the input signals I1 I8 Each WIENER Plein amp Baus GmbH 15 www wiener d com Werk Air Indusivie elektronik WIENER 2 5 an efekironik Plein amp Baus Elektr
20. ger The configuration words for each scaler are combined in the scaler configuration register 28 31 24 27 20 23 16 19 12 15 8 11 4 7 Bits 0 3 SCLRS SCLR7 SCLR6 SCLRS5 SCLR4 SCLR3 SCLR2 SCLRI1 2 3 9 FGG Input Selector Registers 0x08C 0x090 RW There are two FGG Input Selector Registers which are used to determine which signal triggers the start ofa FGG Each FGG Input Selector Register sets the input trigger for 4 FGGs The input for each FGG is specified by a 5 bit configuration word which specifies which input or signal will be used to trigger the gate The table below shows the valid values for the configuration word and which correspond to each triggerable signal Code Trigger Signal 0 7 I1 I8 8 15 FGG1 FGG8 16 19 CG1 CG 4 20 Common Input The FGG input selection configuration words are combined into the two FGG input selector registers FGG Input Selector A 0x08C RW Bits24 28 Bits 16 20 Bits 8 12 Bits 0 4 TrigSelFGG4 TrigSelFGG3 TrigSelFGG2 TrigSelFGG1 FGG Input Selector B 0x090 RW Bits24 28 Bits 16 20 Bits 8 12 Bits 0 4 TrigSelFGG8 TrigSelFGG7 TrigSelFGG6 TrigSelFGG5 WIENER Plein amp Baus GmbH 13 www wiener d com Werk Sr Indusivie elektronik WIENER se efekivonit Plein amp Baus Elektro Regekon dos D 2 3 10 NIM Output Selector
21. idence Register Read only 2 3 1 Firmware ID Register 0x000 RO The Firmware ID register holds the firmware revision identifier 2 3 2 Global Register 0x004 RW The Global register stores information for the global signals that affect all different devices that the MDGG 8 is capable of providing Bits 24 28 Bits 16 20 Bits 8 12 Bits 0 4 SelMReset SelSclrLatch SelSclrGa SelFGGVeto SelFGG VETO This value specifies which signal or input will be used to VETO all FGGs that are configured to be susceptible to VETOs SelSclrGa This value specifies which signal or input will be used as the gate for internal scalers that are configured as gated scalers SelSclrLatch This value specifies which signal or input will be used as the latching signal for internal scalers that are configured as latched scalers WIENER Plein amp Baus GmbH 9 www wiener d com Werk Sr Industie efekironit WIENER elektronik Plein amp Baus Elektronik Regelngs technik SelMReset This value specifies which signal or input will be used as the master reset used to reset SRG scaler and the coincidence registers The valid signals for each of the settings in the Global Register are represented by a 5 bit code These codes are shown in the table below Values Signal Comments 0 None selected No signal will perform that function 1 8 I1 I8 1 8 corresp
22. o Regekngs technik CG has two 8 bit mask words that ware used to determine whether to trigger the gate using the following logic equation CGn AMASK n 1 AND NIM OR AMASK n 2 AND NIM where NIM is an 8 bit word representing the status ofthe 8 NIM inputs The mask words for two CGs are combined in each Combination Gate Mask Register Combination Gate Mask A 0x0AC RW Bits24 31 Bits 16 23 Bits 8 15 Bits 0 7 AMASK 2 2 AMASK 2 1 AMASK 1 2 AMASK 1 1 Combination Gate Mask A 0x0B0 RW Bits24 31 Bits 16 23 Bits 8 15 Bits 0 7 AMASK 4 2 AMASK 4 1 AMASK 3 2 AMASK 3 1 2 3 14 Scaler Data Registers 0x100 4 channel RO For each scaler a 1kx32 bit FIFO exists to store the scaler data The data is read via a VME call to the Scaler data registers The depth of the FIFO number values in the FIFO for each scaler channel can be read from the corresponding Scaler Latch Multiplicity Register For scalers operated only in gated mode the depth of the FIFO is always 1 Gated scalers must be reset before being able to accept a subsequent gate The Scaler Data Register can be read out via VME block transfers BLT 2 3 15 Scaler Multiplicity Registers 0x120 4 channel RO The scaler multiplicity register stores the depth number of 32 bit words that are stored in the Scaler Data FIFO for each scaler 2 3 16 Coincidence Register 0x120 4
23. onds to I1 I8 respectively 9 16 FGG1 FGG8 9 16 corresponds to FGG1 FGG8 respectively 17 20 CG1 CG4 17 20 corresponds to CG1 CG4 respectively 21 Common Input The common input will serve the function 2 3 3 Auxiliary Register 0x008 RW The Auxiliary Register determines which FGGs are cleared upon a master reset signal which signal is used to clear the coincidence register and whether the coincidence register is cleared upon a master reset signal Bits 13 Bits 8 12 Bits 0 7 CRegMResetMask SelCRegGa FGGMResetMask FGGMResetMask This 8 bit mask determines which FGG channels will be reset by a master reset signal SelCRegGa This value specifies which signal or input will be used to clear the coincidence register Valid values are Code Signal 0 7 I1 I8 8 15 FGG1 FGG8 16 19 CG1 CG 4 20 Common Input CRegMResetMask If this bit is set the coincidence register will be reset upon a master reset signal being received 2 3 4 Delay FGG 0x040 8 channel RW The Delay FGG registers store the 32 bit delay between receiving a trigger and the start of the gate There are eight Delay FGG registers each corresponding to one of eight FGG Gate registers The delay can be set with 8ns granularity with a maximum of 34s For a given delay time taelay the register value ryatue can be calculated by WIENER Plein amp Baus GmbH 10 www wiener d com Werk Sr Industrie
24. ou wish to return the gate value Return Value WIENER Plein amp Baus GmbH 21 www wiener d com Werk Rar Industrie elektironik WIENER 2 i er efekivonit Plein amp Baus Elektro Regeln s On success the value of the specified gate register is returned Otherwise the return value is 0 Remarks The gate value is returned as it is stored in the gate register To obtain the gate length multiply the non zero return value by 8ns 4 3 7 setDelay The setDelay function writes a delay value to the specified FGG delay register int setDelay int channel unsigned long delay j Parameters channel in the FGG channel whose gate should be set valid values 1 8 delay in the length to which the delay should be set in terms of 8ns steps Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 8 getDelay The getDelay function returns the delay of the specified FGG delay register unsigned long getDelay int channel D Parameters channel in the FGG channel for which you wish to return the delay value Return Value On success the value of the specified delay register is returned Otherwise the return value is 0 Remarks WIENER Plein amp Baus GmbH 22 www wiener d com Werk Sr Industrie eiektond WIENER ez i ee efekivonit Plein amp Baus Elektro Regeln s The delay value is returned as it is stored in the delay register To obtain
25. p via a jumper of the PCB The latest firmware revsions can be found at http www wiener d com Because of the open architecture of the module users are invited to develop custom firmware As of this writing the MDGG 38 ships with firmware revision 7930 0100 This firmware provides e 8 Flexible Gate and Delay Generators FGG Up to eight FGG s are individually configurable logic signals with flexible gates and delays They are programmable as non triggerable delay and gate generators DGG delay and retriggerable gate RDGG set resest gates SRG or pulse generators PG Alternatively the FGG s can be set as1 n PSG or 1 1 n CPSG prescaler gates The gates and delays are set with 8ns granularity up to 34s each e 8 Scaler Devices The eight scaler devices can be configured as either a gated scaler or a latched scaler Gated scalers GSC provide 32 bits of storage for each channel The latched scalers LSC provide each have a 1kx32 bit FIFO for storing the scaler data e Coincidence Register There is one 8 bit coincidence register to do something This register will record input coincidences e 4 Combined Gates There are up to four combined gates CG available for two fold Ors or eight fold ANDs of the module inputs This allows the user to build complex triggers e Output Mulitplexing The eight outputs can be multiplexed to have any one of 20 signals choosing from the 8 FGGs output signals trailing edge of the 8 FG
26. plicity 2 Scaler Latch Multiplicity 3 Scaler Latch Multiplicity 4 Scaler Latch Multiplicity 5 Scaler Latch Multiplicity 6 Scaler Latch Multiplicity 7 Scaler Latch Multiplicity 8 Coincidence Register WIENER Plein amp Baus GmbH Delay DGG15 Gate DGG15 Delay DGG16 Gate DGG16 LED NIM Select Scaler Data 1 Scaler Data 2 Scaler Data 3 Scaler Data 4 Scaler Data 5 Scaler Data 6 Scaler Data 7 Scaler Data 8 Scaler Latch Multiplicity 1 Scaler Latch Multiplicity 2 Scaler Latch Multiplicity 3 Scaler Latch Multiplicity 4 Scaler Latch Multiplicity 5 Scaler Latch Multiplicity 6 Scaler Latch Multiplicity 7 Scaler Latch Multiplicity 8 Coincidence Register 18 Read write Read write Read write Read write Read write Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only www wiener d com Werk Sr Industrie elektronik WIENER Ge eer elektronik Plein amp Baus Elektro Regeln s 4 SOFTWARE SUPPORT WIENER supplies software support for the MDGG 8 when it is used in combination with the VM USB VME crate controller 4 1 Microsoft Windows Support WIENER support of the MDGG 8 under Microsoft Windows comes in two forms The first is an open source C DLL which will provide an easy way to develop custom applications for the MDGG 8 and VM USB Additionally a prepackaged executable is available for
27. r 2 Return Value On success the value of the specified FGGInputSelector register is returned Otherwise the return value is 0 Remarks 4 3 16 setNIMOutputSelector The setNIMOutputSelector function writes a given value to the specified NIMOutputSelector register int setNIMOutputSelector WIENER Plein amp Baus GmbH 25 www wiener d com Werk Rir Industrie elektironik WIENER i ee efekivonit Plein amp Baus Elektroni Regeson s int reg unsigned long value j Parameters Reg in which NIMOutputSelector register to write 1 or 2 value in the value to write to the NIM Output Selector register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 17 getNIMOutputSelector The getNIMOutputSelector function returns the value of the specified NIMOutputSelector register unsigned long getNIMOutputSelector int reg Parameters Reg in which NIMOutputSelector register to read 1 or 2 Return Value On success the value of the specified NIMOutputSelector register is returned Otherwise the return value is 0 Remarks 4 3 18 setFGGStopSelector The setFGGStopSelector function writes a given value to the specified FGGStopSelector register int setFGGStopSelector int reg unsigned long value j WIENER Plein amp Baus GmbH 26 www wiener d com Werk Rir Industrie elektironik WIENER i ee efekivonit Plein amp
28. r registers That gate will remain active until a stop signal is received The stop signal can come from a master reset subject to the FGGMResetMask in the Auxiliary Register a VME reset via the Action Register or from a signal specified in the FGG Stop Selector Register The reset for each FGG is specified by a 5 bit configuration word which specifies which signal will reset a given SRG The table below shows the valid values for the configuration word and which code corresponds to each available signal Code Reset Signal Comments 0 7 ID The reset will be performed upon a signal in the corresponding input 8 15 TrEdg1 TrEdg8 The reset be performed on the trailing edge of FGG1 FGG8 16 19 CG1 CG 4 The reset will be performed upon signal from one of the combined gates CG1 CG2 14 www wiener d com Werk Rar Jndustvie efekironit WIENER Ka Bar elekironit pi amp Baus Elektro Regeln CG 20 Common Input The rest will performed upon signal from the common input The FGG Stop selection configuration words are combined into the two FGG Stop selector registers FGG Stop Selector A 0x09C RW Bits24 28 Bits 16 20 Bits8 12 Bits 0 4 NIMOutSel 4 NIMOutSel 3 NIMOutsSel 2 NIMOutSell FGG Stop Selector B 0x0A0 RW Bits24 28 Bits 16 20 Bits 8 12 Bits 0 4 NIMOutSel 8 NIMOutSel 7 NIMOutSel 6 NIMOutSel 5 2 3 12 Scal
29. ter figuring out the PSG If bit 3 of the configuration word is set the FGG will not respond to triggers while a VETO signal is present The configuration words for each FGG are combined in the FGG configuration register 28 31 24 27 20 23 16 19 12 15 8 11 4 7 Bits 0 3 FGG8 FGG7 FGG6 FGG5 FGG4 FGG3 FGG2 FGG1 2 3 8 Scaler Configuration 0x088 RW The Scaler Configuration allows the user to set each scaler as a gated latched or gated latched scaler The settings for each scaler are set via a 4 bit configuration word 3 Bits 0 2 MReset Behavior Valid values for the Behavior bits are Value Behavior Description 0 Scaler Off Scaler will not count WIENER Plein amp Baus GmbH 12 www wiener d com Dee WIENER ES de Plein amp Baus Elektronik ee et ve Gated Scaler Scaler will count triggers anytime the gated is active and will suspend counting when the gate is inactive The count is stored in a 32 bit register 2 Latched Scaler Scaler will count until a latch signal is received The count will be placed in 1kx32 bit FIFO and a new count will begin 3 Gated Scaler will act as a latched scaler but will suspend count Latched Scaler counting when the gate is inactive If bit 3 of the configuration word is set the scaler count will be reset via a master reset trig
30. the delay length multiply the non zero return value by 8ns 4 3 9 setActionRegister The setActionRegister function writes a specified value to the action register int setActionRegister unsigned long value j Parameters value in the value to write to the action register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks The action register acts as a momentary switch when a value written to the register some action is performed and the register is cleared in the next FPGA cycle 4 3 10 setFGGConfiguration The setFGGConfiguration function writes a specified value to the FGG configuration register int setFGG Configuration unsigned long value Parameters value in the value to write to the FGG configuration Register Return Value On Success the return value will be gt 0 Otherwise the return value will be lt 1 Remarks 4 3 11 getFGGConfiguration The getFGGConfiguration function returns the value in the FGG Configuration register WIENER Plein amp Baus GmbH 23 www wiener d com Werk Sr Industrie elekivonik WIENER i ee efekivonit Plein amp Baus Elektro Regeln s unsigned long getFGGConfiguration D Parameters Return Value On success the value of the FGG Configuration register is returned Otherwise the return value is 0 Remarks 4 3 12 setScalerConfiguration The setScalerConfiguration function writes a
31. which scaler to read 1 8 Return Value On success the scaler value is returned Otherwise the return value is 0 Remarks 4 3 25 getScalerMulitplicity The getScalerMulitplicity function returns the depth of the scaler FIFO for a specified channel unsigned long getScalerMulitplicity int channel WIENER Plein amp Baus GmbH 29 www wiener d com Werk f r oos WIENER Plein amp Baus Elektronik Regelungs technik D Parameters channel in which scaler multiplicity to read 1 8 Return Value On success the scaler multiplicity is returned Otherwise the return value is 0 Remarks 4 3 26 getCoincidenceRegister The getCoincidenceRegister function returns the current value of the coincidence register unsigned long getCoincidenceRegister Parameters Return Value On success the coincidence register is returned Otherwise the return value is 0 Remarks WIENER Plein amp Baus GmbH 30 www wiener d com Plein amp Baus Elektronik 5 FIRMWARE UPGRADE PROCEDURE Hardware needed VM USB Software XXUSBWinAppli exe 1 Check Base address of MDGG 16 following example shown for factory default bade address 0x100000 2 Check current Firmware Version with XXUSBWinAppli exe Leave Jumper JP 25 in right RUN position Power VME crate Run XXUSBWinAppli exe Read A24 from Address 0x100000 hex should return firmware ID D XXUSBWin VMO167 Sem File Options Applictions Macro Help DAQ
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