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1. 5 64 Deterministic Opcode Tracking 5 64 MC68340 USER S MANUAL ix 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Continued Paragraph Page Number Title Number 5 6 1 3 On Chip Hardware Breakpoint 5 64 5 6 2 Background Debug Mode sese 5 65 5 6 2 1 Enabling BDM aa erdt ote rte lee eae teed tec dud 5 65 5 6 2 2 BD SOURCES o Qa ONE NUN Ue DUM MS 5 66 5 6 2 2 1 External BKPT Signal eter itt bx reli cxi seated 5 66 5 6 2 2 2 5 66 5 6 2 2 3 Double Bus Paullo etn notitiae 5 66 5 6 2 3 BD esee reb 5 66 5 6 2 4 Command EXOQUPOL sro en rne eue cae 5 67 5 6 2 5 BDM Registers 5 67 5 6 2 5 1 Fault Address Register FAR ce coto UR C ictus 5 67 5 6 2 5 2 Return Program Counter RPO sess 5 67 5 6 2 5 3 Current Instruction Program Counter 5 67 5 6 2 6 Returning from BDM 5 68 5 6 2 7 Serial PH Y 5 68 5 6 2 7 1 CPU Beta EOS doeet tae d 5 69 5 6 2 7 2 Development System Serial
2. 7 31 7 41 11 Auxiliary Control Register 22244240 0 0 7 32 7 4 1 12 Interrupt Status Register IGI ioo teo 7 32 7 4 1 13 Interrupt Enable Register IER esses 7 34 7 4 1 14 Iripplb POTE TIB La oec euet italie i E RE 7 35 7 4 1 15 Output Port Control Register 7 35 7 4 1 16 Output Port Data Register OP 7 37 7 4 1 17 Mode Register 2 un e utut um cde qu reds 7 37 7 4 2 7 40 7 4 2 1 Serial Module Initialization 7 40 7 4 2 2 I O Driver Example estes Rene iet 7 40 7 4 2 3 Interrupt Pahdlilig 2e te eon ete nas reer ee ean 7 40 7 5 Serial Module Initialization Sequence esses 7 46 7 5 1 Serial Module Configuration essent 7 46 7 5 2 Serial Module Example Configuration Code 7 47 Section 8 Timer Modules 8 1 Module Overview tte ose entr rece a c 8 1 8 1 1 Timer and Counter EuUroloris ee oot rte iio eese 8 2 8 1 1 1 Prescaler GOBTIIGr aoreet tein dant dat cae ie 8 2 8 1 1 2 Timeout
3. 3 5 3 4 DSACK BERR and HALT Assertion 3 33 4 1 Clock 4 9 4 2 System Frequencies from 32 768 kHz 4 13 4 3 Glock GontrolSlgtials c totu atten an 4 13 4 4 Port A Pin Assignment Register 000 4 15 4 5 Port B Pin Assignment Register aoo I eO E ech 4 16 4 6 SHENX Control BITS wack 4 22 4 7 Deriving Software Watchdog Timeout eese 4 25 4 8 BMIX Encodings ocio 4 26 4 9 ila ME miror c 4 26 4 10 DDX Encoding s oe inde oae 4 32 SSC ECOG diode ve oet cd ed as 4 32 5 1 Pd 5 6 5 2 Instruction Set SUT ie odia eode ptt ede ds 5 16 5 3 Condition Code Computations essent 5 20 5 4 Data Movement 5 21 5 5 Integer Arithmetic Operators s casta edit ca dotate ie citta etude 5 23 5 6 LOGICS RATONS mace RP 5 24 5 7 Shift and Ro
4. 6 38 Section 7 Serial Module 7 1 Module OVervil8W itr ei t pe tee ttn edt sia Ede oa 7 2 7 1 1 Serial Communication Channels A and 7 3 7 1 2 Baud Rate Generator Logic essere 7 3 7 1 3 Internal Channel Control Logic esee 7 3 7 1 4 Interrupt Control 7 3 Xii MC68340 USER S MANUAL MOTOROLA 11 2 95 Number 7 1 5 7 2 7 2 1 7 2 2 7 2 3 7 2 4 7 2 5 7 2 6 7 2 7 7 2 8 7 2 8 1 7 2 8 2 7 2 9 7 2 9 1 7 2 9 2 7 2 10 7 2 11 7 2 12 7 2 12 1 7 2 12 2 7 2 13 7 2 13 1 7 2 13 2 7 2 13 3 7 3 7 3 1 7 3 2 7 3 2 1 7 3 2 2 7 3 2 3 7 3 3 7 3 3 1 7 3 3 2 7 3 3 3 7 3 4 7 3 5 7 3 5 1 7 3 5 2 7 3 5 3 7 4 7 4 1 7 4 1 1 MOTOROLA SECTION 1 OVERVIEW UM Rev 1 TABLE OF CONTENTS Continued Page Title Number Comparison of Serial Module to MC68681 7 4 Serial Module Signal 00 4 7 4 Crystal Input or External Clock X1 esses 7 5 Crystal OUIDUL DX 2 7 5 External Input C9 LIS y 7 6 Channel A Transmitter Serial Data Output TxDA 7 6 Channel A Receiver Serial Data Input
5. CS o 1 pese cEmue L3 o see La o pesseEmue TGE Timing Gate Enable 1 The TGATE signal is enabled to control the enabling and disabling of the prescaler and counter except in the input capture output compare mode see 8 3 1 Input Capture Output Compare 0 The TGATE signal has no effect on the timer operation PCLK Prescaler Clock Select This bit selects which clock is used for the counter clock 1 The counter is decremented by the prescaler output tap as selected by the POT field in the CR 0 The counter is decremented by the selected clock The prescaler continues to decrement regardless of how PCLK is set CPE Counter Prescaler Enable 1 The selected clock is enabled If the TGE bit is set then TGATE must also be asserted except in the input capture output compare mode 0 The selected clock is held high halting the prescaler and counter CLK Clock 1 The selected clock is taken from the TINx input 0 The selected clock is one half the system clock s frequency The TOUTx of one timer be fed externally into the TINx input of the other timer resulting in a 32 bit counter if the prescalers are not used and a 48 bit counter if they are used MOTOROLA MC68340 USER S MANUAL 8 21 POT2 POTO Prescaler Output If PCLK is set these bits encode which of the prescaler s output taps act
6. 5 71 5 6 2 8 tere teeter pee 5 73 5 6 2 8 1 Command o oe bed eles 5 73 5 6 2 8 2 Command Sequence Diagram sse 5 74 5 6 2 8 3 Command Set 9umimaly scies os eu mi 5 75 5 6 2 8 4 Read A D Register 5 76 5 6 2 8 5 Write A D Register WAREG WDREG 5 77 5 6 2 8 6 Read System Register RSREQ sss 5 77 5 6 2 8 7 Write System Register WSREQ sse 5 78 5 6 2 8 8 Read Memory Location READ sss 5 79 5 6 2 8 9 Write Memory Location WRITE seen 5 79 5 6 2 8 10 Dump Memory Block DUMP CREER s 5 80 5 6 2 8 11 Fill Memory Block FILL uocauit desit ttti rre ete thes ed 5 82 5 6 2 8 12 Resume Execution GO een enean 5 83 5 6 2 8 13 Call User Code ORLL aede re petiere 5 83 5 6 2 8 14 Reset Peripherals 5 85 5 6 2 8 15 No Operallon oie itu oce 5 85 5 6 2 8 16 Euture Commands ttr ettet 5 86 5 6 3 Deterministic Opcode Tracking eese 5 86 5 6 3 1 Instruction Fetch IB E EO eir 5 86 5 6 3 2 Instruction Pipe PIPE ed
7. 1 6 1 3 1 3 Melee Ac S 1 6 1 3 1 4 Chip Select and Wait State 1 6 1 3 1 5 Irntertupb Fiandlinges oot ti ice hahet 1 6 1 3 1 6 LO PINS aros ood bein caet 1 6 1 3 1 7 IEEE 1149 1 Test Access Port eese 1 7 1 3 2 Direct Memory Access Module seen 1 7 1 3 3 Serial sont tb Ene 1 7 1 3 4 timer Modules minnn 1 8 1 4 Power Consumption 1 8 1 5 PUNY SICA 1 9 1 6 4 aeui oreet 1 9 1 7 More Information cece eee a tsi 1 10 Section 2 Signal Descriptions 2 1 Signal Index tuetur totu Pay Weare 2 2 2 2 Address c 2 4 2 2 1 Address Bus 23 0 iicet ruv Mu repite t bod n ie 2 4 2 2 2 Address BUS AS 1 24 cuc etta te UE E RN ptu 2 4 2 3 Data BIS OEHEDSDO fett dct 2 4 2 4 Function Codes FOSSE ss aud bie up RUE 2 5 2 5 Chip Selects 993 0 SO 4a bre rst ers 2 5 2 6 Interrupt Request Level IRQ7 IRQ6 IRQ5 2 6
8. esL D 5 53 Types of c i ice cM 5 55 Type I Released Write 22222 1 5 55 Type II Prefetch Operand RMW and MOVEP Faults 5 56 Type III Faults During MOVEM Operand Transfer 5 57 Type 5 During Exception Processing 5 57 Co rrecting a P quit cona ete eat Eo B eeu 5 57 Type I Completing Released Writes via Software 5 57 Type I Completing Released Writes via RTE 5 57 Type lIl Correcting Faults via 5 58 Type lll Correcting Faults via 5 58 Type III Correcting Faults by Conversion and Restart 5 58 Type Ill Correcting Faults via RTE esses 5 59 Type IV Oorrecting Faults via Software 5 59 GPUSZ Stack Frames 5 60 Four Word Stack Erame e a eet 5 60 Six Wold Stack Frater eter eec ees 5 60 Bis Error Stack EIafTiG us crei pee dE etc dca ma ee 5 60 Development 5 63 CPU32 Integrated Development 5 63 Background Debug Mode
9. 5 7 Privilege States 5 7 Architecture Summary Aerie eee Oe A 5 8 POOR IIIT das 5 8 5 10 RD 5 11 M68000 Family Compatibility esee 5 11 New SURG ONS MP Tc RU 5 11 Low Power Stop LPSTOP iiiter ette beet ne en t 5 11 Table Lookup and Interpolation 5 12 Unimplemented Instructions seen 5 12 Instruction Format and 5 12 Instruction D 5 15 Condition Code 5 20 Data Movement Instructions o erect De tette 5 21 Integer Arithmetic Operations esee 5 22 Logic Instt e loris qt tette trace ceca 5 24 Shift and Rotate Instructions essen 5 24 Bit Manipulation 1 51 5 25 Binary Coded Decimal BCD Instructions 5 26 Program Control Insttotlls cuu iced c ede P t dee 5 26 System Control Instructions eoe i eae ee 5 27 Condition TS SUG E 5 29 Using the TBL Instructions texte t
10. 5 94 Timing Example 2 Branch Instructions sss 5 95 Timing Example 3 Negative Tails sss 5 96 Instruction Timing Tables uote eet 5 97 Fetch Effective Address 5 99 Calculate Effective Address esses 5 100 MOVE ns FU HOT oss cerei 5 101 Special Purpose MOVE Instruction eese 5 101 Arithmetic Logic Instructions essent 5 102 Immediate Arithmetic Logic Instructions esses 5 105 Binary Coded Decimal and Extended Instructions 5 106 single Operand o nai e ett t ecce 5 107 Shift Rotate Instructions eeessseseeeeenenne teens 5 108 Bit Manipulation Instit ietlOlis quesos 5 109 Conditional Branch Instructions sese 5 110 Control INSTFUCTIONS Mel 5 111 Exception Related Instructions and Operations 5 111 Save and Restore Operations esses 5 111 Section 6 DMA Controller Module DMA Module OVSrViQW eoe paio ek a edits 6 2 DMA Module Signal Definitloris ene rnt Ree 6 4 ete epp 6 4 DMA Acknowledge
11. 04404 0 2 0 1 000000000 01 8 2 8 1 1 3 8 2 8 1 1 4 Glock SOI CHGS iu ont 8 3 8 1 2 Internal Control EGG C 25 hie nate a 8 3 8 1 3 Interrupt Control LOGIC aiite t desserts iue 8 4 8 2 Timer Modules Signal Definitions esses 8 4 8 2 1 Timer Input TIN1 deco ede nieder eee e 8 5 8 2 2 Timer Gate TGATE1 TGATE2 sss 8 6 8 2 3 Timer Output TOUT 1 TODT2 tainen ec ete eene 8 6 8 3 wt uto en tate 8 6 8 3 1 Input Capture Output 8 6 8 3 2 Square Wave GeMeratOl eccececcecceceeesceeeeeceeeeececeaeeeesceaeeeeeeeeeeseeeeeeseaees 8 8 xiv MC68340 USER S MANUAL MOTOROLA 11 2 95 Number 8 3 3 8 3 4 8 3 5 8 3 6 8 3 7 8 3 8 8 3 9 8 3 9 1 8 3 9 2 8 3 9 3 8 4 8 4 1 8 4 2 8 4 3 8 4 4 8 4 5 8 4 6 8 4 7 8 4 8 8 5 8 5 1 8 5 2 10 1 10 1 1 MOTOROLA SECTION 1 OVERVIEW UM Rev 1 TABLE OF CONTENTS Continued Page Title Number Variable Duty Cycle Square Wave 8 9 Variable Width Single Shot Pulse Generator 8 10
12. eese 10 10 10 3 Power Consumption Considerations eese 10 10 10 3 1 MC68340 Power Reduction at sese 10 11 10 3 2 MC68340V 3 3 V sabe udo etc topi rl He PUR UR UR 10 13 Section 11 Electrical Characteristics 11 1 Rating aseo oet esee ed te teo 11 1 11 2 Thermal 11 1 11 3 Power Considerations ied cg te tad itur toda 11 2 11 4 AC Electrical Specification Definitions esses 11 2 11 5 DC Electrical Specifications centers ois iunt tee eb ceo ead 11 5 11 6 AC Electrical Specifications Control 11 6 11 7 AG Tm SpecificatioNS nien 11 8 11 8 DMA Module AC Electrical 11 19 11 9 Timer Module Electrical Specifications sess 11 20 11 10 Serial Module Electrical 11 22 11 11 IEEE 1149 1 Electrical 11 25 Section 12 Ordering Information and Mechanical Data 12 1 Standard MC68340 Ordering Information 12 1
13. 5 10 5 6 Instruction Word General 5 12 5 7 Table Example hes ean ee 5 30 5 8 Table Example 5 31 5 9 Table Example cc 5 33 5 10 Exception Stack PralTie i iced o itr entren 5 42 5 11 Reset OperatohHloWCPh ATE sss ea ou nacta is p ce Rute 5 45 5 12 Format 0 Four Word Stack Frame sese 5 60 5 13 Format 2 Six Word Stack Frame sse 5 60 5 14 Internal Transfer Count 5 61 5 15 Format C BERR Stack for Prefetches and 5 62 5 16 Format C BERR Stack on MOVEM 5 62 5 17 Format C Four and Six Word BERR 5 63 5 18 1 Emulator COMNGUTATION auae occ tec tet ett mra ie pete eus 5 64 5 19 State Analyzer Configuration essere 5 64 5 20 BDM Block BIagEalT 5 65 5 21 Command Execution Flowchart essen 5 68 5 22 Debug Serial I O Block 0444400 5 70 5 23 Serial Interface Timing 5 71 5 24 BKPT Timing for Single Bus Cycle 5 72 5 25 Timing for Forcing BDM su
14. 7 6 Channel B Transmitter Serial Data Output 7 6 Channel B Receiver Serial Data Input 7 6 Channel A Request To Send RTSA 7 6 HITS ono LEID REEL 7 6 opc pr PRSE 7 6 Channel B Request To Send 7 6 RISB MN PE 7 7 OPI 7 7 Channel Clear To Send CTSA sse 7 7 Channel Clear To Send 7 7 Channel A Transmitter Ready 7 7 TD Aio ais o dus 7 7 PD qui imn d EE 7 7 Channel A Receiver Ready 7 7 156 Alco E E OEUVRE 7 7 gg NH nee chalet e caged aay be tensile a alae ae 7 7 ber tems 7 7 LC MP 7 8 Baud Bate Genera Ors a eue eee Rp deae 7 8 Transmitter and Receiver Operating 7 8 MIC D DI MILI DN
15. Figure 5 16 Format C BERR Stack on MOVEM Operand 5 62 MC68340 USER S MANUAL MOTOROLA SP STATUS REGISTER 02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 06 1 1 0 0 VECTOR OFFSET 08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW 0C PRE EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMAT VECTOR WORD 10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH SIX WORD FRAME ONLY FAULTED INSTRUCTION PROGRAM COUNTER LOW SIX WORD FRAME ONLY 14 INTERNAL TRANSFER COUNT REGISTER 16 1 0 SPECIAL STATUS WORD Figure 5 17 Format C Four and Six Word BERR Stack 5 6 DEVELOPMENT SUPPORT All M68000 family members have the following special features that facilitate applications development Trace on Instruction Execution All M68000 processors include an instruction by instruction tracing facility to aid in program development The MC68020 MC68030 and CPU32 can also trace those instructions that change program flow In trace mode an exception is generated after each instruction is executed allowing a debugger program to monitor execution of a program under test See 5 5 2 10 Tracing for more information Breakpoint Instruction An emulator can insert software breakpoints into target code to indicate when a breakpoint occurs On the MC68010 MC68020 MC68030 CPU32 this function is provided via illegal instructions 4848 484F that
16. 401 020 020 0 0 0 024041 0 61 6 4 DMA Don DONE emis 6 4 Transfer Request Generation eese 6 4 Internal Request Generation sse 6 4 Internal Request Maximum Rate sss 6 5 Internal Request Limited 2 24 101 6 5 External Request Generation eese 6 5 External Burst 6 5 MC68340 USER S MANUAL xi 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Continued Paragraph Page Number Title Number 6 3 2 2 External Cycle Steal eese 6 5 6 4 Data Transfer MOd6S c see ob b e UE Sim 6 6 6 4 1 Single Address Mot 6 6 6 4 1 1 Single AdUress Redd sa ooo eate phi aste turae au 6 7 6 4 1 2 Single Address 2 88 6 9 6 4 2 D al Address Modere conet a eue 6 12 6 4 2 1 Dual Address Head aate Se eed 6 12 6 4 2 2 Dual Address Wille 45 deii adeo tei 6 14 6 5 BUS JAEDIT QUOI oon ceo en dante 6 18 6 6 DMA Channel Operation 2o dtc ee Pee pa te 6 18 6 6 1 Channel Initialization and Startups 6 18 6 6 2 Data Transfers aaae T T 6 19 6 6 2 1 Internal Request Transfers sess 6 19 6 6 2 2 External
17. m s vo we 5 t9 sox ww we s ioca ws v wa ae rem vex m 9 ocen as vo abc 44 Orach packi output as onan owe ono e wm mower omo Par rece ww 48 Otath DACK2 Oups 49 Donez s en owe ow 52 ioco mc 53 Ocen 06 10 54 oco igo 5e ocw ic 58 e 27 TGATE2 ef wow ca 29 ou2ct 6 30 Pm mu ien mut 66 mon com S2 Olan Oups 6 ocen ro vo deci 99 Olan RTSA Oups e ocen Dt vo wm om ma v vo MOTOROLA MC68340 USER S MANUAL 9 5 Table 9 2 Boundary Scan Bit Definitions Continued EXPE Cell Type Name Type CTL Cell 78 ocen o vo doch 75 cer os vo 7e cer Do vo 80 vo doch Pas oon Le oo te eoo wer Le vo woo Le ws vo awe
18. and RxDx 10 4 MC68340 USER S MANUAL MOTOROLA 15 pF j 3 6864 MHz EG X1 2 Spo MC68340 Rxl RxDx Txl TxDx lt 232 CONNECTOR Figure 10 7 Serial Interface 10 2 MEMORY INTERFACE INFORMATION The following paragraphs contain information on using an 8 bit boot ROM performing access time calculations calculating frequency adjusted outputs and interfacing an 8 bit device to 16 bit memory using the DMA channel single address mode 10 2 1 Using an 8 Bit Boot ROM Upon power up the MC68340 uses CSO to begin operation CSO is a three wait state 16 bit chip select until otherwise programmed If an 8 bit ROM is desired external circuitry be added to return an 8 bit DSACK in two wait states see Figure 10 8 393 CLKOUT CP Q0 01 O DSACKO Q2 cso MR Q3 Figure 10 8 External Circuitry for 8 Bit Boot ROM The 393 is a falling edge triggered counter thus CSO is stable during the time in which it is being clocked CSO acts as the asynchronous reset i e when it is asserted the 393 is allowed to count The falling edge of S2 provides the first counting edge Q1 does not transition on this falling edge but transitions to a logic one on the subsequent edge DSACKO is Q1 inverted thus on the next falling edge DSACKO is seen as asserted indicating an 8 bit port When 50 is negated Q1 is again held in reset and DSACKO is negated The timing diagram in Fig
19. lt gt WRITE INTERNAL STACK CYCLE gt PROCESSING WRITE Figure 3 18 Late Bus Error with DSACK 3 5 2 Retry Operation When both BERR and HALT are asserted by an external device during a bus cycle the MC68340 enters the retry sequence shown in Figure 3 19 A delayed retry which is similar to the delayed signal described previously can also occur see Figure 3 20 The MC68340 terminates the bus cycle places the control signals in their inactive state and does not begin another bus cycle until the BERR and HALT signals are negated by external logic After a synchronization delay the MC68340 retries the previous cycle using the same access information address function code size etc BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle 3 36 MC68340 USER S MANUAL MOTOROLA DSACKx N nn AAA 2777 BERR HALT lt READ CYCLE WITH gt lt HALT gt lt READ RERUN gt RETRY Figure 3 19 Retry Sequence The MC68340 retries any read or write cycle of a read modify write operation separately RMC remains asserted during the entire retry sequence Asserting BR along with BERR and HALT provides a relinquish and retry operation The MC68340 does not relinquish the bus during a read modify write operation Any device that requires the MC68340 to give up the
20. wow wsa woo Fe a vo 98 aso 10 o9 aoa NOTES pz s Cell Type Name Type CTL Cell 10 m vo 112 Olan Output H3 BR mut jo bera 1000 modkci ifetch ctl Les Oraon Freeze Own D mw iem we modck ctl ifetch ctl 114 115 116 117 118 119 120 121 122 123 124 125 126 127 The noted pins are implemented differently than defined in the signal definition description Input during Motorola factory test Output during Motorola factory test 9 6 MC68340 USER S MANUAL MOTOROLA 1 EXTEST TO NEXT 0 OTHERWISE SHIFT DR CELL DATA FROM SYSTEM TO OUTPUT LOGIC BUFFER FROM CLOCK DR UPDATE DR LAST CELL Figure 9 3 Output Latch Cell O Latch 1 EXTEST 0 OTHERWISE TONEXT INPUT PIN UPDATE DR CLOCK DR FROM LAST SHIFT DR CELL Figure 9 4 Input Pin Cell MOTOROLA MC68340 USER S MANUAL 9 7 1 EXTEST TO NEXT 0 OTHERWISE CELL OUTPUT CONTROL TO OUTPUT FROM SYSTEM ENAS E LOGIC 1 DRIVE 1D S C1 R SHIFT DR FROM CLOCK DR RESET LAST CELL UPDATE DR
21. 0715200 3 4 Data Stobe rb E fr 3 4 Bus Cycle Termination 4 4 3 4 Data Transfer and Size Acknowledge Signals DSACK1 and DSACKO sss 3 4 BUS Emon eda Ra Qu tru e AERE NA 3 5 52 3 5 Data Transfer 2 intet 3 5 Dynamic Bus FIZ IIA aod tutos as thee tata ip 3 5 ve P oce ie Deer e 3 7 Operand Transfer Cases 3 7 Byte Operand to 8 Bit Port Odd or Even AO 3 7 Byte Operand to 16 Bit Port Even AO 0 3 8 Byte Operand to 16 Bit Port Odd AO 1 3 9 Word Operand to 8 Bit Port 3 9 Word Operand to 16 Bit Port 3 10 Long word Operand to 8 Bit Port 3 10 Long Word Operand to 16 Bit Port 3 12 silere eM PP n 3 14 Synchronous Operation with DSACKe
22. 1 When FREEZE is asserted the bus monitor is disabled 0 When FREEZE is asserted the bus monitor continues to operate as programmed FIRQ Full Interrupt Request Mode 1 Configures port B for seven interrupt request lines autovector and no external chip selects 0 Configures port B for four interrupt request lines and four external chip selects See Table 4 5 for pin function selection SHEN 1 SHENO Show Cycle Enable These two control bits determine what the EBI does with the external bus during internal transfer operations see Table 4 6 A show cycle allows internal transfers to be externally monitored The address data and control signals except for AS are driven externally DS is used to signal address strobe timing for show cycles Data is valid on the next falling clock edge after DS is negated However data is not driven externally and AS and DS are not asserted externally for internal accesses unless show cycles are enabled If external bus arbitration is disabled the EBI will not recognize an external bus request until arbitration is enabled again To prevent bus conflicts external peripherals must not attempt to initiate cycles during show cycles with arbitration disabled Table 4 6 SHENx Control Bits sneno mw show jes enteral abiaton rated 77171 Stew ales enabed enteral arbiratn SUPV Supervisor User Data Space The SUPV bit defines t
23. 2 9 2 10 4 Clock Mode Select MODQOCK esses 2 9 2 11 Instrumentation and Emulation Signals esses 2 9 2 11 1 Instruction ripa 2 9 2 11 2 Instroetion Ripe PIP Ey cuneta d 2 9 2 11 3 Breakpbolht BKP un a Ea RE 2 10 2 11 4 Freeze FREEZE RR 2 10 2 12 DMAModu le Sigale 2 5 oreste tato ode 2 10 2 12 1 DMA Request DREQ2 raquette xri Dn et 2 10 2 12 2 DMA Acknowledge DACK2 DACK 1 sss 2 10 2 12 3 DMA Done DONEZ rec exnunc 2 10 2 13 Seral Module ode 2 11 2 13 1 Serial Crystal Oscillator X2 X1 sse 2 11 2 13 2 Serial External Clock Input SCLK sese 2 11 2 13 3 Receive Data RxDA BXDB soin ct o cea tee to rr 2 11 2 13 4 Transmit Data TxXDA seo decur eei E 2 11 2 13 5 Clear to Send CTSA 0202222 22 2 2 4 2 42440 44 448440 06 2 11 2 13 6 Request to Send RTSA 2 11 2 13 7 Transmitter Ready 2 2 2 11 2 13 8 Receiver Ready R amp RDYA sse 2 12 2 14 SIgials united etis 2 12 2 14 1 Ti
24. 3 10 MC68340 USER S MANUAL MOTOROLA CLKOUT A31 A0 FC3 FCO 5120 5171 DSACKO DSACK1 D15 D8 07 00 50 52 54 50 52 54 50 52 54 50 52 54 E EDI NES Ne pr 4 BYTES 3 BYTES 2 BYTES 1BYTE aR lt BYTE gt lt BYTE gt lt BYTE gt lt BYTE gt READ READ READ READ lt LONG WORD OPERAND READ FROM 8 BIT BUS gt Figure 3 3 Long Word Operand Read Timing from 8 Bit Port MOTOROLA MC68340 USER S MANUAL CLKOUT A31 A0 Jap te pns pe E des SS qe IK n K TK eo X KITI 5170 4 BYTES 3 BYTES 2 BYTES 1 5171 DSACKO N N DSACK1 015 08 07 00 1 1 0 3 lt WRITE gt lt WRITE lt WRITE WRITE lt LONG WORD OPERAND WRITE TO 8 BIT BUS gt Figure 3 4 Long Word Operand Write Timing to 8 Bit Port 3 2 3 7 LONG WORD OPERAND TO 16 BIT PORT ALIGNED Figure 3 5 shows both long word and word read and write timing to a 16 bit port LONG WORDOPERAND OPO 0 1 OP2 OP3 31 23 15 7 0 DATA BUS D15 D8 D7 DO 5121 5120 A0 DSACKi DSACKO CYCLE Opo OPI 0 0 0 0 X CYCLE 2 1 0 0 0 X 3 12 MC68340 USER S MANUAL MOTOROLA 50 52 S4 S0 S2 S4
25. 31 19 16 0 0111 1111111111111111 1111111 11 1 1 1 LEVEL 1 INTERRUPT ACKNOWLEDGE CPU SPACE TYPE FIELD Figure 3 10 CPU Space Address Encoding MOTOROLA MC68340 USER S MANUAL 3 21 3 4 1 Breakpoint Acknowledge Cycle The breakpoint acknowledge cycle allows external hardware to insert an instruction directly into the instruction pipeline as the program executes The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction BKPT or the assertion of the BKPT pin The T bit state shown in Figure 3 10 differentiates a software breakpoint cycle T 0 from a hardware breakpoint cycle T 1 When a BKPT instruction is executed software breakpoint the MC68340 performs a word read from CPU space type 0 at an address corresponding to the breakpoint number bits 2 0 of the BKPT opcode 4 2 and the T bit A1 is cleared If this bus cycle is terminated with BERR i e no instruction word is available the MC68340 then performs illegal instruction exception processing If the bus cycle is terminated by the MC68340 uses the data 015 00 for 16 bit ports or two reads from D15 D8 for 8 bit ports to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction When the CPU32 acknowledges pin assertion hardware breakpoint with background mode disabled
26. 4 10 MC68340 USER S MANUAL MOTOROLA To use an external clock source see Figure 4 6 the operating clock frequency can be driven directly into the EXTAL pin the XTAL pin must be left floating for this case This approach results in a system clock and CLKOUT that are the same as the input signal frequency but not tightly coupled to it To enable this mode MODCK must be held low during reset and VccsvN held at 0 V while the chip is in operation VCCSYN xrcl 0 1 uF EXTERNAL CLKOUT NOTES 1 Must be low leakage capacitor 2 External mode uses this path only Figure 4 6 Clock Block Diagram for External Oscillator Operation Alternatively an external clock signal can be directly driven into EXTAL with XTAL left floating using the on chip PLL This configuration results in an internal clock and CLKOUT signal of the same frequency as the input signal with a tight skew between the external clock and the internal clock and CLKOUT signals To enable this mode MODCK must be held low during reset and Vccsyn should be connected to a quiet 5 V source If an input signal loss for either of the clock modes utilizing the PLL occurs chip operation can continue in limp mode with the VCO running at approximately one half the operating speed affected by the value of the X bit in the SYNCR using an internal voltage reference The SLIMP bit in the SYNCR indicates that a loss of input signal reference has been de
27. RxRDYB Channel B Receiver Ready or FIFO Full The function of this bit is programmed by MR1B bit 6 1 If programmed as receiver ready a character has been received in channel B and is waiting in the receiver buffer FIFO If programmed as FIFO full a character has been transferred from the receiver shift register to the FIFO and the transfer has caused the channel B FIFO to become full all three positions are occupied 0 If programmed as receiver ready the CPU32 has read the receiver buffer After this read if more characters are still in the FIFO the bit is set again after the FIFO is popped If programmed as FIFO full the CPU32 has read the receiver buffer If a character is waiting in the receiver shift register because the FIFO is full the bit will be set again when the waiting character is loaded into the FIFO TxRDYB Channel B Transmitter Ready This bit is the duplication of the TxRDY bit in SRB 1 The transmitter holding register is empty and ready to be loaded with a character This bit is set when the character is transferred to the transmitter shift register This bit is also set when the transmitter is first enabled Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted 0 The transmitter holding register was loaded by the CPU32 or the transmitter is disabled XTAL RDY Serial Clock Running This bit is always read as a zero when the X1 clock is running
28. an CLKOUT Cycle Time ae 82 2 Clock Rise or Fall Time Clock Input X1 or SCLK Synchronizer Setup 15 Time Clock Input X1 or SCLK Synchronizer Hold Time X1 Cycle Time ta X1 High or Low Time tX1HL 0 55 0 75 tcS tCH SCLK High Low Time Asynchronous 16x tAHL tcyc tCS tCH Mode SCLK High Time Synchronous 1x Mode tcyc tcs tcH SCLK Low Time Synchronous 1x Mode greater of 1 tes Tx tvLD Tx O 5tcyc Rx bd tcH Rx TxD Data Valid from SCLK Low Synchronous tT xD 1 TX 1x Mode tcs TX tvLD TX 2 RxD Setup Time to SCLK High Synchronous iR 0 5 tes Rx tcH 1x Mode RxD Hold Time from SCLK High Synchronous 0 5 tcs tCH Rx 1x Mode 596 40 rs Ks el 5 ES EE 4 The electrical specifications in this document for both the 8 39 and 16 78 MHz 9 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part The 16 78 MHz specifications apply to the MC68340 9 5 0 V 5 operation The 25 16 MHz 5 0 V 5 electrical specifications are preliminary For extended temperature parts T A 40 to 85 C These specifications are preliminary 1 Asynchronous operation numbers take into account a receiver and transmitter operating at different clock frequencies Rx refe
29. s x wem VES nee o xem resas 5 m x me m fof e sem GA o cem 1 uw o o oem o _ x ce m aom oem uu m X There is one bus cycle for byte and word operands and two bus cycles for long word operands For long word bus cycles add two clocks to the tail and to the number of cycles NOTE The CHK instruction involves a save step which other instructions do not have To calculate the total instruction time calculate the save the EA and the operation execution times and combine in the order listed using the equations given in 5 7 1 6 Instruction Execution Time Calculation MOTOROLA MC68340 USER S MANUAL 5 111 5 7 3 13 EXCEPTION RELATED INSTRUCTIONS AND OPERATIONS The exception related instructions and operations table indicates the number of clock periods needed for the processor to perform the specified exception related actions No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes BKPT Acknowledged BKPT Bus Error Breakpoint Acknowledged 14 1
30. 0 to 70 see Figures 11 13 and 11 14 Characteristic CLKOUT Period in Crystal Mode Clock Rise and Fall Time TIN TGATE High or Low Time Minimum Pulse Width Asynchronous Input Setup Time to CLKOUT Low 5 Asynchronous Input Hold Time from CLKOUT Low Asynchronous Input Setup Time to CLKOUT High 7 Asynchronous Input Hold Time from CLKOUT High CLKOUT High to TOUT Valid NOTES The electrical specifications in this document for both the 8 39 and 16 78 MHz 9 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part The 16 78 MHz specifications apply to the MC68340 9 5 0 V 5 operation The 25 16 MHz 5 0 V 5 electrical specifications are preliminary For extended temperature parts T A 40 to 85 C These specifications are preliminary 1 Specification 4 for 16 78 MHz 3 3 V 0 3 V will be 8 ns E ES CLKOUT X TIN TGATE G Figure 11 13 Timer Module Clock Signal Timing Diagram 11 20 MC68340 USER S MANUAL MOTOROLA CLKOUT TIN TGATE 6 Figure 11 14 Timer Module Signal Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 21 11 10 SERIAL MODULE ELECTRICAL SPECIFICATIONS see notes b and d corresponding to part operation GND 0 Vdc TA 0 to 70 see numbered notes see Figures 11 15 11 18 5 0 V 7676 mHz 2516 mHz Characteristic
31. 50 51 52 53 54 55 DSACKO BR 6 D BG BGACK Figure 11 6 Bus Arbitation Timing Active Bus Case MOTOROLA MC68340 USER S MANUAL 11 15 Figure 11 7 Bus Arbitration Timing Idle Bus Case 50 541 542 543 50 51 52 CLKOUT lt gt o 1 0 gt H 18 AS DS mso Y L SHOW CYCLE gt lt 5 OF EXTERNAL CYCLE gt Figure 11 8 Show Cycle Timing Diagram 11 16 MC68340 USER S MANUAL MOTOROLA so 0 2CLOCKS 51 S2 53 54 55 5171 5170 8 DSACKO DSACK1 u e e Up to two wait states may be inserted by the processor between states SO and 51 Figure 11 9 IACK Cycle Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 17 FREEZE BKPT DSCLK lt IFETCH DSI X X IPIPE DSO Figure 11 10 Background Debug Mode Serial Port Timing CLKOUT PLE ee EE FREEZE __ t 5 IFETCH DSI gt 88 lt Figure 11 11 Background Debug Mode FREEZE Timing 11 18 MC68340 USER S MANUAL MOTOROLA 11 8 DMA MODULE AC ELECTRICAL SPECIFICATIONS see notes b c and d corresponding to part operation GND 0 Vdc TA 0 to 70 see Figure 11 12 33Vor50V 50V 16 78 MHz ojo 3 o o Characteri
32. 6 14 Dual Address Write External Burst Destination Requesting 6 16 Dual Address Write Cycle Steal Destination Requesting 6 17 Fast Termination Cycle Steal 6 21 Fast Termination External Burst Source Requesting 6 22 Transfer Type 3 5 Transfers Control of Bus 6 6 6 18 Transfers 32 Bits 6 2 6 7 6 35 Documentation 1 10 DONE Bit 6 15 6 20 6 27 6 31 6 37 6 38 6 30 Double Bus Fault 3 39 3 41 5 43 5 66 Monitor 3 40 4 1 4 4 4 6 4 23 4 37 DSACK Encoding 3 5 Signals 4 2 4 4 4 6 4 14 4 32 10 5 DSCLK Signal 5 69 5 71 DSI Signal 5 69 5 71 DSIZE Bits 6 15 6 29 6 37 DSO Signal 5 69 5 71 Dual Address Destination Write 6 15 Mode 6 12 6 28 6 37 Source Read 6 12 Transfer 6 3 Dump Memory Block Command 5 80 5 81 Dynamic Bus Sizing 3 5 3 14 MOTOROLA MC68340 USER S MANUAL Early Bus Error 3 34 EBI 4 2 4 22 4 33 ECO Bit 6 7 6 27 6 28 6 37 Effects of Wait States on Instruction Timing 5 92 Electrical Characteristics 11 1 AC Electrical Specifications Definitions 11 2 11 4 Control Timing 11 6 11 7 Timing Specifications 11 8 11 10 Timing Diagram 11 11 11 18 DMA Module Specifications 11 19 DMA Timing Diagram 11 19 Timer Module Specifications 11 20 Timer Module Timing Diagrams 11 20 1 1 21 Serial Module Specifications 11 22 Serial Module Timing Diagrams 11 22 11 23 IEEE 1149 1 Specifications 11 24 IEEE 1149 1 Timing Diagrams 11 24 1 1 25 Typical Ch
33. DRIVE FUNCTION CODE ON FC3 FCO DRIVE SIZE PINS FOR OPERAND SIZE ASSERT A5 ACCEPT DATA PLACE DATA ON 015 00 ASSERT DS Cn gt CO PO r3 1 DECODE ADDRESS 2 LATCH DATA FROM 015 00 TERMINATE OUTPUT TRANSFER See DER TOR ARK SIGNALS 1 NEGATE DS AND AS 2 REMOVE DATA FROM D15 D0 TERMINATE CYCLE 1 NEGATE DSACKx START NEXT CYCLE Figure 3 8 Word Write Cycle Flowchart State 0 The write cycle starts in SO During SO the MC68340 places a valid address on 1 0 and valid function codes on FC3 FCO The function codes select the address space for the cycle The MC68340 drives R W low for a write cycle SIZ1 SIZO become valid indicating the number of bytes to be transferred State 1 One half clock later during S1 the MC68340 asserts AS indicating a valid address on the address bus State 2 During S2 the MC68340 places the data to be written onto 015 00 and samples DSACK at the end of S2 State 3 The MC68340 asserts DS during S3 indicating that data is stable on the data bus As long as at least one of the DSACK signals is recognized by the end of S2 meeting the asynchronous input setup time requirement the cycle terminates one clock later If DSACK is not recognized by the start of S3 the MC68340 inserts wait states instead of proceeding to S4 and S5 To ensure that wait states are inserted both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold time
34. Disable interrupt Bit 3 Reserved DBA Delta Break A 1 Enable interrupt 0 Disable interrupt RxRDYA Channel A Receiver Ready or FIFO full 1 Enable interrupt 0 Disable interrupt TxRDYA Channel A Transmitter Ready 1 Enable interrupt 0 Disable interrupt 7 4 1 14 INPUT PORT IP IP register shows the current state of the CTS inputs This register can only be read when the serial module is enabled i e the STP bit in the MCR is cleared IP 71D 7 6 5 4 3 2 1 0 jojo jo ce jc n 0 0 0 0 0 U U Read Only Supervisor User CTSB CTSA Current State 1 The current state of the respective CTS input is negated 0 The current state of the respective CTS input is asserted The information contained in these bits is latched and reflects the state of the input pins at the time that the IP is read NOTE These bits have the same function and value of the IPCR bits 1 and 0 MOTOROLA MC68340 USER S MANUAL 7 35 7 4 1 15 OUTPUT PORT CONTROL REGISTER OPCR The OPCR individually configures four bits of the 8 bit parallel OP for general purpose use or as an auxiliary function serving the communication channels This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared OPCR 71D 6 5 4 3 2 1 0 OP7 OP6 OP5 2 T RDYB T RDYA R RDYB R RDYA RTSB RTSA RESET 0 0 0 0 0 0 0 0 Write Only Supervisor U
35. LIST OF ILLUSTRATIONS Continued Figure Number Title 9 3 Output Latch Cell O Latch rire Entente 9 4 C OP occ nA 9 5 Active High Output Control Cell 9 6 Active Low Output Control Cell IO CtlO esses 9 7 Bidirectional Data Cell IO Cell eene 9 8 General Arrangement for Bidirectional 9 9 Bypass 10 Minimum System Configuration Block 10 2 Sample Crystal calor en est ta tete 10 3 Statek Corporation Crystal Circuit eese 10 4 and Vccsvw Capacitor Connections esses 10 5 gt cen tem dept testen a 10 6 IBIGITAOD uut intus eet e fett tire iae Ron tuat tct 10 7 Serial eigen E 10 8 External Circuitry for 8 Bit Boot ROM essere 10 9 8 Boot ROM TIMDO iiid det tt edi e iate e renidet 10 10 Access Time Computation Diagram seen 10 11 Signal Relationships to 10 12 Signal Width Specifications ee eececeecee
36. Table 7 1 FRZx Control Bits o Lo 1 Reserves FREEZE nored EREA Freeze on Character Boundary Freeze on Character Boundary If FREEZE is asserted channel A and channel B freeze independently of each other The transmitter and receiver freeze at character boundaries The transmitter does not freeze in the send break mode Communications can be lost if the channel is not programmed to support flow control See Section 5 CPU32 for more information on FREEZE ICCS Input Capture Clock Select 1 Selects SCLK as the clear to send input capture clock for both channels Clear to send operation is enabled by setting bit 4 in MR2 The data is captured on the CTS pins on the rising edge of the clock 0 The crystal clock is the clear to send input capture clock for both channels 7 20 MC68340 USER S MANUAL MOTOROLA Bits 11 8 6 4 Reserved SUPV Supervisor User The value of this bit has no affect on registers permanently defined as supervisor only 1 The serial module registers which are defined as supervisor or user reside in supervisor data space and are only accessible from supervisor programs 0 The serial module registers which are defined as supervisor or user reside in user data space and are accessible from either supervisor or user programs IARB3 IARBO Interrupt Arbitration Bits Each module that generates interrupts has an IARB field These
37. counter reaches 0000 toggle TOUTx In the input capture output compare mode TOUTx is immediately set to zero if the timer is disabled SWR 0 If the timer is enabled SWR 1 timer compare events toggle TOUTx Timer compare events occur when the counter reaches the value stored in the COM Zero Mode lf the timer is disabled SWR 0 when this encoding is programmed TOUTx is immediately set to zero If the timer is enabled SWR 1 will be set to zero at the next timeout In the input capture output compare mode TOUTx is immediately set to zero if the timer is disabled SWR 0 If the timer is enabled SWR 1 TOUTx will be set to zero at timeouts and set to one at timer compare events If the COM is 0000 TOUTx will be set to zero at the timeout timer compare event One Mode f the timer is disabled SWR 0 when this encoding is programmed TOUTx is immediately set to one If the timer is enabled SWR 1 TOUTx will be set to one at the next timeout In the input capture output compare mode TOUTx is immediately set to one if the timer is disabled SWR 0 If the timer is enabled SWR 1 TOUTx will be set to one at timeouts and set to zero at timer compare events If the COM is 0000 TOUTx will be set to one at the timeout timer compare event 8 4 4 Status Register SR The SR contains timer status information as well as the state of the prescaler This register is updated on the rising edge of the syst
38. is low the address is even and is a word and byte boundary When 0 is high the address is odd and is byte boundary only A byte operand is properly aligned at any address a word or long word operand is misaligned at an odd address At most each bus cycle can transfer a word of data aligned on a word boundary If the MC68340 transfers a long word operand over a 16 bit port the most significant operand word is transferred on the first bus cycle and the least significant operand word is transferred on a following bus cycle The CPU32 restricts all operands both data and instructions to be aligned That is word and long word operands must be located on a word or long word boundary respectively The only type of transfer that can be performed to an odd address is a single byte transfer referred to as an odd byte transfer If a misaligned access is attempted the CPU32 generates an address error exception and enters exception processing Refer to Section 5 CPU32 for more information on exception processing 3 2 3 Operand Transfer Cases The following cases are examples of the allowable alignments of operands to ports 3 2 3 1 BYTE OPERAND TO 8 BIT PORT ODD OR EVEN A0 X The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single byte operand MOTOROLA MC68340 USER S MANUAL 37 BYTEOPERAND OPO 7 0 DATA BUS D15 D8 D7 DO 5121 5120 A0 DSACKi DSACKO 1 0 0 OPO
39. ore e Dot etas Lets 9 3 ete ue UE 9 9 EXTEST 000 2 2 9 10 SAMPLE PRELOAD OD iret ixaso ieu eel ip 9 10 BYPASS XIX tenian Doct Recs 9 11 COG 9 11 MC68340 see ego 9 11 Non IEEE 1149 1 ODOrallOllc see 9 12 Section 10 Applications Minimum System Configuration esee 10 1 Processor Clock 10 1 MC68340 USER S MANUAL XV 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Concluded Paragraph Page Number Title Number 10 1 2 Reset Gigi mp 10 3 10 1 3 SRAM TMG ACG eite ote uA 10 3 10 1 4 ROM Interface ese i adieu tu es 10 4 10 1 5 SerialAnterta Do ette cQ a a 10 4 10 2 Memory Interface Information esses 10 5 10 2 1 Using an 8 Bit Boot tete 10 5 10 2 2 Access Time Calculations essent 10 6 10 2 3 Calculating Frequency Adjusted 10 7 10 2 4 Interfacing an 8 Bit Device to 16 Bit Memory Using Single Address DMA Mode
40. 0 0 0 0 0 0 0 Supervisor User 6 30 MC68340 USER S MANUAL MOTOROLA IRQ Interrupt Request This bit is the logical OR of the DONE BES BED CONF and BRKP bits and is cleared when they are all cleared IRQ is positioned to allow conditional testing as a signed binary integer The state of this bit is not affected by the interrupt enable bits in the CCR The STR bit in the CCR cannot be set when this bit is set all error status bits except the BRKP bit must be cleared before the STR bit can be set 1 An interrupt condition has occurred 0 An interrupt condition has not occurred DONE DMA Done 1 The DMA channel has terminated normally 0 The DMA channel has not terminated normally This bit is cleared by writing a logic one or by a hardware reset Writing a zero has no effect BES Bus Error on Source 1 The DMA channel has terminated with a bus error during the read bus cycle 0 The DMA channel has not terminated with a bus error during the read bus cycle This bit is cleared by writing a logic one or by a hardware reset Writing a zero has no effect BED Bus Error on Destination 1 The DMA channel has terminated with a bus error during the write bus cycle 0 The DMA channel has not terminated with a bus error during the write bus cycle This bit is cleared by writing a logic one or by a hardware reset Writing a zero has no effect CONF Configuration Error A configuration error results when either
41. 0 1 X 1 0 For a read operation the slave responds by placing data on bits 15 8 of the data bus asserting DSACKO and negating DSACKH1 to indicate an 8 bit port The MC68340 then reads the operand byte from bits 15 8 and ignores bits 7 0 For a write operation the MC68340 drives the single byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read The slave device reads the byte operand from bits 15 8 and places the operand in the specified location The slave then asserts DSACKO to terminate the bus cycle 3 2 3 2 BYTE OPERAND TO 16 BIT PORT EVEN A0 0 The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single byte operand BYTEOPERAND 7 0 DATA BUS D15 08 07 00 671 5120 A0 DSACKi DSACKO CYCLE 1 0 0 OPO 0 1 0 0 X For a read operation the slave responds by placing data on bits 15 8 of the data bus and asserting DSACK1 to indicate a 16 bit port The MC68340 then reads the operand byte from bits 15 8 and ignores bits 7 0 For a write operation the MC68340 drives the single byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read The slave device reads the operand from bits 15 8 of the data bus and uses the address to place the operand the specified location The slave then asserts DSACK1 to terminate the bus cycle 3 8 MC68340 USER S MA
42. 12 2 PIN ASSIGN CIA tie tia diste ect dll oeste etate 12 2 12 2 1 144 Lead Ceramic Quad Flat Pack FE Suffix 12 2 12 2 2 145 Lead Plastic Pin Grid Array RP Suffix 12 4 12 3 Package Ditlebslols sunu cote toh ee ne 12 6 12 3 1 FE SUX oir a ues ca eit 12 6 12 3 2 RR SUID aun 12 7 Index xvi MC68340 USER S MANUAL MOTOROLA 11 2 95 SECTION 1 OVERVIEW UM Rev 1 LIST OF ILLUSTRATIONS Figure Page Number Title Number 1 1 Block Diagram ou ies abeft se 1 1 2 1 Functional Signal GIOBDS oe sto 2 1 3 1 Input Sample VIFIOOW 2 ro e ido ges Eee 3 2 3 2 MC68340 Interface to Various Port Sizes sss 3 7 3 3 Long Word Operand Read Timing from 8 Bit 3 11 3 4 Long Word Operand Write Timing to 8 Bit 3 12 3 5 Long Word and Word Read and Write Timing 16 Bit Port 3 13 3 6 Fast Termination sooo teri eoe edu ceti dua doeet dc ade 3 15 3 7 Word Read Cycle Flowchart ca cute eite dtt eaten 3 16 3 8 Word Write Cycle deer te neve ce cheer 3 18 3 9 Read Modify Write Cycle Timing c ccccccceceeseeeeseesceeeeeeeceeeaeees
43. 584 MC68340 USER S MANUAL MOTOROLA Command Sequence CALL MS ADDR LS ADDR 247 NOT READY READY NEXT CMD ILLEGAL READY STACK RETURN PC FREEZE NEGATED PREFETCH STARTED NORMAL MODE XXX BERR AERR NEXT CMD NOT READY Operand Data The 32 bit operand data is the starting location of the patch routine which is the initial PC upon exiting BDM Result Data None As an example consider the following code segment It outputs a character from the MC68340 serial module channel A CHKSTAT MOVE B SRA DO Move serial status to DO BNE B CHKSTAT Loop until condition true MOVE B TBA OUTPUT Transmit character MISSING ANDI B 3 D0 Check for flag RTS BDM and the CALL command can be used to patch the code as follows Breakpoint user program at CHKSTAT Enter BDM Execute CALL command to MISSING Exit BDM Execute MISSING code Return to user program QUU ee ae 5 6 2 8 14 Reset Peripherals RST RST asserts RESET for 512 clock cycles The CPU is not reset by this command This command is synonymous with the CPU RESET instruction MOTOROLA MC68340 USER S MANUAL 5 85 Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ojo o o oji fo jo jojofjo ofjo jo jo o Command Sequence Gori READY uD OVRE EY CMD COMPLETE NEXT CE CID READY RESET ASSERT 22 RESET XXX ILLEGAL Operand Data
44. 590 CLOCK gt 512 CLOCK ___ gt ec BY MC68340 Figure 3 27 Timing for External Devices Driving RESET RESET If reset is asserted from any other source the reset control logic asserts RESET for 328 input clock periods plus 512 output clock periods and until the source of reset is negated After any internal reset occurs a 14 cycle rise time is allowed before testing for the presence of an external reset If no external reset is detected the CPU32 begins its vector fetch Figure 3 28 is a timing diagram of the power up reset operation showing the relationships between RESET VCC and bus signals During the reset period the entire bus three states except for non three statable signals which are driven to their inactive state Once RESET negates all control signals are driven to their inactive state the data bus is in read mode and the address bus is driven After this the first bus cycle for RESET exception processing begins MOTOROLA MC68340 USER S MANUAL 3 47 CLKOUT vo ff o po 0C oO oc sd red LOCK Vcc 328 x TCLKIN 512 x __ lt 14 CLOCKS gt TCLKOUT E lt lt RESET 27777777 BUS CYCLES NOTES 1 Internal start up time BUS STATE UNKNOWN 2 SSP read here 3 PC read here 4 First instruction fetched here ADDRESS AND CONTROL SIGNALS THREE STATED Figure 3 28 Power Up Reset Timing Diagram When a RESET instru
45. 7 12 7 7 Looping Modes Functional 7 15 7 8 Multidrop Mode Timing Diagram eese 7 16 7 9 Serial Module Programming Model 7 19 7 10 Serial Module Programming 7 41 8 1 Simplified utorrent ctt cent teni ec 8 1 8 2 Timer Functional exco qo edges 8 3 8 3 External and Internal Interface Signals sss 8 5 8 4 Input Capture Output Compare 2 8 7 8 5 Square Wave Generator 8 8 8 6 Variable Duty Cycle Square Wave Generator Mode 8 10 8 7 Variable Width Single Shot Pulse Generator 8 11 8 8 Pulse Width Measurement Mode tete 8 12 8 9 Period Measurement Mode esses trennen 8 14 8 10 Event Gourt MOOG REDE uas oe RES es 8 15 8 11 Timer Module Programming Model seeeeeeeeeees 8 18 9 1 Test Access Port Block Diagram sse 9 2 9 2 Controller State Machine eese 9 3 MOTOROLA MC68340 USER S MANUAL 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0
46. 8 24 8 25 Input Signal 2 12 8 2 8 5 8 17 Interrupt Operation 8 4 8 17 8 19 8 21 8 23 8 24 8 27 Output Signal 2 12 8 2 8 5 8 17 Prescaler 8 2 8 3 8 21 Programming Model 8 28 Uses 8 2 Using to Compare Values 8 6 8 8 TMS Signal 2 13 9 2 TO Bit 8 8 8 9 8 23 8 24 8 27 Toggle Mode 8 23 TP Bit 5 61 TR Bit 5 56 5 58 5 61 Trace Exception 5 57 Modes 5 10 on Instruction Execution 5 63 Tracing 5 56 5 58 Control Bits Encoding 5 53 Transfer Cases 3 5 Mechanism 3 5 3 16 3 18 Transition to Background Mode 5 65 5 68 Transmit Data Signal 2 11 Shift Register 7 9 7 11 Transmitter 7 10 7 11 Baud Rates 7 27 Buffer 7 9 7 10 7 25 7 30 7 31 Disable Command 7 29 Enable Command 7 29 Holding Register 7 9 7 10 7 25 7 33 Ready Signal 2 11 Timing 7 10 TRAP Instruction 5 46 Two Clock Bus Cycles 10 3 TxCTS Bit 7 39 7 47 TxDx Signal 7 8 7 6 7 10 7 14 7 29 TxEMP Bit 7 10 7 25 7 28 TxRDY Bit 7 10 7 25 7 28 7 31 TxRDYA Bit 7 34 7 35 TxRDYA Signal 7 7 7 36 TxRDYB Bit 7 33 7 35 Index 8 MC68340 USER S MANUAL TxRTS Bit 7 38 7 47 Types of DMA Interrupts 6 20 ex Unimplemented Instructions 5 12 Emulation 5 74 Exception 5 48 5 50 UNLK Instruction 5 36 Use of Chip Selects 4 15 10 3 10 4 User Privilege Level 5 7 5 37 5 38 5 48 Using 8 Bit Boot ROM 10 5 TGATE as an Input Port 8 16 Table Lookup and Interpolate Instructions 5 7 5 12 5 20 5 35 TOU
47. Figure 9 5 Active High Output Control Cell IO Ctl1 1 EXTEST TO NEXT 0 OTHERWISE CELL FIG 9 4 OUTPUT CONTROL FROM TO OUTPUT SYSTEM gt gt ENABLE LOGIC 1 DRIVE SHIFT DR FROM CLOCK DR RESET LAST CELL UPDATE DR Figure 9 6 Active Low Output Control Cell IO CtlO 9 8 MC68340 USER S MANUAL MOTOROLA 1 EXTEST TO NEXT 0 OTHERWISE SHIFT DR CELL OUTPUT FROM TO OUTPUT SYSTEM gt DRIVER LOGIC FROM OUTPUT FROM PIN FROM LAST CLOCK DR UPDATE DR ENABLE CELL Figure 9 7 Bidirectional Data Cell IO Cell TO NEXT CELL OUTPUT ENABLE gt OR I0 CTLI A gt DATA IO CELL INPUT lt DATA FROM LAST CELL TO NEXT BIDIRECTIONAL PIN NOTE More than one IO Cell could be serially connected and controlled by a single IO Ctlx cell Figure 9 8 General Arrangement for Bidirectional Pins 9 4 INSTRUCTION REGISTER The MC68340 IEEE 1149 1 implementation includes the three mandatory public instructions EXTEST SAMPLE PRELOAD and BYPASS but does not support any of the optional public instructions defined by IEEE 1149 1 One additional public instruction HI Z provides the capability for disabling all device output drivers The MC68340 MOTOROLA MC68340 USER S MANUAL 9 9 includes a 3 bit instruction register without parity consisting of a shift register with three parallel outputs Data is transferred from
48. IEC bits Output Port Control Register OPCR Select the function of the output port pins Interrupt Status Register ISR e The XTAL RDY bit should be polled until it is cleared to ensure that an unstable crystal input is not applied to the baud rate generator 7 46 MC68340 USER S MANUAL MOTOROLA The following steps are channel specific Clock Select Register CSR Select the receiver and transmitter clock Mode Register 1 MR1 e If desired program operation of receiver ready to send RxRTS bit Select receiver ready or FIFO full notification R F bit Select character or block error mode ERR bit Select parity mode and type PM and PT bits e Select number of bits per character B Cx bits Mode Register 2 MR2 e Select the mode of channel operation CMx bits If desired program operation of transmitter ready to send TxRTS bit If desired program operation of clear to send TxCTS bit Select stop bit length SBx bits Command Register CR Enable the receiver and transmitter 7 5 2 Serial Module Example Configuration Code The following code is an example of a configuration sequence for the serial module kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MC68340 basic serial module register initialization example code This code is used to initialize the 68340 s internal serial module registers providing basic functions for operation It sets up seria
49. None Result Data The command complete response 0FFFF is loaded into the serial shifter after negation of RESET 5 6 2 8 15 No Operation NOP NOP performs no operation and may be used as a null command where required Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dq os ee spe p esp xor nee pog s Command Sequence NOP N NEXT CMD CMD COMPLETE ILLEGAL NOT READY Operand Data None Result Data The command complete response 0FFFF is returned during the next shift operation 5 86 MC68340 USER S MANUAL MOTOROLA 5 6 2 8 16 Future Commands Unassigned command opcodes are reserved by Motorola for future expansion All unused formats within any revision level will perform a NOP and return the ILLEGAL command response 5 6 3 Deterministic Opcode Tracking The CPU32 utilizes deterministic opcode tracking to trace program execution Two signals IPIPE and IFETCH provide all information required to analyze instruction pipeline operation 5 6 3 1 INSTRUCTION FETCH IFETCH IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline IFETCH is pulse width modulated to multiplex two indications on a single pin Asserted for a single clock cycle IFETCH indicates that the data from the current bus cycle is to be routed to the instruction pipeline IFETCH held low for two clock cycles indicates that the instruction pipeline has been flushe
50. SO 52 S4 SO 2 S4 SO S2 S4 SO S2 54 CLKOUT A31 A0 FC3 FCO EU X TXI T KU TKTT X ULT EC CREE Subs uu NL db Ne NL EM NL NELLE NET T NEM 5170 4 5 2 5 2 5 4 BYTES 2 BYTES 2 BYTES 5121 NELLY pucr Xe ode we Be ere re she eile sil eh a od qoc PN NE Ni ede DSACK1 015 08 0 0 0 2 09 09 0 2 07 00 3 1 WORD i LONG WORD READ WORD READ 4 amp LONG WORD WRITE 3 WRITE gt FROM 16 BIT BUS FROM 16 817 BUS 16 BIT BUS 16 BIT BUS Figure 3 5 Long Word and Word Read and Write Timing 16 Bit Port The MC68340 drives the address bus with the desired address and drives the SIZx pins to indicate a long word operand For a read operation the slave responds by placing the two most significant bytes of the operand on bits 15 0 of the data bus and asserting DSACK1 to indicate a 16 bit port The MC68340 reads the two most significant bytes of the operand bytes 0 and 1 from bits 15 0 The MC68340 then decrements the transfer size counter by 2 increments the address by 2 initiates a new cycle and reads bytes 2 and 3 of the operand from bits 15 0 of the data b
51. The M68000PM AD M68000 Family Programmer s Reference Manual contains detailed register information Except where noted the following notation is used in this section Data Immediate data from an instruction Destination Destination contents Source Source contents Vector Location of exception vector An Any address register A7 A0 Ax Ay Address registers used in computation Dn Any data register 07 00 Rc Control register VBR SFC DFC Rn Any address or data register Dh DI Data registers high and low order 32 bits of product Dr Dq Data registers division remainder division quotient Dx Dy Data registers used in computation Dym Dyn Data registers table interpolation values Xn Index register An Address extension Condition code di Displacement Example d16 is a 16 bit displacement ea Effective address data Immediate data a literal integer label Assembly program label list List of registers f MOTOROLA Example 03 00 Bits of an operand Examples 7 is bit 7 31 24 are bits 31 24 MC68340 USER S MANUAL 5 13 CCR PC SP SR SSP USP FC DFC SFC x lt gt iI BCD LSW MSW R W Contents of a referenced location Example Rn refers to the contents of Rn Condition code register lower byte of SR X extend bit N negative bit Z zero bit V overflow bit C carry bit Program counter Active stack pointer Status register Supervisor stack pointer
52. The frame shown in Figure 5 17 is written below the faulting frame Stacking begins at the address pointed to by SP 6 SP value is the value before initial stacking on the faulted frame The frame can have either four or six words depending on the type of error Four word stack frames do not include the faulted instruction PC the internal transfer count register is located at SP 10 and the SSW is located at SP 12 The fault address of a dynamically sized bus cycle is the address of the upper byte regardless of the byte that caused the error MOTOROLA MC68340 USER S MANUAL 5 61 SP gt STATUS REGISTER 02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 06 1 1 0 0 VECTOR OFFSET 08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW 0C DBUF HIGH DBUF LOW 10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW 14 INTERNAL TRANSFER COUNT REGISTER 16 0 0 SPECIAL STATUS WORD Figure 5 15 Format C BERR Stack for Prefetches and Operands 15 0 SP gt STATUS REGISTER 02 RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 06 1 1 0 0 VECTOR OFFSET 08 FAULTED ADDRESS HIGH FAULTED ADDRESS LOW 0C DBUF HIGH DBUF LOW 10 CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW 14 INTERNAL TRANSFER COUNT REGISTER 16 0 1 SPECIAL STATUS WORD
53. User stack pointer Function code Destination function code register Source function code register Arithmetic addition or postincrement Arithmetic subtraction or predecrement Arithmetic division or conjunction symbol Arithmetic multiplication Equal to Not equal to Greater than Greater than or equal to Less than Less than or equal to Logical AND Logical OR Logical exclusive OR Invert operand is logically complemented Binary coded decimal indicated by subscript Example Source10 is a BCD source operand Least significant word Most significant word Read write indicator In a description of an operation a destination operand is placed to the right of source operands and is indicated by an arrow 5 14 MC68340 USER S MANUAL MOTOROLA 5 3 3 Instruction Summary The instructions form a set of tools to perform the following operations Data movement Bit manipulation Integer arithmetic Binary coded decimal arithmetic Logic Program control Shift and rotate System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development All CPU32 instructions are summarized in Table 5 2 MOTOROLA MC68340 USER S MANUAL 5 15 Table 5 2 Instruction Set Summary Syntax ABCD Source 40 Destination40 X Destination ABCD Dy Dx ABCD Ay Ax Source Destination Destination ADD ea Dn ADD Dn ea ADDA Source Destination Desti
54. branches New instructions such as table lookup and interpolate and low power stop support the specific requirements of embedded control applications Many addressing modes complement these instructions including predecrement and postincrement which allow simple stack and queue maintenance and scaled indexed for efficient table accesses Data types and addressing modes are supported orthogonally by all data operations and with all appropriate addressing modes Position independent code is easily written CPU32 is specially optimized to run with the MC68340 s 16 bit data bus Most instructions execute in one half the number of clocks compared to the original MC68000 yielding an overall 1 6 times the performance of the same speed MC68000 and measuring 10 045 Dhrystones sec 25 16 MHz 6 742 Dhrystones sec 16 78 MHz Like all M68000 family processors the CPU32 recognizes interrupts of seven different priority levels and allows the peripheral to vector the processor to the desired service routine Internal trap exceptions ensure proper instruction execution with good addresses and data allow operating system intervention in special situations and permit instruction tracing Hardware signals can either terminate or rerun bad memory accesses before instructions process data incorrectly The CPU32 offers the programmer full 32 bit data processing performance with complete M68000 compatibility yet with more compact code than is available
55. it must be at least two clock periods long The DMA channel responds to cycle steal requests the same as all other requests However if subsequent DREQs pulses are generated before DACK is asserted in response to each request they are ignored If DREQx is asserted after the DMA channel asserts DACK for the previous request but before DACK is negated then the new request is serviced before bus ownership is released If a new request is not generated by the time DACK is negated the bus is released 6 3 2 3 EXTERNAL REQUEST WITH OTHER MODULES The DMA controller can be externally connected to the serial module and used in conjunction with the serial module to send or receive data The DMA takes the place of a separate service routine for accessing or storing data that is sent or received by the serial module Using the DMA also lowers the CPU32 overhead required to handle the data transferred by the serial module Figure 6 4 shows the external connections required for using the DMA with the serial module DMA MODULE SERIAL MODULE TxRDYA Figure 6 4 External Connections to Serial Module For serial receive the DMA reads data from the serial receive buffer RB register when the serial module has filled the buffer on input and writes data to memory For serial transmit the DMA reads data from memory and writes data to the serial transmit buffer TB register Only dual address mode can be used with the seri
56. n T 3 MEC Overflow Clear 1000 Overflow Set 1001 Not uu for the Bcc instruction Boolean AND Boolean OR Boolean NOT N 5 3 4 Using the TBL Instructions There are four TBL instructions TBLS returns a signed rounded byte word or long word result TBLSN returns a signed unrounded byte word or long word result TBLU returns an unsigned rounded byte word or long word result TBLUN returns an unsigned unrounded byte word or long word result All four instructions support two types of interpolation data an n element table stored in memory and a two element range stored in a pair of data registers The latter form provides a means of performing surface 3D interpolation between two previously calculated linear interpolations The following examples show how to compress tables and use fewer interpolation levels between table entries Example 1 see Figure 5 7 demonstrates TBL for a 257 entry table allowing up to 256 interpolation levels between entries Example 2 see Figure 5 8 reduces table length for the same data to four entries Example 3 see Figure 5 9 demonstrates use of an 8 bit independent variable with an instruction MOTOROLA MC68340 USER S MANUAL 5 29 Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation Example 4 demonstrates addition of the results of three table interpolations Example 5 illustrates use
57. paragraphs describe the types of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing 3 4 4 1 INTERRUPT ACKNOWLEDGE CYCLE TERMINATED NORMALLY When the CPU32 processes an interrupt exception it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use The following paragraphs describe the interrupt acknowledge cycle for these devices Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3 4 4 2 Autovector Interrupt Acknowledge Cycle MOTOROLA MC68340 USER S MANUAL 3 27 The interrupt acknowledge cycle is a read cycle It differs from the read cycle described in 3 3 1 Read Cycle in that it accesses the CPU address space Specifically the differences are as follows 1 FC3 FOO are set to 7 FC3 FC2 FC1 FCO 0111 for CPU address space 2 2 and A1 are set to the interrupt request level and the IACK strobe corresponding to the current interrupt level is asserted Either the function codes and address signals or the IACK strobes can be monitored to determine that interrupt acknowledge cycle is in progress and the current interrupt level 3 The CPU32 space type field 19 16 is set to F interrupt acknow
58. retransmit the command NOTE The not ready response can be ignored unless a memory bus cycle is in progress Otherwise the CPU can accept a new serial transfer with eight system clock periods In the third cycle the development system supplies the low order 16 bits of a memory address The CPU always returns the not ready response in this cycle At the completion of the third cycle the CPU initiates a memory read operation Any serial transfers that begin while the memory access is in progress return the not ready response Results are returned in the two serial transfer cycles following the completion of memory access The data transmitted to the CPU during the final transfer is the opcode for the following command Should a memory access generate either a bus or address error an error status is returned in place of the result data 5 74 MC68340 USER S MANUAL MOTOROLA m COMMANDS TRANSMITTED TO THE CPU32 m COMMAND CODE TRANSMITTED DURING THIS CYCLE READ LONG MS ADDR NOT READY XXX ILLEGAL LS ADDR NOT READY NEXT CMD READY DATA UNUSED FROM THIS TRANSFER SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY CPU32 RESULTS FROM PREVIOUS COMMAND RESPONSES FROM THE CPU MEMORY LOCATION HIGH ORDER 16 BITS OF MEMORY ADDRESS r LOW ORDER 16 BITS OF MEMORY ADDRESS NONSERIAL RELATED ACTIVITY SEQUENCE TAKEN IF OPERATION HAS N
59. the ACR can be programmed to generate an interrupt to the CPUS2 0 The CPU32 has read the IPCR No change of state has occurred A read of the IPCR also clears the ISR COS bit CTSB CTSA Ourrent State Starting two serial clock periods after reset the CTS bits reflect the state of the CTS pins If a CTS pin is detected as asserted at that time the associated COSx bit will be set which will initiate an interrupt if the corresponding IECx bit of the ACR register is enabled 1 The current state of the respective CTS input is negated 0 The current state of the respective CTS input is asserted MOTOROLA MC68340 USER S MANUAL 7 31 7 4 1 11 AUXILIARY CONTROL REGISTER The ACR selects which baud rate is used and controls the handshake of the transmitter receiver This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared ACR 714 7 6 5 4 3 2 1 0 o o o o o 0 0 0 0 0 0 0 Write Only Supervisor User BRG Baud Rate Generator Set Select 1 Set 2 of the available baud rates is selected 0 Set 1 of the available baud rates is selected Refer to 7 4 1 6 Clock Select Register CSR for more information on the baud rates IECB IECA Input Enable Control 1 ISR bit 7 will be set and an interrupt will be generated when the corresponding bit in the IPCR COSB or COSA is set by an external transition on the channel s 5 input if bit
60. this case clearing the INTN or the DONE bit causes the IRQ bit to be cleared If the interrupt breakpoint CCR INTB and the CSR BRKP bits are set the IRQ bit is set Clearing INTB or BRKP clears IRQ 6 6 3 3 FAST TERMINATION OPTION Using the system integration module SIM40 chip select logic the fast termination option Figure 6 13 can be employed to give a fast bus access of two clock cycles rather than the standard three cycle access time for external requests The fast termination option is described in Section 3 Bus Operation and Section 4 System Integration Module 6 20 MC68340 USER S MANUAL MOTOROLA CPU CYCLE DMA READ CPU CYCLE DMA READ 50 52 54 50 54 50 52 54 50 52 DONEx o 45 UM 122477 OUTPUT NOTE 1 To cause another DMA transfer DREQx is asserted after DACKx is asserted and before DACKx is negated 2 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle Figure 6 13 Fast Termination Option Cycle Steal If the fast termination option is used with external burst request mode Figure 6 14 an extra DMA cycle may result on every burst transfer Normally DREQ is negated when DACK is returned In the burst mode with fast termination selected a new cycle starts even if DREQ is negated simultaneously with DACK assertion MOTOROLA MC68340 USER S MANUAL CPU CYCLE DMAREAD DMA WRITE CPU CYCLE DMAREAD DMA WRITE S0 S2 S4 S0 54 S0 S4 S0 52 54 50 94 S0 54 50 CLK
61. to allow tracing of instruction execution CPU32 tracing also has the ability to trap on changes in program flow In trace mode a trace exception is generated after each instruction executes allowing a debugging program to monitor the execution of a program under test The T1 and TO bits in the supervisor portion of the SR are used to control tracing When T1 TO 00 tracing is disabled and instruction execution proceeds normally see Table 5 18 Table 5 18 Tracing Control 0 roras 00 _0 1 Trace onchange oftiow ion executi Trace on instruction execution Undefined reserved When T1 TO 01 at the beginning of instruction execution a trace exception will be generated if the PC changes sequence during execution All branches jumps subroutine calls returns and SR manipulations can be traced in this way No exception occurs if a branch is not taken When T1 TO 10 at the beginning of instruction execution a trace exception will be generated when execution is complete If the instruction is not executed either because an interrupt is taken or because the instruction is illegal unimplemented or privileged an exception is not generated At the present time T1 TO 11 is an undefined condition It is reserved by Motorola for future use Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction Exception process
62. 0 0 1 0 0 0 0 0 0 0 Read Write Supervisor Only MOTOROLA MC68340 USER S MANUAL 7 19 STP Stop Mode Bit 1 The serial module will be disabled Setting the STP bit stops all clocks within the serial module including the crystal or external clock and SCLK except for the clock from the IMB The clock from the IMB remains active to allow 2 access to the MCR The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPUS2 or a hardware reset Accesses to serial module registers while in stop mode produce a bus error The serial module should be disabled in a known state prior to setting the STP bit otherwise unpredictable results may occur The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption The serial module is enabled and will operate in normal mode When STP 0 make sure the external crystal is stable XTAL_RDY bit bit of the interrupt status register ISR is zero before continuing NOTE The serial module should be disabled i e the STP bit in the MCR is set before executing the LPSTOP instruction to obtain the lowest power consumption The X1 X2 oscillator will continue to run during LPSTOP if STP 0 FRZ1 FRZ0 Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPU32 has entered background debug mode Table 7 1 lists the action taken for each combination of bits
63. 11 LPSTOP 3 23 MAID Bits 6 25 6 36 Master Station 7 15 Maximum Rating 11 1 MC68681 7 4 Memory Access Times 10 7 Interfacing 10 5 10 10 Memory to Memory Transfer 6 1 6 3 6 5 Microbus Controller 5 89 5 91 Microsequencer Operation 5 89 5 90 Misaligned Operands 3 7 MISC Bits 7 28 MODCK Signal 2 9 4 7 4 35 MODE Bits 8 6 8 8 8 10 8 12 8 14 8 16 8 22 8 28 Mode Register 1 7 13 7 16 7 17 7 22 7 34 7 47 Mode Register 2 7 4 7 17 7 38 7 47 Module Base Address Register 4 2 4 20 4 36 Access 3 27 Module Configuration Register 4 21 4 36 6 23 7 19 7 46 8 18 8 27 Locations 4 3 4 5 MOVE Instruction Timing Table 5 101 5 102 MOVEM Faults 5 56 5 58 5 59 5 61 MOVEP Faults 5 55 5 56 Multidrop Mode 7 15 7 16 7 23 Timing 7 16 Multiprocessor Systems 5 61 MOTOROLA MC68340 USER S MANUAL N NCS Bit 4 31 Negate RTS Command 7 29 Negative Tails 5 93 5 94 No Operation Command 5 86 Oi OC Bits 8 6 8 8 8 10 8 22 8 28 OE Bit 7 13 7 25 7 28 ON Bit 8 6 8 8 8 11 8 24 One Mode 8 23 OPO 7 6 7 36 7 38 OP1 7 7 7 36 7 38 7 7 7 36 7 37 OP6 7 7 7 36 7 37 Opcode Tracking in Loop Mode 5 88 Operand Faults 5 56 5 58 5 61 Misalignment 3 7 Size Field 5 73 Operation Field 5 73 Ordering Information 12 1 OUT Bit 8 7 8 8 8 10 8 24 Output Port Control Register 7 36 7 46 Data Register 7 6 7 7 7 22 7 37 Overrun Error 7 1
64. 3 5 7 PORT B DATA REGISTER PORTB 1 This is a single register that can be accessed at two different addresses This register affects only those pins configured as discrete I O A write is stored in the internal data latch and if any port B pin is configured as an output the value stored for that bit is driven on the pin A read of this register returns the value stored in the register only if the pin is configured as a discrete output Otherwise the value read is the value of the pin This register can be read or written at any time PORTB PORTB1 019 01B 7 6 5 4 3 2 1 0 es ope es m m Jm RESET U U U U U U U U Supervisor User MOTOROLA MC68340 USER S MANUAL 4 35 4 4 MC68340 INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the MC68340 after power up 4 4 1 Startup RESET is asserted by the MC68340 during the time in which Vcc is ramping up the VCO is locking onto the frequency and the MC68340 is going through the reset operation After RESET is negated four bus cycles are run with global CSO being asserted to fetch the 32 bit supervisor stack pointer SSP and the 32 bit program counter PC from the boot ROM Until programmed differently CSO is a global 16 bit wide three wait state chip select CSO can be programmed to continue decode for a range of addresses after the V bit is set provided the desired address range is first loaded into the 50 base address reg
65. 5 7 1 5 EFFECTS OF WAIT STATES The CPU32 access time for on chip peripherals is two clocks While two clock external accesses are possible when the bus is operated in a synchronous mode a typical external memory speed is three or more clocks All instruction times listed in this section are for word access only unless an explicit exception is given and are based on the assumption that both instruction fetches and operand cycles are to a two clock memory Any time a long access is made time for the additional bus cycle s must be added to the overall execution time Wait states due to slow external memory must be added to the access time for each bus cycle A typical application has a mixture of bus speeds program execution from an off chip ROM accesses to on chip peripherals storage of variables in slow off chip RAM and accesses to external peripherals with speeds ranging from moderate to very slow To arrive at an accurate instruction time calculation each bus access must be individually considered Many instructions have a head cycle count which can overlap the cycles of an operand fetch to slower memory started by a previous instruction In these cases an increase in access time has no effect on the total execution time of the pair of instructions To trace instruction execution time by monitoring the external bus note that the order of operand accesses for a particular instruction sequence is always the same provided bus speed is unc
66. 7 of the interrupt enable register IER is set to enable interrupts 0 Setting the corresponding bit in the IPCR has no effect on ISR bit 7 7 4 1 12 INTERRUPT STATUS REGISTER ISR The ISR provides status for all potential interrupt sources The contents of this register are masked by the IER If a flag in the ISR is set and the corresponding bit in IER is also set the IRQ output is asserted If the corresponding bit in the IER is cleared the state of the bit in the ISR has no effect on the output This register can only be read when the serial module is enabled i e the STP bit in the MCR is cleared NOTE The IER does not mask reading of the ISR True status is provided regardless of the contents of IER The contents of ISR are cleared when the serial module is reset ISR 715 7 6 5 4 3 2 1 0 COS DBB RxRDYB TxRDYB XTAL RxRDYA TxRDYA RDY RESET 0 0 0 0 1 0 0 0 Read Only Supervisor User COS Change of State 1 Achange of state has occurred at one of the CTS inputs and has been selected to cause an interrupt by programming bit 1 and or bit 0 of the ACR 0 The CPU32 has read the IPCR 7 32 MC68340 USER S MANUAL MOTOROLA DBB Delta Break B 1 The channel B receiver has detected the beginning end of a received break 0 The CPU32 has issued a channel B reset break change interrupt command Refer to 7 4 1 7 Command Register CR for more information on the reset break change interrupt command
67. 85 C MC68340CRP8V 0 C to 70 C MC68340RP16V MOTOROLA MC68340 USER S MANUAL 12 1 12 2 PIN ASSIGNMEN CERAMIC SURFACE MOUNT 12 2 1 144 Lead Ceramic Quad Flat Pack FE Suffix 2 REA B RG d1nnnnnnnannnnnnnnr dE TOP VIEW 33 MC68340 90 C vec x2 SCLK CTSB RTSB TxDB RxDB RxRDYA TxRDYA CTSA RTSA GND Vcc TxDA RxDA 2 rOUT2 GATE2 12 2 MC68340 USER S MANUAL MOTOROLA The and GND pins are separated into groups to help electrically isolate the output drivers for different functions of the MC68340 These groups are shown in the following table for the FE suffix package Pin Group FE Suffix 23 Address Bus Function Codes 41 50 59 68 134 42 51 60 69 135 Data Bus 113 123 114 124 AS BG CLKOUT DS FREEZE HALT IFETCH IPIPE 15 17 35 143 13 21 36 144 MODCK RESET RMC R W SIZ TDO TOUTI Internal Logic CS DACK DONE IRQ RTS R RDYA 78 90 102 79 91 103 TOUT2 TxDx T RDYA Internal Logic Oscillator gt lf m 3 Internal Only BEES SEU 55 126 MOTOROLA MC68340 USER S MANUAL 12 3 12 2 2 145 Lead Plastic Pin Grid Array RP Suffix O O O Cee MODCK EXTAL RESET BERR Cc cQ WOCHE Vcc XTAL Vcc CLKOUT HALT BGACK 05 GN O m O w E en r4 9 gt N nm N E 20 amp 0 O O
68. 9A AS to DS or CS Asserted Read tSTS 30 15 15 6 6 Address FC SIZ RMC Valid to AS CS and tAVS DS Read Asserted 12 CLKOUT Low to AS DS CS IFETCH tCLS IPIPE 1 Negated 30 612 Invalid Address Hold 3 AS DS CS IACK Negated to Address FC 14 AS CS and DS Read Width Asserted tsw 200 14A DS Width Asserted Write tswaw 90 14 AS CS IACK and DS Read Width Asserted tswp Fast Termination Cycle 3 AS DS CS Width Negated ton 80 6 CLKOUT High to AS DS R W High Impedance tcHsz 120 AS DS CS Negated to R W High tSNR 3 olo gt 42 ol 3 o EF gt n gt n EEE EA EA EA gt o 17 18 CLKOUT High to R W High tcHRH 0 20 AEN 23 i 24 i ite 215 oio gt o CLKOUT High to Data Out Valid tcHbO EH 60 60 e 60 m Fast Termination Write EA Z 3 o N gt n 5 DS CS Negated to Data Out Invalid Data Out tSNDO Hold 6 Data Out Valid to DS Asserted Write tDVS 0 27 Data In Valid to CLKOUT Low Data Setup tDIC 27A Late BERR HALT BKPT Asserted to CLKOUT tBELCL 40 Low Setup Time AS DS Negated to DSACK BERR HALT tSNDN Negated DS CS Negated to Data In Invalid Data In tSNDI gt 3 o r gt o 3 3 o o e EN 5 o Hold 4 DS CS Negated to Data In High Impedance tS
69. Bus Arbitration Control The bus arbitration control unit in the MC68340 is implemented with a finite state machine As discussed previously all asynchronous inputs to the MC68340 are internally synchronized in a maximum of two cycles of the clock As shown in Figure 3 25 input signals labeled R and A are internally synchronized versions of BR and BGACK respectively The BG output is labeled G and the internal high impedance control signal is labeled T If T is true the address data and control buses are placed in the high impedance state after the next rising edge following the negation of AS and RMC signals are shown in positive logic active high regardless of their true active voltage level The state machine shown in Figure 3 25 does not have a state 1 or state 4 State changes occur on the next rising edge of the clock after the internal signal is valid The BG signal transitions on the falling edge of the clock after a state is reached during which G changes The bus control signals controlled by T are driven by the MC68340 immediately following a state change when bus mastership is returned to the MC68340 State 0 in which G and T are both negated is the state of the bus arbiter while the MC68340 is bus master R and A keep the arbiter in state 0 as long as they are both negated The MC68340 does not allow arbitration of the external bus during the RMC sequence For the duration of this sequence the MC68340 ignores the BR inpu
70. Condition True Scc ea then 1s Destination else Os Destination If supervisor state STOP data then Immediate Data SR STOP else TRAP SUB Destination Source Destination SUB ea Dn SUB Dn ea SUBA Destination Source gt Destination SUBA ea An SUBI Destination Immediate Data Destination SUBI data ea SUBQ Destination Immediate Data Destination SUBQ data ea SUBX Destination Source X Destination SUBX Dx Dy SUBX Ax Ay SWAP Register 31 16 amp Register 15 0 SWAP Dn TAS Destination Tested Condition Codes TAS ea 1 bit 7 of Destination TBLS ENTRY n ENTRY n 1 ENTRY n TBLS size ea Dx Dx 7 0 256 Dx TBLS size Dym Dyn Dx TBLSN ENTRY n x 256 ENTRY n 1 ENTRY n TBLSN size ea Dx Dx 7 0 Dx TBLSN size Dym Dyn Dx TBLU ENTRY n ENTRY n 1 ENTRY n TBLU size ea Dx Dx 7 0 256 Dx TBLU size Dym Dyn Dx TBLUN ENTRY n 256 ENTRY n 1 ENTRY n TBLUN size ea Dx Dx 7 0 Dx TBLUN size Dym Dyn Dx TRAP SSP 2 SSP Format Offset SSP TRAP 4 vector SSP 4 SSP PC SSP SSP 2 SSP SR SSP Vector Address TRAPcc If cc then TRAP TRAPcc TRAPcc W data TRAPcc L data TRAPV If V then TRAP TRAPV Destination Tested Condition Codes TST ea UNLK An SP SP An SP 4 SP UNLK An NOTE 1 is direction L or R MOTOROLA MC68340 USER S MANUAL 5 19
71. EBI handles the transfer of information between the internal CPU32 or DMA controller and memory peripherals or other processing elements in the external address space Based on the MC68030 bus the external bus provides up to 32 address lines and 16 data lines Address extensions identify each bus cycle as CPU32 or DMA initiated supervisor or user privilege level and instruction or data access The data bus allows dynamic sizing for 8 or 16 bit bus accesses plus 32 bits for Synchronous transfers from the 2 or the DMA can be made in as little as two clock cycles Asynchronous transfers allow the MOTOROLA MC68340 USER S MANUAL 1 5 memory system to signal the CPU32 DMA when the transfer is complete and to note the number of bits in the transfer An external master can arbitrate for the bus using a three line handshaking interface 1 3 1 2 SYSTEM CONFIGURATION AND PROTECTION The M68000 family of processors is designed with the concept of providing maximum system safeguards System configuration and various monitors and timers are provided in the MC68340 Power on reset circuitry is a part of the SIM40 bus monitor ensures that the system does not lock up when there is no response to a memory access The bus fault monitor can reset the processor when a catastrophic bus failure occurs Spurious interrupts are detected and handled appropriately A software watchdog can pull the processor out of an infinite loop An interrupt
72. Family may incorporate other modules that may also be bus masters For these devices the MAID bits will be required For the MAID bits zero is the lowest priority and seven is the highest priority IARB Interrupt Arbitration ID Each module that generates interrupts has an IARB field These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level No two modules can share the same IARB value MOTOROLA MC68340 USER S MANUAL 6 25 The reset value of the IARB field is 0 which prevents the module from arbitrating during the interrupt acknowledge cycle The system software should initialize the IARB field to a value from F highest priority to 1 lowest priority NOTE The DMA module uses only one set of IARB bits for both channels A read or write to either MCR accesses the same IARB control bits 6 7 2 Interrupt Register INTR The INTR contains the priority level for the channel interrupt request and the 8 bit vector number of the interrupt The register can be read or written to at any time while in supervisor mode and while the DMA module is enabled i e the STP bit in the MCR is cleared INTR1 INTR2 784 7A4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ex seeds NTV RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Supervisor Only Bits 15 11 Reserved INTL Interrupt Level Bits Each module that can generate i
73. Figure 5 35 Example 2 Branch Not Taken 5 7 2 3 TIMING EXAMPLE 3 NEGATIVE TAILS This example see Figure 5 36 shows how to use negative tail figures for branches and other change of flow instructions In this example bus speed is assumed to be four clocks per access Instruction three is at the branch destination Although the CPU32 has a two word instruction pipeline internal delay causes minimum branch instruction time to be three bus cycles The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus on a slower bus there is no extra time for the third word Instructions MOVEQ 7 D1 BRA W FARAWAY MOVE L D1 DO BUS FETCH NEXT CONTROLLER BRANCH OFFSET FETCH MOVE L INSTRUCTION PREFETCH INSTRUCTION OFFSET MOVE EXECUTION MOVEQ 7 D1 BRA W FARAWAY MOVE L D1 D0 Figure 5 36 Example 3 Branch Negative Tail 5 96 MC68340 USER S MANUAL MOTOROLA Example 3 illustrates three different aspects of instruction time calculation 1 The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself 2 The negative tail allows execution to begin sooner than a three word pipeline would allow 3 There is a one clock delay due to late arrival of the displacement at the CPU Only changes of flow require negative tail ca
74. MANUAL 7 21 IVR 7 6 5 4 3 2 1 0 IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVRO RESET 0 0 0 0 Read Write IVR7 IVRO Interrupt Vector Bits 705 1 Supervisor Only Each module that generates interrupts has an interrupt vector field This 8 bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located The IVR is reset to 0F which indicates an uninitialized interrupt condition See Section 5 CPU32 for more information 7 4 1 4 MODE REGISTER 1 MR1 1 controls some of the serial module configuration This register can be read or written at any time when the serial module is enabled i e the STP bit in the MCR is cleared MR1A MR1B RESET 0 0 0 0 Read Write RxRTS Receiver Request to Send Control 710 718 7 6 5 4 3 2 1 0 0 Supervisor User 1 Upon receipt of a valid start bit RTS is negated if the channel s FIFO is full RTSz is reasserted when the FIFO has an empty position available 0 RTSz is asserted by setting bit 1 or the OP and negated by clearing bit 1 or 0 in the OP This feature can be used for flow control to prevent overrun in the receiver by using the RTS output to control the CTS input of the transmitting device If both the receiver and transmitter are programmed for RTS control RTS control will be disabled for both since this configuration is incorrect See 7 4 1 17 Mode Regist
75. My MOTOROLA MC68340 Integrated Processor with DMA User s Manual MOTOROLA INC 1992 Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and the are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer The complete docum
76. NEXT BUS MASTER ASSERTS BGACK BUS MASTER NEGATES BR 1 NEGATE BG AND WAIT FOR BGACK TO BE NEGATED OPERATE AS BUS MASTER 1 PERFORM DATA TRANSFERS READ AND WRITE CYCLES ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP RE ARBITRATE OR RESUME a PROCESSOR OPERATION 1 NEGATE BGACK Figure 3 22 Bus Arbitration Flowchart for Single Request MOTOROLA MC68340 USER S MANUAL 3 41 Figure 3 23 Bus Arbitration Timing Diagram ldle Bus Case S0 S1 52 53 54 55 DSACKO DSACK1 BR BGACK N Figure 3 24 Bus Arbitration Timing Diagram Active Bus Case 3 42 MC68340 USER S MANUAL MOTOROLA 3 6 1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR This signal can be wire ORed to indicate to the MC68340 that some external device requires control of the bus The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle if one has started If no BGACK is received while the BR is active the MC68340 remains bus master once BH is negated This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership 3 6 2 Bus Grant The MC68340 supports operand coherency thus if an operand transfe
77. O O O O O O 0O D Vccsyn Vcc GND SIZO GND gt m e c j gt a gt j gt gt O O O O gt N ce lt iw lt O lt gt gt w O O O O gt gt lt wo gt N gt Co I N gt O O O O gt a gt lt iw lt O O I e O O O O O gt gt gt e b ua gt N gt N gt a BOTTOM VIEW O O O O O O I m N I Co e iw O am iw gt jw O O O O O gt m lt O m O O O O O O m I gt lt jw e amp OTAD EC 20 ECCO eC 20 SQ BO EC ECC O O O O O O GND TxDB Vcc GND O O I S4 I lt eG POL qx Oe TxDA RTSA TxRDYA RTSB X2 X1 DONE1 CO SOLO CTSA RxRDYA RxDB 5 SCLK DREQ1 DREQ2 O c N O wn e O wn jw Rx C I 12 4 MC68340 USER S MANUAL MOTOROLA The and GND pins are separated into groups to help electrically isolate the different output drivers of the MC68340 Thes
78. OJA C W 33 27 MOTOROLA MC68340 USER S MANUAL 11 3 POWER CONSIDERATIONS The average chip junction temperature Ty in can be obtained from TA PD 1 where TA Ambient Temperature Package Thermal Resistance Junction to Ambient C W PD PINT PINT ICC x Vcc Watts Chip Internal Power PIO Power Dissipation on Input and Output Pins User Determined For most applications P o lt PINT and can be neglected An approximate relationship between P p and T J if P1 O is neglected is Pp K TJ 273 C Solving Equations 1 and 2 for K gives TA 273 C 09JA Pp where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at thermal equilibrium for a Known TA Using this value of K the values of PD and TJ can be obtained by solving Equations 1 and 2 iteratively for any value of TA 11 4 AC ELECTRICAL SPECIFICATION DEFINITIONS The AC specifications presented consist of output delays input setup and hold times and signal skew times All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals The measurement of the AC specifications is defined by the waveforms shown in Figure 11 1 To test the parameters guaranteed by Motorola inputs must be driven to the voltage levels specified in the figure Outputs are specified with minimum and or max
79. READY NEXT CMD ILLEGAL NOT READY NEXT CMD COMPLETE XXX BERR AERR NEXT CMD NOT READY FILL LONG DATA gran i XXX NOT READY LOCATION NOT READY NEXT CMD COMPLETE BERR AERR XXX ILLEGAL NEXT CMD READY NEXT CMD READY Operand Data A single operand is data to be written to the memory location Byte data is transmitted as a 16 bit word justified in the least significant byte 16 and 32 bit operands are transmitted as 16 and 32 bits respectively Result Data Status is returned as in the WRITE command 0FFFF for a successful operation and 10001 for a bus or address error during write 5 6 2 8 12 Resume Execution GO The pipeline is flushed and refilled before normal instruction execution is resumed Prefetching begins at the return PC and current privilege level If either the PC or SR is altered during BDM the updated value of these registers is used when prefetching commences NOTE The processor exits BDM when a bus error or address error occurs on the first instruction prefetch from the new error is trapped as a normal mode exception The stacked value of the current PC may not be valid in this case depending on the state of the machine prior to entering BDM For address error the PC does not reflect the true return PC Instead the stacked fault address is the odd retu
80. Rev 1 TABLE OF CONTENTS Continued Page Title Number Changing Privilege 5 39 m feeit 5 39 Exception VOGLOLS aeui ete e E ee tat ade eae tate 5 40 Types OL ECO PHONG ooi t 5 41 Exception Processing Sequence eese 5 41 5 42 5 42 Processing of Specific Exceptions 5 44 PRES CE stasera fuc a nds cai e ctae is Stel 5 44 BUS EIOS eo preste da 5 46 Address deca e te eH i aote t LL 5 46 Instruction ete 5 47 Software 5 47 Hardware Breakpoints sse 5 48 etie cota lod dg bs Eie cde 5 48 Illegal or Unimplemented Instructions 5 48 Privilege VIOIdHOFIS t uide ale 5 49 Brie EN 5 50 IFITGETEDIS e ona eee 5 51 Return from 5 52 FSCO MG IG
81. SU 60A 64A S U COUNTER REGISTER CNTR so E sut sU 00 sU 2 90 Figure 8 11 Timer Module Programming Model In the registers discussed in the following paragraphs the numbers in the upper right hand corner indicate the offset of the register from the base address specified by the module base address register MBAR in the 5 40 The first number is the offset for timer 1 the second number is the offset for timer 2 The numbers on the top line of the register represent the bit position in the register The register contains the mnemonic for the bit The value of these bits after a hardware reset is shown below the register The access privilege is shown in the lower right hand corner NOTE A CPU32 RESET instruction will not affect the MCR but will reset all other registers in the timer modules as though a hardware reset occurred The term timer is used to reference either timer 1 or timer 2 since the two are functionally equivalent 8 4 1 Module Configuration Register MCR The MCR controls the timer module configuration This register can be either read or written when the module is enabled and is in the supervisor state The MCR is not affected by a CPU32 RESET instruction MCR 600 640 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Supervisor Only 8 18 MC68340 USER S MANUAL MOTOROLA STP Stop bit 1 Setting the STP bit stops all clocks within
82. The MC68340 always attempts to transfer the maximum amount of data on all bus cycles for a word operation it always assumes that the port is 16 bits wide when beginning the bus cycle The bytes of operands are designated as shown in Figure 3 2 The most significant byte of a long word operand is OPO and OP3 is the least significant byte The two bytes of a word length operand are OPO most significant and OP1 The single byte of a byte length operand is OPO These designations are used in the figures and descriptions that follow Figure 3 2 shows the required organization of data ports on the MC68340 bus for both 8 and 16 bit devices The four bytes shown in Figure 3 2 are connected through the internal data bus and data multiplexer to the external data bus The data multiplexer establishes the necessary connections for different combinations of address and data sizes The multiplexer takes the two bytes of the 16 bit bus and routes them to their required positions The positioning of bytes is determined by the SIZ1 SIZO and AO outputs The SIZ1 SIZO outputs indicate the number of bytes to be transferred during the current bus cycle see Table 3 1 The number of bytes transferred during a read or write bus cycle is equal to or less than the size indicated by the SIZ1 SIZO outputs depending on port width For example during the first bus cycle of a long word transfer to a word port the size outputs indicate that four bytes are to be transferred alt
83. The TRAPcc CHK and CHk2 instructions force exceptions when a program detects a run time error The DIVS and DIVU instructions force an exception if a division operation is attempted with a divisor of zero Exception processing for traps follows the regular sequence If tracing is enabled when an instruction that causes a trap begins execution a trace exception will be generated by the instruction but the trap handler routine will not be traced the trap exception will be processed first then the trace exception The vector number for the TRAP instruction is internally generated part of the number comes from the instruction itself The trap vector number PC value and a copy of the SR are saved on the supervisor stack The saved PC value is the address of the instruction that follows the instruction that generated the trap For all instruction traps other than TRAP a pointer to the instruction causing the trap is also saved in the fifth and sixth words of the exception stack frame 5 5 2 5 SOFTWARE BREAKPOINTS To support hardware emulation the CPU32 must provide a means of inserting breakpoints into target code and of announcing when a breakpoint is reached The MC68000 and 68008 can detect an illegal instruction inserted at a breakpoint when the processor fetches from the illegal instruction exception vector location Since the VBR on the CPU32 allows relocation of exception vectors the exception vector address is not a
84. The receiver clock is always 16 times the baud rate shown in this list except when SCLK is used Set setz _ 5 a ow _ 300 0 _ eo 120 1200 1200 1200 7 26 MC68340 USER S MANUAL MOTOROLA TCS3 TCSO Transmitter Clock Select These bits select the baud rate clock for the channel transmitter from a set of baud rates listed in Table 7 5 The baud rate set selected depends upon ACR bit 7 Set 1 is selected if ACR bit 7 0 and set 2 is selected if ACR bit 7 1 The transmitter clock is always 16 times the baud rate shown in this list except when SCLK is used Table 7 TCS2 e TCSx Control Bits TCS1 TCSO Psat sa m e o 5 e owe 7 7 4 1 7 COMMAND REGISTER CR The is used to supply commands to the channel Multiple commands can be specified in a single write to the CR if the commands are not conflicting e g reset transmitter and enable transmitter commands cannot be specified in a single command This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared MOTOROLA CRA CRB 712 71A 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User MC68340 USER S MANUAL 7 27 MISC3 MISCO Miscellaneous Commands These bits select a single command as listed in Table 7 6 Table 7 6 MISCx Control Bits Reset Break Change Interrupt ec Exec poscit Po f
85. This bit cannot be enabled to generate an interrupt 1 This bit is set at reset 0 This bit is cleared after the baud rate generator is stable The CSR should not be accessed until this bit is zero DBA Delta Break 1 The channel A receiver has detected the beginning or end of a received break 0 The CPU32 has issued a channel A reset break change interrupt command Refer to 7 4 1 7 Command Register CR for more information on the reset break change interrupt command MOTOROLA MC68340 USER S MANUAL 7 33 RxRDYA Channel A Receiver Ready or FIFO Full The function of this bit is programmed by MR14 bit 6 1 If programmed as receiver ready a character has been received in channel A and is waiting in the receiver buffer FIFO If programmed as FIFO full a character has been transferred from the receiver shift register to the FIFO and the transfer has caused the channel A FIFO to become full all three positions are occupied 0 If programmed as receiver ready the CPU32 has read the receiver buffer After this read if more characters are still in the FIFO the bit is set again after the FIFO is popped If programmed as FIFO full the CPU32 has read the receiver buffer If a character is waiting in the receiver shift register because the FIFO is full the bit will be set again when the waiting character is loaded into the FIFO TxRDYA Channel A Transmitter Ready This bit is the duplication of the TxRDY bit in SRA 1 The
86. This field can be used to specify the destination access to a certain address space type The destination function code bits are defined in Table 6 6 Table 6 6 Address Space Encoding 3 2 1 0 Address Spaces 0 o o o f Reserved Motorola 0 o o 1 UserData Space 1 0 UserProgramSpace Reserved User Reserved Motorola Supervisor Data Space CPU Space DMA Space ae o ESO pex 1 1 Supervisor Program pT ptt es ED RETE NOTE Although FC3 can be set for DMA transfers to distinguish the source or destination space from other data or program spaces it is not required to be set Since the CPU32 currently has only 3 bit SFC and DFC capability it cannot emulate FC3 1 at this time However it is recommended that FC3 be set to one to distinguish DMA or CPU access during debug 6 32 MC68340 USER S MANUAL MOTOROLA 6 7 6 Source Address Register SAR The SAR is a 32 bit register that contains the address of the source operand used by the DMA to access memory or peripheral registers This register is accessible in either supervisor or user space The SAR can always be read or written to when the DMA module is enabled i e the STP bit in the MCR is cleared SAR1 SAR2 78C 7AC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 t U Unaffected by reset Supervisor User During the DMA read cycle the SAR drives
87. USER S MANUAL 5 109 5 7 3 11 CONDITIONAL BRANCH INSTRUCTIONS The conditional branch instruction table indicates the number of clock periods needed for the processor to perform the specified branch on the given branch size with complete execution times given No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes ke 10 0 2 0 po T o CEO 9 8 0 1 0 DBcc F not 1 taken 6 10 0 0 0 In loop mode 5 110 MC68340 USER S MANUAL MOTOROLA 5 7 3 12 CONTROL INSTRUCTIONS The control instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode Footnotes indicate when to account for the appropriate EA times The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Cycles Em am o o eem m em os o oem _ mo e o seem Em gt e see e sms x mmm _ s _ 2 mmm _ o sm
88. USER S MANUAL MOTOROLA COUNTER CLOCK COUNTER 0 f f f f f 0 0 0 0 10 f f f f f f 0 0 0 0 0 0 f f rof f f f f 0 0 0 0 0 10 f f d C b 2 1 1 1 1 0 f e TGATE ENABLE TG BIT SET TIMEOUT TO BIT SET MODEx Bits in Control Register 110 Bit of the Control Register 1 Figure 8 10 Event Count Mode The timer is enabled by setting the SWR and CPE bits in the CR and if TGATE is enabled TGE bit of the CR is set then asserting TGATEz When the timer is enabled the SR ON bit is set On the next falling edge of the counter clock the counter is loaded with the value of FFFF With each successive falling edge of the counter clock the counter decrements The PREL1 and PREL2 registers are not used in this mode If TGATE is not enabled CR TGE bit is cleared then TGATE does not start or stop the timer or affect the TG bit of the SR In this case the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set If TGATE is enabled CR bit is set then the assertion of TGATE starts the counter The negation of TGATE disables the counter sets the SR TG bit and clears the ON bit in the SR If TGATE is reasserted the timer resumes counting from where it was stopped and the ON bit is set again Further assertions and negations of TGATE have the same effect The TGL bit in the SR reflects the level of TGATE
89. When the external device uses DREG the channel can be programmed to operate in either burst transfer mode or cycle steal mode 6 4 2 1 DUAL ADDRESS READ During the dual address read cycle the DMA reads data from a device or memory into the internal DHR The device or memory is selected by the address specified in the SAR the source function codes in the FCR and the source size in the CCR Data is read from the memory or peripheral and placed in the DHR when the bus cycle is terminated When the complete operand has been read the SAR is incremented by 0 1 2 or 4 according to the size and increment information specified by the SSIZE and SAPI bits of the CCR The DMA control signals DACK and DONE asserted in the source read cycle when the source device makes a request See Figures 6 9 and 6 10 for timing diagrams of dual address read for external burst and cycle steal modes 6 12 MC68340 USER S MANUAL MOTOROLA VIOYOLOW TWANVIN S YASN 07289921 619 CPUCYCLE DMA READ DMA WRITE DMA READ DMA WRITE CPU CYCLE SO S2 54 SO 52 54 SO S2 54 SO S2 54 SO S2 54 SO S2 S4 CLKOUT 1 FC3 FCO 5121 5120 B H 015 00 DSACKx DREQx DONEx INPUT DACKx N N DONEx OUTPUT NOTE 1 Timing to generate more than one DMA transfer 2 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle 3 DREQx must be asserted while DACKx is asserted and meet th
90. Y A0 X N 5170 X 1 5171 X N 1 VECTOR FROM 16 BIT PORT DSACKx VECTOR FROM 8 BIT PORT IACK7 IACK1 READ gt CYCLE lt INTERNAL gt lt WRITE ARBITRATION STACK lt IACK CYCLE gt Internal Arbitration may take between 0 2 clock cycles Figure 3 15 Interrupt Acknowledge Cycle Timing 3 4 4 2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE When the interrupting device cannot supply a vector number it requests an automatically generated vector autovector Instead of placing a vector number on the data bus and asserting DSACK the device asserts AVEC to terminate the cycle If the DSACK signals are asserted during an interrupt acknowledge cycle terminated by AVEC the DSACK signals and MOTOROLA MC68340 USER S MANUAL 3 29 data will be ignored if AVEC is asserted before or at the same time as the DSACK signals The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt When AVEC is asserted instead of DSACK during an interrupt acknowledge cycle the MC68340 ignores the state of the data bus and internally generates the vector number the sum of the interrupt level plus 24 18 AVEC is multiplexed with CSO The FIRQ bit in the SIM40 module configuration register controls whether the AVEC CSO pin is used as an autovector input or as CSO refer to Section 4 System Integration Module for a
91. a single 4 Kbyte block that is relocatable along 4 Kbyte boundaries The location is fixed by writing the desired base address of the SIM40 block to the module base address register using the MOVES instruction The module base address register is only accessible in CPU space at address 0003FF00 The SFC or DFC register must indicate CPU space 7 using the MOVEC instruction before accessing the module base address register Refer to Section 4 System Integration Module for additional information on the module base address register 3 4 4 Interrupt Acknowledge Bus Cycles The CPU32 makes an interrupt pending in three cases The first case occurs when peripheral device signals the CPUS2 with IRQ7 IRQ1 that the device requires service and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register The second case occurs when a transition has occurred in the case of a level 7 interrupt A recognized level 7 interrupt must be removed for one clock cycle before a second level 7 can be recognized The third case occurs if upon returning from servicing a level 7 interrupt the request level stays at 7 and the processor mask level changes from 7 to a lower level a second level 7 is recognized The CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any other pending exception with a higher priority The following
92. a value other than 0 for the 5 40 to autovector for external interrupts 4 3 2 3 RESET STATUS REGISTER RSR The RSR contains a bit for each reset source to the SIM40 A set bit indicates the last type of reset that occurred and only one bit can be set in the register The RSR is updated by the reset control logic when the SIM40 comes out of reset This register can be read at any time a write has no effect For more information see Section 3 Bus Operation RSR 007 1 6 5 4 3 2 1 0 er sw oor o Te T5 Supervisor Only EXT External Reset 1 The last reset was caused by an external signal driving RESET POW Power Up Reset 1 The last reset was caused by the power up reset circuit SW Software Watchdog Reset 1 The last reset was caused by the software watchdog circuit DBF Double Bus Fault Monitor Reset 1 The last reset was caused by the double bus fault monitor Bits 3 O Reserved MOTOROLA MC68340 USER S MANUAL 4 23 LOC Loss of Clock Reset 1 The last reset was caused by a loss of frequency reference to the clock synthesizer This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled SYS System Reset 1 The last reset was caused by the CPU32 executing a RESET instruction The system reset does not load a reset vector or affect any internal CPU32 registers SIM40 configuration registers or the MCR in each internal peripheral module DMA timers and serial
93. address and the SIZx pins to indicate a long word operand LONG WORDOPERAND OPO 0 2 0 DSACK1 DSACKO 1 0 gt DATA BUS 5121 5120 0 0 1 1 1 0 1 0 1 0 0 1 1 0 For a read operation shown in Figure 3 3 the slave responds by placing the most significant byte of the operand on bits 15 8 of the data bus and asserting DSACKO to indicate an 8 bit port The MC68340 reads the most significant byte of the operand byte 0 from bits 15 8 and ignores bits 7 0 The MC68340 then decrements the transfer size counter increments the address initiates a new cycle and reads byte 1 of the operand from bits 15 8 of the data bus The MC68340 repeats the process of decrementing the transfer size counter incrementing the address initiating a new cycle and reading a byte to transfer the remaining two bytes For a write operation shown in Figure 3 4 the MC68340 drives the two most significant bytes of the operand on bits 15 0 of the data bus The slave device then reads only the most significant byte of the operand byte 0 from bits 15 8 of the data bus and asserts DSACKO to indicate reception and an 8 bit port The MC68340 then decrements the transfer size counter increments the address and writes byte 1 of the operand to bits 15 8 of the data bus The MC68340 continues to decrement the transfer size counter increment the address and write a byte to transfer the remaining two bytes to the slave device
94. all parameters specified relative to the falling edge of the clock 3 This input timing is applicable to all parameters specified relative to the rising edge of the clock 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters specified relative to the assertion negation of another signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Signal valid to signal valid specification maximum or minimum F Signal valid to signal invalid specification maximum or minimum Figure 11 1 Drive Levels and Test Points for AC Specifications 11 4 MC68340 USER S MANUAL MOTOROLA 11 5 DC ELECTRICAL SPECIFICATIONS See notes a b c and d corresponding to part operation GND 0 Vdc TA 0 to 70 see numbered notes Input Leakage Current All Input Only Pins Vin or GND Hi Z Off State Leakage Current All Noncrystal Outputs and I O Pins Vin 0 5 2 4 V1 Signal Low Input Current TMS TDI VIL 0 8 V Signal High Input Current TMS TDI ViH 2 2 0 V Output High Voltage 2 0 8 mA 4 75 V All Noncrystal Outputs except HALT RESET DONE2 DONE1 Output Low Voltage IOL 2 0 mA CLKOUT FREEZE IPIPE IFETCH IOL 3 2 mA 23 0 015 00 FC3 FOO 5171 SIZO IOL 5 3 mA All Other Output Only and
95. an address character After a slave receives a block of data the slave station s CPU disables the receiver and initiates the process again MOTOROLA MC68340 USER S MANUAL 7 15 C6 C7 C8 ARE LOST RECEIVER ENABLED RXRDY SRO W FFULL SR1 RXRDYA 7 CS R R R R R RRR STATUS DATA STATUS DATA STATUS DATA STATUS DATA C1 C2 C3 by C5 OVERRUN ST SR4 RESET BY COMMAND OPR 0 21 NOTES 1 Timing shown for MR1 7 1 2 Timing shown for OPCR 4 1 and MR1 6 0 3 R Read 4 CN Received Character Figure 7 8 Multidrop Mode Timing Diagram A transmitted character from the master station consists of a start bit a programmed number of data bits an address data A D bit flag and a programmed number of stop bits The A D bit identifies the type of character being transmitted to the slave station The character is interpreted as an address character if the A D bit is set or as a data character if the A D bit is cleared The polarity of the A D bit is selected by programming bit 2 of the MR1 The MR1 should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer In multidrop mode the receiver continuously monitors the received data stream regardless of whether it is enabled or disabled If the receiver is disabled it sets the 7 16 MC68340 USER S MANUAL MOTOROLA RxRDY bit and loads the character into the receiver
96. arithmetic operations 5 22 MC68340 USER S MANUAL MOTOROLA Table 5 5 Integer Arithmetic Operations Operand Syntax Operand Size Operation Dn 8 16 32 Source Destination Destination ea Dn 8 16 32 16 32 Source Destination Destination data ea 8 16 32 Immediate Data Destination Destination data ea 8 16 32 Immediate Data Destination Destination Dn Dn 8 16 32 Source Destination X gt Destination An An 8 16 32 0 Destination Destination Source CCR shows results Destination Source CCR shows results Destination Immediate Data CCR shows results Destination Source CCR shows results 8 16 32 Lower bound lt Rn lt Upper Bound CCR shows results Dr Dq 64 32 32 32 Dq 32 32 32 DIVSL DIVUL Dr Dq 32 32 32 32 DIVS DIVU EXTB Sign Extended Destination Destination MULS MULU Dn 16 x16 gt 32 Source x Destination Destination signed or DI 32 x 32 32 unsigned ea Dh DI 32 x32 64 8 16 32 0 Destination Destination 8 16 32 0 Destination X Destination 8 16 32 Destination Source gt Destination 16 32 Destination Source gt Destination data ea 8 16 32 Destination Immediate Data Destination data ea 8 16 32 Destination Immediate Data Destination Dn Dn 8 16 32 Destination Source X Destinati
97. as the counter clock A division of the selected clock is applied to the counter as listed in Table 8 4 Table 8 4 POT Encoding IPIE POT2 POT1 POTO Selected Clock o o 1 bme o mewa o o Duets L3 s o fewe o pveetrsz 3 3 pveetrss o o o bewe MODE2 MODE0 Operation Mode These bits select one of the eight modes of operation for the timer as listed in Table 8 5 Refer to 8 3 Operating Modes for more information on the individual modes Table 8 5 MODEx Encoding wooe OPERATIONmoDE o o wewCaweOwpuCompae o o _ Sauare wave Generator o o Varane Duy Cycle Square Wave Generator o 3 1 Varene wan Singe Shot Pulse Generator Pas With Measurement 3 0 1 Period 3 9 OC1 OC0 Output Control These bits select the conditions under which TOUTx changes see Table 8 6 These bits may have a different effect when in the input capture output compare mode Caution should be used when modifying the OC bits near timer events Table 8 6 OCx Encoding o o o 1 Toogemode La 8 22 MC68340 USER S MANUAL MOTOROLA Disabled TOUTx is disabled and three stated Toggle Mode lf the timer is disabled SWR 0 when this encoding is programmed TOUTx is immediately set to zero If the timer is enabled SWR 1 timeout events
98. be delayed To maximize available bus bandwidth the CPU32 will schedule prefetch only when the next instruction is not a change of flow instruction and when there is room in the pipeline for the prefetch 5 7 1 3 2 Write Pending Buffer The CPU32 incorporates a single operand write pending buffer The buffer permits the microsequencer to continue execution after a request for a write cycle is queued in the bus controller The time needed for a write at the end of an instruction can overlap the head cycle time for the following instruction thus reducing overall execution time Interlocks prevent the microsequencer from overwriting the buffer 5 7 1 3 3 Microbus Controller The microbus controller performs bus cycles issued by the microsequencer Operand accesses always have priority over instruction prefetches Word and byte operands are accessed in a single CPU initiated bus cycle although the external bus interface may be required to initiate a second cycle when a word operand is sent to a byte sized external port Long operands are accessed in two bus cycles most significant word first The instruction pipeline is capable of recognizing instructions that cause a change of flow It informs the bus controller when a change of flow is imminent and the bus controller refrains from starting prefetches that would be discarded due to the change of flow 5 7 1 4 INSTRUCTION EXECUTION OVERLAP Overlap is the time measured in clock cycles that an
99. bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the periodic timer When the SIM40 responds to the IACK cycle the periodic interrupt vector from the PICR is placed on the bus This vector number is multiplied by four to form the vector offset which is added to the vector base register to obtain the address of the vector 4 3 2 7 PERIODIC INTERRUPT TIMER REGISTER PITR The PITR contains control for prescaling the software watchdog and periodic timer as well as the count value for the periodic timer This register can be read or written at any time Bits 15 10 are not implemented and always return zero when read A write does not affect these bits PITR 024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 MODCK MODCK 0 0 0 0 0 0 0 0 Supervisor Only Bits 15 10 Reserved SWP Software Watchdog Prescale This bit controls the software watchdog clock source as shown in 4 3 2 5 System Protection Control Register SYPCR 1 Software watchdog clock prescaled by a value of 512 0 Software watchdog clock not prescaled The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset PTP Periodic Timer Prescaler Control This bit contains the prescaler control for the periodic timer 1 Periodic timer clock prescaled by a value of 512 0 Periodic timer clock not prescaled The PTP reset value is the inverse of the MODCK bit state on the rising
100. bus and retry a bus cycle during a read modify write cycle must assert only BERR and BR HALT must not be included The bus error handler software should examine the read modify write bit in the special status word see Section 5 CPU32 and take the appropriate action to resolve this type of fault when it occurs MOTOROLA MC68340 USER S MANUAL 3 37 50 S2 54 S0 S2 54 CLKOUT RW 3 N DS N N DSACKx cane Cae BERR HALT N gt WRITE HALT WRITE lt gt lt gt lt CYCLE RERUN Figure 3 20 Late Retry Sequence 3 5 3 Halt Operation When HALT is asserted and is not asserted the MC68340 halts external bus activity at the next bus cycle boundary see Figure 3 21 HALT by itself does not terminate a bus cycle Negating and reasserting HALT in accordance with the correct timing requirements provides a single step bus cycle to bus cycle operation Since HALT affects external bus cycles only a program that does not require use of the external bus may continue executing The single cycle mode allows the user to proceed through and debug external MC68340 operations one bus cycle at a time Since the occurrence of a bus error while HALT is asserted causes a retry operation the user must anticipate retry cycles while debugging in the single cycle mode The single step operation and the software trace capability allow the system
101. bus master If no exceptions occur all operands in the data block will be transferred in one burst so that the will use 100 of the available bus bandwidth 6 3 1 2 INTERNAL REQUEST LIMITED RATE To guarantee that the DMA will not use all of the available bus bandwidth during a transfer internal requests can be generated according to the amount of bus bandwidth allocated to the DMA There are three programmed constants in the CCR used to monitor the bus activity and allow the DMA to use a percentage of the bus bandwidth Options are 25 50 and 75 of 1024 clock periods See Table 6 5 for more information 6 3 2 External Request Generation To control the transfer of operands to or from memory in an orderly manner a peripheral device uses the DREQx input signal to request service If the channel is programmed for external request and the CCR STR bit is set an external request DREQ signal must be asserted before the channel requests the bus and begins a transfer The DMA supports external burst mode and external cycle steal mode The generation of the request from the source or destination is specified by the ECO bit of the CCR The external requests can be for either single or dual address transfers 6 3 2 1 EXTERNAL BURST MODE For external devices that require very high data transfer rates the burst request mode allows the DMA channel to use all of the bus bandwidth under control of the external device In burst mode the DR
102. can be lowered under software control to reduce current consumption when performance is less critical Idle internal peripheral modules can be turned off to save power 5 10 each Running a special low power stop LPSTOP instruction shuts down the active circuits in the CPU and peripheral modules halting instruction execution Power consumption in this standby mode is reduced to about 350 uW Processing and power consumption can be resumed by resetting the part or by generating an interrupt with the 51 40 5 periodic interrupt timer 1 5 PHYSICAL The MC68340 is available as 0 16 78 MHz and 0 25 16 MHz 0 C to 70 and 40 C to 85 C 5 0 V 5 and 3 3 V 0 3 supply voltages reduced frequencies at 3 3 V Thirty two power and ground leads minimize ground bounce and ensure proper isolation of different sections of the chip including the clock oscillator A 144 pins are used for signals and power The MC68340 is available in a gull wing ceramic quad flat pack CQFP with 25 6 mil 0 001 in lead spacing or a 15 x 15 plastic pin grid array PPGA with 0 1 in pin spacing 1 6 COMPACT DISC INTERACTIVE The MC68340 was designed to meet the needs of many markets including compact disc interactive CD I CD I is an emerging standard for a publishing medium that will bring multimedia to a broad general audience the consumer CD I players combine television and stereo systems as output devices with interactive control using a TV remote
103. can be programmed to enable and disable the counters and prescalers TGATE can also be programmed as a simple input 2 14 2 Timer Input TIN2 TIN1 These inputs can be programmed as clocks that cause events to occur in the counters and prescalers 2 14 3 Timer Output TOUT2 TOUT1 These outputs drive the various output waveforms generated by the timers 2 12 MC68340 USER S MANUAL MOTOROLA 2 15 TEST SIGNALS The following signals are used with the on board test logic defined by the IEEE 1149 1 standard See Section 9 IEEE 1149 1 Test Access Port for more information on the use of these signals 2 15 1 Test Clock TCK This input provides a clock for on board test logic defined by the IEEE 1149 1 standard 2 15 2 Test Mode Select TMS This input controls test mode operations for on board test logic defined by the IEEE 1149 1 standard 2 15 3 Test Data In TDI This input is used for serial test instructions and test data for on board test logic defined by the IEEE 1149 1 standard 2 15 4 Test Data Out TDO This output is used for serial test instructions and test data for on board test logic defined by the IEEE 1149 1 standard 2 16 SYNTHESIZER POWER VCCSYN This pin supplies a quiet power source to the VCO to provide greater frequency stability It is also used to control the synthesizer mode after reset See Section 4 System Integration Module for more information 2 17 SYSTEM POWER AND GROUND V cc AND GND Th
104. can be sent to the CPU32 with programmable regularity for DRAM refresh time of day clock task switching etc 1 3 1 3 CLOCK SYNTHESIZER The clock synthesizer generates the clock signals used by all internal operations as well as a clock output used by external devices The clock synthesizer can operate with an inexpensive 32768 Hz watch crystal or an external oscillator for reference using an internal phase locked loop and voltage controlled oscillator At any time software can select clock frequencies from 131 kHz to 16 78 MHz or 25 16 MHz favoring either low power consumption or high performance Alternately an external clock can drive the clock signal directly at the operating frequency With its fully static HCMOS design it is possible to completely stop the system clock without losing the contents of the internal registers 1 3 1 4 CHIP SELECT AND WAIT STATE GENERATION Four programmable chip selects provide signals to enable external memory and peripheral circuits providing all handshaking and timing signals with up to 175 ns access times with a 25 MHz system clock 265 ns 16 78 MHz Each chip select signal has an associated base address and an address mask that determine the addressing characteristics of that chip select Address space and write protection can be selected for each The block size can be selected from 256 bytes up to 4 Gbytes in increments of 2 Accesses can be preselected for either 8 or 16 bit transfers Fast synch
105. capable of a scanning user defined values into the output buffers b capturing values presented to input pins c controlling the direction of bidirectional pins and d controlling the output drive of three state output pins For more details on the function and uses of EXTEST please refer to the IEEE 1149 1 document 9 4 2 SAMPLE PRELOAD 001 The SAMPLE PRELOAD instruction selects the 132 bit boundary scan register and provides two separate functions First it provides a means to obtain a snapshot of system data and control signals The snapshot occurs on the rising edge of TCK in the capture DR controller state The data can be observed by shifting it transparently through the boundary scan register 9 10 MC68340 USER S MANUAL MOTOROLA Since there is no internal synchronization between the IEEE 1149 1 clock TCK and the system clock CLKOUT the user must provide some form of external synchronization to achieve meaningful results The second function of SAMPLE PRELOAD is to initialize the boundary scan register output bits prior to selection of EXTEST This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction 9 4 3 BYPASS X1X 101 The BYPASS instruction selects the single bit bypass register as shown in Figure 9 9 This creates a shift register path from TDI to the bypass register and finally to TDO circumventing the 132 bit boundary scan register This instructi
106. causes a reset to occur if the internal HALT is asserted by the CPUS2 indicating a double bus fault A double bus fault results when a bus or address error occurs during the exception processing sequence for a previous bus or address error a reset or while the CPU32 is loading information from a bus error stack frame during an RTE instruction This function can be disabled See Section 3 Bus Operation for more information Spurious Interrupt Monitor If no interrupt arbitration occurs during an interrupt acknowledge IACK cycle the bus error signal is asserted internally This function cannot be disabled Software Watchdog The software watchdog asserts reset or a level 7 interrupt as selected by the system protection and control register if the software fails to service the software watchdog for a designated period of time i e because it is trapped in a loop or lost There are eight selectable timeout periods This function can be disabled Periodic Interrupt Timer The SIM40 provides a timer to generate periodic interrupts The periodic interrupt time period can vary from 122 us to 15 94 s with a 32 768 kHz crystal used to generate the system clock This function can be disabled Figure 4 2 shows a block diagram of the system configuration and protection function 4 4 MC68340 USER S MANUAL MOTOROLA MODULE CONFIGURATION RESET STATUS DOUBLE BUS FAULT MONITOR SOFTWARE RESET REQUEST or CLOCK Fig
107. channel B The output is held high mark condition when the transmitter is disabled idle or operating in the local loopback mode Data is shifted out on this signal at the falling edge of the clock source with the least significant bit transmitted first 7 2 7 Channel B Receiver Serial Data Input RxDB This signal is the receiver serial data input for channel B Data on this signal is sampled on the rising edge of the clock source with the least significant bit received first 7 2 8 Channel A Request To Send RTSA This active low output signal is programmable as the channel A request to send or as a dedicated parallel output 7 2 8 1 RTSA When used for this function this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter When connected to the clear to send CTS input of a transmitter this signal can be used to control serial data flow 7 2 8 2 OPO When used for this function this output is controlled by bit O in the output port data register OP 7 2 9 Channel B Request To Send RTSB This active low output signal is programmable as the channel B request to send or as a dedicated parallel output 7 6 MC68340 USER S MANUAL MOTOROLA 7 2 9 1 RTSB When used for this function this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter When connected to the CTS input of a transmitter this signal can be used to control s
108. clock module 3 46 MC68340 USER S MANUAL MOTOROLA 3 INTRST internal reset goes to all other internal circuits Synchronous reset sources are not asserted until the end of the current bus cycle whether or not RMC is asserted The internal bus monitor is automatically enabled for synchronous resets therefore if the current bus cycle does not terminate normally the bus monitor terminates it Only single byte or word transfers are guaranteed valid for synchronous resets An external or clock reset is a synchronous reset source Asynchronous reset sources indicate a catastrophic failure and the reset controller logic immediately resets the system Resetting the MC68340 causes any bus cycle in progress to terminate as if BERR had been asserted In addition the MC68340 appropriately initializes registers for a reset exception Asynchronous reset sources include power up software watchdog double bus fault resets and execution of the RESET instruction If an external device drives RESET low RESET should be asserted for at least 590 clock periods to ensure that the MC68340 resets The reset control logic holds reset asserted internally until the external RESET is released When the reset control logic detects that external RESET is no longer being driven it drives both internal and external reset low for an additional 512 cycles to guarantee this length of reset to the entire system Figure 3 27 shows the RESET timing
109. compare mode when a read of the register is not in progress This read only register can be read when the timer module is enabled i e the STP bit in the MCR is cleared CNTR 60A 64A Supervisor User 24 bits of the prescaler and the counter may be obtained by one long word read at the address of the SR since the CNTR is contiguous to it Any changes in the prescaler value due to the two cycles necessary to perform a long word read should be considered If this latency presents a problem the TGATE signal may be used to disable the decrement function while the reads are occurring 8 4 6 Preload 1 Register PREL1 The PREL1 stores a value that is loaded into the counter in some modes of operation This value is loaded into the counter on the first falling edge of the counter clock after the counter is enabled This register can be be read and written when the timer module is enabled i e the STP bit in the MCR is cleared However a write to this register must be completed before timeout for the new value to be reliably loaded into the counter MOTOROLA MC68340 USER S MANUAL 8 25 PREL1 60C 64C Supervisor User For some modes of operation this register is also used to reload the counter one falling clock edge after a timeout occurs Refer to 8 3 Operating Modes for more information on the individual modes 8 4 7 Preload 2 Register PREL2 PREL2 is used in addition to PREL1 in the variable duty cycle square wav
110. control like device to provide a multimedia experience selected from software titles contained in compressed form on standard compact discs The highly integrated MC68340 is ideal as the central processor for CD I players It provides the M68000 microprocessor code compatibility and DMA functions required by the CD Green Book specification as well as many other useful on chip functions for a very cost effective solution The extra demands of full motion video CD I systems make the best use of the MC68340 high performance The MC68340 is CD I compliant and has been CD I qualified With its low voltage operation the MC68340V is the only practical choice for portable CD I MOTOROLA MC68340 USER S MANUAL 1 9 1 7 MORE INFORMATION The following table lists available documentation related to the MC68340 1 10 MC68340 USER S MANUAL MOTOROLA SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2 1 A3IJPORT AT IACK gt d d E Y A30 PORT 6 6 lt gt m 29 A29 PORT AS IACKS gt A28 PORT A4 IACK4 7 PORTA A27 PORT gt A26 PORT A2 IACK2 lt gt A25 PORT gt g 8 lt RxDA A2AIPORT lt gt Pee TxDA CPU32 TWO CHANNEL 2 CTSA CORE SERIAL RxDB 0 TxDB lt TSB TxRDYA OP6 EXTERNAL OUTPUT RxRDYA FFULLA OP4
111. creto a dace 3 46 3 27 Timing for External Devices Driving RESET 3 47 3 28 Power Up Reset Timing Diagram sss 3 48 4 1 SIM40 Module Register 4 3 4 2 System Configuration and Protection Function 4 5 4 3 Software Watchdog Block Diagram seen 4 7 4 4 Clock Block Diagram for Crystal Operation 4 10 MOTOROLA MC68340 USER S MANUAL xvii 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 4 5 MC68340 Crystal Oscillator essere 4 10 4 6 Clock Block Diagram for External Oscillator Operation 4 11 4 7 Full Interrupt Request Multiplexer eene 4 16 4 8 SIM40 Programming coo epe eite sue i elo te ait on tes 4 19 5 1 CGRUSZ BIOGK tu dct ae usen coc 5 3 5 2 Loop Mode Instruction Sequence seen 5 3 5 3 User Programming Modell cccsceccsceseeececeeeeeceateeeeceaeeeeseeseeesseeseeeseeeseeeseanseees 5 9 5 4 Supervisor Programming Model 5 9 5 5 status Registeren emia ere ott
112. debugger to trace single bus cycles single instructions or changes in program flow When the MC68340 completes a bus cycle with HALT asserted D15 DO is placed in the high impedance state and bus control signals are negated not high impedance state the 1 0 SIZx and R W signals remain in the same state The halt operation has no effect on bus arbitration see 3 6 Bus Arbitration When bus arbitration occurs while the MC68340 is halted the address and control signals are also placed in the high impedance state Once bus mastership is returned to the MC68340 if HALT is still 3 38 MC68340 USER S MANUAL MOTOROLA asserted the 1 0 SIZx and R W signals again driven to their previous states The MC68340 does not service interrupt requests while it is halted S0 52 54 50 52 54 50 YT T tf Wes DSACKx VRE HALT lt READ gt lt HALT gt lt READ gt ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED Figure 3 21 HALT Timing 3 5 4 Double Bus Fault A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following previous bus error A previous address error Areset For example the MC68340 attempts to stack several words containing information about the state of the machine while processing a bus error exception If a bus error exception MOT
113. edge of reset PITR7 PITRO Periodic Interrupt Timer Register Bits 7 0 The remaining bits of the PITR contain the count value for the periodic timer A zero value turns off the periodic timer MOTOROLA MC68340 USER S MANUAL 4 27 4 3 2 8 SOFTWARE SERVICE REGISTER SWSR The SWSR is the location to which the software watchdog servicing sequence is written The software watchdog can be enabled or disabled by the SWE bit in the SYPCR SWSR can be written at any time but returns all zeros when read SWSR 027 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Supervisor Only 4 3 3 Clock Synthesizer Control Register SYNCR The SYNCR can be read or written only in supervisor mode The reset state of SYNCR produces an operating frequency of 8 39 MHz when the PLL is referenced to a 32 768 kHz reference signal The system frequency is controlled by the frequency control bits in the upper byte of the SYNCR as follows Fsystem FcnvsrAL 2 9 W 99 x 1 SYNCR 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 De Ps Dw se Ts Teo ssw sree B 0 1 1 1 1 1 1 0 0 0 U U 0 0 0 U Unaffected by reset Supervisor Only W Frequency Control Bit This bit controls the prescaler tap in the synthesizer feedback loop Setting the bit increases the VCO speed by a factor of 4 requiring a time delay for the VCO to relock see equation for determining system frequency X Frequency Control Bit This bit controls a divide by two pre
114. every possible circumstance This approach is used because exact execution time for an instruction or operation depends on concurrence of independently scheduled resources on memory speeds and on other variables An assembly language programmer or compiler writer can use the information in this section to predict the performance of the CPUS2 Additionally timing for exception processing is included so that designers of multitasking or real time systems can predict task switch overhead maximum interrupt latency and similar timing parameters Instruction timing is given in clock cycles to eliminate clock frequency dependency 5 7 1 Resource Scheduling The CPU32 contains several independently scheduled resources The organization of these resources within the CPUS2 is shown in Figure 5 30 Some variation in instruction execution timing results from concurrent resource utilization Because resource scheduling is not directly related to instruction boundaries it is impossible to make an accurate prediction of the time required to complete an instruction without knowing the entire context within which the instruction is executing 5 7 1 1 MICROSEQUENCER The microsequencer either executes microinstructions or awaits completion of accesses necessary to continue microcode execution The microsequencer supervises the bus controller instruction execution and internal processor operations such as calculation of EA and setting of condition codes It als
115. falling edge of the clock The assertion of IPIPE for a single cycle after one or more cycles of negation indicates use of the data in IRB advance of IRA into IRB Assertion for two clock cycles indicates that a new instruction has started IRB IRC and IRA IRB transfers have occurred Loading IRC always indicates that an instruction is beginning execution the opcode is loaded into IRC by the transfer In some cases instructions using immediate addressing begin executing and initiate a second pipeline advance simultaneously at the same time IPIPE will not be negated between the two indications which implies the need for a state machine to track the state of IPIPE The state machine can be resynchronized during periods of inactivity on the signal 5 6 3 3 OPCODE TRACKING DURING LOOP MODE IPIPE and IFETCH continue to work normally during loop mode IFETCH indicates all instruction fetches up through the point that data begins recirculating within the instruction pipeline IPIPE continues to signal the start of instructions and the use of extension words even though data is being recirculated internally IFETCH returns to normal operation with the first fetch after exiting loop mode 5 88 MC68340 USER S MANUAL MOTOROLA 5 7 INSTRUCTION EXECUTION TIMING This section describes the instruction execution timing of the CPU32 External clock cycles are used to provide accurate execution and operation timing guidelines but not exact timing for
116. follows the regular sequence Vector number 12 offset 30 is internally generated The PC of the currently executing instruction the PC of the next instruction to execute and a copy of the SR are saved on the supervisor stack 5 5 2 7 FORMAT ERROR The processor checks certain data values for control operations The validity of the stack format code and in the case of a bus cycle fault format the version number of the processor that generated the frame are checked during execution of the RTE instruction This check ensures that the program does not make erroneous assumptions about information in the stack frame If the format of the control data is improper the processor generates a format error exception This exception saves a four word format exception frame and then vectors through vector table entry number 14 The stacked PC is the address of the RTE instruction that discovered the format error 5 5 2 8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal 32 instruction if it is MOVEC instruction that contains an undefined register specification field in the first extension word or if it contains an indexed addressing mode extension word with bits 5 4 00 or bits 3 0 0000 If an illegal instruction is fetched during instruction execution an illegal instruction exception occurs This facility allows the
117. generated bus error The exception processing sequence is the same as that for bus error except that the vector number refers to the address error exception vector Address error exception processing begins when the processor attempts to use information from the aborted bus cycle If the aborted cycle is a data space access exception processing begins when the processor attempts to use the data except in the MOTOROLA MC68340 USER S MANUAL 5 45 case of a released operand write Released write exceptions are delayed until the next instruction boundary or attempted operand access An address exception on a branch to an odd address is delayed until the PC is changed No exception occurs if the branch is not taken In this case the fault address and return PC value placed in the exception stack frame are the odd address and the current instruction PC points to the instruction that caused the exception If an address error occurs during exception processing for a bus error another address error or a reset the processor halts 5 5 2 4 INSTRUCTION TRAPS Traps are exceptions caused by instructions They arise from either processor recognition of abnormal conditions during instruction execution or from use of specific trapping instructions Traps are generally used to handle abnormal conditions that arise in control routines The TRAP instruction which always forces an exception is useful for implementing system calls for user programs
118. holding register FIFO stack provided the received A D bit is a one address tag The character is discarded if the received A D bit is a zero data tag If the receiver is enabled all received characters are transferred to the CPU32 via the receiver holding register stack during read operations In either case the data bits are loaded into the data portion of the stack while the A D bit is loaded into the status portion of the stack normally used for a parity error SR bit 5 Framing error overrun error and break detection operate normally The A D bit takes the place of the parity bit therefore parity is neither calculated nor checked Messages in this mode may still contain error detection and correction information One way to provide error detection if 8 bit characters are not required is to use software to calculate parity and append it to the 5 6 or 7 bit character 7 3 5 Bus Operation This section describes the operation of the IMB during read write and interrupt acknowledge cycles to the serial module All serial module registers must be accessed as bytes 7 3 5 1 READ CYCLES The serial module is accessed by the CPU32 with no wait states The serial module responds to byte reads Reserved registers return logic zero during reads 7 3 5 2 WRITE CYCLES The serial module is accessed by the CPU32 with no wait states The serial module responds to byte writes Write cycles to read only registers and reserved registers compl
119. in the case of released operand writes Released write bus errors are delayed until the next instruction boundary or until another operand access is attempted Exception processing for bus error exceptions follows the regular sequence but context preservation is more involved than for other exceptions because a bus exception can be initiated while an instruction is executing Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault First any register altered by a faulted instruction EA calculation is restored to its initial value Then a special status word SSW is placed on the stack The SSW contains specific information about the aborted access size type of access read or write bus cycle type and function code Finally fault address bus error exception vector number PC value and a copy of the SR are saved If a bus error occurs during exception processing for a bus error an address error a reset or while the processor is loading stack information during RTE execution the processor halts This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory Only assertion of RESET can restart a halted processor 5 5 2 3 ADDRESS ERROR Address error exceptions occur when the processor attempts to access an instruction word operand or long word operand at an odd address The effect is much the same as an internally
120. information refer to 7 4 Register Description and Programming 7 8 MC68340 USER S MANUAL MOTOROLA CHANNEL A EXTERNAL INTERFACE COMMAND REGISTER CRA MODE REGISTER A MR1A MODE REGISTER B MR2A STATUS REGISTER SRA TRANSMIT BUFFER TBA TRANSMIT HOLDING REGISTER 2 REGISTERS TRANSMIT SHIFT REGISTER RECEIVER HOLDING REGISTER 1 RECEIVER HOLDING REGISTER 2 RECEIVER HOLDING REGISTER 3 RECEIVE RxDA BUFFER RBA RECEIVER SHIFT REGISTER 4 REGISTERS CHANNEL B COMMAND REGISTER CRB MODE REGISTER 1 MR1B MODE REGISTER 2 MR2B STATUS REGISTER SRB TRANSMIT TRANSMIT HOLDING REGISTER BUFFER TBB TxDB 2 REGISTERS TRANSMIT SHIFT REGISTER RECEIVER HOLDING REGISTER 1 RECEIVER HOLDING REGISTER 2 RECEIVER HOLDING REGISTER 3 RECEIVE RECEIVER SHIFT REGISTER BUFFER RBB 4 REGISTERS NOTE R W READ WRITE R READ W WRITE Figure 7 4 Transmitter and Receiver Functional Diagram MOTOROLA MC68340 USER S MANUAL 7 3 2 1 TRANSMITTER The transmitters are enabled through their respective command registers CR located within the serial module The serial module signals the CPUS2 when it is ready to accept a character by setting the transmitter ready bit TXRDY in the channel s status register SR Functional timing information for the transmitter is shown in Figure 7 5 The transmitter converts parallel data from the CPUS2 to a serial bit stream on TxDx It automatically sends a start bit followed by the prog
121. interrupt command clears the delta break DBx bits in the ISR 7 28 MC68340 USER S MANUAL MOTOROLA Start Break The start break command forces the channel s TxDx low If the transmitter is empty the start of the break conditions can be delayed up to one bit time If the transmitter is active the break begins when transmission of the character is complete If a character is in the transmitter shift register the start of the break is delayed until the character is transmitted If the transmitter holding register has a character that character is transmitted after the break The transmitter must be enabled for this command to be accepted The state of the CTS input is ignored for this command Stop Break The stop break command causes the channel s TxDx to go high mark within two bit times Characters stored in the transmitter buffer if any are transmitted Assert RTS The assert RTS command forces the channel s RTS output low Negate RTS The negate RTS command forces the channel s RTS output high TC1 TCO Transmitter Commands These bits select a single command as listed in Table 7 7 Table 7 7 TCx Control Bits Teo No Action Taken Disable Transmitter Do Not Use No Action Taken The no action taken command causes the transmitter to stay in its current mode If the transmitter is enabled it remains enabled if disabled it remains disabled Ls Erene Teremto EAEE Transmitter Enable The
122. is given by the following formula divide count EXTAL frequency The software watchdog timeout period listed in Table 4 7 gives the formula to derive the software watchdog timeout for any clock frequency The timeout periods are listed for a 32 768 kHz crystal used with the VCO and for a 16 777 MHz external oscillator Table 4 7 Deriving Software Watchdog Timeout 211 EXTAL Input Frequency 213 EXTAL Input Frequency 215 EXTAL Input Frequency NOTE When the SWP and SWT bits are modified to select a software timeout other than the default the software service sequence 55 followed by AA written to the software service register must be performed before the new timeout period takes effect Refer to 4 2 2 5 Software Watchdog for more information DBFE Double Bus Fault Monitor Enable 1 Enable double bus fault monitor function 0 Disable double bus fault monitor function For more information see 4 2 2 3 Double Bus Fault Monitor and Section 5 CPU32 Monitor External Enable 1 Enable bus monitor function for an internal to external bus cycle 0 Disable bus monitor function for an internal to external bus cycle For more information see 4 2 2 2 Internal Bus Monitor BMT1 BMTO Bus Monitor Timing These bits select the timeout period for the bus monitor see Table 4 8 Upon reset the bus monitor is set to 64 system clocks MOTOROLA MC68340 USER S MANUAL 4 25 Table 4 8 BMTx Encoding BMT1 B
123. is entered via a double bus fault immediately out of reset CPU32 ACTIVITY DEVELOPMENT SYSTEM ACTIVITY ENTER BDM ASSERT FREEZE SIGNAL WAIT FOR COMMAND SEND INITIAL COMMAND LOAD COMMAND REGISTER ENABLE SHIFT CLOCK SHIFT OUT 17 BITS DISABLE SHIFT CLOCK EXECUTE COMMAND LOAD NOT READY RESPONSE PERFORM COMMAND STORE RESULTS READ RESULTS NEW COMMAND LOAD COMMAND REGISTER ENABLE SHIFT CLOCK SHIFT IN OUT 17 BITS DISABLE SHIFT CLOCK READ RESULT REGISTER IF RESULTS YES NOT READY CONTINUE Figure 5 21 BDM Command Execution Flowchart 5 6 2 6 RETURNING FROM BDM BDM is terminated when a resume execution GO or call user code CALL command is received Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the RPC The return PC and the memory space referred to by the SR SUPV bit reflect any changes made during BDM FREEZE is negated prior to initiating the first prefetch Upon negation of FREEZE the serial subsystem is disabled and the signals revert to IPIPE and IFETCH functionality 5 6 2 7 SERIAL INTERFACE Communication with the CPU32 during BDM occurs via a dedicated serial interface which shares pins with other development features The BKPT signal becomes the DSCLK DSI is received on IFETCH and DSO is transmitted on IPIPE 5 68 MC68340 USER S MANUAL MOTOROLA The serial interface uses a full duplex synchr
124. is important to be aware of the difference between exception processing mode and execution of an exception handler Each exception has an assigned vector that points to an associated handler routine Exception processing includes steps described in 5 5 1 2 Exception Processing Sequence but does not include execution of handler routines which is done in normal mode MOTOROLA MC68340 USER S MANUAL 5 41 When the CPUS32 completes exception processing it is ready to begin either exception processing for a pending exception or execution of a handler routine Priority assignment governs the order in which exception processing occurs not the order in which exception handlers are executed Table 5 17 Exception Priority Groups Group Exception and Characteristics Priority Relative Priority Reset Aborts all processing instruction or exception does not save old context Address Error Suspends processing instruction or Bus Error exception saves internal context 2 BKPT n CHK2 Exception processing is a part of Division by Zero RTE instruction execution TRAP n TRAPcc TRAPV Trace Exception processing begins when current Hardware Breakpoint instruction or previous exception 4 3 Interrupt processing is complete 1 1 1 2 3 Illegal Instruction Line A Exception processing begins before Unimplemented Line F instruction execution Privilege Violation 4 1 4 2 As a general rule when simultaneous exceptions occur the hand
125. is reloaded into the bus controller if the RR bit is set during unstacking 0 Faulted cycle was an operand write 1 Faulted cycle was a prefetch or operand read The LG bit indicates an original operand size of long word LG is cleared if the original operand was a byte or word SIZ will indicate original and remaining size LG is set if the original was a long word SIZ will indicate the remaining size at the time of fault LG is ignored during unstacking 0 Original operand size was byte or word 1 Original operand size was long word The SSW SIZ field shows operand size remaining when a fault was detected This field does not indicate the initial size of the operand nor does it necessarily indicate the proper status of a dynamically sized bus cycle Dynamic sizing occurs on the external bus and is transparent to the CPU Byte size is shown only when the original operand was a byte The field is reloaded into the bus controller if the RR bit is set during unstacking The SIZ field is encoded as follows 00 Long word 01 Byte 10 Word 11 Unused reserved The function code for the faulted cycle is stacked in the FUNC field of the SSW which is a copy of FC2 FCO for the faulted bus cycle This field is reloaded into the bus controller if the RR bit is set during unstacking All unused bits are stacked as zeros and are ignored during unstacking Further discussion of the SSW is included in 5 5 3 1 Types of Faults 5 5 3 1
126. la cta reste tata cuta tSc cee ta e ae EE 8 22 8 5 MODEX COIN ee doeet du da Bad tae diei 8 22 8 6 dni o ere CH EN LE 8 22 9 1 Boundary Scan Control Bits 9 4 9 2 Boundary Scan Bit Definitions esssssssseeeeenernes 9 5 9 3 HR IPC DC PEE 9 10 10 1 Memory Access Times at 16 78 2 2 2 10 7 10 Typical Electrical Characteristics essen 10 13 MOTOROLA MC68340 USER S MANUAL xxiii SECTION 1 OVERVIEW UM Rev 1 LIST OF TABLES Continued SECTION 1 DEVICE OVERVIEW The MC68340 is a high performance 32 bit integrated processor with direct memory access DMA combining an enhanced M68000 compatible processor 32 bit DMA and other peripheral subsystems on a single integrated circuit The MC68340 CPU32 delivers 32 bit CISC processor performance from a lower cost 16 bit memory system The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor based systems including embedded control and general computing Systems requiring very high speed block transfers of data can especially benefit from the MC68340 The MC68340 s high level of functional integration results in significant reductions in component count power consumption board space and cost while yielding much higher system reliability and
127. no count the register is not incremented after the operand transfer The SAR and DAR are incremented if a bus error terminates the transfer Therefore either the SAR or the DAR contain the next address after the one that caused the bus error The BTC must be loaded with the number of byte transfers that are to occur This register is decremented by 1 2 or 4 at the end of each transfer The FCR must be loaded with the source and destination function codes Although these function codes may not be used in the address decode for the memory or peripheral they are provided if needed The CSR must be cleared for channel startup Once the channel has been initialized it is started by writing a one to the STR bit in the CCR Programming the channel for internal request causes the channel to request the bus and start transferring data immediately If the channel is programmed for external request DREQ must be asserted before the channel requests the bus The DREQ lt input is ignored until the channel is started since the channel does not recognize transfer requests until it is active If any fields in the CCR are modified while the channel is active that change is effective immediately To avoid any problems with changing the setup for the DMA channel a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle 6 6 2 Data Transfers Each operand transfer requires from one to five bus cycles
128. of 15 ns when the chip enable E input is low If buffers are required to reduce signal loading or if slower and less expensive memories are desired a three clock cycle can be used In the circuit shown in Figure 10 5 additional memories can be used provided the MC68340 specification for MOTOROLA MC68340 USER S MANUAL 10 3 load capacitance on the chip select CS signal is not exceeded Address buffers may be needed however 10 1 4 ROM Interface Using the programmable chip selects creates a very straightforward ROM interface As shown in Figure 10 6 no external circuitry is needed Care must be used however not to overload the address bus Address buffers may be required to ensure that the total system input capacitance on the address signals does not exceed the CL specification MC68340 16 1 D15 D0 CS0 Figure 10 6 ROM Interface 10 1 5 Serial Interface The necessary circuitry to create an RS 232 interface with the MC68340 includes an external crystal and an RS 232 receiver driver see Figure 10 7 The resistor and capacitor values shown are typical the crystal manufacturer s documentation should be consulted for specific recommendations on external component values The circuit shown does not include modem support ready to send RTS and clear to send CTS are not shown however these signals can be connected to the receiver driver and to the connector in a similar manner as the connections for
129. of TBLSN in surface interpolation 5 3 4 1 TABLE EXAMPLE 1 STANDARD USAGE The table consists of 257 word entries As shown in Figure 5 7 the function is linear within the range 32768 lt X lt 49152 Table entries within this range are as given in Table 5 13 Table 5 13 Standard Usage Entries These values are the end points of the range All entries between these points fall on the line DEPENDENT VARIABLE 16384 32168 49152 65536 INDEPENDENT VARIABLE Figure 5 7 Table Example 1 5 30 MC68340 USER S MANUAL MOTOROLA The table instruction is executed with the following bit pattern in Dx 31 16 15 0 USED 1 0 1 0 0 O 1 110000000 Table Entry Offset Dx 8 15 A3 163 Interpolation Fraction Dx 0 7 80 128 Using this information the table instruction calculates dependent variable Y Y 1669 128 1679 1669 256 1674 5 3 4 2 TABLE EXAMPLE 2 COMPRESSED TABLE In Example 2 see Figure 5 8 the data from Example 1 has been compressed by limiting the maximum value of the independent variable Instead of the range 0 lt X 65535 X is limited to 0 lt X lt 1023 The table has been compressed to only five entries but up to 256 levels of interpolation are allowed between entries DEPENDENT VARIABLE 256 512 786 1024 X INDEPENDENT VARIABLE Figure 5 8 Table Example 2 NOTE Extreme table compression with many levels of interpolation is possible only wi
130. of special instructions or a double bus fault Background processing allows interactive debugging of the system via a simple serial interface Refer to 5 4 Processing States for details 5 1 9 Privilege States The processor operates at one of two levels of privilege supervisor or user The supervisor level has higher privileges than the user level Not all instructions are permitted to execute in the lower privileged user level but all instructions are available at the supervisor level This scheme allows the supervisor to protect system resources from uncontrolled access The processor uses the privilege level indicated by the S bit in the SR to select either the user or supervisor privilege level and either the user stack pointer USP or SSP for stack operations MOTOROLA MC68340 USER S MANUAL 57 5 2 ARCHITECTURE SUMMARY The CPU32 is upward source and object code compatible with the MC68000 and MC68010 It is downward source and object code compatible with the MC68020 Within the M68000 family architectural differences are limited to the supervisory operating state User state programs can be executed unchanged on upward compatible devices The major CPU32 features are as follows e 32 Bit Internal Data Path and Arithmetic Hardware 32 Bit Address Bus Supported by 32 Bit Calculations Rich Instruction Set Eight 32 Bit General Purpose Data Registers Seven 32 Bit General Purpose Address Registers Separate User and Supervisor S
131. only the data cycles associated with the instruction and suppresses all instruction fetches The termination MOTOROLA MC68340 USER S MANUAL 53 condition and count are checked after each execution of the data operations of the looped instruction The CPU32 automatically exits the loop mode on interrupts or other exceptions 5 1 4 Vector Base Register The vector base register VBR contains the base address of the 1024 byte exception vector table which consists of 256 exception vectors Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing These routines perform a series of operations appropriate for the corresponding exceptions Because the exception vectors contain memory addresses each consists of one long word except for the reset vector The reset vector consists of two long words the address used to initialize the supervisor stack pointer SSP and the address used to initialize the PC The address of an interrupt exception vector is derived from an 8 bit vector number and the VBR The vector numbers for some exceptions are obtained from an external device other numbers are supplied automatically by the processor The processor multiplies the vector number by 4 to calculate the vector offset which is added to the VBR The sum is the memory address of the vector All exception vectors are located in supervisor data space except the reset vector which is located in su
132. operating system to detect program errors or to emulate instructions in software Word patterns with bits 15 12 1010 referred to as A line opcodes are unimplemented instructions A separate exception vector vector 10 offset 28 is given to unimplemented instructions to permit efficient emulation Word patterns with bits 15 12 1111 referred to as F line opcodes are used for M68000 family instruction set extensions They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word A separate F line emulation vector vector 11 offset 2C is used for the exception vector MOTOROLA MC68340 USER S MANUAL 5 47 All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture Opcode pattern 4AFC is defined to be illegal on all M68000 family members Those customers requiring the use of an unimplemented opcode for synthesis of custom instructions operating system calls etc should use this opcode Exception processing for illegal and unimplemented instructions is similar to that for traps The instruction is fetched and decoding is attempted When the processor determines that execution of an illegal instruction is being attempted exception processing begins No registers are altered Exception processing follows the regular sequence The vector number is generated to refer to th
133. register contains the count for the next access that would have been run had the error not occurred 6 8 DATA PACKING The internal DHR is a 32 bit register that can serve as a buffer register for the data being transferred during dual address DMA cycles No address is specified since this register can not be addressed by the programmer The DHR allows the data to be packed and unpacked by the DMA during the dual address transfer For example if the source operand size is byte and the destination operand size is word then two byte read cycles occur followed by a one word write cycle see Figure 6 16 The two bytes of data are buffered in the DHR until the destination write word cycle occurs The DHR allows for packing and unpacking of operands for the following sizes bytes to words bytes to long words words to long words words to bytes long words to bytes and long words to words SOURCE DESTINATION DESTINATION SOURCE BYTEO lt gt BYTEO 1 BYTE1 BYTEO BYTE1 0 1 2 2 BYTEO BYTE1 lt BYTEO 1 2 2 Figure 6 16 Packing and Unpacking of Operands MOTOROLA MC68340 USER S MANUAL 6 35 For normal transfers aligned with the size and address only two bus cycles are required for each transfer a read from
134. register is specified by the register field see Table 5 24 Table 5 24 Register Field for RSREG and WSREG System Register Select Code Return Program Counter RPC 0000 Current Instruction Program Counter PCC 0001 Destination Function Code Register DFC 5 6 2 8 7 Write System Register WSREG Operand data is written into the specified system control register All registers that can be written in supervisor mode can be written in BDM Several internal temporary registers are also accessible Status Register SR Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 resister Command Sequence WSREG 2 MS DATA gt L5 DATA NEXT CMD NOT READY NOT READY COMPLETE NEXT CMD ILLEGAL NOT READY Operand Data The data to be written into the register is always supplied as a 32 bit long word If the register is less than 32 bits the least significant word is used Result Data Command complete status is returned when register write is complete 5 78 MC68340 USER S MANUAL MOTOROLA Register Field The system control register is specified by the register field see Table 5 24 The FAR is a read only register any write to it is ignored 5 6 2 8 8 Read Memory Location READ Read the sized data at the memory location specified by the long word address Only absolute addressing is supported The SFC register determines the addre
135. reliable indication of a breakpoint CPU32 breakpoint support is provided by extending the function of a set of illegal instructions 4848 484F When a breakpoint instruction is executed the CPU32 performs a read from CPU space 0 at a location corresponding to the breakpoint number If this bus cycle is terminated by BERR the processor performs illegal instruction exception processing If the bus cycle is terminated by 5 the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction See Section 3 Bus Operation for a description of CPU space operations 5 46 MC68340 USER S MANUAL MOTOROLA 5 5 2 6 HARDWARE BREAKPOINTS The CPU32 recognizes hardware breakpoint requests Hardware breakpoint requests do not force immediate exception processing but are left pending An instruction breakpoint is not made pending until the instruction corresponding to the request is executed A pending breakpoint can be acknowledged between instructions or at the end of exception processing To acknowledge a breakpoint the CPU performs a read from CPU space 0 at location 1E see Section 3 Bus Operation If the bus cycle terminates normally instruction execution continues with the next instruction as if no breakpoint request occurred If the bus cycle is terminated by BERR the CPU begins exception processing Data returned during this bus cycle is ignored Exception processing
136. serve as breakpoint instructions See 5 5 2 5 Software Breakpoints for more information Unimplemented Instruction Emulation When an attempt is made to execute an illegal instruction an illegal instruction exception occurs Unimplemented instructions F line A line utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software See 5 5 2 8 Illegal or Unimplemented Instructions for more information 5 6 1 CPU32 Integrated Development Support In addition to standard MC68000 family capabilities the CPU32 has features to support advanced integrated system development These features include background debug mode deterministic opcode tracking hardware breakpoints and internal visibility in a single chip environment MOTOROLA MC68340 USER S MANUAL 5 63 5 6 1 1 BACKGROUND DEBUG BDM OVERVIEW Microprocessor systems generally provide a debugger implemented in software for system analysis at the lowest level The BDM on the CPU32 is unique because the debugger is implemented in CPU microcode BDM incorporates a full set of debug options registers can be viewed and or altered memory can be read or written and test features can be invoked A resident debugger simplifies implementation of an in circuit emulator In a common setup see Figure 5 18 emulator hardware replaces the target system processor A complex expensive pod and cable interface provides a communication path betwee
137. sess 3 14 Fast Termination Cycles essent 3 15 Data Transter y Clase ciet bc tto 3 16 3 16 MV AS VCS o de EI Eu 3 18 Read Modify Write 3 19 MC68340 USER S MANUAL 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Continued Paragraph Page Number Title Number 3 4 5 Cycle CR aa ee eee ee een eee er nner en 3 21 3 4 1 Breakpoint Acknowledge Cycle sss 3 22 3 4 2 LPSTOP 3 23 3 4 3 Module Base Address Register 3 27 3 4 4 Interrupt Acknowledge Bus 2 00 4 3 27 3 4 4 1 Interrupt Acknowledge Cycle Terminated Normally 3 27 3 4 4 2 Autovector Interrupt Acknowledge Cycle 3 29 3 4 4 3 Spurious Interrupt Cyele i 3 30 3 5 Bus Exception Control Cycles eese 3 32 3 5 1 BUS EITOIS dei eae Od 3 34 3 5 2 Retry Operationerna teu 3 36 3 5 3 tutte 3 38 3 5 4 Double Bus 3 39 3
138. shorter design time The 3 3 V MC68340V is particularly attractive to applications requiring a very tight power budget Complete code compatibility with the MC68000 and MC68010 affords the designer access to a broad base of established real time kernels operating systems languages applications and development tools many oriented towards embedded control SYSTEM INTEGRATION MODULE SIM40 CPU32 68020 BASED SYSTEM PROCESSOR PROTECTION CHIP SELECTS AND WAIT STATES CLOCK SYNTHESIZER INTERMODULE BUS EXTERNAL BUS INTERFACE BUS ARBITRATION TWO CHANNEL DMA TIMER TIMER CONTROLLER IEEE TEST Figure 1 1 Block Diagram MOTOROLA MC68340 USER S MANUAL 1 1 The primary features of the MC68340 illustrated in Figure 1 1 are as follows High Functional Integration on a Single Piece of Silicon CPU32 MC68020 Derived 32 Bit Central Processor Unit Upward Object Code Compatible with MC68000 and MC68010 Additional MC68020 Instructions and Addressing Modes Unique Embedded Control Instructions Fast Two Clock Register Instructions 10 045 Dhrystones Two Channel Low Latency DMA Controller for High Speed Memory Transfers Single or Dual Address Transfers 32 Bit Addresses and Counters 8 16 and 32 Bit Data Transfers 50 Mbyte Sec Sustained Transfers 12 5 Mbyte Sec Memory to Memory Two Channel Universal Synchronous Asynchronous Recei
139. state is held low The STEXT and STSIM bits in the SYNCR control clock activity during LPSTOP Refer to 4 2 6 Low Power Stop for additional information Table 4 3 Clock Control Signals STSIM STEXT SIMCLK CLKOUT VCO NOTE SIMCLK runs the periodic interrupt RESET and synchronizers in LPSTOP mode 4 2 4 Chip Select Operation Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals The MC68340 integrates these functions on chip to provide the cost speed and reliability benefits of a higher level of integration The chip select function contains register pairs for each external chip select signal The pair consists of a base address register and an address mask register that define the characteristics of a single chip select The register pair provides flexibility for a wide variety of chip select functions MOTOROLA MC68340 USER S MANUAL 4 13 4 2 4 1 PROGRAMMABLE FEATURES The chip select function supports the following programmable features Four Programmable Chip Select Circuits All four chip select circuits are independently programmable from the same list of selectable features Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select The base address register selects the starting address for the address block in 256 byte increments The address mask reg
140. system clock The resulting system clock frequency must be within the limits specified for the device The frequency of the system clock is given by the following equation Fsystem FcnvsrAL 2 9 W99 x 1 The maximum VCO frequency limit must also be observed The VCO frequency is given by the following equation Fsystem 2 27 Since clearing the X bit causes the VCO to run at twice the system frequency the VCO upper frequency limit must be considered when programming the SYNCR Both the system clock and VCO frequency limits are given in Section 11 Electrical Characteristics Table 4 2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32 768 KHz 4 12 MC68340 USER S MANUAL MOTOROLA Table 4 2 System Frequencies from 32 768 kHz Reference weexee ene 3 Pon oem itera ze one omo i _ m une 79s 399 unn aem qd NOTE System frequencies are in KHz 4 2 3 3 CLOCK CONTROL The clock control circuits determine the source used for both internal and external clocks during special circumstances such as low power stop LPSTOP execution Table 4 3 summarizes the clock activity during LPSTOP in crystal mode operation Any clock in the off
141. the CPU32 performs a word read from CPU space type 0 at an address corresponding to all ones on 4 2 BKPT 7 and the T bit A1 is set If this bus cycle is terminated by BERH the MC68340 performs hardware breakpoint exception processing If this bus cycle is terminated by DSACK the MC68340 ignores data on the data bus and continues execution of the next instruction NOTE The BKPT pin is sampled on the same clock phase as data and is latched with data as it enters the CPU32 pipeline If BKPT is asserted for only one bus cycle and a pipeline flush occurs before BKPT is detected by the CPU32 is ignored To ensure detection of BKPT by the CPU32 BKPT can be asserted until a breakpoint acknowledge cycle is recognized The breakpoint operation flowchart is shown in Figure 3 11 Figures 3 12 and 3 13 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled respectively 3 22 MC68340 USER S MANUAL MOTOROLA 3 4 2 LPSTOP Broadcast Cycle The low power stop LPSTOP broadcast cycle is generated by the CPU32 executing the LPSTOP instruction Since the external bus interface must get a copy of the interrupt mask level from the CPU32 the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus as shown in the following figure The CPU space type 3 cycle waits for the bus to be available and is shown externally to indicate
142. the FIFO to become full all three FIFO holding register positions are occupied 0 The CPU32 has read the receiver buffer and one or more FIFO positions available Note that if there is a character in the receiver shift register because the FIFO is full this character will be moved into the FIFO when a position is available and the FIFO will remain full RxRDY Receiver Ready 1 A character has been received and is waiting in the FIFO to be read by the CPU32 This bit is set when a character is transferred from the receiver shift register to the FIFO 0 The CPU32 has read the receiver buffer and no characters remain in the FIFO after this read MOTOROLA MC68340 USER S MANUAL 7 25 7 4 1 6 CLOCK SELECT REGISTER CSR The CSR selects the baud rate clock for the channel receiver and transmitter This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared NOTE This register should only be written after the external crystal is stable RDY bit of the ISR is zero CSRA CSRB 711 719 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User 5 50 Clock Select These bits select the baud rate clock for the channel receiver from a set of baud rates listed in Table 7 4 The baud rate set selected depends upon the auxiliary control register ACR bit 7 Set 1 is selected if ACR bit 7 0 and set 2 is selected if ACR bit 7 1
143. the ISR This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full 7 2 13 3 OP4 When used for this function this output is controlled by bit 4 in the OP MOTOROLA MC68340 USER S MANUAL 7 7 7 3 OPERATION The following paragraphs describe the operation of the baud rate generator transmitter and receiver and other functional operating modes of the serial module 7 3 1 Baud Rate Generator The baud rate generator consists of a crystal oscillator baud rate generator and clock selectors see Figure 7 3 The crystal oscillator operates directly from a 3 6864 MHz crystal or from an external clock of the same frequency The SCLK input bypasses the baud rate generator and provides a synchronous clock mode of operation when used as a divide by 1 clock and an asynchronous clock mode when used as a divide by 16 clock The clock is selected by programming the clock select register CSR for each channel BAUD RATE GENERATOR LOGIC CRYSTAL OSCILLATOR EXTERNAL INTERFACE X1 BAUD RATE GENERATOR CLOCK SELECTORS Figure 7 3 Baud Rate Generator Block Diagram X2 SCLK 7 3 2 Transmitter and Receiver Operating Modes The functional block diagram of the transmitter and receiver including command and operating registers is shown in Figure 7 4 The paragraphs that follow contain descriptions for both these functions in reference to this diagram For detailed register
144. the address on the address bus This register can be programmed to increment CCR SAPI bit set or remain constant CCR SAPI bit cleared after each operand transfer The register is incremented using unsigned arithmetic and will roll over if overflow occurs For example if the register contains FFFFFFFF and is incremented by 1 it will roll over to 00000000 This register is incremented by 1 2 or 4 depending on the size of the operand and the memory starting address If the operand size is byte then the register is always incremented by 1 If the operand size is word and the starting address is even word aligned then the register is incremented by 2 If the operand size is long word and the address is even word aligned then the register is incremented by 4 The SAR value must be aligned to an even word boundary if the transfer size is word or long word otherwise the CSR CONF bit is set and the transfer does not occur When read this register always contains the next source address If a bus error terminates the transfer this register contains the next source address that would have been run had the error not occurred 6 7 7 Destination Address Register DAR The DAR is a 32 bit register that contains the address of the destination operand used by the DMA to write to memory or peripheral registers This register is accessible in either supervisor or user space The DAR can always be read or written to when the DMA module is enabled
145. the base address register and FCM bits in the address mask register are used to select address spaces for which the chip selects will be asserted 4 2 4 2 GLOBAL CHIP SELECT OPERATION Global chip select operation allows address decode for a boot ROM before system initialization occurs 50 is the global chip select output and its operation differs from the other external chip select outputs following reset When the CPU32 begins fetching after reset CSO is asserted for every address until the V bit is set in the CSO base address register 4 14 MC68340 USER S MANUAL MOTOROLA If an access matches multiple chip selects the lowest numbered chip select will have priority For example if CSO and CS2 overlap for a certain range CSO will assert when accessing the overlapped address range and CS2 will not Global chip select provides a 16 bit port with three wait states which allows a boot ROM to be located in any address space and still provide the stack pointer and program counter values at 00000000 and 00000004 respectively Global chip select does not provide write protection and responds to all function codes While CSO is a global chip select no other chip select CS1 CS2 CS3 be used 50 operates in this manner until the V bit is set in the CSO base address register which will then allow the use of CS3 CS1 Provided the desired address range is first loaded into the CSO base address register 50 can be progr
146. the counter is enabled and begins counting down 0 The counter is not enabled and does not begin counting down OUT Output Level 1 TOUTx is a logic one 0 TOUTx is a logic zero or the pin is three stated COM Compare Bit This bit is used to indicate when the counter output value is at or between the value in the COM and 0000 timeout 8 24 MC68340 USER S MANUAL MOTOROLA 1 This bit is set when the counter output equals the value in the 0 This bit is cleared when a timeout occurs the COM register is accessed read or write the timer is reset with the SWR bit or the RESET signal is asserted on the IMB This bit is cleared regardless of the state of the TC bit This bit can be used to indicate when a write to the PREL1 or PREL2 registers will not cause a problem during a counter reload at timeout To ensure that the write to the PREL register is recognized at timeout the latency between the read of the COM bit and the write to the PREL register must be considered PO7 PO0 Prescaler Output These bits show the levels on each of the eight output taps of the prescaler These values are updated every time that the system clock goes high and a read cycle of this byte in the SR is not in progress 8 4 5 Counter Register CNTR The CNTR reflects the value of the counter This value can be reliably read at any time since it is updated on every rising edge of the system clock except in the input capture output
147. the manual please reference by the page number paragraph number figure number table number and line number if needed Reference the line number from the top of the page When we receive a FAX between the hours of 7 30 AM and 5 00 PM EST Monday through Friday we will respond within two hours If the FAX is received after 5 00 PM or on the weekend we will respond within two hours on the first working day following receipt of the FAX When sending a FAX please provide your name company FAX number and voice number including area code so we can talk to a real person if needed 11 2 95 SECTION 1 OVERVIEW UM Rev 1 TABLE OF CONTENTS Paragraph Page Number Title Number Section 1 Device Overview 1 1 M69300 F aFTlly se ia ea ox S dh ett rte 1 2 1 1 1 ON eet Ds 1 3 1 1 2 PROV ANAS Stabe sons 1 3 1 2 Central Processor ioo 1 3 1 2 1 re sse A 1 4 1 2 2 Background Debug Ce me E ed 1 4 1 3 On Chip Peripherals tte utes eto ip Eta 1 5 1 3 1 System Integration Module uc enc qu E ies 1 5 1 3 1 1 External Bus 1 5 1 3 1 2 System Configuration and
148. the operation in the channel status register 6 2 MC68340 USER S MANUAL MOTOROLA A g MEMORY M PERIPHERAL PERIPHERAL gt MEMORY Figure 6 2 Single Address Transfers MEMORY MEMORY d B Figure 6 3 Dual Address Transfer MOTOROLA MC68340 USER S MANUAL 6 3 6 2 MODULE SIGNAL DEFINITIONS This section contains a brief description of the DMA module signals used to provide handshake control for either a source or destination external device NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a signal is inactive or false 6 2 1 DMA Request DREQ This active low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory The assertion of DREQ starts the DMA process The assertion level in external burst mode is level sensitive in external cycle steal mode it is falling edge sensitive 6 2 2 DMA Acknowledge This active low output is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request 6 2 3 DMA Done DONE This active low bidirectional signal is asserted by the
149. the shift register to the parallel outputs during the update IR controller state The three bits are used to decode the four unique instructions listed in Table 9 3 The parallel output of the instruction register is reset to all ones in the test logic reset controller state Note that this preset state is equivalent to the BYPASS instruction Table 9 3 Instructions Fe 5 exe o o smereenecono Pepe b evens During the capture IR controller state the parallel inputs to the instruction shift register are loaded with the standard 2 bit binary value 01 into the two least significant bits and the loss of crystal LOC status signal into bit 2 The parallel outputs however remain unchanged by this action since an update IR signal is required to modify them The LOC status bit of the instruction register indicates whether an internal clock is detected when operating with a crystal clock source The LOC bit is clear when a clock is detected and set when it is not The LOC bit is always clear when an external clock is used The LOC bit can be used to detect faulty connectivity when a crystal is used to clock the device 9 4 1 EXTEST 000 The external test EXTEST instruction selects the 132 bit boundary scan register EXTEST asserts internal reset for the MC68340 system logic to force a predictable benign internal state while performing external boundary scan operations By using the TAP the register is
150. the source and a write to the destination 6 9 DMA CHANNEL INITIALIZATION SEQUENCE The following paragraphs describe DMA channel initialization and operation If the DMA capability of the MC68340 is being used the initialization steps should be performed during the part initialization sequence The mode operation steps should be performed to start a DMA transfer The DONEz pin requires an external pullup resistor even if operating only in the internal request mode 6 9 1 DMA Channel Configuration The following steps can be accomplished in any order when initializing the DMA channel These steps need to be performed for each channel used Module Configuration Register MCR Clear the stop bit STP for normal operation Only one STP bit exists for both channels Select whether to respond to or ignore FREEZE FRZx bits Only one set of FRZx bits exits for both channels If desired enable the external data bus operation in single address mode SE bit Program the interrupt service mask to set the level below which interrupts are ignored during a DMA transfer ISM bits The channel will begin operation when the level of the CPU32 12 10 bits is less than or equal to the level of the DMA ISM bits Select the access privilege for the supervisor user registers SUPV bit Program the master arbitration ID MAID to establish priority on the IMB between both DMA channels Note that the two DMA channels should have distinct MAI
151. the system and IEEE 1149 1 logic The purpose for applying POR to the IEEE 1149 1 circuitry is to avoid the possibility of bus contention during power on The time required to complete device power on is power supply dependent However the IEEE 1149 1 TAP controller remains in the test logic reset state while POR is asserted The TAP controller does not respond to user commands until POR is negated The MC68340 features a low power stop mode that uses a CPU instruction called LPSTOP The interaction of the IEEE 1149 1 interface with LPSTOP mode is as follows 1 Leaving the TAP controller test logic reset state negates the ability to achieve minimal power consumption but does not otherwise affect device functionality 2 The TCK input is not blocked in LPSTOP mode To consume minimal power the input should be externally connected to or ground 3 The TMS and TDI pins include on chip pullup resistors In LPSTOP mode these two pins should remain either unconnected or connected to Vcc to achieve minimal power consumption 9 6 NON IEEE 1149 1 OPERATION In non IEEE 1149 1 operation there are two constraints First the TCK input does not include an internal pullup resistor and should be pulled up externally to preclude mid level inputs The second constraint is to ensure that the IEEE 1149 1 test logic is kept transparent to the system logic by forcing the TAP controller into the test logic reset state using either of two method
152. the timer module except for the clock from the IMB The clock from the IMB remains active to allow the CPU32 access to the MCR The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPUS2 or a hardware reset Accesses to timer module registers while in stop mode produce a bus error The timer module should be disabled in a known state prior to setting the STP bit otherwise unpredictable results may occur The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption 0 The timer operates in normal mode FRZ1 FRZO Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPUS2 has entered background debug mode Table 8 2 lists the action taken for each bit combination Table 8 2 FRZx Control Bits rmm ACTION o o i Reseved FREEZE noe Execution Freeze Execution Freeze Bits 12 8 6 4 Reserved SUPV Supervisor User The value of this bit has no effect on registers permanently defined as supervisor only access 1 The timer registers defined as supervisor user reside in supervisor data space and are only accessible from supervisor programs 0 The timer registers defined as supervisor user reside in user data space and are accessible from either supervisor or user programs IARB3 IARBO Interrupt Arbitration Bits Ea
153. this document for both the 8 39 and 16 78 MHz 9 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part The 16 78 MHz specifications apply to the MC68340 9 5 0 V 5 operation c The 25 16 MHz 5 0 V 5 electrical specifications are preliminary d For extended temperature parts TA 40 to 85 C These specifications are preliminary 1 2 3 All AC timing is shown with respect to 0 8 V and 2 0 V levels unless otherwise noted This number can be reduced to 5 ns if strobes have equal loads If multiple chip selects are used the CS width negated 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select 4 These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast termination reads The user is free to use either hold time for fast termination reads 5 If the asynchronous setup time 47 requirements are satisfied the DSACK low to data setup time 31 and DSACK low to BERR low setup time 48 can be ignored The data must only satisfy the data in to CLKOUT low setup time 27 for the following clock cycle must only satisfy the late low to CLKOUT low setup time 27A for the following clock cycle 6 Toensure coherency during every operand transfer BG will not be asserted in response to BR until after cycles of the current operand transfer are compl
154. this happens the bus cycle is queued and the bus controller runs the cycle when the current cycle is complete MICROSEQUENCER AND CONTROL INSTRUCTION PIPELINE CONTROL STORE CONTROL LOGIC EXECUTION UNIT PROGRAM DATA COUNTER SEC LUN BUS SECTION WRITE P ENDING PREFETCH BUFFER CONTROLLER MICROBUS CONTROLLER ADDRESS BUS BUS CONTROL SIGNALS Figure 5 30 Block Diagram of Independent Resources 5 7 1 3 1 Prefetch Controller The instruction prefetch controller receives an initial request from the microsequencer to initiate prefetching at a given address Subsequent prefetches are initiated by the prefetch controller whenever a pipeline stage is invalidated either through instruction completion or through use of extension words Prefetch occurs as soon as the bus is free of operand accesses previously requested by the microsequencer Additional state information permits the controller to inhibit prefetch requests when a change in instruction flow e g a jump or branch instruction is anticipated In a typical program 10 to 25 percent of the instructions cause a change of flow Each time a change occurs the instruction pipeline must be flushed and refilled from the new instruction stream If instruction prefetches rather than operand accesses were given 5 90 MC68340 USER S MANUAL MOTOROLA priority many instruction words would be flushed unused and necessary operand cycles would
155. this table only Notaffected Sm U Undefined Dm 2 special definition Rm General case R X C Rm r Z RmaA A RO LB Boolean AND UB V Boolean OR Rm Source operand MSB Destination operand MSB Result operand MSB Register tested Bit Number Shift count Lower bound Upper bound NOT Rm 5 3 3 2 DATA MOVEMENT INSTRUCTIONS The MOVE instruction is the basic means of transferring and storing address and data MOVE instructions transfer byte word and long word operands from memory to memory memory to register register to memory and register to register Address movement instructions MOVE or MOVEA transfer word and long word operands and ensure that only valid address manipulations are executed In addition to the general MOVE instructions there are several special data movement instructions move multiple registers MOVEM move peripheral data MOVEP move quick MOVEQ exchange registers EXG load effective address LEA push effective address PEA link stack LINK and unlink stack UNLK Table 5 4 is a summary of the data movement operations Table 5 4 Data Movement Operations ea ea 8 16 32 Source Destination 16 32 SP 4 gt SP An 2 SP SP gt An SP d gt SP 16 32 gt 32 Source Destination list ea 16 32 Listed registers Destination ea list 16 32 32 Source Listed registers Dn 15 8 An d 4 Dn 7 0 gt An d 6
156. time of a fault is conveyed by the SSW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w m e Te we w w w e s e The bus error stack frame is 12 words in length There are three variations of the frame each distinguished by different values in the SSW TP and MV fields An internal transfer count register appears at location SP 14 in all bus error stack frames The register contains an 8 bit microcode revision number and for type III faults an 8 bit transfer count Register format is shown in Figure 5 14 15 8 7 0 MICROCODE REVISION NUMBER TRANSFER COUNT Figure 5 14 Internal Transfer Count Register The microcode revision number is checked before a bus error stack frame is restored via RTE In a multiprocessor system this check ensures that a processor using stacked information is at the same revision level as the processor that created it The transfer count is ignored unless the MV bit in the stacked SSW is set If the MV bit is set the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution For faults occurring during normal instruction execution both prefetches and non MOVEM operand accesses SSW TP MV 00 Stack frame format is shown in Figure 5 15 Faults that occur during the operand portion of the MOVEM instruction are identified by SSW TP MV 01 Stack frame format is shown in Figure 5 16 When bus error occurs during exception processing SSW TP MV 10
157. to external devices that the MC68340 is going into LPSTOP mode If an external device requires additional time to prepare for entry into LPSTOP mode entry can be delayed by asserting HALT The SIM40 provides internal DSACK response to this cycle For more information on how the SIMAO responds to LPSTOP mode see Section 4 System Integration Module 12 10 Interrupt Mask Level The interrupt mask level is encoded on bits 2 0 of the data bus during an LPSTOP broadcast MOTOROLA MC68340 USER S MANUAL 3 23 BREAKPOINT OPERATION FLOW EXTERNAL DEVICE PROCESSOR ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED SET R W TO READ SET FUNCTION CODE TO CPU SPACE PLACE CPU SPACE TYPE 0 ON A19 A16 PLACE BREAKPOINT NUMBER ON A2 A4 CLEAR T BIT A1 SET SIZE TO WORD 7 ASSERT AS AND DS KPT PIN ASSERTED SET R W TO READ SET FUNCTION CODE TO CPU SPACE PLACE CPU SPACE TYPE 0 ON A19 A16 PLACE ALL ONE S ON A4 A2 SET T BIT A 1 TO ONE SET SIZE TO WORD ASSERT AS AND DS Un IF BREAKPOINT INSTRUCTION EXECUTED 1 PLACE REPLACEMENT OPCODE ON DATA BUS 2 ASSERT DSACKx __ OR 1 ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED 1 ASSERT DSACKx 0 1 ASSERT BERR INITIATE EXCEPTION PROCESSING Cn IF BREAKPOINT INSTRUCTION EXECUTED AND DSACKx IS ASSERTED 1 LATCHDATA 0 02 2 NEGATE AS AND DS 3 GO TO A IF BKPT PIN ASSERTED
158. to sample the input at one bit time intervals at the theoretical center of the bit until the proper number of data bits and parity if any is assembled and one stop bit is detected Data on the RxDx input is sampled on the rising edge of the programmed clock source The least significant bit is received first The data is then transferred to a receiver holding register and the RxRDY bit in the appropriate SR is set If the character length is less than eight bits the most significant unused bits in the receiver holding register are cleared After the stop bit is detected the receiver immediately looks for the next start bit However if a nonzero character is received without a stop bit framing error and RxDx remains low for one half of the bit period after the stop bit is sampled the receiver operates as if a new start bit is detected The parity error PE framing error FE overrun error OE and received break RB conditions if any set error and break flags in the appropriate SR at the received character boundary and are valid only when the RxRDY bit in the SR is set If a break condition is detected RxDx is low for the entire character including the stop bit a character of all zeros is loaded into the receiver holding register and the RB and RxRDY bits in the SR are set The RxDx signal must return to a high condition for at least one half bit time before a search for the next start bit begins MOTOROLA MC68340 USER S MANUAL 7
159. transmitter holding register is empty and ready to be loaded with a character This bit is set when the character is transferred to the transmitter shift register This bit is also set when the transmitter is first enabled Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted 0 The transmitter holding register was loaded by the CPU32 or the transmitter is disabled 7 4 1 13 INTERRUPT ENABLE REGISTER IER The IER selects the corresponding bits in the ISR that cause an interrupt output IRQ If one of the bits in the ISR is set and the corresponding bit in the IER is also set the IRQ output is asserted If the corresponding bit in the IER is zero the state of the bit in the ISR has no effect on the IRQ output The IER does not mask the reading of the ISR The ISR RDY bit cannot be enabled to generate an interrupt This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared IER 715 7 6 5 4 3 2 1 0 cos oes Furovelnaove o oon pesvi peosn RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User COS Change of State 1 Enable interrupt 0 Disable interrupt DBB Delta Break B 1 Enable interrupt 0 Disable interrupt 7 34 MC68340 USER S MANUAL MOTOROLA RxRDYB Channel B Receiver Ready or FIFO full 1 Enable interrupt 0 Disable interrupt TxRDYB Channel B Transmitter Ready 1 Enable interrupt 0
160. two clock bus cycles If the previous instruction has a negative tail then a prefetch for the current instruction can begin during the execution of that previous instruction Certain instructions requiring an immediate extension word immediate word EA absolute word EA address register indirect with displacement EA conditional branches with word offsets bit operations LPSTOP TBL MOVEM MOVES MOVEP MUL L DIV L CHK2 CMP2 and DBcc are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle This does not apply to long offsets or displacements 5 98 MC68340 USER S MANUAL MOTOROLA 5 7 3 1 FETCH EFFECTIVE ADDRESS The fetch EA table indicates the number of clock periods needed for the processor to calculate and fetch the specified EA The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes J Cycles Nos ____ ooj An f ooj 1 An An An d 16 An or d1g PC A xxx L data B data W data L dg An Xn Sz x Sc or dg PC Xn Sz x Sc 0 Suppressed d 16 or d1g PC oei l oej o 2l el co gt gt 5 lt lt lt lt
161. until the shift register is ready to accept more data When the shift register is empty it checks to see if the holding register has a valid character to be sent TxRDY bit cleared If there is a valid character the shift register loads the character and reasserts the TxRDY bit in the channel s SR Writes to the transmitter buffer when the channel s SR TxRDY bit is clear and when the transmitter is disabled have no effect on the transmitter buffer This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared TBA TBB 713 71B 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User TB7 TBO These bits contain the character in the transmitter buffer 7 4 1 10 INPUT PORT CHANGE REGISTER IPCR The IPCR shows the current state and the change of state for the CTSA and CTSB pins This register can only be read when the serial module is enabled i e the STP bit in the MCR is cleared IPCR 714 7 6 5 4 3 2 1 0 s s oss oo T Tes ors jm 0 0 0 0 0 U U Read Only Supervisor User Bits 7 6 3 2 Reserved COSB COSA Change of State 1 Achange of state high to low or low to high transition lasting longer than 25 50 us when using a crystal as the sampling clock or longer than one or two periods when using SCLK has occurred at the corresponding CTS input MCR ICCS bit controls selection of the sampling clock for clear to send operation When these bits are set
162. when it is enabled to control the timer 1 the prescaler and counter are disabled Additionally the SR TG bit is set indicating that was negated The SR ON bit is cleared indicating that the timer is disabled If TGATE is 8 8 MC68340 USER S MANUAL MOTOROLA reasserted the timer is re enabled and begins counting from the value attained when was negated The SR ON bit is set again If TGATE is disabled 0 TGATE has no effect on the operation of the timer In this case the counter begins counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set The TG bit of the SR cannot be set At all times TGL in the SR reflects the level of TGATE If the counter counts down to the value stored in the COM register then the COM and TC bits in the SR are set The counter continues counting down to timeout At this time the SR TO bit is set and the SR COM bit is cleared The next falling edge of the counter clock after timeout causes the value in PREL1 to be loaded back into the counter and the counter begins counting down from this value The period of the square wave generator can be changed dynamically by writing a new value into the PREL1 Caution must be used because if PREL1 is accessed simultaneously by the counting logic and a CPUS2 write the old PREL1 value may actually get loaded into the counter at timeout Periodic interrupt generation can be
163. words for addresses or immediate data Addresses require two extension words because only absolute long addressing is permitted Immediate data can be either one or two words in length byte and word data each require a single extension word long word data requires two words Both operands and addresses are transferred most significant word first 5 6 2 8 2 Command Sequence Diagram A command sequence diagram see Figure 5 27 illustrates the serial bus traffic for each command Each bubble in the diagram represents a single 17 bit transfer across the bus The top half in each diagram corresponds to the data transmitted by the development system to the CPU the bottom half corresponds to the data returned by the CPU in response to the development system commands Command and result transactions are overlapped to minimize latency The cycle in which the command is issued contains the development system command mnemonic in this example read memory location During the same cycle the CPU responds with either the lowest order results of the previous command or with a command complete status if no results were required During the second cycle the development system supplies the high order 16 bits of the memory address The CPU returns a not ready response unless the received command was decoded as unimplemented in which case the response data is the illegal command encoding If an illegal command response occurs the development system should
164. 0 State Machine 5 69 5 71 SFC Bits 6 32 Shadowing 8 6 8 7 SHEN Bits 4 5 4 22 Shift and Rotate Instructions 5 24 5 25 Instruction Timing Table 5 108 Show Cycles 4 3 4 22 Operation 3 42 3 43 3 45 Signal Relationships to CLKOUT 10 7 Signal Widths 10 8 SIM40 Configuration 4 3 Programming Model 4 19 Simultaneous Interrupts 4 9 Single Address Mode 6 2 6 6 6 7 6 10 6 19 6 27 6 37 Source Read 6 7 6 8 Source Write 6 10 6 11 Single Operand Instruction Timing Table 5 107 Single Step Operation 3 36 Six Word Stack Frame 5 52 5 60 SIZ Bits 5 56 5 57 5 73 Size Signal Encoding 2 7 3 3 Signals 2 7 3 3 3 5 3 7 Skew Between Outputs 10 9 Slave Station 7 15 SLIMP Bit 4 11 4 29 SLOCK 4 11 4 29 Software Breakpoints 5 53 5 54 MOTOROLA MC68340 USER S MANUAL Interrupt Vector Register 4 7 4 24 4 36 Operation 4 4 4 6 4 17 4 27 Service Register 4 7 4 28 Service Routine 4 7 4 25 Timeout 4 25 Watchdog 4 1 4 4 4 6 Watchdog Clock Rate 4 7 Source Address Register 6 7 6 12 6 18 6 19 6 28 6 33 6 37 6 38 Special Status Word 5 45 5 52 Special Purpose MOVE Instruction Timing Table 5 101 5 102 Spurious Interrupt 3 29 Monitor 4 1 4 4 4 6 4 17 Square Wave Generation 8 6 8 8 8 9 SRAM Interface 10 3 SSIZE Bits 6 12 6 19 6 29 6 37 Stack Frames 5 60 5 63 Pointer 5 60 5 63 Start Break Command 7 29 Status Register 5 57 5 59 5 60 5 62 5 63 7 10 7 11
165. 0 0 35 3 2 4 10 1 0 0 oe NX ES Interrupt Head sm 22407 LN NN A GC NEM NIAI 2 ase 2 meme es ew ETE Breakpoint Bus Error i 2 3 4 F line Second word illegal Op S ee t o a e s TRAP 2 Tze TRAPeoL wap 0 0 euo C capa 1 Minimum interrupt acknowledge cycle time is assumed to be three clocks NOTE The F line second word illegal operation involves a save step which other operations do not have To calculate the total operation time calculate the save the calculate EA and the operation execution times and combine in the order listed using the equations given in 5 7 1 6 Instruction Execution Time Calculation 5 112 MC68340 USER S MANUAL MOTOROLA 5 7 3 14 SAVE AND RESTORE OPERATIONS The save and restore operations table indicates the number of clock periods needed for the processor to perform the specified state save or return from exception Complete execution times and stack length are given No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The num
166. 0 family Other members of the family include the MC68302 MC68330 MC68331 MC68332 and MC68333 1 2 MC68340 USER S MANUAL MOTOROLA 1 1 1 Organization The M68300 family of integrated processors and controllers is built on an M68000 core processor an on chip bus and a selection of intelligent peripherals appropriate for a set of applications The CPU32 is a powerful central processor with nearly the performance of the MC68020 A system integration module incorporates the external bus interface and many of the smaller circuits that typically surround a microprocessor for address decoding wait state insertion interrupt prioritization clock generation arbitration watchdog timing and power on reset timing Each member of the M68300 family is distinguished by its selection of peripherals Peripherals are chosen to address specific applications but are often useful in a wide variety of applications The peripherals may be highly sophisticated timing or protocol engines that have their own processors or they may be more traditional peripheral functions such as UARTs and timers Since each major function is designed in a standalone module each module might be found in many different M68300 family parts Driver software written for a module on one M68300 part can be used to run the same module that appears on another part 1 1 2 Advantages By incorporating so many major features into a single M68300 family chip a system designer can rea
167. 0000001 binary to 31 128 ms with a PITR value of FF 11111111 binary Solving the equation with the prescaler enabled 1 in the PITR gives the following values PITR count value periodic interrupt timer period 32768 512 22 periodic interrupt timer period PITR count value 16 This gives a range from 62 5 ms with a PITR value of 01 to 15 94 s with a PITR value of FF For fast calculation of periodic timer period using a 32 768 kHz crystal the following equations can be used With prescaler disabled programmable interrupt timer period 122 us With prescaler enabled programmable interrupt timer period 62 5 ms 4 8 MC68340 USER S MANUAL MOTOROLA 4 2 2 6 2 Using the Periodic Timer as a Real Time Clock The periodic interrupt timer can be used as a real time clock interrupt by setting it up to generate an interrupt with a one second period Rearranging the periodic timer period equation to solve for the desired count value PITR count value PIT period EXTAL frequency Prescaler value 22 1 32768 512 22 PITR count value PITR count value 16 decimal Therefore when using a 32 768 kHz crystal the PITR should be loaded with a value of 10 with the prescaler enabled to generate interrupts at a one second rate 4 2 2 7 SIMULTANEOUS INTERRUPTS BY SOURCES IN THE SIM40 If multiple interrupt sources at the same interrupt level are simultaneously asserted in the SI
168. 03FF00 Address of Module Base Address Reg MODBASE EQU FFFFF000 Default Module Base address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SIM40 register offsets from MBAR base address MCR EQU 00 SYNCR EQU 04 SYPCR EQU 21 CSAMO EQU 40 CSBARO EQU 44 CSAM1 EQU 48 CSBAR1 EQU 4c CSAM2 EQU 50 CSBAR2 EQU 54 CSAM3 EQU 58 CSBAR3 EQU 5c Reset vectors These two vectors should be located at addresses 0 and 4 after a processor hardware reset kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk ORG 60000 SSP VEC DC L SSP INIT Supervisor stack pointer initial value DC L INIT340 Reset vector pointing to initialization code 4 38 MC68340 USER S MANUAL MOTOROLA kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialization code kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Start Chip Select Initialization INIT340 MOVE W 2700 SR Init SR interrupts masked kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Set up default module base address value MOVEQ L 7 D0 MBAR is in CPU space MOVEC L D0 DFC load DFC to indicate CPU space MOVE L MODBASE 1 D0 Set address valid bit MOVES L D0 MBAR write to MBAR kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Set up system protection register Software watchdog disabled double bus fault monitor disa
169. 1 7 25 225 pi Package Dimensions 12 6 12 7 Package Types 1 9 12 1 12 2 12 4 Parity Error 7 11 7 24 Mode 7 23 Type 7 23 PCLK Bit 8 21 8 22 8 27 PE Bit 7 11 7 13 7 24 7 28 Period Measurement 8 13 Periodic Interrupt Control Register 4 7 4 26 4 37 Generation 8 6 8 8 8 9 Timer Register 4 7 4 27 4 37 Timer 4 1 4 4 4 7 4 9 4 17 Periodic Timer Period Calculation 4 8 Phase Comparator 4 11 4 12 Phase Locked Loop 4 9 4 12 10 1 10 2 Pin Group 12 3 12 5 PIRQL Bits 4 7 4 26 4 37 PITR Bits 4 27 4 37 PIV Bits 4 26 PM Bits 7 23 7 47 PO Bits 8 25 Port A Data Direction Register 4 34 Data Register 4 34 Index 5 Pin Assignment Register 1 4 15 4 33 4 37 Pin Assignment Register 2 4 15 4 34 4 37 Pins Functions 4 15 Assignment Encoding 4 15 4 34 Port B Configuration 4 5 4 16 Data Direction Register 4 35 Data Register 4 35 Functions 4 16 Pin Assignment Register 4 16 4 35 4 37 Pins Functions 2 6 2 9 4 16 Pin Assignment Encoding 4 16 4 35 Port Size 4 14 6 31 Port Width 3 1 3 7 POT Bits 8 22 8 28 Power Considerations 11 2 Power Consumption 1 8 1 9 10 11 Power Dissipation 10 11 Prefetch Controller 5 90 5 91 Prefetch Faults 5 55 5 58 5 62 Preload Register 1 8 6 8 13 8 25 8 27 Preload Register 2 8 10 8 11 8 13 8 26 8 27 Privilege Violations 5 48 Processor Clock Circuitry 10 1 10 2 Program Control Instructions 5 26 5 27 Program Counter
170. 11 C6 C7 C8 ARE LOST RECEIVER ENABLED RXRDY SRO W FFULL SR1 RXRDYA 7 CS R R R R R RRR STATUS DATA STATUS DATA STATUS DATA STATUS DATA C1 C2 C3 by C5 OVERRUN ST SR4 RESET BY COMMAND OPR 0 21 NOTES 1 Timing shown for MR1 7 1 2 Timing shown for OPCR 4 1 and MR1 6 0 3 R Read 4 CN Received Character Figure 7 6 Receiver Timing Diagram The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time When the break begins in the middle of a character the receiver places the damaged character in the receiver first in first out FIFO stack and sets the corresponding error conditions and RxRDY bit in the SR Then if the break persists until the next character time the receiver places an all zero character into the receiver FIFO and sets the corresponding RB and RxRDY bits in the SR 7 3 2 3 FIFO STACK The FIFO stack is used in each channel s receiver buffer logic The stack consists of three receiver holding registers The receive buffer consists of the FIFO and a receiver shift register connected to the RxDx refer to Figure 7 4 Data is 7 12 MC68340 USER S MANUAL MOTOROLA assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO Thus data flowing from the receiver to the CPU32 is quadruple buffered In addition t
171. 3 14 3 15 3 22 3 24 3 30 3 32 3 37 3 44 4 4 4 6 4 22 4 30 Error Stack Frame 5 60 5 63 Errors Types 3 34 Timing without DSACK 3 35 Timing Late Bus Error 3 36 Resulting in Double Bus Faults 3 39 Index 1 During Transfers 6 18 6 20 6 31 6 33 6 35 Grant Acknowledge Signal 3 40 3 44 Request Signal 2 7 3 37 3 40 3 44 6 25 State Diagram 3 45 Bypass Register 9 11 Byte Transfer Counter 6 15 6 19 6 20 6 34 6 35 6 37 6 38 oe Calculate Effective Address Instruction Timing Table 5 100 Calculating Frequency Adjusted Output 10 7 10 9 CALL Command 5 68 5 84 5 85 CD I 1 9 10 11 CD ROM 10 11 Cell Types 9 4 Output Latch Diagram 9 7 Input Pin Diagram 9 7 Active High Output Control Diagram 9 8 Active Low Output Control Diagram 9 8 Bidirectional Data Diagram 9 9 Change of Flow 5 91 5 94 Changing Privilege Levels 5 38 Timer Modes 8 6 Channel Control Register 6 4 6 5 6 18 6 20 6 26 6 30 6 36 6 37 Mode 7 38 Status Register 6 18 6 20 6 30 6 37 6 38 Character Mode 7 13 7 23 Chip Select 0 Signal 3 30 4 14 4 16 4 33 4 36 10 5 Chip Select 4 1 4 13 4 15 4 29 Access Time 10 6 10 7 Overlapped 4 15 4 33 Programming Example 4 33 Registers 4 29 Signals 2 5 4 15 4 17 10 4 10 6 10 7 Clear to Send Signal 2 11 CLK Bit 8 21 8 27 CLKOUT Signal 2 8 4 1 4 9 4 11 4 13 4 17 5 69 8 3 9 11 Clock Operating Modes 4 9 4 12 Select Register 7 8 7 1
172. 340 inserts wait states instead of proceeding to S4 and S5 To ensure that wait states are inserted both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2 If wait states are added the MC68340 continues to sample the DSACK signals on the falling edges of the clock until one is recognized State 4 At the end of S4 the MC68340 latches the incoming data State 5 The MC68340 negates AS and DS during S5 If more than one read cycle is required to read in the operand s 50 55 are repeated for each read cycle When finished reading the MC68340 holds the address R W and FC3 FCO valid in preparation for the write portion of the cycle The external device keeps its data and DSACK signals asserted until it detects the negation of AS or DS whichever it detects first The device must remove the data and negate within approximately one clock period after sensing the negation of AS DS DSACK signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation Idle States The MC68340 does not assert any new control signals during the idle states but it may internally begin the modify portion of the cycle at this time 50 55 are omitted if no write cycle is required If a write cycle is required R W remains in the read mode until SO to prevent bus conflicts with the preceding read portion of the cycle the data bus is not dri
173. 400 BASIC o jzrzxo oco m MOTOROLA MC68340 USER S MANUAL 12 7 INDEX LA LI A Line Instructions 5 47 A D Bit 7 15 7 16 7 23 Field 5 73 Register 5 76 5 77 Signal 3 6 3 13 Access Time Calculations 10 6 Address Access Time 10 6 Bus Signals 2 4 3 4 3 16 Error Exception 3 7 3 39 5 42 5 43 5 45 5 46 Mask Register Example 4 33 Mask Registers 4 31 4 37 Registers 5 10 5 13 Space Bits 4 20 Space Block Size 4 2 4 3 4 14 Spaces 2 5 3 8 3 4 4 2 4 20 4 30 4 31 6 32 Strobe Signal 2 6 3 2 3 4 3 14 3 21 3 44 3 46 4 22 with Postincrement 5 14 with Predecrement 5 14 Advantages 10 13 Alternate Function Code Registers 5 10 Applications Profile 10 10 Arithmetic Logical Instruction Timing Table 5 102 5 104 Assert RTS Command 7 28 7 29 Asynchronous Inputs 3 1 3 2 3 14 3 15 3 44 Operation 3 14 Setup and Hold Times 3 2 3 15 3 18 3 21 10 7 ATEMP Register 5 67 Automatic Echo Modes 7 14 7 38 Autovector Operation Timing 3 31 Register 4 5 4 6 4 23 Signal 2 6 3 5 3 29 3 32 4 6 Auxiliary Control Register 7 18 7 26 7 27 7 32 7 46 B Bits 5 56 5 57 5 58 B C Bits 7 23 7 24 7 47 Background Debug Mode 5 64 5 65 5 94 Command Execution 5 67 Command Summary 5 75 5 76 Serial Interface 5 68 5 69 Background Processing State 5 7 5 37 5 64 5 73 5 95 5 101 Base Address Bits 4 20 Base Address Regi
174. 5 0 3 to 46 5 TA or 40 to 85 Operating Temperature Range Storage Temperature Range 55 to 150 NOTES 1 Permanent damage can occur if maximum ratings are exceeded Exposure to voltages or currents in excess of recommended values affects device reliability Device modules may not operate normally while being exposed to electrical extremes 2 Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields take normal precautions to avoid exposure to voltages higher than maximum rated voltages This device contains protective circuitry against damage due to high static voltages or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either GND or Vcc The following ratings define a range of conditions in which the device will operate without being damaged However sections of the device may not operate normally while being exposed to the electrical extremes 11 2 THERMAL CHARACTERISTICS C cranar J Symbol Value Unit Thermal Resistance Junction to Case C W 6 TBD Ceramic 144 Pin QFP Plastic 145 Pin PGA Thermal Resistance Junction to Ambient Ceramic 144 Pin QFP Plastic 145 Pin PGA Estimated
175. 5 0 V 5 operation The 25 16 MHz 5 0 V 5 electrical specifications are preliminary For extended temperature parts T A 40 to 85 C These specifications are preliminary HET EA TCK Clock Pulse Width Measured at 1 5 V EE EA EA EN UE Cc N Figure 11 19 Test Clock Input Timing Diagram 11 24 MC68340 USER S MANUAL MOTOROLA TCK DATA INPUTS DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS TCLK TD TMS TDO TDO TDO MOTOROLA OUTPUT DATA VALID OUTPUT DATA VALID OUTPUT DATA VALID OUTPUT DATA VALID Figure 11 21 Test Access Port Timing Diagram MC68340 USER S MANUAL 11 25 SECTION 12 ORDERING INFORMATION AND MECHANICAL DATA This section contains ordering information pin assignments and package dimensions of the MC68340 12 1 STANDARD MC68340 ORDERING INFORMATION Supply Package Type Frequency MHz Temperature Order Number 5 0 V Ceramic Quad Flat Pack 0 C to 70 C MC68340FE16 FE Suffix 40 C to 85 C MC68340CFE16 0 C to 70 C MC68340FE25 Plastic Pin Grid Array 0 C to 70 C MC68340RP16 RP Suffix 40 C to 85 C MC68340CRP16 0 C to 70 C MC68340RP25 Ceramic Quad Flat Pack 8 0 C to 70 C MC68340FE8V FE Suffix 8 40 C to 85 C MC68340CFE8V 0 C to 70 C MC68340FE16V Plastic Pin Grid Array 8 0 C to 70 C MC68340RP8V RP Suffix 8 40 C to
176. 5 3 3 1 CONDITION CODE REGISTER The CCR portion of the SR contains five bits that indicate the result of a processor operation Table 5 3 lists the effect of each instruction on these bits The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them Refer to Table 5 7 as an example 5 20 Table 5 3 Condition Code Computations Operations SpecialDefiniton ABCD U U C Decimal Carry Z Z A RO ADD ADDI ADDQ ADDX AND ANDI EOR EORI MOVEQ MOVE OR ORI CLR EXT NOT TAS TST CHK CHK2 CMP2 SUB SUBI SUBQ SUBX CMP CMPI CMPM DIVS DIVU MULS MULU N NEGX A LSL ROXL T r 0 0 ASR LSR r 0 ROXR r 0 EG ROL 1V SmADm A R9 V S9 A Dd A Rm C Sm A Dm V Ro A Dm V Sm A VSmADm A Ro V Sd A D A Rm C Sm A Dm VRo A Dm V Sm A Ro 7 7 RO Z R LB V UB C LB lt UB A IR lt LB V R gt UB V UB LB A R UB A R LB V V Sd A Dm A Ra V Sm ADo A Rm C Sm ADd V Rm A 09 Sm A Rm Z Z AROA A RO Dm A Rm Dm V Rm 2 AROA A RO A Dd 1V VDd r VDO A Dm 1 V Dm r MC68340 USER S MANUAL MOTOROLA Table 5 3 Condition Code Computations Continued operations SpecialDetintion le mong Ss NOTE The following notations apply to
177. 5 6 5 67 5 68 Programming Model CPU32 5 8 5 9 DMA 6 23 Serial 7 19 SIM40 4 19 Timer 8 18 Propagation Delays 10 7 PS Bits 4 14 4 32 PT Bit 7 23 7 47 PTP Bit 4 7 4 27 4 37 Pulse Width Measurement 8 12 8 13 Pulse Width Modulation 8 6 8 7 Ri R F Bit 7 22 7 47 R W Field 5 73 RB Bit 7 13 7 24 7 30 RC Bits 7 30 RCS Bits 7 26 Read A D Register Command 5 76 5 77 Cycle Word Read Flowchart 3 16 Memory Location Command 5 79 5 80 Modify Write Cycle 5 53 Modify Write Faults 5 55 5 56 5 58 System Register Command 5 67 5 77 5 78 Read Modify Write Cycle Timing 3 19 Retry Operation 3 36 Interruption 3 36 3 43 Operation 3 4 Index 6 MC68340 USER S MANUAL Read Modify Write Signal 2 8 3 19 3 21 3 40 3 42 3 43 3 45 Read Write Signal 2 7 3 2 Real Time Clock 4 9 Receive Data Signal 2 11 Received Break 7 11 7 24 7 33 Receiver 7 9 7 11 Baud Rates 7 26 Buffer 7 11 7 12 7 25 7 30 Disable Command 7 30 Enable Command 7 30 FIFO 7 12 7 13 7 17 7 22 7 23 7 25 7 33 7 34 Holding Registers 7 9 7 11 Ready Signal 2 12 Shift Register 7 9 7 12 Timing 7 12 Register Field 5 74 Indirect Addressing Mode 5 5 Released Write 5 57 Remote Loopback Mode 7 14 7 38 REQ Bits 6 27 6 29 6 37 Request to Send Signal 2 11 Reset Break Change Interrupt 7 28 Effect on DMA Transfers 6 20 Error Status Command 7 28 Exception 5 43 5 44 Instruction 5 85 Peripherals Co
178. 6 Bs ATDIUSMO 6 3 40 3 6 1 5120 3 43 3 6 2 CAIN di eu 3 43 3 6 3 Bus Grant Acknowledge essent 3 43 3 6 4 Bus Arbitration COMO leet i seul 3 44 3 6 5 Sow GVeles Lido ce i 3 44 3 7 Reset Ober dioi seid decet eue dte eta siti tarda et aun 3 46 Section 4 System Integration Module 4 1 5st tepida a Mec 4 1 4 2 Module Operation mE 4 2 4 2 1 Module Base Address Register 4 2 4 2 2 System Configuration and Protection 4 3 4 2 2 1 System Configuration 5 4 5 4 2 2 2 Internal Bus Monitor tates 4 6 4 2 2 3 Double Bus Fault eso 4 6 4 2 2 4 Spurious Interrupt pee 4 6 4 2 2 5 Software Annie sedie bte dt 4 6 4 2 2 6 Periodic Interrupt TIMOR eene 4 7 4 2 2 6 1 Periodic Timer Period 4 8 4 2 2 6 2 Using the Periodic Timer as a Real Time Clock 4 9 4 2 2 7 Simultaneous
179. 7 24 8 2 8 4 8 23 8 25 STEXT Bit 4 13 4 17 4 29 4 36 Stop Bit 7 11 Length 7 39 Stop Break Command 7 29 STOP Instruction 4 17 Stop Module Operation 6 24 7 20 8 19 Stopped Processing State 5 37 STP Bit 4 17 6 24 6 36 7 20 7 46 8 19 STR Bit 6 3 6 4 6 5 6 19 6 30 6 35 6 37 6 38 STSIM Bit 4 13 4 17 4 29 4 36 Supervisor Privilege Level 3 3 SUPV Bit 4 22 6 22 6 25 6 36 7 21 7 46 8 19 8 27 Surface Interpolation with Tables 5 29 5 36 SW Bit 4 23 SWE Bit 4 6 4 24 4 37 SWP Bit 4 7 4 25 4 27 4 37 SWR Bit 8 6 8 8 8 13 8 20 8 27 SWRI Bit 4 7 4 24 4 37 SWT Bits 4 7 4 25 4 37 Synchronous Accesses 3 4 Operation 3 14 System Clock 8 3 Configuration and Protection 4 1 4 3 4 6 Control Instructions 5 27 5 28 Protection and Control Register 4 6 4 24 4 37 Table Lookup and Interpolate Instructions 5 7 5 12 5 29 5 36 TAP Controller 9 2 9 3 TC Bits 8 7 8 24 TCK Signal 2 13 9 2 9 11 9 12 Index 7 TCS Bits 7 27 TDI Signal 2 13 9 2 TDO Signal 2 13 9 2 9 4 Test Access Port 9 1 TG Bit 8 6 8 8 8 23 8 24 8 27 TGE Bit 8 8 8 11 8 15 8 24 8 27 TGL Bit 8 7 8 24 Thermal Characteristics 11 1 Three Point Three Volts 10 11 Timeout 8 2 8 7 8 9 8 12 8 15 Timer Bypass 8 16 Clock Selection Logic 8 3 Compare Function 8 2 8 6 8 9 8 11 8 12 8 14 8 15 8 25 Counter 8 2 Counting Function 8 13 8 15 Gate Signal 2 12 8 6 8 7 8 16 8 21
180. 8 7 26 7 27 7 33 7 47 Synthesizer Control Register 4 10 4 11 4 13 4 28 4 36 Synthesizer 4 1 4 9 OM Bits 7 38 Code Compatibility 5 8 5 11 COM Bit 8 7 8 9 8 12 8 24 8 25 8 27 Command Format 5 73 5 74 Register 7 10 7 11 7 23 7 27 7 46 7 47 Sequence Diagram 5 74 5 75 Index 2 MC68340 USER S MANUAL Compare Register 8 2 8 12 8 26 8 27 Compressed Tables 5 31 5 32 Condition Code Register 5 10 5 14 5 20 5 21 Condition Codes 5 10 5 26 5 27 Condition Test Instructions 5 20 5 21 5 29 Conditional Branch Instruction Timing Table 5 110 CONF Bit 6 20 6 30 6 31 6 37 6 38 Configuration Code Modules SIMAO 4 38 4 40 6 38 6 45 Serial 7 47 4 49 Timer 8 28 8 31 Control Instruction Timing Table 5 111 Control Register 8 4 8 20 8 23 COS Bit 7 31 7 32 7 34 Counter Clock 8 3 Events 8 2 Register 8 6 8 7 8 13 8 14 8 25 CPE Bit 8 6 8 8 8 21 8 24 8 28 CPU Space 3 3 3 21 3 23 3 28 Address Encoding 3 21 CPU32 Block Diagram 5 3 Privilege Levels 5 7 5 37 5 38 Processing States 5 7 5 36 5 37 Programming Model 5 8 5 9 Serial Logic 5 71 5 73 Stack Frames 5 60 5 63 Crystal Oscillator 4 9 4 10 4 29 CTS Bits 7 31 7 35 Operation 7 11 CTSx Signal 7 6 7 7 7 11 7 13 7 20 7 22 7 29 7 31 7 32 7 35 7 39 Current Drain 10 11 Typical Operation Data 10 12 10 13 Current Instruction Program Counter 5 67 5 68 Cycle Steal Tra
181. 8 27 FTE Bit 4 14 4 30 Full Format Instruction Word Function Code 3 6 18 6 32 Encoding 2 5 3 3 Register 6 7 6 10 6 12 6 15 6 32 6 38 6 37 Signals 2 5 3 2 3 17 ER Global Chip Select 4 14 4 15 4 36 GO Command 5 68 5 83 5 84 H Halt Operation 3 38 3 39 3 41 Signal 2 8 3 4 3 13 3 15 3 30 3 32 3 38 4 4 4 6 4 17 Halted Processing State Halted Processor Causes 3 40 Hardware Breakpoints 5 60 5 64 5 65 IACK Signals 4 15 4 34 IARB Bits 4 5 4 22 4 36 6 25 6 26 6 36 7 21 7 46 8 19 8 27 ICCS Bit 7 20 7 46 IE Bits 8 4 8 8 8 9 8 21 8 27 IEC Bits 7 32 7 46 IEEE 1149 1 4 2 9 1 Capabilities 9 1 9 4 Implementation 9 2 Block Diagram 9 2 Instruction Encoding 9 10 Control Bits 9 4 Restrictions 9 11 IFETCH Signal 5 64 5 68 5 69 5 87 5 88 Index 4 MC68340 USER S MANUAL IL Bits 7 21 7 46 8 20 8 27 IMB 6 19 7 1 8 1 Immediate Arithmetic Logical Instruction Timing Table 5 105 IN Bit 5 53 5 56 5 61 Input Port 7 35 Change Register 7 31 Instruction Cycles 5 97 Execution Overlap 5 91 5 92 5 94 5 95 Execution Time Calculation 5 92 5 93 Fetch Signal 2 19 Heads 5 91 5 94 5 97 Pipe Signal 2 10 Pipeline Operation 5 89 5 90 5 93 Register 9 9 9 10 Stream Timing Examples 5 94 5 97 Tails 5 91 5 94 5 97 Timing Table Overview 5 97 5 98 INTB Bit 6 20 6 27 6 36 INTE Bit 6 20 6 27 6 36 Integer Arithmetic Operatio
182. 8340 USER S MANUAL MOTOROLA The timer is enabled by setting both the SWR and CPE bits in the CR and if TGATE is enabled TGE bit in the CR is set then asserting TGATE When the timer is enabled the ON bit in the SR is set On the next falling edge of the counter clock the counter is loaded with the value stored in the PREL1 register N1 With each successive falling edge of the counter clock the counter decrements The time between enabling the timer and the first timeout can range from N1 to 1 periods When is used to enable the counter the enabling of the timer is asynchronous however if timing is carefully considered the time to the first timeout can be known For additional details on timing see Section 11 Electrical Characteristics If the counter counts down to the value stored in the COM the COM and TC bits in the SR are set The counter continues counting down to timeout At this time the SR TO bit is set and the SR COM bit is cleared The next falling edge of the counter clock after timeout causes the value in PREL2 N2 to be loaded into the counter and the counter begins counting down from this value After the second timeout the selected clock is held high disabling the prescaler and counter Additionally the SR ON and COM bits are cleared TOUTx behaves as a variable width pulse when the OCx bits of the CR are programmed for toggle mode TOUTx is a logic zero between the time that the timer is enabled a
183. AND DSACKx IS ASSERTED 1 NEGATE AS AND DS 2 GO TO A IF BERR ASSERTED 1 NEGATE AS AND DS 2 GO TO B A 1 NEGATE DSACKx or BERR IF BREAKPOINT INSTRUCTION EXECUTED 1 PLACE LATCHED DATA IN INSTRUCTION PIPELIN 2 CONTINUE PROCESSING IF BKPT PIN ASSERTED 1 CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED 1 INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED 1 INITIATE HARDWARE BREAKPOINT PROCESSING Figure 3 11 Breakpoint Operation Flowchart 3 24 MC68340 USER S MANUAL MOTOROLA 50 51 52 53 54 55 50 51 S2 S3 54 S5 50 51 52 S3 54 55 50 A19 A16 AENEA E BREAKPOINT ENCODING 0000 A15 A5 A0 RW ERO FETCHED INSTRUCTION MK BREAKPOINT READ BREAKPOINT EXECUTION OCCURS ACKNOWLEDGE INSTRUCTION WORD FETCH Figure 3 12 Breakpoint Acknowledge Cycle Timing Opcode Returned MOTOROLA MC68340 USER S MANUAL 3 25 50 51 52 53 S4 S5 50 S1 52 53 54 S55 50 51 52 S3 54 S5 50 A19 A16 COO BREAKPOINT ENCODING 0000 A15 A5 0 RW ey BREAKPOINT STACKING 6 2 BREAKPOINT gt lt lt READ gt lt ACKNOWLEDGE OCCURS BUS ERROR ASSERTED Figure 3 13 Breakpoint Acknowledge Cycle Timing Exception Signaled 3 26 MC68340 USER S MANUAL MOTOROLA 3 4 3 Module Base Address Register Access All internal module registers including the SIM40 occupy
184. An d 4 Dn 15 8 An d 6 Dn 7 0 916 An 16 32 Dn 31 24 Dn 23 16 d 2 116 An Dn An d Dn 31 24 An d 2 Dn 23 16 data Dn Immediate Data Destination An MOTOROLA MC68340 USER S MANUAL An SP SP 2 An SP 4 gt SP SP 4 SP em SP an 5 21 5 3 3 3 INTEGER ARITHMETIC OPERATIONS The arithmetic operations include the four basic operations of add ADD subtract SUB multiply MUL and divide DIV as well as arithmetic compare CMP CMPM CMP2 clear CLR and negate NEG The instruction set includes ADD CMP and SUB instructions for both address and data operations with all operand sizes valid for data operations Address operands consist of 16 or 32 bits The clear and negate instructions apply to all sizes of data operands Signed and unsigned MUL and DIV instructions include Word multiply to produce a long word product Long word multiply to produce a long word or quad word product Division of a long word dividend by a word divisor word quotient and word remainder Division of a long word or quad word dividend by a long word divisor long word quotient and long word remainder A set of extended instructions provides multiprecision and mixed size arithmetic These instructions are add extended ADDX subtract extended SUBX sign extend EXT and negate binary with extend NEGX Refer to Table 5 5 for a summary of the integer
185. BUS PORT RTSB OP1 INTERFACE SYSTEM RTSA OPO INTEGRATION MODULE IMB BGACK ARBITRATIO R TWO CHANNEL DMA CONTROLLER IRQ7 PORT B7 lt gt IRQG PORT B6 lt gt IR Q5 PORT B5 IRQ3 PORT B3 CS3IIRQAPORT B4 lt gt PORTB CS2 IRQ2 PORT 2 CST IRQI PORT lt gt CSO AVEC lt MODCK PORT 80 Figure 2 1 Functional Signal Groups MOTOROLA MC68340 USER S MANUAL 2 1 2 1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2 1 The name mnemonic and brief functional description are presented For more detail on each signal refer to the signal paragraph Guaranteed timing specifications for the signals listed in Table 2 1 can be found in Section 11 Electrical Characteristics Table 2 1 Signal Index Input Signal Name Function Output Address Bus A23 A0 Lower 24 bits of the address bus Address Bus Port A7 A0 1 24 Upper eight bits of the address bus parallel I O port or Out l O Out Interrupt Acknowledge interrupt acknowledge lines Data Bus D15 DO The 16 bit data bus used to transfer byte or word data y o Function Codes FC3 FCO Identify the processor state and the address space of the Out current bus cycle Chip Select 3 1 CS3 CS1 Enables peripherals at programmed addresses interrupt Out In Interrupt Request Level priority level to the CPU32 or parallel I O port Port 4 B2 B1 Chip Select O Au
186. C68340 then decrements the transfer size counter increments the address and reads the least significant byte of the operand from bits 15 8 of the data bus For a write operation the MC68340 drives the word operand on bits 15 0 of the data bus The slave device then reads the most significant byte of the operand from bits 15 8 of the data bus and asserts DSACKO to indicate that it received the data but is an 8 bit port The MC68340 then decrements the transfer size counter increments the address and writes the least significant byte of the operand to bits 15 8 of the data bus MOTOROLA MC68340 USER S MANUAL 3 9 3 2 3 5 WORD OPERAND 16 PORT ALIGNED The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand WORDOPERAND opo OPI 15 0 DATA BUS D15 807 DO SIZi SIZO 0 DSACK DSACKO CYCLE1 opo OPl 1 0 0 0 X For a read operation the slave responds by placing the data on bits 15 0 of the data bus and asserting DSACK 1 to indicate a 16 bit port When DSACK 1 is asserted the MC68340 reads the data on the data bus and terminates the cycle For a write operation the MC68340 drives the word operand on bits 15 0 of the data bus The slave device then reads the entire operand from bits 15 0 of the data bus and asserts DSACK1 to terminate the bus cycle 3 2 3 6 LONG WORD OPERAND TO 8 BIT PORT ALIGNED The MC68340 drives the address bus with the desired
187. CHI IS CHANNEL B TRANSMITTER READY SEND A LINE FEED CHARACTER TO CHANNEL B TRANSMITTER POUTCHR RETURN Figure 7 10 Serial Module Programming Flowchart 5 of 5 MOTOROLA MC68340 USER S MANUAL 7 45 7 5 SERIAL MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the serial module 7 5 1 Serial Module Configuration If the serial capability of the MC68340 is being used the following steps are required to properly initialize the serial module NOTE The serial module registers can only be accessed by byte operations Command Register CR Reset the receiver and transmitter for each channel The following steps program both channels Module Configuration Register MCR Initialize the stop bit STP for normal operation Select whether to respond to or ignore FREEZE FRZx bits Select the input capture clock ICCS bit Select the access privilege for the supervisor user registers SUPV bit Select the interrupt arbitration level for the serial module IARBx bits Interrupt Vector Register IVR Program the vector number for a serial module interrupt Interrupt Level Register ILR Program the interrupt priority level for a serial module interrupt Interrupt Enable Register IER Enable the desired interrupt sources Auxiliary Control Register ACR Select baud rate set BRG bit Initialize the input enable control
188. CPU enables the serial communication hardware and awaits a command 5 66 MC68340 USER S MANUAL MOTOROLA The CPU writes a unique value indicating the source of BDM transition into temporary register A ATEMP as part of the process of entering BDM A user can poll ATEMP and determine the source see Table 5 20 by issuing a read system register command RSREG ATEMP is used in most debugger commands for temporary storage it is imperative that the RSREG command be the first command issued after transition into BDM Table 5 20 Polling the BDM Entry Source Double Bus Fault FFFF BGND Instruction 0000 0001 Hardware Breakpoint 0000 0000 SSW is described in detail in 5 5 3 Fault Recovery A double bus fault during initial SP PC fetch sequence is distinguished by a value of FFFFFFFF in the current instruction PC At no other time will the processor write an odd value into this register 5 6 2 4 COMMAND EXECUTION Figure 5 21 summarizes BDM command execution Commands consist of one 16 bit operation word and can include one or more 16 bit extension words Each incoming word is read as it is assembled by the serial interface The microcode routine corresponding to a command is executed as soon as the command is complete Result operands are loaded into the output shift register to be shifted out as the next command is read This process is repeated for each command until the CPU returns to normal operating mode 5 6 2 5 BDM REGISTE
189. CPU32 access to the MCR of each module The system clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPU32 or until reset For more information see the description of the MCR STP bit for each module If an external device requires additional time to prepare for entry into LPSTOP mode entry can be delayed by asserting HALT see 3 4 2 LPSTOP Broadcast Cycle 4 2 7 Freeze FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode enabled Refer to Section 5 CPU32 for more information on the background mode When FREEZE is asserted the double bus fault monitor and spurious interrupt monitor continue to operate normally However the software watchdog the periodic interrupt timer and the internal bus monitor will be affected When FREEZE is asserted setting the FRZ1 bit in MOTOROLA MC68340 USER S MANUAL 4 17 the MCR disables the software watchdog and periodic interrupt timer and setting the FRZO bit in the MCR disables the bus monitor 4 3 PROGRAMMING MODEL Figure 4 8 is a programming model register map of all registers the SIM40 For more information about a particular register refer to the description of the module or function indicated in the right column The ADDR address column indicates the offset of the register from the address stored in the module base address register The FC function code column indicates whether a register is restricted to super
190. D DISABLED gt DOx OUTPUT a Automatic Echo DISABLED INPUT DISABLED TxDx b Local Loopback DISABLED DISABLED INPUT CPU DISABLED DISABLED TxDx c Remote Loopback CPU Figure 7 7 Looping Modes Functional Diagram 7 3 4 Multidrop Mode A channel can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications Functional timing information for the multidrop mode is shown in Figure 7 8 The mode is selected by setting bits 3 and 4 in mode register 1 MR1 This mode of operation allows the master station to be connected to several slave stations maximum of 256 In this mode the master transmits an address character followed by a block of data characters targeted for one of the slave stations The slave stations have their channel receivers disabled However they continuously monitor the data stream sent out by the master station When an address character is sent by the master the slave receiver channel notifies its respective CPU by setting the RxRDY bit in the SR and generating an interrupt if programmed to do so Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station Slave stations not addressed continue to monitor the data stream for the next address character Data fields in the data stream are separated by
191. D DMASAR1 A0 Initialize destination operand address Destination address is equal to 8000 MOVE L DARADD DMADAR1 A0 Initialize the byte transfer count register The number of bytes to be transferred is 64 or 50 words MOVE L NUMBYTE DMABTC 1 A0 Channel control reg init and Start DMA transfers No interrupts are enabled destination write cycle Source address is not incremented Increment the destination address Source size is word destination size is word REQ is internal 100 of bus bandwidth dual address transfers start the transfers MOVE W 068D DMACCR1 A0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Example 4 Cycle Steal Request Generation Dual Address Transfers MC68340 basic DMA channel register initialization example code This code is used to initialize the 68340 s internal DMA channel registers providing basic functions for operation The code sets up channel 1 for external cycle steal request generation dual address transfers DMA 16 bit wide data from an odd address to an even address Control signals are asserted on the DMA read cycle kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SIM40 equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
192. DBASE EQU FFFFF000 SIM40 MBAR address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DMA Channel 1 equates DMACH 1 EQU 780 Offset from MBAR for channel 1 regs DMAMCR1 EQU 0 MCR for channel 1 Channel 1 register offsets from channel 1 base address 6 38 MC68340 USER S MANUAL MOTOROLA DMAINT1 EQU 4 interrupt register channel 1 DMACCR1 EQU 8 control register channel 1 DMACSR1 EQU A status register channel 1 DMAFCR1 EQU B function code register channel 1 DMASAR1 EQU C source address register channel 1 DMADAR1 EQU 910 destination address register channel 1 DMABTC1 EQU 14 byte transfer count register channel 1 SARADD EQU 10000 source address NUMBYTE EQU C number of bytes to transfer kk kk kc ke ec ec ke ee e e ee e ce hee e ke ec e echec e ee e e ec e hee eee ke e e ee eee e ke e e ke ee ke e ke e e ke e e e kk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialize DMA Channel 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE DMACH1 A0 Pointer to channel 1 Initialize DMA channel 1 MCR Normal Operation ignore FREEZE single address mode ISM field at 2 Make sure CPU32 SR 12 10 bits are less than or equal to ISM bits for channel startup Supervisor user reg unrestricted MAID field at 7 IARB priority at 1 MOVE W 1271 0 Clear channel control reg Clear STR start bit to prevent the c
193. DMA or a peripheral device during any DMA bus cycle to indicate that the last data transfer is being performed DONE is an active input in any mode As an output DONE is only active in external request mode An external pullup resistor is required even if operating only in the internal request mode 6 3 TRANSFER REQUEST GENERATION The DMA channel supports two types of request generation methods internal and external Internally generated requests can be programmed to limit the amount of bus utilization Externally generated requests can be either burst mode or cycle steal mode The request generation method used for the channel is programmed by the channel control register CCR in the REQ field 6 3 1 Internal Request Generation Internal requests are accessed in two clocks by the intermodule bus IMB The channel is started as soon as the STR bit in the CCR is set The channel immediately requests the bus and begins transferring data Only internal requests can limit the amount of bus utilization The percentage of the bandwidth that the DMA channel can use during a transfer can be selected by the CCR BB field 6 4 MC68340 USER S MANUAL MOTOROLA 6 3 1 1 INTERNAL REQUEST MAXIMUM RATE Internal generation using 100 of the internal bus always has a transfer request pending for the channel until the transfer is complete As soon as the channel is started the DMA will arbitrate for the internal bus and begin to transfer data when it becomes
194. DRE Input that starts a DMA process Q2 DREQ1 DMA Acknowledge DACK2 DACK1 DMA Done DONE2 Bi directional signal that indicates the last transfer DONE1 Timer Gate TGATE2 Counter enable input to timer TGATE1 Timer Input TIN2 TIN1 Time reference input to timer Timer Output TOUT2 Output waveform from timer TOUT1 Test Clock TC In In In Ou In In Ou In In n TDI Shifts in instructions and test data TDO Shifts out instructions and test data Synchronizer Power VCCSYN Quiet power supply to VCO also used to control synthesizer mode after reset System Power Supply Voc GND Power supply and ground to the MC68340 and Ground MOTOROLA MC68340 USER S MANUAL 2 3 t ut t t ut The terms assert and negate used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a signal is inactive or false 2 2 ADDRESS BUS The address bus signals are outputs that define the address of the byte or the most significant byte to be transferred during a bus cycle The MC68340 places the address on the bus at the beginning of a bus cycle The address is valid while AS is asserted The address bus consists of the following two groups Refer to Section 3 Bus Op
195. DSACKx AVEC TW WRITE lt CYCLE F INTERNAL READ ARBITRATION Internal Arbitration may take between 0 2 clocks Figure 3 16 Autovector Operation Timing MOTOROLA MC68340 USER S MANUAL STACK 3 31 3 5 BUS EXCEPTION CONTROL CYCLES The bus architecture requires assertion of from an external device to signal that a bus cycle is complete Neither DSACK nor AVEC is asserted in the following cases e DSACK AVEC is programmed to respond internally The external device does not respond Various other application dependent errors occur The MC68340 provides BERR when no device responds by asserting DSACK AVEC within an appropriate period of time after the MC68340 asserts AS This mechanism allows the cycle to terminate and the MC68340 to enter exception processing for the error condition HALT is also used for bus exception control This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation or in combination with BERR a retry of a bus cycle in error To properly control termination of a bus cycle for a retry or a bus error condition BERR and HALT can be asserted and negated with the rising edge of the MC68340 clock This assures that when two signals are asserted simultaneously the required setup and hold time for both is met for the same falling edge of the MC68340 clock This or an
196. Ds if both channels are being used If they are programmed the same channel 1 has priority Select the interrupt arbitration level for the DMA channel IARB bits Only one set of IARB bits exits for both channels Interrupt Register INTR Program the interrupt priority level for the channel interrupt INTL bits Program the vector number for the channel interrupt INTV bits Channel Control Register CCR If desired enable the interrupt when breakpoint is recognized and the channel is the bus master INTB bit If desired enable the interrupt when done without an error condition INTN bit If desired enable the interrupt when the channel encounters an error INTE bit 6 36 MC68340 USER S MANUAL MOTOROLA Select the direction of transfer if in single address mode ECO bit or select which device generates requests if in dual address mode 6 9 1 1 DMA CHANNEL OPERATION IN SINGLE ADDRESS MODE The following steps are required to begin a DMA transfer in single address mode Channel Control Register CCR Write a zero to the start bit STR to prevent the channel from starting the transfer prematurely Select the amount by which to increment the source address for a read cycle SAPI bit or the destination address for a write cycle DAPI bit Define the transfer size by selecting the source size for a read cycle SSIZE field or by selecting the destination size for a write cycle DSIZE field Select ext
197. EL1 Caution must be used because if PREL2 is accessed simultaneously by the counting logic and a CPU32 write the old PREL2 value may actually get loaded into the counter at timeout 8 3 5 Pulse Width Measurement This mode is used to count the clock cycles during a particular event see Figure 8 8 The event is defined by the assertion and negation of When TGATEz is asserted the counter begins counting down from FFFF When TGATE is negated the counter stops counting and holds the value at which it stopped Further assertions and negations of TGATE have no effect on the counter This mode be selected by programming the CR MODEx bits to 100 The timer is enabled by setting the SWR CPE and TGE bits in the CR Asserting starts the counter When the timer is enabled the SR ON bit is set On the next falling edge of the counter clock the counter is loaded with the value FFFF With each successive falling edge of the counter clock the counter decrements The PREL1 and PREL2 registers are not used in this mode When TGATEz is negated the SR TG bit is set the ON bit is negated and the prescaler and counter are disabled Subsequent transitions on TGATE do not re enable the counter The TGL bit in the SR reflects the level of TGATE at all times COUNTER CLOCK COUNTER Q f f f f f f f f f E EENE f f f f f f e d C b TGATE MEASURED PULSE _ R
198. EQ input to the DMA is level sensitive and is sampled at certain points to determine when a valid request is asserted by the device The device requests service by asserting DREQ and leaving it asserted In response the DMA arbitrates for the bus and performs an operand transfer During each operand transfer the DMA asserts DMA acknowledge DACK to indicate to the device that a request is being serviced DACK is asserted on the cycle of either the source or destination device depending on which one generated the request as programmed by the CCR ECO bit To allow more than one transfer to be recognized DREQ must meet the asynchronous setup and hold times while DACK is asserted in the DMA bus cycle Upon completion of a request DREQ should be held asserted bursting into the following DMA bus cycle to allow another transfer to occur The recognized request will immediately be serviced If DREQ is negated before DACK is asserted a new request is not recognized and the DMA channel releases ownership of the bus 6 3 2 2 EXTERNAL CYCLE STEAL MODE For external devices that generate a pulsed signal for each operand to be transferred the cycle steal request mode uses the DREQ signal as a falling edge sensitive input The DREQ pulse generated by the device must be asserted during two consecutive falling edges of the clock to be recognized as valid MOTOROLA MC68340 USER S MANUAL 6 5 Therefore if a peripheral generates it asynchronously
199. EQU 604 interrupt register timer1 CR1 EQU 606 control register timer1 SR1 EQU 608 status register timer1 1 EQU 60 counter register timer1 PRLD11 EQU 60C preload register 1 timer1 1 EQU 610 compare register timer1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialize Timer1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE TIMER1 A0 Pointer to timeri module Disable timer1 CLR W CR1 A0 Clear the TO TG and TC bits CLR W SR1 A0 8 28 MC68340 USER S MANUAL MOTOROLA Module configuration register Timer1 module is set for normal operation ignore FREEZE Supervisor user timer1 registers unrestricted Interrupt arbitration at priority 03 MOVE W 0003 MCR1 A0 Initialize timer1 interrupt level to 2 and vector to 0F MOVE W 020F IR1 A0 Initialize preload 1 to 3 MOVE W 0003 PRLD11 A0 nitialize the compare register to 0 CLR W A0 Control register 1 Enable timer1 no interrupts are enabled TGATE signal has no effect Use the selected clock for the counter clock and enable it Selected clock is 1 2 system s freq Square wave generation toggle TOUT MOVE W 8205 CR1 A0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
200. ES L A0 DO load DO with the contents of MBAR Address 0003FF00 in CPU space MBAR will be loaded with the value FFFFFO01 This value will set the base address of the internal registers to FFFFF MBAR can be written to using the following code MOVE L 7 00 load DO with the CPU space function code MOVEC L DO DFC load DFC to indicate CPU space LEA L 0003FF00 A0 load AO with the address of MBAR MOVE L FFFFFO01 DO load DO with the value to be written into MBAR MOVES L DO write the value contained in DO into MBAR 4 3 2 System Configuration and Protection Registers The following paragraphs provide descriptions of the system configuration and protection registers 4 3 2 1 MODULE CONFIGURATION REGISTER MCR The MCR which controls the SIM40 configuration can be read or written at any time MCR 000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 21 20 FIRQ ofo SHEN1 SHENO SUPV ofofo IARB3 IARB2 IARB1 IARBO RESET 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 Supervisor Only Bits 15 11 10 6 4 Reserved FRZ1 Freeze Software Enable 1 When FREEZE is asserted the software watchdog and periodic interrupt timer counters are disabled preventing interrupts from occurring during software debug 0 When FREEZE is asserted the software watchdog and periodic interrupt timer counters continue to run See 4 2 7 Freeze for more information MOTOROLA MC68340 USER S MANUAL 4 21 FRZO Freeze Bus Monitor Enable
201. Group 2 I O Pins IOL 15 3 mA HALT RESET Total Su upply Current at 5 V 5 16 78 MHz RUN LPSTOP VCO Off Power Dissipation at 5 V 5 16 78 24 Total RE PA Current at 3 3 V 0 3 V 8 39 MHz qa VCO Off Power Dissipation at 3 3 V 0 3 V 8 39 26 Input Capacitance 7 All Input Only Pins All I O Pins Load Capacitance NOTES a The electrical specifications in this document for both the 8 39 and 16 78 MHz 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part The 16 78 MHz specifications apply to the MC68340 9 5 0 V 5 operation The 25 16 MHz 5 0 V 5 electrical specifications are preliminary For extended temperature parts TA 40 to 85 C These specifications are preliminary 1 Input Only Pins BERR BG BKPT BR CTSB CTSA DREQ2 DREQ1 DSACK1 DSACKO EXTAL RxDB RxDA 5 TDI TGATE2 TGATE1 TIN2 TIN1 TMS Output Only Pins 23 0 AS BG CLKOUT DACK2 DACK1 DS FREEZE IFETCH RMC RTSB RTSA R W R RDYA SIZ1 5120 TOUT2 TOUT1 TxDB TxDA T RDYA Input Output Pins Group 1 015 00 Group 2 1 24 53 50 DONE2 DONE1 IRQ7 IRQ5 IRQ3 MODCK Group 3 HALT RESET specification for HALT RESET DONE2 and 1 is not applicable because they are open drain pins Supply current measured with system clock frequency of 16 78 MHz 9 5 25 V Power dissipation measu
202. HDI o 2 SER gt 23 gt B 11 8 MC68340 USER S MANUAL MOTOROLA 11 7 AC TIMING SPECIFICATIONS Continued Characteristic 304 CLKOUT Low to Data In Invalid Fast Termination Hold DSACK Asserted to DSACK Valid Skew 33 BR Asserted to BG Asserted RMC Not Asserted A R W Width Asserted Fast Termination Write or tRwas 18 Read E z 6A RESET Pulse Width Input from External Device BERR Negated to HALT Negated Rerun tBNHN 0 CLKOUT Low to Data Bus Driven Show Cycle tSCLDD 71 Data Setup Time to CLKOUT Low Show tSCLDS Cycle s 2 3 4 4 gt o amp lo 212 N Vis a KE N N 8 83 DSCLK Hold Time tDSCH 8 MOTOROLA MC68340 USER S MANUAL 2 gt 5 gt 2 gt 5 gt gt 5 3 o 3 o gt o gt o 3 o OJO KI x l la a a a a a a al l l G cic c 313191 a4 11 7 AC TIMING SPECIFICATIONS Continued sae mHz Miz 25 16 Characteristic Symbol Min Max Min Max Min Max __ 2 2 CLKOUT High to FREEZE Asserted CLKOUT High to FREEZE Asserted tFRZA CLKOUT High to FREEZE Negated temzN 0 CLKOUT High to IFETCH High Impedance 0 CLKOUT High to IFETCH Valid NOTES The electrical specifications in
203. I 7 10 zc gm EE H 7 11 an 7 12 Looping Modes ccc 7 14 Automatic Echo Mode 7 14 local Eoepbacke 7 14 Remote Loopback Mode 2 doe e 7 14 eec RA 7 15 B s Operation ECTS 7 17 Read Cycles mM DR 7 17 cR 7 17 Interrupt Acknowledge Cycles eese 7 17 Register Description and Programming sess 7 17 Hegister DOSscrpllOfVss cu 7 17 Module Configuration Register 7 19 MC68340 USER S MANUAL xiii 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Continued Paragraph Page Number Title Number 7 4 1 2 Interrupt Level Register ILR escas 7 21 7 4 1 3 Interrupt Vector Register IVR sss 7 21 7 4 1 4 Mode Register 1 MB ees Dette D thiet te Dee pner te eet 7 22 7 4 1 5 Status Register some Eco he tanta 7 24 7 4 1 6 Clock Select Register CSR sees 7 26 7 4 1 7 Command Register CR s ois ut oet ettet 7 27 7 4 1 8 Receiver Buffer eite eget recent ie tede Seite 7 30 7 4 1 9 Trarismiltet BUlter TB oa titudo doter diit tee 7 30 7 4 1 10 Input Port Change Register
204. IM40 clock is driven from an external crystal or oscillator and the VCO is turned off to conserve power STEXT Stop Mode External Clock 1 When the LPSTOP instruction is executed the external clock pin CLKOUT is driven from the SIM40 clock as determined by the STSIM bit 0 When the LPSTOP instruction is executed the external clock CLKOUT is held low to conserve power No external clock will be driven in LPSTOP mode 4 3 4 Chip Select Registers The following paragraphs provide descriptions of the registers in the chip select function and an example of how to program the registers The chip select registers cannot be used until the V bit in the MBAR is set MOTOROLA MC68340 USER S MANUAL 4 29 4 3 4 1 BASE ADDRESS REGISTERS There are four 32 bit base address registers in the chip select function one for each chip select signal Base Address 1 044 04C 054 05C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET U U U U U U U U U U U U U U U U Supervisor Only Base Address 2 046 04E 056 05E 3l 30 29 28 21 26 25 24 23 22 2 20 19 18 17 16 RESET U U U U U U U U U U U U U U 0 0 U Unaffected by reset Supervisor Only BA31 BA8 Base Address Bits 31 8 The base address field the upper 24 bits of each base address register selects the starting address for the chip select The specified base address must be on a multiple of the selected block size The corresponding bits 1 8 in the address m
205. Input Capture Output Compare for additional information on this mode 8 2 MC68340 USER S MANUAL MOTOROLA TIMER EXTERNAL INTERFACE MODULE CONFIGURATION REGISTER INTERRUPT REGISTER CONTROL REGISTER STATUS REGISTER PRELOAD 1 REGISTER CLOCK SYSTEM CLOCK SELECTED CLOCK 8 BIT PRESCALER COUNTER REGISTER E TIMEOUT 16 BIT COMPARE REGISTER Figure 8 2 Timer Functional Diagram COUNTER CLOCK 8 1 1 4 CLOCK SELECTION LOGIC The clock selection logic consists of two multiplexers that select the clocks applied to the prescaler and counter The first multiplexer labeled clock logic in Figure 8 2 selects between the clock input to the timer TINx or one half the frequency of the system clock CLKOUT This output of the first multiplexer called selected clock is applied to both the 8 bit prescaler and the second multiplexer The second multiplexer selects the clock for the 16 bit counter which is either the selected clock or the 8 bit prescaler output 8 1 2 Internal Control Logic The timer receives operation commands on the IMB and in turn issues appropriate operation signals to the internal timer control logic This mechanism allows the timer registers to be accessed and programmed Refer to 8 4 Register Description for additional information MOTOROLA MC68340 USER S MANUAL 8 3 8 1 3 Interrupt Control Logic Each timer provides seven interrupt request outputs IRQ7 IRQ1 to noti
206. Interrupts by Sources in the SIMAO 4 9 4 2 3 Clock Synthesizer 2 44440 00 0 4 9 4 2 3 1 Phase Comparator and Filter eese 4 11 4 2 3 2 Freg ency Divide et bod outer 4 12 4 2 3 3 Glock GAL OM esac ech ac sin tete 4 13 4 2 4 Ghip Select zoo ee pa Ucet peu adea p s 4 13 4 2 4 1 Programmable 22 0000 4 14 MC68340 USER S MANUAL MOTOROLA 11 2 95 Number 4 2 4 2 4 2 5 4 2 5 1 4 2 5 2 4 2 6 4 2 7 4 3 4 3 1 4 3 2 4 3 2 1 4 3 2 2 4 3 2 3 4 3 2 4 4 3 2 5 4 3 2 6 4 3 2 7 4 3 2 8 4 3 3 4 3 4 4 3 4 1 4 3 4 2 4 3 4 3 4 3 5 4 3 5 1 4 3 5 2 4 3 5 3 4 3 5 4 4 3 5 5 4 3 5 6 4 3 5 7 4 4 4 4 1 4 4 2 4 4 3 ann C1 MOTOROLA SECTION 1 OVERVIEW UM Rev 1 TABLE OF CONTENTS Continued Page Title Number Global Chip Select Operation esses 4 14 External Bus Interface Operation sess 4 15 sm 4 15 ND QUUD UNI IM 4 16 Low Power Stop t 1o dn idee added 4 17 Re 4 17 Programming 2 4 18 Module Base Address Register 4 20 Sys
207. L WING LEAD CONFIGURA 9 SNO MILLIMETE INCHE NOTES DIN MIN MA MID 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5N 25 8 27 7 1 01 1 09 2 CONTROLLING DIMENSION MILLIMETERS 25 8 27 7 1 01 1 09 3 DIMA AND B DEFINE MAXIMUM CERAMIC BODY DIMEN 3 5 43 0 14 0 17 INCLUDING GLASS PROTRUSION AND MISMATCH OF C D 02 04 0 00 0 01 BODY TOP AND BOTTOM G 0 65 BS 0 0256 B 4 DATUM PLANE W IS LOCATED AT THE UNDERSIDE C H 02 08 0 01 0 03 WHERE LEADS EXIT PACKAGE BODY J 01 02 0 00 0 01 5 DATUMS X Y AND Z TO BE DETERMINED WHERE CENT 06 09 0 02 0 03 EXIT PACKAGE BODY AT DATUM W M 0 8 0 8 6 DIM S AND V TO BE DETERMINED SEATING PLANE Q 0 325 BS 0 0128 Bt 7 DIMA AND TO BE DETERMINED DATUM PLANE 12 6 MC68340 USER S MANUAL MOTOROLA 12 3 2 RP Suffix 145 PIN PGA CASE NO 768E 01 gt 5 lt 0 N 000000000000 M K J BOTTOM H G F E D C oOo A o 15PL lt MILLIMETERS INCHES DIM MIN MAX MIN MAX 3937 3988 1550 1570 39 37 3988 1550 1570 2275 2297 0 895 0 905 22 75 2297 0 895 0 905 2 54 BASIC 0 100 BASIC 2 92 343 0 115 0 135 1 02 1 52 0 040 0 060 0 43 0 55 0 017 0 022 432 4 95 0 170 0 195 35 56 BASIC 1
208. LA MC68340 USER S MANUAL 3 45 State 0 During state 0 the 1 0 and FCx become valid R W is driven to indicate a show read or write cycle and the SIZx pins indicate the number of bytes to transfer During a read the addressed peripheral is driving the data bus and the user must take care to avoid bus conflicts State 41 One half clock cycle later DS rather than AS is asserted to indicate that address information is valid State 42 No action occurs in state 42 The bus controller remains in state 42 wait states will be inserted until the internal read cycle is complete State 43 When DS is negated show data is valid on the next falling edge of the system clock The external data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus State 0 1 0 FCx R W and SIZx pins change to begin the next cycle Data from the preceding cycle is valid through state O S0 541 542 543 50 51 52 _ Nf NN A31 A0 5121 5120 N e show CYCLE 9 START OF EXTERNAL CYCLE Figure 3 26 Show Cycle Timing Diagram 3 7 RESET OPERATION The MC68340 has reset control logic to determine the cause of reset synchronize it if necessary and assert the appropriate reset lines The reset control logic can independently drive three different lines 1 EXTRST external reset drives the external RESET pin 2 CLKRST clock reset resets the
209. MAO it will prioritize and service the interrupts in the following order 1 software watchdog 2 periodic interrupt timer and 3 external interrupts 4 2 3 Clock Synthesizer Operation The clock synthesizer can operate with either an external crystal or an external oscillator for reference using the internal phase locked loop PLL and voltage controlled oscillator VCO or an external clock can directly drive the clock signal at the operating frequency The four modes of clock operation are listed in Table 4 1 Table 4 1 Clock Operating Modes MODCK VCCSYN Description Reset Operating Value Value External crystal or oscillator used with the on chip PLL and VCO to Crystal Mode generate a system clock and CLKOUT of programmable rates 5V 5V External Clock The desired operating frequency is driven into EXTAL resulting in a Mode without PLL system clock and CLKOUT of the same frequency not tightly coupled OV OV The desired operating frequency is driven into EXTAL resulting in a External Clock system clock and CLKOUT of the same frequency with a tight skew Mode with PLL between input and output signals OV 5V Upon input signal loss for either clock mode using the PLL operation continues at approximately one half operating speed affected by the Limp Mode value of the X bit in the SYNCR X 5V In crystal mode see Figure 4 4 the clock synthesizer can operate from the on chip PLL and VCO using a parallel resonant crystal connected
210. MC68340 USER S MANUAL MOTOROLA last falling edge of the clock for that bus cycle For a write cycle all 16 bits of the data bus are driven regardless of the port width or operand size The MC68340 places the data on the data bus approximately one half clock cycle after AS is asserted in a write cycle 2 4 FUNCTION CODES FC3 FCO These signals are outputs that indicate one of 16 address spaces to which the address applies Fifteen of these spaces are designated as either user or supervisor program or data and normal or direct memory access DMA spaces One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles The function code signals are valid while AS is asserted See Table 2 2 for more information Table 2 2 Address Space Encoding 3 2 o Address spaces po o o o Reserved Motorola o o o QuseDaaSpae o o t o UserProgram Space o o e 3 s 1 0 1 3 1 0 rer Prom oce 2 5 CHIP SELECTS 53 50 These pins be programmed to be chip select output signals port B parallel I O and autovector input or additional interrupt request lines Refer to Section 4 System Integration Module for more information on these signals CS3 CSO The chip select o
211. MCR 6 40 MC68340 USER S MANUAL MOTOROLA Normal Operation ignore FREEZE dual address mode ISM field at 3 Make sure CPU32 SR 12 10 bits are less than or equal to ISM bits for channel startup Supervisor user reg unrestricted MAID field at IARB priority at 4 MOVE W 0334 A0 Clear channel control reg Clear STR start bit to prevent the channel from starting a transfer early CLR W DMACCR1 A0 nitialize interrupt reg Interrupt priority at 7 interrupt vector at 42 MOVE W _ 4 0742 DMAINT1 0 nitialize channel status reg Clear the DONE BES BED CONF and BRKP bits to allow channel to startup MOVE B 7C DMACSR1 A0 Initialize function code reg DMA space supervisor data space for source and destination MOVE B DD DMAFCR1 A0 Initialize source operand address Source address is equal to 6000 MOVE L SARADD DMASAR1 A0 Initialize destination operand address Destination address is equal to 8000 MOVE L DARADD DMADAR1 A0 Initialize the byte transfer count reg The number of bytes to be transferred is E or 7 words MOVE L NUMBYTE DMABTC1 A0 Channel control reg init and Start DMA transfers No interrupts are enabled destination write cycle Increment source and destination addresses source size is word destination size is word REQ is internal 100 of bus bandwidth dual address transfers start the DMA transfers MOVE W 4 0E8D DMACCR1 0 kkkkkk
212. MODCK Selects the source of the internal system clock upon reset In I O Port BO or becomes a parallel I O port Instruction Fetch IFETCH DSI Indicates when the CPU32 is performing an instruction Out In Development Serial In word prefetch and when the instruction pipeline has been flushed or provides background debug mode serial in Instruction Pipe IPIPE DSO Used to track movement of words through the instruction Out Out Development Serial Out pipeline or provides background debug mode serial out Breakpoint Development BKPT DSCLK Signals a hardware breakpoint to the CPUS2 or provides In Serial Clock background debug mode serial clock FREEZE Indicates that the CPU32 has entered background debug mode Transmit Data TxDA TxDB Transmitter serial data output from the serial module Clear to Send CTSA CTSB Serial module clear to send inputs Request to Send RTSB RTSA Channel request to send outputs or discrete outputs Out Out OP1 OPO Serial Crystal Oscillator X1 X2 Connections for an external crystal to the serial module internal oscillator circuit Serial Clock SCLK External serial module clock input Transmitter Ready OP6 T RDYA Indicates transmit buffer has a character or becomes a Out Out parallel output Receiver Ready R RDYA Indicates receive buffer has a character the receiver Out Out Out FIFO Full OP4 FIFO buffer is full or becomes a parallel output Output that signals an access during DMA DMA Request
213. MOTOROLA MC68340 USER S MANUAL ii 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Continued Paragraph Page Number Title Number 2 7 Bus Control SIghals eo ic etes 2 6 2 7 1 Data and Size Acknowledge DSACK1 2 6 2 7 2 Address Stroba esc aac duce Diae Ma Ast Ind oA Eres 2 6 2 7 3 Data Strobe DS et dro en oC Ud advo eo tou PURA EE 2 7 2 7 4 Transfer Size 51 1 9120 te psi tene 2 7 2 7 5 Read Write EUM Sas ai a uta md tust cus a 2 7 2 8 Bus Arbitration Signals 2 7 2 8 1 Bus Request sem ista cos nar o n i d emu fe os 2 7 2 8 2 Bis Grant aso ica cater be tot a 2 7 2 8 3 Bus Grant Acknowledge BGAQCK sss 2 7 2 8 4 Read Modify Write Cycle RMO esses 2 8 2 9 Exception Control SIgrials u reo aec eese rto erede 2 8 2 9 1 ud nes MM M 2 8 2 9 2 s Pessina oen d orbe bep NOn 2 8 2 9 3 BUS Eror BEI is tua stets deu RUM UR 2 8 2 10 MOGI CIAL ice c S 2 8 2 10 1 System Clock 2a ale iat 2 8 2 10 2 Crystal Oscillator EX TAL X TAL ah itat teria ipo aiti mean 2 9 2 10 3 External Filter Capacitor AEG
214. MTO Bus Monitor Timeout Period 0 o 64 system clocks CLKOUT 32 system clocks 5 s 4 3 2 6 PERIODIC INTERRUPT CONTROL REGISTER PICR The PICR contains the interrupt level and the vector number for the periodic interrupt request This register can be read or written at any time Bits 15 11 are unimplemented and always return zero a write to these bits has no effect PICR 022 15 M 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIRQL2 PIRQL1 PIRQLO PIV7 PIV6 PIV5 PIV4 PIV3 PIV2 PIV1 PIVO RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Supervisor Only Bits 15 11 Reserved PIRQL2 PIRQLO Periodic Interrupt Request Level These bits contain the periodic interrupt request level Table 4 9 lists which interrupt request level is asserted during an IACK cycle when a periodic interrupt is generated The periodic timer continues to run when the interrupt is disabled Table 4 9 PIRQL Encoding 0 Perodie merupt Disabled o interrupt Request Level o interrupt Request Lova o Request Loves NOTE Use caution with a level 7 interrupt encoding due to the SIM40 s interrupt servicing order See 4 2 2 7 Simultaneous Interrupts by Sources in the SIM40 for the servicing order o UNE E RECONNUE oi 4 26 MC68340 USER S MANUAL MOTOROLA PIV7 PIVO Periodic Interrupt Vector Bits 7 0 These
215. N ENABLE START STOP NO EFFECT COUNTING COUNTING MODEx Bits in Control Register 100 TGE Bit of Control Register 1 Figure 8 8 Pulse Width Measurement Mode If the counter counts down to the value stored in the COM register the COM and TC bits in the SR are set If the counter counts down to 0000 a timeout is detected This sets the SR TO and the clears the COM bit At timeout the next falling edge of the counter clock 8 12 MC68340 USER S MANUAL MOTOROLA causes the counter to reload with FFFF TOUTx transitions at timeout or is disabled as programmed by the CR bits The SR OUT bit reflects the level on TOUTx To determine the number of cycles counted the value in the CNTR must be read inverted and incremented by 1 the first count is FFFF which in effect includes a count of zero The counter counts in a true 216 fashion For measuring pulses of even greater duration the value in the POx bits in the SR is readable and can be thought of as an extension of the least significant bits in the CNTR NOTE Once the timer has been enabled do not clear the SR TG bit until the pulse has been measured and TGATE has been negated 8 3 6 Period Measurement This mode is used to count the period of a particular event The event is defined by the assertion negation and subsequent reassertion of TGATE When is asserted the counter begins counting down from FFFF The negation of TGATE h
216. NUAL MOTOROLA 3 2 3 3 BYTE OPERAND 16 BIT PORT ODD 0 1 The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single byte operand BYTE OPERAND 7 0 DATA BUS D15 08 D7 DO 5121 5120 A0 1 DSACKO CYCLE1 0 0 0 1 1 0 X For a read operation the slave responds by placing data on bits 7 0 of the data bus and asserting DSACK1 to indicate a 16 bit port The MC68340 then reads the operand byte from bits 7 0 and ignores bits 15 8 For a write operation the MC68340 drives the single byte operand on both bytes of the data bus because it does not know the port size until the DSACK signals are read The slave device reads the operand from bits 7 0 of the data bus and uses the address to place the operand in the specified location The slave then asserts DSACK1 to terminate the bus cycle 3 2 3 4 WORD OPERAND TO 8 BIT PORT ALIGNED The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a word operand WORDOPERAND opo 0 1 15 87 0 DATA BUS 015 D8D7 DO SIZi SIZO 0 DSACK DSACKO opo OP 1 0 0 1 0 CYCLE 2 0 1 1 1 0 For a read operation the slave responds by placing the most significant byte of the operand on bits 15 8 of the data bus and asserting DSACKO to indicate an 8 bit port The MC68340 reads the most significant byte of the operand from bits 15 8 and ignores bits 7 0 The M
217. OROLA MC68340 USER S MANUAL 3 39 occurs during the stacking operation the second error is considered a double bus fault When a double bus fault occurs the MC68340 halts and asserts HALT Only a reset operation can restart a halted MC68340 However bus arbitration can still occur see 3 6 Bus Arbitration A second bus error or address error that occurs after exception processing has completed during the execution of the exception handler routine or later does not cause a double bus fault A bus cycle that is retried does not constitute a bus error or contribute to a double bus fault The MC68340 continues to retry the same bus cycle as long as the external hardware requests it Reset can also be generated internally by the halt monitor see Section 5 CPU32 3 6 BUS ARBITRATION The bus design of the MC68340 provides for a single bus master at any one time either the MC68340 or an external device One or more of the external devices on the bus can have the capability of becoming bus master for the external bus but not the MC68340 internal bus Bus arbitration is the protocol by which an external device becomes bus master the bus controller in the MC68340 manages the bus arbitration signals so that the MC68340 has the lowest priority External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following paragraphs Systems having several devices that can become bus master require exter
218. OT COMPLETED NEXT COMMAND gt XX NJ CODE NOT READY XXX NEXT CMD MS RESULT LS RESULT XXX NEXT CMD BERR AERR NOT READY SEQUENCE TAKEN IF BUS ERROR OR ADDRESS ERROR OCCURS ON MEMORY ACCESS HIGH AND LOW ORDER 16 BITS OF RESULT Figure 5 27 Command Sequence Diagram 5 6 2 8 3 Command Set Summary The BDM command set is summarized in Table 5 23 Subsequent paragraphs contain detailed descriptions of each command MOTOROLA MC68340 USER S MANUAL 5 75 Table 5 23 BDM Command Summary command Read A D Register RAREG RDREG Read the selected address or data register and return the results via the serial interface Write A D Register WAREG WDREG The data operand is written to the specified address or data register Read System Register RSREG The specified system control register is read All registers that can be read in supervisor mode can be read in BDM Write System Register WSREG The operand data is written into the specified system control register Read Memory Location READ Read the sized data at the memory location specified by the long word address The SFC register determines the address space accessed Write Memory Location WRITE Write the operand data to the memory location specified by the long word address The DFC register determines the address space accessed Dump Memory Block DUMP Used in conjunction with the READ command to
219. OUT DACKx N N DONEx N OUTPUT NOTE 1 To cause another DMA transfer the DREQx is asserted after DACKx is asserted and before DACKx is negated 2 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle Figure 6 14 Fast Termination Option External Burst Source Requesting 6 7 REGISTER DESCRIPTION The following paragraphs contain a detailed description of each register and its specific function Figure 6 15 is a programmer s model register map of all registers in the DMA module Each channel has an independent set of registers For more information about a particular register refer to the individual register description The ADDRESS column indicates the offset of the register from the base address of the DMA channel The FC column designation of S indicates that register access is restricted to supervisor only A designation of S U indicates that access is governed by the SUPV bit in the module configuration register MCR Unimplemented memory locations return logic zero when accessed All registers support both byte and word transfers 6 22 MC68340 USER S MANUAL MOTOROLA ADDRESS FC CH1 CH2 15 8 7 0 Figure 6 15 DMA Module Programming Model In the registers discussed in the following paragraphs the numbers in the upper right hand corner indicate the offset of the register from the base address specified by the module base address register MBAR i
220. Op FEA Dn DI o2 o smo U I DINEM a a M TERM sp gos DIVS L Save Dn 3 0 1 0 DIVS L Op TBL su TBL su Save TBL su Op TBLSN Save TBLSN Op MOTOROLA FEA Dn Dn Dm Dp CEA Dn Dn CEA Dn CEA Dn 26 o 7179 cese m 10 MC68340 USER S MANUAL 46 52 0 1 0 lt 46 0 1 0 28 30 0 2 0 5 103 5 104 Head Tal Cycles __ d ur 5 1 TBLUN CEA Dn 3 0 1 0 TBLUN Op CEA Dn 6 o 9 45 2 1 0 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles Maximum time certain data or mode combinations may execute faster su The execution time is identical for signed or unsigned operands These instructions have an additional save operation that other instructions do not have To calculate total instruction time calculate save ea and operation execution times then combine in the order shown using equations in 5 7 1 6 Instruction Execution Time Calculations A save operation is not run for long word divide and multiply instructions when FEA Dn MC68340 USER S MANUAL MOTOROLA 5 7 3 6 IMMEDIATE ARITHMETIC LOGIC INSTRUCTIONS The immediate arithmetic logic in
221. Pulse Width Measurementt ccecceeceeeeeseceeeeeeeeeeeeeeeaeeeaeeeeeeeeeeeeeaeeeaeesees 8 12 Period Measurement cene ete n xr OC 8 13 ecco as crise tu sp Cu t etai 8 14 DD LL 8 16 Bus 6o scie RR TNR HO 8 17 Read Gy6lo8 estt utes D 8 17 Write Cycles out esee ntis Etc e Led 8 17 Interrupt Acknowledge Cycles esses 8 17 Regisiter DeSOCHDHODL s eie ad eR eec e eroe 8 17 Module Configuration Register 8 18 ein uh eee 8 20 Control Register GR Sheetal 8 20 t 8 23 GounterHegister sso ec tie Sara dh ste ttes 8 25 Preload 1 Register PBELT u seti ie 8 25 Preload 2 Register 2 8 26 Compare Register onere uincere utm 8 26 Timer Module Initialization Sequence sess 8 27 Timer Module ColHfIQBIl atiOD tassi toe SE Ca eec Rt ben Re 8 27 Timer Module Example Configuration 8 28 Section 9 IEEE 1149 1 Test Access Port i ico t tc 9 1 TAR Controllera Dno LEM ES UE 9 2 Boundary Scan Register
222. ROLA 10 3 2 MC68340V 3 3 V The 68340 can operate with a 3 3 V power supply for significant power savings The formula for power dissipation is Pg V2 x f dc Table 10 2 shows typical electrical characteristics for both the MC68340 and MC68340V Table 10 2 Typical Electrical Characteristics 68340 5 0 V MC68340V 3 3 V Clock Frequency 0 16 78 MHz 0 8 39 MHz 0 25 MHz 0 16 78 MHz Typical Current 8 MHz Standby Current 60 uA 25 uA Running at 3 3 V saves 66 of the power consumption The 3 3 V operation provides the following user advantages Advantage Lower Supply Voltage Fewer Batteries Fewer Batteries Less Weight Smaller Size Lower Current Drain Extended Battery Life Less Heat Generated No Fan No Fan Noise Less EMF Radiation Easier FCC Certification Less Crosstalk Closer PCB Traces High Functional Integration All In One 3 3 V Part Processor Peripherals Glue Logic These advantages result in a much more portable system MOTOROLA MC68340 USER S MANUAL 10 13 SECTION 11 ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations DC AC electrical characteristics and AC timing specifications of the MC68340 Refer to Section 12 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage frequency and temperature ratings 11 1 MAXIMUM RATINGS Rang Supply Voltage 1 2 Input Voltage 2 0 3 to 46
223. RS BDM processing uses three special purpose registers to track program context during development A description of each register follows 5 6 2 5 1 Fault Address Register FAR The FAR contains the address of the faulting bus cycle immediately following a bus or address error This address remains available until overwritten by a subsequent bus cycle Following a double bus fault the FAR contains the address of the last bus cycle The address of the first fault if one occurred is not visible to the user 5 6 2 5 2 Return Program Counter RPC The RPC points to the location where fetching will commence after transition from BDM to normal mode This register should be accessed to change the flow of a program under development Changing the RPC to an odd value will cause an address error when normal mode prefetching begins 5 6 2 5 3 Current Instruction Program Counter PCC The PCC holds a pointer to the first word of the last instruction executed prior to transition into BDM Due to instruction pipelining the instruction pointed to may not be the instruction which caused the transition An example is a breakpoint on a released write The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer A BKPT asserted during this cycle will not be acknowledged until the end of the instruction MOTOROLA MC68340 USER S MANUAL 5 67 executing at completion of the bus cycle PCC will contain 00000001 if BDM
224. Read Timing External Burst 6 8 6 6 Single Address Read Timing Cycle 6 9 6 7 Single Address Write Timing External 6 10 6 8 Single Address Write Timing Cycle 6 11 6 9 Dual Address Read Timing External Burst Source Requesting 6 13 6 10 Dual Address Read Timing Cycle Steal Source Requesting 6 14 6 11 Dual Address Write Timing External Burst Destination Requesting 6 16 6 12 Dual Address Write Timing Cycle Steal Destination Requesting 6 17 6 13 Fast Termination Option Cycle 6 21 6 14 Fast Termination Option External Burst Source Requesting 6 22 6 15 Module Programming Model essent 6 23 6 16 Packing and Unpacking of Operands sex esee ice erect 6 35 7 1 Simplified Block 0 222220244 7 1 7 2 External and Internal Interface Signals sss 7 5 7 3 Baud Rate Generator Block Diagram sse 7 8 7 4 Transmitter and Receiver Functional 7 9 7 5 Transmitter Timing Diagram nte 7 10 7 6 Diagram a tte
225. Refer to 5 5 2 1 Reset for details of reset processing As exception processing begins the processor makes an internal copy of the SR After the copy is made the processor state bits in the SR are changed the S bit is set establishing supervisor access level and bits T1 and TO are cleared disabling tracing For reset and interrupt exceptions the interrupt priority mask is also updated Next the exception number is obtained For interrupts the number is fetched from CPU space F the bus cycle is an interrupt acknowledge For all other exceptions internal logic provides a vector number Next current processor status is saved An exception stack frame is created and placed on the supervisor stack All stack frames contain copies of the SR and the PC for use by RTE The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame 5 40 MC68340 USER S MANUAL MOTOROLA Finally the processor prepares to resume normal execution of instructions The exception vector offset is determined by multiplying the vector number by 4 and the offset is added to the contents of the VBR to determine displacement into the exception vector table The exception vector is loaded into the PC If no other exception is pending the processor will resume normal execution at the new address in the PC 5 5 1 3 EXCEPTION STACK FRAME During exception processing the most volatile portion of the cur
226. Request Transfers cccccecessceseeeeeeeseeeeeeeeeeeeeeenensaeeeaeeaeesees 6 19 6 6 3 Channel 6 20 6 6 3 1 Channel Terminations 6 20 6 6 3 2 Spe Trio 6 20 6 6 3 3 Fast 6 20 6 7 Register Description m 6 22 6 7 1 Module Configuration Register 6 23 6 7 2 Interrupt Register eos ero tee E ot e au 6 26 6 7 3 Channel Control Register CCR essen 6 26 6 7 4 Channel Status Register CSR sist ec tet otra eate uu t 6 30 6 7 5 Function Code Register FCR essen 6 32 6 7 6 Source Address Register SAR sse 6 33 6 7 7 Destination Address Register DAR sess 6 33 6 7 8 Byte Transfer Counter Register BTC 6 34 6 8 Data ione aut IE 6 35 6 9 DMA Channel Initialization Sequence sss 6 36 6 9 1 DMA Channel Configuration 6 36 6 9 1 1 DMA Channel Operation in Single Address 6 37 6 9 1 2 DMA Channel Operation in Dual Address Mode 6 37 6 9 2 DMA Channel Example Configuration Code
227. Rn If Rn gt upper bound then TRAP 0 Destination CLR ea Destination Source cc CMP ea Dn CMPA Destination Source Destination Immediate Data CMPI 4 data ea CMPM Destination Source cc CMPM Ay Ax 5 16 MC68340 USER S MANUAL MOTOROLA Table 5 2 Instruction Set Summary Continued CMP2 Compare Rn lower bound or 2 ea Rn gt upper bound Set Condition Codes If condition false then Dn 1 Dn DBcc Dn label If Dn 1 then PC d 2 PC DIVS Destination Source Destination DIVS W ea Dn 32 16 16r 16q DIVSL DIVS L ea Dq 32 32 32q DIVS L ea Dr Dq 64 32 32r 32q DIVSL L ea Dr Dq 32 32 32r 32q DIVU Destination Source Destination DIVU W ea Dn 32 16 2 16r 16q DIVUL DIVU L 32 32 32q DIVU L ea Dr Dq 64 32 32r 32q DIVUL L ea Dr Dq 32 32 32r 32q EOR Source Destination Destination EOR Dn ea Immediate Data Destination Destination EORI data ea Source CCR CCR EORI lt data CCR to CCR EORI If supervisor state EORI data SR to SR the Source 6 SR SR else TRAP EXG Rx Ry EXG Dx Dy EXG Ax Ay EXG Dx Ay EXG Ay Dx EXT Destination Sign Extended Destination EXT WDn extend byte to word EXTB EXT LDn extend word to long word EXTB LDn extend byte to long word SSP 2 SSP Vector Offset SSP ILLEGAL SSP 4 gt SSP PC SSP SSp 2 gt SSP SR gt
228. SE Illegal Instruction Vector Address PC MP Destination Address gt JMP ea JSR SP 4 gt SP PC SP JSR ea Destination Address PC LEA Gs An LINK SP 4 gt SP An SP LINK An displacement SP gt SP d gt SP LPSTOP If supervisor state LPSTOP lt data Immediate Data SR Interrupt Mask External Bus Interface EBI STOP else TRAP LSL LSR Destination Shifted by count Destination LSd Dx Dy 1501 data Dy 1501 ea MOVE Source gt Destination MOVE MOVEA Source gt Destination MOVEA MOVE from CCR Destination MOVE CCR ea CCR MOTOROLA MC68340 USER S MANUAL 5 17 Table 5 2 Instruction Set Summary Continued MOVE to CCR Source 2 CCR MOVE ea CCR MOVE from SR If supervisor state MOVE SR ea then SR Destination else TRAP MOVE to SR If supervisor state MOVE ea SR then Source SR else TRAP MOVE USP If supervisor state MOVE USP An then USP An or An USP MOVE An USP else TRAP MOVEC If supervisor state MOVEC Rc Rn then Rc Rn or Rn gt Rc MOVEC Rn Rc else TRAP MOVEM Registers Destination MOVEM register list ea Source Registers MOVEM ea register list MOVEP Source Destination MOVEP Dx d Ay MOVEP d Ay Dx MOVEQ Immediate Data Destination MOVEQ data Dn MOVES If supervisor state MOVES then Rn 2 Destination DFC or Source MOVES ea Rn SFC Rn else TRAP MULS Source x Destination D
229. T CONTROL REGISTER PICR PERIODIC INTERRUPT TIMING REGISTER PITR SYPCR RESERVED SOFTWARE SERVICE SWSR Figure 4 8 SIM40 Programming Model MC68340 USER S MANUAL SYSTEM PROTECTION CONTROL SYSTEM PROTECTION CLOCK SYSTEM PROTECTION EBI SYSTEM PROTECTION SYSTEM PROTECTION SYSTEM PROTECTION SYSTEM PROTECTION CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT 4 19 4 3 1 Module Base Address Register MBAR MBAR 1 0003FF00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only MBAR 2 0003FF02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bars sars paz o o ase asz ase ass ase ass ase asi v RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPU Space Only BA31 BA12 Base Address Bits 31 12 The base address field is the upper 20 bits of the MBAR that provides for block starting locations in increments of 4 Kbytes Bits 11 10 Reserved AS8 AS0 Address Space Bits 8 0 The address space field allows particular address spaces to be masked placing the 4K module block into a particular address space s If an address space is masked an access to the register block location in that address space becomes an
230. T as an Output Port 8 16 8 17 V Bit 4 14 4 15 4 20 4 31 4 36 Variable Duty Cycle Square Wave Generator 8 9 8 10 Variable Width Single Shot Pulse Generator 8 10 8 12 VCCSYN 2 13 4 9 4 11 10 2 10 3 Vector Base Register 5 4 5 10 5 39 5 41 5 43 Vector Numbers 5 34 5 40 Virtual Memory 5 2 Voltage Controlled Oscillator 4 9 4 12 4 28 4 29 10 1 10 2 W W Bit 4 10 4 12 4 13 4 28 4 36 Wait States 3 14 3 16 3 20 4 1 4 14 4 15 4 17 4 32 Wakeup Mode 7 15 Word Operands 5 12 WP Bit 4 14 Write A D Register Command 5 77 5 79 Cycle Word Flowchart 3 18 Memory Location Command 5 79 5 80 System Register Command 5 78 5 79 Write Pending Buffer 5 91 que X Bit 4 9 4 11 4 13 4 28 4 36 X1 Signal 2 11 7 5 X2 Signal 2 11 7 5 XFC Pin 2 9 4 12 10 2 10 3 XTAL Pin 2 9 4 9 4 11 10 1 10 2 XTAL_RDY Bit 7 4 7 26 7 33 7 34 7 46 MOTOROLA iA Y Bits 4 12 4 13 4 28 4 36 Zero Mode 8 23 MOTOROLA MC68340 USER S MANUAL Index 9
231. TER BUFFER A TBA 714 INPUT PORT CHANGE REGISTER IPCR AUXILIARY CONTROL REGISTER ACR 755 SU INTERRUPT STATUS REGISTER ISR INTERRUPT ENABLE REGISTER IER 716 S U DO NOT ACCESS DO NOT ACCESS 717 S U DO NOT ACCESS DO NOT ACCESS 78 85 0 MODE REGISTER 1B MR1B MODE REGISTER 1B MR1B 79 5 STATUS REGISTER B SRB CLOCK SELECT REGISTER B CSRB 7A X SU COMMAND REGISTER B CRB 7B 5 0 RECEIVER BUFFER B RBB TRANSMITTER BUFFER B TBB 7C S U DO NOT ACCESS DO NOT ACCESS 71D S U INPUT PORT REGISTER IP OUTPUT PORT CONTROL REGISTER OPCR 71 S U DO NOT ACCESS OUTPUT PORT OP BIT SET 71 S U DO NOT ACCESS OUTPUT PORT BIT RESET 720 S U MODE REGISTER 2A MR2A MODE REGISTER 2A MR2A 721 S U MODE REGISTER 2B MR2B MODE REGISTER 2B MR2B NOTES 1 S Register permanently defined as supervisor only access 2 5 0 Register programmable as either supervisor or user access 3 Areador write to these locations currently has no effect 4 Address triggered commands Figure 7 9 Serial Module Programming Model 7 4 1 1 MODULE CONFIGURATION REGISTER MCR The MCR controls the serial module configuration This register can be either read or written when the module is enabled and is in the supervisor state The MCR is not affected by a CPU32 RESET instruction Only the MCR can be accessed when the module is disabled i e the STP bit in the MCR is set MCR 700 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 on 0 0 0 0 0
232. TUS REGISTER PROGRAM COUNTER ALTERNATE FUNCTION CODE REGISTERS Figure 5 4 Supervisor Programming Model Supplement MC68340 USER S MANUAL 59 5 2 2 Registers Registers 07 00 are used as data registers for bit byte 8 bit word 16 bit long word 32 bit and quad word 64 bit operations Registers A6 to 0 and the USP and SSP are address registers that may be used as software SPs or base address registers Register shown as A7 and 7 in Figures 5 3 and 5 4 is a register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level In addition address registers may be used for word and long word operations All of the 16 general purpose registers 07 00 A7 A0 may be used as index registers The PC contains the address of the next instruction to be executed by the CPU32 During instruction execution and exception processing the processor automatically increments the contents of the PC or places a new value in the PC as appropriate The SR see Figure 5 5 contains condition codes an interrupt priority mask three bits and three control bits Condition codes reflect the results of a previous operation The codes are contained in the low byte CCR of the SR The interrupt priority mask determines the level of priority an interrupt must have to be acknowledged The control bits determine trace mode and privilege level At user privilege level only the CCR is a
233. TYPES OF FAULTS An efficient implementation of instruction restart dictates that faults on some bus cycles be treated differently than faults on other bus cycles The 32 defines four fault types released write faults faults during exception processing faults during MOVEM operand transfer and faults on any other bus cycle 5 5 3 1 1 Type I Released Write Faults CPUS2 instruction pipelining can cause a final instruction write to overlap the execution of a following instruction A write that is overlapped is called a released write A released write fault occurs when a bus error or some other fault occurs on the released write Released write faults are taken at the next instruction boundary The stacked PC is that of the next unexecuted instruction If a subsequent instruction attempts an operand access while a released write fault is pending the instruction is aborted and the write fault is acknowledged This action prevents stale data from being used by the instruction 5 54 MC68340 USER S MANUAL MOTOROLA The SSW for a released write fault contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 pojoyj mjs sm t oj oj oj tao sz TR B1 and BO are set if the corresponding exception is pending when the bus error exception is taken Status regarding the faulted bus cycle is reflected in the LG SIZ and FUNC fields The remainder of the stack contains the PC of the next unexecuted instruction the curr
234. Timing MOTOROLA MC68340 USER S MANUAL 315 3 3 DATA TRANSFER CYCLES The transfer of data between the MC68340 and other devices involves the following signals Address Bus 1 0 Data Bus D15 DO Control Signals The address bus and data bus are parallel nonmultiplexed buses The bus master moves data on the bus by issuing control signals and the bus uses a handshake protocol to ensure correct movement of the data In all bus cycles the bus master is responsible for de skewing all signals it issues at both the start and end of the cycle In addition the bus master is responsible for de skewing the acknowledge and data signals from the slave devices The following paragraphs define read write and read modify write cycle operations Each bus cycle is defined as a succession of states that apply to the bus operation These states are different from the MC68340 states described for the CPU32 The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency Bus operations are described in terms of external bus states 3 3 1 Read Cycle During a read cycle the MC68340 receives data from a memory or peripheral device If the instruction specifies a long word or word operation the MC68340 attempts to read two bytes at once For a byte operation the MC68340 reads one byte The section of the data bus from which each byte is read depends on the operand size address sign
235. UAL 6 45 SECTION 7 SERIAL MODULE The MC68340 serial module is a dual universal asynchronous synchronous receiver transmitter that interfaces directly to the CPUS2 processor via the intermodule bus IMB The serial module shown in Figure 7 1 consists of the following major functional areas Two Independent Serial Communication Channels A and B Baud Rate Generator Logic Internal Channel Control Logic Interrupt Control Logic SERIAL COMMUNICATIONS RxRDYA CHANNELS A AND B TxRDYA X1 BAUD RATE GENERATOR LOGIC SCLK INTERNAL CHANNEL CONTROL LOGIC INTERRUPT CONTROL LOGIC Figure 7 1 Simplified Block Diagram MOTOROLA MC68340 USER S MANUAL 7 1 7 1 MODULE OVERVIEW Features of the serial module are as follows 7 2 Two Independent Full Duplex Asynchronous Synchronous Receiver Transmitter Channels Maximum Data Transfer Rate 1x mode 3 Mbps 8 39 MHz CLKOUT 9 8 Mbps 925 MHz CLKOUT 16x mode 188 kbps 9 8 39 MHz CLKOUT 612 kbps 925 MHz CLKOUT Quadruple Buffered Receiver Double Buffered Transmitter Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable from 19 Fixed Rates 50 to 76 8k Baud External 1x Clock or 16x Clock Programmable Data Format Five to Eight Data Bits Plus Parity Even No Parity or Force Parity Nine Sixteenths to Two Stop Bits Programmable in One Sixteenth Bit Increments Programmable Channel Modes Norma
236. Writes x 2 Clocks Write 6 Clocks of Bus Activity The number of internal clocks not overlapped by bus activity is as follows 10 Clocks Total 6 Clocks Bus Activity 4 Internal Clocks Memory read requires two bus cycles at two clocks each This read time implied in the tail figure for the EA cannot be overlapped with the instruction because the instruction has a head of zero An additional two clocks are required for the ADD instruction itself The total is 6 4 2 12 clocks If bus cycles take more time i e the memory is off chip add an appropriate number of clocks to each memory access The instruction sequence MOVE L DO 0 followed by LSL L 7 D2 provides an example of overlapped execution The MOVE instruction has a head of zero and a tail of four because it is a long write The LSL instruction has a head of four The trailing write from the MOVE overlaps the LSL head completely Thus the two instruction sequence has a head of zero and a tail of zero and a total execution of 8 rather than 12 clocks General observations regarding calculation of execution time are as follows Any time the number of bus cycles is listed as X substitute a value of one for byte and word cycles and a value of two for long cycles For long bus cycles usually add a value of two to the tail The time calculated for an instruction on a three clock or longer bus is usually longer than the actual execution time All times shown are for
237. accomplished by enabling the TO TG and or TC bits in the to generate interrupts by programming the CR IE bits When enabled the programmed signal is asserted whenever the specified bits set 8 3 3 Variable Duty Cycle Square Wave Generator In this mode both the PREL1 and PREL2 registers are used to generate a square wave with virtually any duty cycle The square wave is generated by counting down from the value in the PREL1 to timeout count value 0000 then loading that value from PREL2 and again counting down to timeout When this second timeout occurs the value from PREL1 is loaded into the counter and the cycle repeats TOUTx can be programmed to change state with every timeout thus generating a variable duty cycle square wave This mode can be selected by programming the MODE bits in the CR to 010 The timer is enabled by setting both the SWR and CPE bits in the CR and if TGATE is enabled CR TGE bit is set then asserting TGATE When the timer is enabled the ON bit in the SR is set On the next falling edge of the counter clock the counter is loaded with the value stored in the PREL1 register N1 With each successive falling edge of the counter clock the counter decrements The time between enabling the timer and the first timeout can range from N1 to N1 1 periods When TGATE is used to enable the timer the enabling of the timer is asynchronous however if timing is carefully considered the time to the fi
238. ail for the instruction is the tail for the operation Therefore the actual equation for execution time becomes Cop1 min HEA2 2 min TEA2 Hop2 Cop2 min Tope Heas Every instruction must prefetch to replace itself in the instruction pipe Usually these prefetches occur during or after an instruction A prefetch is permitted to begin in the first clock of any indexed EA mode operation Additionally a prefetch for an instruction is permitted to begin two clocks before the end of an instruction provided the bus is not being used If the bus is being used then the prefetch occurs at the next available time when the bus would otherwise be idle 5 7 1 7 EFFECTS OF NEGATIVE TAILS When the CPUS2 changes instruction flow the instruction decode pipeline must begin refilling before instruction execution can resume Refilling forces a two clock idle period at the end of the change of flow instruction This idle period can be used to prefetch an additional word on the new instruction path MOTOROLA MC68340 USER S MANUAL 5 93 Because of the stipulation that each instruction must prefetch to replace itself the concept of negative tails has been introduced to account for these free clocks on the bus On a two clock bus it is not necessary to adjust instruction timing to account for the potential extra prefetch The cycle times of the microsequencer and bus are matched and no additional benefit or penalty is ob
239. al unimplemented or privileged instruction while tracing is enabled no trace exception will occur because the instruction is not executed This is particularly important to an emulation routine that performs an instruction function adjusts the stacked PC to beyond the unimplemented instruction and then returns The SR on the stack must be checked to determine if tracing is on before the return is executed If tracing is on trace exception processing must be emulated so that the trace exception handler can account for the emulated instruction Tracing also affects normal operation of the STOP and LPSTOP instructions If either instruction begins execution with T1 set a trace exception will be taken after the instruction loads the SR Upon return from the trace handler routine execution will continue with the instruction following STOP LPSTOP and the processor will not enter the stopped condition 5 5 2 11 INTERRUPTS There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table Careful use of multiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor Interrupt recognition and subsequent processing are based on internal interrupt request signals IRQ7 IRQ1 and the current priority set in SR priority mask 12 10 Interrupt request level zero IRQ7 IRQ1 negated indicates that no service is requested When an inter
240. al AO and the port size Refer to 3 2 1 Dynamic Bus Sizing and 3 2 2 Misaligned Operands for more information Figure 3 7 is a flowchart of a word read cycle BUS MASTER SLAVE ADDRESS DEVICE SET RW TO READ DRIVE ADDRESS ON A31 A0 DRIVE FUNCTION CODE ON FC3 FCO DRIVE SIZE PINS FOR OPERAND SIZE ASSERT AS AND DS PRESENT DATA 1 DECODE ADDRESS 2 PLACE DATA ON D15 DO ACQUIRE DATA 3 DRIVE DSACKx SIGNALS 1 LATCH DATA TERMINATE CYCLE 2 NEGATE AS AND DS 1 REMOVE DATA FROM 15 00 2 NEGATE DSACKx START NEXT CYCLE Figure 3 7 Word Read Cycle Flowchart 3 16 MC68340 USER S MANUAL MOTOROLA State 0 The read cycle starts in state 0 S0 During SO the MC68340 places a valid address on A31 A0 and valid function codes on FC3 FCO The function codes select the address space for the cycle The MC68340 drives R W high for a read cycle SIZ1 SIZO become valid indicating the number of bytes requested for transfer State 1 One half clock later in state 1 81 the MC68340 asserts AS indicating a valid address on the address bus The MC68340 also asserts DS during S1 The selected device uses R W SIZ1 or SIZO AO and DS to place its information on the data bus One or both of the bytes 015 08 and 07 00 are selected by 5141 5120 and AO State 2 As long as at least one of the DSACK signals is recognized on the falling edge of S2 meeting the asynchronous input setup time requirement data is la
241. al mode used for system debugging Refer to 5 6 Development Support for more information Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines interrupt routines and other exception handlers Exception processing includes the stack operations the exception vector fetch and the filling of the instruction pipeline caused by an exception Exception processing ends when execution of an exception handler routine begins Refer to 5 5 Exception Processing for comprehensive information A catastrophic system failure occurs if the processor detects a bus error or generates an address error while in the exception processing state This type of failure halts the processor For example if a bus error occurs during exception processing caused by a bus error the CPU32 assumes that the system is not operational and halts The halted condition should not be confused with the stopped condition After the processor executes a STOP or LPSTOP instruction execution of instructions can resume when trace interrupt or reset exception occurs 5 4 2 Privilege Levels To protect system resources the processor can operate with either of two levels of access user or supervisor Supervisor level is more privileged than user level All instructions are available at the supervisor level but execution of some instructions is not permitted at the user level There are separate SPs for
242. al module The MC68340 on chip peripherals do not support single address transfers The timer modules can be used with the DMA in a similar manner By connecting TOUTx to DREQ the timer can request a DMA transfer 6 4 DATA TRANSFER MODES The DMA channel supports single and dual address transfers The single address transfer mode consists of one DMA bus cycle which allows either a read or a write cycle to occur The dual address transfer mode consists of a source operand read and a destination operand write Two DMA bus cycles are executed for the dual address mode a DMA read cycle and a DMA write cycle 6 4 1 Single Address Mode The single address DMA bus cycle allows data to be transferred directly between a device and memory without going through the DMA In this mode the operand transfer takes 6 6 MC68340 USER S MANUAL MOTOROLA place in one bus cycle where only the memory is explicitly addressed The bus cycle may be either a read or a write cycle The DMA provides the address and control signals required for the operation The requesting device either sends or receives data to or from the specified address Only external requests can be used to start a transfer when the single address mode is selected An external device uses DREQ to request transfer Each DMA channel can be independently programmed to provide single address transfers The CCR ECO bit controls whether a source read or a destination write cycle occur
243. almtop Computers Telephony Stylus Input Cordless Phones Voice Input Cellular Phones Image Input e CD I CD ROM e Transaction Tracking e Defense Industry Car Rental Guidance Systems Cargo Tracking Systems Courier Data Entry Handheld Instruments Bar Code Scanners Handheld Games 10 10 MC68340 USER S MANUAL MOTOROLA 10 3 1 MC68340 Power Reduction at 5V The following figures show how different variables affect typical power consumption at 5 V Figure 10 15 shows how system activity affects current drain Figure 10 16 shows how voltage affects current drain at some typical operating temperatures Figure 10 17 shows how system clock frequency affects current drain 120 loc mA MOTOROLA Typical values 32KHz xtal 16 78 MHz 24 C NITIALIZATION MAX SERIAL TIMER 1 TIMER 2 DMA LPSTOP CURRENT OFF OFF OFF OFF Figure 10 15 MC68340 Current vs Activity at 5 V MC68340 USER S MANUAL 10 11 120 E y 0 C Oo 24 C 100 Typical values 100 C 32KHz xtal Q 16 78 MHz 9 peak current 80 60 1 J 4 5 5 5 Vcc V Figure 10 16 MC68340 Current vs Voltage Temperature 120 90 T E o 60 Typical values EL 32KHz xtal peak current ol 24 30 0 0 2 4 6 8 10 12 14 16 Clock Frequency MHz Figure 10 17 MC68340 Current vs Clock Frequency at 5 V 10 12 MC68340 USER S MANUAL MOTO
244. als its port size byte or word and indicates completion of the bus cycle to the MC68340 through the use of the DSACK inputs Refer to Table 3 3 for DSACK encoding Table 3 3 DSACK Encoding DSACKi DSACKO Result 1 1 Negated Negated Insert Wait States in Current Bus Cycle 1 0 Negated Asserted Complete Cycle Data Bus Port Size Is 8 Bits 0 1 Asserted Negated Complete Cycle Data Bus Port Size Is 16 Bits 0 0 Reserved Defaults to 16 Bit Port Size Can Be Asserted Asserted Used for 32 Bit DMA cycles MOTOROLA MC68340 USER S MANUAL 3 5 For example if the MC68340 is executing an instruction that reads a long word from a 16 bit port the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits The operation from an 8 bit port is similar but requires four read cycles The addressed device uses DSACK to indicate the port width For instance a 16 bit device always returns DSACK for a 16 bit port regardless of whether the bus cycle is a byte or word operation Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed A 16 bit port must reside on data bus bits 15 0 and an 8 bit port must reside on data bus bits 15 8 This requirement minimizes the number of bus cycles needed to transfer data to 8 and 16 bit ports and ensures that the MC68340 correctly transfers valid data
245. ame is invalid a format error exception is taken If it is inaccessible a bus error exception is taken Otherwise the processor reads the entire frame into the proper internal registers de allocates the stack 12 words and resumes normal processing Bus error frames for faults during exception processing require the RTE instruction to rewrite the faulted stack frame If an error occurs during any of the bus cycles required by rewrite the processor halts If a format error occurs during RTE execution the processor creates a normal four word fault stack frame below the frame that it was attempting to use If a bus error occurs a bus error stack frame will be created The faulty stack frame remains intact so that it may be examined and repaired by an exception handler or used by a different type of processor e g MC68010 MC68020 or future M68000 processor in a multiprocessor system 5 5 3 Fault Recovery There are four phases of recovery from a fault recognizing the fault saving the processor state repairing the fault if possible and restoring the processor state Saving and restoring the processor state are described in the following paragraphs The stack contents are identified by the special status word SSW In addition to identifying the fault type represented by the stack frame the SSW contains the internal processor state corresponding to the fault 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TP BERR frame type MV MOVEM i
246. ammed to continue decode for a range of addresses after the V bit is set After the V bit is set for CSO global chip select can only be restarted with a system reset A system can use an 8 bit boot ROM if an external 8 bit DSACK that responds in two or less wait states is generated The 8 bit must respond in two or less wait states so that the global chip select which responds with three wait states will not be used See Section 10 Applications for a detailed discussion 4 2 5 External Bus Interface Operation This section describes port A and port B functions Refer to Section 3 Bus Operation for more information about the EBI 4 2 5 1 PORT A Port A pins can be independently programmed to function as either addresses A31 A24 discrete I O pins or IACKx pins The port A pin assignment registers PPARA1 and PPARA2 control the function of the port A pins as listed in Table 4 4 Upon reset port A is configured as input pins If the system uses these signals as addresses pulldowns should be put on these signals to avoid indeterminate values until the port A registers can be programmed Table 4 4 Port A Pin Assignment Register Pin Function PPARA1 0 PPARA 1 PPARA1 0 ee m MOTOROLA MC68340 USER S MANUAL 4 15 4 2 5 2 PORT Port B pins can be independently programmed to function as chip selects IRQ and MODCK pins or discrete I O pins These pins are multiplexed as shown
247. an be completed in three clock cycles in this mode Additionally using the fast termination option of the chip select signals two clock operation is possible Furthermore for all inputs the MC68340 latches the level of the input during a sample window around the falling edge of the clock signal This window is illustrated in Figure 3 1 where and th are the input setup and hold times respectively To ensure that an input signal is recognized on a specific falling edge of the clock that input must be stable during MOTOROLA MC68340 USER S MANUAL 3 1 the sample window If an input makes a transition during the window time period the level recognized by the MC68340 is not predictable however the MC68340 always resolves the latched level to either a logic high or low before using it In addition to meeting input setup and hold times for deterministic operation all input signals must obey the protocols described in this section tsu CLKOUT DOOYOO OOOO SAMPLE WINDOW Figure 3 1 Input Sample Window NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a signal is inactive or false 3 1 1 Bus Control Signals The MC68340
248. and TxDx remains in the mark state until CTS is asserted again If the transmitter is forced to send a continuous low condition by issuing a send break command the state of CTS is ignored by the transmitter The transmitter can be programmed to automatically negate request to send RTSz outputs upon completion of a message transmission If the transmitter is programmed to operate in this mode RTS must be manually asserted before a message is transmitted In applications in which the transmitter is disabled after transmission is complete and RTS is appropriately programmed RTS is negated one bit time after the character in the shift register is completely transmitted The transmitter must be manually re enabled by reasserting RTS before the next message is to be sent 7 3 2 2 RECEIVER The receivers are enabled through their respective CRs located within the serial module Functional timing information for the receiver is shown in Figure 7 6 The receiver looks for a high to low mark to space transition of the start bit on RxDx When a transition is detected the state of RxDx is sampled each 16x clock for eight clocks starting one half clock after the transition asynchronous operation or at the next rising edge of the bit time clock synchronous operation If RxDx is sampled high the start bit is invalid and the search for the valid start bit begins again If RxDx is still low a valid start bit is assumed and the receiver continues
249. and data block This initialization is accomplished by programming the appropriate information into the channel registers The SAR is loaded with the source read address If the transfer is from a peripheral device to memory the source address is the location of the peripheral data register If the transfer is from memory to a peripheral device or memory to memory the source address is the starting address of the data block This address may be any byte address In the single address mode with the destination write device requesting mode of operation this register is not used The DAR should contain the destination write address If the transfer is from a peripheral device to memory or memory to memory the DAR is loaded with the starting address of the data block to be written If the transfer is from memory to a peripheral device the DAR is loaded with the address of the peripheral data register This address may be any byte 6 18 MC68340 USER S MANUAL MOTOROLA address In the single address mode with the source read device requesting mode of operation this register is not used The manner in which the SAR and DAR change after each cycle depends upon the values in the CCR SSIZE and DSIZE fields and SAPI and DAPI bits and the starting address in the SAR and DAR If programmed to increment the increment value is 1 2 or 4 for byte word or long word operands respectively If the address register is programmed to remain unchanged
250. and that arbitration and interrupts can be handled in parallel with data transfers greatly improving system performance Internal accesses across the IMB may be monitored from outside of the chip if desired Each module operates independently No direct connections between peripheral modules are made inside the chip however external connections could for instance link a serial output to a DMA control line Modules and their registers are accessed in the memory map of the CPU32 and DMA for easy access by general M68000 instructions and are relocatable Each module may be assigned its own interrupt level response vector and arbitration priority Since each module is a self contained design and adheres to the IMB interface specifications the modules may appear on other M68300 family products retaining the investment in the software drivers for the module 1 3 1 System Integration Module MC68340 SIM40 provides the external bus interface for both the CPU32 and the DMA It also eliminates much of the glue logic that typically supports the microprocessor and its interface with the peripheral and memory system The SIM40 provides programmable circuits to perform address decoding and chip selects wait state insertion interrupt handling clock generation bus arbitration watchdog timing discrete and power on reset timing A boundary scan test capability is also provided 1 3 1 1 EXTERNAL BUS INTERFACE The external bus interface
251. and the CPU32 is fixed at the lowest level below level 0 The direct memory access DMA module is the only other module that can become bus master and arbitrate for the bus It must be initialized with a level other than 0 or 7 The AVR contains bits that correspond to external interrupt levels that require an autovector response The 5 40 supports up to seven discrete external interrupt requests If the bit corresponding to an interrupt level is set in the AVR the SIMAO returns an autovector in response to the IACK cycle servicing that external interrupt request Otherwise external circuitry must either return an interrupt vector or assert the external AVEC signal 4 2 2 2 INTERNAL BUS MONITOR The internal bus monitor continually checks for the bus cycle termination response time by checking the DSACK BERR and HALT status or the AVEC status during an IACK cycle The monitor initiates a bus error if the response time is excessive The bus monitor feature cannot be disabled for internal accesses to an internal module The internal bus monitor cannot check the DSACK response on the external bus unless the MC68340 is the bus master The BME bit in the system protection control register SYPCR enables the internal bus monitor for internal to external bus cycles If the system contains external bus masters whose bus cycles must be monitored an external bus monitor must be implemented In this case the internal to external bus monitor option m
252. ap on any 5 64 MC68340 USER S MANUAL MOTOROLA memory access Off chip address comparators will not detect breakpoints on internal accesses unless show cycles are enabled Breakpoints on prefetched instructions which are flushed from the pipeline before execution are not acknowledged but operand breakpoints are always acknowledged Acknowledged breakpoints can initiate either exception processing or BDM See 5 5 2 6 Hardware Breakpoints for more information 5 6 2 Background Debug Mode BDM is an alternate CPU32 operating mode During BDM normal instruction execution is suspended and special microcode performs debugging functions under external control Figure 5 20 is a BDM block diagram BDM can be initiated in several ways by externally generated breakpoints by internal peripheral breakpoints by the background instruction BGND or by catastrophic exception conditions While in BDM the CPUS2 ceases to fetch instructions via the parallel bus and communicates with the development system via a dedicated high speed SPI type serial command interface SERIAL INTERFACE SEQUENCER gt 050 MICROCODE FETCH DSI BKPT DSCLK BUS CONTROL DATA BUS BERR FREEZE ADDRESS BUS EXECUTION UNIT Figure 5 20 BDM Block Diagram 5 6 2 1 ENABLING BDM Accidentally entering BDM in a nondevelopment environment could lock up the CPU32 since the serial
253. aracteristics 10 11 DC Electrical Specifications 11 5 ERR Bit 7 13 7 23 7 47 Error Status Serial 7 13 Event Counting 8 14 8 15 Exception Handler 5 42 5 51 5 57 5 59 5 56 Priorities 5 41 5 42 Processing 3 32 5 4 5 38 5 61 Faults 5 54 5 59 Sequence 5 40 5 41 State 5 7 5 38 5 40 5 41 Stack Frame 5 4 Vectors 5 39 5 40 Exception Related Instructions and Operands Timing Table 5 112 EXTAL Pin 2 9 4 7 4 9 4 11 10 21 External Bus Interface 4 2 Bus Master 3 4 3 16 3 40 3 44 4 6 Request 6 2 6 5 6 6 6 19 6 20 6 29 6 30 Exceptions 5 40 Reset 10 3 LEV F Line Instructions 5 47 Fast Termination Timing 3 15 Operation 3 4 3 15 4 14 4 30 4 33 DMA Transfers 6 20 Fault Address Register 5 67 Correction 5 57 5 59 Recovery 5 52 Types 5 54 5 55 5 57 5 59 5 83 5 86 FC Bits 4 2 Bits 4 32 FE Bit 7 13 7 24 7 28 Index 3 Fetch Effective Address Instruction Timing Table 5 99 FFULL Bit 7 25 FFULLA Signal 7 7 Fill Memory Block Command 5 82 FIRQ Bit 4 5 4 16 4 22 4 35 4 36 FORCE BGND 5 72 Format Error Exception 5 47 5 52 Four Word Stack Frame 5 51 5 60 Framing Error 7 11 7 24 Freeze Operation 4 17 6 24 7 20 8 19 FREEZE Signal 2 10 4 3 4 17 4 22 4 23 4 36 5 66 5 68 5 71 5 72 Frequency Adjusted Signal Skew 10 9 Width 10 8 Frequency Divider 4 12 FRZ Bits 4 17 4 18 4 21 4 22 4 36 6 24 7 20 7 46 8 19
254. are To complete a bus cycle in software a handler must first read the SSW function code field to determine the appropriate address space access the fault address pointer on the stack and then transfer data from the stacked image of the output buffer to the fault address Because the CPU32 has a 16 bit internal data bus long operands require two bus accesses A fault during the second access of a long operand causes the LG bit in the SSW to be set The SIZ field indicates remaining operand size If operand coherency is important the complete operand must be rewritten After a long operand is rewritten the RR bit must be cleared Failure to clear the RR bit can cause the RTE instruction to rerun the bus cycle Following rewrite it is not necessary to adjust the PC or other stack contents before executing RTE 5 5 3 2 2 Type I Completing Released Writes via RTE An exception handler can use the RTE instruction to complete a faulted bus cycle When RTE executes the fault address data output buffer PC and SR are restored from the stack Any pending breakpoint or trace exceptions as indicated by TR B1 and BO in the stacked SSW are requeued during SSW restoration The RR bit in the SSW is checked during the unstacking operation if it is set the RW FUNC and SIZ fields are restored and the released write cycle is rerun To maintain long word operand coherence stack contents must be adjusted prior to RTE execution The fault address mus
255. art 2 of 5 7 42 MC68340 USER S MANUAL MOTOROLA RSTCHN DISABLE CHANNEL S TRANSMITTER RESTORE CHANNEL TO ORIGINAL MODE RETURN HAVE PARITY ERROR SETPA ERROR RITY FLAG CHRCHK F GET CHARACTER FROM RECEIVER AS CHARACTER TRANSMITTED SET INCORRECT CHARACTER FLAG Figure 7 10 Serial Module Programming Flowchart 3 of 5 MOTOROLA MC68340 USER S MANUAL 7 43 7 44 IRQx CAUSED BY BEGINNING OF A BREAK CLEAR CHANG E IN BREAK STATUS BIT ABRKI1 HAS END OF BREAK IRQx ARRIVED YET CLEAR CHANGE IN BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS RTE Figure 7 10 Serial Module Programming Flowchart 4 of 5 DOES CHANNELA RECEIVER HAVE A CHARACTER Y Y PLACE CHARACTER IN DO RETURN MC68340 USER S MANUAL MOTOROLA OUTCH IS CHANNELA TRANSMITTER READY SEND CHARACTER IN DO TO CHANNEL A TRANSMITTER WAS CHARACTER A CARRIAGE RETURN OUTCHI 5 TRANSMITTER READY SEND A LINE FEED CHARACTER TO CHANNEL A TRANSMITTER OUTCHR RETURN POUCH IS CHANNEL B TRANSMITTER READY SEND CHARACTER IN DO TO CHANNEL B TRANSMITTER WAS CHARACTER A CARRIAGE RETURN POU
256. as no effect on the counter When TGATEz is reasserted the counter stops counting and holds the value at which it stopped Further assertions and negations of TGATE have no effect on the counter This mode can be selected by programming the CR MODEx bits to 101 The timer is enabled by setting the SWR CPE and the TGE bits in the CR The assertion of TGATE starts the counter When the timer is enabled the SR ON bit is set On the next falling edge of the counter clock the counter is loaded with the value of FFFF With each successive falling edge of the counter clock the counter decrements The PREL1 and PREL2 registers are not used in this mode The first negation of TGATEz is ignored but on the second assertion of TGATE the SR TG bit is set the SR ON bit is negated and the prescaler and counter are disabled Subsequent transitions on TGATE do not re enable the counter See Figure 8 9 for a depiction of this mode The SR TGL bit reflects the level of TGATE at all times MOTOROLA MC68340 USER S MANUAL 8 13 COUNTER CLOCK COUNTER 0 ws T ENABLE PERIOD MEASURED START STOP NO EFFECT COUNTING COUNTING 6 6 oh Q n 6 C WO m mn MODEx Bits in Control Register 101 TGE Bit of Control Register 1 Figure 8 9 Period Measurement Mode If the cou
257. ask register define the size of the block for the chip select The base address field and the base function code field is compared to the address on the address bus to determine if a chip select should be generated Function Code Bits 3 0 The value programmed into this field causes a chip select to be asserted for a certain address space type There are nine function code address spaces see Section 3 Bus Operation specified as either user or supervisor program or data CPU and DMA These bits should be used to allow access to one type of address space If access to more than one type of address space is desired the FCMx bits should be used in addition to the bits To prevent access to CPU space set the NCS bit WP Write Protect This bit can restrict write accesses to the address range in a base address register An attempt to write to the range of addresses specified in a base address register that has this bit set returns BERR 1 Only read accesses are allowed 0 Either read or write accesses are allowed FTE Fast Termination Enable This bit causes the cycle to terminate early with an internal DSACK giving a fast two clock external access When clear all external cycles are at least three clocks If fast termination is enabled the DD bits of the corresponding address mask register are overridden see Section 3 Bus Operation 1 Fast termination cycle enabled termination determined
258. at all times If the counter counts down to the value stored in the COM register the COM and bits in the SR are set If the counter counts down to 0000 a timeout is detected This event sets the TO in the SR and clears the COM bit At timeout the next falling edge of the counter clock reloads the counter with FFFF TOUTx transitions at timeout or is disabled as programmed by the CR OC bits The SR OUT bit reflects the level on TOUTx To determine the number of cycles counted the value in the CNTR must be read inverted and incremented by 1 the first count is FFFF which in effect includes a count of zero The counter counts in a true 216 fashion For measuring pulses of even greater duration the value in the POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR MOTOROLA MC68340 USER S MANUAL 8 15 8 3 8 Timer Bypass In this mode the counter and prescaler cannot be enabled However TGATE and TOUTx can be used for I O This mode be selected by programming the CR MODE bits to 111 can be used as a simple input port when the CR is configured as follows CR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGATE AS A SIMPLE INPUT X X 0 X X X 1 X X X X 1 1 1 X X X Don t care When TGATE is asserted the SR ON bit is set When TGATE is negated the ON bit is cleared The value of the TGL bit in the SR reflects the level of TG ATE TGATE can also be us
259. at information is on the stack so that it may be properly restored 5 4 MC68340 USER S MANUAL MOTOROLA 5 1 6 Addressing Modes Addressing in the CPUS2 is register oriented Most instructions allow the results of the specified operation to be placed either in a register or directly in memory this flexibility eliminates the need for extra instructions to store register contents in memory The seven basic addressing modes are as follows Register Direct Register Indirect Register Indirect with Index Program Counter Indirect with Displacement Program Counter Indirect with Index Absolute Immediate Included in the register indirect addressing modes are the capabilities to postincrement predecrement and offset The PC relative mode also has index and offset capabilities In addition to these addressing modes many instructions implicitly specify the use of the SR SP and or PC Addressing is explained fully in the M68000PM AD M68000 Family Programmer s Reference Manual 5 1 7 Instruction Set The instruction set of the CPU32 is very similar to that of the MC68020 see Table 5 1 Two new instructions have been added to facilitate embedded control applications LPSTOP and table lookup and interpolate TBL The following M68020 instructions are not implemented on the CPU32 BFxxx Bit Field Instructions BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST CALLM Call Module Return Module CAS CAS2 Compa
260. ature parts T A 40 to 85 C These specifications are preliminary All internal registers retain data at 0 Hz Assumes that a stable VCCSYN is applied that an external filter capacitor with a value of 0 1 uF is attached to the XFC pin and that the crystal oscillator is stable Lock time is measured from power up to RESET release This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register SYNCR while the PLL is running and to the period required for the clock to lock after LPSTOP Determined by the initial control voltage applied to the on chip VCO The X bit in the SYNCR controls a divide by two scaler on the system clock output CLKOUT stability is the average deviation from programmed frequency measured at maximum fsys Measurement is made with a stable external clock input applied using the PLL All crystal mode clock specifications are based on using a 32 768 kHz crystal for the input When using the external clock input mode MODCK reset value 0 V the minimum allowable tEXTcyc period will be reduced when the duty cycle of the signal applied to EXTAL exceeds 5 tolerance The relationship between external clock input duty cycle and minimum is expressed Minimum tEXTcyc period minimum tgxrcw 50 external clock input duty cycle tolerance Minimum external clock low and high times are based on a 45 duty cycle When using t
261. be programmed The DMA channels support two external request modes burst mode and cycle steal mode The DMA controller supports single and dual address transfers In single address mode a channel supports 32 bits of address and 32 bits of data Only an external request can be used to start a transfer in the single address mode The DMA provides address and control signals during a single address transfer The requesting device either sends or receives data to or from the specified address see Figure 6 2 In dual address mode a channel supports 32 bits of address and 16 bits of data The dual address transfers can be started by either the internal request mode or by an external device using the request signal In this mode two bus transfers occur one from a source device and the other to a destination device see Figure 6 3 In dual address mode operands are packed or unpacked according to port sizes and addresses Any operation involving the DMA will follow the same basic steps channel initialization data transfer and channel termination In the channel initialization step the DMA channel registers are loaded with control information address pointers and a byte transfer count The channel is then started During the data transfer step the DMA accepts requests for operand transfers and provides addressing and bus control for the transfers The channel termination step occurs after operation is complete The channel indicates the status of
262. bers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes instruction Head Cycles emere ETE RTE six word frame 26 4 2 0 RTE BERR on instruction 50 12 12 Y RTE BERR on four word frame 66 10 2 4 RTE BERR on six word frame 70 12 2 6 Maximum time is indicated certain data or mode combinations execute faster Y If a bus error occurred during a write cycle the cycle is rerun by the RTE MOTOROLA MC68340 USER S MANUAL 5 113 SECTION 6 DMA CONTROLLER MODULE The direct memory access DMA controller module provides for high speed transfer capability to from an external peripheral or for memory to memory data transfer The DMA module shown in Figure 6 1 provides two channels that allow byte word or long word operand transfers These transfers can be either single or dual address and to either on or off chip devices The DMA contains the following features Two Independent Fully Programmable DMA Channels Single Address Transfers with 32 Bit Address and 32 Bit Data Capability Dual Address Transfers with 32 Bit Address and 16 Bit Data Capability Two 32 Bit Transfer Counters Four 32 Bit Address Pointers That Can Increment or Remain Constant Operand Packing and Unpacking for Dual Address Transfers Supports All Bus Termination Modes Provides Two Clock Cycle Internal Module Access Prov
263. between the EXTAL and XTAL pins or an external oscillator connected to EXTAL as a reference frequency source The oscillator circuit is shown in Figure 4 5 A 32 768 kHz watch crystal provides an inexpensive reference but the reference crystal or external oscillator frequency can be any frequency in the range specified in Section 11 Electrical Characteristics When MOTOROLA MC68340 USER S MANUAL 4 9 using crystal mode the system clock frequency is programmable using the W X and Y bits in the SYNCR over the range specified in Section 11 Electrical Characteristics see Table 4 2 YDDSYN Ms a xrc 1 0 1 uF 20 pF 20 pF 20M al 0 1 pF VpDSYN 0 01 pF NOTE 1 Must be low leakage capacitor Figure 4 4 Clock Block Diagram for Crystal Operation x 2 exo EXTAL XTAL 2 60 Figure 4 5 MC68340 Crystal Oscillator A separate power pin Vccsyn is used to allow the clock circuits to run with the rest of the device powered down and to provide increased noise immunity for the clock circuits The source for Vccsyn should be a quiet power supply with adequate external bypass capacitors placed as close as possible to the Vccsyn pin to ensure a stable operating frequency Figure 4 4 shows typical values for the bypass and PLL external capacitors The crystal manufacturer s documentation should be consulted for specific recommendations for external components
264. bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level No two modules can share the same IARB value The reset value of the IARB field is 0 which prevents this module from arbitrating during the interrupt acknowledge cycle The system software should initialize the IARB field to a value from F highest priority to 1 lowest priority 7 4 1 2 INTERRUPT LEVEL REGISTER ILR The ILR contains the priority level for the serial module interrupt request When the serial module is enabled i e the STP bit in the MCR is cleared this register can be read or written to at any time while in supervisor mode ILR 704 7 6 5 4 3 2 1 0 fo fo fo io fe vo TOU 0 0 0 0 0 0 0 Read Write Supervisor Only Bits 7 3 Reserved IL2 ILO Interrupt Level Bits Each module that can generate interrupts has an interrupt level field The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal The CPUS2 uses this value to determine servicing priority The hardware reset value of 00 will not generate any interrupts See Section 5 CPU32 for more information 7 4 1 3 INTERRUPT VECTOR REGISTER The IVR contains the 8 bit vector number of the interrupt When the serial module is enabled i e the STP bit in the MCR is cleared this register can be read or written to at any time while in supervisor mode MOTOROLA MC68340 USER S
265. ble the timer Enable the desired interrupts IEx bits Enable TGATE if required for mode of operation TGE bit e Select the prescaler clock PCLK bit MOTOROLA MC68340 USER S MANUAL 8 27 Enable the counter prescaler CPE bit e Select the selected clock CLK bit e If the PCLK bit is set select the POTx bits e Select the mode of operation MODEx bits e Select the operation of TOUT bits 8 5 2 Timer Module Example Configuration Code The following code is an example of a configuration sequence for the timer module kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MC68340 basic timer module register initialization example code This code is used to initialize the 68340 s internal timer module registers providing basic functions for operation It sets up timer1 for square wave generation kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MODBASE EQU FFFFF000 SIM40 MBAR address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Timer1 module equates TIMER1 EQU 600 Offset from MBAR for timer1 module regs 1 EQU 0 MCR for timer1 Timer1 register offsets from timer1 base address IR1
266. bled bus monitor BERR after 16 clocks MOVE B 6 SYPCR MODBASE kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Clock synthesizer control register Switch from 8 3 to 16 7 MHZ MOVE W 7F00 SYNCR MODBASE X bit doubles the default speed kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Module configuration register When FREEZE is asserted software watchdog and periodic interrupt timer are disabled bus monitor is enabled Port B 4 IRQs 4 chip selects Show Cycles enabled external arbitration enabled Supervisor user SIM registers unrestricted Interrupt Arbitration at priority F MOVE W 420F MCR MODBASE kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Now set up Address masks and base addresses for the chip selects LEA CSAM0 MODBASE AO CSO addr mask location MOVEQ 7 D Set up a loop counter LEA CSAMO A1 Point to addr mask memory location LOOP MOVE L A1 A0 Init addr mask and base addr reg DBRA DO LOOP MOTOROLA MC68340 USER S MANUAL 4 39 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Data table for chip select initialization kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk CS0 EPROM 00060000 0007ffff 3 wait states 16 bit term write protect CSAMO DC L 0001FFFD CSBARO DC L 00060009 CS1 RAM 00000000 0000 fas
267. by PS bits 0 Fast termination cycle disabled termination determined by DD and PS bits 4 30 MC68340 USER S MANUAL MOTOROLA NCS No CPU Space This bit specifies whether or not a chip select will assert on a CPU space access cycle FC3 FCO 7 or F If both supervisor data and program accesses are desired while ignoring CPU space accesses then this bit should be set The NCS bit is cleared at reset 1 Suppress the chip select on a CPU space access 0 Assert the chip select on a CPU space access V Valid Bit This bit indicates that the contents of its base address register and address mask register pair are valid The programmed chip selects do not assert until the V bit is set A reset clears the V bit in each base address register but does not change any other bits in the base address and address mask registers CSO is a special case see 4 2 4 2 Global Chip Select Operation 1 Contents are valid 0 Contents are not valid 4 3 4 2 ADDRESS MASK REGISTERS There are four 32 bit address mask registers in the chip select function one for each chip select signal Address Mask 1 040 048 050 058 3l 30 29 28 21 26 25 24 23 22 2 20 19 18 17 16 RESET U U U U U U U U U U U U U U U U Supervisor Only Address Mask 2 042 04A 052 05A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET U U U U U U U U U U U U U U U U U Unaffected by reset Supervisor Only AM31 AM8 Address Mask Bits 31 8 The ad
268. c Input Output Active State Three State Request to Send RTSB RTSA Out Out Low No OP1 OPO FIFO Full OP4 omes 777772710 nf 1 mem _ Fmeoqa vw 1 ms n wm mw n Teroa m _ System Power Supply and Voc GND Return MOTOROLA MC68340 USER S MANUAL 2 15 SECTION 3 BUS OPERATION This section provides a functional description of the bus the signals that control it and the bus cycles provided for data transfer operations It also describes the error and halt conditions bus arbitration and reset operation Operation of the external bus is the same whether the MC68340 or an external device is the bus master the names and descriptions of bus cycles are from the viewpoint of the bus master For exact timing specifications refer to Section 11 Electrical Characteristics The MC68340 architecture supports byte word and long word operands allowing access to 8 and 16 bit data ports through the use of asynchronous cycles controlled by the SIZ1 SIZO outputs and DSACK1 DSACKO inputs The MC68340 requires word and long word operands to be located in memory on word boundaries The only type of transfer that can be performed to an odd address is a single byte transfer referred to as an odd byte transfer For an 8 bit port
269. c CPU serial logic shown in the left hand portion of Figure 5 22 consists of transmit and receive shift registers and of control logic that includes synchronization serial clock generation circuitry and a received bit counter Both DSCLK and DSI are synchronized to on chip clocks thereby minimizing the chance of propagating metastable states into the serial state machine Data is sampled during the high phase of CLKOUT At the falling edge of CLKOUT the sampled value is made available to internal logic If there is no synchronization between CPU32 and development system hardware the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT MOTOROLA MC68340 USER S MANUAL 5 69 CPU DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS 16 RCV DATA LATCH SERIAL IN PARALLEL OUT PARALLEL IN SERIAL OUT STATUS 4 EXECUTION Y SYNCHRONIZE MICROSEQUENCER CONTROL LOGIC DSCLK CONTROL SERIAL LOGIC CLOCK Figure 5 22 Debug Serial Block Diagram The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK see Figure 5 23 Synchronized serial data is transferred to the input shift register and the received bit counter is decremented One half clock period later the output shift register is updated bringing the next output bit to the DSO signal DSO changes relative to the rising edge of DSCLK and does not necessaril
270. c compare logic and clock selection logic Figure 8 2 shows a functional diagram of the timer module 8 1 1 1 PRESCALER AND COUNTER The counter can be driven directly by the selected clock or the prescaler output Both the counter and prescaler are updated on the falling edge of the clock During reset the prescaler is set to FF and the counter is set to 0000 The counter is loaded with a programmed value on the first falling edge of the counter clock after the timer is enabled and again when a timeout occurs counter reaches 0000 The prescaler and counter can be used as one 24 bit counter by enabling the prescaler and selecting the divide by 256 prescaler output Refer to 8 4 Register Description for additional information on how to program the timer 8 1 1 2 TIMEOUT DETECTION Timeout is achieved when all 16 stages of the counter transition to zero a counter value of 0000 Timeout is a defined counter event which triggers specific actions depending upon the programmed mode of operation Refer to 8 3 Operating Modes for descriptions of the individual modes 8 1 1 3 COMPARATOR The comparator block compares the value in the 16 bit compare register COM with the output of the 16 bit counter When an exact match is detected bits in the status register SR are set to indicate this condition When in the input capture output compare mode a match is a defined counter event that can affect the output of the timer Refer to 8 3 1
271. ception Vector Assignments Vector VectorOffset Po o o SP Resomia SackPomer Pt f a f oa S RestmaPrgamComer e s s s f me wo s WmesEm 4 vo Sb Weameneon s v s 6 ws s ow omemsmcon O 7 we se TRA TRAPVWemudons s f s oo Sb PWegeVomon o s me 10 40 SD jtmetOtOEmuatr wc s uennEmmo pe o Sb Hardware Brearpoint Essa cierre et oa TT Format Error Uninitialized Interrupt Unassigned Reserved Spurious Interrupt Level 1 Interrupt Autovector Level 2 Interrupt Autovector Level 3 Interrupt Autovector Level 4 Interrupt Autovector Level 6 Interrupt Autovector Level 7 Interrupt Autovector Trap Instruction Vectors 0 15 Reserved for Coprocessor Unassigned Reserved User Defined Vectors 192 MOTOROLA MC68340 USER S MANUAL 539 mE EE SD SD SD SD SD SD Level 5 Interrupt Autovector E teh CAUTION Because there is no protection on the 64 processor defined vectors external devices can access vectors reserved for internal purposes This practice is strongly discouraged All exception vectors except the reset vector are located in supervisor data space The reset vector is located in supervisor program space Only the initial reset vector is fixed in t
272. ch module that generates interrupts has an IARB field These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level No two modules can share the same IARB value Timer 1 and timer 2 should be programmed with different values if both are used The reset value of the IARB field is 0 which prevents this module from arbitrating during the interrupt acknowledge cycle The system software should initialize the IARB field to a value from F highest priority to 1 lowest priority MOTOROLA MC68340 USER S MANUAL 8 19 8 4 2 Interrupt Register IR The IR contains the priority level for the timer interrupt request and the 8 bit vector number of the interrupt The register can be read or written to at any time while in supervisor mode and while the timer module is enabled i e the STP bit in the MCR is cleared IR 604 644 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TT Pe Tele Tw ives we v vs RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Supervisor Only Bits 15 11 Reserved IL2 ILO Interrupt Level Bits Each module that can generate interrupts has an interrupt level field The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal The CPU32 uses this value to determine servicing priority See Section 5 CPU32 for more information IV7 IVO Interrupt Vector Bits Each module that can generat
273. clock periods needed for the processor to fetch calculate and perform the special purpose MOVE operation on control registers or a specified EA Footnotes indicate when to account for the appropriate EA times The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes MOTOROLA MC68340 USER S MANUAL 5 101 instruction Head xa e o vovec o f o mow Movee 2 o meow 2 o 4w MOVE OCR CED o 2 MOVE 2 o 0 1 0 MOVE o o MOVE SRD 2 o Move o 2 MOVE 58 o gt 0090 CEN RL 1 o 8 nx ain t 2 0 RL CE 1 o se8enx4 2m MOVEML o 402 2 2 0 Wow mem e wem MOVEP W d46 An D 11 2 2 0 MOVEP L Dn dig An Low d 14 0 2 4 MOVEP L 916 An D 19 4 2 0 Rn cE 9 2 MOVE o o o o wp D o X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles Each bus cycle may take up to four clocks without increas
274. command interface would probably not be available For this reason BDM is enabled during reset via the BKPT signal MOTOROLA MC68340 USER S MANUAL 5 65 BDM operation is enabled when BKPT is asserted low at the rising edge of RESET BDM remains enabled until the next system reset A high BKPT on the trailing edge of RESET disables BDM BKPT is relatched on each rising transition of RESET BKPT is synchronized internally and must be held low for at least two clock cycles prior to negation of RESET BDM enable logic must be designed with special care If hold time on BKPT after the trailing edge of RESET extends into the first bus cycle following reset this bus cycle could be tagged with a breakpoint Refer to Section 3 Bus Operation for timing information 5 6 2 2 BDM SOURCES When BDM is enabled any of several sources can cause the transition from normal mode to BDM These sources include external BKPT hardware the BGND instruction a double bus fault and internal peripheral breakpoints If BDM is not enabled when an exception condition occurs the exception is processed normally Table 5 19 summarizes the processing of each source for both enabled and disabled cases As depicted in the table the BKPT instruction never causes a transition into BDM Table 5 19 BDM Source Summary BDM Enabled BDM Disabled BKPT Background Breakpoint Exception Double Bus Fault Background Halted BGND Instruction Background Illegal Instruct
275. cter being received is lost The command has no effect on the receiver status bits or any other control register If the serial module is programmed to operate in the local loopback mode or multidrop mode the receiver operates even though this command is selected If the receiver is already disabled this command has no effect Do Not Use Do not use this bit combination because the result is indeterminate 7 4 1 8 RECEIVER BUFFER RB The receiver buffer contains three receiver holding registers and a serial shift register The channel s RxDx pin is connected to the serial shift register The holding registers act as a FIFO The CPU32 reads from the top of the stack while the receiver shifts and updates from the bottom of the stack when the shift register has been filled see Figure 7 4 This register can only be read when the serial module is enabled i e the STP bit in the MCR is cleared RBA RBB 713 71B 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Read Only Supervisor User RB7 RBO These bits contain the character the receiver buffer 7 4 1 9 TRANSMITTER BUFFER TB The transmitter buffer consists of two registers the transmitter holding register and the transmitter shift register see Figure 7 4 The holding register accepts characters from the bus master if the TxRDY bit in the channel s SR is set A write to the transmitter buffer clears the TxRDY bit inhibiting any more 7 30 MC68340 USER S MANUAL MOTOROLA characters
276. ction is executed the MC68340 drives the RESET signal for 512 clock cycles The SIM40 registers and the module control registers in each internal peripheral module DMA timers and serial modules are not affected All other peripheral module registers are reset the same as for a hardware reset The external devices connected to the RESET signal are reset at the completion of the RESET instruction 3 48 MC68340 USER S MANUAL MOTOROLA SECTION 4 SYSTEM INTEGRATION MODULE The MC68340 system integration module SIM40 consists of several functions that control the system start up initialization configuration and the external bus with a minimum of external devices It also provides the IEEE 1149 1 boundary scan capabilities The SIM40 includes the following functions System Configuration and Protection Clock Synthesizer Chip Selects and Wait States External Bus Interface Bus Arbitration Dynamic Bus Sizing IEEE 1149 1 Test Access Port 4 1 MODULE OVERVIEW SIM40 is essentially identical to the SIM implemented in the MC68330 The SIM40 has similar features to the SIM in the MC68331 MC68332 and MC68333 The periodic interrupt timer double bus fault monitor software watchdog internal bus monitor and spurious interrupt monitor are identical However many of the other features in the SIM s differ in their use and details The system configuration and protection function controls system configuration and provides variou
277. d The data from the bus cycle is used to begin filling the empty pipeline Both user and supervisor mode fetches are signaled by IFETCH Proper tracking of bus cycles via IFETCH on a fast bus requires a simple state machine On a two clock bus IFETCH may signal a pipeline flush with associated prefetch followed immediately by a second prefetch That is IFETCH remains asserted for three clocks two clocks indicating the flush fetch and a third clock signaling the second fetch These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT which follow the AS DS during show cycles falling edge Three clock and slower bus cycles allow time for negation of the signal between consecutive indications and do not experience this operation 5 6 3 2 INSTRUCTION PIPE IPIPE The internal instruction pipeline can be modeled as a three stage FIFO see Figure 5 28 Stage A is an input buffer data can be used out of stages B and C IPIPE signals advances of instructions in the pipeline Instruction register A IRA holds incoming words as they are prefetched No decoding takes place in the buffer Instruction register B IRB provides initial decoding of the opcode and decoding of extension words it is a source of immediate data Instruction register C IRC supplies residual opcode decoding during instruction execution DATA BUS gt R R A c EXTENSION OPCODES WORDS RESIDUAL Figure 5 28 Functi
278. d Format The following standard bit format is utilized by all BDM commands 15 10 9 8 7 6 5 4 3 2 0 OPERATION RW OP SIZE o REGISTER EXTENSION WORD S Bits 15 0 Operation Field The operation field specifies the commands This 6 bit field provides for a maximum of 64 unique commands R W Field The R W field specifies the direction of operand transfer When the bit is set the transfer is from CPU to development system When the bit is cleared data is written to the CPU or to memory from the development system Operand Size For sized operations this field specifies the operand data size All addresses are expressed as 32 bit absolute values The size field is encoded as listed in Table 5 22 Table 5 22 Size Field Encoding Encodng OperandSize pow Address Data A D Field The A D field is used by commands that operate on address and data registers It determines whether the register field specifies a data or address register One indicates an address register zero indicates a data register For other commands this field may be interpreted differently MOTOROLA MC68340 USER S MANUAL 5 73 Register Field In most commands this field specifies the register number for operations performed on an address or data register Extension Word s as required At this time no command requires an extension word to specify fully the operation to be performed but some commands require extension
279. d user accessible test logic that is fully compliant with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to the development of this standard under the sponsorship of the IEEE Test Technology Committee and Joint Test Action Group JTAG The MC68340 implementation supports circuit board test strategies based on this standard Refer to Section 9 IEEE 1149 1 Test Access Port for additional information 4 2 MODULE OPERATION The following paragraphs describe the operation of the module base address register system configuration and protection clock synthesizer chip select functions and the external bus interface NOTE The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a signal is inactive or false 4 2 1 Module Base Address Register Operation The module base address register MBAR controls the location of all internal module registers see 4 3 1 Module Base Address Register MBAR The address stored in this register is the base address starting location for all internal registers All internal module registers are contained in a single 4 Kbyte block see Figure 4 1 that is r
280. data is written to memory selected by the address specified in the destination address register DAR the destination function codes in the FCR and the size in the CCR The destination write DMA bus cycle has timing identical to a write bus cycle The DMA control signals DACK and DONE are asserted in the destination write cycle See Figures 6 7 and 6 8 for timing diagrams of single address write for external burst and cycle steal modes CPU CYCLE DMA WRITE DMA WRITE CPU CYCLE S0 S2 54 50 52 54 50 52 54 50 ap EE MAE eu KO K X K Ko X K K wes DREQx N DONEx 7 77 INPUT DACKx N N DONEx OUTPUT NOTE 1 Timing to generate more than one DMA request 2 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle 2 DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized Figure 6 7 Single Address Write Timing External Burst 6 10 MC68340 USER S MANUAL MOTOROLA VIOYOLOW TWANVIN S 4YASN 07289921 LL9 CLKOUT 1 5121 5120 i D15 DO DSACKx DREQx DONEx INPUT DACKx DONEx OUTPUT NOTE 50 CPU CYCLE S2 54 SO CPU CYCLE S2 S4 so DMA WRITE S2 54 50 CPU CYCLE 52 54 1 DREQx must be active for two consecutive clocks f
281. dditional information AVEC is only sampled during an interrupt acknowledge cycle During all other cycles AVEC is ignored Additionally AVEC can be internally generated for external devices by programming the autovector register Seven distinct autovectors can be used corresponding to the seven levels of interrupt available with signals IRQ7 IRQ1 Figure 3 16 shows the timing for an autovector operation 3 4 4 3 SPURIOUS INTERRUPT CYCLE Requested interrupts whether internal or external are arbitrated internally When no internal module including the SIM40 which responds for external requests responds during an interrupt acknowledge cycle by arbitrating for the interrupt acknowledge cycle internally the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition The MC68340 automatically generates the spurious interrupt vector number 24 instead of the interrupt vector number in this case When an external device does not respond to an interrupt acknowledge cycle with AVEC or a bus monitor must assert BERR which results in the CPUS2 taking the spurious interrupt vector If HALT is also asserted the MC68340 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector 3 30 MC68340 USER S MANUAL MOTOROLA 50 52 54 S0 0 2CLOCKS 51 52 54 50 52 A31 A4 X 1 C INTERRUPT LEVEL A0 X N 5170 N 1BYTE 5171 X RW N
282. dress mask field the upper 24 bits of each address mask register defines the chip select block size The block size is equal to 2 where n number of bits set in the address mask field 8 Any set bit masks the corresponding base address register bit the base address register bit becomes a don t care By masking the address bits independently external devices of different size address ranges can be used Address mask bits can be set or cleared in any order in the field allowing a resource to reside in more than one area of the address map This field can be read or written at any time MOTOROLA MC68340 USER S MANUAL 4 31 FCM3 FCMO Function Code Mask Bits 3 0 This field can be used to mask certain function code bits allowing more than one address space type to be assigned to a chip select Any set bit masks the corresponding function code bit DD1 DDO DSACK Delay Bits 1 and 0 This field determines the number of wait states added before an internal DSACK is returned for that entry Table 4 10 lists the encoding for the DD bits NOTE The port size field must be programmed for an internal DSACK response and the FTE bit in the base address register must be cleared for the DDx bits to have significance If external DSACK signals are returned earlier than indicated by the DDx bits the cycle will terminate sooner than programmed See 4 2 5 2 PORT B for a discussion on using the internal DSACK z generation without using
283. ducing memory requirements Intermediate values are recovered with this instruction via linear interpolation The results may be rounded by a round to nearest algorithm 5 1 7 2 LOW POWER STOP INSTRUCTION In applications where power consumption is a consideration the CPUS32 forces the device into a low power standby mode when immediate processing is not required The low power stop mode is entered by executing the LPSTOP instruction The processor will remain in this mode until a user specified or higher interrupt level or reset occurs 5 1 8 Processing States The processor is always in one of four processing states normal exception halted or background The normal processing state is that associated with instruction execution the bus is used to fetch instructions and operands and to store results The exception processing state is associated with interrupts trap instructions tracing and other exception conditions The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction Externally exception processing can be forced by an interrupt a bus error or a reset The halted processing state is an indication of catastrophic hardware failure For example if during the exception processing of a bus error another bus error occurs the processor assumes that the system is unusable and halts The background processing state is initiated by breakpoints execution
284. dump large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result Subsequent operands are retrieved with the DUMP command Fill Memory Block FILL Used in conjunction with the WRITE command to fill large blocks of memory An initial WRITE is executed to set up the starting address of the block and to supply the first operand Subsequent operands are written with the FILL command Resume Execution GO The pipeline is flushed and refilled before resuming instruction execution at the return PC Call User Code CALL Current PC is stacked at the location of the current SP Instruction execution begins at user patch code Reset Peripherals RST Asserts RESET for 512 clock cycles The CPU is not reset by this command Synonymous with the CPU RESET instruction No Operation performs no operation and may be used as a null command 5 6 2 8 4 Read A D Register RAREG RDREG Read the selected address or data register and return the results via the serial interface Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 Abo Command Sequence RDREG RAREG S XXX NEXT CMD 77 MS RESULT LS RESULT XXX gt NEXT CMD ILLEGAL NOT READY Operand Data None 5 76 MC68340 USER S MANUAL MOTOROLA Result Data The contents of the selected register are returned as a long word value The data is return
285. dware breakpoint handler De allocate the stack and return control to the faulted program 5 5 3 2 5 Type Ill Correcting Faults by Conversion and Restart In some situations it may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand Clearing the MV bit in the stacked SSW converts a type fault into a type fault Consequently MOVEM like all other type Il 5 58 MC68340 USER S MANUAL MOTOROLA exceptions will be restarted upon return from the exception handler When a fault occurs after an operand has transferred that transfer is not undone However these memory locations are accessed a second time when the instruction is restarted If a register used in an EA calculation is overwritten before a fault occurs an incorrect EA is calculated upon instruction restart 5 5 3 2 6 Type Ill Correcting Faults via RTE The preferred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents The RTE recognizes that MOVEM was in progress when a fault occurred restores the appropriate machine state refetches the instruction repeats the faulted transfer and continues the instruction MOVEM is the only instruction continued upon return from an exception handler Although the instruction is refetched the EA is not recalculated and the mask is rescanned the same number of times as before
286. dware interlocks in the CPU prevent result data from corrupting serial transfers in progress 5 6 2 7 2 Development System Serial Logic The development system as the master of the serial data link must supply the serial clock However normal and BDM operations could interact if the clock generator is not properly designed Breakpoint requests are made by asserting BKPT to the low state in either of two ways The primary method is to assert BKPT during a single bus cycle for which an exception is desired Another method is to assert BKPT then continue to assert it until the 2 responds by asserting FREEZE This method is useful for forcing a transition into BDM when the bus is not being monitored Each method requires a slightly different serial logic design to avoid spurious serial clocks Figure 5 24 represents the timing required for asserting BKPT during a single bus cycle MOTOROLA MC68340 USER S MANUAL 5 71 FORCE BGND BKPT TAG LLL LOS WU i TTFUILITTLFULTLFTLTUFLTLTTATLI FREEZE ls Figure 5 24 BKPT Timing for Single Bus Cycle Figure 5 25 depicts the timing of the BKPT FREEZE method In both cases the serial clock is left high after the final shift of each transfer This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session As mentioned previously all timing within the CPU is derived f
287. e counter TOUTx responds as selected by the CR bits A square wave generator can be implemented by programming the CR bits to toggle mode The value in the COM should be one half the value in PREL1 to cause an event to happen twice in the countdown This mode can be used as a pulse width modulator by programming the CR bits to zero mode or one mode The value in the PREL1 specifies the frequency and the COM determines the pulse width The pulse widths can be changed by writing a new value to the COM MOTOROLA MC68340 USER S MANUAL 8 7 Periodic interrupt generation can be accomplished by enabling the TO TG and or TC bits in the SR to generate interrupts by programming the IE bits of the CR When enabled the programmed signal is asserted whenever the specified bits are set TOUTx signal transitions can be controlled by writing new values into the COM Caution must be exercised when accessing the COM If it were to be accessed simultaneously by the compare logic and by a write the old compare value may actually get compared to the counter value 8 3 2 Square Wave Generator This mode can be used for generating both square wave output and periodic interrupts The square wave is generated by counting down from the value in the PREL1 to timeout counter value of 0000 TOUTx changes state on each timeout as programmed This mode can be selected by programming the CR MODEx bits to 001 The timer is enabled by s
288. e S bit in the SR are privileged The TRAP n instruction provides controlled user access to operating system services 5 4 2 2 USER PRIVILEGE LEVEL If the S bit in the SR is cleared the processor executes instructions at the user privilege level The bus cycles for an instruction executed at the user privilege level are classified as user references and the values of the function codes FC2 FCO specify user address spaces While the processor is at the user level implicit references to the system SP and explicit references to address register seven A7 refer to the USP 5 4 2 3 CHANGING PRIVILEGE LEVEL To change from user privilege level to supervisor privilege level a condition that causes exception processing must occur When exception processing begins the current values in the SR including the S bit are saved on the supervisor stack and then the S bit is set to enable supervisory access Execution continues at supervisor privilege level until exception processing is complete To return to user access level a system routine must execute one of the following instructions MOVE to SR ANDI to SR EORI to SR ORI to SR or RTE These instructions execute only at supervisor privilege level and can modify the S bit of the SR After these instructions execute the instruction pipeline is flushed then refilled from the appropriate address space The RTE instruction causes a return to a program that was executing when an exception occur
289. e allows a data reception speed advantage but does have a disadvantage since each character is not individually checked for error conditions by software If an error occurs within the message the error is not recognized until the final check is performed and no indication exists as to which character in the message is at fault In either mode reading the SR does not affect the FIFO The FIFO is popped only when the receive buffer is read The SR should be read prior to reading the receive buffer If all three of the FIFO s receiver holding registers are full when a new character is received the new character is held in the receiver shift register until a FIFO position is available If an additional character is received during this state the contents of the FIFO are not affected However the character previously in the receiver shift register is lost and the OE bit in the SR is set when the receiver detects the start bit of the new overrunning character To support control flow capability the receiver can be programmed to automatically negate and assert RTS When in this mode RTS is automatically negated by the receiver when a valid start bit is detected and the FIFO stack is full When a FIFO position becomes available RTS is asserted by the receiver Using this mode of operation overrun errors are prevented by connecting the RTS to the CTS input of the transmitting device If the FIFO stack contains characters and the receiver is d
290. e channel A transmitter POUTCH sends the character in the lower byte of DO to the channel B transmitter 7 4 2 3 INTERRUPT HANDLING The interrupt handling routine consists of SIRQ which is executed after the serial module generates an interrupt caused by a channel A change in break beginning of a break SIRQ then clears the interrupt source waits for the next change in break interrupt end of break clears the interrupt source again then returns from exception processing to the system monitor 7 40 MC68340 USER S MANUAL MOTOROLA SERIAL MODULE ENABLA INITIATE CHANNEL A CHANNEL B INTERRUPTS ANY ERRORS IN CHANNEL A CHK1 POINT TO CHANNEL A CALL CHCHK ENABLB SAVE CHANNEL A ST ATUS ANY ERRORS IN CHANNEL B CHK2 POINT TO CHANNEL B CALL CHCHK ENABLE CHANNEL B S TRANSMITTER SINITR RETURN Figure 7 10 Serial Module Programming Flowchart 1 of 5 SAVE CHANNEL B STATUS MOTOROLA MC68340 USER S MANUAL 7 41 CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE CHANNEL S TRANSMITTER CLEAR CHANNEL STATUS WORD TxCHK p WAITED TOO LONG TRANSMITTER READY SEND CHARACTER TO TRANSMITTER SET TRANSMITTER NEVER READY FLAG RECEIVER WAITED SET RECEIVER RECEIVED TOO LONG NEVER READY FLAG CHARACTER Figure 7 10 Serial Module Programming Flowch
291. e cycle this indicates that the external device has successfully stored the data and that the cycle may terminate These signals also indicate to the MC68340 the size of the port for the bus cycle just completed see Table 3 3 Refer to 3 3 1 Read Cycle for timing relationships of 5 1 and DSACKO Additionally the system integration module SIM40 chip select address mask register can be programmed to internally generate DSACK1 and DSACKO for external accesses eliminating logic required to generate these signals However if external DSACK signals are returned earlier than indicated by the DD bits in the chip select address mask register the cycle will terminate sooner than programmed Refer to Section 4 System Integration Module for additional information The SIM40 can alternatively be programmed to generate a fast termination cycle providing a two cycle external access Refer to 3 2 6 Fast Termination Cycles for additional information on these cycles 3 4 MC68340 USER S MANUAL MOTOROLA 3 1 7 2 BUS ERROR BERR This signal is also a bus cycle termination indicator and can be used in the absence of DSACK s to indicate a bus error condition BERR can also be asserted in conjunction with DSACK to indicate a bus error condition provided it meets the appropriate timing described in this section and in Section 11 Electrical Characteristics Additionally BERR and HALT can be asserted together to indicate a retry termination Refer to 3 5 B
292. e for the channel PT Parity Type This bit selects the parity type if parity is programmed by the parity mode bits and if multidrop mode is selected it configures the transmitter for data character transmission or address character transmission Table 7 2 lists the parity mode and type or the multidrop mode for each combination of the parity mode and the parity type bits Table 7 2 PMx and PT Control Bits No Parity Multidrop Mode Multidrop Mode B C1 B CO Bits per Character These bits select the number of data bits per character to be transmitted The character length listed in Table 7 3 does not include start parity or stop bits No Parity Data Character Address Character Pm EE M EU 0 1 1 HighParity MOTOROLA MC68340 USER S MANUAL 7 23 Table 7 3 B Cx Control Bits Lo mem of ses CON 7 4 1 5 STATUS REGISTER SR The SR indicates the status of the characters in the FIFO and the status of the channel transmitter and receiver This register can only be read when the serial module is enabled i e the STP bit in the MCR is cleared SRA SRB 711 719 7 6 5 4 3 2 1 0 re Te Tee nay RESET 0 0 0 0 0 0 0 0 Read Only Supervisor User RB Received Break 1 all zero character of the programmed length has been received without a stop 0 bit The RB bit is onl
293. e fs po aero e MSIE a p 3 p owems cM E 1 ERE 7 puces tra ERE 11971 Reset Receiver The reset receiver command resets the channel receiver receiver is immediately disabled the FFULL and RxRDY bits in the SR are cleared and the receiver FIFO pointer is reinitialized All other registers are unaltered This command should be used in lieu of the receiver disable command whenever the receiver configuration is changed because it places the receiver in a known state Reset Transmitter The reset transmitter command resets the channel transmitter The transmitter is immediately disabled and the and TxRDY bits the SR are cleared All other registers are unaltered This command should be used in lieu of the transmitter disable command whenever the transmitter configuration is changed because it places the transmitter in a known state Reset Error Status The reset error status command clears the channel s RB FE PE and OE bits in the SR This command is also used in the block mode to clear all error bits after a data block is received Reset Break Change Interrupt The reset break change
294. e generator and variable width single shot pulse generator modes When in either of these modes the value in PREL1 is loaded into the counter on the first falling edge of the counter clock after the counter is enabled After timeout the value in PREL2 is loaded into the counter This register can be be read and written when the timer module is enabled i e the STP bit in the MCR is cleared However a write to this register must be completed before timeout for the new value to be reliably loaded into the counter PREL2 60E 64E 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Supervisor User 8 4 8 Compare Register COM The COM can be used in any mode When the 16 bit counter reaches the value in the COM the TC and COM bits in the SR are set In the input capture output compare mode a compare event can be programmed to set clear or toggle TOUTx The register can be be read and written when the timer module is enabled i e the STP bit in the MCR is cleared COM 610 650 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Supervisor User The COM can be used to produce an interrupt when the SR TC bit has been enabled to produce an interrupt and the counter counts down to a preselected value The COM can also be used to indicate that the timer is approaching timeout 8 26 MC68340 USER S MANUAL MOTOROLA Caution must be exercised when accessing the COM If it w
295. e gites 5 87 5 6 3 3 Opcode Tracking during Loop 5 88 5 7 Instruction Execution ccce eret tete tone tnter Peer eee 5 88 5 7 1 Reso rce Sochedulifig auo ett De 5 88 5 7 1 1 eb 5 89 5 7 1 2 Instruction PIBellle eet t ceat dee e ced 5 89 xX MC68340 USER S MANUAL MOTOROLA 11 2 95 Paragraph Number 5 7 1 3 5 7 1 3 1 5 7 1 3 2 5 7 1 3 3 5 7 1 4 5 7 1 5 5 7 1 6 5 7 1 7 5 7 2 5 7 2 1 5 7 2 2 5 7 2 3 5 7 3 5 7 3 1 5 7 3 2 5 7 3 3 5 7 3 4 5 7 3 5 5 7 3 6 5 7 3 7 5 7 3 8 5 7 3 9 5 7 3 10 5 7 3 11 5 7 3 12 5 7 3 13 5 7 3 14 6 1 6 2 6 2 1 6 2 2 6 2 3 6 3 6 3 1 6 3 1 1 6 3 1 2 6 3 2 6 3 2 1 MOTOROLA SECTION 1 OVERVIEW UM Rev 1 TABLE OF CONTENTS Continued Page Title Number Bus Controller 22 4 4 000 nennen 5 89 Prefetch Gohtrollet sot ioo ene 5 90 Write Pending Buffer cocotte 5 90 Microb s ONCOL 5 91 Instruction Execution 5 91 Effects of Wat SLA 5 92 Instruction Execution Time 5 92 Effects of Negative 5 93 Instruction Stream Timing Examples esses 5 94 Timing Example 1 Execution
296. e groups are shown in the following table for the RP suffix package Pin Group RP Suffix P7 Address Bus Function Codes D2 G3 K3 K14 M3 D3 G2 J3 K13 M2 C14 F13 D13 G13 AS BG CLKOUT DS FREEZE HALT IFETCH IPIPE M13 N4 N9 P9 N3 N7 N10 N13 MODCK RESET RMC R W SIZx TDO TOUT1 Internal Logic 5 DACK DONE RTS Re RDYA TOUT2 B11 C4 C7 C5 C8 C11 TxDx T RDYA Internal Logic Oscillator Wer xd Internal Only H3 H13 MOTOROLA MC68340 USER S MANUAL 12 5 12 3 PACKAGE DIMENSIONS 12 3 1 FE Suffix FE SUFFIX PACKAC gt X CERAMIC QFP CASE 863A 01 TT DU CE DDR ALL PINON Noe a A c E a S E E TOP VIEV TRIMMED FORMED DISCRET SHOWING DATUM FEATUF a gt I lt LE Z lt Em EX C Ly uu o m L LI L i L Lu L Y r Q gt 0 501 6 209 Y W 0 1 144 SEATING PLANI D144 0 210 0 2069 F6 0 20 T xvo 26 o 2 l T Z 9 XX GUL
297. e illegal instruction vector or in the case of an unimplemented instruction to the corresponding emulation vector The illegal instruction vector number current PC and a copy of the SR are saved on the supervisor stack with the saved value of the PC being the address of the illegal or unimplemented instruction 5 5 2 9 PRIVILEGE VIOLATIONS To provide system security certain instructions can be executed only at the supervisor access level An attempt to execute one of these instructions at the user level will cause an exception The privileged exceptions are as follows AND Immediate to SR EOR Immediate to SR LPSTOP MOVE from SR e MOVE to SR e MOVE USP e MOVEC e MOVES OR Immediate to SR RESET e e STOP Exception processing for privilege violations is nearly identical to that for illegal instructions The instruction is fetched and decoded If the processor determines that a privilege violation has occurred exception processing begins before instruction execution Exception processing follows the regular sequence The vector number 8 is generated to reference the privilege violation vector Privilege violation vector offset current PC and SR are saved on the supervisor stack The saved PC value is the address of the first word of the instruction causing the privilege violation 5 48 MC68340 USER S MANUAL MOTOROLA 5 5 2 10 TRACING To aid in program development M68000 processors include a facility
298. e interrupts has an interrupt vector IV field This 8 bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located The IV field is reset to 0F which indicates an uninitialized interrupt condition See Section 5 CPU32 for more information 8 4 3 Control Register CR The CR controls the operation of the timer The register can always be read or written when the timer module is enabled i e the STP bit in the MCR is cleared Changing the contents of the CR should only be attempted when the timer is disabled the SWR bit in the CR is cleared Changing the CR while the timer is running may produce unpredictable results CR 606 646 Supervisor User SWR Software Reset 1 Removes the software reset 0 A software reset is performed by first clearing this bit and then clearing the TG and TC bits in the SR The prescaler is loaded with FF the counter is set to 0000 and the SR COM bit is cleared When this bit is zero the timer is disabled 8 20 MC68340 USER S MANUAL MOTOROLA IE2 IEO Interrupt Enable These bits determine which sources of interrupts TO TG and TC are enabled to generate an interrupt request to the CPU32 Table 8 3 lists which interrupts are enabled for all bit combinations Table 8 3 IEx Encoding Lie uer oe Enabledinterpis o o o Mode Wo Po fo tenes
299. e is written below the faulted exception stack frame The SSW for a fault within an exception contains the following bit pattern 15 14 18 12 11 10 9 8 7 6 5 4 3 2 0 1 61 sz TR B1 and are set if corresponding exception is pending when the bus error exception is taken The contents of the faulted exception stack frame are included in the bus fault stack frame The pre exception SR and the format vector word of the faulted frame are stacked The type of exception can be determined from the format vector word If the faulted exception stack frame contains six words the PC of the instruction that caused the initial 5 56 MC68340 USER S MANUAL MOTOROLA exception is also stacked This data is placed on the stack in the format shown in Figure 5 13 The return address from the initial exception is stacked for RTE 5 5 3 2 CORRECTING A FAULT There are two ways to complete a faulted released write bus cycle The first is to use a software handler The second is to rerun the bus cycle via RTE Type 11 fault handlers must terminate with RTE but specific requirements must also be met before an instruction is restarted There are three varieties of type Ill operand fault recovery The first is completion of an instruction in software The second is conversion to type II with restart via RTE The third is continuation from the fault via RTE 5 5 3 2 1 Type I Completing Released Writes via Softw
300. e setup and hold times for more than one DMA transfer to be recognized 4 DONEx input can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one Figure 6 9 Dual Address Read Timing External Burst Source Requesting 9 TWANVIN 6 07289921 V IOHOLON Sepoo y Hyda eui JO eoi ep y SI HHA ur y JO eor ep SOM YNA eui m ssejppe enp eui 31IHM SSa3duaav 1vna 22779 CLKOUT FC3 FCO SIZ1 SIZO DONEx INPUT DACKx DONEx OUTPUT NOTE 50 1 DREQx must be active for two consecutive clocks for a request to be recognized 2 To cause another DMA transfer the DREQx is asserted after DACKx is asserted and before DACKx is negated 3 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle CPU CYCLE 52 54 50 CPU CYCLE S2 54 SO DMA READ S2 54 50 DMA WRITE S2 54 so CPU CYCLE S2 54 50 DMA READ 52 54 50 4 DONEx input can be asserted in either the read or write bus cycle to indicate that the next transfer will be the last Figure 6 10 Dual Address Read Tim
301. e size of the source read bus cycle that the DMA channel is running Table 6 2 defines these bits Table 6 2 SSIZEx Encoding Bis ete Definition o o omowe 0o 1 L3 9 v External logic is required to complete a long word transfer 6 28 MC68340 USER S MANUAL MOTOROLA DSIZE Destination Size Control Field This field controls the size of the destination write bus cycle that the DMA channel is running Table 6 3 defines these bits Table 6 3 DSIZEx Encoding sis Demos o o tong Word Po fs ee L3 3 we External logic is required to complete long word transfer REQ Request Generation Field This field controls the mode of operation the DMA channel uses to make an operand transfer request Table 6 4 defines these bits Table 6 4 REQx Encoding Internal Request at Programmable Rate External Request Burst Transfer Mode External Request Cycle Steal BB Bus Bandwidth Field This field controls the percentage of 1024 clock periods of the IMB that the DMA channel can use during internal requests only Table 6 5 defines these bits Table 6 5 BBx Encoding and Bus Bandwidth REQ Field MOTOROLA MC68340 USER S MANUAL 629 S D Single Dual Address Transfer 1 The DMA channel runs single address transfers from a peripheral to memory or from memory to a peripheral The destination holding register is not used for these transfers because the data i
302. each level The S bit in the SR indicates privilege level and determines which SP is used for stack operations The processor identifies each bus access supervisor or user mode via function codes to enforce supervisor and user access levels In a typical system most programs execute at the user level User programs can access only their own code and data areas and are restricted from accessing other information The operating system executes at the supervisor privilege level has access to all resources performs the overhead tasks for the user level programs and coordinates their activities 5 4 2 1 SUPERVISOR PRIVILEGE LEVEL If the S bit in the SR is set supervisor privilege level applies and all instructions are executable The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references and the values of the function codes on FC2 FCO refer to supervisor address spaces MOTOROLA MC68340 USER S MANUAL 5 37 All exception processing is performed at the supervisor level All bus cycles generated during exception processing are supervisor references and all stack accesses use the SSP Instructions that have important system effects can only be executed at supervisor level For instance user programs are not permitted to execute STOP LPSTOP or RESET instructions To prevent a user program from gaining privileged access except in a controlled manner instructions that can alter th
303. ed as an input port that generates interrupts on a low to high transition of TGATE when the CR is configured as follows CR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGATE AS AN INPUT INTERRUPT X X 1 X 1 X 1 X X X X 1 1 1 X X When TGATE is negated the SR TG bit is set and the programmed IRQx signal is asserted to the CPU32 The TG bit can only be cleared by writing a one to this bit position The value of the SR TGL bit reflects the level of TGATE Additionally TOUTx can be used as a simple output port when the CR is configured as follows CR 6 5 4 3 2 15 14 13 12 11 10 9 8 7 1 0 TGATE AS A SIMPLE OUTPUT 0 X X X X X 1 X X X X 1 1 1 OC1 OCO SWR must be a zero to change the value of TOUTx Changing the value of the CR OCx bits determines the level of TOUTx as shown in Table 8 1 8 16 MC68340 USER S MANUAL MOTOROLA Table 8 1 Encoding A read of the SR while in this mode always shows the TO TC and COM bits cleared and the PO bits as FF The SR OUT bit always indicates the level on the TOUTx pin 8 3 9 Bus Operation The following paragraphs describe the operation of the IMB during read write and interrupt acknowledge cycles to the timer 8 3 9 1 READ CYCLES The timer is accessed with no wait states The timer responds to byte word and long word reads and 16 bits of valid data are returned Read cycles from reserved registers return logic zero 8 3 9 2 WRITE CYCLES The timer is accessed with n
304. ed from the EXTAL input pin unless an external frequency source is used When an external frequency source is used MODCK low during reset the default state of the prescaler control bits SWP and PTP in the PITR is changed to enable both prescalers Either clock source EXTAL or EXTAL 512 is divided by 4 before driving the modulus counter PITCLK When the modulus counter value reaches zero an interrupt is generated The level of the generated interrupt is programmed into the PIRQL bits in the periodic interrupt control register PICR During the IACK cycle the SIM40 places the periodic interrupt vector programmed into the PIV bits in the PICR onto the internal bus The value of bits 7 0 in the PITR is then loaded again into the modulus counter and the counting process starts over If a new value is written to the PITR this value is loaded into the modulus counter when the current count is completed MOTOROLA MC68340 USER S MANUAL 4 7 4 2 2 6 1 Periodic Timer Period Calculation The period of the periodic timer can be calculated using the following equation PITR count value periodic interrupt timer period frequency prescaler value 22 Solving the equation using a crystal frequency of 32 768 kHz with the prescaler disabled gives PITR count value periodic interrupt timer period 32768 1 22 periodic interrupt timer period PITR count value 8192 This gives a range from 122 us with a PITR value of 01 0
305. ed most significant word first 5 6 2 8 5 Write A D Register WAREG WDREOQ The operand long word data is written to the specified address or data register All 32 bits of the register are altered by the write Command Format 15 14 18 12 11 10 9 8 7 6 5 4 3 2 0 1 reaster Command Sequence WDREGAWAREG CR MT DATA ENDE DATA NEXT 22 Gor RAT READY ene READY COMPLETE NEXT CMD ILLEGAL NOT READY Operand Data Long word data is written into the specified address or data register The data is supplied most significant word first Result Data Command complete status 0FFFF is returned when register write is complete 5 6 2 8 6 Read System Register RSREG The specified system control register is read All registers that can be read in supervisor mode can be read in BDM Several internal temporary registers are also accessible Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 0 pe Command Sequence RSREG N NEXT CMD N GHD RESULT CI RESULT RESULT NEXT CMD N ILLEGAL 7 ROT READY READY Operand Data None MOTOROLA MC68340 USER S MANUAL 5 77 Result Data Always returns 32 bits of data regardless of the size of the register being read If the register is less than 32 bits the result is returned zero extended Register Field The system control
306. eeceeeeeeeeeeeeeeeseeseeeeeeeeseeeaeeeeeeeeees 10 13 Skew between Two Outputs sese 10 14 Circuitry for Interfacing 8 Bit Device to 16 Bit Memory in Single Address DMAoOMOGS s tal ets etos br t e es 10 15 MC68340 Current vs Activity 10 16 68340 Current vs 2 10 17 MC68340 Current vs Clock Frequency at 5 11 1 Drive Levels and Test Points for AC Specifications 11 2 Read Cycle Timing 11 3 Write Cycle Timing Diagram eese teen 11 4 Fast Termination Read Cycle Timing Diagram 11 5 Fast Termination Write Cycle Timing 11 6 Bus Arbitation Timing Active Bus 11 7 Bus Arbitration Timing ldle Bus Case sss 11 8 Show Cycle Timing Diag Al aeos terio oor aicut teens 11 9 IACK Cycle Timing 2 2 11 10 Background Debug Mode Serial Port 11 11 Background Debug Mode FREEZE 11 12 DMA Signal Timing Diagram essent 11 13 Timer Module Clock Signa
307. eeeaeeeseeeesateatenees 3 19 3 10 CPU Space Address Encodilig reet Eee e t te Enos 3 21 3 11 Breakpoint Operation Flowchart sse 3 24 3 12 Breakpoint Acknowledge Cycle Timing Opcode Returned 3 25 3 13 Breakpoint Acknowledge Cycle Timing Exception Signaled 3 26 3 14 Interrupt Acknowledge Cycle Flowchart esses 3 28 3 15 Interrupt Acknowledge Cycle Timing sees 3 29 3 16 Autovector Operation Timing eessssssssseseseseseeetne te 3 31 3 17 Bus Error without DSACKE nuo tar donor me Ep redde uci aa 3 35 3 18 Late Bus Error with 3 36 3519 ROU SCG INC 2 uL 3 37 3 20 Late Retry 2 0 3 38 3 2 AALT SUPA ROTE E Hot ade 3 39 3 22 Bus Arbitration Flowchart for Single 3 41 3 23 Bus Arbitration Timing Diagram ldle Bus 3 42 3 24 Bus Arbitration Timing Diagram Active Bus 3 42 3 25 Arbitration State ds Deben b usar eves cee eles 3 45 3 26 Show Cycle Timing Diagram s oui i
308. eguarded design present in all M68000 members In addition many functions that normally must be provided by external circuits are incorporated in this device The following features are provided in the system configuration and protection function SIM40 Module Configuration The SIM40 allows the user to configure the system to the particular requirements The functions include control of FREEZE and show cycle operation the function of the CS signals the access privilege of the supervisor user registers the level of interrupt arbitration and automatic vectoring for external interrupts Reset Status The reset status register provides the user with information on the cause of the most recent reset The possible causes of reset include external power up software watchdog double bus fault loss of clock and RESET instruction MOTOROLA MC68340 USER S MANUAL 4 3 Internal Bus Monitor The SIM40 provides an internal bus monitor to monitor the DSACK response time for all internal bus accesses An option allows the monitoring of external bus accesses For external bus accesses four selectable response times are provided to allow for variations in response speed of memory and peripherals used in the system A bus error signal is asserted internally if the response limit is exceeded BERR is not asserted externally This monitor can be disabled for external bus cycles only Double Bus Fault Monitor The double bus fault monitor
309. el lt 5 esas o en 5 5 5 5 5 5 fo S UII D R e 9 eo on gt lt 2 2 i el an e d 32 An or d32 PC An Xm or da PC Xm d 45 An Xm Sz x Sc or d45 PC Xm Sz x Sc 0 1 2 3 4 d ao An Xm Sz x Sc or d32 PC Xm Sz x Sc 9 3 0 1 2 3 4 X There is one bus cycle for byte and word operands and two bus cycles for long word operands For long word bus cycles add two clocks to the tail and to the number of cycles NOTES 1 The read of the EA and replacement fetches overlap the head of the operation by the amount specified in the tail 2 Size and scale of the index register do not affect execution time 3 The PC may be substituted for the base address register An L R p e 09 gt lt e TH 51 x gt lt 65 Y 106 o 4 When adjusting the prefetch time for slower buses extra clocks may be subtracted from the head until the head reaches zero at which time additional clocks must be added to both the tail and cycle counts MOTOROLA MC68340 USER S MANUAL 5 99 5 7 3 2 CALCULATE EFFECTIVE ADDRESS The calculate EA table indicates the number of clock periods needed for the processor to calculate a specified EA The timing is equivalent to fetch EA except there is
310. elocatable along 4 Kbyte boundaries The location of the internal registers is fixed by writing the desired base address of the 4 Kbyte block to the MBAR using the MOVES instruction to address 0003FF00 in CPU space The source function code SFC and destination function code DFC registers contain the address space values FC3 FCO for the read or write operand of the MOVES instruction see Section 5 CPU32 or M68000PM AD Programmer s Reference Manual Therefore the SFC DFC register must indicate CPU space FC3 FCO 7 using the MOVEC instruction before accessing MBAR The offset from the base address is shown above each register diagram 4 2 MC68340 USER S MANUAL MOTOROLA FFFFFFFF XXXXXFFF MC68340 RELOCATABLE MODULE Bock 222222222 SERIAL PORTS 222222 TIMER MODULES SIM 40 D MBAR 000 0003FF00 gt FC 0111 RAM TYPICAL 00000000 NOTE XXXXX is the value contained in the MBAR bits BA31 BA12 Figure 4 1 SIM40 Module Register Block 4 2 2 System Configuration and Protection Operation The SIM40 allows the user to control certain features of system configuration by writing bits in the module configuration register MCR This register also contains read only status bits that show the state of the SIM40 All M68000 family members are designed to provide maximum system safeguards As an extension of the family the MC68340 promotes the same basic concepts of saf
311. em clock when a read of its location is not in progress allowing the most current information to be contained in this register The register can be read and the TO TG and TC bits can be written when the timer module is enabled i e the STP bit in the MCR is cleared SR 608 648 RESET NEGATED 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 RESET ASSERTED 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Supervisor User IRQ Interrupt Request bit The positioning of this bit in the most significant location in this register allows it it be conditionally tested as if it were a signed binary integer 1 An interrupt condition has occurred This bit is the logical OR of the enabled TO TG and TC interrupt bits 0 The bit s that caused the interrupt condition has been cleared If an IRQ signal has been asserted it is negated when this bit is cleared MOTOROLA MC68340 USER S MANUAL 8 23 TO Timeout Interrupt 1 The counter has transitioned from 0001 to 0000 and the counter has rolled over This bit does not affect the programmed IRQ signal if the IE2 bit in the CR is cleared 0 This bit is cleared by the timer whenever the RESET signal is asserted on the IMB regardless of the mode of operation This bit may also be cleared by writing a one to it Writing a zero to this bit does not alter its contents This bit is not affected by disabling the timer SWR 0 TG Timer Gate Interrupt 1 This bit is set wheneve
312. ent SR the address of the faulted memory location and the contents of the data buffer that was to be written to memory This data is written on the stack in the format depicted in Figure 5 15 When a released write fault exception handler executes the machine will complete the faulted write and then continue executing instructions wherever the PC indicates 5 5 3 1 2 Type 11 Operand RMW and MOVEP Faults The majority of bus error exceptions are included in this category all instruction prefetches all operand reads all RMW cycles and all operand accesses resulting from execution of MOVEP except the last write of a MOVEP Rn ea or the last write of MOVEM which type faults The TAS MOVEP and MOVEM instructions account for all operand writes not considered released All type Il faults cause an immediate exception that aborts the current instruction Any registers that were altered as the result of an EA calculation i e postincrement or predecrement are restored prior to processing the bus cycle fault The SSW for faults in this category contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 o o 8B jg o Re ta The trace pending bit is always cleared since the instruction will be restarted upon return from the handler Saving a pending exception on the stack causes a trace exception to be taken prior to restarting the instruction If the exceptio
313. entation package for the MC68340 consists of the MC68340UM AD MC68340 Integrated Processor with DMA User s Manual M68000PM AD MC68000 Family Programmer s Reference Manual and the MC68340P D MC68340 Integrated Processor with DMA Product Brief The MC68340 Integrated with DMA Processor User s Manual describes the programming capabilities registers and operation of the MC68340 the MC68000 Family Programmer s Reference Manual provides instruction details for the MC68340 and the MC68340 Integrated Processor with DMA Product Brief provides a brief description of the MC68340 capabilities This user s manual is organized as follows Section 1 Device Overview Section8 Modules Section 2 Signal Descriptions Section 9 IEEE 1149 1 Test Access Section 3 Bus Operation Port Section 4 System Integration Module Section 10 Applications Section 5 CPU32 Section 11 Electrical Characteristics Section 6 Controller Module Section 12 Ordering Information and Section 7 Serial Module Mechanical Data 68K FAX IT FAX 512 891 8593 The Motorola High End Technical Publication Department provides a FAX number for you to submit any questions and comments about this document We welcome your suggestions for improving our documentation or any questions concerning our products Please provide the part number and revision number located in upper right hand corner on the cover and the title of the document when submitting When referring to items in
314. ept the open drain pins DONE1 DONE2 HALT and RESET have a single register bit for pin data and an associated control bit in the boundary scan register All open drain I O pins have two register bits input and output for pin data and no associated control bit To ensure proper operation the open drain pins require external pullups Twenty three control bits in the boundary scan register define the output enable signal for associated groups of bidirectional and three state pins The control bits and their bit positions are listed in Table 9 1 MOTOROLA MC68340 USER S MANUAL 9 3 Table 9 1 Boundary Scan Control Bits ame simae name name BitNombor ma w ama 9 aen 125 Boundary scan bit definitions are shown in Table 9 2 The first column in Table 9 2 defines the bit s ordinal position in the boundary scan register The shift register bit nearest TDO i e first to be shifted out is defined as bit 0 the last bit to be shifted out is 131 The second column references one of the five MC68340 cell types depicted in Figures 9 3 9 7 which describe the cell structure for each type The third column lists the pin name for all pin related bits or defines the name of bidirectional control register bits The active level of the control bits i e output driver on is defined by the last digit of the cell type listed for each control bit For example the active high level for
315. equivalent precaution should be designed into the external circuitry to provide these signals Alternatively the internal bus monitor could be used The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK assertion as follows case numbers refer to Table 3 4 Normal Termination DSACK is asserted BERR and HALT remain negated case 1 Halt Termination HALT is asserted at the same time as or before DSACKx and BERR remains negated case 2 Bus Error Termination BERR is asserted in lieu of at the same time as or before DSACK case 3 or after DSACK case 4 HALT remains negated BERR is negated at the same time as or after Retry Termination HALT and are asserted in lieu of at the same time as or before DSACK case 5 or after DSACK case 6 is negated at the same time as or after DSACK HALT may be negated at the same time as or after BERR Table 3 4 lists various combinations of control signal sequences and the resulting bus cycle terminations To ensure predictable operation BERR and HALT should be negated according to the specifications given in Section 11 Electrical Characteristics BERR and HALT may be negated after AS If DSACK or BERR remain asserted into S2 of the next bus cycle that cycle may be terminated prematurely EXAMPLE A A system uses a bus monitor timer to terminate accesses to an unpopulated address
316. er Enable serial module for normal operation ignore FREEZE select the crystal clock Supervisor user serial registers unrestricted Interrupt arbitration at priority 02 MOVE B 00 MCRH A0 MOVE B 4 02 MCRL AO WAIT FOR TRANSMITTER EMPTY OR TIMEOUT MOVE W 2000 D0 init loop counter XBMTWAIT EQU BTST 13 SRA AO0 TX empty in status reg NOP DBNE DO XBMTWAIT loop until set or timeout NEGATE RTSA SIGNAL OUTPUT MOVE B 0 OPCR AO make 7 general purpose MOVE B 01 BR AO clear RTSA OPO output RESET RECEIVER TRANSMITTER MOVE B 20 CRA A0 Issue reset receiver command MOVE B 30 CRA A0 Issue reset transmitter command SET BAUD RATE SET 2 MOVE B 80 ACR A0 MODE REGISTER 1 MOVE B 93 MR1A A0 8 bits no parity auto RTS control 7 48 MC68340 USER S MANUAL MOTOROLA MODE REGISTER 2 MOVE B 07 2 Normal 1 stop bit SET UP BAUD RATE FOR PORT IN CLOCK SELECT REGISTER MOVE B BB CSRA A0 Set 9600 baud for RX and TX SET RTSA ACTIVE MOVE B 01 OP_BS A0 set RTSA OPO output ENABLE PORT MOVE B 45 CRA A0 Reset error status enable RX amp TX END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MOTOROLA MC68340 USER S MANUAL 7 49 SECTION 8 TIMER MODULES Each MC68340 timer module contains a counter timer timer 1 and timer 2 as shown in Figure 8 1 Each timer interfaces directly to the CPU32 via the intermodule bus IMB Each timer co
317. er 2 for information on programming the transmitter RTS control R F Receiver Ready Select 1 Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel FIFO full status These ISR bits are set when the receiver FIFO is full and are cleared when a position is available in the FIFO 0 Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiver ready status These ISR bits are set when a character has been received and are cleared when the CPU32 reads the receive buffer 7 22 MC68340 USER S MANUAL MOTOROLA ERR Error Mode This bit controls the meaning of the three FIFO status bits RB FE and PE in the SR for the channel 1 Block mode The values in the channel SR are the accumulation i e the logical OR of the status for all characters coming to the top of the FIFO since the last reset error status command for the channel was issued Refer to 7 4 1 7 Command Register CR for more information on serial module commands 0 Character mode The values in the channel SR reflect the status of the character at the top of the FIFO NOTE ERR 0 must be used to get the correct A D flag information when in multidrop mode PM1 PMO0 Parity Mode These bits encode the type of parity used for the channel see Table 7 2 The parity bit is added to the transmitted character and the receiver performs a parity check on incoming data These bits can alternatively select multidrop mod
318. eration for information on the address bus and its relationship to bus operation 2 2 1 Address Bus 23 0 These three state outputs along with A31 A24 provide the address for the current bus Cycle except in the CPU address space 2 2 2 Address Bus A31 A24 These pins can be programmed as the most significant eight address bits port A parallel or interrupt acknowledge signals These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves interaction between the different functions A31 A24 These pins can function as the most significant eight address bits Port 7 0 These eight pins can serve as a dedicated parallel I O port See Section 4 System Integration Module for more information on programming these pins IACK7 IACK1 The MC68340 asserts one of these pins to indicate the level of an external interrupt during an interrupt acknowledge cycle Peripherals can use the IACK signals instead of monitoring the address bus and function codes to determine that an interrupt acknowledge cycle is in progress and to obtain the current interrupt level 2 3 DATA BUS D15 DO This bidirectional nonmultiplexed parallel bus contains the data being transferred to or from the MC68340 A read or write operation may transfer 8 or 16 bits of data one or two bytes in one bus cycle During a read cycle the data is latched by the MC68340 on the 2 4
319. ere to be accessed simultaneously by the compare logic and by a write the old compare value may get compared to the counter value 8 5 TIMER MODULE INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the timer module Since both timers are functionally equivalent only one timer module will be referenced 8 5 1 Timer Module Configuration If the timer capability of the MC68340 is being used the following steps should be followed to initialize a timer module properly Note that this sequence must be done for each timer module used Control Register CR Clear the SWR bit to disable the timer Status Register SR Clear the TO TG and TG bits to reset the interrupts Module Configuration Register MCR Initialize the STP for normal operation e Select whether to respond to or ignore FREEZE FRZx bits e Select the access privilege for the supervisor user registers SUPV bit e Select the interrupt arbitration level for the timer module IARBx bits Interrupt Register IR Program the interrupt priority level for the timer interrupts ILx bits Program the interrupt vector number for the timer interrupts IVx bits Preload Registers PREL1 and PREL2 If required initialize the preload registers for mode of operation Compare Register COM If desired initialize the compare register The following steps begin operation Control Register CR e Set the SWR bit to ena
320. erial data flow 7 2 9 2 OP1 When used for this function this output is controlled by bit 1 in the OP 7 2 10 Channel A Clear To Send CTSA This active low input is the channel A clear to send 7 2 11 Channel B Clear To Send CTSB This active low input is the channel B clear to send 7 2 12 Channel A Transmitter Ready T RDYA This active low output signal is programmable as the channel A transmitter ready or as a dedicated parallel output and cannot be masked by the interrupt enable register IER 7 2 12 1 T RDYA When used for this function this signal reflects the complement of the status of bit 2 of the channel A status register SRA This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character 7 2 12 2 OP6 When used for this function this output is controlled by bit 6 in the OP 7 2 13 Channel A Receiver Ready R RDYA This active low output signal is programmable as the channel A receiver ready channel A FIFO full indicator or a dedicated parallel output and cannot be masked by the IER 7 2 13 1 R RDYA When used for this function this signal reflects the complement of the status of bit 1 of the ISR This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character 7 2 13 2 FFULLA When used for this function this signal reflects the complement of the status of bit 1 of
321. ermine the number of cycles counted the value in CNTR1 must be read inverted and incremented by 1 MOVE W CNTR1 A0 DO NOT W DO ADDQ W 4 1 DO DO contains the number of cycles counted kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MOTOROLA MC68340 USER S MANUAL 8 31 SECTION 9 IEEE 1149 1 TEST ACCESS PORT The MC68340 includes dedicated user accessible test logic that is fully compatible with the EEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group JTAG The MC68340 implementation supports circuit board test strategies based on this standard The test logic includes a test access port TAP consisting of four dedicated signal pins a 16 state controller an instruction register and two test data registers A boundary scan register links all device signal pins into a single shift register The test logic implemented using static logic design is independent of the device system logic The MC68340 implementation provides the following capabilities a Perform boundary scan operations to test circuit board electrical continuity b Sample the MC68340 system pins during operation and transparent
322. ernal burst request mode or external cycle steal request mode REQ field Set the S D bit for signal address transfer Channel Status Register CSR Clear the CSR by writing 7C into it The DMA cannot be started until the DONE BES BED CONF and BRKP bits are cleared Function Code Register FCR Encode the source function code for a read cycle or the destination function code for a write cycle Address Register SAR or DAR Write the source address for a read cycle or the destination address for a write cycle Byte Transfer Counter BTC Encode the number of bytes to be transferred Channel Control Register CCR Write a one to the start bit STR to allow the transfer to begin 6 9 1 2 DMA CHANNEL OPERATION IN DUAL ADDRESS MODE The following steps are required to begin a DMA transfer in dual address mode Channel Control Register CCR Write a zero to the start bit STR to prevent the channel from starting the transfer prematurely Select the amount by which to increment the source and destination addresses SAPI and DAPI bits Select the source and destination sizes SSIZE and DSIZE fields Select internal request external burst request mode or external cycle steal request mode REQ field MOTOROLA MC68340 USER S MANUAL 6 37 If using internal request select the amount of bus bandwidth to be used by the DMA BB field Clear the S D bit for dual address transfer Channel Status Regis
323. errupt levels for internal autovectoring 4 36 MC68340 USER S MANUAL MOTOROLA System Protection Control Register SYPCR Note that this register only be written once after reset Enable the software watchdog if desired SWE bit If the watchdog is enabled select whether a system reset or a level 7 interrupt is desired at timeout SWRI bit If the watchdog is enabled select the timeout period SWTx bits Enable the double bus fault monitor if desired DBFE bit Enable the external bus monitor if desired BME bit Select timeout period for bus monitor BMTx bits Software Watchdog Interrupt Vector Register SWIV If using the software watchdog program the vector number for a software watchdog interrupt Periodic Interrupt Timer Register PITR If using the software watchdog select whether or not to prescale SWP bit If using the periodic interrupt timer select whether or not to prescale bit Program the count value for the periodic timer or program a zero value to turn off the periodic timer PITRx bits Periodic Interrupt Control Register PICR If using the periodic timer program the desired interrupt level for the periodic interrupt timer PIRQLx bits If using the periodic timer program the vector number for a periodic timer interrupt Chip Select Base Address and Address Mask Registers Initialize and set the V bits in the necessary chip select base address and addr
324. ership of the bus 3 40 MC68340 USER S MANUAL MOTOROLA Figure 3 22 is flowchart showing bus arbitration for a single device This technique allows processing of bus requests during data transfer cycles Refer to Figures 3 23 and 3 24 for bus arbitration timing diagrams BR is negated at the time that BGACK is asserted This type of operation applies to a System consisting of the MC68340 and one device capable of bus mastership In a system having a number of devices capable of bus mastership BR from each device can be wire ORed to the MC68340 In such a system more than one bus request could be asserted simultaneously BG is negated a few clock cycles after the transition of BGACK However if bus requests are still pending after the negation of BG the MC68340 asserts another BG within a few clock cycles after it was negated This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus The following paragraphs provide additional information about the three steps in the arbitration process Bus arbitration requests are recognized during normal processing HALT assertion and a CPU32 halt caused by a double bus fault PROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION ASSERT BR 1 ASSERT BG ACKNOWLEDGE BUS MASTERSHIP EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED
325. es an area of the stack for use Using this instruction in a series of subroutine calls will generate a linked list of stack frames The UNLK instruction removes a stack frame from the end of the list by loading an address into the SP and pulling the value at that address from the stack When the instruction operand is the address of the link address at the bottom of a stack frame the effect is to remove the stack frame from both the stack and the linked list 5 3 6 Pipeline Synchronization with the NOP Instruction Although the no operation NOP instruction performs no visible operation it does force synchronization of the instruction pipeline since all previous instructions must complete execution before the NOP begins 5 4 PROCESSING STATES This section describes the processing states of the CPU32 It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the processor in response to exception conditions 5 36 MC68340 USER S MANUAL MOTOROLA 5 4 1 State Transitions The processor is in normal background or exception state unless halted When the processor fetches instructions and operands or executes instructions it is in the normal processing state The stopped condition which the processor enters when a STOP or LPSTOP instruction is executed is a variation of the normal state in which no further bus cycles are generated Background state is an alternate operation
326. ese pins provide system power and ground to the MC68340 Multiple pins are provided for adequate current capability All power supply pins must have adequate bypass capacitance for high frequency noise suppression 2 18 SIGNAL SUMMARY Table 2 5 presents a summary of all the signals discussed in the preceding paragraphs MOTOROLA MC68340 USER S MANUAL 2 13 Table 2 5 Signal Summary SignalName Mnemonic Input Output Active State Three State AddessBus Interrupt Acknowledge mams m Function Codes Ou Ys Out In O Low Low Level Port B4 B2 B1 Bus Request EB O BsGem B BOACK S gt MER EN RT EN ial DSACKO mc tw wusste musme o se l smsm o e 8 2 Port B7 B6 B5 B3 IRQ5 IRQ3 CE semo wow 9 omoi Emo mo _ memes Coe Mode seroren eo vooo mo Instruction Fetch IFETCH DSI Out In Low No Development Serial In Instruction Pipe IPIPE DSO Out Out Low No Development Serial Out Breakpoint BKPT DSCLK In In Low Development Serial Clock No No Yes Yes Yes Yes Yes In Out In In Out Out Out Out ut 2 14 MC68340 USER S MANUAL MOTOROLA Table 2 5 Signal Summary Continued Signal Name Mnemoni
327. ess mask registers Following this step other system resources requiring the CS signals can be accessed Care must be exercised when changing the address for CSO The address of the instruction following the MOVE instruction to the CSO base address register must match the value of the PC at that time CSO must be taken out of global chip select mode by setting the V bit in the base address register before CS3 CS1 can be used Port A and B Registers e Program the desired function of the port A signals PPARA1 and PPARA2 registers Program the desired function of the port B signals PPARB register MOTOROLA MC68340 USER S MANUAL 4 37 4 4 3 SIM40 Example Configuration Code The following code is an example configuration sequence for the SIM40 module MC68340 basic SIM40 register initialization example code This code is used to initialize the MC68340 s internal 51 40 registers providing basic functions for operation It includes chip select programming for external devices This code would be programmed beginning at offset 0 into ROM which is relocated to address 60000 by the initialization code 55 RST vectors used to initialize the system stack pointer and initial PC respectively are located at offset 0 after reset kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk equates SSP_INIT EQU 10000 Stack pointer initial value top of RAM MBAR EQU 00
328. ess register channel 1 DMADAR1 EQU 10 destination address register channel 1 DMABTC1 EQU 14 byte transfer count register channel 1 SARADD EQU 6000 source address DARADD EQU 8000 destination address NUMBYTE EQU 64 number of bytes to transfer kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialize DMA Channel 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE DMACH1 A0 Pointer to channel 1 Initialize DMA channel 1 MCR Normal Operation ignore FREEZE dual address mode ISM field at 3 Make sure CPU32 SR 12 10 bits are less than or equal to ISM bits for channel startup Supervisor user reg unrestricted MAID field at 3 IARB priority at 4 MOVE W 0334 A0 Clear channel control reg Clear STR start bit to prevent the channel from starting a transfer early CLR W DMACCR1 A0 Initialize interrupt reg Interrupt priority at 7 interrupt vector at 42 6 42 MC68340 USER S MANUAL MOTOROLA MOVE W 0742 0 1 0 nitialize channel status Clear the DONE BES BED CONF and BRKP bits to allow channel to startup MOVE B 7C DMACSR1 A0 Initialize function code reg DMA space supervisor data space for source and destination MOVE B DD DMAFCR1 A0 Initialize source operand address Source address is equal to 6000 MOVE L SARAD
329. estination MULS W 16 16 gt 32 MULS L ea DI 32x322 32 MULS L ea Dh DI 32 x 32 64 MULU Source x Destination Destination MULU W 16 x 16 gt 32 MULU L ea DI 32 x32 gt 32 MULU L ea Dh DI 32 32 64 NBCD 0 Destination10 X Destination NBCD ea 0 Destination Destination NEG NEGX 0 Destination X Destination NEGX ea No Ne Destination Destination NOT ea Source V Destination Destination OR lt ea Dn OR Dn ea Immediate Data V Destination Destination ORI data ea ORI to CCR Source V CCR CCR ORI data CCR ORI to SR If supervisor state ORI 2 data SR then Source V SR SR else TRAP Sp 4 SP ea 5059 RESET If supervisor state RESET then Assert RESET else TRAP ROL ROR Destination Rotated by count Destination ROd Rx Dy ROd 1 data Dy ea 5 18 MC68340 USER S MANUAL MOTOROLA Table 5 2 Instruction Set Summary Concluded ROXL ROXR estination Rotated with X by count Destination ROXd1 Rx Dy ROXd 1 data Dy ROXd ea TEPE SP 5 PC SP 4 d gt SP RTD 4 displacement RTE If supervisor state RTE the SP 2 SR SP 2 2 SP SP 2 PC SP 4 SP restore state and deallocate stack according to SP else TRAP RTR SP CCR SP 2 SP SP SP 4 gt SP RTR ATS GP 8 4 SP Destination 9 Source 10 X Destination SBCD Dx Dy SBCD Ax Ay If
330. ete and RMC is negated In the absence of DSACK BERR is an asynchronous input using the asynchronous setup time 47 Specification 447A for 16 78 MHz 9 3 3 V 0 3V will be 8 ns During interrupt acknowledge cycles up to two wait states may be inserted by the processor between states SO and S1 ON 11 10 MC68340 USER S MANUAL MOTOROLA CLKOUT 5171 5170 FC3 FCO A31 A0 RW DSACKO DSACK1 D15 D0 IFETCH ASYNCHRONOUS INPUTS BKPT 50 51 52 53 54 55 as a P MT 8 H 8 NOTE All timing is shown with respect to 0 8V and 2 0V levels Figure 11 2 Read Cycle Timing Diagram MC68340 USER S MANUAL 11 11 50 51 52 53 54 55 JO AA DSACKO DSACK1 D15 D0 BERR N HALT N BKPT X NOTE All timing is shown with respect to 0 8 V and 2 0 V levels Figure 11 3 Write Cycle Timing Diagram 11 12 MC68340 USER S MANUAL MOTOROLA 50 51 54 55 50 A31 A0 RW D15 D0 0600 Figure 11 4 Fast Termination Read Cycle Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 13 CLKOUT A31 A0 FC3 FCO 5171 5170 D15 D0 BKPT Figure 11 5 Fast Termination Write Cycle Timing Diagram 11 14 MC68340 USER S MANUAL MOTOROLA
331. ete in a normal manner without exception processing however the data is ignored 7 3 5 3 INTERRUPT ACKNOWLEDGE CYCLES The serial module is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration The vector number must be provided if interrupt servicing is necessary thus the interrupt vector register IVR must be initialized If the IVR is not initialized a spurious interrupt exception will be taken if interrupts are generated 7 4 REGISTER DESCRIPTION AND PROGRAMMING This section contains a detailed description of each register and its specific function as well as flowcharts of basic serial module programming 7 4 1 Register Description The operation of the serial module is controlled by writing control bytes into the appropriate registers A list of serial module registers and their associated addresses are shown in Figure 7 9 The mode status command and clock select registers are duplicated for each channel to provide independent operation and control MOTOROLA MC68340 USER S MANUAL 7 17 All serial module registers are only accessible as bytes The contents of the mode registers MR1 and MR2 clock select register CSR and the auxiliary control register ACR bit 7 should only be changed after the receiver transmitter is issued a software RESET command i e channel operation must be disabled Care should also be taken if the register contents a
332. etting the SWR and CPE bits in the CR and if TGATE is programmed to control the enabling and disabling of the counter TGE bit set in the CR then asserting TGATE When the timer is enabled the ON bit in the SR is set On the next falling edge of the counter clock the counter is loaded with the value stored in the PREL1 N With each successive falling edge of the counter clock the counter decrements The time between enabling the timer and the first timeout can range from N to N 1 periods When TGATE is used to enable the timer the enabling of the timer is asynchronous however if timing is carefully considered the time to the first timeout can be known For additional details on timing see Section 11 Electrical Characteristics TOUTx behaves as a square wave when the bits of the CR are programmed for toggle mode A timeout occurs every 1 periods allowing for the zero cycle resulting in a change of state on TOUTx see Figure 8 5 The SR OUT bit reflects the level of TOUTx If this mode is used to generate periodic interrupts TOUTx may be enabled if a square wave is also desired COUNTER CLOCK A 1 COUNTER 0 20403 2 1 10 3 2 10010 3 2 i od 1 ON N41 J 1 gt ENABLE TIMEOUT TIMEOUT TIMEOUT MODEx Bits in Control Register 001 Preload 1 Register N 3 OCx Bits in Control Register 01 Figure 8 5 Square Wave Generator Mode If TGATEz is negated
333. external access The module block is not accessed The address space bits are as follows AS8 mask DMA Space address space FC3 FCO 1xxx AS7 mask CPU Space address space FC3 FCO 0111 AS6 mask Supervisor Program address space FC3 FCO 0110 AS5 mask Supervisor Data address space FC3 FCO 0101 AS4 mask Reserved Motorola address space FC3 FCO 0100 AS3 mask Reserved User address space FC3 FCO 0011 AS2 mask User Program address space FC3 FCO 0010 AS1 mask User Data address space FC3 FCO 0001 AS0 mask Reserved Motorola address space FC3 FCO 0000 For each address space bit 1 Mask this address space from the internal module selection The bus cycle goes external 0 Decode for the internal module block V Valid Bit This bit indicates when the contents of the MBAR are valid The base address value is not used therefore all internal module registers are not accessible until the V bit is set 1 Contents are valid 0 Contents are not valid 4 20 MC68340 USER S MANUAL MOTOROLA An access to this register does not affect external space since the cycle is not run externally Example code for accessing the MBAR is as follows Register DO will contain the value of MBAR MBAR can be read using the following code MOVE L 7 00 load DO with the CPU space function code MOVEC L DO SFC load SFC to indicate CPU space LEA L 0003FF00 A0 load 0 with the address of MBAR MOV
334. fer will be the last one Figure 6 11 Dual Address Write Timing External Burst Destination Requesting VIOYOLOW TWANVIN S 4YASN 0768921 1 2 9 CPU CYCLE CPU CYCLE DMA READ DMA WRITE CPU CYCLE DMA READ 50 52 54 50 52 54 50 52 54 50 52 54 50 52 54 50 52 54 50 52 54 CLKOUT 1 22 Jr xe em Nee a DREQx DONEx INPUT 4h DACKx DONEx N OUTPUT NOTE 1 DREQx must be active for two consecutive clocks for a DMA request to be recognized 2 To cause another DMA transfer DREQx is asserted after DACKx is asserted and before DACKx is negated 3 DACKx and DONEx DMA control signals are asserted in the destination write DMA cycle 4 DONEx Input can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one Figure 6 12 Dual Address Write Timing Cycle Steal Destination Requesting 6 5 BUS ARBITRATION The DMA controller module uses the M68000 bus arbitration protocol to request bus mastership for DMA transfers Each channel arbitrates for the bus independently The source read DMA bus cycle has timing identical to a read bus cycle The destination write DMA bus cycle has timing identical to a write bus cycle However the DMA channel transfers are unique in one respect FC3 can be asserted during the sou
335. filled The third number is the number of write accesses performed by the instruction As an example consider an ADD L 12 A3 D7 W 4 D2 instruction Paragraph 5 7 3 5 Arithmetic Logic Instructions shows that the instruction has a head 0 a tail 0 and cycles 2 0 1 0 However in indexed address register indirect addressing mode additional time is required to fetch the EA Paragraph 5 7 3 1 Fetch Effective Address gives addressing mode data For dg An Xn Sz Scale head 4 tail 2 cycles 8 2 1 0 Because this example is for a long access and the fetch EA table lists data for word accesses add two clocks to the tail and to the number of cycles in table notation to obtain head 4 tail 4 cycles 10 2 1 0 Assuming that no trailing write exists from the previous instruction EA calculation requires six clocks Replacement fetch for the EA occurs during these six clocks leaving a head of MOTOROLA MC68340 USER S MANUAL 5 97 four If there is no time in the head to perform a prefetch due to a previous trailing write then additional time to perform the prefetches must be allotted in the middle of the instruction or after the tail 8 2 10 TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES NUMBER OF WRITE CYCLES The total number of clocks for bus activity is as follows 2 Reads x 2 Clocks Read 1 Instruction Access x 2 Clocks Access 0
336. ft and rotate operations can be performed on either registers or memory Register shift and rotate operations shift all operand sizes The shift count may be specified in the instruction operation word to shift from 1 to 8 places or in a register modulo 64 shift count Memory shift and rotate operations shift word length operands one bit position only The SWAP instruction exchanges the 16 bit halves of a register Performance of shift rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping Table 5 7 is a summary of the shift and rotate operations 5 24 MC68340 USER S MANUAL MOTOROLA Table 5 7 Shift and Rotate Operations Operand Syntax Operand Size Operation ASL Dn Dn 8 16 32 data Dn 8 16 32 XIC lt 0 ea 16 ASR Dn Dn 8 16 Dn 816 1 L LSL Dn Dn data Dn XIC lt 0 ea gt Lac Ic Dn Dn ea Dn Dn data Dn c c hH lt ea gt D lt lt lt x lt Dn Dn 8 16 3 data Dn 8 16 3 gt gt ea 5 3 3 6 BIT MANIPULATION INSTRUCTIONS Bit manipulation operations are accomplished using the following instructions bit test BTST bit test and set BSET bit test and clear BCLR and bit test and change BCHG All bit manipulation operations can be performed on either registers
337. fy the CPU32 that an interrupt has occurred The interrupts are described in 8 4 Register Description Bits in the SR indicate all currently active interrupt conditions The interrupt enable IE bits in the control register CR are programmable to mask any events that may cause an interrupt 8 2 TIMER MODULES SIGNAL DEFINITIONS This section contains a brief description of the timer module signals see Figure 8 3 NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a signal is inactive or false 8 4 MC68340 USER S MANUAL MOTOROLA TIMER 1 PRESCALER EXTERNAL INTERFACE SIGNALS COUNTER OUTPUT CONTROL INTERRUPT CONTROL TIMER 2 PRESCALER EXTERNAL INTERFACE SIGNALS INTERRUPT Cpu Figure 8 3 External and Internal Interface Signals 8 2 1 Timer Input TIN1 TIN2 This input can be programmed to be the clock that causes events to occur in the counter and prescaler TINx is internally synchronized to the system clock to guarantee that a valid TINx level is recognized Additionally the high and low levels of TINx must each be stable MOTOROLA MC68340 USER S MANUAL 8 5 for at least one system clock period plus the sum of the setup and h
338. g o o Em o ses EM MU EM EE EE Lar MCN MOTOROLA MC68340 USER S MANUAL 7 39 7 4 2 Programming The basic interface software flowchart required for operation of the serial module is shown in Figure 7 10 The routines are divided into three categories e Serial Module Initialization O Driver Interrupt Handling 7 4 2 1 SERIAL MODULE INITIALIZATION The serial module initialization routines consist of SINIT and CHCHK SINIT is called at system initialization time to check channel A and channel B operation Before SINIT is called the calling routine allocates two words on the system stack Upon return to the calling routine SINIT passes information on the system stack to reflect the status of the channels If SINIT finds no errors in either channel A or channel B the respective receivers and transmitters are enabled The CHCHK routine performs the actual channel checks as called from the SINIT routine When called SINIT places the specified channel in the local loopback mode and checks for the following errors Transmitter Never Ready Receiver Never Ready Parity Error Incorrect Character Received 7 4 2 2 I O DRIVER EXAMPLE The I O driver routines consist of INCH OUTCH and POUTCH INCH is the terminal input character routine and gets a character from the channel A receiver and places it in the lower byte of register DO OUTCH is used to send the character in the lower byte of register DO to th
339. gh software A Setup for Rerun Read the MOVEM opcode and extension from locations pointed to by stackframe PC and PC 2 The EA need not be recalculated since the next operand address is saved in the stack frame However the opcode EA field must be examined to determine how to update the address register and PC when the instruction is complete Adjust the mask to account for operands already transferred Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred Scan the mask using this count value Each time a set bit is found clear it and decrement the counter When the count is zero the mask is ready for use Adjust the operand address If the predecrement addressing mode is in effect subtract the operand size from the stacked value otherwise add the operand size to the stacked value B Rerun Instruction Scan the mask for set bits Read write the selected register from to the operand address as each bit is found As each operand is transferred clear the mask bit and increment decrement the operand address When all bits in the mask are cleared all operands have been transferred If the addressing mode is predecrement or postincrement update the register to complete the execution of the instruction If TR is set in the stacked SSW create a six word stack frame and execute the trace handler If either B1 or BO is set in the SSW create another six word stack frame and execute the har
340. hanged and the interleaving of instruction prefetches with operands within each sequence is identical 5 7 1 6 INSTRUCTION EXECUTION TIME CALCULATION The overall execution time for an instruction depends on the amount of overlap with previous and subsequent instructions To calculate an instruction time estimate the entire code sequence must be 5 92 MC68340 USER S MANUAL MOTOROLA analyzed To derive the actual instruction execution times for an instruction sequence the instruction times listed in the tables must be adjusted to account for overlap The formula for this calculation is as follows C min T4 H2 C2 min T2 Ca min where Cn is the number of cycles listed for instruction Ty is the tail time for instruction is the head time for instruction min TN Hy is the minimum of parameters TN and HM The number of cycles for the instruction CN can include one or two EA calculations in addition to the raw number in the cycles column In these cases calculate overall instruction time as if it were for multiple instructions using the following equation CEA min Hop where CEA is the instruction s EA time Cop is the instruction s operation time Tea is the EA s tail time Hop is the instruction operation s head time min TN Hy is the minimum of parameters TN and The overall head for the instruction is the head for the EA and the overall t
341. hannel 1 for internal request generation memory to memory transfers kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SIM40 equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MODBASE EQU FFFFF000 SIM40 MBAR address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DMA Channel 1 equates DMACH 1 EQU 780 Offset from MBAR for channel 1 regs DMAMCR1 EQU 0 MCR for channel 1 Channel 1 register offsets from channel 1 base address DMAINT1 EQU 4 interrupt register channel 1 DMACCR1 EQU 8 control register channel 1 DMACSR1 EQU A status register channel 1 DMAFCR1 EQU B function code register channel 1 DMASAR1 EQU C source address register channel 1 DMADAR1 EQU 10 destination address register channel 1 DMABTC1 EQU 14 byte transfer count register channel 1 SARADD EQU 6000 source address DARADD 8000 destination address NUMBYTE EQU E number of bytes to transfer kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialize DMA Channel 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE DMACH1 A0 Pointer to channel 1 Initialize DMA channel 1
342. hannel from starting a transfer early CLR W DMACCR1 A0 Initialize interrupt reg Interrupt priority at 7 interrupt vector at 42 MOVE W _ 0742 DMAINT1 A0 Initialize channel status reg Clear the DONE BES BED CONF and BRKP bits to allow channel to startup MOVE B 7C DMACSR1 A0 Initialize function code reg DMA space user data space for source MOVE B 99 DMAFCR1 A0 Initialize source operand address Source address is equal to 10000 MOVE L SARADD DMASAR1 A0 Initialize the byte transfer count reg The number of bytes to be transferred is C or 3 long words MOVE L NUMBYTE DMABTC 1 A0 Channel control reg init and Start DMA transfers MOTOROLA MC68340 USER S MANUAL 6 39 No interrupts are enabled source read cycle Increment source address source size is long word REQ is external burst request Single address mode start the DMA transfers MOVE W 1823 DMACCR 1 0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Example 2 Internal Request Generation Memory to Memory Transfers kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MC68340 basic DMA channel register initialization example code This code is used to initialize the 68340 s internal DMA channel registers providing basic functions for operation The code sets up c
343. he MC68340 does not issue a BG signal in response to a BR signal during this operation Figure 3 9 is an example of a functional timing diagram of a read modify write instruction specified in terms of clock periods CLK OUT DSACKx READ lt WRITE gt m INDIVISIBLE gt CYCLE Figure 3 9 Read Modify Write Cycle Timing MOTOROLA MC68340 USER S MANUAL 3 19 State 0 The 68340 asserts SO to identify read modify write cycle The MC68340 places a valid address on A31 A0 and valid function codes on FC3 FCO The function codes select the address space for the operation SIZ1 SIZO become valid in SO to indicate the operand size The MC68340 drives R W high for the read cycle State 1 One half clock later during S1 the MC68340 asserts AS indicating a valid address on the address bus The MC68340 also asserts DS during S1 State 2 The selected device uses R W SIZ1 SIZO 0 and DS to place information on the data bus Either or both of the bytes D15 D8 and 07 00 are selected by SIZ1 SIZO and AO Concurrently the selected device may assert DSACK State 3 As long as at least one of the DSACK signals is recognized by the end of S2 meeting the asynchronous input setup time requirement data is latched on the next falling edge of the clock and the cycle terminates If DSACK is not recognized by the start of S3 the MC68
344. he SIM40 registers as either supervisor data space or user unrestricted data space 1 The 51 40 registers defined as supervisor user are restricted to supervisor data access FC3 FCO 5 An attempted user space write is ignored and returns BERR 0 The SIMAO registers defined as supervisor user data are unrestricted FC2 is a don t care IARBS IARBO Interrupt Arbitration Bits 3 0 These bits are used to arbitrate for the bus in the case that two or more modules simultaneously generate an interrupt at the same priority level No two modules can share the same IARB value The reset value of IARB is F allowing the SIM40 to arbitrate during an IACK cycle immediately after reset The system software should initialize the IARB field to a value from F highest priority to 1 lowest priority 4 22 MC68340 USER S MANUAL MOTOROLA value of 0 prevents arbitration and causes all SIM40 interrupts including external interrupts to be discarded as extraneous 4 3 2 2 AUTOVECTOR REGISTER AVR The AVR contains bits that correspond to external interrupt levels that require an autovector response Setting a bit allows the SIM40 to assert an internal AVEC during the IACK cycle in response to the specified interrupt request level This register can be read and written at any time AVR 006 7 6 5 4 3 2 1 0 os T To T T RESET 0 0 0 0 0 0 0 0 Supervisor Only NOTE The IARB field in the MCR must contain
345. he external clock input mode with the PLL MODCK reset value 0 V the external clock input duty cycle can be at minimum 2096 to produce a CLKOUT with a 5096 duty cycle For crystal mode operation the minimum CLKOUT pulse width is based on a 47 duty cycle For external clock mode operation the minimum CLKOUT pulse width is based on a 45 duty cycle with a 5096 duty cycle input clock MC68340 USER S MANUAL MOTOROLA 10 For external clock w PLL mode operation the minimum CLKOUT pulse width is based on a 50 duty cycle For external clock mode there is a 10 40 ns skew between the input clock signal and the output CLKOUT signal from the MC68340 Clock skew is measured from the rising edges of the clock signals 12 For external clock mode w PLL there is a 5 ns skew between the input clock signal and the output CLKOUT signal from the MC68340 Clock skew is measured from the rising edges of the clock signals MOTOROLA MC68340 USER S MANUAL 11 7 11 7 TIMING SPECIFICATIONS See notes a b c and d corresponding to part operation GND 0 Vdc TA 0 to 70 see numbered notes see Figures 11 2 11 11 3 3 V or 3 3V 5 0V 5 0V Characteristic Symbol Min Max Min Min e SZ i E 7 CLKOUT High to Address Data FC SIZ RMC tCHAZx 120 40 ns High Impedance CLKOUT High to Address FC SIZ RMC tCHAZn Invalid CLKOUT Low to AS DS CS IFETCH IPIPE ters 3 IACK Asserted
346. he interrupt status register ISR is read by the CPU32 to determine all MOTOROLA MC68340 USER S MANUAL 7 3 currently active interrupt conditions The interrupt enable register IER is programmable to mask any events that can cause an interrupt 7 1 5 Comparison of Serial Module to MC68681 The serial module is code compatible with the MC68681 with some modifications The following paragraphs describe the differences The programming model is slightly altered The supervisor user block in the MC68340 closely follows the MC68681 The supervisor only block has the following changes The interrupt vector register is moved from supervisor user to supervisor only at a new address MR2A and MR2B are moved from a hidden address location to a location at the bottom of the programming model The timer counter is eliminated as well as all associated command and status registers Only certain output port pins are available There are no IP pins on the MC68340 RxRTS and TxRTS are more automated on the MC68340 The XTAL RDY bit the ISR should be polled until it is cleared to prevent an unstable frequency from being applied to the baud rate generator The following code is an example if XTAL_RDY 0 begin write CSR end else begin wait jump loop end 7 2 SERIAL MODULE SIGNAL DEFINITIONS The following paragraphs contain a brief description of the serial module signals Figure 7 2 shows both the external and internal signa
347. he operation word specifies instruction length and the operation to be performed The remaining words called extension words further specify the instruction and operands These words may be immediate operands extensions to the effective address mode specified in the operation word branch displacements bit number special register specifications trap operands or argument counts 15 0 OPERATION WORD ONE WORD SPECIFIES OPERATION AND MODES SPECIAL OPERAND SPECIFIERS IF ANY ONE OR TWO WORDS IMMEDIATE OPERAND OR SOURCE ADDRESS EXTENSION IF ANY ONE TO THREE WORDS DESTINATION EFFECTIVE ADDRESS EXTENSION IF ANY ONE TO THREE WORDS Figure 5 6 Instruction Word General Format 5 12 MC68340 USER S MANUAL MOTOROLA Besides the operation code which specifies the function to be performed an instruction defines the location of every operand for the function Instructions specify an operand location in one of three ways Register Specification A register field of the instruction contains the number of the register An effective address field of the instruction contains address mode information Effective Address Implicit Reference The definition of an instruction implies the use of specific registers The register field within an instruction specifies the register to be used Other fields within the instruction specify whether the register is an address or data register and how it is to be used
348. he processor memory map When initialization is complete there are no fixed assignments Since the VBR stores the vector table base address the table can be located anywhere in memory It can also be dynamically relocated for each task executed by an operating system Each vector is assigned an 8 bit number Vector numbers for some exceptions are obtained from an external device others are supplied by the processor The processor multiplies the vector number by 4 to calculate vector offset then adds the offset to the contents of the VBR The sum is the memory address of the vector 5 5 1 1 TYPES OF EXCEPTIONS An exception can be caused by internal or external events An internal exception can be generated by an instruction or by an error The TRAP TRAPcc TRAPV BKPT CHK CHK2 RTE and DIV instructions can cause exceptions during normal execution Illegal instructions instruction fetches from odd addresses word or long word operand accesses from odd addresses and privilege violations also cause internal exceptions Sources of external exception include interrupts breakpoints bus errors and reset requests Interrupts are peripheral device requests for processor action Breakpoints are used to support development equipment Bus error and reset are used for access control and processor restart 5 5 1 2 EXCEPTION PROCESSING SEQUENCE For all exceptions other than a reset exception exception processing occurs in the following sequence
349. he software watchdog requires special service sequence to be executed on a periodic basis If this periodic servicing action does not occur the software watchdog times out and issues a reset or a level 7 46 MC68340 USER S MANUAL MOTOROLA interrupt as programmed by the SWRI bit in the SYPCR The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register SWIV Figure 4 3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer register PITR and the SWT bits in the SYPCR See Table 4 7 for a list of watchdog timeout periods The software watchdog service sequence consists of the following steps 1 write 55 to the software service register SWSR and 2 write AA to the SWSR Both writes must occur in the order listed prior to the watchdog timeout but any number of instructions or accesses to the SWSR can be executed between the two writes SWP PTP FREEZE PIT INTERRUPT 9 PRESCALER 27 PRECLK CLOCK DISABLE LPSTOP Figure 4 3 Software Watchdog Block Diagram 4 2 2 6 PERIODIC INTERRUPT TIMER The periodic interrupt timer consists of an 8 bit modulus counter that is loaded with the value contained in the PITR see Figure 4 3 The modulus counter is clocked by a signal deriv
350. hen a bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception 0 Breakpoint not pending 1 Breakpoint pending BO indicates that a breakpoint exception was pending on channel 0 internal breakpoint source when the bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception 0 Breakpoint not pending 1 Breakpoint pending RR will be set if the faulted bus cycle was a released write A released write is one that is overlapped If the write is completed rerun in the exception handler the RR bit should be cleared before executing RTE The bus cycle will be rerun if the RR bit is set upon return from the exception handler 0 Faulted cycle was read RMW or unreleased write 1 Faulted cycle was a released write Faulted RMW bus cycles set the RM bit RM is ignored during unstacking 0 Faulted cycle was non RMW cycle 1 Faulted cycle was either the read or write of an RMW cycle Instruction prefetch faults are distinguished from operand both read and write faults by the IN bit If IN is cleared the error was on an operand cycle if IN is set the error was on an instruction prefetch IN is ignored during unstacking 0 Operand 1 Prefetch MOTOROLA MC68340 USER S MANUAL 5 53 Read and write bus cycles are distinguished by the RW bit Read bus cycles will set this bit and write bus cycles will clear it RW
351. his output is the additional connection to a crystal If a crystal is used a capacitor of approximately 5 pF should be connected from this signal to ground If an external TTL level clock is used on X1 the X2 output must be left open Refer to Section 10 Applications for an example of a clock driver circuit MOTOROLA MC68340 USER S MANUAL 7 5 7 2 3 External Input 5 This input can be used as the clock input for channel A and or channel B and is programmable in the clock select registers CSR When used as the receiver clock received data is sampled on the rising edge of the clock When used as the transmitter clock data is output on the falling edge of the clock If this input is not used it must be connected to Vcc or GND 7 2 4 Channel A Transmitter Serial Data Output TxDA This signal is the transmitter serial data output for channel A The output is held high mark condition when the transmitter is disabled idle or operating in the local loopback mode Data is shifted out on this signal on the falling edge of the clock source with the least significant bit transmitted first 7 2 5 Channel A Receiver Serial Data Input RxDA This signal is the receiver serial data input for channel A Data received on this signal is sampled on the rising edge of the clock source with the least significant bit received first 7 2 6 Channel B Transmitter Serial Data Output TxDB This signal is the transmitter serial data output for
352. hold time for memory systems R W and FC3 FCO also remain valid throughout S5 If more than one write cycle is required states 50 55 repeated for each write cycle The external device keeps DSACK asserted until it detects the negation of AS or DS whichever it detects first The device must remove its data and negate DSACK within approximately one clock period after sensing the negation of AS or DS 3 4 CPU SPACE CYCLES FCS FCO select user and supervisor program and data areas The area selected by FC3 FCO 7 is classified as the CPU space The breakpoint acknowledge LPSTOP broadcast module base address register access and interrupt acknowledge cycles described in the following paragraphs use CPU space The CPU space type which is encoded 19 16 during a CPU space operation indicates the function that the MC68340 is performing On the MC68340 four of the encodings are implemented as shown in Figure 3 10 All unused values are reserved by Motorola for additional CPU space types CPU SPACE CYCLES FUNCTION ADDRESS BUS 94 1 19 16 0 000000 0000000000 00000000 0 0 0 BREAKPOINT ACKNOWLEDGE rA 94 9 m 16 0 0000000000000111111111111111110 LOW POWER STOP BROADCAST m m w w a 1 1 0 00000000000000111111111100000000 MODULE BASE ADDRESS REGISTER ACCESS m m 94
353. hough only two bytes are moved on that bus cycle The address line AO also affects the operation of the data multiplexer During an operand transfer A31 A1 indicate the word base address of that portion of the operand to be accessed 0 indicates the byte offset from the base i e either odd or even byte Figure 3 2 lists the bytes required on the data bus for read cycles The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by 5121 5140 and 0 for the bus cycle 3 6 MC68340 USER S MANUAL MOTOROLA Case Transfer Case 5171 5170 0 DSACK1 DSACKO D15 D8 D7 a Byte to Byte 0 1 b Byte to Word Even c Byte to Word Odd d Word to Byte Aligned e Word to Word Aligned Long Word to Byte Aligned g9 Long Word to Word Aligned gt lt gt lt gt lt gt lt 0 1 0 0 0 0 0 0 1 1 0 0 NOTES 1 Operands in parentheses are ignored by the MC68340 during read cycles 2 A 3 byte to byte transfer does occur as the second byte transfer of a long word to byte port transfer Figure 3 2 MC68340 Interface to Various Port Sizes 3 2 2 Misaligned Operands In this architecture the basic operand size is 16 bits Operand misalignment refers to whether an operand is aligned on a word boundary or overlaps the word boundary determined by address line 0 When
354. hree state test data output that is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TEST DATA REGISTERS BOUNDARY SCAN REGISTER 133 BITS M TDI U X 55 DECODER 2 0 3 BIT INSTRUCTION REGISTER TMS TCK TAP CTLR Figure 9 1 Test Access Port Block Diagram 9 2 TAP CONTROLLER The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal It is a synchronous state machine that controls the operation of the JTAG logic The state machine is shown in Figure 9 2 the value shown adjacent to each arc represents the value of the TMS signal sampled on the rising edge of the TCK signal For a description of the TAP controller states please refer to the IEEE 1149 1 document 9 2 MC68340 USER S MANUAL MOTOROLA 0 1 1 0 SELECT DR SCAN 0 1 1 CAPTURE DR CAPTURE IR 0 1 NM 0 PAUSE DR 1 UPDATE IR 1 UP DATE DR 0 Figure 9 2 TAP Controller State Machine 9 3 BOUNDARY SCAN REGISTER The MC68340 IEEE 1149 1 implementation has a 132 bit boundary scan register This register contains bits for all device signal and clock pins and associated control signals The XTAL X2 and XFC pins are associated with analog signals and are not included in the boundary scan register All MC68340 bidirectional pins exc
355. i e the STP bit in the MCR is cleared MOTOROLA MC68340 USER S MANUAL 6 33 DAR1 DAR2 790 7BO 31 30 29 28 27 26 25 24 23 22 21 2 19 18 17 16 U Unaffected by reset Supervisor User During the DMA write cycle this register drives the address on the address bus This register can be programmed to increment CCR DAPI bit set or remain constant CCR DAPI bit cleared after each operand transfer The register is incremented using unsigned arithmetic and will roll over if overflow occurs For example if a register contains FFFFFFFF and is incremented by 1 it will roll over to 00000000 This register can be incremented by 1 2 or 4 depending on the size of the operand and the starting address If the operand size is byte the register is always incremented by 1 If the operand size is word and the starting address is even word aligned the register is incremented by 2 If the operand size is long word and the address is even word aligned the register is incremented by 4 The DAR value must be aligned to an even word boundary if the transfer size is word or long word otherwise the CSR CONF bit is set and the transfer does not occur When read this register always contains the next destination address If a bus error terminates the transfer this register contains the next destination address that would have been run had the error not occurred 6 7 8 Byte Transfer Counter Register BTC The is a 32 bit register tha
356. icate that although the first exception received a bus error while stacking the bus error exception stacking successfully completed This occurrence is extremely improbable but the CPU32 supports recovery from it Once the exception handler determines that the fault has been corrected recovery can proceed as described previously If the fault cannot be corrected move the supervisor stack to another area of memory copy all valid stack frames to the new stack create a faulted exception frame on top of the stack and resume execution at the exception handler address MOTOROLA MC68340 USER S MANUAL 5 59 5 5 4 CPU32 Stack Frames The CPUS2 generates three different stack frames four word frames six word frames and twelve word bus error frames 5 5 4 1 FOUR WORD STACK FRAME This stack frame is created by interrupt format error TRAP n illegal instruction A line and F line emulator trap and privilege violation exceptions Depending on the exception type the PC value is either the address of the next instruction to be executed or the address of the instruction that caused the exception see Figure 5 12 15 0 SP STATUS REGISTER 02 PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 06 0 0 0 0 VECTOR OFFSET Figure 5 12 Format 0 Four Word Stack Frame 5 5 4 2 SIX WORD STACK FRAME This stack frame see Figure 5 13 is created by instruction related traps which include CHK CHK2 TRAPcc TRAPV and div
357. ide by zero and by trace exceptions The faulted instruction PC value is the address of the instruction that caused the exception The next PC value the address to which RTE returns is the address of the next instruction to be executed 15 SP STATUS REGISTER 02 NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 06 ololt1 o VECTOR OFFSET 08 FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW Figure 5 13 Format 2 Six Word Stack Frame Hardware breakpoints also utilize this format The faulted instruction PC value is the address of the instruction executing when the breakpoint was sensed Usually this is the address of the instruction that caused the breakpoint but because released writes can overlap following instructions the faulted instruction PC may point to an instruction following the instruction that caused the breakpoint The address to which RTE returns is the address of the next instruction to be executed 5 5 4 3 BUS ERROR STACK FRAME This stack frame is created when a bus cycle fault is detected The CPU32 bus error stack frame differs significantly from the equivalent stack frames of other M68000 Family members The only internal machine state required in the CPU32 stack frame is the bus controller state at the time of the error and a single register 5 60 MC68340 USER S MANUAL MOTOROLA Bus operation in progress at the
358. ides Two Clock Cycle External Access Using MC68340 Chip Selects Provides Full DMA Handshake for Burst Transfers and Cycle Steal DMA INTERRUPT HANDSHAKE ARBITRATION SIGNALS y SLAVE BIU MASTER BIU A E DMA DMA CHANNEL 2 HANDSHAKE ARBITRATION SIGNALS Figure 6 1 DMA Block Diagram MOTOROLA MC68340 USER S MANUAL 6 1 6 1 MODULE OVERVIEW The main purpose of the controller module is to transfer data at very high rates usually much faster than the CPU32 under software control can handle The term is used to refer to the ability of a peripheral device to access memory in a system in the same manner as a microprocessor does DMA operations can greatly increase overall system performance The MC68340 DMA module consists of two independent programmable channels The term DMA is used throughout this section to reference either channel 1 or channel 2 since the two are functionally equivalent Each channel has independent request acknowledge and done signals However both channels cannot own the bus at the same time Therefore it is impossible to implicitly address both DMA channels at the same time The MC68340 on chip peripherals do not support the single address transfer mode DMA requests may be internally generated by the channel or externally generated by a device For an internal request the amount of bus bandwidth allocated for the DMA can
359. ignals are used for test or software debugging See Section 5 CPU32 for more information on these signals and background debug mode 2 11 1 Instruction Fetch IFETCH This pin functions as IFETCH in normal operation and as DSI in background debug mode IFETCH This active low output signal indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed DSI This development serial input signal helps to provide serial communications for background debug mode 2 11 2 Instruction Pipe IPIPE This pin functions as IPIPE in normal operation and as DSO in background debug mode MOTOROLA MC68340 USER S MANUAL 2 9 This active low output signal is used to track movement of words through the instruction pipeline DSO This development serial output signal helps to provide serial communications for background debug mode 2 11 3 Breakpoint BKPT This pin functions as BKPT in normal operation and as DSCLK in background debug mode BKPT This active low input signal is used to signal a hardware breakpoint to the CPU32 DSCLK This development serial clock input helps to provide serial communications for background debug mode 2 11 4 Freeze FREEZE Assertion of this active high output signal indicates that the CPU32 has acknowledged a breakpoint and has initiated background mode operation 2 12 DMA MODULE SIGNALS The following signals are used by the di
360. ignificant byte of a word result Word results return 16 bits of significant data long word results return 32 bits Status of the read operation is returned as in the READ command 0xxxx for success 10001 for bus or address errors 5 6 2 8 11 Fill Memory Block FILL FILL is used in conjunction with the WRITE command to fill large blocks of memory An initial WRITE is executed to set up the starting address of the block and to supply the first operand Subsequent operands are written with the FILL command The initial address is incremented by the operand size 1 2 or 4 and is saved in a temporary register Subsequent FILL commands use this address increment it by the current operand size and store the updated address back in the temporary register NOTE The FILL command does not check for a valid address in the temporary register FILL is a valid command only when preceded by another FILL or by a WRITE command Otherwise the results are undefined The NOP command can be used for intercommand padding without corrupting the address pointer The size field is examined each time a FILL command is given allowing the operand size to be altered dynamically Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMOBNGNONSUEEUNRUN 5 82 MC68340 USER S MANUAL MOTOROLA Command Sequence WRITE FILL B W MS DATA LS DATA MEMORY C XXX 22 READY READY LOCATION NOT
361. imum limits as appropriate and are measured as shown Inputs are specified with minimum setup and hold times and are measured as shown Finally the measurement for signal to signal specifications are shown Note that the testing levels used to verify conformance to the AC specifications do not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics 11 2 MC68340 USER S MANUAL MOTOROLA MC68340V low voltage parts can operate up to 8 39 MHz or 16 78 MHz with a 3 3 V 50 3 V supply Separate part numbers are used to distinguish the operation of the parts according to the supply voltage Refer to Section 12 Ordering Information and Mechanical Data for the part numbering schemes MC68340 is used throughout this section to refer to the 16 78 or 25 16 MHz parts at 5 0 V 5 MC68340V is used throughout this section to refer to the 8 39 or 16 78 MHz parts at 3 3 V 0 3 V NOTE The electrical specifications in this section for the MC68340 25 16 MHz at 5 0 V 5 and the 3 3 V 0 3 V specifications for both the 8 39 and 16 78 MHz parts are preliminary MOTOROLA MC68340 USER S MANUAL 11 3 CLKOUT OUTPUTS 1 OUTPUTS 2 vaup 20 20V VALID OUTPUT n nd m ogy OUTPUT INPUTS 3 INPUTS 4 ALL SIGNALS 5 NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This output timing is applicable to
362. in Figure 4 7 Selection of a pin function is accomplished by a combination of the port B pin assignment register PPARB and the FIRQ bit of the MCR See Table 4 5 for port B combinations By changing the value of the FIRQ bit and the corresponding bits in the PPARB for a particular signal the port B pins can be configured for different pin functions Upon reset port B is configured as MODCK IRQ7 IRQ6 IRQ5 IRQ3 and CS3 CSO0 MODCK PORT BO IRQ7 PORT B7 IRQ6 PORT B6 INTERRUPT IRQ5 PORT B5 PORT IRQ3 PORT B3 LOGIC RQ4 P ORT IRQ2 P ORT B2 YYY YY FULL IRQ MUX 4 oA i IRQ1 PORT AVEC YYYY CHIP S2 SELECT S1 MODULE Figure 4 7 Full Interrupt Request Multiplexer Table 4 5 Port B Pin Assignment Register Pin Function FIRQ 0 FIRQ 0 FIRQ 1 FIRQ 1 mm PPARB 1 PPARB 0 PPARB 1 NOTE MODCK has no function after reset 4 16 MC68340 USER S MANUAL MOTOROLA The number of wait states programmed into the internal wait state generation logic by a chip select can be used even though the is not used as CS signal The programmed number of wait states in the CS signal applies to the port B pins configured as IRQ or I O pins This is done by programming the chip select with the number of wait states to be added as though it were to be used The DD1 DDO and PS1 PSO bits in the chip select address mask register must be set to add the desired nu
363. indicates the number of clock periods needed for the processor to calculate the destination EA and to perform a MOVE or MOVEA instruction For entries with CEA or FEA refer to the appropriate table to calculate that portion of the instruction time Destination EAs are divided by their formats see 5 3 4 4 Effective Address Encoding Summary The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes When using this table begin at the top and move downward Use the first entry that matches both source and destination addressing modes MOVE Rn Am MOVE Rn Am MOVE Rn Am MOVE FEA MOVE FEA An MOVE MOVE 6 0 1 x MOVE FEA 6 0 1 x X There is one bus cycle for byte and word operands and two bus cycles for long word operands For long word bus cycles add two clocks to the tail and to the number of cycles An fetch EA time must be added for this instruction FEA CEA OPER NOTE For instructions not explicitly listed use the MOVE CEA FEA entry The source EA is calculated by the calculate EA table and the destination EA is calculated by the fetch EA table even though the bus cycle is for the source EA 5 7 3 4 SPECIAL PURPOSE MOVE INSTRUCTION The special purpose MOVE instruction table indicates the number of
364. ing Cycle Steal Source Requesting DMA WRITE 52 54 the FCR and the size in the When the complete operand is written the DAR is incremented by 0 1 2 or 4 according to the increment and size information specified by the DAPI and DSIZE bits of the CCR and the byte transfer count register BTC is decremented by the number of bytes transferred If the BTC is equal to zero and there were no errors the CSR DONE bit is set and the DONE signal for the DMA handshake is asserted The DMA control signals DACK and DONE are asserted in the destination write cycle when the destination device makes a request See Figures 6 11 and 6 12 for timing diagrams of dual address write for external burst and cycle steal modes MOTOROLA MC68340 USER S MANUAL 6 15 91 9 TWANVIN S H3Sf 0v 89DIN VIOYOLOW 50 CPU CYCLE DMA READ DMA READ DMA WRITE CPU CYCLE S2 54 SO S2 S4 50 52 54 50 52 54 50 52 54 50 52 54 CLKOUT 1 DREQx DONEx INPUT NOTE 1 Timing to generate more than one DMA transfer 2 DACKx and DONEx DMA control signals are asserted in the destination write DMA cycle 3 DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized 4 DONEx input can be asserted in either the read or write DMA bus cycle to indicate that the next DMA trans
365. ing follows the regular sequence tracing is disabled so that the trace exception itself is not traced A vector number is generated to reference the trace exception vector The address of the instruction that caused the trace exception the trace exception vector offset the current PC and a copy of the SR are saved on the supervisor stack The saved value of the PC is the address of the next instruction to be executed A trace exception can be viewed as an extension to the function of any instruction If a trace exception is generated by an instruction the execution of that instruction is not complete until the trace exception processing associated with it is also complete If an instruction is aborted by a bus error or address error exception trace exception processing is deferred until the suspended instruction is restarted and completed normally An RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault MOTOROLA MC68340 USER S MANUAL 5 49 If an instruction is executed and an interrupt is pending on completion the trace exception is processed before the interrupt exception If an instruction forces an exception the forced exception is processed before the trace exception If an instruction is executed and a breakpoint is pending upon completion of the instruction the trace exception is processed before the breakpoint If an attempt is made to execute an illeg
366. ing total execution time Cr Control registers USP VBR SFC and DFC n Number of registers to transfer RL Register List lt Maximum time certain data or mode combinations may execute faster NOTE The MOVES instruction has an additional save step which other instructions do not have To calculate the total instruction time calculate the save the EA and the operation execution times and combine in the order listed using the equations given in 5 7 1 6 Instruction Execution Time Calculation 5 7 3 5 ARITHMETIC LOGIC INSTRUCTIONS The arithmetic logic instruction table indicates the number of clock periods needed to perform the specified arithmetic logical instruction using the specified addressing mode Footnotes indicate when to account for the appropriate EA times The total number of clock cycles is outside the parentheses 5 102 MC68340 USER S MANUAL MOTOROLA The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Rn Rm FEA Rn Dn FEA Dn Dm FEA Dn Dn FEA Dn Dm Dn FEA Dn Dm FEA Dn Dn FEA mm SUB A E 0 o 299 ua dm jJ CMP2 Op o o m FEA Rn veo s MUL su L Save FEA Dn 3 0 1 0 MUL su L Op FEA 01 In mE ae MUL su L
367. initiates a bus cycle by driving the 1 0 SIZx and R W outputs At the beginning of a bus cycle SIZ1 and SIZO are driven with FC3 FCO SIZ1 and SIZO indicate the number of bytes remaining to be transferred during an operand cycle consisting of one or more bus cycles Table 3 1 lists the encoding of the SIZx signal These signals are valid while AS is asserted The R W signal determines the direction of the transfer during a bus cycle Driven at the beginning of a bus cycle R W is valid while AS is asserted R W only transitions when a write cycle is preceded by a read cycle or vice versa The signal may remain low for consecutive write cycles The RMC signal is asserted at the beginning of the first bus cycle of a read modify write operation and remains asserted until completion of the final bus cycle of the operation 32 MC68340 USER S MANUAL MOTOROLA Table 3 1 SIZx Signal Encoding meterse foe NE eee t3 Three Bytes o 3 1 2 Function Code Signals FCS3 FCO are outputs that indicate one of 16 address spaces to which the address applies Fifteen of these spaces are designated as either user or supervisor program or data and normal or direct memory access DMA spaces One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles FC3 FCO are valid while AS is asser
368. instruction executes concurrently with the previous instruction As shown in Figure 5 31 portions of instructions A and B execute simultaneously reducing total execution time Because portions of instructions B and C also overlap overall execution time for all three instructions is also reduced Each instruction contributes to the total overlap time The portion of execution time at the end of instruction A that can overlap the beginning of instruction B is called the tail of instruction A The portion of execution time at the beginning of instruction B that can overlap the end of instruction A is called the head of instruction B The total overlap time between instructions A and B is the smaller tail of A and the head of B ns ruction a instruction _ INSTRUCTION OVERLAP OVERLAP Figure 5 31 Simultaneous Instruction Execution MOTOROLA MC68340 USER S MANUAL 591 The execution time attributed to instructions A B and C after considering the overlap is illustrated in Figure 5 32 The overlap time is attributed to the execution time of the completing instruction The following equation shows the method for calculating the overlap time Overlap min Headw 4 INSTRUCTION A INSTRUCTION B L instruction OVERLAP OVERLAP PERIOD PERIOD ABSORBED BY ABSORBED BY INSTRUCTION A INSTRUCTION B Figure 5 32 Attributed Instruction Times
369. ion BKPT Instruction Opcode Substitution Opcode Substitution Illegal Instruction Illegal Instruction 5 6 2 2 1 External BKPT Signal Once enabled BDM is initiated whenever assertion of is acknowledged If BDM is disabled a breakpoint exception vector 0C is acknowledged The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data There is no breakpoint acknowledge bus cycle when BDM is entered 5 6 2 2 2 BGND Instruction An illegal instruction 4AFA is reserved for use by development tools The CPU32 defines 4AFA BGND to be a BDM entry point when BDM is enabled If BDM is disabled an illegal instruction trap is acknowledged Illegal instruction traps are discussed in 5 5 2 8 Illegal or Unimplemented Instructions 5 6 2 2 3 Double Bus Fault The CPU32 normally treats a double bus fault two bus faults in succession as a catastrophic system error and halts When this condition occurs during initial system debug a fault in the reset logic further debugging is impossible until the problem is corrected In BDM the fault can be temporarily bypassed so that its origin can be isolated and eliminated 5 6 2 3 ENTERING BDM When the processor detects a BKPT or a double bus fault or decodes a BGND instruction it suspends instruction execution and asserts the FREEZE output FREEZE assertion is the first indication that the processor has entered BDM Once FREEZE has been asserted the
370. ion using the new value in Dx yields Table Entry Offset Dx 8 15 0B 11 Interpolation Fraction Dx 0 7 DO 208 Thus Y is calculated as follows Y 80 208 64 80 256 67 5 3 4 4 TABLE EXAMPLE 4 MAINTAINING PRECISION In this example three TBL operations are performed and the results are summed The calculation is done once with the result of each TBL rounded before addition and once with only the final result rounded Assume that the result of the three interpolations are as follows a indicates the binary radix point TBL 1 0010 0000 0111 0000 TBL 2 0011 1111 0111 0000 TBL 3 0000 0001 0111 0000 5 34 MC68340 USER S MANUAL MOTOROLA First the results of each TBL are rounded with the TBLS round to nearest even algorithm The following values would be returned by TBLS TBL 1 0010 0000 TBL 2 0011 1111 TBL 3 0000 0001 Summing the following result is obtained 0010 0000 0011 1111 0000 0001 0110 0000 Now using the same TBL results the sum is first calculated and then rounded according to the same algorithm 0010 0000 0111 0000 0111 0000 0011 1111 0000 0001 0111 0000 0110 0001 0101 0000 Rounding yields 0110 0001 The second result is preferred The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results LO TBLSN B ea Dx TBLSN B ea D
371. irq7 ctl bit 52 is logic zero since the cell type is IO CtlO The active level for ab ctl bit 83 is logic one since the cell type is IO Ctl1 IO CtlO see Figure 9 6 differs from IO Ctl1 see Figure 9 5 by an inverter in the output enable path The fourth column lists the pin type TS Output indicates a three state output pin I O indicates a bidirectional pin and OD I O denotes an open drain bidirectional pin An open drain output pin has two states off high impedance and logic zero The last column indicates the associated boundary scan register control bit for bidirectional three state and open drain output pins Bidirectional pins include a single scan bit for data IO Cell as depicted in Figure 9 7 These bits are controlled by one of the two bits shown in Figures 9 5 and 9 6 The value of the control bit determines whether the bidirectional pin is an input or an output One or more bidirectional data bits can be serially connected to a control bit as shown in Figure 9 8 Note that when sampling the bidirectional data bits the bit data can be interpreted only after examining the control bit to determine pin direction 9 4 MC68340 USER S MANUAL MOTOROLA Table 9 2 Boundary Scan Bit Definitions Eg amp e m SS Cell Type Name Type CTL Cell Cell Type Name Type CTL Cell lOCel vor 35 A Fer wm w 95 Olan Oups oram mr
372. isabled the characters in the FIFO can still be read by the CPU32 If the receiver is reset the FIFO stack and all receiver status bits corresponding output ports and interrupt request are reset No additional characters are received until the receiver is re enabled MOTOROLA MC68340 USER S MANUAL 7 13 7 3 3 Looping Modes Each serial module channel can be configured to operate in various looping modes as shown in Figure 7 7 These modes are useful for local and remote system diagnostic functions The modes are described in the following paragraphs with further information available in 7 4 Register Description and Programming The channel s transmitter and receiver should both be disabled when switching between modes The selected mode is activated immediately upon mode selection regardless of whether a character is being received or transmitted 7 3 3 1 AUTOMATIC ECHO MODE In this mode the channel automatically retransmits the received data on a bit by bit basis The local CPU32 to receiver communication continues normally but the CPUS2 to transmitter link is disabled While in this mode received data is clocked on the receiver clock and retransmitted on TxDx The receiver must be enabled but the transmitter need not be enabled Since the transmitter is not active the SR and TxRDY bits are inactive and data is transmitted as it is received Received parity is checked but not recalculated for transmission Character frami
373. ister After the V bit is set for 50 global chip select can only be restarted with system reset After the SSP and the PC are fetched the module base address register MBAR should be initialized and the MBAR V bit should be set CPU space address 0003 00 with the desired base address for the internal modules 4 4 2 SIM40 Module Configuration The order of the following SIM40 register initializations is not important however time can be saved by initializing the SYNCR first to quickly increase to the desired processor operating frequency The module base address register must be initialized prior to any of following steps Clock Synthesizer Control Register SYNCR Set frequency control bits W X Y to specify frequency Select action taken during loss of crystal RSTEN bit activate a system reset or operate in limp mode Select system clock and CLKOUT during LPSTOP STSIM and STEXT bits Module Configuration Register MCR If using the software watchdog periodic interrupt timer and or the bus monitor select action taken when FREEZE is asserted FRZx bits Select port B configuration FIRQ bit Note that this bit is used in combination with the bits in the PPARB to program the function of the port B pins Select the access privilege for the supervisor user registers SUPV bit Select the interrupt arbitration level for the SIM40 IARBx bits Autovector Register AVR Select the desired external int
374. ister specifies the size of the address block range The base address register V bit indicates that the register information for that chip select is valid A global chip select CSO allows address decode for a boot ROM before System initialization occurs Variable Block Sizes The block size starting from the specified base address can vary in size from 256 bytes up to 4 Gbytes in 2 increments The specified base address must be on a multiple of the the block size The block size is specified in the address mask register Both 8 and 16 Bit Ports Supported The 8 bit ports are accessible on both odd and even addresses when connected to data bus bits 15 8 the 16 bit ports can be accessed as odd bytes even bytes or even words The port size is specified by the PS bits in the address mask register Write Protect Capability The WP bit in each base address register can restrict write access to its range of addresses Fast Termination Option Programming the FTE bit in the base address register for the fast termination option causes the chip select to terminate the cycle by asserting the internal DSACK early providing a two cycle external access Internal DSACK Generation for External Accesses with Programmable Wait States DSACK can be generated internally with up to three wait states for a particular device using the DD bits in the address mask register Full 32 Bit Address Decode with Address Space Checking The FC bits in
375. iting a zero to this address MOTOROLA MC68340 USER S MANUAL 7 37 7 4 1 17 MODE REGISTER 2 MR2 MR2 controls some of the serial module configuration This register can be read or written at any time the serial module is enabled i e the STP bit in the MCR is cleared MR2A MR2B 720 721 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 Read Write Supervisor User CM1 CMO0 Channel Mode These bits select a channel mode as listed in Table 7 9 See 7 3 3 Looping Modes for more information on the individual modes Table 7 9 CMx Control Bits To Ata CN ee TxRTS Transmitter Ready to Send This bit controls the negation of the RTSA or RTSB signals The output is normally asserted by setting OPO or OP1 and negated by clearing OPO or OP1 see 7 4 1 15 Output Port Control Register OPCR 1 In applications where the transmitter is disabled after transmission is complete setting this bit causes the particular OP bit to be cleared automatically one bit time after the characters if any in the channel transmit shift register and the transmitter holding register are completely transmitted including the programmed number of stop bits This feature is used to automatically terminate transmission of a message If both the receiver and the transmitter in the same channel are programmed for RTS control RTS control is disabled for both since this is an incorrect configuration 0 Clearing this bit has
376. ity at 8 MOVE W _ 00C8 A0 Clear channel control reg Clear STR start bit to prevent the channel from starting a transfer early CLR W DMACCR1 A0 Initialize interrupt reg Interrupt priority at 7 interrupt vector at 42 MOVE W 4 0742 DMAINT1 0 Initialize channel status reg Clear the DONE BES BED CONF and BRKP bits to allow channel to startup MOVE B 7C DMACSR1 A0 Initialize function code reg DMA space supervisor data space for source and destination MOVE B DD DMAFCR1 A0 Initialize source operand address 6 44 MC68340 USER S MANUAL MOTOROLA Source address is equal to 6001 and odd address MOVE L SARADD DMASAR 1 A0 Initialize destination operand address Destination address is equal to 10000 and even address MOVE L DARADD DMADAR1 A0 Initialize the byte transfer count register The number of bytes to be transferred is 14 or 20 bytes MOVE L NUMBYTE DMABTC1 A0 Channel control reg init and Start DMA transfers No interrupts are enabled source read cycle Increment the source and destination addresses Source size is byte destination size is word REQ is external cycle steal dual address transfers start the DMA transfers MOVE W 10 1 0 1 0 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MOTOROLA MC68340 USER S MAN
377. kkkkkkkkkkkk Initialize Timer1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE TIMER1 A0 Pointer to timeri module Disable timer1 CLR W CR1 A0 Allow TGATE to negate and assert so that an accurate count will result If SR1 TGL bit 1 continue looping TGATE is negated LOOP1 BTST B 3 SR1 A0 BNE B LOOP 1 If TGL bit 0 continue looping TGATE is asserted LOOP2 BTST B 3 SR1 A0 BEQ B LOOP2 Ready to initialize timer1 TGATE is negated Module configuration register Timer1 module is set for normal operation ignore FREEZE Supervisor user timer1 registers unrestricted Interrupt arbitration at priority 03 MOVE W _ 0003 MCR1 A0 Initialize timer1 interrupt level to 2 and vector to 0F MOVE W 020F IR1 A0 nitialize the compare register to 0 CLR W A0 Clear the SR1 TG bit by writing a 1 to use as a flag MOVE B 20 SR1 A0 Control register 1 Enable timer1 no interrupts are enabled TGATE signal used to control the counter Use the selected clock for the counter clock and enable it Selected clock is 1 2 system s freq Pulse width measurement disable TOUT 8 30 MC68340 USER S MANUAL MOTOROLA MOVE W 4 8A10 CR1 AO If SR TG bit 0 continue looping TGATE is asserted else TG 1 indicating TGATE was negated When TG 1 counting is stopped LOOP3 BTST B 5 SR1 A0 BEQ B LOOP3 Counting is complete To det
378. kkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MODBASE EQU FFFFF000 SIM40 MBAR address value MOTOROLA MC68340 USER S MANUAL 6 43 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DMA Channel 1 equates DMACH 1 EQU 780 Offset from MBAR for channel 1 regs DMAMCR1 EQU 0 MCR for channel 1 Channel 1 register offsets from channel 1 base address DMAINT1 EQU 4 interrupt register channel 1 DMACCR1 EQU 8 control register channel 1 DMACSR1 EQU A status register channel 1 DMAFCR1 EQU B function code register channel 1 DMASAR1 EQU C source address register channel 1 DMADAR1 EQU 910 destination address register channel 1 DMABTC1 EQU 14 byte transfer count register channel 1 SARADD EQU 6001 source address is an ODD address DARADD EQU 10000 destination address is and EVEN address NUMBYTE EQU 14 number of bytes to transfer kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialize DMA Channel 1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE DMACH1 A0 Pointer to channel 1 Initialize DMA channel 1 MCR Normal Operation ignore FREEZE dual address mode ISM field at 0 Make CPU32 SR 12 10 bits are less than or equal to ISM bits for channel startup Supervisor user reg unrestricted MAID field at 4 IARB prior
379. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MC68340 basic timer module register initialization example code This code is used to initialize the 68340 s internal timer module registers providing basic functions for operation It sets up timer1 for pulse width measurement In this mode the number of clock cycles during a particular event are counted The event is defined by the assertion and negation of TGATE kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MODBASE EQU FFFFF000 SIM40 MBAR address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Timer1 module equates TIMER1 EQU 600 Offset from MBAR for timer1 module regs 1 EQU 0 MCR for timer1 MOTOROLA MC68340 USER S MANUAL 8 29 Timer1 register offsets from timer1 base address IR1 EQU 604 interrupt register timer1 CR1 EQU 606 control register timer SR1 EQU 608 status register timer1 1 EQU 60 counter register timer1 1 EQU 610 compare register timer1 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
380. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Example 3 Internal Request Generation Memory Block Initialization kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MC68340 basic DMA channel register initialization example code MOTOROLA MC68340 USER S MANUAL 6 41 This code is used to initialize the 68340 s internal channel registers providing basic functions for operation The code sets up channel 1 for internal request generation to perform a memory block initialization for 100 bytes kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SIM40 equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MODBASE EQU FFFFF000 SIM40 MBAR address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DMA Channel 1 equates DMACH 1 EQU 780 Offset from MBAR for channel 1 regs DMAMCR1 EQU 0 MCR for channel 1 Channel 1 register offsets from channel 1 base address DMAINT1 EQU 4 interrupt register channel 1 DMACCR1 EQU 8 control register channel 1 DMACSR1 EQU A status register channel 1 DMAFCR1 EQU B function code register channel 1 DMASAR1 EQU C source addr
381. kpoint is recognized and the channel is the bus master 0 Does not enable an IRQ when a breakpoint is recognized and the channel is the bus master INTN Interrupt Normal 1 Enables IRQ when the channel finishes a transfer without an error condition CSR DONE bit is set 0 Does not enable an IRQ when the channel finishes a transfer without an error condition INTE Interrupt Error 1 Enables an IRQ when the channel encounters an error on source read CSR BES bit is set destination write CSR BED bit is set or configuration for channel setup CSR CONF bit is set 0 Does not enable an IRQ when the channel encounters an error on source read destination write or configuration for channel setup ECO External Control Option If request generation is programmed to be internal REQ bits 00 this bit has no effect Single Address Mode This bit defines the direction of transfer 1 If request generation is programmed to be external REQ 1x the requesting device receives the data read from memory and the control signals DREQ DACK and DONE are used by the requesting device to write data during the source read portion of the transfer 0 If request generation is programmed to be external REQ 1x the requesting device provides the data write to memory and the control signals DREQ DACK and DONE are used by the requesting device to provide data during the destination write porti
382. l Full Duplex Automatic Echo Local Loopback Remote Loopback Automatic Wakeup Mode for Multidrop Applications Seven Maskable Interrupt Conditions Parity Framing and Overrun Error Detection False Start Bit Detection Line Break Detection and Generation Detection of Breaks Originating in the Middle of a Character Start End Break Interrupt Status On Chip Crystal Oscillator MC68340 USER S MANUAL MOTOROLA 7 1 1 Serial Communication Channels A and B Each communication channel provides a full duplex asynchronous synchronous receiver and transmitter using an operating frequency independently selected from a baud rate generator or an external clock input The transmitter accepts parallel data from the IMB converts it to a serial bit stream inserts the appropriate start stop and optional parity bits then outputs a composite serial data stream on the channel transmitter serial data output TxDx Refer to 7 3 2 1 Transmitter for additional information The receiver accepts serial data on the channel receiver serial data input RxDx converts it to parallel format checks for a start bit stop bit parity if any or break condition and transfers the assembled character onto the IMB during read operations Refer to 7 3 2 2 Receiver for additional information 7 1 2 Baud Rate Generator Logic The crystal oscillator operates directly from a 3 6864 MHz crystal connected across the X1 input and the X2 output or from an ex
383. l Timing 11 14 Timer Module Signal Timing 11 15 Serial Module General Timing MC68340 USER S MANUAL Z Ooooooooooooo MOTOROLA 11 2 95 SECTION 1 OVERVIEW UM Rev 1 LIST OF ILLUSTRATIONS Concluded Figure Page Number Title Number 11 16 Serial Module Asynchronous Mode Timing 1 11 23 11 17 Serial Module Asynchronous Mode Timing SCLK 196X 11 23 11 18 Serial Module Synchronous Mode Timing Diagram 11 23 11 19 Test Clock Input Timing Diagtam sc c acento to em eee teat 11 25 11 20 Boundary Scan Timing Diagram sse 11 26 11 21 Test Access Port Timing uude te ledit eiue 11 26 MOTOROLA MC68340 USER S MANUAL xxi 11 2 95 SECTION 1 OVERVIEW UM Rev 1 0 LIST OF TABLES Table Page Number Title Number 2 1 Index cssc otc 2 2 2 2 Address Space Encodirigr us ae neret 2 5 2 3 SACK mc 2 6 2 4 5174 Signal Encodings E I E ald de 2 7 2 5 Signali tT ANY here eek S 2 14 3 1 Signal BAC OGIAG e cence DC ceed DIES 3 3 3 2 Address Space Encodiligi c dn eater eto Dente espe edes 3 3 3 3 SACK
384. l channel A for communication with 9600 baud terminal Note All serial module registers must be accessed as bytes kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MODBASE EQU FFFFF000 SIM40 MBAR address value kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Serial module equates SERIAL EQU 700 Offset from MBAR for serial module regs MCRH EQU 0 serial MCR high byte MCRL EQU 1 serial MCR low byte MOTOROLA MC68340 USER S MANUAL 7 47 Serial register offsets from serial base address MR1A EQU 10 Mode register 1 A MR2A EQU 20 Mode register 2 A SRA EQU 11 Status register A CSRA EQU 11 Clock select reg A CRA EQU 12 Command reg A ACR EQU 14 Auxiliary control reg OPCR EQU 1D Output port control reg OP BS EQU 1E Output port bit set write 1 to set OP EQU 1F Output port bit reset write 1 to clear kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Initialize Serial channel A kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk LEA MODBASE SERIAL AO Pointer to serial channel A Module configuration regist
385. l groups NOTE The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active low and active high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a signal is inactive or false 7 4 MC68340 USER S MANUAL MOTOROLA ADDRESS BUS X1 BAUD RATE 2 amp 0 CONTROL GENERATOR u NTROL LOGIC LOGIC SCLK TEM t E 6 gt _ CHANNEL A FOUR CHARACTER RECEIVE BUFFER DATA BUS MUX TWO CHARACTER TRANSMIT BUFFER CUO CTSA RxRDYA S NVNDIS SOVJH31NI TVNH DX zomcz CHANNEL B FOUR CHARACTER RECEIVE BUFFER TWO CHARACTER TRANSMIT BUFFER Figure 7 2 External and Internal Interface Signals 7 2 1 Crystal Input or External Clock X1 This input is one of two connections to a crystal or a single connection to an external clock A crystal or an external clock signal at 3 6864 MHz must be supplied when using the baud rate generator If a crystal is used a capacitor of approximately 10 pF should be connected from this signal to ground If this input is not used it must be connected to Vcc or GND Refer to Section 10 Applications for an example of a clock driver circuit 7 2 2 Crystal Output X2 T
386. lculation but the concept can be generalized to any instruction only two words are required to be in the pipeline but up to three words may be present When there is an opportunity for an extra prefetch it is made A prefetch to replace an instruction can begin ahead of the instruction resulting in a faster processor 5 7 3 Instruction Timing Tables The following assumptions apply to the times shown in the subsequent tables A 16 bit data bus is used for all memory accesses Memory access times are based on two clock bus cycles with no wait states The instruction pipeline is full at the beginning of the instruction and is refilled by the end of the instruction Three values are listed for each instruction and addressing mode Head number of cycles available at the beginning of an instruction to complete a previous instruction write or to perform a prefetch Tail The number of cycles an instruction uses to complete a write Cycles Four numbers per entry three contained in parentheses The outer number is the minimum number of cycles required for the instruction to complete Numbers within the parentheses represent the number of bus accesses performed by the instruction The first number is the number of operand read accesses performed by the instruction The second number is the number of instruction fetches performed by the instruction including all prefetches that keep the instruction and the instruction pipeline
387. le shot pulse generation event counting period measurement and pulse width measurement Each timer consists of a 16 bit countdown counter with an 8 bit countdown prescaler for a composite 24 bit resolution The two timers can be externally cascaded for a maximum count width of 48 bits The counter timer can be clocked by the internal system clock generated by the SIM40 2 or by an external clock input Either the processor or external stimuli can trigger the starting and stopping of the counter When a counter reaches a predetermined value either an external output signal can be driven or an interrupt can be made to the CPU32 The finest resolution of the timer is 80 ns with 25 MHz system clock 125 ns e 16 78 MHz 1 4 POWER CONSUMPTION MANAGEMENT The MC68340 is very power efficient due to its advanced 0 8 u HCMOS process technology and its static logic design The resulting power consumption is typically 900 mW full operation 25 MHz 650 mW qe 16 78 MHz far less than the comparable discrete component implementation the MC68340 can replace For applications employing reduced voltage operation selection of the MC68340V which 1 8 MC68340 USER S MANUAL MOTOROLA requires only a 3 3 V power supply reduces current consumption by 40 60 in all modes of operation as well as reducing noise emissions The MC68340 has many additional methods of dynamically controlling power consumption during operation The frequency of operation
388. ledge 4 Other address signals A31 A20 A15 A4 and 0 are set to one 5 The SIZO SIZ1 and R W signals are driven to indicate a single byte read cycle The responding device places the vector number on the least significant byte of its data port for an 8 bit port the vector number must be on D15 D8 for a 16 bit port the vector must be on 07 00 during the interrupt acknowledge cycle The cycle is then terminated normally with DSACK Figure 3 14 is a flowchart of the interrupt acknowledge cycle Figure 3 15 shows the timing for an interrupt acknowledge cycle terminated with DSACK INTERRUPTING DEVICE MC68340 REQUEST INTERRUPT GRANT INTERRUPT 1 SYNCHRONIZE IRQ7 IRQ1 COMPARE IRQ1 IRQ7 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE PLACE INTERRUPT LEVEL ON 1 TYPE FIELD A19 A16 F SET R W TO READ SET FC3 FCO TO 0111 DRIVE SIZE PINS TO INDICATE A ONE BYTE TRANSFER ASSERT AS AND DS PROVIDE VECTOR NUMBER ASSERT THE CORRESPONDING IACKx STROBE 1 PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA BUS 2 ASSERT DSACKx OR AVEC IF NO VECTOR NUMBER ACQUIRE VECTOR NUMBER 1 LATCH VECTOR NUMBER RELEASE 2 NEGATE DS AND AS 1 NEGATE DSACKx START NEXT CYCLE Figure 3 14 Interrupt Acknowledge Cycle Flowchart 3 28 MC68340 USER S MANUAL MOTOROLA N 0 2CLOCKS 51 52 54 50 52 CLKOUT TUUU 8 1 4 X
389. ler and counter are disabled Additionally the TG bit of the SR is set indicating that TGATE was negated The ON bit of the SR is cleared indicating that the timer is disabled If TGATE z is reasserted the timer is re enabled and begins counting from the value attained when was negated The ON bit is set again If TGATE is not enabled TGE 0 TGATE has no effect on the operation of the timer In this case the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set The SR TG bit cannot be set At all times the TGL bit in the SR reflects the level of TGATE The duty cycle of the waveform generated on TOUTx can be dynamically changed by writing new values into PREL1 and or PREL2 If PREL1 or PREL2 is being accessed simultaneously by the counter logic and a CPU32 write the old preload value may actually get loaded into the counter at timeout If at timeout the counting logic was accessing PREL2 and the CPU32 was writing to PREL1 or visa versa there would be no unexpected results 8 3 4 Variable Width Single Shot Pulse Generator This mode is used to produce a one time pulse that has a delay controlled by the value stored in PREL1 and a duration controlled by the value stored in PREL2 With TOUTx programmed to change state this sequence creates a single pulse of variable width This mode can be selected by programming the CR MODE bits to 011 8 10 MC6
390. ler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions For example consider the arrival of an interrupt during execution of a TRAP instruction while tracing is enabled Trap exception processing 2 is done first followed immediately by exception processing for the trace 4 1 and then by exception processing for the interrupt 4 3 Each exception places a new context on the stack When the processor resumes normal instruction execution it is vectored to the interrupt handler which returns to the trace handler that returns to the trap handler There are special cases to which the general rule does not apply The reset exception will always be the first exception handled since reset clears all other exceptions It is also possible for high priority exception processing to begin before low priority exception processing is complete For example if a bus error occurs during trace exception processing the bus error will be processed and handled before trace exception processing is completed 5 42 MC68340 USER S MANUAL MOTOROLA 5 5 2 Processing of Specific Exceptions The following paragraphs provide details concerning sources of specific exceptions how each arises and how each is processed 5 5 2 1 RESET Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception The reset exception has the highest priority of a
391. lize significant savings in design time power consumption cost board space pin count and programming The equivalent functionality can easily require 20 separate components Each component might have 16 64 pins totaling over 350 connections Most of these connections require interconnects or are duplications Each connection is a candidate for a bad solder joint or misrouted trace Each component is another part to qualify purchase inventory and maintain Each component requires a share of the printed circuit board Each component draws power often to drive large buffers to get the signal to another chip The cumulative power consumption of all the components must be available from the power supply The signals between the CPU and a peripheral might not be compatible nor run from the same clock requiring time delays or other special design considerations In a M68300 family component the major functions and glue logic are all properly connected internally timed with the same clock fully tested and uniformly documented Power consumption stays well under a watt and a special standby mode drops current well under a milliamp during idle periods Only essential signals are brought out to pins The primary package is the surface mount quad flat pack for the smallest possible footprint pin grid arrays are also available 1 2 CENTRAL PROCESSOR UNIT The CPU32 is a powerful central processor that supervises system functions makes decisions
392. logic may assert to abort the bus cycle with HALT to retry the bus cycle DSACK can be asserted before the data from a slave device is valid on a read cycle The length of time that may precede data must not exceed a specified value in any asynchronous system to ensure that valid data is latched into the MC68340 See Section 11 Electrical Characteristics for timing parameters Note that no maximum time is specified from the assertion of AS to the assertion of DSACK z Although the MC68340 can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK the MC68340 inserts wait cycles in clock period increments until DSACK is recognized BERR and or HALT can be asserted after DSACK is asserted BERR and or HALT must be asserted within the time specified after DSACK is asserted in any asynchronous system If this maximum delay time is violated the MC68340 may exhibit erratic behavior 3 2 5 Synchronous Operation with DSACK Although cycles terminated with DSACK z are classified as asynchronous cycles terminated with DSACK can also operate synchronously in that signals are interpreted relative to clock edges The devices that use these cycles must synchronize the response to the MC68340 clock CLKOUT to be synchronous Since the devices terminate bus cycles with DSACKs the dynamic bus sizing capabilities of the MC68340 are available The minimum cycle time for these cycles is al
393. ly shift out the result in the boundary scan register c Bypass the MC68340 for a given circuit board test by effectively reducing the boundary scan register to a single bit d Disable the output drive to pins during circuit board testing NOTE Certain precautions must be observed to ensure that the IEEE 1149 1 test logic does not interfere with nontest operation See 9 6 Non IEEE 1149 1 Operation for details 9 1 OVERVIEW NOTE This description is not intended to be used without the supporting IEEE 1149 1 document The discussion includes those items required by the standard and provides additional information specific to the MC68340 implementation For internal details and applications of the standard refer to the IEEE 1149 1 document MOTOROLA MC68340 USER S MANUAL 9 1 An overview of the MC68340 implementation of IEEE 1149 1 is shown in Figure 9 1 The MC68340 implementation includes a 16 state controller a 3 bit instruction register and two test registers a 1 bit bypass register and a 132 bit boundary scan register This implementation includes a dedicated TAP consisting of the following signals atest clock input to synchronize the test logic TMS atest mode select input with an internal pullup resistor that is sampled on the rising edge of TCK to sequence the TAP controller s state machine TDI atest data input with an internal pullup resistor that is sampled the rising edge of TCK at
394. manipulates data and directs A special debugging mode simplifies processor emulation during system debug MOTOROLA MC68340 USER S MANUAL 1 3 1 2 1 CPU32 The CPU32 is an M68000 family processor specially designed for use as a 32 bit core processor and for operation over the intermodule bus IMB Designers used the MC68020 as a model and included advances of the later M68000 family processors resulting in an instruction execution performance of 4 MIPS VAX equivalent at 25 16 MHz The powerful and flexible M68000 architecture is the basis of the CPU32 68000 including the 68 000 and the MC68ECO000 and MC68010 user programs will run unmodified on the CPU32 The programmer can use any of the eight 32 bit data registers for fast manipulation of data and any of the eight 32 bit address registers for indexing data in memory The CPU32 can operate on data types of single bits binary coded decimal BCD digits and 8 16 and 32 bits Peripherals and data in memory can reside anywhere in the 4 Gbyte linear address space A supervisor operating mode protects system level resources from the more restricted user mode allowing a true virtual environment to be developed Flexible instructions for data movement arithmetic functions logical operations shifts and rotates bit set and clear conditional and unconditional program branches and overall system control are supported including a fast 32 x 32 multiply and 32 bit conditional
395. many control signals and the address on the address bus AS is asserted approximately one half clock cycle after the beginning of a bus cycle 3 1 5 Data Bus D15 D0 This bidirectional nonmultiplexed parallel bus contains the data being transferred to or from the MC68340 A read or write operation may transfer 8 or 16 bits of data one or two bytes in one bus cycle During a read cycle the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle For a write cycle all 16 bits of the data bus are driven regardless of the port width or operand size The MC68340 places the data on the data bus approximately one half clock cycle after AS is asserted in a write cycle 3 1 6 Data Strobe DS DS is an output timing signal that applies to the data bus For a read cycle the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus For a write cycle DS signals to the external device that the data to be written is valid The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle 3 1 7 Bus Cycle Termination Signals The following signals can terminate a bus cycle 3 1 7 1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS DSACK1 AND DSACKO During bus cycles external devices assert DSACK1 and or DSACKO as part of the bus protocol During a read cycle this signals the MC68340 to terminate the bus cycle and to latch the data During a writ
396. mat 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 34 AEEONEEREGNEXSEXES Command Sequence WRITE WRITE BIW MS ADDR LS ADDR DATA XXX gt WOT READY gt NOT READY gt NOT READY 7 MEAN gt NOT READY XXX gt NEXT CND NEXT CMD ILLEGAL NOT READY CMD COMPLETE BERR AERR V LS NEXT CMD NOT READY WRITE LONG gt NS ADDR LS ADDR Y MS DATA NOT READY NOT READY J READY XXX gt NEXT CMD ILLEGAL READY LS DATA WERDE y XXX NOT READY LOCATION NOT READY NEXT CMD CMD COMPLETE BERR AERR NEXT CMD NOT READY Operand Data Two operands are required for this instruction The first operand is a long word absolute address that specifies a location to which the operand data is to be written The second operand is the data Byte data is transmitted as a 16 bit word justified in the least significant byte 16 and 32 bit operands are transmitted as 16 and 32 bits respectively Result Data Successful write operations return a status of 0FFFF Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of 0001 5 6 2 8 10 Dump Memory Block DUMP DUMP is used in conjunction with the READ command to dump large blocks of memory An initial READ is executed to set up the 5 80 MC68340 USER S MANUAL MOTOROLA starting addre
397. mat Ree MEM M cla tegi 5 72 5 26 5 1 Logic P dts 5 72 5 27 Command Sequence 2 2 2 0 4 4 40 0 0 5 75 5 28 Functional Model of Instruction Pipeline esses 5 87 5 29 Instruction Pipeline Timing 2202 04 5 88 5 30 Block Diagram of Independent 5 90 5 31 Simultaneous Instruction Execution seeeeeeeennnne 5 91 5 32 Attributed Instruction tte cans tp qan depre 5 92 5 33 Example 1 Stream cccceceseeceeceseeeeeceeeeeeeeeeeceeeseeeceaneeeseeaneeeaees 5 95 5 34 Example 2 5 95 5 35 Example 2 Branch Not Taken nie pae tenue 5 96 5 36 Example 3 Branch Negative Tail essen 5 96 xviii MC68340 USER S MANUAL MOTOROLA 11 2 95 SECTION 1 OVERVIEW UM Rev 1 LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 6 1 DMA Block tue 6 1 6 2 Single Address a at 6 3 6 3 6 3 6 4 DMA External Connections to Serial 6 6 6 5 Single Address
398. mber of wait states the V bit in the module base address register should be set 4 2 6 Low Power Stop Executing the LPSTOP instruction provides reduced power consumption when the MC68340 is idle only the 5 40 remains active Operation of the 5 40 clock and CLKOUT during LPSTOP is controlled by the STSIM and STEXT bits in the SYNCR see Table 4 3 LPSTOP disables the clock to the software watchdog in the low state The software watchdog remains stopped until the LPSTOP mode ends it begins to run again on the next rising clock edge NOTE When the CPUS2 executes the STOP instruction as opposed to LPSTOP the software watchdog continues to run If the software watchdog is enabled it issues a reset or interrupt when timeout occurs The periodic interrupt timer does not respond to an LPSTOP instruction thus it can be used to exit LPSTOP as long as the interrupt request level is higher than the 2 interrupt mask level To stop the periodic interrupt timer while in LPSTOP the PITR must be loaded with a zero value before LPSTOP is executed The bus monitor double bus fault monitor and spurious interrupt monitor are all inactive during LPSTOP The STP bit in the MCR of each on chip module DMA timers and serial modules should be set prior to executing the LPSTOP instruction Setting the STP bit stops all clocks within each of the modules except for the clock from the IMB The clock from the IMB remains active to allow the
399. me as for a hardware reset The external devices connected to the RESET signal are reset at the completion of the RESET instruction MOTOROLA MC68340 USER S MANUAL 5 43 ENTRY 15 0 P TOTI 7 p 2 0 0 0 p VBR FETCH VECTOR 0 OTHERWISE BUS ERROR SP b VECTOR 0 FETCH VECTOR 1 OTHERWISE BUS ERROR PC P VECTOR 1 PREFETCH 3 WORDS BUS ERROR ADDRESS OTHERWISE BEGIN INSTRUCTION ERROR EXECUTION DOUBLE BUS FAULT ASSERT HALT EXIT Figure 5 11 Reset Operation Flowchart EXIT MC68340 USER S MANUAL MOTOROLA 5 5 2 2 BUS ERROR bus error exception occurs when an assertion of the BERR signal is acknowledged The signal can be asserted by one of three sources 1 External logic by assertion of the BERR input pin 2 Direct assertion of the internal BERR signal by an internal module 3 Direct assertion of the internal BERR signal by the on chip hardware watchdog after detecting a no response condition Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle When the aborted bus cycle is an instruction prefetch the processor will not initiate exception processing unless the prefetched information is used For example if a branch instruction flushes an aborted prefetch that word is not accessed and no exception occurs When the aborted bus cycle is a data access the processor initiates exception processing immediately except
400. mer Gate TGATE2 TGATE 1 serene 2 12 2 14 2 Timer Input TIN2 eeu pe m oc littere opere 2 12 2 14 3 Timer TOUT 2 TOUT T aciei Ru E E her be aeter 2 12 iv MC68340 USER S MANUAL MOTOROLA 11 2 95 Number 2 15 2 15 1 2 15 2 2 15 3 2 15 4 2 16 2 17 2 18 Co Co N CO On 3 2 3 1 3 2 3 2 3 2 3 3 3 2 3 4 3 2 3 5 3 2 3 6 3 2 3 7 3 2 4 3 2 5 3 2 6 3 3 3 3 1 3 3 2 3 3 3 MOTOROLA SECTION 1 OVERVIEW UM Rev 1 TABLE OF CONTENTS Continued Page Title Number c 2 13 MGStGCIOCK TOK 4 A aa 2 13 Test Mode Select IMS n repete 2 13 kest DAIM D 2 13 Test Data Out PB 2 13 Synthesizer Power 2 13 System Power and Ground Vcc and 2 13 Signal S MMAT RN ELLO 2 13 Section 3 Bus Operation Bus Tratisterdldghale co esca diat oin oa cttm 3 1 Bus Control Signals eC Cc 3 2 Function Code denen rere atia enis 3 3 Address BUSAST A O ee adt 3 4 Address otobe a i tas hs e 3 4
401. mmand 5 85 5 86 Operation 3 45 3 46 Receiver Command 7 28 Signal 2 8 3 45 3 48 5 66 Status Register 4 3 4 23 Types 3 45 Timing 3 47 Transmitter Command 7 28 Values for Counter and Prescaler 8 2 Vector 5 4 RESET Signal 3 45 3 48 5 43 Retry Bus Cycle Operation 3 32 3 34 3 35 Timing 3 37 Timing Late Retry 3 38 Return From Exception 5 51 5 52 Return Program Counter 5 67 5 68 Returning From Background Mode 5 68 RM Bit 5 53 ROM Interface 10 3 RR Bit 5 53 RS 232 Interface 10 4 10 5 RSTEN Bit 4 29 RTE Instruction 5 57 5 59 5 61 RTS Operation 7 11 7 22 RTSA Signal 7 6 7 37 RTSB Signal 7 6 7 36 RTS Signal 7 11 7 13 7 22 7 29 7 38 RW Bit 5 54 RxDx Signal 7 6 7 11 7 14 7 24 RxRDA Bit 7 11 7 13 7 15 7 24 7 25 RxRDYA Bit 7 34 7 35 MOTOROLA R RDYA Signal 7 7 7 36 RxRDYB Bit 7 33 7 35 RxRTS Bit 7 22 7 47 mE S D Bit 6 30 6 37 SAPI Bits 6 12 6 19 6 28 6 37 Save and Restore Operations Timing Table 5 113 SB Bits 7 39 7 47 SCLK Signal 7 3 7 6 7 8 7 20 SE Bit 6 25 6 36 Selected Clock 8 3 8 21 Serial Clock Signal 2 11 Command Control 7 27 Communication Overview 7 3 Compatibility with MC68681 7 4 Crystal Oscillator 7 3 7 5 Diagnostic Functions 7 14 Initialization 7 46 7 49 Interface Timing 5 68 5 71 Interface 10 4 10 5 Maximum Data Transfer Rate 7 2 Module Capabilities 7 2 Module Programming Model 7 19 Module Programming 7 4
402. mmand SUrmialfy desi ot 5 77 5 24 Register Field for RSREG and WSREG essent 5 79 6 1 FRZX Control lc 6 24 6 2 SoIZEx Eneoditiq a n de AT E 6 28 6 3 DSIZEX MINER DN 6 29 6 4 BEOQX EncodIit sense tensa desta nese 6 29 6 5 BBx Encoding and BUS o oo Su aite etude 6 29 6 6 Address Space Encoding o edt eee e e ed p Gate 6 32 7 1 EEZXOGOnDEIOLBIIS iecur acer esee eta cse eu an 7 20 7 2 PMx and Control BIS oot cd eee dn e di pe 7 23 7 3 B OX GOntTOPBIIS ooo idest o 7 24 7 4 RCSx Control BIS eal e tto dote 7 26 7 5 Control a NM E ME 7 27 7 6 MISCx Control 7 28 7 7 pne seen act 7 29 7 8 RGX Control BIS uidet ido eta 7 30 7 9 CM Gontro BIG a te eatery o dee ee ad 7 38 SBX Control BING setti a Send uL 7 39 8 1 Encodild ios 8 17 8 2 ERZXCGODIEOLBIIS deed ee 8 19 8 3 RD LLL DU LIAE 8 21 8 4 PDT VC OGM
403. modify the CCR provide system control operations All of these instructions cause the processor to flush the instruction pipeline Table 5 11 summarizes the instructions The preceding list of condition tests also applies to the TRAPcc instruction Refer to 5 3 3 10 Condition Tests for detailed information on condition codes MOTOROLA MC68340 USER S MANUAL 5 27 Table 5 11 System Control Operations Operand Syntax Operand Size Operation Privileged ANDI data SR Immediate Data A SR SR EORI data SR Immediate Data SR SR MOVE ea SR Source SR SR ea SR Destination MOVEA USP An USP 2 An An USP MOVEC Rc Rn Rn Rc MOVES Rn ea 8 16 32 ea Rn 3 3 3 3 Rn Destination using DFC Source using SFC Rn An USP Rc data SR 1 Immediate Data V SR gt SR none Assert RESET line Rn Rc none none SP SR SP 2 gt SP gt SP 4 gt SP restore stack according to format data 1 Immediate Data SR STOP LPSTOP data none Immediate Data SR interrupt mask EBI STOP Trap Generating BKPT data none If breakpoint cycle acknowledged then execute returned operation word else trap as illegal instruction BGND none If background mode enabled then enter background mode else format vector offset 2 SSP PC SSP SR SSP vector 16 32 If Dn lt 0 or Dn lt ea then CHK exception CHK2 Rn 8 16 32 If Rn lower b
404. modules It will however reset external devices and all other registers in the peripheral modules 4 3 2 4 SOFTWARE INTERRUPT VECTOR REGISTER SWIV The SWIV contains the 8 bit vector that is returned by the SIM40 during an IACK cycle in response to an interrupt generated by the software watchdog This register can be read or written at any time This register is set to the uninitialized vector 0F at reset SWIV 020 7 6 5 4 3 2 1 0 SWIV7 SWIV6 SWIV5 SWIV4 SWIV3 SWIV2 SWIV1 SWIVO RESET 0 0 0 0 1 1 1 1 Supervisor Only 4 3 2 5 SYSTEM PROTECTION CONTROL REGISTER SYPCR The SYPCR controls the system monitors the prescaler for the software watchdog and the bus monitor timing This register can be read at any time but can be written only once after reset SYPCR 021 1 6 5 4 3 2 1 0 SWRI SWTO DBFE BMT1 BMTO RESET 0 0 0 0 0 0 0 0 Supervisor Only SWE Software Watchdog Enable 1 Software watchdog is enabled 0 Software watchdog is disabled See 4 2 2 5 Software Watchdog for more information SWRI Software Watchdog Reset Interrupt Select 1 Software watchdog causes a system reset 0 Software watchdog causes a level 7 interrupt to the CPU32 4 24 MC68340 USER S MANUAL MOTOROLA SWT1 SWT0 Software Watchdog Timing These bits along with the SWP bit in the PITR control the divide ratio used to establish the timeout period for the software watchdog The software watchdog timeout period
405. multiple bus cycles may be required for an operand transfer due to either misalignment or a word or long word operand 3 1 BUS TRANSFER SIGNALS The bus transfers information between the MC68340 and external memory or a peripheral device External devices can accept or provide 8 bits or 16 bits in parallel and must follow the handshake protocol described in this section The maximum number of bits accepted or provided during a bus transfer is defined as the port width The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer The selected device then controls the length of the cycle with the signal s used to terminate the cycle Strobe signals one for the address bus and another for the data bus indicate the validity of the address and provide timing information for the data Both asynchronous and synchronous operation is possible for any port width In asynchronous operation the bus and control input signals are internally synchronized to the MC68340 clock introducing a delay This delay is the time required for the MC68340 to sample an input signal synchronize the input to the internal clocks and determine whether it is high or low In synchronous mode the bus and control input signals must be timed to setup and hold times Since no synchronization is needed bus cycles c
406. n target system and emulator IN CIRCUIT EMULATOR TARGET MCU Figure 5 18 In Circuit Emulator Configuration TARGET SYSTEM By contrast an integrated debugger supports use of a bus state analyzer BSA for in circuit emulation The processor remains in the target system see Figure 5 19 and the interface is simplified The BSA monitors target processor operation and the on chip debugger controls the operating environment Emulation is much closer to target hardware thus many interfacing problems i e limitations on high frequency operation AC and DC parametric mismatches and restrictions on cable length are minimized TARGET SYSTEM lt lt BUS STATE Figure 5 19 Bus State Analyzer Configuration 5 6 1 2 DETERMINISTIC OPCODE TRACKING OVERVIEW 2 function code outputs are augmented by two supplementary signals that monitor the instruction pipeline The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline and signals pipeline flushes The IPIPE output signal indicates when each mid instruction pipeline advance occurs and when instruction execution begins These signals allow a BSA to synchronize with instruction stream activity Refer to 5 6 3 Deterministic Opcode Tracking for complete information 5 6 1 3 ON CHIP HARDWARE BREAKPOINT OVERVIEW An external breakpoint input and an on chip hardware breakpoint capability permit breakpoint tr
407. n handler does not alter the stacked SR trace bits the trace is requeued when the instruction is started The breakpoint pending bits are stacked in the SSW even though the instruction is restarted upon return from the handler This avoids problems with bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location If this response is not desired the exception handler can clear the bits before return The RM IN RW LG FUNC and SIZ fields all reflect the type of bus cycle that caused the fault If the bus cycle was an RMW the RM bit will be set and the RW bit will show whether the fault was on a read or write MOTOROLA MC68340 USER S MANUAL 5 55 5 5 3 1 3 Type Ill Faults During MOVEM Operand Transfer Bus faults that occur as result of MOVEM operand transfer are classified as type III faults MOVEM instruction prefetch faults are type II faults Type III faults cause an immediate exception that aborts the current instruction None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler This includes any register predecremented as a result of the effective address calculation or any register overwritten during instruction execution Since postincremented registers are not updated until the end of an instruction the register retains its pre instruction value unless overwritten by opera
408. n of bus cycles while the sequencer is calculating the next EA One clock is saved between instructions since that is the minimum time of the individual head and tail numbers Instructions MOVE W A1 ADDQ W 1 AO CLR W 30 A1 5 94 MC68340 USER S MANUAL MOTOROLA BUS CONTROLLER WRITE 1 PRE READ WRITE 2 PRE 3PRE 3PRE WRITE FOR 1 FETCH FOR 2 FOR 2 FETCH FETCH FETCH FOR 3 EA ADDQ EA CLR MOVE W A1 AO ADDQ W 0 CLR W 30 A1 Figure 5 33 Example 1 Instruction Stream INSTRUCTION CONTROLLER EXECUTION TIME 5 7 2 2 TIMING EXAMPLE 2 BRANCH INSTRUCTIONS Example 2 shows what happens when a branch instruction is executed for both the taken and not taken cases see Figures 5 34 and 5 35 The instruction stream is for a simple limit check with the variable already in a data register Instructions MOVEQ 7 D1 CMP L D1 DO BLE B NEXT MOVE L D1 A0 BUS CONTROLLER PRE WRITE FETCH FETCH FETCH FOR 3 OFFSET NEXT CALC TAKEN TAKEN TAKEN INST INSTRUCTION CONTROLLER BLE B NOT TAKEN EXECUTION TIME Figure 5 34 Example 2 Branch Taken MOTOROLA MC68340 USER S MANUAL 5 95 BUS 3 PRE 4PRE CONTROLLER FETCH FETCH INSTRUCTION OFFSET NOT MOVE TO CONTROLLER CALC TAKEN A0 ERE BLE B NOT TAKEN MOVE L 01 40
409. n progress TR Trace pending B1 Breakpoint channel 1 pending BO Breakpoint channel 0 pending RR Rerun write cycle after RTE RM Faulted cycle was read modify write IN Instruction other RW Read write of faulted bus cycle LG Original operand size was long word SIZ Remaining size of faulted bus cycle FUNC Function code of faulted bus cycle 5 52 MC68340 USER S MANUAL MOTOROLA The TP field defines the class of the faulted bus operation Two bus error exception frame types are defined One is for faults on prefetch and operand accesses and the other is for faults during exception frame stacking 0 Operand or prefetch bus fault 1 Exception processing bus fault MV is set when the operand transfer portion of the MOVEM instruction is in progress at the time of a bus fault If a prefetch bus fault occurs while prefetching the MOVEM opcode and extension word both the MV and IN bits will be set 0 MOVEM was not in progress when fault occurred 1 MOVEM was in progress when fault occurred TR indicates that a trace exception was pending when a bus error exception was processed The instruction that generated the trace will not be restarted upon return from the exception handler This includes MOVEM and released write bus errors indicated by the assertion of either MV or RR in the SSW 0 Trace not pending 1 Trace pending B1 indicates that a breakpoint exception was pending on channel 1 external breakpoint source w
410. n the 5 40 The first number is the offset for channel 1 the second number is the offset for channel 2 The numbers above the register represent the bit position in the register The register contains the mnemonic for the bit The value of these bits after a hardware reset is shown below the register The access privilege is shown in the lower right hand corner NOTE A CPU32 RESET instruction will not affect the MCR but will reset all other registers in the DMA module as though a hardware reset occurred The term DMA is used to reference either channel 1 or channel 2 since the two are functionally equivalent 6 7 1 Module Configuration Register MCR The MCR controls the DMA channel configuration Each DMA channel has an MCR This register can be either read or written when the channel is enabled and is in the supervisor state The MCR is not affected by a CPU32 RESET instruction MOTOROLA MC68340 USER S MANUAL 6 23 MCR1 MCR2 780 7A0 15 14 3 2 1 0 13 12 11 10 9 8 7 6 5 4 RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Supervisor Only STP Stop Bit 1 Setting the STP bit stops all clocks within the DMA module except for the clock from the IMB The clock from the IMB remains active to allow the CPU32 access to the MCR The clock stops on the low phase of the clock and remains stopped until the STP bit is cleared by the CPUS2 or a hardware reset Accesses to DMA module registers while in stop mode produce a bus error The DMA mod
411. nal circuitry to assign priorities to the devices so that when two or more external devices attempt to become bus master at the same time the one having the highest priority becomes bus master first The sequence of the protocol is as follows 1 An external device asserts BR 2 The MC68340 asserts to indicate that the bus is available 3 The external device asserts BGACK to indicate that it has assumed bus mastership NOTE The MC68340 does not place CS3 CSO in a high impedance state after reset or when the bus is granted to an external master BR may be issued any time during a bus cycle or between cycles BG is asserted in response to BR To guarantee operand coherency BG is only asserted at the end of an operand transfer Additionally BG is not asserted until the end of a read modify write operation when RMC is negated in response to a BR signal When the requesting device receives BG and more than one external device can be bus master the requesting device should begin whatever arbitration is required When the external device assumes bus mastership it asserts BGACK and maintains BGACK during the entire bus cycle or cycles for which it is bus master The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure 1 it must have received BG through the arbitration process and 2 BGACK must be inactive indicating that no other bus master has claimed own
412. nation ADDA ea An ADDQ Immediate Data Destination Destination ADDQ 5t data ea DD ADDX Source Destination X Destination ADDX Dy Dx ADDX Ay Ax AND Source A Destination Destination AND ea Dn AND Dn ea ADDI Immediate Data Destination 2 Destination ADDI ANDI Immediate Data Destination Destination ANDI ANDI to Source A CCR CCR ANDI data CCR ANDI to SR If supervisor state ANDI data SR the Source A SR SR else TRAP ASL ASR Destination Shifted by count Destination ASd Dx Dy ASd data Dy ASd ea If condition true then PC d PC Bcc label BCHG number of Destination Z BCHG Dn ea number of Destination bit number of BCHG data ea Destination BCLR number of Destination Z BCLR Dn ea 0 bit number of Destination BCLR 4 data ea BGND If background mode enabled then BGND enter background mode else Format Vector offset SSP PC 2 SSP SR 2 SSP Vector 2 PC BKPT Run breakpoint acknowledge cycle BKPT data TRAP as illegal instruction PC d PC BRA label BSET number of Destination Z BSET Dn e3 1 bit number of Destination BSET data ea SP 4 gt SP PC gt SP PC d 5 PC BSR label BTST number of Destination Z BTST Dn ea BTST data ea If Dn lt 0 or Dn gt Source then TRAP CHK ea Dn CHK2 If Rn lt lower bound or 2 ea
413. nchronous data transfers and dynamic data bus sizing between the MC68340 and external devices as listed in Table 2 3 During bus cycles external devices assert DSACK1 and or DSACKO as part of the bus protocol During a read cycle this signals the MC68340 to terminate the bus cycle and to latch the data During a write cycle this indicates that the external device has successfully stored the data and that the cycle may terminate Table 2 3 DSACK Encoding DSACK DSACK 1 0 1 1 Insert Wait States in Current Bus Cycle pass 1 0 Complete Cycle Data Bus Port Size Is 8 Bits Kc nei 1 Complete Cycle Data Bus Port Size Is 16 Bits Reserved Defaults to 16 Bit Port Size Can Be Used for 32 Bit DMA Cycles 2 7 2 Address Strobe AS AS is an output timing signal that indicates the validity of both an address on the address bus and many control signals AS is asserted approximately one half clock cycle after the beginning of a bus cycle 2 6 MC68340 USER S MANUAL MOTOROLA 2 7 3 Data Strobe DS DS is an output timing signal that applies to the data bus For a read cycle the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus For a write cycle DS signals to the external device that the data to be written is valid The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle 2 7 4 Transfer Size SIZ1 SIZO These output signals are dri
414. nd cycle steal modes MOTOROLA MC68340 USER S MANUAL 6 7 CPU CYCLE S0 S2 54 50 DMA READ 52 54 50 DMA READ 52 54 CPU CYCLE S0 DREQx DONEx INPUT DACKx N N DONEx N OUTPUT NOTE 1 Timing to generate more than one DMA request 2 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle 3 DREQx must be asserted while DACKx is asserted and meet the setup and hold times for more than one DMA transfer to be recognized Figure 6 5 Single Address Read Timing External Burst 6 8 MC68340 USER S MANUAL MOTOROLA VIOYOLOW TWANVIN S YASN 07289921 69 CLKOUT 1 FC3 FCO 5121 5120 B 2 015 00 DSACKx DREQx DONEx INPUT DACKx DONEx OUTPUT NOTE CPU CYCLE SO S2 54 CPU CYCLE so S2 54 50 DMA READ S2 54 so CPU CYCLE S2 54 1 DREQx must be active for two consecutive clocks for request to be recognized 2 To cause another DMA transfer DREQ x is asserted after DACKx is asserted and before DACKx is negated 3 DACKx and DONEx DMA control signals are asserted in the source read DMA cycle Figure 6 6 Single Address Read Timing Cycle Steal so DMA READ S2 54 6 4 1 2 SINGLE ADDRESS WRITE During the single address destination write cycle the DMA controls the transfer of data from a device to memory The
415. nd movement The SSW for faults in this category contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 mj s MV is set indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler TR B1 and BO are set if a corresponding exception is pending when the bus error exception is taken IN is set if a bus fault occurs while prefetching an opcode or an extension word during instruction restart RW LG SIZ and FUNC all reflect the type of bus cycle that caused the fault All write faults have the RR bit set to indicate that the write should be rerun upon return from the exception handler The remainder of the stack frame contains sufficient information to continue MOVEM with operand transfer following a faulted transfer The address of the next operand to be transferred incremented or decremented by operand size is stored in the faulted address location 08 The stacked transfer counter is set to 16 minus the number of transfers attempted including the faulted cycle Refer to Figure 5 12 for the stacking format 5 5 3 1 4 Type IV Faults During Exception Processing The fourth type of fault occurs during exception processing If this exception is a second address or bus error the machine halts in the double bus fault condition However if the exception is one that causes a four or six word stack frame to be written a bus cycle fault fram
416. nd negated according to the configuration programmed by RxRTS bit 7 in the MR1A for the receiver and TxRTS bit 5 in the MR2A for the transmitter 0 The OPO RTSA pin functions as a dedicated output The signal reflects the complement of the value of bit O of the OP 7 4 1 16 OUTPUT PORT DATA REGISTER OP The bits in the OP register are set by performing a bit set command writing to offset 71E and are cleared by performing a bit reset command writing to offset 71F This register can only be written when the serial module is enabled i e the STP bit in the MCR is cleared Bit Set OP 71E 7 6 5 4 3 2 1 0 os ors o om RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User NOTE OP bits 7 5 3 and 2 are not pinned out on the MC68340 thus changing these bits has no effect OP6 OP4 OP1 OPO Output Port Parallel Outputs 1 These bits can be set by writing a one to the bit position s at this address 0 These bits are not affected by writing a zero to this address Bit Reset OP 71F 7 6 5 4 3 2 1 0 om oe RESET 0 0 0 0 0 0 0 0 Write Only Supervisor User NOTE OP bits 7 5 3 and 2 are not pinned out on the MC68340 thus changing these bits has no effect OP6 OP4 OP1 OPO Output Port Parallel Outputs 1 These bits can be cleared by writing a one to the bit position s at this address 0 These bits are not affected by wr
417. nd the first timeout When this event occurs TOUTx transitions to a logic one The second timeout occurs after 2 1 periods allowing for the zero cycle resulting in TOUTx returning to a logic zero see Figure 8 7 The OUT bit in the SR reflects the level of TOUTx COUNTER CLOCK COUNTER 00 2 1 0 5 4 3 2 1 0 N2 1 TOUT ONDE NL 41 ENABLE TIMEOUT TIMEOUT MODEx Bits in Control Register 011 Preload 1 Register N1 2 Preload 2 Register N2 5 OCx bits in Control Register 01 Figure 8 7 Variable Width Single Shot Pulse Generator Mode If TGATE is negated when it is enabled TGE 1 the prescaler and counter are disabled Additionally the SR TG bit is set indicating that TGATE was negated The SR ON bit is cleared indicating that the timer is disabled If TGATE is reasserted the timer is re enabled and begins counting from the value attained when TGATE was negated The ON bit is set again If TGATE is not enabled TGE 0 TGATE has no effect on the operation of the timer In this case the counter would begin counting on the falling edge of the counter clock MOTOROLA MC68340 USER S MANUAL 8 11 immediately after the SWR and CPE bits in the CR are set The SR TG bit cannot be set At all times the TGL bit in the SR reflects the level of TGATE The width of the pulse generated on TOUTx the value in PREL2 can be changed while the counter is counting down from the value in PR
418. ndent Variable Entries X X Y Subroutine Instruction Low 768 s oo s s ea o xm 3 os T 9 3 1 The first column is the value passed to the subroutine the second column is the value expected by the table instruction and the third column is the result returned by the subroutine MOTOROLA MC68340 USER S MANUAL 5 33 The following value has been calculated for independent variable X 31 16 15 0 NOT USED 0 000000 0 10 1 1 1 1 0 1 Since X is an 8 bit value the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction The following results are obtained from the subroutine Table Entry Offset Dx 4 7 B 11 Interpolation Fraction Dx 0 3 D 13 Thus Y is calculated as follows Y 80 13 64 80 16 67 If the 8 bit value for X were used directly by the table instruction interpolation would be incorrectly performed between entries 0 and 1 Data must be shifted to the left four places before use LSL W 4 Dx The new range for X is 0 x X x 4096 however since a left shift fills the least significant digits of the word with zeros the interpolation fraction can only have one of 16 values After the shift operation Dx contains the following value 31 16 15 0 NOT USED 0 0001 0 1 1 1 1 0 1 0 0 0 0 Execution of the table instruct
419. nerator An external clock is connected to the X1 pin X2 is left floating 2 13 2 Serial External Clock Input SCLK This input can be used as the external clock input for channel A or channel B bypassing the baud rate generator 2 13 3 Receive Data RxDA RxDB These signals are the receiver serial data input for each channel Data received on this signal is sampled on the rising edge of the clock source with the least significant bit received first 2 13 4 Transmit Data TxDA TxDB These signals are the transmitter serial data output for each channel The output is held high mark condition when the transmitter is disabled idle or operating in the local loopback mode Data is shifted out on this signal at the falling edge of the clock source with the least significant bit transmitted first 2 13 5 Clear to Send CTSA CTSB These active low signals can be programmed as the clear to send inputs for each channel 2 13 6 Request to Send RTSA RTSB These active low signals can be programmed as request to send outputs or used as discrete outputs RTSB RTSA When used for this function these signals function as the request to send outputs OP1 OPO When used for this function these outputs are controlled by the value of bit 1 and bit respectively in the output port data registers 2 13 7 Transmitter Ready T RDYA This active low output can be programmed as the channel A transmitter ready status indicator o
420. ng an inexpensive 32 768 kHz watch crystal The 20 M resistor connected between the EXTAL and XTAL pins provides biasing for a faster oscillator startup time The crystal manufacturer s documentation should be consulted for specific recommendations on external component values MOTOROLA MC68340 USER S MANUAL 10 1 330 k 4 7 pF XTAL MC68340 20M 32768kHz 10 pF ue EXTAL Figure 10 2 Sample Crystal Circuit The circuit shown in Figure 10 3 is the typical circuit recommended by Statek Corporation for 32768 kHz crystal part number CX IV It is recommended to start with these values but parameter values may need to be adjusted to compensate for variables in layout XTAL MC 68340 22M 32768kHz 4 EXTAL Figure 10 3 Statek Corporation Crystal Circuit A separate power pin Vccsyn is used to allow the clock circuits to operate with the rest of the device powered down and to provide increased noise immunity for the clock circuits The source for Vccsyn should be a quiet power supply and external bypass capacitors see Figure 10 4 should be placed as close as possible to the Vccsyn pin to ensure a stable operating frequency Additionally the PLL requires that an external low leakage filter capacitor typically in the range of 0 01 to 0 1 uF be connected between the XFC and Vccsyn pins The XFC capacitor should provide 50 MQ insulation but should not be electrolytic For external clock m
421. ng down the 2 and other IMB modules greatly reducing power consumption Ease of programming is an important consideration when using an integrated processor The CPU32 instruction format reflects predominate register memory interaction philosophy All data resources are available to all operations that require them The programming model includes eight multifunction data registers and seven general purpose addressing registers The data registers readily support 8 bit byte 16 bit word and 32 bit long word operand lengths for all operations Address manipulation is supported by word and long word operations Although the program counter PC and stack pointers SP are special purpose registers they are also available for most data addressing activities Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level As processor applications become more complex and programs become larger high level language HLL will become the system designer s choice in programming languages HLL aids in the rapid development of complex algorithms with less error and is readily portable The CPUS2 instruction set will efficiently support HLL MOTOROLA MC68340 USER S MANUAL 5 1 5 1 1 Features Features of the CPU32 are as follows Fully Upward Object Code Compatible with M68000 Family Virtual Memory Implementation Loop Mode of Instruction Execution Fast Multiply Divide and Shift Instructi
422. ng is also checked but stop bits are transmitted as received A received break is echoed as received until the next valid start bit is detected 7 3 3 2 LOCAL LOOPBACK MODE In this mode TxDx is internally connected to RxDx This mode is useful for testing the operation of a local serial module channel by sending data to the transmitter and checking data assembled by the receiver In this manner correct channel operations can be assured Also both transmitter and CPUS2 to receiver communications continue normally in this mode While in this mode the RxDx input data is ignored the TxDx is held marking and the receiver is clocked by the transmitter clock The transmitter must be enabled but the receiver need not be enabled 7 3 3 3 REMOTE LOOPBACK MODE In this mode the channel automatically transmits received data on the TxDx output on a bit by bit basis The local CPUS2 to transmitter link is disabled This mode is useful in testing receiver and transmitter operation of a remote channel While in this mode the receiver clock is used for the transmitter Since the receiver is not active received data cannot be read by the CPU32 and the error status conditions are inactive Received parity is not checked and is not recalculated for transmission Stop bits are transmitted as received A received break is echoed as received until the next valid start bit is detected 7 14 MC68340 USER S MANUAL MOTOROLA RxDx INPUT CPU DISABLE
423. no effect on the transmitter RTS 7 38 MC68340 USER S MANUAL MOTOROLA TxCTS Transmitter Clear to Send 1 Enables clear to send operation The transmitter checks the state of the CTS input each time it is ready to send a character If CTS is asserted the character is transmitted If CTS is negated the channel TxDx remains in the high state and the transmission is delayed until CTS is asserted Changes in CTS while a character is being transmitted do not affect transmission of that character If both TxCTS and TxRTS are enabled TxCTS controls the operation of the transmitter 0 The CTS has no effect on the transmitter SBS3 SBO0 Stop Bit Length Control These bits select the length of the stop bit appended to the transmitted character as listed in Table 7 10 Stop bit lengths of nine sixteenth to two bits in increments of one sixteenth bit are programmable for character lengths of six seven and eight bits For a character length of five bits one and one sixteenth to two bits are programmable in increments of one sixteenth bit In all cases the receiver only checks for a high condition at the center of the first stop bit position i e one bit time after the last data bit or after the parity bit if parity is enabled If an external 1x clock is used for the transmitter MR2 bit 3 0 selects one stop bit and MR2 bit 3 1 selects two stop bits for transmission Table 7 10 SBx Control Bits _5 2_ EM o EE I
424. no read cycle The tail and cycle time are reduced by the amount of time the read would occupy The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Teil Cycles Notes 77778 RE me E 2 o fao ov sAnXnSzxS ordgPOXnSzxSO 254 2 e 4 __ 4 0 Jem 24 4 0 24 i zeros o d 16 An Xm Sz x Sc or dig PC Xm Sz x So 2 o eo 234 dap An Xm Sz x So or dag PC Xm Sz x Sc X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles NOTES Replacement fetches overlap the head of the operation by the amount specified in the tail Size and scale of the index register do not affect execution time The PC may be substituted for the base address register An When adjusting the prefetch time for slower buses extra clocks may be subtracted from the head until the head reaches zero at which time additional clocks must be added to both the tail and cycle counts 5 100 MC68340 USER S MANUAL MOTOROLA 5 7 3 3 MOVE INSTRUCTION The MOVE instruction table
425. ns 5 46 5 47 Internal Autovector 3 4 3 29 4 23 4 36 Bus Arbitration 6 18 Bus Masters 4 6 6 25 Bus Monitor 3 4 3 32 4 4 4 6 4 17 Data Multiplexer 3 7 DMA Request 6 2 6 4 6 5 DSACK signals 3 5 3 13 3 14 3 28 4 2 4 4 4 14 4 15 4 32 Exceptions 5 66 Interrupt Acknowledge Arbitration 4 6 6 25 6 26 7 17 Acknowledge Cycle Types 3 27 Autovector 3 29 Autovector Timing 3 31 Flowchart 3 28 Terminated Normally 3 27 4 7 Timing 3 29 Acknowledge Cycle 3 27 Acknowledge Signals 3 29 Arbitration 4 5 4 6 7 21 Enable Register 7 4 7 34 7 46 Exception 5 68 5 69 Level Register 7 21 7 46 Register 6 26 8 20 8 27 Request Signals 2 5 2 6 3 27 3 28 6 26 7 3 7 21 7 34 8 4 8 8 8 9 8 20 Status Register 7 4 7 22 7 32 7 34 7 46 Vector Register 7 4 7 17 7 21 7 46 INTL Bits 6 26 6 36 INTN Bit 6 27 6 36 Bits 6 26 6 36 IPIPE Signal 5 87 5 88 5 64 5 68 5 69 IRQ Bit 6 20 6 31 8 23 ISM Bits 6 25 6 36 IVR Bits 7 22 8 20 8 27 MOTOROLA JTAG 4 2 Late Bus Error 3 34 LG Bit 5 56 5 57 Limp Mode 4 19 4 29 Local Loopback Mode 7 14 7 38 Location of Modules 4 2 4 3 4 20 Logical Instructions 4 48 Long Word Read 8 Bit Port Timing 3 11 16 Bit Port Timing 3 13 Write 8 Bit Port Timing 3 12 16 Bit Port Timing 3 13 Looping Modes 7 14 7 15 Loss of Input Signal 4 9 4 11 4 29 Low Power Stop Mode 3 23 4 13 4 17 4 29 10 12 Low Voltage 10 10 10
426. nsfers 6 5 6 6 Cycle Termination 3 1 DAPI Bits 6 19 6 28 6 37 Data Bus Signals 2 4 3 2 3 16 Holding Register 6 12 6 15 Misalignment 5 45 5 46 Movement Instructions 5 21 Port Organization 3 5 3 7 Registers 5 10 Strobe Signal 2 7 3 4 3 17 3 21 3 44 3 46 4 22 Transfer and Size Acknowledge Signals 2 6 3 5 3 8 3 15 3 17 3 23 3 28 3 30 3 32 3 36 4 2 4 4 4 6 4 14 4 15 4 32 Transfer Capabilities 3 5 3 8 3 15 Bit 7 33 7 35 DBB Bit 7 33 7 34 DBcc Instruction 5 3 MOTOROLA DBF Bit 4 6 4 23 DBFE Bit 4 6 4 25 4 37 DD Bits 4 14 4 17 4 32 Destination Address Register 6 15 6 18 6 19 6 28 6 33 6 34 6 37 6 38 Deterministic Opcode Tracking 5 64 5 87 5 88 DFC Bits 6 32 Differences between 68020 Instruction Set and MC68340 Instruction Set 5 5 DIV Instructions DMA Acknowledge Signals 2 10 6 4 6 7 6 10 6 12 6 15 Capabilities 6 1 Channel Initialization 6 18 6 19 6 36 Operation Sequence 6 18 6 21 Termination 6 18 6 20 6 21 Done Signals 2 10 6 4 6 7 6 10 6 12 6 15 Programming Model 6 23 Programming Sequence 6 18 Request Signals 2 10 6 4 6 7 6 18 6 19 6 21 Timing Single Address Read External Burst 6 8 Single Address Read Cycle Steal 6 9 Single Address Write External Burst 6 10 Single Address Write Cycle Steal 6 11 Dual Address Read External Burst Source Requesting 6 13 Dual Address Read Cycle Steal Source Requesting
427. nsists of the following major areas A General Purpose Counter Timer Internal Control Logic Interrupt Control Logic TIMER 1 TIMER 2 TIMER 1 TIMER 2 INTERRUPT INTERRUPT CONTROL CONTROL LOGIC LOGIC IMB IMB INTERFACE INTERFACE Figure 8 1 Simplified Block Diagram 8 1 MODULE OVERVIEW Each timer module consists of the following functional features Versatile General Purpose Timer 8 Bit Prescaler 16 Bit Counter Timers Can Be Externally Cascaded for a Maximum Count Width of 48 Bits Programmable Timer Modes nput Capture Output Compare Square Wave Generation Variable Duty Cycle Square Wave Generation Variable Width Single Shot Pulse Generation MOTOROLA MC68340 USER S MANUAL 8 1 Pulse Width Measurement Period Measurement Event Counting e Seven Maskable Interrupt Conditions Based on Programmable Events 8 1 1 Timer and Counter Functions The term timer is used to reference either timer 1 or timer 2 since the two are functionally equivalent The timer can perform virtually any application traditionally assigned to timers and counters The timer can be used to generate timed events that are independent of the timing errors to which real time programmed microprocessors are susceptible for example those of dynamic memory refreshing DMA cycle steals and interrupt servicing The timer has several functional areas an 8 bit countdown prescaler a 16 bit downcounter timeout logi
428. nter counts down to the value stored in the COM register the COM and TC bits in the SR are set If the counter counts down to 0000 a timeout is detected This sets the SR TO bit and clears the SR COM bit At timeout the next falling edge of the counter clock reloads the counter with FFFF TOUTx transitions at timeout or is disabled as programmed by the OCx bits of the CR and the OUT bit in the SR reflects the level on TOUTx To determine the number of cycles counted the value in the CNTR must be read inverted and incremented by 1 the first count is FFFF which in effect includes a count of zero The counter counts in a true 216 fashion For measuring pulses of even greater duration the value in the POx bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR NOTE Once the timer has been enabled do not clear the SR TG bit until the pulse has been measured and TGATE has been negated 8 3 7 Event Count This mode is used to count events by interpreting the falling edges of the counter clock as events see Figure 8 10 These events may be external or internal to the chip for example counting the number of system clock cycles required to execute a sequence of instructions As another example by connecting AS to TINx the number of bus cycles to complete a sequence of instructions could be counted This mode can be selected by programming the CR MODEx bits to 110 8 14 MC68340
429. nterrupts has an interrupt level field The interrupt level field contains the priority level of the interrupt for its associated channel The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQ signal The CPU32 uses this value to determine servicing priority See Section 5 CPU32 for more information INTV Interrupt Vector Bits Each module that can generate interrupts has an interrupt vector field The interrupt vector field contains the vector number of the interrupt for its associated channel This 8 bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located The INTV field is reset to 0F which indicates an uninitialized interrupt condition See Section 5 CPU32 for more information 6 7 3 Channel Control Register CCR The CCR controls the configuration of the DMA channel This register is accessible in either supervisor or user space The CCR can always be read or written to when the DMA module is enabled i e the STP bit in the MCR is cleared 6 26 MC68340 USER S MANUAL MOTOROLA CCR1 CCR2 788 7A8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET U U U U U U U U U U U U U U U 0 U Unaffected by reset Supervisor User INTB Interrupt Breakpoint Setting the interrupt breakpoint bit sets the BRKP bit in the CSR The logic AND of INTB and BRKP generates an interrupt request 1 Enables an IRQ when a brea
430. ny exception Reset is used for system initialization and for recovery from catastrophic failure The reset exception aborts any processing in progress when it is recognized and that processing cannot be recovered Reset performs the following operations 1 Clears TO and T1 in the to disable tracing Sets the S bit in the SR to establish supervisor privilege Sets the interrupt priority mask to the highest priority level 96111 Initializes the VBR to zero 00000000 Generates a vector number to reference the reset exception vector Loads the first long word of the vector into the interrupt SP Loads the second long word of the vector into the PC Fetches and initiates decode of the first instruction to be executed a uix OI Ol Figure 5 11 is a flowchart of the reset exception After initial instruction prefetches normal program execution begins at the address in the PC The reset exception does not save the value of either the PC or the SR If a bus error or address error occurs during reset exception processing sequence a double bus fault occurs the processor halts and the HALT signal is asserted to indicate the halted condition Execution of the RESET instruction does not cause a reset exception nor does it affect any internal CPU register The SIMAO registers and the MCR in each internal peripheral module DMA timers and serial modules are not affected All other internal peripheral module registers are reset the sa
431. o initiates instruction word prefetches after a change of flow and controls validation of instruction words in the instruction pipeline 5 7 1 2 INSTRUCTION PIPELINE The 2 contains a two word instruction pipeline where instruction opcodes are decoded Each stage of the pipeline is initially filled under microsequencer control and subsequently refilled by the prefetch controller as it empties Stage A of the instruction pipeline is a buffer Prefetches completed on the bus before stage B empties are temporarily stored in this buffer Instruction words instruction operation words and all extension words are decoded at stage B Residual decoding and execution occur in stage C Each pipeline stage has an associated status bit that shows whether the word in that stage was loaded with data from a bus cycle that terminated abnormally 5 7 1 3 BUS CONTROLLER RESOURCES The bus controller consists of the instruction prefetch controller the write pending buffer and the microbus controller These three resources transact all reads writes and instruction prefetches required for instruction execution MOTOROLA MC68340 USER S MANUAL 5 89 The bus controller and microsequencer operate concurrently The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls EA calculation or sets condition codes The microsequencer can also request a bus cycle that the bus controller cannot perform immediately When
432. o the data byte three status bits PE FE and RB are appended to each data character in the FIFO OE is not appended By programming the ERR bit in the channel s mode register MR1 status is provided in character or block modes The RxRDY bit in the SR is set whenever one or more characters are available to be read by the CPU32 A read of the receiver buffer produces an output of data from the top of the FIFO stack After the read cycle the data at the top of the FIFO stack and its associated status bits are popped and new data can be added at the bottom of the stack by the receiver shift register The FIFO full status bit FFULL is set if all three stack positions are filled with data Either the RxRDY or FFULL bit can be selected to cause an interrupt In the character mode status provided in the SR is given on a character by character basis and thus applies only to the character at the top of the FIFO In the block mode the status provided in the SR is the logical OR of all characters coming to the top of the FIFO stack since the last reset error command A continuous logical OR function of the corresponding status bits is produced in the SR as each character reaches the top of the FIFO stack The block mode is useful in applications where the software overhead of checking each character s error cannot be tolerated In this mode entire messages are received and only one data integrity check is performed at the end of the message This mod
433. o wait states The timer responds to byte word and long word writes Write cycles to read only registers and bits as well as reserved registers complete in a normal manner without exception processing however the data is ignored 8 3 9 3 INTERRUPT ACKNOWLEDGE CYCLES The timer is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration The vector number must be provided if interrupt servicing is necessary thus the interrupt register IR must be initialized If the IR is not initialized a spurious interrupt exception will be taken if interrupt servicing is necessary 8 4 REGISTER DESCRIPTION The following paragraphs contain a detailed description of each register and its specific function The operation of the timer is controlled by writing control words into the appropriate registers Timer registers and their associated addresses are listed in Figure 8 11 For more information about a particular register refer to the individual register description The ADDR column indicates the offset of the register from the base address of the timer An FC column designation of S indicates that register access is restricted to supervisor only A designation of S U indicates that access is governed by the SUPV bit in the module configuration register MCR MOTOROLA MC68340 USER S MANUAL 8 17 TIMER 1 TIMER 2 FC 15 0 mo s so sU sso
434. ode without PLL the XFC pin can be left open Smaller values of the external filter capacitor provide a faster response time for the PLL and larger values provide greater frequency stability Figure 10 4 depicts examples of both an external filter capacitor and bypass capacitors for V ccsvN 10 2 MC68340 USER S MANUAL MOTOROLA VCCSYN VCCSYN MC68340 0101 010 001yF NOTE 1 Must be low leakage capacitor Figure 10 4 XFC and Vccsyn Capacitor Connections 10 1 2 Reset Circuitry Because it is optional reset circuitry is not shown in Figure 10 1 The MC68340 holds itself in reset after power up and asserts RESET to the rest of the system If an external reset pushbutton switch is desired an external reset circuit is easily constructed by using open collector cross coupled NAND gates to debounce the output from the switch 10 1 3 SRAM Interface The SRAM interface is very simple when the programmable chip selects are used External circuitry to decode address information and circuitry to return data and size acknowledge DSACK is not required However external ICs are required to provide write enables for the high and low bytes of data A15 A1 5170 A0 AS MC68340 01500 Figure 10 5 SRAM Interface The SRAM interface shown in Figure 10 5 is a two clock interface at 16 78 MHz operating frequency The MCM6206C 35 memories provide an access time
435. old times for TINx Refer to Section 11 Electrical Characteristics for additional information 8 2 2 Timer Gate TGATE1 TGATE2 This active low input can be programmed to enable and disable the counter and prescaler TGATE may also be programmed to be a simple input For more information on the modes of operation refer to 8 3 OPERATING MODES To guarantee that the timer recognizes a valid level on TGATEzs the signal is synchronized with the system clock Additionally the high and low levels of this input must each be stable for at least one system clock period plus the sum of the setup and hold times for TGATE Refer to Section 11 Electrical Characteristics for additional information 8 2 3 Timer Output TOUT1 TOUT2 This output drives the various output waveforms generated by the timer The initial level and transitions can be programmed by the output control OC bits in the CR 8 3 OPERATING MODES The following paragraphs contain a detailed description of each timer operation mode and of the IMB operation during accesses to the timer Changing the contents of the CR should only be attempted when the timer is disabled the software reset SWR bit in the CR is cleared Changing the CR while the timer is running may produce unpredictable results 8 3 1 Input Capture Output Compare This mode has the capability of capturing a counter value by holding the value in the counter register CNTR Additionally this mode can provide com
436. om an exception 2 9 1 Reset RESET This active low open drain bidirectional signal is used to initiate a system reset An external reset signal as well as a reset from the SIM40 resets the MC68340 and all external devices A reset signal from the CPU32 asserted as part of the RESET instruction resets external devices the internal state of the CPU32 is not affected The on chip modules are reset except for the 51 40 However the module configuration register for each on chip module is not altered When asserted by the MC68340 this signal is guaranteed to be asserted for a minimum of 512 clock cycles Refer to Section 3 Bus Operation for a description of bus reset operation and Section 5 CPU32 for information about the reset exception 2 9 2 Halt HALT This active low open drain bidirectional signal is asserted to suspend external bus activity to request a retry when used with BERH or to perform a single step operation As an output HALT indicates a double bus fault by the CPUS2 Refer to Section 3 Bus Operation for a description of the effects of HALT on bus operation 2 9 3 Bus Error BERR This active low input signal indicates that an invalid bus operation is being attempted or when used with HALT that the processor should retry the current cycle Refer to Section 3 Bus Operation for a description of the effects of BERR on bus operation 2 10 CLOCK SIGNALS These signals are used by the MC68340 for controlling or gene
437. on An An 8 16 32 TBLS TBLU 8 16 32 Dyn Dym Temp Dym Dyn Dn Temp x Dn 7 0 Temp Dym x 256 Temp Dn TBLSN TBLUN Dn 8 16 32 Dyn Dym Temp Dym Dyn Dn Temp x Dn 7 0 256 Temp Dym Temp Dn MOTOROLA MC68340 USER S MANUAL 5 23 5 3 3 4 LOGIC INSTRUCTIONS The logical operation instructions AND OR EOR and NOT perform logical operations with all sizes of integer data operands A similar set of immediate instructions ANDI ORI and EORI provide these logical operations with all sizes of immediate data The test TST instruction arithmetically compares the operand with zero placing the result in the CCR Table 5 6 summarizes the logical operations Table 5 6 Logic Operations Operand Syntax Operand Size Operation ea Dn 8 16 32 Source A Destination Destination Dn 8 16 32 data ea 8 16 32 Immediate Data A Destination Destination 8 16 32 Source Destination Destination data ea 8 16 32 Immediate Data Destination Destination 81632 Destination Destination data ea 8 16 32 Immediate Data V Destination Destination 5 3 3 5 SHIFT AND ROTATE INSTRUCTIONS The arithmetic shift instructions ASR and ASL and logical shift instructions LSR and LSL provide shift operations in both directions The ROR ROL ROXR and ROXL instructions perform rotate circular shift operations with and without the extend bit All shi
438. on is used to enhance test efficiency when a component other than the MC68340 becomes the device under test SHIFT DR 0 FROM TDI TO TDO CLOCK DR Figure 9 9 Bypass Register When the bypass register is selected by the current instruction the shift register stage is set to a logic zero on the rising edge of TCK in the capture DR controller state Therefore the first bit to be shifted out after selecting the bypass register will always be a logic zero 9 4 4 HI Z 100 The HI Z instruction is not included in the IEEE 1149 1 standard It is provided as a manufacturer s optional public instruction to prevent having to backdrive the output pins during circuit board testing When HI Z is invoked all output drivers including the two state drivers are turned off i e high impedance The instruction selects the bypass register 9 5 MC68340 RESTRICTIONS The control afforded by the output enable signals using the boundary scan register and the EXTEST instruction requires a compatible circuit board test environment to avoid device destructive configurations The user must avoid situations in which the MC68340 output drivers are enabled into actively driven networks Overdriving the TDO driver when itis active is not recommended MOTOROLA MC68340 USER S MANUAL 9 11 The MC68340 includes on chip circuitry to detect the initial application of power to the device Power on reset POR the output of this circuitry is used to reset both
439. on of the transfer MOTOROLA MC68340 USER S MANUAL 6 27 Dual Address Mode This bit defines which device generates requests 1 If request generation is programmed to be external REQ 1x the source device generates the request and the control signals DREQ DACK and DONE are part of the source read portion of the transfer 0 If request generation is programmed to be external REQ 1x the destination device generates the request and the control signals DREQ DACK and DONE are part of the destination write portion of the transfer SAPI Source Address Pointer Increment 1 The SAR is incremented by 1 2 or 4 after each transfer according to the source size The address that is written into the SAR points to a memory block and is incremented to complete the data transfer The SAR is not incremented during operand transfer The address that is written into the SAR points to a peripheral device and is used for the complete data transfer DAPI Destination Address Pointer Increment 1 The DAR is incremented by 1 2 or 4 after each transfer according to the source size The address that is written into the DAR points to a memory block and is incremented to complete the data transfer 0 The DAR is not incremented during operand transfer The address that is written into the DAR points to a peripheral device and is used for the complete data transfer SSIZE Source Size Control Field This field controls th
440. on the operation of the timer thus the input capture function is inoperative At all times the TGATE level bit TGL in the SR reflects the level of the TGATE signal COUNTER CLOCK COUNTER 0 00 8 8 7 7 6 6 5 5 4 43 3 2 2 1 10 0 8 8 7 7 COUNTER 00008 8 7 7 6 6 6 6 6 6 63 2 2 11 0 0 8 8 8 REGISTER T TGATE 5 y M y TG SET TG CLEARED TG SET TOUT ENABLE TC SET TIMEOUT TC SET Modex Bits in Control Register 000 Preload 1 Register 8 Compare Register 7 TGE Bit of Status Register 1 TG Bit in Status Register Initially 0 OCx Bits in Control Register 10 Figure 8 4 Input Capture Output Compare Mode Since the counter is not affected by TGATE it continues to decrement on the falling edge of the counter clock and load from the PREL1 at timeout regardless of the value of TGATE When the counter counts down to the value contained in the COM this condition is reflected by setting the timer compare TC and compare COM bits in the SR TOUTx responds as selected by the OCx bits in the CR The output level OUT bit in the SR reflects the value on TOUTx Shadowing does not affect this operation If the counter counts down to 0000 a timeout is detected causing the SR timeout interrupt TO bit to be set and the SR COM bit to be cleared On the next falling edge of the counter clock after the timeout is detected the value in PREL1 is again loaded into th
441. onal Model of Instruction Pipeline MOTOROLA MC68340 USER S MANUAL 587 Assertion of IPIPE for a single clock cycle indicates the use of data from IRB Regardless of the presence of valid data in IRA the contents of IRB are invalidated when IPIPE is asserted If IRA contains valid data the data is copied into IRB IRA IRB and the IRB stage is revalidated Assertion of IPIPE for two clock cycles indicates the start of a new instruction and subsequent replacement of data in IRC This action causes a full advance of the pipeline IRB IRC and IRA IRB IRA is refilled during the next instruction fetch bus cycle Data loaded into IRA propagates automatically through subsequent empty pipeline stages Signals that show the progress of instructions through IRB and IRC are necessary to accurately monitor pipeline operation These signals are provided by IRA and IRB validity bits When a pipeline advance occurs the validity bit of the stage being loaded is set and the validity bit of the stage supplying the data is negated Because instruction execution is not timed to bus activity IPIPE is synchronized with the system clock not the bus Figure 5 29 illustrates the timing in relation to the system clock IR IR lt IR gt IR gt lt IRB gt IRC 3 RR aH ae cc PT EXTENSION INSTRUCTION EXTENSION INSTRUCTION WORD USED START WORD USED START Figure 5 29 Instruction Pipeline Timing Diagram IPIPE should be sampled on the
442. onous protocol similar to the serial peripheral interface SPI protocol The development system serves as the master of the serial link since it is responsible for the generation of DSCLK If DSCLK is derived from the CPU32 system clock development system serial logic is unhindered by the operating frequency of the target processor Operable frequency range of the serial clock is from DC to one half the processor system clock frequency The serial interface operates in full duplex mode i e data is transmitted and received simultaneously by both master and slave devices In general data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK Data is transmitted MSB first and is latched on the rising edge of DSCLK The serial data word is 17 bits wide 16 data bits and a status control S C bit 16 15 0 S C DATA FIELD Bit 16 indicates the status of CPU generated messages as shown in Table 5 21 Table 5 21 CPU Generated Message Encoding Encoding Data Message Type Command Complete Status 0000 Not Ready with Response Come Again 0001 BERR Terminated Bus Cycle Data Invalid FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16 The current implementation ignores this bit however Motorola reserves the right to use this bit for future enhancements 5 6 2 7 1 CPU Serial Logi
443. ons Fast Bus Interface with Dynamic Bus Port Sizing Improved Exception Handling for Embedded Control Applications Additional Addressing Modes Scaled Index Address Register Indirect with Base Displacement and Index Expanded PC Relative Modes 32 Bit Branch Displacements Instruction Set Additions High Precision Multiply and Divide Trap On Condition Codes Upper and Lower Bounds Checking Enhanced Breakpoint Instruction Trace on Change of Flow Table Lookup and Interpolate Instruction LPSTOP Instruction Hardware BKPT Signal Background Mode Fully Static Implementation A block diagram of the CPU32 is shown in Figure 5 1 The major blocks depicted operate in a highly independent fashion that maximizes concurrences of operation while managing the essential synchronization of instruction execution and bus operation The bus controller loads instructions from the data bus into the decode unit The sequencer and control unit provide overall chip control managing the internal buses registers and functions of the execution unit 5 1 2 Virtual Memory A system that supports virtual memory has a limited amount of high speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device When the processor attempts to access a location in the virtual memory map that is not resident in physical memory a page fault occurs The acces
444. ontain the interrupt service mask level for the channel When the interrupt service level on the IMB is greater than the interrupt service mask level the DMA vacates the bus and negates BH until the interrupt service level is less than or equal to the interrupt service mask level NOTE When the CPU32 status register SR interrupt priority mask bits 12 10 are at a higher level than the DMA ISM bits the DMA channel will not start The channel will begin operation when the level of the SR 12 10 bits is less than or equal to the level of the DMA ISM bits SUPV Supervisor User The value of this bit has no effect on registers permanently defined as supervisor only access 1 The DMA channel registers defined as supervisor user reside in supervisor data space and are only accessible from supervisor programs 0 channel registers defined as supervisor user reside in user data space and are accessible from either supervisor or user programs MAID Master Arbitration ID These bits establish bus arbitration priority level among modules that have the capability of becoming bus master For the MC68340 the MAID bits are used to arbitrate between DMA channel 1 and channel 2 If both channels are programmed with the same MAID level channel 1 will have priority These bits are implemented for future MC683xx Family compatibility In the MC68340 only the SIM and the DMA can be bus masters However future versions of the MC683xx
445. or request to be recognized 2 To cause another DMA transfer DREQx is asserted after DACKx is asserted and before DACKx is negated 3 DACKx and DONEx DMA control signals are asserted in the destination write DMA cycle 50 DMA WRITE S2 54 Figure 6 8 Single Address Write Timing Cycle Steal 6 4 2 Dual Address Mode The dual address DMA bus cycle transfers data between a device or memory and the DMA internal holding register DHR In this mode any operand transfer takes place in two DMA bus cycles one where a device is addressed and one where memory is addressed The data transferred during a dual address operation is either read from the data bus into the DHR or written from the DHR to the data bus Each DMA channel can each be programmed to operate in the dual address transfer mode In this mode the operand is read from the source address specified in the SAR and placed in the DHR The operand read may take up to four bus cycles to complete because of differences in operand sizes of the source and destination The operand is then written to the address specified in the DAR This transfer may also be up to four bus cycles long In this manner various combinations of peripheral memory and operand sizes may be used See 6 7 Register Description for more information The dual address transfers can be started by either the internal request mode or by an external device using the DREQ input signal
446. or all the following operations Data Movement Arithmetic Operations Logical Operations Shifts and Rotates Bit Manipulation Conditionals and Branches System Control The large instruction set encompasses a complete range of capabilities and combined with the enhanced addressing modes provides a flexible base for program development 5 3 1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user mode programs can execute unchanged on a more advanced processor and that supervisor mode programs and exception handlers should require only minimal alteration The CPU32 can be thought of as an intermediate member of the M68000 family Object code from an MC68000 or MC68010 may be executed on the CPU32 and many of the instruction and addressing mode extensions of the MC68020 are also supported 5 3 1 1 NEW INSTRUCTIONS Two instructions have been added to the M68000 instruction set for use in embedded control applications LPSTOP and table lookup and interpolation TBL 5 3 1 1 1 Low Power Stop LPSTOP In applications where power consumption is a consideration the CPU32 can force the device into a low power standby mode when immediate processing is not required The low power mode is entered by executing the LPSTOP instruction The processor remains in this mode until a user specified or higher level interrupt or a reset occurs MOTOROLA MC68340 USER S MANUAL 5 11 5 3 1 1 2 Table Lookup and Interpola
447. or an empty FIFO position When this occurs the character in the receiver shift register and its break detect framing error status and parity error if any are lost This bit is cleared by the reset error status command in the CR 0 No overrun has occurred TxEMP Transmitter Empty 1 The channel transmitter has underrun both the transmitter holding register and transmitter shift registers are empty This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission 0 The transmitter buffer is not empty The transmitter holding register is loaded by the CPU32 or the transmitter is disabled The transmitter is enabled disabled by programming the bits in the CR TxRDY Transmitter Ready This bit is duplicated in the ISR bit 0 for channel A and bit 4 for channel B 1 The transmitter holding register is empty and ready to be loaded with a character This bit is set when the character is transferred to the transmitter shift register This bit is also set when the transmitter is first enabled Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted and are lost 0 The transmitter holding register was loaded by the CPU32 or the transmitter is disabled FFULL FIFO Full 1 Acharacter was transferred from the receiver shift register to the receiver FIFO and the transfer caused
448. or memory The bit number is specified as immediate data or in a data register Register operands are 32 bits long and memory operands are 8 bits long Table 5 8 is a summary of bit manipulation instructions Table 5 8 Bit Manipulation Operations Operand Syntax Operand Size Operation BCHG Dn ea 8 32 bit number of destination Z bit of data ea 8 32 destination BCLR Dn ea 8 32 bit number of destination 2 Z 0 bit of data ea 8 32 destination BSET Dn ea 8 32 bit number of destination 2 Z 1 bit of data ea 8 32 destination BTST Dn ea 8 32 bit number of destination 2 Z data ea 8 32 MOTOROLA MC68340 USER S MANUAL 5 25 5 3 3 7 BINARY CODED DECIMAL BCD INSTRUCTIONS Five instructions support operations on BCD numbers The arithmetic operations on packed BCD numbers are add decimal with extend ABCD subtract decimal with extend SBCD and negate decimal with extend NBCD Table 5 9 is a summary of the BCD operations Table 5 9 Binary Coded Decimal Operations Operand Syntax Operand Size Operation ABCD Dn Dn Source Destination X Destination x An Destination49 Source10 X Destination 8 An 8 NBCD 0 Destinationjg X Destination 8 SBCD Dn Dn 8 An 8 5 3 3 8 PROGRAM CONTROL INSTRUCTIONS A set of subroutine call and return instructions and conditional and unconditional branch instructions perf
449. ore timing information Table 10 1 Memory Access Times at 16 78 MHz AccessTime N 2 N 3 N 4 5 N 6 The values can be used to determine how many clock cycles an access will take given the access time of the memory devices and any delays through buffers or external logic that may be needed 10 2 3 Calculating Frequency Adjusted Output The general relationship between the CLKOUT and most input and output signals is shown in Figure 10 11 Most outputs transition off of a falling edge of CLKOUT but the same principle applies to those outputs that transition off of a rising edge CLKOUT f lx ty OUTPUTS tsu ASYNCHRONOUS INPUTS Figure 10 11 Signal Relationships to CLKOUT For outputs that are referenced to a clock edge the propagation delay tg does not change as the frequency changes For instance specification 6 in the electrical characteristics shown in Section 11 Electrical Characteristics shows that address function code and size information is valid 3 to 30 ns after the rising edge of SO This specification does not change even if the device frequency is less than 16 78 MHz MOTOROLA MC68340 USER S MANUAL 10 7 Additionally the relationship between the asynchronous inputs and the clock edge as shown in Figure 10 11 does not change as frequency changes A second type of specification indicates the minimum amount of time a signal will be asserted This type of specification i
450. orm program control operations Table 5 10 summarizes these instructions Table 5 10 Program Control Operations Operand Syntax Operand Size Operation Bcc label 8 16 32 If condition true then PC d PC Dn label 16 If condition false then Dn 1 PC if Dn z 1 then PC d gt PC Scc ea If condition true then destination bits are set to 1 else destination bits are cleared to 0 Unconditional label 8 16 32 PC d PC label 8 16 32 SP 4 SP PC SP PC d PC Destination SP 4 SP PC SP destination PC POT ZOPO SP PC SP 4 d gt SP SP CCR SP 2 SP SP PC SP 4 gt SP SP PC SP 4 gt SP 5 26 MC68340 USER S MANUAL MOTOROLA To specify conditions for change in program control condition codes must be substituted for the letters cc in conditional program control opcodes Condition test mnemonics are given below Refer to 5 3 3 10 Condition Tests for detailed information on condition codes CC CS EQ F GT LE Carry clear Carry set Equal False Greater or equal Greater than High Less or equal S pr MI NE PL VC VS Not applicable to the Bcc instruction Low or same Less than Minus Not equal Plus True Overflow clear Overflow set 5 3 3 9 SYSTEM CONTROL INSTRUCTIONS Privileged instructions trapping instructions and instructions that use or
451. ound or Rn upper bound then CHK exception ILLEGAL none none SSP 2 SSP vector offset SSP SSP 4 gt SSP PC SSP SSP 2 gt SSP SR SSP llegal instruction vector address PC TRAP data SSP 2 SSP format vector offset SSP SSP 4 SSP PC SSP SR SSP vector address PC TRAPcc none none If cc true then TRAP exception data 16 32 TRAPV none If V set then overflow TRAP exception Condition Code Register ANDI data CCR Immediate Data A CCR CCR EORI data CCR i Immediate Data CCR CCR MOVE ea CCR CCR ea Source CCR CCR Destination CCR Immediate Data V CCR CCR 16 16 16 16 2 2 2 2 6 6 16 16 5 28 MC68340 USER S MANUAL MOTOROLA 5 3 3 10 CONDITION TESTS Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tests A condition test is the evaluation of a logical expression related to the state of the CCR bits If the result is 1 the condition is true If the result is 0 the condition is false For example the T condition is always true and the EQ condition is true only if the Z bit condition code is true Table 5 12 lists each condition test Table 5 12 Condition Tests conaiion Encoding 0000 Mnemonic portu GEM CENE O W 2 __ Oc CamyCea oo pS Case 00 NE NeEqal 009 Oo ooe O NS d O M O E
452. pare information via TOUTx to indicate when the counter has reached the compare value This mode be used for square wave generation pulse width modulation or periodic interrupt generation This mode can be selected by programming the operation mode bits MODEx in the CR to 000 The timer is enabled when the counter prescaler enable CPE and SWRx bits in the CR are set Once enabled the counter enable ON bit in the SR is set and the next falling edge of the counter clock causes the counter to be loaded with the value in the preload 1 register PREL1 The TGATE signal functions differently in this mode than it does in the other modes TGATE does not enable or disable the counter prescaler input clock instead it is used to disable shadowing Normally the counter is decremented on the falling edge of the counter clock and the CNTR is updated on the next rising edge of the system clock thus the CNTR shadows the actual value of the counter The timer gate interrupt TG bit in the SR must be cleared for shadowing to occur TGATE is used to set the TG bit and disable shadowing If the timing gate is enabled TGE bit of the CR is set the TG bit is set by the rising edge of TGATE Shadowing is disabled until the TG bit is cleared by writing a one 8 amp 6 MC68340 USER S MANUAL MOTOROLA to its location in the SR See Figure 8 4 for a depiction of this mode If the timing gate is disabled CR TGE bit is cleared TGATE has no effect
453. pervisor program space Only the initial reset vector is fixed in the processor s memory map once initialization is complete there are no fixed assignments Since the VBR provides the base address of the vector table the vector table can be located anywhere in memory it can even be dynamically relocated for each task that is executed by an operating system Refer to 5 5 Exception Processing for additional details 31 0 VECTOR BASE REGISTER 5 1 5 Exception Handling The processing of an exception occurs in four steps with variations for different exception causes During the first step a temporary internal copy of the status register SR is made and the SR is set for exception processing During the second step the exception vector is determined During the third step the current processor context is saved During the fourth step a new context is obtained and the processor then proceeds with instruction processing Exception processing saves the most volatile portion of the current context by pushing it on the supervisor stack This context is organized in a format called the exception stack frame This information always includes the SR and PC context of the processor when the exception occurred To support generic handlers the processor places the vector offset in the exception stack frame The processor also marks the frame with a frame format The format field allows the return from exception RTE instruction to identify wh
454. ported A 3 6864 MHz crystal drives the baud rate generators Each transmit and receive channel can be programmed for a different baud rate or an external 1x and 16x clock input can be selected Full modem support is provided with separate request to send RTS and clear to send CTS signals for each channel One channel also provides service request signals The two serial ports can sustain rates of 9 8 Mbps with a 25 MHz system clock in 1x mode 612 kbps in 16x mode 6 5 Mbps 410 kbps 16 78 MHz 1 3 4 Timer Modules Timers and counters are used in a system to monitor elapsed time generate waveforms measure signals keep time of day clocks initiate DRAM refresh cycles count events and provide time slices to ensure that no task dominates the activity of the processor A counter that counts clock pulses makes a timer which is most useful when it causes certain actions to occur in response to reaching desired counts The MC68340 has two identical versatile on chip counter timers as well as a simple timer in the 5 40 These general purpose counter timers can be used for precisely timed events without the errors to which software based counters and timers are susceptible 0 errors caused by dynamic memory refreshing cycle steals and interrupt servicing The programmable timer operating modes are input capture output compare square wave generation variable duty cycle square wave generation variable width sing
455. pt acknowledge cycles 5 5 2 12 RETURN FROM EXCEPTION When exception stacking operations for all pending exceptions are complete the processor begins execution of the handler for the last exception processed After the exception handler has executed the processor must restore the system context in existence prior to the exception The RTE instruction is designed to accomplish this task When RTE is executed the processor examines the stack frame on top of the supervisor stack to determine if it is valid and determines what type of context restoration must be performed See 5 5 4 CPU32 Stack Frames for a description of stack frames For a normal four word frame the processor updates the SR and PC with data pulled from the stack increments the SSP by 8 and resumes normal instruction execution For a six word frame the SR and PC are updated from the stack the active SSP is incremented by 12 and normal instruction execution resumes For a bus fault frame the format value on the stack is first checked for validity In addition the version number on the stack must match the version number of the processor that is MOTOROLA MC68340 USER S MANUAL 5 51 attempting to read the stack frame The version number is located in the most significant byte bits 15 8 of the internal register word at location SP 14 in the stack frame The validity check ensures that stack frame data will be properly interpreted in multiprocessor systems If a fr
456. r requires multiple bus cycles the MC68340 does not release the bus until the entire transfer is complete Therefore assertion of BG is subject to the following constraints The minimum time for BG assertion after BR is asserted depends on internal synchronization see Section 11 Electrical Characteristics During an external operand transfer the MC68340 does not assert BG until after the last cycle of the transfer determined by SIZx and DSACK During an external operand transfer the MC68340 does not assert BG as long as RMC is asserted If the show cycle bits SHEN1 SHENO 01 the MC68340 does not assert BG to an external master Externally the BG signal can be routed through a daisy chained network or a priority encoded network The MC68340 is not affected by the method of arbitration as long as the protocol is obeyed 3 6 3 Bus Grant Acknowledge An external device cannot request and be granted the external bus while another device is the active bus master A device that asserts BGACK remains the bus master until it negates BGACK BGACK should not be negated until all required bus cycles are completed Bus mastership is terminated at the negation of BGACK Once an external device receives the bus and asserts BGACK it should negate BR If BR remains asserted after BGACK is asserted the MC68340 assumes that another device is requesting the bus and prepares to issue another BG MOTOROLA MC68340 USER S MANUAL 3 43 3 6 4
457. r the CR TGE bit is set and the TGATE signal transitions in the manner to which the particular mode of operation responds Refer to 8 3 Operating Modes for more details This bit does not affect the programmed signal if the IE1 bit in the CR is cleared 0 This bit is cleared by the timer whenever the RESET signal is asserted on the IMB regardless of the mode of operation This bit may also be cleared by writing a one to it Writing a zero to this bit does not alter its contents This bit is not affected by disabling the timer SWR 0 TC Timer Compare Interrupt 1 This bit is set when the counter transitions off a clock event falling edge to the value in the COM This bit does not affect the programmed signal if the IEO bit in the CR is cleared 0 This bit is cleared by the timer whenever the RESET signal is asserted on the IMB regardless of the mode of operation This bit may also be cleared by writing a one to it Writing a zero to this bit does not alter its contents This bit is not affected by disabling the timer SWR 0 TGL TGATE Level 1 The TGATE signal is negated 0 The TGATE signal is asserted ON Counter Enabled 1 This bit is set whenever the SWR and CPE bits are set in the CR If the CR TGE bit is set TGATE must also be asserted except in the input capture output compare mode since this signal then controls the enabling and disabling of the counter If all these conditions are met
458. r used as a discrete output MOTOROLA MC68340 USER S MANUAL 2 11 T RDYA When used for this function this signal reflects the complement of the status of bit 2 of the channel A status register This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character OP6 When used for this function this output is controlled by bit 6 in the output port data registers 2 13 8 Receiver Ready R RDYA This active low output signal can be programmed as the channel A receiver ready channel A FIFO full indicator or a dedicated parallel output R RDYA When used for this function this signal reflects the complement of the status of bit 1 of the interrupt status register This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character FFULLA When used for this function this signal reflects the complement of the status of bit 1 of the interrupt status register This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full When used for this function this output is controlled by bit 4 in the output port data registers 2 14 TIMER SIGNALS The following external signals are used by the timer modules See Section 8 Timer Modules for additional information on these signals 2 14 1 Timer Gate TGATE2 TGATE1 These active low inputs
459. rammed number of data bits an optional parity bit and the programmed number of stop bits The least significant bit is sent first Data is shifted from the transmitter output on the falling edge of the clock source C1IN TRANSMISSION TxDx TRANSMITTER ENABLED TXRDY SR2 RIS 2 MANUALLY ASSERTED MANUALLY BY BIT SET COMMAND ASSERTED NOTES 1 TIMING SHOWN FOR MR2 4 1 2 TIMING SHOWN FOR MR2 5 1 3 CN TRANSMIT CHARACTER 4 W WRITE Figure 7 5 Transmitter Timing Diagram Following transmission of the stop bits if a new character is not available in the transmitter holding register the TxDx output remains high mark condition and the transmitter empty bit TXEMP in the SR is set Transmission resumes and the TxEMP bit is cleared when the CPU32 loads a new character into the transmitter buffer TB If a disable command is sent to the transmitter it continues operating until the character in the 7 10 MC68340 USER S MANUAL MOTOROLA transmit shift register if any is completely sent out If the transmitter is reset through a software command operation ceases immediately refer to 7 4 1 7 Command Register CR The transmitter is re enabled through the to resume operation after a disable or software reset If clear to send operation is enabled CTS2 must be asserted for the character to be transmitted If CTS is negated in the middle of a transmission the character in the shift register is transmitted
460. rating the system clocks See Section 4 System Integration Module for more information on the various clocking methods and frequencies 2 10 1 System Clock CLKOUT This output signal is the system clock output and is used as the bus timing reference by external devices CLKOUT can be varied in frequency or slowed in low power stop mode to conserve power 2 8 MC68340 USER S MANUAL MOTOROLA 2 10 2 Crystal Oscillator EXTAL XTAL These two pins are the connections for an external crystal to the internal oscillator circuit If an external oscillator is used it should be connected to EXTAL with XTAL left open 2 10 3 External Filter Capacitor XFC This pin is used to add an external capacitor to the filter circuit of the phase locked loop The capacitor should be connected between XFC and VCCSYN 2 10 4 Clock Mode Select MODCK This pin selects the source of the internal system clock during reset After reset it can be programmed to be port B parallel I O MODCK The state of this active high input signal during reset selects the source of the internal system clock If MODCK is high during reset the internal voltage controlled oscillator VCO furnishes the system clock in crystal mode If MODCK is low during reset an external clock source at the EXTAL pin furnishes the system clock output in external clock mode Port BO This pin be used as a port B parallel I O 2 11 INSTRUMENTATION AND EMULATION SIGNALS These s
461. rce operand bus cycle and remain asserted until the end of the destination operand bus cycle For internal request generation as soon as the CCR STR bit is set the DMA channel arbitrates for the bus and begins to transfer data when it becomes bus master For external request generation the STR bit must be set and a DREQx signal must be asserted before the channel arbitrates for the bus and begins a transfer 6 6 DMA CHANNEL OPERATION The following paragraphs describe the programmable channel functions available for the DMA channel the data transfer operations and behavior during cycle termination This description applies to both channels Any DMA channel operation adheres to the following basic sequence 1 Channel Initialization and Startup The channel registers are initialized The channel is then started by setting the CCR STR bit The first operand transfer request either internally or externally generated is recognized 2 Data Transfer After a channel is started it transfers one operand in response to each request until an entire data block is transferred 3 Channel Termination The channel can terminate by normal completion or from an error The channel status register CSR indicates the status of the operation 6 6 1 Channel Initialization and Startup Before starting a block transfer operation the channel registers must be initialized with information describing the channel configuration request generation method
462. re Set Read Modify Write Instructions Coprocessor Instructions cpDBcc cpRESTORE CpSAVE cpScc cpTRAPcc PACK UNPK Pack Unpack BCD Instructions The CPU32 traps on unimplemented instructions or illegal effective addressing modes allowing user supplied code to emulate unimplemented capabilities or to define special purpose functions However Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements MOTOROLA MC68340 USER S MANUAL 5 5 Table 5 1 Instruction Set memoni mnemone Description Add Decimal with Extend MOVEA Move Address Add MOVE CCR Move Condition Code Register Add Address MOVE SR Move to from Status Register Add Immediate MOVE USP Move User Stack Pointer Add Quick MOVEC Move Control Register Logical AND MOVEM Move Multiple Registers Logical AND Immediate MOVEP Move Peripheral Data Arithmetic Shift Left MOVEQ Move Quick Arithmetic Shift Right MOVES Move Alternate Address Space Branch Conditionally 16 Tests MULS Signed Multiply Bit Test and Change MULU Unsigned Multiply Bit Test and Clear Negate Decimal with Extend Enter Background Mode Negate Breakpoint Negate with Extend Branch Always No Operation Bit Test and Set Ones Complement Branch to Subroutine Logical Inclusive OR Bit Test Logical Inclusive OR Immediate Check Register against Bounds Check Register agains
463. re changed during receiver transmitter operations as undesirable results may be produced In the registers discussed in the following pages the numbers in the upper right hand corner indicate the offset of the register from the base address specified in the module base address register MBAR in the 5 40 The numbers above the register description represent the bit position in the register The register description contains the mnemonic for the bit The values shown below the register description are the values of those register bits after a hardware reset A value of U indicates that the bit value is unaffected by reset The read write status and the access privilege are shown in the last line 7 18 NOTE A CPU32 RESET instruction will not affect the MCR but will reset all the other serial module registers as though a hardware reset had occurred The module is enabled when the STP bit in the MCR is cleared The module is disabled when the STP bit in the MCR is set MC68340 USER S MANUAL MOTOROLA Address FC Register Read R W 1 Register Write R W z 0 700 s MCR HIGH BYTE MCR HIGH BYTE 701 MCR LOW BYTE MCR LOW BYTE S S S 704 INTERRUPT LEVEL ILR NTERRUPT LEVEL ILR 705 INTERRUPT VECTOR IVR INTERRUPT VECTOR IVR 720 SU MODE REGISTER 1 MR1A MODE REGISTER 1A MR1A 711 S U STATUS REGISTER A SRA CLOCK SELECT REGISTER A CSRA 712 S U COMMAND REGISTER A CRA 73 RECEIVER BUFFER A RBA TRANSMIT
464. rect memory access DMA controller module to provide external handshake for either a source or destination See Section 6 DMA Module for additional information on these signals 2 12 1 DMA Request DREQ2 DREQ1 This active low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory The assertion of DREQ starts the DMA process The assertion level in external burst mode is level sensitive in external cycle steal mode it is falling edge sensitive 2 12 2 DMA Acknowledge DACK2 DACK1 This active low output is asserted by the DMA to signal to a peripheral that an operand is being transferred in response to a previous transfer request 2 12 3 DMA Done DONE2 DONE1 This active low bidirectional signal is asserted by the DMA or a peripheral device during any bus cycle to indicate that the last data transfer is being performed DONE is an active input in any mode As an output it is only active in external request mode An external pullup resistor is required even during operation in the internal request mode 2 10 MC68340 USER S MANUAL MOTOROLA 2 13 SERIAL MODULE SIGNALS The following signals are used by the serial module for data and clock signals See Section 7 Serial Module for more information on these signals 2 13 1 Serial Crystal Oscillator X2 X1 These pins furnish the connection to a crystal or external clock which must be supplied when using the baud rate ge
465. red When RTE is executed the exception stack frame saved on the supervisor stack can be restored in either of two ways If the frame was generated by an interrupt breakpoint trap or instruction exception the SR and PC are restored to the values saved on the supervisor stack and execution resumes at the restored PC address with access level determined by the S bit of the restored SR If the frame was generated by a bus error or an address error exception the entire processor state is restored from the stack 5 5 EXCEPTION PROCESSING An exception is a special condition that preempts normal processing Exception processing is the transition from normal mode program execution to execution of a routine that deals with an exception The following paragraphs discuss system resources related to exception handling exception processing sequence and specific features of individual exception processing routines 5 38 MC68340 USER S MANUAL MOTOROLA 5 5 1 Exception Vectors An exception vector is the address of a routine that handles an exception The VBR contains the base address of a 1024 byte exception vector table which consists of 256 exception vectors Sixty four vectors are defined by the processor and 192 vectors are reserved for user definition as interrupt vectors Except for the reset vector which is two long words each vector in the table is one long word Refer to Table 5 16 for information on vector assignment Table 5 16 Ex
466. red with a system clock frequency of 16 78 MHz all modules active Supply current measured with system clock frequency of 8 39 MHz 9 3 6 V Power dissipation measured with a system clock frequency of 8 39 MHz all modules active Capacitance is periodically sampled rather than 100 tested WP MOTOROLA MC68340 USER S MANUAL 11 5 11 6 AC ELECTRICAL SPECIFICATIONS CONTROL TIMING see notes 0 c d corresponding to part operation GND 0 Vdc TA 0 to 70 see numbered notes 167 CLKOUT Pulse Width in Crystal Mode 839MHz 1678MHz 25 16 MHz Characteristic Min Mex Min Max Min Max System Frequency fsys d 8 39 dc 16 78 dc 25 16 MHz eC oe 8 2 Symbol 5 PLL Start up Time Limp Mode Clock Frequency flimp SYNCR X bit 0 SYNCR X bit 1 External Clock Input Period tExTcyc External Clock Input Period with PLL 125 2B 3 9 CLKOUT Pulse Width in External Mode tEXTCW 2C CLKOUT Pulse Width in External w PLL tExTCW 62 5 3c 10 Mode CLKOUT Rise and Fall Times as 10 NOTES A The electrical specifications in this document for both the 8 39 and 16 78 MHz 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part The 16 78 MHz specifications apply to the MC68340 9 5 0 V 5 operation The 25 16 MHz 9 5 0 V 5 electrical specifications are preliminary For extended temper
467. rent context is saved on the top of the supervisor stack This context is organized in a format called the exception stack frame The exception stack frame always includes the contents of SR and PC at the time the exception occurred To support generic handlers the processor also places the vector offset in the exception stack frame and marks the frame with a format code The format field allows an RTE instruction to identify stack information so that it can be properly restored The general form of the exception stack frame is illustrated in Figure 5 10 Although some formats are peculiar to a particular M68000 Family processor format 0000 is always legal and always indicates that only the first four words of a frame are present See 5 5 4 CPU32 Stack Frames for a complete discussion of exception stack frames SP STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT VECTOR OFFSET STACKING ORDER OTHER PROCESSOR STATE INFORMATION DEPENDING ON EXCEPTION 0 2 OR 8 WORDS HIGHER ADDRESSES Figure 5 10 Exception Stack Frame 5 5 1 4 MULTIPLE EXCEPTIONS Each exception has been assigned a priority based on its relative importance to system operation Priority assignments are shown in Table 5 17 Group 0 exceptions have the highest priorities group 4 exceptions have the lowest priorities Exception processing for exceptions that occur simultaneously is done by priority from highest to lowest It
468. rente tope ees 5 29 Table Example 1 Standard 5 30 Table Example 2 Compressed Table 5 31 Table Example 3 8 Bit Independent Variable 5 32 Table Example 4 Maintaining 5 34 Table Example 5 Surface Interpolations 5 36 Nested Subroutine Calls na 5 36 Pipeline Synchronization with the Instruction 5 36 PrOCGSSIFIC CLOSE 5 36 State T TatisiliOliSs c e oasis tdt tt etti ect ita races tuuc os IL feu 5 37 tre er SRR ear en a 5 37 Supervisor Privilege 5 37 User Privilege 5 39 MC68340 USER S MANUAL MOTOROLA 11 2 95 Number 5 4 2 3 5 5 5 5 1 5 5 1 1 5 5 1 2 5 5 1 3 5 5 1 4 5 5 2 5 5 2 1 5 5 2 2 5 5 2 3 5 5 2 4 5 5 2 5 5 5 2 6 5 5 2 7 5 5 2 8 5 5 2 9 5 5 2 10 5 5 2 11 5 5 2 12 5 5 3 5 5 3 1 5 5 3 1 1 5 5 3 1 2 5 5 3 1 3 5 5 3 1 4 5 5 3 2 5 5 3 2 1 5 5 3 2 2 5 5 3 2 3 5 5 3 2 4 5 5 3 2 5 5 5 3 2 6 5 5 3 2 7 5 5 4 5 5 4 1 5 5 4 2 5 5 4 3 5 6 5 6 1 5 6 1 1 5 6 1 2 MOTOROLA SECTION 1 OVERVIEW UM
469. rn PC Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 op vec orsi of 0 0 oe ow esos MOTOROLA MC68340 USER S MANUAL 5 83 Command Sequence NORMAL MODE ILLEGAL NEXT CMD NOT READY Operand Data None Result Data None 5 6 2 8 13 Call User Code CALL This instruction provides a convenient way to patch user code The return PC is stacked at the location pointed to by the current SP The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine After stacking is complete the 32 bit operand data is loaded into the PC The pipeline is flushed and refilled from the location pointed to by the new PC BDM is exited and normal mode instruction execution begins NOTE If a bus error or address error occurs during return address stacking the CPU returns an error status via the serial interface and remains in BDM If a bus error or address error occurs on the first instruction prefetch from the new PC the processor exits BDM and the error is trapped as a normal mode exception The stacked value of the current PC may not be valid in this case depending on the state of the machine prior to entering BDM For address error the PC does not reflect the true return PC Instead the stacked fault address is the odd return PC Command Format 15 14 11 13 12 10 9 8 7 6 5 4 3 2 1 0 o jo o i ojofo jo jojo fjo jofjo jof o
470. rom the rising edge of the clock the falling edge is effectively ignored suck VU LuuuuL i irr ru FORCE BGND BKPT TAG Ka LL TU WU uuu nnrnrnrnrnrri FREEZE Figure 5 25 BKPT Timing for Forcing BDM Figure 5 26 represents a sample circuit providing for both BKPT assertion methods As the name implies FORCE BGND is used to force a transition into BDM by the assertion of BKPT FORCE BGND can be a short pulse or can remain asserted until FREEZE is asserted Once asserted the set reset latch holds BKPT low until the first SHIFT CLK is applied BKPT TAG SHIFT BKPT DSCLK RESET gt o FORCE_BGND Figure 5 26 BKPT DSCLK Logic Diagram BKPT_TAG should be timed to the bus cycles since it is not latched If extended past the assertion of FREEZE the negation of BKPT_TAG appears to the CPU32 as the first DSCLK 572 MC68340 USER S MANUAL MOTOROLA DSCLK the gated serial clock is normally high but it pulses low for each bit to be transferred At the end of the seventeenth clock period it remains high until the start of the next transmission Clock frequency is implementation dependent and may range from DC to the maximum specified frequency Although performance considerations might dictate a hardware implementation software solutions can be used provided serial bus timing is maintained 5 6 2 8 COMMAND SET The following paragraphs describe the command set available in BDM 5 6 2 8 1 Comman
471. ronous termination or up to three wait states can be programmed whether or not the chip select signals are used External handshakes can also signal the end of a bus transfer A system can boot from reset out of 8 bit wide memory if desired 1 3 1 5 INTERRUPT HANDLING Seven input signals are provided to trigger an external interrupt one for each of the seven priority levels supported Seven separate outputs can indicate the priority level of the interrupt being serviced An input can direct the processor to a default service routine if desired Interrupts at each priority level can be preprogrammed to go to the default service routine For maximum flexibility interrupts can be vectored to the correct service routine by the interrupting device 1 3 1 6 DISCRETE PINS When not used for other functions 16 pins can be programmed as discrete input or output lines Additionally in other peripheral modules pins for otherwise unused functions can often be used for general input output 1 6 MC68340 USER S MANUAL MOTOROLA 1 3 1 7 IEEE 1149 1 TEST ACCESS PORT To aid in system diagnostics the MC68340 includes dedicated user accessible test logic that is fully compliant with the IEEE 1149 1 standard for boundary scan testability often referred to as JTAG Joint Test Action Group 1 3 2 Direct Memory Access Module The most distinguishing MC68340 characteristic is the high speed 32 bit DMA controller used to quickly move large blocks of da
472. rs inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes NL e sew s e fooro ENS s s Direction left or right NOTES 1 Head and cycle times can be derived from the following table or calculated as follows Max 3 n 4 mod n 4 mod n 4 mod n 4 1 2 6 2 Head and cycle times are calculated as follows count x 63 max 8 n mod n 1 2 6 3 Head and cycle times are calculated as follows count x 8 max 2 n mod n 2 6 Shift Counts 5 108 MC68340 USER S MANUAL MOTOROLA 5 7 3 10 BIT MANIPULATION INSTRUCTIONS The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes instruction Head Tal Cycles pae m _ mcs LOC UT E o soo pes pum ee BSET 41050 _ ee Ce erst 1 o x fetch EA time must be added for this instruction FEA FEA OPER MOTOROLA MC68340
473. rs to receiver value Tx refers to transmitter value Gx refers to the value that is greater either receiver or transmitter 2 Specification 3 for 16 78 MHz 9 3 3 V 0 3 V will be 8 ns O CLKOUT O gt TxD Figure 11 15 Serial Module General Timing Diagram 11 22 MC68340 USER S MANUAL MOTOROLA 7 7 ND RD Figure 11 16 Serial Module Asynchronous Mode Timing X1 SCLK 16x Figure 11 17 Serial Module Asynchronous Mode Timing SCLK 16X SCLK 1x TxD Figure 11 18 Serial Module Synchronous Mode Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 23 11 11 IEEE 1149 1 ELECTRICAL SPECIFICATIONS see rotes b c and d corresponding to part operation GND 0 Vdc TA 0 to 70 see Figures 11 19 11 21 3 3 V or 3 3 V 5 0 V 5 0 V Characteristic TCK Frequency of Operation 1 Cycle Time in Crystal Mode 3 TCK Rise and Fall Times Boundary Scan Input Data Setup Time 7 Boundary Scan Input Data Hold Time TCK Low to Output Data Valid TCK Low to Output High Impedance TMS TDI Data Setup Time TMS TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO High Impedance NOTES The electrical specifications in this document for both the 8 39 and 16 78 MHz 9 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part The 16 78 MHz specifications apply to the MC68340 9
474. rst timeout can be known For additional details on timing see the Section 11 Electrical Characteristics If the counter counts down to the value stored in the COM register the COM and timer compare interrupt TC bits in the SR are set The counter continues counting down to timeout At this time the TO bit in the SR is set and the COM bit is cleared The next falling edge of the counter clock after timeout causes the value in PREL2 N2 to be loaded into the counter and the counter begins counting down from this value Each MOTOROLA MC68340 USER S MANUAL 8 9 successive timeout causes the counter to be loaded alternately with the values from PREL1 and PREL2 TOUTx behaves as a variable duty cycle square wave when the CR OC bits are programmed for toggle mode The second timeout occurs after N2 1 periods allowing for the zero cycle resulting in a change of state on TOUTx The third timeout occurs after N1 1 periods resulting in a change of state on and so on see Figure 8 6 The OUT bit in the SR reflects the level of TOUTx COUNTER CLOCK COUNTER 0 0 4 3 2 1 0 4 3 2 1 0 2 1 1 TOUT 1 1 IN ENABLE TIMEOUT TIMEOUT TIMEOUT TIMEOUT MODEx Bits in Control Register 010 Preload 1 Register N1 4 Preload 2 Register N2 2 OOCx Bits in Control Register 01 Figure 8 6 Variable Duty Cycle Square Wave Generator Mode If is negated when it is enabled TGE 1 the presca
475. rupt of level one through six is requested via IRQ6 IRQ1 the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed Interrupt requests are inhibited for all priority levels less than or equal to the current priority Level seven interrupts are nonmaskable IRQ7 IRQ1 are synchronized and debounced by input circuitry on consecutive rising edges of the processor clock To be valid an interrupt request must be held constant for at least two consecutive clock periods Interrupt requests do not force immediate exception processing but are left pending A pending interrupt is detected between instructions or at the end of exception processing all interrupt requests must be held asserted until they are acknowledged by the CPU If the priority of the interrupt is greater than the current priority level exception processing begins Exception processing occurs as follows First the processor makes an internal copy of the SR After the copy is made the processor state bits in the SR are changed the S bit is set establishing supervisor access level and bits T1 and TO are cleared disabling 5 50 MC68340 USER S MANUAL MOTOROLA tracing Priority level is then set to the level of the interrupt and the processor fetches vector number from the interrupting device CPU space F The fetch bus cycle is classified as an interrupt acknowledge and the encoded level number of the interrupt i
476. s During power on POR forces the TAP controller into this state Alternatively sampling TMS as a logic one for five consecutive TCK rising edges also forces the TAP controller into this state If TMS either remains unconnected or is connected to VCC then the TAP controller cannot leave the test logic reset state regardless of the state of TCK 9 12 MC68340 USER S MANUAL MOTOROLA SECTION 10 APPLICATIONS This section provides guidelines for using the MC68340 Minimum system configuration requirements and memory interface information are discussed 10 1 MINIMUM SYSTEM CONFIGURATION One of the powerful features of the MC68340 is the small number of external components needed to create an entire system The information contained in the following paragraphs details a simple high performance MC68340 system see Figure 10 1 This system configuration features the following hardware Processor Clock Circuitry Reset Circuitry SRAM Interface ROM Interface Serial Interface SRAM CLOCK CIRCUITRY MC68340 SERIAL INTERFACE Figure 10 1 Minimum System Configuration Block Diagram 10 1 1 Processor Clock Circuitry The MC68340 has an on chip clock synthesizer that can operate from an on chip phase locked loop PLL and a voltage controlled oscillator VCO The clock synthesizer uses an external crystal connected between the EXTAL and XTAL pins as a reference frequency source Figure 10 2 shows a typical circuit usi
477. s placed on the address bus If an interrupting device requests automatic vectoring the processor generates a vector number 25 to 31 determined by the interrupt level number If the response to the interrupt acknowledge bus cycle is a bus error the interrupt is taken to be spurious and the spurious interrupt vector number 24 is generated The exception vector number PC and SR are saved on the supervisor stack The saved value of the PC is the address of the instruction that would have executed if the interrupt had not occurred Priority level 7 interrupt is a special case Level 7 interrupts are nonmaskable interrupts NMI Level 7 requests are transition sensitive to eliminate redundant servicing and resultant stack overflow Transition sensitive means that the level 7 input must change state before the CPU will detect an interrupt An NMI is generated each time the interrupt request level changes to level 7 regardless of priority mask value and each time the priority mask changes from 7 to a lower number while the request level remains at 7 Many M68000 peripherals provide for programmable interrupt vector numbers to be used in the system interrupt request acknowledge mechanism If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request the peripheral should return the uninitialized interrupt vector number 15 See Section 3 Bus Operation for detailed information on interru
478. s around the end of S2 If wait states are added the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized The selected device uses R W 5121 5120 and 0 to latch data from the appropriate byte s of 015 08 and 07 00 SIZ1 SIZO and AO select the bytes of the data bus If it has not already done so the device asserts DSACK to signal that it has successfully stored the data 3 18 MC68340 USER S MANUAL MOTOROLA State 4 The MC68340 issues no new control signals during S4 State 5 The MC68340 negates AS and DS during S5 It holds the address and data valid during S5 to provide address hold time for memory systems R W 5121 5140 and FC3 FCO also remain valid throughout S5 The external device must keep DSACK asserted until it detects the negation of AS or DS whichever it detects first The device must negate DSACK within approximately one clock period after sensing the negation of AS or DS DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle 3 3 3 Read Modify Write Cycle The read modify write cycle performs a read conditionally modifies the data in the arithmetic logic unit and may write the data out to memory In the MC68340 this operation is indivisible providing semaphore capabilities for multiprocessor systems During the entire read modify write sequence the MC68340 asserts RMC to indicate that an indivisible operation is occurring T
479. s illustrated in Figure 10 12 OUTPUT t Figure 10 12 Signal Width Specifications The method for calculating a frequency adjusted tw is as follows tw tw N TI 2 Tf 2 Tf 2 tg where tw the frequency adjusted signal width tw the signal width at 16 78 MHz N the number of full one half clock periods in tw Tf 2 one half the new clock period Tf 2 one half the clock period at full speed td the propagation time from the clock edge The following calculation uses a 16 78 2 part specification 14 AS width asserted at 12 5 MHz as an example tw 100 ns N 3 Tf 2 80 2 40 ns Tf 2 60 2 30 ns td 30 ns maximum therefore tw 100 3 40 30 40 30 140 ns The third type of specification used is a skew between two outputs see Figure 10 13 10 8 MC68340 USER S MANUAL MOTOROLA CLKOUT tg OUTPUT1 X tq OUTPUT2 ts Figure 10 13 Skew between Two Outputs The method for calculating a frequency adjusted ts is as follows ts N Tf 2 Tf 2 Tf 2 tg1 where ts the frequency adjusted skew ts the skew at full speed N the number of full one half clock periods in ts if any Tf 2 one half the new clock period Tf 2 one half the clock period at full speed tdi the propagation time for the first output from the clock edge The following calculation uses a 16 78 MHz port specification 21 R W high to AS a
480. s monitors and timers including the internal bus monitor double bus fault monitor spurious interrupt monitor software watchdog timer and the periodic interrupt timer The clock synthesizer generates the clock signals used by the SIM40 and the other on chip modules as well as CLKOUT used by external devices The programmable chip select function provides four chip select signals that can enable external memory and peripheral circuits providing all handshaking and timing signals Each chip select signal has an associated base address register and an address mask register that contain the programmable characteristics of that chip select Up to three wait states can be programmed by setting bits in the address mask register MOTOROLA MC68340 USER S MANUAL 4 1 The external bus interface handles the transfer of information between the internal CPUS2 and memory peripherals or other processing elements in the external address space See Section 3 Bus Operation for further information The MC68340 dynamically interprets the port size of an addressed device during each bus cycle allowing operand transfers to or from 8 16 and 32 bit ports The device signals its port size and indicates completion of the bus cycle through the use of the DSACK inputs Dynamic bus sizing allows a programmer to write code that is not bus width specific For a discussion on dynamic bus sizing see Section 3 Bus Operation The MC68340 includes dedicate
481. s on the data bus If the ECO bit is set the external handshake signals are used with the source operand and a single address source read occurs If the ECO bit is cleared the external handshake signals are used with the destination operand and a single address destination write occurs The channel can be programmed to operate in either burst transfer mode or cycle steal mode See 6 7 Register Description for more information If external 32 bit devices and a 32 bit bus are used with the MC68340 the DMA can control 32 bit transfers between devices that use the 32 bit bus in single address mode only External logic is required to complete a 32 bit long word transfer If both byte and word devices are used on an external bus then an external multiplexer must be used to correctly transfer data The SIZx and 0 signals can be used to control this external multiplexer 6 4 1 1 SINGLE ADDRESS READ During the single address source read cycle the DMA controls the transfer of data from memory to a device The memory selected by the address specified in the source address register SAR the source function codes in the function code register FCR and the source size in the CCR provides the data and control signals on the data bus This bus cycle operates like a normal read bus cycle The DMA control signals DACK and DONE are asserted in the source read cycle See Figures 6 5 and 6 6 for timing diagrams single address read for external burst a
482. s register can be read or written at any time PORTA 011 1 6 5 4 3 2 1 0 em re ro jm jm jm m rm RESET U U U U U U U U Supervisor User 4 34 MC68340 USER S MANUAL MOTOROLA 4 3 5 5 PORT B PIN ASSIGNMENT REGISTER PPARB PPARB controls the function of each port B pin Any set bit defines the corresponding pin to be an IRQ input CS as defined in Table 4 5 Any cleared bit defines the corresponding pin to be a discrete pin or CS if the FIRQ bit of the MCR is zero controlled by the port B data and data direction registers The MODCK signal has no function after reset PPARB is configured to all ones at reset to provide for MODCK IRQ7 IRQ6 IRQ5 IRQ3 and CS3 CSO This register can be read or written at any time PPARB 01F 7 6 5 4 3 2 1 0 PPARB7 PPARB6 5 PPARB4 PPARB3 PPARB2 PPARB1 PPARBO IRQ7 IRQ5 MODCK RESET 1 1 1 1 1 1 1 1 Supervisor Only 4 3 5 6 PORT B DATA DIRECTION REGISTER DDRB DDRB controls the direction of the pin drivers when the pins are configured as l O Any set bit configures the corresponding pin as an output any cleared bit configures the corresponding pin as an input This register affects only pins configured as discrete This register be read or written at any time DDRB 01D 7 6 5 4 3 2 1 0 5 oos oos oos 9 oor ooo RESET 0 0 0 0 0 0 0 0 Supervisor User 4
483. s to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory The 5 2 MC68340 USER S MANUAL MOTOROLA CPU32 uses instruction restart which requires that only a small portion of the internal machine state be saved After correcting the page fault the machine state is restored and the instruction is refetched and restarted This process is completely transparent to the application program UENCER NTROL INSTRUCTION UNIT PREFETCH AND DECODE DATA BUS lt T EXECUTION BUS CONTROL UNIT ADDRESS BUS Figure 5 1 CPU32 Block Diagram 5 1 3 Loop Mode Instruction Execution The CPU32 has several features that provide efficient execution of program loops One of these features is the DBcc looping primitive instruction To increase the performance of the CPU32 a loop mode has been added to the processor The loop mode is used by any single word instruction that does not change the program flow Loop mode is implemented in conjunction with the DBcc instruction Figure 5 2 shows the required form of an instruction loop for the processor to enter loop mode ONE WORD INSTRUCTION DBcc DBcc DISPLACEMENT FFFC 2 4 Figure 5 2 Loop Mode Instruction Sequence The loop mode is entered when the DBcc instruction is executed and the loop displacement is 4 Once in loop mode the processor performs
484. s transferred directly into the destination location The MC68340 on chip peripherals do not support single address transfers The DMA channel runs dual address transfers STR Start This bit is cleared by a hardware software reset writing a logic zero or setting one of the following CSR bits DONE BES BED CONF or BRKP The STR bit cannot be set when the CSR IRQ bit is set The DMA channel cannot be started until the CSR DONE BES BED CONF and BRKP bits are cleared Internal Request Mode 1 The DMA transfer starts as soon as this bit is set 0 The DMA transfer can be stopped by clearing this bit External Request Mode 1 Setting this bit allows the DMA to start the transfer when a DREQx input is received from an external device 0 The DMA transfer can be stopped by clearing this bit NOTE If any fields in the CCR are modified while the channel is active that change is effective immediately To avoid any problems with changing the setup for the DMA channel a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle 6 7 4 Channel Status Register CSR The CSR contains the channel status information This register is accessible in either supervisor or user space The CSR can always be read or written to when the DMA module is enabled i e the STP bit in the MCR is cleared CSR1 CSR2 78A 7AA 7 6 5 4 3 2 1 0 owe ees cow e o o
485. scaler which is not in the synthesizer feedback loop Setting the bit doubles the system clock speed without changing the VCO speed as specified in the equation for determining system frequency therefore no delay is incurred to relock the VCO Y5 Y0 Frequency Control Bits The Y bits with a value from 0 63 control the modulus downcounter in the synthesizer feedback loop causing it to divide by the value of Y 1 see the equation for determining system frequency Changing these bits requires a time delay for the VCO to relock Bits 5 Bit 7 is reserved for factory testing 4 28 MC68340 USER S MANUAL MOTOROLA SLIMP Limp Mode 1 Aloss of input signal reference has been detected and the VCO is running at approximately one half the maximum speed affected by the X bit determined from an internal voltage reference 0 External input signal frequency is at VCO reference SLOCK Synthesizer Lock 1 VCO has locked onto the desired frequency or system clock is driven externally 0 VCO is enabled but has not yet locked RSTEN Reset Enable 1 Loss of input signal causes a system reset Loss of input signal causes the VCO to operate at a nominal speed without external reference limp mode and the device continues to operate at that speed STSIM Stop Mode System Integration Clock 1 When LPSTOP is executed the SIM40 clock is driven from the VCO 0 When LPSTOP is executed the S
486. ser NOTE OP bits 7 5 3 and 2 are not pinned out on the MC68340 thus changing bits 7 5 3 and 2 of this register has no effect OP6 Output Port 6 T RDYA 1 The OP6 T RDYA pin functions as the transmitter ready signal for channel A The signal reflects the complement of the value of bit 2 of the SRA thus T RDYA is a logic zero when the transmitter is ready 0 The OP6 T RDYA pin functions as a dedicated output The signal reflects the complement of the value of bit 6 of the OP OP4 Output Port 4 R RDYA 1 The OP4 R RDYA pin functions as the FIFO full or receiver ready signal for channel A depending on the value of bit 6 of MR1A The signal reflects the complement of the value of ISR bit 1 thus Re RDYA is a logic zero when the receiver is ready 0 The OP4 R RDYA pin functions as a dedicated output The signal reflects the complement of the value of bit 4 of the OP OP1 Output Port 1 RTSB 1 The OP1 RTSB pin functions as the ready to send signal for channel B The signal is asserted and negated according to the configuration programmed by RxRTS bit 7 in the MR1B for the receiver and TxRTS bit 5 in the MR2B for the transmitter 0 The OP1 RTSB pin functions as a dedicated output The signal reflects the complement of the value of bit 1 of the OP 7 36 MC68340 USER S MANUAL MOTOROLA OP0 Output Port 0 RTSA 1 The OPO RTSA pin functions as the ready to send signal for channel A The signal is asserted a
487. so three clocks To support systems that use the system clock to generate DSACK and other asynchronous inputs the asynchronous input setup time and the asynchronous input hold time are given If the setup and hold times are met for the assertion or negation of a signal such as DSACK the MC68340 is guaranteed to recognize that signal level on that specific falling edge of the system clock If the assertion of DSACK is recognized a particular falling edge of the clock valid data is latched into the MC68340 for a read cycle on the next falling clock edge if the data meets the data setup time In this case the parameter for asynchronous operation can be ignored The timing parameters are described in Section 11 Electrical Characteristics 3 14 MC68340 USER S MANUAL MOTOROLA If a system asserts DSACK for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK and or BERR HALT until and throughout the clock edge that negates AS with the appropriate asynchronous input hold time no wait states are inserted The bus cycle runs at its maximum speed for bus cycles terminated with DSACK three clocks per cycle When BERR BERR and HALT is asserted after DSACK BERR and HALT must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACK is recognized This setup time is critical and the MC68340 may exhibit erratic behavior if it is violated When opera
488. space The timer asserts BERR after timeout case 3 3 32 MC68340 USER S MANUAL MOTOROLA EXAMPLE B A system uses error detection and correction RAM contents The designer may 1 Delay DSACK until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle case 5 or if data is valid assert DSACK case 1 2 Delay DSACK until data is verified and assert BERR with or without DSACK if data is in error case 3 This initiates exception processing for software handling of the condition 3 Return prior to data verification if data is invalid BERR is asserted on the next clock cycle case 4 This initiates exception processing for software handling of the condition 4 Return DSACK prior to data verification if data is invalid assert BERR and HALT on the next clock cycle case 6 The memory controller can then correct the RAM prior to or during the automatic retry Table 3 4 DSACK BERR and HALT Assertion Results Asserted on Rising Edge of State Normal cycle terminate and continue Normal cycle terminate and halt continue when HALT negated Terminate and take bus error exception possibly deferred Terminate and take bus error exception possibly deferred Terminate and retry when HALT negated Terminate and retry when HALT negated N Number of the current even bus state e g S2 S4 etc A Signal is asser
489. ss of the block and to retrieve the first result Subsequent operands retrieved with the DUMP command The initial address is incremented by the operand size 1 2 or 4 and saved in a temporary register Subsequent DUMP commands use this address increment it by the current operand size and store the updated address back in the temporary register NOTE The DUMP command does not check for a valid address in the temporary register DUMP is a valid command only when preceded by another DUMP or by a READ command Otherwise the results are undefined The NOP command can be used for intercommand padding without corrupting the address pointer The size field is examined each time a DUMP command is given allowing the operand size to be altered dynamically Command Format 15 14 11 13 12 10 9 8 7 6 5 4 3 2 1 0 KUNEESNESEZENXEEE rse o o o o o o Command Sequence XXX NOT READY NEXT CMD RESULT XXX BERR AERR XXX ILLEGAL READ MEMORY LOCATION DUMP LONG 22 NEXT CMD NOT READY NEXT CMD NOT READY READ MEMORY LOCATION NOT READY NEXT CMD NEXT CMR MS RESULT LS RESULT XXX NEXT CMD BERR AERR NOT READY XXX NEXT CMD ILLEGAL NOT READY DUMP LONG Ne A 22 MOTOROLA MC68340 USER S MANUAL 5 81 Operand Data None Result Data Requested data is returned as either a word or long word Byte data is returned in the least s
490. ss space accessed Valid data sizes include byte word or long word Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM URE Command Sequence READ BMW MS ADDR LS ADDR READ Y gt 7 v gt MEMORY NOT READY NOT READY LOCATION SGEN anm ILLEGAL READY XXX gt NOT READY NEXT CMD RESULT XXX BERR AERR gt NEXT CMD NOT READY READ LONG MS ADDR LS ADDR READ NOT READY WNOTREADY MEMORY XXX gt NEXT CMD ILLEGAL NOT READY XXX gt NOT READY XXX gt NEXT CMD MS RESULT LS RESULT NEXT CMD NOT READY BERR AERR Operand Data The single operand is the long word address of the requested memory location Result Data The requested data is returned as either a word or long word Byte data is returned in the least significant byte of a word result with the upper byte cleared Word results return 16 bits of significant data long word results return 32 bits A successful read operation returns data bit 16 cleared If a bus or address error is encountered the returned data is 10001 5 6 2 8 9 Write Memory Location WRITE Write the operand data to the memory location specified by the long word address The DFC register determines the address MOTOROLA MC68340 USER S MANUAL 5 79 space accessed Only absolute addressing is supported Valid data sizes include byte word and long word Command For
491. sserted at 8 MHz as an example ts 15 ns minimum 0 2 125 2 62 5 ns Tf 2 60 2 30 ns td1 30 ns maximum therefore ts 15 0 62 5 30 62 5 30 47 5 ns minimum In this manner new specifications for lower frequencies can be derived for an MC68340 MOTOROLA MC68340 USER S MANUAL 10 9 10 2 4 Interfacing an 8 Bit Device to 16 Bit Memory Using Single Address DMA Mode One of the requirements of single address mode is that the source and destination must be the same port size However the MC68340 can perform direct memory accesses in single address mode between an 8 bit device and 16 bit memory The port size must be specified as 8 bits and some external logic is required as shown in Figure 10 14 DEVICE D15 D8 gt B T R MEMORY 74 245 07 00 gt Figure 10 14 Circuitry for Interfacing 8 Bit Device to 16 Bit Memory in Single Address DMA Mode During even byte accesses the data is transferred directly on D15 D8 However during odd byte accesses the data must be routed on D15 D68 for the 8 bit device and on 7 DO for the 16 bit memory 10 3 POWER CONSUMPTION CONSIDERATIONS The MC68340 can be designed into low power applications that involve high performance processing capability 32 bits high functional density small size portable capability and battery operation The MC68340 fits into the following types of applications e P
492. sters 4 14 4 30 4 33 4 37 Battery Operation 10 10 Baud Rate Clock 7 2 7 26 7 27 Generator 7 3 7 8 MOTOROLA MC68330 USER S MANUAL BB Bits 6 4 6 29 6 38 BDM Sources 5 66 BED Bit 6 27 6 27 6 30 6 31 6 37 BERR Signal 5 45 5 47 BES Bit 6 20 6 31 6 37 BFC Bits 4 30 BGND Instruction 5 66 Binary Coded Decimal Extended Instructions Timing Table 5 106 Instructions 5 26 Bit Manipulation Instructions 5 25 Timing Table 5 109 Bit Set Reset Command 7 37 Bits per Character 7 23 BKPT Signal 5 65 5 66 5 68 5 71 5 72 BKPT TAG 5 72 Block Mode 7 13 7 23 BME Bit 4 6 4 25 4 37 BMT Bits 4 25 4 26 4 37 Boot ROM 4 14 4 15 4 36 Boundary Scan Bit Definitions 9 4 Register 9 1 9 3 Break Condition 7 11 Breakpoint Acknowledge Cycle Operation 3 22 Flowchart 3 24 Timing Opcode Returned 3 25 Timing Exception Signaled 3 26 Breakpoint Exception 5 42 5 46 5 47 5 53 Breakpoint Instruction 3 22 5 28 5 40 5 42 5 46 5 63 5 94 5 97 Breakpoint Signal 2 10 3 22 3 24 6 31 BRG Bit 7 32 7 46 BRKP Bit 6 20 6 27 6 31 6 37 6 38 Burst Mode Transfers 6 5 Bus Arbitration Operation 3 40 3 41 3 45 Flowchart 3 41 Interaction with Show Cycles 3 44 Control 3 44 State Diagram 3 45 Bandwidth 6 4 6 5 6 29 Controller Operation 5 89 5 90 Cycle Termination Response Time 4 6 4 30 4 32 Cycle Termination 3 34 3 36 3 47 Cycle 3 2 Error Exception 5 45 Error Signal 2 8 3 5
493. stic CLKOUT Low to AS DACK DONE Asserted 2 CLKOUT Low to AS DACK Negated DREQ Asserted to AS Asserted for DMA Bus tAIST tCLSA Cycle 3 o ojo 3 42 41 Asynchronous Input Setup Time to CLKOUT 1 Low Asynchronous Input Hold Time from CLKOUT Low 3 o al e al Of a AS to DACK Assertion Skew DACK to DONE Assertion Skew AS DACK DONE Width Asserted 200 AS DACK DONE Width Asserted Fast Termination Cycle NOTES The electrical specifications in this document for both the 8 39 and 16 78 MHz 9 3 3 V 0 3 V are preliminary and apply only to the appropriate MC68340V low voltage part C 1 3 o o ojo aja ala gt o 0 16 78 MHz specifications apply to the 68340 9 5 0 V 5 operation 25 16 MHz 5 0 V 5 electrical specifications are preliminary d For extended temperature parts T A 40 to 85 C These specifications are preliminary 1 Specification 4 for 16 78 MHz 9 3 3 V 0 3 V will be 8 ns CPU CYCLE DMA REQUEST DMA CYCLE S0 S1 52 53 54 55 50 51 52 53 54 55 CLKOUT DONE INPUT DRE AS 0 gt e DACK 7 Q DONE OUTPUT Figure 11 12 DMA Signal Timing Diagram MOTOROLA MC68340 USER S MANUAL 11 19 11 9 TIMER MODULE ELECTRICAL SPECIFICATIONS notes b c and corresponding to part operation GND 0 Vdc TA
494. struction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perform the specified arithmetic logic instruction using the specified addressing mode Footnotes indicate when to account for the appropriate fetch effective or fetch immediate EA times The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes DOO strueion O SUBQ FEA ADDI Rn ADDI FEA SUBI FEA CMPI Rn e X There is one bus cycle for byte and word operands and two bus cycles for long word operands For long word bus cycles add two clocks to the tail and to the number of cycles An fetch EA time must be added for this instruction FEA FEA OPER MOTOROLA MC68340 USER S MANUAL 5 105 5 7 3 7 BINARY CODED DECIMAL AND EXTENDED INSTRUCTIONS The BCD extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode No additional tables are needed to calculate total effective execution time for these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes ins
495. t If mastership of the bus is required during an RMC operation BERR must be used to abort the RMC sequence 3 6 5 Show Cycles The MC68340 can perform data transfers with its internal modules without using the external bus but when debugging it is desirable to have address and data information appear on the external bus These external bus cycles called show cycles are distinguished by the fact that AS is not asserted externally DS is used to signal address strobe timing in show cycles After reset show cycles are disabled and must be enabled by writing to the SHEN bits in the module configuration register see 4 3 2 1 Module Configuration Register MCR When show cycles are disabled the A31 A0 SIZx and R W signals continue to reflect internal bus activity However AS and DS are not asserted externally and the external data bus remains in a high impedance state When show cycles are enabled DS indicates address strobe timing and the external data bus contains data The following paragraphs are a state by state description of show cycles and Figure 3 26 illustrates a show cycle timing diagram Refer to Section 11 Electrical Characteristics for specific timing information 3 44 MC68340 USER S MANUAL MOTOROLA R BUS REQUEST G BUS GRANT A BUS GRANT ACKNOWLEDGE 5 SIGNAL TO BUS CONTROL B BUS CYCLE IN PROGRESS V BUS AVAILABLE TO BUS CONTROL Figure 3 25 Bus Arbitration State Diagram MOTORO
496. t Upper and Reset External Devices Lower Bounds Rotate Left and Right Clear Operand ROXL ROXR Rotate with Extend Left and Right Compare Return and Deallocate Compare Address Return from Exception Compare Immediate Return and Restore Compare Memory Return from Subroutine Compare Register against Upper Subtract Decimal with Extend and Lower Bounds Set Conditionally DBcc Test Condition Decrement and Stop Branch 16 Tests Subtract DIVS DIVSL Signed Divide Subtract Address DIVU DIVUL Unsigned Divide Subtract Immediate EOR Logical Exclusive OR Subtract Quick EORI Logical Exclusive OR Immediate Subtract with Extend EXG Exchange Registers Swap Data Register Halves EXT EXTB Sign Extend Test and Set Operand ILLEGAL Take Illegal Instruction Trap TBLS TBLSN Table Lookup and Interpolate JMP Jump Signed JSR Jump to Subroutine TBLU TBLUN Table Lookup and Interpolate LEA Load Effective Address Unsigned LINK Link and Allocate TRAPcc Trap Conditionally 16 Tests LPSTOP Low Power Stop TRAPV Trap on Overflow LSL LSR Logical Shift Left and Right TST Test UNLK 5 6 MC68340 USER S MANUAL MOTOROLA 5 1 7 1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS To maximize throughput for real time applications reference data is often particulated and stored in memory for quick access The storage of each data point would require an inordinate amount of memory The table instruction requires only a sample of data points stored in the array thus re
497. t be decremented by 2 if LG is set and SIZ indicates a remaining byte or word SIZ must be set to long All other fields should be left unchanged The bus controller uses the modified fault address and SIZ field to rerun the complete released write cycle Manipulating the stacked SSW can cause unpredictable results because RTE checks only the RR bit to determine if a bus cycle must be rerun Inadvertent alteration of the control bits could cause the bus cycle to be a read instead of a write or could cause access to a different address space than the original bus cycle If the rerun bus cycle is a read returned data will be ignored MOTOROLA MC68340 USER S MANUAL 5 57 5 5 3 2 3 Type Il Correcting Faults via RTE Instructions aborted because of a type Il fault are restarted upon return from the exception handler A fault handler must establish safe restart conditions If a fault is caused by a nonresident page in a demand paged virtual memory configuration the fault address must be read from the stack and the appropriate page retrieved An RTE instruction terminates the exception handler After unstacking the machine state the instruction is refetched and restarted 5 5 3 2 4 Type Ill Correcting Faults via Software Sufficient information is contained in the stack frame to complete MOVEM in software After the cause of the fault is corrected the faulted bus cycle must be rerun Perform the following procedures to complete an instruction throu
498. t contains the number of bytes left to transfer in a given block This register is accessible in either supervisor or user space The BTC can always be read or written to when the DMA module is enabled i e the STP bit in the MCR is cleared 1 BTC2 794 7B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 U Unaffected by reset Supervisor User 6 34 MC68340 USER S MANUAL MOTOROLA This register is decremented by 1 2 or 4 for each successful operand transfer from source to destination locations When the BTC decrements to zero and no error has occurred the CSR DONE bit is set In the external request mode the DONE handshake line is also asserted when the BTC is decremented to zero If the operand size is byte then the register is always decremented by 1 If the operand size is word and the starting count is even word the register is decremented by 2 If the operand size is word and the byte count is not multiple of 2 the CSR CONF bit is set and a transfer does not occur If the operand size is long word and the count is even long word then the register is decremented by 4 If the operand size is long word and the byte count is not a multiple of 4 the CSR CONF bit is set and a transfer does not occur If the STR bit is set with a zero count in the BTC the CONF bit is set and the STR bit is cleared When read this register always contains the count for the next access If a bus error terminates the transfer this
499. t control the pins used with the EBI Refer to the Section 3 Bus Operation for more information about the EBI For a list of pin numbers used with port A and port B see the pinout diagram in Section 12 Ordering Information and Mechanical Data Section 2 Signal Descriptions shows a block diagram of the port control circuits 4 3 5 1 PORT A PIN ASSIGNMENT REGISTER 1 PPARA1 PPARA1 selects between an address and discrete I O function for the port A pins Any set bit defines the corresponding pin to be an pin controlled by the port A data and data direction registers Any cleared bit defines the corresponding pin to be an address bit as defined in the following register diagram Bits set in this register override the configuration setting of PPARA2 The FF reset value of PPARA1 configures it as an input port This register can be read or written at any time PPARA1 015 7 6 5 4 3 2 1 0 PRTA7 6 5 PRTA4 2 1 PRTAO A31 30 29 28 27 26 25 A24 1 1 1 1 1 1 1 1 RESET Supervisor Only MOTOROLA MC68340 USER S MANUAL 4 33 4 3 5 2 PORT PIN ASSIGNMENT REGISTER 2 PPARA2 PPARA2 selects between an address and IACK function for the port A pins Any set bit defines the corresponding pin to be an output pin Any cleared bit defines the corresponding pin to be an address bit as defined in the register diagram Any set bits in PPARA1 o
500. t termination CSAM1 DC L 0000FFFO CSBAR1 DC L 00000005 CS2 external device OOFFE8xx external termination CSAM2 000000F3 CSBAR2 00FFE801 CS3 secondary memory 00000000 0003ffff 3 wait states 16 bit term CSAM3 DC L 0003FFFD CSBAR3 DC L 00000001 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk END 4 40 MC68340 USER S MANUAL MOTOROLA SECTION 5 CPU32 The CPU32 the first generation instruction processing module of the M68300 family is based on the industry standard MC68000 core processor It has many features of the MC68010 and MC68020 as well as unique features suited for high performance processor applications The CPU32 provides a significant performance increase over the MC68000 CPU yet maintains source code and binary code compatibility with the M68000 family 5 1 OVERVIEW The CPU32 is designed to interface to the intermodule bus IMB allowing interaction with other IMB submodules In this manner integrated processors can be developed that contain useful peripherals on chip This integration provides high speed accesses among the IMB submodules increasing system performance Another advantage of the CPU32 is low power consumption The CPUS2 is implemented in high speed complementary metal oxide semiconductor HCMOS technology providing low power use during normal operation During periods of inactivity the LPSTOP instruction can be executed shutti
501. ta Register PORTA eese 4 34 Port B Pin Assignment Register 4 35 Port B Data Direction Register 4 35 Port B Data Register PORTB 4 35 MC68340 Initialization Sequence eene 4 36 Ma Ic E I 4 36 SIMAO Module Configuration cese ier che de ett easet ses 4 36 SIM40 Example Configuration Code sess 4 38 Section 5 CPU32 e E E E eds 5 1 APS c iacu I ELM cute 5 2 Virtual Memory oh 5 2 Loop Mode Instruction Execution essen 5 3 MC68340 USER S MANUAL vii 11 2 95 Number viii SECTION 1 OVERVIEW UM Rev 1 0 TABLE OF CONTENTS Continued Page Title Number Vector Base BIBOISIBL E 5 4 terea tasa os 5 4 Addressing 5 5 Instruction ERE 5 5 Table Lookup and Interpolate 5 7 Low Power STOP Instruction s tac cette e pe xut cde 5 7 Processing
502. ta between internal peripherals external peripherals or memory without processor intervention The DMA module consists of two independent programmable channels Each channel has separate request acknowledge and done signals Each channel can operate in a single address or a dual address flyby mode In single address mode only one the source or the destination address is provided and a peripheral device such as a serial communications controller receives or supplies the data An external request must start a single address transfer In this mode each channel supports 32 bits of address and 8 16 or 32 bits of data In dual address mode two bus transfers occur one from a source device and the other to a destination device Dual address transfers can be started by either an internal or external request In this mode each channel supports 32 bits of address and 8 or 16 bits of data 32 bits require external logic The source and destination port size can be selected independently when they are different the data will be packed or unpacked An 8 bit disk interface can be read twice before the concatenated 16 bit result is passed into memory Byte word and long word counts up to 32 bits can be transferred All addresses and transfer counters are 32 bits Addresses increment or remain constant as programmed The DMA channels support two external request modes burst transfer and cycle steal Internal requests can be programmed to occup
503. tack Pointers Separate User and Supervisor State Address Spaces Separate Program and Data Address Spaces Many Data Types Flexible Addressing Modes Full Interrupt Processing Expansion Capability 5 2 1 Programming Model The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels User programs can only use the registers of the user model The supervisor programming model which supplements the user programming model is used by CPU32 system programmers who wish to protect sensitive operating system functions The supervisor model is identical to that of MC68010 and later processors The CPU32 has eight 32 bit data registers seven 32 bit address registers a 32 bit PC separate 32 bit SSP and USP a 16 bit SR two alternate function code registers and a 32 bit VBR see Figures 5 3 and 5 4 5 8 MC68340 USER S MANUAL MOTOROLA 31 DO D1 D2 D3 D4 D5 D6 D7 31 AO A1 A2 A4 A5 A6 31 16 31 Figure 5 3 User Programming Model 31 16 15 0 15 8 7 0 CCR SR 31 0 PC 31 2 0 SFC DFC MOTOROLA USP CCR 7 SSP DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER SUPERVISOR STACK POINTER STA
504. tained In the instruction execution time equations a zero should be used instead of a negative number Negative tails are used to adjust for slower fetches on slower buses Normally increasing the length of prefetch bus cycles directly affects the cycle count and tail values found in the tables In the following equations negative tail values are used to negate the effects of a slower bus The equations are generalized however so that they may be used on any speed bus with any tail value NEW OLD NEW CLOCK 2 IF INEW CLOCK 4 gt 0 THEN NEW CYCLE OLD CYCLE NEW CLOCK 2 NEW CLOCK 4 ELSE NEW CYCLE OLD CYCLE NEW _CLOCK 2 where NEW TAIL NEW CYCLE is the adjusted tail cycle at the slower speed OLD TAIL OLD CYCLE is the value listed in the instruction timing tables NEW CLOCK is the number of clocks per cycle at the slower speed Note that many instructions listed as having negative tails are change of flow instructions and that the bus speed used in the calculation is that of the new instruction stream 5 7 2 Instruction Stream Timing Examples The following programming examples provide a detailed examination of timing effects In all examples the memory access is from external synchronous memory the bus is idle and the instruction pipeline is full at the start 5 7 2 1 TIMING EXAMPLE 1 EXECUTION OVERLAP Figure 5 33 illustrates execution overlap caused by the bus controller s completio
505. tate 5 25 5 8 Bit Manipulation 210 440 1000 5 25 5 9 Binary Coded Decimal Operations sees 5 26 5 10 Program Control Operations pep e te ib ace bU p te o gebe 5 26 5 11 System Control 4 4 4 00 5 28 Aoondillan tS cona eec oci eade te mu D ttc 5 29 5 13 Standard Usage Entries esee 40000 5 30 5 14 Compressed Table 5 32 xxii MC68340 USER S MANUAL MOTOROLA 11 2 95 Table Page Number Title Number 5 15 8 Bit Independent Variable Entries esses 5 33 5 16 Exception Vector ASSIQDTTOHRIS susci tede pet ets 5 40 5 17 Exception Priority GIOUDS iden omoes ease dt kd tice 5 43 HMAC Gorntrolossacs oou dta ekle ges Le 5 50 5 19 BDM Source Summary ege ente bean tn scd io aD area deus 5 67 5 20 Polling the BDM Entry SODEGL iecit ded eee pee retta tens 5 68 5 21 CPU Generated Message Encoding c cccesceeceeeereeeeeeeeeeeeeseeeeceeseeeseneeeaeeeaes 5 70 5 22 Sizes Field EniGOdIhg 5 74 5 23 BDM Co
506. tched on the falling edge of S4 and the cycle terminates State 3 If DSACK is not recognized by the start of state 3 S3 the MC68340 inserts wait states instead of proceeding to states 4 and 5 To ensure that wait states are inserted both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2 If wait states are added the MC68340 continues to sample on the falling edges of the clock until one is recognized State 4 At the falling edge of state 4 54 the MC68340 latches the incoming data and samples DSACK s to get the port size State 5 The MC68340 negates AS and DS during state 5 S5 It holds the address valid during S5 to provide address hold time for memory systems R W SIZ1 and SIZO and FCS3 FCO also remain valid throughout S5 The external device keeps its data and DSACK signals asserted until it detects the negation of AS or DS whichever it detects first The device must remove its data and negate DSACK within approximately one clock period after sensing the negation of AS or DS DSACK signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle MOTOROLA MC68340 USER S MANUAL 3 17 3 3 2 Write Cycle During a write cycle the MC68340 transfers data to memory or a peripheral device Figure 3 8 is a flowchart of a word write cycle BUS MASTER SLAVE ADDRESS DEVICE SET RAW TO WRITE DRIVE ADDRESS ON A31 A0
507. te Once the DMA channel has started a dual address operand transfer it must complete that transfer before releasing ownership of the bus or servicing a request for another channel of equal or higher priority unless one of the bus cycles is terminated with a bus error during the transfer 6 6 3 Channel Termination The channel can terminate by normal completion or from an error The status of a DMA operation can be determined by reading the CSR The DMA channel can also interrupt the processor to inform it of errors normal transfer completion or breakpoints The fast termination option can also be used to provide a two clock access for external requests 6 6 3 1 CHANNEL TERMINATION The channel operation can be terminated for several reasons the BTC is decremented to zero a peripheral device asserts DONE during an operand transfer the STR bit is cleared in the a bus cycle is terminated with a bus error or a reset occurs 6 6 3 2 INTERRUPT OPERATION Interrupts can be generated by error termination of a bus cycle or by normal channel completion Specifically if the CCR interrupt error INTE bit is set and a bus error on source CCR BES bit bus error on destination CCR BED bit or configuration error CCR CONF bit is set the CCR IRQ bit is set In this case clearing the INTE BES BED or CONF bits causes the IRQ bit to be cleared If the interrupt normal CCR INTN bit is set and the CCR DONE bit is set the IRQ bit is set In
508. tected The RSTEN bit in the SYNCR controls whether an input signal loss causes a system reset or causes the device to operate in limp mode The SLOCK bit in the SYNCR indicates when the VCO has locked onto the desired frequency or if an external clock is being used 4 2 3 1 PHASE COMPARATOR AND FILTER The phase comparator takes the output of the frequency divider and compares it to an external input signal reference The result of MOTOROLA MC68340 USER S MANUAL 4 11 this compare is low pass filtered and used to control the VCO The comparator also detects when the external crystal or oscillator stops running to initiate the limp mode for the system clock The PLL requires an external low leakage filter capacitor typically in the range from 0 01 to 0 1 uF connected between the XFC and Vccsyn pins The capacitor should provide 50 MQ insulation but should not be electrolytic Smaller values of the external filter capacitor provide a faster response time for the PLL and larger values provide greater frequency stability For external clock mode without PLL the XFC pin can be left open 4 2 3 2 FREQUENCY DIVIDER The frequency divider circuits divide the VCO frequency down to the reference frequency for the phase comparator The frequency divider consists of 1 a 2 bit prescaler controlled by the W bit in the SYNCR and 2 a 6 bit modulo downcounter controlled by the Y bits in the SYNCR Several factors are important to the design of the
509. ted Function codes see Table 3 2 can be considered as extensions of the 32 bit address that can provide up to 16 different 4 Gbyte address spaces Function codes are automatically generated by the CPU32 to select address spaces for data and program at both user and supervisor privilege levels a CPU address space for processor functions and an alternate master address space User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information The S bit in the CPU32 status register is set for supervisor accesses and cleared for user accesses to provide differentiation Refer to 3 4 CPU Space Cycles for more information Table 3 2 Address Space Encoding _ 2 1 0 Address spaces o o o o Reserved motorin o o o 1 UserDaaspae o o 1 o userProgamspae o o f f 1 o t o Reserved Motorola _ 1 o 1 supervisor data Space _ t 1 f o Supervisor Program space o 1 or 1 cPuspe MOTOROLA MC68340 USER S MANUAL 33 3 1 3 Address Bus A31 A0 These signals are outputs that define the address of the byte or the most significant byte to be transferred during a bus cycle The MC68340 places the address on the bus at the beginning of a bus cycle The address is valid while AS is asserted 3 1 4 Address Strobe AS This output timing signal indicates the validity of
510. ted in this bus state NA Signal is not asserted in this state X Don t care S Signal was asserted in previous state and remains asserted in this state MOTOROLA MC68340 USER S MANUAL 3 33 3 5 1 Bus Errors BERR can be used to abort the bus cycle and the instruction being executed takes precedence over DSACK provided it meets the timing constraints described in Section 11 Electrical Characteristics If BERR does not meet these constraints it may cause unpredictable operation of the MC68340 If BERR remains asserted into the next bus cycle it may cause incorrect operation of that cycle When is issued to terminate a bus cycle the MC68340 can enter exception processing immediately following the bus cycle or it can defer processing the exception The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them If a bus error occurs on an instruction fetch the MC68340 does not take the exception until it attempts to use that instruction word Should an intervening instruction cause a branch or should a task switch occur the bus error exception does not occur The bus error condition is recognized during a bus cycle in any of the following cases e DSACK and HALT are negated and BERR is asserted e HALT and BERR are negated DSACKe is asserted BERR is then asserted within one clock cycle HALT remains negated e BERR HALT are asserted sim
511. tem Configuration and Protection 4 21 Module Configuration Register 4 21 Autovector Register AVE stt ttr brace 4 23 Reset Status Register RSR esses 4 23 Software Interrupt Vector Register 4 24 System Protection Control Register 4 24 Periodic Interrupt Control Register 4 26 Periodic Interrupt Timer Register 4 27 Software Service Register 5 2 22222 21 4 28 Clock Synthesizer Control Register SYNCR 4 28 Chip Select Registers ee 4 29 Base Address Registers esses 4 30 Address Mask Registers oio te lat a tM 4 31 Chip Select Registers Programming 4 33 External Bus Interface ace aeta irepl aedem 4 33 Port A Pin Assignment Register 1 1 4 33 Port A Pin Assignment Register 2 2 4 34 Port A Data Direction Register 4 34 Port A Da
512. ter CSR Clear the CSR by writing 7C into it The DMA cannot be started until the DONE BES BED CONF and BRKP bits are cleared Function Code Register FCR Encode the source and destination function codes Address Registers SAR and DAR e Write the source and destination addresses Byte Transfer Counter BTC Encode the number of bytes to be transferred Channel Control Register CCR Write a one to the start bit STR to allow the transfer to begin 6 9 2 DMA Channel Example Configuration Code The following are examples of configuration sequences for a DMA channel in single and dual addressing modes kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MC68340 basic DMA channel register initialization example code This code is used to initialize the 68340 s internal DMA channel registers providing basic functions for operation The code sets up channel 1 for external burst request generation single address mode long word size transfers Control signals are asserted on the DMA read cycle kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Example 1 External Burst Request Generation Single Address Transfers kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SIM40 equates kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk MBAR EQU 0003FF00 Address of SIM40 Module Base Address Reg MO
513. ternal clock of the same frequency connected to X1 The clock serves as the basic timing reference for the baud rate generator and other internal circuits The baud rate generator operates from the oscillator or external TTL clock input and is capable of generating 19 commonly used data communication baud rates ranging from 50 to 76 8k by producing internal clock outputs at 16 times the actual baud rate Refer to 7 2 Serial Module Signal Definitions and 7 3 1 Baud Rate Generator for additional information The external clock input SCLK which bypasses the baud rate generator provides a synchronous clock mode of operation when used as a divide by 1 clock and an asynchronous clock mode when used as a divide by 16 clock The external clock input allows the user to use SCLK as the only clock source for the serial module if multiple baud rates are not required 7 1 3 Internal Channel Control Logic The serial module receives operation commands from the host and in turn issues appropriate operation signals to the internal serial module control logic This mechanism allows the registers within the module to be accessed and various commands to be performed Refer to 7 4 Register Description and Programming for additional information 7 1 4 Interrupt Control Logic Seven interrupt request IRQ7 IRQ1 signals are provided to notify the CPU32 that an interrupt has occurred These interrupts are described in 7 4 Register Description and Programming T
514. th highly linear functions The table entries within the range of interest are listed in Table 5 14 MOTOROLA MC68340 USER S MANUAL 531 Table 5 14 Compressed Table Entries 512 1311 1966 Since the table is reduced from 257 to 5 entries independent variable X must be scaled appropriately In this case the scaling factor is 64 and the scaling is done by a single instruction LSR W 6 Thus Dx now contains the following bit pattern 31 16 15 0 NOT USED 0 000001 01 00 O 1 1 1 Table Entry Offset Dx 8 15 02 2 Interpolation Fraction 0 7 8E 142 Using this information the table instruction calculates dependent variable Y Y 1331 142 1966 1311 256 1674 The function chosen for Examples 1 and 2 is linear between data points If another function had been been used interpolated values might not have been identical 5 3 4 3 TABLE EXAMPLE 3 8 BIT INDEPENDENT VARIABLE This example shows how to use a table instruction within an interpolation subroutine Independent variable X is calculated as an 8 bit value allowing 16 levels of interpolation on a 17 entry table X is passed to the subroutine which returns an 8 bit result The subroutine uses the data listed in Table 5 15 based on the function shown in Figure 5 9 5 32 MC68340 USER S MANUAL MOTOROLA INDEPENDENT VARIABLE 1024 2048 302 4096 X INDEPENDENT VARIABLE Figure 5 9 Table Example 3 Table 5 15 8 Bit Indepe
515. the CS signal Table 4 10 DDx Encoding por Response 9 0 Zero Waitstate 9 onewaitstate twowaitstates PS1 PSO Port Size Bits 1 and 0 This field determines whether a given chip select responds with DSACK and if so what port size is returned Table 4 11 lists the encoding for the PSx bits Table 4 11 PSx Encoding Ces rm Mee Po fo ENENNENE T NNNM c mop gp _ Use only for 32 bit DMA transfers To use the external DSACK response PS1 PSO 11 should be selected to suppress internal DSACK generation The DDx bits then have no significance 4 32 MC68340 USER S MANUAL MOTOROLA 4 3 4 3 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE The following listing is an example of programming a chip select at starting address 00040000 for a block size of 256 Kbytes accessing supervisor and user data spaces with a 16 bit port requiring two wait states There will be no write protection no fast termination and no CPU space accesses base address 1 0004 base address 2 0013 address mask 1 0003 address mask 2 FF49 NOTE If an access matches multiple chip selects the lowest numbered chip select will have priority For example if CSO and CS2 overlap for a certain range CSO will assert when accessing the overlapped address range and CS2 will not 4 3 5 External Bus Interface Control The following paragraphs describe the registers tha
516. the SAR or the DAR contains an address that does not match the port size specified in the CCR and the BTC register does not match the larger port size or is zero 1 The CCR STR bit is set and a configuration error is present The CCR STR bit is set and no configuration error exists This bit is cleared by writing a logic one or by a hardware reset Writing a zero has no effect BRKP Breakpoint 1 The breakpoint signal was set during a DMA transfer 0 The breakpoint signal was not set during a DMA transfer This bit is cleared by writing a logic one or by a hardware reset Writing a zero has no effect Bits 1 O Reserved NOTE The CSR is cleared by writing 7C to its location The DMA channel cannot be started until the CSR DONE BES BED CONF BRKP bits are cleared MOTOROLA MC68340 USER S MANUAL 631 6 7 5 Function Code Register FCR The FCR contains the source and destination function codes for the channel This register is accessible in either supervisor or user space The FCR can always be read or written to when the DMA module is enabled i e the STP bit in the MCR is cleared FCR1 FCR2 78B 7AB 7 6 5 4 3 2 1 0 SFC DFC RESET U U U U U U U U U Unaffected by reset Supervisor User SFC Source Function Code Field This field can be used to specify the source access to a certain address space type The source function code bits are defined in Table 6 6 DFC Destination Function Code Field
517. the fault modifying the code prior to RTE can cause unexpected results 5 5 3 2 7 Type IV Correcting Faults via Software Bus error exceptions can occur during exception processing while the processor is fetching an exception vector or while it is stacking The same stack frame and SSW are used in both cases but each has a distinct fault address The stacked faulted exception format vector word identifies the type of faulted exception and the contents of the remainder of the frame A fault address corresponding to the vector specified in the stacked format vector word indicates that the processor could not obtain the address of the exception handler A bus error exception handler should execute RTE after correcting a fault RTE restores the internal machine state fetches the address of the original exception handler recreates the original exception stack frame and resumes execution at the exception handler address If the fault is intractable the exception handler should rewrite the faulted exception stack frame at SP 14 06 and then jump directly to the original exception handler The stack frame can be generated from the information in the bus error frame the pre exception SR SP 0C the format vector word SP 0E and if the frame being written is a six word frame the PC of the instruction causing the exception SP 10 The return PC value is available at SP 02 A stacked fault address equal to the current SP may ind
518. ting synchronously the data in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS 3 2 6 Fast Termination Cycles With an external device that has a fast access time the chip select circuit fast termination enable FTE can provide a two clock external bus transfer Since the chip select circuits are driven from the system clock the bus cycle termination is inherently synchronized with the system clock Refer to Section 4 System Integration Module for more information on chip selects When fast termination is selected the DD bits of the corresponding address mask register are overridden Fast termination can only be used with zero wait states To use the fast termination option an external device should be fast enough to have data ready within the specified setup time by the falling edge of S4 Figure 3 6 shows the DSACK timing for a read with two wait states followed by a fast termination read and write When using the fast termination option DS is asserted only in a read cycle not in a write cycle 50 S1 S2 53 SW SW SW SW S4 S5 50 S1 54 S5 50 S1 S4 S5 50 CLKOUT di QNEM x dE mp ME NE m e DSACKx r TWO WAIT STATES IN READ 3 FAST gt lt FAST TERMINATION TERMINATION READ WRITE DSACKx only internally asserted for fast termination cycles Figure 3 6 Fast Termination
519. tion TBL To maximize throughput for real time applications reference data is often precalculated and stored in memory for quick access The storage of sufficient data points can require an inordinate amount of memory The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points and thus conserves memory When the TBL instruction is executed the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them Byte word and long word operand sizes are supported The result can be rounded according to a round to nearest algorithm or returned unrounded along with the fractional portion of the calculated result byte and word results only This extra precision can be used to reduce cumulative error in complex calculations See 5 3 4 Using the TBL Instructions for examples 5 3 1 2 UNIMPLEMENTED INSTRUCTIONS The ability to trap on unimplemented instructions allows user supplied code to emulate unimplemented capabilities or to define special purpose functions However Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements See 5 5 2 8 Illegal or Unimplemented Instructions for more details 5 3 2 Instruction Format and Notation All instructions consist of at least one word Some instructions can have as many as seven words as shown in Figure 5 6 The first word of the instruction called t
520. to complete Once a bus request is recognized and the operand transfer begins both the source read cycle and or the destination write cycle occur before a new bus request may be honored even if the new bus request is of higher priority 6 6 2 1 INTERNAL REQUEST TRANSFERS Internally generated request transfers are accessed as two clock bus cycles The IMB can access on chip peripherals in two clocks The percentage of bus bandwidth utilization can be limited for internal request transfers 6 6 2 2 EXTERNAL REQUEST TRANSFERS In single address mode only one bus cycle is run for each request Since the operand size must be equal to the device port size in single address mode the number of normally terminated bus cycles executed during a transfer operation is always equal to the value programmed into the corresponding size field of the CCR The sequencing of the address bus follows the programming of the CCR and address register SAR or DAR for the channel MOTOROLA MC68340 USER S MANUAL 6 19 Each operand transfer in dual address mode requires from two to five bus cycles in response to each operand transfer request If the source and destination operands are the same size two cycles will transfer the complete operand If the source and destination operands are different sizes the number of cycles will vary If the source is a long word and the destination is a byte there would be one bus cycle for the read and four bus cycles for the wri
521. tovector CSO Enables peripherals at programmed addresses or Out In requests an automatic vector Bus Request BR O Indicates that an external device requires bus mastership In Bus Grant Indicates that current bus cycle is complete and the Out MC68340 has relinquished the bus Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus In mastership Data and Size DSACK1 Provides asynchronous data transfers and dynamic bus In Acknowledge DSACKO sizing Read Modify Write Cycle RMC Identifies the bus cycle as part of an indivisible read Out modify write operation Address Strobe Indicates that a valid address is on the address bus Data Strobe During a read cycle DS indicates that an external device should place valid data on the data bus During a write cycle DS indicates that valid data is on the data bus Size SIZ1 SIZO Indicates the number of bytes remaining to be transferred Out for this cycle Port B7 B6 B5 B3 IRQ5 IRQ3 becomes a parallel I O port Indicates an invalid bus operation is being attempted o h System Clock CLKOUT System clock out Crystal Oscillator EXTAL XTAL Connections for an external crystal or oscillator to the In Out internal oscillator circuit External Filter Capacitor XFC Connection pin for an external capacitor to filter the circuit of the phase locked loop 2 2 MC68340 USER S MANUAL MOTOROLA Table 2 1 Signal Index Continued Input Signal Name Output Clock Mode Select
522. transmitter enable command enables operation of the channel s transmitter The and TxRDY bits in the SR are also set If the transmitter is already enabled this command has no effect Transmitter Disable The transmitter disable command terminates transmitter operation and clears the and TxRDY bits in the SR However if a character is being transmitted when the transmitter is disabled the transmission of the character is completed before the transmitter becomes inactive If the transmitter is already disabled this command has no effect Do Not Use Do not use this bit combination because the result is indeterminate MOTOROLA MC68340 USER S MANUAL 7 29 RC1 RCO Receiver Commands These bits select a single command as listed in Table 7 8 Table 7 8 RCx Control Bits Cms o To 1 enable EN NENNEN Disable Receiver Do Not Use No Action Taken The no action taken command causes the receiver to stay in its current mode If the receiver is enabled it remains enabled if disabled it remains disabled Receiver Enable The receiver enable command enables operation of the channel s receiver If the serial module is not in multidrop mode this command also forces the receiver into the search for start bit state If the receiver is already enabled this command has no effect Receiver Disable The receiver disable command disables the receiver immediately Any chara
523. truction Head Cycles We mm m 2 s SECO Boe ADDX pue quom um meam p o 9 CMPM os o seo 5 106 MC68340 USER S MANUAL MOTOROLA 5 7 3 8 SINGLE OPERAND INSTRUCTIONS The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes NEGX Dn NOT Dn NOT NBCD Dn Scc Dn Scc CEA TAS Dn TAS CEA TST FEA X There is one bus cycle for byte and word operands and two bus cycles for long word operands For long word bus cycles add two clocks to the tail and to the number of cycles MOTOROLA MC68340 USER S MANUAL 5 107 5 7 3 9 SHIFT ROTATE INSTRUCTIONS The shift rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode Footnotes indicate when to account for the appropriate EA times The number of bits shifted does not affect the execution time unless noted The total number of clock cycles is outside the parentheses The numbe
524. ule should be disabled in a known state before setting the STP bit The STP bit should be set prior to executing the LPSTOP instruction to reduce overall power consumption 0 The channel operates in normal mode NOTE The DMA module uses only one STP bit for both channels A read or write to either MCR accesses the same STP control bit FRZ1 FRZO Freeze These bits determine the action taken when the FREEZE signal is asserted on the IMB when the CPUS2 has entered background debug mode The DMA module negates BR and keeps it negated until FREEZE is negated or reset Table 6 1 lists the action taken for each bit combination Table 6 1 FRZx Control Bits Ignore FREEZE Freeze on Boundary Reserved boundary is defined as bus cycle by the DMA module FRZi FRZO 0 1 Reseved egies E NOTE The DMA module uses only one set of FRZx bits for both channels A read or write to either MCR accesses the same FRZXx control bits 6 24 MC68340 USER S MANUAL MOTOROLA SE Single Address Enable This bit is implemented for future MC683xx family compatibility 1 In single address mode the external data bus is driven during a DMA transfer 0 In single address mode the external data bus remains in a high impedance state during a DMA transfer used for intermodule DMA In dual address mode the SE bit has no effect Bit 11 Reserved ISM2 ISMO Interrupt Service Mask These bits c
525. ultaneously indicating a retry When the MC68340 recognizes a bus error condition it terminates the current bus cycle in the normal way Figure 3 17 shows the timing of a bus error for the case in which DSACK lt is not asserted Figure 3 18 shows the timing for a bus error that is asserted after DSACK Exceptions are taken in both cases Refer to Section 5 CPU32 for details of bus error exception processing In the second case in which BERR is asserted after DSACK is asserted BERR must be asserted within the time specified for purely asynchronous operation or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACK is recognized If BERR is not stable at this time the MC68340 may exhibit erratic behavior BERR has priority over In this case data may be present on the bus but it may not be valid This sequence can be used by systems that have memory error detection and correction logic and by external cache memories 3 34 MC68340 USER S MANUAL MOTOROLA 50 52 SW SW 54 50 52 54 RW DSACKx N BERR N N 2 READ CYCLE WITH BUS gt gt INTERNAL gt lt lt STACK PROCESSING WRITE Figure 3 17 Bus Error without DSACK MOTOROLA MC68340 USER S MANUAL 3 35 50 52 54 50 52 54 CLKOUT RW N DS N N DSACKx eg 8 PE BERR
526. ure 10 9 illustrates this operation MOTOROLA MC68340 USER S MANUAL 10 5 ao Jf tf tf ty ti 50 Figure 10 9 8 bit Boot ROM Timing 10 2 2 Access Time Calculations The two time paths that are critical in an MC68340 application using the CS signals are shown in Figure 10 10 The first path is the time from address valid to when data must be available to the processor the second path is the time from CS asserted to when data must be available to the processor S0 S1 54 55 50 CLKOUT N t6 A31 A0 X D15 D0 Figure 10 10 Access Time Computation Diagram As shown in the diagram an equation for the address access time tApy can be developed as follows tADV tcyc Nc 0 5 ts9 1527 where system CLKOUT period Nc number of clocks per bus cycle CLKOUT high to address valid 30 ns maximum at 16 78 MHz 1527 data in valid to CLKOUT low setup 5 ns minimum at 16 78 MHz 10 6 MC68340 USER S MANUAL MOTOROLA An equation for the chip select access time tc Spy can be developed as follows tCSDV 1 159 1527 where System clock period Nc number of clocks per access CLKOUT low to CS asserted 30 ns maximum at 16 78 MHz 1527 data in valid to CLKOUT low setup 5 ns minimum at 16 78 MHz Using these equations the memory access times at 16 78 MHz are shown in Table 10 1 See Section 11 Electrical Characteristics for m
527. ure 4 2 System Configuration and Protection Function 4 2 2 1 SYSTEM CONFIGURATION Aspects of the system configuration are controlled by the MCR and the autovector register AVR The configuration of port B is controlled by the combination of the FIRQ bit in the MCR and the port B pin assignment register PPARB Port B pins can function as dedicated I O lines chip selects interrupts or autovector input For debug purposes internal bus accesses can be shown on the external bus This function is called show cycles The SHEN1 SHENO bits in the MCR control show cycles Bus arbitration can be either enabled or disabled during show cycles Arbitration for servicing interrupts is controlled by the value programmed into the interrupt arbitration IARB field of the MCR Each module that generates interrupts including the SIM40 has an IARB field The value of the IARB field allows arbitration during an IACK cycle among modules that simultaneously generate the same interrupt level No two modules should share the same IARB value The IARB must contain a value other than 0 for all modules that can generate interrupts interrupts with IARB 0 are discarded as extraneous SIM40 arbitrates for both its own interrupts and externally generated interrupts MOTOROLA MC68340 USER S MANUAL 4 5 There are eight arbitration levels for access to the intermodule bus The 5 40 is fixed at the highest level above the programmable level 7
528. us For a write operation the MC68340 drives the two most significant bytes of the operand on bits 15 0 of the data bus The slave device then reads the two most significant bytes of the operand bytes 0 and 1 from bits 15 0 of the data bus and asserts DSACK1 to indicate reception and a 16 bit port The MC68340 then decrements the transfer size counter by 2 increments the address by 2 and writes bytes 2 and 3 of the operand to bits 15 0 of the data bus MOTOROLA MC68340 USER S MANUAL 313 3 2 4 Bus Operation The MC68340 bus is asynchronous allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68340 Bus operation uses the handshake lines AS DS DSACK1 DSACKO BERR and HALT to control data transfers AS signals a valid address on the address bus and DS is used as a condition for valid data on a write cycle Decoding the SIZx outputs and lower address line AO provides strobes that select the active portion of the data bus The slave device memory or peripheral responds by placing the requested data on the correct portion of the data bus for a read cycle or by latching the data on a write cycle the slave asserts the DSACK1 DSACKO combination that corresponds to the port size to terminate the cycle Alternatively the SIM40 can be programmed to assert the DSACK1 DSACKO combination internally and respond for the slave If no slave responds or the access is invalid external control
529. us Exception Control Cycles for additional information on the use of these signals The internal bus monitor can be used to generate an internal bus error signal for internal and internal to external transfers If the bus cycles of an external bus master are to be monitored external BERR generation must be provided since the internal bus error monitor has no information about transfers initiated by an external bus master 3 1 7 3 AUTOVECTOR AVEC This signal can be used to terminate interrupt acknowledge cycles indicating that the MC68340 should internally generate a vector autovector number to locate an interrupt handler routine AVEC can be generated either externally or internally by the 5 40 see Section 4 System Integration Module for additional information AVEC is ignored during all other bus cycles 3 2 DATA TRANSFER MECHANISM The MC68340 supports byte word and long word operands allowing access to 8 and 16 bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACKO The MC68340 also supports byte word and long word operands allowing access to 8 and 16 bit data ports through the use of synchronous cycles controlled by the fast termination capability of the SIM40 3 2 1 Dynamic Bus Sizing The MC68340 dynamically interprets the port size of the addressed device during each bus cycle allowing operand transfers to or from 8 and 16 bit ports During an operand transfer cycle the slave device sign
530. ust be disabled The bus cycle termination response time is measured in clock cycles and the maximum allowable response time is programmable The bus monitor response time period ranges from 8 to 64 system clocks see Table 4 8 These options are provided to allow for different response times of peripherals that might be used in the system 4 2 2 3 DOUBLE BUS FAULT MONITOR A double bus fault is caused by a bus error or address error during the exception processing sequence The double bus fault monitor responds to an assertion of HALT on the internal bus Refer to Section 3 Bus Operation for more information The DBF bit in the reset status register RSR indicates that the last reset was caused by the double bus fault monitor The double bus fault monitor reset can be enabled by the DBFE bit in the SYPCR 4 2 2 4 SPURIOUS INTERRUPT MONITOR The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an IACK cycle Normally during an IACK cycle one or more internal modules recognize that the CPU32 is responding to interrupt request s and arbitrate for the privilege of returning a vector or asserting AVEC The SIM40 reports and arbitrates for externally generated interrupts This feature cannot be disabled 4 2 2 5 SOFTWARE WATCHDOG The SIM40 provides a software watchdog option to prevent system lock up in case the software becomes trapped in loops with no controlled exit Once enabled by the SWE bit in the SYPCR t
531. utput signals enable peripherals at programmed addresses These signals are inactive high not high impedance after reset CSO is the chip select for a boot ROM containing the reset vector and initialization program It functions as the boot chip select immediately after reset IRQ4 IRQ2 IRQ1 Interrupt request lines are external interrupt lines to the CPU32 These additional interrupt request lines are selected by the FIRQ bit in the module configuration register MOTOROLA MC68340 USER S MANUAL 2 5 Port B4 B2 B1 AVEC This signal group functions as three bits of parallel I O and the autovector input AVEC requests an automatic vector during an interrupt acknowledge cycle 2 6 INTERRUPT REQUEST LEVEL IRQ7 IRQ6 IRQ5 IRQ3 These pins can be programmed to be either prioritized interrupt request lines or port B parallel I O IRQ7 IRQ6 IRQ5 IRQ3 IRQ7 the highest priority is nonmaskable IRQ6 IRQ1 are internally maskable interrupts Refer to Section 5 CPU32 for more information on interrupt request lines Port B7 B6 B5 B3 These pins can be used as port B parallel I O Refer to Section 4 System Integration Module for more information on parallel I O signals 2 7 BUS CONTROL SIGNALS These signals control the bus transfer operations of the MC68340 Refer to Section 3 Bus Operation for more information on these signals 2 7 1 Data and Size Acknowledge DSACK1 DSACKO These two active low input signals allow asy
532. vailable At supervisor privilege level software can access the full SR The VBR contains the base address of the exception vector table in memory The displacement of an exception vector is added to the value in this register to access the vector table Alternate source and destination function code registers SFC and DFC contain 3 bit function codes The CPU32 generates a function code each time it accesses an address Specific codes are assigned to each type of access The codes can be used to select eight dedicated 4 Gbyte address spaces The instruction can use registers SFC and DFC to specify the function code of a memory address USER BYTE ub BYTE CONDITION CODE REGISTER 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR USER ZERO STATE OVERFLOW CARRY Figure 5 5 Status Register 510 MC68340 USER S MANUAL MOTOROLA 5 3 INSTRUCTION SET The following paragaphs describe the set of instructions provided in the CPU32 and demonstrate their use Descriptions of the instruction format and the operands used by instructions are included After a summary of the instructions by category a detailed description of each instruction is listed in alphabetical order Complete programming information is provided as well as a description of condition code computation and an instruction format summary The CPU32 instructions include machine functions f
533. ven by the bus master to indicate the number of operand bytes remaining to be transferred in the current bus cycle as noted in Table 2 4 Table 2 4 SIZx Signal Encoding UNE Pong Word 2 7 5 Read Write R W This active high output signal is driven by the bus master to indicate the direction of a data transfer on the bus A logic one indicates a read from a slave device a logic zero indicates a write to a slave device 2 8 BUS ARBITRATION SIGNALS The following signals are the bus arbitration control signals used to determine the bus master Refer to Section 3 Bus Operation for more information on these signals 2 8 1 Bus Request BR This active low input signal indicates that an external device needs to become the bus master 2 8 2 Bus Grant BG Assertion of this active low output signal indicates that the MC68340 has relinquished the bus 2 8 3 Bus Grant Acknowledge BGACK Assertion of this active low input indicates that an external device has become the bus master MOTOROLA MC68340 USER S MANUAL 2 7 2 8 4 Read Modify Write Cycle RMC This output signal identifies the bus cycle as part of an indivisible read modify write operation It remains asserted during all bus cycles of the read modify write operation to indicate that bus ownership cannot be transferred 2 9 EXCEPTION CONTROL SIGNALS These signals are used by the MC68340 to recover fr
534. ven until S2 State 0 The MC68340 drives R W low for a write cycle Depending on the write operation to be performed the address lines may change during SO State 1 In S1 the MC68340 asserts AS indicating a valid address on the address bus State 2 During S2 the MC68340 places the data to be written onto 015 00 State 3 The MC68340 asserts DS during S3 indicating stable data on the data bus As long as at least one of the DSACK signals is recognized by the end of S2 meeting the asynchronous input setup time requirement the cycle terminates one clock later If DSACK is not recognized by the start of 53 the MC68340 inserts wait states instead of 3 20 MC68340 USER S MANUAL MOTOROLA proceeding to S4 and S5 To ensure that wait states are inserted both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2 If wait states are added the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized The selected device uses R W DS SIZ1 SIZO and 0 to latch data from the appropriate section s of 015 08 and 07 00 5121 5140 AO select the data bus sections If it has not already done so the device asserts DSACK when it has successfully stored the data State 4 The MC68340 issues no new control signals during S4 State 5 The MC68340 negates AS and DS during S5 It holds the address and data valid during S5 to provide address
535. ver Transmitter USART Baud Rate Generators Modem Control MC68681 MC2681 Compatible 9 8 Mbits Sec Maximum Transfer Rate Two Independent Counter Timers 16 Bit Counter Up to 8 Bit Prescaler Multimode Operation 80 ns Resolution System Integration Module Incorporates Many Functions Typically Relegated to External PALs TTL and ASIC such as System Configuration External Bus Interface System Protection Periodic Interrupt Timer Chip Select and Wait State Generation Interrupt Response Generation Bus Arbitration Dynamic Bus Sizing EEE 1149 1 Boundary Scan JTAG Up to 16 Discrete Lines Power On Reset 32 Address Lines 16 Data Lines Power Consumption Control Static HCMOS Technology Reduces Power in Normal Operation Low Voltage Operation at 3 3 V 0 3 V MC68340V only Programmable Clock Generator Throttles Frequency Unused Peripherals Can Be Turned Off LPSTOP Provides an Idle State for Lowest Standby Current 0 16 78 MHz or 0 25 16 MHz Operation 144 Pin Ceramic Quad Flat Pack CQFP or 145 Pin Plastic Pin Grid Array PGA As a low voltage part the MC68340V can operate with a 3 3 V power supply MC68340 is used throughout this manual to refer to both the low voltage and standard 5 V parts since both are functionally equivalent 1 1 M68300 FAMILY The MC68340 is one of a series of components in the M6830
536. verride the configuration set in PPARA2 Bit 0 has no function in this register because there is no level 0 interrupt This register can be read or written at any time PPARA2 017 7 6 5 4 3 2 1 0 IACK7 IACK6 IACKS IACK4 IACK3 IACK2 IACK1 A31 A30 A29 28 A27 26 A25 RESET 0 0 0 0 0 0 0 0 Supervisor Only The IACK signals are asserted if a bit in PPARA2 is set and the CPU32 services an external interrupt at the corresponding level IACK signals have the same timing as address strobes NOTE Upon reset port A is configured as an input port 4 3 5 3 PORT A DATA DIRECTION REGISTER DDRA DDRA controls the direction of the pin drivers when the pins are configured as l O Any set bit configures the corresponding pin as an output Any cleared bit configures the corresponding pin as an input This register affects only pins configured as discrete This register be read or written at any time DDRA 013 7 6 5 4 3 2 1 0 GOO RESET 0 0 0 0 0 0 0 0 Supervisor User 4 3 5 4 PORT A DATA REGISTER PORTA PORTA affects only pins configured as discrete 1 A write to PORTA is stored in the internal data latch and if any port A is configured as an output the value stored for that bit is driven on the pin A read of PORTA returns the value at the pin only if the pin is configured as discrete input Otherwise the value read is the value stored in the internal data latch Thi
537. visor access S or programmable to exist in either supervisor or user space S U For the registers discussed in the following pages the number in the upper right hand corner indicates the offset of the register from the address stored in the module base address register The numbers on the top line of the register represent the bit position in the register The second line contains the mnemonic for the bit The numbers below the register represent the bit values after a hardware reset The access privilege is indicated in the lower right hand corner NOTE A CPU32 RESET instruction will not affect any of the SIM40 registers 4 18 MC68340 USER S MANUAL MOTOROLA ADDR FC 004 006 010 012 014 016 018 01A 01C 01E 020 022 024 026 040 042 044 046 048 04A 04C 04 050 052 054 056 058 05 05 05 MOTOROLA Oo 15 8 7 CLOCK SYNTHESIZER CONTROL REGISTER SYNCR RESET STATUS REGISTER RSR AUTOVECTOR REGISTER AVR RESERVED RESERVED RESERVED 0 000 S MODULE CONFIGURATION REGISTER MCR PORT A DATA PORTA PORT A DATA DIRECTION PORT A PIN ASSIGNMENT 1 DDRA PPRA1 RESERVED PORT A PIN ASSIGNMENT 2 PPRA2 RESERVED RESERVED RESERVED PORT B DATA PORTB PORTB1 PORT B DATA PORT B DATA DIRECTION DDRB RESERVED PORT B PIN ASSIGNMENT PPARB SW INTERRUPT VECTOR SWIV PERIODIC INTERRUP
538. with RISC processors The 2 is identical in all CPU32 based M68300 family products 1 2 2 Background Debug Mode A special operating mode is available in the CPU32 in which normal instruction execution is suspended while special on chip microcode performs the functions of a debugger 1 4 MC68340 USER S MANUAL MOTOROLA Commands are received over a dedicated high speed full duplex serial interface Commands allow the manual reading or writing of CPUS2 registers reading or writing of external memory locations and diversion to user specified patch code This background debug mode permits a much simpler emulation environment while leaving the processor chip in the target system running its own debugging operations 1 3 ON CHIP PERIPHERALS To improve total system throughput and reduce part count board size and cost of system implementation the M68300 family integrates on chip intelligent peripheral modules and typical glue logic These functions on the MC68340 include the SIM40 a DMA controller a serial module and two timers The processor communicates with these modules over the on chip intermodule bus IMB This backbone of the chip is similar to traditional external buses with address data clock interrupt arbitration and handshake signals Because bus masters like the 2 and peripherals and the 5 40 all on the chip the IMB ensures that communication between these modules is fully synchronized
539. x TBLSN B DI ADD L Dx Dm Long addition avoids problems with carry ADD L Dm DI ASR L 8 DI Move radix point BCC B L1 Fraction MSB in carry ADDQ B 1 DI L1 MOTOROLA MC68340 USER S MANUAL 5 35 5 3 4 5 Table Example 5 Surface Interpolations The various forms of table can be used to perform surface 3D TBLs However since the calculation must be split into a series of 2D TBLs the possibility of losing precision in the intermediate results is possible The following code sequence incorporating both TBLS and TBLSN eliminates this possibility LO MOVE W Dx DI Copy entry number and fraction number TBLSN B ea Dx TBLSN B ea DI TBLS W Dx DI Dm Surface interpolation with round ASR L 8 Dm Read just the result BCC B L1 No round necessary ADDQ B 1 DI Half round up L1 Before execution of this code sequence Dx must contain fraction and entry numbers for the two TBL and Dm must contain the fraction for surface interpolation The ea fields in the TBLSN instructions point to consecutive columns in a 3D table The TBLS size parameter must be word if the TBLSN size parameter is byte and must be long word if TBLSN is word Increased size is necessary because a larger number of significant digits is needed to accommodate the scaled fractional results of the 2D TBL 5 3 5 Nested Subroutine Calls The LINK instruction pushes an address onto the stack saves the stack address at which the address is stored and reserv
540. y 25 50 75 or 100 percent of the data bus bandwidth Interrupts can be programmed to postpone DMA completion The DMA module can sustain a transfer rate of 12 5 Mbytes sec in dual address mode and nearly 50 Mbytes sec in single address mode 25 16 MHz 8 4 and 33 3 Mbytes sec 16 78 MHz respectively The DMA controller arbitrates with the CPU32 for the bus in parallel with existing bus cycles and is fully synchronized with the CPU32 eliminating all delays normally associated with bus arbitration by allowing DMA bus cycles to butt seamlessly with CPU bus cycles 1 3 3 Serial Module Most digital systems use serial I O to communicate with host computers operator terminals or remote devices The MC68340 contains a two channel full duplex USART An on chip baud rate generator provides standard baud rates up to 76 8k baud independently to each channel s receiver and transmitter The module is functionally equivalent to the MC68681 MC2681 DUART MOTOROLA MC68340 USER S MANUAL 1 7 Each communication channel is completely independent Data formats be 5 6 7 or 8 bits with even odd or no parity and stop bits up to 2 in 1 16 increments Four byte receive buffers and two byte transmit buffers minimize CPU service calls A wide variety of error detection and maskable interrupt capability is provided on each channel Full duplex autoecho loopback local loopback and remote loopback modes can be selected Multidrop applications are sup
541. y remain stable until the falling edge of DSCLK One clock period after the synchronized DSCLK has been seen internally the updated counter value is checked If the counter has reached zero the receive data latch is updated from the input shift register At this same time the output shift register is reloaded with the not ready come again response Once the receive data latch has been loaded the CPU is released to act on the new data Response data overwrites the not ready response when the CPU has completed the current operation Data written into the output shift register appears immediately on the DSO signal In general this action changes the state of the signal from a high not ready response status bit to a low valid data status bit logic level However this level change only occurs if the command completes successfully Error conditions overwrite the not ready response with the appropriate response that also has the status bit set 5 70 MC68340 USER S MANUAL MOTOROLA CLKOUT FREEZE DSCLK DSI wow A UL UL UL UD INTERNAL SYNCHRONIZED DSCLK SYNCHRONIZED DSI DSO CLKOUT Figure 5 23 Serial Interface Timing Diagram A user can use the state change on DSO to signal hardware that the next serial transfer may begin A timeout of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design Har
542. y valid when the RxRDY bit is set Only a single FIFO position is occupied when a break is received Further entries to the FIFO are inhibited until the channel RxDx returns to the high state for at least one half bit time which is equal to two successive edges of the internal or external 1x clock or 16 successive edges of the external 16x clock The received break circuit detects breaks that originate in the middle of a received character However if a break begins in the middle of a character it must persist until the end of the next detected character time No break has been received FE Framing Error 1 0 A stop bit was not detected when the corresponding data character the FIFO was received The stop bit check is made in the middle of the first stop bit position The bit is valid only when the RxRDY bit is set No framing error has occurred PE Parity Error 7 24 1 When the with parity or force parity mode is programmed in the MR1 the corresponding character in the FIFO was received with incorrect parity When the multidrop mode is programmed this bit stores the received A D bit This bit is valid only when the RxRDY bit is set No parity error has occurred MC68340 USER S MANUAL MOTOROLA OE Overrun Error 1 One or more characters in the received data stream have been lost This bit is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting f

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