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ST62T10 Datasheet

1. ST6210B 15B 20B 25B 3 2 RESETS The MCU can be reset in three ways by the external Reset input being pulled low by Power on Reset by the digital Watchdog peripheral timing out 3 2 1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required The RESET pin may be pulled low in RUN WAIT or STOP mode This input can be usedto reset the MCU internal state and ensure a correct start up procedure The pin is active low and features a Schmitt trigger input The internal Reset signal is generated by adding a delay to the external signal Therefore even short pulses on the RESET pin are acceptable provided Vpp has completed its rising phase and that the oscillator is nunning correctly normal RUN or WAIT modes The MCU is keptin the Reset state as long as the RESET pin is held low If RESET activation occurs in the RUN or WAIT modes processing ofthe user pogram is stopped RUN moce only the Inputs and Outputs are con figured as inputs with pull up resistors and the main Oscillator is restarted When the level onthe RESET pin then goes high the initialization se quence is executed following expiry of the internal delay period If RESET pin activation occurs inthe STOP mode the oscillator starts up and all Inputs and Outputs are configured as inputs with pull up resistors When the level of the RESET pin the
2. 45 42 TIMER ostende 47 4 2 1 Timer Operating Modes 48 4 2 2 Gated Mode sepe rada RUN ES an E TER 48 4 2 3 Clock Input Mode eii EU A YE xev n Xx xu RUE e 48 4 2 4 Output Mode 48 4 2 5 Timer nterr pt iuge rrr MER AI aree ee ON CR E A 48 4 2 6 Application Notes me Gala conte ated ba DG eB MORE ba EE Ad 49 4 2 7 TimenrBReglsterS soc orco S RE upaya ai es XIX URP ga rU NEERU 49 43 A D CONVERTER ADC hrs 50 4 3 1 Application Notes 50 5 SOFTWARE 2 5 c 52 Dt STA ROHITECTURE y t mu eX E a 52 5 2 ADDRESSING MODES 0 0 hr rss 52 5 3 INSTRUCTION SET tr yuq cote ee dite E dee a eee ene Po Dead ett 35 53 6 ELECTRICAL CHARACTERISTICS ee eee 58 6 1 ABSOLUTE MAXIMUM RATINGS 00 00 cee ce cette eee 58 6 2 RECOMMENDED OPERATING CONDITIONS 0000 eee eee eee 59 6 3 DC TELECTRICAL CHARACTERISTICS 60 6 4 AC TELECTRICAL CHARACTERISTICS 61 6 5 READOUT PROTECTION FUSE 20 0c cece cece eee nnn nnn 63 7 GENERAL INFORMATION 64 7 1 PACKAGE MECHANICAL DATA 64 7 2 ORDERING INFORMATION 67 7 2 1 Transfer of Customer Code 67 7 2 2 Listing Generation and Verification 67 4 68 SGS THOMSON YA aa EECH 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The S
3. 11 7 GENERAL INFORMATION 0 0000 hh 3h n 3 n n nh 12 7 1 PACKAGE MECHANICAL DATA 12 7 2 ORDERING INFORMATION sasaa aeaaaee 15 2 68 57 SGS THOMSON AE S65 THOMSON Table of Contents S16210B 15B 20B 25B 0000000 17 T GENERAL DESCRIPTION ier eur a oe Ronin eee a Dati Cn nie LE Din 18 Tt VINTIRODUGTIONS a eU ed SR E uie REDE Vea E eee art pest 18 1 2 PIN DESCRIPTION ele dee TT ee ee Ee ee EEN 19 F 2iWMEMORYIMAP2 3t eee rt deep 20 1 3 1 Introduction rre teg cedem eg do eo 20 1 32 Program Pace a FRU aA SO a a E gus dua ott eee es 21 1 39 Data Space eet Re ges tt a UE 3 ex Pre d 21 1 9 4 StacK Space casey dal ds GR SER Xdou eva WNOWEEMEE NE Due bua TS US 22 1 3 5 Data Window Register DWR eae 23 2 CENTRAL PROCESSING UNIT 0 2 0 c e RR n hh hr 24 231 INIRODUGTION 2 2 hees CE VON age aoe bdo ebore TCU ER 24 22 GPU REGISTERS ci a p D aed 24 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 26 3 1 CLOCK SYSTEM Su uy ERE EE 26 SCT Main Oscillators Geet oe cuit oe EA a ok eer 26 3 1 2 Low Frequency Auxiliary Oscillator LFAO 27 3 1 3 Oscillator Safe Guard 27 9 2 RESETS aie ver Renee sales pale EELER EE eae ne rete bee Cues eet Gala 30 3 21 RESET INPUT 5t wets Sors o oia 30 KE Poweron Reset i3 anaes ds ES pu od RM ER dE 30 3 2 3 Watchdog Reset ira AA ne eae a 31 3 2
4. lings Pin Injection current positive All I O VDD 4 5V mA mA mA ling Pin Injection current negative All O VDD 4 5V Notes Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1 Within these limits clamping diodes are non conducting Voltages outside these limits are authorised provided injection current is kept within the specification 2 The total current through ports A and B combined may not exceed 50mA The total current through port C combined may not exceed 50mA If the application is designed with care and observing the limits stated above total current may reach 100mA THERMAL CHARACTERISTIC Symbol Test Conditions PDIP20 Wm Tw Mae Ee Pesoz e Pops o s Pos m Thermal Resistance 10 68 GS THOMSON D S65 THOMSON ST62T10 T15 T20 T25 ST62E20 E25 6 2 RECOMMENDED OPERATING CONDITIONS Value Ty Max 6 Suffix Version 85 Operating Supply Votage 3 aa v Programming Votage f 9 6 v Pin Injection Current positive Digital Input Vpp 4 5 to 5 5V 5 mA Analog Inputs Pin Injection Current negative Digital Input Vpp 4 5 to 5 5V 5 mA Analog Inputs Notes
5. If a total current of 1mA is flowing into a single analog channel or if the total current flowing into all the analog inputs is 1mA all resulting A D conversions will be shifted by 1 LSB If a total positive current is flowing into a single analog channel or if the total current flowing into all analog inputs is 5mA all the resulting conversions are shifted by 2 LSB Figure 6 MAXIMUM OPERATING FREQUENCY Fmax VERSUS SUPPLY VOLTAGE Doc Maximum FREQUENCY MHz FUNCTIONALITY IS NOT GUARANTEED IN THIS AREA 4 4 5 5 6 Supply Voltage V VRO1807H Note The shaded area is outside the recommended operating range device functionality is not guaranteed under these conditions vy SGS THOMSON YA aa EECH ST62T10 T15 T20 T25 ST62E20 E25 7 GENERAL INFORMATION 7 1 PACKAGE MECHANICAL DATA Figure 1 20 Pin Plastic Dual In Line Package 300 mil Width mm noes BE fas me e dejas ray Bep L ps wm pev T ET s pad E EEES rs EC pof Par ise A DE FS ref o e p EIL pe Fe e psp DLL pes a VROA1725 EU Number of Pins Figure 7 28 Pin Plastic Dual In Line Package 600 mil Width Fc o paolo fool p Fr p Fe Es ss E Pe pes re oj ale l T T L Fes E Fee wem CL Tal fos NumberofPins N Ss 12 68 57 SGS THOMSON J S65 THOMSON ST62T10 T15 T20 T25 ST62E20 E25 PACKAGE MECHANICAL DATA Cont d Figure 8 20 Pin
6. 2 JRNZ e 0100 1 pcr 2 JRNZ 3 e 0101 1 pcr 2 JRNZ y e 0110 1 pcr 2 JRNZ 7 0111 1 pcr 2 JRNZ 8 e 1000 1 pcr 2 RNZ 9 e 1001 1 pcr c o UA JRNC SET JRZ cat per b d per 2 JRNC RES JRZ MN pcr b d pcr 2 e e e e e e e SET JRZ 4 e b6 rr pcr b d pcr e e e e e e e lt TU a TU lt U 2 JRNC RES JRZ LC pcr b d pcr 2 JRNC SET JRZ D pcr b d pcr o x 2 JRNC RES JRZ a pcr b d pcr 2 JRNC SET JRZ W pcr b d pcr 1 1 1 1 1 c o c E v o SX 2 JRNC RES JRZ MN pcr b d pcr 2 JRNC SET JRZ E pcr b d pcr 2 JRNC RES JRZ W 1 pcr b d pcr 2 JRNC SET JRZ 1 pcr b d pcr sd prc o S2 o sie Abbreviations for Addressing Modes Legend dir Direct D Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement I imm Immediate b 3 Bit Address Cycle Mnemonic inh Inherent rr 1byte dataspace address Operand ext Extended nn 1 byte immediate data bd BitDirect abc 12bit address Bytes bt Bit Test ee 8 bit Displacement por Program Counter Relative Addressing Mode ind Indirect TF SGS THOMSON 7168 YA aa EECH ST6210B 15B 20B 25B 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages how ever it is advisable to take normal precaution to Power Considerations The average chip junc tion temperature Tj in Celsius can be o
7. THERMAL CHARACTERISTIC j fo PDIP20 ES LEE EE mes o 5 ps 1 1 5 Thermal Resistance 58 68 GS THOMSON D S65 THOMSON ST6210B 15B 20B 25B 6 2 RECOMMENDED OPERATING CONDITIONS Value Symbol anne L e Min Typ Max 6 Suffix Version 85 Operating Supply Votage 3 aa v Programming Votage f 9 6 v Pin Injection Current positive Digital Input Vpp 4 5 to 5 5V 5 mA Analog Inputs Pin Injection Current negative Digital Input Vpp 4 5 to 5 5V 5 mA Analog Inputs Notes If a total current of 1mA is flowing into a single analog channel or if the total current flowing into all the analog inputs is 1mA all resulting A D conversions will be shifted by 1 LSB If a total positive current is flowing into a single analog channel or if the total current flowing into all analog inputs is 5mA all the resulting conversions are shifted by 2 LSB Figure 29 Maximum Operating FREQUENCY Fmax Versus SUPPLY VOLTAGE Non Maximum FREQUENCY MHz 4 4 5 SUPPLY VOLTAGE V VR01807C Note The shaded area is outside the ST6210B ST6215B ST6220B and ST6225B recommended operating range device functionality is not guaranteed under these conditions TF SGS IMOMSON 1 o 5966 YA aa EECH ST6210B 15B 20B 25B 6 3 DC TELECTRICAL CHARACTERISTICS Ta 40 to 85 C unless otherwise specified Symbol Parameter Input Low
8. that the CPU is in Non Maskable Interrupt mode this prevents the initialisation routine from being interrupted The initialisation routine should there fore be terminated by a RETI instruction in order to revert to normal mode and enable interrupts If no pending interruptis present atthe end of the in itialisation routine the MCU will continue by processing the instruction immediately following the RETI instruction If however a pending inter rupt is present it will be serviced Figure 17 Reset and Interrupt Processing JP 2 BYTES 4 CYCLES RESET VECTOR INITIALIZATION ROUTINE RETI 1 BYTE 2 CYCLES VA00181 ST6 INTERNAL RESET COUNTER RESET 31 68 ST6210B 15B 20B 25B RESETS Cont d Table 2 Register Reset Status Register Address es Sus Comment Port Data Registers PA PB PC OCOh to 0C2h Port Direction Register PA PB PC OC4h to OC6h l Os are Inputs with pull up Port Option Register PA PB PC OCCh to OCEh I Os are Inputs with pull up Interrupt Option Register 0C8h Interrupts disabled Timer Status Control 0D4h Timer disabled X Y V W Register to 083h Accumulator Data RAM to OBFh Undefined Data ROM Window Register A D Result Register Timer Counter Register Timer Prescaler Register Maximum count loaded Watchdog Counter Register A D Control Register ODth A D in Stand by main oscillator on 32 68 Gr GS THOMSON J S65 THOMSON 3 3 DIGITAL WATCHDOG The dig
9. 6 7 8 9 A o Sy 65 THOMSON YA aa EECH ST6210B 15B 20B 25B PAO PA3 PA4 PA7 These 8 lines are organized as one UO port A Each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts PAO PA3 can also sink 20mA for direct LED driving while PA4 PA7 can be programmed as an alog inputs for the A D converter Note PA4 PA7 are not available on ST6210B ST6220B PBO PB7 These 8 lines are organized as one I O port B When the External STOP Mode Control option is disabled each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts and as analog inputs for the A D converter When the External STOP Mode Control option is enabled PBO output Mode is forced as open drain push pull output is not possible The other lines are unchanged PC4 PC7 These 4 lines are organized as one I O port C When the External STOP Mode Control option is disabled each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts and as analog inputs for the A D converter When the External STOP Mode Control is enabled PC7 output Mode is forced as open d
10. FFF FETCH INSTRUCTION VA000427 Sy 65 THOMSON YA aa EECH RESETS Cont d 3 2 3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets If the Watchdog register is not refreshed before an end of count condition is reached the internal reset will be activated This amongst oth er things resets the watchdog counter The MCU restarts just as though the Reset had been generated by the RESET pin including the built in stabilisation delay period 3 2 4 Application Notes No external resistor is required between Vpp and the Reset pin thanks to the built in pull up device The POR circuit operates dynamically in that it triggers MCU initialization on detecting the rising edge of Vpp The typical threshold is in the region of 2 volts but the actual value of the detected threshold depends on the way in which Vpp rises The POR circuit is NOT designed to supervise static or slowly rising or falling Vpp 3 2 5 MCU Initialization Sequence When a reset occurs the stack is reset the PC is loaded with the address of the Reset Vector lo cated in program ROM starting at address OFFEh A jump to the beginning of the user pro gram must be coded atthis address Following a Reset the Interrupt flag is automatically set so Figure 18 Reset Block Diagram 2 8kQ POWER ON RESET WATCHDOG RESET SGS THOMSON YA Winara EECH ST6210B 15B 20B 25B
11. the user can configure the microcontroller in WAIT mode because this mode minimises noise distur bances and power supply variations due to output switching Nevertheless the WAIT instruction should be executed as soon as possible after the beginning of the conversion because execution of the WAIT instruction may cause a small variation ofthe Vpp voltage The negative effect of this var iation is minimized at the beginning of the conver sion when the converter is less sensitive rather than at the end of conversion when the less sig nificant bits are determined The best configuration from an accuracy stand point is WAIT mode with the Timer stopped In deed only the ADC peripheral and the oscillator are then still working The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion It should be noted that waking Sy 65 THOMSON YA aa EECH ST6210B 15B 20B 25B up the microcontroller could also be done using the Timer interrupt but in this case the Timer will be working and the resulting noise could affect conversion accuracy A D Converter Control Register ADCR Address 0D1h Read Write T 0 sn eoc sta eos os 02 or f o Bit 7 EAI Enable A D Interrupt If this bitis set to 1 the A D interrupt vector 4 is enabled when EAI 0 the interrupt is disabled Bit 6 EOC End of conversion Read Only This read only bit indicates when a conversion has been completed
12. the ST6 instruction set can use the indirect registers as any other reg ister of the data space Short Direct Registers V W These two regis ters are used to save a byte in short direct ad dressing mode They can be addressed in Data space as RAM locations at addresses 82h V and 83h W They can also be accessed using the di rect and bit direct addressing modes Thus the ST6 instruction set can use the short direct regis ters as any other register of the data space Program Counter PC The program counter is a 12 bit register which contains the address of the next ROM location to be processed by the core This ROM location may be an opcode an oper and or the address of an operand The 12 bit length allows the direct addressing of 4096 bytes in Program space 0 01 TO 8MHz CONTROLLER CONTROL SIGNALS OPCODE VALUES PROGRAM ROM EPROM 24 68 INTERRUPTS DATA SPACE DATA ADDRESS READ LINE ADDRESS DECODER ES RAM EEPROM DATA ROM EPROM DEDICATIONS ACCUMULATOR RESULTS TO DATA SPACE WRITE LINE SGS THOMSON YA aa EECH CPU REGISTERS Cont d However if the program space contains more than 4096 bytes the additional memory in pro gram space can be addressed by using the Pro gram Bank Switch register The PC value is incremented after reading the ad dress of the current instruction To execute rela tive jumps the PC and the offset are shifted through the ALU where they ar
13. 1 ROM Protection The ST6210B ST6215B ST6220B and ST6225B Program Space can be protected against external read out of ROM contents when the READOUT PROTECTION mask option is chosen This option allows the user to blow a dedicated fuse on the sil icon by applying a high voltage at Vpp see de tailed information in the Electrical Specification Figure 6 ST6210B 15B Program Memory Map NOT IMPLEMENTED RESERVED USER PROGRAM MEMORY ROM 1824 BYTES SGS THOMSON YA Winara EECH ST6210B 15B 20B 25B Note Once the Read out Protection fuse is blown it is no longer possible even for SGS THOMSON to gain access to the ROM contents Returned parts with a blown fuse can therefore not be accepted 1 3 3 Data Space Data Space accommodates all the data necessary for processing the user program This space com prises the RAM resource the processor core and peripheral registers as well as read only data such as constants and look up tables in ROM Figure 7 ST6220B 25B Program Memory Map RESERVED USER PROGRAM MEMORY ROM 3872 BYTES RESERVED INTERRUPT VECTORS RESERVED NMI VECTOR USER RESET VECTOR 21 68 ST6210B 15B 20B 25B MEMORY MAP Cont d 1 3 3 1 Data ROM All read only data is physically stored in ROM memory which also accommodates the Program Space The ROM memory consequently contains the program code to be executed as well as the constants and look up tables req
14. 15B 20B 25B The following circuit can be used for this purpose Figure 34 Programming Circuit PROTECT T 1 iay ZPD15 15V VR02003 Note ZPD15 is used for overvoltage protection 63 68 ST6210B 15B 20B 25B 7 GENERAL INFORMATION 7 1 PACKAGE MECHANICAL DATA Figure 35 20 Pin Plastic Dual In Line Package 300 mil Width mm Lie 7 Pal use P a pep ps mpa T F CAEN E E rs pa pof Par ise E DES FS ref o bof p at DS Fe E Feo DLL pes e zm Fa res ss L Joss VR0A1725 Figure 36 28 Pin Plastic Dual In Line Package 600 mil Width ess moos Fom Fe e ua Fe ep ep E pes re oj Fes enr F I e Fes szopese see oss pest qs er esc ER E EA T L EE NER BC RN worse PE Tas Ka Number ofFins L m 64 68 GS THOMSON a D SGS THOMSON ST6210B 15B 20B 25B PACKAGE MECHANICAL DATA Cont d Figure 37 20 Pin Plastic Small Outline Package 300 mil Width mm inches bv Fs e rici ve a A 23 j 265joo93 oo OA oso ooo4 ong 033 o 51 o 013 o 020 c o23 o 32 0 0091 o o13 p i260 13 00fo 496 p 512 mMM E poo rekt Fa GOROM ko ess el ee ped Pe a TUN CIS zk Fe Ft os 127 Joore os eL te ILLA wenns Number of Ping Figure 38 28 Pin Plastic Small Outline Package 300 mil Width Cn was we e um el oi o
15. 4 3 2 1 0 CONTENTS ZZ DWR ST6210B 15B 20B 25B Data Window Register DWR Address 0C9h Write Only 7 0 ERES DWR5 DWR4 DWR3 DWR2 DWR1 DWRO Bit 7 2 This bit is not used Bit 6 0 DWR6 DWRO Data ROM Window Reg ister Bits These are the Data ROM Window bits that correspond tothe upper bits of the data ROM space Caution This register is undefined on reset Nei ther read nor single bit instructions may be used to address this register Note Care is required when handling the DWR register as it is write only For this reason it is not allowed to change the DWR contents while exe cuting interrupt service routine as the service rou tine cannot save and then restore its previous con tent If it is impossible to avoid the writing of this register in the interrupt service routine an image of this register must be saved in a RAM location and each time the program writes to the DWR it must write also to the image register The image register must be written first so if an interrupt oc curs between the two instructions the DWR is not affected PROGRAMSPACE ADDRESS READ DATASPACE ADDRESS 40h 7Fh Example DWR 28h ININSTRUCTION DATASPACE ADDRESS PROGRAMMEMORY ADDRESS A19h GF Sy 65 THOMSON YA aa EECH VR01573C 23 68 ST6210B 15B 20B 25B 2 CENTRAL PROCESSING UNIT 2 1 INT
16. Figure 11 illustrates various possible oscillator con figurations using an external crystal or ceramic res onator an external clock input an external resistor Rngr or the lowest cost solution using only the LFAO C 1 an C shouldhave a capacitance in the range 12to 22 pf for an oscillator frequency in the 4 8 MHz range Thevalue of RNET can beobtained by referring to Figure 31 and Figure 32 The internal MCU clock frequency f y7 is divided by 12 to drive the Timer the A D converter and the Watchdog timer and by 13 to drivethe CPU core as may be seen in Figure 14 With an 8MHz oscillator frequency the fastest machine cycle is therefore 1 625us A machine cycle is the smallest unit of time needed to execute any operation for instance to increment the Program Counter An instruction may require two four or five machine cycles for execution 3 1 1 Main Oscillator The oscillator configuration may be specified by se lecting the appropriate mask option When the CRYSTAL RESONATOR option is selected it must be used with a quartz crystal a ceramic resonator or an external signal provided on the OSCin pin WhentheRC NETWORK optionis selected the sys tem clock is generated by an external resistor The main oscillator can be turned off when the OSG ENABLED mask option is selected by set ting the OSCOFF bit of the ADC Control Register The Low Frequency Auxiliary Oscillator is auto matically started 26 68 GS TH
17. Level Voltage TIMER NMI RE SET pins Input High Level V Voltage IH TIMER NMI RE SET pins Hysteresis Volt Vhys age All Inputs Low Level Output Voltage TIMER pin High Level Output VoH Voltage TIMER pin Input Leakage m Current TIMER D NMI pins Input Leakage Vin Vpp Watchdog Res e Current RESET Vin Vpp No Watch Res H pin Vin Vss External Res Supply Current in Vreset Vss RESET Mode fosc 8MHz Vop 5 0V finr 8M Hz RUN Mode 2 Vpp 5 0V fiNr LFAO Supply Current in Vpp 3 0V finr 2MHz Supply Current in Vpp 5 0Vfiyr 8MHz 3 Vpp 5 0Vfinr fLFAO WAIT Mode Vpp 3 0V finy 2MHz Supply Current in lLoap OMA STOP Mode 9 Vpp 5 0V Notes 1 No watchdog reset activated 2 Allperipherals running 3 A D Converter in Stand by 4 Hysteresis voltage between switching levels 60 68 GS THOMSON SS e D S65 THOMSON ST6210B 15B 20B 25B 6 4 AC TELECTRICAL CHARACTERISTICS Ta 40 to 85 C unless otherwise specified Parameter Test Conditions Min Typ Max b Vpp 3 0V OSG disabled 2 Oscillator Frequency Vpn 4 5V OSG disabled 8 MHz f Maximum internal frequency VDD 3 0V 2 MHz OSG with OSG enabled Vpp 4 5V 4 Low Frequency Auxiliary Oscillator 290 299 sue t Oscillator Start up Time Ceramic Resonator 5 100 js SU at Power On 2 Cui Co 22pF Oscillator STOP mode tsus Recovery Time 2 8MHz Quartz CL1 C 2 22pF Supply Recovery Time R
18. Maximum Frequency for the device to work correctly 2 Actual Quartz Crystal Frequency at OSCin pin 3 Noise from OSCin 4 Resulting Internal Frequency VR001932 Figure 13 OSG Emergency Oscillator Principle Main Oscillator Emergency Oscillator Internal Frequency VR001933 28 68 sr GS THOMSON AE S65 THOMSON ST6210B 15B 20B 25B CLOCK SYSTEM Cont d Figure 14 Clock Circuit Block Diagram MAIN Watchdog OSCILLATOR Main Oscillator off Figure 15 Maximum Operating Frequency fmax versus Supply Voltage Vpp Maximum FREQUENCY MHz 8 ss SOC age ES ORR RRS elo lo N pas E aba SRR RRR RRR RS px R A RRAN ere RS AREA roses EN al o l SUPPLY VOLTAGE op Notes 1 Inthis area operation is guaranteed at the quartz crystal frequency 2 When the OSG is disabled operation in this area is guaranteed at the crystal frequency When the OSG is enabled operation in this area is guaranteed at a frequency of at least fosa Min 3 When the OSG is disabled operation in this area is guaranteed at the quartz crystal frequency When the OSG is enabled access to this area is prevented The internal frequency is kept a fosa 4 When the OSG is disabled operation in this area is not guaranteed When the OSG is enabled access to this area is prevented The internal frequency is kept at fosa SGS THOMSON 29 68 YA ieroeLeemontes
19. NMI VECTOR USER RESET VECTOR Reserved areas should be filled with OFFh 7 68 Sy 65 THOMSON YA aa EECH ST62T10 T15 T20 T25 ST62E20 E25 1 4 PARTICULARITIES OF OTP AND EPROM DEVICES OTP and EPROM devices are identical save for the package which in the EPROM device is fitted with a transparent window to allow erasure of memory contents by exposure to UV light Both OTP and EPROM parts may be programmed using programming equipment approved by SGS THOMSON 1 4 1 OTP EPROM Programming Programming mode is selected by applying a 12 5V voltage to the Vpp TEST pin during reset Programming of OTP and EPROM parts is fully described in the EPROM Programming Board User Manual 1 4 2 Eprom Erasure Thanks to the transparent window present in the EPROM package its memory contents may be erased by exposure to UV light 8 68 Erasure begins when the device is exposed to light with a wavelength shorter than 40004 It should be noted that sunlight as well as some types of artificial light includes wavelengths in the 3000 4000A range which on prolonged exposure can cause erasure of memory contents It is thus recommended that EPROM devices be fitted with an opaque label over the window area in order to prevent unintentional erasure The recommended erasure procedure for EPROM devices consists of exposure to short wave UV light having a wavelength of 2537A The minimum recommended integrated dose intensity x ex
20. PC contents are stored in the first level of the stack The normal interrupt lines are inhibited NMI still active The first internal latch is cleared The associated interrupt vector is loaded in the User User selected registers are saved within the in terrupt service routine normally on a software stack The source of the interrupt is found by polling the interrupt flags if more than one source is asso ciated with the same vector The interrupt is serviced Return from interrupt RETI Sy 65 THOMSON YA aa EECH ST6210B 15B 20B 25B MCU Automatically the MCU switches back to the nor mal flag set or the interrupt flag set and pops the previous PC value from the stack The interrupt routine usually begins by the identi fying the device which generated the interrupt re quest by polling The user should save the regis ters which are used within the interrupt routine in a software stack After the RETI instruction is exe cuted the MCU returns to the main routine Figure 22 Interrupt Processing Flow Chart NSTRUCT WAS NO LOAD PC FROM PAINS TRUGTIO INTERRUPT VECTOR A RETI FFC FFD Y ES IS THE CORE ALREADY IN NORMAL MODE Oo SET RRU N CLEAR PUSH THE INTERRUPT MASK PC INTO THE STACK SELECT SELECT PROGRAM FLAGS INTERNAL MODE FLAG POP THE STACKED PC Mel CHECK IF THERE IS NO AN INTERRUPT REQUEST AND INTERR
21. Plastic Small Outline Package 300 mil Width mm inches Ts ici e a A 235 j265 oo93 oo OA oso ooo4 ong 033 o 51 o 013 o o20 c o23 o 32 0 0091 o o13 p i260 13 00fo 496 p 512 mMM E poo rekt Fa GOROM ko ess el ee ped Pe a TUN CIS zk Fe Ft os 127 Joore os eL te ILLA wenns Number of Ping Figure 9 28 Pin Plastic Small Outline Package 300 mil Width Cn was we e um el oi ooaj og ol foo o og zl oi PS ad p of p Ey 0 050 o ojo CIS o RES wo o rales ES 10 65 0 3 7 60 o ES 2 NI spo E EE s e o o oa o gt jun ES DS Er 70 ES SE Ser 1 N 2 VR001726 vy SGS THOMSON dus YA aa EECH ST62T10 T15 T20 T25 ST62E20 E25 PACKAGE MECHANICAL DATA Cont d Figure 10 20 Pin Ceramic Dual In Line Package 300 mil Width VR0C1725 Figure 11 28 Ceramic Dual In Line Package 600 mil Width VR0B1725 mm Ss om asa Tuc s s PLE L ges Fr oso e pox ko Fe oso oss ppow jes Fc foz Jak ko P pep fro For os 127000 E Number of Pins CL T Hen L bes ar oso rajas oz Pe oso Skoda rer rir Pese poss Fc faze EECHER p F freo For ree EZE pos oss E HER FER IRE RE Ee Ss peajes Fa re faoof T oj _ rer 220 ferlo E La eas Tak Fa IB of ins _ SSS D S65 THOMSON ST62T10 T15 T20 T25 ST62E20 E25 7 2 ORDERING IN
22. This bit is automatically reset to 0 when the STA bit is written If the user is using the interrupt option then this bit can be used as an interrupt pending bit Data in the data conversion register are valid only when this bit is set to 1 Bit 5 STA Start of Conversion Write Only Writ ing a 1 to this bit will start a conversion on the se lected channel and automatically reset to 0 the EOC bit If the bitis set again when a conversion is in progress the present conversion is stopped and a new one will take place This bit is write on ly any attempt to read it will show a logical zero Bit 4 PDS Power Down Selection This bit acti vates the A D converter if set to 1 Writing a 0 to this bit will put the ADC in power down mode idle mode Bit 3 0 D3 DO Not used A D Converter Data Register ADR Address ODOh Read only 7 0 or os os os fos of or Bit 7 0 D7 DO 8 Bit A D Conversion Result 51 68 ST6210B 15B 20B 25B 5 SOFTWARE 5 1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum in short to provide byte efficient programming capability The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction Furthermore the program may branch to a selected address depending on the status of any bit of the Data
23. Timer comprising an 8 bit counter equipped with a 7 bit software programmable prescaler an 8 bit A D Converter with up to 16 analog inputs as I O pin alternate functions and a Digital Watchdog timer Figure 2 Block Diagram 8 BIT A D CONVERTER a TEST a INTERRUPT ROM Memory Size 1836 Bytes ST6210B 15B 3884 Bytes ST6220B 25B DATA RAM 64 Bytes POWER SUPPLY OSCILLATOR RESET 5 a o VppVss OSCin OSCout RESET 8 BIT CORE 18 68 a DATA ROM d USER SELECTABLE lt A The ST6210B ST6215B ST6220B and ST6225B devices feature various options such as a choice of Quartz Ceramic or RC oscillators an Oscillator Safe Guard circuit Read out Protection against unauthorised copying of program code and an External STOP Mode Control to offer optimum tradeoff between power consumption and noise immunity depending on the application These devices are well suited for automotive ap pliance and industrial applications The user pro grammable parts for program development are the ST62E20 and E25 which are pin compatible devices with 4Kbytes of EPROM eq P gt PAO PA3 20mA Sink PORTA PA4 P A7 Ain PORT B CJ P gt PB0 PB7 Ain L gt PORT C lt L P gt PC4 PC7 Ain NOT AVAILABLE ON ST6210B 20B TIMER DIGITAL WATCHDOG Sy 65 THOMSON YA aa EECH 1 2 PIN DESCRIPTION Vpp and Vgs Power is supplied to the MCU via these two pins Vpp is the power connection and Vss
24. in ROM Data ROM User selectable size in program ROM Data RAM 64 bytes ROM read out Protection m 12 20 I O pins fully programmable as Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input m 4 1 O lines can sink up to 20mA to drive LEDs or TRIACs directly m 8 bit Timer Counter with 7 bit programmable prescaler m Digital Watchdog m Oscillator Safe Guard m 8 bit A D Converter with 8 ST6210B ST6220B and 16 ST6215B ST6225B analog inputs m On chip Clock oscillator can be driven by Quartz crystal Ceramic resonator or RC network m Power on Reset m One external Non Maskable Interrupt m ST626x EMU Emulation and Development System connects to an MS DOS PC via an RS232 serial line DEVICE SUMMARY PDIP28 e PDIP20 PSO28 ST6210B ST6220B ST6215B ST6225B See end of Datasheet for Ordering Information July 1996 17 68 ST6210B 15B 20B 25B 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST6210B ST6215B ST6220B and ST6225B microcontrollers are members of the 8 bit HCMOS ST62xx family of devices which is targeted at low to medium complexity applications All ST62xx de vices are based on a building block approach a common core is surrounded by a number of on chip peripherals The ST6210B ST6215B ST6220B and ST6225B devices feature the following peripherals a
25. pull outputs or as analog inputs for the A D converter PC4 PC7 These 4 lines are organized as one I O port C Each line may be configured under soft ware control as inputs with or without internal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull outputs or as analog inputs for the A D converter Note PC4 PC7 are not available on ST62T10 T20 or E20 Figure 3 ST62T15 T25 E25 Pin Configuration Von Vss TIMER PAO OSCin PA1 OSCout PA2 NMI PA3 Ain PC7 PA4 Ain Ain PC6 PA5 Ain Ain PC5 PA6 Ain PA7 Ain PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain Ain PC4 Vpp TEST RESET Ain PB7 Ain PB6 Ain PB5 6 68 GS THOMSON D Ses THOMSON 1 3 MEMORY MAPS 1 3 1 Program Memory Maps Figure 4 ST62T10 T15 Program Memory Map NOT IMPLEMENTED RESERVED USER PROGRAM MEMORY OTP 1824 BYTES RESERVED Reserved areas should be filled with OFFh 1 3 2 Data Space Data Space accommodates all the data necessary for processing the user program This space com prises the RAM resource the processor core and peripheral registers as well as read only data such as constants and look up tables in OTP EPROM The Data Space is fully described and illustrated on page 21 ST62T10 T15 T20 T25 ST62E20 E25 Figure 5 ST62T20 T25 E20 E25 Program Memory Map RESERVED USER PROGRAM MEMORY OTP EPROM 3872 BYTES RESERVED INTERRUPT VECTORS RESERVED
26. se lected Bit 4 GEN Global Enable Interrupt When this bit is set to one all interrupts are enabled When this bit is cleared to zero all the interrupts exclud ing NMI are disabled When the GEN bitis low the NMI interruptis active but cannot cause a wake up from STOP WAIT modes This register is cleared on reset 38 68 Table 5 Interrupt Options Enables all interrupts N CLEARED GE Disables all interrupts Except NMI Rising edge mode on Port A Falling edge mode on Port A Level sensitive mode on Port B amp C CLEARED Falling edge mode on Port B amp C LES ESB 3 4 4 External Interrupt Operating Modes The NMI interrupt is associated with the external interrupt pin This pin is falling edge sensitive and the interrupt pin signal is latched by a flip flop which is automatically reset by the core at the be ginning of the non maskable interrupt service rou tine A Schmitt trigger is present on the NMI pin The user can choose to have an on chip pull up on the NMI pin by specifying the appropriate ROM mask option see Option List at the end of the Da tasheet The two interrupt sources associated with the fall ing rising edge mode of the external interrupt pins Port A vector 1 Port B amp C vector 2 are con nected to two internal latches Each latch is set when a falling rising edge occurs during the processing of the previous one will be processed as soon as the first one has been serv
27. space The carry bit is stored with the value of the bit when the SET or RES instruction is processed 5 2 ADDRESSING MODES The ST6 core offers nine addressing modes which are described in the following paragraphs Three different address spaces are available Pro gram space Data space and Stack space Pro gram space contains the instructions which are to be executed plus the data for immediate mode in structions Data space contains the Accumulator the X Y V and W registers peripheral and In put Output registers the RAM locations and Data ROM locations for storage of tables and con stants Stack space contains six 12 bit RAM cells used to stack the return addresses for subroutines and interrupts Immediate In the immediate addressing mode the operand of the instruction follows the opcode location As the operand is a ROM byte the imme diate addressing mode is used to access con stants which do not change during program exe cution e g a constant used to initialize a loop counter Direct In the direct addressing mode the address ofthe byte which is processed by the instruction is stored in the location which follows the opcode Direct addressing allows the user to directly ad dress the 256 bytes in Data Space memory with a single two byte instruction Short Direct The core can address the four RAM registers X Y V W locations 80h 81h 82h 83h in the short direct addressing mode In this case the in
28. to set the characteristics of the input pin interrupt pull up analog input these may be unintentionally reprogrammed de pending on the state of the input pins As a gener al rule it is better to limit the use of single bit in structions on data registers to when the whole port ST6210B 15B 20B 25B is in output mode In the case of inputs or of mixed inputs and outputs it is advisable to keep a copy of the data register in RAM Single bit instructions may then be used on the RAM copy after which the whole copy register can be written to the port data register SET bit datacopy LD a datacopy LD DRA a Care must also be taken to not use INC or DEC in structions on a port register when the 8 bits are not available on the devices The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed The lowest power con sumption is achieved by configuring I Os in input mode with well defined logic levels The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion Figure 25 Diagram showing Safe UO State Transitions Interrupt pull up Reset Output Open Drain Push pull Note xxx DDR OR DR Bits respectively Sy 65 THOMSON YA aa EECH Output Open Drain Push pull 45 68 ST6210B 15B 20B 25B 1 O PORTS Contd Table 8 I O Port Op
29. vectors are Jump addresses to the asso ciated service routine which reside in specific ar eas of Program space The following vectors are present The interrupt vector associated with the non maskable interrupt source is referred to as Inter rupt Vector 0 It is located at addresses OFFCh and OFFDh in Program space This vector is as sociated with the falling edge sensitive Non Maskable Interrupt pin NMI Sy 65 THOMSON YA aa EECH ST6210B 15B 20B 25B The interrupt vector associated with Port A pins is referred to as interrupt vector 1 It is located at addresses OFF6h OFF7h is named It can be programmed either as falling edge sensitive or as low level sensitive by setting the Interrupt Op tion Register IOR accordingly The interrupt vector associated with Port B and C pins is referred to as interrupt vector 2 Itis lo cated at addresses OFF4h OFF5h is named It can be programmed either as falling edge sensi tive or as rising edge sensitive by setting the In terrupt Option Register IOR accordingly Thetwo interrupt vectors located respectively at addresses OFF2h OFF3h and addresses OFFOh OFF1h are respectively known as Interrupt Vec tors 3 and 4 Vector 3 is associated with the TIMER peripheral and vector 4 with the A D Converter peripheral Each on chip peripheral has an associated inter rupt request flag TMZ forthe Timer EOC for the A D Converter which is set to 1 wh
30. wy SGS THOMSON ST62T10 T15 T20 125 JA MICROELECTRONICS ST62E20 E25 8 BIT OTP EPROM MCUs WITH A D CONVERTER 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 85 C Operating Temperature Range OTP PACKAGES Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability in OTP EPROM Data OTP EPROM User selectable size in program EPROM Data RAM 64 bytes m 12 20 I O pins fully programmable as Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input m 4 1 O lines can sink up to 20mA to drive LEDs or TRIACs directly m 8 bit Timer with 7 bit programmable prescaler and external input m Digital Watchdog m 8 bit A D Converter with 8 ST62T10 T20 E20 or 16 ST62T15 T25 E25 analog inputs m On chip Clock oscillator can be driven by Quartz crystal or Ceramic resonator EPROM PACKAGES m Power on Reset m One external Non Maskable Interrupt m ST626x EMU Emulation and Development System connects to an MS DOS PC via an RS232 serial line DEVICE SUMMARY Bytes Bytes ST62T10 1836 EA See end of Datasheet for Ordering Information ST62T20 3884 12 Seen 3 S t as m 20 sme 3 July 1996 1 68 Table of Contents ST62T10 T15 T20 T25 ST62E20 E25 1 1 GENERAL DESCRIPTION lli a EE 5 ded INTRODUCTIO
31. 1836 Bytes ROM 0000h 087Fh 0880h 0F9Fh OFAOh OFEFh Reserved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector OFFOh OFF7h OFF8h OFFBh OFFCh OFFDh OFFEh OFFFh Table 18 Program Memory Map for ST6220B amp ST6225B 3884 Bytes ROM 0000h 007Fh Reserved 0080h 0F9Fh User ROM OFAOh 0FEFh Reserved OFFOh OFF7h Interrupt Vectors OFF8h OFFBh Reserved OFFCh OFFDh NMI Interrupt Vector OFFEh OFFFh Reset Vector Note 1 Reserved Areas should be filled with FFh ROM WO Additional Features Temperature Range ST6210BB1 XXX URSUS 010 70 C ST6210BB6 XXX y 40 to 85 C SE ST6220BB1 XXX UE Lan s to 70 C ST6220BB6 XXX y WW to 85 C A D CONVERTER ST6220BM1 XXX ST6220BM6 XXX 3994 Bytes ST6225BB1 XXX ST6225BB6 XXX 9904 Bytes ST6215BM1 XXX ST6215BM6 XXX 1996 Byles ST6225BM1 XXX ST6225BM6 XXX 2884 Byles Note XXX is a 2 3 alphanumeric character code added to the generic sales type on receipt of a ROM code and valid options ST6215BB1 XXX ST6215BB6 XXX 1936 Eyes i SGS THOMSON YA aa EECH 0 to 70 C 40 to 85 C PSO20 Ww Cw to 70 C Ww Cw to 85 C 0 to 70 C 40 to 85 C PDIP28 ee d to 70 C ee d to 85 C 0 to 70 C 40 to 85 C PSO28 B m to 70 C B m to 85 C 67 68 ST6210B 15B 20B 25B Notes Information furnished is believed to be accurate and reliable However SGS THOMSON Microelectronics assumes no responsibility for the conseque
32. 4 Application Notes 31 3 2 5 MCU Initialization Sequence 31 3 9 DIGITAL WATCHDOG xr chop e aH Gea a kee did 33 3 3 1 Digital Watchdog Register DWDR 35 3 3 2 Application Notes ss Ee Phere aad RIN T eu a ee eae 35 3 4 INTERRUPTS rk est a rt AAA A P q ae ae 37 3 41 nterrupt Vectors cette aitor bee ewe Peewee vee eee a 37 3 4 2 Interrupt Priorities ui EEEE Bc Meee Deedee a Pee ats eee NY 37 3 4 3 Interrupt Option Register IOR 38 3 4 4 External Interrupt Operating Modes 38 3 4 5 Interrupt Procedure iss foun ds ae ideas er a Eee A Seed b Yeu Hew dew ds 39 3 5 POWER SAVING MODES 0 1 41 93 5 WAIT ModE 3o cardo eii 41 350 2 STOP Mode oxicorte rc a a H a irae dues 41 3 5 3 Exit from WAIT and STOP Modes ocococcccccc ns 42 SGS THOMSON 3 68 YA ierceLeemontes Table of Contents AON CHIP PERIPHERALS ie de en ro Sith eines o od 43 4 1 OBORTS erus a a Yu Lae NR ESAME E nS 43 4 1 1 Operating Modes cooooccocccco s 44 4 1 2 UO Port Option Registers 1 44 4 1 3 I O Port Data Direction Registers llle 44 4 1 4 I O Port Data Registers 44 4 1 5 Safe I O State Switching Sequence
33. DOUT bit is transferred to the TIMER pin when TMZ is set to one by software or due to counter decrement When TMZ is high the latch is trans parent and DOUT is copied to the timer pin When TMZ goes low DOUT is latched A write to the TCR register will predominate over the 8 bit counter decrement to 00h function i e if a write and a TCR register decrement to 00h occur simultaneously the write will take precedence and the TMZ bit is not set until the 8 bit counter reaches 00h again The values of the TCR and the PSC registers can be read accurately at any time 4 2 7 Timer Registers Timer Status Control Register TSCR Address 0D4h Read Write 7 0 Bit 7 TMZ Timer Zero bit A low to high transition indicates that the timer count register has decrement to zero This bit must be cleared by user software before starting a new count Bit 6 ETI Enable Timer Interrupt When set enables the timer interrupt request vector 3 If ETI 0 the timer interrupt is disabled If ETl 1 and TMZ 1 an interrupt request is gener ated Bit 5 TOUT Timers Output Control When low this bit selects the input mode for the TIMER pin When high the output mode is select ed SGS THOMSON YA aa EECH ST6210B 15B 20B 25B Bit 4 DOUT Data Output Data sent to the timer output when TMZ is set high output mode only Input mode selection input mode only Bit 3 PSI Prescaler Initialize Bit Used to initialize the p
34. EESE DX Minimum Pulse Width Vpp 5V T RESET pin NMI pin WR Input Capacitance Il Inputs Pins Output Capacitance All Outputs Pins Notes 1 Period for which Vpp has to be connected at OV to allow internal Reset function at next power up 2 This value is highly dependent on the Ceramic Resonator or Quartz Crystal used in the application Figure 30 Power on Reset Vpp 1 2V Typical OV ove III tsu 2048 cycles INTERNAL RESET t VA0295B SGS THOMSON 61 68 YA Vue EE ST6210B 15B 20B 25B Figure 31 RC Oscillator Er versus RNET Indicative Values The shaded area is outside the ST6210B ST6215B ST6220B and ST6225B recommended operating range device functionality is not guar anteed under these conditions Figure 32 RC Oscillator Fnr versus RNET Indicative Values Note The shaded area is outside the ST6210B ST6215B ST6220B and ST6225B recommended operating range device functionality is not guaranteed under these conditions 62 68 sr GS THOMSON J S65 THOMSON 6 5 READOUT PROTECTION FUSE If the ROM READOUT PROTECTION option is selected the waveform illustrated below must be applied to the TEST pin in order to blow the fuse Figure 33 Programming wave form 0 5s min 100 s max Le 150 s typ lt t VR02001 SGS THOMSON AE vence e montes ST6210B
35. ERNAL STOP MODE CONTROL should be chosen NMI should be high by default to allow STOP mode to be entered when the MCU is idle The NMI pin can be connected to PBO see Figure 20 to allow its state to be controlled by software PBO can then be used to keep NMI low while Watchdog protection is required orto avoid noise or key bounce When no more processing is re quired PBO is released and the device placed in STOP mode for lowest power consumption When software activation is selected and the Watchdog is not activated the downcounter may be used as a simple 7 bit timer remember that the bits are in reverse order The software activation option should be chosen only when the Watchdog counter is to be used as atimer To ensure the Watchdog has not been un expectedly activated the following instructions should be executed within the first 27 instructions WD 4 3 OFDH jrr 0 ldi WD 35 68 ST6210B 15B 20B 25B DIGITAL WATCHDOG Cont d These instructions test the C bit and Reset the Figure 20 A typical circuit making use of the MCU i e disable the Watchdog if the bit is set EXERNAL STOP MODE CONTROL feature i e if the Watchdog is active thus disabling the Watchdog In all modes a minimum of 28 instructions are ex ecuted after activation before the Watchdog can generate a Reset Consequently user software should load the watchdog counter within the first 27 instructions following Watchdog activation so
36. FORMATION Table 1 OTP Device Sales di Sales Type UO Pins Temperature range Package EAE Hardware Watchdog Hardware Watchdog STE2T10B6 SWD Go See ST62T20B6 SWD rot STeerMeSwD ECC Hardware Watchdog 3884 ST62T20M6 SWD Software Watchdog Watch Software Watchdog EE 5B6 HWD 1836 Hardware Watchdog ST62T15B6 SWD Software Watchdog Software Watchdog EET 3884 Hardware Watchdog Hardware Watchdog ST62T25B6 SWD Software Watchdog Software Watchdog GE RO 5M6 HWD 1836 Hardware Watchdog Hardware Watchdog IE 5M6 SWD Software Watchdog Software Watchdog ST62T25M6 HWD Se Hardware Watchdog Hardware Watchdog ST62T25M6 SWD Software Watchdog Software Watchdog 40 C TO 85 C PDIP28 Table 2 EPROM Device Sales Types EPROM Sales Type UO Pins Temperature range Package Bytes T62E20F1 HWD Hardware Watchd STGGEDFUSWD SEN EEN oftware atcnao 0 TO 70 C ST62E25F1 HWD 20 Hardware Watchdog ST62E25F1 SWD Software Watchdog CDIP28W vy SGS THOMSON YA aa EECH ST62T10 T15 T20 T25 ST62E20 E25 Notes 16 68 GS THOMSON A T D S65 THOMSON SGS THOMSON JA MICROELECTRONICS ST6210B 15B 20B 25B 8 BIT HCMOS MCU WITH A D CONVERTER 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 85 C Operating Temperature Range Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability
37. IT mode can be used when the user wants to reduce the MCU power consumption during idle periods while not losing track of time or the capa bility of monitoring external events The active os cillator main oscillator or LFAO is not stopped in order to provide a clock signal to the peripherals Timer counting may be enabled as well as the Timer interrupt before entering the WAIT mode this allows the WAIT mode to be exited when a Timer interrupt occurs The same applies to other peripherals which use the clock signal If the power consumption has to be further re duced the Low Frequency Auxiliary Oscillator LFAO can be used in place of the main oscillator if its operating frequency is lower If required the LFAO must be switched on before entering the WAIT mode SGS THOMSON YA aa EECH ST6210B 15B 20B 25B If the WAIT mode is exited due to a Reset either by activating the external pin or generated by the Watchdog the MCU enters a normal reset proce dure If an interrupt is generated during WAIT mode the MCU s behaviour depends on the state of the processor core prior to the WAIT instruction but also on the kind of interrupt request which is generated This is described in the following para graphs The processor core does not generate a delay following the occurrence of the interrupt be cause the oscillator clock is still available and no stabilisation period is necessary 3 5 2 STOP Mode If the Watchdog is d
38. N Ta Sp ae up A A ced a ach ham ae or 5 1 2 PINDESCRIPTION uc uyu suu yura as quya hh haha 6 1 32 MEMORY MAPS ie ti issuu EE wal NOR NE dee 7 1 3 1 Program Memory Maps ssaber eerd yi susu R Cu hr 7 1 9 2 Data Space Luychu payah kuah e OU te eae eMac ace KS 7 1 4 PARTICULARITIES OF OTP AND EPROM DEVICES 8 1 4 1 OTP EPROM Programming 8 1 4 2 ele E EEN 8 2 CENTRAL PROCESSING UNIT coococ a 9 241 INTRODUCTION cuicos e e qe Ae ales 9 2 2 GPU BEGISTERS ct Fee eee a s OL e EE dE EE 9 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES sees 9 3 1 CLOCK SYSTEM amp eerta ts theo bees a whi dae Rena 9 Bi2 RESETS uo e EP SEDE ERO ERO eap Cem Nata bags aree his 9 3 9 DIGITAL WATCHDOG ior dee ea Eco de A DW HERE E E 9 2 4 INTERRUPTS LA 2s tthe dus no D oA I cede Dese were tu Le pg duet ch 9 3 5 POWER SAVING MODES u zL pus kula hr 9 4 ON CHIP PERIPHERALS i 5 2 es ee a ee ham acm exe x CR RURSUS 9 Ste LEE em ee bebe Iden eR NND a task S dne beu dos 9 42 TIMER eere teri t Sexe ud eh S me Nauta ftus sta t a advan at ARBRES 9 4 3 AD CONVERTER ADG o T trie ama eos atte ceno tee eter EES 9 SOFTWARE gt MUI 9 5 1 STO ARCHITECTURE d prm Sere ee ana ae ae ene RR RU Recta 9 5 2 ADDRESSINGMOBES tns Pian A ENEE s 9 5 3 INSTRUCTION GET 9 6 ELECTRICAL CHARACTERISTICS eee n n nn nn 10 6 1 ABSOLUTE MAXIMUM RATINGS sssssesesee eee 10 6 2 RECOMMENDED OPERATING CONDITIONS
39. OMSON 2 X D GE Figure 11 Oscillator Configurations CRYSTAL R ESONATOR CLOCK CRYSTAL RESON ATOR mask option ST6xxx OSC OSC u Cu n Clo E E EXTERNAL CLOCK CRYSTAL RESONATOR mask option ST6xxx OSC OSCout RC NETWORK RC NETWORK mask option ST6xxx OSCin OSCout m INTEGRATED CLOCK CRYSTAL RESONATOR mask option OSG ENABLED mask option ST6xxx OSC OSC u m CLOCK SYSTEM Cont d Turning on the main oscillator is achieved by re setting the OSCOFF bit of the A D Converter Con trol Register or by resetting the MCU Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at fj pag clock frequency 3 1 2 Low Frequency Auxiliary Oscillator LFAO The Low Frequency Auxiliary Oscillator has three main purposes Firstly it can be used to reduce power consumption in non timing critical routines Secondly it offers a fully integrated system clock without any external components Lastly itacts as a safety oscillator in case of main oscillator failure This oscillator is available when the OSG ENA BLED mask option is selected In this case it au tomatically starts one of its periods after the first missing edge from the main oscillator whatever the reason main oscillator defective no clock cir cuitry provided main oscillator switched off User code normal interrupts WAIT and STOP in structions are pr
40. RODUCTION The CPU Core of ST6 devices is independent of the UO or Memory configuration As such it may be thought of as an independent central processor communicating with on chip UO Memory and Pe ripherals via internal address data and control buses In core communication is arranged as shown in Figure 9 the controller being externally linked to both the Reset and Oscillator circuits while the core is linked to the dedicated on chip pe ripherals via the serial data bus and indirectly for interrupt purposes through the control registers 2 2 CPU REGISTERS TheST6 Family CPU corefeatures six registers and three pairs of flags available to the programmer These are described in the following paragraphs Accumulator A The accumulator is an 8 bit general purpose register used in all arithmetic cal culations logical operations and data manipula tions The accumulator can be addressed in Data space as a RAM location at address FFh Thus the ST6 can manipulate the accumulator just like any other register in Data space Figure 9 ST6 Core Block Diagram Indirect Registers X Y These two indirect reg isters are used as pointers to memory locations in Data space They are used in the register indirect addressing mode These registers can be ad dressed in the data space as RAM locations at ad dresses 80h X and 81h Y They can also be ac cessed with the direct short direct or bit direct ad dressing modes Accordingly
41. Read Write T 0 Bit 7 0 Px7 Px0 Port A B and C Data Regis ters bits Co f o f o O ipt Win pulcup nomerupt Reset state 8 0 T ip No purr no interrupt I3 7e names i nr pt No pull up no interrupt PA0 PA3 pins Analog input PA4 PA7 PB0 PB7 PC4 PC7 pins 2 Output 20mA sink open drain output PAO PA3 pins Output Standard open drain output PA4 PA7 PBO PB7 PC4 PC7 pins Output 20mA sink push pull output PA0 PA3 pins Note X Don t care Device dependent 44 68 SGS THOMSON YA aa EECH 1 O PORTS Contd 4 1 5 Safe I O State Switching Sequence Switching the I O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur The recom mended safe transitions are illustrated in Figure 25 All other transitions are potentially risky and should be avoided when changing the l O operat ing mode asit is most likely that undesirable side effects will be experienced such as spurious inter rupt generation or two pins shorted together by the analog multiplexer Single bit instructions SET RES INC and DEC should be used with great caution on Ports A and B Data registers sincethese instructions make an implicit read and write back of the entire register In port input mode however the data register reads from the input pins directly and not from the data register latches Since data register informa tion in input mode is used
42. T62T10 T15 T20 and T25 devices are low cost members of the 8 bit HCMOS ST62xx family of microcontrollers which is targeted at low to me dium complexity applications All ST62xx devices are based on a building block approach a com mon core is surrounded by a number of on chip peripherals The ST62E20 device is an erasable EPROM ver sion of the ST62T20 device which may be used to emulate the T10 and T20 devices as well as the respective ST6210B and 20B ROM devices The ST62E25 device is an erasable EPROM ver sion of the ST62T25 device which may be used to emulate the T15 and T25 devices as well as the respective ST6215B and 25B ROM devices OTP and EPROM devices are functionally identi cal The ROM based versions offer the following additional features RC Oscillator Oscillator Safe Figure 1 Block Diagram 8 BIT A D CONVERTER TEST Vpp TEST INTERRUPT er OTP EPROM Memory Size 1836 Bytes ST62T10 T15 3884 Bytes ST62T20 T25 E20 E25 V BOWER OSCILLATOR RESET um O VppVss OSCin OSCout RESET DATA ROM ER SELECTABLE GA DATA RAM 64 Bytes dck 8 BIT CORE Sy 65 THOMSON YA ae EECH ST62T10 T15 T20 T25 ST62E20 E25 guard external Stop mode control program code readout protection and the possibility of having an internal pullup on the NMI and TIMER pins OTP devices offer all the advantages of user pro grammability at low cost which make them the idea
43. The Carry flag is also set to the value of the bit tested in a bit test instruction it also partic ipates in the rotate left instruction The Zero flag is set if the result of the last arithme tic or logical operation was equal to zero other wise it is cleared Switching between the three sets of flags is per formed automatically when an NMI an interrupt or a RETI instructions occurs As the NMI mode is SGS THOMSON YA aa EECH ST6210B 15B 20B 25B automatically selected after the reset of the MCU the ST6 core uses at first the NMI flags Stack The ST6 CPU includes a true LIFO hard ware stack which eliminates the need for a stack pointer The stack consists of six separate 12 bit RAM locations that do not belong to the data space RAM area When a subroutine call or inter rupt request occurs the contents of each level are shifted into the next higher level while the content of the PC is shifted into the first level the original contents of the sixth stack level are lost When a subroutine or interrupt return occurs RET or RETI instructions the first level register is shift ed back into the PC and the value of each level is popped back into the previous level Since the ac cumulator in common with all other data space registers is not stored in this stack management of these registers should be performed within the subroutine The stack will remain in its deepest position if more than 6 nested calls or int
44. UPT MASK VA0000 14 39 68 ST6210B 15B 20B 25B INTERRUPTS Cont d Table 6 Interrupt Requests and Mask Bits Address Interrupt GENERAL IOR C8 GEN All Interrupts excluding NMI ee recn m En IMZ TIMER Overflow AID CONVERTER Figure 23 Interrupt Block Diagram INT 40 NMI FFC D Ig Start PORTA FROM REGISTER PORT A B C INT 1 FF6 7 SINGLE BIT ENABLE f RESTART FROM IOR REG C8H bit 6 STOP WAIT INT 42 FF4 5 IOR REG C8H bit 5 TMZ INT 3 FF2 3 TIMER E KL EAI INT 4 FFO 1 A D CON coc VA0H426 40 68 CS THOMSON ES AAA D S65 THOMSON 3 5 POWER SAVING MODES The WAIT and STOP modes have been imple mented in the ST62xx family of MCUS in order to reduce the product s electrical consumption dur ing idle periods These two power saving modes are described in the following paragraphs In addition the Low Frequency Auxiliary Oscillator LFAO can be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes 3 5 1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed The microcontroller can be considered as being in a software frozen state where the core stops processing the pro gram instructions the RAM contents and periph eral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage In this mode the peripherals are still ac tive WA
45. analog input via the Op tion and Data registers refer to I O ports descrip tion for additional information Only one I O line must be configured as an analog input at any time The user must avoid any situation in which more than one I O pin is selected as an analog input si multaneously to avoid device malfunction The ADC uses two registers in the data space the ADC data conversion register ADR which stores the conversion result and the ADC control regis ter ADCR used to program the ADC functions A conversion is started by writing a 1 to the Start bit STA in the ADC control register This auto matically clears resets to 0 the End Of Conver sion Bit EOC When a conversion is complete the EOC bit is automatically set to 1 in order to flag that conversion is complete and that the data inthe ADC data conversion register is valid Each conversion has to be separately initiated by writing to the STA bit The STA bit is continuously scanned sothat ifthe user sets itto 1 while a previous conversion is in progress a new conversion is started before com pleting the previous one The start bit STA is a write only bit any attempt to read it will show a log ical 0 The A D converter features a maskable interrupt associated with the end of conversion This inter rupt is associated with interrupt vector 4 and oc curs when the EOC bit is set i e when a conver sion is completed The interrupt is mas
46. ata space It allows di rect reading of 64 consecutive bytes located any where in ROM memory between address 0000h and 1FFFh top memory address depends on the specific device All the ROM memory can there fore be used to store either instructions or read only data Indeed the window can be moved in steps of 64 bytes along the ROM memory by writing the appropriate code in the Write only Data Win dow register DWR register location 00C9h The DWR register can be addressed like any RAM location in the Data Space at address 00C9h it is however a write only register and cannot be ac cessed using single bit operations This register is used to move the 64 byte read only data window from address 40h to address 7Fh of the Data space up and down the ROM memory of the MCU in steps of 64 bytes The effective address of the byte to be read as data in ROM memory is ob tained by concatenating the 6 least significant bits of the register address given in the instruction as least significant bits and the content of the DWR register as most significant bits see Figure 8 So when addressing location 0040h of the Data Space with 0 loaded in the DWR register the physical location addressed in ROM is 00h The DWR register is not cleared on reset therefore it must be written to prior to the first access to the Data ROM window area Figure 8 Data ROM Window Memory Addressing DATAREAD ONLY MEMORY 13 12 11109 8 7 6 WINDOW REGISTER 7 6 5
47. ate Direct Short Direct Extended Program Counter Relative Bit Direct Bit Test amp Branch In direct and Inherent For a complete description of the available addressing modes refer to page 52 5 3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which when combined with nine addressing modes yield 244 usable opcodes these may be subdivided into six types load store arithme tic logic conditional branch control jump call and bit manipulation For further details refer to page 53 9 68 ST62T10 T15 T20 T25 ST62E20 E25 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices designed to protect the inputs against damage due to high static volt ages however it is advisable to take normal pre Power Considerations The average chip junc tion temperature Tj in degrees Celsius can be ob tained from cautions to avoid applying voltages higher than the specified maximum ratings For proper operation it is recommended that V and Vo be higher than Vss and lower than Vpp Reliability is enhanced if unused inputs are con nected to an appropriate logic voltage level Vpp or Vss Tj TA Pp x RinJA Where Ta Ambient Temperature Rinya Package thermal resistance junction to ambient Pp Pint Pport Pint Ipp X Vpp chip internal power Poort Port power dissipation to be determined by the user Syme ICI T value Dn _ v 5
48. btained from avoid application of any voltage higher than the specified maximum rated voltages For proper operation it is recommended that V and Vo be higher than Vss and lower than Vpp Reliability is enhanced if unused inputs are con nected to an appropriate logic voltage level Vpp or Vss Tj TA PD x RthJA Where TA Ambient Temperature RthJA Package thermal resistance junc tion to ambient PD Pint Pport Pint IDD x VDD chip internal power Pport Port power dissipation determined by the user Pea Vals Unt o Curent Dran per Pin Excluding VOD W5S m Pin Injection current positive All 1 0 VDD 4 5V Pin Injection current negative All O VDD 4 5V Notes Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This isa stress rating only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1 Within these limits clamping diodes are guarantee to be not conductive Voltages outside these limits are authorised as long as injection current is kept within the specification 2 The total current through ports A and B combined may not exceed 50mA The total current through port C may not exceed 50mA If the application is designed with care and observing the limits stated above total current may reach 100mA
49. d used to perform the arithmetic calculations and dressing mode In CLR DEC INC instructions the logic operations In AND ADD CP SUB instruc operand can be any of the 256 data space ad tions one operand is always the accumulator while dresses In COM HLC SLA the operand is al the other can be either a data space memory con ways the accumulator Table 12 Arithmetic amp Logic Instructions ADD A X Indirect ADD A Y Indirect ADD A rr me DOE mme 2 AND A X GE AND A Y Indirect ANDA rr Gen CLR A Shai Direct EE ee IC den Indirect me OPA RN Images 2 Gu Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect d oe eee ee SLAA i SUB A X Indirect SUB A Y Indirect SUB A rr me SUBI A N mmdae 2 4 4 J a Notes X Y Indirect Register Pointers V amp W Short Direct RegistersD Affected Immediate data stored in ROM memory Not Affected rr Data space register O ND IN IN ro zt IW 7 1 1 1 2 2 4 1 1 1 1 1 2 2 1 1 A A SS SIE AED SS BDO P P P P P P P PIP P P P b b bp D k z l IW 54 68 GS THOMSON FETTE 2 D S65 THOMSON INSTRUCTION SET Cont d Conditional Branch The branch instructions achieve a branch in the program when the select ed condition is met Bit Manipulation Instructions Th
50. des yield 244 usable opcodes They can be di vided into six different types load store arithme tic logic conditional branch control instructions jump call and bit manipulation The following par agraphs describe the different types All the instructions belonging to a given type are presented in individual tables Table 11 Load amp Store Instructions Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect LD Y A LDI A N Immediate LDI rr N Immediate Notes X Y Indirect Register Pointers V amp W Short Direct Registers Immediate data stored in ROM memory rr Data space register A Affected Not Affected SGS THOMSON YA aa EECH ST6210B 15B 20B 25B Load amp Store These instructions use one two or three bytes in relation with the addressing mode One operand is the Accumulator for LOAD andthe other operand is obtained from data memory us ing one of the addressing modes For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Opa a aA pop A a odo a Dib gt bp bp b b b b p p pb b b b 53 68 ST6210B 15B 20B 25B INSTRUCTION SET Cont d Arithmetic and Logic These instructions are tent or an immediate value in relation with the a
51. e added the result is then shifted back into the PC The program counter can be changed in the following ways JP Jump instructionPC Jump address CALL instructionPC Call address Relative Branch Instruction PC PC offset Interrupt PC Interrupt vector ResetPC Reset vector RET amp RETI instructionsPC Pop stack Normal instructionPC PC 1 Flags C Z The ST6 CPU includes three pairs of flags Carry and Zero each pair being associated with one of the three normal modes of operation Normal mode Interrupt mode and Non Maskable Interrupt mode Each pair consists of a CARRY flag and a ZERO flag One pair CN ZN is used during Normal operation another pair is used dur ing Interrupt mode Cl ZI anda third pair is used in the Non Maskable Interrupt mode CNMI ZN MI The ST6 CPU uses the pair of flags associated with the current mode as soon as an interrupt or a Non Maskable Interrupt is generated the ST6 CPU uses the Interrupt flags resp the NMI flags instead of the Normal flags When the RETI in struction is executed the previously used set of flags is restored It should be noted that each flag set can only be addressed in its own context Non Maskable Interrupt Normal Interrupt or Main rou tine The flags are not cleared during context switching and thus retain their status The Carry flag is set when a carry or a borrow oc curs during arithmetic operations otherwise it is cleared
52. en the pe ripheral generates an interrupt request Each on chip peripheral also has an associated mask bit ETI for the Timer EAI for the A D Converter which must be set to 1 to enable the associated interrupt request 3 4 2 Interrupt Priorities The Non Maskable Interrupt request has the high est priority and can interrupt any interrupt routine at any time the other four Interrupts cannot inter rupt each other If more than one interrupt request is pending these are processed by the processor core according to their priority level vector 1 has the higher priority while vector 4 the lower The priority of each interrupt source is fixed 37 68 ST6210B 15B 20B 25B IINTERRUPTS Cont d 3 4 3 Interrupt Option Register IOR The Interrupt Option Register IOR is used to en able disable the individual interrupt sources and to selectthe operating mode of the external interrupt inputs This register is write only and cannot be accessed by single bit operations Address 0C8h Write Only Reset status 00h 7 0 Bit 7 Bits 3 0 Unused Bit 6 LES Level Edge Selection bit When this bit is set to one the interrupt 1 Port A is low level sensitive when cleared to zero the negative edge sensitive interrupt is selected Bit 5 ESB Edge Selection bit When this bit is set to one the interrupt 2 Port B and C is positive edge sensitive when cleared to zero the negative edge sensitive interrupt is
53. errupts are executed and consequertly the last return ad dress will be lost It will also remain in its highest position if the stack is empty and a RET or RETI is executed In this case the next instruction will be executed Figure 10 ST6 CPU Programming Mode b7 XREG POINTER b INDEX SHORT sien b7 YREG POINTER pol DIRECT ADDRESSING b7 VREGISTER X bp J MODE b7 WREGISTER b0 b7 ACCUMULATOR b0 b11 PROGRAM COUNTER bo SIX LEVELS STACK REGISTER NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS C Z VA000423 25 68 ST6210B 15B 20B 25B 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 3 1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock or used in conjunction with an AT cut parallel resonant crystal or a suita ble ceramic resonator or with an external resistor Rug In addition a Low Frequency Auxiliary Os cillator LFAO can be switched in for security rea sons to reduce power consumption or to offer the benefits of a back up clock system The Oscillator Safeguard OSG option filters spikes from the oscillator lines provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automati cally limits the internal clock frequency fir as a function of Vpp in order to guarantee correct op eration These functions are illustrated in Figure 12 Figure 13 Figure 14 and Figure 15
54. es feature 20 Input Output lines refer to the Block Diagram in Figure 2 which may be individually programmed as any of the following input or output configurations Input without pull up or interrupt Input with pull up and interrupt Input with pull up but without interrupt Analog input only on certain pins see Figure 2 Push pull output Standard Open drain output 20mA Open drain output PAO PAS3 only ae lines are organized as three Ports A B and Each port is associated with 3 registers in Data space Each bit of these registers is associated with a particular line for instance bits 0 of PortA Data Direction and Option registers are associat ed with the PAO line of Port A The three DATA registers DRA DRB and DRC are used to read the voltage level values of the lines which have been configured as inputs or to write the logic value of the signal to be output on Figure 24 I O Port Block Diagram SIN CONTROLS ESE DATA DIRECTION SHIFT REGISTER IE OPTION REGISTER SoUT TO INTERRUPT TO ADC SGS THOMSON YA aa EECH E REGISTER j EE DATA j REGISTER ST6210B 15B 20B 25B the lines configured as outputs The port data reg isters can be read to get the effective logic levels of the pins but they can be also written by user software in conjunction with the related option registers to select the different input mode op tions Single bit operations o
55. ese instruc tions can handle any bit in data space memory One group either sets or clears The other group see Conditional Branch performs the bit test branch operations Table 13 Conditional Branch Instructions JRR b rr ee JRS b rr ee Notes b 3 bit address e 5 bitsigned displacement inthe range 15 to 16 lt F128M gt ee 8 bitsigned displacement in the range 126 to 129 Table 14 Bit Manipulation Instructions ST6210B 15B 20B 25B Control Instructions The control instructions control the MCU operations during program exe cution Jump and Call These two instructions are used to perform long 12 bit jumps or subroutines call inside the whole program space rr Data space register A Affected The tested bit is shifted into carry Not Affected SET b rr Bit Direct 2 4 RES b rr Bit Direct 2 4 Notes b 3 bit address rr Data space register Table 15 Control Instructions Not lt M gt Affected NOP E Inherent Inherent Inherent Inherent Inherent Notes 1 This instruction is deactivated lt N gt and a WAIT is automatically executed instead of a STOP if the watchdog function is selected A Affected Not Affected Table 16 Jump amp Call Instructions Notes abc 12 bit address Not Affected SGS THOMSON YA aa EECH 55 68 ST6210B 15B 20B 25B Opcode Map Summary Thefollowing table contains an opcode map for the instructions used b
56. ftware mode or within the first 27 instructions executed following a Reset hardware activation It should be noted that when the GEN bit is low in terrupts disabled the NMI interrupt is active but cannot cause a wake up from STOP WAIT modes SWITCH VR02002 Figure 21 Digital Watchdog Block Diagram 27 DB1 7 LOAD SET OSCILLATOR CLOCK DATA BUS VA00010 36 68 GS THOMSON EE D S65 THOMSON 3 4 INTERRUPTS The CPU can manage four Maskable Interrupt sources in addition to a Non Maskable Interrupt source top priority interrupt Each source is as sociated with a specific Interrupt Vector which contains a Jump instruction to the associated in terrupt service routine These vectors are located in Program space see Table 4 When an interrupt source generates an interrupt request and interrupt processing is enabled the PC register is loaded with the address of the inter rupt vector i e of the Jump instruction which then causes a Jump to the relevant interrupt serv ice routine thus servicing the interrupt Table 4 Interrupt Vector Map Interrupt Source Associated Vector Vector Address Interrupt vector 0 NMI pin NMI FFCh FFDh Port A pins Interrupt vector 1 FF6h FF7h Port B amp C pins Interrupt vector 2 FF4h FF5h TIMER peripheral Interrupt vector 3 FF2h FF3h ADC peripheral Interrupt vector 4 FFOh FF1h 3 4 1 Interrupt Vectors Interrupt
57. gister Figure 27 illustrates the Timer s working principle DATABUS 8 S74 SGS THOMSON MICROELECTRONICS D INTERRUPT LINE VA00009 47 68 ST6210B 15B 20B 25B TIMER Cont d 4 2 1 Timer Operating Modes There are three operating modes which are se lected by the TOUT and DOUT bits see TSCR register These three modes correspond to the two clocks which can be connected to the 7 bit prescaler fint 12 or TIMER pin signal and to the output mode 4 2 2 Gated Mode TOUT 0 DOUT 1 In this mode the prescaler is decremented by the Timer clock input Dr 12 but ONLY when the signal on the TIMER pin is held high allowing pulse width measurement This mode is selected by clearing the TOUT bit in the TSCR register to 0 i e as input and setting the DOUT bit to 1 4 2 3 Clock Input Mode TOUT 0 DOUT 0 In this mode the TIMER pin is an input and the prescaler is decremented on the rising edge 4 2 4 Output Mode TOUT 1 DOUT data out The TIMER pin is connected to the DOUT latch hence the Timer prescaler is clocked by the pres caler clock input finr 12 Figure 27 Timer Working Principle 48 68 The user can select the desired prescaler division ratio through the PS2 PS1 PSO bits When the TCR count reaches 0 it sets the TMZ bit in the TSCR The TMZ bit can be tested under program co
58. he interrupt type Interrupts do not affect the oscillator selection consequently when the LFAO is used the user program must manage oscillator selection as soon as normal RUN mode is resumed 3 5 3 1 Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was executed exit from Stop or Wait mode will occur as soon as an interrupt oc curs the related interrupt routine is executed and on completion the instruction which follows the STOP or WAIT instruction is then executed pro viding no other interrupts are pending 3 5 3 2 Non Maskable Interrupt Mode If the STOP or WAIT instruction has been execut ed during execution of the non maskable interrupt routine the MCU exits from the Stop or Wait mode as soon as an interrupt occurs the instruction which follows the STOP or WAIT instruction is ex ecuted and the MCU remains in non maskable in terrupt mode even if another interrupt has been generated 3 5 3 3 Normal Interrupt Mode If the MCU was in interrupt mode before the STOP or WAIT instruction was executed it exits from STOP or WAIT mode as soon as an interrupt oc curs Nevertheless two cases must be consid ered If the interrupt is a normal one the interrupt rou tine in which the WAIT or STOP mode was en 42 68 tered will be completed starting with the execution of the instruction which follows the STOP or the WAIT instruction and the MCU is still in the interrupt mode At
59. iced unless a higher priority interrupt request is present If more than one interrupt occurs while processing the first one the subsequent ones will be lost Storage of interrupt requests is not available in level sensitive detection mode To be taken into account the low level must be present on the in terrupt pin when the MCU samples the line after instruction execution At the end of every instruction the MCU tests the interrupt lines if there is an interrupt request the next instruction is not executed and the appropri ate interrupt service routine is executed instead When the GEN bit is low the NMI interrupt is ac tive but cannot cause a wake up from STOP WAIT modes SGS THOMSON YA aa EECH 3 4 5 Interrupt Procedure The interrupt procedure is very similar to a call procedure indeed the user can consider the inter ruptas an asynchronous call procedure As this is an asynchronous event the user cannot knowthe context and the time at which it occurred As a re sult the user should save all Data space registers which may be used within the interrupt routines There are separate sets of processor flags for nor mal interrupt and non maskable interrupt modes which are automatically switched and so do not need to be saved The following list summarizes the interrupt proce dure MCU The interrupt is detected The C and Z flags are replaced by the interrupt flags or by the NMI flags The
60. is the ground connection OSCin and OSCout These pins are internally connected to the on chip oscillator circuit When the QUARTZ CERAMIC RESONATOR Mask Op tion is selected a quartz crystal a ceramic reso nator or an external clock signal can be connected between these two pins When the RC OSCILLA TOR Mask Option is selected a resistor must be connected between the OSCout pin and ground The OSCin pin is the input pin the OSCout pin is the output pin RESET The active low RESET pin is used to re start the microcontroller TEST The TEST pin must be held at Vgg for nor mal operation an internal 100kQ pull down resis tor selects normal operating mode if the TEST pin is not connected externally NMI The NMI pin provides the capability for asyn chronous interruption by applying an external non maskable interrupt to the MCU The NMI is falling edge sensitive A ROM mask option makes avail able an on chip pull up on the NMI pin TIMER This is the timer UO pin In input mode it is connected to the prescaler and acts as external timer clock input or as control gate input forthe in ternal timer clock In output mode the timer pin outputs the data bit when a time out occurs A ROM mask option makes available an on chip pull up on the TIMER pin Figure 3 ST6210B ST6220B Pin Configuration Vpp TIMER OSCin OSCout NMI TEST RESET Ain PB7 Ain PB6 Ain PB5 PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain 1 2 3 4 5
61. isabled STOP mode is avail able When in STOP mode the MCU is placed in the lowest power consumption mode In this oper ating mode the microcontroller can be considered as being frozen no instruction is executed the oscillator is stopped the RAM contents and pe ripheral registers are preserved as long as the power supply voltage is higher than the RAM re tention voltage and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exit the STOP state If the STOP state is exited due to a Reset by ac tivating the external pin the MCU will enter a nor mal reset procedure Behaviour in response to in terrupts depends on the state of the processor core prior to issuing the STOP instruction and also on the kind of interrupt request that is gener ated This case will be described in the following para graphs The processor core generates a delay af ter occurrence of the interrupt request in order to wait for complete stabilisation of the oscillator be fore executing the first instruction 41 68 ST6210B 15B 20B 25B POWER SAVING MODE Cont d 3 5 3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes when an inter rupt occurs not a Reset It should be noted that the restart sequence depends on the original state ofthe MCU normal interrupt or non maskable in terrupt mode prior to entering WAIT or STOP mode as well as on t
62. ital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets The Watchdog circuit generates a Reset whenthe downcounter reaches zero User software can prevent this reset by reloading the counter and should therefore be written so that the counter is regularly reloaded while the user program runs correctly In the event of a software mishap usu ally caused by externally generated interference the user program will no longer behave in its usual fashion and the timer register will thus not be re loaded periodically Consequently the timer will decrement down to 00h and reset the MCU In or der to maximise the effectiveness of the Watch dog function user software must be written with this concept in mind Watchdog behaviour is governed by two mask op tions known as WATCHDOG ACTIVATION i e HARDWARE or SOFTWARE and EXTERNAL STOP MODE CONTROL see Table 3 In the SOFTWARE mask option the Watchdog is disabled until bit C of the DWDR register has been set When the Watchdog is disabled low power Stop mode is available Once activated the Watchdog cannot be disabled save by resetting the MCU Table 3 Recommended Mask Option Choices ST6210B 15B 20B 25B In the HARDWARE mask option the Watchdog is permanently enabled Since the oscillator will run continuously low power mode is not available The STOP instruction is interpreted as a WAIT in
63. ked using the EAI interrupt mask bit in the control register The power consumption of the device can be re duced by turning off the ADC peripheral This is done by setting the PDS bit in the ADC control register to 0 If PDS 1 the A D is powered and enabled for conversion This bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the A D con 50 68 verter This action is also needed before entering WAIT mode since the A D comparator is not auto matically disabled in WAIT mode During Reset any conversion in progress is stopped the control register is reset to 40h and the ADC interrupt is masked EAI O Figure 28 ADC Block Diagram INTERRUPT CLOCK RESET AVss AVpp CONVERTER RESULT REGISTER CONTROL REGISTER CORE CONTROL SIGNALS CORE VA00418 4 3 1 Application Notes The A D converter does not feature a sample and hold circuit The analog voltage to be measured should therefore be stable during the entire con version cycle Voltage variation should not exceed 1 2 LSB for the optimum conversion accuracy A low pass filter may be used at the analog input pins to reduce input voltage variation during con version When selected as an analog channel the input pin is internally connected to a capacitor Caa of typi cally 12pF For maximum accuracy this capacitor must be fully charged at the beginning of conver sion In the worst case co
64. l When it decrements to zero then the TMZ Timer Zero bit inthe TSCR is set to 1 Ifthe ETI Enable Tim er Interrupt bit in the TSCR is also set to 1 an interrupt request associated with interrupt vector 3 is generated The Timer interrupt can be used to exit the MCU from WAIT mode Figure 26 Timer Block Diagram ST6210B 15B 20B 25B The prescaler input can be the internal frequency fint divided by 12 or an external clock applied to the TIMER pin The prescaler decrements on the rising edge Depending on the division factor pro grammed by PS2 PS1 and PSO bits in the TSCR see Table 10 the clock input of the timer counter register is multiplexed to different sources For di vision factor 1 the clock input of the prescaler is also that of timer counter for factor 2 bit O of the prescaler register is connected to the clock input of TCR This bit changes its state at half the fre quency of the prescaler input clock For factor 4 bit 1 of the PSC is connected to the clock input of TCR and so forth The prescaler initialize bit PSI in the TSCR register must be set to 1 to allow the prescaler and hence the counter to start If it is cleared to 0 all the prescaler bits are set to 1 and the counter is inhibited from counting The prescaler can be loaded with any value between 0 and 7Fh if bit PSI is setto 1 The prescaler tap is selected by means of the PS2 PS1 PSO bits in the control re
65. l choice in a wide range of applications where frequent code changes multiple code versions or last minute programmability are required EPROM devices thanks to their ease of erasure and reprogrammability are best suited for pro gram development and evaluation These compact low cost devices feature a Timer comprising an 8 bit counter and a 7 bit program mable prescaler an 8 bit A D Converter with 8 16 analog inputs and a Digital Watchdog timer mak ing them well suited for a wide range of automo tive appliance and industrial applications lt A gt PA0 PA3 20mA Sink PORTA PA4 PA7 Ain PORTB lt A P gt PB0 PB7 Ain it PORT C lt L P gt PC4 PC7 Ain NOT AVAILABLE ON ST62T10 T20 E20 TIMER DIGITAL WATCHDOG 5 68 ST62T10 T15 T20 T25 ST62E20 E25 1 2 PIN DESCRIPTION Vpp and Vss Power is supplied to the MCU via these two pins Vpp is the power connection and Vss is the ground connection OSCin and OSCout These pins are internally connected to the on chip oscillator circuit A quartz crystal a ceramic resonator or an external clock signal can be connected between these two pins The OSCin pin is the input pin the OSCout pin is the output pin RESET The active low RESET pin is used to re start the microcontroller TEST Vpp The TEST must be held at Vss for nor mal operation If TEST pin is connected to a 12 5V level during the reset phase the EPROM programming Mode is e
66. mming the OR and DR registers accordingly If the pull up option is not selected the input pin will be in the high imped ance state 4 1 1 2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly The pins of Port A are AND connected to the interrupt associ ated with Vector 1 The pins of Port B and C are AND connected to the interrupt associated with Vector 42 The interrupt trigger modes falling edge rising edge and low level can be selected by software for each port by programming the IOR register accordingly 4 1 1 3 Analog Input Options Some pins refer to the Block Diagram Figure 2 can be configured as analog inputs by program ming the OR and DR registers accordingly These analog inputs are connected to the on chip 8 bit Analog to Digital Converter ONLY ONE pin Table 7 UO Port Option Selection should be programmed as an analog input at any time since by selecting more than one input si multaneously their pins will be effectively shorted 4 1 2 1 0 Port Option Registers ORA B C CCh PA CDh PB CEh PC Read Write 7 0 Bit 7 0 Px7 Px0 Port A B and C Option Reg ister bits 4 1 3 I O Port Data Direction Registers DDRA B C C4h PA C5h PB C6h PC Read Write fe 0 Bit 7 0 Px7 Px0 Port A Band C Data Direction Registers bits 4 1 4 I O Port Data Registers DRA B C COh PA Cth PB C2h PC
67. n I O registers are possible but care is necessary because reading in input mode is done from I O pins while writing will direct ly affect the Port data register causing an unde sired change of the input configuration The three Data Direction registers DDRA DDRB and DDRO allow the data direction input or out put of each pin to be set The three Option registers ORA ORB and ORC are used to select the different port options availa ble both in input and in output mode All 1 O registers can be read or written to just as any other RAM location in Data space so noextra RAM cells are needed for port data storage and manipulation During MCU initialization all WO registers are cleared and the input mode with pull ups and no interrupt generation is selected for all the pins thus avoiding pin conflicts r INPUT OUTPUT VA000413 43 68 ST6210B 15B 20B 25B UO PORTS Cont d 4 1 1 Operating Modes Each pin may be individually programmed as input or output with various configurations except for PBO and PC7 on devices with the EXTERNAL STOP MODE CONTROL option This is achieved by writing the relevant bit in the Data DR Data Direction DDR and Option reg isters OR Table 7 illustrates the various port configurations which can be selected by user soft ware 4 1 1 1 Input Options Pull up High Impedance Option All input lines can be individually programmed with or without an internal pull up by progra
68. n goes high the initialization sequence is executed following expiry of the internal delay period 3 2 2 Power on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power on sequence At the beginning of this se quence the MCU is configured in the Reset state all UO ports are configured as inputs with pull up resistors and no instruction is executed When the power supply voltage rises to a sufficient level the oscillator starts to operate whereupon an internal delay is initiated in order to allow the oscillator to fully stabilize before executing the first instruction The initialization sequence is executed immedi ately following the internal delay 30 68 The internal delay is generated by an on chip coun ter The internal reset line is released 2048 internal clock cycles after release of the external reset Notes To ensure correct start up the user should take care that the reset signal is not released before the Vpp level is sufficient to allow MCU operation at the chosen frequency see Recommended Op erating Conditions A proper reset signal for a slow rising Vpp supply can generally be provided by an external RC net work connected to the RESET pin Figure 16 Reset and Interrupt Processing NMI MASK SET INT LATCH CLEARED IF PRESENT SELECT NMI MODE FLAGS PUT FFEH ON ADDRESS BUS IS RESET STILL PRESENT LOAD PC FROM RESET LOCATIONS FFE
69. nces of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of SGS THOMSON Microelectronics Specification mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS THOMSON Microelectronics 01996 SGS THOMSON Microelectronics Printed in Italy All Rights Reserved SGS THOMSON Microelectronics GROUP OF COMPANIES Australia Brazil Canada China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U S A 68 68 GS THOMSON SEENEN D S65 THOMSON
70. ntered NMI The NMI pin provides the capability for asyn chronous interruption by applying an external non maskable interrupt to the MCU The NMI input is falling edge sensitive A pull up device must be provided externally on OTP and EPROM devices TIMER This is the timer I O pin In input mode it is connected to the prescaler and acts as external timer clock input or as control gate input forthe in ternal timer clock In output mode the timer pin outputs the data bit when a time out occurs A pull up device must be provided externally on OTP and EPROM devices Figure 2 ST62T10 T20 E20 Pin Configuration Vpp TIMER OSCin OSCout NMI Vpp TEST PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain RESET Ain PB7 Ain PB6 Ain PB5 o OO JO Q O N A o PAO PA3 PA4 PA7 These 8 lines are organized as one UO port A Each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts PAO PAG can also sink 20mA for direct LED driving while PA4 PA7 can be programmed as an alog inputs for the A D converter Note PA4 PA7 are not available on ST62T10 T20 or E20 PBO PB7 These 8 lines are organized as one I O port B Each line may be configured under soft ware control as inputs with or without internal pull up resistors interrupt generating inputs with pull up resistors open drain or push
71. ntrol to perform a timer function whenever it goes high The low to high TMZ bit transition is used to latch the DOUT bit of the TSCR and trans fer itto the TIMER pin This operating mode allows external signal generation on the TIMER pin Table 9 Timer Operating Modes TOUT BOUT 0 0 Event Counter 0 1 1 0 1 1 4 2 5 Timer Interrupt When the counter register decrements to zero with the ETI Enable Timer Interrupt bit set to one an interrupt request associated with Interrupt Vec tor 3 is generated When the counter decrements to zero the TMZ bit in the TSCR register is set to one Gated Input Output 0 Output 1 VA00186 SGS THOMSON YA aa EECH TIMER Cont d 4 2 6 Application Notes The user can select the presence of an on chip pull up on the TIMER pin as a ROM mask option see Option List at the end of the Datasheet TMZ is set when the counter reaches zero how ever it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid unde sired interrupts when leaving the interrupt service routine After reset the 8 bit counter register is loaded with OFFh while the 7 bit prescaler is load ed with 07Fh and the TSCR register is cleared This means that the Timer is stopped PSI 0 and the timer interrupt is disabled If the Timer is programmed in output mode the
72. nversion starts one in struction 6 5 us after the channel has been se lected In worst case conditions the impedance ASI of the analog voltage source is calculated us ing the following formula 6 5us 9 x Cag x ASI capacitor charged to over 99 9 i e 30 KQ in cluding a 5096 guardband ASI can be higher if Cag has been charged for a longer period by add ing instructions before the start of conversion adding more than 26 CPU cycles is pointless Sy 65 THOMSON YA aa EECH A D CONVERTER Cont d Since the ADC is on the same chip as the micro processor the user should not switch heavily loaded output signals during conversion if high precision is required Such switching will affect the supply voltages used as analog references The accuracy of the conversion depends on the quality of the power supplies Vpp and Vss The user must take special care to ensure a well regu lated reference voltage is present on the Vpp and Vss pins power supply voltage variations must be less than 5V ms This implies in particular that a suitable decoupling capacitor is used at the Vpp pin The converter resolution is given by Voo Vss 256 The Input voltage Ain which is to be converted must be constant for 1us before conversion and remain constant during conversion Conversion resolution can be improved if the pow er supply voltage Vpp to the microcontroller is lowered In order to optimise conversion resolution
73. oaj og ol foo o og zl oi PS ad p of p Ey 0 050 o ojo CIS o RES wo o rales ES 10 65 0 3 7 60 o ES 2 NI spo E EE s e o o oa o gt jun ES DS Er 70 ES SE Ser 1 N 2 VR001726 TF SGS THOMSON 8168 Of aa EECH ST6210B 15B 20B 25B ST6210B ST6215B ST6220B and ST6225B MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference SGS THOMSON Microelectronics references Device ST6210B ST6215B ST6220B ST6225B Package Dual in Line Plastic Small Outline Plastic In this case select conditioning Standard Stick Tape amp Reel Temperature Range 0 C to 70 C 40 C to 85 C Special Marking No Yes d Authorized characters are letters digits and spaces only Maximum character count DIP20 DIP28 10 SO20 SO28 8 Oscillator Source Selection Crystal Quartz Ceramic resonator Default RC Network Watchdog Selection Software Activation STOP mode available Hardware Activation no STOP mode OSG Enabled Disabled Default Input pull up selection on NMI pin Yes No Input pull up selection on TIMER pin Yes No ROM Readout Protection Standard Fuse cannot be blown Enabled Fuse can be blown by the customer Note No part is delivered with protected ROM The fuse must be blown for protection to be effective External STOP Mode Control Enabled Disabled Defa
74. ocessed as normal at the re duced irae frequency The A D converter accu racy is decreased since the internal frequency is below 1MHz At power on the Low Frequency Auxiliary Oscilla tor starts faster than the Main Oscillator It there fore feeds the on chip counter generating the POR delay until the Main Oscillator runs The Low Frequency Auxiliary Oscillator is auto matically switched off as soon asthe main oscilla tor starts ADCR Address 0D1h 7 0 ADCR ADCR ADCR ADCR ADCR OSC ADCR ADCR 7 6 5 4 3 OFF 1 0 Bit 7 3 1 0 ADCR7 ADCR3 ADCR1 ADCRO ADC Control Register These bits are not used Bit 2 OSCOFF When low this bit enables main oscillator to run The main oscillator is switched off when OSCOFF is high Read Write Sy 65 THOMSON YA aa EECH ST6210B 15B 20B 25B 3 1 3 Oscillator Safe Guard The Oscillator Safe Guard OSG affords drasti cally increased operational integrity in ST62xx de vices The OSG circuit provides three basic func tions it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU it gives access to the Low Frequency Auxiliary Os cillator LFAO used to ensure minimum process ing in case of main oscillator failure to offer re duced power consumption or to provide a fixed frequency low cost oscillator finally it automati cally limits the internal clock frequency as a func tion of supply voltage in order to ensure cor
75. ongest Watchdog timer period This time period can be set to the user s requirements by setting the appropriate value for bits TO to T5 in the DWDR register The SR bit must be set to 1 since it is this bit which generates the Reset signal whenit changes to 0 clearing this bit would gen erate an immediate Reset It should be noted that the order of the bits in the DWDR register is inverted with respect to the as sociated bits in the down counter bit 7 of the DWDR register corresponds in fact to TO and bit 2 to T5 The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis ter The relationship between the DWDR register bits and the physical implementation of the Watch dog timer downcounter is illustrated in Figure 19 Only the 6 most significant bits may be used to de fine the time period since it is bit 6 which triggers the Reset when it changes to 0 This offers the user a choice of 64 timed periods ranging from 3 072 to 196 608 clock cycles with an oscillator frequency of 8 MHz this is equivalent to timer pe riods ranging from 384us to 24 576ms Figure 19 oc Li kE o O m tr ES O ia E Z Q O OH o a O lt 34 68 GS THOMSON D Ses THOMSON Watchdog Counier Control WATCHDOG COUNTER DIGITAL WATCHDOG Cont d 3 3 1 Digital Watchdog Register DWDR Address 0D8h Read Write Reset statu
76. po sure time for complete erasure is 15Wsec cm This is equivalent to an erasure time of 15 20 min utes using a UV source having an intensity of 12mW cm at a distance of 25mm 1 inch from the device window S OMSON YA aa EECH 2 CENTRAL PROCESSING UNIT 2 1 INTRODUCTION The CPU Core may be thought of as an independ ent central processor communicating with on chip IO memory and peripherals For further details referto page 18 2 2 CPU REGISTERS The CPU Core features six registers and three pairs of flags available to the programmer For a detailed description refer to page 24 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 3 1 CLOCK SYSTEM The Oscillator may be driven by an external clock or by a crystal or ceramic resonator ROM devices also offer RC oscillator and Oscillator Safeguard features For a complete description refer to page 26 3 2 RESETS The MCU can be reset in three ways by the exter nal Reset input being pulled low by the Power on Reset circuit or by the Digital Watchdog timing out For further details refer to page 30 3 3 DIGITAL WATCHDOG The Digital Watchdog can be used to provide con trolled recovery from software upsets Software and Hardware enabled Watchdog options are available in order to achieve optimum trade off be tween power consumption and noise immunity For a complete description and a selection guide refer to page 33 3 4 INTERRUPTS The CPU can manage fo
77. rain push pull output is not possible The other lines are un changed Note PC4 PC7 are not available on ST6210B ST6220B Figure 4 ST6215B ST6225B Pin Configuration Von TIMER OSCin OSCout NMI Ain PC7 Ain PC6 Ain PC5 Ain PC4 TEST RESET Ain PB7 Ain PB6 Ain PB5 PA4 Ain PAS Ain PA6 Ain PA7 Ain PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain 19 68 ST6210B 15B 20B 25B 1 3 MEMORY MAP 1 3 1 Introduction The MCU operates in three separate memory spaces Program space Data space and Stack space Operation in these three memory spaces is described in the following paragraphs Figure 5 Memory Addressing Diagram PROGRAM SPACE INTERRUPT amp RESET VECTORS 20 68 Briefly Program space contains user program code in ROM and user vectors Data space con tains user data in RAM and in ROM and Stack space accommodates six levels of stack for sub routine and interrupt service routine nesting DATA SPACE RAM EEPROM BANKING AREA DATA ROM WINDOW DATA ROM WINDOW SELECT DATA RAM BANK SELECT A TVTZT gt ACCUMULATOR Sy 65 THOMSON YA aa EECH MEMORY MAP Cont d 1 3 2 Program Space Program Space is physically implemented in ROM memory lt comprises the instructions to be execut ed the data required for immediate addressing mode instructions the reserved factory test area andthe user vectors Program Space is addressed viathe 12 bitProgram Counterregister PCregister 1 3 2
78. rect operation even if the power supply should drop The OSG is enabled or disabled by choosing the relevant OSG mask option It may be viewed as a filter whose cross over frequency is device de pendent Spikes on the oscillator lines resultin an effective ly increased internal clock frequency In the ab sence of an OSG circuit this may lead to an over frequency for a given power supply voltage The OSG filters out such spikes as illustrated in Fig ure 12 In all cases when the OSG is active the maximum internal clock frequency finr is limited to fosa which is supply voltage dependent This relationship is illustrated in Figure 15 When the OSG is enabled the Low Frequency Auxiliary Oscillator may be accessed This oscilla tor starts operating after the first missing edge of the main oscillator see Figure 13 Over frequency at a given power supply level is seen by the OSG as spikes it therefore filters out some cycles in order that the internal clock fre quency of the device is kept within the range the particular device can stand depending on Vpp and below fosg the maximum authorised fre quency with OS enabled Note The OSG should be used wherever possi ble as it provides maximum safety Care must be taken however as it can increase power con sumption and reduce the maximum operating fre quency to fosa 27 68 ST6210B 15B 20B 25B CLOCK SYSTEM Cont d Figure 12 OSG Filtering Principle 1
79. rescaler and inhibit its counting When PSI 0 the prescaler is set to 7Fh and the counter is inhibited When PSI 1 the prescaler is enabled to count downwards As long as PSI 0 both counter and prescaler are not running Bit 2 1 0 PS2 PS1 PSO Prescaler Mux Se lect These bits select the division ratio of the pres caler register Table 10 Prescaler Division Factors Pe Pst PS Dividedby 1 220000 O O CO CH 0 1 0 1 0 1 0 4 Timer Counter Register TCR Address 0D3h Read Write S 0 or 06 os os oe oe 09 on Bit 7 0 D7 DO Counter Bits Prescaler Register PSC Address 0D2h Read Write 7 0 or 6 os 06 03 02 09 00 Bit 7 D7 Always read as 0 Bit 6 0 D6 DO Prescaler Bits 49 68 ST6210B 15B 20B 25B 4 3 A D CONVERTER ADC The A D converter peripheral is an 8 bit analog to digital converter with analog inputs as alternate I O functions the number of which is device de pendent offering 8 bit resolution with a typical conversion time of 70us at an oscillator clock fre quency of 8MHz The ADC converts the input voltage by a process of successive approximations using a clock fre quency derived from the oscillator with a division factor of twelve With an oscillator clock frequency less than 1 2MHz conversion accuracy is de creased Selection of the input pin is done by configuring the related I O line as an
80. s 1111 1110b 7 0 Bit 0 C Watchdog Control bit Ifthe hardware option is selected this bit is forced high and the user cannot change it the Watchdog is always active When the software option is se lected the Watchdog function is activated by set ting bit C to 1 and cannot then be disabled save by resetting the MCU When C is kept low the counter can be used as a 7 bit timer This bit is cleared to 0 on Reset Bit 1 SR Software Reset bit This bit triggers a Reset when cleared When C 0 Watchdog disabled it is the MSB of the 7 bit timer This bit is set to 1 on Reset Bits 2 7 T5 T0 Downcounter bits It should be noted that the register bits are re versed and shifted with respect to the physical counter bit 7 TO is the LSB of the Watchdog downcounter and bit 2 T5 is the MSB These bits are set to 1 on Reset SGS THOMSON YA aa EECH ST6210B 15B 20B 25B 3 3 2 Application Notes The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices and should be used wherever possible Watchdog re lated options should be selected on the basis of a trade off between application security and STOP mode availability When STOP mode is not required hardware acti vation without EXTERNAL STOP MODE CON TROL should be preferred as it provides maxi mum security especially during power on When STOP mode is required hardware activa tion and EXT
81. struction and the Watchdog continues to count down However when the EXTERNAL STOP MODE CONTROL mask option available in ROM ver sions only has been selected low power con sumption may be achieved in Stop Mode Execution of the STOP instruction is then gov erned by a secondary function associated with the NMI pin If a STOP instruction is encountered when the NMI pin is low it is interpreted as WAIT as described above If however the STOP in struction is encountered when the NMI pin is high the Watchdog counter is frozen and the CPU en ters STOP mode When the MCU exits STOP mode i e whenan in terrupt is generated the Watchdog resumes its activity Note when the EXTERNAL STOP MODE CON TROL mask option has been selected port PBO must be defined as an open drain output and PA2 as an input Function s Required Recommended Mask Options Stop Mode amp Watchdog EXTERNAL STOP MODE amp HARDWARE WATCHDOG Stop Mode SOFTWARE WATCHDOG Watchdog HARDWARE WATCHDOG Sy 65 THOMSON YA Winara EECH 33 68 ST6210B 15B 20B 25B DIGITAL WATCHDOG Cont d The Watchdog is associated with a Data space register Digital WatchDog Register DWDR loca tion OD8h which is described in greater detail in Section 3 3 1 This register is set to OFEh on Re set bit C is cleared to 0 which disables the Watchdog the timer downcounter bits TO to T5 and the SR bit are all set to 1 thus selecting the l
82. struction is only one byte and the selection of the location to be processed is contained in the opcode Short direct addressing is a subset of the direct addressing mode Note that 80h and 81h are also indirect registers Extended In the extended addressing mode the 12 bit address needed to define the instruction is obtained by concatenating the four less significant 52 68 bits of the opcode with the byte following the op code The instructions JP CALL which use the extended addressing mode are able to branch to any address of the 4K bytes Program space An extended addressing mode instruction is two byte long Program Counter Relative The relative ad dressing mode is only used in conditional branch instructions The instruction is used to perform a test and if the condition is true a branch with a span of 15 to 16 locations around the address of the relative instruction If the condition is not true the instruction which follows the relative instruc tion is executed The relative addressing mode in struction is one byte long The opcode is obtained in adding the three most significant bits which characterize the kind of the test one bit which de termines whether the branch is a forward when it is 0 or backward when it is 1 branch and the four less significant bits which give the span of the branch Oh to Fh which must be added or sub tracted to the address of the relative instruction to obtain the address of
83. the branch Bit Direct In the bit direct addressing mode the bit to be set or cleared is part of the opcode and the byte following the opcode points to the ad dress of the byte in which the specified bit must be set orcleared Thus any bit in the 256 locations of Data space memory can be set or cleared Bit Test amp Branch The bit test and branch ad dressing mode is a combination of direct address ing and relative addressing The bit test and branch instruction is three byte long The bit iden tification and the tested condition are included in the opcode byte The address of the byte to be tested follows immediately the opcode in the Pro gram space The third byte is the jump displace ment which is in the range of 126 to 129 This displacement can be determined using a label which is converted by the assembler Indirect In the indirect addressing mode the byte processed by the register indirect instruction is at the address pointed by the content of one of the indirect registers X or Y 80h 81h The indirect register is selected by the bit 4 of the opcode A register indirect instruction is one byte long Inherent In the inherent addressing mode all the information necessary to execute the instruction is contained in the opcode These instructions are one byte long Sy 65 THOMSON YA aa EECH 5 3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which when combined with nine addressing mo
84. the end of this rou tine pending interrupts will be serviced in accord ance with their priority In the event of a non maskable interrupt the non maskable interrupt service routine is proc essed first then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction The MCU remains in normal interrupt mode Notes To achieve the lowest power consumption during RUN or WAIT modes the user program must take care of configuring unused l Os as inputs without pull up these should be externally tied to well defined logic levels placing all peripherals in their power down modes before entering STOP mode selecting the Low Frequency Auxiliary Oscillator provided this runs at a lower frequency than the main oscillator When the hardware activated Watchdog is select ed or when the software Watchdog is enabled the STOP instruction is disabled and a WAIT in struction will be executed in its place If all interrupt sources are disabled GEN low the MCU can only be restarted by a Reset Although setting GEN low does not mask the NMI as an in terrupt it will stop it generating a wake up signal The WAIT and STOP instructions are not execut ed if an enabled interrupt request is pending SGS THOMSON YA aa EECH 4 ON CHIP PERIPHERALS 4 11 0 PORTS The 20 pin devices feature 12 Input Output lines and the 28 pin devic
85. tion Selections AVAILABLE ON Device Dependent SCHEMATIC PAO PA7 PB0 PB7 PC4 PC7 Data in Interrupt PA0 PA7 Input PB0 PB7 with pull up PC4 PC7 Data in QTTRTLInterrupt Input PA0 PA7 with pull up PB0 PB7 Data in with interrupt PC4 PC7 Interrupt ber ADC PA4 PA7 PB0 PB7 PC4 PC7 Analog Input Device Dependent Open drain output PA4 PA7 5mA PB0 PB7 PC4 PC7 T Data out Open drain output PAO PAS3 20mA Push pull output PA4 PA7 5mA PBO PB7 PC4 PC7 pene Data out Push pull output PAO PA3 20mA Note 1 Provided the correct configuration has been selected 46 68 GS THOMSON SS D S65 THOMSON 4 2 TIMER The MCU features an on chip Timer peripheral consisting of an 8 bit counter with a 7 bit program mable prescaler giving a maximum count of 2 The peripheral may be configured in three differ ent operating modes Figure 26 shows the Timer Block Diagram The external TIMER pin is available to the user The content of the 8 bit counter can be read written in the Timer Counter register TCR which can be addressed in Data space as a RAM location at ad dress OD3h The state of the 7 bit prescaler can be read in the PSC register at address OD2h The control logic device is managed in the TSCR reg ister as described in the following paragraphs The 8 bit counter is decrement by the output ris ing edge coming from the 7 bit prescaler and can be loaded and read under program contro
86. uired by the ap plication The Data Space locations in which the different constants and look up tables are addressed by the processor core may be thought of as a 64 byte window through which it is possible to access the read only data stored in ROM 1 3 3 2 Data RAM In ST6210B ST6215B ST6220B and ST6225B devices the data space includes 60 bytes of RAM the accumulator A the indirect registers X Y the short direct registers V W the I O port reg isters the peripheral data and control registers the interrupt option register and the Data ROM Window register DRW register 1 3 4 Stack Space Stack space consists of six 12 bit registers which are used to stack subroutine and interrupt return addresses as well as the current program counter contents Table 1 ST6210B ST6215B ST6220B and ST6225B Data Memory Space NOT IMPLEMENTED DATA ROM WINDOW 64 BYTES X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM 60 BYTES RESERVED RESERVED WATCHD OG REGISTER RESERVED ACCUMULATOR WRITE ONLY REGISTER 22 68 Ger SGS THOMSON J S65 THOMSON 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h OBFh 0COh 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h OCAh OCBh 0CCh 0CDh OCEh OCFh 0D0h OD1h 0D2h 0D3h 0D4h OD5h 0D7h 0D8h 0D9h OFEh OFFh MEMORY MAP Cont d 1 3 5 Data Window Register DWR The Data ROM window is located from address 0040h to address 007Fh in D
87. ult Comments Supply Operating Range in the application Oscillator Fequency in the application Notes Signature Date 66 68 GS THOMSON EA 2 e D S65 THOMSON 7 2 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS THOMSON 7 2 1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file gener ated by the development tool All unused bytes must be set to FFh The selected mask options are communicated to SGS THOMSON using the correctly filled OP TION LIST appended 7 2 2 Listing Generation and Verification When SGS THOMSON receives the users ROM contents a computer listing is generated from it This listing refers exactly to the mask which will be used to produce the specified MCU The listing is then returned to the customer who must thorough ly check complete sign and return it to SGS THOMSON The signed listing forms a part of the contractual agreement for the creation of the spe cific customer mask The SGS THOMSON Sales Organization will be pleased to provide detailed information on con tractual points Table 19 Ordering Information Sales Type Sales Type ST6210BM1 XXX ST6210BM6 XXX 1836 Byles ST6210B 15B 20B 25B Table 17 Program Memory Map for ST6210B amp ST6215B
88. ur Maskable and one Non Maskable Interrupt source Each source is associated with a specific Interrupt Vector An in ternal pullup option on the NMI pin is available on ROM devices For a complete description refer to page 37 3 5 POWER SAVING MODES WAIT mode reduces electrical consumption dur ing idle periods while STOP mode achieves the SGS THOMSON YA aa EECH ST62T10 T15 T20 T25 ST62E20 E25 lowest power consumption by stopping all CPU activity For a complete description refer to page 41 4 ON CHIP PERIPHERALS 4 1 l O PORTS Input Output lines may be individually pro grammed as one of a number of different configu rations For further details refer to page 43 4 2 TIMER The on chip Timer peripheral consists of an 8 bit counter with a 7 bit programmable prescaler giv ing a maximum count of 2 For a complete de scription refer to page 47 4 3 A D CONVERTER ADC The 8 bit on chip ADC features multiplexed ana log inputs as alternate I O functions Conversion is by successive approximations with a typical conversion time of 70us at 8 MHz oscillator fre quency For a complete description refer to page 50 5 SOFTWARE 5 1 ST6 ARCHITECTURE The ST6 architecture has been designed to exploit the hardware in the most efficient way possible while keeping byte usage to a minimum For fur ther details refer to page 52 5 2 ADDRESSING MODES The ST6 core offers nine addressing modes Im medi
89. y the ST6 LOW 7 0111 H JRR 4 LD bO rr ee a x 0000 bt 1 ind 4 LDI a nn 2 imm C a x 1 a nn JRR P b4 rr ee ind 4 4 CPI b4 rr ee bt 2 imm JRR 4 ADD b2 rr ee a x ind JRS b2 rr ee JRR b6 rr ee JRS b6 rr ee bt JRR b1 rr ee b1 rr ee JRR b5 rr ee bt JRS b5 rr ee JRR b3 rr ee JRS 2 b3 rr ee bt JRR b7 rr ee JRN e b7 rr ee pc D bt pcr sd prc Abbreviations for Addressing Modes Legend dir Direct Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement imm Immediate b 3 Bit Address eyes Mnemonic inh Inherent rr 1byte dataspace address Operand ext Extended nn 1 byte immediate data bd BitDirect abc 12bit address Bytes bt Bit Test ee 8 bit Displacement por Program Counter Relative Addressing Mode ind Indirect 56 68 GS THOMSON M D S65 THOMSON ST6210B 15B 20B 25B Opcode Map Summary Continued LOW LOW 8 E F i 1000 1001 1011 1110 1111 2 JRNZ 2 JRNC RES JRZ LDI 2 JRC 4 LD oM e bO rr rr nn a y f 1 per per b d 3 1 ind 2 JRNZ 2 JRNC SET JRZ 4 DEC 4 LD e bO rr D a rr 1 pcr pcr b d pcr 1 sd 2 dir 5 2 JRNZ 2 JRNC RES JRZ 4 4 CP 0010 e b4 rr a a y f 1 pcr per b d per 1 ind 2 JRNZ 2 JRZ 4 CP e arr 1 per per 2 dir DD 2 C D 1100 1101 E A o o o ez TU lo o T alo UA A Co TU OD N JRNC SET MN pcr b d 2 JRNC RES JRZ 4 A ag pcr b d pcr i i 1 1 1 1 1 1 1 1 1 ES TU N

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