PLS OpenABEL Synthesis
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1. The following dot extension are not supported FC and LD OpenABEL Synthesis 2 OpenABEL Synthesis 4 type specification The type section is used to define the symbols used in the PLA matrix The values f r fd fr rd and fdr correspond to the classical Espresso definition Defining the type through a string allows to give a different interpretation to the symbols in the PLA matrix for each Output Value 0 corresponds to f Value 1 corresponds to r Value 2 corresponds to fd default value Value 3 corresponds to fr Value 4 corresponds to dr Value 5 corresponds to fdr For example assuming 4 Outputs the following notations are equivalent type fdr type 5555 With logical type f for each Output a l in the PLA matrix means that this product term belongs to the ON set a 0 a ora means that this product term has no meaning for the value of the function This logical type corresponds to an actual PLA where only the ON set is actually implemented With logical type r for each Output a 0 in the PLA matrix means that this product term belongs to the OFF set a l a or means that this product term has no meaning for the value of the function With logical type fd default for each Output a 1 in the PLA matrix means that this product term belongs to the ON set a 0 or a means that this product term has no meaning for the value of the function a means that th2. optional number of Product Terms see below in the file phase lt Phase Vector gt optional section defining whether Output are complemented or not type lt TypeValue gt optional section defining the meaning of the digits in the lt Output Vector gt field lt Input Vector gt lt Output Vector gt Output definition the number of lt Input Vector gt lt Output Vector gt lines must be equal to the value of the p field Input Vector and lt Output Vector are defined by Input Vector any string made up of value of i 0 1 or also called Product Term Output Vector any string made up of value of o gt 0 1 or lt Identifier gt any char string can be followed by a l to say whether the signal is complemented or not lt OtherKeywords gt TOOL TITLE MODULE JEDECFILE DEVICE VECTORFILE PROPERTY lt Phase Vector gt any string made up of 0 when the Output is complemented or 1 when the Output is not complemented lt TypeValue gt f r fd fr dr fdr lt String Value gt StringValue is a string of length equal to the number of Outputs containing only 0 1 2 3 4 or 5 For example assume 6 Outputs then type 121312 is a valid specification Figure 1 OpenABEL format syntax OpenABEL Synthesis 1 OpenABEL Synthesis 2 Information comment fields The information comment fields are supported
3. DC SET intersect Warning OFF SET and DC SET intersect Error ON SET and OFF SET intersect Error OFF SET and DC SET intersect Error ON SET and DC SET intersect The example of figure 6 will cause a warning because 00 belongs to the DC and ON sets Figure 6 ABEL disjoint DC and ON sets create a warning Beware that when ON SET and DC SET intersect some points of the ON set may be moved to the OFF set during minimization For example given the following specification f ON a b a c f DC a b c the result after minimization will be f ON a b The same result is obtained when OFF SET and DC SET intersect some points of the OFF set may be moved to the ON set during minimization For example given the following specification type dr f OFF a b f DC a b the result after minimization will be f ON b Note that these specifications will result in an error if the specified type is changed to fdr OpenABEL Synthesis 6 OpenABEL Synthesis 9 OpenABEL synthesis using PLS From the command menu of the Graphical User Interface GUI select the Execute menu Then select the OpenABEL format from the list of available inputs Input Format as shown in figure 7 Synthesis Parameters Dpen bel E ra E 1 e E Figure 7 Selecting OpenABEL input format in PLS menus Then using the selection boxes select all other appropriate synthesis parameters Refer to the techno
4. PLS OpenABEL Synthesis Table of Contents OpenABEL Synthesis 1 Information comment fields Identifier Construction dot extension type specification Example 1 Simple combinatorial design Example 2 Sequential design Warning and error messages Remarks OpenABEL synthesis using PLS WN 00D UB wn OpenABEL Format Syntax OpenABEL Synthesis OpenABEL Synthesis ANDNFHRWNNE OpenABEL Synthesis OpenABEL Synthesis OpenABEL Synthesis OpenABEL Synthesis The OpenABEL Truth Table or PLA TT formats can be used to describe the behavior of combinatorial and sequential circuits 1 OpenABEL Format Syntax An example of the syntax of the OpenABEL format is shown in figure 1 Note that comments start with a and end at the end of the line PINSINODES lt Integer gt Information optional information comment fields OtherKeywords lt FieldInformation gt Unsupported information comment fields 1 lt integer gt number of Inputs o integer number of Outputs ilb lt Identifier gt optional Input name list allowed separators are Space Tab or CR if defined size of the Input name list must be equal to the value of the i field ob lt Identifier gt optional Output name list allowed separators are Space Tab or CR if defined size of the Output name list must be equal to the value of the o field p lt integer gt
5. Sequential design In this design the D Input of the flip flop is connected to A B xor C D the Q Output of the flip flop is connected to an inverting 3 state gate with low polarity OE OpenABEL Synthesis 4 OpenABEL Synthesis TOOL ABEL 4 00 MODULE xor JEDECFILE u2 DEVICE P20X10 PINS 7 Clk 1 OE 14 A 2 B 3 C 4 D 5 Q16 16 47 04 ilb Clk O0EA BCD ob Q16 D X1 Q16 D X2 Q16 CLK Q16 0E phase 1111 p4 11 1000 11 0100 0 0001 e Figure 5 Sequential design using OpenABEL syntax 7 Warning and error messages The following warnings errors may be displayed when reading a Truth Table format file Warning PRESET PresetSignalName will be used as asynchronous PRESET Warning RESET ResetSignalName will be used as asynchronous RESET Synchronous reset and preset are used as asynchronous reset and preset DotExtension extension unknown The dot extension found is unknown and will be ignored The Gate GateName has no Output The Gate GateName has no Input XOR XORName with bad number of entry not created For example ifthe Q16 D X2 is missing the following message will be displayed XOR Q16 D with bad number of entry not created OpenABEL Synthesis 5 OpenABEL Synthesis 8 Remarks It is checked that the given ON OFF and DC sets are disjoint if not one of the following warning error messages is printed according to the type value Warning ON SET and
6. for the keywords PINS and NODES and are ignored for the other keywords The syntax for information comment fields is shown in figure 2 PINSINODES Integer Information Information PinOrNodeName lt PinOrNodeAssignement gt PinOrNodeName Identifier PinOrNodeAssignement lt Integer gt Figure 2 OpenABEL syntax for PINS and NODES 3 Identifier Construction dot extension The following dot extensions are supported for the definition of signal names AP Flip flop asynchronous preset AR Flip flop asynchronous reset CE Flip flop clock enable CLK or C Clock Input CP Flip flop clock from pin D D flip flop Input FB Register feedback J J Input of a JK flip flop K K Input of a JK flip flop LE Flip flop latch enable transparent low LH Flip flop latch enable transparent high OE Output enable control PIN Output signal on a device pin PR Flip flop preset synchronous or asynchronous Q Register feedback R R Input of a RS flip flop RE Flip flop reset synchronous or asynchronous REG D flip flop Input S S Input of a RS flip flop SP Flip flop synchronous preset SR Flip flop synchronous reset T T flip flop Input X1 and X2 The 2 entries of a XOR Figure 3 Supported dot extensions in OpenABEL syntax Remarks The flip flop synchronous preset and reset are used as asynchronous preset and reset
7. is product term belongs to the DC set With logical type dr for each Output a 0 in the PLA matrix means that this product term belongs to the OFF set a means that this product term belongs to the DC set a l or a means that this product term has no meaning for the value of the function OpenABEL Synthesis 3 OpenABEL Synthesis With logical type fr for each Output a 1 in the PLA matrix means that this product term belongs to the ON set a 0 means that this product term belongs to the OFF set ur tr a or a means that this product term has no meaning for the value of the function With logical type fdr for each Output a 1 in the PLA matrix means that this product term belongs to the ON set a 0 means that this product term belongs to the OFF set a means that this product belongs to the DC set a means that this product term has no meaning for the value of the function 5 Example 1 Simple combinatorial design The following lines give the specification of a 5 inputs 3 outputs combinatorial design AS number of Inputs 0 3 number of Outputs ilbabcde names of Inputs optional ob fl f2 f3 names of Outputs optional p4 Number of product terms in the file 1 0 111 First product term a d appears in functions f1 f2 f3 is negation 111 011 0 00000 e end of file Figure 4 Simple combinatorial design using OpenABEL syntax 6 Example 2
8. logy pages of the user manual for details on the technology specific options OpenABEL Synthesis 7 OpenABEL Synthesis OpenABEL Synthesis 8
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