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LTspice IV User Manual - Department of Electrical, Computer, and

1. Syntax Exxx n n nc nc Laplace lt func s gt window lt time gt nfft lt number gt mtol lt number gt The transfer function of this circuit element is specified by its Laplace transform The Laplace transform must be a function of s The frequency response at frequency f is found by substituting s with sqrt 1 2 pi f The time domain behavior is found from the impulse response found from the Fourier transform of the frequency domain response LTspice must guess an appropriate frequency range and resolution The response must drop at high frequencies or an error is reported It is recommended that the LTspice first be allowed to make a guess at this and then check the accuracy my reducing reltol or explicitly setting nfft and the window The reciprocal of the value of the window is the frequency resolution 114 The value of nfft times this resolution is the highest frequency considered The Boolean XOR operator is understood to mean exponentiation when used in a Laplace expression Syntax Exxx n n value lt expression gt This is an alternative syntax of the behavioral source arbitrary behavioral voltage source B Syntax Exxx n n POLY lt N gt lt nodel nodel node2 node2 nodeN nodeN gt lt c0 cl c2 c3 Ch gt This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for r
2. Automatically delete log files This allows the simulation log to be automatically deleted whenever the simulation is closed These files contain various simulation statistics such as lapsed time during the simulation warning and error messages and step parameters used for step temp dc analyses Directory for Temporary Files Directory for temporary storage of waveform and update files Save Defaults These settings are used when you don t explicitly state which nodes should be saved ina simulation Useful setting are Save Device Currents Save Subcircuit Node Voltages and Save Subcircuit Device Currents Device voltages and internal device voltages are only of internal program development use 175 Control Panel Save Device Currents Check this so that you can plot device and terminal currents You will also need it to be able to plot dissipation Save Subcircuit Node Voltages You will need to check this to plot voltages in hierarchical designs Save Subcircuit Device Currents You will need to check this to plot currents in hierarchical designs Don t save Ib Ie Is Ig This saves only the collector drain currents of transistors in the interest of reducing the size of the output data file This is useful for IC design but it using it means that there isn t enough data available to compute transistor dissipation 176 Save De
3. Settings marked with an asterisk are remembered between program invocations Marching Waveforms Check to enable simulation results to be incrementally plotted during the simulation Generate Expanded Listing Dump the flat netlist after expanding subcircuits to the in the SPICE Error Log file Open Demo circuits as regular schematics Use File Open to open demo circuits in LTspiceIV lib app app All SPICE commands will be visible The schematic can be edited and saved to a new file The double dots is for demo circuit display control use Only one dot is required for editing 174 Don t warn when using preliminary models Turn off the warning message for all preliminary models Note All SMPS models are flagged as preliminary as a disclaimer Automatically delete raw files This allows waveform data files to be deleted automatically after closing a simulation This dramatically reduces the amount of disk space used by LTspice but requires the simulation to be rerun when you reopen the simulation Automatically delete net files This allows the schematic s netlist to be automatically deleted whenever the schematic is closed These files can be thought of as small temporary files and deleting them makes exploring the directory tidier They define th lectrical connectivity of the schematic to the LTspice simulator Some people prefer not to delete them because they have further use for them
4. pacitances for bot wer of junction vol d and PB rker and D mulators Nam Vto Bet Lam bda Rd Rs Cgs Cgd 124 Jie IEEE Trans CA The and Is the saturation Two ohmic resistances Rd an arge storage is modeled by nonlinear depletion DC characteristics are defined by which d LAMBI layer An Skellern Description Threshold voltage Transconductance parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zero bias G S junction Capacitance Zero bias G D junction Capacitance th gate junctions tage and are defined by i A fitting parameter B has been added Improved FET Model for Computer D vol 9 no 5 pp 551 553 May 1990 termine the variation of DA which determines th current of the two d Rs are included which vary as the 1 2 U Def n aul i t t s V 2 0 A le f 4 V V 1 0 V Q 0 Q 0 F 0 F 0 the parameters Cgs See A E Exam ple le 3 le 4 100 100 Sp ip Pb KF AF Fc Tno Bet alc Vto Te alp ha VK Gate j potent Gate j unction ial unction Satura Doping parame tion current tail Eet Flicker noise coefficient Flicker noise exponent Coefficient for forward depletion Capacitance Paramete
5. Capacitor Inductor and Diode commands Rotate Rotate the sprited objects Note this is grayed out when there are no objected sprited Mirror Mirror the sprited objects Note this is grayed out when there are no objected sprited Draw Wire Click the left mouse button to start a wire Each mouse click will define a new wire segment Click on an existing wire segment to join the new wire with an existing one Right click once to cancel the current wire Right click again to quit this command You can draw wires through components such as resistors The wire will automatically be cut such that the resistor is now in series with the wire Label Net Specify the name of a node so an arbitrary one isn t generated by the netlister for this node Place GND Place a GROUND symbol This is node 0 the global circuit common 16 Delete Delete objects by clicking on them or dragging a box around them Duplicate Duplicate objects by clicking on them or dragging a box around them You can copy from one schematic to another if they are both opened in the same invocation of LTspice IV Start the Duplicate command in the window of the first schematic Then make the second schematic the active window and type Ctrl V Move Click on or drag a box around the objects you wish to move Then you can move those objects to a new location Paste It is ena
6. When non zero the simulator tries to condense LTRA transmission lines history of input voltages and currents Sets the absolute voltage error tolerance Sets the relative error tolerance for waveform compression Sets the absolute voltage plotabstol Num InA plotwinsize Num 300 ptrantau Num el ptranmax Num 0 PARAM User Defined Parameters The The variables value for the sake of clarit subcircuits so that abstrac libraries error tolerance for waveform compression Sets the absolute current error tolerance for waveform compression Number of data points to compress in one window to zero to disable compression Set Characteristic source start up time for a damped pseudo transient analysis to find the operating point Set to zero to disable pseudo transient If set non zero that time of the damped pseudo transient analysis is used as the operating point whether the Circuit has settled or not param directive allows the creation of user defined This is useful for associating a name with a ty and parameterizing circuits can be saved in param statement can be included inside a subcircuit definition to limit the scope the parameter value to that subcircuit and subcircuits invoked by that subcircuit To invoke parameter substitution and expression evaluation enc will lose the expression in curly braces The
7. Where is the waveform stored during simulation All the waveform data are stored on hard disk Only the plotted traces are loaded into RAM Turning off the marching waveforms can reduce the RAM memory requirement Note that for most analysis types there is no particular file size limit You can generate and view raw files that are very many Gigabytes in size What if I don t have enough disk space for long simulation The waveform data has been compressed but it is still proportional to the run time and the number of traces saved The easiest way to save memory is to select desired traces for storing before the simulation starts OK I ve done everything and I m still running out of memory What can I do During a transient analysis you can interactively throw away the past waveforms by pressing the 0 key That will retrigger the simulation time to t 0 as the present time 195 Model Compatibility Are the switching regulator models compatible with PSpice models and others The LTspice SMPS macromodels are implemented in a combination of new proprietary native LTspice devices and or a proprietary hardware description language While it is possible in principle to develop generic SPICE or PSpice macromodels the resultant simulation speed would not be viable LTspice can however run PSpice semiconductor and behavioral models and is generally a much higher performance simulator so you
8. Fe Linear Technology LTspice SwitcherCAD III LT1371 Of x File View Tools Window Help AS EP 40 QQQR EERE 100pIs 200us 300us 400us ETE dx 174 938us 5 71631KHz dy 3 24 7 There are toolbar buttons and menu commands for zooming out panning and returning to the autoranged zoom Note the undo and redo commands allow you to review the different zooms used Waveform Arithmetic There are thr types of mathematical operations that can be performed on waveform data 1 Plot expressions of traces 2 Compute the average or RMS of a trace 3 Display the Fourier Transform of a Trace 40 1 Plot expressions of traces Both the View gt Visible Traces and View gt Add Trace commands allow one to enter an expression of data Another method to plot an expression of available simulation data traces is to move the mouse to the trace s label and right click This dialog box also allows you to set the trace s color and allows you to attach a cursor to the waveform LTspice will do a dimensional analysis of the expression and plot it against a vertical axis labeled with those units All waveforms in a plotting pane with the same units are plotted on the same axis ice SwitcherCAD III warning2 cir y File View Plot Settings Simulation Tools Window Help AsO P49 QQQRQ Eise ReAl SS Expression Editor D Trace Color Cc Attached Cursor none Enter an algebraic expression
9. How do I create my own symbol Start with the menu command File gt New Symbol Can I create my own switching regulator models Not very easily The switching regulator models that ship with LTspice IV use a new hardware description language and new intrinsic SPICE devices designed to encapsulate the behavior of LTC s switching regulator products Even if you succeed in making a model with standard SPICE primitives the simulation will run orders of magnitude slower Note that some people hav made such switching regulator models with standard SPICE devices LTspice can run these models and will usually outperform the simulator for which they were targeted Memory Problems How much memory do I need to run the program 194 You can basically run the LTspice IV if you can operate your Windows system We have spent a great deal of effort in minimizing the memory requirement of this program While a typical simulation might generate 8Gigabytes of raw data that data will be compressed on the disk to 400Megabytes To view a single trace would require less than 65Megabytes of RAM Of course the more memory the better the performance will be Also LTspice IV benefits from the improved memory performance of Windows NT and later operating systems so you might consider upgrading operating system if you run out of memory An x64 OS will be the best choice in this regard
10. ccccceeeeeeeeceeeeeeeeeeeeeeeeseaeeeesaeeeeeeesaas 159 T Lossless Transmission Lime cece eeeseeeeeeeneeeeeenaeeeeeeenaeeeeneaas 161 We Uniform Re TE 161 V Voltage Source ceeeeceeecceceeeeeeeaeeeeaeeceeeeeeaaeeseeaeeseaeeesaeeeeaaeeseneesaas 163 W Current Controlled Gwitch 167 eeler DIE 169 Z MESFET Iransietor AANEREN 169 Control Panel 171 Accessing the Control Panel 171 COMpresSlONn s322c 8u tied cee eas ea ee ee 171 Operatlom EE 173 Save etlecher ee 175 SPICE EE 177 NetlistOptions nospam ege at Bache le nnd dna 178 HACKS erigani ee te A ee a et 179 Drafting Options aa vettacs eth pare eaa aaea tet tide ee 180 Interne Options aw Acae ania ait a alana wel 182 FAQs 184 Program Ree EE 184 Transformer Models AAA 185 Phird2party e EE 186 die Deel de 189 de RO EE 190 License and DIStriDUtiON aser iraniani iuan kuyanni eek eani usani kurant iira 192 Circuit Efficiency Calculation c cceccccceeeeeseeeeceeeeeeeeeeeeeseeeeeeeeeseaeeeeeeeees 193 C stomM SyMDOlS srren sraa aantas taaa aaan aaa tates aara EAEE kar ARa Akae 194 Memory Problems aori Tsaa aeaa SAT EET ARAARA AEE TATAARS ARATE 194 Model Compatibility 0 ccccccceceeeeeeeeeeeeeeeeeeee seas eeeeaeeeeeeeseaeeesaeeeeeeeeeeeeess 196 Sale EE TEE 196 Exporting Merging Waveform Datz 196 Running Under Lmmus aeieeiaii naa EAEE AEA ETARE ERE 198 What about a Paper Manual 199 What about a Users Group 199 LTspice IV Overview 200 SPICE Error Log Command 20
11. How do I control the inductor parasitic resistance By default LTspice will supply losses to inductors to aid SMPS transient analysis For SMPS these losses are of usually of no consequence but may be turned off if desired On the Tools gt Control Panel gt Hacks page uncheck Supply a min inductor damping if no Rpar is given This setting will be remembered between invocations of the program There is also a default series resistance of 1 milliohm for inductors that aren t mentioned in a mutual inductance statement This Rser allows LTspice IV to integrate the inductance as a Norton equivalent circuit instead of Thevenin equivalent in order to reduce the size of the circuit s linearized matrix If you don t want LTspice to introduce this minimum resistance you must explicitly set Rser 0 for that inductor This will require LTspice to use the more cumbersome Thevenin equivalent of the inductor during transient analysis 189 Can I add edit my own inductor model Open the file typically installed as C Program Files LTC LTspiceIV lib cmp standard ind to add or edit inductor models MOSFET Models What is the difference between LTspice IV MOSFET and standard SPICE MOSFET models Besides the standard SPICE MOSFET models LTspice IV also includes a proprietary MOSFET model that is not implemented in other SPICE programs It directly encapsulates the charge behavior of the ver
12. hypot x y LE XY rZ int x inv x limit x y zZ in x log x log10 x max x y e g aSin 5 returns 1 57080 not 1 57080 2 29243i Synonym for asin Arc hyperbolic sine Arc tangent of x Synonym for atan Four quadrant arc tangent of y x Arc hyperbolic tangent TL ab r Meise D Cube root of x Integer equal or greater than x Cosine of x Hyperbolic cosine of x e to the x Same as abs x Random number between x and x with uniform distribution Integer equal to or less than x Random number from Gaussian distribution with sigma of x sqrt x 2 y 2 If x gt 5 then y else z Convert x to integer O if x gt 5 else l Intermediate value of x y and z Natural logarithm of x Alternate syntax for In Base 10 logarithm The greater of x or y 87 mc x y min x y pow x y pwr x y pwrs x y rand x random x round x sgn x sin x sinh x sqrt x table x a b c d A random number between x 1 y and x 1l y with uniform distribution The smaller of x or y Real part of x y e g pow 5 1 5 returns Urp not 0 353553 abs x y sgn x abs x y Random number between O and 1 depending on the integer value of X Similar to rand but smoothly transitions between values Nearest integer to x Sign of x Sine of x Hyperbolic sine of x Real part of the squar
13. Transconductance parameter Bulk threshold parameter Surface inversion potential Channel lengt h modulation level 1 and 2 on Drain oh resistan ly mic ce Source ohmic resistan Zero bias B D ce Uni ts A V Vis 1 V D and CBS Farad series resistance can be expressed as or RSH Ohms square the latter ltiplied by the number of squares NRD and NRS input Def Exa aul mpl t e 0 Tat 2e 3e 5 5 0 0 3 ah 0 6 0 6 5 0 0 0 2 0 20f Cbs Pb Cgs Cgd Cgb Rsh Cj Mj Cjs Mjs junction capacitance Zero bias B S junction capacitance Bulk junction saturation current Bulk diode emission coefficient Bulk junction potential Gate source overlap capacitance per meter channel width Gate drain overlap capacitance per meter channel width Gate bulk overlap capacitance per meter channel width Drain and source diffusion sheet resistance Zero bias bulk junction bottom capacitance per square meter of junction area Bulk junction bottom grading coefficient Zero bias bulk junction sidewall capacitance per meter of junction perimeter Bulk junction F m F m F m F m F m 137 0 20 le le 14 15 0 8 0 8 7 0 4e 11 0 4e 11 0 2e 10 0 10 0 2e 4 0 5 0 5 0 lp 50 level 1 Js TOX TPG Xj Ld Ucr it
14. 3 Place the mouse over a symbol hold down the control key and click the right mouse button A dialog box will appear that displays all available symbol attributes Next to each field is a check box to indicate if the field should be visible on the schematic Edit a Visible Attribute Most visible component attribute fields can be edited by pointing at it with the mouse and then right clicking The mouse cursor will turn into a text caret when it s pointing at the text This is a convenient way of changing the value of a component 22 Enter new Value for L1 Specialized Component Editors Many component types such are resistors capacitors inductors diodes bipolar transistors MOSFET transistors JFET transistors independent voltage sources independent current sources and hierarchical circuit blocks have special editors These editors can access the appropriate database of related components To use these editors right mouse click on the body of the component 23 General Attribute Editor Sometimes it is desired to get direct access to every available component attribute to edit their contents and visibility An editor that allows you to do this can be reached by placing the mouse over the body of a symbol holding down the control key and clicking the right mouse button A dialog box will appear that displays all available symbol attributes Next to each field is a check box to
15. AC analysis correspond to the network being terminated in the same manner as in the NET statement NODESET Supply Hints for Initial DC Solution The nodeset directive supplies hints for finding the DC operating point If a circuit has multiple possible DC states as for example a flipflop the iteration process 79 for finding the DC solution may never converge A nodeset directive can be used to lead the circuit to one or another state Basically after a solution pass is done with the voltage specified on the nodeset directive the constraint is removed for subsequent iterative passes Syntax NODESET V nodel lt voltage gt V node2 lt voltage NOISE Perform a Noise Analysis This is a frequency domain analysis that computes the noise due to Johnson shot and flicker noise The output data is noise spectral density per unit square root bandwidth Syntax noise V lt out gt lt ref gt lt srce gt lt oct dec Linz lt Nsteps gt lt StartFreq gt lt EndFreq gt V lt out gt lt ref gt is the node at which the total output noise is calculated It can be expressed as V nl n2 to represent the voltage between two nodes lt src gt is the name of an independent source to which input noise is referred lt src gt is the noiseless input signal The parameters lt oct dec lin gt lt Nsteps gt lt StartFreq gt
16. K 1 5V 5V 10m 1110 asc R3 File name 1 5v DN 50m 1610 asc K 2 5 12 120mA 1302 asc 4 1 5V3 3 75mA 1307B asc K 2 5V3 cal K zm easel 5V 100m 1 denen 222 237 KB V 5v 100m 1 X 3 3v 12V 100m 1301 asc MBRS140 3 3V 12 120m 4 3 3v 5V 200m BY 5V 250m TL 3V 5V 100mA 1 A pe Files of type Schematics asc sch app si Cancel Zi General Purpose Schematic Driven SPICE You are free to use LTspice capture SPICE program but many aspects of analog engineering IV as a general purpose schematic This is useful not only for SMPS design The example circuits typically installed in the directory C Program Files LTC LTspicelV examples Educational illustrate various LTspice capabilities Fejlinear Technology LTspice SwitcherCAD III astable asc File Edit Hierarchy view Simulate Tools Window Help ASIP ZORLAR BG HEET EE 1 Oms 3ms 6ms ms 12ms 15ms 18ms 2ims 24ms astable asc Click to plot NO02 Externally Generated Netlists You can open netlists generated either by hand or by other schematic capture programs These files usually have a filename extension of cir but H net and sp are understood The ASC editor used for netlist files supports unlimited file size and unlimited undo redo The menu command Tools gt Color Preferences can be used to adjust the colors used in the ASC editor 10 lay Linear Te
17. O Weak avalanche and Bas Physical separation of Improved Improved Self heating modeling Model Structure 150 It is a widely used alternative to SiGe and V HBT devices IC Capabilities compared to Standard Gummel Poon Model Integrated Substrate transistor for parasitic devices in Depletion capacii temperature modeling in this version mitter breakdown model Improved Early Effect modeling Ic and not Ib tance model Cx Jore Parameters Because the VBIC model is based on SGP model it is possible to start with SGP parameters carry out some transformations Following parameters are from VBIC version 1 2 which is implemented in LTSpice in the 4 terminal version without excess phase network and self heating effect To switch from SGP to VBIC you should set the extra parameter level to 9 Na Parameter meaning Uni Defau me t Lt tn Parameter measurement SC 27 om temperature EC Extrinsic coll resistance Q 0 1 151 EC VO ga mm hr CGE rb rb re rs rb is nf fc cb GO pe me aj 152 Intrinsic coll resistance Epi drift saturation voltage Epi doping parameter High current RC factor In trinsic base resistance trinsic base resistance trinsic emitter In resistance resistance trinsic substrate Parasitic bas
18. This is a linearly dependent source specified solely by a constant gain Syntax Gxxx n n nc nc table lt value pair gt lt value pair gt Here a lookup table is used to specify the transfer function The table is a list of pairs of numbers The second value of the pair is the output current when the control voltage is equal to the first value of that pair The output is linearly interpolated when the control voltage is between specified points If the control voltage is beyond the range of the look up table the output current is extrapolated as a constant current of the last point of the look up table Syntax Gxxx n n nc nc Laplace lt func s gt window lt time gt nfft lt number gt mtol lt number gt 116 The transfer function of this circuit element is specified by its Laplace transform The Laplace transform must be a function of s The frequency response at frequency f is found by substituting s with sqrt 1 2 pi f The time domain behavior is found from the impulse response which is found from the Fourier transform of the frequency domain response LTspice must guess an appropriate frequency range and resolution The response must drop at high frequencies or an error is reported It is recommended that the LTspice first be allowed to make a guess at this and then check the accuracy my reducing reltol or explicitly setting nfft and
19. Uex 138 sidewall grading coefficient Bulk junction saturation current per square meter of junction area Oxide thickness Substrate doping Surface state density Fast surface state Type of gate material l opp to substrate 1 same as substrate 0 Al gate Metallurgical junction depth Lateral diffusion Surface mobility Critical field for mobility degradation level 2 only Critical field exponent in mobility degradation level 2 only A m cm 2 V Vic 33 level 2 3 0 le 8 Lie dee H H 0 4el 5 0 le 10 0 le 10 1 0 ly 0 0 8 u 600 700 1le4 1e4 0 Oise Utr Vma Nef Kf Af BG Del ta The ta Eta Kap pa Tno Transverse field coefficient level 2 only Maximum carrier drift velocity levels 2 amp 3 only Total channel charge exponent level 2 only Flicker noise coefficient Flicker noise exponent Coefficient for forward bias depletion Capacitance formula Width effect on threshold voltage levels 2 and 3 Mobility modulation level 3 only Static feedback level 3 only Saturation field level 3 only Parameter measurement temperature m s ao 27 5e4 26 50 139 VDMOS Rd Rb ae Body R G H Rs Diode The discrete vertical double diffused MOSFET transistor VDMOS popularly
20. W C u1 1 I C u1 15 V ul n010 L1 I C u1 2 I D u1 1 mem I R1 ven 5 I D u1 2 I R2 I D u1 3 V ul n013 R3 I C u1 8 I D u1 5 V ul n01 4 Uu I C u1 9 K D u1 7 V ut n015 I B u1 1 I C u1 10 K G u1 1 User Defined Functions The menu command Plot Settings gt Edit Plot Defs File allows you to enter your own function definitions and parameter definitions for use in the waveform viewer These functions are kept in the file plot defs in the same directory as the LTspiceIV executable scad3 exe Then the syntax is the same as the param and func statements used for parameterized circuits E g the line func Pythag x y sqrt x x y y 47 defines the function Pythag to be the square root of the sum of its two arguments Similarly the line param twopi 2 pi would define twopi to be 6 28318530717959 Note that it uses the already internally defined constant pi of the waveform viewer Axis Control When you move the mouse cursor beyond the data plotting region the cursor turns into a ruler This tries to indicate that you are pointing at that axis attributes When you left click you can enter a dialog to manually enter that axis range and the nature of the plot For example for real data if you move the mouse to the bottom of the screen and left click you can enter a dialog to change the horizontal quantity plotted This lets you make parametric plots For c
21. model can have different sizes and the electrical behavior is scaled to the size of the instance Syntax model lt modname gt lt type gt lt parameter list gt The model name must be unique That is two different types of circuit elements such as a diode and a transistor cannot have the same model name The parameter list depends on the type of model Below is a list of model types Type Associated Circuit Element SW Voltage Controlled Switch CSW Current Controlled Switch URC Uniform Distributed RC Line LTRA Lossy Transmission Line D Diode NPN NPN Bipolar Transistor PNP PNP Bipolar Transistor NJF N channel JFET model PJF P channel JFET model NMOS N channel MOSFET PMOS P channel MOSFET NMF N channel MESFET PMF P channel MESFET VDMOS Vertical Double Diffused Power MOSFET See the description of the circuit element for a list of which parameters are instance specific and which are common to a model NET Compute Network Parameters in a AC Analysis 78 This statement is used with a small signal AC analysis to compute the input and output admittance impedance Y parameters Z parameters H parameters and S parameters of a 2 port network It can also be used to compute the input admittance and impedance of a l port network This must be used with a AC statement which determines the frequency sweep of the network analysis Syntax
22. will depend more on the amount of physical memory you have than your hard disk speed ct ct To convert a waveform window to Fast Access format make the waveform window the active window and execute menu command gt Files gt Convert to Fast Access The conversion process will require an amount of free disk space equal to the file size to be converted but the converted file will be only 11 bytes larger than the original file The conversion process can take a long time and use up to one quarter of your physical memory In fact it can take more time to convert the file to Fast Access format then was required for the initial simulation The exact time the conversion requires will depend on such factors as the state of the hard disk fragmentation and the amount of physical memory you have During conversion you may find your machine is not very responsive to your mouse and keyboard It is possible to convert files in a batch command with the following command line syntax 55 scad3 exe FastAccess lt file gt Where lt file gt is the name of the raw file you wish to convert to Fast Access format This format is only supported for real data not the complex data that comes from a ac analysis Memory RAM and Address Space LTspice was the first PC based SPICE program to implement its own 64bit address on the hard disk to allow one to view wav
23. OPTI values specified are assumed to have been the temperature TNOM which can be specified ONS control line or overridden by a specification on the model line The BJT parameters used in the modified Gummel Poon model are listed below Modified Gummel Poon BJT Parameters Name 146 Description Un Defa BE Nf Vat Ikf Ise Var Rb Irb Rbm Re Re Cje Vje Transport saturation current Ideal maximum forward beta Forward current emission coefficient Forward Early voltage Corner for forward beta high current roll off B E leakage saturation current mission coefficient B E leakag Ideal maximum reverse beta Reverse current emission coefficient Reverse Early voltage Corner for reverse beta high current roll off B C leakage saturation current mission coefficient B C leakag Zero bias base resistance Current where base resistance falls halfway to its min value Minimum base resistance at high currents Emitter resistance Collector resistance B E zero bias depletion Capacitance B E built in potential it ult le 1 100 Infi Infi Infi Rb 147 Mie TE Vic Mjc Xcyjc Tr Xtb Eg Xti Kf Af 148 B E junction exponential factor Ideal forward transit time Coefficient for bias dependence of Tf Voltage desc
24. The current can also be specified as a function of the voltage across the output nodes with a look up table This is useful for modeling the characteristics of a load Syntax Ixxx n n lt value gt step lt valuel gt lt value2 gt lt value3 gt load This is a special form for the current source The current is specified as a list of currents to use in a step load response transient analysis In this mode the simulation is computed until steady state is reached at the first current inthe list lt valuel gt Then the current is stepped to the next value in the list lt value2 gt The simulation proceeds until steady state is achieved at that current Then the current is stepped to the next value and the process repeats until the list is exhausted If the tran command doesn t specify step then the original lt value gt is used Syntax Ixxx n n R lt value gt This is not a current source at all but a resistor It is used to model a resistive load when the load is netlisted as a current source Syntax Ixxx n n PWL tl il t2 12 t3 i3 Arbitrary Piece wise linear current source For times before tl the current is il For times between tl and t2 the current varies linearly between il and i2 There 122 can be any number of time current points given For times after the last time the current is the last current Syntax
25. a special graphical symbol instead of the name 0 There is also a graphical symbol defined for node COM but this node has no special significance That is it s not the SPICE global common and it s not even a global node It s just sometimes convenient to have a graphical symbol associated with a node distinct from ground If you give a node a name starting with the characters SG_ as in for example G_VDD then that node is global no matter where the name occurs in the circuit hierarchy SS GND global node 0 J C com Pe Port Type None sl Port type is only visible if drawn at the end of a wire Cancel It is possible to indicate that a node is a port of type input output or bi directional These port types will be drawn differently but have no significance to the netlister Indicating a port type can make circuit more readable Global nodes are also drawn differently in that a box is drawn around the name 18 Schematic Colors The menu command Tools gt Color Preferences colors allows you to set the colors used in displaying the schematics You click on an object in the sample schematic and use the red green and blue sliders to adjust the colors to your preferences Color Palette Editor Eee 19 Note Non electrical graphical annotations made to schematics such as lines and circles will be draw in the same color as a component body P
26. a top leve that block lower level schematic You can add SPICE directives to and run simulations using only it and any schematics to which it refers 33 To open a schematic block as an instance of a block of a higher level schematic first open the higher level schematic and then move the mouse to the body of the instance of the symbol calling the block When you right mouse click on the body of the instance of that symbol a special dialog appears that allows you to open the schematic When you open the schematic in this manner you can cross probe the nodes and current in the block Note that you should have the options Save Subcircuit Node Voltages and Save Subcircuit Device Currents checked on the Save Defaults Pane of the Control Panel Also if you ve highlighted a node on the top level schematic that node will be also highlighted in the lower level block Note that is dialog also allows you to enter parameters to pass to this instance of the circuitry in preamp asc 34 Waveform Viewer Waveform Viewer Overview LTspice IV includes an integrated waveform viewer that allows complete control over the manner the simulation data is plotted Data Trace Selection There ar Ta ae 3 thr basic means of selecting plotted traces Probing directly from the schematic Menu command Plot Set tings gt Visible Traces Menu command Plot S
27. can attach both cursors to a single trace by right clicking on the trace label and selecting 1st amp 2nd You can also attach the lst or 2nd cursor or both cursors to any trace by right clicking on that trace s label and using the Attached Cursor drop down box The attached cursors can be dragged moved with the cursor keys 50 about with the mouse or SC Ble View Toos Window Help la sl Deu ez QQQR LI Sas saa ass lous 20us 24us 28us 32us 36us 40s 44s 48us 52us 56s 60ps Right Click to edit expression Control Left Click to integrate a h When there are attached cursors active a readout display becomes visible that will tell you the location and difference of the cursors 51 File View Tools Window Help x As G T 4 IRAR REEE BBA SSH LT1074 app NI m Cursor 1 out Horz 741 Ei us Vert 5 11878V Cursor 2 Vout B Horz 45 6867 s Vert 5 13251V Diff Horz 4 1747p1s Vert 13 7339mV Freq 239 538KHz Slope 3289 79 lous 20us 24s 28us 32us 36us 40s 44s 48s 52us X 40 72us y 5 12132 56us 60s Note that there is also mouse cursor readout independent of the above attached cursor readout As you move the mouse over the waveform window the mouse position is readout on the status bar If you drag the mouse as if you were going to zoom the size of box is displayed on the status bar This lets you quickly measure differences with the mo
28. ceteeeeeeeeeeeeeteeeeetaeeeseeeeeeeeee 92 TEMP Temperature Sweeps sssessseesseesseseseseennstnretnnertnnstnnsennsennns 93 TF Find the DC Small Signal Transfer Functton 94 TRAN Perform a Nonlinear Transient Analysis cccceseeeeeeeees 94 WAVE Write Selected Nodes to a Wav File 95 Transient Analysis Option 96 TRAN Modtiers s ioana rie Na EET EEE A 96 le 96 STOUTUP na nae aaaea EEN icena tubd aa aia naD aiii 96 Stay AE E A EA A E AT E A es 97 Weller EE 97 STOP WEE 98 Gire Elements saraa a a A E EA E AANE 98 A Special Functions ecccececeeeceeeeeeeeeeceeeeeeaeeseaeeseeeeeseaeeeseaeeseneeeaas 98 B Arbitrary behavioral voltage or current Sources 101 Ee lee e EE 107 RH Elle EE 110 E Voltage Dependent Voltage Source sessseeesseeseeeeeere rere nrree nne 113 F Current Dependent Current Gource seetri rererere eene 115 G Voltage Dependent Current SOUICE ssssessesreeeerrreerrrrisrrerreenes 116 H Current Dependent Voltage Gource 117 k Current Source ET 118 Jy JFET transistori ninian ana a i ai 123 K Mutual INGUCtANCE A 126 E INCQUCLON EE 127 KM MOSFET gaer tested opeeds aaa e a aa eet oa 132 O Lossy Transmission Line 143 Q Bipolar transistor 0 cecccceeeeeeceeeeeeeeeseeeeecaeeeeaaeseeeeeseeeeeeaeeeeeeeeaas 145 Paramete S geed ege de eet deed ege d Egeg 151 References A 158 Fe ROSISION ett Seed EE dee ERER de DEENEN Gaetan And 158 S Voltage Controlled Switch
29. create a symbol with the same name as the block schematic and then by placing that symbol on the higher level schematic For example if you have a top level schematic called topxYZ asc and another schematic file called preamp asc that you wish to place in the schematic of topXYZ then create a symbol called preamp asy and place an instance of that symbol on the schematic of topxYZ The electrical connectivity between the schematics is established by connecting wires of the higher level schematic to pins on the lower level block s symbol that matches the name of a node in the lower level schematic As the names of symbols used as schematic blocks and the names of the schematics corresponding to those block must consist of valid characters that can be used as filenames They also cannot contain the space character 32 Fe Linear Technology LTspice SwitcherCAD III preamp asc File Edit Hierarchy View Simulate Tools Window Help AS EP F 0 QQQRQ RBA BSBE seem 44 2492 EE PULSE 1m 1m 0 0 0 5u 10u tran 100u Click to plot 1 N003 LTspice will look in the directory of the top level schematic for symbols and blocks to complete the circuitry of the top level schematic The symbol you create to represent the lower level schematic block should have no attributes defined Navigating the Hierarchy Any file opened with the File gt Open command is considered
30. diffusion area Default MOS source diffusion area Default MOS channel length Default MOS channel width Used for eye diagrams Shifts the bit transitions in the diagram Convert to fastaccess file format at end of simulation Flags external current sources as loads Conductance added to every PN junction to aid convergence Set to zero to prevent gminstepping for the initial DC solution Optional conductance added from every node to ground DC iteration count limit DC transfer curve iteration count limit Transient analysis time point iteration count limit Set to zero to prevent source srcsteps maxclocks maxstep meascplxfmt measdgt method minclocks MinDeltaGmin nomarch noopiter numdgt pivrel pivtol Num Num Num string Num string Num Num Num Num Num 25 Infin Infin bode trap 10 le 4 false false le 3 le 13 stepping for the initial DC solution Alternative name for itl6 maximum number of clock cycles to save Maximum step size for transient analysis Complex number format of meas statement results One of polar cartesian or bode W Number of significant figures used for measure statement output Numerical integration method either trapezoidal or Gear minimum number of clock cycles to save Sets a l
31. editing can be slow If this is a problem with your video card reduce the area of the symbol editing window to speed up screen redraws and or reduce the screen s color resolution This will give better tactical response to mouse movement Drawing the body You draw the body of the symbol as a series of lines rectangles circles and arcs The objects have no electrical impact on the circuit You can also draw text on the symbol with the Draw gt Text command that has no impact on the circuit The anchor points of these objects are drawn with small red circles so you know what to grab when dragging them about You can toggle the red markers off and on with the menu command View gt Mark Object Anchors l l x 3 ei G Adding the Pins The pins allow electrical connection to the symbol Use the menu command Edit gt Add Pin Port to add a new pin 27 Pin Port Properties E Label Pa Netlist Order fi Pin Label Position TOP WEET RIGHT Ze BOTTOM 2 C NONE Not Visible Cancel lv Vertical Text Offset E The Pin Label Position determines how the pin label is presented TOP BOTTOM LEFT and RIGHT are text justifications For example if a pin label is TOP justified the pin the label s text justification s anchor point will be above the label If the symbol represents a SPICE primitive element or a subcircuit froma library then the pin label has no direct electrical impact
32. ehh Adeieg av by Siti ete a 145 R Keesen 158 Rul s of Hierarchy siii e ei a e e EE 32 Runnin s Under Trix e e a e heel een asks aeae AE MR EE Ee 198 S S Voltage Controlled Switches tn a a a 159 Save Plot Conf erageet higeet e ee S REE RA REE tinal e AEEA 54 Schematic E 19 Schematic Se 14 Software Installation EE 5 Specialized Component Editors sisirin hree are a e sheave ee a E e E ets 23 SPICE Error Log Command sissien treise eee era ao E E R E EEEE S 201 Starting the Control Panel 3 13 sess ee n E A E E Een 171 Arr EE 97 Symbol Edin 83s iore aeea e een EA E A E EE 22 T T Lossl ss SAO Eine a aE ee Seele E aE E T 161 Trace Selection seii e a E EEE E EN Aee des EEEE E EE 35 PAD orie are aid ides absinthe Aig tee sel ead doses ae deere 96 97 98 TOGISCALA EE 97 SERA E 96 SE 98 U U Uniform E 161 User Defined Funct ns renesse en e E E E E E 47 V V Voltage opgeet EE EE EEE EAEE e 163 Viewer OVERVIEW See ge eegend dr E R a each 35 W W Current Controlled Switch 167 Wavefomi Arithmetic sekene irena Ere E AE EN ERRENA Zei EESE EE SAS ERRERA en 40 What about a Users S OGrO p ra meere areae e eo E e E ea EER aea EEE e E EER r 199 205 Windows Memory ies nial uti nt elt eens ie ei ee era aati ed eet 56 A X Subcircuit oo cece ceesseesccsccecesssssssececesssesssseeccsesssessssccsesesssesssssceceesessssssseeceessssesesessesseeeees 169 Z Z MESFET AS SOT ee ee Ee ai eee Blac 169 SEH eer AE ENEE E 40 206
33. enclosed expression be replaced with the floating point value 85 Below isa x This is example using both a param statement and directly passing parameters on the subcircuit invocation line the circuit definition params x Xl abod Vl a 0 pul this is subckt di ri nl n2 y y z z 1lk tan pi 4 1 ivider top x bot z sei 10 5p 5p 0 Lui the definition of the subcircuit vider nl n2 n3 top r2 n2 n3 bot ends stran 3p end The parameter substitution scheme is a symbolic rative language The parameters are not passed to decla the subcircuit as evaluated values and r basis toa but by the expressions elations themselves When curly braces are encountered the enclosed expression is evaluated on the of all relations available at the s floating point value cope and reduced The following functions and operations are available Function Name Description abs x Absolute value of x acos x Real part of the arc cosine of x 86 e g acos 5 not 3 14159 2 returns 3 14159 292431 arccos x Synonym for acos acosh x Real part of the arc hyperbolic cosine of x e g acosh 5 returns DU not 1 04721 asin x Real part of the arc sine of x arcsin x asinh x atan x arctan x atan2 y x atanh x buf x cbrt x ceil x cos x cosh x exp x fabs x flat x floor x gauss x
34. for real data Ope Description ran d amp Convert the expressions to either side to Boolean then AND Convert the expressions to either side to Boolean then OR Convert the expressions to either side to Boolean then XOR gt TRUE if expression on the left is greater than the expression on the right otherwise FALSE lt TRUE if expression on the left is less than the expression on the right otherwise FALSE gt TRUE if expression on the left is less than or equal the expression on the right otherwise FALSE lt TRUE if expression on the left is greater than or equal the expression on the right otherwise FALSE ch Addition Subtraction x Multiplication Division 44 FE Raise left hand side to power of right hand side Convert the following expression to Boolean and invert Step selection operator TRUE is numerically equal to 1 and FALSE is 0 Conversion to Boolean converts a value to 1 if the value is greater than 0 5 otherwise the value is converted to 0 The step selection operator is useful when multiple simulation runs are available as ina step temp or dc analysis It selects the data from a specific run For example V 1 3 would plot the data from the 37 run no matter what steps where selected for plotting For complex data only an
35. from an xterm to start the program The schematic fonts don t scale as smoothly under WINE as Windows Why is that WINE is doing the best it can with the fonts it finds It will do better if you tell it how to find the files arial ttf and cour ttf from your Windows system The PWL additional point editor doesn t look right under WINE Try using the native Windows dll from your licensed Windows system The command line to then invoke LTspice from WINE is wine dll commctrl comct132 n scad3 exe It seems LTspice is running slightly differently under WINE Linux than windows Why is that LTspice detects whether or not it s running under WINE f so it works around a few WINE issues You can force LTspice to think it s running under WINE with the command line switch wine You can force it to think it s not with the command line switch nowine in case you re interesting in working on WINE issues What about a Paper Manual You can download a pdf of these help pages from http LTspice linear com software scad3 pdf and print it if you wish What about a Users Group There is an independent users group at http groups yahoo com group LTspice The group has a Files section with additional tutorials libraries and examples 199 LTspice IV Overview LTspice IV is a fourth generation switching regulator design program from Linear Technology The program consists of a high p
36. has two basic modes of driving the simulator Ta Use the program as a general purpose schematic capture program with an integrated simulator and File gt 0pen file type File gt New De Feed the simulator with a handcrafted ne foreign net capture tool LTspice capture program with an in is you draw a circuit or start already drafted Menu commands asc tlist ora list generated with a different schematic Menu command File gt Open file type SCRE IV is intended to be used as a general purpose schematic tegrated SPICE simulator The idea with an example circuit that s and observe its operation in the simulator The design process involves iterating the circuit until the desired circuit behavior is achieved in simulation Earlier versions of LTspice included a synthesizer that would attempt to divine a SMPS design from a user supplied specification but that mode of operation has been obsoleted cf ct The schematic is ultimately converted to a textual SPICE netlist that is passed to the simulator While the netlist is usually extracted from a graphical schematic drafted in LTspice an imported netlist can be run directly without having a schematic This has several uses i Linear Technology s filter synthesis program FilterCAD can synthesize a netlist for LTspice to simulate the time domain or frequency response of a filter ii it sim
37. in every schematic that uses the symbol Prefix X SpiceModel lt name of file including the spicemodel gt Value lt What ever you want visible on the schematic gt 29 Value2 lt The value as you want in the netlist gt Value2 would be made to coincide with a subcircuit name defined in the file including the spicemodel and may pass additional parameters to the subcircuit When a symbol is defined in this manner an instance of the symbol as a component on a schematic cannot be edited to have different attributes If you wish the symbol to represent another page of a hierarchical schematic all attributes should be left blank the symbol type should be changed from Cell to Block No attribute values need be set There is a symbol attribute ModelFile that may be specified This is used for the name of a file to be included in the netlist as a library If the prefix attribute is X and there is a symbol attribute SpiceModel defined that is subcircuit defined in the model file then a drop list of all subcircuits names will be available when an instance of the symbol is edited on a schematic Attribute Visibility You can edit the visibility of attributes using the menu command Edit gt Attributes gt Attribute Window After you select an attribu 30 te with this dialog you will then be able to position it as yo
38. includes that number of harmonics The number of harmonics defaults to 9 if not specified The Fourier analysis is performed over the period from the final time Tend to one period before Tend unless an integer Nperiods is given after Nharmonics If Nperiods is given as 1 the Fourier analysis is performed over the entire simulation data range 66 FUNC User Defined Functions syntax func lt name gt args lt expression gt Example func Pythag x y sqrt x xty y The func directive allows the creation of user defined functions for use with user parameterized circuits and behavioral sources This is useful for associating a name with a function for the sake of clarity and parameterizing subcircuits so that abstract circuits can be saved in libraries The func statement can be included inside a subcircuit definition to limit the scope the function to that subcircuit and the subcircuits invoked by that subcircuit To invoke parameter substitution and expression evaluation with these user defined functions enclose th xpression in curly braces The enclosed expression will be replaced with the floating point value Below is a example using both a func and param statements Example deck using a func statement func myfunc x y sqrt x xty y param u 100 v 600 Vl a 0 pulse 0O 1 0 In In 5p 1p Rl ab myfunc u v 3 C 1 b 0 100p tran 3u end A
39. n region Reveps Width of reverse quad V 0 ilon region This idealized model is used if any of Ron Roff Vfwd Vrev or Rrev is specified in the model The other model available is the standard Berkeley SPICE semiconductor diode but extended to handle more detailed breakdown behavior and recombination current The area factor determines the number of equivalent parallel devices of a specified model Below are the diode model parameters for this diode Na Description Un Def Exam me it aul ple s t Is saturation current A le le 7 14 111 Rs Tt Eg Xt KE Af Fc BV 112 Ohmic resistance Emission coefficient Transit time Zero bias junction cap Junction potential Grading coefficient Activation energy Sat current temp exp Flicker noise coeff Flicker noise exponent Coeff for forward bias depletion capacitance formula Reverse breakdown voltage Current at breakdown voltage Parameter measurement temp Recombination current parameter Inf le 10 27 10 2n 2p Eet ER 0 69 Sbd 0 67 Ge 3 0 jn Sbd 40 50 Nr Tas kf Tr sl Tr s2 It is possib dissipation ratings for a model affect the e if the diode Isr emission coeff 2 High injection knee A Inf current iri Linear Ikf temp 0 coeff Cc linear Rs temp i 0 coeff C Quadrati
40. net V out ref I Rout lt Vin Iin gt Rin lt val gt Rout lt val gt The network input is specified by either an independent voltage source lt Vin gt or an independent current source lt Iin gt The optional output port is specified either with a node V out or a resistor I Rout The ports will be terminated with resistances Rin and Rout If unspecified the termination impedances default to 1 Ohm except in the case of the Voltage source with an Rser specified or an output port specified with a resistor In those two cases the termination resistances defaults to the device impedance Termination values specified on the NET statement will override device impedances for the NET calculation but not for the normal AC node voltages and currents That is the NET statement will not impose terminating impedances on the network for the normal voltages and currents computed as part of the AC analysis See the example file typically installed as C Progra Files LTC LTspicelIV examples Educational S param It recommends using a voltage source V4 with Rser set the desired source impedance and a resistor Rout to set the output termination with a NET statement reading simply net I Rout V4 No Rin or Rout values specified on the net statement and the input output devices supply default termination values This arrangement makes the node voltages and currents of the
41. not scale correctly in metafiles OK that works for bitmaps but can I get the data itself to an application like Excel There is an export utility Waveform Menu File gt Export that allows data to be exported to an ACS file There is alsoa 277 party free utility written by Helmut Sennewald It is available from the independent users group http groups yahoo com group LTspice This utility allows various forms of manipulation of the data including the ability to merge waveforms from different simulation runs Who is Helmut Sennewald The guy on the right 197 Running Under Linux Do you have a Linux version of this program Not a separate edition but it does run under WINE The program has been tested on Linux RedHat 8 0 with WINE version 20030219 RedHat 9 0 with WINE 20040716 and SuSE 9 1 with 20040716 OK I ve never used WINE how do I install this Check with http www winehq com to find the current version of WINE for your system At the time of this writing for RedHat 8 0 this pointed to http mecano gme usherb ca vberon wine Copy the appropriate rpm file to your machine and open it from nautilus Get the file LTspicelV exe from http www linear com In an xterm execute wine LTspicelV exe to install LTspice 198 There will now be a Linear Technology Logo on your gnome desktop Double click it to start or type wine LTspicelIV exe
42. on the circuit However if the symbol represents lower level schematic of a hierarchical schematic then the pin name is significant as the name of a net in the lower level schematic The Netlist Order determines the order this pin is netlisted for SPICE Adding Attributes You can define default attributes for a symbol using the menu command Edit gt Attributes gt Edit Attributes The most important attribute is called the Prefix This determines the basic type of symbol If the symbol is intended to represent a SPICE primitive the symbol should have the appropriate prefix R for resistor C or capacitor M for MOSFET etc See the LTspice reference for a complete set of SPICE primitives available The 28 prefix should be X if you want to use the symbol to represent a subcircuit defined in a library Symbol Attribute Editor ES SpiceModel Value Value2 SpiceLine SpiceLine2 The symbol s attributes can be overridden in the instance of the symbol as a component in a schematic For example if you have a symbol for a MOSFET with a prefix attribute of M it s possible to override the prefix to an X on an instance by instance basis so that the transistor can be modeled as subcircuit instead There is a special combination of attributes that will cause a required library to be automatically included
43. other than point PD and PS default to zero while N The model card keyword VDMOS Nd Ng NS S Note that the suf If any of L W AD D an VGS optional TEMP value is d width d source fix u or AS d PS are s in number of UES the MODEL R D and NRS the device 133 this device is to operate and overrides the temperature specification on the OPTION control line The temperature specification is ONLY valid for level 1 2 3 and 6 MOSFETs not for level 4 5 or 8 BSIM devices LTspice contains seven different types of monolithic MOSFET s and one type of vertical double diffused Power MOSFET There are seven monolithic MOSFET device models The model parameter LEVEL specifies the model to be used The default level is one level model 1 Shichman Hodges 2 MOS2 see A Vladimirescu and S Liu The Simulation of MOS Integrated Circuits Using SPICE2 ERL Memo No M80 7 Electronics Research Laboratory University of California Berkeley October 1980 3 MOS3 a semi empirical model s reference for level 2 4 BSIM see B J Sheu D L Scharfetter and P K Ko SPICE2 Implementation of BSIM ERL Memo No ERL M85 42 Electronics Research Laboratory University of California Berkeley May 1985 J BSIM2 s Min Chie Jeng Design and Modeling of Deep Submicrometer MOSFETs ERL Memo Nos
44. refer to a range over the abscissa The first version those that point to one point on the abscissa are used to print a data value or expression thereof at a specific point or when a condition is met The following syntax is used Syntax MEAS SURE AC DC OP TRAN TF NOISE lt name gt 73 lt FIND DERIV PARAM gt lt expr gt WHEN lt expr gt AT lt expr gt TD lt vall gt lt RISE FALL CROSS gt lt count1 gt LAST Note one can optionally state the type of analysis to which the MEAS statement applies This allows you to use certain MEAS statements only for certain analysis types The name is required to give the result a parameter name that can be used in other MEAS statements Below are example MEAS statements that refer to a single point along the abscissa MEAS TRAN resl FIND V out AT 5m Print the value of V out at t 5ms labeled as resl MEAS TRAN res2 FIND V out I Vout WHEN V x 3 V y Print the value of the expression V out I Vout the first time the condition V x 3 V y is met This will be labeled res2 MEAS TRAN res3 FIND V out WHEN V x 3 V y cross 3 Print the value of V out the third time the condition V x 3 V y is met This will be labeled res3 MEAS TRAN res4 FIND V out WHEN V x 3 V y rise last Print the value of V out the last time the condition V x 3 V y is met
45. scroll as you move the mouse close the edge while editing the schematic Mark text Justification anchor points Draw a small circle to indicate the reference point of text blocks Mark unconnected pins Draw a small square at each unconnected pin to flag it as unconnected Show schematic grid points Start with visible grid enabled 181 Orthogonal snap wires Force wires to be drawn in vertical and horizontal segments while drawing If not checked a wire can drawn at any angle and will snap to any grid Holding down the control key will momentarily toggle the current setting while drawing wires Cut angled wires during drags During the Drag command a non orthogonal wire will be broken into two connected wires if you click along the middle of the wire Undo history size Set the size of the undo redo buffer Draft with thick lines Increases the all line widths Useful for generating images for publication Show Title Block For internal use Internet Options 182 Control Panel http LT spice linear tech com gt Default Recommended gt SGT WSU Ee EEA ElSzetl zs Passworar This pane of the Control Panel is used for the incremental updates obtained from the web LTspice is often updated with new features and models Use the menu command Tools gt Sync Release to update to the current version If you don t update for a couple months LTspice will begin to ask if y
46. sectional area and thin or uniformly distributed gap 131 Below is an example that shows inductance vs current for Ll an inductor wound on a gapped core You can read out the inductance as V n001 since current source Il supplies a unity dI dt The core follows the initial magnetization curve so you can see that the permeability first increases from the initial value as the current is ramped and then drops as it saturates Since the gap makes the inductance insensitive to the exact permeability of the core you have to really zoom in on V n001 to see that it does increase The peak is when H inside the core is equal to its Hc ja 1 NOO1 0 Hc 16 Bs 44 Br 10 A 0 0000251 Lm 0 0198 Lg 0 0006858 N 1000 I1 0 NOO1 PWL O O 1 1 eteran so options maxstep 10u end M MOSFET Symbol Names NMOS NMOS3 PMOS PMOS3There are two fundamentally different types of MOSFETS in LTspice monolithic MOSFETs and a new vertical double diffused power MOSFET model Monolithic MOSFET Syntax Mxxx Nd Ng Ns Nb lt model gt m lt value gt L lt len gt W lt width gt AD lt area gt AS lt area gt PD lt perim gt PS lt perim gt NRD lt value gt NRS lt value gt off IC lt Vds Vgs Vbs gt temp lt T gt M1 Nd Ng Ns 0 MyMOSFET model MyMOSFET NMOS KP 001 132 M1 Nd Ng Ns Nb MypMOSFET model MypMOSFET PMOS KP 001
47. statement to the file typically installed as C Program Files LTC LTspicelIV lib cmp standard bjt If you do that you will automatically s the model as a choice was editing the NPN transistor If you edit this standard bjt file outside of LTspice you will have to restart LTspice for it to notice that the file has change Example for a 5 SUBCKT stateme d pin opamp This will be defined with a ne 1 Add an instance of symbol opamp2 to your schematic 187 2 Edit the value opamp2 to TLO72 on the schematic to coincide with the name of the SUBCKT 3 Hither 3a Paste the SUBCKT TLO72 ENDS definition as one multi line SPICE directive to your schematic 3b If you have a file called TI 1lib containing the definition of subcircuit TLO72 It will look like a line that starts out as SUBCKT TLO72 add the SPICE directive INCLUDE TI lib to the schematic It is possible to create a new symbol and program it to automatically include the necessary model for the Simulation See help section Schematic Capture gt Creating New Symbols Example for a 3 pin NPN transistor but defined with a SUBCKT statement 1 Add an instance of symbol NPN to your schematic 2 Move the cursor over the body of the newly placed NPN symbol instance Press lt Ctrl gt RightMouseButton Adialog box will appear Change Pref
48. the menu command Tools gt Control Panel There you can configure many aspects of LTspice IV Compression Control Panel LTspice compresses the raw data files as they are generated A compressed file can be 50 times smaller than the un compressed one This is a lossy compression This pane of the control panel allows you to control how lossy the compression runs Window Size No of Points Maximum number of points that can be compressed into two end points 171 Relative Tolerance The relative error allowed between th compressed data and the uncompressed data Absolute Voltage tolerance V The voltage error allowed by the compression algorithm Absolute Current tolerance A The current error allowed be the compression algorithm These compression settings are not remembered between program invocations to encourage use of the defaults They are available on the control panel for diagnostic purposes The tolerances and window size can be specified with option parameters plotreltol plotvntol plotabstol and plotwinsize in option statements placed as SPICE directives on the schematic File Size Vs Fidelity study 172 F 4 Linear Technology SwitcherCAD III full raw File View Window Help Viez Step Step Response BCompressed File 16KB LT1613 Step Response E E Compression 2 ssion AV S Operation 173 Control Panel on Z SaveDetute 3 Wie
49. times for a switch mode power supply must be in minutes no There have b t hours for a simulator to be useful tion methods that have n analog circuit simulat shown some success in speeding up swit tch mode power supply simul don com int con times flexibility for arbit pl LTspice is a new SPICE circuits fast enough i interactive Incorporat element parasit or internal nodes Also developed for power MOSFET s usual gate charge behavior wi internal nodes that was developed to make simulation of complex SMPS syst ted into the new SPI ts to model practical board level components and inductors can be modeled with series resistance and ot tic aspects of their behavior without using sub circ a Simulation circuit element was lation but at a cost of making simplifying assumptions which t allow arbitrary control logic and fully simulate the lexity of the switching waveforms egrated logic primitives that perform the switch mode trol provides a better answer yield detailed waveforms trary circuit modificat A new SPICE with simulation the It can give fast and still allows tions to simulate analog tems CE are circuit Capacit tors ther uits that accurately exhibit thout using sub circuit Reducing the number of nodes the simulator ts their ts or needs to solve significantly reduces the computation required f
50. to be displayed in your web browser that explains the error LTspice can t always read these pages as error conditions so you may get some cryptic error message when the simulation tries to proceed with the included html language error page included in the simulation as valid SPICE syntax If the http transferred url is a pdf file the simulation will abort after the download For example the following deck will download this manual as a pdf file Dummy Simulation to download the help file The simulation will abort with an error but you ll be left with the file scad3 pdf in the same directory containing the netlist inc http ltspice linear com software scad3 pdf end LIB Include a Library Syntax lib lt filename gt This directive includes the model and subcircuit definitions of the named file as if that file had been typed into the netlist instead of the lib command Circuit elements at global scope are ignored An absolute path name may be entered for the filename Otherwis LTspice looks first in the directory lt LTspicelIV gt lib cmp and then lt LTspicelIV gt lib sub and then in the directory that contains the calling netlist where lt LTspicelV gt is the directory containing the scad3 exe executable typically installed as C Program Files LTC LTspicelv 70 No file nam xtension is assumed
51. when approached as V x increasing wrt 3 V y This will be labeled res4 MEAS TRAN res5 FIND V out WHEN V x 3 V y cross 3 TD 1m Print the value of V out the third time the condition V x 3 V y is met but don t start counting until the time as elapsed to lms This will be labeled res5d 74 MEAS TRAN resp PARAM 3 resl res2 Prin t in ta no da such as V 3 evaluated but if they are the value of 3 resl res2 printing expressions of other meas s tended that expressions based are present in simulated point dependent variables The result Note that the above examples whi the abscissa the requested result will be label This form is useful for tatement results on direct simulation the expression to be the data is taken from the last It s d res6 le referring to one point along t is based on ordinate data If no ordinate information is requested the then the MEAS statement prints point on the abscissa that the measurement condition occurs MEAS TRAN resp WHEN V x 3 V y Print the first time the condition V x 3 V y is met This will be labeled res6 The other type of MEAS statement refers to a range over the abscissa The following syntax is used Syntax MEAS AC DC OP TRAN TF NOISE lt name gt SE lt AVG MAX MIN PP RMS INTEG gt lt expr gt TRIG
52. window The reciprocal of the value of window is the frequency resolution The value of nfft times this resolution is the highest frequency considered The Boolean XOR operator is understood to mean exponentiation when used in a Laplace expression Syntax Gxxx n n value lt expression gt This is an alternative syntax of the behavioral source arbitrary behavioral voltage source B Syntax Gxxx n n POLY lt N gt lt nodel nodel node2 node2 nodeN nodeN gt lt c0 cl c2 c3 c4 gt This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models H Current Dependent Voltage Source Symbol Name H Syntax Hxxx n n lt Vnam gt lt transresistance gt This circuit element applies a voltage between nodes n and n The voltage applied is equal to the value of the gain times the current through the voltage source lt Vnam gt Syntax Hxxx n n value lt expression gt 117 This is an alternative syntax of the behavioral source arbitrary behavioral voltage source B Syntax Hxxx n n POLY lt N gt lt V1 V2 V3 gt lt c0 cl c2 c3 C4 ee This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models I Current Source Symbol Name CURRENT Syntax Ixxx n n lt c
53. 1 Web Update 202 Introduction Preface Do we need another SPI CE Analog circuit simula design SPICE simula prior to integration onto a chi allows measurements of cu impossible to do any oth er wa tion has been inseparable from anal tors are the only way to ch p rrents and voltages that are virtu Vy og IC eck circuitry Further the SPICE simulation ally alog The success of these an circuit simulators has made circuit simulation spread to board level circuit design rather than breadboard and th in the simulation for performan of well understood robust ci Given the number of commercial should a new simulator be wri It is easier in many cases e LY E functions are extremely diffic ei available SPICE simulators overall loop response ten to simulate the circuit ability to analyze ce and problems speeds the design reuits available SPICE simulators why Because certain analog t to simulate with commercially Switch mode power supplies have fast high frequency switching square waves as well as slow This means simulations must run for thousands to hundreds of thousands of cycles the overall response of a switching regulator in order to see Commercially lable SP lation method Simula aval simul ICE s simply take too long for this to be a useful tion
54. 1 to 32 bits lt SampleRate gt is the number of samples to write per simulated second The valid range is 1 to 4294967295 samples be second The remainder of the syntax lists the nodes that you wish to save Each node will be an independent channel in the wav file The number of channels may be as few as one or as many as 65535 It is possible to write a device current e g Ib Q1 as well as node voltage The wav analog to digital converter has a full scale range of 1 to 1 Volt or Amp Note that it is possible to write wav files that cannot be played on your PC sound system because of the number of channels sample rate or number of bits due to limitations of your PC s codec But these wav files may still be used in LTspice as input for another simulation See the sections LTspice gt Circuit Elements gt V Voltage Source and I Current source for information on playing a wav file into an LTspice simulation If you want to play the wav file on your PC sound card keep in mind that the more popularly supported wav file formats have 1 or 2 channels 8 or 16 bits channel and a sample rate of 11025 22050 or 44100 Hz 95 Transient Analysis Options TRAN Modifiers UIC Skip the D C operating solution and use user specified initial conditions steady Stop the simulation when steady state has been reached nodiscard Don t delete the part of the transient simulation before steady state is reac
55. CC SO 156 Activation Activation Activation BCI BEIP BCIP Activation Activation Activation BCN BENP IBCNP Tempe Tempe Activation energy for IS energy for IBE energy for energy for energy for IBEN energy for energy for rature exponent of IS rature exponent of BEL BCI BEIP IBCIP Tempe rature exponent of BEN BCN BENP IBCNP Tempe Tempe AVC2 Therm Therm Punch rature exponent of NF rature exponent of al resistance al capacitance through voltage of internal B C junction Smoothing parameter for reach through Fixed C S capacitance K W Ws GO CH qb nk kf xr CX xr xr bp is EE sr de ar ea vb be nb be ib be bb el bb e2 tn bb Select SGP gb formulation High current beta rolloff Temperat IKF Temperat RCX Temperat RBX Temperat RBP Separate Ee re re re expon expon expon expon ent ent ent en of of of of Temperature exponent of ISR Excitation en B E breakdown B E breakdown coefficient B E breakdown current Linear temperatu coefficient of VBBE Quadratic tempera
56. ERL M90 90 Electronics Research Laboratory University of California Berkeley October 1990 134 6 MOS6 see T Sakurai and A R Newton A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series connected MOSFET Structure ERL Memo No ERL M90 19 Electronics Research Laboratory University of California Berkeley March 1990 8 BSIM3v3 3 0 from University of California Berkeley as of July 29 2005 9 BSIMSOI3 2 Silicon on insulator from the BSIM Research Group of the University of California Berkeley February 2004 12 EKV 2 6 based on code from Ecole Polytechnique Federale de Lausanne See http legwww epfl ch ekv and The EPFL EKV MOSFET Model Equations for Simulation Version 2 6 M Bucher C Lallement F Theodoloz C Enz F Krummenacher EPFL DE LEG June 1997 14 BSIM4 6 1 from the University of California Berkeley BSIM Research Group May 18 2007 The DC characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters VTO KP LAMBDA PHI and GAMMA These parameters are computed if the process parameters NSUB TOX are given but user specified values always override VTO is positive negative for enhancement mode and negative positive for depletion mode N channel P channel devices Charge storage is modeled by three constant capacitors CGSO CGDO and CGBO which represent overlap
57. G V onoise MEAS NOISE in_totn INTEG V inoise to a noise analysis the total integrated input and output referenced rms noise will be printed in the log file MEAS statements are done in post processing after the simulation is completed This allows you to write a script of MEAS statements and execute them on a dataset To do this make the waveform window the active window and execute menu command File gt Execute MEAS Script Another consequence of MEAS statements being done in post processing after the Simulation is that the accuracy of the MEAS statement output is limited by the accuracy of the waveform data after compression You may want to adjust the compression settings for more precise MEAS statement output Note when testing a condition such as when lt condl gt lt cond2 gt you will want the condition to go through the equality not must meet it This relates to the fact that floating point equality should never be required due to the finite precession used in storing numbers MODEL Define a SPICE Model 77 Defines a model for a diode transistor switch lossy transmission line or uniform RC line Some circuit elements for example transistors have many parameters Instead of defining every transistor parameter for every instance of atransistor transistors are grouped by model name and have parameters in common The transistors of the same
58. Ixxx n n wavefile lt filename gt chan lt nnn gt This allows a wav file to be used as an input to LTspice lt filename gt is either a full absolute path for the wav file or a relative path computed from the directory containing the simulation schematic or netlist Double quotes may be used to specify a path containing spaces The wav file may contain up to 65536 channels numbered 0 to 65535 Chan may be set to specify which channel is used By default the first channel number 0 is used The wav file is interpreted as having a full scale range from 1A to 1A This source only has meaning in a tran analysis J JFET transistor Symbol Names NJF PJF Syntax Jxxx D G S lt model gt area off IC Vds Vgs temp T Examples J1 0 in out MyJFETmodel model MyJFETmodel NJF Lambda 001 J2 0 in out MyPJFETmodel model MyPJFETmodel PJF Lambda 001 A JFET transistor requires a model card to specify its characteristics Note that the model card keywords NJF and PJF specify the polarity of the transistor The area factor determines the number of equivalent parallel devices of a specified model 123 Th an th dr ou ga Ch ca po Cg Pa Si e JFET model is derived from the FET model of Shichman and Hodges extended to include Gate junction recombination current d impact ionization e parameters VTO and BETA ain current with gate voltage tput conductance te junctions
59. Settings gt Visible Traces is the dialog seen at the beginning of plotting data from a simulation It lets you select the initial traces to start the plot It also gives you random access to the full list of traces plotted Select Visible Waveforms Select Waveforms to Plot Ctrl Click to toggle AltDouble Click to enter an expression 38 ER Menu command View gt Add Trace The Plot Settings gt Add Trace command is similar to the Plot Settings gt Visible Traces command However you can not delete traces that are already visible with it It has two useful capabilities One is an edit box near the top of the dialog that allows you to enter a pattern of characters Only trace names that match the pattern will be shown in the dialog This is very useful for finding a trace when you can only partially remember the name Also it s a bit easier to compose an expression of trace data because you can click on a name in the dialog instead of typing out its name Rit year Technology LTspice SwitcherCAD III butter asc of x File View Tools Window Help Aa P F 0 QQQR Seid SS AS o GQ faa butter asc 0 6 0 4 UEA 0 0 O2V O0 4V m Only list traces containing 3 X Cancel Expression s to add C24 1 C32 39 Zooming LTspice IV autozooms whenever there is new data to plot To zoom up on an area simply drag a box about the region you wish to see drawn larger
60. Table of Contents Introduction 4 PrefaC ried secsistesicrstehenastacckees vaca taactinabs TEA PETE EEEE T 4 Hardware Requirement ccceccceceseececeeeeneeeeeeeaeeeeeseeneeseeaneeeeeeeneeeseeeneeees 5 software Installations sgeirean eenia neea ea aaa a eaaa en deed 5 License Agreement uscamer 6 Mode of Operation 7 OV OIVIGW ee Ee ee H SE CAAA E A nevi ten tesla dE EE 8 General Purpose Schematic Driven SPICE eccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeees 9 Externally Generated Netlists 0 c ccecceeseeeeceeeeeeeeeeeeeeseeeeeseaeeesaeeeseeseenes 10 le Ge a EE 11 Command Line Switches c cccccceceeeeeeeeeeeeeeeeeeeecaeeeeeaeeeeeeesaeeesaaeseeeeeeaas 13 Schematic Capture 14 Basic Schematic Editing ccccceeeseeceeeeeeeeeeeeeeeeeeeeeseaeeeeeaeseeeeeesaeeneneeseaees 14 Labela node Tu 17 Eelere e EE 19 Placing New Components sseesseeseeeiesiesiesississrinttinstnnstnnttnnntnnnnnnnnnnne 20 Programming Keyboard Shortcuts cccceeeeceeeeeeeeeeeeeeeeeesecaeeeseaeeeeeeesaees 20 PCB Netlist Extraction 0 0 cccccececceseeeceeseeeeneeceeeeeseaeeeeaaeseeneeeseaeeesaaesseneessaees 21 Editing Components isidin aneii anin aiidis 22 Edit a Visible Attribute AAA 22 Specialized Component Editors eeceeeeeeceeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeaees 23 General Attribute Editor 24 Creating New SyMbols 0 ccccceeeeeeeeeeeeeeeeeeee scenes ceaeeecaaeeeeeeeesaeeesaeeeeeeeeaas 26 Symbol Editi
61. Technology for help For all software issues e mail LTspice linear com For all hardware issues such as additional application information for Linear Technology IC s call Linear Technology application department at 408 954 8400 during normal business hours Circuit Efficiency Calculation What is the difference between APP and ASC files An APP file is a schematic file and has embedded control statements to help calculate efficiency and other product information ASC file is the general schematic file without any hidden SPICE commands ASC file is the more general and powerful file format It is recommended that you save your own designs with a ASC file name extension How can I get an efficiency report for my schematic 193 You need to add a TRAN lt time gt steady statement on the schematic The program will automatically detect the steady state by checking the internal state of the LTC macro models It doesn t work when LTC switching regulator part is absent There must be exactly one Voltage source in the circuit This will be identified as the input There must be exactly one current source in the circuit This will be identified as the load After the simulation is done you can select the Efficiency Report under the View menu to see the report on the schematic Custom Symbols Can I create my own symbols Yes you can create your own symbols
62. Tools gt Export Netlist allows you to generate the ASCII netlist for PCB layout Note that you would have to make a set of symbols that have the same order of pin netlist order For example if you want to import an LTspice schematic s netlist into ExpressPCB you would have to make a set of symbols for either LTspice or ExpressPCB that had the same netlist order for every symbol you use Otherwise diodes could netlist backwards or transistor lead connections could be scrambled The following formats are available Accel Algorex Allegro Applicon Bravo Applicon Leap Cadnetix Calay Calay90 CBDS Computervision EE Designer ExpressPCB Intergraph Mentor Multiwire PADS Scicards Tango Telesis Vectron and Wire List 21 Editing Components Editing Components Components can be edited in two or three different ways depending on the type of component 1 Most visible component attribute fields can be edited by pointing at it with the mouse and then right clicking The mouse cursor will turn into atext caret when it s pointing at the text 2 Many component types such as resistors capacitors inductors diodes bipolar transistors MOSFET transistors JFET transistors independent voltage sources independent current sources and hierarchical Circuit blocks have special editors These editors can access the appropriate database of devices To use these editors right mouse click on the body of the component
63. Vertical double diffused power MOSFET Syntax Mxxx Nd Ng Ns lt model gt L lt len gt W lt width gt M lt area gt m lt value gt off IC lt Vds Vgs Vbs gt temp lt T gt Example The MOSFET s model card specifies which type is intended M1 Nd Ng Ns Si441 model Si4410DY VDMOS Rd 3m Rs 3m Vto 2 6 Kp 60 Cgdmax 1 9n Cgdmin 50p Cgs 3 1n Cjo l1n Ts 5 5p Rb 5 7m ODY The model card keywords NMOS and PMOS specify a monolithic N or D channel MOSFET transistor specifies a vertical double diffused power MOSFET Monolithic MOSFETS are four terminal devices and Nb are the drain substrate nodes L and W are the channel length an D and AS are the areas of the drain an in meters diffusions specifies um and p square um are not specified default values are used PI ters of the drain and source junction D and NRS designate the equivalent squares of the drain and source diffusions these val tiply the sheet resistance RSH specified on the mult meters gate source and bulk A in square meters perime NRI con for the trol to one using DC The line OFF indicates an initial condition on The initial condition specification VBS is for use with the UIC option on when a transient analysis is the quiescent operating the temperature at which analysis IC VDS TRAN control line desired starting from
64. Whenever a diode is used in an LTspice schematic the default model statement model D D is added 178 to the netlist to suppress messages about using the default model Unchecking this option suppresses inclusion of this line as well as the analogous model statements for bipolar MOSFET and JFET transistors Default Libraries Whenever a diode is used in an LTspice schematic the default library standard dio is included in the simulation by a lib statement Unchecking this option suppresses inclusion of this library as well as the analogous library statements for bipolar MOSFET and JFET transistors Convergence Aids For Internal program development use only Control Panel Hacks This pane was used for internal program development but is currently almost obsolete 179 Usually you can leave these options as they are If you have frequently updated the program over the web you might want to press Reset to Default Values to reset to the current recommended settings Control Panel mak i Lag Drafting Options 180 Control Panel LS 1 ee Hole _ Allow direct component pin shorts Normally you can draw a wire directly through a component and the wire segment shorting pins is deleted If you check it the shorting wire will not be automatically deleted Automatically scroll the view Checking this box makes the view of the schematic
65. You must use 1lib myfile lib not libmyfile if the file is called myfile 1lib It is possible to specify a URL of the following form as a file name lib http www company com models library mod The file library mod will be http transferred to the circuit directory and included as a library For subsequence simulations in the interest of avoiding downloading the file each time you run the simulation you can edit the lib statement to lib library mod Note that if the URL you specify doesn t exist most web servers don t return an error but return a html web page to be displayed in your web browser that explains the error LTspice can t always read these pages as error conditions so you may get some cryptic error message when the simulation tries to proceed with the included html language error page included in the simulation as valid SPICE syntax If the http transferred URL is a pdf file the simulation will abort after the download For example the following deck will download this manual as a pdf file Dummy Simulation to download the help file The simulation will abort with an error but you ll be left with the file scad3 pdf in the same directory containing the netlist lib http ltspice linear com software scad3 pdf end ZZ F Encrypted Libraries 71 LTspice can generate and read a special form of encrypted libraries This allows one u
66. a The amount of output can be restricted by using the save directive to save only the specific node voltages and device current of interest Syntax Save V out V in I L1 1 S2 dialogbox The directive save 1 Q2 will save the base collector and emitter currents of bipolar transistor Q2 To save a single terminal current specify Ic Q2 The wildcard characters and can be used to specify data traces matching a pattern For example save V Id will save every voltage and every drain current If the keyword dialogbox is specified then a dialog box with a list of all available default nodes and currents is displayed allowing the user to select from the list which should be saved If the netlist was generated from a schematic then nodes and devices can be pointed to and clicked on in the schematic to highlight them as selected in the dialog box SAVEBIAS Save Operating Point to Disk Syntax savebias lt filename gt internal temp lt value gt time lt value gt repeat step lt value gt DCl lt value gt DC2 lt value gt DC3 lt value gt This command writes a text file to disk that is reloaded with a loadbias command in a subsequent simulation If you have a circuit that has a difficult to solve DC operating point you can save that solution to disk so that the next analysis can save time finding the DC solu
67. able for general use The improved performance of the SPICE simulation engine is a benefit for simulating general analog circuits and should be of interest to all electronic engineers There are no arbitrary limits on component count or content With an installed base of over 2 000 000 licenses so far LTspice has arisen as the de facto standard SPICE simulator We hope you enjoy the program and find it useful 200 Fe Linear Technology LTspice SwitcherCAD III LT1613 app File Edit View Simulate Tools Window Help As OTF 9 QOQ8 BC BSY sBEM AS LLH 2 3 dVO 300mA 240mA 180mA 120mA 60mA OmA 80us 160s 240s 320s 400s 480s 560us 640s 720s 800us SPICE Error Log Command Use this command to display the simulation log file Atypical log file is shown as follows Circuit Ds XP lib app LT1300 DCO35A app Date Tue Oct 05 16 57 31 1999 Total elapsed time 6 64 seconds tnom 27 temp 27 method modified trap totiter 14872 traniter 14862 tranpoints 3865 accept 2986 rejected 879 trancuriters 0 201 matrix size 12 fillins 2 solver Normal Web Update All windows must be closed first before the sS can be activated The user ne eds to establish the internet 1l then download the ync_Release command connection first The LTspice master index file release log IV program w
68. able summarizes the command line switches understood by the LTspice executable scad3 exe Flag ascii b big encryp ie FastAc cess SINI lt path gt max netlis Use ASC raw files Description performance Run in batch mode Seriously degrades program E g scad3 exe b deck cir will leave the data in file deck raw Start as a maximized window Encrypt a model library to allow people to use revealing impl For 3 parties wishing libraries without Not used by ementation details Linear Technology Corporation models Batch conversion of a binary Access format Specify an SWIND raw file to Fast ini file to use other than R scad3 ini Synonym for big Batch conversion of a schematic to a netlist 13 nowine Prevent use of WINE Linux workarounds PCBnet Batch conversion of a schematic to a PCB format list netlist regist Force LTspice to store user preferences MRU ry etc in the registry instead of the WINDIR scad3 ini file ol Run Start simulating the schematic opened on the command line without pressing the Run button SOI Allow MOSFET s to have up to 7 nodes even in subcircuit expansion uninst Executes one step of the uninstallation process all web Equivalent to executing menu command Tools gt Sync update Rel
69. ameter 1 B C weak ava parameter 2 C Ideal B C emission mission lanche lanche Parasitic transport saturation current Portion of Parasitic fwd emission coefficient ICCP Ideal parasitic B E saturation current Non ideal parasitic B E saturation c saturation c urrent Ideal parasitic B C urrent Ideal parasitic B C emission coefficient Non ideal parasitic B C saturation current Non ideal parasitic B C emission coefficient Forward Ear y vol Reverse Earl y vol tage tage 1 V 1 V oO Infin Infin xr bi xr xr XV Forward knee current Reverse kn current Parasitic knee current Ideal forward transit time Variation of TF with base width modulation Coefficient for bias dependence of TF Voltage giving VBC dependence of TF High current dependence of TF Ideal reverse transit time Forward excess phas delay time B E Flicker Noise Coefficient B E Flicker Noise Exponent B E Flicker Noise 1 f dependence Temperature exponent of RE Temperature exponent of RBI Temperature exponent of RCI Temperature exponent of RS Temperature exponent of VO Sec Dec Infin Infin Infin Infin Infin O i Les 155 ea ea ie ea ic ea is
70. ameters Arbitrary behavioral Bxx n n lt V or I gt source Capacitor Cxx n n lt capacitance gt ic lt val gt Rser lt val gt Lser lt val gt Rpar lt val gt Cpar lt val gt m lt val gt Diode Dxx A K lt model gt area voltage Exx n n nct re lt gain gt Current dependent current Fxx n n lt Vnam gt lt gain gt Voltage dependent current Gxx n n net ne lt transcond gt Current dependent voltage Hxx n n lt Vnam gt lt transres gt Voltage dependen ITT 62 Independent current Ixx n n lt current gt source JFET transistor Jxx D G S lt model gt area off IC lt Vds Vgs gt temp lt T gt Mutual inductance Kxx Ll L2 L3 lt coeff gt Inductance Lxx n n lt inductance gt ic lt val gt Rser lt val gt Rpar lt val gt Cpar lt val gt m lt val gt MOSFET transistor Mxx D GS B lt model gt L lt len gt W lt width gt AD lt area gt AS lt area gt PD lt perim gt PS lt perim gt NRD lt value gt NRS lt value gt off IC lt Vds Vgs Vbs gt temp lt T gt Lossy transmission line Oxx L L R R lt model gt Bipolar transistor QOxx C B E S lt model gt area off IC Vbe Vce temp lt T gt Resistor Rxx nl n2 lt value gt Voltage controlled switch Sxx n1 n2 nc
71. an Four quadrant arc tangent of y x Arc hyperbolic tangent if x gt 5 else 0 Integer equal or greater than x Cosine of x Hyperbolic cosine of x Time derivative of x Same as absdelay e to the x Integer equal to or less than x sqrt x 2 y 2 Integrate x optional initial condition ic reset if ais true Integrate x optional initial condition ic reset on reaching 103 if x y z int x inv x limit x y z in x log x log10 x max x y min x y pow x y pwr x y pwrs x y rand x random x round x sdt x ic assert sgn x sin x sinh x sqrt x table x a b c d tan x 104 modulus m offset output by o If x gt 5 then y else z Convert x to integer D if x gt 5 else l Intermediate value of x y and z Natural logarithm of x Alternate syntax for In Base 10 logarithm The greater of x or y The smaller of x or y Real part of x y e g pow 1 5 0 not i abs x y sgn x abs x y Random number between 0 and 1 depending on the integer value of X Similar to rand but smoothly transitions between values Nearest integer to x Alternate syntax for idt Sign of x Sine of x Hyperbolic sine of x Square root of x Interpolate a value for x based on a look up table given as a set of pairs of points Tangent o
72. an Small Signal AC Analysis Linearized About the DC Operating Point DEE 64 BACKANNO Annotate the Subcircuit Pin Names to the Port Currents65 DC Perform a DC Source Sweep Analysis cccceeeeeeeeteeeeereeees 65 END End of Neat 2 2eedeeeg Deeg ee cd devs videcds ues 66 ENDS End of Subcircuit Definition ec eeeeee eee eeeete teens eeeeeees 66 FOUR Compute a Fourier Component after a TRAN Analysis 66 FUN User Defined Functions cccceececeeeeeeeeeeeeeeeeeseaeeeeaeeneeeees 67 FERRET Download a File Given the UL 68 IC Set Initial Conditions ANE 68 INCLUDE Include Another Elei 69 HB INGlUde a Bee EE 70 LOADBIAS Load a Previously Solved DC Solution cceeeeee 73 MEASURE Evaluate User Defined Electrical Ouanities 73 MODEL Define a SPICE Model 77 NET Compute Network Parameters in a AC Analvsls 78 NODESET Supply Hints for Initial DC Solution cece 79 NOISE Perform a Noise Analysis cccccceeeeeeseeeeeeeeeceaeeeeaeeeeneeee 80 OP Find the DC Operating Point 81 OPTIONS Set Simulator Options cececeeeeeeeeeeeeeeeeeeeeeeeeeteeeee 81 PARAM User Defined Parameters c cccccceseeeeeeeeeeeieeeeneeeeeeeeees 85 SAVE Limit the Quantity of Saved Data 90 SAVEBIAS Save Operating Point to Disk 0 cceeeeceseeeeeeseeeeeeeees 90 STEP Parameter Gweepe AA 91 SUBCKT Define a Gubcireun eee eee
73. an error message that that file can t be found Is there a tool for generating native LTspice VDMOS MOSFET models instead of subcircuits Yes Hendrik Jan Zwerver developed a free VDMOS tool that is distributed from the Files section of the independent users group http groups yahoo com group LTspice ct ct Who is Hendrik Jan Zwerver The guy on the right 191 LE VIII Paris Nov 20 2006 License and Distribution Can I re distribute the software Yes you can distribute the software freely whether you are a Linear Technology customer or not See the license section for more details Technical support for non Linear Technology customers is purely discretionary Is it a shareware freeware or demo 192 This program is not a shareware or a demo It is fully functional freeware The purpose of this software is to help our customers use our products It can also be used as a general purpose circuit design package with schematic capture and SPICE Simulation We do encourage students using the program to become familiar with the analog design process We cannot guarantee support for non Linear Technology related program usage but we ll fix all general program bugs and appreciate such reports We do extensive in house testing and believe the program has superior convergence capability There are no known outstanding bugs Who can I contact at Linear
74. and lt EndFregq gt define the frequency range of interest and resolution in the manner used in the ac directive Output data trace V onoise is the noise spectral voltage density referenced to the node s specified as the output in the above syntax If the input signal is given as a voltage source then data trace V inoise is the input referred noise voltage density If the input is specified as a current source then the data trace inoise is the noise referred to the inpu current source signal The noise contribution of each component can be plotted These contributions are referenced to the output You can reference them to the input by dividing by the data trace gain CF e 80 The waveform viewer can integrate noise over a bandwidth by lt C da trl Key gt ta trace label left mouse button clicking on the corresponding OP Find the DC Operating Point Perform a circuited and inductances short circuited DC operating point solution with capacitances open DC Usually a solution is performed as part of another analysis in order to find the operating point of only this operating point to in a dialog box Aftera node or current the OP sol OD simulation ution wi the circuit be found Use op if you wish The results will appear when you point ata appear on the status bar 1 There is no guarant
75. ax Rp Resistance per unit length Q er 1 Cp Capacitance per unit length F er 1 Is Saturation Current per unit A pe length wel Rs Diode Resistance per unit length Q pe rl 162 V Voltage Source Symbol Names VOLTAGE BATTERY Syntax Vxxx n n lt voltage gt AC lt amplitude gt Rser lt value gt Cpar lt value gt This element sources a constant voltage between nodes n and n For AC analysis the value of AC is used as the amplitude of the source at the analysis frequency A series resistance and parallel capacitance can be defined The equivalent circuit is lt Voltage gt Voltage sources have historically been used as the current meters in SPICE and are used as current sensors for current controlled elements If Rser is specified the voltage source can not be used as a sense element for F H or Welements However the current of any circuit element including the voltage source can be plotted 163 Syntax Vxxx n n PULSE V1 V2 Tdelay Trise Tfall Ton Tperiod Neycles Time dependent pulsed voltage source Nam Description Un e it s Vof Initial value V SR Von Pulsed value V Tde Delay se lay g EE Rise time se C RE Fall time se E Ton On time se e Tpe Period se rio Cc d Ncy Number of cycles Omit cy cle for free running pulse coal s function es Syntax Vxxx n n SINE Voffset Vamp Freq Td Theta Phi Ncycles Time dependent
76. ber between 0 and 1 depending on the integer value of xX random x Similar to rand but smoothly transitions between values round x Nearest integer to x sgn x Sign of x Sin x Sine of x sinh x Hyperbolic sine of x sqrt x Square root of x table x a b c d Interpolate a value for x based 5 on a look up table given as a set of pairs of points tan x Tangent of x tanh x Hyperbolic tangent of x u x Unit step i e 1if x gt 0 else 0 uramp x x if x gt 0 else O white x Random number between 5 and 5 For complex buf inv min limi available smoothly transitions between values even more smoothly than random data the functions atan2 sgn u uramp int floor ceil rand t if and table are not The functions Re x and Im x are available for complex data and return a complex number with the real part equal to the real or imaginary part of the argument respectively functions Ph and the imaginary part equal to zero The x and Mag x are also available for complex data and return a complex number with the real part equal 43 to the phase angle or magnitude of the argument respectively and the imaginary part equal to zero The function conj x is also available for complex data and returns the complex conjugate of x The following operations grouped in reverse order of precedence of evaluation are available
77. bled in a new schematic window when objects were already selected with the Duplicate command Drag Click on or drag a box around the objects you wish to drag Then you can move those objects to a new location and the attached the wires are rubber band with the new location Draw gt Line Draw a line on the schematic Such lines have no electrical impact on the circuit but can be useful for annotating the circuit with notes Draw gt Rectangle Draw a rectangle on the schematic This rectangle has no electrical impact on the circuit but can be useful for annotating the circuit with notes Draw gt Circle Draw a circle on the schematic This circle has no electrical impact on the circuit but can be useful for annotating the circuit with notes Draw gt Arc Draw an arc on the schematic This arc has no electrical impact on the circuit but can be useful for annotating the circuit with notes NOTE The graphical annotations to the schematic lines rectangles circles and arcs snap by default to the same grid as the used for electrical contacts of wires and pins Hold down the control key while positioning these to defeat this snap Label a node name Each node in the circuit requires a unique name You can specify the name of a node so an arbitrary one isn t generated by the 17 netlister Node 0 is the circuit global ground and is drawn with
78. but simply not part The reason that these gates are implemented of the simulation like that is that is the AND device propagation delay Name Vhigh Vlow Trise this allows one device to act as 2 3 4 or 5 input gates with true inverted or complementary outpu with no simulation speed penalty for unused terminals That Gt et acts as 12 different types of AND gates The gates default to OV 1V logic with a and a 10hm output impedance Output characteristics are set with these instance parameters logic threshold of 5V no Def Description aul t 1 Logic high level 0 Logic low level 0 Rise time 99 Tfall Tra Fall time se Tau O Output RC time constant Cout 0 Output capacitance Rout 1 Output impedance Rhigh Rou Logic high level impedance Rlow Rou Logic low level impedance Note that not all parameters can be specified on the same instance at the same time e g the output characteristics are either a slewing rise time or an RC time constant not both The propagation delay defaults to zero and is set with instance parameter Td Input holdtime is equal to the propagation delay The input logic threshold defaults to 5 Vhigh Vlow but can be set with the instance parameter Ref The hold time is equal to the propagation delay The exclusive XOR device has non standard behavior when more than two inpu
79. c Rs temp Le coeff SCH ZE is being used beyond its rated capabilit following parameters apply to either model do not scale Na me Vp with area Description Peak voltage rating Peak current rating Ave current rating RMS current rating Maximum power dissipation rating E Voltage Dependent Voltage Source Symbol Names z Ra E2 le to specify voltage current and power These model parameters do not lectrical behavior They allow LTspice to check ty The These parameters 113 There are thr types of voltage dependent voltage source circuit elements Syntax Exxx n n net no lt gain gt This circuit element asserts an output voltage between the nodes n and n that depends on the input voltage between nodes nc and nc This is a linearly dependent source specified solely by a constant gain Syntax Exxx n n nc nc table lt value pair gt lt value pair gt A look up table is used to specify the transfer function The table is a list of pairs of numbers The second value of the pair is the output voltage when the control voltage is equal to the first value of that pair The output is linearly interpolated when the control voltage is between specified points If the control voltage is beyond the range of the look up table the output voltage is extrapolated as a constant voltage of the last point of the look up table
80. capacitances by the non linear thin oxide capacitance which is distributed among the gate source drain and bulk regions and by the nonlinear depletion layer capacitances for both substrate junctions divided into bottom and periphery which vary as the MJ and MJSW power of junction voltage respectively and are determined by the parameters CBD CBS CJ CJSW MJ MJSW and PB Charge storage effects are modeled by the piecewise linear voltages dependent capacitance model proposed by Meyer The thin oxide charge storage effects are 135 treated slightly different for the Level 1 model These voltage dependent capacitances are included only if Tox is specified There is some overlap among the parameters describing the S e g the reverse current can junction either through Ts Amp the first is an absolute value the secon current of the drain and by Ad and As to giv th revers source junctions respectively to the zero bias junction capacitances CB on one hand and CJ Farad m m on the other The parasitic drain an either R d sourc being mul on the d MOSFET 1 vice lin evel 1 2 Nam Vto Kp Gam ma Phi Lam bda Rd Rs Cbd 136 D and RS Ohms The same i be specified or through Js Amp m m Whereas d is multiplied dea applies also and 3 parameters Description Zero bias threshold voltage
81. ceseeecsseceeeeeseceeesecnereeaeeees 73 MEASURE Evaluate User Defined Electrical Quantities cccccccccsssecssceeseeceseeeeseeceseeeeneees 73 MODED r a E Aa AIA EEE A anni don eg inna ere 78 NET Compute Network Parameters in a AC Analysis seseseeesesesseeeieseessesesreerererrsesierrereeese 78 NODESET supply hints for initial DC solution seeseseseseeeeseeeeesssesisrerrersssesrsrerrersrsesrerrerereeee 79 NOISE Perform a noise analysis csseesscssseecssecseeecsecsecseecessecseesecsessecsaeeeeaecaseeeeaecaeeeeenees 80 OP Find the DC operating pont 81 OPTIONS Set simulator Options 0 ceeeescsseeeseceeeceeeeceseeecsaecseesecsesseesesneseesaeeeeeaecaeeseenees 81 PARAM User defined Darameterg 85 SAVE Limit the amount of saved data 90 SAVEBIAS Save operating point to disk cc eeceeecsseseceseceeeecerseceaeeecsaeceeesecaecaeeeeeneseeseaeeees 90 STEP Parameter s weeps eer eer 91 SUBCKT define a subeirc it sinense evnini tir des aeie a ti E A 92 TEMP 2 Temperature sweeps ocon tei Ae ERE A eevee epee E AER ETN 93 TF Find the DC small signal transfer function sssseesesesseeseereeeesereseserrterseserreerereesesrereereeeeee 94 TRAN Do a non linear transient apnalvais 94 TRAN Molereien ENEE AE E EEEE EEE EE 96 WAVE Write selected nodes to a way Die 95 A A General Structure and Convention 59 Ar Special funch Ons eer eene Ee AE Ee Aes 98 Adding Attributes aeie e i aa E E
82. chnology LTspice SwitcherCAD III tube cir E File Edit View Simulate Tools Window Help Ags EFPIA O FOOR Sit Bae teem ae x triode asc un VIAGOGO Q Pnl U2 GO 0 X1 A G O SU3CX300 de U1 500 1 U2 50 10 10 subckt SU3CX300 A G K Emu mu VALUE PWRS U G K 0 98 Eshape shape UALUE 280 U G K 280 Egs gs VALUE LIMIT U A K U G K 7 5 0 1E6 Egs2 gs2 0 VALUE PWRS U gs xU shape 1 5 135E 6 Ecath cc 0 VALUE U gs2 Ga A K UVALUE U cc Cok G K 25p Cga A G 10p Cak A K 1p ends Efficiency Report It is possible to obtain an efficiency report from a DC DC converter from a time domain tran analysis that contains the keyword steady After a steady state simulation an efficiency report can be made visible on the schematic as a block of comment text 11 Efficiency Report Efficiency 77 6 Input 16 5W 9 97 Output 12 9W 5 12 Irms Ipeak Dissipation 339mA 495mA Bmw 105mA 190mA Ami OmA OmA Dm 1460mA 2686 mA 418mw 2504mA 2691mA Em Im m Sm 4imA IMA 2mWw OmA OMA Op 2040mA 2994mA 3266 mW The efficiency of the DC DC converter is derived in the following manner In order to identify the input and output there must be exactly one voltage source and one current source The voltage source is assumed to be the input while the current source is assumed to be the output The circuit is run until steady state is sensed by the simulator This requires
83. ct precisely LTspice must guess an appropriate frequency ommended that the LTspice first The length of the window log gorithm s choices by explicitly The reciprocal of the value resolution The value of nfft the highest frequency considered Note t the convolution of the impulse response with the behavioral lly a compute bound process ic lt value gt Rpar lt value gt It is possible to specify an equivalent series resistance lel resistance and parall lel shut Low ircuit is given bel 107 108 lt Capacitance gt RLshunt Capacitor Instance Parameters Nam Rse Lse Rpa Cpa RLs hun tem iC Description Equivalent series resistance Equivalent series inductance Equivalent parallel resistance Equivalent parallel capacitance Shunt resistance across Lser Number of parallel units Instance temperature for tempcos ina corresponding model statement Initial voltage used only if uic is flagged on the tran card It is computationally better to include the parasitic Rpar Rser RLshunt Cpar and Lser in the capacitor than to explicitly draft them LTspice uses proprietary circuit simulation technology to simulate this model of a physical capacitor without any internal nodes This makes the simulation matrix smaller faster to solve and less likely to be singular at short time steps Note that sinc
84. d H are available Also with regard to complex data the Boolean XOR operator is understood to mean exponentiation The following constants are internally defined Na Value me E 2 7182818284590452354 Pi 3 14159265358979323846 K 1 3806503e 23 Q 1 602176462e 19 The keyword time is understood when plotting transient analysis waveform data Similarly freq and omega are understood when plotting data from an AC analysis w can be used as a synonym for omega 45 2 Compute the average or RMS of a trace The waveform viewer can integrate a trace to obtain the average and RMS value over the displayed region First zoom the waveform to the region of interest then move the mouse to the label of the trace hold down the control key and left mouse click Rit year Technology LTspice SwitcherCAD III LT1074 app Bisi oi File View Tools window Help sl Deum FU QQQRQ Sid SS Air Waveform I D1 x Interval Start Qs Interval End 98 260748 Average 849 69mA RMS 1 45834 BUT 40uUs 60us 80us Right Click to edit expression Control Left Click to integrate 3 Display the Fourier Transform of a Trace You can use the menu command View gt FFT to perform a Fast Fourier transform on various data traces 46 Select Waveforms to include in FFT n003 ICH I B u1 2 K C u1 11 I C2 I B u1 4 W C u1 12 I C3 I B u1 5 I C u1 13 01 IE C Y u1 n005 load
85. deling with SPICE by Giuseppe Massobrio and Paolo Antognetti McGraw Hill 1993 and later reprints That book documents the semiconductor device equations and extensions that have been used in various commercial SPICE programs including those used inthis one For BSIM 3 and 4 devices s the relevant documentation available from the UC Berkeley CAD group LTspice is a registered trademark of Linear Technology Corporation Introduction Circuit Description Circuits are defined by a text netlist The netlist consists of a list of circuit elements and their nodes model definitions and other SPICE commands The netlist is usually graphically entered To start a new schematic select the File gt Open menu item A windows file browser will appear Either select an existing schematic and 58 save it under a new name or type in a new name to create a new blank schematic file LTspice uses many different types of files and documents You will want to make a file with a file name extension of asc The schematic capture commands are under the Edit menu Keyboard shortcuts for the commands are listed under Schematic Editor Overview When you simulate a schematic the netlist information is extracted from the schematic graphical information to a file with the same name as the schematic but with a file extension of net LTspice reads in this netlist You can also open simulate and edit a text netlist generat
86. e IV Overview LTspice IV is a schematic driven circuit simulation program The LTspice simulator was originally based years ago on Berkeley SPICE 3F4 5 The simulator has gone through a complete re writ in order to improve the performance of the simulator fix bugs and extend the simulator so that it can run industry standard semiconductor and behavioral models A digital simulation capability including co simulation has been added Extensive enhancements have been made to the analog SPICE simulator such as parallel processing and dynamic assembly and object code 57 generation in the SPARSE matrix solver to make LTspice IV the industry superlative analog simulator Many Linear Technology products are modeled with proprietary building blocks and or proprietary hardware description languages that accurately encapsulate realistic behavior with custom macromodels This allows a SMPS to be prototyped rapidly via simulation LTspice can be used as a general purpose SPICE simulator New circuits can be drafted with the built in schematic capture Simulation commands and parameters are placed as text on the schematic using established SPICE syntax Waveforms of circuit nodes and device currents can be plotted by clicking the mouse on the nodes in the schematic during or after simulation An invaluable reference that complements this documentation is the 2nd Edition of Semiconductor Device Mo
87. e DEE ies EEEE EEE ie Bava ote il 28 Addie the E 27 Attached OTE O N EA ES EE E enee GEES eer Eege 50 51 54 Attribute Visibili EE 30 Automatic Symbol Generation sareren eran a a ee eege ee een G rii 31 AXIS Contohe r Eeer a E E A eA E E S AAE EE neces 48 B B Arbitrary behavioral voltage or current Sources eseseeesesseesreeeereeeestserrteretersesrerrerereersrseee 101 B e de le 58 C C Simulator directives dot commande 63 C Capacitor soiree a e e e A e E EEEE AE EE ee EE 107 Color e EE 49 203 Command shine S WitChes 7 hees ee eege deele ele 13 COMPLESSION Ee eier be ee ee ees 171 172 Creating Symbol Overview cccccesccesccesecesecsceeseeeseesneeeeesecesecesecesecaecsaecsaecaeecaeeeaeeeneeeseeerenenenaees 26 D LEE 110 Drawitie the DODY eessen eege E 27 E E Voltage Dependent Voltage Source 113 Edita visible attribute nicsen eer neriie i KEE EENEG 22 Efficiency Report erener rrira RE EEE RR E RE E R E EEE EE R EE 11 Example Circuits dude ECKE E E RE E E edd 8 Exporting Waveform Data ege iis e ern E aA EEEE EE S ESEE EEE ER e TER 196 Externally Generated Netlist ciccsccsceccccvsesccvsescse cuvea sce ai Eii E EE EEE KE aa 10 F F Current Dependent Current Some 115 Fast ACc ss File Formats ie ccic aiscitiviuticiettiet ois hedsts navies tciadetades eege EE e 55 G G Voltage Dependent Current Source 116 General Attribute Editors s erener ireen oeei E See e Ep NaN Cd ESSEER EEE d i ec 24 General Pu
88. e resistance Transport saturation current Forward emission coefficient Reverse emission coefficient Fwd bias depletion capacitance limit Extrinsic B E overlap capacitance Zero b ias B E depletion capacitance B E built in potential B E junct tion grading coefficient B E capacitance smoothing Cc Oo Les Infin Infin 275 333 ch CO Ge cj ep pc mc cj cp ms ib ei wb ne ib en ne ib factor Extrinsic B C overlap capacitance Zero bias B C depletion capacitance Epi charge parameter B C extrinsic zero bias capacitance B C built in potential B C junction grading coefficient B C capacitance smoothing factor Zero bias S C capacitance S C junction built in potential S C junction grading coefficient S C capacitance smoothing factor Ideal B E saturation current Portion of IBEI from Vbei 1 WBE from Vbex Ideal B E emission coefficient Non ideal B E saturation current Non ideal B E emission coefficient Ideal B C saturation current ECH Le le 18 le 16 153 nc ib cn nc cl av c2 is WS nf ib ei ib en ib Ga nc ip ib cn nc np ve ve 154 coefficient Non ideal B C saturation current Non ideal B coefficient B C weak ava par
89. e root of x e g sqrt 1 returns 0 not O 70710714 Interpolate a value for x based on a look up table given as a set of pairs of points Tangent of x Hyperbolic tangent of x Unit step i e lif x gt 0 else OD x if x gt 0 else O The following operations are grouped in reverse order of precedence of evaluation 88 Ope Description ran d amp Convert the expressions to either side to Boolean then AND Convert the expressions to either side to Boolean then OR Convert the expressions to either side to Boolean then XOR gt True if expression on the left is greater than the expression on the right otherwise false lt True if expression on the left is less than the expression on the right otherwise false gt True if expression on the left is less than or equal the expression on the right otherwise false lt True if expression on the left is greater than or equal the expression on the right otherwise false Floating point addition Floating point subtraction Floating point multiplication Floating point division be Raise left hand side to power of right hand side only real part is returned e g 2 1 5 returns zero not 2 828431 89 SAVE Limit the Quantity of Saved Data Some simulations particularly time domain simulations can generate large amount of dat
90. e such a situation two transmission line elements are required U Uniform RC line Symbol Names URC Syntax Uxxx N1 N2 Ncom lt model gt L lt len gt N lt lumps gt N1 and N2 are the two element nodes the RC line connects whereas Ncom is the node to which the capacitances are connected MNAME is the model name and LEN is the length of the RC line in meters 161 Lumps if specified is the number of lumped segments to use in modeling the RC line A guess at an appropriate number of lumps to use will be made if lumps is not specified The URC model is derived from a model proposed by L Gertzberrg in 1974 The model is accomplished by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes The RC segments are ina geometric progression increasing toward the middle of the URC line with K as a proportionality constant The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a nonzero value in which case the capacitors are replaced with reverse biased diodes with a zero bias junction capacitance equivalent to the capacitance replaced and with a saturation current of ISPERL amps per meter of transmission line and an optional series resistance equivalent to RSPERL ohms per meter Na Description Un Defa me it s K Propagation Constant Fm Maximum Frequency of interest Hz
91. e technology used to implement this library Permission is granted to use this file for simulations but not to revers ngineer its contents Begin 50 3E 46 OF FA 6E 67 FF B8 4D D9 62 14 32 60 24 36 71 35 0B 66 4F AD 52 B8 F5 9E 22 9F CO 18 8B PB FER LD ess 72 you can change this to be LTspice Encrypted File This encrypted file has been supplied by a 3rd party vendor that does not wish to publicize the technology used to implement this library Permission is granted to use this file for simulations but not to revers ngineer its contents Copyright 2005 Acme SPICE Modeling For additional information see www acmespicemodels com Begin 50 3E 46 OF FA 6E 67 FF B8 4D D9 62 14 32 60 24 36 71 35 OB 66 4F AD 52 B8 F5 9E 22 9F CO 18 8B FB FE 1D LOADBIAS Load a Previously Solved DC Solution Syntax loadbias lt filename gt The loadbias command is the compliment to the savebias command First run a simulation that executes a savebias command Then change the savebias command to a loadbias command MEASURE Evaluate User Defined Electrical Quantities There are two basic different types of MEASURE statements Those that refer to a point along the abscissa the independent variable plotted along the horizontal axis i e the time axis of a tran analysis and MEASURE statements that
92. e the capacitor element includes these parasitics it is useful for macromodeling the fundamental of a piezoelectric crystal There is also a general nonlinear capacitor available Instead of specifying the capacitance one writes an expression for the charge LTspice will compile this expression and symbolically differentiate it with respect to all the variables finding the partial derivative s that correspond to capacitances Syntax Cnnn nl n2 Q lt expression gt ic lt value gt m lt value gt There is a special variable x that means the voltage across the device Therefore a 100pF constant capacitance can be written as Cnnn nl n2 Q 100p x A capacitance with an abrupt change from 100p to 300p at zero volts can be written as Cnnn nl n2 Q x if x lt 0 100p 300p This device is useful for rapidly evaluating the behavior of a new a hypothetical charge model for e g a transistor 109 D Diode Symbol Names DIODE ZENER SCHOTTKY VARACTOR Syntax Dnnn anode cathode lt model gt area off m lt val gt n lt val gt temp lt value gt Examples D1 SW OUT MyIdealDiode model MyIdealDiode D Ron 1 Roff 1Meg Vfwd 4 model dio2 Ins ins D2 SW OUT dio2 D Is le 10 tance parameter M sets the number of parallel devices while tance parameter N sets the number of series dev
93. e voltages e g V n001 o Node voltage differences e g V n001 n002 o Circuit element currents for example I S1 the current through switch S1 or Ib Q1 the base current of Ql However it is assumed that the circuit element current is varying quasi statically that is there is no instantaneous feedback between the current through the referenced devic and the behavioral source output Similarly any ac component of such a device current is assumed to be zero in a small signal linear AC analysis o The keyword time meaning the current time in the Simulation o The keyword pi meaning 3 14159265358979323846 o The following functions Function Name Description abs x Absolute value of x 102 absdelay x t tmax acos xX arccos x acosh x asin x arcsin x asinh x atan x arctan x atan2 y x atanh x buf x ceil x cos x cosh x ddt x delay x t tmax exp x floor x hypot x y idt x ic a idtmod x ic m o x delayed by t Optional max delay notification tmax Real part of the arc cosine of x e g acos 5 returns 3 14159 not 3 14159 2 292433 Synonym for acos Real part of the arc hyperbolic cosine of x e g acosh 5 returns 0 not 1 04721 Real part of the arc sine of x asin 5 is 1 57080 not 1 570804 2 292431 Synonym for asin Arc hyperbolic sine Arc tangent of x Synonym for at
94. ease wine Force use of WINE Linux workarounds Schematic Capture Basic Schematic Editing The schematic capture program is used to create new schematics or modify the example circuits provided The circuit size and depth of hierarchy is limited only by computer resources The program ships with approximately 800 symbols These symbols cover most of LTC s power ICs opamps comparators and many general purpose devices for circuit design You can also draw your own symbols for devices you wish to import into the program 14 Fe Linear Technology LTspice SwitcherCAD III LTC3729 asc L File Edit Hierarchy View Simulate Tools Window Help ee Undo Redo ap SPICE Directive SPICE Analysis lt Resistor Capacitor 2 Inductor SC Diode D Component me Rotate Ea Mino _ Draw Wire Label Net xb Place GND A Delete Ba Duplicate amp Move F Paste lt gt Drag N Line Rectangle Circle Are Unlike many schematic capture programs this one was written explicitly for running SPICE simulations This means that if you click on an object the default behavior is to plot the voltage on that wire or current through that component not select the object for editing or some other editing behavior which would then invalidate the simulation just performed Hence when you wish to move mirror rotate drag or delete objects first select the move drag or delete command Then
95. ed either by hand or externally generated Files with the extensions net cir or sp are recognized by LTspice as netlists This section of the help documents the syntax used in netlists but occasionally gives schematic level advice General Structure and Conventions The circuit to be analyzed is described by a text file called a netlist The first line in the netlist is ignored that is it is assumed to be a comment The last line of the netlist is usually simply the line END but this can be omitted Any lines after the line END are ignored The order of the lines between the comment and end is irrelevant Lines can be comments circuit element declarations or simulation directives Let s start with an example This first line is ignored The circuit below represents an RC circuit driven with a 1MHz square wave signal R1 nl n2 1K a 1KOhm resistor between nodes nl and n2 C1 n2 0100p a 100pF capacitor between nodes n2 and ground Vl nil 0 PULSE O 100 O 5p 1p a 1Mhz square wave stran 3u do a us long transient analysis end 59 The first two lines are comments Any line starting with a is a comment and is ignore d The line starting with R1 declares that there is a 1K resistor connected between nodes nl and n2 Note that the s emicolon can be used to start a comment in the middle of a line The line starting w
96. edly performed while stepping the temperature a model parameter a global parameter or an independent source Steps may be linear logarithmic or specified as a list of values Example step oct v1 1 20 5 Step independent voltage source V1 from 1 to 20 logarithmically with 5 points per octave 91 Example step Il 10u 100u 10u Step independent current source Il from 10u to 100u in step increments of 10u Example step param RLOAD LIST 5 10 15 Perform the simulation three times with global parameter Rload being 5 10 and 15 Example step NPN 2N2222 VAF 50 100 25 Step NPN model parameter VAF from 50 to 100 in steps of 25 Example step temp 55 125 10 Step the temperature from 55 C to 125 C in 10 degr step Step sweeps may be nested up to thr levels deep SUBCKT Define a Subcircuit As an aid to defining a circuit repetitive circuitry can be enclosed in a subcircuit definition and used as multiple instances inthe same circuit Before the simulation runs the circuit is expanded to a flat netlist by replacing each invocation of a subcircuit with the circuit elements in the subcircuit definition There is no limit on the size or complexity of subcircuits The end of a subcircuit definition must be a ends directive Here is an example using a subcircuit 92 This is the circuit definition a b O divider a 0 pulse O 10 5p 5u 0 1p lt S K x t
97. ee that nonlinear circuit can be fo approximations as is done in direct Newton iteration fail the operating point of a general und with successive linear Newton Raphson iteration Should LTspice tries a number of other me me particular method Method Iteration Direct Newton Adaptive Gmin Stepping Adaptive Source Stepping Pseudo Transient OPTIONS Set Simulator Opt thods to find an operating point thods used and the options settings required to disable a Below is a table of the Directive to disable options NoOpiIter options GminSteps 0 options SrcSteps 0 options pTranTau 0 ions Keyword Data Default Description Type Value abstol Num 1pA Absolute current error tolerance baudrate Num none Used for eye diagrams Tells 81 chgtol cshunt cshuntintern defad defas defl defw delay fastaccess flagloads Gmin gminsteps 82 Num Num Num Num Num 10fC cshunt O Oo 100um 100um false false le 12 25 100 50 10 25 the waveform viewer how to wrap the abscissa time to overlay the bit transitions Absolute charge toleranc Optional capacitance added from every node to ground Optional capacitance added from every device internal node to ground Default MOS drain
98. eform data files of essentially unlimited file size LTspice can address data files containing many Gigabytes of data and page in up to four Gigabytes at a time for plotting in the waveform viewer However most editions Microsoft Windows allow a maximum of 2GB of address space for application software despite the fact that 32 bits can address 4GB uniquely If as is common you have 4GB of physical RAM you can configure Windows to override this default Under Windows XP and variations you can edit the boot ini file to add the 3GB option to the operating system line From http www microsoft com whdc system platform server P AE PAEmem mspx Typical boot ini file boot loader timeout 30 default multi 0 disk 0 rdisk 0 partition 2 WINNT operating systems 56 multi 0 disk 0 rdisk 0 partition 2 WINNT 2 3GB Where would be the programmatic name for one of the following Windows XP Professional Windows Server 2003 Windows Server 2003 Enterprise Edition Windows Server 2003 Datacenter Edition Windows 2000 Advanced Server Windows 2000 Datacenter Server Windows NT Server 4 0 Enterprise Edition Microsoft Vista is different and you should use the utility bcededit exe d r C Windows System32 gt bcdedit exe set IncreaseUserVa 3072 The change doesn t take place until the system reboots LTspice LTspic
99. el and Poon This modified Gummel Poon model extends the original model to include sev ral effects at high bias levels quasi saturation and substrate conductivity The model automaticall y simplifies to the Ebers Moll model when certain parameters are not specified The DC model is defined by the parameters Is Bf Nf Ise Ikf and Ne which determine the forward current gain characteristics Is Br NY SC kr and Nc which determine the revers current gain characteristics and Vaf and Var which determine the output conductance for forward and reverse regions Three ohmic resistances Rb Rc and Re are included where Rb can be high current dependent Base charge storage is modeled by forward and reverse transit times Tf and Tr the forward transit time Tf being bias dependent if desired and nonlinear depletion layer capacitances which are determined by Cie Vje and Mie for the B E j and Cjs Vis and Mis for the Collector Substrate unction Cjc Vjc and MJG for the B C junction junction The temperature dependence of the saturation current Is is determined by the energy gap Eg and the saturation current temperature exponent XTI Additionally base current temperature dependence is modeled by the beta temperature exponent XTB in the new model The measured at on the
100. equency Un it MDI Modulation index Fsi Signal frequency Hz The voltage is given by Voff Vamp sin 2 pi Fcar time MDI sin 2 pi Fsig tim bc Syntax Vxxx n n PWL t1 vl t2 v2 t3 v3 Arbitrary Piece wise linear voltage source For times before t1 the voltage is v1 For times between t1 and t2 the voltage varies linearly between v1 and v2 There can be any number of time voltage points given For times after the last time the voltage is the last voltage Syntax Vxxx n n wavefile lt filename gt chan lt nnn gt This allows a wav file to be used as an input to LTspice lt filename gt is either a full absolute path for the wav file or a relative path computed from the directory containing the simulation schematic or netlist Double quotes may be used to specify a path containing spaces The wav file may contain up to 65536 channels numbered 0 to 65535 Chan may be set to specify which channel is used By default the first channel number 0 is used The wav file is interpreted as having a full scale range from 1V to 1V This source only has meaning in a tran analysis W Current Controlled Switch Symbol Names CSW 167 Syntax Wxxx nl n2 Vnam lt model gt on off Example W1 out 0 Vsense MySwitch Vsense ab 0 model MySwitch CSW Ron 1 Roff 1Meg It 0 Ih 5 The current through the named voltage source co
101. er MOSFETS if the gate source voltage is not driven negative The gate drain capacitance follows the following empirically found form 140 Cgdmax C atan a Ved D A tanh a Ved B ee anes Cgdmin Vod For positive Vgd Cgd varies as the hyperbolic tangent of Vgd For negative Vdg Cgd varies as the arc tangent of Vgd The model parameters a Cgdmax and Cgdmax parameterize the gate drain capacitance The source drain capacitance is supplied by the graded capacitance of a body diode connected across the source drain electrodes outside of the source and drain resistances Name Description U Def Exa n aul mpl i t e t s Vto Threshold voltage V 0 1 0 Kp Transconductance A 1 5 parameter V 2 Phi Surface inversion V 0 6 0 6 potential 5 Lamb Channel length L 0 0 0 da modulation is 2 V Rd Drain ohmic Q 0 resistance Rs Source ohmic Q 0 141 Rg Rds Rb CG Cgs Cgdm in Cgdm ax Vj Fc tt Eg 142 resist Gate ohm resist can can resist can ce alge ce Drain source shunt ce Body diode ohmic resist can ce Zero bias body diode junction Capacitance Gate source Capacitance Minimum non linear G D capacitance Maximum non linear G D capacitance Non linear Cgd Capacitance parameter Body diode saturation current Bulk diode emission coefficient Body diode junction potential Bod
102. erformance SPICE simulator extended with a mixed mode simulation capability that includes new intrinsic SPICE devices for macromodeling Switch Mode Power Supply SMPS controllers and regulators The program includes an integrated hierarchical schematic capture program that allows users to edit example SMPS circuits or design new circuits An integrated waveform viewer displays the simulated waveforms and allows further analysis of the simulation data There is a built in database for most of Linear Technology s power ICs and many pasSive components The device database schematic editing simulation control and waveform analysis are integrated into one program Due to the mixed mode simulation capability and many other enhancements over previous SPICE programs the simulation speed is greatly improved while simulation accuracy is retained Detailed cycle by cycle SMPS simulations can be performed and analyzed in minutes A user can get a detailed simulation of power systems with a few mouse clicks without knowing anything about the device SPICE or the schematic capture program Pre drafted demo circuits can be used as a starting point to build the custom circuit to fit different power supply requirements After the new schematic is created the system can be simulated and reports generated The program s integrated hierarchical schematic capture and SPICE simulator are avail
103. es across state changes Its breakdown Its rolled oscillator See at 1V and space is The voltage on the AM input and defaults to 1V if that input is unused connected to the MO The schema these devices in a special manner are automat DULATE common tic capture aspect of LTspice netlists symbols for All unconnected terminals 8 is unconnected then it is connected to node 0 B Arbitrary behavioral voltage or current sources Symbol names BV BI Syntax Bnnn n001 n002 V lt expression tripdv lt value gt tripdt lt laplace lt expression gt win nfft lt number gt mtol lt num Bnnn n001 n002 I lt expression tripdv lt value gt tripdt lt laplace lt expression gt win nfft lt number gt mtol lt num gt ic lt value gt value gt dow lt time gt ber gt gt ic lt value gt tically connected to terminal 8 Also if terminal value gt Rpar lt value gt dow lt time gt ber gt 101 The first syntax specifies a behavioral voltage source and the next is a behavioral current source For the current source a parallel resistance may be specified with the Rpar instance parameter Tripdv and tripdt control step rejection If the voltage across a source changes by more than tripdv volts in tripdt seconds that simulation time step is rejected Expressions can contain the following o Nod
104. es of the hysteresis major loop are given by H He Bup H Bs D I H H He He Bs Br 1 129 and H He Bdn H Bs H H H He He Bs Br 1 These functions are plotted in following figure Hc and Br are the intersections of the major hysteresis loop with the H and B axes Bs is the B axis intersection of the asymptotic line Bsat H Bs 0 H approached as H goes to infinity The initial magnetization curve is given by Bmag H D Bup H Bdn H Minor loops are obtained by various translations of the above equations per the cited reference The core s absolute and differential permeabilities are a function of H and the history of values of H The plot below shows the path taken by an asymmetrical minor loop for a typical power ferrite Hc 16 A turns m Bs 44T Br 10T 130 asymmetric minor loop major Loop WC initial magnetization In addition to the core property parameters Hc Br and Bs mechanical dimensions of the core are required Na Description Units me Lm Magnetic Length excl meter gap Lg Length of gap meter A Cross sectional area meter x2 N Number of turns Note that if specifying a non zero gap the magnetic field H is not proportional to the current in the windings LTspice solves for the magnetic fields in the core and gap under the assumption of uniform cross
105. et tings gt Add Trace The undo and redo commands allow you to review the different trace selections plotted no matter which method of selection is used Ty Th Probing directly from the schematic asiest method is to simply probe the schematic You simply point and click at a wire to plot the voltage on any that wire You plot the current through any component with two connections like a resistor capacitor or an inductor by clicking on the body of the component This works at level of the circuit s hierarchy You can also plot current into a particular connection of a component with more than two pins by clicking on that pin of the symbol If you click the same voltage or current twice then all other traces will be erased and the double clicked trace will be plotted by itself traces by clicking on the trace s The following to point at a pin current Notice turns into an icon that looks like a clamp on ammeter when the delete command You can delete individual label after selecting screen shot shows how that the mouse cursor it s pointing at a current that can be plotted 35 Fe Linear Technology LTspice SwitcherCAD III LT1371 Eifel Ey File Edit View Simulate Tools Window Help As EP 40 QQQR KC See sae 1 238V 1 221 V Ous 4us Sus 12us 16us Left button click to plot I U1 SW When plotting a pin current the convention of p
106. f x tanh x Hyperbolic tangent of x u x Unit step i e 1if x gt 0 else 0 uramp x x if x gt 0 else 0 white x Random number between 5 and 5 smoothly transitions between values even more smoothly than random x Alternative syntax for inv x x Alternative syntax for inv x The following operations grouped in reverse order of precedence of evaluation Ope Description ran d amp Convert the expressions to either side to Boolean then AND Convert the expressions to either side to Boolean then OR Convert the expressions to either side to Boolean then XOR gt True if expression on the left is greater than the expression on the right otherwise false lt True if expression on the left is less than the expression on the right otherwise false gt True if expression on the left is less than or equal the expression on the right otherwise false lt True if expression on the left is greater than or equal the expression on the right otherwise false 105 Floating point addition Floating point subtraction S Floating point multiplication Floating point division raed Raise left hand side to power of right hand side Only the real part is returned e g 1 1 5 gives zero not i Convert the following expression to Boo
107. first opened that plot settings file is read for initial plot configuration Each analysis type tran ac noise etc has its own entry inthe plot settings file It isn t possible to load the settings from one analysis type to another But you can use the plot settings file from another simulation of the same analysis type 54 Fast Access File Format During simulation LTspice usually uses a compressed binary file format that allows additional simulation data to be appended without modifying the rest of the file But once the simulation is completed this file format can be slow to access for the purposes of adding a single new plot trace fromthe file To reduce this time you can convert the file to an alternative Fast Access format This format can only be done after th simulation is completed when no new data will be added to the file But once the file is converted to this format the load time of a new traces will be reduced typically by a factor equal to the number of data traces that have been saved in the file For example if you have a 5GB file with 2000 data traces i might take 4min to add a new trace But after you convert it to Fast Access format this four minute load time would be reduced to a single second This makes cross probing large circuits with huge simulation data files interactive The exact time it takes to load a trace from a Fast Access format file
108. he settings in a file and inc that file Also interesting is which solver is used LTspice contains two complete versions of SPICE One is called the normal solver and the other is called the alternate solver The alternat solver uses a different sparse matrix package with reduced roundoff error Typically the alternate solver will simulate at half the speed of the normal solver but with one thousand times more internal accuracy This can be a useful diagnostic to have available There is no option to specify which solver is used the choice must be made before the netlist is parsed because the two solvers use different parsers Check the box next to Accept 3K4 as 3 4K to force LTspice to understand a number written as 4K99 to be equal to 4 99K Normal SPICE practice does not allow this but it is available in LTspice by popular request Netlist Options Convert uf to u Replace all instances of p to u Useful if your MS Windows installation can t display a Greek Mu as e g some Chinese editions of Windows don t with default fonts and ii generating netlists for SPICE simulators that don t understand the ui character as the metric multiplier of le 6 Reverse comp order Circuit elements are normally netlisted in the order in which they were added to the schematic Checking this box causes this order to be reversed Default Devices
109. hed startup Solve the initial operating point with independent voltage and current sources turned off Then start the transient analysis and turn these sources on in the first 20 us of the simulation step Compute the step response of the circuit UIC Use Initial Conditions Normally a DC operating point analysis is performed before starting the transient analysis This directive suppresses this initialization The initial conditions of some circuit elements can be can be specified on an instance per instance basis Uic is not a particularly recommended feature of SPICE Skipping the DC operating point analysis leads to a nonphysical initial condition For example consider a voltage source connected in parallel to a capacitance The node voltage is taken as zero if not specified Then inthe first time step an infinite current is required to charge the capacitor The simulator cannot find a short enough time step to make the current nonsingular anda time step too small convergence fail message is issued startup This is similar to SPICE s original uic It means that independent sources should be ramped on during the first 20yus of the simulation However a DC operating point analysis is performed using the constraints specified on a ic directive 96 steady Stop the simulation when steady state has been reached This is required for an efficiency calculation rep
110. his is the definition of the subcircuit subckt divider nl n2 n3 ri nil n2 1k r2 n2 n3 1k ends tran Zu end Which runs after expanding to Expand X1 into two resistor network rrisl a P 1k rede d EL Lk vl a 0 pulse 0 10 5p 5p 0 Lui tran 3p Note that unique names based on the subcircuit name and the subcircuit definition element names are made for the circuit elements inserted by subcircuit expansion TEMP Temperature Sweeps This is an archaic form for the step command for temperature It performs the simulation for each temperature listed The syntax TEMP lt T1 gt lt T2 gt is equivalent to 93 STEP TEMP LIST lt T1 gt lt T2 gt TF Find the DC Small Signal Transfer Function This is an analysis mode that finds the DC small signal transfer function of a node voltage or branch current due to small variations of an independent source Syntax TF V lt node gt lt ref gt lt source gt TF I lt voltage source gt lt source gt Examples TE V out Vin ERY V 5 3 Vin TF I Vload Vin TRAN Perform a Nonlinear Transient Analysis Perform a transient analysis This is the most direct Simulation of a circuit It basically computes what happens when the circuit is powered up Test signals are often applied as independent sources Syntax TRAN lt Tstep gt lt Tstop gt Tstart dTmax modifiers TRAN lt Tst
111. i from the LTC web server The master index file contains the checksums for every file in the sub directories The local file s checksum is then calculated and checked against the one in the master index file The file on the web server will then be downloaded automatically if there LTspicelV program files that were saved under the same name will be overwritten Most of the macromodels are less than 3KB and can be transferred ina few seconds During the update of the SCAD3 E is a difference in checksum first copied to the Windows temp direc XE the new file is tory and the old SCAD3 EXE is overwritten after the download is complete The old program is still preserved if the user cancels the changelog txt file lists the changes of program revisions 202 file transfer The Index AC Performan AC analysis s sccccscescgesvieneee a a weston nibh tsb aeredeas Moe aban cath ieee eects 64 BACKANNO Annotate the subcircuit pin names on to the port currents 0 0 ee eeeeeeeeeeeeeee 65 DC Perform a DC source sweep analysis 65 END EE 66 ENDS oiea e eebe Aandi naam eeneg Ape baile wens 66 Ferret Download a File Given the URL 68 GLOBAL Declare global nodes 42 25 525 5 sssussshi oesie reei eE SEET EE E E S 68 IC s t o E Eeer TEE 68 INCLUDE 1nclide another EE 69 LIB gt Includ a library EE 70 LOADBIAS Load a previously solved DC solutton cc ccceeecseeee
112. ial fit to the logarithm of the switch s conduction There is also a level 2 voltage controlled switch which is an advanced version of the level 1 switch with negative hysteresis The level 2 switch is never completely on or off The conduction as a function of control voltage Vc is g Vc exp A atn Vc Vt Vh B where A pi log 1 Ron log 1 Roff B log 1 Ron log 1 Roff Also the transition of the level 2 switch to current limit is gradual instead of abrupt At a fixed control voltage the I V curve is giving by the equation 160 I V Ilimit tanh g Vc V The level 2 switch supports the option to conduct in only one direction by either specifying the flag oneway or specifying a voltage drop with parameter Vser The transition between forward conduction and reverse open circuit can be specified to be a smooth transition by specifying the parameter epsilon to be non zero T Lossless Transmission Line Symbol Name TLINE Syntax Txxx L L R R Zo lt value gt Td lt value gt L and L are the nodes at one port R and R are the nodes for the other port Zo is the characteristic impedance The length of the line is given by the propagation delay Td This element models only one propagation mode If all four nodes are distinct in the actual circuit then two modes may be excited To simulat
113. ices A diode requires a model card to specify its charac One is a comp ideali conduc conduc teristics There are two types of diodes available a conduction region wise linear model that yields utationally light weight representation of an zed diode It has thr linear regions of tion on off and reverse breakdown Forward tion and reverse breakdown can non linear by specifying a current limit with Ilimit revIlimit tanh is used to fit the slope of the forward conduction to the limit current The parameters epsilon and revepsilon can be specified to smoothly switch between the off and conduc ting states A quadratic function is fit between the off and on state such that the diode s IV curve is contin over a off to transi 110 uous in value and slope and the transition occurs voltage specified by the value of epsilon for the forward conduction and revepsilon for the tion between off and reverse breakdown Below are the model parameters for this type of diode Name Description U Def n aul i t t s Ron Resistance in forward Q i conduction Roff Resistance when off Q Te Gmi n Vfwd Forward threshold V 0 voltage to enter conduction Vrev Reverse breakdown V Inf voltage in Rrev Breakdown impedance Q Ron Ilimit Forward current limit A Inf in Revili Reverse current limit A Inf mit ims Epsilo Width of quadratic V 0
114. ify an equivalent series resistance series inductances parallel resistance and parallel shut capacitance The equivalent circuit is given below Rser Cpar lt Inductance gt Inductor Instance Parameters Na Description me Rs Equivalent series resistance er Rp Equivalent parallel resistance ar 127 Cp Equivalent parallel capacitance ar m Number of parallel units we Initial current used only if uic flagged on the tran card tec Linear inductance temperature coeff Tce Quadratic inductance temperature coeff te Instance temp mp It is better to include the device parasitics Rpar Rser and Cpar in the inductor than to explicitly draft them LTspice uses proprietary circuit simulation technology to simulate this physical inductor without any internal nodes This makes the simulation matrix smaller faster to compute and less likely to be singular over all time step sizes By default LTspice will supply losses to inductors to aid SMPS transient analysis For SMPS these losses are of usually of no consequence but may be turned off if desired On the Tools gt Control Panel gt Hacks page uncheck Supply a min inductor damping if no Rpar is given This setting will be remembered between invocations of the program There is also a default series resistance of 1 milliohm for inductors that aren t mentioned in a mutual inductance statement This R
115. ile won t be affected Transformer Models How do I build a transformer model The best way would be to draft a model with coupled inductors with a mutual inductance statement placed as a SPICE directive on the schematic See the section on mutual Inductance for more information Inductors participating in a mutual inductance will be drawn with a phasing dot The following example demonstrates a transformer with 1 3 turns ratio one to nine inductance ratio with a sine wave input and simulates for 0 1ms The K is set to 1 to model a transformer with no leakage inductance 185 Linear Technology SwitcherCAD Ill xformer asc lp si gy File Edit View Simulate Tools Window Help lei x ST Hl o seage sla Sls vlelclel alal li K1 L1 L2 1 L2 9OOWH 100K sine 0 1 100K tran 0 14ms Third party Models This section explains the basics to adding a third party model to LTspice IV Basically there are two types of third party SPICE models those described with a MODEL statement and those defined with a SUBCKT Models given as MODEL statements are for intrinsic SPICE devices like diodes and transistors The MODEL statement gives the parameters for the specific component The behavior of the device it already known by SPICE only the parameters need to be given to finish specifying the component s electrical characteristics On the other ha
116. imit for termination of adaptive gmin stepping Do not plot marching waveforms Go directly to gmin stepping Historically numdgt was used to set the number of Significant figures used for output data In LTspice if numdgt is set to be gt 6 double precision is used for dependent variable data Relative ratio between the largest column entry and an acceptable pivot value Absolute minimum value for a matrix entry to be accepted as a pivot 83 reltol srcstepmethod sstol startclocks temp tnom topologycheck trtol trytocompact vntol plotreltol plotvntol 84 Num Num Num Num Num Num Num Num 001 001 2726 SE luv 0025 10V Relative error tolerance Which source stepping algorithm to start with Relative error for steady state detection Number of clock cycles to wait before looking for steady state Default temperature for circuit element instances that don t specify temperature Default temperature at which device parameters were measured for models that don t specify this temperature Set to zero to skip check for floating nodes loops of voltage sources and non physical transformer winding topology Set the transient error tolerance This parameter is an estimate of the factor by which the actual truncation error is overestimated
117. imulate gt Efficiency jon gt Mark Start whenever it is clear that you ve ted substantial data that you don t want to be included ntegration of efficiency ic directive to specify node voltages and inductor to reduce the length of the transient analysis required the steady state nodiscard state is Don t delete the part of the transient simulation before steady reached 97 step Compute the step response of the circuit This function works with a current source used as a load with a list of step currents The procedure is 1 compute to steady state and discard the history unless nodiscard is set 2 ramp the step load to the next value in the list of currents at the rate of 20A us 3 compute to steady state 4 change the step load to the next value in the list or quit if there is none Due to the circuit complexity the automatic STEP transition might not be detectable Under this circumstance it is best to use the TRAN command to run the transient simulation and observe the starting and ending periods of the desired step load response Use PWL command to program the output load current and switches to different levels at desired time periods For example PWL 0 0 5 Im 0 5 1 01m 0 1 3m 0 1 3 01m 0 5 The load current starts with 0 5A at time 0 stays at 0 5A at I1ms switches to 0 1A at time 1 01ms stays at 0 1A until 3ms and switches to 0 5A at 3 01ms and stays a
118. indicate if the field should be visible on the schematic 24 Component Attribute Editor Casen Prefix InstName piceModel Value2 SpiceLine SpiceLine2 The attributes SpiceModel Value Value2 SpiceLine and SpiceLine2 are all part of the overall value of the component In terms of the way the component is netlisted for SPICE the component will generate a line of SPICE that looks like this lt name gt nodel node2 lt SpiceModel gt lt Value gt lt Value2 gt lt SpiceLine gt lt SpiceLine2 gt The prefix attribute character is prefixed to the reference designator if different than the first character of the reference designator The Prefix character and InstName will be separated with a character in this case For example if you have a Prefix attribute of M and an InstName attribute of Q1 the name in the netlist will be M Q1l This allows you use reference designators with a leading character different than SPICE uses to identify the type of device There are three exceptions to the above rule There is one special symbol jumper that does not translate into a circuit element but is a directive to the netlist generator that there are two different names for the same electrically identical 25 node Another exception is a symbol defined to have a prefix of X and both a Value and Value2 attributes defined Such a component netlis
119. it subckt divider A BC Rl AB top R2 B C bot ends divider tran 3m end Z MESFET transistor Symbol Names MESFET Syntax ZXxxx D G S model area off IC lt Vds Vgs gt temp lt value gt A MESFET transistor requires a model card to specify its characteristics The model card keywords NMF and PMF specify the polarity of the transistor The MESFET model is derived from the GaAs FET model described in H Statz et al GaAs FET Device and Circuit Simulation in SPICE EEE Transactions on Electron Devices V34 Number 2 February 1987 pp1l60 169 169 Two ohmic resistances Rd and Rs are included is modeled by total gate charge as a function of gate drain and gate source voltages and is defined by the parameters Cgs Cgd and Pb Na me Al ph La md Rd Pb Kf Af 170 Description Pinch off voltage Transconductance parameter Doping tail extending parameter Saturation voltage parameter Channel length modulation Source Drain ohmic resistance ohmic resistance Zero bias G S junction capaci Zero bias G D Cance Capacitance Gate j unction Flicker noise Flicker noise junction potential coefficient exponent Forward bias depletion coefficient Un it A V2 Charge storage Defa ult oO oO Control Panel Accessing the Control Panel To get to the Control Panel use
120. ith C1 declares that there is a 100pF capacitor between nodes n2 and ground The node 0 is the global Circuit common ground Below is an overview of the lexicon of LTspice o Letter case leading spaces ignored blanks and tabs are o The first non blank character of a line defines the type of circuit element Leading Type of line Charact er e Comment A Special function device B Arbitrary behavioral source C Capacitor D Diode E Voltage dependent voltage source F Current dependent current source G Voltage dependent current source H Current dependent voltage source I Independent current source J JFET transistor K Mutual inductance 60 H a WW O O R HF SW 2 lt a Inductor MOSFET transistor Lossy transmission line Bipolar transistor Resistor Voltage controlled switch Lossless transmission line Uniform RC line Independent voltage source Current controlled switch Subcircuit Invocation MESFET transistor A simulation directive For example options reltol le 4 A continuation of the previous line The is removed and the remainder of the line is considered part of the prior line Numbers can be expressed not only in scientific notation e g lel2 but also using engineering multipliers That is 1000 0 or Lei can also be written as 1K Below is a table of understood multipliers Suffix T G Meg K Mil M u or ul Multi
121. ix QN to Prefix X This causes this instance of the symbol to netlist as a subcircuit instead of an intrinsic bipolar transistor 3 Edit the value NPN to be BFG135 to coincide with the name given on the SUBCKT line 4 Then either 4a Add the SUBCKT BFG135 lines to your schematic or 4b If you have a file Phil lib containing your SUBCKT BFG135 others may be too in this file then you have to add a SPICE directive INCLUDE Phil lib One aspect of adding a SUBCKT model to LTspice is that you need have the symbol used to call the subcircuit and the model agree 188 on the same pin port netlist order The above examples assume the 3 party model you re adding follows popular pin order conventions Further related information is in the help sections Schematic Capture and LTspice The basic idea is that the schematic capture program generates a netlist that the simulator LTspice reads Any aspect of importing 27 party models can be resolved by understanding SPICE netlist syntax and how the schematic capture program generates that syntax There are also tutorials prepared on this topic archived at the independent users group at http groups yahoo com group LTspice Inductor Models How do I design a coupled inductor You first draw at least two inductors and then define the K coefficient between the two inductors See mutual inductance section
122. l of V NSO5 to 1 5V after 1 lus and the 1st fall of V NSO3 to 1 5V after 1l lus This will be labeled res 7 For AC analyses the conditional expressions of complex data are translated to real conditions by converting the expression to its magnitude So in this example MEAS AC rel8 when V out 1 sqrt 2 The result rel8 is the frequency that the magnitude of V out is equal to 0 7071067811865475 Also the result of a MEAS statement can be used in another MEAS statement In this example the 3dB bandwidth is computed MEAS AC tmp max mag V out find the peak response and call it tmp MEAS AC BW trig mag V out tmp sgrt 2 rise l targ mag V out tmp sqrt 2 fall last E 76 Print the difference in frequency between the two points 3dB down from peak response NOTE The data froma AC analysis is complex and so are the measurement statements results However the equality refers only to the real part of the complex number that is mag V out tmp sgrt 2 is equivalent to Re mag V out Re tmp sqrt 2 The AVG RMS and INTEG operations are different for NOISE analysis than the analysis types since the noise is more meaningfully integrated in quadrature over frequency Hence AVG and RMS both give the RMS noise voltage and INTEG gives the integrated total noise Hence if you add the SPICE directives MEAS NOISE out_totn INTE
123. lacing New Components Certain frequently used components such as resistors capacitors and inductors can be selected for placing on the schematic with a toolbar button For most symbols use the menu command Edit gt Component to start a dialog to browse for the device you wish Select Component Symbol Top Directory D xp lib sym DN Power Synchronous Buck Boost DC DC Converter D xp lib sym PowerProducts LTC3440 LTC1983 3 LTC3402 LTC3406B 1 8 LTC3716 LTC1983 5 LTC3404 LTC3411 LTC3717 LTC1986 LTC3405 LTC3412 LTC3718 LTC3200 LTC34054 LTC3413 LTC3719 LTC3200 5 LTC3405A 1 5 C3440 LT C3720 LTC3202 LTC3405A 1 8 LTC3701 LTC372 LTC3251 LTC3406 LTC3704 LTC3728 LTC3251co LTC3406 1 5 LTC370 LTC3728L LTC3400 LTC3406 1 8 LTC3711 LTC3729 LTC3400B LTC3406B LTC3713 LTC3732 LTC3401 LTC3406B 1 5 LTC3714 LTC3778 Cancel Programming Keyboard Shortcuts The menu command Tools gt Control Panel gt Drafting Options gt Hot Keys allows you to program the keyboard short cuts for most commands Simply mouse click on a command and then press the key or key combination you would like to code for the command 20 To remove a shortcut click on the command and press the Delete key Schematic Editing Keyboard Shortcut Map Er S 5 E Sa yy Cite Enders Siis EZ ES Siilin GUILL SSC 2 S A ES ER E7 ER A a F H A EE PCB Netlist Extraction The schematic menu command
124. lean and invert True is numerically equal to 1 and False is 0 Conversion to Boolean converts a value to 1 if the value is greater than 0 5 otherwise the value is converted to 0 Note that LTspice uses the caret character for Boolean XOR and for exponentiation Also LTspice distinguishes between exponentiation x y and the function pwr x y Some 3rd party simulators have an incorrect implementation of behavioral exponentiation evaluating 3 3 incorrectly to 27 instead of 27 presumably in the interest of avoiding the problem of exponentiating a negative number to a non integer power LTspice handles this issue by returning the real part of the result of the exponentiation E g 2 1 5 evaluates to zero which is the real part of the correct answer of 2 828427124746191 This means that when you import a 3rd party model that was targeted at a 3rd party simulator you may need to translate the syntax such as x y to x y or even pwr x y If an optional Laplace transform is defined that transform is applied to the result of the behavioral current or voltage The Laplace transform must be a function solely of s The Boolean 106 AN XOR operator is understood t used in a Laplace expression o mean exponentiation when The frequency response at frequency f is found by substituting s with sqrt 1 2 pi f Th in his Numerical inversion of a Laplac d
125. len C F unit OD len Len Number of Unit 0 Lengths Rel Relative rate of ER change of derivative to set a breakpoint Abs Absolute rate of Ts change of derivative to set a breakpoint NoStepLim Don t limit time flag not it step to less than set line delay NoControl Don t attempt flag not complex time step set 144 control LinInterp Use linear flag not interpolation set MixediInte Use linear flag not rp interpolation set when quadratic seems to fail CompactRe Reltol for RELT 1 history OL compaction CompactAb Abstol for ABST E history OL compaction TruncNr Use flag not Newton Raphson set method for time step control TruncDont Don t limit flag not Cut time step to keep set impulse response errors low Q Bipolar transistor Symbol Names NPN PNP NPN2 PNP2 Syntax Qxxx Collector Base Emitter Substrate Node model area off CH IC lt Vbe Vce gt temp lt T gt Example Ql C B E MyNPNmodel model MyNPNmodel NPN Bf 75 145 Bipolar transistors require a model card to specify its characteristics The model card keywords NPN and PNP indicate the polarity of the transistor The area factor determines th number of equivalent parallel devices of a specified model The bipolar the integral junction transistor model is an adaptation of charge control model of Gumm
126. ll parameter substitution evaluation is done before th simulation begins 67 FERRET Download a File Given the URL This command allows you to download files in batch mode by specifying the urls to have to point your browser a file will be inth or netlist example deck This is handy when you don t wa t every file The download same direct ferret http ltspice linear com software scad3 pdf end GLOBAL Declare Global Nodes Syntax global lt nodel gt Example global VI The global command all lows you to declare that Incdes Tal nt ed tory as the source schematic This command has no effect on the simulation certain nodes mentioned in subcircuits are not local to subcircuit but are absolute global nodes Note that global statement is not Statement IC Set Initial Conditions The ic directive allows initial required circuit common is node 0 and that a global node names that of the form SG_ are also global nodes without being mentioned ina g obal analysis to be specified currents may be specified conditions for transient Node voltages and inductor DC solution is performed using the initial conditions as constraints Note tha although inductors are normally treated as short circuits in the DC solution in oi is specified current so current infinit 68 t
127. lt lhsl gt VAL lt rhsl1 gt TD lt vall gt lt RISE FALL CROSS gt lt count1l gt TARG lt lhs2 gt VAL lt rhs2 gt TD lt val2 gt lt RISE FALL CROSS gt lt count2 gt The range over the abscissa is specified with the points defined by TRIG and TARG The TRI y the simulation if omitted to the end of simulation data and the previous WHEN points statement operates over th LEALL G point defaults Similarly the TARG three of t to the point the TR start of defaults are omit ntir ted then range of data the G TARG MEAS The types of measurement operations that can be done over an interval are Keyw ord AVG Compute th averag of lt expr gt MAX Find the maximum value of lt expr gt Operation perform over interval 75 MIN Find the minimum value of lt expr gt PP Find the peak to peak of lt expr gt RMS Compute the root mean square of lt expr gt NTE Integrate lt expr gt G If no measurement operation is specified the result of the MEAS statement is the distance along the abscissa between the TRIG and TARG points Below are example interval MEAS statements MEAS TRAN res7 AVG V NSO1 TRIG V NSO5 VAL 1 5 TD 1 1lu FALL 1 TARG V NSO3 VAL 1 5 TD 1 1lu FALL 1 Print the value of average value of V NS01 from the 1 fal
128. might move your Pspice simulations to LTspice Many users upgrade from PSpice to LTspice SPICE Netlist How do I create a SPICE netlist A netlist can be created with any text editor capable of generating an ASC file You can view the SPICE netlist of any schematic in LTspice IV with the command View gt SPICE netlist From this view you can copy the netlist to the clipboard by selecting all text and typing Ctrl C to bring the netlist to a different editor How do I run a netlist Just open the text file first and then run it LTspice IV will recognize the file as a netlist if it has file extension of MCT eM Exporting Merging Waveform Data Can I export the waveform data to other applications 196 You can copy a plot as bitmap by making a waveform window the active window and typing Ctrl C Then in an application that accepts bitmap pastes from the clipboard like Word or Paint type Ctrl V Note that this also works for bitmaps of schematics These images can also be exported as Windows metafiles Menu command Tools gt Write to a wmf file which writes the image as vector graphics to a wmf file that can be imported in various desktop publishing tools When exporting a metafile of waveform data you first go to Tools gt Control Panel gt Waveform gt Font and select Arial The default System is highly legible on a CRT but is a fixed font that does
129. nc lt model gt on off Lossless transmission Txx L L R R ZO lt value gt line TD lt value gt Uniform RC line Uxx nl n2 ncommon lt model gt L lt len gt N lt lumps gt Independent voltage Vxx n n lt voltage gt source Current controlled switch Wxx n1 n2 lt Vnam gt lt model gt on off Subcircuit Xxx nl n2 n3 lt subckt name gt MESFET transistor zZzxx D G S model area off IC lt Vds Vgs gt Dot Commands C Simulator Directives Dot Commands To run a simulation sweep noise DC operating point function and transient analysis analyses must be specified not only must the circuit be defined but also the type of analysis to be performed different types of analyses linearized small signal AC There are six be small signal DC transfer Precisely one of these six 63 Whereas the circuit topology is typically schematically drafted the commands are usually placed on the schematic as text All such commands start with a period and are therefor called dot commands AC Perform an Small Signal AC Analysis Linearized About the DC Operating Point The small signal linear AC portion of LTspice computes the AC complex node voltages as a function of frequency First the DC operating point of the circuit is found Next linearized small signal models for all of the nonlinear devices in the circuit are found for this operating point Finally using i
130. nd models given by SUBCKT statements define the modeled component by a collection of circuitry of intrinsic SPICE devices For example the SPICE model of an opamp would be given as a subcircuit 186 The way how to include the model in LTspice depends on whether s a MODEL statement or a SUBCKT the model is given a Example for an NPN transist 1 Add an instance of 2 Edit the value 3 Now either NPN to be BC547C name used in the target MODEL statement 3a Add the MODEL BC5S47C directive on your schematic tor defined with a MODEL statement the symbol NPN to your schematic to coincide with the statement as a SPICE 3b If you have a file bipol lib containing your MODEL other models may be too inthis file then BC547C add the SP schematic extension bipol lib bipol sub iS wlng D CE directive INCLUI DE bipolslib on your Note that bipol lib must be the complete name with any file extensions and that Windows Explorer defaults to not showing the file So you if you have a file called txt which you can edit view in notepad and Windows Explorer shows you the file exits as The SPICE directive to include this file ipol sub txt bipol sub file can t 3c You can alternatively add the If you used inc you will get an error message that that be found MODEL BC547C
131. ndependent voltage and current sources as the driving signal the resultant linearized circuit is solved in the frequency domain over the specified range of frequencies This mode of analysis is useful for filters networks stability analyses and noise considerations Syntax ac lt oct dec Linz lt Nsteps gt lt StartFreq gt lt EndFreq gt The frequency is swept between frequencies StartFreg and EndFreq The number of steps is defined with the keyword oct dec or lin and Nsteps according to the following table Key Nsteps wor d Oct No of steps per octave Dec No of steps per decad Lin Total number of linearly spaced steps between StartFreq and EndFr 64 BACKANNO Annotate the Subcircuit Pin Names to the Port Currents Syntax backanno This directive is automatically included in every netlist LTspice IV generates from a schematic It directs LTspice to include information in the raw file that can be used to refer to port currents by the pin name This allows you to plot the current into the pin of a symbol by mouse clicking on the symbol s pin DC Perform a DC Source Sweep Analysis This performs a DC analysis while sweeping the DC value of a source It is useful for computing the DC transfer function of an amplifier or plotting the characteristic curves of a transistor for model verification Syntax dc lt srcnam gt l
132. ng OVerview cecccecececeseeeeeeeeeceneeesaeeseeeeeseaeeesaeeneaeeesaees 26 Drawing ae fele VE 27 Adding the EE 27 Adding Attrbutes AAA 28 Attribute Vieibltv AA ara iiaa ia 30 Automatic Symbol Generation seseeseeeseeeeeereeresrresrresrissrisssrrssrrssens 31 Piara ehy ieoten dao tet tha eae A EE RA 32 Hierarchy OvervieW ora inti aitain tie a as 32 Rules of Hierarchy sac ascetic Pa ett ate el ai faai liaere ees 32 Navigating the Hierarchie 33 Waveform Viewer 35 Waveform Viewer Overview ccccceceeececeneeeeseeceeaeeeeaaeeeeneeseneeesaeeeeaaeeneneeeed 35 Data Trace Selection cccececcceceeeceeeceeeaeeseneeceeeeeeeaeeseaaesseneeseaaeeeeaaeeseneeesaees 35 ZOOMING EE 40 Waveform Arithmetic 0 cccceesceeeeeececceeeeeeeeeeeeeeceaeeecaaeeeeaeeseeeeesaaeeseaeeseeeees 40 User Defined FUNCtIONS ecccececceeeeceeneeeeaeeeeeeeeeaeeesaaeseeaaeseeeeesaeeneeeeenaees 47 AXIS Tue 48 POU DE ee Eech ENEE EE Ee EE e 48 Color optrett d m ices Pies teeth aes AE dE 49 Attached Cursors taka aa aaa aaa a a aa S aa aa iiad 50 Save Plot Configurations 0 c cccccceeceeeeeceeeeeneeseeeeecaeeeeaaeeeeeeeseaeeesaeeeeeeesaas 54 Fast Access File Fomat a a aa o aa aita 55 LTspice 57 WTO CUCTION EE 58 Circuit Deene eee eine dele ade ieee dade Ae 58 General Structure and Conventions 59 Circuit Element Quick Heierence 62 Do COMMANAS EE 63 C Simulator Directives Dot Commande reer eeree eee 63 AC Perform
133. nt Disclaimer LTspice License Agreement Disclaimer Copyright 2001 2009 Linear Technology Corporation All rights reserved LTspice is Linear Technology Corporation s switch mode power supply synthesis and analog circuit simulation software This software is copyrighted You are granted a non exclusive non transferable non sublicenseable royalty free right solely to evaluate LTC products and also to perform general circuit simulation Linear Technology Corporation owns the software You may not modify adapt translate reverse ngineer decompile or disassemble the software executable s or models of LTC products provided We take no responsibility for the accuracy of third party models used in the simulator whether provided by LTC or the user While we have made every effort to ensure that LTspice operates in the manner described we do not guarantee operation to be error free Upgrades modifications or repairs to this program will be strictly at the discretion of LTC If you encounter problems installing or operating LTspice for the purpose of selecting and evaluating LTC products you may obtain technical assistance by calling our Applications Department at 408 432 1900 between 8 00 am and 5 00 pm Pacific time Monday through Friday general LTC products computer systems We do not provide such technical support circuit simulations that are not for the evaluation of Beca
134. ntrols the switch s impedance A model card is required to define the behavior of the current controlled switch Current Controlled Switch Model Parameters Na Description Un Defaul me it t s TE Threshold current V EL Th Hysteresis V 0 current Ro On resistance Q hr n Ro Off resistance Q 1 Gmin Ef The switch has three distinct modes of current control depending on the value of the hysteresis current Ih f Ih is zero the switch is always completely on or off according to whether the control current is above threshold f Ih is positive the switch shows hysteresis with trip point currents at It Ih and It Ih If Ih is negative the switch will smoothly transition between the on and off impedances The transition occurs between the control currents of It Ih and It Ih The 168 smooth transition follows a low order polynomial fit to the logarithm of the switch s conduction X Subcircuit Syntax Xxxx nl n2 n3 lt subckt name gt lt parameter gt lt expression gt Subcircuits allow circuitry to be defined and stored ina library for later retrieval by name Below is an example of defining and calling a voltage divider and invoking it in a circuit calling a subcircuit This is the circuit Xl in out 0 divider top 9K bot 1K Vl in 0 pulse O 1 0 5m 5m D 1m This is the subcircu
135. omain impulse response is a pol an impulse response is found from in frequency domain response artifacts of FFT s such as spect that is common to discrete FFT S algorithm that exploits that it tentially compu d a topic of current numerical research the FFT of a discrete set points This process is prone to the usual e time domain behavior is found from the sum of the tantaneous current or voltage with the convolution of the tory of this current or voltage wit th the impulse response fer function to the time te bound process the e trans In LTspice tral leakage and picket fencing s LTspice uses a proprietary has an exact analytical expression for the frequency domain response and chooses point and windows to cause such arti Zero However range and resolution It is rec be allowed to make a guess at and number of FFT data points used will be reported in the file sett of the window is the frequency times this resolution is 1 tha source is also potential You can then adjust the al C Capacitor Symbol names CAP POLCAP Syntax Rser lt value gt Cpar lt value gt RLshunt lt value gt series inductance capacitance parall The equival lent c this ting nfft and window length Cnnn nl n2 lt capacitance gt Lser lt value gt m lt value gt temp lt value gt CS LO facts to diffra
136. omplex data you can choose to plot either phase group delay or nothing against the right vertical axis You can change the representation of complex data from Bode to Nyquist or Cartesian by moving the mouse to the left vertical axis of complex data Plot Panes Multiple plot panes can be displayed on one window This allows better separation between traces and allows different traces to be independently autoscaled Traces can be dragged between panes by dragging the label A copy of a trace can be made on another pane by holding down the control key when you release the mouse button 48 Fe inear Technology LTspice SwitcherCAD III astable asc de File View Tools Window Help As E F 4 0 QQQRQ RC Bae saeaoasls Color Control The menu command Tools gt Color Preferences colors allows you to set the colors used for plotting data You click on an object in the sample plot and use the red green and blue sliders to adjust the colors to your preferences 49 Color Palette Editor ER x WaveForm Schematic E Netist Click on an item above to change its color Selected ltem Trace v M Selected Item Color Mix 7 i ance Red _______ 0 EE Apply S I J 0 Defaults OK D OD OD es CA Be on Attached Cursors There are up to two attached cursors available You can attach a cursor to a trace by left mouse clicking on the trace label You
137. on off model MySwitch SW Ron 1 Roff 1lMeg Vt 0 Vh 5 Lser 10n Vser 6 The voltage between nodes nc and nc controls the switch s betw n nodes nl and n2 impedanc to defin the behavior of the switch examples Educational Vswitch asc to see an card placed directly on a schematic as a SPICE direct A model th S schema card is required Eiter Fake example of a model tive Voltage Controlled Switch Model Parameters Na me vt Vh Ro Ro ff Ls er Description Threshold voltage Hysteresis voltage On resistance Off resistance Series inductance Un it Defa ult 1 Gm in 159 Vs Series voltage V Ove er Il Current limit A Infi im n it The switch has three distinct modes of voltage control depending on the value of the hysteresis voltage Vh If Vh is zero the switch is always completely on or off depending upon whether the input voltage is above the threshold If Vh is positive the switch shows hysteresis as if it was controlled by a Schmitt trigger with trip points at Vt Vh and Vt Vh Note that Vh is half the voltage between trip points which is different than the common laboratory nomenclature If Vh is negative the switch will smoothly transition between the on and off impedances The transition occurs between the control voltages of Vt Vh and Vt Vh The smooth transition follows a low order polynom
138. op gt modifiers The first form is the traditional tran SP is the plotting increment for the waveform ICE command Tstep s but is also used as an initial step size guess LTspice uses waveform compression so this parameter is of little value and can be omitted or set to zero Tstop is the duration of the simulation Transient analyses always start at time equal to zero However if Tstart is specified the waveform data between zero and Tstart is not saved This is a means of managing the size of waveform files by allowing startup transients to be ignored 94 The final parameter dTmax is the maximum time step to take while integrating the circuit equations If Tstart or dTmax is specified Tstep must be specified Several modifiers can be placed on the tran line WAVE Write Selected Nodes to a Wav File LTspice can write wav audio files These files can then be listened to or be used as the input of another simulation Syntax wave lt filename wav gt lt Nbits gt lt SampleRate gt V out V out2 example wave C output wav 16 44 1K V left V right lt filename wav gt is either a complete absolute path for the wav file you wish to create or a relative path computed from the directory containing the simulation schematic or netlist Double quotes may be used to specify a path containing spaces lt Nbits gt is the number of sampling bits The valid range is from
139. or a given simulation without compromising the accuracy or detail of the switching waveforms Another benefit of these new simulation devices is that convergence problems are easier to avoid since they like the board level component the model have finite impedance at all frequencies Modern switch mode power supplies include controller logic with multiple modes of operation For example devices may change from pulse switch modulation to burst mode or to cycle skipping depending on the circuit s operation An original new mixed mode compiler and simulator were written into LTspice that allows these products to be realistically modeled ina computationally fast manner But despite LTspice s close association with SMPS design it not a SMPS specific SPICE but simply a SPICE program fast enough to simulate a SMPS interactively There are currently approximately fifteen hundred Linear Technology products modeled in LTspice The program is freely downloadable from the Linear Technology website and is a high performance general purpose SPICE simulator Included are demonstration files that allow you to watch step load response start up and transient behavior on a cycle by cycle basis Included with the SPICE is a full featured schematic entry program for entering new circuits Hardware Requirements LTspice IV runs on PC s running Windows 98 2000 NT4 0 Me XP Vista or Windows 7 Since a simula
140. ort Steady state detectio are writ nis written into the SMPS macromodels Typically they ten to look for zero error amp output current averaged over a clock cycle The algorithm takes the error amp s output compliance range into consideration The fraction of peak current that is considered zero current is specified with the sstol option The auto too Grit specify simulati Calculat command integrat matic steady state detection can fail either by being ical or not critical enough You can interactively steady state in the following manner As soon as the on starts execute menu command Simulate gt Efficiency ion gt Mark Start The first time you execute this you tell LTspice you re going to manually specify the ion limits After the circuit looks like it s reached steady s history awhile Simulate execute tate execute that command again That will clear the and restart the Efficiency Calculation Then after as in you see well more than 10 clock cycles execut gt Efficiency Calculation gt Mark End Each time you Simulate gt Efficiency Calculation gt Mark Start you restart history the efficiency calculation and clear the waveform This is a good method of preventing the data file from becoming too large and slowing down plotting so it s recommen Calculat accumula in the i Use the currents to find ded that you periodically execute S
141. ositive current is in the direction into the pin It is also possible to point at voltage differences with the mouse You can click on one node and drag the mouse to another node You will see the red voltage probe at the first node and a black probe on the second This allows you to differentially plot voltages 36 Fe Linear Technology LTspice SwitcherCAD III LT1371 l EF File Edit View Simulate Tools Window Help ASOT 4 9 QQQRQ CC Bae sae gt MBRS340 SUS 12us 16us Release Left button to plot SWV OUT Yet another schematic probing technique is to plot the instantaneous power dissipation of a component To dothis hold down the Alt key and click on the body of the symbol of the component The instantaneous power dissipation will be plotted as an expression of voltages and currents It will be plotted on its own scale with the units of Watts The mouse cursor turns into an icon that looks like a thermometer when it s pointing at a dissipation that can be plotted You can find the average power dissipation by control clicking the trace label 37 F Linear Technology LTspice SwitcherCAD III LT1371 Mi E3 File Edit Hierarchy View Simulate Tools Window Help DeH e F 0 QQQRQ E Ss Ar 1 340 m m D MBR i fLT1371 asc Sus 12us 16us Left click to plot D1 dissipation V SW OUT I D1 Ax Menu command Plot Settings gt Visible Traces The menu command Plot
142. ou would like to check for updates LTspice never accesses the web without asking for your permission to do so LTspice contains no spyware or transmits any type of data while obtaining the files it need for update Don t cache files Neither cache nor use files cached on our machine for the update Don t verify checksums For security reasons LTspice uses a proprietary and confidential 128bit checksum algorithm to authenticate the files it receives off the web for updating This authentication can be disabled in case there s an error in that algorithm However no problem with this has ever been reported so it is not recommended that you ever defeat this security feature 183 LTspice uses only high level operating system calls for its Internet access It should not be required to make any adjustments to these settings except in rare cases when you need to specify the Proxy server and password since LTspice is not managing the Internet access but your computer and operating system Settings on this pane are not remembered between program invocations FAQs Installation Problems How do I install LTspice IV 1 Go to http www linear com and download the file LTspicelV exe into a temporary directory on your PC 2 Execute the file LTspicelIV exe to install On Vista you will want to run this as Administrator I m running a Chinese Edition of Windows The Greek Mu character doesn t sho
143. plier lel2 leg le6 le3 25 4e 6 le 3 6 9 le 12 15 61 The suffixes are not case sensitive Unrecognized letters immediately following a number or engineering multiplier are ignored Hence 10 10V 10Volts and 10Hz all represent the same number and M MA MSec and MMhos all represent the same scale factor 001 A common error is to draft a resistor with value of 1M thinking of a one Megaohm resistor however 1M is interpreted as a one milliohm resistor This is necessary for compatibility with standard SPICE practice LTspice will accept numbers written in the form 6K34 to mean 6 34K This works for any of the multipliers above It can be turned off by going to Tools gt Control Panel gt SPICE and unchecking Accept 3K4 as 3 4K Nodes names may be arbitrary character strings Global circuit common node ground is 0 though GND is special synonym Note that since nodes are character strings O and 00 are distinct nodes Throughout the following sections of the manual angle brackets are placed around data fields that need to be filled with specific information for example lt srcname gt would be the name of some specific source Square brackets indicate that the enclosed data field is optional Circuit Element Quick Reference Component Syntax Special functions Axx nl n2 n3 n4 n5 n6 n7 n8 lt model gt extra par
144. plifies benchmarking LTspice against other SPICE programs iii professionals historically experienced with SPICE circuit simulators are familiar with working directly with the textual netlists because schematic capture was not integrated with SPICE simulators in older systems Example Circuits There are several resources of example circuits for LTspice IV There is a directory typically installed at C Program Files LTC LTspiceIV examples Educational that gives numbers non commercial examples of SPICE simulations that illustrate different analysis types methods or program features In the directory C Program Files LTC LTspicelV examples jigs there is an example simulation for every Linear Technology device with a macromodel in LTspice IV Note that these jig circuits are often only test jigs for the macromodel not necessarily recommended reference designs Most importantly your Linear Technology office can probably give you design support specific you your application needs F jlinear Technology LTspice SwitcherCAD III 5v 12 20mA 1316 asc Eg File Edit Hierarchy View Simulate Tools Window Help ASHT ZJ QQQRQ EKE eA S Ain sw Open an existing file Look in Le boost D DI cr ES ASV 12V 16m 1073 asc 41 5 3 39 75mA 1307 asc 1 54 3V 20mA 1073 asc K 1 5V 3V 30mA 1610 asc
145. r measurement temperature Transconductance parameter exponential temperature coefficient Threshold voltage temperature coefficient Gate junction emission coefficient Gate junction recombination current parameter Emission coefficient for Isr Tonization coefficient Tonization knee oN d i Q E ee lt 27 50 125 voltage Xti Saturation current 3 temperature coefficient K Mutual Inductance Symbol Names None this is placed as text on the schematic Syntax Kxxx Ll L2 L3 lt coefficient gt Ll and L2 are the names of inductors in the circuit The mutual coupling coefficient must be in the range of 1 to 1 The line Kl L1 L2 L3 La 1 is synonymous with the six lines K1 L1 L2 K2 L2 L3 K3 L3 L4 K4 L1 L3 K5 L2 L4 K6 L1 14 It is recommended to start with a mutual coupling coefficient equal to 1 This will eliminate leakage inductance that can ring at extremely high frequencies if damping is not supplied and slow the simulation However a mutual inductance value of 1 or 1 can lead to simulation difficulties if the uic directive is flagged on the tran card 126 L Inductor Symbol Names IND IND2 Syntax Lxxx n n lt inductance gt ic lt value gt Rser lt value gt Rpar lt value gt Cpar lt value gt m lt value gt temp lt value gt It is possible to spec
146. ratic temperature coefficient Rc linear temperature coefficient Rc quadratic temperature coefficient C 27 2 42 NPN ie PNP 87 NPN 52 PNP le 1 1 Co 0 ul not set Q 0 V 1 20 6 V 10 1 0 mG 1 0 Gs 2 1 0 2G 1 0 wC 2 1 0 SE 1 0 SE 149 Trm1 Rmb linear temperature coefficient 1 ye Trm2 Rmb quadratic temperature 17 coefficient SE 2 Iss Substrate junction saturation A current Ns Substrate junction emission Coefficient The model parameter level can be used to specify another type DAnalyse GmbH contribution of source Berlin Set Level 4 is a synonym for of BJT in LTspice Due to a generous code from Dr Ing Dietmar Warning of Germany LTspice includes a version of VBIC Level 9 to use the alternate devic level 9 The following documentation has been supplied by Dr Warning VBIC Vertical Bipolar Inter Company model VB O The VBIC model is a Gummel Poon bipolar transistors technologies xtended development of the Standard SGP model with the focus of integrated in today s modern semiconductor With the implemented modified Quasi Saturation model from Kull and Nagel it is also possible to model the special output characteristic of switching transistors the SGP model for silicon integrated processes O O O O O
147. reated as urces in LTspice ICE programs if an initial Syntax ic V lt nl1 gt lt voltage gt I lt inductor gt lt current gt Example ic V in 2 V out 5 V vc 1 8 I L1 300m INCLUDE Include Another File Syntax include lt filename gt This directive includes the named file as if that file had been typed into the netlist instead of the include command This is useful for including libraries of models or subcircuits An absolute path name may be entered for the filename Otherwis LTspice looks first in the directory lt LTspiceIV gt lib sub and then in the directory that contains the calling netlist where lt LTspicelV gt is the directory containing the scad3 exe executable typically installed as C Program Files LTC LTspicelV No file nam xtension is assumed You must use inc myfile lib not inc myfile if the file is called myfile lib It is possible to specify a url of the following form as a file name inc http www company com models library lib The file library lib will be http transferred to the circuit directory and included For subsequence simulations in the interest of avoiding downloading the file each time you run the Simulation you can edit the inc statement to 69 inc library lib Note that if the url you specify doesn t exist most web servers don t return an error but return a html web page
148. ribing Vbc dependence of Tf High current parameter for effect on TE Excess phase at freq l1 T 2 PI Hz B C zero bias depletion Capacitance B C built in potential B C junction exponential factor Fraction of B C depletion Capacitance connected to internal base node Ideal reverse transit time Zero bias collector substrate Capacitance Substrate junction built in potential Substrate junction exponential factor Forward and reverse beta temperature exponent Energy gap for temperature effect on Is Temperature exponent for effect on Is Flicker noise coefficient Flicker nois xponent eV 533 sTo 233 275 EEN Fe Tnom Cn Gamm Qco Quas imod Rco Vg Vo Trel Tre2 Trbl Trb2 Tred EREZ Coefficient for forward bias depletion capacitance formula Parameter measurement temperature Quasi saturation temperature coefficient for hole mobility Quasi saturation temperature coefficient for scattering limited hole carrier velocity Epitaxial region doping factor Epitaxial region charge factor Quasi saturation flag for temperature dependenc Epitaxial region resistance Quasi saturation extrapolated bandgap voltage at 0 K Carrier mobility knee voltage Re linear temperature coefficient Re quadratic temperature coefficient Rb linear temperature coefficient Rb quad
149. rpose Schematic Driven SPICE AA 9 H H Current Dependent Voltage Source 117 Hardware Requirements nsei renees r usta evitGhins EES chase een dE 5 I TCurrent Sour e aeeoa aa eaa ra a E a Aaa aE EE SAET aap Ra ESE REEE A 118 TH Circuit Element Quick Reterence 62 Is there a paper Mana 3 ccs sc ssissesssessspstetechastssveussdaasdessissssveesseseveshsceoeosddseeesepsasnsosiesvsessessaeeecans 199 J J JFET transistor E 123 K K Mu t al Inductance ieia ei EEE cante bls dE E E E A 126 L Reg rte E TEE 127 Leabel a Node Mame orien oprni anen SE EENE ETARE deed Dee aaa 17 License Agreement Disclaimer ist0ss achat Meena Ee 6 LT Spice Overview sities ieee ihe ee acne shale aia 57 TE PSpiCe LV OVELVICW sricsts Sesied ae EE ZE 200 M MMOS BEE tege eher eet 132 Modes of Operation eeh Eege Ee Ee T N Navigating the Hietarc EE 33 204 Netlist Options it c3s ni ene on Seege Ane ae eae ee eier beeen 178 O O Lossy Transinission LANet ieas eaa e E EE SEENEN 143 Operations tesa euer EENS 173 ON GRVIC Wes E A E E siasdravsausssdusevunsave suataguebnetuansast ssbesvonsare EE 32 P PCB Netlist Batraeten et B nner eege eege aun hie abandon 21 Placing Components onni ecco dea dee aceite deed see ened ee 20 Plot Pane Sin niran eeneg EES Ego 48 Lee E A Programming Keyboard Shortcuts 0 ceceescsssessssecsseseceeeeeceseccessecseesccneeseesaeeeseecsaecaessecaeeaeeneeeeeeas 20 Q CH Bipolar transistor soie iaro reee ee aie
150. ser allows LTspice IV to integrate the inductance as a Norton equivalent circuit instead of Thevenin equivalent in order to reduce the size of the circuit s linearized matrix If you don t want LTspice to introduce this minimum resistance you must explicitly set Rser 0 for that inductor This will require LTspice to use the more cumbersome Thevenin equivalent of the inductor during transient analysis There are two forms of non linear inductors available in LTspice One is a behavioral inductance specified with an 128 expression for the flux The inductor s current is referred to by the keyword x in the expression Below is an example in a netlist L1 NOO1 0 Flux lm tanh 5 x O NOO1 PWL O O 1 1 tran end In the above example Il supplies a unity dI dT so that the inductance can be read off as the voltage on node N001 There other non linear inductor available in LTspice is a hysteretic core model based on a model first proposed in by John Chan et la in IEEE Transactions On Computer Aided Design Vol 10 No 4 April 1991 but extended with the methods in United States Patent 7 502 723 This model defines the hysteresis loop with only three parameters N Description Units a m e H Coercive force Amp turns mete e r B Remnant flux density Tesla r B Saturation flux density Tesla s The upper and lower branch
151. ser to prepare a library that another user can use in a simulation without revealing the implementation of the library A reasonable attempt has been made to make the encrypted library difficult to decode by unauthorized concerns but it cannot be considered perfectly secure if for no other reason than it is implemented in software To prepare an encrypted library you need to invoke LTspice from the command line with the command line option encrypt You will need to first backup the library because it will be replaced with the encrypted version THERE EXISTS NO UTILITY TO CONVERT AN ENCRYPTED LIBRARY BACK TO CLEAR TEXT Below summarizes the two steps 1 Make a backup copy of the library The version you encrypt is deleted 2 From a command line type scad3 exe encrypt lt filename gt The file lt filename gt will be replaced with an encrypted version The encryption process will take a few minutes One this process is finished you have an encrypted ASC file It s possible to add a copyright notice above the Begin line but the first 9 lines of the file must remain unchanged and each line of copyright notice you add must begin with the character That is here an encrypted file written by LTspice LTspice Encrypted File This encrypted file has been supplied by a 3rd party vendor that does not wish to publicize th
152. sine wave voltage source Nam Description Uni e ts Vof DC offset V fse 164 Vam Amplitude V p Fre Frequency Hz q Td Delay sec The Damping factor ifs ta ec Phi Phase of sine wave deg ree E Ncy Number of cycles Omit cyc cle for free running pulse les S function For times less than Td or times after completing Ncycles have run the output voltage is given by Voffset Vamp sin pi Phi 180 Otherwise the voltage is given by Voffset Vamp exp time Td Theta sin 2 pi Freg time Td pi Phi 180 The damping factor Theta is the reciprocal of the decay time constant Syntax Vxxx n n EXP V1 V2 Tdl Taul Td2 Tau2 Tim dependent exponential voltage source Nam Description Un e it s Vi1 Initial value V V2 Pulsed value V 165 Tdl Tau Td2 Tau Rise delay time Rise time constant Fall delay time Fal time constant For times less than between Tdl and Td2 V1 V2 V1 1 se se se se Tdl the output voltage is Vl For times the voltage is given by For times after Td2 xp time Td1 Taul the voltage is given by V1 V2 V1 1 exp tine Tdl Taul V1 V2 l exp time Td2 Tau2 Syntax Vxxx n n SFFM Voff Vamp Fcar MDI Fsig Time dependent single frequency FM voltage source Nam Vof Vam Fca 166 Description DC offset Amplitude Carrier fr
153. t DU DA The PWL can have almost unlimited pairs of time value sequence Circuit Elements A Special Functions 98 Symbol names INV BUF AND OR XOR SCHMITT SCHMTBUF SCHMTINV DFLOP VARISTOR and MODULATE Syntax Annn n001 n002 n003 n004 n005 n006 n007 n008 lt model gt instance parameters These are Linear Technology Corporation s proprietary special function mixed mode simula behavior are undoc tion devices Most of these and their umented as they frequently change with each new set of models available for LTspice However here w document some of them because of their general interest INV BUF AND OR gates All gates and XOR are generic idealized behavioral are netlisted wi gates require no from the complementary oul through device com inputs Unused in terminal 8 The d xternal power mon terminal 8 puts and outputs flag that that terminal is not use th eight terminals These Current is sourced or sunk tputs terminals 6 and 7 and returned Terminals 1 through 5 are are to be connected to igital device compiler recognizes that as a d and removes it from the simulation This leads to the potentially confusing situation where AND gates act differently when an input is grounded or at zero volts If ground is the gate s common then the grounded input is not at a logic false condition
154. t Vstart gt lt Vstop gt lt Vincr gt lt srcnam2 gt lt Vstart2 gt lt Vstop2 gt lt Vincr2 gt The lt srcnam gt is either an independent voltage or current source that is to be swept from lt Vstart gt to lt Vstop gt in lt Vincr gt step sizes Inthe following example the default BSIM3v3 2 4 characteristic curves are plotted Example dc sweep MI 2 1 0 0 nbsim Vgs 1 0 3 5 Vds 2 0 3 5 sde Vds 3 5 0 0 05 Vgs 0 3 5 0 5 model nbsim NMOS Level 8 save I Vds end 65 END End of Netlist This directive marks the end of the textual netlist All lines after this one are ignored Do not place this as text on the schematic as the netlist extractor supplies it at the end ENDS End of Subcircuit Definition This directive marks the end of a subcircuit definition See SUBCKT for more information FOUR Compute a Fourier Component after a TRAN Analysis Syntax four lt frequency gt Nharmonics Nperiods data tracel gt lt data trace2 gt Example four 1kHz V out This command is performed after a transient analysis It s supplied in order to be compatible with legacy SPICE simulators The output from this command is printed in the log file Use the menu item View gt Spice Error Log to see the output For most purposes the FFT capability built into the waveform viewer is more useful If the integer Nharmonics is present then the analysis
155. the SMPS macromodels to be written with information on how to detect steady state Usually this is detected by noting when the error amp current averaged over a clock cycle diminishes to a small value for several cycles Then at a clock edge the energy stored in each reactance is noted and the simulation is run for another ten clock cycles but now integrating the dissipation in every device At the clock edge of the last cycle the energy stored in every reactance is noted again and the simulation is stopped The efficiency is reported as the ratio of output power delivered to the load by the input power sourced by the input voltage after making an adjustment for the change in energy 12 stored in the reactances Since the dissipation of each device was also noted it is possible to look how close the energy checksum is to zero You can usually compute efficiency of SMPS circuits you draft yourself by using steady state is detected on the Edit Simulation Command editor After the simulation checking the Stop simulating if use the menu command View gt Efficiency Report Automatic detection of steady state doesn t always work Sometimes the criteria for steady state detection is too strict and sometimes too lenient parameter sstol or simply interactively set th efficiency integration You then either adjust the option limits for the Command Line Switches The following t
156. tical double diffused MOS transistor This allows a power device to be modeled with an intrinsic VDMOS device LTspice instead of a subcircuit as in other SPICE programs See models definition for details Can I add my own MOSFET models Yes you can add your own model in the C Program Files LTC LTspicelIV lib cmp standard mos file This file is only for devices defined with a model statement not as subcircuits If you want to use a subcircuit follow the following steps 1 Change the Prefix attribute of the component instance of the symbol to be an X Don t change the symbol just the instances of the symbol as a component on a schematic You can access this attribute by holding down the control key and right clicking on the body of the component 190 2 Edit the Value attribute of the component to coincide with the name of the subcircuit you wish to use Add a SPICE directive on the schematic such as inc filename where filename is the name of the file containing the definition of the subcircuit Note that this must be the complete name with any file extension and Windows Explorer defaults to not showing the fil xtension So you if you have a file called mylib sub txt which you can edit view in notepad and Windows Explorer shows you the file exists as mylib sub The SPICE directive to include this file is inc mylib sub txt If you used inc mylib sub you will get
157. tion before proceeding to the rest of the simulation 90 The keyword internal can be added to indicate that the internal nodes of some devices should also be kept so that a more complete version of the DC solution is kept If you want to save a particular DC operating point froma tran analysis you can give specify a time The first solved time point after the stipulated time will be written The modifier repeat will cause the DC solution to be written after every period specified by this time The file will contain only the most recently solved DC point DC1 DC2 and DC3 can be given to extract a single operating point from dc sweep analysis The savebias command writes a text file in the form of a nodeset command Note that nodeset statements are only recommendations of the solution That is the solver will start iterating the solution with the node voltages given in the nodeset statements but will continue iterating until it s satisfied that the solution is valid If you want to restart a tran solution from the DC operating point you can edit the file from a nodeset to a ic to try to coercive the solver to start from this DC state Since the integration state of all the circuit reactances isn t saved inthe savebias file success with this technique varies STEP Parameter Sweeps This command causes an analysis to be repeat
158. tion can generate many megabytes of data ina few minutes free hard disk space gt 10GB and large amount of RAM gt 1GB are recommended Basically the program can run on any PC with Windows 98 or above but the simulation may not finish if there is not enough hard disk space LTspice IV will also run on Linux The program has been tested on Linux RedHat 8 0 with WINE version 20030219 Software Installation LTspice IV can be downloaded from the LTC website http www linear com A direct link to the distributed file is http litspice linear com software LTspicelIV exe The file LTspicelV exe is a self extracting gziped file that installs LTspice IV as it extracts LTspice IV is updated often After LTspice IV is initially installed you can use a built in update menu command that will bring your installation to the current revision level if you have access to the web The update process will first download a master index file from Linear s website that has the size and checksum of each file in the distribution If there is a file missing of a different size or a difference between the local checksum and the one from the index file then that file will be updated automatically Component databases are merged in the update process so if you ve added devices to your installation those additions won t be lost when you run the automatic update utility License Agreeme
159. to plot 1 pow v 9 2 abs V 1 1 le Q13 T l Delete this trace 50ns 100ns 150ns 200ns 250ns Right Click to edit expression Control Left Click to integrate The difference of two voltages e g V a V b can equivalently written as V a b The following functions are available for real data Function Name Description abs x Absolute value of x acos xX Arc cosine of x 41 arccos x acosh x asin x arcsin x asinh x atan x arctan x atan2 y x atanh x buf x ceil x COS x cosh x d exp x floor x hypot x y if x y z int x inv x limit x y z ln x log x log10 x max x y min x y Synonym for acos Arc hyperbolic cosine Arc sine Synonym for sin Arc hyperbolic sine Arc tangent of x Synonym for atan Four quadrant arc tangent of y x Arc hyperbolic tangent if x gt 5 else 0 Integer equal or greater than x Cosine of x Hyperbolic cosine of x Finite difference based derivative e to the x Integer equal to or less than x sqrt x 2 y 2 If x gt 5 then y else z Convert x to integer D if x gt 5 else l Intermediate value of x y and Natural logarithm of x Alternate syntax for In Base 10 logarithm The greater of x or y The smaller of x or y pow x y Kee pwr x y abs x y pwrs x y sgn x abs x y rand x Random num
160. ts are used The output is true only when exactly one of all inputs is true Use the associative property of XOR s with multiple XOR devices to implement an XOR block with more than two inputs The Schmitt trigger devices have similar output characteristics as the gates Their trip points are specified with instance parameters Vt and Vh The low trip point is Vt Vh and the high trip point is Vt Vh The gates and Schmitt trigger devices supply no timestep information to the simulation engine by default That is they 100 don t look when they ar The VAR STOR is a voltage controlled varistor voltage is set by the voltage between breakdown impedance is specified with the instance parameter See the example schematic examples Educational varistor asc rclamp terminals 1 and 2 The MODULATE device is a voltage cont the example schematic the FM input and set by the is the frequency when the FM input is frequency when the input is at OV The ampl examples Educational PLL asc instantaneous oscillation frequency is set by the voltage on The conversion from voltage to frequency is linear two instance parameters mark and space Mark the litude is set by the about to change state and make sure there s a timestep close to either side of the state change The instance parameter tripdt can be set to stipulate a maximum timestep size the simulator tak
161. ts as two lines of SPICE lib lt SpiceModel gt lt name gt nodel node2 lt Value2 gt This allows symbols to be defined that automatically include the library that contains the definition of the subcircuit called by the component The netlist compiler removes duplicate lib statements Note that such components are not editable on the schematic The third exception is a symbol that has other exception is a symbol defined to have a prefix of X anda ModelFile attribute defined Such a component also netlists as two lines of SPICE lib lt ModelFile gt lt name gt nodel node2 lt SpiceModel gt lt Value gt lt Value2 gt lt SpiceLine gt lt SpiceLine2 gt Use this method when you want to automatically include a library file yet still want to have an instance of this symbol editable If the symbol attribute SpiceModel exists and is the name of a subcircuit inthe file specified as lt ModelFile gt then a drop list of all subcircuits names will be available when an instance of the symbol is edited on a schematic Creating New Symbols Symbol Editing Overview Symbols can represent a primitive device such as a resistor or a capacitor a subcircuit libraried in a separate file or another page of the schematic This section describes how to define your own new symbols To start a new symbol use the menu command File gt New Symbol 26 NOTE Screen updates during symbol
162. ture coefficient of VBBE ergy for voltage re Delta activation energy for ISRR emission Temperature coefficient of NBBE IS for fwd and rev ISP G3 le 06 157 eb exp VBBE NBBE Vtv 0 be dt Locale Temperature 0 em difference D ve Revision Version E rs vr Reference Version 0 ef References C C McAndrew et al Vertical Bipolar Inter Company 1995 An Improved Vertical IC Bipolar Transistor Model Proceedings of the IEEE Bipolar Circuits and Technology Meeting pp 170 177 1995 C C McAndrew et al VBIC95 The Vertical Bipolar Inter Company Model IEEE Journal of Solid State Circuits vol 31 No 10 October 1996 C C McAndrew VBIC Model Definition Release 1 2 18 Sep 1999 R Resistor Symbol Names RES RES2 Syntax Rxxx nl n2 lt value gt tc tcl tc2 temp lt value gt CH The resistor supplies a simple linear resistance between nodes nl and n2 A temperature dependence can be defined for each resistor instance with the parameter tc The resistance R at will be RS RO o Ce odie ech dee Ae Be FERNS OF SESH sas where RO is the resistance at the nominal temperature and dt is the difference between the resistor s temperature and the nominal temperature 158 S Voltage Controlled Switch Symbol Names Syntax Example SW Sxxx nl n2 nc nc lt model gt S1 out 0 in 0 MySwitch T
163. u wish with respect to the symbol Attribute Window to Add InstName Type SpiceModel Value SpiceLine SpiceLine2 You can modify the text justification and contents of attributes that you ve already made visible by right mouse clicking on the text of the attribute Symbol Attribute lt Value gt Automatic Symbol Generation A symbol can be automatically generated in two situations 31 When editing a schematic you can execute menu item Hierarchy gt Open this Sheet s Symbol When no symbol is found LTspice will ask if you would like one automatically generated This symbol then can be used to call this sheet of circuitry is some higher level schematic Also when editing an ASC netlist that contains subcircuit definitions you place the cursor on the line containing the name of the subcircuit right click and execute context menu item Create Symbol Hierarchy Hierarchy Overview Hierarchical schematic drafting has powerful advantages Much larger circuits can be drafted than can fit onto a one sheet schematic while retaining the clarity of the smaller schematics Repeated circuitry to be easily handled in an abstract manner Blocks of circuitry can be libraried for latter use in a different project Rules of Hierarchy The way to refer to another schematic as a block in a higher level schematic is to
164. unning existing Linear Technology behavioral models Note It is better to use a G source shunted with a resistance to approximate an E source than to use an E source A voltage controlled current source shunted with a resistance will compute faster and cause fewer convergence problems than a voltage controlled voltage source Also the resultant nonzero output impedance is more representative of a practical circuit F Current Dependent Current Source Symbol Name F Syntax Fxxx n n lt Vnam gt lt gain gt This circuit element applies a current between nodes nt and n The current applied is equal to the value of the gain times the current through the voltage source specified as lt Vnam gt Syntax Fxxx n n value lt expression gt This is an alternative syntax of the behavioral source arbitrary behavioral voltage source B 115 Syntax Fxxx n n POLY lt N gt lt V1 V2 VN gt lt c0 cl c2 c3 C4 24 gt This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models G Voltage Dependent Current Source Symbol Names G G2 There are thr types of voltage dependent current source circuit elements Syntax Gxxx n n nc nc lt gain gt This circuit element asserts an output current between the nodes n and n that depends on the input voltage between nodes nc and nc
165. urrent gt AC lt amplitude gt load This circuit element sources a constant current between nodes n and n If the source is flagged as a load the source is forced to be dissipative that is the current goes to zero if the voltage between nodes n and n goes to zero or a negative value The purpose of this option is to model a current load on a power supply that doesn t draw current if the output voltage is zero For AC analysis the value of AC is used as the amplitude of the source at the analysis frequency Syntax Ixxx n n PULSE oft Ion Tdelay Trise Tfall Ton Tperiod Ncycles Time dependent pulsed current source Nam Description Un e it s Tor Initial value A 118 Ion Tde TE Ton Tpe rio Ncy cle Syntax Ixxx n n SINE Pulsed value A Delay se G Rise time se E Fall time se e On time se C Period se C Number of cycles Omit cy for free running pulse cl function es offset Iamp Freq Td Theta Phi Ncycles Time dependent sine wave current source Nam e Iof fse Iam D Fre Td The ta Description Uni ts DC offset A Amplitude A Frequency Hz Delay sec Damping factor l s ec 119 Phi Ncy cle Phase of sine wave Number of cycles Omit for free running pulse function deg ree cyc les For times less than Td or times after completing Ncycles have run the outp
166. use cursor If the horizontal axis is time then this time difference is also converted to frequency 52 Fe Linear Technology LTspice SwitcherCAD III preamp asc File Edit Hierarchy View Simulate Tools Window Help Bs BT 4 0 QQQRQ Sig Aes EE _topxyzasc RIES top xvZ asc PULSE 1m 1m 0 0 0 5u 10u tran 100u Click to plot 1 N003 You can measure differences in this manner without performing the zoom by either pressing the Esc key or right mouse button before releasing the left mouse button 53 Cursor Step Information D A Cursor 1 11 60p 2n2222 vafj 100 Temp 25 Run 4 24 OmV 100mV 200mV 300mV 400mV 500mV Left Click amp drag to move Cursor 1 Right Click to see step temp de values Alternate 7 The attached cursors can also be used to readout which trace belongs to which run of a step dc temp set of simulation runs You can navigate the cursor from dataset to dataset with the up down keyboard cursor keys and then right click on the cursor to see the step information for that run Save Plot Configurations The menu commands Plot Settings gt Save Plot Settings Open Plot Settings files allow you to read and write plot configurations to disk Plot setting files are ASC files that have a file extension of plt The default filename is computed from the name of the data file by replacing the data file s raw extension with plt If such a file name exists when a data file is
167. use of the great variety of PC compatible operating system versions fOr and peripherals currently in use we do not guarantee that you will be able to use LTspice successfully on all such systems to use LTspice switching regulator The software and related documentation are provided AS If you are unable LTC does provide design support for LTC ICs by whatever means necessary IS and without warranty of any kind and Linear Technology Corporation expressly disclaims all including but not limited to merchantability and fitness for a particu other warranties express or implied the implied warranties of lar purpose Under no circumstances will LTC be liable for damages either direct or consequential arising from the use of this product or from the inability to use this product even if we have been informed in advance of the possibility of such damages Redistribution of this software is permitted as long as it is distributed in its entirety files symbols This program is specifically not with all documentation and models without modification or additions example licensed for use by semiconductor manufacturers in the promotion demonstration or sale of their products Specific permission must be obtained from Linear Technology for the use of LTspice for these applications Mode of Operation Overview LTspice IV
168. used in board level switch mode power supplies has behavior that is qualitatively different than the above monolithic MOSFET models In particular i the body diode of a VDMOS transistor is connected differently to the external terminals than the substrate diode of a monolithic MOSFET and ii the gate drain capacitance Cgd non linearity cannot be modeled with the simple graded capacitances of monolithic MOSFET models Ina VDMOS transistor Cgd abruptly changes about zero gate drain voltage Vgd When Vgd is negative Cgd is physically based a capacitor with the gate as one electrode and the drain on the back of the die as the other electrode This capacitance is fairly low due to the thickness of the non conducting die But when Vgd is positive the die is conducting and Cgd is physically based on a capacitor with the thickness of the gate oxide Traditionally elaborate subcircuits have been used to duplicate the behavior of a power MOSFET A new intrinsic spice device was written that encapsulates this behavior in the interest of compute speed reliability of convergence and simplicity of writing models The DC model is the same as a level 1 monolithic MOSFET except that the length and width default to one so that transconductance can be directly specified without scaling The AC model is as follows The gate source capacitance is taken as constant This was empirically found to be a good approximation for pow
169. ut current is given byloffset I by pi phi 18s0 The damping constant amp sin pi phi 180 Otherwise the current Ioffsett Iamp exp time Td Theta sin 2 pi Freq is given time Td factor Theta is the reciprocal of the decay time Td2 Tau2 Syntax Ixxx n n EXP I1 I2 Tdl Taul Time dependent Nam e Tdl Tau Td2 Tau 120 Description Initial value Pulsed value Rise delay time Rise time constant Fall delay time Fall time constant xponential current source Un it se se se se For times less than Tdl the output current is Il For times between Tdl and Td2 the current is given by 1 2 I1 1 exp time Td1 Tau1 For times after Td2 the current is given by 1 I2 I1 1 exp time Td1 Taul T1 12 1 exp time Td2 Tau2 Syntax Ixxx n n SFFM Ioff Iamp Fcar MDI Fsig Time dependent single frequency FM current source Nam Description Un e it s LOE DC offset A f Iam Amplitude A D Fca Carrier frequency Hz r MDI Modulation index Fsi Signal frequency Hz g The current is given by off amp sin 2 pi Fcar time MDI sin 2 pi F sig time 121 Syntax Txxx n n tbhl lt voltage current gt lt voltage GEES BE unas
170. vice Currents Check this so that you can plot device and terminal currents You will also need it to be able to plot dissipation SPICE This pane allows you to define the various defaults for LTspice These defaults can be overridden in any simulation by specifying the options in that simulation Usually you can leave these options as they are If you have frequently updated the program over the web you might want to press Reset to Default Values to reset to the current recommended settings Control Panel One default you may want to change is Trtol Most commercial SPICE programs default this to 7 In LTspice this defaults to 1 so that simulations using the SMPS macromodels are less likely to show any simulation artifacts in their waveforms Trtol more affects the timestep strategy than directly affects the accuracy of the simulation For transistor level simulations a value larger than 1 is usually a better overall solution You 177 might find that you get a speed of 2x if you increase trtol with out adversely affecting simulation accuracy Your trtol is remembered between program invocations However most of the traditional SPICE tolerance parameters gmin abstol reltol chgtol vntol are not remembered between program invocations If you want to use something other than the default values you will have to write a option statement specifying the values you want to use and place it on the schematic or keep t
171. w up correctly what can I do That problem should be completely fixed in the current version of LTspice IV But you can go to the menu item Tools gt Control Panel gt Netlist Options and check Convert ui to u This option now not only applies to netlists but will draw a Greek Mu as u wherever it might appear on the screen Program Updates How do I get the latest version Once installed there are two ways to getting the latest version You can always reinstall the program again as mentioned in Installation Problems You don t have to remove the old 184 version before installing If your PC has an internet connection it is easier to get the latest release by using the Sync_Release feature but not necessarily faster How do I know what new features are added After you have updated your file to the latest version the changelog txt file in your root directory usually at C Program Files LTC LTspicelIV Changelog txt has a detailed program revision list Can I go back to the old version after Sync_Release It is not reversible All symbols models and programs are updated with the new ones You need to make a backup copy before the Sync_Release starts The component databases standard will be merged with the new ones automatically If you added new inductors or capacitors your devices will be preserved and merged with the new ones from program update Your own local working f
172. y diode grading coefficient Body diode coefficient for forward bias depletion capacitance formula Body diode transit time Body diode O Inf in EX le 10M eg le 15 10n Xti KE Af ncha n pcha n Tnom x The model name V activation energy V for temperature effect on Is Body diode saturation current temperature exponent Length scaling Width scaling Flicker noise S coefficient Flicker noise exponent N channel VDMOS SS P channel VDMOS Parameter measurement C temperature P channel device The polarity defaults specify P channel flag the model with e g model xyz VDMOS Kp 3 pchan defines a P channel transistor ochan O Lossy Transmission Line Symbol Name LTLI Syntax Oxxx Li L Pi R lt model gt Example tr ue fa lse 27 50 DMOS is used both for a N channel and to N channel the keyword To 143 Ol in 0 out O MyLossyTline model MyLossyTline LTRA len 1 R 10 L 1lu C 10n This is a single conductor lossy transmission line N1 and N2 are the nodes at port 1 N3 and N4 are the nodes at port 2 A model card is required to define th lectrical characteristics of this circuit element Model parameters for Lossy Transmission Lines Name Description Units Typ Defa e ult R QO unit 0 len L H unit D len G 1 Q unit 0
173. you can select an object by clicking on it You can select multiple objects by dragging a box about them The program will stay in the move drag or delete mode until the right mouse button is clicked or the Esc key is pressed All schematic edits can be undone or redone Undo Undo the last command 15 Redo Redo the last Undo command Text Place text on the schematic This merely annota schematic with information This text has no elect impact on the circuit tes the trical SPICE Directive Place text on the schematic that will be included inthe netlist This lets you mix schematic capture with a SPICE netlist It lets you set simulation options include files that contain models define new models any other valid SPICE commands You can even use it or use to run a subcircuit that you don t have a symbol for by stating an instance of the model a SPICE command that begins with and X on the schematic and including the definition SPICE Analysis Enter edit the simulation command Resistor Place a new resistor on the schematic Capacitor Place a new capacitor on the schematic Inductor Place a new inductor on the schematic Diode Place a new diode on the schematic Component Place a new component on the schematic The command brings up a dialog that lets you browse and preview the symbol database This is a more general form of the Resistor

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