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1. ioe ee eee 2 eee Ee ee gt aes Figure 2 m41 s schematic 13 1996 Sep 27 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs Does Design architect Scher m i 2 11 ham warnings Cryer 1 TIE earning 2 DIT EI 1 t marndrne Dargis IKIT Properties raii sen d iin Tem aa feed Fle Figure 3 Electrical rules check results With the schematic open use the pull down menus from the Menu bar Check to ensure that there are no electrical rule violations 1996 Sep 27 14 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ANDES Figure 4 Generating a symbol After the schematic is checked without errors use the Menu bar to select Miscellaneous Generate Symbol and change the radio buttons in the dialog box to Replace Existing Save and Activare the symbol 1996 Sep 27 15 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs 59 Desten architect Sol T LI pedi warning hamiwa ey na D Errors Haminga Fig2. Mentor Graphics Design Flow for targeting Philips CPLDs MINC_PATH default pi cp MINC_PATH default cst mv default pi 1 pi mv default cst 1 cst make src 1 edf plcomp 1 src plsim 1 stm plopt 1 afb plscan 1 1 plfuse 1 pldoc 1 modgen 1 j1 pz3032 8 qfp44 vhdl Application note 59 This produces jedec file 1 j1 and a delay annotated vhdl model 1 The jedec file can be used to program a PZ3000 or PZ5000 series device This file can be read into Quickvhdl but there may be modifications to the toriginal testbench for a simulation Selecting a Philips CPLD The Philips CPLD used is specified in the lt design gt pi and lt design gt cst files This allows a user to direct PLDesigner to either target a specific device as the PZ3032 or to scan all devices and provide multiple solutions The use of these files is described in detail in Chapters 14 16 of the PLDesigner XL User s Guide To target the PZ3032 the following can be used lt design gt cst TEMPLATE XPLA32 32 XPLA64_64 lt design gt pi DEVICE TARGET TEMPLATE XPLA32_32 TQFP 44 P32 default END DEVICE Quicksim simulation steps From the lt design gt eddm lt design gt directory enter quicksim timing mode typ plds2 vpt File Open design sheet Select signals to be monitored in schematic Invoke Trace List 1 Depending on the pi file PLDesigner can partition a design acros
3. signal b std_logic_vector 5 downto 0 signal c std logic vector 5 downto 0 signal d std logic vector 5 downto 0 signal sel std logic vector 1 downto O signal z std logic vector 5 downto 0 signal vector cnt integer 1 signaltype test record is record 4 logic vector 5 downto 0 b std logic vector 5 downto 0 std_logic_vector 5 downto 0 std_logic_vector 5 downto 0 sel std_logic_vector 1 downto 0 z std_logic_vector 5 downto 0 end record type test_array is array positive range lt gt of test_record constant test_vectors test_array a b sel 2 000000 000111 111000 111111 00 000000 000000 000111 111000 111111 01 000111 000000 000111 111000 111111 10 111000 000000 000111 111000 111111 11 111111 begin dut m41 port map a gt a b gt b gt 1996 27 7 Application note 59 Philips Semiconductors Mentor Graphics Design Flow for targeting Philips CPLDs d gt d sel gt sel Z gt 7 testrun process variable vector test_record begin for index in test_vectors range loop vector cnt index vector test vectors index a vector a b vector b lt vector c d vector d S
4. 1 v1 gt opt area low gt opt area low opt area low DMAG library version 1 0 installed Creating new view mgc_operators eq_2u_2u_Zd6dc662 INTERFACE Creating new view mgc_operators eq_2u_2u_Z1fb8c43 INTERFACE Starting top level cell m41 v1 Optimizing v1 Netlist Count 1 of 1 Starting area optimization effort low factoring option factor original area litweight current area litweight top 0 890 gt 0 890 Starting combinational optimization original area litweight current area litweight top 0 890 gt 0 890 local 0 570 gt 0 570 End of combinational optimization original area litweight current area litweight top 0 890 gt 34000 320 local 0 570 gt 34000 0 End of area optimization effort low original area litweight current area litweight top 0 890 gt 34000 320 1996 Sep 27 11 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ees gt sav design eddm model m41 map eddm schematic This step produces alot of output and indicates that a schematic has been written gt quit f Invoke Design Architect steps by entering amp Figure 1 Opening a schematic in Design Architect Open the schemaitc by selecting Open Sheet in the palette window and selecting m41_s as shown 1996 Sep 27 12 Application note Philips Semiconductors 59 Mentor Graphics Design Flow for targeting Philips CPLDs i LI pp p dp
5. APPLICATION NOTE 59 Mentor Graphics Design Flow for targeting Philips CPLDs 1996 Sep 27 Philips PHILIPS Semiconductors LI D Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs dd INTRODUCTION The Programmable Logic Group of Philips Semiconductor is developing a family of advanced 3 volt and 5 volt complex programmable logic devices CPLDs The XPLA series designated as the PZ5000 5 volt and PZ3000 3 volt series devices is footprint compatible with the Altera 7000 series devices The principle advantage of Philips CPLDs over all existing CPLDs is that they consume zero static power The other advantages are 25 higher logic capacity and a better ability to fit logic with fixed pinouts The first devices the 32 macrocell PZ3032 and PZ5032 began sampling in Feb 1996 The 23064 25064 iand the PZ5128 PZ3128 are scheduled to sample in Q4 1996 The PZ5128 PZ3128 are in system programmable All devices all programmable on Data I O and BP Microsystems programmers Minc Inc has developed fitters for the PZ5000 PZ3000 series for up to 128 macrocells This allows workstation users to target Philips CPLDs within workstation environments The software is capable of automatically partitioning across multiple CPLDs Verilog and VHDL models are generated for timing simulation and post fit board level simulation This note provides scripts for using this capability The Min
6. c fitter can be used with most workstation flows which use VHDL or Verilog from Cadence Synopsys Mentor Graphics and Exemplar Logic It can be used with Composer and Concept schematic editors from Cadence and Design Architect from Mentor In this application note an example of a design flow for using Mentor Graphics softwarefor simulation and compilation of VHDL designs is given This flow can be used with minor edits for Verilog synthesis For additional information telephone Philips Applications Support at 888 coolpld or browse http www coolpld com The following documentation is available either through the web server or telephoning 888 coolpld PLDesigner XL User s Guide PLDSynthesis Il User s Manual PZ5000 PZ3000 Series Data Sheets DESIGN FLOWS The software needed to target Philips CPLDs is available from Mentor Graphics The software required depends on the design flow This software should be installed as provided in Chapter 1 in the PLDSII User s Manual In the steps listed below 1 is used to represent the design name and tbthe testbench name Generally there are a number of different methods to design using Mentor tools and scripts will usually vary based on the design Mentor Graphics may have access to different tools including Synthesis Autologic VHDL or Verilog Synopsys VHDL or Verilog Exemplar VHDL or Verilog Simulation Quicksim QuickVHDL This note provides a design flow for using the Autologic synt
7. complib ma Loading library export home2 mgc pkgs np any userware default gc util ma Loading file export home2 mgc pkgs syn any userware default lo m loading export home2 mgc pkgs np any userware default synrc m Copyright c Mentor Graphics Corporation 1990 1995 All Rights Reserved UNPUBLISHED LICENSED SOFTWARE CONFIDENTIAL AND PROPRIETARY INFORMATION PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS Loading Generic Technology loading export home2 mgc pkgs aui any userware default opt m Redefinition of function update all vhdl library browser Redefinition of function env INI Redefinition of function read vhdl gt gt opn design vhdl src m41 vhd opn design vhdl src m41 vhd 1996 Sep 27 9 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs alx hdl v8 4 1 22 Messages will be logged to file export home2 mgc tmp gn842537606 log Reading file export home2 mgc pkgs qvhdl libs data standard vhd Loading package STANDARD into library STD Reading root vhdl file src m41 vhd Reading file export home2 mgc pkgs qvhdl libs data std 1164 vhd Loading package STD LOGIC 1164 into library IEEE Loading entity M41 into library WORK Loading architecture V1 of M41 into library WORK Compiling root entity M41 V1 VHDL source successfully analyzed Loading MGC HOME lib autologic ini Warning Overwriting netlist mgc_op
8. el vector sel wait for 50 ns z 2 vector z then error flag lt 1 assert false report Output did not match else error flag lt 0 end if end loop wait end process end To begin the design flow from the project directory enter mkdir src cp lt path gt m41 vhd src cp path m41 tb vhd src Then create and map the llibrary qvlib work work lt path gt work 1996 Sep 27 8 Application note 59 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs mee Now compile the files qvcom src m41 vhd work work synth qvcom src m41 tb vhd work work synth Now start autologic for synthesis by entering alui nodisplay export home Iss designs mgc vhdl practice3 alui nodisplay This will cause the following to be displayed The Autologic session is given in the next three pages A prompt precedes user input Lines without a prompt are Autologic output AutoLogic Optimizer v8 4 3 2 Tue Jun 27 10 34 53 PDT 1995 Autologic idea license granted GENIE version 9 16 Loading library export home2 mgc pkgs se any userware default ipc ma Loading library export home2 mgc pkgs syn any userware default autologic ma Loading AutoLogic Timing Driven Layout Library Loading library export home2 mgc pkgs syn any userware default opt cli ma Loading library export home2 mgc pkgs syn any userware default
9. erators eq_2u_2u INTERFACE Warning Overwriting netlist mgc_work m41 v1 0 gt gt env dst gen lib env dst gen lib Loading Technology export home2 lib synlib gen lib gen lib Library Version 1 3 01Nov93 Loading Cell Definition bin celldef ma Loading Database export home2 lib synlib gen lib celldb Warning Cannot find auxiliary rules Consider creation of auxiliary rules using do aux rules lt gt 0 syn vhdl work m41 arch v1 Synthesizing alx hdl v8 4 1 22 Messages will be logged to file export home2 mgc tmp synth842537685 log Reading file export home2 mgc pkgs qvhdl libs data standard vhd Loading package STANDARD into library STD Reading file export home Iss designs mgc vhdl practice3 work m41 m41 alx vhd into library work Reading file export home2 mgc pkgs qvhdl libs data std 1164 vhd Loading package STD LOGIC 1164 into library IEEE Loading entity M41 into library work 1996 Sep 27 10 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ANUS Reading root vhdl file export home lIss designs mgc vhdl practice3 work m41 vi arch alx vhd Loading architecture V1 of M41 into library work Compiling root entity M41 V1 VHDL source successfully analyzed Loading MGC HOME lib autologic ini Warning Overwriting netlist mgc_operators eq_2u_2u INTERFACE Warning Overwriting netlist work m41 v1 netlist work m4
10. flow for a functional simulation in Quickvhdl is as follows Although recommended a test bench is not required 1996 Sep 27 3 Philips Semiconductors Mentor Graphics Design Flow for targeting Philips CPLDs qvcom 1_tb vhd work designs qvsim lib lt library gt lt entity gt File Load testbench view wave signals list Autologic steps To invoke Autologic to use the command line intrface enter alui nodisplay The autologic session will include the following steps opn design vhdl path src 1 vhd env dst gen lib syn vhdl library entity arch architecture opt area low sav design eddm model entity map library schematic quit f Design Architect steps To invoke Design Architect enter da amp The steps in Design Architect are open sheet in eddm check schematic generate and check symbol re open schematic export to pldsll produces src eddm design minc directory PLDSII steps Application note 59 Either the PLDesigner graphical user interface or a script can be used For use ot the PLDesigner GUI see the PLDesigner User Manual As of this writing Philips CPLDs are not released with PLDSII Below is a script for compiling to Philips CPLDs which requires release of only Philips device files These are available through Mentor Graphics To run the script enter minc script 1 The contents of minc script are 1996 Sep 27 4 Philips Semiconductors
11. hat such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 print code Date of release 07 98 Telephone 800 234 7381 Document order number 9397 750 04182 45 make things bette S PHILIPS
12. hesis tool The flow and examples for both Quicksim and QuickVHDL simulators are given 1996 Sep 27 2 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ANOS Synthesis using the Autologic Flow The steps given below do the following Setup environment Create library and compile VHDL source Synthesize using Autologic Open and check the schematic in Design Architect Generate and check the symbol Export to PDSII to generate a 1 src file Compile the edif file to a jedec file and produce a delay annotated VHDL model from the jedec file 8 69 19 25 Simulate using Quicksim or Quickvhdl To use Autologic for Philips CPLDs the mgc location map in the user s home or project directory should contain the following LOCATION MAP 2 Synlib MGC SYNLIB export home2 lib synlib tmp_mnt export home2 lib synlib MGC_GENLIB export home2 lib gen lib tmp mnt export home2 lib gen lib MINC PATH PLDS2_ SYN LIB The flow for Mentor tools is as follows broken down into Quickvhdl Autologic Design Architect PLDSII and Quicksim functions Quickvhdl steps mkdir src cp 1 vhd src export LOCATION MAP export home Iss designs mgc mgc location map qvlib work work lt project_directory gt work qvcom src 1 vhd work work synth In some cases testbenches do not compile with the synth option to the qvcom command The
13. s multiple devices so that 1 j1 1 j2 are produced 1996 Sep 27 5 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs 995 Generate Stimuli Run DESIGN FLOW EXAMPLE An example of a flow using Autologic Design Architect and either Quicksim II or the Quickvhdl simulator is given below The example is an 4 to 1 multiplexer of 6 bit busses The vhdl source is Philips CPLD Applications 6 bit 4 to 1 multiplexer August 20 1995 library ieee use ieee std logic 1164 all entity m41 is port a b c d in std logic vector 5 downto 0 sel in std logic vector 1 downto 0 z Ooutstd logic vector 5 downto 0 end m41 architecture v1 of m41 is begin z lt a when sel 00 else b when sel 01 else when sel 10 else d end v1 The testbench for Quickvhdl is Philips CPLD Applications m41 tb vhd 17 oct 1995 library ieee use ieee std logic 1164 all entity testbench is end architecture tb of testbench is component m41 1996 Sep 27 6 Philips Semiconductors Mentor Graphics Design Flow for targeting Philips CPLDs port a in std_logic_vector 5 downto 0 b in std_logic_vector 5 downto 0 c in std_logic_vector 5 downto 0 d in std_logic_vector 5 downto 0 sel in std_logic_vector 1 downto 0 z out std_logic_vector 5 downto 0 end component signal a std_logic_vector 5 downto 0
14. the palette menu enter Stimulus and provide the input stimuli Enter run 500 to a simulation 1996 Sep 27 20 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs Oe ma 11 eee Seip Aun Hep uu rt 1 AA 19 lum F Figure 10 Simulation results 1996 Sep 27 21 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ae Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty t
15. tten a src file which can be compiled to a Philips CPLD The PLDesigner GUI is shown in the lower part of the screen shot 1996 Sep 27 18 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ANUJ rf QuickSim Fie Edit Add Delete Setup Run Report View WF EDITOR 086 GATES ANALYZE RUN gt DELETE UNSELECT ALL WDB DEFAULTS Fo F10 ET F12 Windows Puldown Read Fil Pop Window Edit File Dlose windo F1 F2 F3 F4 F5 F6 Fr FS Elect Area Unselect All Hd Flag Popup Menu Add Probe View Selected Add Signal View Area Areallet Select F ilte s Add Keeps View All ume ear Select Filllbjectat Cursd Step Into Step Over e Open Up Open Down a Figure 8 Using Quicksim II To simulate with Quicksim enter quicksim timing mode typ plds2 vpt From the palette menu select Open Sheet Using the mouse elect the nets to monitor in the schematic Invoke Trace and List from the palette 1996 Sep 27 19 Philips Semiconductors Application note Mentor Graphics Design Flow for targeting Philips CPLDs ee Cm ires bm 11 Mun Pe Emi Pan Vm rel 8 iim mm ni 1 29 zl 2 5 n Figure 9 Schematic Trace and List windows displayed run simulation from
16. ure 5 Check the symbol Close the schematic upper right corner Use the palette to Open Symbol From the Menu bar check the symbol with default registration 1996 Sep 27 16 Philips Semiconductors Mentor Graphics Design Flow for targeting Philips CPLDs Design architect CM cea jes miiy Expert te PLES Parr irem Eu Be ene Doh hane gt red te DE Cancel Application note 59 ad nude CET CRS Canine aie Gary 1 lei as 2n A Der d Pores Cosas ares ee Temm Ch Ehan Figure 6 Export to PLDSII 1996 Sep 27 17 Philips Semiconductors Mentor Graphics Design Flow for targeting Philips CPLDs Design Archit Me Dep MmcrHanecum Libraries Gheck Amport wew mlda _ ume Aja de E Lopuriget SIBC nenrporaeces Loe Plows File Edit View Build Device A X F war Design File axparthemellzzidasigrurmgeivhelipraetico acidi md minem abus Ready Figure 7 Invoking plds2 Application note 59 Pre iig This shows that PLDSII ha successfully wri
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