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1. Log Results Components bertEngine1 properties class Bert Engine e TN continuous Duration 1000 BERT Setup en d le Shot Duration in bits 110 000 000 bertScan2520Mbps BERNIE single bertScan4960Mbps neChannelList Channel List 1 bertScan5040Mbps single Shot Length 1000000 globalClockConfig syncError Threshold 3 Phase Sweep Setup mChannelList 1 txChannelList 1 Stat Phase DO ps End Phase 20 pe continuous Duration duration in milliseconds for continuous BERT measurements Input Digital Signal Add Remove Test Procedure txphase_end 310 txphase step 10 Output BER Bathtub E22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22 22 2 2 2 2 2 2 22 2 2 2 2 2 2 2 2 22 2 2 2 22 22 2 2 2 2 2 22 2 22 2 2 2 22 22 2 22 AAA RA AAA set datarate to 2480Mbps globalClockConfig dataRate 2480 0 Setup data rate and source Tx pattern globalClockConfig setup txChannelListi setup a b Figure 9 Screen capture of Introspect ESP user environment Page 9 introspect technology SV1C Specifications Specifications Table 1 General Specifications Number of Differential Transmitters Number of Differential Receivers Number of Dedicated Clock Outputs Individually synthesized frequency and output format Number of Dedicated Clock Inputs 1 Used as external Reference Clock input Consult user manual for included capability Consult factory for c2. 32 Programmable in 3 steps Preliminary Programmable in 3 steps Preliminary Both high pass and low pass functions are available This is the smallest achievable range based on worst case conditions Typical operating conditions result in wider pre emphasis range Only high pass function is available This is the smallest achievable range based on worst case conditions Typical operating conditions result in wider pre emphasis range Both high pass and low pass functions are available This is the smallest achievable range based on worst case conditions Typical operating conditions result in wider pre emphasis range Random Jitter Noise Floor 700 fs Based on measurement with high bandwidth scope and with first order clock recovery Minimum Frequency of Injected 0 1 kHz Consult factory for further customization Deterministic Jitter Maximum Frequency of Injected 80 MHz Deterministic Jitter Frequency Resolution of Injected 0 1 kHz Consult frequency for further customization Deterministic Jitter Maximum Peak to Peak Injected 8 Ul Deterministic Jitter Magnitude Resolution of Injected 500 fs Jitter injection is based on multi resolution synthesizer Deterministic Jitter so this number is an effective resolution Internal synthesizer resolution is defined in equivalent number of bits Injected Deterministic Jitter Setting Common Common across all channels within a bank Maximum Random Jitter Injection 0 5 Ul Magni
3. of electrical optical media such as e Backplane e Cable e CFP MSA SFP MSA SFP MSA Plug and play system level validation such as e PCI Express e DisplayPort sink source e MIPIM PHY Timing verification e PLL transfer function measurement e Clock recovery bandwidth verification e Frequency ppm offset characterization Mixed technology applications e High speed ADC and DAC J ESD204 data capture and or synthesis e FPGA based system development e Channel and device emulation e Clock recovery triggering for external oscilloscope or BERT equipment Page 3 introspect technology SVIC Introduction and Features Features Multi Lane Loopback The SVIC is the only bench top tool that offers instrument grade loopback capability on all differential lanes The loopback capability of the SV1C includes e Retiming of data for the purpose of decoupling DUT receiver performance from DUT transmitter performance e Arbitrary jitter or voltage swing control on loopback data Figure 1 shows two common loopback configurations that can be used with the SVIC In the first configuration a single DUT s transmitter and receiver channels are connected together through the SVIC In the second configuration arbitrary pattern testing can be performed on an end to end communications link The SVIC is used to pass data through from a traffic generator such as an end point on a real system board to the DUT while stressing the DUT rece
4. Introspect technology 1 2 3 4 5 b 7 8 SVIC Personalized SerDes Tester Data Sheet N introspect NA technology SV1C Personalized SerDes Tester Data Sheet Revision 1 0 2013 02 27 Revision Revision History Date 1 0 Document release Feb 27 2013 The information in this document is subject to change without notice and should not be construed as acommitment by Introspect Technology While reasonable precautions have been taken Introspect Technology assumes no responsibility for any errors that may appear in this document No part of this document may be reproduced in any form or by any means without the prior written consent of Introspect Technology Product SVIC Personalized SerDes Tester Status Released Copyright 2013 Introspect Technology ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without ST 3 detection Permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality inGrospecG technology Table of Contents Table of Contents an bg CR Rs A 2 EN id ii e pa ina ied ic an a E DO Roa 2 A E A 3 AAA IRI A A NR SAR RR 4 Multi Lane Loopback ccccceessseecccceccsecccceccesececccssceeseesceeceeseeececsecesseeccceeu
5. able 6 Table 7 Table 8 SV1C Introduction and Features List of Tables General OCT ONS AAA ennai 10 iii o ia eee ee A 11 Receiver Characteristics PER NE EB MIRO NE E NR AR PR PR PRR N 12 Clocking Characteristics rinda din ai 13 Pattern Handling Characteristics sssssscccccccssssssssssccccccsseeeesssscccessseeeeessees 14 Measurement and Throughput Characteristics oooooooonccnnnnnnnnnnononanonnnnnnnnss 15 LUCRO OIDO IES orar iets 16 DIRE e AAA AA 16 Page 1 inGrospecG Overview Key Benefits SV1C Introduction and Features Introduction The SVIC Personalized SerDes Tester is an ultra portable high performance instrument that creates a new category of tool for high speed digital product engineering teams It integrates multiple technologies in order to enable the self contained test and measurement of complex SerDes interfaces such as PCI Express Gen 3 DisplayPort Thunderbolt or MIPI M PHY Coupled with a seamless easy to use development environment this tool enables product engineers with widely varying skill sets to efficiently work with and develop SerDes verification algorithms The SVIC fits in one hand and contains 8 independent stimulus generation ports 8 independent capture and measurement ports and various clocking synchronization and lane expansion capabilities It has been designed specifically to address the growing need of a parallel system oriented test methodology while offerin
6. cy Mismatch 0 Preset Patterns Standard Built In Patterns All Zeros D21 5 K28 5 K28 7 DIV 16 DIV 20 DIV 40 DIV 50 PRBS 5 PRBS 7 PRBS 9 PRBS 11 PRBS 13 PRBS 15 PRBS 21 PRBS 23 PRBS 31 Per transmitter Maintained across cascaded modules Pattern Choice per Transmit Channel Pattern Choice per Receive Channel Per receiver Automatic seed generation for PRBS BERT Comparison Mode Automatically aligns to PRBS data patterns User programmable Pattern Memory Total Available Memory Individual Force Pattern Individual Expected Pattern Minimum Pattern Segment Size Maximum Pattern Segment Size Total Memory Space for Transmitters Total Expected Memory Space for Receivers Pattern Sequencing Sequence Control Number of Sequencer Slots per Pattern Generator Maximum Loop Count per Sequencer Slot 2 Per transmitter Per receiver 512 65536 2097152 2097152 Loop infinite Loop on count Play to end Memory allocation is customizable Consult factory Memory allocation is customizable Consult factory Memory allocation is customizable Consult factory This refers to the number of sequencer slots that can operate at any given time The instrument has storage space for 16 different sequencer programs Page 14 introspect Additional Pattern Characteristics Pattern Switching Wait to end of segment Immediate Raw Data Capture Length 8192 SV1C Specifications When sourci
7. eneesceesees 4 MU AS Source iier MECHO ua sana om a nm e a e ne e i a e ni 4 Pre Emphasis Generation cccsseccccccccssececccceccsseecccsecesseescccseeessecsccseceseecccsseeeesessess 6 Per Lane otk ROO MAA 7 al a a RA PP T 7 A e e PR OS E idila aa RER 8 e NR n RR NR ORE CSR MN IP OR RI IRI ENDRE IN NR 9 TE PA A LEO II RA RR PR RR RPR OR RN INN RN AI IRI OARA ART 10 List of Figures Figure 1 Illustration of loopback applicCationsS cocoooooonnccnnnnnnnonononanonnnnnnnnnnnnonaninonoss 4 Figure 2 Illustration of calibrated jitter waveform ccccccccccececccseeeeeeesssseeceeceeeeeeees 5 Figure 3 Illustration of jitter tolerance CUIVE ssccccececccccccccceseecccesssssessssececceccees 5 Figure 4 Illustration of pre emphasis design oocccccncccnonnocnnnnnnnnnnnnnananononcnnnnnononaninonos 6 Figure5 Illustration of multiple waveform shapes that can be synthesized using the pre emphasis function Of the SVIC ooonncnnnnnnnnoccnnnncnonacocnnononnnaconononananosos 6 Figure 6 Illustration of per lane clock recovery circuit cccececccceeeceeeeeeeeeeesssseeeeeees 7 Figure 7 Photograph of the auxiliary control port on the SVIC nen 7 Figure 8 Sampling of analysis and report Windows eee eee 8 Figure 9 Screen capture of Introspect ESP user environment ooonnnnccccncnnnnnnnnnnnnnnnnnnonos 9 inGrospecG Table 1 Table 2 Table 3 Table 4 Table 5 T
8. enerator Performance Resolution at Maximum Data Rate 31 25 Resolution as a percentage of Ul improves for lower data rate Consult factory Differential Non Linearity Error 0 5 Integral Non Linearity Error 5 Range Unlimited Lane to Lane Skew Measurement Accuracy Table 4 Clocking Characteristics Internal Time Base Number of Internal Frequency 2 Relevant for future customization References Embedded Clock Applications Transmit Timing Modes System Extracted Clock can be extracted from one data receive channels in order to drive all transmitter channels Receive Timing Modes System Extracted All channels have clock recovery for extracted mode operation Lane to Lane Tracking Bandwidth Single Lane CDR Tracking Bandwidth Maximum native CDR bandwidth of individual receiver channels Forwarded Clock Applications Transmit Timing Modes System Forwarded Channel 1 acts as forwarded clock samplers Receive Timing Modes System Forwarded Channel 1 acts as forwarded clock samplers Clock Tracking Bandwidth 4 Second order critically damped response Spread Spectrum Support Receive Lanes Track SSC Data Requires operation in extracted clock mode Transmit Lanes Generate SSC Data Consult factory for availability Generated SSC Down Spread Spreading Frequency Page 13 introspect technology SV1C Specifications Table 5 Pattern Handling Characteristics Loopback Rx to Tx Loopback Capability Per channel Lane to Lane Laten
9. eration Conventionally offered as a separate instrument per lane pre emphasis control is integrated on the 8 lane SVIC tester The user can individually set the transmitter pre emphasis using a built in Tap structure Pre emphasis allows the user to optimize signal characteristics at the DUT input pins Fach transmitter in the SVIC implements a discrete time linear equalizer as part of the driver circuit An illustration of such equalizer is shown in Figure 4 and sample synthesized waveform shapes are shown in Figure 5 Pre Tap 1 Figure 4 Illustration of pre emphasis design Figure 5 Illustration of multiple waveform shapes that can be synthesized using the pre emphasis function of the SV1C Page 6 inGrospec technology SVIC Introduction and Features Per Lane Clock Recovery Like pre emphasis conventional tools often require separate clock recovery instrumentation In the SVIC each receiver has its own embedded analog clock recovery circuit Additionally the clock recovery is integrated directly inside the receiver s high speed sampler thus offering the lowest possible sampling latency in the industry The user does not have to make special connections or carefully match cable lengths The integrated nature of the SVIC clock recovery helps achieve wide tracking bandwidth for measuring signals that possess spread spectrum clocking or very high amplitude wander Figure 6 shows a block diagram of
10. g world class signal integrity features such as jitter injection and jitter measurement With a small form factor an extensive signal integrity feature set and an exceptionally powerful software development environment the SV1C is not only suitable for signal integrity verification engineers that perform traditional characterization tasks but it is also ideal for FPGA developers and software developers who need rapid turnaround signal verification tools or hardware software interoperability confirmation tools The SV1C integrates state of the art functions such as digital data capture bit error rate measurement clock recovery jitter decomposition and jitter generation True parallel bit error rate measurement across 8 lanes Fully synthesized integrated jitter injection on all lanes Fully automated integrated jitter testing on all lanes Optimized pattern generator rise time for receiver stress test applications Flexible loopback support per lane e Clock recovery per lane e State of the art programming environment based on the highly intuitive Python language e Integrated device control through SPI 12C or J TAG e Reconfigurable protocol customization on request Page 2 inGrospecG Applications SV1C Introduction and Features Parallel PHY validation of serial bus standards such as e PCI Express PCle e HDMI e DisplayPort DP e Thunderbolt e MIPI M PHY e XAUI e CPRI e SRIO e USB3 0 e SATA Interface test
11. iver with jitter skew or voltage swing Traffic Generator a b Figure 1 Illustration of loopback applications Multiple Source Jitter Injection The SVIC is capable of generating calibrated jitter stress on any data pattern and any output lane configuration Sinusoidal jitter injection is calibrated in the time and frequency domain in order to generate high purity stimulus signals as shown in Figure 2 Page 4 introspect SV1C Introduction and Features Injected Jitter ps Time ns Figure 2 Illustration of calibrated jitter waveform The jitter injection feature is typically exploited in order to perform automated jitter tolerance testing as shown in the example in Figure 3 As is the case for other features in the SV1C Personalized SerDes Tester jitter tolerance testing happens in parallel across all lanes For advanced applications the SVIC also includes RJ injection and a third source arbitrary waveform jitter synthesizer Introspect ESP ShmooBertViewer ES Color Mapping ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 ch 8 Min 0 E va 5000 MinValue 0 MaxValue 751485 400 5000 4500 4000 3500 3000 2500 Jitter Amplitude ps 5 o Error Count 2000 200 15001 150 10001 100 N w 6 7 8 9 10 Jitter Frequency MHz Figure 3 Illustration of jitter tolerance curve Page 5 inGrospecG technology SVIC Introduction and Features Pre Emphasis Gen
12. ng PRBS patterns this option does not exist Table 6 Measurement and Throughput Characteristics BERT Sync Alignment Alignment Modes Pattern PRBS Minimum SYNC Error Threshold 3 Maximum SYNC Error Threshold 4294967295 Minimum SYNC Sample Count 1024 Maximum SYNC Sample Count 2 SYNC Time 20 Error Counter Size 32 17179869184 Continuous Duration Indefinite Maximum Single Shot Duration CDR Lock Time Self Alignment Time Test Sequences Total Jitter Measurement Time Single Point Pass Fail Jitter Test Time DUT Transmit Skew Test Time DUT 6 Point Mask Test Time Time to Change Jitter Parameters Time to Change Data Rate Module can align to any user pattern or preset pattern Assumes a PRBS7 pattern that is stored in a user pattern segment and worst case misalignment between DUT pattern and expected pattern data rate is 3 25 Gbps Sample counts in the BERT are programmed in increments of 32 bits This includes measurement time and processing time to extract jitter values on eight simultaneous lanes The extraction algorithm is based on Q scale analysis Data rate is 3 25 Gbps Assumes a BERT SYNC has already been performed This test sets the Rx phase generators in the middle of the eye and performs a BERT measurement Data rate is 3 25 Gbps Assumes a BERT SYNC has been performed This test divides the DUT Ul into 16 intervals for the purpose of skew measurement Data is post processed in the tes
13. ptions are executed in parallel on all activated lanes OL PA der toga f OV1E00 GPI Bersconvemer M we gt gt mti a None RJ ps DJ pa Ti le 12 Estimated BER Eye Carter pa Channel 3 n 142 6587 1 y a Bathtub Plot DIRA DADA AA ERA eee AR AE eee A A Voltage mv BER e 1600 GR Eyebcanibewer A Eye Heeght m Eye Width pa ENTO 586 0 foe Dag BEA al GER Contour Eye Diagram Channel 3 Figure 8 Sampling of analysis and report windows Page 8 inGrospecG technology SV1C Introduction and Features Automation The SVIC is operated using the award winning Introspect ESP Software It features a comprehensive scripting language with an intuitive component based design as shown in the screen shot in Figure 9 a Component based design is Introspect ESP s way of organizing the flexibility of the instrument in a manner that allows for easy program development It highlights to the user only the parameters that are needed for any given task thus allowing program execution in a matter of minutes For further help the SV1C features automatic code generation for common tasks such as Eye Diagram or Bathtub Curve generation as shown in Figure 9 b pa DV1600 GPI test RXTG bathtub e E RS File Edit DV1600 Wizards Help y DV1600 GP BERT Scan Wizard Untitied DFT microsystems
14. t system software Data rate is 3 25 Gbps Assumes a BERT SYNC has been performed This test programs the six mask locations and performs a 1 shot BERT at each location Data rate is 3 25 Gbps Page 15 introspect vechnology SV1C Specifications Table 7 Instruction Sequence Cache Advanced Instruction Cache Local Instruction Storage 1M Instructions Instruction Sequence Segments 1000 Simple Instruction Cache Instruction Learn mode Instruction Table 8 DUT Control Capabilities Parameter Value DUT IEEE 1149 1 JTAG Port Option JTAG Port Transmit Signals JTAG Port Receive Signals JTAG Port Transmit Voltage Swing V Fixed JTAG Port Receive Max Voltage Swing V TDI Bit Memory TDO Bit Memory Description and Conditions DUT SPI Port Option SPI Signals Voltage Swing Fixed Page 16 Introspect technology Introspect Technology 195 Labrosse Avenue Pointe Claire Quebec Canada H9R 1A3 http introspect ca
15. the clock recovery capability inside the SV1C Personalized SerDes Tester ES Channel DSP i amp Analysis Logic Figure 6 Illustration of per lane clock recovery circuit Auxiliary Control Port The SVIC includes a low speed auxiliary control port that is based on a standard SCSI connector Figure 7 This port enables controlling DUT registers through J TAG I2C or SPI Additionally the port includes reconfigurable trigger and flag capability for synchronizing the SV1C with external tools or events Figure 7 Photograph of the auxiliary control port on the SVIC Page inGrospecG technology SVIC Introduction and Features Analysis The SV1C instrument has an independent Bit Error Rate Tester BERT for each of its input channels Each BERT compares recovered retimed data from a single input channel against a specified data pattern and reports the bit error count Apart from error counting the instrument offers a wide range of measurement and analysis features including e Jitter separation e Eye mask testing e Voltage level pre emphasis level and signal parameter measurement e Frequency measurement and SSC profile extraction Figure 8 illustrates a few of the analysis and reporting features of the SVIC Starting from the top left and moving in a clock wise manner the figure illustrates bathtub acquisition and analysis waveform capture raw data viewing and eye diagram plotting As always these analysis o
16. tude Resolution of Injected Jitter 1 ps This is the equivalent peak to peak number for the injected Gaussian signal Page 11 introspect technology SV1C Specifications Accuracy of Injected Jitter Magnitude larger of 4 PS of programmed value and 4 ps Injected Random Jitter Setting Common Common across all channels within a bank Transmitter to Transmitter Skew Performance Lane to Lane Integer Ul Minimum Skew Lane to Lane Integer Ul Maximum Skew Effect of Skew Adjustment on Jitter Injection Maximum Lane to Lane Skew Table 3 Receiver Characteristics o Parameter Value Units Description and Conditions Description and Conditions and Conditions Input A E AC Input Differential Impedance AC Performance Minimum Detectable Differential Voltage Maximum Allowable Differential Voltage Minimum Programmable Comparator Threshold Voltage Maximum Programmable Comparator Threshold Voltage Differential Comparator Threshold 10 Voltage Resolution Differential Comparator Threshold larger of 1 5 Voltage Accuracy of programmed value and 5mV Resolution Enhancement amp Equalization DC Gain CTLE Maximum Gain CTLE Resolution DC Gain Control Per receiver Equalization Control Per receiver Jitter Performance Input Jitter Noise Floor in System Reference Mode Input Jitter Noise Floor in Extracted Clock Mode Page 12 introspect technology SV1C Specifications Timing G
17. ustomization Number of Trigger Input Pins Multiple Consult user manual for included capability Consult factory for customization Number of Flag Output Pins Multiple Data Rates and Frequencies Minimum Programmable Data Rate Mbps Maximum Programmable Data Rate Gbps Maximum Data Rate Purchase Options Gbps Gbps Gbps Data Rate Field Upgrade Contact factory Frequency Resolution of Programmed kHz Finer resolution is possible Consult factory for Data Rate customization Minimum External Input Clock MHz Frequency Maximum External Input Clock MHz Frequency Minimum Output Clock Frequency MHz Maximum Output Clock Frequency MHz Output Clock Frequency Resolution ppm Consult factory for further customization Page 10 introspect vechnology SV1C Specifications Table 2 Transmitter Characteristics Output Coupling AC Output Differential Impedance 100 Ohm Voltage Performance Minimum Differential Voltage Swing Maximum Differential Voltage Swing Differential Voltage Swing Resolution Accuracy of Differential Voltage Swing Rise and Fall Time Pre emphasis Performance Pre Emphasis Pre Tap Range Pre Emphasis Pre Tap Resolution Pre Emphasis Post1 Tap Range Pre Emphasis Post1 Tap Resolution Pre Emphasis Post2 Tap Range Pre Emphasis Post2 Tap Resolution Jitter Performance 20 1260 20 larger of 1 5 of programmed value and 5mV 30 60 90 Range 32 Oto 6 Range 32 4 to 4 Range
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