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1. is used as a part of typefile S Simulates and writes simulation results into file with filename supplied Simulation results are just a set of strings like the following 0000000000000100 0 000122 0000000000101000 0 001221 1111111111001000 0 001709 0000001000000000 0 015625 0000000110010000 0 012207 0000001100101000 0 024658 0000001000110000 0 017090 0001010101011100 0 166870 1101110010111000 0 275635 0000011101110000 0 058105 1111110111100000 0 016602 1111111111000000 0 001953 67 Results are provided both in 2 s compliment binary notation and in decimal floating point form to simplify comparing with VHDL simulation in VSIM or other HDL simulator and design information 68 FI LINK PING UNIVERSITY A ELECTRONIC PRESS 2 kd T P svenska Detta dokument h lls tillg ngligt p Internet eller dess framtida ers ttare under en l ngre tid fr n publiceringsdatum under f ruts ttning att inga extra ordin ra omst ndigheter uppst r Tillg ng till dokumentet inneb r tillst nd f r var och en att l sa ladda ner skriva ut enstaka kopior f r enskilt bruk och att anv nda det of r ndrat f r ickekommersiell forskning och f r undervisning verf ring av upphovsr tten vid en senare tidpunkt kan inte upph va detta tillst nd All annan anv ndning av dokumentet kr ver upphovsmannens medgivande F r att garantera ktheten s kerheten och tillg ngligheten finns det l sningar av tekn2. The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost The creating VHDL generator of Farrow based structure to speed up the design process is the main task of this work The suitable design technique which is the most important thing in any design work is presented in the report as well The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB The source code is attached to the report And some results from tests of the implemented scheme Nyckelord Keyword VHDL code generator digital filter ajustable delay Farrow sampling rate converter Abstract In different applications in digital domain it is necessary to change the sampling rate by an arbitrary number For an example Software Radio which should handle different conversion factors and standards This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost The creating VHDL generator of Farrow based structure to speed up the design process is the main task of this work The suitable design technique which is the most important thing in any design work is presented in the report as well The scheme which is considered to be suitable is created by VHDL gene
3. IVN ll lt s 1 n N a X b x ey 8 14 n D N lt ll lt s The block diagram of the filter presented in Figure 4 shows the structure with 5 sampling sections Filter Filter Filter Filter Filter Y1 Y2 Y3 Y4 Y5 b Figure 4 The structure a no block structure b block structure Kernel with block structure is the modification of the kernel without block structure Changing coefficients of multiplication e allows changing the ratio of sampling rate conversion The proposed Kernel of the general form is a X b xe 0 lt Ixl lt 1 N a X b xc n DN lt Ixl lt 1 ela x b xc Q x bl lt 1 1 N g x 2 eas 0 bsc ess 1 N I N lt Ixl lt 2 alas b te s 1 n 1 N x bd lt s I n N es aux bo xt eoa S 1 N IY N lt Ixl lt S To produce a useful filter from the proposed general form some restrictions to equation 2 should be applied 1 g x Z for x 0 2 g x g for x n N 3 g x 0 for x s 4 Co continuous The design problem is to find coefficients e Figure 4 b quadratic coefficients a and g which satisfy the equation mo Se S GGT cos ioT 8 W 0 D O 9 i Where L is a number of evaluation points in one sampling section T 1 L W o is weighting function D is ideal frequency characteristic and 6 is the maximum allowable approximation error When the difference between 6 and 8 is less than 10 the filter can be
4. assurance that implemented schematic is correct or not The mathematical model looks like the following consider f is a matrix containing the FAD filters coefficients i is a time instance within time period when FAD impulse response is at output i 1 max length delay for k 1 m where m is anumber of FAD stages length number of stages for filter number k delay delay value before the filter number k j is a filter number being considered j 1 m Matrix composition rule column j is the list ofthe filter 7 coefficients The list starts from the row number delay 45 m 2 m F GC fir ci fs as fs Ile fa Te fin where F is the response value at i th time instance i 1 max length delay for k 1 m To achieve the full accordance with VHDL model generated it is necessary that rounding is introduced into the model in a way as it is performed in generated FAD Thus the simulation algorithm is the following 1 Build the f matrix according to the matrix composition rule above The important think is that all the coefficients are rounded to the number of bits as implied by specification 2 Loop for i 1 N N max length delay 2 1 multiplicand fij fi 2 2 Loop for j 3 M 1 M is number of stages 2 2 1 multiplicand round multiplicand o fjj 2 3 F round multiplicand fiy The result is a vector F Simulation can be also useful during parameters selection and adjustment fo
5. inputs ys yc two independent channel outputs with required width I channel entity rounder lt num of chan inp width gt x lt out width is port inpl in std logic vector 16 downto 0 ys out std logic vector 15 downto 0 end rounder num of chan inp width gt x lt out width I channel quantizer has the same name convention and interface as the 2 channel one 58 FIR filter entity connect name is port indata in std logic array delay name yc ys out std logic vector 21 1 downto 0 clk in std logic end connect name Component file name includes name of a filter specified in the configuration file indata filter input in special format STD LOGIC ARRAY DELAY FILI IS ARRAY DOWNTO 0 OF STD LOGIC VECTOR DOWNTO 0 In fact it is the array of buses ys yc filter outputs clk clock signal meaningful if only tree is divided by pipeline registers Delay chain entity delay chain convertor name 0 is port a in std logic vector 12 1 downto 0 y outstd logic array commondelay fedor clk in std logic end delay chain name 0 a input signal in parallel code y output array containing input signal values delayed from 0 to maximum possible value Output type looks like the following STD LOGIC ARRAY COMMONDELAY FEDOR IS ARRAY lt gt DOWNTO 0 OF STD LOGIC VECTOR lt gt DOWNTO 0 clk clock signal at wh
6. the interaction with a user It gets initial data supplied in some certain format in configuration file in our case and transforms them into the internal representation Calculating core performs all the necessary tool functionality and generates the output Simulator provides the mathematical model of the generated schematic and makes possible the comparison between the mathematical simulation and VHDL level simulation The identity of the results from these two types of simulations guarantees at certain level of reliability that produced VHDL level model is equal to the signal flow graph SFG required Simulation results are real decimal and binary representation of a simulator output given to the user via terminal console or with another type of interface Generated output is the set of VHDL files representing the desired structure It has been already mentioned that the simulator provides mathematical model of the desired schematic When certain test vector is applied to the input it might be a single impulse that is the case here 21 22 only certain output sequence is expected The equality between mathematical simulation and VHDL modeling guarantee that the equal transformation has been obtained and hence the current realization is correct Simulation can be performed in different ways e System level modeling in Simulink Ptolemy and in similar frameworks e Mathematical model in MATLAB Mathcad Excel etc e Integ
7. together with special language means Thus developer obtain hierarchical structure of his project The FAD being designed can be hierarchically split in the following way Figure 25 Detailed input output description for each component in realization is presented in Appendix A 34 Converter Delay chain FIR filter Quantizer Multiplier CLA 4 input adder Shift generator Adder tree Shift generator Adder tree CLA CLA sert tipple Carry generator FA carry adder Figure 25 FAD VHDL level hierarchical diagram CSA CLA 35 3 6 Generator C code structure Software VHDL component code generation is a process when target file is created the necessary component functionality is put into it obeying correct VHDL program structure The standard C file input output procedures are used to achieve this aim FAD code generator tool is built according to the system approach as a set of independent loosely coupled procedures This approach implies that each procedure can be written and debugged with individual test bench The final program consists of a set of several files modules Each file contains one or several procedures that intended for either certain component generatio
8. D n D n D v Y v Y H z H z Hs z Hm 2 v Y v Q q QU Q q aan M Adm E EN alaan gt Output Figure 11 SFG for FAD Input information is applied with signed parallel code Output sequence produced by a FAD has also signed parallel representation Input bus is connected to the set of delay chains There can be arbitrary delay before the input information reaches a filter in each stage 23 We used the following shortening symbols for the delay chain Figure 12 and for FIR filter Figure 13 in this schematic 1 gt D O D D D D Jes D gt We n Figure 12 Delay chain 2 Filters denoted as H are linear phase FIR filters N M gt H gt 0 VY N D D D D D Figure 13 FIR filter M Output bus width depends on the input bus width and on the maximum coefficient length 3 Quantizers Q q manage with internal bit width They can be used either for intermediate rounding truncation or for bus width extension according to the specification It will be carefully discussed below 4 Multipliers perform the multiplication of the input value by the fixed coefficients 24 3 3 3 Prerequisites definition The given structure implies that the following input information must be provided by a user 1 Number of sections of FAD 2 Input word l
9. Design and Implementation of Sampling Rate Converters for Conversions between Arbitrary Sampling Rates by Fedor Merkelov Yaroslav Kodess LiTH ISY EX 3520 2004 Link ping 2004 Design and Implementation of Sampling Rate Converters for Conversions Between Arbitrary Sampling Rates by Fedor Merkelov Yaroslav Kodess LiTH ISY EX 3520 2004 Supervisor H kan Johansson Examiner H kan Johansson Link ping 26 of March 2004 Avdelning Institution Datum Division Department Date 2004 03 26 Institutionen f r systemteknik 7 P V x Vers UND LINK PINGS UNIVERSITET 581 83 LINK PING Spr k Rapporttyp ISBN Language Report category Svenska Swedish Licentiatavhandling ISRN LITH ISY EX 3520 2004 X Engelska English X Examensarbete C uppsats Serietitel och serienummer D uppsats Title of series numbering vrig rapport URL f r elektronisk version http www ep liu se exjobb isy 2004 3520 Design and Implementation of Sampling Rate Converters for Conversions between Arbitrary Sampling Rates F rfattare Fedor Merkelov Yaroslav Kodess Author Sammanfattning Abstract In different applications in digital domain it is necessary to change the sampling rate by an arbitrary number For example Software Radio which should handle different conversion factors and standards This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates
10. a FIR filter with the found transfer function Otherwise an order and coefficients recalculation 1s needed An advantage of the digital kernel technique is that there is no necessity to redesign filter whenever the sampling rate is changed Another advantage is that the kernel obtained is easy to implement The disadvantage of this method is high computational complexity This is because of the large number of quadratic functions which are needed to obtain a high attenuation in the stopband Another implementation of sample rate converter is based on the Farrow structure Some modifications that can be produced to achieve low area and efficiency of it according to Djordje Babic Jussi Vesma Tapio Saramuki and Markku Renfors from Nokia and Tampere Universitet of Technology Finland 3 Firstly it is modified Farrow structure shown in Figure 5 that has fixed filter coefficients as a benefit The only changeable parameter is the fractional interval u u KR KR Where R is the decimation factor co N 2 cn N 2 1 c N 2 1 co N 2 1 V n 2u 1 Figure 5 Modified Farrow structure The output samples are N 1 v 1 N N k k x n gt em A 0 of the m 1 FIR filters Where m is the quantity of the filters c is multiplication coefficient Each of the FIR filter has the transfer function N 1 C z Ye k N 2 z k 0 Where N is the parametrical coefficient Structure in the Figu
11. as well 56 inl in3 are input of adder outs outc outputs Four input adder entity FourXAdd name 0 is port inl in std logic vector 30 downto 0 in2 in std logic vector 30 downto 0 in3 in std logic vector 30 downto 0 ind in std logic vector 30 downto 0 ys out std logic vector 31 downto 0 yc out std logic end FourXAdd name 0 This is an adder which produces sum for four items inl in4 are inputs of adder ys yc result of the addition Multiplier entity mul convertor name 0 is port indata in std logic vector 21 downto 0 ys out std logic vector 30 downto 0 yc out std logic vector 30 downto 0 clk in std logic end mul lt convertor name 0 indata number in parallel cod to be multiplied by fixed coefficient ys yc output result and carry signal Quantizer 2 channel entity rounder lt num of chan inp width gt x lt out width is port inpl in std logic vector 13 downto 0 inp2 in std logic vector 13 downto 0 ys out std logic vector 12 downto 0 yc out std logic vector 12 downto 0 end rounder lt num of chan inp width gt x lt out width Number of channels is included in component name and the flle name as well It affects the interface as well as the 57 functionality File name also built from the input buses width and the output width required by the specification inpl inp2 two independent channel
12. ded SFG Figure 14 FAD SFG part and its expansion It is evident that having individual delay lines for each filter and for prefilter delays is redundant SFG hence can be reduced by introducing the single common delay chain Figure 15 26 Delay line H z H 2 Haz Where IT gt p D xs Lis zi M Figure 15 Introducing the common delay line Here M max n k for i 1 m where n length of the i th filter predelay k number of i th filter internal delays m number of stages of FAD Now each filter loses its own delay chain and gets appropriately delayed samples from the common one b Multipliers simplification There exist many types of parallel multipliers Although this structure is quite regular from the implementational point of view it is very large But often it can be simplified for example if fixed coefficients are used like in our case 27 General view of multiplier block schematic is shown in Figure 16 Multiplicand Partial product generator PPG Adder tree AT Y Y Carry lookahead adder CLA Product Figure 16 General block schematic of parallel multiplier Number of partial product is equal to number of nonzero elements binary ones in binary representation of a coefficient It can be reduc
13. djustable fractional delay filter eese 14 Figure 9 Block definition of FAD nn ae eK 20 Figure 10 Generator system level block diagram neen 21 Figure TL SEG for FAD un save 23 Figure 12 Delay O a E 24 Figure BARE Anena e a TEE 24 Figure 14 FAD SFG part and its expansion esee 26 Figure 15 Introducing the common delay line sess 27 Figure 16 General block schematic of parallel multiplier 28 Figure 17 6 input adder tree example dia 28 Figure 18 FAD fragment with expanded FIR filters 29 Figure 19 FAD fragment with joined adder tree sss 29 Figure 20 Simplified and adapted FAD block schematic 31 Figure 21 Block schematic of a 4 input adder sroronrnonrnonrnonrnrnnnnrnvnenrnrnrnenrnennne 32 Figure 22 Quantizer Rounding sen an 33 Figure 23 Quantizer Extension Case eese eee eene entente ean een terne tate 33 Figure 24 Ouantizer Pass through case asus 33 Figure 25 FAD VHDL level hierarchical diagram sess 35 Figure 26 Tool block schmal 37 Figure 27 Design Example Structure dada 43 Figure 28 Design Example Impulse response 44 viii 1 Introduction 1 1 Background Now the video and audio move more and more to completely digital processing of a signal Hence the problem of dealing with equipment w
14. e because it allows to operate with only two changeable parameters 17 FIR filters coefficients and fractional delay But mathematically it is not that simple problem 3 Implementation 3 1 Introduction The primary topic of the work is developing a software VHDL code generator for a filter with adjustable delay FAD This chapter describes the FAD generator implementation 3 2 Implementation details The tool is written in C programming languages The output data is a VHDL code which can be further implemented as a register transfer level RTL model in FPGA for instance Also simulation in MATLAB was performed for FAD structure to test the generated VHDL model 3 3 Setting up the task 3 3 1 System level approach To determine starting design conditions the main initial factors of the further tool were studied such as L Software platform Solaris 2 Application field assumed sampling rate converter generation for its further study and hardware implementation 3 User qualification experienced Unix user scientist programmer 4 The generator sources will be apparently used as a key part of the higher level generators 5 High portability for using in variety of software environments and operation systems 6 High efficiency of using fast evoking fast output generation 7 High functionality 8 Efficient verification mechanism Basing on these key characteristics the following solution fo
15. ed a lot by converting coefficient to canonic signed digit code CSDC where the number of nonzero bits is minimized 5 6 Adder tree is based on carry save adders CSA Each CSA takes 3 numbers at its input adds them and produces 2 output result Thus if it is used in the tree structure it reduces any number of inputs to 2 A 6 input each input is multibit adder tree is shown in Figure 17 CSA Y1 CSA CSA CSA a HR yo qup me Figure 17 6 input adder tree example 28 This tree is able to add 6 multibit numbers with latency of t 3 tcsa tesa IS equal to the propagation time of full adder In order to decrease critical path interlayer latches may be introduced where dotted lines intersect outputs of CSAs CLA shown in Figure 16 is optional It might be used if only final result needed of number of buses should be decreased c Filters simplification According to the discussion above part of the FAD SFG with FIR filters can be drawn like in Figure 18 N Input gt Delay line v v PPG PPG PPG AT AT AT Y y y y Y Y AT Figure 18 FAD fragment with expanded FIR filters It is evident that the separated adder trees can be joined into a single tree and schematic can be st
16. ematic descripta ius 30 SS VHDL code sn ee 34 3 6 Generator code Severn 36 3 7 Configuration file description sssesssesssrrssrrssrrrsrrsernrsernrsernrsnrrsrrrsrrerrrrnrrernr enn 38 4 Design Example and Experimental Results eeeeeeeee eere eere 43 AT Troeen 43 42 Experiments on Benchmark ne sa 43 4 3 Internal behavioral Simulator i en 45 AA User manual SUITE saken 46 5 Conclusion and future WOFK ssssis sescsssvesasessdesesosscadesndesseesticstssesesessetsorebssenssess 49 AAA ee 49 FN see UT I 49 Referentes Aa S1 ADbreVi ll DS ec anio OR TO CARRO a RR 53 Appendix A VHDL components interface description 55 Appendix B Configuration file example scerssscossssssnsssssonssssnonsnssnsnsnsnsnnnnene 63 Appendix C Command line parameters ssssssoossssssnsssssnnsssnnonnssnsnsnsnsnnsnnnne 67 vi Figure list Figure I Analog method of sample rate conversion sees 6 Figure 2 All digital method of sample rate conversion esses 6 Figure 3 Time domain view of sample rate conversion sssssrseresrrssesresorennennn 7 Figure 4 The structure a no block structure b block structure 9 Figure 5 Modified Farrow structure ee odio niet e ero e ES 11 Figure 6 Modified transposed Farrow Structure I sess 12 Figure 7 Transposed modified Farrow structure HI 13 Figure 8 A
17. ength 3 Prefilter delays for each section number of delays in chain ini i 1 m 4 Quantizers parameters input output word length Q q j 1 2 m 5 Filter parameters a Number of sections k filter order b Multipliers coefficients 6 Coefficients for multipliers of a FAD This list includes essential input information for the FAD generator It will be replenished as may be necessary 3 4 Task solution 3 4 1 Step by step adaptation and simplification of the SFG The SFG mentioned in the previous chapter primarily illustrates the schematic to be realized but cannot be implemented directly It does not contain detailed information about the parts that it is composed of about bus structure and their sizes etc Therefore the model must be analyzed and optimized at the lower hierarchical level The task of the current work is not to design a mathematically optimal solution that can be further implemented in FPGA with minimal cost Therefore obvious simplification will be carried out 25 a Delay chain simplification Consider the part of FAD SFG and its expanded view paying attention to the delay elements Figure 14 N Input v v n D nD v v H z H z v v Q q Q qz Nonexpanded SFG Input UO TU Q a Expan
18. ers 1 4 Summary of main results In order to test created automatic tool existing high level synthesis benchmark is used In addition a new one was created to provide testing with more precision and accuracy Design examples and experimental results are presented in chapter 4 of this document 1 5 About this document Literature review Information on this subject was obtained from academic papers found in electronic libraries such as IEEE from some books in this area from some papers which focus on describing design techniques and tools Most of the information was taken from academic papers In addition there was used Internet databases to find some information related to programming and design techniques The bibliography section includes the links referenced in this document Prerequisites It must be noticed that reader of this thesis is assumed to have general knowledge in digital signal processing Outline Chapter 2 provides detail concerning the different converter techniques In addition more precise definition of the problem is presented Chapter 3 describes the system and tool implementation details The architecture is presented Chapter 4 concluded with the implementation by introducing the experimental results based on testing some design examples It also includes a user manual Chapter 5 presents some conclusions and proposes suggestions for future work Appendix A contains VHDL component
19. etween two cases ripples such as a factor of ten The nonlinear optimization problem could be solved in MATLAB as a standard function minimax Then the relaxation of the design specification by factor A is used to find less complex structure The A is chosen that the number of optimization iterations is rational The main idea is to use some kind of automatic implementation tools in low level and furthermore in FPGA to reduce design time The overall filter consists of subfilters which orders and coefficients are the only changeable parameters before complete implementation Hence it is necessary to create the program which will do all kind of smart implementation with respect to the low area The main problem with it is that automatic process should use techniques which are optimal from engineer s point of view To reach that aim it should be created some base of suitable designing solutions For example it is the sharing of the delay elements among the subfilters and suitable schematics for signed multiplication These improvements are playing the main role in the reducing the area Thus the important first step is implementation of the single rate fractional delay filter and creating the VHDL code generator for it Then the appropriate way must be chosen the suitable way to find that kind of parameters which are suitable for adjustable sampling rate conversion Assumption that all subfilters have the same parameters seems to be simpl
20. ich rising edge delay chain shift occurred 59 60 Shift generator entity shift gen lt name gt _0 is port a in std logic vector 12 1 downto 0 y outstd logic array shift name clk in std logic end shift gen name 0 It is a supporting component which generates partial products for multiplication The rules how it composes the result are hardly coded in component code FAD VHDL implementation contains many shift generators for different coefficients required Component name includes lt name gt field that defines which component is the owner of shifter a input value in parallel code y output set of partial products The type declaration is similar to the type described in the filter section clk clock signal Adder tree entity tree lt name gt 0 is port clk in std logic in 0 in std logic array shift fill in l in std logic array shift fill in 2 instd logic array shift fill in 3 in std logic array shift fill in 4 in std logic array shift fill in 5 in std logic array shift fill in 6 in std logic array shift fill in 7 in std logic array shift fill outc outs out std logic vector 21 1 downto 0 end tree lt name gt 0 Number of inputs depends on the number of partial products to be added in 0 in 7 inputs to be added outs outc sum result clk clock signal Meaningful if only tree is pipelined 61 62 Appendix B Configuration fi
21. ignal is first interpolated by a factor of M using digital filters and decimated by a factor of N to obtain the final sampling rate If the integers M and N are manageable numbers less then 10 for example it is possible to solve this problem by combination of interpolator and decimator But there are cases when this number can be irrational or too high to implement in simple way For example the ratio of 44 1 and 48 kHz can be expressed as 147 160 Hence the sample rate of the input signal is first interpolated by a factor of M 160 using digital filters and decimated back by a factor of N 147 but resulting filter would become rather big To overcome this problem 147 160 can be accomplished by breaking this into the conversion procedures of 3 2 and 7 5 The overall conversion filter can be obtained by taking the cascade combination of all these Hence the overall filter should consist of cascaded subfilters 2 3 Schematics of sampling rate converters N Aikawa and Y Mori proposed an interpolation kernel filter 2 It is approximated in each sampling section piece by using a quadratic functions in equation 1 The block structure of the proposed kernel shown in Figure 4 b The linear combination of the input data and reconstruction kernel is SE D f 9 1 where f are the sample values and y x is the reconstruction kernel a b x c 0 lt lxl lt 1 N am binx cm n D N lt ld lt 1 y i 1 ax bxc s I n
22. in VHDL Output response is saved and converted to MATLAB to be analyzed there The same structure in MATLAB was tested and showed the same results The parameters of the Design example are shown in Appendix B 0 5 5 5 0 5 NN Figure 27 Design Example Structure The same input vector applied during VHDL and MATLAB modeling The output impulse responses Figure 28 were compared and found to be identical Impulse responce 0 2 0 15 0 1 0 05 0 05 0 1 0 15 0 2 0 25 0 3 0 35 Figure 28 Design Example Impulse response The impulse response value shown below 0 00061 0 001709 0 001343 0 012207 0 014893 0 03186 0 02417 0 016479 0 16577 0 27783 0 053711 0 02539 0 01953 44 Three different examples were used as test information and results obtained proved the equality of the VHDL model output and MATLAB mathematical model In addition to simplify the testing for future work the internal behavioral simulator was created 4 3 Internal behavioral simulator Internal simulator emulates the single pulse of the highest positive value and applies it to the input of FAD Such an input cause a certain output vector called impulse response Vector length depends on the number of stages in filters the schematic is composed from and number of stages in FAD itself The comparison between the mathematical simulation results and test bench output gives a user an
23. ion file syntax gives an unambiguous interpretation of the information supplied The information above may be put into the configuration description according the following rules in Backus Naur notation BNF 1 Configuration file lt Header gt Filter description j lt Multiplier description 39 2 Header converter lt space gt lt name gt lt space gt lt number gt word lt space gt lt number gt lt Additional param gt lt Delays gt l st line converter name is supplied and FAD output bus width output quantizer parameter 2 nd line input bus width 3 Additional param lt compensation gt lt guardbits gt lt pipelining gt lt symmetry gt lt vma gt lt symmetrypipelinig gt lt vmapipelining gt n 4 Delays delay lt space gt lt number gt lt space gt lt number gt Number of delays before each stage of FAD is supplied All of them must be entered 5 Filter description filter lt space gt lt name gt lt space gt lt number gt lt number gt lt coefficient gt n lt coefficient gt l st line filter name and filter output bus width corresponding quantizer parameter 2 nd line number of filter stages 3 rd line starts a coefficient list All of them must be included Number of coefficients must be equal to number of filter stages 6 Multiplier description mul lt space gt lt coefficient gt lt number gt 40 Here the value of the coefficien
24. isk och administrativ art Upphovsmannens ideella r tt innefattar r tt att bli n mnd som upphovsman i den omfattning som god sed kr ver vid anv ndning av dokumentet p ovan beskrivna s tt samt skydd mot att dokumentet ndras eller presenteras i s dan form eller 1 s dant sammanhang som r kr nkande f r upphovsmannens litter ra eller konstn rliga anseende eller egenart F r ytterligare information om Link ping University Electronic Press se f rlagets hemsida http www ep liu se In English The publishers will keep this document online on the Internet or its possible replacement for a considerable time from the date of publication barring exceptional circumstances The online availability of the document implies a permanent permission for anyone to read to download to print out single copies for your own use and to use it unchanged for any non commercial research and educational purpose Subsequent transfers of copyright cannot revoke this permission All other uses of the document are conditional on the consent of the copyright owner The publisher has taken technical and administrative measures to assure authenticity security and accessibility According to intellectual property law the author has the right to be mentioned when his her work is accessed as described above and to be protected against infringement For additional information about the Link ping University Electronic Press and its procedures for publicati
25. ith different sampling rates has become really severe There was usually only a single digital processor in any particular signal chain and only Analog to Digital A D or Digital to Analog D A converters used in that kind of chains But today it is common to find completely digital studio for processing audio or and video signals In that kind of studios the signal is digitized immediately after the receiver original analog source All operations such as editing and processing remain in the digital domain which is considered to be an advantageous solution in all future equipment For all that was said above there is a need for simple digital interfacing between different digital equipments 1 2 Motivation The main problem in designing such a system is the complexity of design process The manual design usually provides the desired implementation results but leads to long design times During the design process a fast design technique is needed to reduce the time of the design process 1 3 Purpose The purposes of this thesis are To study different converter techniques in order to work out the best solution for the problem at hand To select the schematics which are suitable to implement with respect of small area and low power consumption To find suitable techniques to design sample rate converters To reduce the time of the design by creating an automatic tool to generate the VHDL code of the system with given paramet
26. l method of sample rate conversion The sample rate conversion problem may be formulated using the interpolation decimation model in the time domain view shown in Figure 3 The output sample rate trace C is higher than the original input sample rate trace A It can be done by first interpolating by A and then decimating by B The interpolated values are fed into a zero order hold and then resampled by the output switch trace D The output values appear to be representation of the values produced by interpolation filter which is the nearest in time Because the output sampling switch is not closing in exactly the time corresponding to a point on the fine time grid of the interpolated output there appear some errors which could be made small by increasing the filter order Amplitude I im e Amplitude B o o o o o o o o o o lime Am plitude Am plitude E i I I l l l l I t l l D l l l l zi gt ime Figure 3 Time domain view of sample rate conversion Sampling rate conversions performed between arbitrary sampling rates tends to make the sample rates conversion factor to be a ratio of two very large integers or even an irrational number The ratio of f and f can be expressed as M N where M N is computed by the least common multiple of the two sampling rates f f Hence the sample rate of the input s
27. le example converter fedor 16 word 12 5 delay 01234 filter fill 12 8 0 001953125 0 015625 0 06640625 0 3046875 0 3046875 0 06640625 0 015625 0 001953125 filter fil2 12 8 0 001953125 0 015625 0 06640625 0 3046875 0 3046875 0 06640625 0 015625 0 001953125 63 64 filter fil3 12 8 0 001953125 0 015625 0 06640625 0 3046875 0 3046875 0 06640625 0 015625 0 001953125 filter fil4 12 8 0 001953125 0 015625 0 06640625 0 3046875 0 3046875 0 06640625 0 015625 0 001953125 filter fil5 12 8 0 001953125 0 015625 0 06640625 0 3046875 0 3046875 0 06640625 0 015625 0 001953125 mul 0 5 13 mul 0 5 13 mul 0 5 14 mul 0 5 15 65 66 Appendix C Command line parameters The only parameter that cannot be omitted is the name of a configuration file The evoking syntax in BNF notation is the following lt program name gt lt config file name gt m t name s name The additional parameters can be given in any order after the configuration file name m Creates makefile for VCOM If such a parameter is given the tool creates file called makefile containing all the components of ready FAD enumerated in proper order It allows removing the interdependency problem during compilation the VHDL code VCOM compiler should be evoked in the following way vcom f makefile t Defines name used as a key part of converter type file name If the option is not given noname
28. n or supporting means like data reencoding generation with templates etc Functional approach used in C language is quite old however fast and effective if used in appropriate way Data exchange between functions is only carried out by function parameters no global variables are used for this It also makes for the functions independency and increases code clarity Tool block schematic is shown in Figure 26 36 main Configuration file parsing z Filters generation 3 a s Buses width calculation 4 ne Multipliers generation Quantizers generation 6 1 Adders generation 7 Delay chain generation Signals declaration and definition 9 Buses width adjustment at adders inputs 10 Buses merging at multipliers inputs 11 Components interconnection gt Output Figure 26 Tool block schematic 37 Tool input information is taken from the configuration file written according to special simple syntax that will be carefully discussed in the next chapter Procedure 1 that is responsible for that fills the internal structures with filter parameters information multiplier coefficient values etc Filters are generated only with information supplied in configuration file procedure 2 Internal bus width depends only on the filter result width quantizers parameters adders input bus widths Multiplier generation
29. of design generated by the tool was performed and proofed that generator works correctly 5 2 Future work This work implies using the multipliers with fixed coefficient The variable coefficient multiplier may be introduced in order to increase the flexibility and get more functionality In order to be implemented more improvements and optimization must be done 49 50 References 1 R Adams T Kwan A Stereo Asynchronous Digital Sample Rate Converter for Digital Audio IEEE Journal of solid state circuits vol 29 NO 4 pp 481 488 April 1994 2 N Aikawa Y Mori Kernel with block structure for sampling rate converter 0 7803 7663 3 03 2003 IEEE ICASSP 2003 NO VI pp 269 272 2003 3 D Babic J Vesma T Saramaki M Renfors Implementation of the transposed Farrow structure 0 7803 7448 7 02 2002 IEEE NO IV pp 5 8 2002 4 H Johansson P Lowenborg On the Design of adjustable Fractional Delay FIR Filters IEEE Transactions on circuits and systems II Analog and digital signal processing vol 50 No 4 pp 164 169 2003 5 L Wanhammar DSP integrated circuits pp 468 470 6 H Ohlsson Studies on implementation of digital filters with high throughput and low power consumption Thesis 1031 LiU Tec Lic 2003 30 Linkoping University 2003 p 13 51 52 Abbreviations AT adder tree BNF Backus Naur form CLA carry look ahead adder CSA carry
30. on and for assurance of document integrity please refer to its WWW home page http www ep liu se Fedor Merkelov Yaroslav Kodess
31. onsuming register transfer level RTL implementation On the other hand when a coefficient has few of nonzero bits the approach used may seem ineffective however implementation tool optimizes RTL representation and disposes unnecessary gates that compensate such a weakness As it was mentioned in previous chapters this work is not focused on carrying out the accurate optimizations Quantizer might be realized differently depending on the input output width ratio 32 If n is the input bit width and m is the output bit width then a When n m gt 1 rounding is performed Rounding schematic being implemented in this case is shown in Figure 22 Logic Signed increment Mux m Saturation m v Figure 22 Quantizer Rounding case b When n m 1 extension is performed m n 0 s sequence m Figure 23 Quantizer Extension case Here n most significant bits are taken from the input the less significant part is extended by zeros c When n m Lit is a pass through Figure 24 Quantizer Pass through case 33 3 5 VHDL code structure System approach in design implies that system is decomposed into independent or relatively independent components that could be in turn developed separately VHDL language provides a special component approach It means that device being designed can be figured as a set of logically independent blocks that further are joined
32. procedure requires that coefficient be given in input configuration file and bus widths be calculated at previous step The quantizer input parameter that is taken from the configuration file is an output bus width while the input bus width is calculated Number of quantizer channels is implied by the schematic to be implemented The adder width is chosen as the broadest input width Two guard bits are added inside the adder Delay chain length is chosen so it can supply all the possible delays required for all the schematic and for each separate filter All the components are interconnected according to the schematic shown in the Figure 26 If FAD schematic should be adjusted it would cause serious program code modification 3 7 Configuration file description Configuration file is the main and generally the one interaction means between a user and the tool It should contain all the information about FAD that is necessary to successfully generate the schematic 38 The sufficient information required see figure 27 1 Input data width 2 Number of stages 3 Input delay value 4 Filter parameters 4 1 Number of stages 4 2 Multiplier coefficients for each stage 5 Quantizers parameters 6 Multipliers coefficients The logical information required l Schematic name to be used as a part of VHDL file name for the component 2 Filter names Additional information contains details about filter realization Configurat
33. r example quantizers width to achieve the proper accuracy It is important that input parameters for the simulator are given by the same configuration file that makes the design cycle faster and decrease mistake probability due to mistyping for example 4 4 User manual guide 1 Locate the executable file called convgen All the generated VHDL code will be placed into the same directory as the program located 46 2 Write the configuration file Configuration file syntax is described in the respective chapter Example of the configuration file could be found in Appendix B 3 Place the configuration file into the same directory where the executable is 4 Put the generator file into the execution giving the proper command line parameters The list of possible parameters and their description is adduced in Appendix C 5 Ifno simulation option passed program produces a set of VHDL files representing HDL model for a FAD with specified parameters If simulation mode is activated then simulation result file produced with a name specified as a parameter in command line together with generated VHDL code 6 If it is needed testbenching may be performed and compared with a simulation results 47 5 Conclusion and future work 5 1 Conclusion The suitable architecture with respect to low area cost has been chosen The tool for automatic generation of the architecture with given parameters has been created The testing
34. r is completely calculated 3 4 2 Final schematic description After the suggested simplification has been carried out the FAD schematic shown in Figure 20 is obtained 30 Delay line H z I Q q vv EB HER H z N Q q vv vr H z m I Qlan Aland ES vr Figure 20 Simplified and adapted FAD block schematic 31 This realization uses 2 s compliment fixed point binary representation Most significant bit MSB is a sign bit The 2 s compliment binary encoded number xi can be converted into decimal representation by the equation O 1 yr X where x are binary number bits N is a word length In this approach 4 input adders are used instead of CLA s at filter outputs Inner structure of an adder is shown in Figure 21 Ex N 2 N 2 Satur N 2 Y 1 WY SHE CSA CSA CLA N N 2 Ex Ex is a bus width extension with guard bits Figure 21 Block schematic of a 4 input adder 4 input adder in Figure 21 has one output It is done to avoid multiplier duplication in the next stage When a multiplier coefficient has many nonzero bits a complex CSA tree must be used in it which leads to an area c
35. r the system level is suggested 1 Input data is supplied in noninteractive mode with configuration file read by the tool It doesn t bring many problems for a Unix user because this way is the most commonly used for this software environment 2 User specifies the necessary operating mode with command line keys 3 The programming language being used is ANSI C because it is supported by all the software platforms known and provides high degree of portability even for recent operation systems Special supporting libraries like input output library for instance from the side software makers are not being used 4 Minimal configuration file syntax The block definition of ready FAD is presented in the Figure 9 N M Input gt FAD VHDL component gt Output Il Clock Reset Figure 9 Block definition of FAD Here N and M are an input and output bus width respectively Reset sets the block into initial state The rate at that an input information is accepted is controlled by a clock signal 20 The system level block diagram showing how the main blocks of the tool are interconnected is adduced in the Figure 10 gt Simulator Simulation results User Interface Calculating core gt Generated output Figure 10 Generator system level block diagram Short blocks description User interface block is responsible for
36. rated simulator When a supplementary modeling tool is implied it requires that at first it must be installed into user environment Secondly user must be able to use it that is though not a serious problem for the user assumed Multi purpose visual simulators often do not provide the necessary flexibility and adjustability for the new input data number of stages for instance Evoking the environment with considerable functionality for executing the couple of line code seems redundant The FAD mathematical model is quite simple therefore integrating the simulation facilities into software being developed seems an optimal solution Since the VHDL code generator and the simulator use the single configuration file it gives additional guarantee of that the mathematical and VHDL models represent the same entity The additional advantage is that it is very fast and may be performed in parallel with generation process Disadvantages of the approach e A simple verifying simulator complicates for example parameters adjusting for given output It is good only for verifying Often user trusts more the well known systems like MATLAB especially if he can see the block schematic or the model source code that he examines 3 3 2 Signal flow graph level analysis Consider general view of a SFG for FAD Figure 11 Input v Y v y n D n
37. rator and tested in MATLAB The source code is attached to the report And some results from tests of the implemented scheme 11 Acknowledgements This Master thesis has been written at the Department of Electrical Engineering ISY Link ping University as a final work of the International Master Program in SoCware We would like to thank H kan Johansson and Henrik Ohlsson for providing us with source code of filter generator that we used in our thesis work as well as for their help in any other questions Our special thanks are to our friend Oleg Zakaznov for his suggestions in different aspects iii iv Table of contents AAA A sse eonsei sesso so iesst s oeii esaeen ieie 1 1 Back rou cens anne 1 NM 1 DD MP OSS EE EN A 1 1 4 Summary of main rs a a Eh 2 1 5 About this domene 2 A PENE 2 2 Different converters techniques ussessossssssonsssssnssssnnnsssnnsnsssnsnnsssnnnnnnnnnsnsnsnnnne 5 21 Trodde 5 2 2 Basic concepts and definitions cero pare 5 2 3 Schematics of sampling rate converters ueeeeseseeessessneesnnensenennnnensneennn anne 8 24 Destinia 14 3 Implementation sis 19 3T Introductions een 19 3 2 Implementation dei ss realen 19 3 3 Setting up the task ent eden 19 3 3 1 System NN 19 3 3 2 Signal flow graph level analysis anna ann 23 3 3 3 Prerequisites definition sjanse ee SST 25 TE 25 3 4 1 Step by step adaptation and simplification of the SFG 25 3 4 2 Final sch
38. re 6 contains m 1 N m multipliers working at the input sampling rate f N integrators as well as dump circuits and N delay elements at the output sampling rate f co N 2 ci N 2 c N2 D eCN2 1 Cm N 2 1 x n ov 2u Figure 6 Modified transposed Farrow Structure I The fractional interval here is Hk Hk 1 R uk 1 R where R is decimation factor and the signal ov is needed to indicate an overflow of the accumulator The fractional interval for each sample is Hk AT ny T2y T where k is number of sample T is period of sample co N 2 1 ci N 2 1 co N 2 1 ci N 2 1 cn N 2 1 Figure 7 Transposed modified Farrow structure II The structure shown in Figure 7 has N m 1 multipliers working at the output sampling rate and m multipliers working at the input sampling rate In addition there are m I amp D circuits working at the input sampling rate as well as N 1 delay elements working at the output sample rate The structures shown in Figures 5 6 and 7 have almost the same performance but the second one consumes less power during conversion from higher sample rate to lower The main advantage of those structures is that the filter coefficients are fixed which is very good for designing and producing The fractional interval is the only one changeable parameter The modification of the Farrow structure shown in Figure 5 is in fact adjustable fractional dela
39. ructurally simplified Figure 19 gt Delay line PPG PPG PPG Correction AT Figure 19 FAD fragment with joined adder tree 29 Correction block here is in fact a constant binary number It is also used in previous case Figure 18 in every infilter adder tree Correction vector is needed to avoid a sign extension of the partial products Rules of partial product PP and the correction vector generation CSDC encoded coefficient is built according to the following BNF notation 04 11 Denote the coefficient length as m input number length as n and input number as x n x n 1 x 0 Initial value of correction is equal to 0 e Iterate from the position 0 to m from right to left If 0 is met in the coefficient in position k nothing is added to the correction and no PP generated If 1 is met in the coefficient in position k then PP lt 0 gt lt x n 1 x n 2 x 0 gt lt 0 gt correction correction lt 1 gt lt 0 gt If 1 is met in the coefficient in position k then PP lt 0 gt lt x n 1 x n 2 x 0 gt lt 0 gt correction correction 1 gt lt 0 41 Here 1 and 0 denote sequence of i ones or i zeros in binary form After the iterating through all the coefficient bits is finished PP vector contains all the partial products and the value of correction vecto
40. s interface description Appendix B provides with configuration file example Appendix C presents command line parameters 2 Different converters techniques 2 1 Introduction The chapter considers different converter techniques First some basic concepts and definitions will be considered Then some techniques will be introduced as well as some discussion of their advantages and disadvantages Finally some suggestion of suitable techniques will be presented 2 2 Basic concepts and definitions Interpolation and decimation are operations used respectively to increase and reduce the sampling rate or frequency usually by an integer factor Increasing of a sampling rate requires that new values not presented in the signal be computed and inserted between the existing samples The new value is estimated from a neighborhood of the samples of the original signal Similarly in decimation a new value is calculated from a neighborhood of samples and replaces these values in the lower sampling rate Integer factor interpolation and decimation algorithms may be implemented using efficient Finite Impulse Response FIR filters and are therefore relatively easy to implement Alternatively interpolation by non integer factors typically uses polynomial interpolation techniques resulting in more complex solutions There are two classes of sample rate converters The first class is synchronous and the second one is asynchronous In synchronous
41. sample rate converters the sample rate of incoming signal is converted to a new sample rate by an integer factor It is suitable in many applications but if irrational conversion factors are needed the problem appears Its digital output is producing the output samples at a fixed rate related to the input rate On the other hand asynchronous sample rate converters produce output samples at rate which is independent from the input rate There are two methods of sample rate conversion The first one is analog that is the simplest in principle but not in practice The idea is to use a D A converter in combination with a brick wall filter The brick wall filter removes all signal images Then output A D converter converts signal back to a digital format The A D converter runs at the output sampling rate Figure 1 shows the block diagram of that design 1 Digital Digital Brick Wall A D on Analog filter converter in D A converter F in F out Figure 1 Analog method of sample rate conversion But the main problem of Analog method is that Analog functions are more difficult to implement than digital functions On that reason the all digital solution is more preferred The general principle of all digital sample rate converter is almost the same but the analog filter is replaced by a digital interpolation filter The Figure 2 shows the block diagram of all digital sample rate converter 1 Figure 2 All digita
42. save adder CSDC canonic signed digit form FAD filter with adjustable delay FIR finite impulse responce MSB most significant bit PP partition product PPG partial product generator SFG signal flow graph 53 54 Appendix A VHDL components interface description Converter component entity converter converter name number is port indata in std logic vector 12 1 downto 0 ys out std logic vector 41 1 downto 0 yc out std logic reset in std logic clk in std logic end converter converter name number indata input data to converter Its width depends on the configuration file settings ys yc output result and output carry out clk reset clock and reset signals Carry lookahead adder entity cla lt width gt converter name 0 is port in a in std logic vector 23 downto 0 in b in std logic vector 23 downto 0 c in std logic sout out std logic vector 23 downto 0 cout out std logic end cla lt width gt converter name 0 CLA width is used as a part of the component name and file name as well 55 in a in b are inputs of CLA c0 carry in sout cout output result and carry signal Carry save adder entity CSA width is port inl in2 in3 in std logic vector 20 downto 0 outc outs out std logic vector 20 downto 0 end CSA width CSA width is used as a part of the component name and file name
43. t is passed and the bus width after multiplier compensation compensation lt space gt lt Boolean gt guardbits guardbits lt space gt lt number gt pipelining pipelining lt space gt lt number gt Compensation tells whether compensation vector should be added in the filter adder tree Guardbits points how many guard bits should be used in filter adder tree Pipelining keyword precedes the number of pipeline stages in adder tree boolean 0 1 number lt digit gt lt digit gt name lt letter gt lt letter gt lt digit gt coefficient lt float gt space digit is a one character digit float is a real number in any notation including exponential letter is a single capital or lower case latin letter Configuration file parser has a proof against the incorrect data typed by the user and strong syntax checking mechanism The sample configuration file is adduced in the Appendix B 41 42 4 Design Example and Experimental Results 4 1 Introduction In the previous chapters both the low area consuming architecture was introduced and the tool for producing it This tool is used to generate the example of the design This section shows the experimental results 4 2 Experiments on Benchmark For testing of the system Figure 27 the testbench was created in MATLAB The source signal is generated with special test vector generator component done
44. technique is based on distributing the allowable errors in the error functions This approach results in subfilters that can have different order That allows to reduce arithmetic complexity comparatively with the case where all subfilters are of equal orders The specification is H e q 1 6 where the complex error H e d is He d H P Has e oT e 0 OT lal lt 0 5 To satisfy the specification the selection of L and separately optimization H c T is needed so that 25 en 0 50 T PE L D NS where L 2 k 1s odd L 2 1 k is even This optimization can be solved in MATLAB using function remez m The specification e is set that sink C4 42 2 2 6 When lt 1 the specification is satisfied To find the subfilters orders it is easy to design several filters by increasing the filter order until the specification is met But in this approach the overall filter will be overdesigned for the reason that the interaction between filters could appear and this technique does not consider this Than the order of filters and the complexity could be higher than necessary The other proposed technique is filter design via simultaneous optimization of the subfilters To reduce the complexity of the overall structure some nonlinear optimization routine should be used Relaxed specification is used in order to allow iteration of this design procedure The relaxed specification might have differences b
45. y filter It is suitable for interpolation while transposed Farrow structures Figure 6 and 7 are suitable for decimation Adjustable fractional delay filter has the low area cost due to possibility to share delay elements among subfilters Due to this it is considered to be very suitable to implement The designing process of that structure will be discussed in the next chapter 2 4 Design techniques This structure shown in Figure 8 consists of several parallel subfilters which are linear phase FIR filters Due to the coefficient symmetry of such filters the number of required multiplications may be reduced Figure 8 Adjustable fractional delay filter The transfer function of the overall filter is H gt d z H 2 Where d 0 5 0 5 is a multiplication coefficient D is the delay of k th subfilter L is the quantity of subfilters and H z are subfilters frequency responses MENO H e e 2 H R T Where N is order of subfilter The desired real function Ar des OT is k is even H kr des OT ale jon k is odd Where k 0 Each subfilter should approximate the frequency response of an Ni th order differentiator The advantage of such a structure is that there is no need in redesigning the subfilters but just change the single coefficient d The subfilters are designed only one time Hakan Johansson and Per Lowenborg 4 recommend separate optimization of the subfilters This design
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